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Dependents: STM32_F103-C8T6basecanblink_led
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Revision 183:a56a73fd2a6f, committed 2018-03-20
- Comitter:
- AnnaBridge
- Date:
- Tue Mar 20 16:56:18 2018 +0000
- Parent:
- 182:57724642e740
- Child:
- 184:5166a824ec1a
- Commit message:
- mbed-dev library. Release version 160
Changed in this revision
--- a/drivers/TimerEvent.h Fri Feb 16 16:09:33 2018 +0000
+++ b/drivers/TimerEvent.h Tue Mar 20 16:56:18 2018 +0000
@@ -47,13 +47,31 @@
// The handler called to service the timer event of the derived class
virtual void handler() = 0;
- // insert relative timestamp in to linked list
+ /** Set relative timestamp of the internal event.
+ * @param timestamp event's us timestamp
+ *
+ * @warning
+ * Do not insert more than one timestamp.
+ * The same @a event object is used for every @a insert/insert_absolute call.
+ *
+ * @warning
+ * Ticker's present timestamp is used for reference. For timestamps
+ * from the past the event is scheduled after ticker's overflow.
+ * For reference @see convert_timestamp
+ */
void insert(timestamp_t timestamp);
- // insert absolute timestamp into linked list
+ /** Set absolute timestamp of the internal event.
+ * @param timestamp event's us timestamp
+ *
+ * @warning
+ * Do not insert more than one timestamp.
+ * The same @a event object is used for every @a insert/insert_absolute call.
+ */
void insert_absolute(us_timestamp_t timestamp);
- // remove from linked list, if in it
+ /** Remove timestamp.
+ */
void remove();
ticker_event_t event;
--- a/hal/mbed_ticker_api.c Fri Feb 16 16:09:33 2018 +0000
+++ b/hal/mbed_ticker_api.c Tue Mar 20 16:56:18 2018 +0000
@@ -235,6 +235,14 @@
}
timestamp_t match_tick = compute_tick(ticker, match_time);
+ // The time has been checked to be future, but it could still round
+ // to the last tick as a result of us to ticks conversion
+ if (match_tick == queue->tick_last_read) {
+ // Match time has already expired so fire immediately
+ ticker->interface->fire_interrupt();
+ return;
+ }
+
ticker->interface->set_interrupt(match_tick);
timestamp_t cur_tick = ticker->interface->read();
--- a/mbed.h Fri Feb 16 16:09:33 2018 +0000 +++ b/mbed.h Tue Mar 20 16:56:18 2018 +0000 @@ -16,13 +16,13 @@ #ifndef MBED_H #define MBED_H -#define MBED_LIBRARY_VERSION 159 +#define MBED_LIBRARY_VERSION 161 #if MBED_CONF_RTOS_PRESENT // RTOS present, this is valid only for mbed OS 5 #define MBED_MAJOR_VERSION 5 #define MBED_MINOR_VERSION 7 -#define MBED_PATCH_VERSION 5 +#define MBED_PATCH_VERSION 7 #else // mbed 2
--- a/platform/FilePath.cpp Fri Feb 16 16:09:33 2018 +0000
+++ b/platform/FilePath.cpp Tue Mar 20 16:56:18 2018 +0000
@@ -18,9 +18,10 @@
namespace mbed {
FilePath::FilePath(const char* file_path) : file_name(NULL), fb(NULL) {
- if ((file_path[0] != '/') || (file_path[1] == 0)) return;
+ // skip slashes
+ file_path += strspn(file_path, "/");
- const char* file_system = &file_path[1];
+ const char* file_system = file_path;
file_name = file_system;
int len = 0;
while (true) {
@@ -36,6 +37,7 @@
file_name++;
}
+ MBED_ASSERT(len != 0);
fb = FileBase::lookup(file_system, len);
}
--- a/platform/mbed_retarget.cpp Fri Feb 16 16:09:33 2018 +0000
+++ b/platform/mbed_retarget.cpp Tue Mar 20 16:56:18 2018 +0000
@@ -740,12 +740,13 @@
extern "C" int errno;
// Dynamic memory allocation related syscall.
-#if defined(TARGET_NUVOTON)
+#if (defined(TARGET_NUVOTON) || defined(TWO_RAM_REGIONS))
// Overwrite _sbrk() to support two region model (heap and stack are two distinct regions).
// __wrap__sbrk() is implemented in:
// TARGET_NUMAKER_PFM_NUC472 targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/TOOLCHAIN_GCC_ARM/nuc472_retarget.c
// TARGET_NUMAKER_PFM_M453 targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/TOOLCHAIN_GCC_ARM/m451_retarget.c
+// TARGET_STM32L4 targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L4/l4_retarget.c
extern "C" void *__wrap__sbrk(int incr);
extern "C" caddr_t _sbrk(int incr) {
return (caddr_t) __wrap__sbrk(incr);
--- a/platform/mbed_sleep.h Fri Feb 16 16:09:33 2018 +0000
+++ b/platform/mbed_sleep.h Tue Mar 20 16:56:18 2018 +0000
@@ -24,7 +24,7 @@
#ifndef MBED_SLEEP_H
#define MBED_SLEEP_H
-#include "sleep_api.h"
+#include "hal/sleep_api.h"
#include "mbed_toolchain.h"
#include <stdbool.h>
@@ -128,7 +128,7 @@
* Flash re-programming and the USB serial port will remain active, but the mbed program will no longer be
* able to access the LocalFileSystem
*/
-__INLINE static void sleep(void)
+static inline void sleep(void)
{
#if !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED))
#if DEVICE_SLEEP
@@ -158,7 +158,7 @@
*/
MBED_DEPRECATED_SINCE("mbed-os-5.6", "One entry point for an application, use sleep()")
-__INLINE static void deepsleep(void)
+static inline void deepsleep(void)
{
#if !(defined(FEATURE_UVISOR) && defined(TARGET_UVISOR_SUPPORTED))
#if DEVICE_SLEEP
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_ARM_SSG/TARGET_BEETLE/device/TOOLCHAIN_ARM_STD/startup_BEETLE.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,268 @@ +;/* +; * BEETLE CMSIS Library +; */ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * http://www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ +; +; This file is derivative of CMSIS V5.00 startup_ARMCM3.s +; +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + + +__initial_sp EQU 0x20020000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD UART0_Handler ; UART 0 RX and TX Handler + DCD Spare_IRQ_Handler ; Undefined + DCD UART1_Handler ; UART 1 RX and TX Handler + DCD I2C0_Handler ; I2C 0 Handler + DCD I2C1_Handler ; I2C 1 Handler + DCD RTC_Handler ; RTC Handler + DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler + DCD PORT1_COMB_Handler ; GPIO Port 1 Combined Handler + DCD TIMER0_Handler ; TIMER 0 handler + DCD TIMER1_Handler ; TIMER 1 handler + DCD DUALTIMER_HANDLER ; Dual timer handler + DCD SPI0_Handler ; SPI 0 Handler + DCD UARTOVF_Handler ; UART 0,1 Overflow Handler + DCD SPI1_Handler ; SPI 1 Handler + DCD QSPI_Handler ; QSPI Handler + DCD DMA_Handler ; DMA handler + DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler + DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler + DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler + DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler + DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler + DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler + DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler + DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler + DCD PORT0_8_Handler ; GPIO Port 0 pin 8 Handler + DCD PORT0_9_Handler ; GPIO Port 0 pin 9 Handler + DCD PORT0_10_Handler ; GPIO Port 0 pin 10 Handler + DCD PORT0_11_Handler ; GPIO Port 0 pin 11 Handler + DCD PORT0_12_Handler ; GPIO Port 0 pin 12 Handler + DCD PORT0_13_Handler ; GPIO Port 0 pin 13 Handler + DCD PORT0_14_Handler ; GPIO Port 0 pin 14 Handler + DCD PORT0_15_Handler ; GPIO Port 0 pin 15 Handler + DCD SysError_Handler ; System Error (Flash Cache) + DCD EFLASH_Handler ; Embedded Flash + DCD LLCC_TXCMD_EMPTY_Handler ; LLCC_TXCMDIRQ + DCD LLCC_TXEVT_EMPTY_Handler ; LLCC_TXEVTIRQ + DCD LLCC_TXDMAH_DONE_Handler ; LLCC_TXDMA0IRQ + DCD LLCC_TXDMAL_DONE_Handler ; LLCC_TXDMA1IRQ + DCD LLCC_RXCMD_VALID_Handler ; LLCC_RXCMDIRQ + DCD LLCC_RXEVT_VALID_Handler ; LLCC_RXEVTIRQ + DCD LLCC_RXDMAH_DONE_Handler ; LLCC_RXDMA0IRQ + DCD LLCC_RXDMAL_DONE_Handler ; LLCC_RXDMA1IRQ + DCD PORT2_COMB_Handler ; GPIO 2 + DCD PORT3_COMB_Handler ; GPIO 3 + DCD TRNG_Handler ; TRNG +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT UART0_Handler [WEAK] + EXPORT Spare_IRQ_Handler [WEAK] + EXPORT UART1_Handler [WEAK] + EXPORT I2C0_Handler [WEAK] + EXPORT I2C1_Handler [WEAK] + EXPORT RTC_Handler [WEAK] + EXPORT PORT0_COMB_Handler [WEAK] + EXPORT PORT1_COMB_Handler [WEAK] + EXPORT TIMER0_Handler [WEAK] + EXPORT TIMER1_Handler [WEAK] + EXPORT DUALTIMER_HANDLER [WEAK] + EXPORT SPI0_Handler [WEAK] + EXPORT UARTOVF_Handler [WEAK] + EXPORT SPI1_Handler [WEAK] + EXPORT QSPI_Handler [WEAK] + EXPORT DMA_Handler [WEAK] + EXPORT PORT0_0_Handler [WEAK] + EXPORT PORT0_1_Handler [WEAK] + EXPORT PORT0_2_Handler [WEAK] + EXPORT PORT0_3_Handler [WEAK] + EXPORT PORT0_4_Handler [WEAK] + EXPORT PORT0_5_Handler [WEAK] + EXPORT PORT0_6_Handler [WEAK] + EXPORT PORT0_7_Handler [WEAK] + EXPORT PORT0_8_Handler [WEAK] + EXPORT PORT0_9_Handler [WEAK] + EXPORT PORT0_10_Handler [WEAK] + EXPORT PORT0_11_Handler [WEAK] + EXPORT PORT0_12_Handler [WEAK] + EXPORT PORT0_13_Handler [WEAK] + EXPORT PORT0_14_Handler [WEAK] + EXPORT PORT0_15_Handler [WEAK] + EXPORT SysError_Handler [WEAK] + EXPORT EFLASH_Handler [WEAK] + EXPORT LLCC_TXEVT_EMPTY_Handler [WEAK] + EXPORT LLCC_TXCMD_EMPTY_Handler [WEAK] + EXPORT LLCC_RXEVT_VALID_Handler [WEAK] + EXPORT LLCC_RXCMD_VALID_Handler [WEAK] + EXPORT LLCC_TXDMAL_DONE_Handler [WEAK] + EXPORT LLCC_RXDMAL_DONE_Handler [WEAK] + EXPORT LLCC_TXDMAH_DONE_Handler [WEAK] + EXPORT LLCC_RXDMAH_DONE_Handler [WEAK] + EXPORT PORT2_COMB_Handler [WEAK] + EXPORT PORT3_COMB_Handler [WEAK] + EXPORT TRNG_Handler [WEAK] + +UART0_Handler +Spare_IRQ_Handler +UART1_Handler +I2C0_Handler +I2C1_Handler +RTC_Handler +PORT0_COMB_Handler +PORT1_COMB_Handler +TIMER0_Handler +TIMER1_Handler +DUALTIMER_HANDLER +SPI0_Handler +UARTOVF_Handler +SPI1_Handler +QSPI_Handler +DMA_Handler +PORT0_0_Handler +PORT0_1_Handler +PORT0_2_Handler +PORT0_3_Handler +PORT0_4_Handler +PORT0_5_Handler +PORT0_6_Handler +PORT0_7_Handler +PORT0_8_Handler +PORT0_9_Handler +PORT0_10_Handler +PORT0_11_Handler +PORT0_12_Handler +PORT0_13_Handler +PORT0_14_Handler +PORT0_15_Handler +SysError_Handler +EFLASH_Handler +LLCC_TXEVT_EMPTY_Handler +LLCC_TXCMD_EMPTY_Handler +LLCC_RXEVT_VALID_Handler +LLCC_RXCMD_VALID_Handler +LLCC_TXDMAL_DONE_Handler +LLCC_RXDMAL_DONE_Handler +LLCC_TXDMAH_DONE_Handler +LLCC_RXDMAH_DONE_Handler +PORT2_COMB_Handler +PORT3_COMB_Handler +TRNG_Handler + B . + + ENDP + + + ALIGN + + END
--- a/targets/TARGET_ARM_SSG/TARGET_BEETLE/device/TOOLCHAIN_ARM_STD/startup_BEETLE.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,268 +0,0 @@ -;/* -; * BEETLE CMSIS Library -; */ -;/* -; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Licensed under the Apache License, Version 2.0 (the License); you may -; * not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * http://www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an AS IS BASIS, WITHOUT -; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; */ -; -; This file is derivative of CMSIS V5.00 startup_ARMCM3.s -; -;/* -;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -;*/ - - -__initial_sp EQU 0x20020000 ; Top of RAM - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD UART0_Handler ; UART 0 RX and TX Handler - DCD Spare_IRQ_Handler ; Undefined - DCD UART1_Handler ; UART 1 RX and TX Handler - DCD I2C0_Handler ; I2C 0 Handler - DCD I2C1_Handler ; I2C 1 Handler - DCD RTC_Handler ; RTC Handler - DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler - DCD PORT1_COMB_Handler ; GPIO Port 1 Combined Handler - DCD TIMER0_Handler ; TIMER 0 handler - DCD TIMER1_Handler ; TIMER 1 handler - DCD DUALTIMER_HANDLER ; Dual timer handler - DCD SPI0_Handler ; SPI 0 Handler - DCD UARTOVF_Handler ; UART 0,1 Overflow Handler - DCD SPI1_Handler ; SPI 1 Handler - DCD QSPI_Handler ; QSPI Handler - DCD DMA_Handler ; DMA handler - DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler - DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler - DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler - DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler - DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler - DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler - DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler - DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler - DCD PORT0_8_Handler ; GPIO Port 0 pin 8 Handler - DCD PORT0_9_Handler ; GPIO Port 0 pin 9 Handler - DCD PORT0_10_Handler ; GPIO Port 0 pin 10 Handler - DCD PORT0_11_Handler ; GPIO Port 0 pin 11 Handler - DCD PORT0_12_Handler ; GPIO Port 0 pin 12 Handler - DCD PORT0_13_Handler ; GPIO Port 0 pin 13 Handler - DCD PORT0_14_Handler ; GPIO Port 0 pin 14 Handler - DCD PORT0_15_Handler ; GPIO Port 0 pin 15 Handler - DCD SysError_Handler ; System Error (Flash Cache) - DCD EFLASH_Handler ; Embedded Flash - DCD LLCC_TXCMD_EMPTY_Handler ; LLCC_TXCMDIRQ - DCD LLCC_TXEVT_EMPTY_Handler ; LLCC_TXEVTIRQ - DCD LLCC_TXDMAH_DONE_Handler ; LLCC_TXDMA0IRQ - DCD LLCC_TXDMAL_DONE_Handler ; LLCC_TXDMA1IRQ - DCD LLCC_RXCMD_VALID_Handler ; LLCC_RXCMDIRQ - DCD LLCC_RXEVT_VALID_Handler ; LLCC_RXEVTIRQ - DCD LLCC_RXDMAH_DONE_Handler ; LLCC_RXDMA0IRQ - DCD LLCC_RXDMAL_DONE_Handler ; LLCC_RXDMA1IRQ - DCD PORT2_COMB_Handler ; GPIO 2 - DCD PORT3_COMB_Handler ; GPIO 3 - DCD TRNG_Handler ; TRNG -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT UART0_Handler [WEAK] - EXPORT Spare_IRQ_Handler [WEAK] - EXPORT UART1_Handler [WEAK] - EXPORT I2C0_Handler [WEAK] - EXPORT I2C1_Handler [WEAK] - EXPORT RTC_Handler [WEAK] - EXPORT PORT0_COMB_Handler [WEAK] - EXPORT PORT1_COMB_Handler [WEAK] - EXPORT TIMER0_Handler [WEAK] - EXPORT TIMER1_Handler [WEAK] - EXPORT DUALTIMER_HANDLER [WEAK] - EXPORT SPI0_Handler [WEAK] - EXPORT UARTOVF_Handler [WEAK] - EXPORT SPI1_Handler [WEAK] - EXPORT QSPI_Handler [WEAK] - EXPORT DMA_Handler [WEAK] - EXPORT PORT0_0_Handler [WEAK] - EXPORT PORT0_1_Handler [WEAK] - EXPORT PORT0_2_Handler [WEAK] - EXPORT PORT0_3_Handler [WEAK] - EXPORT PORT0_4_Handler [WEAK] - EXPORT PORT0_5_Handler [WEAK] - EXPORT PORT0_6_Handler [WEAK] - EXPORT PORT0_7_Handler [WEAK] - EXPORT PORT0_8_Handler [WEAK] - EXPORT PORT0_9_Handler [WEAK] - EXPORT PORT0_10_Handler [WEAK] - EXPORT PORT0_11_Handler [WEAK] - EXPORT PORT0_12_Handler [WEAK] - EXPORT PORT0_13_Handler [WEAK] - EXPORT PORT0_14_Handler [WEAK] - EXPORT PORT0_15_Handler [WEAK] - EXPORT SysError_Handler [WEAK] - EXPORT EFLASH_Handler [WEAK] - EXPORT LLCC_TXEVT_EMPTY_Handler [WEAK] - EXPORT LLCC_TXCMD_EMPTY_Handler [WEAK] - EXPORT LLCC_RXEVT_VALID_Handler [WEAK] - EXPORT LLCC_RXCMD_VALID_Handler [WEAK] - EXPORT LLCC_TXDMAL_DONE_Handler [WEAK] - EXPORT LLCC_RXDMAL_DONE_Handler [WEAK] - EXPORT LLCC_TXDMAH_DONE_Handler [WEAK] - EXPORT LLCC_RXDMAH_DONE_Handler [WEAK] - EXPORT PORT2_COMB_Handler [WEAK] - EXPORT PORT3_COMB_Handler [WEAK] - EXPORT TRNG_Handler [WEAK] - -UART0_Handler -Spare_IRQ_Handler -UART1_Handler -I2C0_Handler -I2C1_Handler -RTC_Handler -PORT0_COMB_Handler -PORT1_COMB_Handler -TIMER0_Handler -TIMER1_Handler -DUALTIMER_HANDLER -SPI0_Handler -UARTOVF_Handler -SPI1_Handler -QSPI_Handler -DMA_Handler -PORT0_0_Handler -PORT0_1_Handler -PORT0_2_Handler -PORT0_3_Handler -PORT0_4_Handler -PORT0_5_Handler -PORT0_6_Handler -PORT0_7_Handler -PORT0_8_Handler -PORT0_9_Handler -PORT0_10_Handler -PORT0_11_Handler -PORT0_12_Handler -PORT0_13_Handler -PORT0_14_Handler -PORT0_15_Handler -SysError_Handler -EFLASH_Handler -LLCC_TXEVT_EMPTY_Handler -LLCC_TXCMD_EMPTY_Handler -LLCC_RXEVT_VALID_Handler -LLCC_RXCMD_VALID_Handler -LLCC_TXDMAL_DONE_Handler -LLCC_RXDMAL_DONE_Handler -LLCC_TXDMAH_DONE_Handler -LLCC_RXDMAH_DONE_Handler -PORT2_COMB_Handler -PORT3_COMB_Handler -TRNG_Handler - B . - - ENDP - - - ALIGN - - END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_ARM_SSG/TARGET_BEETLE/device/TOOLCHAIN_IAR/startup_BEETLE.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,421 @@ +;/* +; * BEETLE CMSIS Library +; */ +;/* +; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. +; * +; * SPDX-License-Identifier: Apache-2.0 +; * +; * Licensed under the Apache License, Version 2.0 (the License); you may +; * not use this file except in compliance with the License. +; * You may obtain a copy of the License at +; * +; * http://www.apache.org/licenses/LICENSE-2.0 +; * +; * Unless required by applicable law or agreed to in writing, software +; * distributed under the License is distributed on an AS IS BASIS, WITHOUT +; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; * See the License for the specific language governing permissions and +; * limitations under the License. +; */ +;/* +; * This file is derivative of CMSIS V5.00 startup_Device.s +; */ + + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD UART0_Handler ; 0: UART 0 RX and TX Handler + DCD Spare_IRQ_Handler ; 1: Undefined + DCD UART1_Handler ; 2: UART 1 RX and TX Handler + DCD I2C0_Handler ; 3: I2C 0 Handler + DCD I2C1_Handler ; 4: I2C 1 Handler + DCD RTC_Handler ; 5: RTC Handler + DCD PORT0_COMB_Handler ; 6: GPIO Port 0 Combined Handler + DCD PORT1_COMB_Handler ; 7: GPIO Port 1 Combined Handler + DCD TIMER0_Handler ; 8: TIMER 0 handler + DCD TIMER1_Handler ; 9: TIMER 1 handler + DCD DUALTIMER_HANDLER ; 10: Dual timer handler + DCD SPI0_Handler ; 11: SPI 0 Handler + DCD UARTOVF_Handler ; 12: UART 0,1 Overflow Handler + DCD SPI1_Handler ; 13: SPI 1 Handler + DCD QSPI_Handler ; 14: QSPI Handler + DCD DMA_Handler ; 15: DMA handler + DCD PORT0_0_Handler ; 16: GPIO Port 0 pin 0 Handler + DCD PORT0_1_Handler ; 17: GPIO Port 0 pin 1 Handler + DCD PORT0_2_Handler ; 18: GPIO Port 0 pin 2 Handler + DCD PORT0_3_Handler ; 19: GPIO Port 0 pin 3 Handler + DCD PORT0_4_Handler ; 20: GPIO Port 0 pin 4 Handler + DCD PORT0_5_Handler ; 21: GPIO Port 0 pin 5 Handler + DCD PORT0_6_Handler ; 22: GPIO Port 0 pin 6 Handler + DCD PORT0_7_Handler ; 23: GPIO Port 0 pin 7 Handler + DCD PORT0_8_Handler ; 24: GPIO Port 0 pin 8 Handler + DCD PORT0_9_Handler ; 25: GPIO Port 0 pin 9 Handler + DCD PORT0_10_Handler ; 26: GPIO Port 0 pin 10 Handler + DCD PORT0_11_Handler ; 27: GPIO Port 0 pin 11 Handler + DCD PORT0_12_Handler ; 28: GPIO Port 0 pin 12 Handler + DCD PORT0_13_Handler ; 29: GPIO Port 0 pin 13 Handler + DCD PORT0_14_Handler ; 30: GPIO Port 0 pin 14 Handler + DCD PORT0_15_Handler ; 31: GPIO Port 0 pin 15 Handler + DCD SysError_Handler ; 32: System Error (Flash Cache) + DCD EFLASH_Handler ; 33: Embedded Flash + DCD LLCC_TXCMD_EMPTY_Handler ; 34: LLCC_TXCMDIRQ + DCD LLCC_TXEVT_EMPTY_Handler ; 35: LLCC_TXEVTIRQ + DCD LLCC_TXDMAH_DONE_Handler ; 36: LLCC_TXDMA0IRQ + DCD LLCC_TXDMAL_DONE_Handler ; 37: LLCC_TXDMA1IRQ + DCD LLCC_RXCMD_VALID_Handler ; 38: LLCC_RXCMDIRQ + DCD LLCC_RXEVT_VALID_Handler ; 39: LLCC_RXEVTIRQ + DCD LLCC_RXDMAH_DONE_Handler ; 40: LLCC_RXDMA0IRQ + DCD LLCC_RXDMAL_DONE_Handler ; 41: LLCC_RXDMA1IRQ + DCD PORT2_COMB_Handler ; 42: GPIO 2 + DCD PORT3_COMB_Handler ; 43: GPIO 3 + DCD TRNG_Handler ; 44: TRNG +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SecureFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SecureFault_Handler + B SecureFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + + PUBWEAK UART0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UART0_Handler + B UART0_Handler + + PUBWEAK Spare_IRQ_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +Spare_IRQ_Handler + B Spare_IRQ_Handler + + PUBWEAK UART1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UART1_Handler + B UART1_Handler + + PUBWEAK I2C0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C0_Handler + B I2C0_Handler + + PUBWEAK I2C1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_Handler + B I2C1_Handler + + PUBWEAK RTC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Handler + B RTC_Handler + + PUBWEAK PORT0_COMB_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_COMB_Handler + B PORT0_COMB_Handler + + PUBWEAK PORT1_COMB_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT1_COMB_Handler + B PORT1_COMB_Handler + + PUBWEAK TIMER0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER0_Handler + B TIMER0_Handler + + PUBWEAK TIMER1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER1_Handler + B TIMER1_Handler + + PUBWEAK DUALTIMER_HANDLER + SECTION .text:CODE:REORDER:NOROOT(1) +DUALTIMER_HANDLER + B DUALTIMER_HANDLER + + PUBWEAK SPI0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI0_Handler + B SPI0_Handler + + PUBWEAK UARTOVF_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UARTOVF_Handler + B UARTOVF_Handler + + PUBWEAK SPI1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_Handler + B SPI1_Handler + + PUBWEAK QSPI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +QSPI_Handler + B QSPI_Handler + + PUBWEAK DMA_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA_Handler + B DMA_Handler + + PUBWEAK PORT0_0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_0_Handler + B PORT0_0_Handler + + PUBWEAK PORT0_1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_1_Handler + B PORT0_1_Handler + + PUBWEAK PORT0_2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_2_Handler + B PORT0_2_Handler + + PUBWEAK PORT0_3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_3_Handler + B PORT0_3_Handler + + PUBWEAK PORT0_4_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_4_Handler + B PORT0_4_Handler + + PUBWEAK PORT0_5_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_5_Handler + B PORT0_5_Handler + + PUBWEAK PORT0_6_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_6_Handler + B PORT0_6_Handler + + PUBWEAK PORT0_7_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_7_Handler + B PORT0_7_Handler + + PUBWEAK PORT0_8_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_8_Handler + B PORT0_8_Handler + + PUBWEAK PORT0_9_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_9_Handler + B PORT0_9_Handler + + PUBWEAK PORT0_10_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_10_Handler + B PORT0_10_Handler + + PUBWEAK PORT0_11_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_11_Handler + B PORT0_11_Handler + + PUBWEAK PORT0_12_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_12_Handler + B PORT0_12_Handler + + PUBWEAK PORT0_13_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_13_Handler + B PORT0_13_Handler + + PUBWEAK PORT0_14_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_14_Handler + B PORT0_14_Handler + + PUBWEAK PORT0_15_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_15_Handler + B PORT0_15_Handler + + PUBWEAK SysError_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysError_Handler + B SysError_Handler + + PUBWEAK EFLASH_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +EFLASH_Handler + B EFLASH_Handler + + PUBWEAK LLCC_TXCMD_EMPTY_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +LLCC_TXCMD_EMPTY_Handler + B LLCC_TXCMD_EMPTY_Handler + + PUBWEAK LLCC_TXEVT_EMPTY_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +LLCC_TXEVT_EMPTY_Handler + B LLCC_TXEVT_EMPTY_Handler + + PUBWEAK LLCC_TXDMAH_DONE_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +LLCC_TXDMAH_DONE_Handler + B LLCC_TXDMAH_DONE_Handler + + PUBWEAK LLCC_TXDMAL_DONE_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +LLCC_TXDMAL_DONE_Handler + B LLCC_TXDMAL_DONE_Handler + + PUBWEAK LLCC_RXCMD_VALID_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +LLCC_RXCMD_VALID_Handler + B LLCC_RXCMD_VALID_Handler + + PUBWEAK LLCC_RXEVT_VALID_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +LLCC_RXEVT_VALID_Handler + B LLCC_RXEVT_VALID_Handler + + PUBWEAK LLCC_RXDMAH_DONE_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +LLCC_RXDMAH_DONE_Handler + B LLCC_RXDMAH_DONE_Handler + + PUBWEAK LLCC_RXDMAL_DONE_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +LLCC_RXDMAL_DONE_Handler + B LLCC_RXDMAL_DONE_Handler + + PUBWEAK PORT2_COMB_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT2_COMB_Handler + B PORT2_COMB_Handler + + PUBWEAK PORT3_COMB_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT3_COMB_Handler + B PORT3_COMB_Handler + + PUBWEAK TRNG_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +TRNG_Handler + B TRNG_Handler + + END
--- a/targets/TARGET_ARM_SSG/TARGET_BEETLE/device/TOOLCHAIN_IAR/startup_BEETLE.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,421 +0,0 @@ -;/* -; * BEETLE CMSIS Library -; */ -;/* -; * Copyright (c) 2009-2016 ARM Limited. All rights reserved. -; * -; * SPDX-License-Identifier: Apache-2.0 -; * -; * Licensed under the Apache License, Version 2.0 (the License); you may -; * not use this file except in compliance with the License. -; * You may obtain a copy of the License at -; * -; * http://www.apache.org/licenses/LICENSE-2.0 -; * -; * Unless required by applicable law or agreed to in writing, software -; * distributed under the License is distributed on an AS IS BASIS, WITHOUT -; * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; * See the License for the specific language governing permissions and -; * limitations under the License. -; */ -;/* -; * This file is derivative of CMSIS V5.00 startup_Device.s -; */ - - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler - DCD HardFault_Handler - DCD MemManage_Handler - DCD BusFault_Handler - DCD UsageFault_Handler -__vector_table_0x1c - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD SVC_Handler - DCD DebugMon_Handler - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD UART0_Handler ; 0: UART 0 RX and TX Handler - DCD Spare_IRQ_Handler ; 1: Undefined - DCD UART1_Handler ; 2: UART 1 RX and TX Handler - DCD I2C0_Handler ; 3: I2C 0 Handler - DCD I2C1_Handler ; 4: I2C 1 Handler - DCD RTC_Handler ; 5: RTC Handler - DCD PORT0_COMB_Handler ; 6: GPIO Port 0 Combined Handler - DCD PORT1_COMB_Handler ; 7: GPIO Port 1 Combined Handler - DCD TIMER0_Handler ; 8: TIMER 0 handler - DCD TIMER1_Handler ; 9: TIMER 1 handler - DCD DUALTIMER_HANDLER ; 10: Dual timer handler - DCD SPI0_Handler ; 11: SPI 0 Handler - DCD UARTOVF_Handler ; 12: UART 0,1 Overflow Handler - DCD SPI1_Handler ; 13: SPI 1 Handler - DCD QSPI_Handler ; 14: QSPI Handler - DCD DMA_Handler ; 15: DMA handler - DCD PORT0_0_Handler ; 16: GPIO Port 0 pin 0 Handler - DCD PORT0_1_Handler ; 17: GPIO Port 0 pin 1 Handler - DCD PORT0_2_Handler ; 18: GPIO Port 0 pin 2 Handler - DCD PORT0_3_Handler ; 19: GPIO Port 0 pin 3 Handler - DCD PORT0_4_Handler ; 20: GPIO Port 0 pin 4 Handler - DCD PORT0_5_Handler ; 21: GPIO Port 0 pin 5 Handler - DCD PORT0_6_Handler ; 22: GPIO Port 0 pin 6 Handler - DCD PORT0_7_Handler ; 23: GPIO Port 0 pin 7 Handler - DCD PORT0_8_Handler ; 24: GPIO Port 0 pin 8 Handler - DCD PORT0_9_Handler ; 25: GPIO Port 0 pin 9 Handler - DCD PORT0_10_Handler ; 26: GPIO Port 0 pin 10 Handler - DCD PORT0_11_Handler ; 27: GPIO Port 0 pin 11 Handler - DCD PORT0_12_Handler ; 28: GPIO Port 0 pin 12 Handler - DCD PORT0_13_Handler ; 29: GPIO Port 0 pin 13 Handler - DCD PORT0_14_Handler ; 30: GPIO Port 0 pin 14 Handler - DCD PORT0_15_Handler ; 31: GPIO Port 0 pin 15 Handler - DCD SysError_Handler ; 32: System Error (Flash Cache) - DCD EFLASH_Handler ; 33: Embedded Flash - DCD LLCC_TXCMD_EMPTY_Handler ; 34: LLCC_TXCMDIRQ - DCD LLCC_TXEVT_EMPTY_Handler ; 35: LLCC_TXEVTIRQ - DCD LLCC_TXDMAH_DONE_Handler ; 36: LLCC_TXDMA0IRQ - DCD LLCC_TXDMAL_DONE_Handler ; 37: LLCC_TXDMA1IRQ - DCD LLCC_RXCMD_VALID_Handler ; 38: LLCC_RXCMDIRQ - DCD LLCC_RXEVT_VALID_Handler ; 39: LLCC_RXEVTIRQ - DCD LLCC_RXDMAH_DONE_Handler ; 40: LLCC_RXDMA0IRQ - DCD LLCC_RXDMAL_DONE_Handler ; 41: LLCC_RXDMA1IRQ - DCD PORT2_COMB_Handler ; 42: GPIO 2 - DCD PORT3_COMB_Handler ; 43: GPIO 3 - DCD TRNG_Handler ; 44: TRNG -__Vectors_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SecureFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SecureFault_Handler - B SecureFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - - PUBWEAK UART0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UART0_Handler - B UART0_Handler - - PUBWEAK Spare_IRQ_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -Spare_IRQ_Handler - B Spare_IRQ_Handler - - PUBWEAK UART1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UART1_Handler - B UART1_Handler - - PUBWEAK I2C0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C0_Handler - B I2C0_Handler - - PUBWEAK I2C1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C1_Handler - B I2C1_Handler - - PUBWEAK RTC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC_Handler - B RTC_Handler - - PUBWEAK PORT0_COMB_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_COMB_Handler - B PORT0_COMB_Handler - - PUBWEAK PORT1_COMB_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT1_COMB_Handler - B PORT1_COMB_Handler - - PUBWEAK TIMER0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER0_Handler - B TIMER0_Handler - - PUBWEAK TIMER1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER1_Handler - B TIMER1_Handler - - PUBWEAK DUALTIMER_HANDLER - SECTION .text:CODE:REORDER:NOROOT(1) -DUALTIMER_HANDLER - B DUALTIMER_HANDLER - - PUBWEAK SPI0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI0_Handler - B SPI0_Handler - - PUBWEAK UARTOVF_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UARTOVF_Handler - B UARTOVF_Handler - - PUBWEAK SPI1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI1_Handler - B SPI1_Handler - - PUBWEAK QSPI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -QSPI_Handler - B QSPI_Handler - - PUBWEAK DMA_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA_Handler - B DMA_Handler - - PUBWEAK PORT0_0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_0_Handler - B PORT0_0_Handler - - PUBWEAK PORT0_1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_1_Handler - B PORT0_1_Handler - - PUBWEAK PORT0_2_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_2_Handler - B PORT0_2_Handler - - PUBWEAK PORT0_3_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_3_Handler - B PORT0_3_Handler - - PUBWEAK PORT0_4_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_4_Handler - B PORT0_4_Handler - - PUBWEAK PORT0_5_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_5_Handler - B PORT0_5_Handler - - PUBWEAK PORT0_6_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_6_Handler - B PORT0_6_Handler - - PUBWEAK PORT0_7_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_7_Handler - B PORT0_7_Handler - - PUBWEAK PORT0_8_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_8_Handler - B PORT0_8_Handler - - PUBWEAK PORT0_9_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_9_Handler - B PORT0_9_Handler - - PUBWEAK PORT0_10_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_10_Handler - B PORT0_10_Handler - - PUBWEAK PORT0_11_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_11_Handler - B PORT0_11_Handler - - PUBWEAK PORT0_12_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_12_Handler - B PORT0_12_Handler - - PUBWEAK PORT0_13_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_13_Handler - B PORT0_13_Handler - - PUBWEAK PORT0_14_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_14_Handler - B PORT0_14_Handler - - PUBWEAK PORT0_15_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_15_Handler - B PORT0_15_Handler - - PUBWEAK SysError_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysError_Handler - B SysError_Handler - - PUBWEAK EFLASH_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -EFLASH_Handler - B EFLASH_Handler - - PUBWEAK LLCC_TXCMD_EMPTY_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -LLCC_TXCMD_EMPTY_Handler - B LLCC_TXCMD_EMPTY_Handler - - PUBWEAK LLCC_TXEVT_EMPTY_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -LLCC_TXEVT_EMPTY_Handler - B LLCC_TXEVT_EMPTY_Handler - - PUBWEAK LLCC_TXDMAH_DONE_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -LLCC_TXDMAH_DONE_Handler - B LLCC_TXDMAH_DONE_Handler - - PUBWEAK LLCC_TXDMAL_DONE_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -LLCC_TXDMAL_DONE_Handler - B LLCC_TXDMAL_DONE_Handler - - PUBWEAK LLCC_RXCMD_VALID_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -LLCC_RXCMD_VALID_Handler - B LLCC_RXCMD_VALID_Handler - - PUBWEAK LLCC_RXEVT_VALID_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -LLCC_RXEVT_VALID_Handler - B LLCC_RXEVT_VALID_Handler - - PUBWEAK LLCC_RXDMAH_DONE_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -LLCC_RXDMAH_DONE_Handler - B LLCC_RXDMAH_DONE_Handler - - PUBWEAK LLCC_RXDMAL_DONE_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -LLCC_RXDMAL_DONE_Handler - B LLCC_RXDMAL_DONE_Handler - - PUBWEAK PORT2_COMB_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT2_COMB_Handler - B PORT2_COMB_Handler - - PUBWEAK PORT3_COMB_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT3_COMB_Handler - B PORT3_COMB_Handler - - PUBWEAK TRNG_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -TRNG_Handler - B TRNG_Handler - - END
--- a/targets/TARGET_ARM_SSG/TARGET_BEETLE/us_ticker.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_ARM_SSG/TARGET_BEETLE/us_ticker.c Tue Mar 20 16:56:18 2018 +0000
@@ -100,7 +100,7 @@
void us_ticker_fire_interrupt(void)
{
- uint32_t us_ticker_irqn1 = Timer_GetIRQn(TIMER1);
+ uint32_t us_ticker_irqn1 = Timer_GetIRQn(TIMER0);
NVIC_SetPendingIRQ((IRQn_Type)us_ticker_irqn1);
}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_ARM_SSG/TARGET_IOTSS/TARGET_IOTSS_BEID/device/TOOLCHAIN_ARM_STD/startup_MPS2.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,358 @@ +; MPS2 CMSIS Library +; +; Copyright (c) 2006-2016 ARM Limited +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; +; 3. Neither the name of the copyright holder nor the names of its contributors +; may be used to endorse or promote products derived from this software without +; specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +;****************************************************************************** +; @file startup_CMSDK_BEID.s +; @brief CMSIS Core Device Startup File for +; CMSDK_BEID Device +; +;****************************************************************************** +; +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; + + +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00004000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00001000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD UART0_IRQHandler ; 0:UART 0 RX and TX Combined Interrupt + DCD Spare_IRQHandler ; 1:Undefined + DCD UART1_IRQHandler ; 2:UART 1 RX and TX Combined Interrupt + DCD I2C0_IRQHandler ; 3:I2C 0 Interrupt + DCD I2C1_IRQHandler ; 4:I2C 1 Interrupt + DCD RTC_IRQHandler ; 5:RTC Interrupt + DCD PORT0_IRQHandler ; 6:GPIO Port 0 combined Interrupt + DCD PORT1_ALL_IRQHandler ; 7:GPIO Port 1 combined Interrupt + DCD TIMER0_IRQHandler ; 8:TIMER 0 Interrupt + DCD TIMER1_IRQHandler ; 9:TIMER 1 Interrupt + DCD DUALTIMER_IRQHandler ; 10:Dual Timer Interrupt + DCD SPI0_IRQHandler ; 11:SPI 0 Interrupt + DCD UARTOVF_IRQHandler ; 12:UART 0,1,2 Overflow Interrupt + DCD SPI1_IRQHandler ; 13:SPI 1 Interrupt + DCD RESERVED0_IRQHandler ; 14:Reserved + DCD TSC_IRQHandler ; 15:Touch Screen Interrupt + DCD PORT01_0_IRQHandler ; 16:GPIO Port 0 pin 0 Handler + DCD PORT01_1_IRQHandler ; 17:GPIO Port 0 pin 1 Handler + DCD PORT01_2_IRQHandler ; 18:GPIO Port 0 pin 2 Handler + DCD PORT01_3_IRQHandler ; 19:GPIO Port 0 pin 3 Handler + DCD PORT01_4_IRQHandler ; 20:GPIO Port 0 pin 4 Handler + DCD PORT01_5_IRQHandler ; 21:GPIO Port 0 pin 5 Handler + DCD PORT01_6_IRQHandler ; 22:GPIO Port 0 pin 6 Handler + DCD PORT01_7_IRQHandler ; 23:GPIO Port 0 pin 7 Handler + DCD PORT01_8_IRQHandler ; 24:GPIO Port 0 pin 8 Handler + DCD PORT01_9_IRQHandler ; 25:GPIO Port 0 pin 9 Handler + DCD PORT01_10_IRQHandler ; 26:GPIO Port 0 pin 10 Handler + DCD PORT01_11_IRQHandler ; 27:GPIO Port 0 pin 11 Handler + DCD PORT01_12_IRQHandler ; 28:GPIO Port 0 pin 12 Handler + DCD PORT01_13_IRQHandler ; 29:GPIO Port 0 pin 13 Handler + DCD PORT01_14_IRQHandler ; 30:GPIO Port 0 pin 14 Handler + DCD PORT01_15_IRQHandler ; 31:GPIO Port 0 pin 15 Handler + DCD SYSERROR_IRQHandler ; 32:System Error Interrupt + DCD EFLASH_IRQHandler ; 33:Embedded Flash Interrupt + DCD RESERVED1_IRQHandler ; 34:Reserved + DCD RESERVED2_IRQHandler ; 35:Reserved + DCD RESERVED3_IRQHandler ; 36:Reserved + DCD RESERVED4_IRQHandler ; 37:Reserved + DCD RESERVED5_IRQHandler ; 38:Reserved + DCD RESERVED6_IRQHandler ; 39:Reserved + DCD RESERVED7_IRQHandler ; 40:Reserved + DCD RESERVED8_IRQHandler ; 41:Reserved + DCD PORT2_ALL_IRQHandler ; 42:GPIO Port 2 combined Interrupt + DCD PORT3_ALL_IRQHandler ; 43:GPIO Port 3 combined Interrupt + DCD TRNG_IRQHandler ; 44:Random number generator Interrupt + DCD UART2_IRQHandler ; 45:UART 2 RX and TX Combined Interrupt + DCD UART3_IRQHandler ; 46:UART 3 RX and TX Combined Interrupt + DCD ETHERNET_IRQHandler ; 47:Ethernet interrupt t.b.a. + DCD I2S_IRQHandler ; 48:I2S Interrupt + DCD MPS2_SPI0_IRQHandler ; 49:SPI Interrupt (spi header) + DCD MPS2_SPI1_IRQHandler ; 50:SPI Interrupt (clcd) + DCD MPS2_SPI2_IRQHandler ; 51:SPI Interrupt (spi 1 ADC replacement) + DCD MPS2_SPI3_IRQHandler ; 52:SPI Interrupt (spi 0 shield 0 replacement) + DCD MPS2_SPI4_IRQHandler ; 53:SPI Interrupt (shield 1) + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT UART0_IRQHandler [WEAK] ; 0:UART 0 RX and TX Combined Interrupt + EXPORT Spare_IRQHandler [WEAK] ; 1:Undefined + EXPORT UART1_IRQHandler [WEAK] ; 2:UART 1 RX and TX Combined Interrupt + EXPORT I2C0_IRQHandler [WEAK] ; 3:I2C 0 Interrupt + EXPORT I2C1_IRQHandler [WEAK] ; 4:I2C 1 Interrupt + EXPORT RTC_IRQHandler [WEAK] ; 5:RTC Interrupt + EXPORT PORT0_IRQHandler [WEAK] ; 6:GPIO Port 0 combined Interrupt + EXPORT PORT1_ALL_IRQHandler [WEAK] ; 7:GPIO Port 1 combined Interrupt + EXPORT TIMER0_IRQHandler [WEAK] ; 8:TIMER 0 Interrupt + EXPORT TIMER1_IRQHandler [WEAK] ; 9:TIMER 1 Interrupt + EXPORT DUALTIMER_IRQHandler [WEAK] ; 10:Dual Timer Interrupt + EXPORT SPI0_IRQHandler [WEAK] ; 11:SPI 0 Interrupt + EXPORT UARTOVF_IRQHandler [WEAK] ; 12:UART 0,1,2 Overflow Interrupt + EXPORT SPI1_IRQHandler [WEAK] ; 13:SPI 1 Interrupt + EXPORT RESERVED0_IRQHandler [WEAK] ; 14:Reserved + EXPORT TSC_IRQHandler [WEAK] ; 15:Touch Screen Interrupt + EXPORT PORT01_0_IRQHandler [WEAK] ; 16:GPIO Port 0 pin 0 Handler + EXPORT PORT01_1_IRQHandler [WEAK] ; 17:GPIO Port 0 pin 1 Handler + EXPORT PORT01_2_IRQHandler [WEAK] ; 18:GPIO Port 0 pin 2 Handler + EXPORT PORT01_3_IRQHandler [WEAK] ; 19:GPIO Port 0 pin 3 Handler + EXPORT PORT01_4_IRQHandler [WEAK] ; 20:GPIO Port 0 pin 4 Handler + EXPORT PORT01_5_IRQHandler [WEAK] ; 21:GPIO Port 0 pin 5 Handler + EXPORT PORT01_6_IRQHandler [WEAK] ; 22:GPIO Port 0 pin 6 Handler + EXPORT PORT01_7_IRQHandler [WEAK] ; 23:GPIO Port 0 pin 7 Handler + EXPORT PORT01_8_IRQHandler [WEAK] ; 24:GPIO Port 0 pin 8 Handler + EXPORT PORT01_9_IRQHandler [WEAK] ; 25:GPIO Port 0 pin 9 Handler + EXPORT PORT01_10_IRQHandler [WEAK] ; 26:GPIO Port 0 pin 10 Handler + EXPORT PORT01_11_IRQHandler [WEAK] ; 27:GPIO Port 0 pin 11 Handler + EXPORT PORT01_12_IRQHandler [WEAK] ; 28:GPIO Port 0 pin 12 Handler + EXPORT PORT01_13_IRQHandler [WEAK] ; 29:GPIO Port 0 pin 13 Handler + EXPORT PORT01_14_IRQHandler [WEAK] ; 30:GPIO Port 0 pin 14 Handler + EXPORT PORT01_15_IRQHandler [WEAK] ; 31:GPIO Port 0 pin 15 Handler + EXPORT SYSERROR_IRQHandler [WEAK] ; 32:System Error Interrupt + EXPORT EFLASH_IRQHandler [WEAK] ; 33:Embedded Flash Interrupt + EXPORT RESERVED1_IRQHandler [WEAK] ; 34:Reserved + EXPORT RESERVED2_IRQHandler [WEAK] ; 35:Reserved + EXPORT RESERVED3_IRQHandler [WEAK] ; 36:Reserved + EXPORT RESERVED4_IRQHandler [WEAK] ; 37:Reserved + EXPORT RESERVED5_IRQHandler [WEAK] ; 38:Reserved + EXPORT RESERVED6_IRQHandler [WEAK] ; 39:Reserved + EXPORT RESERVED7_IRQHandler [WEAK] ; 40:Reserved + EXPORT RESERVED8_IRQHandler [WEAK] ; 41:Reserved + EXPORT PORT2_ALL_IRQHandler [WEAK] ; 42:GPIO Port 2 combined Interrupt + EXPORT PORT3_ALL_IRQHandler [WEAK] ; 43:GPIO Port 3 combined Interrupt + EXPORT TRNG_IRQHandler [WEAK] ; 44:Random number generator Interrupt + EXPORT UART2_IRQHandler [WEAK] ; 45:UART 2 RX and TX Combined Interrupt + EXPORT UART3_IRQHandler [WEAK] ; 46:UART 3 RX and TX Combined Interrupt + EXPORT ETHERNET_IRQHandler [WEAK] ; 47:Ethernet interrupt t.b.a. + EXPORT I2S_IRQHandler [WEAK] ; 48:I2S Interrupt + EXPORT MPS2_SPI0_IRQHandler [WEAK] ; 49:SPI Interrupt (spi header) + EXPORT MPS2_SPI1_IRQHandler [WEAK] ; 50:SPI Interrupt (clcd) + EXPORT MPS2_SPI2_IRQHandler [WEAK] ; 51:SPI Interrupt (spi 1 ADC replacement) + EXPORT MPS2_SPI3_IRQHandler [WEAK] ; 52:SPI Interrupt (spi 0 shield 0 replacement) + EXPORT MPS2_SPI4_IRQHandler [WEAK] ; 53:SPI Interrupt (shield 1) + +UART0_IRQHandler +Spare_IRQHandler +UART1_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +RTC_IRQHandler +PORT0_IRQHandler +PORT1_ALL_IRQHandler +TIMER0_IRQHandler +TIMER1_IRQHandler +DUALTIMER_IRQHandler +SPI0_IRQHandler +UARTOVF_IRQHandler +SPI1_IRQHandler +RESERVED0_IRQHandler +TSC_IRQHandler +PORT01_0_IRQHandler +PORT01_1_IRQHandler +PORT01_2_IRQHandler +PORT01_3_IRQHandler +PORT01_4_IRQHandler +PORT01_5_IRQHandler +PORT01_6_IRQHandler +PORT01_7_IRQHandler +PORT01_8_IRQHandler +PORT01_9_IRQHandler +PORT01_10_IRQHandler +PORT01_11_IRQHandler +PORT01_12_IRQHandler +PORT01_13_IRQHandler +PORT01_14_IRQHandler +PORT01_15_IRQHandler +SYSERROR_IRQHandler +EFLASH_IRQHandler +RESERVED1_IRQHandler +RESERVED2_IRQHandler +RESERVED3_IRQHandler +RESERVED4_IRQHandler +RESERVED5_IRQHandler +RESERVED6_IRQHandler +RESERVED7_IRQHandler +RESERVED8_IRQHandler +PORT2_ALL_IRQHandler +PORT3_ALL_IRQHandler +TRNG_IRQHandler +UART2_IRQHandler +UART3_IRQHandler +ETHERNET_IRQHandler +I2S_IRQHandler +MPS2_SPI0_IRQHandler +MPS2_SPI1_IRQHandler +MPS2_SPI2_IRQHandler +MPS2_SPI3_IRQHandler +MPS2_SPI4_IRQHandler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END
--- a/targets/TARGET_ARM_SSG/TARGET_IOTSS/TARGET_IOTSS_BEID/device/TOOLCHAIN_ARM_STD/startup_MPS2.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,358 +0,0 @@ -; MPS2 CMSIS Library -; -; Copyright (c) 2006-2016 ARM Limited -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, -; this list of conditions and the following disclaimer. -; -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; -; 3. Neither the name of the copyright holder nor the names of its contributors -; may be used to endorse or promote products derived from this software without -; specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; POSSIBILITY OF SUCH DAMAGE. -;****************************************************************************** -; @file startup_CMSDK_BEID.s -; @brief CMSIS Core Device Startup File for -; CMSDK_BEID Device -; -;****************************************************************************** -; -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; - - -; <h> Stack Configuration -; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; </h> - -Stack_Size EQU 0x00004000 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; <h> Heap Configuration -; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; </h> - -Heap_Size EQU 0x00001000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD UART0_IRQHandler ; 0:UART 0 RX and TX Combined Interrupt - DCD Spare_IRQHandler ; 1:Undefined - DCD UART1_IRQHandler ; 2:UART 1 RX and TX Combined Interrupt - DCD I2C0_IRQHandler ; 3:I2C 0 Interrupt - DCD I2C1_IRQHandler ; 4:I2C 1 Interrupt - DCD RTC_IRQHandler ; 5:RTC Interrupt - DCD PORT0_IRQHandler ; 6:GPIO Port 0 combined Interrupt - DCD PORT1_ALL_IRQHandler ; 7:GPIO Port 1 combined Interrupt - DCD TIMER0_IRQHandler ; 8:TIMER 0 Interrupt - DCD TIMER1_IRQHandler ; 9:TIMER 1 Interrupt - DCD DUALTIMER_IRQHandler ; 10:Dual Timer Interrupt - DCD SPI0_IRQHandler ; 11:SPI 0 Interrupt - DCD UARTOVF_IRQHandler ; 12:UART 0,1,2 Overflow Interrupt - DCD SPI1_IRQHandler ; 13:SPI 1 Interrupt - DCD RESERVED0_IRQHandler ; 14:Reserved - DCD TSC_IRQHandler ; 15:Touch Screen Interrupt - DCD PORT01_0_IRQHandler ; 16:GPIO Port 0 pin 0 Handler - DCD PORT01_1_IRQHandler ; 17:GPIO Port 0 pin 1 Handler - DCD PORT01_2_IRQHandler ; 18:GPIO Port 0 pin 2 Handler - DCD PORT01_3_IRQHandler ; 19:GPIO Port 0 pin 3 Handler - DCD PORT01_4_IRQHandler ; 20:GPIO Port 0 pin 4 Handler - DCD PORT01_5_IRQHandler ; 21:GPIO Port 0 pin 5 Handler - DCD PORT01_6_IRQHandler ; 22:GPIO Port 0 pin 6 Handler - DCD PORT01_7_IRQHandler ; 23:GPIO Port 0 pin 7 Handler - DCD PORT01_8_IRQHandler ; 24:GPIO Port 0 pin 8 Handler - DCD PORT01_9_IRQHandler ; 25:GPIO Port 0 pin 9 Handler - DCD PORT01_10_IRQHandler ; 26:GPIO Port 0 pin 10 Handler - DCD PORT01_11_IRQHandler ; 27:GPIO Port 0 pin 11 Handler - DCD PORT01_12_IRQHandler ; 28:GPIO Port 0 pin 12 Handler - DCD PORT01_13_IRQHandler ; 29:GPIO Port 0 pin 13 Handler - DCD PORT01_14_IRQHandler ; 30:GPIO Port 0 pin 14 Handler - DCD PORT01_15_IRQHandler ; 31:GPIO Port 0 pin 15 Handler - DCD SYSERROR_IRQHandler ; 32:System Error Interrupt - DCD EFLASH_IRQHandler ; 33:Embedded Flash Interrupt - DCD RESERVED1_IRQHandler ; 34:Reserved - DCD RESERVED2_IRQHandler ; 35:Reserved - DCD RESERVED3_IRQHandler ; 36:Reserved - DCD RESERVED4_IRQHandler ; 37:Reserved - DCD RESERVED5_IRQHandler ; 38:Reserved - DCD RESERVED6_IRQHandler ; 39:Reserved - DCD RESERVED7_IRQHandler ; 40:Reserved - DCD RESERVED8_IRQHandler ; 41:Reserved - DCD PORT2_ALL_IRQHandler ; 42:GPIO Port 2 combined Interrupt - DCD PORT3_ALL_IRQHandler ; 43:GPIO Port 3 combined Interrupt - DCD TRNG_IRQHandler ; 44:Random number generator Interrupt - DCD UART2_IRQHandler ; 45:UART 2 RX and TX Combined Interrupt - DCD UART3_IRQHandler ; 46:UART 3 RX and TX Combined Interrupt - DCD ETHERNET_IRQHandler ; 47:Ethernet interrupt t.b.a. - DCD I2S_IRQHandler ; 48:I2S Interrupt - DCD MPS2_SPI0_IRQHandler ; 49:SPI Interrupt (spi header) - DCD MPS2_SPI1_IRQHandler ; 50:SPI Interrupt (clcd) - DCD MPS2_SPI2_IRQHandler ; 51:SPI Interrupt (spi 1 ADC replacement) - DCD MPS2_SPI3_IRQHandler ; 52:SPI Interrupt (spi 0 shield 0 replacement) - DCD MPS2_SPI4_IRQHandler ; 53:SPI Interrupt (shield 1) - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT UART0_IRQHandler [WEAK] ; 0:UART 0 RX and TX Combined Interrupt - EXPORT Spare_IRQHandler [WEAK] ; 1:Undefined - EXPORT UART1_IRQHandler [WEAK] ; 2:UART 1 RX and TX Combined Interrupt - EXPORT I2C0_IRQHandler [WEAK] ; 3:I2C 0 Interrupt - EXPORT I2C1_IRQHandler [WEAK] ; 4:I2C 1 Interrupt - EXPORT RTC_IRQHandler [WEAK] ; 5:RTC Interrupt - EXPORT PORT0_IRQHandler [WEAK] ; 6:GPIO Port 0 combined Interrupt - EXPORT PORT1_ALL_IRQHandler [WEAK] ; 7:GPIO Port 1 combined Interrupt - EXPORT TIMER0_IRQHandler [WEAK] ; 8:TIMER 0 Interrupt - EXPORT TIMER1_IRQHandler [WEAK] ; 9:TIMER 1 Interrupt - EXPORT DUALTIMER_IRQHandler [WEAK] ; 10:Dual Timer Interrupt - EXPORT SPI0_IRQHandler [WEAK] ; 11:SPI 0 Interrupt - EXPORT UARTOVF_IRQHandler [WEAK] ; 12:UART 0,1,2 Overflow Interrupt - EXPORT SPI1_IRQHandler [WEAK] ; 13:SPI 1 Interrupt - EXPORT RESERVED0_IRQHandler [WEAK] ; 14:Reserved - EXPORT TSC_IRQHandler [WEAK] ; 15:Touch Screen Interrupt - EXPORT PORT01_0_IRQHandler [WEAK] ; 16:GPIO Port 0 pin 0 Handler - EXPORT PORT01_1_IRQHandler [WEAK] ; 17:GPIO Port 0 pin 1 Handler - EXPORT PORT01_2_IRQHandler [WEAK] ; 18:GPIO Port 0 pin 2 Handler - EXPORT PORT01_3_IRQHandler [WEAK] ; 19:GPIO Port 0 pin 3 Handler - EXPORT PORT01_4_IRQHandler [WEAK] ; 20:GPIO Port 0 pin 4 Handler - EXPORT PORT01_5_IRQHandler [WEAK] ; 21:GPIO Port 0 pin 5 Handler - EXPORT PORT01_6_IRQHandler [WEAK] ; 22:GPIO Port 0 pin 6 Handler - EXPORT PORT01_7_IRQHandler [WEAK] ; 23:GPIO Port 0 pin 7 Handler - EXPORT PORT01_8_IRQHandler [WEAK] ; 24:GPIO Port 0 pin 8 Handler - EXPORT PORT01_9_IRQHandler [WEAK] ; 25:GPIO Port 0 pin 9 Handler - EXPORT PORT01_10_IRQHandler [WEAK] ; 26:GPIO Port 0 pin 10 Handler - EXPORT PORT01_11_IRQHandler [WEAK] ; 27:GPIO Port 0 pin 11 Handler - EXPORT PORT01_12_IRQHandler [WEAK] ; 28:GPIO Port 0 pin 12 Handler - EXPORT PORT01_13_IRQHandler [WEAK] ; 29:GPIO Port 0 pin 13 Handler - EXPORT PORT01_14_IRQHandler [WEAK] ; 30:GPIO Port 0 pin 14 Handler - EXPORT PORT01_15_IRQHandler [WEAK] ; 31:GPIO Port 0 pin 15 Handler - EXPORT SYSERROR_IRQHandler [WEAK] ; 32:System Error Interrupt - EXPORT EFLASH_IRQHandler [WEAK] ; 33:Embedded Flash Interrupt - EXPORT RESERVED1_IRQHandler [WEAK] ; 34:Reserved - EXPORT RESERVED2_IRQHandler [WEAK] ; 35:Reserved - EXPORT RESERVED3_IRQHandler [WEAK] ; 36:Reserved - EXPORT RESERVED4_IRQHandler [WEAK] ; 37:Reserved - EXPORT RESERVED5_IRQHandler [WEAK] ; 38:Reserved - EXPORT RESERVED6_IRQHandler [WEAK] ; 39:Reserved - EXPORT RESERVED7_IRQHandler [WEAK] ; 40:Reserved - EXPORT RESERVED8_IRQHandler [WEAK] ; 41:Reserved - EXPORT PORT2_ALL_IRQHandler [WEAK] ; 42:GPIO Port 2 combined Interrupt - EXPORT PORT3_ALL_IRQHandler [WEAK] ; 43:GPIO Port 3 combined Interrupt - EXPORT TRNG_IRQHandler [WEAK] ; 44:Random number generator Interrupt - EXPORT UART2_IRQHandler [WEAK] ; 45:UART 2 RX and TX Combined Interrupt - EXPORT UART3_IRQHandler [WEAK] ; 46:UART 3 RX and TX Combined Interrupt - EXPORT ETHERNET_IRQHandler [WEAK] ; 47:Ethernet interrupt t.b.a. - EXPORT I2S_IRQHandler [WEAK] ; 48:I2S Interrupt - EXPORT MPS2_SPI0_IRQHandler [WEAK] ; 49:SPI Interrupt (spi header) - EXPORT MPS2_SPI1_IRQHandler [WEAK] ; 50:SPI Interrupt (clcd) - EXPORT MPS2_SPI2_IRQHandler [WEAK] ; 51:SPI Interrupt (spi 1 ADC replacement) - EXPORT MPS2_SPI3_IRQHandler [WEAK] ; 52:SPI Interrupt (spi 0 shield 0 replacement) - EXPORT MPS2_SPI4_IRQHandler [WEAK] ; 53:SPI Interrupt (shield 1) - -UART0_IRQHandler -Spare_IRQHandler -UART1_IRQHandler -I2C0_IRQHandler -I2C1_IRQHandler -RTC_IRQHandler -PORT0_IRQHandler -PORT1_ALL_IRQHandler -TIMER0_IRQHandler -TIMER1_IRQHandler -DUALTIMER_IRQHandler -SPI0_IRQHandler -UARTOVF_IRQHandler -SPI1_IRQHandler -RESERVED0_IRQHandler -TSC_IRQHandler -PORT01_0_IRQHandler -PORT01_1_IRQHandler -PORT01_2_IRQHandler -PORT01_3_IRQHandler -PORT01_4_IRQHandler -PORT01_5_IRQHandler -PORT01_6_IRQHandler -PORT01_7_IRQHandler -PORT01_8_IRQHandler -PORT01_9_IRQHandler -PORT01_10_IRQHandler -PORT01_11_IRQHandler -PORT01_12_IRQHandler -PORT01_13_IRQHandler -PORT01_14_IRQHandler -PORT01_15_IRQHandler -SYSERROR_IRQHandler -EFLASH_IRQHandler -RESERVED1_IRQHandler -RESERVED2_IRQHandler -RESERVED3_IRQHandler -RESERVED4_IRQHandler -RESERVED5_IRQHandler -RESERVED6_IRQHandler -RESERVED7_IRQHandler -RESERVED8_IRQHandler -PORT2_ALL_IRQHandler -PORT3_ALL_IRQHandler -TRNG_IRQHandler -UART2_IRQHandler -UART3_IRQHandler -ETHERNET_IRQHandler -I2S_IRQHandler -MPS2_SPI0_IRQHandler -MPS2_SPI1_IRQHandler -MPS2_SPI2_IRQHandler -MPS2_SPI3_IRQHandler -MPS2_SPI4_IRQHandler - B . - - ENDP - - - ALIGN - - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap PROC - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDP - - ALIGN - - ENDIF - - - END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M0/device/TOOLCHAIN_ARM_STD/startup_MPS2.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,270 @@ +; MPS2 CMSIS Library +; +; Copyright (c) 2006-2016 ARM Limited +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; +; 3. Neither the name of the copyright holder nor the names of its contributors +; may be used to endorse or promote products derived from this software without +; specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +;****************************************************************************** +; @file startup_CMSDK_CM0.s +; @brief CMSIS Core Device Startup File for +; CMSDK_CM0 Device +; +;****************************************************************************** +; +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; + + +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00004000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00001000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD UARTRX0_Handler ; UART 0 RX Handler + DCD UARTTX0_Handler ; UART 0 TX Handler + DCD UARTRX1_Handler ; UART 1 RX Handler + DCD UARTTX1_Handler ; UART 1 TX Handler + DCD UARTRX2_Handler ; UART 2 RX Handler + DCD UARTTX2_Handler ; UART 2 TX Handler + DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler + DCD PORT1_COMB_Handler ; GPIO Port 1 Combined Handler + DCD TIMER0_Handler ; TIMER 0 handler + DCD TIMER1_Handler ; TIMER 1 handler + DCD DUALTIMER_HANDLER ; Dual timer handler + DCD SPI_Handler ; SPI exceptions Handler + DCD UARTOVF_Handler ; UART 0,1,2 Overflow Handler + DCD ETHERNET_Handler ; Ethernet Overflow Handler + DCD I2S_Handler ; I2S Handler + DCD TSC_Handler ; Touch Screen handler + DCD PORT2_COMB_Handler ; GPIO Port 2 Combined Handler + DCD PORT3_COMB_Handler ; GPIO Port 3 Combined Handler + DCD UARTRX3_Handler ; UART 3 RX Handler + DCD UARTTX3_Handler ; UART 3 TX Handler + DCD UARTRX4_Handler ; UART 4 RX Handler + DCD UARTTX4_Handler ; UART 4 TX Handler + DCD ADCSPI_Handler ; SHIELD ADC SPI exceptions Handler + DCD SHIELDSPI_Handler ; SHIELD SPI exceptions Handler + DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler + DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler + DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler + DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler + DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler + DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler + DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler + DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT UARTRX0_Handler [WEAK] + EXPORT UARTTX0_Handler [WEAK] + EXPORT UARTRX1_Handler [WEAK] + EXPORT UARTTX1_Handler [WEAK] + EXPORT UARTRX2_Handler [WEAK] + EXPORT UARTTX2_Handler [WEAK] + EXPORT PORT0_COMB_Handler [WEAK] + EXPORT PORT1_COMB_Handler [WEAK] + EXPORT TIMER0_Handler [WEAK] + EXPORT TIMER1_Handler [WEAK] + EXPORT DUALTIMER_HANDLER [WEAK] + EXPORT SPI_Handler [WEAK] + EXPORT UARTOVF_Handler [WEAK] + EXPORT ETHERNET_Handler [WEAK] + EXPORT I2S_Handler [WEAK] + EXPORT TSC_Handler [WEAK] + EXPORT PORT2_COMB_Handler [WEAK] + EXPORT PORT3_COMB_Handler [WEAK] + EXPORT UARTRX3_Handler [WEAK] + EXPORT UARTTX3_Handler [WEAK] + EXPORT UARTRX4_Handler [WEAK] + EXPORT UARTTX4_Handler [WEAK] + EXPORT ADCSPI_Handler [WEAK] + EXPORT SHIELDSPI_Handler [WEAK] + EXPORT PORT0_0_Handler [WEAK] + EXPORT PORT0_1_Handler [WEAK] + EXPORT PORT0_2_Handler [WEAK] + EXPORT PORT0_3_Handler [WEAK] + EXPORT PORT0_4_Handler [WEAK] + EXPORT PORT0_5_Handler [WEAK] + EXPORT PORT0_6_Handler [WEAK] + EXPORT PORT0_7_Handler [WEAK] + +UARTRX0_Handler +UARTTX0_Handler +UARTRX1_Handler +UARTTX1_Handler +UARTRX2_Handler +UARTTX2_Handler +PORT0_COMB_Handler +PORT1_COMB_Handler +TIMER0_Handler +TIMER1_Handler +DUALTIMER_HANDLER +SPI_Handler +UARTOVF_Handler +ETHERNET_Handler +I2S_Handler +TSC_Handler +PORT2_COMB_Handler +PORT3_COMB_Handler +UARTRX3_Handler +UARTTX3_Handler +UARTRX4_Handler +UARTTX4_Handler +ADCSPI_Handler +SHIELDSPI_Handler +PORT0_0_Handler +PORT0_1_Handler +PORT0_2_Handler +PORT0_3_Handler +PORT0_4_Handler +PORT0_5_Handler +PORT0_6_Handler +PORT0_7_Handler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END
--- a/targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M0/device/TOOLCHAIN_ARM_STD/startup_MPS2.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,270 +0,0 @@ -; MPS2 CMSIS Library -; -; Copyright (c) 2006-2016 ARM Limited -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, -; this list of conditions and the following disclaimer. -; -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; -; 3. Neither the name of the copyright holder nor the names of its contributors -; may be used to endorse or promote products derived from this software without -; specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; POSSIBILITY OF SUCH DAMAGE. -;****************************************************************************** -; @file startup_CMSDK_CM0.s -; @brief CMSIS Core Device Startup File for -; CMSDK_CM0 Device -; -;****************************************************************************** -; -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; - - -; <h> Stack Configuration -; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; </h> - -Stack_Size EQU 0x00004000 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; <h> Heap Configuration -; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; </h> - -Heap_Size EQU 0x00001000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD UARTRX0_Handler ; UART 0 RX Handler - DCD UARTTX0_Handler ; UART 0 TX Handler - DCD UARTRX1_Handler ; UART 1 RX Handler - DCD UARTTX1_Handler ; UART 1 TX Handler - DCD UARTRX2_Handler ; UART 2 RX Handler - DCD UARTTX2_Handler ; UART 2 TX Handler - DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler - DCD PORT1_COMB_Handler ; GPIO Port 1 Combined Handler - DCD TIMER0_Handler ; TIMER 0 handler - DCD TIMER1_Handler ; TIMER 1 handler - DCD DUALTIMER_HANDLER ; Dual timer handler - DCD SPI_Handler ; SPI exceptions Handler - DCD UARTOVF_Handler ; UART 0,1,2 Overflow Handler - DCD ETHERNET_Handler ; Ethernet Overflow Handler - DCD I2S_Handler ; I2S Handler - DCD TSC_Handler ; Touch Screen handler - DCD PORT2_COMB_Handler ; GPIO Port 2 Combined Handler - DCD PORT3_COMB_Handler ; GPIO Port 3 Combined Handler - DCD UARTRX3_Handler ; UART 3 RX Handler - DCD UARTTX3_Handler ; UART 3 TX Handler - DCD UARTRX4_Handler ; UART 4 RX Handler - DCD UARTTX4_Handler ; UART 4 TX Handler - DCD ADCSPI_Handler ; SHIELD ADC SPI exceptions Handler - DCD SHIELDSPI_Handler ; SHIELD SPI exceptions Handler - DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler - DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler - DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler - DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler - DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler - DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler - DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler - DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT UARTRX0_Handler [WEAK] - EXPORT UARTTX0_Handler [WEAK] - EXPORT UARTRX1_Handler [WEAK] - EXPORT UARTTX1_Handler [WEAK] - EXPORT UARTRX2_Handler [WEAK] - EXPORT UARTTX2_Handler [WEAK] - EXPORT PORT0_COMB_Handler [WEAK] - EXPORT PORT1_COMB_Handler [WEAK] - EXPORT TIMER0_Handler [WEAK] - EXPORT TIMER1_Handler [WEAK] - EXPORT DUALTIMER_HANDLER [WEAK] - EXPORT SPI_Handler [WEAK] - EXPORT UARTOVF_Handler [WEAK] - EXPORT ETHERNET_Handler [WEAK] - EXPORT I2S_Handler [WEAK] - EXPORT TSC_Handler [WEAK] - EXPORT PORT2_COMB_Handler [WEAK] - EXPORT PORT3_COMB_Handler [WEAK] - EXPORT UARTRX3_Handler [WEAK] - EXPORT UARTTX3_Handler [WEAK] - EXPORT UARTRX4_Handler [WEAK] - EXPORT UARTTX4_Handler [WEAK] - EXPORT ADCSPI_Handler [WEAK] - EXPORT SHIELDSPI_Handler [WEAK] - EXPORT PORT0_0_Handler [WEAK] - EXPORT PORT0_1_Handler [WEAK] - EXPORT PORT0_2_Handler [WEAK] - EXPORT PORT0_3_Handler [WEAK] - EXPORT PORT0_4_Handler [WEAK] - EXPORT PORT0_5_Handler [WEAK] - EXPORT PORT0_6_Handler [WEAK] - EXPORT PORT0_7_Handler [WEAK] - -UARTRX0_Handler -UARTTX0_Handler -UARTRX1_Handler -UARTTX1_Handler -UARTRX2_Handler -UARTTX2_Handler -PORT0_COMB_Handler -PORT1_COMB_Handler -TIMER0_Handler -TIMER1_Handler -DUALTIMER_HANDLER -SPI_Handler -UARTOVF_Handler -ETHERNET_Handler -I2S_Handler -TSC_Handler -PORT2_COMB_Handler -PORT3_COMB_Handler -UARTRX3_Handler -UARTTX3_Handler -UARTRX4_Handler -UARTTX4_Handler -ADCSPI_Handler -SHIELDSPI_Handler -PORT0_0_Handler -PORT0_1_Handler -PORT0_2_Handler -PORT0_3_Handler -PORT0_4_Handler -PORT0_5_Handler -PORT0_6_Handler -PORT0_7_Handler - B . - - ENDP - - - ALIGN - - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap PROC - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDP - - ALIGN - - ENDIF - - - END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M0P/device/TOOLCHAIN_ARM_STD/startup_MPS2.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,270 @@ +; MPS2 CMSIS Library +; +; Copyright (c) 2006-2016 ARM Limited +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; +; 3. Neither the name of the copyright holder nor the names of its contributors +; may be used to endorse or promote products derived from this software without +; specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +;****************************************************************************** +; @file startup_CMSDK_CM0P.s +; @brief CMSIS Core Device Startup File for +; CMSDK_CM0P Device +; +;****************************************************************************** +; +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; + + +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00004000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00001000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD UARTRX0_Handler ; UART 0 RX Handler + DCD UARTTX0_Handler ; UART 0 TX Handler + DCD UARTRX1_Handler ; UART 1 RX Handler + DCD UARTTX1_Handler ; UART 1 TX Handler + DCD UARTRX2_Handler ; UART 2 RX Handler + DCD UARTTX2_Handler ; UART 2 TX Handler + DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler + DCD PORT1_COMB_Handler ; GPIO Port 1 Combined Handler + DCD TIMER0_Handler ; TIMER 0 handler + DCD TIMER1_Handler ; TIMER 1 handler + DCD DUALTIMER_HANDLER ; Dual timer handler + DCD SPI_Handler ; SPI exceptions Handler + DCD UARTOVF_Handler ; UART 0,1,2 Overflow Handler + DCD ETHERNET_Handler ; Ethernet Overflow Handler + DCD I2S_Handler ; I2S Handler + DCD TSC_Handler ; Touch Screen handler + DCD PORT2_COMB_Handler ; GPIO Port 2 Combined Handler + DCD PORT3_COMB_Handler ; GPIO Port 3 Combined Handler + DCD UARTRX3_Handler ; UART 3 RX Handler + DCD UARTTX3_Handler ; UART 3 TX Handler + DCD UARTRX4_Handler ; UART 4 RX Handler + DCD UARTTX4_Handler ; UART 4 TX Handler + DCD ADCSPI_Handler ; SHIELD ADC SPI exceptions Handler + DCD SHIELDSPI_Handler ; SHIELD SPI exceptions Handler + DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler + DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler + DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler + DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler + DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler + DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler + DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler + DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT UARTRX0_Handler [WEAK] + EXPORT UARTTX0_Handler [WEAK] + EXPORT UARTRX1_Handler [WEAK] + EXPORT UARTTX1_Handler [WEAK] + EXPORT UARTRX2_Handler [WEAK] + EXPORT UARTTX2_Handler [WEAK] + EXPORT PORT0_COMB_Handler [WEAK] + EXPORT PORT1_COMB_Handler [WEAK] + EXPORT TIMER0_Handler [WEAK] + EXPORT TIMER1_Handler [WEAK] + EXPORT DUALTIMER_HANDLER [WEAK] + EXPORT SPI_Handler [WEAK] + EXPORT UARTOVF_Handler [WEAK] + EXPORT ETHERNET_Handler [WEAK] + EXPORT I2S_Handler [WEAK] + EXPORT TSC_Handler [WEAK] + EXPORT PORT2_COMB_Handler [WEAK] + EXPORT PORT3_COMB_Handler [WEAK] + EXPORT UARTRX3_Handler [WEAK] + EXPORT UARTTX3_Handler [WEAK] + EXPORT UARTRX4_Handler [WEAK] + EXPORT UARTTX4_Handler [WEAK] + EXPORT ADCSPI_Handler [WEAK] + EXPORT SHIELDSPI_Handler [WEAK] + EXPORT PORT0_0_Handler [WEAK] + EXPORT PORT0_1_Handler [WEAK] + EXPORT PORT0_2_Handler [WEAK] + EXPORT PORT0_3_Handler [WEAK] + EXPORT PORT0_4_Handler [WEAK] + EXPORT PORT0_5_Handler [WEAK] + EXPORT PORT0_6_Handler [WEAK] + EXPORT PORT0_7_Handler [WEAK] + +UARTRX0_Handler +UARTTX0_Handler +UARTRX1_Handler +UARTTX1_Handler +UARTRX2_Handler +UARTTX2_Handler +PORT0_COMB_Handler +PORT1_COMB_Handler +TIMER0_Handler +TIMER1_Handler +DUALTIMER_HANDLER +SPI_Handler +UARTOVF_Handler +ETHERNET_Handler +I2S_Handler +TSC_Handler +PORT2_COMB_Handler +PORT3_COMB_Handler +UARTRX3_Handler +UARTTX3_Handler +UARTRX4_Handler +UARTTX4_Handler +ADCSPI_Handler +SHIELDSPI_Handler +PORT0_0_Handler +PORT0_1_Handler +PORT0_2_Handler +PORT0_3_Handler +PORT0_4_Handler +PORT0_5_Handler +PORT0_6_Handler +PORT0_7_Handler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END
--- a/targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M0P/device/TOOLCHAIN_ARM_STD/startup_MPS2.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,270 +0,0 @@ -; MPS2 CMSIS Library -; -; Copyright (c) 2006-2016 ARM Limited -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, -; this list of conditions and the following disclaimer. -; -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; -; 3. Neither the name of the copyright holder nor the names of its contributors -; may be used to endorse or promote products derived from this software without -; specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; POSSIBILITY OF SUCH DAMAGE. -;****************************************************************************** -; @file startup_CMSDK_CM0P.s -; @brief CMSIS Core Device Startup File for -; CMSDK_CM0P Device -; -;****************************************************************************** -; -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; - - -; <h> Stack Configuration -; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; </h> - -Stack_Size EQU 0x00004000 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; <h> Heap Configuration -; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; </h> - -Heap_Size EQU 0x00001000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD UARTRX0_Handler ; UART 0 RX Handler - DCD UARTTX0_Handler ; UART 0 TX Handler - DCD UARTRX1_Handler ; UART 1 RX Handler - DCD UARTTX1_Handler ; UART 1 TX Handler - DCD UARTRX2_Handler ; UART 2 RX Handler - DCD UARTTX2_Handler ; UART 2 TX Handler - DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler - DCD PORT1_COMB_Handler ; GPIO Port 1 Combined Handler - DCD TIMER0_Handler ; TIMER 0 handler - DCD TIMER1_Handler ; TIMER 1 handler - DCD DUALTIMER_HANDLER ; Dual timer handler - DCD SPI_Handler ; SPI exceptions Handler - DCD UARTOVF_Handler ; UART 0,1,2 Overflow Handler - DCD ETHERNET_Handler ; Ethernet Overflow Handler - DCD I2S_Handler ; I2S Handler - DCD TSC_Handler ; Touch Screen handler - DCD PORT2_COMB_Handler ; GPIO Port 2 Combined Handler - DCD PORT3_COMB_Handler ; GPIO Port 3 Combined Handler - DCD UARTRX3_Handler ; UART 3 RX Handler - DCD UARTTX3_Handler ; UART 3 TX Handler - DCD UARTRX4_Handler ; UART 4 RX Handler - DCD UARTTX4_Handler ; UART 4 TX Handler - DCD ADCSPI_Handler ; SHIELD ADC SPI exceptions Handler - DCD SHIELDSPI_Handler ; SHIELD SPI exceptions Handler - DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler - DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler - DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler - DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler - DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler - DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler - DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler - DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT UARTRX0_Handler [WEAK] - EXPORT UARTTX0_Handler [WEAK] - EXPORT UARTRX1_Handler [WEAK] - EXPORT UARTTX1_Handler [WEAK] - EXPORT UARTRX2_Handler [WEAK] - EXPORT UARTTX2_Handler [WEAK] - EXPORT PORT0_COMB_Handler [WEAK] - EXPORT PORT1_COMB_Handler [WEAK] - EXPORT TIMER0_Handler [WEAK] - EXPORT TIMER1_Handler [WEAK] - EXPORT DUALTIMER_HANDLER [WEAK] - EXPORT SPI_Handler [WEAK] - EXPORT UARTOVF_Handler [WEAK] - EXPORT ETHERNET_Handler [WEAK] - EXPORT I2S_Handler [WEAK] - EXPORT TSC_Handler [WEAK] - EXPORT PORT2_COMB_Handler [WEAK] - EXPORT PORT3_COMB_Handler [WEAK] - EXPORT UARTRX3_Handler [WEAK] - EXPORT UARTTX3_Handler [WEAK] - EXPORT UARTRX4_Handler [WEAK] - EXPORT UARTTX4_Handler [WEAK] - EXPORT ADCSPI_Handler [WEAK] - EXPORT SHIELDSPI_Handler [WEAK] - EXPORT PORT0_0_Handler [WEAK] - EXPORT PORT0_1_Handler [WEAK] - EXPORT PORT0_2_Handler [WEAK] - EXPORT PORT0_3_Handler [WEAK] - EXPORT PORT0_4_Handler [WEAK] - EXPORT PORT0_5_Handler [WEAK] - EXPORT PORT0_6_Handler [WEAK] - EXPORT PORT0_7_Handler [WEAK] - -UARTRX0_Handler -UARTTX0_Handler -UARTRX1_Handler -UARTTX1_Handler -UARTRX2_Handler -UARTTX2_Handler -PORT0_COMB_Handler -PORT1_COMB_Handler -TIMER0_Handler -TIMER1_Handler -DUALTIMER_HANDLER -SPI_Handler -UARTOVF_Handler -ETHERNET_Handler -I2S_Handler -TSC_Handler -PORT2_COMB_Handler -PORT3_COMB_Handler -UARTRX3_Handler -UARTTX3_Handler -UARTRX4_Handler -UARTTX4_Handler -ADCSPI_Handler -SHIELDSPI_Handler -PORT0_0_Handler -PORT0_1_Handler -PORT0_2_Handler -PORT0_3_Handler -PORT0_4_Handler -PORT0_5_Handler -PORT0_6_Handler -PORT0_7_Handler - B . - - ENDP - - - ALIGN - - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap PROC - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDP - - ALIGN - - ENDIF - - - END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M3/device/TOOLCHAIN_ARM_STD/startup_MPS2.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,290 @@ +; MPS2 CMSIS Library +; +; Copyright (c) 2006-2016 ARM Limited +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; +; 3. Neither the name of the copyright holder nor the names of its contributors +; may be used to endorse or promote products derived from this software without +; specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +;****************************************************************************** +; @file startup_CMSDK_CM3.s +; @brief CMSIS Core Device Startup File for +; CMSDK_CM3 Device +; +;****************************************************************************** +; +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; + + +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00004000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00001000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD UARTRX0_Handler ; UART 0 RX Handler + DCD UARTTX0_Handler ; UART 0 TX Handler + DCD UARTRX1_Handler ; UART 1 RX Handler + DCD UARTTX1_Handler ; UART 1 TX Handler + DCD UARTRX2_Handler ; UART 2 RX Handler + DCD UARTTX2_Handler ; UART 2 TX Handler + DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler + DCD PORT1_COMB_Handler ; GPIO Port 1 Combined Handler + DCD TIMER0_Handler ; TIMER 0 handler + DCD TIMER1_Handler ; TIMER 1 handler + DCD DUALTIMER_HANDLER ; Dual timer handler + DCD SPI_Handler ; SPI exceptions Handler + DCD UARTOVF_Handler ; UART 0,1,2 Overflow Handler + DCD ETHERNET_Handler ; Ethernet Overflow Handler + DCD I2S_Handler ; I2S Handler + DCD TSC_Handler ; Touch Screen handler + DCD PORT2_COMB_Handler ; GPIO Port 2 Combined Handler + DCD PORT3_COMB_Handler ; GPIO Port 3 Combined Handler + DCD UARTRX3_Handler ; UART 3 RX Handler + DCD UARTTX3_Handler ; UART 3 TX Handler + DCD UARTRX4_Handler ; UART 4 RX Handler + DCD UARTTX4_Handler ; UART 4 TX Handler + DCD ADCSPI_Handler ; SHIELD ADC SPI exceptions Handler + DCD SHIELDSPI_Handler ; SHIELD SPI exceptions Handler + DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler + DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler + DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler + DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler + DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler + DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler + DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler + DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT UARTRX0_Handler [WEAK] + EXPORT UARTTX0_Handler [WEAK] + EXPORT UARTRX1_Handler [WEAK] + EXPORT UARTTX1_Handler [WEAK] + EXPORT UARTRX2_Handler [WEAK] + EXPORT UARTTX2_Handler [WEAK] + EXPORT PORT0_COMB_Handler [WEAK] + EXPORT PORT1_COMB_Handler [WEAK] + EXPORT TIMER0_Handler [WEAK] + EXPORT TIMER1_Handler [WEAK] + EXPORT DUALTIMER_HANDLER [WEAK] + EXPORT SPI_Handler [WEAK] + EXPORT UARTOVF_Handler [WEAK] + EXPORT ETHERNET_Handler [WEAK] + EXPORT I2S_Handler [WEAK] + EXPORT TSC_Handler [WEAK] + EXPORT PORT2_COMB_Handler [WEAK] + EXPORT PORT3_COMB_Handler [WEAK] + EXPORT UARTRX3_Handler [WEAK] + EXPORT UARTTX3_Handler [WEAK] + EXPORT UARTRX4_Handler [WEAK] + EXPORT UARTTX4_Handler [WEAK] + EXPORT ADCSPI_Handler [WEAK] + EXPORT SHIELDSPI_Handler [WEAK] + EXPORT PORT0_0_Handler [WEAK] + EXPORT PORT0_1_Handler [WEAK] + EXPORT PORT0_2_Handler [WEAK] + EXPORT PORT0_3_Handler [WEAK] + EXPORT PORT0_4_Handler [WEAK] + EXPORT PORT0_5_Handler [WEAK] + EXPORT PORT0_6_Handler [WEAK] + EXPORT PORT0_7_Handler [WEAK] + +UARTRX0_Handler +UARTTX0_Handler +UARTRX1_Handler +UARTTX1_Handler +UARTRX2_Handler +UARTTX2_Handler +PORT0_COMB_Handler +PORT1_COMB_Handler +TIMER0_Handler +TIMER1_Handler +DUALTIMER_HANDLER +SPI_Handler +UARTOVF_Handler +ETHERNET_Handler +I2S_Handler +TSC_Handler +PORT2_COMB_Handler +PORT3_COMB_Handler +UARTRX3_Handler +UARTTX3_Handler +UARTRX4_Handler +UARTTX4_Handler +ADCSPI_Handler +SHIELDSPI_Handler +PORT0_0_Handler +PORT0_1_Handler +PORT0_2_Handler +PORT0_3_Handler +PORT0_4_Handler +PORT0_5_Handler +PORT0_6_Handler +PORT0_7_Handler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END
--- a/targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M3/device/TOOLCHAIN_ARM_STD/startup_MPS2.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,290 +0,0 @@ -; MPS2 CMSIS Library -; -; Copyright (c) 2006-2016 ARM Limited -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, -; this list of conditions and the following disclaimer. -; -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; -; 3. Neither the name of the copyright holder nor the names of its contributors -; may be used to endorse or promote products derived from this software without -; specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; POSSIBILITY OF SUCH DAMAGE. -;****************************************************************************** -; @file startup_CMSDK_CM3.s -; @brief CMSIS Core Device Startup File for -; CMSDK_CM3 Device -; -;****************************************************************************** -; -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; - - -; <h> Stack Configuration -; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; </h> - -Stack_Size EQU 0x00004000 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; <h> Heap Configuration -; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; </h> - -Heap_Size EQU 0x00001000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD UARTRX0_Handler ; UART 0 RX Handler - DCD UARTTX0_Handler ; UART 0 TX Handler - DCD UARTRX1_Handler ; UART 1 RX Handler - DCD UARTTX1_Handler ; UART 1 TX Handler - DCD UARTRX2_Handler ; UART 2 RX Handler - DCD UARTTX2_Handler ; UART 2 TX Handler - DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler - DCD PORT1_COMB_Handler ; GPIO Port 1 Combined Handler - DCD TIMER0_Handler ; TIMER 0 handler - DCD TIMER1_Handler ; TIMER 1 handler - DCD DUALTIMER_HANDLER ; Dual timer handler - DCD SPI_Handler ; SPI exceptions Handler - DCD UARTOVF_Handler ; UART 0,1,2 Overflow Handler - DCD ETHERNET_Handler ; Ethernet Overflow Handler - DCD I2S_Handler ; I2S Handler - DCD TSC_Handler ; Touch Screen handler - DCD PORT2_COMB_Handler ; GPIO Port 2 Combined Handler - DCD PORT3_COMB_Handler ; GPIO Port 3 Combined Handler - DCD UARTRX3_Handler ; UART 3 RX Handler - DCD UARTTX3_Handler ; UART 3 TX Handler - DCD UARTRX4_Handler ; UART 4 RX Handler - DCD UARTTX4_Handler ; UART 4 TX Handler - DCD ADCSPI_Handler ; SHIELD ADC SPI exceptions Handler - DCD SHIELDSPI_Handler ; SHIELD SPI exceptions Handler - DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler - DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler - DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler - DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler - DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler - DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler - DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler - DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT UARTRX0_Handler [WEAK] - EXPORT UARTTX0_Handler [WEAK] - EXPORT UARTRX1_Handler [WEAK] - EXPORT UARTTX1_Handler [WEAK] - EXPORT UARTRX2_Handler [WEAK] - EXPORT UARTTX2_Handler [WEAK] - EXPORT PORT0_COMB_Handler [WEAK] - EXPORT PORT1_COMB_Handler [WEAK] - EXPORT TIMER0_Handler [WEAK] - EXPORT TIMER1_Handler [WEAK] - EXPORT DUALTIMER_HANDLER [WEAK] - EXPORT SPI_Handler [WEAK] - EXPORT UARTOVF_Handler [WEAK] - EXPORT ETHERNET_Handler [WEAK] - EXPORT I2S_Handler [WEAK] - EXPORT TSC_Handler [WEAK] - EXPORT PORT2_COMB_Handler [WEAK] - EXPORT PORT3_COMB_Handler [WEAK] - EXPORT UARTRX3_Handler [WEAK] - EXPORT UARTTX3_Handler [WEAK] - EXPORT UARTRX4_Handler [WEAK] - EXPORT UARTTX4_Handler [WEAK] - EXPORT ADCSPI_Handler [WEAK] - EXPORT SHIELDSPI_Handler [WEAK] - EXPORT PORT0_0_Handler [WEAK] - EXPORT PORT0_1_Handler [WEAK] - EXPORT PORT0_2_Handler [WEAK] - EXPORT PORT0_3_Handler [WEAK] - EXPORT PORT0_4_Handler [WEAK] - EXPORT PORT0_5_Handler [WEAK] - EXPORT PORT0_6_Handler [WEAK] - EXPORT PORT0_7_Handler [WEAK] - -UARTRX0_Handler -UARTTX0_Handler -UARTRX1_Handler -UARTTX1_Handler -UARTRX2_Handler -UARTTX2_Handler -PORT0_COMB_Handler -PORT1_COMB_Handler -TIMER0_Handler -TIMER1_Handler -DUALTIMER_HANDLER -SPI_Handler -UARTOVF_Handler -ETHERNET_Handler -I2S_Handler -TSC_Handler -PORT2_COMB_Handler -PORT3_COMB_Handler -UARTRX3_Handler -UARTTX3_Handler -UARTRX4_Handler -UARTTX4_Handler -ADCSPI_Handler -SHIELDSPI_Handler -PORT0_0_Handler -PORT0_1_Handler -PORT0_2_Handler -PORT0_3_Handler -PORT0_4_Handler -PORT0_5_Handler -PORT0_6_Handler -PORT0_7_Handler - B . - - ENDP - - - ALIGN - - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap PROC - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDP - - ALIGN - - ENDIF - - - END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M4/device/TOOLCHAIN_ARM_STD/startup_MPS2.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,290 @@ +; MPS2 CMSIS Library +; +; Copyright (c) 2006-2016 ARM Limited +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; +; 3. Neither the name of the copyright holder nor the names of its contributors +; may be used to endorse or promote products derived from this software without +; specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +;****************************************************************************** +; @file startup_CMSDK_CM4.s +; @brief CMSIS Core Device Startup File for +; CMSDK_CM4 Device +; +;****************************************************************************** +; +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; + + +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00004000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00001000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD UARTRX0_Handler ; UART 0 RX Handler + DCD UARTTX0_Handler ; UART 0 TX Handler + DCD UARTRX1_Handler ; UART 1 RX Handler + DCD UARTTX1_Handler ; UART 1 TX Handler + DCD UARTRX2_Handler ; UART 2 RX Handler + DCD UARTTX2_Handler ; UART 2 TX Handler + DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler + DCD PORT1_COMB_Handler ; GPIO Port 1 Combined Handler + DCD TIMER0_Handler ; TIMER 0 handler + DCD TIMER1_Handler ; TIMER 1 handler + DCD DUALTIMER_HANDLER ; Dual timer handler + DCD SPI_Handler ; SPI exceptions Handler + DCD UARTOVF_Handler ; UART 0,1,2 Overflow Handler + DCD ETHERNET_Handler ; Ethernet Overflow Handler + DCD I2S_Handler ; I2S Handler + DCD TSC_Handler ; Touch Screen handler + DCD PORT2_COMB_Handler ; GPIO Port 2 Combined Handler + DCD PORT3_COMB_Handler ; GPIO Port 3 Combined Handler + DCD UARTRX3_Handler ; UART 3 RX Handler + DCD UARTTX3_Handler ; UART 3 TX Handler + DCD UARTRX4_Handler ; UART 4 RX Handler + DCD UARTTX4_Handler ; UART 4 TX Handler + DCD ADCSPI_Handler ; SHIELD ADC SPI exceptions Handler + DCD SHIELDSPI_Handler ; SHIELD SPI exceptions Handler + DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler + DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler + DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler + DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler + DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler + DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler + DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler + DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT UARTRX0_Handler [WEAK] + EXPORT UARTTX0_Handler [WEAK] + EXPORT UARTRX1_Handler [WEAK] + EXPORT UARTTX1_Handler [WEAK] + EXPORT UARTRX2_Handler [WEAK] + EXPORT UARTTX2_Handler [WEAK] + EXPORT PORT0_COMB_Handler [WEAK] + EXPORT PORT1_COMB_Handler [WEAK] + EXPORT TIMER0_Handler [WEAK] + EXPORT TIMER1_Handler [WEAK] + EXPORT DUALTIMER_HANDLER [WEAK] + EXPORT SPI_Handler [WEAK] + EXPORT UARTOVF_Handler [WEAK] + EXPORT ETHERNET_Handler [WEAK] + EXPORT I2S_Handler [WEAK] + EXPORT TSC_Handler [WEAK] + EXPORT PORT2_COMB_Handler [WEAK] + EXPORT PORT3_COMB_Handler [WEAK] + EXPORT UARTRX3_Handler [WEAK] + EXPORT UARTTX3_Handler [WEAK] + EXPORT UARTRX4_Handler [WEAK] + EXPORT UARTTX4_Handler [WEAK] + EXPORT ADCSPI_Handler [WEAK] + EXPORT SHIELDSPI_Handler [WEAK] + EXPORT PORT0_0_Handler [WEAK] + EXPORT PORT0_1_Handler [WEAK] + EXPORT PORT0_2_Handler [WEAK] + EXPORT PORT0_3_Handler [WEAK] + EXPORT PORT0_4_Handler [WEAK] + EXPORT PORT0_5_Handler [WEAK] + EXPORT PORT0_6_Handler [WEAK] + EXPORT PORT0_7_Handler [WEAK] + +UARTRX0_Handler +UARTTX0_Handler +UARTRX1_Handler +UARTTX1_Handler +UARTRX2_Handler +UARTTX2_Handler +PORT0_COMB_Handler +PORT1_COMB_Handler +TIMER0_Handler +TIMER1_Handler +DUALTIMER_HANDLER +SPI_Handler +UARTOVF_Handler +ETHERNET_Handler +I2S_Handler +TSC_Handler +PORT2_COMB_Handler +PORT3_COMB_Handler +UARTRX3_Handler +UARTTX3_Handler +UARTRX4_Handler +UARTTX4_Handler +ADCSPI_Handler +SHIELDSPI_Handler +PORT0_0_Handler +PORT0_1_Handler +PORT0_2_Handler +PORT0_3_Handler +PORT0_4_Handler +PORT0_5_Handler +PORT0_6_Handler +PORT0_7_Handler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END
--- a/targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M4/device/TOOLCHAIN_ARM_STD/startup_MPS2.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,290 +0,0 @@ -; MPS2 CMSIS Library -; -; Copyright (c) 2006-2016 ARM Limited -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, -; this list of conditions and the following disclaimer. -; -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; -; 3. Neither the name of the copyright holder nor the names of its contributors -; may be used to endorse or promote products derived from this software without -; specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; POSSIBILITY OF SUCH DAMAGE. -;****************************************************************************** -; @file startup_CMSDK_CM4.s -; @brief CMSIS Core Device Startup File for -; CMSDK_CM4 Device -; -;****************************************************************************** -; -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; - - -; <h> Stack Configuration -; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; </h> - -Stack_Size EQU 0x00004000 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; <h> Heap Configuration -; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; </h> - -Heap_Size EQU 0x00001000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD UARTRX0_Handler ; UART 0 RX Handler - DCD UARTTX0_Handler ; UART 0 TX Handler - DCD UARTRX1_Handler ; UART 1 RX Handler - DCD UARTTX1_Handler ; UART 1 TX Handler - DCD UARTRX2_Handler ; UART 2 RX Handler - DCD UARTTX2_Handler ; UART 2 TX Handler - DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler - DCD PORT1_COMB_Handler ; GPIO Port 1 Combined Handler - DCD TIMER0_Handler ; TIMER 0 handler - DCD TIMER1_Handler ; TIMER 1 handler - DCD DUALTIMER_HANDLER ; Dual timer handler - DCD SPI_Handler ; SPI exceptions Handler - DCD UARTOVF_Handler ; UART 0,1,2 Overflow Handler - DCD ETHERNET_Handler ; Ethernet Overflow Handler - DCD I2S_Handler ; I2S Handler - DCD TSC_Handler ; Touch Screen handler - DCD PORT2_COMB_Handler ; GPIO Port 2 Combined Handler - DCD PORT3_COMB_Handler ; GPIO Port 3 Combined Handler - DCD UARTRX3_Handler ; UART 3 RX Handler - DCD UARTTX3_Handler ; UART 3 TX Handler - DCD UARTRX4_Handler ; UART 4 RX Handler - DCD UARTTX4_Handler ; UART 4 TX Handler - DCD ADCSPI_Handler ; SHIELD ADC SPI exceptions Handler - DCD SHIELDSPI_Handler ; SHIELD SPI exceptions Handler - DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler - DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler - DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler - DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler - DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler - DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler - DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler - DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT UARTRX0_Handler [WEAK] - EXPORT UARTTX0_Handler [WEAK] - EXPORT UARTRX1_Handler [WEAK] - EXPORT UARTTX1_Handler [WEAK] - EXPORT UARTRX2_Handler [WEAK] - EXPORT UARTTX2_Handler [WEAK] - EXPORT PORT0_COMB_Handler [WEAK] - EXPORT PORT1_COMB_Handler [WEAK] - EXPORT TIMER0_Handler [WEAK] - EXPORT TIMER1_Handler [WEAK] - EXPORT DUALTIMER_HANDLER [WEAK] - EXPORT SPI_Handler [WEAK] - EXPORT UARTOVF_Handler [WEAK] - EXPORT ETHERNET_Handler [WEAK] - EXPORT I2S_Handler [WEAK] - EXPORT TSC_Handler [WEAK] - EXPORT PORT2_COMB_Handler [WEAK] - EXPORT PORT3_COMB_Handler [WEAK] - EXPORT UARTRX3_Handler [WEAK] - EXPORT UARTTX3_Handler [WEAK] - EXPORT UARTRX4_Handler [WEAK] - EXPORT UARTTX4_Handler [WEAK] - EXPORT ADCSPI_Handler [WEAK] - EXPORT SHIELDSPI_Handler [WEAK] - EXPORT PORT0_0_Handler [WEAK] - EXPORT PORT0_1_Handler [WEAK] - EXPORT PORT0_2_Handler [WEAK] - EXPORT PORT0_3_Handler [WEAK] - EXPORT PORT0_4_Handler [WEAK] - EXPORT PORT0_5_Handler [WEAK] - EXPORT PORT0_6_Handler [WEAK] - EXPORT PORT0_7_Handler [WEAK] - -UARTRX0_Handler -UARTTX0_Handler -UARTRX1_Handler -UARTTX1_Handler -UARTRX2_Handler -UARTTX2_Handler -PORT0_COMB_Handler -PORT1_COMB_Handler -TIMER0_Handler -TIMER1_Handler -DUALTIMER_HANDLER -SPI_Handler -UARTOVF_Handler -ETHERNET_Handler -I2S_Handler -TSC_Handler -PORT2_COMB_Handler -PORT3_COMB_Handler -UARTRX3_Handler -UARTTX3_Handler -UARTRX4_Handler -UARTTX4_Handler -ADCSPI_Handler -SHIELDSPI_Handler -PORT0_0_Handler -PORT0_1_Handler -PORT0_2_Handler -PORT0_3_Handler -PORT0_4_Handler -PORT0_5_Handler -PORT0_6_Handler -PORT0_7_Handler - B . - - ENDP - - - ALIGN - - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap PROC - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDP - - ALIGN - - ENDIF - - - END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M7/device/TOOLCHAIN_ARM_STD/startup_CMSDK_CM7.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,290 @@ +; MPS2 CMSIS Library +; +; Copyright (c) 2006-2016 ARM Limited +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, +; this list of conditions and the following disclaimer. +; +; 2. Redistributions in binary form must reproduce the above copyright notice, +; this list of conditions and the following disclaimer in the documentation +; and/or other materials provided with the distribution. +; +; 3. Neither the name of the copyright holder nor the names of its contributors +; may be used to endorse or promote products derived from this software without +; specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +;****************************************************************************** +; @file startup_CMSDK_CM7.s +; @brief CMSIS Core Device Startup File for +; CMSDK_CM7 Device +; +;****************************************************************************** +; +;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; + + +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00004000 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00001000 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD UARTRX0_Handler ; UART 0 RX Handler + DCD UARTTX0_Handler ; UART 0 TX Handler + DCD UARTRX1_Handler ; UART 1 RX Handler + DCD UARTTX1_Handler ; UART 1 TX Handler + DCD UARTRX2_Handler ; UART 2 RX Handler + DCD UARTTX2_Handler ; UART 2 TX Handler + DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler + DCD PORT1_COMB_Handler ; GPIO Port 1 Combined Handler + DCD TIMER0_Handler ; TIMER 0 handler + DCD TIMER1_Handler ; TIMER 1 handler + DCD DUALTIMER_HANDLER ; Dual timer handler + DCD SPI_Handler ; SPI exceptions Handler + DCD UARTOVF_Handler ; UART 0,1,2 Overflow Handler + DCD ETHERNET_Handler ; Ethernet Overflow Handler + DCD I2S_Handler ; I2S Handler + DCD TSC_Handler ; Touch Screen handler + DCD PORT2_COMB_Handler ; GPIO Port 2 Combined Handler + DCD PORT3_COMB_Handler ; GPIO Port 3 Combined Handler + DCD UARTRX3_Handler ; UART 3 RX Handler + DCD UARTTX3_Handler ; UART 3 TX Handler + DCD UARTRX4_Handler ; UART 4 RX Handler + DCD UARTTX4_Handler ; UART 4 TX Handler + DCD ADCSPI_Handler ; SHIELD ADC SPI exceptions Handler + DCD SHIELDSPI_Handler ; SHIELD SPI exceptions Handler + DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler + DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler + DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler + DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler + DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler + DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler + DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler + DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT UARTRX0_Handler [WEAK] + EXPORT UARTTX0_Handler [WEAK] + EXPORT UARTRX1_Handler [WEAK] + EXPORT UARTTX1_Handler [WEAK] + EXPORT UARTRX2_Handler [WEAK] + EXPORT UARTTX2_Handler [WEAK] + EXPORT PORT0_COMB_Handler [WEAK] + EXPORT PORT1_COMB_Handler [WEAK] + EXPORT TIMER0_Handler [WEAK] + EXPORT TIMER1_Handler [WEAK] + EXPORT DUALTIMER_HANDLER [WEAK] + EXPORT SPI_Handler [WEAK] + EXPORT UARTOVF_Handler [WEAK] + EXPORT ETHERNET_Handler [WEAK] + EXPORT I2S_Handler [WEAK] + EXPORT TSC_Handler [WEAK] + EXPORT PORT2_COMB_Handler [WEAK] + EXPORT PORT3_COMB_Handler [WEAK] + EXPORT UARTRX3_Handler [WEAK] + EXPORT UARTTX3_Handler [WEAK] + EXPORT UARTRX4_Handler [WEAK] + EXPORT UARTTX4_Handler [WEAK] + EXPORT ADCSPI_Handler [WEAK] + EXPORT SHIELDSPI_Handler [WEAK] + EXPORT PORT0_0_Handler [WEAK] + EXPORT PORT0_1_Handler [WEAK] + EXPORT PORT0_2_Handler [WEAK] + EXPORT PORT0_3_Handler [WEAK] + EXPORT PORT0_4_Handler [WEAK] + EXPORT PORT0_5_Handler [WEAK] + EXPORT PORT0_6_Handler [WEAK] + EXPORT PORT0_7_Handler [WEAK] + +UARTRX0_Handler +UARTTX0_Handler +UARTRX1_Handler +UARTTX1_Handler +UARTRX2_Handler +UARTTX2_Handler +PORT0_COMB_Handler +PORT1_COMB_Handler +TIMER0_Handler +TIMER1_Handler +DUALTIMER_HANDLER +SPI_Handler +UARTOVF_Handler +ETHERNET_Handler +I2S_Handler +TSC_Handler +PORT2_COMB_Handler +PORT3_COMB_Handler +UARTRX3_Handler +UARTTX3_Handler +UARTRX4_Handler +UARTTX4_Handler +ADCSPI_Handler +SHIELDSPI_Handler +PORT0_0_Handler +PORT0_1_Handler +PORT0_2_Handler +PORT0_3_Handler +PORT0_4_Handler +PORT0_5_Handler +PORT0_6_Handler +PORT0_7_Handler + B . + + ENDP + + + ALIGN + + +; User Initial Stack & Heap + + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + ENDIF + + + END
--- a/targets/TARGET_ARM_SSG/TARGET_MPS2/TARGET_MPS2_M7/device/TOOLCHAIN_ARM_STD/startup_CMSDK_CM7.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,290 +0,0 @@ -; MPS2 CMSIS Library -; -; Copyright (c) 2006-2016 ARM Limited -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; -; 1. Redistributions of source code must retain the above copyright notice, -; this list of conditions and the following disclaimer. -; -; 2. Redistributions in binary form must reproduce the above copyright notice, -; this list of conditions and the following disclaimer in the documentation -; and/or other materials provided with the distribution. -; -; 3. Neither the name of the copyright holder nor the names of its contributors -; may be used to endorse or promote products derived from this software without -; specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -; ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE -; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; POSSIBILITY OF SUCH DAMAGE. -;****************************************************************************** -; @file startup_CMSDK_CM7.s -; @brief CMSIS Core Device Startup File for -; CMSDK_CM7 Device -; -;****************************************************************************** -; -;-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; - - -; <h> Stack Configuration -; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; </h> - -Stack_Size EQU 0x00004000 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; <h> Heap Configuration -; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; </h> - -Heap_Size EQU 0x00001000 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD UARTRX0_Handler ; UART 0 RX Handler - DCD UARTTX0_Handler ; UART 0 TX Handler - DCD UARTRX1_Handler ; UART 1 RX Handler - DCD UARTTX1_Handler ; UART 1 TX Handler - DCD UARTRX2_Handler ; UART 2 RX Handler - DCD UARTTX2_Handler ; UART 2 TX Handler - DCD PORT0_COMB_Handler ; GPIO Port 0 Combined Handler - DCD PORT1_COMB_Handler ; GPIO Port 1 Combined Handler - DCD TIMER0_Handler ; TIMER 0 handler - DCD TIMER1_Handler ; TIMER 1 handler - DCD DUALTIMER_HANDLER ; Dual timer handler - DCD SPI_Handler ; SPI exceptions Handler - DCD UARTOVF_Handler ; UART 0,1,2 Overflow Handler - DCD ETHERNET_Handler ; Ethernet Overflow Handler - DCD I2S_Handler ; I2S Handler - DCD TSC_Handler ; Touch Screen handler - DCD PORT2_COMB_Handler ; GPIO Port 2 Combined Handler - DCD PORT3_COMB_Handler ; GPIO Port 3 Combined Handler - DCD UARTRX3_Handler ; UART 3 RX Handler - DCD UARTTX3_Handler ; UART 3 TX Handler - DCD UARTRX4_Handler ; UART 4 RX Handler - DCD UARTTX4_Handler ; UART 4 TX Handler - DCD ADCSPI_Handler ; SHIELD ADC SPI exceptions Handler - DCD SHIELDSPI_Handler ; SHIELD SPI exceptions Handler - DCD PORT0_0_Handler ; GPIO Port 0 pin 0 Handler - DCD PORT0_1_Handler ; GPIO Port 0 pin 1 Handler - DCD PORT0_2_Handler ; GPIO Port 0 pin 2 Handler - DCD PORT0_3_Handler ; GPIO Port 0 pin 3 Handler - DCD PORT0_4_Handler ; GPIO Port 0 pin 4 Handler - DCD PORT0_5_Handler ; GPIO Port 0 pin 5 Handler - DCD PORT0_6_Handler ; GPIO Port 0 pin 6 Handler - DCD PORT0_7_Handler ; GPIO Port 0 pin 7 Handler -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT UARTRX0_Handler [WEAK] - EXPORT UARTTX0_Handler [WEAK] - EXPORT UARTRX1_Handler [WEAK] - EXPORT UARTTX1_Handler [WEAK] - EXPORT UARTRX2_Handler [WEAK] - EXPORT UARTTX2_Handler [WEAK] - EXPORT PORT0_COMB_Handler [WEAK] - EXPORT PORT1_COMB_Handler [WEAK] - EXPORT TIMER0_Handler [WEAK] - EXPORT TIMER1_Handler [WEAK] - EXPORT DUALTIMER_HANDLER [WEAK] - EXPORT SPI_Handler [WEAK] - EXPORT UARTOVF_Handler [WEAK] - EXPORT ETHERNET_Handler [WEAK] - EXPORT I2S_Handler [WEAK] - EXPORT TSC_Handler [WEAK] - EXPORT PORT2_COMB_Handler [WEAK] - EXPORT PORT3_COMB_Handler [WEAK] - EXPORT UARTRX3_Handler [WEAK] - EXPORT UARTTX3_Handler [WEAK] - EXPORT UARTRX4_Handler [WEAK] - EXPORT UARTTX4_Handler [WEAK] - EXPORT ADCSPI_Handler [WEAK] - EXPORT SHIELDSPI_Handler [WEAK] - EXPORT PORT0_0_Handler [WEAK] - EXPORT PORT0_1_Handler [WEAK] - EXPORT PORT0_2_Handler [WEAK] - EXPORT PORT0_3_Handler [WEAK] - EXPORT PORT0_4_Handler [WEAK] - EXPORT PORT0_5_Handler [WEAK] - EXPORT PORT0_6_Handler [WEAK] - EXPORT PORT0_7_Handler [WEAK] - -UARTRX0_Handler -UARTTX0_Handler -UARTRX1_Handler -UARTTX1_Handler -UARTRX2_Handler -UARTTX2_Handler -PORT0_COMB_Handler -PORT1_COMB_Handler -TIMER0_Handler -TIMER1_Handler -DUALTIMER_HANDLER -SPI_Handler -UARTOVF_Handler -ETHERNET_Handler -I2S_Handler -TSC_Handler -PORT2_COMB_Handler -PORT3_COMB_Handler -UARTRX3_Handler -UARTTX3_Handler -UARTRX4_Handler -UARTTX4_Handler -ADCSPI_Handler -SHIELDSPI_Handler -PORT0_0_Handler -PORT0_1_Handler -PORT0_2_Handler -PORT0_3_Handler -PORT0_4_Handler -PORT0_5_Handler -PORT0_6_Handler -PORT0_7_Handler - B . - - ENDP - - - ALIGN - - -; User Initial Stack & Heap - - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap PROC - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDP - - ALIGN - - ENDIF - - - END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_ARM_MICRO/startup_SAMD21.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,190 @@ +;/***************************************************************************** +; * @file startup_SAMD21.s +; * @brief CMSIS Cortex-M0+ Core Device Startup File for +; * Atmel SAMD21 Device Series +; * @version V1.00 +; * @date 24. February 2014 +; * +; * @note +; * Copyright (C) 2014 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ +__initial_sp EQU 0x20008000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PM_Handler ; 0 Power Manager + DCD SYSCTRL_Handler ; 1 System Control + DCD WDT_Handler ; 2 Watchdog Timer + DCD RTC_Handler ; 3 Real-Time Counter + DCD EIC_Handler ; 4 External Interrupt Controller + DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller + DCD DMAC_Handler ; 6 Direct Memory Access Controller + DCD USB_Handler ; 7 Universal Serial Bus + DCD EVSYS_Handler ; 8 Event System Interface + DCD SERCOM0_Handler ; 9 Serial Communication Interface 0 + DCD SERCOM1_Handler ; 10 Serial Communication Interface 1 + DCD SERCOM2_Handler ; 11 Serial Communication Interface 2 + DCD SERCOM3_Handler ; 12 Serial Communication Interface 3 + DCD SERCOM4_Handler ; 13 Serial Communication Interface 4 + DCD SERCOM5_Handler ; 14 Serial Communication Interface 5 + DCD TCC0_Handler ; 15 Timer Counter Control 0 + DCD TCC1_Handler ; 16 Timer Counter Control 1 + DCD TCC2_Handler ; 17 Timer Counter Control 2 + DCD TC3_Handler ; 18 Basic Timer Counter 0 + DCD TC4_Handler ; 19 Basic Timer Counter 1 + DCD TC5_Handler ; 20 Basic Timer Counter 2 + DCD TC6_Handler ; 21 Basic Timer Counter 3 + DCD TC7_Handler ; 22 Basic Timer Counter 4 + DCD ADC_Handler ; 23 Analog Digital Converter + DCD AC_Handler ; 24 Analog Comparators + DCD DAC_Handler ; 25 Digital Analog Converter + DCD PTC_Handler ; 26 Peripheral Touch Controller + DCD I2S_Handler ; 27 Inter-IC Sound Interface +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT PM_Handler [WEAK] + EXPORT PM_Handler [WEAK] + EXPORT SYSCTRL_Handler [WEAK] + EXPORT WDT_Handler [WEAK] + EXPORT RTC_Handler [WEAK] + EXPORT EIC_Handler [WEAK] + EXPORT NVMCTRL_Handler [WEAK] + EXPORT DMAC_Handler [WEAK] + EXPORT USB_Handler [WEAK] + EXPORT EVSYS_Handler [WEAK] + EXPORT SERCOM0_Handler [WEAK] + EXPORT SERCOM1_Handler [WEAK] + EXPORT SERCOM2_Handler [WEAK] + EXPORT SERCOM3_Handler [WEAK] + EXPORT SERCOM4_Handler [WEAK] + EXPORT SERCOM5_Handler [WEAK] + EXPORT TCC0_Handler [WEAK] + EXPORT TCC1_Handler [WEAK] + EXPORT TCC2_Handler [WEAK] + EXPORT TC3_Handler [WEAK] + EXPORT TC4_Handler [WEAK] + EXPORT TC5_Handler [WEAK] + EXPORT TC6_Handler [WEAK] + EXPORT TC7_Handler [WEAK] + EXPORT ADC_Handler [WEAK] + EXPORT AC_Handler [WEAK] + EXPORT DAC_Handler [WEAK] + EXPORT PTC_Handler [WEAK] + EXPORT I2S_Handler [WEAK] + +PM_Handler +SYSCTRL_Handler +WDT_Handler +RTC_Handler +EIC_Handler +NVMCTRL_Handler +DMAC_Handler +USB_Handler +EVSYS_Handler +SERCOM0_Handler +SERCOM1_Handler +SERCOM2_Handler +SERCOM3_Handler +SERCOM4_Handler +SERCOM5_Handler +TCC0_Handler +TCC1_Handler +TCC2_Handler +TC3_Handler +TC4_Handler +TC5_Handler +TC6_Handler +TC7_Handler +ADC_Handler +AC_Handler +DAC_Handler +PTC_Handler +I2S_Handler + B . + ENDP + + + ALIGN + END
--- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_ARM_MICRO/startup_SAMD21.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,190 +0,0 @@ -;/***************************************************************************** -; * @file startup_SAMD21.s -; * @brief CMSIS Cortex-M0+ Core Device Startup File for -; * Atmel SAMD21 Device Series -; * @version V1.00 -; * @date 24. February 2014 -; * -; * @note -; * Copyright (C) 2014 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ -__initial_sp EQU 0x20008000 ; Top of RAM - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD PM_Handler ; 0 Power Manager - DCD SYSCTRL_Handler ; 1 System Control - DCD WDT_Handler ; 2 Watchdog Timer - DCD RTC_Handler ; 3 Real-Time Counter - DCD EIC_Handler ; 4 External Interrupt Controller - DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller - DCD DMAC_Handler ; 6 Direct Memory Access Controller - DCD USB_Handler ; 7 Universal Serial Bus - DCD EVSYS_Handler ; 8 Event System Interface - DCD SERCOM0_Handler ; 9 Serial Communication Interface 0 - DCD SERCOM1_Handler ; 10 Serial Communication Interface 1 - DCD SERCOM2_Handler ; 11 Serial Communication Interface 2 - DCD SERCOM3_Handler ; 12 Serial Communication Interface 3 - DCD SERCOM4_Handler ; 13 Serial Communication Interface 4 - DCD SERCOM5_Handler ; 14 Serial Communication Interface 5 - DCD TCC0_Handler ; 15 Timer Counter Control 0 - DCD TCC1_Handler ; 16 Timer Counter Control 1 - DCD TCC2_Handler ; 17 Timer Counter Control 2 - DCD TC3_Handler ; 18 Basic Timer Counter 0 - DCD TC4_Handler ; 19 Basic Timer Counter 1 - DCD TC5_Handler ; 20 Basic Timer Counter 2 - DCD TC6_Handler ; 21 Basic Timer Counter 3 - DCD TC7_Handler ; 22 Basic Timer Counter 4 - DCD ADC_Handler ; 23 Analog Digital Converter - DCD AC_Handler ; 24 Analog Comparators - DCD DAC_Handler ; 25 Digital Analog Converter - DCD PTC_Handler ; 26 Peripheral Touch Controller - DCD I2S_Handler ; 27 Inter-IC Sound Interface -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT PM_Handler [WEAK] - EXPORT PM_Handler [WEAK] - EXPORT SYSCTRL_Handler [WEAK] - EXPORT WDT_Handler [WEAK] - EXPORT RTC_Handler [WEAK] - EXPORT EIC_Handler [WEAK] - EXPORT NVMCTRL_Handler [WEAK] - EXPORT DMAC_Handler [WEAK] - EXPORT USB_Handler [WEAK] - EXPORT EVSYS_Handler [WEAK] - EXPORT SERCOM0_Handler [WEAK] - EXPORT SERCOM1_Handler [WEAK] - EXPORT SERCOM2_Handler [WEAK] - EXPORT SERCOM3_Handler [WEAK] - EXPORT SERCOM4_Handler [WEAK] - EXPORT SERCOM5_Handler [WEAK] - EXPORT TCC0_Handler [WEAK] - EXPORT TCC1_Handler [WEAK] - EXPORT TCC2_Handler [WEAK] - EXPORT TC3_Handler [WEAK] - EXPORT TC4_Handler [WEAK] - EXPORT TC5_Handler [WEAK] - EXPORT TC6_Handler [WEAK] - EXPORT TC7_Handler [WEAK] - EXPORT ADC_Handler [WEAK] - EXPORT AC_Handler [WEAK] - EXPORT DAC_Handler [WEAK] - EXPORT PTC_Handler [WEAK] - EXPORT I2S_Handler [WEAK] - -PM_Handler -SYSCTRL_Handler -WDT_Handler -RTC_Handler -EIC_Handler -NVMCTRL_Handler -DMAC_Handler -USB_Handler -EVSYS_Handler -SERCOM0_Handler -SERCOM1_Handler -SERCOM2_Handler -SERCOM3_Handler -SERCOM4_Handler -SERCOM5_Handler -TCC0_Handler -TCC1_Handler -TCC2_Handler -TC3_Handler -TC4_Handler -TC5_Handler -TC6_Handler -TC7_Handler -ADC_Handler -AC_Handler -DAC_Handler -PTC_Handler -I2S_Handler - B . - ENDP - - - ALIGN - END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_ARM_STD/startup_SAMD21.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,190 @@ +;/***************************************************************************** +; * @file startup_SAMD21.s +; * @brief CMSIS Cortex-M0+ Core Device Startup File for +; * Atmel SAMD21 Device Series +; * @version V1.00 +; * @date 24. February 2014 +; * +; * @note +; * Copyright (C) 2014 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ +__initial_sp EQU 0x20008000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PM_Handler ; 0 Power Manager + DCD SYSCTRL_Handler ; 1 System Control + DCD WDT_Handler ; 2 Watchdog Timer + DCD RTC_Handler ; 3 Real-Time Counter + DCD EIC_Handler ; 4 External Interrupt Controller + DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller + DCD DMAC_Handler ; 6 Direct Memory Access Controller + DCD USB_Handler ; 7 Universal Serial Bus + DCD EVSYS_Handler ; 8 Event System Interface + DCD SERCOM0_Handler ; 9 Serial Communication Interface 0 + DCD SERCOM1_Handler ; 10 Serial Communication Interface 1 + DCD SERCOM2_Handler ; 11 Serial Communication Interface 2 + DCD SERCOM3_Handler ; 12 Serial Communication Interface 3 + DCD SERCOM4_Handler ; 13 Serial Communication Interface 4 + DCD SERCOM5_Handler ; 14 Serial Communication Interface 5 + DCD TCC0_Handler ; 15 Timer Counter Control 0 + DCD TCC1_Handler ; 16 Timer Counter Control 1 + DCD TCC2_Handler ; 17 Timer Counter Control 2 + DCD TC3_Handler ; 18 Basic Timer Counter 0 + DCD TC4_Handler ; 19 Basic Timer Counter 1 + DCD TC5_Handler ; 20 Basic Timer Counter 2 + DCD TC6_Handler ; 21 Basic Timer Counter 3 + DCD TC7_Handler ; 22 Basic Timer Counter 4 + DCD ADC_Handler ; 23 Analog Digital Converter + DCD AC_Handler ; 24 Analog Comparators + DCD DAC_Handler ; 25 Digital Analog Converter + DCD PTC_Handler ; 26 Peripheral Touch Controller + DCD I2S_Handler ; 27 Inter-IC Sound Interface +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT PM_Handler [WEAK] + EXPORT PM_Handler [WEAK] + EXPORT SYSCTRL_Handler [WEAK] + EXPORT WDT_Handler [WEAK] + EXPORT RTC_Handler [WEAK] + EXPORT EIC_Handler [WEAK] + EXPORT NVMCTRL_Handler [WEAK] + EXPORT DMAC_Handler [WEAK] + EXPORT USB_Handler [WEAK] + EXPORT EVSYS_Handler [WEAK] + EXPORT SERCOM0_Handler [WEAK] + EXPORT SERCOM1_Handler [WEAK] + EXPORT SERCOM2_Handler [WEAK] + EXPORT SERCOM3_Handler [WEAK] + EXPORT SERCOM4_Handler [WEAK] + EXPORT SERCOM5_Handler [WEAK] + EXPORT TCC0_Handler [WEAK] + EXPORT TCC1_Handler [WEAK] + EXPORT TCC2_Handler [WEAK] + EXPORT TC3_Handler [WEAK] + EXPORT TC4_Handler [WEAK] + EXPORT TC5_Handler [WEAK] + EXPORT TC6_Handler [WEAK] + EXPORT TC7_Handler [WEAK] + EXPORT ADC_Handler [WEAK] + EXPORT AC_Handler [WEAK] + EXPORT DAC_Handler [WEAK] + EXPORT PTC_Handler [WEAK] + EXPORT I2S_Handler [WEAK] + +PM_Handler +SYSCTRL_Handler +WDT_Handler +RTC_Handler +EIC_Handler +NVMCTRL_Handler +DMAC_Handler +USB_Handler +EVSYS_Handler +SERCOM0_Handler +SERCOM1_Handler +SERCOM2_Handler +SERCOM3_Handler +SERCOM4_Handler +SERCOM5_Handler +TCC0_Handler +TCC1_Handler +TCC2_Handler +TC3_Handler +TC4_Handler +TC5_Handler +TC6_Handler +TC7_Handler +ADC_Handler +AC_Handler +DAC_Handler +PTC_Handler +I2S_Handler + B . + ENDP + + + ALIGN + END
--- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21G18A/device/TOOLCHAIN_ARM_STD/startup_SAMD21.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,190 +0,0 @@ -;/***************************************************************************** -; * @file startup_SAMD21.s -; * @brief CMSIS Cortex-M0+ Core Device Startup File for -; * Atmel SAMD21 Device Series -; * @version V1.00 -; * @date 24. February 2014 -; * -; * @note -; * Copyright (C) 2014 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ -__initial_sp EQU 0x20008000 ; Top of RAM - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD PM_Handler ; 0 Power Manager - DCD SYSCTRL_Handler ; 1 System Control - DCD WDT_Handler ; 2 Watchdog Timer - DCD RTC_Handler ; 3 Real-Time Counter - DCD EIC_Handler ; 4 External Interrupt Controller - DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller - DCD DMAC_Handler ; 6 Direct Memory Access Controller - DCD USB_Handler ; 7 Universal Serial Bus - DCD EVSYS_Handler ; 8 Event System Interface - DCD SERCOM0_Handler ; 9 Serial Communication Interface 0 - DCD SERCOM1_Handler ; 10 Serial Communication Interface 1 - DCD SERCOM2_Handler ; 11 Serial Communication Interface 2 - DCD SERCOM3_Handler ; 12 Serial Communication Interface 3 - DCD SERCOM4_Handler ; 13 Serial Communication Interface 4 - DCD SERCOM5_Handler ; 14 Serial Communication Interface 5 - DCD TCC0_Handler ; 15 Timer Counter Control 0 - DCD TCC1_Handler ; 16 Timer Counter Control 1 - DCD TCC2_Handler ; 17 Timer Counter Control 2 - DCD TC3_Handler ; 18 Basic Timer Counter 0 - DCD TC4_Handler ; 19 Basic Timer Counter 1 - DCD TC5_Handler ; 20 Basic Timer Counter 2 - DCD TC6_Handler ; 21 Basic Timer Counter 3 - DCD TC7_Handler ; 22 Basic Timer Counter 4 - DCD ADC_Handler ; 23 Analog Digital Converter - DCD AC_Handler ; 24 Analog Comparators - DCD DAC_Handler ; 25 Digital Analog Converter - DCD PTC_Handler ; 26 Peripheral Touch Controller - DCD I2S_Handler ; 27 Inter-IC Sound Interface -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT PM_Handler [WEAK] - EXPORT PM_Handler [WEAK] - EXPORT SYSCTRL_Handler [WEAK] - EXPORT WDT_Handler [WEAK] - EXPORT RTC_Handler [WEAK] - EXPORT EIC_Handler [WEAK] - EXPORT NVMCTRL_Handler [WEAK] - EXPORT DMAC_Handler [WEAK] - EXPORT USB_Handler [WEAK] - EXPORT EVSYS_Handler [WEAK] - EXPORT SERCOM0_Handler [WEAK] - EXPORT SERCOM1_Handler [WEAK] - EXPORT SERCOM2_Handler [WEAK] - EXPORT SERCOM3_Handler [WEAK] - EXPORT SERCOM4_Handler [WEAK] - EXPORT SERCOM5_Handler [WEAK] - EXPORT TCC0_Handler [WEAK] - EXPORT TCC1_Handler [WEAK] - EXPORT TCC2_Handler [WEAK] - EXPORT TC3_Handler [WEAK] - EXPORT TC4_Handler [WEAK] - EXPORT TC5_Handler [WEAK] - EXPORT TC6_Handler [WEAK] - EXPORT TC7_Handler [WEAK] - EXPORT ADC_Handler [WEAK] - EXPORT AC_Handler [WEAK] - EXPORT DAC_Handler [WEAK] - EXPORT PTC_Handler [WEAK] - EXPORT I2S_Handler [WEAK] - -PM_Handler -SYSCTRL_Handler -WDT_Handler -RTC_Handler -EIC_Handler -NVMCTRL_Handler -DMAC_Handler -USB_Handler -EVSYS_Handler -SERCOM0_Handler -SERCOM1_Handler -SERCOM2_Handler -SERCOM3_Handler -SERCOM4_Handler -SERCOM5_Handler -TCC0_Handler -TCC1_Handler -TCC2_Handler -TC3_Handler -TC4_Handler -TC5_Handler -TC6_Handler -TC7_Handler -ADC_Handler -AC_Handler -DAC_Handler -PTC_Handler -I2S_Handler - B . - ENDP - - - ALIGN - END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_ARM_MICRO/startup_SAMD21.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,190 @@ +;/***************************************************************************** +; * @file startup_SAMD21.s +; * @brief CMSIS Cortex-M0+ Core Device Startup File for +; * Atmel SAMD21 Device Series +; * @version V1.00 +; * @date 24. February 2014 +; * +; * @note +; * Copyright (C) 2014 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ +__initial_sp EQU 0x20008000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PM_Handler ; 0 Power Manager + DCD SYSCTRL_Handler ; 1 System Control + DCD WDT_Handler ; 2 Watchdog Timer + DCD RTC_Handler ; 3 Real-Time Counter + DCD EIC_Handler ; 4 External Interrupt Controller + DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller + DCD DMAC_Handler ; 6 Direct Memory Access Controller + DCD USB_Handler ; 7 Universal Serial Bus + DCD EVSYS_Handler ; 8 Event System Interface + DCD SERCOM0_Handler ; 9 Serial Communication Interface 0 + DCD SERCOM1_Handler ; 10 Serial Communication Interface 1 + DCD SERCOM2_Handler ; 11 Serial Communication Interface 2 + DCD SERCOM3_Handler ; 12 Serial Communication Interface 3 + DCD SERCOM4_Handler ; 13 Serial Communication Interface 4 + DCD SERCOM5_Handler ; 14 Serial Communication Interface 5 + DCD TCC0_Handler ; 15 Timer Counter Control 0 + DCD TCC1_Handler ; 16 Timer Counter Control 1 + DCD TCC2_Handler ; 17 Timer Counter Control 2 + DCD TC3_Handler ; 18 Basic Timer Counter 0 + DCD TC4_Handler ; 19 Basic Timer Counter 1 + DCD TC5_Handler ; 20 Basic Timer Counter 2 + DCD TC6_Handler ; 21 Basic Timer Counter 3 + DCD TC7_Handler ; 22 Basic Timer Counter 4 + DCD ADC_Handler ; 23 Analog Digital Converter + DCD AC_Handler ; 24 Analog Comparators + DCD DAC_Handler ; 25 Digital Analog Converter + DCD PTC_Handler ; 26 Peripheral Touch Controller + DCD I2S_Handler ; 27 Inter-IC Sound Interface +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT PM_Handler [WEAK] + EXPORT PM_Handler [WEAK] + EXPORT SYSCTRL_Handler [WEAK] + EXPORT WDT_Handler [WEAK] + EXPORT RTC_Handler [WEAK] + EXPORT EIC_Handler [WEAK] + EXPORT NVMCTRL_Handler [WEAK] + EXPORT DMAC_Handler [WEAK] + EXPORT USB_Handler [WEAK] + EXPORT EVSYS_Handler [WEAK] + EXPORT SERCOM0_Handler [WEAK] + EXPORT SERCOM1_Handler [WEAK] + EXPORT SERCOM2_Handler [WEAK] + EXPORT SERCOM3_Handler [WEAK] + EXPORT SERCOM4_Handler [WEAK] + EXPORT SERCOM5_Handler [WEAK] + EXPORT TCC0_Handler [WEAK] + EXPORT TCC1_Handler [WEAK] + EXPORT TCC2_Handler [WEAK] + EXPORT TC3_Handler [WEAK] + EXPORT TC4_Handler [WEAK] + EXPORT TC5_Handler [WEAK] + EXPORT TC6_Handler [WEAK] + EXPORT TC7_Handler [WEAK] + EXPORT ADC_Handler [WEAK] + EXPORT AC_Handler [WEAK] + EXPORT DAC_Handler [WEAK] + EXPORT PTC_Handler [WEAK] + EXPORT I2S_Handler [WEAK] + +PM_Handler +SYSCTRL_Handler +WDT_Handler +RTC_Handler +EIC_Handler +NVMCTRL_Handler +DMAC_Handler +USB_Handler +EVSYS_Handler +SERCOM0_Handler +SERCOM1_Handler +SERCOM2_Handler +SERCOM3_Handler +SERCOM4_Handler +SERCOM5_Handler +TCC0_Handler +TCC1_Handler +TCC2_Handler +TC3_Handler +TC4_Handler +TC5_Handler +TC6_Handler +TC7_Handler +ADC_Handler +AC_Handler +DAC_Handler +PTC_Handler +I2S_Handler + B . + ENDP + + + ALIGN + END
--- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_ARM_MICRO/startup_SAMD21.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,190 +0,0 @@ -;/***************************************************************************** -; * @file startup_SAMD21.s -; * @brief CMSIS Cortex-M0+ Core Device Startup File for -; * Atmel SAMD21 Device Series -; * @version V1.00 -; * @date 24. February 2014 -; * -; * @note -; * Copyright (C) 2014 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ -__initial_sp EQU 0x20008000 ; Top of RAM - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD PM_Handler ; 0 Power Manager - DCD SYSCTRL_Handler ; 1 System Control - DCD WDT_Handler ; 2 Watchdog Timer - DCD RTC_Handler ; 3 Real-Time Counter - DCD EIC_Handler ; 4 External Interrupt Controller - DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller - DCD DMAC_Handler ; 6 Direct Memory Access Controller - DCD USB_Handler ; 7 Universal Serial Bus - DCD EVSYS_Handler ; 8 Event System Interface - DCD SERCOM0_Handler ; 9 Serial Communication Interface 0 - DCD SERCOM1_Handler ; 10 Serial Communication Interface 1 - DCD SERCOM2_Handler ; 11 Serial Communication Interface 2 - DCD SERCOM3_Handler ; 12 Serial Communication Interface 3 - DCD SERCOM4_Handler ; 13 Serial Communication Interface 4 - DCD SERCOM5_Handler ; 14 Serial Communication Interface 5 - DCD TCC0_Handler ; 15 Timer Counter Control 0 - DCD TCC1_Handler ; 16 Timer Counter Control 1 - DCD TCC2_Handler ; 17 Timer Counter Control 2 - DCD TC3_Handler ; 18 Basic Timer Counter 0 - DCD TC4_Handler ; 19 Basic Timer Counter 1 - DCD TC5_Handler ; 20 Basic Timer Counter 2 - DCD TC6_Handler ; 21 Basic Timer Counter 3 - DCD TC7_Handler ; 22 Basic Timer Counter 4 - DCD ADC_Handler ; 23 Analog Digital Converter - DCD AC_Handler ; 24 Analog Comparators - DCD DAC_Handler ; 25 Digital Analog Converter - DCD PTC_Handler ; 26 Peripheral Touch Controller - DCD I2S_Handler ; 27 Inter-IC Sound Interface -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT PM_Handler [WEAK] - EXPORT PM_Handler [WEAK] - EXPORT SYSCTRL_Handler [WEAK] - EXPORT WDT_Handler [WEAK] - EXPORT RTC_Handler [WEAK] - EXPORT EIC_Handler [WEAK] - EXPORT NVMCTRL_Handler [WEAK] - EXPORT DMAC_Handler [WEAK] - EXPORT USB_Handler [WEAK] - EXPORT EVSYS_Handler [WEAK] - EXPORT SERCOM0_Handler [WEAK] - EXPORT SERCOM1_Handler [WEAK] - EXPORT SERCOM2_Handler [WEAK] - EXPORT SERCOM3_Handler [WEAK] - EXPORT SERCOM4_Handler [WEAK] - EXPORT SERCOM5_Handler [WEAK] - EXPORT TCC0_Handler [WEAK] - EXPORT TCC1_Handler [WEAK] - EXPORT TCC2_Handler [WEAK] - EXPORT TC3_Handler [WEAK] - EXPORT TC4_Handler [WEAK] - EXPORT TC5_Handler [WEAK] - EXPORT TC6_Handler [WEAK] - EXPORT TC7_Handler [WEAK] - EXPORT ADC_Handler [WEAK] - EXPORT AC_Handler [WEAK] - EXPORT DAC_Handler [WEAK] - EXPORT PTC_Handler [WEAK] - EXPORT I2S_Handler [WEAK] - -PM_Handler -SYSCTRL_Handler -WDT_Handler -RTC_Handler -EIC_Handler -NVMCTRL_Handler -DMAC_Handler -USB_Handler -EVSYS_Handler -SERCOM0_Handler -SERCOM1_Handler -SERCOM2_Handler -SERCOM3_Handler -SERCOM4_Handler -SERCOM5_Handler -TCC0_Handler -TCC1_Handler -TCC2_Handler -TC3_Handler -TC4_Handler -TC5_Handler -TC6_Handler -TC7_Handler -ADC_Handler -AC_Handler -DAC_Handler -PTC_Handler -I2S_Handler - B . - ENDP - - - ALIGN - END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_ARM_STD/startup_SAMD21.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,190 @@ +;/***************************************************************************** +; * @file startup_SAMD21.s +; * @brief CMSIS Cortex-M0+ Core Device Startup File for +; * Atmel SAMD21 Device Series +; * @version V1.00 +; * @date 24. February 2014 +; * +; * @note +; * Copyright (C) 2014 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ +__initial_sp EQU 0x20008000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PM_Handler ; 0 Power Manager + DCD SYSCTRL_Handler ; 1 System Control + DCD WDT_Handler ; 2 Watchdog Timer + DCD RTC_Handler ; 3 Real-Time Counter + DCD EIC_Handler ; 4 External Interrupt Controller + DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller + DCD DMAC_Handler ; 6 Direct Memory Access Controller + DCD USB_Handler ; 7 Universal Serial Bus + DCD EVSYS_Handler ; 8 Event System Interface + DCD SERCOM0_Handler ; 9 Serial Communication Interface 0 + DCD SERCOM1_Handler ; 10 Serial Communication Interface 1 + DCD SERCOM2_Handler ; 11 Serial Communication Interface 2 + DCD SERCOM3_Handler ; 12 Serial Communication Interface 3 + DCD SERCOM4_Handler ; 13 Serial Communication Interface 4 + DCD SERCOM5_Handler ; 14 Serial Communication Interface 5 + DCD TCC0_Handler ; 15 Timer Counter Control 0 + DCD TCC1_Handler ; 16 Timer Counter Control 1 + DCD TCC2_Handler ; 17 Timer Counter Control 2 + DCD TC3_Handler ; 18 Basic Timer Counter 0 + DCD TC4_Handler ; 19 Basic Timer Counter 1 + DCD TC5_Handler ; 20 Basic Timer Counter 2 + DCD TC6_Handler ; 21 Basic Timer Counter 3 + DCD TC7_Handler ; 22 Basic Timer Counter 4 + DCD ADC_Handler ; 23 Analog Digital Converter + DCD AC_Handler ; 24 Analog Comparators + DCD DAC_Handler ; 25 Digital Analog Converter + DCD PTC_Handler ; 26 Peripheral Touch Controller + DCD I2S_Handler ; 27 Inter-IC Sound Interface +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT PM_Handler [WEAK] + EXPORT PM_Handler [WEAK] + EXPORT SYSCTRL_Handler [WEAK] + EXPORT WDT_Handler [WEAK] + EXPORT RTC_Handler [WEAK] + EXPORT EIC_Handler [WEAK] + EXPORT NVMCTRL_Handler [WEAK] + EXPORT DMAC_Handler [WEAK] + EXPORT USB_Handler [WEAK] + EXPORT EVSYS_Handler [WEAK] + EXPORT SERCOM0_Handler [WEAK] + EXPORT SERCOM1_Handler [WEAK] + EXPORT SERCOM2_Handler [WEAK] + EXPORT SERCOM3_Handler [WEAK] + EXPORT SERCOM4_Handler [WEAK] + EXPORT SERCOM5_Handler [WEAK] + EXPORT TCC0_Handler [WEAK] + EXPORT TCC1_Handler [WEAK] + EXPORT TCC2_Handler [WEAK] + EXPORT TC3_Handler [WEAK] + EXPORT TC4_Handler [WEAK] + EXPORT TC5_Handler [WEAK] + EXPORT TC6_Handler [WEAK] + EXPORT TC7_Handler [WEAK] + EXPORT ADC_Handler [WEAK] + EXPORT AC_Handler [WEAK] + EXPORT DAC_Handler [WEAK] + EXPORT PTC_Handler [WEAK] + EXPORT I2S_Handler [WEAK] + +PM_Handler +SYSCTRL_Handler +WDT_Handler +RTC_Handler +EIC_Handler +NVMCTRL_Handler +DMAC_Handler +USB_Handler +EVSYS_Handler +SERCOM0_Handler +SERCOM1_Handler +SERCOM2_Handler +SERCOM3_Handler +SERCOM4_Handler +SERCOM5_Handler +TCC0_Handler +TCC1_Handler +TCC2_Handler +TC3_Handler +TC4_Handler +TC5_Handler +TC6_Handler +TC7_Handler +ADC_Handler +AC_Handler +DAC_Handler +PTC_Handler +I2S_Handler + B . + ENDP + + + ALIGN + END
--- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMD21J18A/device/TOOLCHAIN_ARM_STD/startup_SAMD21.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,190 +0,0 @@ -;/***************************************************************************** -; * @file startup_SAMD21.s -; * @brief CMSIS Cortex-M0+ Core Device Startup File for -; * Atmel SAMD21 Device Series -; * @version V1.00 -; * @date 24. February 2014 -; * -; * @note -; * Copyright (C) 2014 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ -__initial_sp EQU 0x20008000 ; Top of RAM - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD PM_Handler ; 0 Power Manager - DCD SYSCTRL_Handler ; 1 System Control - DCD WDT_Handler ; 2 Watchdog Timer - DCD RTC_Handler ; 3 Real-Time Counter - DCD EIC_Handler ; 4 External Interrupt Controller - DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller - DCD DMAC_Handler ; 6 Direct Memory Access Controller - DCD USB_Handler ; 7 Universal Serial Bus - DCD EVSYS_Handler ; 8 Event System Interface - DCD SERCOM0_Handler ; 9 Serial Communication Interface 0 - DCD SERCOM1_Handler ; 10 Serial Communication Interface 1 - DCD SERCOM2_Handler ; 11 Serial Communication Interface 2 - DCD SERCOM3_Handler ; 12 Serial Communication Interface 3 - DCD SERCOM4_Handler ; 13 Serial Communication Interface 4 - DCD SERCOM5_Handler ; 14 Serial Communication Interface 5 - DCD TCC0_Handler ; 15 Timer Counter Control 0 - DCD TCC1_Handler ; 16 Timer Counter Control 1 - DCD TCC2_Handler ; 17 Timer Counter Control 2 - DCD TC3_Handler ; 18 Basic Timer Counter 0 - DCD TC4_Handler ; 19 Basic Timer Counter 1 - DCD TC5_Handler ; 20 Basic Timer Counter 2 - DCD TC6_Handler ; 21 Basic Timer Counter 3 - DCD TC7_Handler ; 22 Basic Timer Counter 4 - DCD ADC_Handler ; 23 Analog Digital Converter - DCD AC_Handler ; 24 Analog Comparators - DCD DAC_Handler ; 25 Digital Analog Converter - DCD PTC_Handler ; 26 Peripheral Touch Controller - DCD I2S_Handler ; 27 Inter-IC Sound Interface -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT PM_Handler [WEAK] - EXPORT PM_Handler [WEAK] - EXPORT SYSCTRL_Handler [WEAK] - EXPORT WDT_Handler [WEAK] - EXPORT RTC_Handler [WEAK] - EXPORT EIC_Handler [WEAK] - EXPORT NVMCTRL_Handler [WEAK] - EXPORT DMAC_Handler [WEAK] - EXPORT USB_Handler [WEAK] - EXPORT EVSYS_Handler [WEAK] - EXPORT SERCOM0_Handler [WEAK] - EXPORT SERCOM1_Handler [WEAK] - EXPORT SERCOM2_Handler [WEAK] - EXPORT SERCOM3_Handler [WEAK] - EXPORT SERCOM4_Handler [WEAK] - EXPORT SERCOM5_Handler [WEAK] - EXPORT TCC0_Handler [WEAK] - EXPORT TCC1_Handler [WEAK] - EXPORT TCC2_Handler [WEAK] - EXPORT TC3_Handler [WEAK] - EXPORT TC4_Handler [WEAK] - EXPORT TC5_Handler [WEAK] - EXPORT TC6_Handler [WEAK] - EXPORT TC7_Handler [WEAK] - EXPORT ADC_Handler [WEAK] - EXPORT AC_Handler [WEAK] - EXPORT DAC_Handler [WEAK] - EXPORT PTC_Handler [WEAK] - EXPORT I2S_Handler [WEAK] - -PM_Handler -SYSCTRL_Handler -WDT_Handler -RTC_Handler -EIC_Handler -NVMCTRL_Handler -DMAC_Handler -USB_Handler -EVSYS_Handler -SERCOM0_Handler -SERCOM1_Handler -SERCOM2_Handler -SERCOM3_Handler -SERCOM4_Handler -SERCOM5_Handler -TCC0_Handler -TCC1_Handler -TCC2_Handler -TC3_Handler -TC4_Handler -TC5_Handler -TC6_Handler -TC7_Handler -ADC_Handler -AC_Handler -DAC_Handler -PTC_Handler -I2S_Handler - B . - ENDP - - - ALIGN - END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_ARM_MICRO/startup_SAML21.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,194 @@ +;/**************************************************************************//** +; * @file startup_SAML21.s +; * @brief CMSIS Cortex-M4 Core Device Startup File for +; * Atmel SAML21 Device Series +; * @version V1.00 +; * @date 10. February 2015 +; * +; * @note +; * Copyright (C) 2015 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ +__initial_sp EQU 0x20008000 ;Top of RAM + + PRESERVE8 + THUMB + + +;Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ;Top of Stack + DCD Reset_Handler ;Reset Handler + DCD NMI_Handler ;NMI Handler + DCD HardFault_Handler ;Hard Fault Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD SVC_Handler ;SVCall Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD PendSV_Handler ;PendSV Handler + DCD SysTick_Handler ;SysTick Handler + + ;External Interrupts + DCD SYSTEM_Handler ;0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator + DCD WDT_Handler ;1 Watchdog Timer + DCD RTC_Handler ;2 Real-Time Counter + DCD EIC_Handler ;3 External Interrupt Controller + DCD NVMCTRL_Handler ;4 Non-Volatile Memory Controller + DCD DMAC_Handler ;5 Direct Memory Access Controller + DCD USB_Handler ;6 Universal Serial Bus + DCD EVSYS_Handler ;7 Event System Interface + DCD SERCOM0_Handler ;8 Serial Communication Interface 0 + DCD SERCOM1_Handler ;9 Serial Communication Interface 1 + DCD SERCOM2_Handler ;10 Serial Communication Interface 2 + DCD SERCOM3_Handler ;11 Serial Communication Interface 3 + DCD SERCOM4_Handler ;12 Serial Communication Interface 4 + DCD SERCOM5_Handler ;13 Serial Communication Interface 5 + DCD TCC0_Handler ;14 Timer Counter Control 0 + DCD TCC1_Handler ;15 Timer Counter Control 1 + DCD TCC2_Handler ;16 Timer Counter Control 2 + DCD TC0_Handler ;17 Basic Timer Counter 0 + DCD TC1_Handler ;18 Basic Timer Counter 1 + DCD TC2_Handler ;19 Basic Timer Counter 2 + DCD TC3_Handler ;20 Basic Timer Counter 3 + DCD TC4_Handler ;21 Basic Timer Counter 4 + DCD ADC_Handler ;22 Analog Digital Converter + DCD AC_Handler ;23 Analog Comparators + DCD DAC_Handler ;24 Digital-to-Analog Converter + DCD PTC_Handler ;25 Peripheral Touch Controller + DCD AES_Handler ;26 Advanced Encryption Standard + DCD TRNG_Handler ;27 True Random Generator + DCD PICOP_Handler ;28 PicoProcessor +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +;Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +;Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT SYSTEM_Handler [WEAK] + EXPORT WDT_Handler [WEAK] + EXPORT RTC_Handler [WEAK] + EXPORT EIC_Handler [WEAK] + EXPORT NVMCTRL_Handler [WEAK] + EXPORT DMAC_Handler [WEAK] + EXPORT USB_Handler [WEAK] + EXPORT EVSYS_Handler [WEAK] + EXPORT SERCOM0_Handler [WEAK] + EXPORT SERCOM1_Handler [WEAK] + EXPORT SERCOM2_Handler [WEAK] + EXPORT SERCOM3_Handler [WEAK] + EXPORT SERCOM4_Handler [WEAK] + EXPORT SERCOM5_Handler [WEAK] + EXPORT TCC0_Handler [WEAK] + EXPORT TCC1_Handler [WEAK] + EXPORT TCC2_Handler [WEAK] + EXPORT TC0_Handler [WEAK] + EXPORT TC1_Handler [WEAK] + EXPORT TC2_Handler [WEAK] + EXPORT TC3_Handler [WEAK] + EXPORT TC4_Handler [WEAK] + EXPORT ADC_Handler [WEAK] + EXPORT AC_Handler [WEAK] + EXPORT DAC_Handler [WEAK] + EXPORT PTC_Handler [WEAK] + EXPORT AES_Handler [WEAK] + EXPORT TRNG_Handler [WEAK] + EXPORT PICOP_Handler [WEAK] + +SYSTEM_Handler +WDT_Handler +RTC_Handler +EIC_Handler +NVMCTRL_Handler +DMAC_Handler +USB_Handler +EVSYS_Handler +SERCOM0_Handler +SERCOM1_Handler +SERCOM2_Handler +SERCOM3_Handler +SERCOM4_Handler +SERCOM5_Handler +TCC0_Handler +TCC1_Handler +TCC2_Handler +TC0_Handler +TC1_Handler +TC2_Handler +TC3_Handler +TC4_Handler +ADC_Handler +AC_Handler +DAC_Handler +PTC_Handler +AES_Handler +TRNG_Handler +PICOP_Handler + B . + ENDP + + + + ALIGN + END
--- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_ARM_MICRO/startup_SAML21.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,194 +0,0 @@ -;/**************************************************************************//** -; * @file startup_SAML21.s -; * @brief CMSIS Cortex-M4 Core Device Startup File for -; * Atmel SAML21 Device Series -; * @version V1.00 -; * @date 10. February 2015 -; * -; * @note -; * Copyright (C) 2015 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ -__initial_sp EQU 0x20008000 ;Top of RAM - - PRESERVE8 - THUMB - - -;Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ;Top of Stack - DCD Reset_Handler ;Reset Handler - DCD NMI_Handler ;NMI Handler - DCD HardFault_Handler ;Hard Fault Handler - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD SVC_Handler ;SVCall Handler - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD PendSV_Handler ;PendSV Handler - DCD SysTick_Handler ;SysTick Handler - - ;External Interrupts - DCD SYSTEM_Handler ;0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator - DCD WDT_Handler ;1 Watchdog Timer - DCD RTC_Handler ;2 Real-Time Counter - DCD EIC_Handler ;3 External Interrupt Controller - DCD NVMCTRL_Handler ;4 Non-Volatile Memory Controller - DCD DMAC_Handler ;5 Direct Memory Access Controller - DCD USB_Handler ;6 Universal Serial Bus - DCD EVSYS_Handler ;7 Event System Interface - DCD SERCOM0_Handler ;8 Serial Communication Interface 0 - DCD SERCOM1_Handler ;9 Serial Communication Interface 1 - DCD SERCOM2_Handler ;10 Serial Communication Interface 2 - DCD SERCOM3_Handler ;11 Serial Communication Interface 3 - DCD SERCOM4_Handler ;12 Serial Communication Interface 4 - DCD SERCOM5_Handler ;13 Serial Communication Interface 5 - DCD TCC0_Handler ;14 Timer Counter Control 0 - DCD TCC1_Handler ;15 Timer Counter Control 1 - DCD TCC2_Handler ;16 Timer Counter Control 2 - DCD TC0_Handler ;17 Basic Timer Counter 0 - DCD TC1_Handler ;18 Basic Timer Counter 1 - DCD TC2_Handler ;19 Basic Timer Counter 2 - DCD TC3_Handler ;20 Basic Timer Counter 3 - DCD TC4_Handler ;21 Basic Timer Counter 4 - DCD ADC_Handler ;22 Analog Digital Converter - DCD AC_Handler ;23 Analog Comparators - DCD DAC_Handler ;24 Digital-to-Analog Converter - DCD PTC_Handler ;25 Peripheral Touch Controller - DCD AES_Handler ;26 Advanced Encryption Standard - DCD TRNG_Handler ;27 True Random Generator - DCD PICOP_Handler ;28 PicoProcessor -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -;Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -;Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT SYSTEM_Handler [WEAK] - EXPORT WDT_Handler [WEAK] - EXPORT RTC_Handler [WEAK] - EXPORT EIC_Handler [WEAK] - EXPORT NVMCTRL_Handler [WEAK] - EXPORT DMAC_Handler [WEAK] - EXPORT USB_Handler [WEAK] - EXPORT EVSYS_Handler [WEAK] - EXPORT SERCOM0_Handler [WEAK] - EXPORT SERCOM1_Handler [WEAK] - EXPORT SERCOM2_Handler [WEAK] - EXPORT SERCOM3_Handler [WEAK] - EXPORT SERCOM4_Handler [WEAK] - EXPORT SERCOM5_Handler [WEAK] - EXPORT TCC0_Handler [WEAK] - EXPORT TCC1_Handler [WEAK] - EXPORT TCC2_Handler [WEAK] - EXPORT TC0_Handler [WEAK] - EXPORT TC1_Handler [WEAK] - EXPORT TC2_Handler [WEAK] - EXPORT TC3_Handler [WEAK] - EXPORT TC4_Handler [WEAK] - EXPORT ADC_Handler [WEAK] - EXPORT AC_Handler [WEAK] - EXPORT DAC_Handler [WEAK] - EXPORT PTC_Handler [WEAK] - EXPORT AES_Handler [WEAK] - EXPORT TRNG_Handler [WEAK] - EXPORT PICOP_Handler [WEAK] - -SYSTEM_Handler -WDT_Handler -RTC_Handler -EIC_Handler -NVMCTRL_Handler -DMAC_Handler -USB_Handler -EVSYS_Handler -SERCOM0_Handler -SERCOM1_Handler -SERCOM2_Handler -SERCOM3_Handler -SERCOM4_Handler -SERCOM5_Handler -TCC0_Handler -TCC1_Handler -TCC2_Handler -TC0_Handler -TC1_Handler -TC2_Handler -TC3_Handler -TC4_Handler -ADC_Handler -AC_Handler -DAC_Handler -PTC_Handler -AES_Handler -TRNG_Handler -PICOP_Handler - B . - ENDP - - - - ALIGN - END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_ARM_STD/startup_SAML21.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,194 @@ +;/**************************************************************************//** +; * @file startup_SAML21.s +; * @brief CMSIS Cortex-M4 Core Device Startup File for +; * Atmel SAML21 Device Series +; * @version V1.00 +; * @date 10. February 2015 +; * +; * @note +; * Copyright (C) 2015 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ +__initial_sp EQU 0x20008000 ;Top of RAM + + PRESERVE8 + THUMB + + +;Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ;Top of Stack + DCD Reset_Handler ;Reset Handler + DCD NMI_Handler ;NMI Handler + DCD HardFault_Handler ;Hard Fault Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD SVC_Handler ;SVCall Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD PendSV_Handler ;PendSV Handler + DCD SysTick_Handler ;SysTick Handler + + ;External Interrupts + DCD SYSTEM_Handler ;0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator + DCD WDT_Handler ;1 Watchdog Timer + DCD RTC_Handler ;2 Real-Time Counter + DCD EIC_Handler ;3 External Interrupt Controller + DCD NVMCTRL_Handler ;4 Non-Volatile Memory Controller + DCD DMAC_Handler ;5 Direct Memory Access Controller + DCD USB_Handler ;6 Universal Serial Bus + DCD EVSYS_Handler ;7 Event System Interface + DCD SERCOM0_Handler ;8 Serial Communication Interface 0 + DCD SERCOM1_Handler ;9 Serial Communication Interface 1 + DCD SERCOM2_Handler ;10 Serial Communication Interface 2 + DCD SERCOM3_Handler ;11 Serial Communication Interface 3 + DCD SERCOM4_Handler ;12 Serial Communication Interface 4 + DCD SERCOM5_Handler ;13 Serial Communication Interface 5 + DCD TCC0_Handler ;14 Timer Counter Control 0 + DCD TCC1_Handler ;15 Timer Counter Control 1 + DCD TCC2_Handler ;16 Timer Counter Control 2 + DCD TC0_Handler ;17 Basic Timer Counter 0 + DCD TC1_Handler ;18 Basic Timer Counter 1 + DCD TC2_Handler ;19 Basic Timer Counter 2 + DCD TC3_Handler ;20 Basic Timer Counter 3 + DCD TC4_Handler ;21 Basic Timer Counter 4 + DCD ADC_Handler ;22 Analog Digital Converter + DCD AC_Handler ;23 Analog Comparators + DCD DAC_Handler ;24 Digital-to-Analog Converter + DCD PTC_Handler ;25 Peripheral Touch Controller + DCD AES_Handler ;26 Advanced Encryption Standard + DCD TRNG_Handler ;27 True Random Generator + DCD PICOP_Handler ;28 PicoProcessor +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +;Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +;Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT SYSTEM_Handler [WEAK] + EXPORT WDT_Handler [WEAK] + EXPORT RTC_Handler [WEAK] + EXPORT EIC_Handler [WEAK] + EXPORT NVMCTRL_Handler [WEAK] + EXPORT DMAC_Handler [WEAK] + EXPORT USB_Handler [WEAK] + EXPORT EVSYS_Handler [WEAK] + EXPORT SERCOM0_Handler [WEAK] + EXPORT SERCOM1_Handler [WEAK] + EXPORT SERCOM2_Handler [WEAK] + EXPORT SERCOM3_Handler [WEAK] + EXPORT SERCOM4_Handler [WEAK] + EXPORT SERCOM5_Handler [WEAK] + EXPORT TCC0_Handler [WEAK] + EXPORT TCC1_Handler [WEAK] + EXPORT TCC2_Handler [WEAK] + EXPORT TC0_Handler [WEAK] + EXPORT TC1_Handler [WEAK] + EXPORT TC2_Handler [WEAK] + EXPORT TC3_Handler [WEAK] + EXPORT TC4_Handler [WEAK] + EXPORT ADC_Handler [WEAK] + EXPORT AC_Handler [WEAK] + EXPORT DAC_Handler [WEAK] + EXPORT PTC_Handler [WEAK] + EXPORT AES_Handler [WEAK] + EXPORT TRNG_Handler [WEAK] + EXPORT PICOP_Handler [WEAK] + +SYSTEM_Handler +WDT_Handler +RTC_Handler +EIC_Handler +NVMCTRL_Handler +DMAC_Handler +USB_Handler +EVSYS_Handler +SERCOM0_Handler +SERCOM1_Handler +SERCOM2_Handler +SERCOM3_Handler +SERCOM4_Handler +SERCOM5_Handler +TCC0_Handler +TCC1_Handler +TCC2_Handler +TC0_Handler +TC1_Handler +TC2_Handler +TC3_Handler +TC4_Handler +ADC_Handler +AC_Handler +DAC_Handler +PTC_Handler +AES_Handler +TRNG_Handler +PICOP_Handler + B . + ENDP + + + + ALIGN + END
--- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAML21J18A/device/TOOLCHAIN_ARM_STD/startup_SAML21.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,194 +0,0 @@ -;/**************************************************************************//** -; * @file startup_SAML21.s -; * @brief CMSIS Cortex-M4 Core Device Startup File for -; * Atmel SAML21 Device Series -; * @version V1.00 -; * @date 10. February 2015 -; * -; * @note -; * Copyright (C) 2015 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ -__initial_sp EQU 0x20008000 ;Top of RAM - - PRESERVE8 - THUMB - - -;Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ;Top of Stack - DCD Reset_Handler ;Reset Handler - DCD NMI_Handler ;NMI Handler - DCD HardFault_Handler ;Hard Fault Handler - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD SVC_Handler ;SVCall Handler - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD PendSV_Handler ;PendSV Handler - DCD SysTick_Handler ;SysTick Handler - - ;External Interrupts - DCD SYSTEM_Handler ;0 Main Clock, Oscillators Control, 32k Oscillators Control, Peripheral Access Controller, Power Manager, Supply Controller, Trigger Allocator - DCD WDT_Handler ;1 Watchdog Timer - DCD RTC_Handler ;2 Real-Time Counter - DCD EIC_Handler ;3 External Interrupt Controller - DCD NVMCTRL_Handler ;4 Non-Volatile Memory Controller - DCD DMAC_Handler ;5 Direct Memory Access Controller - DCD USB_Handler ;6 Universal Serial Bus - DCD EVSYS_Handler ;7 Event System Interface - DCD SERCOM0_Handler ;8 Serial Communication Interface 0 - DCD SERCOM1_Handler ;9 Serial Communication Interface 1 - DCD SERCOM2_Handler ;10 Serial Communication Interface 2 - DCD SERCOM3_Handler ;11 Serial Communication Interface 3 - DCD SERCOM4_Handler ;12 Serial Communication Interface 4 - DCD SERCOM5_Handler ;13 Serial Communication Interface 5 - DCD TCC0_Handler ;14 Timer Counter Control 0 - DCD TCC1_Handler ;15 Timer Counter Control 1 - DCD TCC2_Handler ;16 Timer Counter Control 2 - DCD TC0_Handler ;17 Basic Timer Counter 0 - DCD TC1_Handler ;18 Basic Timer Counter 1 - DCD TC2_Handler ;19 Basic Timer Counter 2 - DCD TC3_Handler ;20 Basic Timer Counter 3 - DCD TC4_Handler ;21 Basic Timer Counter 4 - DCD ADC_Handler ;22 Analog Digital Converter - DCD AC_Handler ;23 Analog Comparators - DCD DAC_Handler ;24 Digital-to-Analog Converter - DCD PTC_Handler ;25 Peripheral Touch Controller - DCD AES_Handler ;26 Advanced Encryption Standard - DCD TRNG_Handler ;27 True Random Generator - DCD PICOP_Handler ;28 PicoProcessor -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -;Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -;Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT SYSTEM_Handler [WEAK] - EXPORT WDT_Handler [WEAK] - EXPORT RTC_Handler [WEAK] - EXPORT EIC_Handler [WEAK] - EXPORT NVMCTRL_Handler [WEAK] - EXPORT DMAC_Handler [WEAK] - EXPORT USB_Handler [WEAK] - EXPORT EVSYS_Handler [WEAK] - EXPORT SERCOM0_Handler [WEAK] - EXPORT SERCOM1_Handler [WEAK] - EXPORT SERCOM2_Handler [WEAK] - EXPORT SERCOM3_Handler [WEAK] - EXPORT SERCOM4_Handler [WEAK] - EXPORT SERCOM5_Handler [WEAK] - EXPORT TCC0_Handler [WEAK] - EXPORT TCC1_Handler [WEAK] - EXPORT TCC2_Handler [WEAK] - EXPORT TC0_Handler [WEAK] - EXPORT TC1_Handler [WEAK] - EXPORT TC2_Handler [WEAK] - EXPORT TC3_Handler [WEAK] - EXPORT TC4_Handler [WEAK] - EXPORT ADC_Handler [WEAK] - EXPORT AC_Handler [WEAK] - EXPORT DAC_Handler [WEAK] - EXPORT PTC_Handler [WEAK] - EXPORT AES_Handler [WEAK] - EXPORT TRNG_Handler [WEAK] - EXPORT PICOP_Handler [WEAK] - -SYSTEM_Handler -WDT_Handler -RTC_Handler -EIC_Handler -NVMCTRL_Handler -DMAC_Handler -USB_Handler -EVSYS_Handler -SERCOM0_Handler -SERCOM1_Handler -SERCOM2_Handler -SERCOM3_Handler -SERCOM4_Handler -SERCOM5_Handler -TCC0_Handler -TCC1_Handler -TCC2_Handler -TC0_Handler -TC1_Handler -TC2_Handler -TC3_Handler -TC4_Handler -ADC_Handler -AC_Handler -DAC_Handler -PTC_Handler -AES_Handler -TRNG_Handler -PICOP_Handler - B . - ENDP - - - - ALIGN - END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_ARM_MICRO/startup_SAMR21.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,189 @@ +;/***************************************************************************** +; * @file startup_SAMR21.s +; * @brief CMSIS Cortex-M0+ Core Device Startup File for +; * Atmel SAMR21 Device Series +; * @version V1.00 +; * @date 24. February 2014 +; * +; * @note +; * Copyright (C) 2014 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ +__initial_sp EQU 0x20008000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PM_Handler ; 0 Power Manager + DCD SYSCTRL_Handler ; 1 System Control + DCD WDT_Handler ; 2 Watchdog Timer + DCD RTC_Handler ; 3 Real-Time Counter + DCD EIC_Handler ; 4 External Interrupt Controller + DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller + DCD DMAC_Handler ; 6 Direct Memory Access Controller + DCD USB_Handler ; 7 Universal Serial Bus + DCD EVSYS_Handler ; 8 Event System Interface + DCD SERCOM0_Handler ; 9 Serial Communication Interface 0 + DCD SERCOM1_Handler ; 10 Serial Communication Interface 1 + DCD SERCOM2_Handler ; 11 Serial Communication Interface 2 + DCD SERCOM3_Handler ; 12 Serial Communication Interface 3 + DCD SERCOM4_Handler ; 13 Serial Communication Interface 4 + DCD SERCOM5_Handler ; 14 Serial Communication Interface 5 + DCD TCC0_Handler ; 15 Timer Counter Control 0 + DCD TCC1_Handler ; 16 Timer Counter Control 1 + DCD TCC2_Handler ; 17 Timer Counter Control 2 + DCD TC3_Handler ; 18 Basic Timer Counter 0 + DCD TC4_Handler ; 19 Basic Timer Counter 1 + DCD TC5_Handler ; 20 Basic Timer Counter 2 + DCD TC6_Handler ; 21 Basic Timer Counter 3 + DCD TC7_Handler ; 22 Basic Timer Counter 4 + DCD ADC_Handler ; 23 Analog Digital Converter + DCD AC_Handler ; 24 Analog Comparators + DCD DAC_Handler ; 25 Digital Analog Converter + DCD PTC_Handler ; 26 Peripheral Touch Controller + DCD I2S_Handler ; 27 Inter-IC Sound Interface +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT PM_Handler [WEAK] + EXPORT SYSCTRL_Handler [WEAK] + EXPORT WDT_Handler [WEAK] + EXPORT RTC_Handler [WEAK] + EXPORT EIC_Handler [WEAK] + EXPORT NVMCTRL_Handler [WEAK] + EXPORT DMAC_Handler [WEAK] + EXPORT USB_Handler [WEAK] + EXPORT EVSYS_Handler [WEAK] + EXPORT SERCOM0_Handler [WEAK] + EXPORT SERCOM1_Handler [WEAK] + EXPORT SERCOM2_Handler [WEAK] + EXPORT SERCOM3_Handler [WEAK] + EXPORT SERCOM4_Handler [WEAK] + EXPORT SERCOM5_Handler [WEAK] + EXPORT TCC0_Handler [WEAK] + EXPORT TCC1_Handler [WEAK] + EXPORT TCC2_Handler [WEAK] + EXPORT TC3_Handler [WEAK] + EXPORT TC4_Handler [WEAK] + EXPORT TC5_Handler [WEAK] + EXPORT TC6_Handler [WEAK] + EXPORT TC7_Handler [WEAK] + EXPORT ADC_Handler [WEAK] + EXPORT AC_Handler [WEAK] + EXPORT DAC_Handler [WEAK] + EXPORT PTC_Handler [WEAK] + EXPORT I2S_Handler [WEAK] + +PM_Handler +SYSCTRL_Handler +WDT_Handler +RTC_Handler +EIC_Handler +NVMCTRL_Handler +DMAC_Handler +USB_Handler +EVSYS_Handler +SERCOM0_Handler +SERCOM1_Handler +SERCOM2_Handler +SERCOM3_Handler +SERCOM4_Handler +SERCOM5_Handler +TCC0_Handler +TCC1_Handler +TCC2_Handler +TC3_Handler +TC4_Handler +TC5_Handler +TC6_Handler +TC7_Handler +ADC_Handler +AC_Handler +DAC_Handler +PTC_Handler +I2S_Handler + B . + ENDP + + + ALIGN + END
--- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_ARM_MICRO/startup_SAMR21.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,189 +0,0 @@ -;/***************************************************************************** -; * @file startup_SAMR21.s -; * @brief CMSIS Cortex-M0+ Core Device Startup File for -; * Atmel SAMR21 Device Series -; * @version V1.00 -; * @date 24. February 2014 -; * -; * @note -; * Copyright (C) 2014 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ -__initial_sp EQU 0x20008000 ; Top of RAM - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD PM_Handler ; 0 Power Manager - DCD SYSCTRL_Handler ; 1 System Control - DCD WDT_Handler ; 2 Watchdog Timer - DCD RTC_Handler ; 3 Real-Time Counter - DCD EIC_Handler ; 4 External Interrupt Controller - DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller - DCD DMAC_Handler ; 6 Direct Memory Access Controller - DCD USB_Handler ; 7 Universal Serial Bus - DCD EVSYS_Handler ; 8 Event System Interface - DCD SERCOM0_Handler ; 9 Serial Communication Interface 0 - DCD SERCOM1_Handler ; 10 Serial Communication Interface 1 - DCD SERCOM2_Handler ; 11 Serial Communication Interface 2 - DCD SERCOM3_Handler ; 12 Serial Communication Interface 3 - DCD SERCOM4_Handler ; 13 Serial Communication Interface 4 - DCD SERCOM5_Handler ; 14 Serial Communication Interface 5 - DCD TCC0_Handler ; 15 Timer Counter Control 0 - DCD TCC1_Handler ; 16 Timer Counter Control 1 - DCD TCC2_Handler ; 17 Timer Counter Control 2 - DCD TC3_Handler ; 18 Basic Timer Counter 0 - DCD TC4_Handler ; 19 Basic Timer Counter 1 - DCD TC5_Handler ; 20 Basic Timer Counter 2 - DCD TC6_Handler ; 21 Basic Timer Counter 3 - DCD TC7_Handler ; 22 Basic Timer Counter 4 - DCD ADC_Handler ; 23 Analog Digital Converter - DCD AC_Handler ; 24 Analog Comparators - DCD DAC_Handler ; 25 Digital Analog Converter - DCD PTC_Handler ; 26 Peripheral Touch Controller - DCD I2S_Handler ; 27 Inter-IC Sound Interface -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT PM_Handler [WEAK] - EXPORT SYSCTRL_Handler [WEAK] - EXPORT WDT_Handler [WEAK] - EXPORT RTC_Handler [WEAK] - EXPORT EIC_Handler [WEAK] - EXPORT NVMCTRL_Handler [WEAK] - EXPORT DMAC_Handler [WEAK] - EXPORT USB_Handler [WEAK] - EXPORT EVSYS_Handler [WEAK] - EXPORT SERCOM0_Handler [WEAK] - EXPORT SERCOM1_Handler [WEAK] - EXPORT SERCOM2_Handler [WEAK] - EXPORT SERCOM3_Handler [WEAK] - EXPORT SERCOM4_Handler [WEAK] - EXPORT SERCOM5_Handler [WEAK] - EXPORT TCC0_Handler [WEAK] - EXPORT TCC1_Handler [WEAK] - EXPORT TCC2_Handler [WEAK] - EXPORT TC3_Handler [WEAK] - EXPORT TC4_Handler [WEAK] - EXPORT TC5_Handler [WEAK] - EXPORT TC6_Handler [WEAK] - EXPORT TC7_Handler [WEAK] - EXPORT ADC_Handler [WEAK] - EXPORT AC_Handler [WEAK] - EXPORT DAC_Handler [WEAK] - EXPORT PTC_Handler [WEAK] - EXPORT I2S_Handler [WEAK] - -PM_Handler -SYSCTRL_Handler -WDT_Handler -RTC_Handler -EIC_Handler -NVMCTRL_Handler -DMAC_Handler -USB_Handler -EVSYS_Handler -SERCOM0_Handler -SERCOM1_Handler -SERCOM2_Handler -SERCOM3_Handler -SERCOM4_Handler -SERCOM5_Handler -TCC0_Handler -TCC1_Handler -TCC2_Handler -TC3_Handler -TC4_Handler -TC5_Handler -TC6_Handler -TC7_Handler -ADC_Handler -AC_Handler -DAC_Handler -PTC_Handler -I2S_Handler - B . - ENDP - - - ALIGN - END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_ARM_STD/startup_SAMR21.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,189 @@ +;/***************************************************************************** +; * @file startup_SAMR21.s +; * @brief CMSIS Cortex-M0+ Core Device Startup File for +; * Atmel SAMR21 Device Series +; * @version V1.00 +; * @date 24. February 2014 +; * +; * @note +; * Copyright (C) 2014 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ +__initial_sp EQU 0x20008000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD PM_Handler ; 0 Power Manager + DCD SYSCTRL_Handler ; 1 System Control + DCD WDT_Handler ; 2 Watchdog Timer + DCD RTC_Handler ; 3 Real-Time Counter + DCD EIC_Handler ; 4 External Interrupt Controller + DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller + DCD DMAC_Handler ; 6 Direct Memory Access Controller + DCD USB_Handler ; 7 Universal Serial Bus + DCD EVSYS_Handler ; 8 Event System Interface + DCD SERCOM0_Handler ; 9 Serial Communication Interface 0 + DCD SERCOM1_Handler ; 10 Serial Communication Interface 1 + DCD SERCOM2_Handler ; 11 Serial Communication Interface 2 + DCD SERCOM3_Handler ; 12 Serial Communication Interface 3 + DCD SERCOM4_Handler ; 13 Serial Communication Interface 4 + DCD SERCOM5_Handler ; 14 Serial Communication Interface 5 + DCD TCC0_Handler ; 15 Timer Counter Control 0 + DCD TCC1_Handler ; 16 Timer Counter Control 1 + DCD TCC2_Handler ; 17 Timer Counter Control 2 + DCD TC3_Handler ; 18 Basic Timer Counter 0 + DCD TC4_Handler ; 19 Basic Timer Counter 1 + DCD TC5_Handler ; 20 Basic Timer Counter 2 + DCD TC6_Handler ; 21 Basic Timer Counter 3 + DCD TC7_Handler ; 22 Basic Timer Counter 4 + DCD ADC_Handler ; 23 Analog Digital Converter + DCD AC_Handler ; 24 Analog Comparators + DCD DAC_Handler ; 25 Digital Analog Converter + DCD PTC_Handler ; 26 Peripheral Touch Controller + DCD I2S_Handler ; 27 Inter-IC Sound Interface +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT PM_Handler [WEAK] + EXPORT SYSCTRL_Handler [WEAK] + EXPORT WDT_Handler [WEAK] + EXPORT RTC_Handler [WEAK] + EXPORT EIC_Handler [WEAK] + EXPORT NVMCTRL_Handler [WEAK] + EXPORT DMAC_Handler [WEAK] + EXPORT USB_Handler [WEAK] + EXPORT EVSYS_Handler [WEAK] + EXPORT SERCOM0_Handler [WEAK] + EXPORT SERCOM1_Handler [WEAK] + EXPORT SERCOM2_Handler [WEAK] + EXPORT SERCOM3_Handler [WEAK] + EXPORT SERCOM4_Handler [WEAK] + EXPORT SERCOM5_Handler [WEAK] + EXPORT TCC0_Handler [WEAK] + EXPORT TCC1_Handler [WEAK] + EXPORT TCC2_Handler [WEAK] + EXPORT TC3_Handler [WEAK] + EXPORT TC4_Handler [WEAK] + EXPORT TC5_Handler [WEAK] + EXPORT TC6_Handler [WEAK] + EXPORT TC7_Handler [WEAK] + EXPORT ADC_Handler [WEAK] + EXPORT AC_Handler [WEAK] + EXPORT DAC_Handler [WEAK] + EXPORT PTC_Handler [WEAK] + EXPORT I2S_Handler [WEAK] + +PM_Handler +SYSCTRL_Handler +WDT_Handler +RTC_Handler +EIC_Handler +NVMCTRL_Handler +DMAC_Handler +USB_Handler +EVSYS_Handler +SERCOM0_Handler +SERCOM1_Handler +SERCOM2_Handler +SERCOM3_Handler +SERCOM4_Handler +SERCOM5_Handler +TCC0_Handler +TCC1_Handler +TCC2_Handler +TC3_Handler +TC4_Handler +TC5_Handler +TC6_Handler +TC7_Handler +ADC_Handler +AC_Handler +DAC_Handler +PTC_Handler +I2S_Handler + B . + ENDP + + + ALIGN + END
--- a/targets/TARGET_Atmel/TARGET_SAM_CortexM0P/TARGET_SAMR21G18A/device/TOOLCHAIN_ARM_STD/startup_SAMR21.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,189 +0,0 @@ -;/***************************************************************************** -; * @file startup_SAMR21.s -; * @brief CMSIS Cortex-M0+ Core Device Startup File for -; * Atmel SAMR21 Device Series -; * @version V1.00 -; * @date 24. February 2014 -; * -; * @note -; * Copyright (C) 2014 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ -__initial_sp EQU 0x20008000 ; Top of RAM - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD PM_Handler ; 0 Power Manager - DCD SYSCTRL_Handler ; 1 System Control - DCD WDT_Handler ; 2 Watchdog Timer - DCD RTC_Handler ; 3 Real-Time Counter - DCD EIC_Handler ; 4 External Interrupt Controller - DCD NVMCTRL_Handler ; 5 Non-Volatile Memory Controller - DCD DMAC_Handler ; 6 Direct Memory Access Controller - DCD USB_Handler ; 7 Universal Serial Bus - DCD EVSYS_Handler ; 8 Event System Interface - DCD SERCOM0_Handler ; 9 Serial Communication Interface 0 - DCD SERCOM1_Handler ; 10 Serial Communication Interface 1 - DCD SERCOM2_Handler ; 11 Serial Communication Interface 2 - DCD SERCOM3_Handler ; 12 Serial Communication Interface 3 - DCD SERCOM4_Handler ; 13 Serial Communication Interface 4 - DCD SERCOM5_Handler ; 14 Serial Communication Interface 5 - DCD TCC0_Handler ; 15 Timer Counter Control 0 - DCD TCC1_Handler ; 16 Timer Counter Control 1 - DCD TCC2_Handler ; 17 Timer Counter Control 2 - DCD TC3_Handler ; 18 Basic Timer Counter 0 - DCD TC4_Handler ; 19 Basic Timer Counter 1 - DCD TC5_Handler ; 20 Basic Timer Counter 2 - DCD TC6_Handler ; 21 Basic Timer Counter 3 - DCD TC7_Handler ; 22 Basic Timer Counter 4 - DCD ADC_Handler ; 23 Analog Digital Converter - DCD AC_Handler ; 24 Analog Comparators - DCD DAC_Handler ; 25 Digital Analog Converter - DCD PTC_Handler ; 26 Peripheral Touch Controller - DCD I2S_Handler ; 27 Inter-IC Sound Interface -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT PM_Handler [WEAK] - EXPORT SYSCTRL_Handler [WEAK] - EXPORT WDT_Handler [WEAK] - EXPORT RTC_Handler [WEAK] - EXPORT EIC_Handler [WEAK] - EXPORT NVMCTRL_Handler [WEAK] - EXPORT DMAC_Handler [WEAK] - EXPORT USB_Handler [WEAK] - EXPORT EVSYS_Handler [WEAK] - EXPORT SERCOM0_Handler [WEAK] - EXPORT SERCOM1_Handler [WEAK] - EXPORT SERCOM2_Handler [WEAK] - EXPORT SERCOM3_Handler [WEAK] - EXPORT SERCOM4_Handler [WEAK] - EXPORT SERCOM5_Handler [WEAK] - EXPORT TCC0_Handler [WEAK] - EXPORT TCC1_Handler [WEAK] - EXPORT TCC2_Handler [WEAK] - EXPORT TC3_Handler [WEAK] - EXPORT TC4_Handler [WEAK] - EXPORT TC5_Handler [WEAK] - EXPORT TC6_Handler [WEAK] - EXPORT TC7_Handler [WEAK] - EXPORT ADC_Handler [WEAK] - EXPORT AC_Handler [WEAK] - EXPORT DAC_Handler [WEAK] - EXPORT PTC_Handler [WEAK] - EXPORT I2S_Handler [WEAK] - -PM_Handler -SYSCTRL_Handler -WDT_Handler -RTC_Handler -EIC_Handler -NVMCTRL_Handler -DMAC_Handler -USB_Handler -EVSYS_Handler -SERCOM0_Handler -SERCOM1_Handler -SERCOM2_Handler -SERCOM3_Handler -SERCOM4_Handler -SERCOM5_Handler -TCC0_Handler -TCC1_Handler -TCC2_Handler -TC3_Handler -TC4_Handler -TC5_Handler -TC6_Handler -TC7_Handler -ADC_Handler -AC_Handler -DAC_Handler -PTC_Handler -I2S_Handler - B . - ENDP - - - ALIGN - END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/device/TOOLCHAIN_ARM_MICRO/startup_MKL26Z4.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,365 @@ +; * --------------------------------------------------------------------------------------- +; * @file: startup_MKL26Z4.s +; * @purpose: CMSIS Cortex-M0P Core Device Startup File +; * MKL26Z4 +; * @version: 1.7 +; * @date: 2015-2-18 +; * @build: b150218 +; * --------------------------------------------------------------------------------------- +; * +; * Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc. +; * All rights reserved. +; * +; * Redistribution and use in source and binary forms, with or without modification, +; * are permitted provided that the following conditions are met: +; * +; * o Redistributions of source code must retain the above copyright notice, this list +; * of conditions and the following disclaimer. +; * +; * o Redistributions in binary form must reproduce the above copyright notice, this +; * list of conditions and the following disclaimer in the documentation and/or +; * other materials provided with the distribution. +; * +; * o Neither the name of Freescale Semiconductor, Inc. nor the names of its +; * contributors may be used to endorse or promote products derived from this +; * software without specific prior written permission. +; * +; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; * +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; *****************************************************************************/ + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| + +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ;NMI Handler + DCD HardFault_Handler ;Hard Fault Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD SVC_Handler ;SVCall Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD PendSV_Handler ;PendSV Handler + DCD SysTick_Handler ;SysTick Handler + + ;External Interrupts + DCD DMA0_IRQHandler ;DMA channel 0 transfer complete and error interrupt + DCD DMA1_IRQHandler ;DMA channel 1 transfer complete and error interrupt + DCD DMA2_IRQHandler ;DMA channel 2 transfer complete and error interrupt + DCD DMA3_IRQHandler ;DMA channel 3 transfer complete and error interrupt + DCD Reserved20_IRQHandler ;Reserved interrupt + DCD FTFA_IRQHandler ;FTFA command complete and read collision + DCD LVD_LVW_IRQHandler ;Low-voltage detect, low-voltage warning + DCD LLWU_IRQHandler ;Low Leakage Wakeup + DCD I2C0_IRQHandler ;I2C0 interrupt + DCD I2C1_IRQHandler ;I2C1 interrupt + DCD SPI0_IRQHandler ;SPI0 single interrupt vector for all sources + DCD SPI1_IRQHandler ;SPI1 single interrupt vector for all sources + DCD UART0_IRQHandler ;UART0 status and error + DCD UART1_IRQHandler ;UART1 status and error + DCD UART2_IRQHandler ;UART2 status and error + DCD ADC0_IRQHandler ;ADC0 interrupt + DCD CMP0_IRQHandler ;CMP0 interrupt + DCD TPM0_IRQHandler ;TPM0 single interrupt vector for all sources + DCD TPM1_IRQHandler ;TPM1 single interrupt vector for all sources + DCD TPM2_IRQHandler ;TPM2 single interrupt vector for all sources + DCD RTC_IRQHandler ;RTC alarm interrupt + DCD RTC_Seconds_IRQHandler ;RTC seconds interrupt + DCD PIT_IRQHandler ;PIT single interrupt vector for all channels + DCD I2S0_IRQHandler ;I2S0 Single interrupt vector for all sources + DCD USB0_IRQHandler ;USB0 OTG + DCD DAC0_IRQHandler ;DAC0 interrupt + DCD TSI0_IRQHandler ;TSI0 interrupt + DCD MCG_IRQHandler ;MCG interrupt + DCD LPTMR0_IRQHandler ;LPTMR0 interrupt + DCD Reserved45_IRQHandler ;Reserved interrupt + DCD PORTA_IRQHandler ;PORTA pin detect + DCD PORTC_PORTD_IRQHandler ;Single interrupt vector for PORTC and PORTD pin detect +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + +; <h> Flash Configuration +; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset) +; <i> and security information that allows the MCU to restrict access to the FTFL module. +; <h> Backdoor Comparison Key +; <o0> Backdoor Comparison Key 0. <0x0-0xFF:2> +; <o1> Backdoor Comparison Key 1. <0x0-0xFF:2> +; <o2> Backdoor Comparison Key 2. <0x0-0xFF:2> +; <o3> Backdoor Comparison Key 3. <0x0-0xFF:2> +; <o4> Backdoor Comparison Key 4. <0x0-0xFF:2> +; <o5> Backdoor Comparison Key 5. <0x0-0xFF:2> +; <o6> Backdoor Comparison Key 6. <0x0-0xFF:2> +; <o7> Backdoor Comparison Key 7. <0x0-0xFF:2> +BackDoorK0 EQU 0xFF +BackDoorK1 EQU 0xFF +BackDoorK2 EQU 0xFF +BackDoorK3 EQU 0xFF +BackDoorK4 EQU 0xFF +BackDoorK5 EQU 0xFF +BackDoorK6 EQU 0xFF +BackDoorK7 EQU 0xFF +; </h> +; <h> Program flash protection bytes (FPROT) +; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit. +; <i> Each bit protects a 1/32 region of the program flash memory. +; <h> FPROT0 +; <i> Program Flash Region Protect Register 0 +; <i> 1/32 - 8/32 region +; <o.0> FPROT0.0 +; <o.1> FPROT0.1 +; <o.2> FPROT0.2 +; <o.3> FPROT0.3 +; <o.4> FPROT0.4 +; <o.5> FPROT0.5 +; <o.6> FPROT0.6 +; <o.7> FPROT0.7 +nFPROT0 EQU 0x00 +FPROT0 EQU nFPROT0:EOR:0xFF +; </h> +; <h> FPROT1 +; <i> Program Flash Region Protect Register 1 +; <i> 9/32 - 16/32 region +; <o.0> FPROT1.0 +; <o.1> FPROT1.1 +; <o.2> FPROT1.2 +; <o.3> FPROT1.3 +; <o.4> FPROT1.4 +; <o.5> FPROT1.5 +; <o.6> FPROT1.6 +; <o.7> FPROT1.7 +nFPROT1 EQU 0x00 +FPROT1 EQU nFPROT1:EOR:0xFF +; </h> +; <h> FPROT2 +; <i> Program Flash Region Protect Register 2 +; <i> 17/32 - 24/32 region +; <o.0> FPROT2.0 +; <o.1> FPROT2.1 +; <o.2> FPROT2.2 +; <o.3> FPROT2.3 +; <o.4> FPROT2.4 +; <o.5> FPROT2.5 +; <o.6> FPROT2.6 +; <o.7> FPROT2.7 +nFPROT2 EQU 0x00 +FPROT2 EQU nFPROT2:EOR:0xFF +; </h> +; <h> FPROT3 +; <i> Program Flash Region Protect Register 3 +; <i> 25/32 - 32/32 region +; <o.0> FPROT3.0 +; <o.1> FPROT3.1 +; <o.2> FPROT3.2 +; <o.3> FPROT3.3 +; <o.4> FPROT3.4 +; <o.5> FPROT3.5 +; <o.6> FPROT3.6 +; <o.7> FPROT3.7 +nFPROT3 EQU 0x00 +FPROT3 EQU nFPROT3:EOR:0xFF +; </h> +; </h> +; <h> Flash nonvolatile option byte (FOPT) +; <i> Allows the user to customize the operation of the MCU at boot time. +; <o.0> LPBOOT0 +; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT1=0 or 0x1 (divide by 2) when LPBOOT1=1. +; <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) when LPBOOT1=0 or 0x0 (divide by 1) when LPBOOT1=1. +; <o.2> NMI_DIS +; <0=> NMI interrupts are always blocked +; <1=> NMI_b pin/interrupts reset default to enabled +; <o.3> RESET_PIN_CFG +; <0=> RESET pin is disabled following a POR and cannot be enabled as reset function +; <1=> RESET_b pin is dedicated +; <o.4> LPBOOT1 +; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT0=0 or 0x3 (divide by 4) when LPBOOT0=1. +; <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) when LPBOOT0=0 or 0x0 (divide by 1) when LPBOOT0=1. +; <o.5> FAST_INIT +; <0=> Slower initialization +; <1=> Fast Initialization +FOPT EQU 0xFF +; </h> +; <h> Flash security byte (FSEC) +; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled", +; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!! +; <o.0..1> SEC +; <2=> MCU security status is unsecure +; <3=> MCU security status is secure +; <i> Flash Security +; <o.2..3> FSLACC +; <2=> Freescale factory access denied +; <3=> Freescale factory access granted +; <i> Freescale Failure Analysis Access Code +; <o.4..5> MEEN +; <2=> Mass erase is disabled +; <3=> Mass erase is enabled +; <o.6..7> KEYEN +; <2=> Backdoor key access enabled +; <3=> Backdoor key access disabled +; <i> Backdoor Key Security Enable +FSEC EQU 0xFE +; </h> +; </h> + IF :LNOT::DEF:RAM_TARGET + AREA FlashConfig, DATA, READONLY +__FlashConfig + DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3 + DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7 + DCB FPROT0 , FPROT1 , FPROT2 , FPROT3 + DCB FSEC , FOPT , 0xFF , 0xFF + ENDIF + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT init_data_bss + IMPORT __main + + IF :LNOT::DEF:RAM_TARGET + LDR R0, =FlashConfig ; dummy read, workaround for flashConfig + ENDIF + + CPSID I ; Mask interrupts + LDR R0, =SystemInit + BLX R0 + LDR R0, =init_data_bss + BLX R0 + CPSIE i ; Unmask interrupts + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler\ + PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler\ + PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler\ + PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler\ + PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP +Default_Handler\ + PROC + EXPORT DMA0_IRQHandler [WEAK] + EXPORT DMA1_IRQHandler [WEAK] + EXPORT DMA2_IRQHandler [WEAK] + EXPORT DMA3_IRQHandler [WEAK] + EXPORT Reserved20_IRQHandler [WEAK] + EXPORT FTFA_IRQHandler [WEAK] + EXPORT LVD_LVW_IRQHandler [WEAK] + EXPORT LLWU_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI0_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT UART0_IRQHandler [WEAK] + EXPORT UART1_IRQHandler [WEAK] + EXPORT UART2_IRQHandler [WEAK] + EXPORT ADC0_IRQHandler [WEAK] + EXPORT CMP0_IRQHandler [WEAK] + EXPORT TPM0_IRQHandler [WEAK] + EXPORT TPM1_IRQHandler [WEAK] + EXPORT TPM2_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT RTC_Seconds_IRQHandler [WEAK] + EXPORT PIT_IRQHandler [WEAK] + EXPORT I2S0_IRQHandler [WEAK] + EXPORT USB0_IRQHandler [WEAK] + EXPORT DAC0_IRQHandler [WEAK] + EXPORT TSI0_IRQHandler [WEAK] + EXPORT MCG_IRQHandler [WEAK] + EXPORT LPTMR0_IRQHandler [WEAK] + EXPORT Reserved45_IRQHandler [WEAK] + EXPORT PORTA_IRQHandler [WEAK] + EXPORT PORTC_PORTD_IRQHandler [WEAK] + EXPORT DefaultISR [WEAK] +DMA0_IRQHandler +DMA1_IRQHandler +DMA2_IRQHandler +DMA3_IRQHandler +Reserved20_IRQHandler +FTFA_IRQHandler +LVD_LVW_IRQHandler +LLWU_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +ADC0_IRQHandler +CMP0_IRQHandler +TPM0_IRQHandler +TPM1_IRQHandler +TPM2_IRQHandler +RTC_IRQHandler +RTC_Seconds_IRQHandler +PIT_IRQHandler +I2S0_IRQHandler +USB0_IRQHandler +DAC0_IRQHandler +TSI0_IRQHandler +MCG_IRQHandler +LPTMR0_IRQHandler +Reserved45_IRQHandler +PORTA_IRQHandler +PORTC_PORTD_IRQHandler +DefaultISR + LDR R0, =DefaultISR + BX R0 + ENDP + ALIGN + + + END
--- a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/device/TOOLCHAIN_ARM_MICRO/startup_MKL26Z4.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,365 +0,0 @@ -; * --------------------------------------------------------------------------------------- -; * @file: startup_MKL26Z4.s -; * @purpose: CMSIS Cortex-M0P Core Device Startup File -; * MKL26Z4 -; * @version: 1.7 -; * @date: 2015-2-18 -; * @build: b150218 -; * --------------------------------------------------------------------------------------- -; * -; * Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc. -; * All rights reserved. -; * -; * Redistribution and use in source and binary forms, with or without modification, -; * are permitted provided that the following conditions are met: -; * -; * o Redistributions of source code must retain the above copyright notice, this list -; * of conditions and the following disclaimer. -; * -; * o Redistributions in binary form must reproduce the above copyright notice, this -; * list of conditions and the following disclaimer in the documentation and/or -; * other materials provided with the distribution. -; * -; * o Neither the name of Freescale Semiconductor, Inc. nor the names of its -; * contributors may be used to endorse or promote products derived from this -; * software without specific prior written permission. -; * -; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; * -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; *****************************************************************************/ - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ;NMI Handler - DCD HardFault_Handler ;Hard Fault Handler - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD SVC_Handler ;SVCall Handler - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD PendSV_Handler ;PendSV Handler - DCD SysTick_Handler ;SysTick Handler - - ;External Interrupts - DCD DMA0_IRQHandler ;DMA channel 0 transfer complete and error interrupt - DCD DMA1_IRQHandler ;DMA channel 1 transfer complete and error interrupt - DCD DMA2_IRQHandler ;DMA channel 2 transfer complete and error interrupt - DCD DMA3_IRQHandler ;DMA channel 3 transfer complete and error interrupt - DCD Reserved20_IRQHandler ;Reserved interrupt - DCD FTFA_IRQHandler ;FTFA command complete and read collision - DCD LVD_LVW_IRQHandler ;Low-voltage detect, low-voltage warning - DCD LLWU_IRQHandler ;Low Leakage Wakeup - DCD I2C0_IRQHandler ;I2C0 interrupt - DCD I2C1_IRQHandler ;I2C1 interrupt - DCD SPI0_IRQHandler ;SPI0 single interrupt vector for all sources - DCD SPI1_IRQHandler ;SPI1 single interrupt vector for all sources - DCD UART0_IRQHandler ;UART0 status and error - DCD UART1_IRQHandler ;UART1 status and error - DCD UART2_IRQHandler ;UART2 status and error - DCD ADC0_IRQHandler ;ADC0 interrupt - DCD CMP0_IRQHandler ;CMP0 interrupt - DCD TPM0_IRQHandler ;TPM0 single interrupt vector for all sources - DCD TPM1_IRQHandler ;TPM1 single interrupt vector for all sources - DCD TPM2_IRQHandler ;TPM2 single interrupt vector for all sources - DCD RTC_IRQHandler ;RTC alarm interrupt - DCD RTC_Seconds_IRQHandler ;RTC seconds interrupt - DCD PIT_IRQHandler ;PIT single interrupt vector for all channels - DCD I2S0_IRQHandler ;I2S0 Single interrupt vector for all sources - DCD USB0_IRQHandler ;USB0 OTG - DCD DAC0_IRQHandler ;DAC0 interrupt - DCD TSI0_IRQHandler ;TSI0 interrupt - DCD MCG_IRQHandler ;MCG interrupt - DCD LPTMR0_IRQHandler ;LPTMR0 interrupt - DCD Reserved45_IRQHandler ;Reserved interrupt - DCD PORTA_IRQHandler ;PORTA pin detect - DCD PORTC_PORTD_IRQHandler ;Single interrupt vector for PORTC and PORTD pin detect -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - -; <h> Flash Configuration -; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset) -; <i> and security information that allows the MCU to restrict access to the FTFL module. -; <h> Backdoor Comparison Key -; <o0> Backdoor Comparison Key 0. <0x0-0xFF:2> -; <o1> Backdoor Comparison Key 1. <0x0-0xFF:2> -; <o2> Backdoor Comparison Key 2. <0x0-0xFF:2> -; <o3> Backdoor Comparison Key 3. <0x0-0xFF:2> -; <o4> Backdoor Comparison Key 4. <0x0-0xFF:2> -; <o5> Backdoor Comparison Key 5. <0x0-0xFF:2> -; <o6> Backdoor Comparison Key 6. <0x0-0xFF:2> -; <o7> Backdoor Comparison Key 7. <0x0-0xFF:2> -BackDoorK0 EQU 0xFF -BackDoorK1 EQU 0xFF -BackDoorK2 EQU 0xFF -BackDoorK3 EQU 0xFF -BackDoorK4 EQU 0xFF -BackDoorK5 EQU 0xFF -BackDoorK6 EQU 0xFF -BackDoorK7 EQU 0xFF -; </h> -; <h> Program flash protection bytes (FPROT) -; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit. -; <i> Each bit protects a 1/32 region of the program flash memory. -; <h> FPROT0 -; <i> Program Flash Region Protect Register 0 -; <i> 1/32 - 8/32 region -; <o.0> FPROT0.0 -; <o.1> FPROT0.1 -; <o.2> FPROT0.2 -; <o.3> FPROT0.3 -; <o.4> FPROT0.4 -; <o.5> FPROT0.5 -; <o.6> FPROT0.6 -; <o.7> FPROT0.7 -nFPROT0 EQU 0x00 -FPROT0 EQU nFPROT0:EOR:0xFF -; </h> -; <h> FPROT1 -; <i> Program Flash Region Protect Register 1 -; <i> 9/32 - 16/32 region -; <o.0> FPROT1.0 -; <o.1> FPROT1.1 -; <o.2> FPROT1.2 -; <o.3> FPROT1.3 -; <o.4> FPROT1.4 -; <o.5> FPROT1.5 -; <o.6> FPROT1.6 -; <o.7> FPROT1.7 -nFPROT1 EQU 0x00 -FPROT1 EQU nFPROT1:EOR:0xFF -; </h> -; <h> FPROT2 -; <i> Program Flash Region Protect Register 2 -; <i> 17/32 - 24/32 region -; <o.0> FPROT2.0 -; <o.1> FPROT2.1 -; <o.2> FPROT2.2 -; <o.3> FPROT2.3 -; <o.4> FPROT2.4 -; <o.5> FPROT2.5 -; <o.6> FPROT2.6 -; <o.7> FPROT2.7 -nFPROT2 EQU 0x00 -FPROT2 EQU nFPROT2:EOR:0xFF -; </h> -; <h> FPROT3 -; <i> Program Flash Region Protect Register 3 -; <i> 25/32 - 32/32 region -; <o.0> FPROT3.0 -; <o.1> FPROT3.1 -; <o.2> FPROT3.2 -; <o.3> FPROT3.3 -; <o.4> FPROT3.4 -; <o.5> FPROT3.5 -; <o.6> FPROT3.6 -; <o.7> FPROT3.7 -nFPROT3 EQU 0x00 -FPROT3 EQU nFPROT3:EOR:0xFF -; </h> -; </h> -; <h> Flash nonvolatile option byte (FOPT) -; <i> Allows the user to customize the operation of the MCU at boot time. -; <o.0> LPBOOT0 -; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT1=0 or 0x1 (divide by 2) when LPBOOT1=1. -; <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) when LPBOOT1=0 or 0x0 (divide by 1) when LPBOOT1=1. -; <o.2> NMI_DIS -; <0=> NMI interrupts are always blocked -; <1=> NMI_b pin/interrupts reset default to enabled -; <o.3> RESET_PIN_CFG -; <0=> RESET pin is disabled following a POR and cannot be enabled as reset function -; <1=> RESET_b pin is dedicated -; <o.4> LPBOOT1 -; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT0=0 or 0x3 (divide by 4) when LPBOOT0=1. -; <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) when LPBOOT0=0 or 0x0 (divide by 1) when LPBOOT0=1. -; <o.5> FAST_INIT -; <0=> Slower initialization -; <1=> Fast Initialization -FOPT EQU 0xFF -; </h> -; <h> Flash security byte (FSEC) -; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled", -; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!! -; <o.0..1> SEC -; <2=> MCU security status is unsecure -; <3=> MCU security status is secure -; <i> Flash Security -; <o.2..3> FSLACC -; <2=> Freescale factory access denied -; <3=> Freescale factory access granted -; <i> Freescale Failure Analysis Access Code -; <o.4..5> MEEN -; <2=> Mass erase is disabled -; <3=> Mass erase is enabled -; <o.6..7> KEYEN -; <2=> Backdoor key access enabled -; <3=> Backdoor key access disabled -; <i> Backdoor Key Security Enable -FSEC EQU 0xFE -; </h> -; </h> - IF :LNOT::DEF:RAM_TARGET - AREA FlashConfig, DATA, READONLY -__FlashConfig - DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3 - DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7 - DCB FPROT0 , FPROT1 , FPROT2 , FPROT3 - DCB FSEC , FOPT , 0xFF , 0xFF - ENDIF - - - AREA |.text|, CODE, READONLY - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT init_data_bss - IMPORT __main - - IF :LNOT::DEF:RAM_TARGET - LDR R0, =FlashConfig ; dummy read, workaround for flashConfig - ENDIF - - CPSID I ; Mask interrupts - LDR R0, =SystemInit - BLX R0 - LDR R0, =init_data_bss - BLX R0 - CPSIE i ; Unmask interrupts - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) -NMI_Handler\ - PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler\ - PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler\ - PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler\ - PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP -Default_Handler\ - PROC - EXPORT DMA0_IRQHandler [WEAK] - EXPORT DMA1_IRQHandler [WEAK] - EXPORT DMA2_IRQHandler [WEAK] - EXPORT DMA3_IRQHandler [WEAK] - EXPORT Reserved20_IRQHandler [WEAK] - EXPORT FTFA_IRQHandler [WEAK] - EXPORT LVD_LVW_IRQHandler [WEAK] - EXPORT LLWU_IRQHandler [WEAK] - EXPORT I2C0_IRQHandler [WEAK] - EXPORT I2C1_IRQHandler [WEAK] - EXPORT SPI0_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT UART0_IRQHandler [WEAK] - EXPORT UART1_IRQHandler [WEAK] - EXPORT UART2_IRQHandler [WEAK] - EXPORT ADC0_IRQHandler [WEAK] - EXPORT CMP0_IRQHandler [WEAK] - EXPORT TPM0_IRQHandler [WEAK] - EXPORT TPM1_IRQHandler [WEAK] - EXPORT TPM2_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT RTC_Seconds_IRQHandler [WEAK] - EXPORT PIT_IRQHandler [WEAK] - EXPORT I2S0_IRQHandler [WEAK] - EXPORT USB0_IRQHandler [WEAK] - EXPORT DAC0_IRQHandler [WEAK] - EXPORT TSI0_IRQHandler [WEAK] - EXPORT MCG_IRQHandler [WEAK] - EXPORT LPTMR0_IRQHandler [WEAK] - EXPORT Reserved45_IRQHandler [WEAK] - EXPORT PORTA_IRQHandler [WEAK] - EXPORT PORTC_PORTD_IRQHandler [WEAK] - EXPORT DefaultISR [WEAK] -DMA0_IRQHandler -DMA1_IRQHandler -DMA2_IRQHandler -DMA3_IRQHandler -Reserved20_IRQHandler -FTFA_IRQHandler -LVD_LVW_IRQHandler -LLWU_IRQHandler -I2C0_IRQHandler -I2C1_IRQHandler -SPI0_IRQHandler -SPI1_IRQHandler -UART0_IRQHandler -UART1_IRQHandler -UART2_IRQHandler -ADC0_IRQHandler -CMP0_IRQHandler -TPM0_IRQHandler -TPM1_IRQHandler -TPM2_IRQHandler -RTC_IRQHandler -RTC_Seconds_IRQHandler -PIT_IRQHandler -I2S0_IRQHandler -USB0_IRQHandler -DAC0_IRQHandler -TSI0_IRQHandler -MCG_IRQHandler -LPTMR0_IRQHandler -Reserved45_IRQHandler -PORTA_IRQHandler -PORTC_PORTD_IRQHandler -DefaultISR - LDR R0, =DefaultISR - BX R0 - ENDP - ALIGN - - - END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/device/TOOLCHAIN_IAR/startup_MKL26Z4.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,251 @@ +; --------------------------------------------------------------------------------------- +; @file: startup_MKL26Z4.s +; @purpose: CMSIS Cortex-M0P Core Device Startup File +; MKL26Z4 +; @version: 1.7 +; @date: 2015-2-18 +; @build: b150218 +; --------------------------------------------------------------------------------------- +; +; Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc. +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without modification, +; are permitted provided that the following conditions are met: +; +; o Redistributions of source code must retain the above copyright notice, this list +; of conditions and the following disclaimer. +; +; o Redistributions in binary form must reproduce the above copyright notice, this +; list of conditions and the following disclaimer in the documentation and/or +; other materials provided with the distribution. +; +; o Neither the name of Freescale Semiconductor, Inc. nor the names of its +; contributors may be used to endorse or promote products derived from this +; software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + EXTERN init_data_bss + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler ;NMI Handler + DCD HardFault_Handler ;Hard Fault Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved +__vector_table_0x1c + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD SVC_Handler ;SVCall Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD PendSV_Handler ;PendSV Handler + DCD SysTick_Handler ;SysTick Handler + + ;External Interrupts + DCD DMA0_IRQHandler ;DMA channel 0 transfer complete and error interrupt + DCD DMA1_IRQHandler ;DMA channel 1 transfer complete and error interrupt + DCD DMA2_IRQHandler ;DMA channel 2 transfer complete and error interrupt + DCD DMA3_IRQHandler ;DMA channel 3 transfer complete and error interrupt + DCD Reserved20_IRQHandler ;Reserved interrupt + DCD FTFA_IRQHandler ;FTFA command complete and read collision + DCD LVD_LVW_IRQHandler ;Low-voltage detect, low-voltage warning + DCD LLWU_IRQHandler ;Low Leakage Wakeup + DCD I2C0_IRQHandler ;I2C0 interrupt + DCD I2C1_IRQHandler ;I2C1 interrupt + DCD SPI0_IRQHandler ;SPI0 single interrupt vector for all sources + DCD SPI1_IRQHandler ;SPI1 single interrupt vector for all sources + DCD UART0_IRQHandler ;UART0 status and error + DCD UART1_IRQHandler ;UART1 status and error + DCD UART2_IRQHandler ;UART2 status and error + DCD ADC0_IRQHandler ;ADC0 interrupt + DCD CMP0_IRQHandler ;CMP0 interrupt + DCD TPM0_IRQHandler ;TPM0 single interrupt vector for all sources + DCD TPM1_IRQHandler ;TPM1 single interrupt vector for all sources + DCD TPM2_IRQHandler ;TPM2 single interrupt vector for all sources + DCD RTC_IRQHandler ;RTC alarm interrupt + DCD RTC_Seconds_IRQHandler ;RTC seconds interrupt + DCD PIT_IRQHandler ;PIT single interrupt vector for all channels + DCD I2S0_IRQHandler ;I2S0 Single interrupt vector for all sources + DCD USB0_IRQHandler ;USB0 OTG + DCD DAC0_IRQHandler ;DAC0 interrupt + DCD TSI0_IRQHandler ;TSI0 interrupt + DCD MCG_IRQHandler ;MCG interrupt + DCD LPTMR0_IRQHandler ;LPTMR0 interrupt + DCD Reserved45_IRQHandler ;Reserved interrupt + DCD PORTA_IRQHandler ;PORTA pin detect + DCD PORTC_PORTD_IRQHandler ;Single interrupt vector for PORTC and PORTD pin detect +__Vectors_End + + SECTION FlashConfig:CODE +__FlashConfig + DCD 0xFFFFFFFF + DCD 0xFFFFFFFF + DCD 0xFFFFFFFF + DCD 0xFFFFFFFE +__FlashConfig_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + CPSID I ; Mask interrupts + LDR R0, =SystemInit + BLX R0 + LDR R0, =init_data_bss + BLX R0 + CPSIE I ; Unmask interrupts + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + PUBWEAK DMA0_IRQHandler + PUBWEAK DMA1_IRQHandler + PUBWEAK DMA2_IRQHandler + PUBWEAK DMA3_IRQHandler + PUBWEAK Reserved20_IRQHandler + PUBWEAK FTFA_IRQHandler + PUBWEAK LVD_LVW_IRQHandler + PUBWEAK LLWU_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK I2C1_IRQHandler + PUBWEAK SPI0_IRQHandler + PUBWEAK SPI1_IRQHandler + PUBWEAK UART0_IRQHandler + PUBWEAK UART1_IRQHandler + PUBWEAK UART2_IRQHandler + PUBWEAK ADC0_IRQHandler + PUBWEAK CMP0_IRQHandler + PUBWEAK TPM0_IRQHandler + PUBWEAK TPM1_IRQHandler + PUBWEAK TPM2_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK RTC_Seconds_IRQHandler + PUBWEAK PIT_IRQHandler + PUBWEAK I2S0_IRQHandler + PUBWEAK USB0_IRQHandler + PUBWEAK DAC0_IRQHandler + PUBWEAK TSI0_IRQHandler + PUBWEAK MCG_IRQHandler + PUBWEAK LPTMR0_IRQHandler + PUBWEAK Reserved45_IRQHandler + PUBWEAK PORTA_IRQHandler + PUBWEAK PORTC_PORTD_IRQHandler + PUBWEAK DefaultISR + SECTION .text:CODE:REORDER:NOROOT(2) +DMA0_IRQHandler +DMA1_IRQHandler +DMA2_IRQHandler +DMA3_IRQHandler +Reserved20_IRQHandler +FTFA_IRQHandler +LVD_LVW_IRQHandler +LLWU_IRQHandler +I2C0_IRQHandler +I2C1_IRQHandler +SPI0_IRQHandler +SPI1_IRQHandler +UART0_IRQHandler +UART1_IRQHandler +UART2_IRQHandler +ADC0_IRQHandler +CMP0_IRQHandler +TPM0_IRQHandler +TPM1_IRQHandler +TPM2_IRQHandler +RTC_IRQHandler +RTC_Seconds_IRQHandler +PIT_IRQHandler +I2S0_IRQHandler +USB0_IRQHandler +DAC0_IRQHandler +TSI0_IRQHandler +MCG_IRQHandler +LPTMR0_IRQHandler +Reserved45_IRQHandler +PORTA_IRQHandler +PORTC_PORTD_IRQHandler +DefaultISR + LDR R0, =DefaultISR + BX R0 + + END
--- a/targets/TARGET_Freescale/TARGET_KLXX/TARGET_KL26Z/device/TOOLCHAIN_IAR/startup_MKL26Z4.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,251 +0,0 @@ -; --------------------------------------------------------------------------------------- -; @file: startup_MKL26Z4.s -; @purpose: CMSIS Cortex-M0P Core Device Startup File -; MKL26Z4 -; @version: 1.7 -; @date: 2015-2-18 -; @build: b150218 -; --------------------------------------------------------------------------------------- -; -; Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc. -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without modification, -; are permitted provided that the following conditions are met: -; -; o Redistributions of source code must retain the above copyright notice, this list -; of conditions and the following disclaimer. -; -; o Redistributions in binary form must reproduce the above copyright notice, this -; list of conditions and the following disclaimer in the documentation and/or -; other materials provided with the distribution. -; -; o Neither the name of Freescale Semiconductor, Inc. nor the names of its -; contributors may be used to endorse or promote products derived from this -; software without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - EXTERN init_data_bss - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler ;NMI Handler - DCD HardFault_Handler ;Hard Fault Handler - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved -__vector_table_0x1c - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD SVC_Handler ;SVCall Handler - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD PendSV_Handler ;PendSV Handler - DCD SysTick_Handler ;SysTick Handler - - ;External Interrupts - DCD DMA0_IRQHandler ;DMA channel 0 transfer complete and error interrupt - DCD DMA1_IRQHandler ;DMA channel 1 transfer complete and error interrupt - DCD DMA2_IRQHandler ;DMA channel 2 transfer complete and error interrupt - DCD DMA3_IRQHandler ;DMA channel 3 transfer complete and error interrupt - DCD Reserved20_IRQHandler ;Reserved interrupt - DCD FTFA_IRQHandler ;FTFA command complete and read collision - DCD LVD_LVW_IRQHandler ;Low-voltage detect, low-voltage warning - DCD LLWU_IRQHandler ;Low Leakage Wakeup - DCD I2C0_IRQHandler ;I2C0 interrupt - DCD I2C1_IRQHandler ;I2C1 interrupt - DCD SPI0_IRQHandler ;SPI0 single interrupt vector for all sources - DCD SPI1_IRQHandler ;SPI1 single interrupt vector for all sources - DCD UART0_IRQHandler ;UART0 status and error - DCD UART1_IRQHandler ;UART1 status and error - DCD UART2_IRQHandler ;UART2 status and error - DCD ADC0_IRQHandler ;ADC0 interrupt - DCD CMP0_IRQHandler ;CMP0 interrupt - DCD TPM0_IRQHandler ;TPM0 single interrupt vector for all sources - DCD TPM1_IRQHandler ;TPM1 single interrupt vector for all sources - DCD TPM2_IRQHandler ;TPM2 single interrupt vector for all sources - DCD RTC_IRQHandler ;RTC alarm interrupt - DCD RTC_Seconds_IRQHandler ;RTC seconds interrupt - DCD PIT_IRQHandler ;PIT single interrupt vector for all channels - DCD I2S0_IRQHandler ;I2S0 Single interrupt vector for all sources - DCD USB0_IRQHandler ;USB0 OTG - DCD DAC0_IRQHandler ;DAC0 interrupt - DCD TSI0_IRQHandler ;TSI0 interrupt - DCD MCG_IRQHandler ;MCG interrupt - DCD LPTMR0_IRQHandler ;LPTMR0 interrupt - DCD Reserved45_IRQHandler ;Reserved interrupt - DCD PORTA_IRQHandler ;PORTA pin detect - DCD PORTC_PORTD_IRQHandler ;Single interrupt vector for PORTC and PORTD pin detect -__Vectors_End - - SECTION FlashConfig:CODE -__FlashConfig - DCD 0xFFFFFFFF - DCD 0xFFFFFFFF - DCD 0xFFFFFFFF - DCD 0xFFFFFFFE -__FlashConfig_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - CPSID I ; Mask interrupts - LDR R0, =SystemInit - BLX R0 - LDR R0, =init_data_bss - BLX R0 - CPSIE I ; Unmask interrupts - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B . - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B . - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B . - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B . - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B . - - PUBWEAK DMA0_IRQHandler - PUBWEAK DMA1_IRQHandler - PUBWEAK DMA2_IRQHandler - PUBWEAK DMA3_IRQHandler - PUBWEAK Reserved20_IRQHandler - PUBWEAK FTFA_IRQHandler - PUBWEAK LVD_LVW_IRQHandler - PUBWEAK LLWU_IRQHandler - PUBWEAK I2C0_IRQHandler - PUBWEAK I2C1_IRQHandler - PUBWEAK SPI0_IRQHandler - PUBWEAK SPI1_IRQHandler - PUBWEAK UART0_IRQHandler - PUBWEAK UART1_IRQHandler - PUBWEAK UART2_IRQHandler - PUBWEAK ADC0_IRQHandler - PUBWEAK CMP0_IRQHandler - PUBWEAK TPM0_IRQHandler - PUBWEAK TPM1_IRQHandler - PUBWEAK TPM2_IRQHandler - PUBWEAK RTC_IRQHandler - PUBWEAK RTC_Seconds_IRQHandler - PUBWEAK PIT_IRQHandler - PUBWEAK I2S0_IRQHandler - PUBWEAK USB0_IRQHandler - PUBWEAK DAC0_IRQHandler - PUBWEAK TSI0_IRQHandler - PUBWEAK MCG_IRQHandler - PUBWEAK LPTMR0_IRQHandler - PUBWEAK Reserved45_IRQHandler - PUBWEAK PORTA_IRQHandler - PUBWEAK PORTC_PORTD_IRQHandler - PUBWEAK DefaultISR - SECTION .text:CODE:REORDER:NOROOT(2) -DMA0_IRQHandler -DMA1_IRQHandler -DMA2_IRQHandler -DMA3_IRQHandler -Reserved20_IRQHandler -FTFA_IRQHandler -LVD_LVW_IRQHandler -LLWU_IRQHandler -I2C0_IRQHandler -I2C1_IRQHandler -SPI0_IRQHandler -SPI1_IRQHandler -UART0_IRQHandler -UART1_IRQHandler -UART2_IRQHandler -ADC0_IRQHandler -CMP0_IRQHandler -TPM0_IRQHandler -TPM1_IRQHandler -TPM2_IRQHandler -RTC_IRQHandler -RTC_Seconds_IRQHandler -PIT_IRQHandler -I2S0_IRQHandler -USB0_IRQHandler -DAC0_IRQHandler -TSI0_IRQHandler -MCG_IRQHandler -LPTMR0_IRQHandler -Reserved45_IRQHandler -PORTA_IRQHandler -PORTC_PORTD_IRQHandler -DefaultISR - LDR R0, =DefaultISR - BX R0 - - END
--- a/targets/TARGET_Freescale/TARGET_KLXX/us_ticker.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_Freescale/TARGET_KLXX/us_ticker.c Tue Mar 20 16:56:18 2018 +0000
@@ -199,6 +199,9 @@
void us_ticker_fire_interrupt(void)
{
+ us_ticker_int_counter = 0;
+ us_ticker_int_remainder = 0;
+
#if defined(TARGET_KL43Z)
NVIC_SetPendingIRQ(LPTMR0_IRQn);
#else
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/us_ticker.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K66F/us_ticker.c Tue Mar 20 16:56:18 2018 +0000
@@ -83,10 +83,14 @@
void us_ticker_set_interrupt(timestamp_t timestamp)
{
- uint32_t delta = timestamp - us_ticker_read();
+ uint32_t now_us, delta_us;
+
+ now_us = us_ticker_read();
+ delta_us = timestamp >= now_us ? timestamp - now_us : (uint32_t)((uint64_t)timestamp + 0xFFFFFFFF - now_us);
+
PIT_StopTimer(PIT, kPIT_Chnl_3);
PIT_StopTimer(PIT, kPIT_Chnl_2);
- PIT_SetTimerPeriod(PIT, kPIT_Chnl_3, (uint32_t)delta);
+ PIT_SetTimerPeriod(PIT, kPIT_Chnl_3, (uint32_t)delta_us);
PIT_EnableInterrupts(PIT, kPIT_Chnl_3, kPIT_TimerInterruptEnable);
PIT_StartTimer(PIT, kPIT_Chnl_3);
PIT_StartTimer(PIT, kPIT_Chnl_2);
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/us_ticker.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_K82F/us_ticker.c Tue Mar 20 16:56:18 2018 +0000
@@ -83,10 +83,14 @@
void us_ticker_set_interrupt(timestamp_t timestamp)
{
- uint32_t delta = timestamp - us_ticker_read();
+ uint32_t now_us, delta_us;
+
+ now_us = us_ticker_read();
+ delta_us = timestamp >= now_us ? timestamp - now_us : (uint32_t)((uint64_t)timestamp + 0xFFFFFFFF - now_us);
+
PIT_StopTimer(PIT, kPIT_Chnl_3);
PIT_StopTimer(PIT, kPIT_Chnl_2);
- PIT_SetTimerPeriod(PIT, kPIT_Chnl_3, (uint32_t)delta);
+ PIT_SetTimerPeriod(PIT, kPIT_Chnl_3, (uint32_t)delta_us);
PIT_EnableInterrupts(PIT, kPIT_Chnl_3, kPIT_TimerInterruptEnable);
PIT_StartTimer(PIT, kPIT_Chnl_3);
PIT_StartTimer(PIT, kPIT_Chnl_2);
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL27Z/us_ticker.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL27Z/us_ticker.c Tue Mar 20 16:56:18 2018 +0000
@@ -90,9 +90,13 @@
void us_ticker_set_interrupt(timestamp_t timestamp)
{
- uint32_t delta = timestamp - us_ticker_read();
+ uint32_t now_us, delta_us;
+
+ now_us = us_ticker_read();
+ delta_us = timestamp >= now_us ? timestamp - now_us : (uint32_t)((uint64_t)timestamp + 0xFFFFFFFF - now_us);
+
LPTMR_StopTimer(LPTMR0);
- LPTMR_SetTimerPeriod(LPTMR0, (uint32_t)delta);
+ LPTMR_SetTimerPeriod(LPTMR0, (uint32_t)delta_us);
LPTMR_EnableInterrupts(LPTMR0, kLPTMR_TimerInterruptEnable);
LPTMR_StartTimer(LPTMR0);
}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/device/TOOLCHAIN_ARM_STD/startup_MKL43Z4.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,456 @@ +; * --------------------------------------------------------------------------------------- +; * @file: startup_MKL43Z4.s +; * @purpose: CMSIS Cortex-M0P Core Device Startup File +; * MKL43Z4 +; * @version: 1.8 +; * @date: 2016-6-24 +; * @build: b160627 +; * --------------------------------------------------------------------------------------- +; * +; * Copyright (c) 1997 - 2016 , Freescale Semiconductor, Inc. +; * All rights reserved. +; * +; * Redistribution and use in source and binary forms, with or without modification, +; * are permitted provided that the following conditions are met: +; * +; * o Redistributions of source code must retain the above copyright notice, this list +; * of conditions and the following disclaimer. +; * +; * o Redistributions in binary form must reproduce the above copyright notice, this +; * list of conditions and the following disclaimer in the documentation and/or +; * other materials provided with the distribution. +; * +; * o Neither the name of Freescale Semiconductor, Inc. nor the names of its +; * contributors may be used to endorse or promote products derived from this +; * software without specific prior written permission. +; * +; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; * +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; *****************************************************************************/ + +__initial_sp EQU 0x20006000 ; Top of RAM + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ;NMI Handler + DCD HardFault_Handler ;Hard Fault Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD SVC_Handler ;SVCall Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD PendSV_Handler ;PendSV Handler + DCD SysTick_Handler ;SysTick Handler + + ;External Interrupts + DCD DMA0_IRQHandler ;DMA channel 0 transfer complete + DCD DMA1_IRQHandler ;DMA channel 1 transfer complete + DCD DMA2_IRQHandler ;DMA channel 2 transfer complete + DCD DMA3_IRQHandler ;DMA channel 3 transfer complete + DCD Reserved20_IRQHandler ;Reserved interrupt + DCD FTFA_IRQHandler ;Command complete and read collision + DCD PMC_IRQHandler ;Low-voltage detect, low-voltage warning + DCD LLWU_IRQHandler ;Low leakage wakeup + DCD I2C0_IRQHandler ;I2C0 interrupt + DCD I2C1_IRQHandler ;I2C1 interrupt + DCD SPI0_IRQHandler ;SPI0 single interrupt vector for all sources + DCD SPI1_IRQHandler ;SPI1 single interrupt vector for all sources + DCD LPUART0_IRQHandler ;LPUART0 status and error + DCD LPUART1_IRQHandler ;LPUART1 status and error + DCD UART2_FLEXIO_IRQHandler ;UART2 or FLEXIO + DCD ADC0_IRQHandler ;ADC0 interrupt + DCD CMP0_IRQHandler ;CMP0 interrupt + DCD TPM0_IRQHandler ;TPM0 single interrupt vector for all sources + DCD TPM1_IRQHandler ;TPM1 single interrupt vector for all sources + DCD TPM2_IRQHandler ;TPM2 single interrupt vector for all sources + DCD RTC_IRQHandler ;RTC alarm + DCD RTC_Seconds_IRQHandler ;RTC seconds + DCD PIT_IRQHandler ;PIT interrupt + DCD I2S0_IRQHandler ;I2S0 interrupt + DCD USB0_IRQHandler ;USB0 interrupt + DCD DAC0_IRQHandler ;DAC0 interrupt + DCD Reserved42_IRQHandler ;Reserved interrupt + DCD Reserved43_IRQHandler ;Reserved interrupt + DCD LPTMR0_IRQHandler ;LPTMR0 interrupt + DCD LCD_IRQHandler ;LCD interrupt + DCD PORTA_IRQHandler ;PORTA Pin detect + DCD PORTC_PORTD_IRQHandler ;Single interrupt vector for PORTC; PORTD Pin detect +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + +; <h> Flash Configuration +; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset) +; <i> and security information that allows the MCU to restrict access to the FTFL module. +; <h> Backdoor Comparison Key +; <o0> Backdoor Comparison Key 0. <0x0-0xFF:2> +; <o1> Backdoor Comparison Key 1. <0x0-0xFF:2> +; <o2> Backdoor Comparison Key 2. <0x0-0xFF:2> +; <o3> Backdoor Comparison Key 3. <0x0-0xFF:2> +; <o4> Backdoor Comparison Key 4. <0x0-0xFF:2> +; <o5> Backdoor Comparison Key 5. <0x0-0xFF:2> +; <o6> Backdoor Comparison Key 6. <0x0-0xFF:2> +; <o7> Backdoor Comparison Key 7. <0x0-0xFF:2> +BackDoorK0 EQU 0xFF +BackDoorK1 EQU 0xFF +BackDoorK2 EQU 0xFF +BackDoorK3 EQU 0xFF +BackDoorK4 EQU 0xFF +BackDoorK5 EQU 0xFF +BackDoorK6 EQU 0xFF +BackDoorK7 EQU 0xFF +; </h> +; <h> Program flash protection bytes (FPROT) +; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit. +; <i> Each bit protects a 1/32 region of the program flash memory. +; <h> FPROT0 +; <i> Program Flash Region Protect Register 0 +; <i> 1/32 - 8/32 region +; <o.0> FPROT0.0 +; <o.1> FPROT0.1 +; <o.2> FPROT0.2 +; <o.3> FPROT0.3 +; <o.4> FPROT0.4 +; <o.5> FPROT0.5 +; <o.6> FPROT0.6 +; <o.7> FPROT0.7 +nFPROT0 EQU 0x00 +FPROT0 EQU nFPROT0:EOR:0xFF +; </h> +; <h> FPROT1 +; <i> Program Flash Region Protect Register 1 +; <i> 9/32 - 16/32 region +; <o.0> FPROT1.0 +; <o.1> FPROT1.1 +; <o.2> FPROT1.2 +; <o.3> FPROT1.3 +; <o.4> FPROT1.4 +; <o.5> FPROT1.5 +; <o.6> FPROT1.6 +; <o.7> FPROT1.7 +nFPROT1 EQU 0x00 +FPROT1 EQU nFPROT1:EOR:0xFF +; </h> +; <h> FPROT2 +; <i> Program Flash Region Protect Register 2 +; <i> 17/32 - 24/32 region +; <o.0> FPROT2.0 +; <o.1> FPROT2.1 +; <o.2> FPROT2.2 +; <o.3> FPROT2.3 +; <o.4> FPROT2.4 +; <o.5> FPROT2.5 +; <o.6> FPROT2.6 +; <o.7> FPROT2.7 +nFPROT2 EQU 0x00 +FPROT2 EQU nFPROT2:EOR:0xFF +; </h> +; <h> FPROT3 +; <i> Program Flash Region Protect Register 3 +; <i> 25/32 - 32/32 region +; <o.0> FPROT3.0 +; <o.1> FPROT3.1 +; <o.2> FPROT3.2 +; <o.3> FPROT3.3 +; <o.4> FPROT3.4 +; <o.5> FPROT3.5 +; <o.6> FPROT3.6 +; <o.7> FPROT3.7 +nFPROT3 EQU 0x00 +FPROT3 EQU nFPROT3:EOR:0xFF +; </h> +; </h> +; <h> Flash nonvolatile option byte (FOPT) +; <i> Allows the user to customize the operation of the MCU at boot time. +; <o.0> LPBOOT0 +; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT1=0 or 0x1 (divide by 2) when LPBOOT1=1. +; <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) when LPBOOT1=0 or 0x0 (divide by 1) when LPBOOT1=1. +; <o.1> BOOTPIN_OPT +; <0=> Force Boot from ROM if BOOTCFG0 asserted, where BOOTCFG0 is the boot config function which is muxed with NMI pin +; <1=> Boot source configured by FOPT (BOOTSRC_SEL) bits +; <o.2> NMI_DIS +; <0=> NMI interrupts are always blocked +; <1=> NMI_b pin/interrupts reset default to enabled +; <o.3> RESET_PIN_CFG +; <0=> RESET pin is disabled following a POR and cannot be enabled as reset function +; <1=> RESET_b pin is dedicated +; <o.4> LPBOOT1 +; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT0=0 or 0x3 (divide by 4) when LPBOOT0=1. +; <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) when LPBOOT0=0 or 0x0 (divide by 1) when LPBOOT0=1. +; <o.5> FAST_INIT +; <0=> Slower initialization +; <1=> Fast Initialization +; <o.6..7> BOOTSRC_SEL +; <0=> Boot from Flash +; <2=> Boot from ROM +; <3=> Boot from ROM +; <i> Boot source selection +FOPT EQU 0x3F +; </h> +; <h> Flash security byte (FSEC) +; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled", +; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!! +; <o.0..1> SEC +; <2=> MCU security status is unsecure +; <3=> MCU security status is secure +; <i> Flash Security +; <o.2..3> FSLACC +; <2=> Freescale factory access denied +; <3=> Freescale factory access granted +; <i> Freescale Failure Analysis Access Code +; <o.4..5> MEEN +; <2=> Mass erase is disabled +; <3=> Mass erase is enabled +; <o.6..7> KEYEN +; <2=> Backdoor key access enabled +; <3=> Backdoor key access disabled +; <i> Backdoor Key Security Enable +FSEC EQU 0xFE +; </h> +; </h> + IF :LNOT::DEF:RAM_TARGET + AREA FlashConfig, DATA, READONLY +__FlashConfig + DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3 + DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7 + DCB FPROT0 , FPROT1 , FPROT2 , FPROT3 + DCB FSEC , FOPT , 0xFF , 0xFF + ENDIF + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + IF :LNOT::DEF:RAM_TARGET + REQUIRE FlashConfig + ENDIF + + CPSID I ; Mask interrupts + LDR R0, =0xE000ED08 + LDR R1, =__Vectors + STR R1, [R0] + LDR R0, =SystemInit + BLX R0 + CPSIE i ; Unmask interrupts + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler\ + PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler\ + PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler\ + PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler\ + PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP +DMA0_IRQHandler\ + PROC + EXPORT DMA0_IRQHandler [WEAK] + LDR R0, =DMA0_DriverIRQHandler + BX R0 + ENDP + +DMA1_IRQHandler\ + PROC + EXPORT DMA1_IRQHandler [WEAK] + LDR R0, =DMA1_DriverIRQHandler + BX R0 + ENDP + +DMA2_IRQHandler\ + PROC + EXPORT DMA2_IRQHandler [WEAK] + LDR R0, =DMA2_DriverIRQHandler + BX R0 + ENDP + +DMA3_IRQHandler\ + PROC + EXPORT DMA3_IRQHandler [WEAK] + LDR R0, =DMA3_DriverIRQHandler + BX R0 + ENDP + +I2C0_IRQHandler\ + PROC + EXPORT I2C0_IRQHandler [WEAK] + LDR R0, =I2C0_DriverIRQHandler + BX R0 + ENDP + +I2C1_IRQHandler\ + PROC + EXPORT I2C1_IRQHandler [WEAK] + LDR R0, =I2C1_DriverIRQHandler + BX R0 + ENDP + +SPI0_IRQHandler\ + PROC + EXPORT SPI0_IRQHandler [WEAK] + LDR R0, =SPI0_DriverIRQHandler + BX R0 + ENDP + +SPI1_IRQHandler\ + PROC + EXPORT SPI1_IRQHandler [WEAK] + LDR R0, =SPI1_DriverIRQHandler + BX R0 + ENDP + +LPUART0_IRQHandler\ + PROC + EXPORT LPUART0_IRQHandler [WEAK] + LDR R0, =LPUART0_DriverIRQHandler + BX R0 + ENDP + +LPUART1_IRQHandler\ + PROC + EXPORT LPUART1_IRQHandler [WEAK] + LDR R0, =LPUART1_DriverIRQHandler + BX R0 + ENDP + +UART2_FLEXIO_IRQHandler\ + PROC + EXPORT UART2_FLEXIO_IRQHandler [WEAK] + LDR R0, =UART2_FLEXIO_DriverIRQHandler + BX R0 + ENDP + +I2S0_IRQHandler\ + PROC + EXPORT I2S0_IRQHandler [WEAK] + LDR R0, =I2S0_DriverIRQHandler + BX R0 + ENDP + +Default_Handler\ + PROC + EXPORT DMA0_DriverIRQHandler [WEAK] + EXPORT DMA1_DriverIRQHandler [WEAK] + EXPORT DMA2_DriverIRQHandler [WEAK] + EXPORT DMA3_DriverIRQHandler [WEAK] + EXPORT Reserved20_IRQHandler [WEAK] + EXPORT FTFA_IRQHandler [WEAK] + EXPORT PMC_IRQHandler [WEAK] + EXPORT LLWU_IRQHandler [WEAK] + EXPORT I2C0_DriverIRQHandler [WEAK] + EXPORT I2C1_DriverIRQHandler [WEAK] + EXPORT SPI0_DriverIRQHandler [WEAK] + EXPORT SPI1_DriverIRQHandler [WEAK] + EXPORT LPUART0_DriverIRQHandler [WEAK] + EXPORT LPUART1_DriverIRQHandler [WEAK] + EXPORT UART2_FLEXIO_DriverIRQHandler [WEAK] + EXPORT ADC0_IRQHandler [WEAK] + EXPORT CMP0_IRQHandler [WEAK] + EXPORT TPM0_IRQHandler [WEAK] + EXPORT TPM1_IRQHandler [WEAK] + EXPORT TPM2_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT RTC_Seconds_IRQHandler [WEAK] + EXPORT PIT_IRQHandler [WEAK] + EXPORT I2S0_DriverIRQHandler [WEAK] + EXPORT USB0_IRQHandler [WEAK] + EXPORT DAC0_IRQHandler [WEAK] + EXPORT Reserved42_IRQHandler [WEAK] + EXPORT Reserved43_IRQHandler [WEAK] + EXPORT LPTMR0_IRQHandler [WEAK] + EXPORT LCD_IRQHandler [WEAK] + EXPORT PORTA_IRQHandler [WEAK] + EXPORT PORTC_PORTD_IRQHandler [WEAK] + EXPORT DefaultISR [WEAK] +DMA0_DriverIRQHandler +DMA1_DriverIRQHandler +DMA2_DriverIRQHandler +DMA3_DriverIRQHandler +Reserved20_IRQHandler +FTFA_IRQHandler +PMC_IRQHandler +LLWU_IRQHandler +I2C0_DriverIRQHandler +I2C1_DriverIRQHandler +SPI0_DriverIRQHandler +SPI1_DriverIRQHandler +LPUART0_DriverIRQHandler +LPUART1_DriverIRQHandler +UART2_FLEXIO_DriverIRQHandler +ADC0_IRQHandler +CMP0_IRQHandler +TPM0_IRQHandler +TPM1_IRQHandler +TPM2_IRQHandler +RTC_IRQHandler +RTC_Seconds_IRQHandler +PIT_IRQHandler +I2S0_DriverIRQHandler +USB0_IRQHandler +DAC0_IRQHandler +Reserved42_IRQHandler +Reserved43_IRQHandler +LPTMR0_IRQHandler +LCD_IRQHandler +PORTA_IRQHandler +PORTC_PORTD_IRQHandler +DefaultISR + LDR R0, =DefaultISR + BX R0 + ENDP + ALIGN + + + END
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/device/TOOLCHAIN_ARM_STD/startup_MKL43Z4.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,456 +0,0 @@ -; * --------------------------------------------------------------------------------------- -; * @file: startup_MKL43Z4.s -; * @purpose: CMSIS Cortex-M0P Core Device Startup File -; * MKL43Z4 -; * @version: 1.8 -; * @date: 2016-6-24 -; * @build: b160627 -; * --------------------------------------------------------------------------------------- -; * -; * Copyright (c) 1997 - 2016 , Freescale Semiconductor, Inc. -; * All rights reserved. -; * -; * Redistribution and use in source and binary forms, with or without modification, -; * are permitted provided that the following conditions are met: -; * -; * o Redistributions of source code must retain the above copyright notice, this list -; * of conditions and the following disclaimer. -; * -; * o Redistributions in binary form must reproduce the above copyright notice, this -; * list of conditions and the following disclaimer in the documentation and/or -; * other materials provided with the distribution. -; * -; * o Neither the name of Freescale Semiconductor, Inc. nor the names of its -; * contributors may be used to endorse or promote products derived from this -; * software without specific prior written permission. -; * -; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; * -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; *****************************************************************************/ - -__initial_sp EQU 0x20006000 ; Top of RAM - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ;NMI Handler - DCD HardFault_Handler ;Hard Fault Handler - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD SVC_Handler ;SVCall Handler - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD PendSV_Handler ;PendSV Handler - DCD SysTick_Handler ;SysTick Handler - - ;External Interrupts - DCD DMA0_IRQHandler ;DMA channel 0 transfer complete - DCD DMA1_IRQHandler ;DMA channel 1 transfer complete - DCD DMA2_IRQHandler ;DMA channel 2 transfer complete - DCD DMA3_IRQHandler ;DMA channel 3 transfer complete - DCD Reserved20_IRQHandler ;Reserved interrupt - DCD FTFA_IRQHandler ;Command complete and read collision - DCD PMC_IRQHandler ;Low-voltage detect, low-voltage warning - DCD LLWU_IRQHandler ;Low leakage wakeup - DCD I2C0_IRQHandler ;I2C0 interrupt - DCD I2C1_IRQHandler ;I2C1 interrupt - DCD SPI0_IRQHandler ;SPI0 single interrupt vector for all sources - DCD SPI1_IRQHandler ;SPI1 single interrupt vector for all sources - DCD LPUART0_IRQHandler ;LPUART0 status and error - DCD LPUART1_IRQHandler ;LPUART1 status and error - DCD UART2_FLEXIO_IRQHandler ;UART2 or FLEXIO - DCD ADC0_IRQHandler ;ADC0 interrupt - DCD CMP0_IRQHandler ;CMP0 interrupt - DCD TPM0_IRQHandler ;TPM0 single interrupt vector for all sources - DCD TPM1_IRQHandler ;TPM1 single interrupt vector for all sources - DCD TPM2_IRQHandler ;TPM2 single interrupt vector for all sources - DCD RTC_IRQHandler ;RTC alarm - DCD RTC_Seconds_IRQHandler ;RTC seconds - DCD PIT_IRQHandler ;PIT interrupt - DCD I2S0_IRQHandler ;I2S0 interrupt - DCD USB0_IRQHandler ;USB0 interrupt - DCD DAC0_IRQHandler ;DAC0 interrupt - DCD Reserved42_IRQHandler ;Reserved interrupt - DCD Reserved43_IRQHandler ;Reserved interrupt - DCD LPTMR0_IRQHandler ;LPTMR0 interrupt - DCD LCD_IRQHandler ;LCD interrupt - DCD PORTA_IRQHandler ;PORTA Pin detect - DCD PORTC_PORTD_IRQHandler ;Single interrupt vector for PORTC; PORTD Pin detect -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - -; <h> Flash Configuration -; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset) -; <i> and security information that allows the MCU to restrict access to the FTFL module. -; <h> Backdoor Comparison Key -; <o0> Backdoor Comparison Key 0. <0x0-0xFF:2> -; <o1> Backdoor Comparison Key 1. <0x0-0xFF:2> -; <o2> Backdoor Comparison Key 2. <0x0-0xFF:2> -; <o3> Backdoor Comparison Key 3. <0x0-0xFF:2> -; <o4> Backdoor Comparison Key 4. <0x0-0xFF:2> -; <o5> Backdoor Comparison Key 5. <0x0-0xFF:2> -; <o6> Backdoor Comparison Key 6. <0x0-0xFF:2> -; <o7> Backdoor Comparison Key 7. <0x0-0xFF:2> -BackDoorK0 EQU 0xFF -BackDoorK1 EQU 0xFF -BackDoorK2 EQU 0xFF -BackDoorK3 EQU 0xFF -BackDoorK4 EQU 0xFF -BackDoorK5 EQU 0xFF -BackDoorK6 EQU 0xFF -BackDoorK7 EQU 0xFF -; </h> -; <h> Program flash protection bytes (FPROT) -; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit. -; <i> Each bit protects a 1/32 region of the program flash memory. -; <h> FPROT0 -; <i> Program Flash Region Protect Register 0 -; <i> 1/32 - 8/32 region -; <o.0> FPROT0.0 -; <o.1> FPROT0.1 -; <o.2> FPROT0.2 -; <o.3> FPROT0.3 -; <o.4> FPROT0.4 -; <o.5> FPROT0.5 -; <o.6> FPROT0.6 -; <o.7> FPROT0.7 -nFPROT0 EQU 0x00 -FPROT0 EQU nFPROT0:EOR:0xFF -; </h> -; <h> FPROT1 -; <i> Program Flash Region Protect Register 1 -; <i> 9/32 - 16/32 region -; <o.0> FPROT1.0 -; <o.1> FPROT1.1 -; <o.2> FPROT1.2 -; <o.3> FPROT1.3 -; <o.4> FPROT1.4 -; <o.5> FPROT1.5 -; <o.6> FPROT1.6 -; <o.7> FPROT1.7 -nFPROT1 EQU 0x00 -FPROT1 EQU nFPROT1:EOR:0xFF -; </h> -; <h> FPROT2 -; <i> Program Flash Region Protect Register 2 -; <i> 17/32 - 24/32 region -; <o.0> FPROT2.0 -; <o.1> FPROT2.1 -; <o.2> FPROT2.2 -; <o.3> FPROT2.3 -; <o.4> FPROT2.4 -; <o.5> FPROT2.5 -; <o.6> FPROT2.6 -; <o.7> FPROT2.7 -nFPROT2 EQU 0x00 -FPROT2 EQU nFPROT2:EOR:0xFF -; </h> -; <h> FPROT3 -; <i> Program Flash Region Protect Register 3 -; <i> 25/32 - 32/32 region -; <o.0> FPROT3.0 -; <o.1> FPROT3.1 -; <o.2> FPROT3.2 -; <o.3> FPROT3.3 -; <o.4> FPROT3.4 -; <o.5> FPROT3.5 -; <o.6> FPROT3.6 -; <o.7> FPROT3.7 -nFPROT3 EQU 0x00 -FPROT3 EQU nFPROT3:EOR:0xFF -; </h> -; </h> -; <h> Flash nonvolatile option byte (FOPT) -; <i> Allows the user to customize the operation of the MCU at boot time. -; <o.0> LPBOOT0 -; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT1=0 or 0x1 (divide by 2) when LPBOOT1=1. -; <1=> Core and system clock divider (OUTDIV1) is 0x3 (divide by 4) when LPBOOT1=0 or 0x0 (divide by 1) when LPBOOT1=1. -; <o.1> BOOTPIN_OPT -; <0=> Force Boot from ROM if BOOTCFG0 asserted, where BOOTCFG0 is the boot config function which is muxed with NMI pin -; <1=> Boot source configured by FOPT (BOOTSRC_SEL) bits -; <o.2> NMI_DIS -; <0=> NMI interrupts are always blocked -; <1=> NMI_b pin/interrupts reset default to enabled -; <o.3> RESET_PIN_CFG -; <0=> RESET pin is disabled following a POR and cannot be enabled as reset function -; <1=> RESET_b pin is dedicated -; <o.4> LPBOOT1 -; <0=> Core and system clock divider (OUTDIV1) is 0x7 (divide by 8) when LPBOOT0=0 or 0x3 (divide by 4) when LPBOOT0=1. -; <1=> Core and system clock divider (OUTDIV1) is 0x1 (divide by 2) when LPBOOT0=0 or 0x0 (divide by 1) when LPBOOT0=1. -; <o.5> FAST_INIT -; <0=> Slower initialization -; <1=> Fast Initialization -; <o.6..7> BOOTSRC_SEL -; <0=> Boot from Flash -; <2=> Boot from ROM -; <3=> Boot from ROM -; <i> Boot source selection -FOPT EQU 0x3F -; </h> -; <h> Flash security byte (FSEC) -; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled", -; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!! -; <o.0..1> SEC -; <2=> MCU security status is unsecure -; <3=> MCU security status is secure -; <i> Flash Security -; <o.2..3> FSLACC -; <2=> Freescale factory access denied -; <3=> Freescale factory access granted -; <i> Freescale Failure Analysis Access Code -; <o.4..5> MEEN -; <2=> Mass erase is disabled -; <3=> Mass erase is enabled -; <o.6..7> KEYEN -; <2=> Backdoor key access enabled -; <3=> Backdoor key access disabled -; <i> Backdoor Key Security Enable -FSEC EQU 0xFE -; </h> -; </h> - IF :LNOT::DEF:RAM_TARGET - AREA FlashConfig, DATA, READONLY -__FlashConfig - DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3 - DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7 - DCB FPROT0 , FPROT1 , FPROT2 , FPROT3 - DCB FSEC , FOPT , 0xFF , 0xFF - ENDIF - - - AREA |.text|, CODE, READONLY - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - IF :LNOT::DEF:RAM_TARGET - REQUIRE FlashConfig - ENDIF - - CPSID I ; Mask interrupts - LDR R0, =0xE000ED08 - LDR R1, =__Vectors - STR R1, [R0] - LDR R0, =SystemInit - BLX R0 - CPSIE i ; Unmask interrupts - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) -NMI_Handler\ - PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler\ - PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler\ - PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler\ - PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP -DMA0_IRQHandler\ - PROC - EXPORT DMA0_IRQHandler [WEAK] - LDR R0, =DMA0_DriverIRQHandler - BX R0 - ENDP - -DMA1_IRQHandler\ - PROC - EXPORT DMA1_IRQHandler [WEAK] - LDR R0, =DMA1_DriverIRQHandler - BX R0 - ENDP - -DMA2_IRQHandler\ - PROC - EXPORT DMA2_IRQHandler [WEAK] - LDR R0, =DMA2_DriverIRQHandler - BX R0 - ENDP - -DMA3_IRQHandler\ - PROC - EXPORT DMA3_IRQHandler [WEAK] - LDR R0, =DMA3_DriverIRQHandler - BX R0 - ENDP - -I2C0_IRQHandler\ - PROC - EXPORT I2C0_IRQHandler [WEAK] - LDR R0, =I2C0_DriverIRQHandler - BX R0 - ENDP - -I2C1_IRQHandler\ - PROC - EXPORT I2C1_IRQHandler [WEAK] - LDR R0, =I2C1_DriverIRQHandler - BX R0 - ENDP - -SPI0_IRQHandler\ - PROC - EXPORT SPI0_IRQHandler [WEAK] - LDR R0, =SPI0_DriverIRQHandler - BX R0 - ENDP - -SPI1_IRQHandler\ - PROC - EXPORT SPI1_IRQHandler [WEAK] - LDR R0, =SPI1_DriverIRQHandler - BX R0 - ENDP - -LPUART0_IRQHandler\ - PROC - EXPORT LPUART0_IRQHandler [WEAK] - LDR R0, =LPUART0_DriverIRQHandler - BX R0 - ENDP - -LPUART1_IRQHandler\ - PROC - EXPORT LPUART1_IRQHandler [WEAK] - LDR R0, =LPUART1_DriverIRQHandler - BX R0 - ENDP - -UART2_FLEXIO_IRQHandler\ - PROC - EXPORT UART2_FLEXIO_IRQHandler [WEAK] - LDR R0, =UART2_FLEXIO_DriverIRQHandler - BX R0 - ENDP - -I2S0_IRQHandler\ - PROC - EXPORT I2S0_IRQHandler [WEAK] - LDR R0, =I2S0_DriverIRQHandler - BX R0 - ENDP - -Default_Handler\ - PROC - EXPORT DMA0_DriverIRQHandler [WEAK] - EXPORT DMA1_DriverIRQHandler [WEAK] - EXPORT DMA2_DriverIRQHandler [WEAK] - EXPORT DMA3_DriverIRQHandler [WEAK] - EXPORT Reserved20_IRQHandler [WEAK] - EXPORT FTFA_IRQHandler [WEAK] - EXPORT PMC_IRQHandler [WEAK] - EXPORT LLWU_IRQHandler [WEAK] - EXPORT I2C0_DriverIRQHandler [WEAK] - EXPORT I2C1_DriverIRQHandler [WEAK] - EXPORT SPI0_DriverIRQHandler [WEAK] - EXPORT SPI1_DriverIRQHandler [WEAK] - EXPORT LPUART0_DriverIRQHandler [WEAK] - EXPORT LPUART1_DriverIRQHandler [WEAK] - EXPORT UART2_FLEXIO_DriverIRQHandler [WEAK] - EXPORT ADC0_IRQHandler [WEAK] - EXPORT CMP0_IRQHandler [WEAK] - EXPORT TPM0_IRQHandler [WEAK] - EXPORT TPM1_IRQHandler [WEAK] - EXPORT TPM2_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT RTC_Seconds_IRQHandler [WEAK] - EXPORT PIT_IRQHandler [WEAK] - EXPORT I2S0_DriverIRQHandler [WEAK] - EXPORT USB0_IRQHandler [WEAK] - EXPORT DAC0_IRQHandler [WEAK] - EXPORT Reserved42_IRQHandler [WEAK] - EXPORT Reserved43_IRQHandler [WEAK] - EXPORT LPTMR0_IRQHandler [WEAK] - EXPORT LCD_IRQHandler [WEAK] - EXPORT PORTA_IRQHandler [WEAK] - EXPORT PORTC_PORTD_IRQHandler [WEAK] - EXPORT DefaultISR [WEAK] -DMA0_DriverIRQHandler -DMA1_DriverIRQHandler -DMA2_DriverIRQHandler -DMA3_DriverIRQHandler -Reserved20_IRQHandler -FTFA_IRQHandler -PMC_IRQHandler -LLWU_IRQHandler -I2C0_DriverIRQHandler -I2C1_DriverIRQHandler -SPI0_DriverIRQHandler -SPI1_DriverIRQHandler -LPUART0_DriverIRQHandler -LPUART1_DriverIRQHandler -UART2_FLEXIO_DriverIRQHandler -ADC0_IRQHandler -CMP0_IRQHandler -TPM0_IRQHandler -TPM1_IRQHandler -TPM2_IRQHandler -RTC_IRQHandler -RTC_Seconds_IRQHandler -PIT_IRQHandler -I2S0_DriverIRQHandler -USB0_IRQHandler -DAC0_IRQHandler -Reserved42_IRQHandler -Reserved43_IRQHandler -LPTMR0_IRQHandler -LCD_IRQHandler -PORTA_IRQHandler -PORTC_PORTD_IRQHandler -DefaultISR - LDR R0, =DefaultISR - BX R0 - ENDP - ALIGN - - - END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/device/TOOLCHAIN_IAR/startup_MKL43Z4.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,323 @@ +; --------------------------------------------------------------------------------------- +; @file: startup_MKL43Z4.s +; @purpose: CMSIS Cortex-M0P Core Device Startup File +; MKL43Z4 +; @version: 1.8 +; @date: 2016-6-24 +; @build: b160627 +; --------------------------------------------------------------------------------------- +; +; Copyright (c) 1997 - 2016 , Freescale Semiconductor, Inc. +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without modification, +; are permitted provided that the following conditions are met: +; +; o Redistributions of source code must retain the above copyright notice, this list +; of conditions and the following disclaimer. +; +; o Redistributions in binary form must reproduce the above copyright notice, this +; list of conditions and the following disclaimer in the documentation and/or +; other materials provided with the distribution. +; +; o Neither the name of Freescale Semiconductor, Inc. nor the names of its +; contributors may be used to endorse or promote products derived from this +; software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler ;NMI Handler + DCD HardFault_Handler ;Hard Fault Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved +__vector_table_0x1c + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD SVC_Handler ;SVCall Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD PendSV_Handler ;PendSV Handler + DCD SysTick_Handler ;SysTick Handler + + ;External Interrupts + DCD DMA0_IRQHandler ;DMA channel 0 transfer complete + DCD DMA1_IRQHandler ;DMA channel 1 transfer complete + DCD DMA2_IRQHandler ;DMA channel 2 transfer complete + DCD DMA3_IRQHandler ;DMA channel 3 transfer complete + DCD Reserved20_IRQHandler ;Reserved interrupt + DCD FTFA_IRQHandler ;Command complete and read collision + DCD PMC_IRQHandler ;Low-voltage detect, low-voltage warning + DCD LLWU_IRQHandler ;Low leakage wakeup + DCD I2C0_IRQHandler ;I2C0 interrupt + DCD I2C1_IRQHandler ;I2C1 interrupt + DCD SPI0_IRQHandler ;SPI0 single interrupt vector for all sources + DCD SPI1_IRQHandler ;SPI1 single interrupt vector for all sources + DCD LPUART0_IRQHandler ;LPUART0 status and error + DCD LPUART1_IRQHandler ;LPUART1 status and error + DCD UART2_FLEXIO_IRQHandler ;UART2 or FLEXIO + DCD ADC0_IRQHandler ;ADC0 interrupt + DCD CMP0_IRQHandler ;CMP0 interrupt + DCD TPM0_IRQHandler ;TPM0 single interrupt vector for all sources + DCD TPM1_IRQHandler ;TPM1 single interrupt vector for all sources + DCD TPM2_IRQHandler ;TPM2 single interrupt vector for all sources + DCD RTC_IRQHandler ;RTC alarm + DCD RTC_Seconds_IRQHandler ;RTC seconds + DCD PIT_IRQHandler ;PIT interrupt + DCD I2S0_IRQHandler ;I2S0 interrupt + DCD USB0_IRQHandler ;USB0 interrupt + DCD DAC0_IRQHandler ;DAC0 interrupt + DCD Reserved42_IRQHandler ;Reserved interrupt + DCD Reserved43_IRQHandler ;Reserved interrupt + DCD LPTMR0_IRQHandler ;LPTMR0 interrupt + DCD LCD_IRQHandler ;LCD interrupt + DCD PORTA_IRQHandler ;PORTA Pin detect + DCD PORTC_PORTD_IRQHandler ;Single interrupt vector for PORTC; PORTD Pin detect +__Vectors_End + + SECTION FlashConfig:CODE +__FlashConfig + DCD 0xFFFFFFFF + DCD 0xFFFFFFFF + DCD 0xFFFFFFFF + DCD 0xFFFF3FFE +__FlashConfig_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + CPSID I ; Mask interrupts + LDR R0, =0xE000ED08 + LDR R1, =__vector_table + STR R1, [R0] + LDR R0, =SystemInit + BLX R0 + CPSIE I ; Unmask interrupts + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + PUBWEAK DMA0_IRQHandler + PUBWEAK DMA0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA0_IRQHandler + LDR R0, =DMA0_DriverIRQHandler + BX R0 + + PUBWEAK DMA1_IRQHandler + PUBWEAK DMA1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA1_IRQHandler + LDR R0, =DMA1_DriverIRQHandler + BX R0 + + PUBWEAK DMA2_IRQHandler + PUBWEAK DMA2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA2_IRQHandler + LDR R0, =DMA2_DriverIRQHandler + BX R0 + + PUBWEAK DMA3_IRQHandler + PUBWEAK DMA3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA3_IRQHandler + LDR R0, =DMA3_DriverIRQHandler + BX R0 + + PUBWEAK Reserved20_IRQHandler + PUBWEAK FTFA_IRQHandler + PUBWEAK PMC_IRQHandler + PUBWEAK LLWU_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK I2C0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +I2C0_IRQHandler + LDR R0, =I2C0_DriverIRQHandler + BX R0 + + PUBWEAK I2C1_IRQHandler + PUBWEAK I2C1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +I2C1_IRQHandler + LDR R0, =I2C1_DriverIRQHandler + BX R0 + + PUBWEAK SPI0_IRQHandler + PUBWEAK SPI0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SPI0_IRQHandler + LDR R0, =SPI0_DriverIRQHandler + BX R0 + + PUBWEAK SPI1_IRQHandler + PUBWEAK SPI1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SPI1_IRQHandler + LDR R0, =SPI1_DriverIRQHandler + BX R0 + + PUBWEAK LPUART0_IRQHandler + PUBWEAK LPUART0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPUART0_IRQHandler + LDR R0, =LPUART0_DriverIRQHandler + BX R0 + + PUBWEAK LPUART1_IRQHandler + PUBWEAK LPUART1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPUART1_IRQHandler + LDR R0, =LPUART1_DriverIRQHandler + BX R0 + + PUBWEAK UART2_FLEXIO_IRQHandler + PUBWEAK UART2_FLEXIO_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UART2_FLEXIO_IRQHandler + LDR R0, =UART2_FLEXIO_DriverIRQHandler + BX R0 + + PUBWEAK ADC0_IRQHandler + PUBWEAK CMP0_IRQHandler + PUBWEAK TPM0_IRQHandler + PUBWEAK TPM1_IRQHandler + PUBWEAK TPM2_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK RTC_Seconds_IRQHandler + PUBWEAK PIT_IRQHandler + PUBWEAK I2S0_IRQHandler + PUBWEAK I2S0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +I2S0_IRQHandler + LDR R0, =I2S0_DriverIRQHandler + BX R0 + + PUBWEAK USB0_IRQHandler + PUBWEAK DAC0_IRQHandler + PUBWEAK Reserved42_IRQHandler + PUBWEAK Reserved43_IRQHandler + PUBWEAK LPTMR0_IRQHandler + PUBWEAK LCD_IRQHandler + PUBWEAK PORTA_IRQHandler + PUBWEAK PORTC_PORTD_IRQHandler + PUBWEAK DefaultISR + SECTION .text:CODE:REORDER:NOROOT(2) +DMA0_DriverIRQHandler +DMA1_DriverIRQHandler +DMA2_DriverIRQHandler +DMA3_DriverIRQHandler +Reserved20_IRQHandler +FTFA_IRQHandler +PMC_IRQHandler +LLWU_IRQHandler +I2C0_DriverIRQHandler +I2C1_DriverIRQHandler +SPI0_DriverIRQHandler +SPI1_DriverIRQHandler +LPUART0_DriverIRQHandler +LPUART1_DriverIRQHandler +UART2_FLEXIO_DriverIRQHandler +ADC0_IRQHandler +CMP0_IRQHandler +TPM0_IRQHandler +TPM1_IRQHandler +TPM2_IRQHandler +RTC_IRQHandler +RTC_Seconds_IRQHandler +PIT_IRQHandler +I2S0_DriverIRQHandler +USB0_IRQHandler +DAC0_IRQHandler +Reserved42_IRQHandler +Reserved43_IRQHandler +LPTMR0_IRQHandler +LCD_IRQHandler +PORTA_IRQHandler +PORTC_PORTD_IRQHandler +DefaultISR + LDR R0, =DefaultISR + BX R0 + + END
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/device/TOOLCHAIN_IAR/startup_MKL43Z4.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,323 +0,0 @@ -; --------------------------------------------------------------------------------------- -; @file: startup_MKL43Z4.s -; @purpose: CMSIS Cortex-M0P Core Device Startup File -; MKL43Z4 -; @version: 1.8 -; @date: 2016-6-24 -; @build: b160627 -; --------------------------------------------------------------------------------------- -; -; Copyright (c) 1997 - 2016 , Freescale Semiconductor, Inc. -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without modification, -; are permitted provided that the following conditions are met: -; -; o Redistributions of source code must retain the above copyright notice, this list -; of conditions and the following disclaimer. -; -; o Redistributions in binary form must reproduce the above copyright notice, this -; list of conditions and the following disclaimer in the documentation and/or -; other materials provided with the distribution. -; -; o Neither the name of Freescale Semiconductor, Inc. nor the names of its -; contributors may be used to endorse or promote products derived from this -; software without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler ;NMI Handler - DCD HardFault_Handler ;Hard Fault Handler - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved -__vector_table_0x1c - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD SVC_Handler ;SVCall Handler - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD PendSV_Handler ;PendSV Handler - DCD SysTick_Handler ;SysTick Handler - - ;External Interrupts - DCD DMA0_IRQHandler ;DMA channel 0 transfer complete - DCD DMA1_IRQHandler ;DMA channel 1 transfer complete - DCD DMA2_IRQHandler ;DMA channel 2 transfer complete - DCD DMA3_IRQHandler ;DMA channel 3 transfer complete - DCD Reserved20_IRQHandler ;Reserved interrupt - DCD FTFA_IRQHandler ;Command complete and read collision - DCD PMC_IRQHandler ;Low-voltage detect, low-voltage warning - DCD LLWU_IRQHandler ;Low leakage wakeup - DCD I2C0_IRQHandler ;I2C0 interrupt - DCD I2C1_IRQHandler ;I2C1 interrupt - DCD SPI0_IRQHandler ;SPI0 single interrupt vector for all sources - DCD SPI1_IRQHandler ;SPI1 single interrupt vector for all sources - DCD LPUART0_IRQHandler ;LPUART0 status and error - DCD LPUART1_IRQHandler ;LPUART1 status and error - DCD UART2_FLEXIO_IRQHandler ;UART2 or FLEXIO - DCD ADC0_IRQHandler ;ADC0 interrupt - DCD CMP0_IRQHandler ;CMP0 interrupt - DCD TPM0_IRQHandler ;TPM0 single interrupt vector for all sources - DCD TPM1_IRQHandler ;TPM1 single interrupt vector for all sources - DCD TPM2_IRQHandler ;TPM2 single interrupt vector for all sources - DCD RTC_IRQHandler ;RTC alarm - DCD RTC_Seconds_IRQHandler ;RTC seconds - DCD PIT_IRQHandler ;PIT interrupt - DCD I2S0_IRQHandler ;I2S0 interrupt - DCD USB0_IRQHandler ;USB0 interrupt - DCD DAC0_IRQHandler ;DAC0 interrupt - DCD Reserved42_IRQHandler ;Reserved interrupt - DCD Reserved43_IRQHandler ;Reserved interrupt - DCD LPTMR0_IRQHandler ;LPTMR0 interrupt - DCD LCD_IRQHandler ;LCD interrupt - DCD PORTA_IRQHandler ;PORTA Pin detect - DCD PORTC_PORTD_IRQHandler ;Single interrupt vector for PORTC; PORTD Pin detect -__Vectors_End - - SECTION FlashConfig:CODE -__FlashConfig - DCD 0xFFFFFFFF - DCD 0xFFFFFFFF - DCD 0xFFFFFFFF - DCD 0xFFFF3FFE -__FlashConfig_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - CPSID I ; Mask interrupts - LDR R0, =0xE000ED08 - LDR R1, =__vector_table - STR R1, [R0] - LDR R0, =SystemInit - BLX R0 - CPSIE I ; Unmask interrupts - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B . - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B . - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B . - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B . - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B . - - PUBWEAK DMA0_IRQHandler - PUBWEAK DMA0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA0_IRQHandler - LDR R0, =DMA0_DriverIRQHandler - BX R0 - - PUBWEAK DMA1_IRQHandler - PUBWEAK DMA1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA1_IRQHandler - LDR R0, =DMA1_DriverIRQHandler - BX R0 - - PUBWEAK DMA2_IRQHandler - PUBWEAK DMA2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA2_IRQHandler - LDR R0, =DMA2_DriverIRQHandler - BX R0 - - PUBWEAK DMA3_IRQHandler - PUBWEAK DMA3_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA3_IRQHandler - LDR R0, =DMA3_DriverIRQHandler - BX R0 - - PUBWEAK Reserved20_IRQHandler - PUBWEAK FTFA_IRQHandler - PUBWEAK PMC_IRQHandler - PUBWEAK LLWU_IRQHandler - PUBWEAK I2C0_IRQHandler - PUBWEAK I2C0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -I2C0_IRQHandler - LDR R0, =I2C0_DriverIRQHandler - BX R0 - - PUBWEAK I2C1_IRQHandler - PUBWEAK I2C1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -I2C1_IRQHandler - LDR R0, =I2C1_DriverIRQHandler - BX R0 - - PUBWEAK SPI0_IRQHandler - PUBWEAK SPI0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SPI0_IRQHandler - LDR R0, =SPI0_DriverIRQHandler - BX R0 - - PUBWEAK SPI1_IRQHandler - PUBWEAK SPI1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SPI1_IRQHandler - LDR R0, =SPI1_DriverIRQHandler - BX R0 - - PUBWEAK LPUART0_IRQHandler - PUBWEAK LPUART0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -LPUART0_IRQHandler - LDR R0, =LPUART0_DriverIRQHandler - BX R0 - - PUBWEAK LPUART1_IRQHandler - PUBWEAK LPUART1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -LPUART1_IRQHandler - LDR R0, =LPUART1_DriverIRQHandler - BX R0 - - PUBWEAK UART2_FLEXIO_IRQHandler - PUBWEAK UART2_FLEXIO_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -UART2_FLEXIO_IRQHandler - LDR R0, =UART2_FLEXIO_DriverIRQHandler - BX R0 - - PUBWEAK ADC0_IRQHandler - PUBWEAK CMP0_IRQHandler - PUBWEAK TPM0_IRQHandler - PUBWEAK TPM1_IRQHandler - PUBWEAK TPM2_IRQHandler - PUBWEAK RTC_IRQHandler - PUBWEAK RTC_Seconds_IRQHandler - PUBWEAK PIT_IRQHandler - PUBWEAK I2S0_IRQHandler - PUBWEAK I2S0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -I2S0_IRQHandler - LDR R0, =I2S0_DriverIRQHandler - BX R0 - - PUBWEAK USB0_IRQHandler - PUBWEAK DAC0_IRQHandler - PUBWEAK Reserved42_IRQHandler - PUBWEAK Reserved43_IRQHandler - PUBWEAK LPTMR0_IRQHandler - PUBWEAK LCD_IRQHandler - PUBWEAK PORTA_IRQHandler - PUBWEAK PORTC_PORTD_IRQHandler - PUBWEAK DefaultISR - SECTION .text:CODE:REORDER:NOROOT(2) -DMA0_DriverIRQHandler -DMA1_DriverIRQHandler -DMA2_DriverIRQHandler -DMA3_DriverIRQHandler -Reserved20_IRQHandler -FTFA_IRQHandler -PMC_IRQHandler -LLWU_IRQHandler -I2C0_DriverIRQHandler -I2C1_DriverIRQHandler -SPI0_DriverIRQHandler -SPI1_DriverIRQHandler -LPUART0_DriverIRQHandler -LPUART1_DriverIRQHandler -UART2_FLEXIO_DriverIRQHandler -ADC0_IRQHandler -CMP0_IRQHandler -TPM0_IRQHandler -TPM1_IRQHandler -TPM2_IRQHandler -RTC_IRQHandler -RTC_Seconds_IRQHandler -PIT_IRQHandler -I2S0_DriverIRQHandler -USB0_IRQHandler -DAC0_IRQHandler -Reserved42_IRQHandler -Reserved43_IRQHandler -LPTMR0_IRQHandler -LCD_IRQHandler -PORTA_IRQHandler -PORTC_PORTD_IRQHandler -DefaultISR - LDR R0, =DefaultISR - BX R0 - - END
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/us_ticker.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL43Z/us_ticker.c Tue Mar 20 16:56:18 2018 +0000
@@ -90,9 +90,13 @@
void us_ticker_set_interrupt(timestamp_t timestamp)
{
- uint32_t delta = timestamp - us_ticker_read();
+ uint32_t now_us, delta_us;
+
+ now_us = us_ticker_read();
+ delta_us = timestamp >= now_us ? timestamp - now_us : (uint32_t)((uint64_t)timestamp + 0xFFFFFFFF - now_us);
+
LPTMR_StopTimer(LPTMR0);
- LPTMR_SetTimerPeriod(LPTMR0, (uint32_t)delta);
+ LPTMR_SetTimerPeriod(LPTMR0, (uint32_t)delta_us);
LPTMR_EnableInterrupts(LPTMR0, kLPTMR_TimerInterruptEnable);
LPTMR_StartTimer(LPTMR0);
}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/device/TOOLCHAIN_ARM_STD/startup_MKL82Z7.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,616 @@ +; * --------------------------------------------------------------------------------------- +; * @file: startup_MKL82Z7.s +; * @purpose: CMSIS Cortex-M0P Core Device Startup File +; * MKL82Z7 +; * @version: 1.5 +; * @date: 2015-9-24 +; * @build: b151217 +; * --------------------------------------------------------------------------------------- +; * +; * Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc. +; * All rights reserved. +; * +; * Redistribution and use in source and binary forms, with or without modification, +; * are permitted provided that the following conditions are met: +; * +; * o Redistributions of source code must retain the above copyright notice, this list +; * of conditions and the following disclaimer. +; * +; * o Redistributions in binary form must reproduce the above copyright notice, this +; * list of conditions and the following disclaimer in the documentation and/or +; * other materials provided with the distribution. +; * +; * o Neither the name of Freescale Semiconductor, Inc. nor the names of its +; * contributors may be used to endorse or promote products derived from this +; * software without specific prior written permission. +; * +; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; * +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; *****************************************************************************/ + +__initial_sp EQU 0x20012000 ; Top of RAM + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ;NMI Handler + DCD HardFault_Handler ;Hard Fault Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD SVC_Handler ;SVCall Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD PendSV_Handler ;PendSV Handler + DCD SysTick_Handler ;SysTick Handler + + ;External Interrupts + DCD DMA0_DMA4_IRQHandler ;DMA channel 0, 4 transfer complete + DCD DMA1_DMA5_IRQHandler ;DMA channel 1, 5 transfer complete + DCD DMA2_DMA6_IRQHandler ;DMA channel 2, 6 transfer complete + DCD DMA3_DMA7_IRQHandler ;DMA channel 3, 7 transfer complete + DCD DMA_Error_IRQHandler ;DMA channel 0 - 7 error + DCD FLEXIO0_IRQHandler ;Flexible IO + DCD TPM0_IRQHandler ;Timer/PWM module 0 + DCD TPM1_IRQHandler ;Timer/PWM module 1 + DCD TPM2_IRQHandler ;Timer/PWM module 2 + DCD PIT0_IRQHandler ;Periodic Interrupt Timer 0 + DCD SPI0_IRQHandler ;Serial Peripheral Interface 0 + DCD EMVSIM0_IRQHandler ;EMVSIM0 common interrupt + DCD LPUART0_IRQHandler ;LPUART0 status and error + DCD LPUART1_IRQHandler ;LPUART1 status and error + DCD I2C0_IRQHandler ;Inter-Integrated Circuit 0 + DCD QSPI0_IRQHandler ;QuadSPI0 interrupt + DCD Reserved32_IRQHandler ;DryIce tamper detect + DCD PORTA_IRQHandler ;Pin detect Port A + DCD PORTB_IRQHandler ;Pin detect Port B + DCD PORTC_IRQHandler ;Pin detect Port C + DCD PORTD_IRQHandler ;Pin detect Port D + DCD PORTE_IRQHandler ;Pin detect Port E + DCD LLWU_IRQHandler ;Low Leakage Wakeup + DCD LTC0_IRQHandler ;Low power trusted cryptographic + DCD USB0_IRQHandler ;USB OTG interrupt + DCD ADC0_IRQHandler ;Analog-to-Digital Converter 0 + DCD LPTMR0_IRQHandler ;Low-Power Timer 0 + DCD RTC_Seconds_IRQHandler ;RTC seconds + DCD INTMUX0_0_IRQHandler ;Selectable peripheral interrupt INTMUX0-0 + DCD INTMUX0_1_IRQHandler ;Selectable peripheral interrupt INTMUX0-1 + DCD INTMUX0_2_IRQHandler ;Selectable peripheral interrupt INTMUX0-2 + DCD INTMUX0_3_IRQHandler ;Selectable peripheral interrupt INTMUX0-3 + DCD LPTMR1_IRQHandler ;Low-Power Timer 1 (INTMUX source IRQ0) + DCD Reserved49_IRQHandler ;Reserved interrupt (INTMUX source IRQ1) + DCD Reserved50_IRQHandler ;Reserved interrupt (INTMUX source IRQ2) + DCD Reserved51_IRQHandler ;Reserved interrupt (INTMUX source IRQ3) + DCD SPI1_IRQHandler ;Serial Peripheral Interface 1 (INTMUX source IRQ4) + DCD LPUART2_IRQHandler ;LPUART2 status and error (INTMUX source IRQ5) + DCD EMVSIM1_IRQHandler ;EMVSIM1 common interrupt (INTMUX source IRQ6) + DCD I2C1_IRQHandler ;Inter-Integrated Circuit 1 (INTMUX source IRQ7) + DCD TSI0_IRQHandler ;Touch Sensing Input 0 (INTMUX source IRQ8) + DCD PMC_IRQHandler ;PMC controller low-voltage detect, low-voltage warning (INTMUX source IRQ9) + DCD FTFA_IRQHandler ;FTFA command complete/read collision (INTMUX source IRQ10) + DCD MCG_IRQHandler ;Multipurpose clock generator (INTMUX source IRQ11) + DCD WDOG_EWM_IRQHandler ;Single interrupt vector for WDOG and EWM (INTMUX source IRQ12) + DCD DAC0_IRQHandler ;Digital-to-analog converter 0 (INTMUX source IRQ13) + DCD TRNG0_IRQHandler ;True randon number generator (INTMUX source IRQ14) + DCD Reserved63_IRQHandler ;Reserved interrupt (INTMUX source IRQ15) + DCD CMP0_IRQHandler ;Comparator 0 (INTMUX source IRQ16) + DCD Reserved65_IRQHandler ;Reserved interrupt (INTMUX source IRQ17) + DCD RTC_Alarm_IRQHandler ;Real time clock (INTMUX source IRQ18) + DCD Reserved67_IRQHandler ;Reserved interrupt (INTMUX source IRQ19) + DCD Reserved68_IRQHandler ;Reserved interrupt (INTMUX source IRQ20) + DCD Reserved69_IRQHandler ;Reserved interrupt (INTMUX source IRQ21) + DCD Reserved70_IRQHandler ;Reserved interrupt (INTMUX source IRQ22) + DCD Reserved71_IRQHandler ;Reserved interrupt (INTMUX source IRQ23) + DCD DMA4_IRQHandler ;DMA channel 4 transfer complete (INTMUX source IRQ24) + DCD DMA5_IRQHandler ;DMA channel 5 transfer complete (INTMUX source IRQ25) + DCD DMA6_IRQHandler ;DMA channel 6 transfer complete (INTMUX source IRQ26) + DCD DMA7_IRQHandler ;DMA channel 7 transfer complete (INTMUX source IRQ27) + DCD Reserved76_IRQHandler ;Reserved interrupt (INTMUX source IRQ28) + DCD Reserved77_IRQHandler ;Reserved interrupt (INTMUX source IRQ29) + DCD Reserved78_IRQHandler ;Reserved interrupt (INTMUX source IRQ30) + DCD Reserved79_IRQHandler ;Reserved interrupt (INTMUX source IRQ31) +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + +; <h> Flash Configuration +; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset) +; <i> and security information that allows the MCU to restrict access to the FTFL module. +; <h> Backdoor Comparison Key +; <o0> Backdoor Comparison Key 0. <0x0-0xFF:2> +; <o1> Backdoor Comparison Key 1. <0x0-0xFF:2> +; <o2> Backdoor Comparison Key 2. <0x0-0xFF:2> +; <o3> Backdoor Comparison Key 3. <0x0-0xFF:2> +; <o4> Backdoor Comparison Key 4. <0x0-0xFF:2> +; <o5> Backdoor Comparison Key 5. <0x0-0xFF:2> +; <o6> Backdoor Comparison Key 6. <0x0-0xFF:2> +; <o7> Backdoor Comparison Key 7. <0x0-0xFF:2> +BackDoorK0 EQU 0xFF +BackDoorK1 EQU 0xFF +BackDoorK2 EQU 0xFF +BackDoorK3 EQU 0xFF +BackDoorK4 EQU 0xFF +BackDoorK5 EQU 0xFF +BackDoorK6 EQU 0xFF +BackDoorK7 EQU 0xFF +; </h> +; <h> Program flash protection bytes (FPROT) +; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit. +; <i> Each bit protects a 1/32 region of the program flash memory. +; <h> FPROT0 +; <i> Program Flash Region Protect Register 0 +; <i> 1/32 - 8/32 region +; <o.0> FPROT0.0 +; <o.1> FPROT0.1 +; <o.2> FPROT0.2 +; <o.3> FPROT0.3 +; <o.4> FPROT0.4 +; <o.5> FPROT0.5 +; <o.6> FPROT0.6 +; <o.7> FPROT0.7 +nFPROT0 EQU 0x00 +FPROT0 EQU nFPROT0:EOR:0xFF +; </h> +; <h> FPROT1 +; <i> Program Flash Region Protect Register 1 +; <i> 9/32 - 16/32 region +; <o.0> FPROT1.0 +; <o.1> FPROT1.1 +; <o.2> FPROT1.2 +; <o.3> FPROT1.3 +; <o.4> FPROT1.4 +; <o.5> FPROT1.5 +; <o.6> FPROT1.6 +; <o.7> FPROT1.7 +nFPROT1 EQU 0x00 +FPROT1 EQU nFPROT1:EOR:0xFF +; </h> +; <h> FPROT2 +; <i> Program Flash Region Protect Register 2 +; <i> 17/32 - 24/32 region +; <o.0> FPROT2.0 +; <o.1> FPROT2.1 +; <o.2> FPROT2.2 +; <o.3> FPROT2.3 +; <o.4> FPROT2.4 +; <o.5> FPROT2.5 +; <o.6> FPROT2.6 +; <o.7> FPROT2.7 +nFPROT2 EQU 0x00 +FPROT2 EQU nFPROT2:EOR:0xFF +; </h> +; <h> FPROT3 +; <i> Program Flash Region Protect Register 3 +; <i> 25/32 - 32/32 region +; <o.0> FPROT3.0 +; <o.1> FPROT3.1 +; <o.2> FPROT3.2 +; <o.3> FPROT3.3 +; <o.4> FPROT3.4 +; <o.5> FPROT3.5 +; <o.6> FPROT3.6 +; <o.7> FPROT3.7 +nFPROT3 EQU 0x00 +FPROT3 EQU nFPROT3:EOR:0xFF +; </h> +; </h> +; <h> Flash nonvolatile option byte (FOPT) +; <i> Allows the user to customize the operation of the MCU at boot time. +; <o.0> LPBOOT +; <0=> Low-power boot +; <1=> Normal boot +; <o.1> BOOTPIN_OPT +; <0=> Force Boot from ROM if BOOTCFG0 asserted, where BOOTCFG0 is the boot config function which is muxed with NMI pin +; <1=> Boot source configured by FOPT (BOOTSRC_SEL) bits +; <o.2> NMI_DIS +; <0=> NMI interrupts are always blocked +; <1=> NMI_b pin/interrupts reset default to enabled +; <o.5> FAST_INIT +; <0=> Slower initialization +; <1=> Fast Initialization +; <o.6..7> BOOTSRC_SEL +; <0=> Boot from Flash +; <2=> Boot from ROM, configure QSPI0, and enter boot loader mode. +; <3=> Boot from ROM and enter boot loader mode. +; <i> Boot source selection +FOPT EQU 0x3D +; </h> +; <h> Flash security byte (FSEC) +; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled", +; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!! +; <o.0..1> SEC +; <2=> MCU security status is unsecure +; <3=> MCU security status is secure +; <i> Flash Security +; <o.2..3> FSLACC +; <2=> Freescale factory access denied +; <3=> Freescale factory access granted +; <i> Freescale Failure Analysis Access Code +; <o.4..5> MEEN +; <2=> Mass erase is disabled +; <3=> Mass erase is enabled +; <o.6..7> KEYEN +; <2=> Backdoor key access enabled +; <3=> Backdoor key access disabled +; <i> Backdoor Key Security Enable +FSEC EQU 0xFE +; </h> +; </h> + IF :LNOT::DEF:RAM_TARGET + AREA FlashConfig, DATA, READONLY +__FlashConfig + DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3 + DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7 + DCB FPROT0 , FPROT1 , FPROT2 , FPROT3 + DCB FSEC , FOPT , 0xFF , 0xFF + ENDIF + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + IF :LNOT::DEF:RAM_TARGET + REQUIRE FlashConfig + ENDIF + + CPSID I ; Mask interrupts + LDR R0, =0xE000ED08 + LDR R1, =__Vectors + STR R1, [R0] + LDR R0, =SystemInit + BLX R0 + CPSIE i ; Unmask interrupts + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler\ + PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler\ + PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler\ + PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler\ + PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP +DMA0_DMA4_IRQHandler\ + PROC + EXPORT DMA0_DMA4_IRQHandler [WEAK] + LDR R0, =DMA0_DMA4_DriverIRQHandler + BX R0 + ENDP + +DMA1_DMA5_IRQHandler\ + PROC + EXPORT DMA1_DMA5_IRQHandler [WEAK] + LDR R0, =DMA1_DMA5_DriverIRQHandler + BX R0 + ENDP + +DMA2_DMA6_IRQHandler\ + PROC + EXPORT DMA2_DMA6_IRQHandler [WEAK] + LDR R0, =DMA2_DMA6_DriverIRQHandler + BX R0 + ENDP + +DMA3_DMA7_IRQHandler\ + PROC + EXPORT DMA3_DMA7_IRQHandler [WEAK] + LDR R0, =DMA3_DMA7_DriverIRQHandler + BX R0 + ENDP + +DMA_Error_IRQHandler\ + PROC + EXPORT DMA_Error_IRQHandler [WEAK] + LDR R0, =DMA_Error_DriverIRQHandler + BX R0 + ENDP + +FLEXIO0_IRQHandler\ + PROC + EXPORT FLEXIO0_IRQHandler [WEAK] + LDR R0, =FLEXIO0_DriverIRQHandler + BX R0 + ENDP + +SPI0_IRQHandler\ + PROC + EXPORT SPI0_IRQHandler [WEAK] + LDR R0, =SPI0_DriverIRQHandler + BX R0 + ENDP + +LPUART0_IRQHandler\ + PROC + EXPORT LPUART0_IRQHandler [WEAK] + LDR R0, =LPUART0_DriverIRQHandler + BX R0 + ENDP + +LPUART1_IRQHandler\ + PROC + EXPORT LPUART1_IRQHandler [WEAK] + LDR R0, =LPUART1_DriverIRQHandler + BX R0 + ENDP + +I2C0_IRQHandler\ + PROC + EXPORT I2C0_IRQHandler [WEAK] + LDR R0, =I2C0_DriverIRQHandler + BX R0 + ENDP + +QSPI0_IRQHandler\ + PROC + EXPORT QSPI0_IRQHandler [WEAK] + LDR R0, =QSPI0_DriverIRQHandler + BX R0 + ENDP + +INTMUX0_0_IRQHandler\ + PROC + EXPORT INTMUX0_0_IRQHandler [WEAK] + LDR R0, =INTMUX0_0_DriverIRQHandler + BX R0 + ENDP + +INTMUX0_1_IRQHandler\ + PROC + EXPORT INTMUX0_1_IRQHandler [WEAK] + LDR R0, =INTMUX0_1_DriverIRQHandler + BX R0 + ENDP + +INTMUX0_2_IRQHandler\ + PROC + EXPORT INTMUX0_2_IRQHandler [WEAK] + LDR R0, =INTMUX0_2_DriverIRQHandler + BX R0 + ENDP + +INTMUX0_3_IRQHandler\ + PROC + EXPORT INTMUX0_3_IRQHandler [WEAK] + LDR R0, =INTMUX0_3_DriverIRQHandler + BX R0 + ENDP + +SPI1_IRQHandler\ + PROC + EXPORT SPI1_IRQHandler [WEAK] + LDR R0, =SPI1_DriverIRQHandler + BX R0 + ENDP + +LPUART2_IRQHandler\ + PROC + EXPORT LPUART2_IRQHandler [WEAK] + LDR R0, =LPUART2_DriverIRQHandler + BX R0 + ENDP + +I2C1_IRQHandler\ + PROC + EXPORT I2C1_IRQHandler [WEAK] + LDR R0, =I2C1_DriverIRQHandler + BX R0 + ENDP + +DMA4_IRQHandler\ + PROC + EXPORT DMA4_IRQHandler [WEAK] + LDR R0, =DMA4_DriverIRQHandler + BX R0 + ENDP + +DMA5_IRQHandler\ + PROC + EXPORT DMA5_IRQHandler [WEAK] + LDR R0, =DMA5_DriverIRQHandler + BX R0 + ENDP + +DMA6_IRQHandler\ + PROC + EXPORT DMA6_IRQHandler [WEAK] + LDR R0, =DMA6_DriverIRQHandler + BX R0 + ENDP + +DMA7_IRQHandler\ + PROC + EXPORT DMA7_IRQHandler [WEAK] + LDR R0, =DMA7_DriverIRQHandler + BX R0 + ENDP + +Default_Handler\ + PROC + EXPORT DMA0_DMA4_DriverIRQHandler [WEAK] + EXPORT DMA1_DMA5_DriverIRQHandler [WEAK] + EXPORT DMA2_DMA6_DriverIRQHandler [WEAK] + EXPORT DMA3_DMA7_DriverIRQHandler [WEAK] + EXPORT DMA_Error_DriverIRQHandler [WEAK] + EXPORT FLEXIO0_DriverIRQHandler [WEAK] + EXPORT TPM0_IRQHandler [WEAK] + EXPORT TPM1_IRQHandler [WEAK] + EXPORT TPM2_IRQHandler [WEAK] + EXPORT PIT0_IRQHandler [WEAK] + EXPORT SPI0_DriverIRQHandler [WEAK] + EXPORT EMVSIM0_IRQHandler [WEAK] + EXPORT LPUART0_DriverIRQHandler [WEAK] + EXPORT LPUART1_DriverIRQHandler [WEAK] + EXPORT I2C0_DriverIRQHandler [WEAK] + EXPORT QSPI0_DriverIRQHandler [WEAK] + EXPORT Reserved32_IRQHandler [WEAK] + EXPORT PORTA_IRQHandler [WEAK] + EXPORT PORTB_IRQHandler [WEAK] + EXPORT PORTC_IRQHandler [WEAK] + EXPORT PORTD_IRQHandler [WEAK] + EXPORT PORTE_IRQHandler [WEAK] + EXPORT LLWU_IRQHandler [WEAK] + EXPORT LTC0_IRQHandler [WEAK] + EXPORT USB0_IRQHandler [WEAK] + EXPORT ADC0_IRQHandler [WEAK] + EXPORT LPTMR0_IRQHandler [WEAK] + EXPORT RTC_Seconds_IRQHandler [WEAK] + EXPORT INTMUX0_0_DriverIRQHandler [WEAK] + EXPORT INTMUX0_1_DriverIRQHandler [WEAK] + EXPORT INTMUX0_2_DriverIRQHandler [WEAK] + EXPORT INTMUX0_3_DriverIRQHandler [WEAK] + EXPORT LPTMR1_IRQHandler [WEAK] + EXPORT Reserved49_IRQHandler [WEAK] + EXPORT Reserved50_IRQHandler [WEAK] + EXPORT Reserved51_IRQHandler [WEAK] + EXPORT SPI1_DriverIRQHandler [WEAK] + EXPORT LPUART2_DriverIRQHandler [WEAK] + EXPORT EMVSIM1_IRQHandler [WEAK] + EXPORT I2C1_DriverIRQHandler [WEAK] + EXPORT TSI0_IRQHandler [WEAK] + EXPORT PMC_IRQHandler [WEAK] + EXPORT FTFA_IRQHandler [WEAK] + EXPORT MCG_IRQHandler [WEAK] + EXPORT WDOG_EWM_IRQHandler [WEAK] + EXPORT DAC0_IRQHandler [WEAK] + EXPORT TRNG0_IRQHandler [WEAK] + EXPORT Reserved63_IRQHandler [WEAK] + EXPORT CMP0_IRQHandler [WEAK] + EXPORT Reserved65_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT Reserved67_IRQHandler [WEAK] + EXPORT Reserved68_IRQHandler [WEAK] + EXPORT Reserved69_IRQHandler [WEAK] + EXPORT Reserved70_IRQHandler [WEAK] + EXPORT Reserved71_IRQHandler [WEAK] + EXPORT DMA4_DriverIRQHandler [WEAK] + EXPORT DMA5_DriverIRQHandler [WEAK] + EXPORT DMA6_DriverIRQHandler [WEAK] + EXPORT DMA7_DriverIRQHandler [WEAK] + EXPORT Reserved76_IRQHandler [WEAK] + EXPORT Reserved77_IRQHandler [WEAK] + EXPORT Reserved78_IRQHandler [WEAK] + EXPORT Reserved79_IRQHandler [WEAK] + EXPORT DefaultISR [WEAK] +DMA0_DMA4_DriverIRQHandler +DMA1_DMA5_DriverIRQHandler +DMA2_DMA6_DriverIRQHandler +DMA3_DMA7_DriverIRQHandler +DMA_Error_DriverIRQHandler +FLEXIO0_DriverIRQHandler +TPM0_IRQHandler +TPM1_IRQHandler +TPM2_IRQHandler +PIT0_IRQHandler +SPI0_DriverIRQHandler +EMVSIM0_IRQHandler +LPUART0_DriverIRQHandler +LPUART1_DriverIRQHandler +I2C0_DriverIRQHandler +QSPI0_DriverIRQHandler +Reserved32_IRQHandler +PORTA_IRQHandler +PORTB_IRQHandler +PORTC_IRQHandler +PORTD_IRQHandler +PORTE_IRQHandler +LLWU_IRQHandler +LTC0_IRQHandler +USB0_IRQHandler +ADC0_IRQHandler +LPTMR0_IRQHandler +RTC_Seconds_IRQHandler +INTMUX0_0_DriverIRQHandler +INTMUX0_1_DriverIRQHandler +INTMUX0_2_DriverIRQHandler +INTMUX0_3_DriverIRQHandler +LPTMR1_IRQHandler +Reserved49_IRQHandler +Reserved50_IRQHandler +Reserved51_IRQHandler +SPI1_DriverIRQHandler +LPUART2_DriverIRQHandler +EMVSIM1_IRQHandler +I2C1_DriverIRQHandler +TSI0_IRQHandler +PMC_IRQHandler +FTFA_IRQHandler +MCG_IRQHandler +WDOG_EWM_IRQHandler +DAC0_IRQHandler +TRNG0_IRQHandler +Reserved63_IRQHandler +CMP0_IRQHandler +Reserved65_IRQHandler +RTC_Alarm_IRQHandler +Reserved67_IRQHandler +Reserved68_IRQHandler +Reserved69_IRQHandler +Reserved70_IRQHandler +Reserved71_IRQHandler +DMA4_DriverIRQHandler +DMA5_DriverIRQHandler +DMA6_DriverIRQHandler +DMA7_DriverIRQHandler +Reserved76_IRQHandler +Reserved77_IRQHandler +Reserved78_IRQHandler +Reserved79_IRQHandler +DefaultISR + LDR R0, =DefaultISR + BX R0 + ENDP + ALIGN + + + END
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/device/TOOLCHAIN_ARM_STD/startup_MKL82Z7.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,616 +0,0 @@ -; * --------------------------------------------------------------------------------------- -; * @file: startup_MKL82Z7.s -; * @purpose: CMSIS Cortex-M0P Core Device Startup File -; * MKL82Z7 -; * @version: 1.5 -; * @date: 2015-9-24 -; * @build: b151217 -; * --------------------------------------------------------------------------------------- -; * -; * Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc. -; * All rights reserved. -; * -; * Redistribution and use in source and binary forms, with or without modification, -; * are permitted provided that the following conditions are met: -; * -; * o Redistributions of source code must retain the above copyright notice, this list -; * of conditions and the following disclaimer. -; * -; * o Redistributions in binary form must reproduce the above copyright notice, this -; * list of conditions and the following disclaimer in the documentation and/or -; * other materials provided with the distribution. -; * -; * o Neither the name of Freescale Semiconductor, Inc. nor the names of its -; * contributors may be used to endorse or promote products derived from this -; * software without specific prior written permission. -; * -; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; * -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; *****************************************************************************/ - -__initial_sp EQU 0x20012000 ; Top of RAM - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ;NMI Handler - DCD HardFault_Handler ;Hard Fault Handler - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD SVC_Handler ;SVCall Handler - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD PendSV_Handler ;PendSV Handler - DCD SysTick_Handler ;SysTick Handler - - ;External Interrupts - DCD DMA0_DMA4_IRQHandler ;DMA channel 0, 4 transfer complete - DCD DMA1_DMA5_IRQHandler ;DMA channel 1, 5 transfer complete - DCD DMA2_DMA6_IRQHandler ;DMA channel 2, 6 transfer complete - DCD DMA3_DMA7_IRQHandler ;DMA channel 3, 7 transfer complete - DCD DMA_Error_IRQHandler ;DMA channel 0 - 7 error - DCD FLEXIO0_IRQHandler ;Flexible IO - DCD TPM0_IRQHandler ;Timer/PWM module 0 - DCD TPM1_IRQHandler ;Timer/PWM module 1 - DCD TPM2_IRQHandler ;Timer/PWM module 2 - DCD PIT0_IRQHandler ;Periodic Interrupt Timer 0 - DCD SPI0_IRQHandler ;Serial Peripheral Interface 0 - DCD EMVSIM0_IRQHandler ;EMVSIM0 common interrupt - DCD LPUART0_IRQHandler ;LPUART0 status and error - DCD LPUART1_IRQHandler ;LPUART1 status and error - DCD I2C0_IRQHandler ;Inter-Integrated Circuit 0 - DCD QSPI0_IRQHandler ;QuadSPI0 interrupt - DCD Reserved32_IRQHandler ;DryIce tamper detect - DCD PORTA_IRQHandler ;Pin detect Port A - DCD PORTB_IRQHandler ;Pin detect Port B - DCD PORTC_IRQHandler ;Pin detect Port C - DCD PORTD_IRQHandler ;Pin detect Port D - DCD PORTE_IRQHandler ;Pin detect Port E - DCD LLWU_IRQHandler ;Low Leakage Wakeup - DCD LTC0_IRQHandler ;Low power trusted cryptographic - DCD USB0_IRQHandler ;USB OTG interrupt - DCD ADC0_IRQHandler ;Analog-to-Digital Converter 0 - DCD LPTMR0_IRQHandler ;Low-Power Timer 0 - DCD RTC_Seconds_IRQHandler ;RTC seconds - DCD INTMUX0_0_IRQHandler ;Selectable peripheral interrupt INTMUX0-0 - DCD INTMUX0_1_IRQHandler ;Selectable peripheral interrupt INTMUX0-1 - DCD INTMUX0_2_IRQHandler ;Selectable peripheral interrupt INTMUX0-2 - DCD INTMUX0_3_IRQHandler ;Selectable peripheral interrupt INTMUX0-3 - DCD LPTMR1_IRQHandler ;Low-Power Timer 1 (INTMUX source IRQ0) - DCD Reserved49_IRQHandler ;Reserved interrupt (INTMUX source IRQ1) - DCD Reserved50_IRQHandler ;Reserved interrupt (INTMUX source IRQ2) - DCD Reserved51_IRQHandler ;Reserved interrupt (INTMUX source IRQ3) - DCD SPI1_IRQHandler ;Serial Peripheral Interface 1 (INTMUX source IRQ4) - DCD LPUART2_IRQHandler ;LPUART2 status and error (INTMUX source IRQ5) - DCD EMVSIM1_IRQHandler ;EMVSIM1 common interrupt (INTMUX source IRQ6) - DCD I2C1_IRQHandler ;Inter-Integrated Circuit 1 (INTMUX source IRQ7) - DCD TSI0_IRQHandler ;Touch Sensing Input 0 (INTMUX source IRQ8) - DCD PMC_IRQHandler ;PMC controller low-voltage detect, low-voltage warning (INTMUX source IRQ9) - DCD FTFA_IRQHandler ;FTFA command complete/read collision (INTMUX source IRQ10) - DCD MCG_IRQHandler ;Multipurpose clock generator (INTMUX source IRQ11) - DCD WDOG_EWM_IRQHandler ;Single interrupt vector for WDOG and EWM (INTMUX source IRQ12) - DCD DAC0_IRQHandler ;Digital-to-analog converter 0 (INTMUX source IRQ13) - DCD TRNG0_IRQHandler ;True randon number generator (INTMUX source IRQ14) - DCD Reserved63_IRQHandler ;Reserved interrupt (INTMUX source IRQ15) - DCD CMP0_IRQHandler ;Comparator 0 (INTMUX source IRQ16) - DCD Reserved65_IRQHandler ;Reserved interrupt (INTMUX source IRQ17) - DCD RTC_Alarm_IRQHandler ;Real time clock (INTMUX source IRQ18) - DCD Reserved67_IRQHandler ;Reserved interrupt (INTMUX source IRQ19) - DCD Reserved68_IRQHandler ;Reserved interrupt (INTMUX source IRQ20) - DCD Reserved69_IRQHandler ;Reserved interrupt (INTMUX source IRQ21) - DCD Reserved70_IRQHandler ;Reserved interrupt (INTMUX source IRQ22) - DCD Reserved71_IRQHandler ;Reserved interrupt (INTMUX source IRQ23) - DCD DMA4_IRQHandler ;DMA channel 4 transfer complete (INTMUX source IRQ24) - DCD DMA5_IRQHandler ;DMA channel 5 transfer complete (INTMUX source IRQ25) - DCD DMA6_IRQHandler ;DMA channel 6 transfer complete (INTMUX source IRQ26) - DCD DMA7_IRQHandler ;DMA channel 7 transfer complete (INTMUX source IRQ27) - DCD Reserved76_IRQHandler ;Reserved interrupt (INTMUX source IRQ28) - DCD Reserved77_IRQHandler ;Reserved interrupt (INTMUX source IRQ29) - DCD Reserved78_IRQHandler ;Reserved interrupt (INTMUX source IRQ30) - DCD Reserved79_IRQHandler ;Reserved interrupt (INTMUX source IRQ31) -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - -; <h> Flash Configuration -; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset) -; <i> and security information that allows the MCU to restrict access to the FTFL module. -; <h> Backdoor Comparison Key -; <o0> Backdoor Comparison Key 0. <0x0-0xFF:2> -; <o1> Backdoor Comparison Key 1. <0x0-0xFF:2> -; <o2> Backdoor Comparison Key 2. <0x0-0xFF:2> -; <o3> Backdoor Comparison Key 3. <0x0-0xFF:2> -; <o4> Backdoor Comparison Key 4. <0x0-0xFF:2> -; <o5> Backdoor Comparison Key 5. <0x0-0xFF:2> -; <o6> Backdoor Comparison Key 6. <0x0-0xFF:2> -; <o7> Backdoor Comparison Key 7. <0x0-0xFF:2> -BackDoorK0 EQU 0xFF -BackDoorK1 EQU 0xFF -BackDoorK2 EQU 0xFF -BackDoorK3 EQU 0xFF -BackDoorK4 EQU 0xFF -BackDoorK5 EQU 0xFF -BackDoorK6 EQU 0xFF -BackDoorK7 EQU 0xFF -; </h> -; <h> Program flash protection bytes (FPROT) -; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit. -; <i> Each bit protects a 1/32 region of the program flash memory. -; <h> FPROT0 -; <i> Program Flash Region Protect Register 0 -; <i> 1/32 - 8/32 region -; <o.0> FPROT0.0 -; <o.1> FPROT0.1 -; <o.2> FPROT0.2 -; <o.3> FPROT0.3 -; <o.4> FPROT0.4 -; <o.5> FPROT0.5 -; <o.6> FPROT0.6 -; <o.7> FPROT0.7 -nFPROT0 EQU 0x00 -FPROT0 EQU nFPROT0:EOR:0xFF -; </h> -; <h> FPROT1 -; <i> Program Flash Region Protect Register 1 -; <i> 9/32 - 16/32 region -; <o.0> FPROT1.0 -; <o.1> FPROT1.1 -; <o.2> FPROT1.2 -; <o.3> FPROT1.3 -; <o.4> FPROT1.4 -; <o.5> FPROT1.5 -; <o.6> FPROT1.6 -; <o.7> FPROT1.7 -nFPROT1 EQU 0x00 -FPROT1 EQU nFPROT1:EOR:0xFF -; </h> -; <h> FPROT2 -; <i> Program Flash Region Protect Register 2 -; <i> 17/32 - 24/32 region -; <o.0> FPROT2.0 -; <o.1> FPROT2.1 -; <o.2> FPROT2.2 -; <o.3> FPROT2.3 -; <o.4> FPROT2.4 -; <o.5> FPROT2.5 -; <o.6> FPROT2.6 -; <o.7> FPROT2.7 -nFPROT2 EQU 0x00 -FPROT2 EQU nFPROT2:EOR:0xFF -; </h> -; <h> FPROT3 -; <i> Program Flash Region Protect Register 3 -; <i> 25/32 - 32/32 region -; <o.0> FPROT3.0 -; <o.1> FPROT3.1 -; <o.2> FPROT3.2 -; <o.3> FPROT3.3 -; <o.4> FPROT3.4 -; <o.5> FPROT3.5 -; <o.6> FPROT3.6 -; <o.7> FPROT3.7 -nFPROT3 EQU 0x00 -FPROT3 EQU nFPROT3:EOR:0xFF -; </h> -; </h> -; <h> Flash nonvolatile option byte (FOPT) -; <i> Allows the user to customize the operation of the MCU at boot time. -; <o.0> LPBOOT -; <0=> Low-power boot -; <1=> Normal boot -; <o.1> BOOTPIN_OPT -; <0=> Force Boot from ROM if BOOTCFG0 asserted, where BOOTCFG0 is the boot config function which is muxed with NMI pin -; <1=> Boot source configured by FOPT (BOOTSRC_SEL) bits -; <o.2> NMI_DIS -; <0=> NMI interrupts are always blocked -; <1=> NMI_b pin/interrupts reset default to enabled -; <o.5> FAST_INIT -; <0=> Slower initialization -; <1=> Fast Initialization -; <o.6..7> BOOTSRC_SEL -; <0=> Boot from Flash -; <2=> Boot from ROM, configure QSPI0, and enter boot loader mode. -; <3=> Boot from ROM and enter boot loader mode. -; <i> Boot source selection -FOPT EQU 0x3D -; </h> -; <h> Flash security byte (FSEC) -; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled", -; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!! -; <o.0..1> SEC -; <2=> MCU security status is unsecure -; <3=> MCU security status is secure -; <i> Flash Security -; <o.2..3> FSLACC -; <2=> Freescale factory access denied -; <3=> Freescale factory access granted -; <i> Freescale Failure Analysis Access Code -; <o.4..5> MEEN -; <2=> Mass erase is disabled -; <3=> Mass erase is enabled -; <o.6..7> KEYEN -; <2=> Backdoor key access enabled -; <3=> Backdoor key access disabled -; <i> Backdoor Key Security Enable -FSEC EQU 0xFE -; </h> -; </h> - IF :LNOT::DEF:RAM_TARGET - AREA FlashConfig, DATA, READONLY -__FlashConfig - DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3 - DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7 - DCB FPROT0 , FPROT1 , FPROT2 , FPROT3 - DCB FSEC , FOPT , 0xFF , 0xFF - ENDIF - - - AREA |.text|, CODE, READONLY - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - IF :LNOT::DEF:RAM_TARGET - REQUIRE FlashConfig - ENDIF - - CPSID I ; Mask interrupts - LDR R0, =0xE000ED08 - LDR R1, =__Vectors - STR R1, [R0] - LDR R0, =SystemInit - BLX R0 - CPSIE i ; Unmask interrupts - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) -NMI_Handler\ - PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler\ - PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler\ - PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler\ - PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP -DMA0_DMA4_IRQHandler\ - PROC - EXPORT DMA0_DMA4_IRQHandler [WEAK] - LDR R0, =DMA0_DMA4_DriverIRQHandler - BX R0 - ENDP - -DMA1_DMA5_IRQHandler\ - PROC - EXPORT DMA1_DMA5_IRQHandler [WEAK] - LDR R0, =DMA1_DMA5_DriverIRQHandler - BX R0 - ENDP - -DMA2_DMA6_IRQHandler\ - PROC - EXPORT DMA2_DMA6_IRQHandler [WEAK] - LDR R0, =DMA2_DMA6_DriverIRQHandler - BX R0 - ENDP - -DMA3_DMA7_IRQHandler\ - PROC - EXPORT DMA3_DMA7_IRQHandler [WEAK] - LDR R0, =DMA3_DMA7_DriverIRQHandler - BX R0 - ENDP - -DMA_Error_IRQHandler\ - PROC - EXPORT DMA_Error_IRQHandler [WEAK] - LDR R0, =DMA_Error_DriverIRQHandler - BX R0 - ENDP - -FLEXIO0_IRQHandler\ - PROC - EXPORT FLEXIO0_IRQHandler [WEAK] - LDR R0, =FLEXIO0_DriverIRQHandler - BX R0 - ENDP - -SPI0_IRQHandler\ - PROC - EXPORT SPI0_IRQHandler [WEAK] - LDR R0, =SPI0_DriverIRQHandler - BX R0 - ENDP - -LPUART0_IRQHandler\ - PROC - EXPORT LPUART0_IRQHandler [WEAK] - LDR R0, =LPUART0_DriverIRQHandler - BX R0 - ENDP - -LPUART1_IRQHandler\ - PROC - EXPORT LPUART1_IRQHandler [WEAK] - LDR R0, =LPUART1_DriverIRQHandler - BX R0 - ENDP - -I2C0_IRQHandler\ - PROC - EXPORT I2C0_IRQHandler [WEAK] - LDR R0, =I2C0_DriverIRQHandler - BX R0 - ENDP - -QSPI0_IRQHandler\ - PROC - EXPORT QSPI0_IRQHandler [WEAK] - LDR R0, =QSPI0_DriverIRQHandler - BX R0 - ENDP - -INTMUX0_0_IRQHandler\ - PROC - EXPORT INTMUX0_0_IRQHandler [WEAK] - LDR R0, =INTMUX0_0_DriverIRQHandler - BX R0 - ENDP - -INTMUX0_1_IRQHandler\ - PROC - EXPORT INTMUX0_1_IRQHandler [WEAK] - LDR R0, =INTMUX0_1_DriverIRQHandler - BX R0 - ENDP - -INTMUX0_2_IRQHandler\ - PROC - EXPORT INTMUX0_2_IRQHandler [WEAK] - LDR R0, =INTMUX0_2_DriverIRQHandler - BX R0 - ENDP - -INTMUX0_3_IRQHandler\ - PROC - EXPORT INTMUX0_3_IRQHandler [WEAK] - LDR R0, =INTMUX0_3_DriverIRQHandler - BX R0 - ENDP - -SPI1_IRQHandler\ - PROC - EXPORT SPI1_IRQHandler [WEAK] - LDR R0, =SPI1_DriverIRQHandler - BX R0 - ENDP - -LPUART2_IRQHandler\ - PROC - EXPORT LPUART2_IRQHandler [WEAK] - LDR R0, =LPUART2_DriverIRQHandler - BX R0 - ENDP - -I2C1_IRQHandler\ - PROC - EXPORT I2C1_IRQHandler [WEAK] - LDR R0, =I2C1_DriverIRQHandler - BX R0 - ENDP - -DMA4_IRQHandler\ - PROC - EXPORT DMA4_IRQHandler [WEAK] - LDR R0, =DMA4_DriverIRQHandler - BX R0 - ENDP - -DMA5_IRQHandler\ - PROC - EXPORT DMA5_IRQHandler [WEAK] - LDR R0, =DMA5_DriverIRQHandler - BX R0 - ENDP - -DMA6_IRQHandler\ - PROC - EXPORT DMA6_IRQHandler [WEAK] - LDR R0, =DMA6_DriverIRQHandler - BX R0 - ENDP - -DMA7_IRQHandler\ - PROC - EXPORT DMA7_IRQHandler [WEAK] - LDR R0, =DMA7_DriverIRQHandler - BX R0 - ENDP - -Default_Handler\ - PROC - EXPORT DMA0_DMA4_DriverIRQHandler [WEAK] - EXPORT DMA1_DMA5_DriverIRQHandler [WEAK] - EXPORT DMA2_DMA6_DriverIRQHandler [WEAK] - EXPORT DMA3_DMA7_DriverIRQHandler [WEAK] - EXPORT DMA_Error_DriverIRQHandler [WEAK] - EXPORT FLEXIO0_DriverIRQHandler [WEAK] - EXPORT TPM0_IRQHandler [WEAK] - EXPORT TPM1_IRQHandler [WEAK] - EXPORT TPM2_IRQHandler [WEAK] - EXPORT PIT0_IRQHandler [WEAK] - EXPORT SPI0_DriverIRQHandler [WEAK] - EXPORT EMVSIM0_IRQHandler [WEAK] - EXPORT LPUART0_DriverIRQHandler [WEAK] - EXPORT LPUART1_DriverIRQHandler [WEAK] - EXPORT I2C0_DriverIRQHandler [WEAK] - EXPORT QSPI0_DriverIRQHandler [WEAK] - EXPORT Reserved32_IRQHandler [WEAK] - EXPORT PORTA_IRQHandler [WEAK] - EXPORT PORTB_IRQHandler [WEAK] - EXPORT PORTC_IRQHandler [WEAK] - EXPORT PORTD_IRQHandler [WEAK] - EXPORT PORTE_IRQHandler [WEAK] - EXPORT LLWU_IRQHandler [WEAK] - EXPORT LTC0_IRQHandler [WEAK] - EXPORT USB0_IRQHandler [WEAK] - EXPORT ADC0_IRQHandler [WEAK] - EXPORT LPTMR0_IRQHandler [WEAK] - EXPORT RTC_Seconds_IRQHandler [WEAK] - EXPORT INTMUX0_0_DriverIRQHandler [WEAK] - EXPORT INTMUX0_1_DriverIRQHandler [WEAK] - EXPORT INTMUX0_2_DriverIRQHandler [WEAK] - EXPORT INTMUX0_3_DriverIRQHandler [WEAK] - EXPORT LPTMR1_IRQHandler [WEAK] - EXPORT Reserved49_IRQHandler [WEAK] - EXPORT Reserved50_IRQHandler [WEAK] - EXPORT Reserved51_IRQHandler [WEAK] - EXPORT SPI1_DriverIRQHandler [WEAK] - EXPORT LPUART2_DriverIRQHandler [WEAK] - EXPORT EMVSIM1_IRQHandler [WEAK] - EXPORT I2C1_DriverIRQHandler [WEAK] - EXPORT TSI0_IRQHandler [WEAK] - EXPORT PMC_IRQHandler [WEAK] - EXPORT FTFA_IRQHandler [WEAK] - EXPORT MCG_IRQHandler [WEAK] - EXPORT WDOG_EWM_IRQHandler [WEAK] - EXPORT DAC0_IRQHandler [WEAK] - EXPORT TRNG0_IRQHandler [WEAK] - EXPORT Reserved63_IRQHandler [WEAK] - EXPORT CMP0_IRQHandler [WEAK] - EXPORT Reserved65_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT Reserved67_IRQHandler [WEAK] - EXPORT Reserved68_IRQHandler [WEAK] - EXPORT Reserved69_IRQHandler [WEAK] - EXPORT Reserved70_IRQHandler [WEAK] - EXPORT Reserved71_IRQHandler [WEAK] - EXPORT DMA4_DriverIRQHandler [WEAK] - EXPORT DMA5_DriverIRQHandler [WEAK] - EXPORT DMA6_DriverIRQHandler [WEAK] - EXPORT DMA7_DriverIRQHandler [WEAK] - EXPORT Reserved76_IRQHandler [WEAK] - EXPORT Reserved77_IRQHandler [WEAK] - EXPORT Reserved78_IRQHandler [WEAK] - EXPORT Reserved79_IRQHandler [WEAK] - EXPORT DefaultISR [WEAK] -DMA0_DMA4_DriverIRQHandler -DMA1_DMA5_DriverIRQHandler -DMA2_DMA6_DriverIRQHandler -DMA3_DMA7_DriverIRQHandler -DMA_Error_DriverIRQHandler -FLEXIO0_DriverIRQHandler -TPM0_IRQHandler -TPM1_IRQHandler -TPM2_IRQHandler -PIT0_IRQHandler -SPI0_DriverIRQHandler -EMVSIM0_IRQHandler -LPUART0_DriverIRQHandler -LPUART1_DriverIRQHandler -I2C0_DriverIRQHandler -QSPI0_DriverIRQHandler -Reserved32_IRQHandler -PORTA_IRQHandler -PORTB_IRQHandler -PORTC_IRQHandler -PORTD_IRQHandler -PORTE_IRQHandler -LLWU_IRQHandler -LTC0_IRQHandler -USB0_IRQHandler -ADC0_IRQHandler -LPTMR0_IRQHandler -RTC_Seconds_IRQHandler -INTMUX0_0_DriverIRQHandler -INTMUX0_1_DriverIRQHandler -INTMUX0_2_DriverIRQHandler -INTMUX0_3_DriverIRQHandler -LPTMR1_IRQHandler -Reserved49_IRQHandler -Reserved50_IRQHandler -Reserved51_IRQHandler -SPI1_DriverIRQHandler -LPUART2_DriverIRQHandler -EMVSIM1_IRQHandler -I2C1_DriverIRQHandler -TSI0_IRQHandler -PMC_IRQHandler -FTFA_IRQHandler -MCG_IRQHandler -WDOG_EWM_IRQHandler -DAC0_IRQHandler -TRNG0_IRQHandler -Reserved63_IRQHandler -CMP0_IRQHandler -Reserved65_IRQHandler -RTC_Alarm_IRQHandler -Reserved67_IRQHandler -Reserved68_IRQHandler -Reserved69_IRQHandler -Reserved70_IRQHandler -Reserved71_IRQHandler -DMA4_DriverIRQHandler -DMA5_DriverIRQHandler -DMA6_DriverIRQHandler -DMA7_DriverIRQHandler -Reserved76_IRQHandler -Reserved77_IRQHandler -Reserved78_IRQHandler -Reserved79_IRQHandler -DefaultISR - LDR R0, =DefaultISR - BX R0 - ENDP - ALIGN - - - END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/device/TOOLCHAIN_IAR/startup_MKL82Z7.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,479 @@ +; --------------------------------------------------------------------------------------- +; @file: startup_MKL82Z7.s +; @purpose: CMSIS Cortex-M0P Core Device Startup File +; MKL82Z7 +; @version: 1.5 +; @date: 2015-9-24 +; @build: b151217 +; --------------------------------------------------------------------------------------- +; +; Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc. +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without modification, +; are permitted provided that the following conditions are met: +; +; o Redistributions of source code must retain the above copyright notice, this list +; of conditions and the following disclaimer. +; +; o Redistributions in binary form must reproduce the above copyright notice, this +; list of conditions and the following disclaimer in the documentation and/or +; other materials provided with the distribution. +; +; o Neither the name of Freescale Semiconductor, Inc. nor the names of its +; contributors may be used to endorse or promote products derived from this +; software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler ;NMI Handler + DCD HardFault_Handler ;Hard Fault Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved +__vector_table_0x1c + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD SVC_Handler ;SVCall Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD PendSV_Handler ;PendSV Handler + DCD SysTick_Handler ;SysTick Handler + + ;External Interrupts + DCD DMA0_DMA4_IRQHandler ;DMA channel 0, 4 transfer complete + DCD DMA1_DMA5_IRQHandler ;DMA channel 1, 5 transfer complete + DCD DMA2_DMA6_IRQHandler ;DMA channel 2, 6 transfer complete + DCD DMA3_DMA7_IRQHandler ;DMA channel 3, 7 transfer complete + DCD DMA_Error_IRQHandler ;DMA channel 0 - 7 error + DCD FLEXIO0_IRQHandler ;Flexible IO + DCD TPM0_IRQHandler ;Timer/PWM module 0 + DCD TPM1_IRQHandler ;Timer/PWM module 1 + DCD TPM2_IRQHandler ;Timer/PWM module 2 + DCD PIT0_IRQHandler ;Periodic Interrupt Timer 0 + DCD SPI0_IRQHandler ;Serial Peripheral Interface 0 + DCD EMVSIM0_IRQHandler ;EMVSIM0 common interrupt + DCD LPUART0_IRQHandler ;LPUART0 status and error + DCD LPUART1_IRQHandler ;LPUART1 status and error + DCD I2C0_IRQHandler ;Inter-Integrated Circuit 0 + DCD QSPI0_IRQHandler ;QuadSPI0 interrupt + DCD Reserved32_IRQHandler ;DryIce tamper detect + DCD PORTA_IRQHandler ;Pin detect Port A + DCD PORTB_IRQHandler ;Pin detect Port B + DCD PORTC_IRQHandler ;Pin detect Port C + DCD PORTD_IRQHandler ;Pin detect Port D + DCD PORTE_IRQHandler ;Pin detect Port E + DCD LLWU_IRQHandler ;Low Leakage Wakeup + DCD LTC0_IRQHandler ;Low power trusted cryptographic + DCD USB0_IRQHandler ;USB OTG interrupt + DCD ADC0_IRQHandler ;Analog-to-Digital Converter 0 + DCD LPTMR0_IRQHandler ;Low-Power Timer 0 + DCD RTC_Seconds_IRQHandler ;RTC seconds + DCD INTMUX0_0_IRQHandler ;Selectable peripheral interrupt INTMUX0-0 + DCD INTMUX0_1_IRQHandler ;Selectable peripheral interrupt INTMUX0-1 + DCD INTMUX0_2_IRQHandler ;Selectable peripheral interrupt INTMUX0-2 + DCD INTMUX0_3_IRQHandler ;Selectable peripheral interrupt INTMUX0-3 + DCD LPTMR1_IRQHandler ;Low-Power Timer 1 (INTMUX source IRQ0) + DCD Reserved49_IRQHandler ;Reserved interrupt (INTMUX source IRQ1) + DCD Reserved50_IRQHandler ;Reserved interrupt (INTMUX source IRQ2) + DCD Reserved51_IRQHandler ;Reserved interrupt (INTMUX source IRQ3) + DCD SPI1_IRQHandler ;Serial Peripheral Interface 1 (INTMUX source IRQ4) + DCD LPUART2_IRQHandler ;LPUART2 status and error (INTMUX source IRQ5) + DCD EMVSIM1_IRQHandler ;EMVSIM1 common interrupt (INTMUX source IRQ6) + DCD I2C1_IRQHandler ;Inter-Integrated Circuit 1 (INTMUX source IRQ7) + DCD TSI0_IRQHandler ;Touch Sensing Input 0 (INTMUX source IRQ8) + DCD PMC_IRQHandler ;PMC controller low-voltage detect, low-voltage warning (INTMUX source IRQ9) + DCD FTFA_IRQHandler ;FTFA command complete/read collision (INTMUX source IRQ10) + DCD MCG_IRQHandler ;Multipurpose clock generator (INTMUX source IRQ11) + DCD WDOG_EWM_IRQHandler ;Single interrupt vector for WDOG and EWM (INTMUX source IRQ12) + DCD DAC0_IRQHandler ;Digital-to-analog converter 0 (INTMUX source IRQ13) + DCD TRNG0_IRQHandler ;True randon number generator (INTMUX source IRQ14) + DCD Reserved63_IRQHandler ;Reserved interrupt (INTMUX source IRQ15) + DCD CMP0_IRQHandler ;Comparator 0 (INTMUX source IRQ16) + DCD Reserved65_IRQHandler ;Reserved interrupt (INTMUX source IRQ17) + DCD RTC_Alarm_IRQHandler ;Real time clock (INTMUX source IRQ18) + DCD Reserved67_IRQHandler ;Reserved interrupt (INTMUX source IRQ19) + DCD Reserved68_IRQHandler ;Reserved interrupt (INTMUX source IRQ20) + DCD Reserved69_IRQHandler ;Reserved interrupt (INTMUX source IRQ21) + DCD Reserved70_IRQHandler ;Reserved interrupt (INTMUX source IRQ22) + DCD Reserved71_IRQHandler ;Reserved interrupt (INTMUX source IRQ23) + DCD DMA4_IRQHandler ;DMA channel 4 transfer complete (INTMUX source IRQ24) + DCD DMA5_IRQHandler ;DMA channel 5 transfer complete (INTMUX source IRQ25) + DCD DMA6_IRQHandler ;DMA channel 6 transfer complete (INTMUX source IRQ26) + DCD DMA7_IRQHandler ;DMA channel 7 transfer complete (INTMUX source IRQ27) + DCD Reserved76_IRQHandler ;Reserved interrupt (INTMUX source IRQ28) + DCD Reserved77_IRQHandler ;Reserved interrupt (INTMUX source IRQ29) + DCD Reserved78_IRQHandler ;Reserved interrupt (INTMUX source IRQ30) + DCD Reserved79_IRQHandler ;Reserved interrupt (INTMUX source IRQ31) +__Vectors_End + + SECTION FlashConfig:CODE +__FlashConfig + DCD 0xFFFFFFFF + DCD 0xFFFFFFFF + DCD 0xFFFFFFFF + DCD 0xFFFF3DFE +__FlashConfig_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + CPSID I ; Mask interrupts + LDR R0, =0xE000ED08 + LDR R1, =__vector_table + STR R1, [R0] + LDR R0, =SystemInit + BLX R0 + CPSIE I ; Unmask interrupts + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + PUBWEAK DMA0_DMA4_IRQHandler + PUBWEAK DMA0_DMA4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA0_DMA4_IRQHandler + LDR R0, =DMA0_DMA4_DriverIRQHandler + BX R0 + + PUBWEAK DMA1_DMA5_IRQHandler + PUBWEAK DMA1_DMA5_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA1_DMA5_IRQHandler + LDR R0, =DMA1_DMA5_DriverIRQHandler + BX R0 + + PUBWEAK DMA2_DMA6_IRQHandler + PUBWEAK DMA2_DMA6_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA2_DMA6_IRQHandler + LDR R0, =DMA2_DMA6_DriverIRQHandler + BX R0 + + PUBWEAK DMA3_DMA7_IRQHandler + PUBWEAK DMA3_DMA7_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA3_DMA7_IRQHandler + LDR R0, =DMA3_DMA7_DriverIRQHandler + BX R0 + + PUBWEAK DMA_Error_IRQHandler + PUBWEAK DMA_Error_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA_Error_IRQHandler + LDR R0, =DMA_Error_DriverIRQHandler + BX R0 + + PUBWEAK FLEXIO0_IRQHandler + PUBWEAK FLEXIO0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXIO0_IRQHandler + LDR R0, =FLEXIO0_DriverIRQHandler + BX R0 + + PUBWEAK TPM0_IRQHandler + PUBWEAK TPM1_IRQHandler + PUBWEAK TPM2_IRQHandler + PUBWEAK PIT0_IRQHandler + PUBWEAK SPI0_IRQHandler + PUBWEAK SPI0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SPI0_IRQHandler + LDR R0, =SPI0_DriverIRQHandler + BX R0 + + PUBWEAK EMVSIM0_IRQHandler + PUBWEAK LPUART0_IRQHandler + PUBWEAK LPUART0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPUART0_IRQHandler + LDR R0, =LPUART0_DriverIRQHandler + BX R0 + + PUBWEAK LPUART1_IRQHandler + PUBWEAK LPUART1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPUART1_IRQHandler + LDR R0, =LPUART1_DriverIRQHandler + BX R0 + + PUBWEAK I2C0_IRQHandler + PUBWEAK I2C0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +I2C0_IRQHandler + LDR R0, =I2C0_DriverIRQHandler + BX R0 + + PUBWEAK QSPI0_IRQHandler + PUBWEAK QSPI0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +QSPI0_IRQHandler + LDR R0, =QSPI0_DriverIRQHandler + BX R0 + + PUBWEAK Reserved32_IRQHandler + PUBWEAK PORTA_IRQHandler + PUBWEAK PORTB_IRQHandler + PUBWEAK PORTC_IRQHandler + PUBWEAK PORTD_IRQHandler + PUBWEAK PORTE_IRQHandler + PUBWEAK LLWU_IRQHandler + PUBWEAK LTC0_IRQHandler + PUBWEAK USB0_IRQHandler + PUBWEAK ADC0_IRQHandler + PUBWEAK LPTMR0_IRQHandler + PUBWEAK RTC_Seconds_IRQHandler + PUBWEAK INTMUX0_0_IRQHandler + PUBWEAK INTMUX0_0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +INTMUX0_0_IRQHandler + LDR R0, =INTMUX0_0_DriverIRQHandler + BX R0 + + PUBWEAK INTMUX0_1_IRQHandler + PUBWEAK INTMUX0_1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +INTMUX0_1_IRQHandler + LDR R0, =INTMUX0_1_DriverIRQHandler + BX R0 + + PUBWEAK INTMUX0_2_IRQHandler + PUBWEAK INTMUX0_2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +INTMUX0_2_IRQHandler + LDR R0, =INTMUX0_2_DriverIRQHandler + BX R0 + + PUBWEAK INTMUX0_3_IRQHandler + PUBWEAK INTMUX0_3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +INTMUX0_3_IRQHandler + LDR R0, =INTMUX0_3_DriverIRQHandler + BX R0 + + PUBWEAK LPTMR1_IRQHandler + PUBWEAK Reserved49_IRQHandler + PUBWEAK Reserved50_IRQHandler + PUBWEAK Reserved51_IRQHandler + PUBWEAK SPI1_IRQHandler + PUBWEAK SPI1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SPI1_IRQHandler + LDR R0, =SPI1_DriverIRQHandler + BX R0 + + PUBWEAK LPUART2_IRQHandler + PUBWEAK LPUART2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPUART2_IRQHandler + LDR R0, =LPUART2_DriverIRQHandler + BX R0 + + PUBWEAK EMVSIM1_IRQHandler + PUBWEAK I2C1_IRQHandler + PUBWEAK I2C1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +I2C1_IRQHandler + LDR R0, =I2C1_DriverIRQHandler + BX R0 + + PUBWEAK TSI0_IRQHandler + PUBWEAK PMC_IRQHandler + PUBWEAK FTFA_IRQHandler + PUBWEAK MCG_IRQHandler + PUBWEAK WDOG_EWM_IRQHandler + PUBWEAK DAC0_IRQHandler + PUBWEAK TRNG0_IRQHandler + PUBWEAK Reserved63_IRQHandler + PUBWEAK CMP0_IRQHandler + PUBWEAK Reserved65_IRQHandler + PUBWEAK RTC_Alarm_IRQHandler + PUBWEAK Reserved67_IRQHandler + PUBWEAK Reserved68_IRQHandler + PUBWEAK Reserved69_IRQHandler + PUBWEAK Reserved70_IRQHandler + PUBWEAK Reserved71_IRQHandler + PUBWEAK DMA4_IRQHandler + PUBWEAK DMA4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA4_IRQHandler + LDR R0, =DMA4_DriverIRQHandler + BX R0 + + PUBWEAK DMA5_IRQHandler + PUBWEAK DMA5_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA5_IRQHandler + LDR R0, =DMA5_DriverIRQHandler + BX R0 + + PUBWEAK DMA6_IRQHandler + PUBWEAK DMA6_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA6_IRQHandler + LDR R0, =DMA6_DriverIRQHandler + BX R0 + + PUBWEAK DMA7_IRQHandler + PUBWEAK DMA7_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA7_IRQHandler + LDR R0, =DMA7_DriverIRQHandler + BX R0 + + PUBWEAK Reserved76_IRQHandler + PUBWEAK Reserved77_IRQHandler + PUBWEAK Reserved78_IRQHandler + PUBWEAK Reserved79_IRQHandler + PUBWEAK DefaultISR + SECTION .text:CODE:REORDER:NOROOT(2) +DMA0_DMA4_DriverIRQHandler +DMA1_DMA5_DriverIRQHandler +DMA2_DMA6_DriverIRQHandler +DMA3_DMA7_DriverIRQHandler +DMA_Error_DriverIRQHandler +FLEXIO0_DriverIRQHandler +TPM0_IRQHandler +TPM1_IRQHandler +TPM2_IRQHandler +PIT0_IRQHandler +SPI0_DriverIRQHandler +EMVSIM0_IRQHandler +LPUART0_DriverIRQHandler +LPUART1_DriverIRQHandler +I2C0_DriverIRQHandler +QSPI0_DriverIRQHandler +Reserved32_IRQHandler +PORTA_IRQHandler +PORTB_IRQHandler +PORTC_IRQHandler +PORTD_IRQHandler +PORTE_IRQHandler +LLWU_IRQHandler +LTC0_IRQHandler +USB0_IRQHandler +ADC0_IRQHandler +LPTMR0_IRQHandler +RTC_Seconds_IRQHandler +INTMUX0_0_DriverIRQHandler +INTMUX0_1_DriverIRQHandler +INTMUX0_2_DriverIRQHandler +INTMUX0_3_DriverIRQHandler +LPTMR1_IRQHandler +Reserved49_IRQHandler +Reserved50_IRQHandler +Reserved51_IRQHandler +SPI1_DriverIRQHandler +LPUART2_DriverIRQHandler +EMVSIM1_IRQHandler +I2C1_DriverIRQHandler +TSI0_IRQHandler +PMC_IRQHandler +FTFA_IRQHandler +MCG_IRQHandler +WDOG_EWM_IRQHandler +DAC0_IRQHandler +TRNG0_IRQHandler +Reserved63_IRQHandler +CMP0_IRQHandler +Reserved65_IRQHandler +RTC_Alarm_IRQHandler +Reserved67_IRQHandler +Reserved68_IRQHandler +Reserved69_IRQHandler +Reserved70_IRQHandler +Reserved71_IRQHandler +DMA4_DriverIRQHandler +DMA5_DriverIRQHandler +DMA6_DriverIRQHandler +DMA7_DriverIRQHandler +Reserved76_IRQHandler +Reserved77_IRQHandler +Reserved78_IRQHandler +Reserved79_IRQHandler +DefaultISR + LDR R0, =DefaultISR + BX R0 + + END
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/device/TOOLCHAIN_IAR/startup_MKL82Z7.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,479 +0,0 @@ -; --------------------------------------------------------------------------------------- -; @file: startup_MKL82Z7.s -; @purpose: CMSIS Cortex-M0P Core Device Startup File -; MKL82Z7 -; @version: 1.5 -; @date: 2015-9-24 -; @build: b151217 -; --------------------------------------------------------------------------------------- -; -; Copyright (c) 1997 - 2015 , Freescale Semiconductor, Inc. -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without modification, -; are permitted provided that the following conditions are met: -; -; o Redistributions of source code must retain the above copyright notice, this list -; of conditions and the following disclaimer. -; -; o Redistributions in binary form must reproduce the above copyright notice, this -; list of conditions and the following disclaimer in the documentation and/or -; other materials provided with the distribution. -; -; o Neither the name of Freescale Semiconductor, Inc. nor the names of its -; contributors may be used to endorse or promote products derived from this -; software without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler ;NMI Handler - DCD HardFault_Handler ;Hard Fault Handler - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved -__vector_table_0x1c - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD SVC_Handler ;SVCall Handler - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD PendSV_Handler ;PendSV Handler - DCD SysTick_Handler ;SysTick Handler - - ;External Interrupts - DCD DMA0_DMA4_IRQHandler ;DMA channel 0, 4 transfer complete - DCD DMA1_DMA5_IRQHandler ;DMA channel 1, 5 transfer complete - DCD DMA2_DMA6_IRQHandler ;DMA channel 2, 6 transfer complete - DCD DMA3_DMA7_IRQHandler ;DMA channel 3, 7 transfer complete - DCD DMA_Error_IRQHandler ;DMA channel 0 - 7 error - DCD FLEXIO0_IRQHandler ;Flexible IO - DCD TPM0_IRQHandler ;Timer/PWM module 0 - DCD TPM1_IRQHandler ;Timer/PWM module 1 - DCD TPM2_IRQHandler ;Timer/PWM module 2 - DCD PIT0_IRQHandler ;Periodic Interrupt Timer 0 - DCD SPI0_IRQHandler ;Serial Peripheral Interface 0 - DCD EMVSIM0_IRQHandler ;EMVSIM0 common interrupt - DCD LPUART0_IRQHandler ;LPUART0 status and error - DCD LPUART1_IRQHandler ;LPUART1 status and error - DCD I2C0_IRQHandler ;Inter-Integrated Circuit 0 - DCD QSPI0_IRQHandler ;QuadSPI0 interrupt - DCD Reserved32_IRQHandler ;DryIce tamper detect - DCD PORTA_IRQHandler ;Pin detect Port A - DCD PORTB_IRQHandler ;Pin detect Port B - DCD PORTC_IRQHandler ;Pin detect Port C - DCD PORTD_IRQHandler ;Pin detect Port D - DCD PORTE_IRQHandler ;Pin detect Port E - DCD LLWU_IRQHandler ;Low Leakage Wakeup - DCD LTC0_IRQHandler ;Low power trusted cryptographic - DCD USB0_IRQHandler ;USB OTG interrupt - DCD ADC0_IRQHandler ;Analog-to-Digital Converter 0 - DCD LPTMR0_IRQHandler ;Low-Power Timer 0 - DCD RTC_Seconds_IRQHandler ;RTC seconds - DCD INTMUX0_0_IRQHandler ;Selectable peripheral interrupt INTMUX0-0 - DCD INTMUX0_1_IRQHandler ;Selectable peripheral interrupt INTMUX0-1 - DCD INTMUX0_2_IRQHandler ;Selectable peripheral interrupt INTMUX0-2 - DCD INTMUX0_3_IRQHandler ;Selectable peripheral interrupt INTMUX0-3 - DCD LPTMR1_IRQHandler ;Low-Power Timer 1 (INTMUX source IRQ0) - DCD Reserved49_IRQHandler ;Reserved interrupt (INTMUX source IRQ1) - DCD Reserved50_IRQHandler ;Reserved interrupt (INTMUX source IRQ2) - DCD Reserved51_IRQHandler ;Reserved interrupt (INTMUX source IRQ3) - DCD SPI1_IRQHandler ;Serial Peripheral Interface 1 (INTMUX source IRQ4) - DCD LPUART2_IRQHandler ;LPUART2 status and error (INTMUX source IRQ5) - DCD EMVSIM1_IRQHandler ;EMVSIM1 common interrupt (INTMUX source IRQ6) - DCD I2C1_IRQHandler ;Inter-Integrated Circuit 1 (INTMUX source IRQ7) - DCD TSI0_IRQHandler ;Touch Sensing Input 0 (INTMUX source IRQ8) - DCD PMC_IRQHandler ;PMC controller low-voltage detect, low-voltage warning (INTMUX source IRQ9) - DCD FTFA_IRQHandler ;FTFA command complete/read collision (INTMUX source IRQ10) - DCD MCG_IRQHandler ;Multipurpose clock generator (INTMUX source IRQ11) - DCD WDOG_EWM_IRQHandler ;Single interrupt vector for WDOG and EWM (INTMUX source IRQ12) - DCD DAC0_IRQHandler ;Digital-to-analog converter 0 (INTMUX source IRQ13) - DCD TRNG0_IRQHandler ;True randon number generator (INTMUX source IRQ14) - DCD Reserved63_IRQHandler ;Reserved interrupt (INTMUX source IRQ15) - DCD CMP0_IRQHandler ;Comparator 0 (INTMUX source IRQ16) - DCD Reserved65_IRQHandler ;Reserved interrupt (INTMUX source IRQ17) - DCD RTC_Alarm_IRQHandler ;Real time clock (INTMUX source IRQ18) - DCD Reserved67_IRQHandler ;Reserved interrupt (INTMUX source IRQ19) - DCD Reserved68_IRQHandler ;Reserved interrupt (INTMUX source IRQ20) - DCD Reserved69_IRQHandler ;Reserved interrupt (INTMUX source IRQ21) - DCD Reserved70_IRQHandler ;Reserved interrupt (INTMUX source IRQ22) - DCD Reserved71_IRQHandler ;Reserved interrupt (INTMUX source IRQ23) - DCD DMA4_IRQHandler ;DMA channel 4 transfer complete (INTMUX source IRQ24) - DCD DMA5_IRQHandler ;DMA channel 5 transfer complete (INTMUX source IRQ25) - DCD DMA6_IRQHandler ;DMA channel 6 transfer complete (INTMUX source IRQ26) - DCD DMA7_IRQHandler ;DMA channel 7 transfer complete (INTMUX source IRQ27) - DCD Reserved76_IRQHandler ;Reserved interrupt (INTMUX source IRQ28) - DCD Reserved77_IRQHandler ;Reserved interrupt (INTMUX source IRQ29) - DCD Reserved78_IRQHandler ;Reserved interrupt (INTMUX source IRQ30) - DCD Reserved79_IRQHandler ;Reserved interrupt (INTMUX source IRQ31) -__Vectors_End - - SECTION FlashConfig:CODE -__FlashConfig - DCD 0xFFFFFFFF - DCD 0xFFFFFFFF - DCD 0xFFFFFFFF - DCD 0xFFFF3DFE -__FlashConfig_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - CPSID I ; Mask interrupts - LDR R0, =0xE000ED08 - LDR R1, =__vector_table - STR R1, [R0] - LDR R0, =SystemInit - BLX R0 - CPSIE I ; Unmask interrupts - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B . - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B . - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B . - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B . - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B . - - PUBWEAK DMA0_DMA4_IRQHandler - PUBWEAK DMA0_DMA4_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA0_DMA4_IRQHandler - LDR R0, =DMA0_DMA4_DriverIRQHandler - BX R0 - - PUBWEAK DMA1_DMA5_IRQHandler - PUBWEAK DMA1_DMA5_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA1_DMA5_IRQHandler - LDR R0, =DMA1_DMA5_DriverIRQHandler - BX R0 - - PUBWEAK DMA2_DMA6_IRQHandler - PUBWEAK DMA2_DMA6_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA2_DMA6_IRQHandler - LDR R0, =DMA2_DMA6_DriverIRQHandler - BX R0 - - PUBWEAK DMA3_DMA7_IRQHandler - PUBWEAK DMA3_DMA7_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA3_DMA7_IRQHandler - LDR R0, =DMA3_DMA7_DriverIRQHandler - BX R0 - - PUBWEAK DMA_Error_IRQHandler - PUBWEAK DMA_Error_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA_Error_IRQHandler - LDR R0, =DMA_Error_DriverIRQHandler - BX R0 - - PUBWEAK FLEXIO0_IRQHandler - PUBWEAK FLEXIO0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXIO0_IRQHandler - LDR R0, =FLEXIO0_DriverIRQHandler - BX R0 - - PUBWEAK TPM0_IRQHandler - PUBWEAK TPM1_IRQHandler - PUBWEAK TPM2_IRQHandler - PUBWEAK PIT0_IRQHandler - PUBWEAK SPI0_IRQHandler - PUBWEAK SPI0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SPI0_IRQHandler - LDR R0, =SPI0_DriverIRQHandler - BX R0 - - PUBWEAK EMVSIM0_IRQHandler - PUBWEAK LPUART0_IRQHandler - PUBWEAK LPUART0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -LPUART0_IRQHandler - LDR R0, =LPUART0_DriverIRQHandler - BX R0 - - PUBWEAK LPUART1_IRQHandler - PUBWEAK LPUART1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -LPUART1_IRQHandler - LDR R0, =LPUART1_DriverIRQHandler - BX R0 - - PUBWEAK I2C0_IRQHandler - PUBWEAK I2C0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -I2C0_IRQHandler - LDR R0, =I2C0_DriverIRQHandler - BX R0 - - PUBWEAK QSPI0_IRQHandler - PUBWEAK QSPI0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -QSPI0_IRQHandler - LDR R0, =QSPI0_DriverIRQHandler - BX R0 - - PUBWEAK Reserved32_IRQHandler - PUBWEAK PORTA_IRQHandler - PUBWEAK PORTB_IRQHandler - PUBWEAK PORTC_IRQHandler - PUBWEAK PORTD_IRQHandler - PUBWEAK PORTE_IRQHandler - PUBWEAK LLWU_IRQHandler - PUBWEAK LTC0_IRQHandler - PUBWEAK USB0_IRQHandler - PUBWEAK ADC0_IRQHandler - PUBWEAK LPTMR0_IRQHandler - PUBWEAK RTC_Seconds_IRQHandler - PUBWEAK INTMUX0_0_IRQHandler - PUBWEAK INTMUX0_0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -INTMUX0_0_IRQHandler - LDR R0, =INTMUX0_0_DriverIRQHandler - BX R0 - - PUBWEAK INTMUX0_1_IRQHandler - PUBWEAK INTMUX0_1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -INTMUX0_1_IRQHandler - LDR R0, =INTMUX0_1_DriverIRQHandler - BX R0 - - PUBWEAK INTMUX0_2_IRQHandler - PUBWEAK INTMUX0_2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -INTMUX0_2_IRQHandler - LDR R0, =INTMUX0_2_DriverIRQHandler - BX R0 - - PUBWEAK INTMUX0_3_IRQHandler - PUBWEAK INTMUX0_3_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -INTMUX0_3_IRQHandler - LDR R0, =INTMUX0_3_DriverIRQHandler - BX R0 - - PUBWEAK LPTMR1_IRQHandler - PUBWEAK Reserved49_IRQHandler - PUBWEAK Reserved50_IRQHandler - PUBWEAK Reserved51_IRQHandler - PUBWEAK SPI1_IRQHandler - PUBWEAK SPI1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SPI1_IRQHandler - LDR R0, =SPI1_DriverIRQHandler - BX R0 - - PUBWEAK LPUART2_IRQHandler - PUBWEAK LPUART2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -LPUART2_IRQHandler - LDR R0, =LPUART2_DriverIRQHandler - BX R0 - - PUBWEAK EMVSIM1_IRQHandler - PUBWEAK I2C1_IRQHandler - PUBWEAK I2C1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -I2C1_IRQHandler - LDR R0, =I2C1_DriverIRQHandler - BX R0 - - PUBWEAK TSI0_IRQHandler - PUBWEAK PMC_IRQHandler - PUBWEAK FTFA_IRQHandler - PUBWEAK MCG_IRQHandler - PUBWEAK WDOG_EWM_IRQHandler - PUBWEAK DAC0_IRQHandler - PUBWEAK TRNG0_IRQHandler - PUBWEAK Reserved63_IRQHandler - PUBWEAK CMP0_IRQHandler - PUBWEAK Reserved65_IRQHandler - PUBWEAK RTC_Alarm_IRQHandler - PUBWEAK Reserved67_IRQHandler - PUBWEAK Reserved68_IRQHandler - PUBWEAK Reserved69_IRQHandler - PUBWEAK Reserved70_IRQHandler - PUBWEAK Reserved71_IRQHandler - PUBWEAK DMA4_IRQHandler - PUBWEAK DMA4_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA4_IRQHandler - LDR R0, =DMA4_DriverIRQHandler - BX R0 - - PUBWEAK DMA5_IRQHandler - PUBWEAK DMA5_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA5_IRQHandler - LDR R0, =DMA5_DriverIRQHandler - BX R0 - - PUBWEAK DMA6_IRQHandler - PUBWEAK DMA6_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA6_IRQHandler - LDR R0, =DMA6_DriverIRQHandler - BX R0 - - PUBWEAK DMA7_IRQHandler - PUBWEAK DMA7_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA7_IRQHandler - LDR R0, =DMA7_DriverIRQHandler - BX R0 - - PUBWEAK Reserved76_IRQHandler - PUBWEAK Reserved77_IRQHandler - PUBWEAK Reserved78_IRQHandler - PUBWEAK Reserved79_IRQHandler - PUBWEAK DefaultISR - SECTION .text:CODE:REORDER:NOROOT(2) -DMA0_DMA4_DriverIRQHandler -DMA1_DMA5_DriverIRQHandler -DMA2_DMA6_DriverIRQHandler -DMA3_DMA7_DriverIRQHandler -DMA_Error_DriverIRQHandler -FLEXIO0_DriverIRQHandler -TPM0_IRQHandler -TPM1_IRQHandler -TPM2_IRQHandler -PIT0_IRQHandler -SPI0_DriverIRQHandler -EMVSIM0_IRQHandler -LPUART0_DriverIRQHandler -LPUART1_DriverIRQHandler -I2C0_DriverIRQHandler -QSPI0_DriverIRQHandler -Reserved32_IRQHandler -PORTA_IRQHandler -PORTB_IRQHandler -PORTC_IRQHandler -PORTD_IRQHandler -PORTE_IRQHandler -LLWU_IRQHandler -LTC0_IRQHandler -USB0_IRQHandler -ADC0_IRQHandler -LPTMR0_IRQHandler -RTC_Seconds_IRQHandler -INTMUX0_0_DriverIRQHandler -INTMUX0_1_DriverIRQHandler -INTMUX0_2_DriverIRQHandler -INTMUX0_3_DriverIRQHandler -LPTMR1_IRQHandler -Reserved49_IRQHandler -Reserved50_IRQHandler -Reserved51_IRQHandler -SPI1_DriverIRQHandler -LPUART2_DriverIRQHandler -EMVSIM1_IRQHandler -I2C1_DriverIRQHandler -TSI0_IRQHandler -PMC_IRQHandler -FTFA_IRQHandler -MCG_IRQHandler -WDOG_EWM_IRQHandler -DAC0_IRQHandler -TRNG0_IRQHandler -Reserved63_IRQHandler -CMP0_IRQHandler -Reserved65_IRQHandler -RTC_Alarm_IRQHandler -Reserved67_IRQHandler -Reserved68_IRQHandler -Reserved69_IRQHandler -Reserved70_IRQHandler -Reserved71_IRQHandler -DMA4_DriverIRQHandler -DMA5_DriverIRQHandler -DMA6_DriverIRQHandler -DMA7_DriverIRQHandler -Reserved76_IRQHandler -Reserved77_IRQHandler -Reserved78_IRQHandler -Reserved79_IRQHandler -DefaultISR - LDR R0, =DefaultISR - BX R0 - - END
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/us_ticker.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KL82Z/us_ticker.c Tue Mar 20 16:56:18 2018 +0000
@@ -83,10 +83,14 @@
void us_ticker_set_interrupt(timestamp_t timestamp)
{
- uint32_t delta = timestamp - us_ticker_read();
+ uint32_t now_us, delta_us;
+
+ now_us = us_ticker_read();
+ delta_us = timestamp >= now_us ? timestamp - now_us : (uint32_t)((uint64_t)timestamp + 0xFFFFFFFF - now_us);
+
PIT_StopTimer(PIT, kPIT_Chnl_3);
PIT_StopTimer(PIT, kPIT_Chnl_2);
- PIT_SetTimerPeriod(PIT, kPIT_Chnl_3, (uint32_t)delta);
+ PIT_SetTimerPeriod(PIT, kPIT_Chnl_3, (uint32_t)delta_us);
PIT_EnableInterrupts(PIT, kPIT_Chnl_3, kPIT_TimerInterruptEnable);
PIT_StartTimer(PIT, kPIT_Chnl_3);
PIT_StartTimer(PIT, kPIT_Chnl_2);
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/TOOLCHAIN_IAR/startup_MKW24D5.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,718 @@ +; --------------------------------------------------------------------------------------- +; @file: startup_MKW24D5.s +; @purpose: CMSIS Cortex-M4 Core Device Startup File +; MKW24D5 +; @version: 2.0 +; @date: 2014-11-26 +; @build: b160512 +; --------------------------------------------------------------------------------------- +; +; Copyright (c) 1997 - 2016 , Freescale Semiconductor, Inc. +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without modification, +; are permitted provided that the following conditions are met: +; +; o Redistributions of source code must retain the above copyright notice, this list +; of conditions and the following disclaimer. +; +; o Redistributions in binary form must reproduce the above copyright notice, this +; list of conditions and the following disclaimer in the documentation and/or +; other materials provided with the distribution. +; +; o Neither the name of Freescale Semiconductor, Inc. nor the names of its +; contributors may be used to endorse or promote products derived from this +; software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler ;NMI Handler + DCD HardFault_Handler ;Hard Fault Handler + DCD MemManage_Handler ;MPU Fault Handler + DCD BusFault_Handler ;Bus Fault Handler + DCD UsageFault_Handler ;Usage Fault Handler +__vector_table_0x1c + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD SVC_Handler ;SVCall Handler + DCD DebugMon_Handler ;Debug Monitor Handler + DCD 0 ;Reserved + DCD PendSV_Handler ;PendSV Handler + DCD SysTick_Handler ;SysTick Handler + + ;External Interrupts + DCD DMA0_IRQHandler ;DMA channel 0 transfer complete + DCD DMA1_IRQHandler ;DMA channel 1 transfer complete + DCD DMA2_IRQHandler ;DMA channel 2 transfer complete + DCD DMA3_IRQHandler ;DMA channel 3 transfer complete + DCD DMA4_IRQHandler ;DMA channel 4 transfer complete + DCD DMA5_IRQHandler ;DMA channel 5 transfer complete + DCD DMA6_IRQHandler ;DMA channel 6 transfer complete + DCD DMA7_IRQHandler ;DMA channel 7 transfer complete + DCD DMA8_IRQHandler ;DMA channel 8 transfer complete + DCD DMA9_IRQHandler ;DMA channel 9 transfer complete + DCD DMA10_IRQHandler ;DMA channel 10 transfer complete + DCD DMA11_IRQHandler ;DMA channel 11 transfer complete + DCD DMA12_IRQHandler ;DMA channel 12 transfer complete + DCD DMA13_IRQHandler ;DMA channel 13 transfer complete + DCD DMA14_IRQHandler ;DMA channel 14 transfer complete + DCD DMA15_IRQHandler ;DMA channel 15 transfer complete + DCD DMA_Error_IRQHandler ;DMA channel 0 - 15 error + DCD MCM_IRQHandler ;MCM normal interrupt + DCD FTFL_IRQHandler ;FTFL command complete + DCD FTFL_Collision_IRQHandler ;FTFL read collision + DCD PMC_IRQHandler ;PMC controller low-voltage detect, low-voltage warning + DCD LLWU_IRQHandler ;Low leakage wakeup + DCD WDOG_EWM_IRQHandler ;Single interrupt vector for WDOG and EWM + DCD RNG_IRQHandler ;Randon number generator + DCD I2C0_IRQHandler ;Inter-integrated circuit 0 + DCD I2C1_IRQHandler ;Inter-integrated circuit 1 + DCD SPI0_IRQHandler ;Serial peripheral Interface 0 + DCD SPI1_IRQHandler ;Serial peripheral Interface 1 + DCD I2S0_Tx_IRQHandler ;Integrated interchip sound 0 transmit interrupt + DCD I2S0_Rx_IRQHandler ;Integrated interchip sound 0 receive interrupt + DCD Reserved46_IRQHandler ;Reserved interrupt + DCD UART0_RX_TX_IRQHandler ;UART0 receive/transmit interrupt + DCD UART0_ERR_IRQHandler ;UART0 error interrupt + DCD UART1_RX_TX_IRQHandler ;UART1 receive/transmit interrupt + DCD UART1_ERR_IRQHandler ;UART1 error interrupt + DCD UART2_RX_TX_IRQHandler ;UART2 receive/transmit interrupt + DCD UART2_ERR_IRQHandler ;UART2 error interrupt + DCD Reserved53_IRQHandler ;Reserved interrupt + DCD Reserved54_IRQHandler ;Reserved interrupt + DCD ADC0_IRQHandler ;Analog-to-digital converter 0 + DCD CMP0_IRQHandler ;Comparator 0 + DCD CMP1_IRQHandler ;Comparator 1 + DCD FTM0_IRQHandler ;FlexTimer module 0 fault, overflow and channels interrupt + DCD FTM1_IRQHandler ;FlexTimer module 1 fault, overflow and channels interrupt + DCD FTM2_IRQHandler ;FlexTimer module 2 fault, overflow and channels interrupt + DCD CMT_IRQHandler ;Carrier modulator transmitter + DCD RTC_IRQHandler ;Real time clock + DCD RTC_Seconds_IRQHandler ;Real time clock seconds + DCD PIT0_IRQHandler ;Periodic interrupt timer channel 0 + DCD PIT1_IRQHandler ;Periodic interrupt timer channel 1 + DCD PIT2_IRQHandler ;Periodic interrupt timer channel 2 + DCD PIT3_IRQHandler ;Periodic interrupt timer channel 3 + DCD PDB0_IRQHandler ;Programmable delay block + DCD USB0_IRQHandler ;USB OTG interrupt + DCD USBDCD_IRQHandler ;USB charger detect + DCD Reserved71_IRQHandler ;Reserved interrupt + DCD Reserved72_IRQHandler ;Reserved interrupt + DCD MCG_IRQHandler ;Multipurpose clock generator + DCD LPTMR0_IRQHandler ;Low power timer interrupt + DCD PORTA_IRQHandler ;Port A pin detect interrupt + DCD PORTB_IRQHandler ;Port B pin detect interrupt + DCD PORTC_IRQHandler ;Port C pin detect interrupt + DCD PORTD_IRQHandler ;Port D pin detect interrupt + DCD PORTE_IRQHandler ;Port E pin detect interrupt + DCD SWI_IRQHandler ;Software interrupt + DCD DefaultISR ;81 + DCD DefaultISR ;82 + DCD DefaultISR ;83 + DCD DefaultISR ;84 + DCD DefaultISR ;85 + DCD DefaultISR ;86 + DCD DefaultISR ;87 + DCD DefaultISR ;88 + DCD DefaultISR ;89 + DCD DefaultISR ;90 + DCD DefaultISR ;91 + DCD DefaultISR ;92 + DCD DefaultISR ;93 + DCD DefaultISR ;94 + DCD DefaultISR ;95 + DCD DefaultISR ;96 + DCD DefaultISR ;97 + DCD DefaultISR ;98 + DCD DefaultISR ;99 + DCD DefaultISR ;100 + DCD DefaultISR ;101 + DCD DefaultISR ;102 + DCD DefaultISR ;103 + DCD DefaultISR ;104 + DCD DefaultISR ;105 + DCD DefaultISR ;106 + DCD DefaultISR ;107 + DCD DefaultISR ;108 + DCD DefaultISR ;109 + DCD DefaultISR ;110 + DCD DefaultISR ;111 + DCD DefaultISR ;112 + DCD DefaultISR ;113 + DCD DefaultISR ;114 + DCD DefaultISR ;115 + DCD DefaultISR ;116 + DCD DefaultISR ;117 + DCD DefaultISR ;118 + DCD DefaultISR ;119 + DCD DefaultISR ;120 + DCD DefaultISR ;121 + DCD DefaultISR ;122 + DCD DefaultISR ;123 + DCD DefaultISR ;124 + DCD DefaultISR ;125 + DCD DefaultISR ;126 + DCD DefaultISR ;127 + DCD DefaultISR ;128 + DCD DefaultISR ;129 + DCD DefaultISR ;130 + DCD DefaultISR ;131 + DCD DefaultISR ;132 + DCD DefaultISR ;133 + DCD DefaultISR ;134 + DCD DefaultISR ;135 + DCD DefaultISR ;136 + DCD DefaultISR ;137 + DCD DefaultISR ;138 + DCD DefaultISR ;139 + DCD DefaultISR ;140 + DCD DefaultISR ;141 + DCD DefaultISR ;142 + DCD DefaultISR ;143 + DCD DefaultISR ;144 + DCD DefaultISR ;145 + DCD DefaultISR ;146 + DCD DefaultISR ;147 + DCD DefaultISR ;148 + DCD DefaultISR ;149 + DCD DefaultISR ;150 + DCD DefaultISR ;151 + DCD DefaultISR ;152 + DCD DefaultISR ;153 + DCD DefaultISR ;154 + DCD DefaultISR ;155 + DCD DefaultISR ;156 + DCD DefaultISR ;157 + DCD DefaultISR ;158 + DCD DefaultISR ;159 + DCD DefaultISR ;160 + DCD DefaultISR ;161 + DCD DefaultISR ;162 + DCD DefaultISR ;163 + DCD DefaultISR ;164 + DCD DefaultISR ;165 + DCD DefaultISR ;166 + DCD DefaultISR ;167 + DCD DefaultISR ;168 + DCD DefaultISR ;169 + DCD DefaultISR ;170 + DCD DefaultISR ;171 + DCD DefaultISR ;172 + DCD DefaultISR ;173 + DCD DefaultISR ;174 + DCD DefaultISR ;175 + DCD DefaultISR ;176 + DCD DefaultISR ;177 + DCD DefaultISR ;178 + DCD DefaultISR ;179 + DCD DefaultISR ;180 + DCD DefaultISR ;181 + DCD DefaultISR ;182 + DCD DefaultISR ;183 + DCD DefaultISR ;184 + DCD DefaultISR ;185 + DCD DefaultISR ;186 + DCD DefaultISR ;187 + DCD DefaultISR ;188 + DCD DefaultISR ;189 + DCD DefaultISR ;190 + DCD DefaultISR ;191 + DCD DefaultISR ;192 + DCD DefaultISR ;193 + DCD DefaultISR ;194 + DCD DefaultISR ;195 + DCD DefaultISR ;196 + DCD DefaultISR ;197 + DCD DefaultISR ;198 + DCD DefaultISR ;199 + DCD DefaultISR ;200 + DCD DefaultISR ;201 + DCD DefaultISR ;202 + DCD DefaultISR ;203 + DCD DefaultISR ;204 + DCD DefaultISR ;205 + DCD DefaultISR ;206 + DCD DefaultISR ;207 + DCD DefaultISR ;208 + DCD DefaultISR ;209 + DCD DefaultISR ;210 + DCD DefaultISR ;211 + DCD DefaultISR ;212 + DCD DefaultISR ;213 + DCD DefaultISR ;214 + DCD DefaultISR ;215 + DCD DefaultISR ;216 + DCD DefaultISR ;217 + DCD DefaultISR ;218 + DCD DefaultISR ;219 + DCD DefaultISR ;220 + DCD DefaultISR ;221 + DCD DefaultISR ;222 + DCD DefaultISR ;223 + DCD DefaultISR ;224 + DCD DefaultISR ;225 + DCD DefaultISR ;226 + DCD DefaultISR ;227 + DCD DefaultISR ;228 + DCD DefaultISR ;229 + DCD DefaultISR ;230 + DCD DefaultISR ;231 + DCD DefaultISR ;232 + DCD DefaultISR ;233 + DCD DefaultISR ;234 + DCD DefaultISR ;235 + DCD DefaultISR ;236 + DCD DefaultISR ;237 + DCD DefaultISR ;238 + DCD DefaultISR ;239 + DCD DefaultISR ;240 + DCD DefaultISR ;241 + DCD DefaultISR ;242 + DCD DefaultISR ;243 + DCD DefaultISR ;244 + DCD DefaultISR ;245 + DCD DefaultISR ;246 + DCD DefaultISR ;247 + DCD DefaultISR ;248 + DCD DefaultISR ;249 + DCD DefaultISR ;250 + DCD DefaultISR ;251 + DCD DefaultISR ;252 + DCD DefaultISR ;253 + DCD DefaultISR ;254 + DCD 0xFFFFFFFF ; Reserved for user TRIM value +__Vectors_End + + SECTION FlashConfig:CODE +__FlashConfig + DCD 0xFFFFFFFF + DCD 0xFFFFFFFF + DCD 0xFFFFFFFF + DCD 0xFFFFFFFE +__FlashConfig_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + CPSID I ; Mask interrupts + LDR R0, =0xE000ED08 + LDR R1, =__vector_table + STR R1, [R0] + LDR R0, =SystemInit + BLX R0 + CPSIE I ; Unmask interrupts + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B . + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B . + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + PUBWEAK DMA0_IRQHandler + PUBWEAK DMA0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA0_IRQHandler + LDR R0, =DMA0_DriverIRQHandler + BX R0 + + PUBWEAK DMA1_IRQHandler + PUBWEAK DMA1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA1_IRQHandler + LDR R0, =DMA1_DriverIRQHandler + BX R0 + + PUBWEAK DMA2_IRQHandler + PUBWEAK DMA2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA2_IRQHandler + LDR R0, =DMA2_DriverIRQHandler + BX R0 + + PUBWEAK DMA3_IRQHandler + PUBWEAK DMA3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA3_IRQHandler + LDR R0, =DMA3_DriverIRQHandler + BX R0 + + PUBWEAK DMA4_IRQHandler + PUBWEAK DMA4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA4_IRQHandler + LDR R0, =DMA4_DriverIRQHandler + BX R0 + + PUBWEAK DMA5_IRQHandler + PUBWEAK DMA5_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA5_IRQHandler + LDR R0, =DMA5_DriverIRQHandler + BX R0 + + PUBWEAK DMA6_IRQHandler + PUBWEAK DMA6_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA6_IRQHandler + LDR R0, =DMA6_DriverIRQHandler + BX R0 + + PUBWEAK DMA7_IRQHandler + PUBWEAK DMA7_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA7_IRQHandler + LDR R0, =DMA7_DriverIRQHandler + BX R0 + + PUBWEAK DMA8_IRQHandler + PUBWEAK DMA8_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA8_IRQHandler + LDR R0, =DMA8_DriverIRQHandler + BX R0 + + PUBWEAK DMA9_IRQHandler + PUBWEAK DMA9_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA9_IRQHandler + LDR R0, =DMA9_DriverIRQHandler + BX R0 + + PUBWEAK DMA10_IRQHandler + PUBWEAK DMA10_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA10_IRQHandler + LDR R0, =DMA10_DriverIRQHandler + BX R0 + + PUBWEAK DMA11_IRQHandler + PUBWEAK DMA11_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA11_IRQHandler + LDR R0, =DMA11_DriverIRQHandler + BX R0 + + PUBWEAK DMA12_IRQHandler + PUBWEAK DMA12_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA12_IRQHandler + LDR R0, =DMA12_DriverIRQHandler + BX R0 + + PUBWEAK DMA13_IRQHandler + PUBWEAK DMA13_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA13_IRQHandler + LDR R0, =DMA13_DriverIRQHandler + BX R0 + + PUBWEAK DMA14_IRQHandler + PUBWEAK DMA14_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA14_IRQHandler + LDR R0, =DMA14_DriverIRQHandler + BX R0 + + PUBWEAK DMA15_IRQHandler + PUBWEAK DMA15_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA15_IRQHandler + LDR R0, =DMA15_DriverIRQHandler + BX R0 + + PUBWEAK DMA_Error_IRQHandler + PUBWEAK DMA_Error_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA_Error_IRQHandler + LDR R0, =DMA_Error_DriverIRQHandler + BX R0 + + PUBWEAK MCM_IRQHandler + PUBWEAK FTFL_IRQHandler + PUBWEAK FTFL_Collision_IRQHandler + PUBWEAK PMC_IRQHandler + PUBWEAK LLWU_IRQHandler + PUBWEAK WDOG_EWM_IRQHandler + PUBWEAK RNG_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK I2C0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +I2C0_IRQHandler + LDR R0, =I2C0_DriverIRQHandler + BX R0 + + PUBWEAK I2C1_IRQHandler + PUBWEAK I2C1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +I2C1_IRQHandler + LDR R0, =I2C1_DriverIRQHandler + BX R0 + + PUBWEAK SPI0_IRQHandler + PUBWEAK SPI0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SPI0_IRQHandler + LDR R0, =SPI0_DriverIRQHandler + BX R0 + + PUBWEAK SPI1_IRQHandler + PUBWEAK SPI1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SPI1_IRQHandler + LDR R0, =SPI1_DriverIRQHandler + BX R0 + + PUBWEAK I2S0_Tx_IRQHandler + PUBWEAK I2S0_Tx_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +I2S0_Tx_IRQHandler + LDR R0, =I2S0_Tx_DriverIRQHandler + BX R0 + + PUBWEAK I2S0_Rx_IRQHandler + PUBWEAK I2S0_Rx_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +I2S0_Rx_IRQHandler + LDR R0, =I2S0_Rx_DriverIRQHandler + BX R0 + + PUBWEAK Reserved46_IRQHandler + PUBWEAK UART0_RX_TX_IRQHandler + PUBWEAK UART0_RX_TX_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UART0_RX_TX_IRQHandler + LDR R0, =UART0_RX_TX_DriverIRQHandler + BX R0 + + PUBWEAK UART0_ERR_IRQHandler + PUBWEAK UART0_ERR_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UART0_ERR_IRQHandler + LDR R0, =UART0_ERR_DriverIRQHandler + BX R0 + + PUBWEAK UART1_RX_TX_IRQHandler + PUBWEAK UART1_RX_TX_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UART1_RX_TX_IRQHandler + LDR R0, =UART1_RX_TX_DriverIRQHandler + BX R0 + + PUBWEAK UART1_ERR_IRQHandler + PUBWEAK UART1_ERR_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UART1_ERR_IRQHandler + LDR R0, =UART1_ERR_DriverIRQHandler + BX R0 + + PUBWEAK UART2_RX_TX_IRQHandler + PUBWEAK UART2_RX_TX_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UART2_RX_TX_IRQHandler + LDR R0, =UART2_RX_TX_DriverIRQHandler + BX R0 + + PUBWEAK UART2_ERR_IRQHandler + PUBWEAK UART2_ERR_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UART2_ERR_IRQHandler + LDR R0, =UART2_ERR_DriverIRQHandler + BX R0 + + PUBWEAK Reserved53_IRQHandler + PUBWEAK Reserved54_IRQHandler + PUBWEAK ADC0_IRQHandler + PUBWEAK CMP0_IRQHandler + PUBWEAK CMP1_IRQHandler + PUBWEAK FTM0_IRQHandler + PUBWEAK FTM1_IRQHandler + PUBWEAK FTM2_IRQHandler + PUBWEAK CMT_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK RTC_Seconds_IRQHandler + PUBWEAK PIT0_IRQHandler + PUBWEAK PIT1_IRQHandler + PUBWEAK PIT2_IRQHandler + PUBWEAK PIT3_IRQHandler + PUBWEAK PDB0_IRQHandler + PUBWEAK USB0_IRQHandler + PUBWEAK USBDCD_IRQHandler + PUBWEAK Reserved71_IRQHandler + PUBWEAK Reserved72_IRQHandler + PUBWEAK MCG_IRQHandler + PUBWEAK LPTMR0_IRQHandler + PUBWEAK PORTA_IRQHandler + PUBWEAK PORTB_IRQHandler + PUBWEAK PORTC_IRQHandler + PUBWEAK PORTD_IRQHandler + PUBWEAK PORTE_IRQHandler + PUBWEAK SWI_IRQHandler + PUBWEAK DefaultISR + SECTION .text:CODE:REORDER:NOROOT(1) +DMA0_DriverIRQHandler +DMA1_DriverIRQHandler +DMA2_DriverIRQHandler +DMA3_DriverIRQHandler +DMA4_DriverIRQHandler +DMA5_DriverIRQHandler +DMA6_DriverIRQHandler +DMA7_DriverIRQHandler +DMA8_DriverIRQHandler +DMA9_DriverIRQHandler +DMA10_DriverIRQHandler +DMA11_DriverIRQHandler +DMA12_DriverIRQHandler +DMA13_DriverIRQHandler +DMA14_DriverIRQHandler +DMA15_DriverIRQHandler +DMA_Error_DriverIRQHandler +MCM_IRQHandler +FTFL_IRQHandler +FTFL_Collision_IRQHandler +PMC_IRQHandler +LLWU_IRQHandler +WDOG_EWM_IRQHandler +RNG_IRQHandler +I2C0_DriverIRQHandler +I2C1_DriverIRQHandler +SPI0_DriverIRQHandler +SPI1_DriverIRQHandler +I2S0_Tx_DriverIRQHandler +I2S0_Rx_DriverIRQHandler +Reserved46_IRQHandler +UART0_RX_TX_DriverIRQHandler +UART0_ERR_DriverIRQHandler +UART1_RX_TX_DriverIRQHandler +UART1_ERR_DriverIRQHandler +UART2_RX_TX_DriverIRQHandler +UART2_ERR_DriverIRQHandler +Reserved53_IRQHandler +Reserved54_IRQHandler +ADC0_IRQHandler +CMP0_IRQHandler +CMP1_IRQHandler +FTM0_IRQHandler +FTM1_IRQHandler +FTM2_IRQHandler +CMT_IRQHandler +RTC_IRQHandler +RTC_Seconds_IRQHandler +PIT0_IRQHandler +PIT1_IRQHandler +PIT2_IRQHandler +PIT3_IRQHandler +PDB0_IRQHandler +USB0_IRQHandler +USBDCD_IRQHandler +Reserved71_IRQHandler +Reserved72_IRQHandler +MCG_IRQHandler +LPTMR0_IRQHandler +PORTA_IRQHandler +PORTB_IRQHandler +PORTC_IRQHandler +PORTD_IRQHandler +PORTE_IRQHandler +SWI_IRQHandler +DefaultISR + B DefaultISR + + END
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/device/TOOLCHAIN_IAR/startup_MKW24D5.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,718 +0,0 @@ -; --------------------------------------------------------------------------------------- -; @file: startup_MKW24D5.s -; @purpose: CMSIS Cortex-M4 Core Device Startup File -; MKW24D5 -; @version: 2.0 -; @date: 2014-11-26 -; @build: b160512 -; --------------------------------------------------------------------------------------- -; -; Copyright (c) 1997 - 2016 , Freescale Semiconductor, Inc. -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without modification, -; are permitted provided that the following conditions are met: -; -; o Redistributions of source code must retain the above copyright notice, this list -; of conditions and the following disclaimer. -; -; o Redistributions in binary form must reproduce the above copyright notice, this -; list of conditions and the following disclaimer in the documentation and/or -; other materials provided with the distribution. -; -; o Neither the name of Freescale Semiconductor, Inc. nor the names of its -; contributors may be used to endorse or promote products derived from this -; software without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler ;NMI Handler - DCD HardFault_Handler ;Hard Fault Handler - DCD MemManage_Handler ;MPU Fault Handler - DCD BusFault_Handler ;Bus Fault Handler - DCD UsageFault_Handler ;Usage Fault Handler -__vector_table_0x1c - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD SVC_Handler ;SVCall Handler - DCD DebugMon_Handler ;Debug Monitor Handler - DCD 0 ;Reserved - DCD PendSV_Handler ;PendSV Handler - DCD SysTick_Handler ;SysTick Handler - - ;External Interrupts - DCD DMA0_IRQHandler ;DMA channel 0 transfer complete - DCD DMA1_IRQHandler ;DMA channel 1 transfer complete - DCD DMA2_IRQHandler ;DMA channel 2 transfer complete - DCD DMA3_IRQHandler ;DMA channel 3 transfer complete - DCD DMA4_IRQHandler ;DMA channel 4 transfer complete - DCD DMA5_IRQHandler ;DMA channel 5 transfer complete - DCD DMA6_IRQHandler ;DMA channel 6 transfer complete - DCD DMA7_IRQHandler ;DMA channel 7 transfer complete - DCD DMA8_IRQHandler ;DMA channel 8 transfer complete - DCD DMA9_IRQHandler ;DMA channel 9 transfer complete - DCD DMA10_IRQHandler ;DMA channel 10 transfer complete - DCD DMA11_IRQHandler ;DMA channel 11 transfer complete - DCD DMA12_IRQHandler ;DMA channel 12 transfer complete - DCD DMA13_IRQHandler ;DMA channel 13 transfer complete - DCD DMA14_IRQHandler ;DMA channel 14 transfer complete - DCD DMA15_IRQHandler ;DMA channel 15 transfer complete - DCD DMA_Error_IRQHandler ;DMA channel 0 - 15 error - DCD MCM_IRQHandler ;MCM normal interrupt - DCD FTFL_IRQHandler ;FTFL command complete - DCD FTFL_Collision_IRQHandler ;FTFL read collision - DCD PMC_IRQHandler ;PMC controller low-voltage detect, low-voltage warning - DCD LLWU_IRQHandler ;Low leakage wakeup - DCD WDOG_EWM_IRQHandler ;Single interrupt vector for WDOG and EWM - DCD RNG_IRQHandler ;Randon number generator - DCD I2C0_IRQHandler ;Inter-integrated circuit 0 - DCD I2C1_IRQHandler ;Inter-integrated circuit 1 - DCD SPI0_IRQHandler ;Serial peripheral Interface 0 - DCD SPI1_IRQHandler ;Serial peripheral Interface 1 - DCD I2S0_Tx_IRQHandler ;Integrated interchip sound 0 transmit interrupt - DCD I2S0_Rx_IRQHandler ;Integrated interchip sound 0 receive interrupt - DCD Reserved46_IRQHandler ;Reserved interrupt - DCD UART0_RX_TX_IRQHandler ;UART0 receive/transmit interrupt - DCD UART0_ERR_IRQHandler ;UART0 error interrupt - DCD UART1_RX_TX_IRQHandler ;UART1 receive/transmit interrupt - DCD UART1_ERR_IRQHandler ;UART1 error interrupt - DCD UART2_RX_TX_IRQHandler ;UART2 receive/transmit interrupt - DCD UART2_ERR_IRQHandler ;UART2 error interrupt - DCD Reserved53_IRQHandler ;Reserved interrupt - DCD Reserved54_IRQHandler ;Reserved interrupt - DCD ADC0_IRQHandler ;Analog-to-digital converter 0 - DCD CMP0_IRQHandler ;Comparator 0 - DCD CMP1_IRQHandler ;Comparator 1 - DCD FTM0_IRQHandler ;FlexTimer module 0 fault, overflow and channels interrupt - DCD FTM1_IRQHandler ;FlexTimer module 1 fault, overflow and channels interrupt - DCD FTM2_IRQHandler ;FlexTimer module 2 fault, overflow and channels interrupt - DCD CMT_IRQHandler ;Carrier modulator transmitter - DCD RTC_IRQHandler ;Real time clock - DCD RTC_Seconds_IRQHandler ;Real time clock seconds - DCD PIT0_IRQHandler ;Periodic interrupt timer channel 0 - DCD PIT1_IRQHandler ;Periodic interrupt timer channel 1 - DCD PIT2_IRQHandler ;Periodic interrupt timer channel 2 - DCD PIT3_IRQHandler ;Periodic interrupt timer channel 3 - DCD PDB0_IRQHandler ;Programmable delay block - DCD USB0_IRQHandler ;USB OTG interrupt - DCD USBDCD_IRQHandler ;USB charger detect - DCD Reserved71_IRQHandler ;Reserved interrupt - DCD Reserved72_IRQHandler ;Reserved interrupt - DCD MCG_IRQHandler ;Multipurpose clock generator - DCD LPTMR0_IRQHandler ;Low power timer interrupt - DCD PORTA_IRQHandler ;Port A pin detect interrupt - DCD PORTB_IRQHandler ;Port B pin detect interrupt - DCD PORTC_IRQHandler ;Port C pin detect interrupt - DCD PORTD_IRQHandler ;Port D pin detect interrupt - DCD PORTE_IRQHandler ;Port E pin detect interrupt - DCD SWI_IRQHandler ;Software interrupt - DCD DefaultISR ;81 - DCD DefaultISR ;82 - DCD DefaultISR ;83 - DCD DefaultISR ;84 - DCD DefaultISR ;85 - DCD DefaultISR ;86 - DCD DefaultISR ;87 - DCD DefaultISR ;88 - DCD DefaultISR ;89 - DCD DefaultISR ;90 - DCD DefaultISR ;91 - DCD DefaultISR ;92 - DCD DefaultISR ;93 - DCD DefaultISR ;94 - DCD DefaultISR ;95 - DCD DefaultISR ;96 - DCD DefaultISR ;97 - DCD DefaultISR ;98 - DCD DefaultISR ;99 - DCD DefaultISR ;100 - DCD DefaultISR ;101 - DCD DefaultISR ;102 - DCD DefaultISR ;103 - DCD DefaultISR ;104 - DCD DefaultISR ;105 - DCD DefaultISR ;106 - DCD DefaultISR ;107 - DCD DefaultISR ;108 - DCD DefaultISR ;109 - DCD DefaultISR ;110 - DCD DefaultISR ;111 - DCD DefaultISR ;112 - DCD DefaultISR ;113 - DCD DefaultISR ;114 - DCD DefaultISR ;115 - DCD DefaultISR ;116 - DCD DefaultISR ;117 - DCD DefaultISR ;118 - DCD DefaultISR ;119 - DCD DefaultISR ;120 - DCD DefaultISR ;121 - DCD DefaultISR ;122 - DCD DefaultISR ;123 - DCD DefaultISR ;124 - DCD DefaultISR ;125 - DCD DefaultISR ;126 - DCD DefaultISR ;127 - DCD DefaultISR ;128 - DCD DefaultISR ;129 - DCD DefaultISR ;130 - DCD DefaultISR ;131 - DCD DefaultISR ;132 - DCD DefaultISR ;133 - DCD DefaultISR ;134 - DCD DefaultISR ;135 - DCD DefaultISR ;136 - DCD DefaultISR ;137 - DCD DefaultISR ;138 - DCD DefaultISR ;139 - DCD DefaultISR ;140 - DCD DefaultISR ;141 - DCD DefaultISR ;142 - DCD DefaultISR ;143 - DCD DefaultISR ;144 - DCD DefaultISR ;145 - DCD DefaultISR ;146 - DCD DefaultISR ;147 - DCD DefaultISR ;148 - DCD DefaultISR ;149 - DCD DefaultISR ;150 - DCD DefaultISR ;151 - DCD DefaultISR ;152 - DCD DefaultISR ;153 - DCD DefaultISR ;154 - DCD DefaultISR ;155 - DCD DefaultISR ;156 - DCD DefaultISR ;157 - DCD DefaultISR ;158 - DCD DefaultISR ;159 - DCD DefaultISR ;160 - DCD DefaultISR ;161 - DCD DefaultISR ;162 - DCD DefaultISR ;163 - DCD DefaultISR ;164 - DCD DefaultISR ;165 - DCD DefaultISR ;166 - DCD DefaultISR ;167 - DCD DefaultISR ;168 - DCD DefaultISR ;169 - DCD DefaultISR ;170 - DCD DefaultISR ;171 - DCD DefaultISR ;172 - DCD DefaultISR ;173 - DCD DefaultISR ;174 - DCD DefaultISR ;175 - DCD DefaultISR ;176 - DCD DefaultISR ;177 - DCD DefaultISR ;178 - DCD DefaultISR ;179 - DCD DefaultISR ;180 - DCD DefaultISR ;181 - DCD DefaultISR ;182 - DCD DefaultISR ;183 - DCD DefaultISR ;184 - DCD DefaultISR ;185 - DCD DefaultISR ;186 - DCD DefaultISR ;187 - DCD DefaultISR ;188 - DCD DefaultISR ;189 - DCD DefaultISR ;190 - DCD DefaultISR ;191 - DCD DefaultISR ;192 - DCD DefaultISR ;193 - DCD DefaultISR ;194 - DCD DefaultISR ;195 - DCD DefaultISR ;196 - DCD DefaultISR ;197 - DCD DefaultISR ;198 - DCD DefaultISR ;199 - DCD DefaultISR ;200 - DCD DefaultISR ;201 - DCD DefaultISR ;202 - DCD DefaultISR ;203 - DCD DefaultISR ;204 - DCD DefaultISR ;205 - DCD DefaultISR ;206 - DCD DefaultISR ;207 - DCD DefaultISR ;208 - DCD DefaultISR ;209 - DCD DefaultISR ;210 - DCD DefaultISR ;211 - DCD DefaultISR ;212 - DCD DefaultISR ;213 - DCD DefaultISR ;214 - DCD DefaultISR ;215 - DCD DefaultISR ;216 - DCD DefaultISR ;217 - DCD DefaultISR ;218 - DCD DefaultISR ;219 - DCD DefaultISR ;220 - DCD DefaultISR ;221 - DCD DefaultISR ;222 - DCD DefaultISR ;223 - DCD DefaultISR ;224 - DCD DefaultISR ;225 - DCD DefaultISR ;226 - DCD DefaultISR ;227 - DCD DefaultISR ;228 - DCD DefaultISR ;229 - DCD DefaultISR ;230 - DCD DefaultISR ;231 - DCD DefaultISR ;232 - DCD DefaultISR ;233 - DCD DefaultISR ;234 - DCD DefaultISR ;235 - DCD DefaultISR ;236 - DCD DefaultISR ;237 - DCD DefaultISR ;238 - DCD DefaultISR ;239 - DCD DefaultISR ;240 - DCD DefaultISR ;241 - DCD DefaultISR ;242 - DCD DefaultISR ;243 - DCD DefaultISR ;244 - DCD DefaultISR ;245 - DCD DefaultISR ;246 - DCD DefaultISR ;247 - DCD DefaultISR ;248 - DCD DefaultISR ;249 - DCD DefaultISR ;250 - DCD DefaultISR ;251 - DCD DefaultISR ;252 - DCD DefaultISR ;253 - DCD DefaultISR ;254 - DCD 0xFFFFFFFF ; Reserved for user TRIM value -__Vectors_End - - SECTION FlashConfig:CODE -__FlashConfig - DCD 0xFFFFFFFF - DCD 0xFFFFFFFF - DCD 0xFFFFFFFF - DCD 0xFFFFFFFE -__FlashConfig_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - CPSID I ; Mask interrupts - LDR R0, =0xE000ED08 - LDR R1, =__vector_table - STR R1, [R0] - LDR R0, =SystemInit - BLX R0 - CPSIE I ; Unmask interrupts - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B . - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B . - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B . - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B . - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B . - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B . - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B . - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B . - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B . - - PUBWEAK DMA0_IRQHandler - PUBWEAK DMA0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA0_IRQHandler - LDR R0, =DMA0_DriverIRQHandler - BX R0 - - PUBWEAK DMA1_IRQHandler - PUBWEAK DMA1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA1_IRQHandler - LDR R0, =DMA1_DriverIRQHandler - BX R0 - - PUBWEAK DMA2_IRQHandler - PUBWEAK DMA2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA2_IRQHandler - LDR R0, =DMA2_DriverIRQHandler - BX R0 - - PUBWEAK DMA3_IRQHandler - PUBWEAK DMA3_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA3_IRQHandler - LDR R0, =DMA3_DriverIRQHandler - BX R0 - - PUBWEAK DMA4_IRQHandler - PUBWEAK DMA4_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA4_IRQHandler - LDR R0, =DMA4_DriverIRQHandler - BX R0 - - PUBWEAK DMA5_IRQHandler - PUBWEAK DMA5_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA5_IRQHandler - LDR R0, =DMA5_DriverIRQHandler - BX R0 - - PUBWEAK DMA6_IRQHandler - PUBWEAK DMA6_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA6_IRQHandler - LDR R0, =DMA6_DriverIRQHandler - BX R0 - - PUBWEAK DMA7_IRQHandler - PUBWEAK DMA7_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA7_IRQHandler - LDR R0, =DMA7_DriverIRQHandler - BX R0 - - PUBWEAK DMA8_IRQHandler - PUBWEAK DMA8_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA8_IRQHandler - LDR R0, =DMA8_DriverIRQHandler - BX R0 - - PUBWEAK DMA9_IRQHandler - PUBWEAK DMA9_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA9_IRQHandler - LDR R0, =DMA9_DriverIRQHandler - BX R0 - - PUBWEAK DMA10_IRQHandler - PUBWEAK DMA10_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA10_IRQHandler - LDR R0, =DMA10_DriverIRQHandler - BX R0 - - PUBWEAK DMA11_IRQHandler - PUBWEAK DMA11_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA11_IRQHandler - LDR R0, =DMA11_DriverIRQHandler - BX R0 - - PUBWEAK DMA12_IRQHandler - PUBWEAK DMA12_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA12_IRQHandler - LDR R0, =DMA12_DriverIRQHandler - BX R0 - - PUBWEAK DMA13_IRQHandler - PUBWEAK DMA13_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA13_IRQHandler - LDR R0, =DMA13_DriverIRQHandler - BX R0 - - PUBWEAK DMA14_IRQHandler - PUBWEAK DMA14_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA14_IRQHandler - LDR R0, =DMA14_DriverIRQHandler - BX R0 - - PUBWEAK DMA15_IRQHandler - PUBWEAK DMA15_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA15_IRQHandler - LDR R0, =DMA15_DriverIRQHandler - BX R0 - - PUBWEAK DMA_Error_IRQHandler - PUBWEAK DMA_Error_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA_Error_IRQHandler - LDR R0, =DMA_Error_DriverIRQHandler - BX R0 - - PUBWEAK MCM_IRQHandler - PUBWEAK FTFL_IRQHandler - PUBWEAK FTFL_Collision_IRQHandler - PUBWEAK PMC_IRQHandler - PUBWEAK LLWU_IRQHandler - PUBWEAK WDOG_EWM_IRQHandler - PUBWEAK RNG_IRQHandler - PUBWEAK I2C0_IRQHandler - PUBWEAK I2C0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -I2C0_IRQHandler - LDR R0, =I2C0_DriverIRQHandler - BX R0 - - PUBWEAK I2C1_IRQHandler - PUBWEAK I2C1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -I2C1_IRQHandler - LDR R0, =I2C1_DriverIRQHandler - BX R0 - - PUBWEAK SPI0_IRQHandler - PUBWEAK SPI0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SPI0_IRQHandler - LDR R0, =SPI0_DriverIRQHandler - BX R0 - - PUBWEAK SPI1_IRQHandler - PUBWEAK SPI1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SPI1_IRQHandler - LDR R0, =SPI1_DriverIRQHandler - BX R0 - - PUBWEAK I2S0_Tx_IRQHandler - PUBWEAK I2S0_Tx_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -I2S0_Tx_IRQHandler - LDR R0, =I2S0_Tx_DriverIRQHandler - BX R0 - - PUBWEAK I2S0_Rx_IRQHandler - PUBWEAK I2S0_Rx_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -I2S0_Rx_IRQHandler - LDR R0, =I2S0_Rx_DriverIRQHandler - BX R0 - - PUBWEAK Reserved46_IRQHandler - PUBWEAK UART0_RX_TX_IRQHandler - PUBWEAK UART0_RX_TX_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -UART0_RX_TX_IRQHandler - LDR R0, =UART0_RX_TX_DriverIRQHandler - BX R0 - - PUBWEAK UART0_ERR_IRQHandler - PUBWEAK UART0_ERR_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -UART0_ERR_IRQHandler - LDR R0, =UART0_ERR_DriverIRQHandler - BX R0 - - PUBWEAK UART1_RX_TX_IRQHandler - PUBWEAK UART1_RX_TX_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -UART1_RX_TX_IRQHandler - LDR R0, =UART1_RX_TX_DriverIRQHandler - BX R0 - - PUBWEAK UART1_ERR_IRQHandler - PUBWEAK UART1_ERR_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -UART1_ERR_IRQHandler - LDR R0, =UART1_ERR_DriverIRQHandler - BX R0 - - PUBWEAK UART2_RX_TX_IRQHandler - PUBWEAK UART2_RX_TX_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -UART2_RX_TX_IRQHandler - LDR R0, =UART2_RX_TX_DriverIRQHandler - BX R0 - - PUBWEAK UART2_ERR_IRQHandler - PUBWEAK UART2_ERR_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -UART2_ERR_IRQHandler - LDR R0, =UART2_ERR_DriverIRQHandler - BX R0 - - PUBWEAK Reserved53_IRQHandler - PUBWEAK Reserved54_IRQHandler - PUBWEAK ADC0_IRQHandler - PUBWEAK CMP0_IRQHandler - PUBWEAK CMP1_IRQHandler - PUBWEAK FTM0_IRQHandler - PUBWEAK FTM1_IRQHandler - PUBWEAK FTM2_IRQHandler - PUBWEAK CMT_IRQHandler - PUBWEAK RTC_IRQHandler - PUBWEAK RTC_Seconds_IRQHandler - PUBWEAK PIT0_IRQHandler - PUBWEAK PIT1_IRQHandler - PUBWEAK PIT2_IRQHandler - PUBWEAK PIT3_IRQHandler - PUBWEAK PDB0_IRQHandler - PUBWEAK USB0_IRQHandler - PUBWEAK USBDCD_IRQHandler - PUBWEAK Reserved71_IRQHandler - PUBWEAK Reserved72_IRQHandler - PUBWEAK MCG_IRQHandler - PUBWEAK LPTMR0_IRQHandler - PUBWEAK PORTA_IRQHandler - PUBWEAK PORTB_IRQHandler - PUBWEAK PORTC_IRQHandler - PUBWEAK PORTD_IRQHandler - PUBWEAK PORTE_IRQHandler - PUBWEAK SWI_IRQHandler - PUBWEAK DefaultISR - SECTION .text:CODE:REORDER:NOROOT(1) -DMA0_DriverIRQHandler -DMA1_DriverIRQHandler -DMA2_DriverIRQHandler -DMA3_DriverIRQHandler -DMA4_DriverIRQHandler -DMA5_DriverIRQHandler -DMA6_DriverIRQHandler -DMA7_DriverIRQHandler -DMA8_DriverIRQHandler -DMA9_DriverIRQHandler -DMA10_DriverIRQHandler -DMA11_DriverIRQHandler -DMA12_DriverIRQHandler -DMA13_DriverIRQHandler -DMA14_DriverIRQHandler -DMA15_DriverIRQHandler -DMA_Error_DriverIRQHandler -MCM_IRQHandler -FTFL_IRQHandler -FTFL_Collision_IRQHandler -PMC_IRQHandler -LLWU_IRQHandler -WDOG_EWM_IRQHandler -RNG_IRQHandler -I2C0_DriverIRQHandler -I2C1_DriverIRQHandler -SPI0_DriverIRQHandler -SPI1_DriverIRQHandler -I2S0_Tx_DriverIRQHandler -I2S0_Rx_DriverIRQHandler -Reserved46_IRQHandler -UART0_RX_TX_DriverIRQHandler -UART0_ERR_DriverIRQHandler -UART1_RX_TX_DriverIRQHandler -UART1_ERR_DriverIRQHandler -UART2_RX_TX_DriverIRQHandler -UART2_ERR_DriverIRQHandler -Reserved53_IRQHandler -Reserved54_IRQHandler -ADC0_IRQHandler -CMP0_IRQHandler -CMP1_IRQHandler -FTM0_IRQHandler -FTM1_IRQHandler -FTM2_IRQHandler -CMT_IRQHandler -RTC_IRQHandler -RTC_Seconds_IRQHandler -PIT0_IRQHandler -PIT1_IRQHandler -PIT2_IRQHandler -PIT3_IRQHandler -PDB0_IRQHandler -USB0_IRQHandler -USBDCD_IRQHandler -Reserved71_IRQHandler -Reserved72_IRQHandler -MCG_IRQHandler -LPTMR0_IRQHandler -PORTA_IRQHandler -PORTB_IRQHandler -PORTC_IRQHandler -PORTD_IRQHandler -PORTE_IRQHandler -SWI_IRQHandler -DefaultISR - B DefaultISR - - END
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/us_ticker.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW24D/us_ticker.c Tue Mar 20 16:56:18 2018 +0000
@@ -83,10 +83,14 @@
void us_ticker_set_interrupt(timestamp_t timestamp)
{
- uint32_t delta = timestamp - us_ticker_read();
+ uint32_t now_us, delta_us;
+
+ now_us = us_ticker_read();
+ delta_us = timestamp >= now_us ? timestamp - now_us : (uint32_t)((uint64_t)timestamp + 0xFFFFFFFF - now_us);
+
PIT_StopTimer(PIT, kPIT_Chnl_3);
PIT_StopTimer(PIT, kPIT_Chnl_2);
- PIT_SetTimerPeriod(PIT, kPIT_Chnl_3, (uint32_t)delta);
+ PIT_SetTimerPeriod(PIT, kPIT_Chnl_3, (uint32_t)delta_us);
PIT_EnableInterrupts(PIT, kPIT_Chnl_3, kPIT_TimerInterruptEnable);
PIT_StartTimer(PIT, kPIT_Chnl_3);
PIT_StartTimer(PIT, kPIT_Chnl_2);
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/device/TOOLCHAIN_IAR/startup_MKW41Z4.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,305 @@ +; --------------------------------------------------------------------------------------- +; @file: startup_MKW41Z4.s +; @purpose: CMSIS Cortex-M0P Core Device Startup File +; MKW41Z4 +; @version: 1.0 +; @date: 2015-9-23 +; @build: b160720 +; --------------------------------------------------------------------------------------- +; +; Copyright (c) 1997 - 2016 , Freescale Semiconductor, Inc. +; All rights reserved. +; +; Redistribution and use in source and binary forms, with or without modification, +; are permitted provided that the following conditions are met: +; +; o Redistributions of source code must retain the above copyright notice, this list +; of conditions and the following disclaimer. +; +; o Redistributions in binary form must reproduce the above copyright notice, this +; list of conditions and the following disclaimer in the documentation and/or +; other materials provided with the distribution. +; +; o Neither the name of Freescale Semiconductor, Inc. nor the names of its +; contributors may be used to endorse or promote products derived from this +; software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler ;NMI Handler + DCD HardFault_Handler ;Hard Fault Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved +__vector_table_0x1c + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD SVC_Handler ;SVCall Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD PendSV_Handler ;PendSV Handler + DCD SysTick_Handler ;SysTick Handler + + ;External Interrupts + DCD DMA0_IRQHandler ;DMA channel 0 transfer complete + DCD DMA1_IRQHandler ;DMA channel 1 transfer complete + DCD DMA2_IRQHandler ;DMA channel 2 transfer complete + DCD DMA3_IRQHandler ;DMA channel 3 transfer complete + DCD Reserved20_IRQHandler ;Reserved interrupt + DCD FTFA_IRQHandler ;Command complete and read collision + DCD LVD_LVW_DCDC_IRQHandler ;Low-voltage detect, low-voltage warning, DCDC + DCD LLWU_IRQHandler ;Low leakage wakeup Unit + DCD I2C0_IRQHandler ;I2C0 interrupt + DCD I2C1_IRQHandler ;I2C1 interrupt + DCD SPI0_IRQHandler ;SPI0 single interrupt vector for all sources + DCD TSI0_IRQHandler ;TSI0 single interrupt vector for all sources + DCD LPUART0_IRQHandler ;LPUART0 status and error + DCD TRNG0_IRQHandler ;TRNG0 interrupt + DCD CMT_IRQHandler ;CMT interrupt + DCD ADC0_IRQHandler ;ADC0 interrupt + DCD CMP0_IRQHandler ;CMP0 interrupt + DCD TPM0_IRQHandler ;TPM0 single interrupt vector for all sources + DCD TPM1_IRQHandler ;TPM1 single interrupt vector for all sources + DCD TPM2_IRQHandler ;TPM2 single interrupt vector for all sources + DCD RTC_IRQHandler ;RTC alarm + DCD RTC_Seconds_IRQHandler ;RTC seconds + DCD PIT_IRQHandler ;PIT interrupt + DCD LTC0_IRQHandler ;LTC0 interrupt + DCD Radio_0_IRQHandler ;BTLE, ZIGBEE, ANT, GENFSK interrupt 0 + DCD DAC0_IRQHandler ;DAC0 interrupt + DCD Radio_1_IRQHandler ;BTLE, ZIGBEE, ANT, GENFSK interrupt 1 + DCD MCG_IRQHandler ;MCG interrupt + DCD LPTMR0_IRQHandler ;LPTMR0 interrupt + DCD SPI1_IRQHandler ;SPI1 single interrupt vector for all sources + DCD PORTA_IRQHandler ;PORTA Pin detect + DCD PORTB_PORTC_IRQHandler ;PORTB and PORTC Pin detect +__Vectors_End + + SECTION FlashConfig:CODE +__FlashConfig + DCD 0xFFFFFFFF + DCD 0xFFFFFFFF + DCD 0xFFFFFFFF + DCD 0xFFFFFFFE +__FlashConfig_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + CPSID I ; Mask interrupts + LDR R0, =0xE000ED08 + LDR R1, =__vector_table + STR R1, [R0] + LDR R0, =SystemInit + BLX R0 + CPSIE I ; Unmask interrupts + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + PUBWEAK DMA0_IRQHandler + PUBWEAK DMA0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA0_IRQHandler + LDR R0, =DMA0_DriverIRQHandler + BX R0 + + PUBWEAK DMA1_IRQHandler + PUBWEAK DMA1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA1_IRQHandler + LDR R0, =DMA1_DriverIRQHandler + BX R0 + + PUBWEAK DMA2_IRQHandler + PUBWEAK DMA2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA2_IRQHandler + LDR R0, =DMA2_DriverIRQHandler + BX R0 + + PUBWEAK DMA3_IRQHandler + PUBWEAK DMA3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA3_IRQHandler + LDR R0, =DMA3_DriverIRQHandler + BX R0 + + PUBWEAK Reserved20_IRQHandler + PUBWEAK FTFA_IRQHandler + PUBWEAK LVD_LVW_DCDC_IRQHandler + PUBWEAK LLWU_IRQHandler + PUBWEAK I2C0_IRQHandler + PUBWEAK I2C0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +I2C0_IRQHandler + LDR R0, =I2C0_DriverIRQHandler + BX R0 + + PUBWEAK I2C1_IRQHandler + PUBWEAK I2C1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +I2C1_IRQHandler + LDR R0, =I2C1_DriverIRQHandler + BX R0 + + PUBWEAK SPI0_IRQHandler + PUBWEAK SPI0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SPI0_IRQHandler + LDR R0, =SPI0_DriverIRQHandler + BX R0 + + PUBWEAK TSI0_IRQHandler + PUBWEAK LPUART0_IRQHandler + PUBWEAK LPUART0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LPUART0_IRQHandler + LDR R0, =LPUART0_DriverIRQHandler + BX R0 + + PUBWEAK TRNG0_IRQHandler + PUBWEAK CMT_IRQHandler + PUBWEAK ADC0_IRQHandler + PUBWEAK CMP0_IRQHandler + PUBWEAK TPM0_IRQHandler + PUBWEAK TPM1_IRQHandler + PUBWEAK TPM2_IRQHandler + PUBWEAK RTC_IRQHandler + PUBWEAK RTC_Seconds_IRQHandler + PUBWEAK PIT_IRQHandler + PUBWEAK LTC0_IRQHandler + PUBWEAK Radio_0_IRQHandler + PUBWEAK DAC0_IRQHandler + PUBWEAK Radio_1_IRQHandler + PUBWEAK MCG_IRQHandler + PUBWEAK LPTMR0_IRQHandler + PUBWEAK SPI1_IRQHandler + PUBWEAK SPI1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SPI1_IRQHandler + LDR R0, =SPI1_DriverIRQHandler + BX R0 + + PUBWEAK PORTA_IRQHandler + PUBWEAK PORTB_PORTC_IRQHandler + PUBWEAK DefaultISR + SECTION .text:CODE:REORDER:NOROOT(2) +DMA0_DriverIRQHandler +DMA1_DriverIRQHandler +DMA2_DriverIRQHandler +DMA3_DriverIRQHandler +Reserved20_IRQHandler +FTFA_IRQHandler +LVD_LVW_DCDC_IRQHandler +LLWU_IRQHandler +I2C0_DriverIRQHandler +I2C1_DriverIRQHandler +SPI0_DriverIRQHandler +TSI0_IRQHandler +LPUART0_DriverIRQHandler +TRNG0_IRQHandler +CMT_IRQHandler +ADC0_IRQHandler +CMP0_IRQHandler +TPM0_IRQHandler +TPM1_IRQHandler +TPM2_IRQHandler +RTC_IRQHandler +RTC_Seconds_IRQHandler +PIT_IRQHandler +LTC0_IRQHandler +Radio_0_IRQHandler +DAC0_IRQHandler +Radio_1_IRQHandler +MCG_IRQHandler +LPTMR0_IRQHandler +SPI1_DriverIRQHandler +PORTA_IRQHandler +PORTB_PORTC_IRQHandler +DefaultISR + LDR R0, =DefaultISR + BX R0 + + END
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/device/TOOLCHAIN_IAR/startup_MKW41Z4.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,305 +0,0 @@ -; --------------------------------------------------------------------------------------- -; @file: startup_MKW41Z4.s -; @purpose: CMSIS Cortex-M0P Core Device Startup File -; MKW41Z4 -; @version: 1.0 -; @date: 2015-9-23 -; @build: b160720 -; --------------------------------------------------------------------------------------- -; -; Copyright (c) 1997 - 2016 , Freescale Semiconductor, Inc. -; All rights reserved. -; -; Redistribution and use in source and binary forms, with or without modification, -; are permitted provided that the following conditions are met: -; -; o Redistributions of source code must retain the above copyright notice, this list -; of conditions and the following disclaimer. -; -; o Redistributions in binary form must reproduce the above copyright notice, this -; list of conditions and the following disclaimer in the documentation and/or -; other materials provided with the distribution. -; -; o Neither the name of Freescale Semiconductor, Inc. nor the names of its -; contributors may be used to endorse or promote products derived from this -; software without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler ;NMI Handler - DCD HardFault_Handler ;Hard Fault Handler - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved -__vector_table_0x1c - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD SVC_Handler ;SVCall Handler - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD PendSV_Handler ;PendSV Handler - DCD SysTick_Handler ;SysTick Handler - - ;External Interrupts - DCD DMA0_IRQHandler ;DMA channel 0 transfer complete - DCD DMA1_IRQHandler ;DMA channel 1 transfer complete - DCD DMA2_IRQHandler ;DMA channel 2 transfer complete - DCD DMA3_IRQHandler ;DMA channel 3 transfer complete - DCD Reserved20_IRQHandler ;Reserved interrupt - DCD FTFA_IRQHandler ;Command complete and read collision - DCD LVD_LVW_DCDC_IRQHandler ;Low-voltage detect, low-voltage warning, DCDC - DCD LLWU_IRQHandler ;Low leakage wakeup Unit - DCD I2C0_IRQHandler ;I2C0 interrupt - DCD I2C1_IRQHandler ;I2C1 interrupt - DCD SPI0_IRQHandler ;SPI0 single interrupt vector for all sources - DCD TSI0_IRQHandler ;TSI0 single interrupt vector for all sources - DCD LPUART0_IRQHandler ;LPUART0 status and error - DCD TRNG0_IRQHandler ;TRNG0 interrupt - DCD CMT_IRQHandler ;CMT interrupt - DCD ADC0_IRQHandler ;ADC0 interrupt - DCD CMP0_IRQHandler ;CMP0 interrupt - DCD TPM0_IRQHandler ;TPM0 single interrupt vector for all sources - DCD TPM1_IRQHandler ;TPM1 single interrupt vector for all sources - DCD TPM2_IRQHandler ;TPM2 single interrupt vector for all sources - DCD RTC_IRQHandler ;RTC alarm - DCD RTC_Seconds_IRQHandler ;RTC seconds - DCD PIT_IRQHandler ;PIT interrupt - DCD LTC0_IRQHandler ;LTC0 interrupt - DCD Radio_0_IRQHandler ;BTLE, ZIGBEE, ANT, GENFSK interrupt 0 - DCD DAC0_IRQHandler ;DAC0 interrupt - DCD Radio_1_IRQHandler ;BTLE, ZIGBEE, ANT, GENFSK interrupt 1 - DCD MCG_IRQHandler ;MCG interrupt - DCD LPTMR0_IRQHandler ;LPTMR0 interrupt - DCD SPI1_IRQHandler ;SPI1 single interrupt vector for all sources - DCD PORTA_IRQHandler ;PORTA Pin detect - DCD PORTB_PORTC_IRQHandler ;PORTB and PORTC Pin detect -__Vectors_End - - SECTION FlashConfig:CODE -__FlashConfig - DCD 0xFFFFFFFF - DCD 0xFFFFFFFF - DCD 0xFFFFFFFF - DCD 0xFFFFFFFE -__FlashConfig_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - CPSID I ; Mask interrupts - LDR R0, =0xE000ED08 - LDR R1, =__vector_table - STR R1, [R0] - LDR R0, =SystemInit - BLX R0 - CPSIE I ; Unmask interrupts - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B . - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B . - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B . - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B . - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B . - - PUBWEAK DMA0_IRQHandler - PUBWEAK DMA0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA0_IRQHandler - LDR R0, =DMA0_DriverIRQHandler - BX R0 - - PUBWEAK DMA1_IRQHandler - PUBWEAK DMA1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA1_IRQHandler - LDR R0, =DMA1_DriverIRQHandler - BX R0 - - PUBWEAK DMA2_IRQHandler - PUBWEAK DMA2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA2_IRQHandler - LDR R0, =DMA2_DriverIRQHandler - BX R0 - - PUBWEAK DMA3_IRQHandler - PUBWEAK DMA3_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA3_IRQHandler - LDR R0, =DMA3_DriverIRQHandler - BX R0 - - PUBWEAK Reserved20_IRQHandler - PUBWEAK FTFA_IRQHandler - PUBWEAK LVD_LVW_DCDC_IRQHandler - PUBWEAK LLWU_IRQHandler - PUBWEAK I2C0_IRQHandler - PUBWEAK I2C0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -I2C0_IRQHandler - LDR R0, =I2C0_DriverIRQHandler - BX R0 - - PUBWEAK I2C1_IRQHandler - PUBWEAK I2C1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -I2C1_IRQHandler - LDR R0, =I2C1_DriverIRQHandler - BX R0 - - PUBWEAK SPI0_IRQHandler - PUBWEAK SPI0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SPI0_IRQHandler - LDR R0, =SPI0_DriverIRQHandler - BX R0 - - PUBWEAK TSI0_IRQHandler - PUBWEAK LPUART0_IRQHandler - PUBWEAK LPUART0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -LPUART0_IRQHandler - LDR R0, =LPUART0_DriverIRQHandler - BX R0 - - PUBWEAK TRNG0_IRQHandler - PUBWEAK CMT_IRQHandler - PUBWEAK ADC0_IRQHandler - PUBWEAK CMP0_IRQHandler - PUBWEAK TPM0_IRQHandler - PUBWEAK TPM1_IRQHandler - PUBWEAK TPM2_IRQHandler - PUBWEAK RTC_IRQHandler - PUBWEAK RTC_Seconds_IRQHandler - PUBWEAK PIT_IRQHandler - PUBWEAK LTC0_IRQHandler - PUBWEAK Radio_0_IRQHandler - PUBWEAK DAC0_IRQHandler - PUBWEAK Radio_1_IRQHandler - PUBWEAK MCG_IRQHandler - PUBWEAK LPTMR0_IRQHandler - PUBWEAK SPI1_IRQHandler - PUBWEAK SPI1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SPI1_IRQHandler - LDR R0, =SPI1_DriverIRQHandler - BX R0 - - PUBWEAK PORTA_IRQHandler - PUBWEAK PORTB_PORTC_IRQHandler - PUBWEAK DefaultISR - SECTION .text:CODE:REORDER:NOROOT(2) -DMA0_DriverIRQHandler -DMA1_DriverIRQHandler -DMA2_DriverIRQHandler -DMA3_DriverIRQHandler -Reserved20_IRQHandler -FTFA_IRQHandler -LVD_LVW_DCDC_IRQHandler -LLWU_IRQHandler -I2C0_DriverIRQHandler -I2C1_DriverIRQHandler -SPI0_DriverIRQHandler -TSI0_IRQHandler -LPUART0_DriverIRQHandler -TRNG0_IRQHandler -CMT_IRQHandler -ADC0_IRQHandler -CMP0_IRQHandler -TPM0_IRQHandler -TPM1_IRQHandler -TPM2_IRQHandler -RTC_IRQHandler -RTC_Seconds_IRQHandler -PIT_IRQHandler -LTC0_IRQHandler -Radio_0_IRQHandler -DAC0_IRQHandler -Radio_1_IRQHandler -MCG_IRQHandler -LPTMR0_IRQHandler -SPI1_DriverIRQHandler -PORTA_IRQHandler -PORTB_PORTC_IRQHandler -DefaultISR - LDR R0, =DefaultISR - BX R0 - - END
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/us_ticker.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_KW41Z/us_ticker.c Tue Mar 20 16:56:18 2018 +0000
@@ -30,7 +30,7 @@
us_ticker_irq_handler();
}
-void us_ticker_init(void)
+void us_ticker_init(void)
{
if (us_ticker_inited) {
return;
@@ -69,7 +69,7 @@
}
-uint32_t us_ticker_read()
+uint32_t us_ticker_read()
{
if (!us_ticker_inited) {
us_ticker_init();
@@ -78,21 +78,25 @@
return ~(PIT_GetCurrentTimerCount(PIT, kPIT_Chnl_1));
}
-void us_ticker_disable_interrupt(void)
+void us_ticker_disable_interrupt(void)
{
LPTMR_DisableInterrupts(LPTMR0, kLPTMR_TimerInterruptEnable);
}
-void us_ticker_clear_interrupt(void)
+void us_ticker_clear_interrupt(void)
{
LPTMR_ClearStatusFlags(LPTMR0, kLPTMR_TimerCompareFlag);
}
-void us_ticker_set_interrupt(timestamp_t timestamp)
+void us_ticker_set_interrupt(timestamp_t timestamp)
{
- uint32_t delta = timestamp - us_ticker_read();
+ uint32_t now_us, delta_us;
+
+ now_us = us_ticker_read();
+ delta_us = timestamp >= now_us ? timestamp - now_us : (uint32_t)((uint64_t)timestamp + 0xFFFFFFFF - now_us);
+
LPTMR_StopTimer(LPTMR0);
- LPTMR_SetTimerPeriod(LPTMR0, (uint32_t)delta);
+ LPTMR_SetTimerPeriod(LPTMR0, (uint32_t)delta_us);
LPTMR_EnableInterrupts(LPTMR0, kLPTMR_TimerInterruptEnable);
LPTMR_StartTimer(LPTMR0);
}
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/us_ticker.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K22F/us_ticker.c Tue Mar 20 16:56:18 2018 +0000
@@ -83,10 +83,14 @@
void us_ticker_set_interrupt(timestamp_t timestamp)
{
- uint32_t delta = timestamp - us_ticker_read();
+ uint32_t now_us, delta_us;
+
+ now_us = us_ticker_read();
+ delta_us = timestamp >= now_us ? timestamp - now_us : (uint32_t)((uint64_t)timestamp + 0xFFFFFFFF - now_us);
+
PIT_StopTimer(PIT, kPIT_Chnl_3);
PIT_StopTimer(PIT, kPIT_Chnl_2);
- PIT_SetTimerPeriod(PIT, kPIT_Chnl_3, (uint32_t)delta);
+ PIT_SetTimerPeriod(PIT, kPIT_Chnl_3, (uint32_t)delta_us);
PIT_EnableInterrupts(PIT, kPIT_Chnl_3, kPIT_TimerInterruptEnable);
PIT_StartTimer(PIT, kPIT_Chnl_3);
PIT_StartTimer(PIT, kPIT_Chnl_2);
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/TOOLCHAIN_ARM_STD/startup_MK24F12.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,1023 @@ +; * --------------------------------------------------------------------------------------- +; * @file: startup_MK24F12.s +; * @purpose: CMSIS Cortex-M4 Core Device Startup File +; * MK24F12 +; * @version: 2.8 +; * @date: 2016-3-21 +; * @build: b160321 +; * --------------------------------------------------------------------------------------- +; * +; * Copyright (c) 1997 - 2016 , Freescale Semiconductor, Inc. +; * All rights reserved. +; * +; * Redistribution and use in source and binary forms, with or without modification, +; * are permitted provided that the following conditions are met: +; * +; * o Redistributions of source code must retain the above copyright notice, this list +; * of conditions and the following disclaimer. +; * +; * o Redistributions in binary form must reproduce the above copyright notice, this +; * list of conditions and the following disclaimer in the documentation and/or +; * other materials provided with the distribution. +; * +; * o Neither the name of Freescale Semiconductor, Inc. nor the names of its +; * contributors may be used to endorse or promote products derived from this +; * software without specific prior written permission. +; * +; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; * +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; *****************************************************************************/ + +__initial_sp EQU 0x20030000 ; Top of RAM + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ;NMI Handler + DCD HardFault_Handler ;Hard Fault Handler + DCD MemManage_Handler ;MPU Fault Handler + DCD BusFault_Handler ;Bus Fault Handler + DCD UsageFault_Handler ;Usage Fault Handler + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD 0 ;Reserved + DCD SVC_Handler ;SVCall Handler + DCD DebugMon_Handler ;Debug Monitor Handler + DCD 0 ;Reserved + DCD PendSV_Handler ;PendSV Handler + DCD SysTick_Handler ;SysTick Handler + + ;External Interrupts + DCD DMA0_IRQHandler ;DMA Channel 0 Transfer Complete + DCD DMA1_IRQHandler ;DMA Channel 1 Transfer Complete + DCD DMA2_IRQHandler ;DMA Channel 2 Transfer Complete + DCD DMA3_IRQHandler ;DMA Channel 3 Transfer Complete + DCD DMA4_IRQHandler ;DMA Channel 4 Transfer Complete + DCD DMA5_IRQHandler ;DMA Channel 5 Transfer Complete + DCD DMA6_IRQHandler ;DMA Channel 6 Transfer Complete + DCD DMA7_IRQHandler ;DMA Channel 7 Transfer Complete + DCD DMA8_IRQHandler ;DMA Channel 8 Transfer Complete + DCD DMA9_IRQHandler ;DMA Channel 9 Transfer Complete + DCD DMA10_IRQHandler ;DMA Channel 10 Transfer Complete + DCD DMA11_IRQHandler ;DMA Channel 11 Transfer Complete + DCD DMA12_IRQHandler ;DMA Channel 12 Transfer Complete + DCD DMA13_IRQHandler ;DMA Channel 13 Transfer Complete + DCD DMA14_IRQHandler ;DMA Channel 14 Transfer Complete + DCD DMA15_IRQHandler ;DMA Channel 15 Transfer Complete + DCD DMA_Error_IRQHandler ;DMA Error Interrupt + DCD MCM_IRQHandler ;Normal Interrupt + DCD FTFE_IRQHandler ;FTFE Command complete interrupt + DCD Read_Collision_IRQHandler ;Read Collision Interrupt + DCD LVD_LVW_IRQHandler ;Low Voltage Detect, Low Voltage Warning + DCD LLWU_IRQHandler ;Low Leakage Wakeup Unit + DCD WDOG_EWM_IRQHandler ;WDOG Interrupt + DCD RNG_IRQHandler ;RNG Interrupt + DCD I2C0_IRQHandler ;I2C0 interrupt + DCD I2C1_IRQHandler ;I2C1 interrupt + DCD SPI0_IRQHandler ;SPI0 Interrupt + DCD SPI1_IRQHandler ;SPI1 Interrupt + DCD I2S0_Tx_IRQHandler ;I2S0 transmit interrupt + DCD I2S0_Rx_IRQHandler ;I2S0 receive interrupt + DCD UART0_LON_IRQHandler ;UART0 LON interrupt + DCD UART0_RX_TX_IRQHandler ;UART0 Receive/Transmit interrupt + DCD UART0_ERR_IRQHandler ;UART0 Error interrupt + DCD UART1_RX_TX_IRQHandler ;UART1 Receive/Transmit interrupt + DCD UART1_ERR_IRQHandler ;UART1 Error interrupt + DCD UART2_RX_TX_IRQHandler ;UART2 Receive/Transmit interrupt + DCD UART2_ERR_IRQHandler ;UART2 Error interrupt + DCD UART3_RX_TX_IRQHandler ;UART3 Receive/Transmit interrupt + DCD UART3_ERR_IRQHandler ;UART3 Error interrupt + DCD ADC0_IRQHandler ;ADC0 interrupt + DCD CMP0_IRQHandler ;CMP0 interrupt + DCD CMP1_IRQHandler ;CMP1 interrupt + DCD FTM0_IRQHandler ;FTM0 fault, overflow and channels interrupt + DCD FTM1_IRQHandler ;FTM1 fault, overflow and channels interrupt + DCD FTM2_IRQHandler ;FTM2 fault, overflow and channels interrupt + DCD CMT_IRQHandler ;CMT interrupt + DCD RTC_IRQHandler ;RTC interrupt + DCD RTC_Seconds_IRQHandler ;RTC seconds interrupt + DCD PIT0_IRQHandler ;PIT timer channel 0 interrupt + DCD PIT1_IRQHandler ;PIT timer channel 1 interrupt + DCD PIT2_IRQHandler ;PIT timer channel 2 interrupt + DCD PIT3_IRQHandler ;PIT timer channel 3 interrupt + DCD PDB0_IRQHandler ;PDB0 Interrupt + DCD USB0_IRQHandler ;USB0 interrupt + DCD USBDCD_IRQHandler ;USBDCD Interrupt + DCD Reserved71_IRQHandler ;Reserved interrupt 71 + DCD DAC0_IRQHandler ;DAC0 interrupt + DCD MCG_IRQHandler ;MCG Interrupt + DCD LPTMR0_IRQHandler ;LPTimer interrupt + DCD PORTA_IRQHandler ;Port A interrupt + DCD PORTB_IRQHandler ;Port B interrupt + DCD PORTC_IRQHandler ;Port C interrupt + DCD PORTD_IRQHandler ;Port D interrupt + DCD PORTE_IRQHandler ;Port E interrupt + DCD SWI_IRQHandler ;Software interrupt + DCD SPI2_IRQHandler ;SPI2 Interrupt + DCD UART4_RX_TX_IRQHandler ;UART4 Receive/Transmit interrupt + DCD UART4_ERR_IRQHandler ;UART4 Error interrupt + DCD UART5_RX_TX_IRQHandler ;UART5 Receive/Transmit interrupt + DCD UART5_ERR_IRQHandler ;UART5 Error interrupt + DCD CMP2_IRQHandler ;CMP2 interrupt + DCD FTM3_IRQHandler ;FTM3 fault, overflow and channels interrupt + DCD DAC1_IRQHandler ;DAC1 interrupt + DCD ADC1_IRQHandler ;ADC1 interrupt + DCD I2C2_IRQHandler ;I2C2 interrupt + DCD CAN0_ORed_Message_buffer_IRQHandler ;CAN0 OR'd message buffers interrupt + DCD CAN0_Bus_Off_IRQHandler ;CAN0 bus off interrupt + DCD CAN0_Error_IRQHandler ;CAN0 error interrupt + DCD CAN0_Tx_Warning_IRQHandler ;CAN0 Tx warning interrupt + DCD CAN0_Rx_Warning_IRQHandler ;CAN0 Rx warning interrupt + DCD CAN0_Wake_Up_IRQHandler ;CAN0 wake up interrupt + DCD SDHC_IRQHandler ;SDHC interrupt + DCD Reserved98_IRQHandler ;Reserved interrupt 98 + DCD Reserved99_IRQHandler ;Reserved interrupt 99 + DCD Reserved100_IRQHandler ;Reserved interrupt 100 + DCD Reserved101_IRQHandler ;Reserved interrupt 101 + DCD DefaultISR ;102 + DCD DefaultISR ;103 + DCD DefaultISR ;104 + DCD DefaultISR ;105 + DCD DefaultISR ;106 + DCD DefaultISR ;107 + DCD DefaultISR ;108 + DCD DefaultISR ;109 + DCD DefaultISR ;110 + DCD DefaultISR ;111 + DCD DefaultISR ;112 + DCD DefaultISR ;113 + DCD DefaultISR ;114 + DCD DefaultISR ;115 + DCD DefaultISR ;116 + DCD DefaultISR ;117 + DCD DefaultISR ;118 + DCD DefaultISR ;119 + DCD DefaultISR ;120 + DCD DefaultISR ;121 + DCD DefaultISR ;122 + DCD DefaultISR ;123 + DCD DefaultISR ;124 + DCD DefaultISR ;125 + DCD DefaultISR ;126 + DCD DefaultISR ;127 + DCD DefaultISR ;128 + DCD DefaultISR ;129 + DCD DefaultISR ;130 + DCD DefaultISR ;131 + DCD DefaultISR ;132 + DCD DefaultISR ;133 + DCD DefaultISR ;134 + DCD DefaultISR ;135 + DCD DefaultISR ;136 + DCD DefaultISR ;137 + DCD DefaultISR ;138 + DCD DefaultISR ;139 + DCD DefaultISR ;140 + DCD DefaultISR ;141 + DCD DefaultISR ;142 + DCD DefaultISR ;143 + DCD DefaultISR ;144 + DCD DefaultISR ;145 + DCD DefaultISR ;146 + DCD DefaultISR ;147 + DCD DefaultISR ;148 + DCD DefaultISR ;149 + DCD DefaultISR ;150 + DCD DefaultISR ;151 + DCD DefaultISR ;152 + DCD DefaultISR ;153 + DCD DefaultISR ;154 + DCD DefaultISR ;155 + DCD DefaultISR ;156 + DCD DefaultISR ;157 + DCD DefaultISR ;158 + DCD DefaultISR ;159 + DCD DefaultISR ;160 + DCD DefaultISR ;161 + DCD DefaultISR ;162 + DCD DefaultISR ;163 + DCD DefaultISR ;164 + DCD DefaultISR ;165 + DCD DefaultISR ;166 + DCD DefaultISR ;167 + DCD DefaultISR ;168 + DCD DefaultISR ;169 + DCD DefaultISR ;170 + DCD DefaultISR ;171 + DCD DefaultISR ;172 + DCD DefaultISR ;173 + DCD DefaultISR ;174 + DCD DefaultISR ;175 + DCD DefaultISR ;176 + DCD DefaultISR ;177 + DCD DefaultISR ;178 + DCD DefaultISR ;179 + DCD DefaultISR ;180 + DCD DefaultISR ;181 + DCD DefaultISR ;182 + DCD DefaultISR ;183 + DCD DefaultISR ;184 + DCD DefaultISR ;185 + DCD DefaultISR ;186 + DCD DefaultISR ;187 + DCD DefaultISR ;188 + DCD DefaultISR ;189 + DCD DefaultISR ;190 + DCD DefaultISR ;191 + DCD DefaultISR ;192 + DCD DefaultISR ;193 + DCD DefaultISR ;194 + DCD DefaultISR ;195 + DCD DefaultISR ;196 + DCD DefaultISR ;197 + DCD DefaultISR ;198 + DCD DefaultISR ;199 + DCD DefaultISR ;200 + DCD DefaultISR ;201 + DCD DefaultISR ;202 + DCD DefaultISR ;203 + DCD DefaultISR ;204 + DCD DefaultISR ;205 + DCD DefaultISR ;206 + DCD DefaultISR ;207 + DCD DefaultISR ;208 + DCD DefaultISR ;209 + DCD DefaultISR ;210 + DCD DefaultISR ;211 + DCD DefaultISR ;212 + DCD DefaultISR ;213 + DCD DefaultISR ;214 + DCD DefaultISR ;215 + DCD DefaultISR ;216 + DCD DefaultISR ;217 + DCD DefaultISR ;218 + DCD DefaultISR ;219 + DCD DefaultISR ;220 + DCD DefaultISR ;221 + DCD DefaultISR ;222 + DCD DefaultISR ;223 + DCD DefaultISR ;224 + DCD DefaultISR ;225 + DCD DefaultISR ;226 + DCD DefaultISR ;227 + DCD DefaultISR ;228 + DCD DefaultISR ;229 + DCD DefaultISR ;230 + DCD DefaultISR ;231 + DCD DefaultISR ;232 + DCD DefaultISR ;233 + DCD DefaultISR ;234 + DCD DefaultISR ;235 + DCD DefaultISR ;236 + DCD DefaultISR ;237 + DCD DefaultISR ;238 + DCD DefaultISR ;239 + DCD DefaultISR ;240 + DCD DefaultISR ;241 + DCD DefaultISR ;242 + DCD DefaultISR ;243 + DCD DefaultISR ;244 + DCD DefaultISR ;245 + DCD DefaultISR ;246 + DCD DefaultISR ;247 + DCD DefaultISR ;248 + DCD DefaultISR ;249 + DCD DefaultISR ;250 + DCD DefaultISR ;251 + DCD DefaultISR ;252 + DCD DefaultISR ;253 + DCD DefaultISR ;254 + DCD 0xFFFFFFFF ; Reserved for user TRIM value +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + +; <h> Flash Configuration +; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset) +; <i> and security information that allows the MCU to restrict access to the FTFL module. +; <h> Backdoor Comparison Key +; <o0> Backdoor Comparison Key 0. <0x0-0xFF:2> +; <o1> Backdoor Comparison Key 1. <0x0-0xFF:2> +; <o2> Backdoor Comparison Key 2. <0x0-0xFF:2> +; <o3> Backdoor Comparison Key 3. <0x0-0xFF:2> +; <o4> Backdoor Comparison Key 4. <0x0-0xFF:2> +; <o5> Backdoor Comparison Key 5. <0x0-0xFF:2> +; <o6> Backdoor Comparison Key 6. <0x0-0xFF:2> +; <o7> Backdoor Comparison Key 7. <0x0-0xFF:2> +BackDoorK0 EQU 0xFF +BackDoorK1 EQU 0xFF +BackDoorK2 EQU 0xFF +BackDoorK3 EQU 0xFF +BackDoorK4 EQU 0xFF +BackDoorK5 EQU 0xFF +BackDoorK6 EQU 0xFF +BackDoorK7 EQU 0xFF +; </h> +; <h> Program flash protection bytes (FPROT) +; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit. +; <i> Each bit protects a 1/32 region of the program flash memory. +; <h> FPROT0 +; <i> Program Flash Region Protect Register 0 +; <i> 1/32 - 8/32 region +; <o.0> FPROT0.0 +; <o.1> FPROT0.1 +; <o.2> FPROT0.2 +; <o.3> FPROT0.3 +; <o.4> FPROT0.4 +; <o.5> FPROT0.5 +; <o.6> FPROT0.6 +; <o.7> FPROT0.7 +nFPROT0 EQU 0x00 +FPROT0 EQU nFPROT0:EOR:0xFF +; </h> +; <h> FPROT1 +; <i> Program Flash Region Protect Register 1 +; <i> 9/32 - 16/32 region +; <o.0> FPROT1.0 +; <o.1> FPROT1.1 +; <o.2> FPROT1.2 +; <o.3> FPROT1.3 +; <o.4> FPROT1.4 +; <o.5> FPROT1.5 +; <o.6> FPROT1.6 +; <o.7> FPROT1.7 +nFPROT1 EQU 0x00 +FPROT1 EQU nFPROT1:EOR:0xFF +; </h> +; <h> FPROT2 +; <i> Program Flash Region Protect Register 2 +; <i> 17/32 - 24/32 region +; <o.0> FPROT2.0 +; <o.1> FPROT2.1 +; <o.2> FPROT2.2 +; <o.3> FPROT2.3 +; <o.4> FPROT2.4 +; <o.5> FPROT2.5 +; <o.6> FPROT2.6 +; <o.7> FPROT2.7 +nFPROT2 EQU 0x00 +FPROT2 EQU nFPROT2:EOR:0xFF +; </h> +; <h> FPROT3 +; <i> Program Flash Region Protect Register 3 +; <i> 25/32 - 32/32 region +; <o.0> FPROT3.0 +; <o.1> FPROT3.1 +; <o.2> FPROT3.2 +; <o.3> FPROT3.3 +; <o.4> FPROT3.4 +; <o.5> FPROT3.5 +; <o.6> FPROT3.6 +; <o.7> FPROT3.7 +nFPROT3 EQU 0x00 +FPROT3 EQU nFPROT3:EOR:0xFF +; </h> +; </h> +; <h> Data flash protection byte (FDPROT) +; <i> Each bit protects a 1/8 region of the data flash memory. +; <i> (Program flash only devices: Reserved) +; <o.0> FDPROT.0 +; <o.1> FDPROT.1 +; <o.2> FDPROT.2 +; <o.3> FDPROT.3 +; <o.4> FDPROT.4 +; <o.5> FDPROT.5 +; <o.6> FDPROT.6 +; <o.7> FDPROT.7 +nFDPROT EQU 0x00 +FDPROT EQU nFDPROT:EOR:0xFF +; </h> +; <h> EEPROM protection byte (FEPROT) +; <i> FlexNVM devices: Each bit protects a 1/8 region of the EEPROM. +; <i> (Program flash only devices: Reserved) +; <o.0> FEPROT.0 +; <o.1> FEPROT.1 +; <o.2> FEPROT.2 +; <o.3> FEPROT.3 +; <o.4> FEPROT.4 +; <o.5> FEPROT.5 +; <o.6> FEPROT.6 +; <o.7> FEPROT.7 +nFEPROT EQU 0x00 +FEPROT EQU nFEPROT:EOR:0xFF +; </h> +; <h> Flash nonvolatile option byte (FOPT) +; <i> Allows the user to customize the operation of the MCU at boot time. +; <o.0> LPBOOT +; <0=> Low-power boot +; <1=> Normal boot +; <o.1> EZPORT_DIS +; <0=> EzPort operation is disabled +; <1=> EzPort operation is enabled +FOPT EQU 0xFF +; </h> +; <h> Flash security byte (FSEC) +; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled", +; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!! +; <o.0..1> SEC +; <2=> MCU security status is unsecure +; <3=> MCU security status is secure +; <i> Flash Security +; <o.2..3> FSLACC +; <2=> Freescale factory access denied +; <3=> Freescale factory access granted +; <i> Freescale Failure Analysis Access Code +; <o.4..5> MEEN +; <2=> Mass erase is disabled +; <3=> Mass erase is enabled +; <o.6..7> KEYEN +; <2=> Backdoor key access enabled +; <3=> Backdoor key access disabled +; <i> Backdoor Key Security Enable +FSEC EQU 0xFE +; </h> +; </h> + IF :LNOT::DEF:RAM_TARGET + AREA FlashConfig, DATA, READONLY +__FlashConfig + DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3 + DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7 + DCB FPROT0 , FPROT1 , FPROT2 , FPROT3 + DCB FSEC , FOPT , FEPROT , FDPROT + ENDIF + + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + IF :LNOT::DEF:RAM_TARGET + REQUIRE FlashConfig + ENDIF + + CPSID I ; Mask interrupts + LDR R0, =0xE000ED08 + LDR R1, =__Vectors + STR R1, [R0] + LDR R0, =SystemInit + BLX R0 + CPSIE i ; Unmask interrupts + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler\ + PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler\ + PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler\ + PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler\ + PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP +DMA0_IRQHandler\ + PROC + EXPORT DMA0_IRQHandler [WEAK] + LDR R0, =DMA0_DriverIRQHandler + BX R0 + ENDP + +DMA1_IRQHandler\ + PROC + EXPORT DMA1_IRQHandler [WEAK] + LDR R0, =DMA1_DriverIRQHandler + BX R0 + ENDP + +DMA2_IRQHandler\ + PROC + EXPORT DMA2_IRQHandler [WEAK] + LDR R0, =DMA2_DriverIRQHandler + BX R0 + ENDP + +DMA3_IRQHandler\ + PROC + EXPORT DMA3_IRQHandler [WEAK] + LDR R0, =DMA3_DriverIRQHandler + BX R0 + ENDP + +DMA4_IRQHandler\ + PROC + EXPORT DMA4_IRQHandler [WEAK] + LDR R0, =DMA4_DriverIRQHandler + BX R0 + ENDP + +DMA5_IRQHandler\ + PROC + EXPORT DMA5_IRQHandler [WEAK] + LDR R0, =DMA5_DriverIRQHandler + BX R0 + ENDP + +DMA6_IRQHandler\ + PROC + EXPORT DMA6_IRQHandler [WEAK] + LDR R0, =DMA6_DriverIRQHandler + BX R0 + ENDP + +DMA7_IRQHandler\ + PROC + EXPORT DMA7_IRQHandler [WEAK] + LDR R0, =DMA7_DriverIRQHandler + BX R0 + ENDP + +DMA8_IRQHandler\ + PROC + EXPORT DMA8_IRQHandler [WEAK] + LDR R0, =DMA8_DriverIRQHandler + BX R0 + ENDP + +DMA9_IRQHandler\ + PROC + EXPORT DMA9_IRQHandler [WEAK] + LDR R0, =DMA9_DriverIRQHandler + BX R0 + ENDP + +DMA10_IRQHandler\ + PROC + EXPORT DMA10_IRQHandler [WEAK] + LDR R0, =DMA10_DriverIRQHandler + BX R0 + ENDP + +DMA11_IRQHandler\ + PROC + EXPORT DMA11_IRQHandler [WEAK] + LDR R0, =DMA11_DriverIRQHandler + BX R0 + ENDP + +DMA12_IRQHandler\ + PROC + EXPORT DMA12_IRQHandler [WEAK] + LDR R0, =DMA12_DriverIRQHandler + BX R0 + ENDP + +DMA13_IRQHandler\ + PROC + EXPORT DMA13_IRQHandler [WEAK] + LDR R0, =DMA13_DriverIRQHandler + BX R0 + ENDP + +DMA14_IRQHandler\ + PROC + EXPORT DMA14_IRQHandler [WEAK] + LDR R0, =DMA14_DriverIRQHandler + BX R0 + ENDP + +DMA15_IRQHandler\ + PROC + EXPORT DMA15_IRQHandler [WEAK] + LDR R0, =DMA15_DriverIRQHandler + BX R0 + ENDP + +DMA_Error_IRQHandler\ + PROC + EXPORT DMA_Error_IRQHandler [WEAK] + LDR R0, =DMA_Error_DriverIRQHandler + BX R0 + ENDP + +I2C0_IRQHandler\ + PROC + EXPORT I2C0_IRQHandler [WEAK] + LDR R0, =I2C0_DriverIRQHandler + BX R0 + ENDP + +I2C1_IRQHandler\ + PROC + EXPORT I2C1_IRQHandler [WEAK] + LDR R0, =I2C1_DriverIRQHandler + BX R0 + ENDP + +SPI0_IRQHandler\ + PROC + EXPORT SPI0_IRQHandler [WEAK] + LDR R0, =SPI0_DriverIRQHandler + BX R0 + ENDP + +SPI1_IRQHandler\ + PROC + EXPORT SPI1_IRQHandler [WEAK] + LDR R0, =SPI1_DriverIRQHandler + BX R0 + ENDP + +I2S0_Tx_IRQHandler\ + PROC + EXPORT I2S0_Tx_IRQHandler [WEAK] + LDR R0, =I2S0_Tx_DriverIRQHandler + BX R0 + ENDP + +I2S0_Rx_IRQHandler\ + PROC + EXPORT I2S0_Rx_IRQHandler [WEAK] + LDR R0, =I2S0_Rx_DriverIRQHandler + BX R0 + ENDP + +UART0_LON_IRQHandler\ + PROC + EXPORT UART0_LON_IRQHandler [WEAK] + LDR R0, =UART0_LON_DriverIRQHandler + BX R0 + ENDP + +UART0_RX_TX_IRQHandler\ + PROC + EXPORT UART0_RX_TX_IRQHandler [WEAK] + LDR R0, =UART0_RX_TX_DriverIRQHandler + BX R0 + ENDP + +UART0_ERR_IRQHandler\ + PROC + EXPORT UART0_ERR_IRQHandler [WEAK] + LDR R0, =UART0_ERR_DriverIRQHandler + BX R0 + ENDP + +UART1_RX_TX_IRQHandler\ + PROC + EXPORT UART1_RX_TX_IRQHandler [WEAK] + LDR R0, =UART1_RX_TX_DriverIRQHandler + BX R0 + ENDP + +UART1_ERR_IRQHandler\ + PROC + EXPORT UART1_ERR_IRQHandler [WEAK] + LDR R0, =UART1_ERR_DriverIRQHandler + BX R0 + ENDP + +UART2_RX_TX_IRQHandler\ + PROC + EXPORT UART2_RX_TX_IRQHandler [WEAK] + LDR R0, =UART2_RX_TX_DriverIRQHandler + BX R0 + ENDP + +UART2_ERR_IRQHandler\ + PROC + EXPORT UART2_ERR_IRQHandler [WEAK] + LDR R0, =UART2_ERR_DriverIRQHandler + BX R0 + ENDP + +UART3_RX_TX_IRQHandler\ + PROC + EXPORT UART3_RX_TX_IRQHandler [WEAK] + LDR R0, =UART3_RX_TX_DriverIRQHandler + BX R0 + ENDP + +UART3_ERR_IRQHandler\ + PROC + EXPORT UART3_ERR_IRQHandler [WEAK] + LDR R0, =UART3_ERR_DriverIRQHandler + BX R0 + ENDP + +SPI2_IRQHandler\ + PROC + EXPORT SPI2_IRQHandler [WEAK] + LDR R0, =SPI2_DriverIRQHandler + BX R0 + ENDP + +UART4_RX_TX_IRQHandler\ + PROC + EXPORT UART4_RX_TX_IRQHandler [WEAK] + LDR R0, =UART4_RX_TX_DriverIRQHandler + BX R0 + ENDP + +UART4_ERR_IRQHandler\ + PROC + EXPORT UART4_ERR_IRQHandler [WEAK] + LDR R0, =UART4_ERR_DriverIRQHandler + BX R0 + ENDP + +UART5_RX_TX_IRQHandler\ + PROC + EXPORT UART5_RX_TX_IRQHandler [WEAK] + LDR R0, =UART5_RX_TX_DriverIRQHandler + BX R0 + ENDP + +UART5_ERR_IRQHandler\ + PROC + EXPORT UART5_ERR_IRQHandler [WEAK] + LDR R0, =UART5_ERR_DriverIRQHandler + BX R0 + ENDP + +I2C2_IRQHandler\ + PROC + EXPORT I2C2_IRQHandler [WEAK] + LDR R0, =I2C2_DriverIRQHandler + BX R0 + ENDP + +CAN0_ORed_Message_buffer_IRQHandler\ + PROC + EXPORT CAN0_ORed_Message_buffer_IRQHandler [WEAK] + LDR R0, =CAN0_DriverIRQHandler + BX R0 + ENDP + +CAN0_Bus_Off_IRQHandler\ + PROC + EXPORT CAN0_Bus_Off_IRQHandler [WEAK] + LDR R0, =CAN0_DriverIRQHandler + BX R0 + ENDP + +CAN0_Error_IRQHandler\ + PROC + EXPORT CAN0_Error_IRQHandler [WEAK] + LDR R0, =CAN0_DriverIRQHandler + BX R0 + ENDP + +CAN0_Tx_Warning_IRQHandler\ + PROC + EXPORT CAN0_Tx_Warning_IRQHandler [WEAK] + LDR R0, =CAN0_DriverIRQHandler + BX R0 + ENDP + +CAN0_Rx_Warning_IRQHandler\ + PROC + EXPORT CAN0_Rx_Warning_IRQHandler [WEAK] + LDR R0, =CAN0_DriverIRQHandler + BX R0 + ENDP + +CAN0_Wake_Up_IRQHandler\ + PROC + EXPORT CAN0_Wake_Up_IRQHandler [WEAK] + LDR R0, =CAN0_DriverIRQHandler + BX R0 + ENDP + +SDHC_IRQHandler\ + PROC + EXPORT SDHC_IRQHandler [WEAK] + LDR R0, =SDHC_DriverIRQHandler + BX R0 + ENDP + +Default_Handler\ + PROC + EXPORT DMA0_DriverIRQHandler [WEAK] + EXPORT DMA1_DriverIRQHandler [WEAK] + EXPORT DMA2_DriverIRQHandler [WEAK] + EXPORT DMA3_DriverIRQHandler [WEAK] + EXPORT DMA4_DriverIRQHandler [WEAK] + EXPORT DMA5_DriverIRQHandler [WEAK] + EXPORT DMA6_DriverIRQHandler [WEAK] + EXPORT DMA7_DriverIRQHandler [WEAK] + EXPORT DMA8_DriverIRQHandler [WEAK] + EXPORT DMA9_DriverIRQHandler [WEAK] + EXPORT DMA10_DriverIRQHandler [WEAK] + EXPORT DMA11_DriverIRQHandler [WEAK] + EXPORT DMA12_DriverIRQHandler [WEAK] + EXPORT DMA13_DriverIRQHandler [WEAK] + EXPORT DMA14_DriverIRQHandler [WEAK] + EXPORT DMA15_DriverIRQHandler [WEAK] + EXPORT DMA_Error_DriverIRQHandler [WEAK] + EXPORT MCM_IRQHandler [WEAK] + EXPORT FTFE_IRQHandler [WEAK] + EXPORT Read_Collision_IRQHandler [WEAK] + EXPORT LVD_LVW_IRQHandler [WEAK] + EXPORT LLWU_IRQHandler [WEAK] + EXPORT WDOG_EWM_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT I2C0_DriverIRQHandler [WEAK] + EXPORT I2C1_DriverIRQHandler [WEAK] + EXPORT SPI0_DriverIRQHandler [WEAK] + EXPORT SPI1_DriverIRQHandler [WEAK] + EXPORT I2S0_Tx_DriverIRQHandler [WEAK] + EXPORT I2S0_Rx_DriverIRQHandler [WEAK] + EXPORT UART0_LON_DriverIRQHandler [WEAK] + EXPORT UART0_RX_TX_DriverIRQHandler [WEAK] + EXPORT UART0_ERR_DriverIRQHandler [WEAK] + EXPORT UART1_RX_TX_DriverIRQHandler [WEAK] + EXPORT UART1_ERR_DriverIRQHandler [WEAK] + EXPORT UART2_RX_TX_DriverIRQHandler [WEAK] + EXPORT UART2_ERR_DriverIRQHandler [WEAK] + EXPORT UART3_RX_TX_DriverIRQHandler [WEAK] + EXPORT UART3_ERR_DriverIRQHandler [WEAK] + EXPORT ADC0_IRQHandler [WEAK] + EXPORT CMP0_IRQHandler [WEAK] + EXPORT CMP1_IRQHandler [WEAK] + EXPORT FTM0_IRQHandler [WEAK] + EXPORT FTM1_IRQHandler [WEAK] + EXPORT FTM2_IRQHandler [WEAK] + EXPORT CMT_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT RTC_Seconds_IRQHandler [WEAK] + EXPORT PIT0_IRQHandler [WEAK] + EXPORT PIT1_IRQHandler [WEAK] + EXPORT PIT2_IRQHandler [WEAK] + EXPORT PIT3_IRQHandler [WEAK] + EXPORT PDB0_IRQHandler [WEAK] + EXPORT USB0_IRQHandler [WEAK] + EXPORT USBDCD_IRQHandler [WEAK] + EXPORT Reserved71_IRQHandler [WEAK] + EXPORT DAC0_IRQHandler [WEAK] + EXPORT MCG_IRQHandler [WEAK] + EXPORT LPTMR0_IRQHandler [WEAK] + EXPORT PORTA_IRQHandler [WEAK] + EXPORT PORTB_IRQHandler [WEAK] + EXPORT PORTC_IRQHandler [WEAK] + EXPORT PORTD_IRQHandler [WEAK] + EXPORT PORTE_IRQHandler [WEAK] + EXPORT SWI_IRQHandler [WEAK] + EXPORT SPI2_DriverIRQHandler [WEAK] + EXPORT UART4_RX_TX_DriverIRQHandler [WEAK] + EXPORT UART4_ERR_DriverIRQHandler [WEAK] + EXPORT UART5_RX_TX_DriverIRQHandler [WEAK] + EXPORT UART5_ERR_DriverIRQHandler [WEAK] + EXPORT CMP2_IRQHandler [WEAK] + EXPORT FTM3_IRQHandler [WEAK] + EXPORT DAC1_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT I2C2_DriverIRQHandler [WEAK] + EXPORT CAN0_DriverIRQHandler [WEAK] + EXPORT SDHC_DriverIRQHandler [WEAK] + EXPORT Reserved98_IRQHandler [WEAK] + EXPORT Reserved99_IRQHandler [WEAK] + EXPORT Reserved100_IRQHandler [WEAK] + EXPORT Reserved101_IRQHandler [WEAK] + EXPORT DefaultISR [WEAK] +DMA0_DriverIRQHandler +DMA1_DriverIRQHandler +DMA2_DriverIRQHandler +DMA3_DriverIRQHandler +DMA4_DriverIRQHandler +DMA5_DriverIRQHandler +DMA6_DriverIRQHandler +DMA7_DriverIRQHandler +DMA8_DriverIRQHandler +DMA9_DriverIRQHandler +DMA10_DriverIRQHandler +DMA11_DriverIRQHandler +DMA12_DriverIRQHandler +DMA13_DriverIRQHandler +DMA14_DriverIRQHandler +DMA15_DriverIRQHandler +DMA_Error_DriverIRQHandler +MCM_IRQHandler +FTFE_IRQHandler +Read_Collision_IRQHandler +LVD_LVW_IRQHandler +LLWU_IRQHandler +WDOG_EWM_IRQHandler +RNG_IRQHandler +I2C0_DriverIRQHandler +I2C1_DriverIRQHandler +SPI0_DriverIRQHandler +SPI1_DriverIRQHandler +I2S0_Tx_DriverIRQHandler +I2S0_Rx_DriverIRQHandler +UART0_LON_DriverIRQHandler +UART0_RX_TX_DriverIRQHandler +UART0_ERR_DriverIRQHandler +UART1_RX_TX_DriverIRQHandler +UART1_ERR_DriverIRQHandler +UART2_RX_TX_DriverIRQHandler +UART2_ERR_DriverIRQHandler +UART3_RX_TX_DriverIRQHandler +UART3_ERR_DriverIRQHandler +ADC0_IRQHandler +CMP0_IRQHandler +CMP1_IRQHandler +FTM0_IRQHandler +FTM1_IRQHandler +FTM2_IRQHandler +CMT_IRQHandler +RTC_IRQHandler +RTC_Seconds_IRQHandler +PIT0_IRQHandler +PIT1_IRQHandler +PIT2_IRQHandler +PIT3_IRQHandler +PDB0_IRQHandler +USB0_IRQHandler +USBDCD_IRQHandler +Reserved71_IRQHandler +DAC0_IRQHandler +MCG_IRQHandler +LPTMR0_IRQHandler +PORTA_IRQHandler +PORTB_IRQHandler +PORTC_IRQHandler +PORTD_IRQHandler +PORTE_IRQHandler +SWI_IRQHandler +SPI2_DriverIRQHandler +UART4_RX_TX_DriverIRQHandler +UART4_ERR_DriverIRQHandler +UART5_RX_TX_DriverIRQHandler +UART5_ERR_DriverIRQHandler +CMP2_IRQHandler +FTM3_IRQHandler +DAC1_IRQHandler +ADC1_IRQHandler +I2C2_DriverIRQHandler +CAN0_DriverIRQHandler +SDHC_DriverIRQHandler +Reserved98_IRQHandler +Reserved99_IRQHandler +Reserved100_IRQHandler +Reserved101_IRQHandler +DefaultISR + B DefaultISR + ENDP + ALIGN + + + END
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/TARGET_MCU_K24F1M/device/TOOLCHAIN_ARM_STD/startup_MK24F12.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,1023 +0,0 @@ -; * --------------------------------------------------------------------------------------- -; * @file: startup_MK24F12.s -; * @purpose: CMSIS Cortex-M4 Core Device Startup File -; * MK24F12 -; * @version: 2.8 -; * @date: 2016-3-21 -; * @build: b160321 -; * --------------------------------------------------------------------------------------- -; * -; * Copyright (c) 1997 - 2016 , Freescale Semiconductor, Inc. -; * All rights reserved. -; * -; * Redistribution and use in source and binary forms, with or without modification, -; * are permitted provided that the following conditions are met: -; * -; * o Redistributions of source code must retain the above copyright notice, this list -; * of conditions and the following disclaimer. -; * -; * o Redistributions in binary form must reproduce the above copyright notice, this -; * list of conditions and the following disclaimer in the documentation and/or -; * other materials provided with the distribution. -; * -; * o Neither the name of Freescale Semiconductor, Inc. nor the names of its -; * contributors may be used to endorse or promote products derived from this -; * software without specific prior written permission. -; * -; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; * -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; *****************************************************************************/ - -__initial_sp EQU 0x20030000 ; Top of RAM - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ;NMI Handler - DCD HardFault_Handler ;Hard Fault Handler - DCD MemManage_Handler ;MPU Fault Handler - DCD BusFault_Handler ;Bus Fault Handler - DCD UsageFault_Handler ;Usage Fault Handler - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD 0 ;Reserved - DCD SVC_Handler ;SVCall Handler - DCD DebugMon_Handler ;Debug Monitor Handler - DCD 0 ;Reserved - DCD PendSV_Handler ;PendSV Handler - DCD SysTick_Handler ;SysTick Handler - - ;External Interrupts - DCD DMA0_IRQHandler ;DMA Channel 0 Transfer Complete - DCD DMA1_IRQHandler ;DMA Channel 1 Transfer Complete - DCD DMA2_IRQHandler ;DMA Channel 2 Transfer Complete - DCD DMA3_IRQHandler ;DMA Channel 3 Transfer Complete - DCD DMA4_IRQHandler ;DMA Channel 4 Transfer Complete - DCD DMA5_IRQHandler ;DMA Channel 5 Transfer Complete - DCD DMA6_IRQHandler ;DMA Channel 6 Transfer Complete - DCD DMA7_IRQHandler ;DMA Channel 7 Transfer Complete - DCD DMA8_IRQHandler ;DMA Channel 8 Transfer Complete - DCD DMA9_IRQHandler ;DMA Channel 9 Transfer Complete - DCD DMA10_IRQHandler ;DMA Channel 10 Transfer Complete - DCD DMA11_IRQHandler ;DMA Channel 11 Transfer Complete - DCD DMA12_IRQHandler ;DMA Channel 12 Transfer Complete - DCD DMA13_IRQHandler ;DMA Channel 13 Transfer Complete - DCD DMA14_IRQHandler ;DMA Channel 14 Transfer Complete - DCD DMA15_IRQHandler ;DMA Channel 15 Transfer Complete - DCD DMA_Error_IRQHandler ;DMA Error Interrupt - DCD MCM_IRQHandler ;Normal Interrupt - DCD FTFE_IRQHandler ;FTFE Command complete interrupt - DCD Read_Collision_IRQHandler ;Read Collision Interrupt - DCD LVD_LVW_IRQHandler ;Low Voltage Detect, Low Voltage Warning - DCD LLWU_IRQHandler ;Low Leakage Wakeup Unit - DCD WDOG_EWM_IRQHandler ;WDOG Interrupt - DCD RNG_IRQHandler ;RNG Interrupt - DCD I2C0_IRQHandler ;I2C0 interrupt - DCD I2C1_IRQHandler ;I2C1 interrupt - DCD SPI0_IRQHandler ;SPI0 Interrupt - DCD SPI1_IRQHandler ;SPI1 Interrupt - DCD I2S0_Tx_IRQHandler ;I2S0 transmit interrupt - DCD I2S0_Rx_IRQHandler ;I2S0 receive interrupt - DCD UART0_LON_IRQHandler ;UART0 LON interrupt - DCD UART0_RX_TX_IRQHandler ;UART0 Receive/Transmit interrupt - DCD UART0_ERR_IRQHandler ;UART0 Error interrupt - DCD UART1_RX_TX_IRQHandler ;UART1 Receive/Transmit interrupt - DCD UART1_ERR_IRQHandler ;UART1 Error interrupt - DCD UART2_RX_TX_IRQHandler ;UART2 Receive/Transmit interrupt - DCD UART2_ERR_IRQHandler ;UART2 Error interrupt - DCD UART3_RX_TX_IRQHandler ;UART3 Receive/Transmit interrupt - DCD UART3_ERR_IRQHandler ;UART3 Error interrupt - DCD ADC0_IRQHandler ;ADC0 interrupt - DCD CMP0_IRQHandler ;CMP0 interrupt - DCD CMP1_IRQHandler ;CMP1 interrupt - DCD FTM0_IRQHandler ;FTM0 fault, overflow and channels interrupt - DCD FTM1_IRQHandler ;FTM1 fault, overflow and channels interrupt - DCD FTM2_IRQHandler ;FTM2 fault, overflow and channels interrupt - DCD CMT_IRQHandler ;CMT interrupt - DCD RTC_IRQHandler ;RTC interrupt - DCD RTC_Seconds_IRQHandler ;RTC seconds interrupt - DCD PIT0_IRQHandler ;PIT timer channel 0 interrupt - DCD PIT1_IRQHandler ;PIT timer channel 1 interrupt - DCD PIT2_IRQHandler ;PIT timer channel 2 interrupt - DCD PIT3_IRQHandler ;PIT timer channel 3 interrupt - DCD PDB0_IRQHandler ;PDB0 Interrupt - DCD USB0_IRQHandler ;USB0 interrupt - DCD USBDCD_IRQHandler ;USBDCD Interrupt - DCD Reserved71_IRQHandler ;Reserved interrupt 71 - DCD DAC0_IRQHandler ;DAC0 interrupt - DCD MCG_IRQHandler ;MCG Interrupt - DCD LPTMR0_IRQHandler ;LPTimer interrupt - DCD PORTA_IRQHandler ;Port A interrupt - DCD PORTB_IRQHandler ;Port B interrupt - DCD PORTC_IRQHandler ;Port C interrupt - DCD PORTD_IRQHandler ;Port D interrupt - DCD PORTE_IRQHandler ;Port E interrupt - DCD SWI_IRQHandler ;Software interrupt - DCD SPI2_IRQHandler ;SPI2 Interrupt - DCD UART4_RX_TX_IRQHandler ;UART4 Receive/Transmit interrupt - DCD UART4_ERR_IRQHandler ;UART4 Error interrupt - DCD UART5_RX_TX_IRQHandler ;UART5 Receive/Transmit interrupt - DCD UART5_ERR_IRQHandler ;UART5 Error interrupt - DCD CMP2_IRQHandler ;CMP2 interrupt - DCD FTM3_IRQHandler ;FTM3 fault, overflow and channels interrupt - DCD DAC1_IRQHandler ;DAC1 interrupt - DCD ADC1_IRQHandler ;ADC1 interrupt - DCD I2C2_IRQHandler ;I2C2 interrupt - DCD CAN0_ORed_Message_buffer_IRQHandler ;CAN0 OR'd message buffers interrupt - DCD CAN0_Bus_Off_IRQHandler ;CAN0 bus off interrupt - DCD CAN0_Error_IRQHandler ;CAN0 error interrupt - DCD CAN0_Tx_Warning_IRQHandler ;CAN0 Tx warning interrupt - DCD CAN0_Rx_Warning_IRQHandler ;CAN0 Rx warning interrupt - DCD CAN0_Wake_Up_IRQHandler ;CAN0 wake up interrupt - DCD SDHC_IRQHandler ;SDHC interrupt - DCD Reserved98_IRQHandler ;Reserved interrupt 98 - DCD Reserved99_IRQHandler ;Reserved interrupt 99 - DCD Reserved100_IRQHandler ;Reserved interrupt 100 - DCD Reserved101_IRQHandler ;Reserved interrupt 101 - DCD DefaultISR ;102 - DCD DefaultISR ;103 - DCD DefaultISR ;104 - DCD DefaultISR ;105 - DCD DefaultISR ;106 - DCD DefaultISR ;107 - DCD DefaultISR ;108 - DCD DefaultISR ;109 - DCD DefaultISR ;110 - DCD DefaultISR ;111 - DCD DefaultISR ;112 - DCD DefaultISR ;113 - DCD DefaultISR ;114 - DCD DefaultISR ;115 - DCD DefaultISR ;116 - DCD DefaultISR ;117 - DCD DefaultISR ;118 - DCD DefaultISR ;119 - DCD DefaultISR ;120 - DCD DefaultISR ;121 - DCD DefaultISR ;122 - DCD DefaultISR ;123 - DCD DefaultISR ;124 - DCD DefaultISR ;125 - DCD DefaultISR ;126 - DCD DefaultISR ;127 - DCD DefaultISR ;128 - DCD DefaultISR ;129 - DCD DefaultISR ;130 - DCD DefaultISR ;131 - DCD DefaultISR ;132 - DCD DefaultISR ;133 - DCD DefaultISR ;134 - DCD DefaultISR ;135 - DCD DefaultISR ;136 - DCD DefaultISR ;137 - DCD DefaultISR ;138 - DCD DefaultISR ;139 - DCD DefaultISR ;140 - DCD DefaultISR ;141 - DCD DefaultISR ;142 - DCD DefaultISR ;143 - DCD DefaultISR ;144 - DCD DefaultISR ;145 - DCD DefaultISR ;146 - DCD DefaultISR ;147 - DCD DefaultISR ;148 - DCD DefaultISR ;149 - DCD DefaultISR ;150 - DCD DefaultISR ;151 - DCD DefaultISR ;152 - DCD DefaultISR ;153 - DCD DefaultISR ;154 - DCD DefaultISR ;155 - DCD DefaultISR ;156 - DCD DefaultISR ;157 - DCD DefaultISR ;158 - DCD DefaultISR ;159 - DCD DefaultISR ;160 - DCD DefaultISR ;161 - DCD DefaultISR ;162 - DCD DefaultISR ;163 - DCD DefaultISR ;164 - DCD DefaultISR ;165 - DCD DefaultISR ;166 - DCD DefaultISR ;167 - DCD DefaultISR ;168 - DCD DefaultISR ;169 - DCD DefaultISR ;170 - DCD DefaultISR ;171 - DCD DefaultISR ;172 - DCD DefaultISR ;173 - DCD DefaultISR ;174 - DCD DefaultISR ;175 - DCD DefaultISR ;176 - DCD DefaultISR ;177 - DCD DefaultISR ;178 - DCD DefaultISR ;179 - DCD DefaultISR ;180 - DCD DefaultISR ;181 - DCD DefaultISR ;182 - DCD DefaultISR ;183 - DCD DefaultISR ;184 - DCD DefaultISR ;185 - DCD DefaultISR ;186 - DCD DefaultISR ;187 - DCD DefaultISR ;188 - DCD DefaultISR ;189 - DCD DefaultISR ;190 - DCD DefaultISR ;191 - DCD DefaultISR ;192 - DCD DefaultISR ;193 - DCD DefaultISR ;194 - DCD DefaultISR ;195 - DCD DefaultISR ;196 - DCD DefaultISR ;197 - DCD DefaultISR ;198 - DCD DefaultISR ;199 - DCD DefaultISR ;200 - DCD DefaultISR ;201 - DCD DefaultISR ;202 - DCD DefaultISR ;203 - DCD DefaultISR ;204 - DCD DefaultISR ;205 - DCD DefaultISR ;206 - DCD DefaultISR ;207 - DCD DefaultISR ;208 - DCD DefaultISR ;209 - DCD DefaultISR ;210 - DCD DefaultISR ;211 - DCD DefaultISR ;212 - DCD DefaultISR ;213 - DCD DefaultISR ;214 - DCD DefaultISR ;215 - DCD DefaultISR ;216 - DCD DefaultISR ;217 - DCD DefaultISR ;218 - DCD DefaultISR ;219 - DCD DefaultISR ;220 - DCD DefaultISR ;221 - DCD DefaultISR ;222 - DCD DefaultISR ;223 - DCD DefaultISR ;224 - DCD DefaultISR ;225 - DCD DefaultISR ;226 - DCD DefaultISR ;227 - DCD DefaultISR ;228 - DCD DefaultISR ;229 - DCD DefaultISR ;230 - DCD DefaultISR ;231 - DCD DefaultISR ;232 - DCD DefaultISR ;233 - DCD DefaultISR ;234 - DCD DefaultISR ;235 - DCD DefaultISR ;236 - DCD DefaultISR ;237 - DCD DefaultISR ;238 - DCD DefaultISR ;239 - DCD DefaultISR ;240 - DCD DefaultISR ;241 - DCD DefaultISR ;242 - DCD DefaultISR ;243 - DCD DefaultISR ;244 - DCD DefaultISR ;245 - DCD DefaultISR ;246 - DCD DefaultISR ;247 - DCD DefaultISR ;248 - DCD DefaultISR ;249 - DCD DefaultISR ;250 - DCD DefaultISR ;251 - DCD DefaultISR ;252 - DCD DefaultISR ;253 - DCD DefaultISR ;254 - DCD 0xFFFFFFFF ; Reserved for user TRIM value -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - -; <h> Flash Configuration -; <i> 16-byte flash configuration field that stores default protection settings (loaded on reset) -; <i> and security information that allows the MCU to restrict access to the FTFL module. -; <h> Backdoor Comparison Key -; <o0> Backdoor Comparison Key 0. <0x0-0xFF:2> -; <o1> Backdoor Comparison Key 1. <0x0-0xFF:2> -; <o2> Backdoor Comparison Key 2. <0x0-0xFF:2> -; <o3> Backdoor Comparison Key 3. <0x0-0xFF:2> -; <o4> Backdoor Comparison Key 4. <0x0-0xFF:2> -; <o5> Backdoor Comparison Key 5. <0x0-0xFF:2> -; <o6> Backdoor Comparison Key 6. <0x0-0xFF:2> -; <o7> Backdoor Comparison Key 7. <0x0-0xFF:2> -BackDoorK0 EQU 0xFF -BackDoorK1 EQU 0xFF -BackDoorK2 EQU 0xFF -BackDoorK3 EQU 0xFF -BackDoorK4 EQU 0xFF -BackDoorK5 EQU 0xFF -BackDoorK6 EQU 0xFF -BackDoorK7 EQU 0xFF -; </h> -; <h> Program flash protection bytes (FPROT) -; <i> Each program flash region can be protected from program and erase operation by setting the associated PROT bit. -; <i> Each bit protects a 1/32 region of the program flash memory. -; <h> FPROT0 -; <i> Program Flash Region Protect Register 0 -; <i> 1/32 - 8/32 region -; <o.0> FPROT0.0 -; <o.1> FPROT0.1 -; <o.2> FPROT0.2 -; <o.3> FPROT0.3 -; <o.4> FPROT0.4 -; <o.5> FPROT0.5 -; <o.6> FPROT0.6 -; <o.7> FPROT0.7 -nFPROT0 EQU 0x00 -FPROT0 EQU nFPROT0:EOR:0xFF -; </h> -; <h> FPROT1 -; <i> Program Flash Region Protect Register 1 -; <i> 9/32 - 16/32 region -; <o.0> FPROT1.0 -; <o.1> FPROT1.1 -; <o.2> FPROT1.2 -; <o.3> FPROT1.3 -; <o.4> FPROT1.4 -; <o.5> FPROT1.5 -; <o.6> FPROT1.6 -; <o.7> FPROT1.7 -nFPROT1 EQU 0x00 -FPROT1 EQU nFPROT1:EOR:0xFF -; </h> -; <h> FPROT2 -; <i> Program Flash Region Protect Register 2 -; <i> 17/32 - 24/32 region -; <o.0> FPROT2.0 -; <o.1> FPROT2.1 -; <o.2> FPROT2.2 -; <o.3> FPROT2.3 -; <o.4> FPROT2.4 -; <o.5> FPROT2.5 -; <o.6> FPROT2.6 -; <o.7> FPROT2.7 -nFPROT2 EQU 0x00 -FPROT2 EQU nFPROT2:EOR:0xFF -; </h> -; <h> FPROT3 -; <i> Program Flash Region Protect Register 3 -; <i> 25/32 - 32/32 region -; <o.0> FPROT3.0 -; <o.1> FPROT3.1 -; <o.2> FPROT3.2 -; <o.3> FPROT3.3 -; <o.4> FPROT3.4 -; <o.5> FPROT3.5 -; <o.6> FPROT3.6 -; <o.7> FPROT3.7 -nFPROT3 EQU 0x00 -FPROT3 EQU nFPROT3:EOR:0xFF -; </h> -; </h> -; <h> Data flash protection byte (FDPROT) -; <i> Each bit protects a 1/8 region of the data flash memory. -; <i> (Program flash only devices: Reserved) -; <o.0> FDPROT.0 -; <o.1> FDPROT.1 -; <o.2> FDPROT.2 -; <o.3> FDPROT.3 -; <o.4> FDPROT.4 -; <o.5> FDPROT.5 -; <o.6> FDPROT.6 -; <o.7> FDPROT.7 -nFDPROT EQU 0x00 -FDPROT EQU nFDPROT:EOR:0xFF -; </h> -; <h> EEPROM protection byte (FEPROT) -; <i> FlexNVM devices: Each bit protects a 1/8 region of the EEPROM. -; <i> (Program flash only devices: Reserved) -; <o.0> FEPROT.0 -; <o.1> FEPROT.1 -; <o.2> FEPROT.2 -; <o.3> FEPROT.3 -; <o.4> FEPROT.4 -; <o.5> FEPROT.5 -; <o.6> FEPROT.6 -; <o.7> FEPROT.7 -nFEPROT EQU 0x00 -FEPROT EQU nFEPROT:EOR:0xFF -; </h> -; <h> Flash nonvolatile option byte (FOPT) -; <i> Allows the user to customize the operation of the MCU at boot time. -; <o.0> LPBOOT -; <0=> Low-power boot -; <1=> Normal boot -; <o.1> EZPORT_DIS -; <0=> EzPort operation is disabled -; <1=> EzPort operation is enabled -FOPT EQU 0xFF -; </h> -; <h> Flash security byte (FSEC) -; <i> WARNING: If SEC field is configured as "MCU security status is secure" and MEEN field is configured as "Mass erase is disabled", -; <i> MCU's security status cannot be set back to unsecure state since Mass erase via the debugger is blocked !!! -; <o.0..1> SEC -; <2=> MCU security status is unsecure -; <3=> MCU security status is secure -; <i> Flash Security -; <o.2..3> FSLACC -; <2=> Freescale factory access denied -; <3=> Freescale factory access granted -; <i> Freescale Failure Analysis Access Code -; <o.4..5> MEEN -; <2=> Mass erase is disabled -; <3=> Mass erase is enabled -; <o.6..7> KEYEN -; <2=> Backdoor key access enabled -; <3=> Backdoor key access disabled -; <i> Backdoor Key Security Enable -FSEC EQU 0xFE -; </h> -; </h> - IF :LNOT::DEF:RAM_TARGET - AREA FlashConfig, DATA, READONLY -__FlashConfig - DCB BackDoorK0, BackDoorK1, BackDoorK2, BackDoorK3 - DCB BackDoorK4, BackDoorK5, BackDoorK6, BackDoorK7 - DCB FPROT0 , FPROT1 , FPROT2 , FPROT3 - DCB FSEC , FOPT , FEPROT , FDPROT - ENDIF - - - AREA |.text|, CODE, READONLY - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - IF :LNOT::DEF:RAM_TARGET - REQUIRE FlashConfig - ENDIF - - CPSID I ; Mask interrupts - LDR R0, =0xE000ED08 - LDR R1, =__Vectors - STR R1, [R0] - LDR R0, =SystemInit - BLX R0 - CPSIE i ; Unmask interrupts - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) -NMI_Handler\ - PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler\ - PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler\ - PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler\ - PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP -DMA0_IRQHandler\ - PROC - EXPORT DMA0_IRQHandler [WEAK] - LDR R0, =DMA0_DriverIRQHandler - BX R0 - ENDP - -DMA1_IRQHandler\ - PROC - EXPORT DMA1_IRQHandler [WEAK] - LDR R0, =DMA1_DriverIRQHandler - BX R0 - ENDP - -DMA2_IRQHandler\ - PROC - EXPORT DMA2_IRQHandler [WEAK] - LDR R0, =DMA2_DriverIRQHandler - BX R0 - ENDP - -DMA3_IRQHandler\ - PROC - EXPORT DMA3_IRQHandler [WEAK] - LDR R0, =DMA3_DriverIRQHandler - BX R0 - ENDP - -DMA4_IRQHandler\ - PROC - EXPORT DMA4_IRQHandler [WEAK] - LDR R0, =DMA4_DriverIRQHandler - BX R0 - ENDP - -DMA5_IRQHandler\ - PROC - EXPORT DMA5_IRQHandler [WEAK] - LDR R0, =DMA5_DriverIRQHandler - BX R0 - ENDP - -DMA6_IRQHandler\ - PROC - EXPORT DMA6_IRQHandler [WEAK] - LDR R0, =DMA6_DriverIRQHandler - BX R0 - ENDP - -DMA7_IRQHandler\ - PROC - EXPORT DMA7_IRQHandler [WEAK] - LDR R0, =DMA7_DriverIRQHandler - BX R0 - ENDP - -DMA8_IRQHandler\ - PROC - EXPORT DMA8_IRQHandler [WEAK] - LDR R0, =DMA8_DriverIRQHandler - BX R0 - ENDP - -DMA9_IRQHandler\ - PROC - EXPORT DMA9_IRQHandler [WEAK] - LDR R0, =DMA9_DriverIRQHandler - BX R0 - ENDP - -DMA10_IRQHandler\ - PROC - EXPORT DMA10_IRQHandler [WEAK] - LDR R0, =DMA10_DriverIRQHandler - BX R0 - ENDP - -DMA11_IRQHandler\ - PROC - EXPORT DMA11_IRQHandler [WEAK] - LDR R0, =DMA11_DriverIRQHandler - BX R0 - ENDP - -DMA12_IRQHandler\ - PROC - EXPORT DMA12_IRQHandler [WEAK] - LDR R0, =DMA12_DriverIRQHandler - BX R0 - ENDP - -DMA13_IRQHandler\ - PROC - EXPORT DMA13_IRQHandler [WEAK] - LDR R0, =DMA13_DriverIRQHandler - BX R0 - ENDP - -DMA14_IRQHandler\ - PROC - EXPORT DMA14_IRQHandler [WEAK] - LDR R0, =DMA14_DriverIRQHandler - BX R0 - ENDP - -DMA15_IRQHandler\ - PROC - EXPORT DMA15_IRQHandler [WEAK] - LDR R0, =DMA15_DriverIRQHandler - BX R0 - ENDP - -DMA_Error_IRQHandler\ - PROC - EXPORT DMA_Error_IRQHandler [WEAK] - LDR R0, =DMA_Error_DriverIRQHandler - BX R0 - ENDP - -I2C0_IRQHandler\ - PROC - EXPORT I2C0_IRQHandler [WEAK] - LDR R0, =I2C0_DriverIRQHandler - BX R0 - ENDP - -I2C1_IRQHandler\ - PROC - EXPORT I2C1_IRQHandler [WEAK] - LDR R0, =I2C1_DriverIRQHandler - BX R0 - ENDP - -SPI0_IRQHandler\ - PROC - EXPORT SPI0_IRQHandler [WEAK] - LDR R0, =SPI0_DriverIRQHandler - BX R0 - ENDP - -SPI1_IRQHandler\ - PROC - EXPORT SPI1_IRQHandler [WEAK] - LDR R0, =SPI1_DriverIRQHandler - BX R0 - ENDP - -I2S0_Tx_IRQHandler\ - PROC - EXPORT I2S0_Tx_IRQHandler [WEAK] - LDR R0, =I2S0_Tx_DriverIRQHandler - BX R0 - ENDP - -I2S0_Rx_IRQHandler\ - PROC - EXPORT I2S0_Rx_IRQHandler [WEAK] - LDR R0, =I2S0_Rx_DriverIRQHandler - BX R0 - ENDP - -UART0_LON_IRQHandler\ - PROC - EXPORT UART0_LON_IRQHandler [WEAK] - LDR R0, =UART0_LON_DriverIRQHandler - BX R0 - ENDP - -UART0_RX_TX_IRQHandler\ - PROC - EXPORT UART0_RX_TX_IRQHandler [WEAK] - LDR R0, =UART0_RX_TX_DriverIRQHandler - BX R0 - ENDP - -UART0_ERR_IRQHandler\ - PROC - EXPORT UART0_ERR_IRQHandler [WEAK] - LDR R0, =UART0_ERR_DriverIRQHandler - BX R0 - ENDP - -UART1_RX_TX_IRQHandler\ - PROC - EXPORT UART1_RX_TX_IRQHandler [WEAK] - LDR R0, =UART1_RX_TX_DriverIRQHandler - BX R0 - ENDP - -UART1_ERR_IRQHandler\ - PROC - EXPORT UART1_ERR_IRQHandler [WEAK] - LDR R0, =UART1_ERR_DriverIRQHandler - BX R0 - ENDP - -UART2_RX_TX_IRQHandler\ - PROC - EXPORT UART2_RX_TX_IRQHandler [WEAK] - LDR R0, =UART2_RX_TX_DriverIRQHandler - BX R0 - ENDP - -UART2_ERR_IRQHandler\ - PROC - EXPORT UART2_ERR_IRQHandler [WEAK] - LDR R0, =UART2_ERR_DriverIRQHandler - BX R0 - ENDP - -UART3_RX_TX_IRQHandler\ - PROC - EXPORT UART3_RX_TX_IRQHandler [WEAK] - LDR R0, =UART3_RX_TX_DriverIRQHandler - BX R0 - ENDP - -UART3_ERR_IRQHandler\ - PROC - EXPORT UART3_ERR_IRQHandler [WEAK] - LDR R0, =UART3_ERR_DriverIRQHandler - BX R0 - ENDP - -SPI2_IRQHandler\ - PROC - EXPORT SPI2_IRQHandler [WEAK] - LDR R0, =SPI2_DriverIRQHandler - BX R0 - ENDP - -UART4_RX_TX_IRQHandler\ - PROC - EXPORT UART4_RX_TX_IRQHandler [WEAK] - LDR R0, =UART4_RX_TX_DriverIRQHandler - BX R0 - ENDP - -UART4_ERR_IRQHandler\ - PROC - EXPORT UART4_ERR_IRQHandler [WEAK] - LDR R0, =UART4_ERR_DriverIRQHandler - BX R0 - ENDP - -UART5_RX_TX_IRQHandler\ - PROC - EXPORT UART5_RX_TX_IRQHandler [WEAK] - LDR R0, =UART5_RX_TX_DriverIRQHandler - BX R0 - ENDP - -UART5_ERR_IRQHandler\ - PROC - EXPORT UART5_ERR_IRQHandler [WEAK] - LDR R0, =UART5_ERR_DriverIRQHandler - BX R0 - ENDP - -I2C2_IRQHandler\ - PROC - EXPORT I2C2_IRQHandler [WEAK] - LDR R0, =I2C2_DriverIRQHandler - BX R0 - ENDP - -CAN0_ORed_Message_buffer_IRQHandler\ - PROC - EXPORT CAN0_ORed_Message_buffer_IRQHandler [WEAK] - LDR R0, =CAN0_DriverIRQHandler - BX R0 - ENDP - -CAN0_Bus_Off_IRQHandler\ - PROC - EXPORT CAN0_Bus_Off_IRQHandler [WEAK] - LDR R0, =CAN0_DriverIRQHandler - BX R0 - ENDP - -CAN0_Error_IRQHandler\ - PROC - EXPORT CAN0_Error_IRQHandler [WEAK] - LDR R0, =CAN0_DriverIRQHandler - BX R0 - ENDP - -CAN0_Tx_Warning_IRQHandler\ - PROC - EXPORT CAN0_Tx_Warning_IRQHandler [WEAK] - LDR R0, =CAN0_DriverIRQHandler - BX R0 - ENDP - -CAN0_Rx_Warning_IRQHandler\ - PROC - EXPORT CAN0_Rx_Warning_IRQHandler [WEAK] - LDR R0, =CAN0_DriverIRQHandler - BX R0 - ENDP - -CAN0_Wake_Up_IRQHandler\ - PROC - EXPORT CAN0_Wake_Up_IRQHandler [WEAK] - LDR R0, =CAN0_DriverIRQHandler - BX R0 - ENDP - -SDHC_IRQHandler\ - PROC - EXPORT SDHC_IRQHandler [WEAK] - LDR R0, =SDHC_DriverIRQHandler - BX R0 - ENDP - -Default_Handler\ - PROC - EXPORT DMA0_DriverIRQHandler [WEAK] - EXPORT DMA1_DriverIRQHandler [WEAK] - EXPORT DMA2_DriverIRQHandler [WEAK] - EXPORT DMA3_DriverIRQHandler [WEAK] - EXPORT DMA4_DriverIRQHandler [WEAK] - EXPORT DMA5_DriverIRQHandler [WEAK] - EXPORT DMA6_DriverIRQHandler [WEAK] - EXPORT DMA7_DriverIRQHandler [WEAK] - EXPORT DMA8_DriverIRQHandler [WEAK] - EXPORT DMA9_DriverIRQHandler [WEAK] - EXPORT DMA10_DriverIRQHandler [WEAK] - EXPORT DMA11_DriverIRQHandler [WEAK] - EXPORT DMA12_DriverIRQHandler [WEAK] - EXPORT DMA13_DriverIRQHandler [WEAK] - EXPORT DMA14_DriverIRQHandler [WEAK] - EXPORT DMA15_DriverIRQHandler [WEAK] - EXPORT DMA_Error_DriverIRQHandler [WEAK] - EXPORT MCM_IRQHandler [WEAK] - EXPORT FTFE_IRQHandler [WEAK] - EXPORT Read_Collision_IRQHandler [WEAK] - EXPORT LVD_LVW_IRQHandler [WEAK] - EXPORT LLWU_IRQHandler [WEAK] - EXPORT WDOG_EWM_IRQHandler [WEAK] - EXPORT RNG_IRQHandler [WEAK] - EXPORT I2C0_DriverIRQHandler [WEAK] - EXPORT I2C1_DriverIRQHandler [WEAK] - EXPORT SPI0_DriverIRQHandler [WEAK] - EXPORT SPI1_DriverIRQHandler [WEAK] - EXPORT I2S0_Tx_DriverIRQHandler [WEAK] - EXPORT I2S0_Rx_DriverIRQHandler [WEAK] - EXPORT UART0_LON_DriverIRQHandler [WEAK] - EXPORT UART0_RX_TX_DriverIRQHandler [WEAK] - EXPORT UART0_ERR_DriverIRQHandler [WEAK] - EXPORT UART1_RX_TX_DriverIRQHandler [WEAK] - EXPORT UART1_ERR_DriverIRQHandler [WEAK] - EXPORT UART2_RX_TX_DriverIRQHandler [WEAK] - EXPORT UART2_ERR_DriverIRQHandler [WEAK] - EXPORT UART3_RX_TX_DriverIRQHandler [WEAK] - EXPORT UART3_ERR_DriverIRQHandler [WEAK] - EXPORT ADC0_IRQHandler [WEAK] - EXPORT CMP0_IRQHandler [WEAK] - EXPORT CMP1_IRQHandler [WEAK] - EXPORT FTM0_IRQHandler [WEAK] - EXPORT FTM1_IRQHandler [WEAK] - EXPORT FTM2_IRQHandler [WEAK] - EXPORT CMT_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT RTC_Seconds_IRQHandler [WEAK] - EXPORT PIT0_IRQHandler [WEAK] - EXPORT PIT1_IRQHandler [WEAK] - EXPORT PIT2_IRQHandler [WEAK] - EXPORT PIT3_IRQHandler [WEAK] - EXPORT PDB0_IRQHandler [WEAK] - EXPORT USB0_IRQHandler [WEAK] - EXPORT USBDCD_IRQHandler [WEAK] - EXPORT Reserved71_IRQHandler [WEAK] - EXPORT DAC0_IRQHandler [WEAK] - EXPORT MCG_IRQHandler [WEAK] - EXPORT LPTMR0_IRQHandler [WEAK] - EXPORT PORTA_IRQHandler [WEAK] - EXPORT PORTB_IRQHandler [WEAK] - EXPORT PORTC_IRQHandler [WEAK] - EXPORT PORTD_IRQHandler [WEAK] - EXPORT PORTE_IRQHandler [WEAK] - EXPORT SWI_IRQHandler [WEAK] - EXPORT SPI2_DriverIRQHandler [WEAK] - EXPORT UART4_RX_TX_DriverIRQHandler [WEAK] - EXPORT UART4_ERR_DriverIRQHandler [WEAK] - EXPORT UART5_RX_TX_DriverIRQHandler [WEAK] - EXPORT UART5_ERR_DriverIRQHandler [WEAK] - EXPORT CMP2_IRQHandler [WEAK] - EXPORT FTM3_IRQHandler [WEAK] - EXPORT DAC1_IRQHandler [WEAK] - EXPORT ADC1_IRQHandler [WEAK] - EXPORT I2C2_DriverIRQHandler [WEAK] - EXPORT CAN0_DriverIRQHandler [WEAK] - EXPORT SDHC_DriverIRQHandler [WEAK] - EXPORT Reserved98_IRQHandler [WEAK] - EXPORT Reserved99_IRQHandler [WEAK] - EXPORT Reserved100_IRQHandler [WEAK] - EXPORT Reserved101_IRQHandler [WEAK] - EXPORT DefaultISR [WEAK] -DMA0_DriverIRQHandler -DMA1_DriverIRQHandler -DMA2_DriverIRQHandler -DMA3_DriverIRQHandler -DMA4_DriverIRQHandler -DMA5_DriverIRQHandler -DMA6_DriverIRQHandler -DMA7_DriverIRQHandler -DMA8_DriverIRQHandler -DMA9_DriverIRQHandler -DMA10_DriverIRQHandler -DMA11_DriverIRQHandler -DMA12_DriverIRQHandler -DMA13_DriverIRQHandler -DMA14_DriverIRQHandler -DMA15_DriverIRQHandler -DMA_Error_DriverIRQHandler -MCM_IRQHandler -FTFE_IRQHandler -Read_Collision_IRQHandler -LVD_LVW_IRQHandler -LLWU_IRQHandler -WDOG_EWM_IRQHandler -RNG_IRQHandler -I2C0_DriverIRQHandler -I2C1_DriverIRQHandler -SPI0_DriverIRQHandler -SPI1_DriverIRQHandler -I2S0_Tx_DriverIRQHandler -I2S0_Rx_DriverIRQHandler -UART0_LON_DriverIRQHandler -UART0_RX_TX_DriverIRQHandler -UART0_ERR_DriverIRQHandler -UART1_RX_TX_DriverIRQHandler -UART1_ERR_DriverIRQHandler -UART2_RX_TX_DriverIRQHandler -UART2_ERR_DriverIRQHandler -UART3_RX_TX_DriverIRQHandler -UART3_ERR_DriverIRQHandler -ADC0_IRQHandler -CMP0_IRQHandler -CMP1_IRQHandler -FTM0_IRQHandler -FTM1_IRQHandler -FTM2_IRQHandler -CMT_IRQHandler -RTC_IRQHandler -RTC_Seconds_IRQHandler -PIT0_IRQHandler -PIT1_IRQHandler -PIT2_IRQHandler -PIT3_IRQHandler -PDB0_IRQHandler -USB0_IRQHandler -USBDCD_IRQHandler -Reserved71_IRQHandler -DAC0_IRQHandler -MCG_IRQHandler -LPTMR0_IRQHandler -PORTA_IRQHandler -PORTB_IRQHandler -PORTC_IRQHandler -PORTD_IRQHandler -PORTE_IRQHandler -SWI_IRQHandler -SPI2_DriverIRQHandler -UART4_RX_TX_DriverIRQHandler -UART4_ERR_DriverIRQHandler -UART5_RX_TX_DriverIRQHandler -UART5_ERR_DriverIRQHandler -CMP2_IRQHandler -FTM3_IRQHandler -DAC1_IRQHandler -ADC1_IRQHandler -I2C2_DriverIRQHandler -CAN0_DriverIRQHandler -SDHC_DriverIRQHandler -Reserved98_IRQHandler -Reserved99_IRQHandler -Reserved100_IRQHandler -Reserved101_IRQHandler -DefaultISR - B DefaultISR - ENDP - ALIGN - - - END
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/us_ticker.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K24F/us_ticker.c Tue Mar 20 16:56:18 2018 +0000
@@ -83,10 +83,14 @@
void us_ticker_set_interrupt(timestamp_t timestamp)
{
- uint32_t delta = timestamp - us_ticker_read();
+ uint32_t now_us, delta_us;
+
+ now_us = us_ticker_read();
+ delta_us = timestamp >= now_us ? timestamp - now_us : (uint32_t)((uint64_t)timestamp + 0xFFFFFFFF - now_us);
+
PIT_StopTimer(PIT, kPIT_Chnl_3);
PIT_StopTimer(PIT, kPIT_Chnl_2);
- PIT_SetTimerPeriod(PIT, kPIT_Chnl_3, (uint32_t)delta);
+ PIT_SetTimerPeriod(PIT, kPIT_Chnl_3, (uint32_t)delta_us);
PIT_EnableInterrupts(PIT, kPIT_Chnl_3, kPIT_TimerInterruptEnable);
PIT_StartTimer(PIT, kPIT_Chnl_3);
PIT_StartTimer(PIT, kPIT_Chnl_2);
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/us_ticker.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/us_ticker.c Tue Mar 20 16:56:18 2018 +0000
@@ -83,10 +83,14 @@
void us_ticker_set_interrupt(timestamp_t timestamp)
{
- uint32_t delta = timestamp - us_ticker_read();
+ uint32_t now_us, delta_us;
+
+ now_us = us_ticker_read();
+ delta_us = timestamp >= now_us ? timestamp - now_us : (uint32_t)((uint64_t)timestamp + 0xFFFFFFFF - now_us);
+
PIT_StopTimer(PIT, kPIT_Chnl_3);
PIT_StopTimer(PIT, kPIT_Chnl_2);
- PIT_SetTimerPeriod(PIT, kPIT_Chnl_3, (uint32_t)delta);
+ PIT_SetTimerPeriod(PIT, kPIT_Chnl_3, (uint32_t)delta_us);
PIT_EnableInterrupts(PIT, kPIT_Chnl_3, kPIT_TimerInterruptEnable);
PIT_StartTimer(PIT, kPIT_Chnl_3);
PIT_StartTimer(PIT, kPIT_Chnl_2);
--- a/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/lp_ticker.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/api/lp_ticker.c Tue Mar 20 16:56:18 2018 +0000
@@ -135,7 +135,7 @@
lptmr_schedule = 0;
now_us = lp_ticker_read();
- delta_us = timestamp > now_us ? timestamp - now_us : (uint32_t)((uint64_t)timestamp + 0xFFFFFFFF - now_us);
+ delta_us = timestamp >= now_us ? timestamp - now_us : (uint32_t)((uint64_t)timestamp + 0xFFFFFFFF - now_us);
/* Checking if LPTRM can handle this sleep */
delta_ticks = USEC_TO_COUNT(delta_us, CLOCK_GetFreq(kCLOCK_Er32kClk));
--- a/targets/TARGET_Maxim/TARGET_MAX32600/us_ticker.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32600/us_ticker.c Tue Mar 20 16:56:18 2018 +0000
@@ -236,7 +236,9 @@
void us_ticker_fire_interrupt(void)
{
- NVIC_SetPendingIRQ(US_TIMER_IRQn);
+ US_TIMER->ctrl &= ~MXC_F_TMR_CTRL_ENABLE0; // disable timer
+ US_TIMER->term_cnt32 = 1;
+ US_TIMER->ctrl |= MXC_F_TMR_CTRL_ENABLE0; // enable timer
}
//******************************************************************************
--- a/targets/TARGET_Maxim/TARGET_MAX32610/us_ticker.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32610/us_ticker.c Tue Mar 20 16:56:18 2018 +0000
@@ -236,7 +236,9 @@
void us_ticker_fire_interrupt(void)
{
- NVIC_SetPendingIRQ(US_TIMER_IRQn);
+ US_TIMER->ctrl &= ~MXC_F_TMR_CTRL_ENABLE0; // disable timer
+ US_TIMER->term_cnt32 = 1;
+ US_TIMER->ctrl |= MXC_F_TMR_CTRL_ENABLE0; // enable timer
}
//******************************************************************************
--- a/targets/TARGET_Maxim/TARGET_MAX32620/us_ticker.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32620/us_ticker.c Tue Mar 20 16:56:18 2018 +0000
@@ -267,7 +267,9 @@
void us_ticker_fire_interrupt(void)
{
- NVIC_SetPendingIRQ(US_TIMER_IRQn);
+ US_TIMER->ctrl &= ~MXC_F_TMR_CTRL_ENABLE0; // disable timer
+ US_TIMER->term_cnt32 = 1;
+ US_TIMER->ctrl |= MXC_F_TMR_CTRL_ENABLE0; // enable timer
}
//******************************************************************************
--- a/targets/TARGET_Maxim/TARGET_MAX32625/PeripheralPins.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32625/PeripheralPins.c Tue Mar 20 16:56:18 2018 +0000
@@ -163,6 +163,10 @@
{ AIN_3, ADC, ADC_CH_3 },
{ AIN_4, ADC, ADC_CH_0_DIV_5 },
{ AIN_5, ADC, ADC_CH_1_DIV_5 },
+ { AIN_6, ADC, ADC_CH_VDDB_DIV_4 },
+ { AIN_7, ADC, ADC_CH_VDD18 },
+ { AIN_8, ADC, ADC_CH_VDD12 },
+ { AIN_9, ADC, ADC_CH_VRTC_DIV_2 },
{ NC, NC, 0 }
};
--- a/targets/TARGET_Maxim/TARGET_MAX32625/TARGET_MAX32625MBED/PinNames.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32625/TARGET_MAX32625MBED/PinNames.h Tue Mar 20 16:56:18 2018 +0000
@@ -60,7 +60,7 @@
P4_0 = (4 << PORT_SHIFT), P4_1, P4_2, P4_3, P4_4, P4_5, P4_6, P4_7,
// Analog input pins
- AIN_0 = (0xA << PORT_SHIFT), AIN_1, AIN_2, AIN_3, AIN_4, AIN_5,
+ AIN_0 = (0xA << PORT_SHIFT), AIN_1, AIN_2, AIN_3, AIN_4, AIN_5, AIN_6, AIN_7, AIN_8, AIN_9,
LED_GREEN = P3_1,
LED_RED = P3_0,
--- a/targets/TARGET_Maxim/TARGET_MAX32625/TARGET_MAX32625NEXPAQ/PinNames.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32625/TARGET_MAX32625NEXPAQ/PinNames.h Tue Mar 20 16:56:18 2018 +0000
@@ -60,7 +60,7 @@
P4_0 = (4 << PORT_SHIFT), P4_1, P4_2, P4_3, P4_4, P4_5, P4_6, P4_7,
// Analog input pins
- AIN_0 = (0xA << PORT_SHIFT), AIN_1, AIN_2, AIN_3, AIN_4, AIN_5,
+ AIN_0 = (0xA << PORT_SHIFT), AIN_1, AIN_2, AIN_3, AIN_4, AIN_5, AIN_6, AIN_7, AIN_8, AIN_9,
// LEDs
LED1 = P2_4,
--- a/targets/TARGET_Maxim/TARGET_MAX32625/analogin_api.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32625/analogin_api.c Tue Mar 20 16:56:18 2018 +0000
@@ -65,7 +65,7 @@
float result;
// Start conversion with no input scaling and no input buffer bypass
- ADC_StartConvert(obj->channel, 0, 0);
+ ADC_StartConvert(obj->channel, 1, 0);
if (ADC_GetData(&tmp) == E_OVERFLOW) {
result = FLOAT_FULL_SCALE;
@@ -83,7 +83,7 @@
uint16_t result;
// Start conversion with no input scaling and no input buffer bypass
- ADC_StartConvert(obj->channel, 0, 0);
+ ADC_StartConvert(obj->channel, 1, 0);
if (ADC_GetData(&tmp) == E_OVERFLOW) {
result = INT_FULL_SCALE;
--- a/targets/TARGET_Maxim/TARGET_MAX32625/i2c_api.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32625/i2c_api.c Tue Mar 20 16:56:18 2018 +0000
@@ -101,7 +101,6 @@
//******************************************************************************
int i2c_read(i2c_t *obj, int address, char *data, int length, int stop)
{
- MBED_ASSERT(stop != 0);
return I2CM_Read(obj->i2c, address >> 1, NULL, 0, (uint8_t *)data, length);
}
@@ -147,11 +146,6 @@
if (I2CM_WriteTxFifo(i2cm, fifo, MXC_S_I2CM_TRANS_TAG_RXDATA_NACK) != E_NO_ERROR) {
goto byte_write_err;
}
-
- // Send the stop condition
- if (I2CM_WriteTxFifo(i2cm, fifo, MXC_S_I2CM_TRANS_TAG_STOP) != E_NO_ERROR) {
- goto byte_write_err;
- }
} else {
if (I2CM_WriteTxFifo(i2cm, fifo, MXC_S_I2CM_TRANS_TAG_RXDATA_COUNT) != E_NO_ERROR) {
goto byte_write_err;
--- a/targets/TARGET_Maxim/TARGET_MAX32625/serial_api.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32625/serial_api.c Tue Mar 20 16:56:18 2018 +0000
@@ -48,8 +48,8 @@
MXC_F_UART_INTFL_RX_FIFO_OVERFLOW)
// Variables for managing the stdio UART
-int stdio_uart_inited;
-serial_t stdio_uart;
+int stdio_uart_inited = 0;
+serial_t stdio_uart = {0};
// Variables for interrupt driven
static uart_irq_handler irq_handler;
@@ -75,12 +75,6 @@
obj->index = MXC_UART_GET_IDX(obj->uart);
obj->fifo = (mxc_uart_fifo_regs_t*)MXC_UART_GET_BASE_FIFO(obj->index);
- // Manage stdio UART
- if (uart == STDIO_UART) {
- stdio_uart_inited = 1;
- memcpy(&stdio_uart, obj, sizeof(serial_t));
- }
-
// Record the pins requested
obj->tx = tx;
obj->rx = rx;
@@ -111,6 +105,12 @@
obj->cfg.size = UART_DATA_SIZE_8_BITS;
obj->cfg.parity = UART_PARITY_DISABLE;
+ // Manage stdio UART
+ if (uart == STDIO_UART) {
+ stdio_uart_inited = 1;
+ stdio_uart = *obj;
+ }
+
int retval = UART_Init(obj->uart, &obj->cfg, &obj->sys_cfg);
MBED_ASSERT(retval == E_NO_ERROR);
}
@@ -181,7 +181,16 @@
void uart_handler(serial_t *obj)
{
if (obj && obj->id) {
- irq_handler(obj->id, RxIrq);
+ // Check for errors or RX Threshold
+ if (obj->uart->intfl & (MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY | UART_ERRORS)) {
+ irq_handler(obj->id, RxIrq);
+ obj->uart->intfl = (MXC_F_UART_INTFL_RX_FIFO_NOT_EMPTY | UART_ERRORS);
+ }
+ // Check for TX Threshold
+ if (obj->uart->intfl & MXC_F_UART_INTFL_TX_FIFO_AE) {
+ irq_handler(obj->id, TxIrq);
+ obj->uart->intfl = MXC_F_UART_INTFL_TX_FIFO_AE;
+ }
}
}
@@ -199,6 +208,9 @@
//******************************************************************************
void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
{
+ MBED_ASSERT(obj->index < MXC_CFG_UART_INSTANCES);
+ objs[obj->index] = obj;
+
switch (obj->index) {
case 0:
NVIC_SetVector(UART0_IRQn, (uint32_t)uart0_handler);
@@ -250,7 +262,7 @@
//******************************************************************************
int serial_getc(serial_t *obj)
{
- int c = 0;
+ int c = -1;
if (obj->rx != NC) {
// Wait for data to be available
--- a/targets/TARGET_Maxim/TARGET_MAX32625/spi_api.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32625/spi_api.c Tue Mar 20 16:56:18 2018 +0000
@@ -167,19 +167,58 @@
return *req.rx_data;
}
-int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length,
- char *rx_buffer, int rx_length, char write_fill) {
- int total = (tx_length > rx_length) ? tx_length : rx_length;
+//******************************************************************************
+int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, char write_fill)
+{
+ spim_req_t req;
+
+ if (!(tx_length | rx_length) ||
+ (tx_length < 0) ||
+ (rx_length < 0)) {
+ return 0;
+ }
+
+ req.width = SPIM_WIDTH_1;
+ req.ssel = 0;
+ req.deass = 1;
+ req.callback = NULL;
- for (int i = 0; i < total; i++) {
- char out = (i < tx_length) ? tx_buffer[i] : write_fill;
- char in = spi_master_write(obj, out);
- if (i < rx_length) {
- rx_buffer[i] = in;
+ core_util_critical_section_enter();
+ if (tx_length == rx_length) {
+ req.tx_data = (uint8_t *)tx_buffer;
+ req.rx_data = (uint8_t *)rx_buffer;
+ req.len = tx_length;
+ SPIM_Trans(obj->spi, &req);
+ } else if (tx_length < rx_length) {
+ req.tx_data = (tx_length > 0) ? (uint8_t *)tx_buffer : NULL;
+ req.rx_data = (uint8_t *)rx_buffer;
+ req.len = (tx_length > 0) ? tx_length : rx_length;
+ SPIM_Trans(obj->spi, &req);
+
+ if (tx_length) {
+ req.tx_data = NULL;
+ req.rx_data = (uint8_t *)(rx_buffer + tx_length);
+ req.len = rx_length - tx_length;
+ SPIM_Trans(obj->spi, &req);
+ }
+ } else {
+ req.tx_data = (uint8_t *)tx_buffer;
+ req.rx_data = (rx_length > 0) ? (uint8_t *)rx_buffer : NULL;
+ req.len = (rx_length > 0) ? rx_length : tx_length;
+ SPIM_Trans(obj->spi, &req);
+
+ if (rx_length) {
+ req.tx_data = (uint8_t *)(tx_buffer + rx_length);
+ req.rx_data = NULL;
+ req.len = tx_length - rx_length;
+ SPIM_Trans(obj->spi, &req);
}
}
+ core_util_critical_section_exit();
- return total;
+ while (SPIM_Busy(obj->spi));
+
+ return tx_length > rx_length ? tx_length : rx_length;
}
//******************************************************************************
@@ -193,4 +232,3 @@
{
return obj->index;
}
-
--- a/targets/TARGET_Maxim/TARGET_MAX32625/us_ticker.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32625/us_ticker.c Tue Mar 20 16:56:18 2018 +0000
@@ -33,9 +33,11 @@
#include <stddef.h>
#include "mbed_error.h"
+#include "mbed_critical.h"
#include "us_ticker_api.h"
#include "PeripheralNames.h"
#include "tmr.h"
+#include "assert.h"
#define US_TIMER MXC_TMR0
#define US_TIMER_IRQn TMR0_0_IRQn
@@ -49,7 +51,7 @@
#define MAX_TICK_VAL ((uint64_t)0xFFFFFFFF * ticks_per_us)
//******************************************************************************
-static inline void inc_current_cnt(uint32_t inc)
+static inline void inc_current_cnt_no_crit(uint32_t inc)
{
// Overflow the ticker when the us ticker overflows
current_cnt += inc;
@@ -59,6 +61,14 @@
}
//******************************************************************************
+static inline void inc_current_cnt(uint32_t inc)
+{
+ core_util_critical_section_enter();
+ inc_current_cnt_no_crit(inc);
+ core_util_critical_section_exit();
+}
+
+//******************************************************************************
static inline int event_passed(uint64_t current, uint64_t event)
{
// Determine if the event has already happened.
@@ -89,11 +99,12 @@
{
uint32_t cmp = TMR32_GetCompare(US_TIMER);
TMR32_SetCompare(US_TIMER, 0xFFFFFFFF); // reset to max value to prevent further interrupts
+ if (TMR32_GetFlag(US_TIMER)) {
+ inc_current_cnt_no_crit(cmp);
+ }
TMR32_ClearFlag(US_TIMER);
NVIC_ClearPendingIRQ(US_TIMER_IRQn);
- inc_current_cnt(cmp);
-
if (event_passed(current_cnt + TMR32_GetCount(US_TIMER), event_cnt)) {
// the timestamp has expired
event_cnt = 0xFFFFFFFFFFFFFFFFULL; // reset to max value
@@ -162,6 +173,7 @@
uint64_t current_cnt1, current_cnt2;
uint32_t cmp, cnt;
uint32_t flag1, flag2;
+ static uint32_t last = 0;
if (!us_ticker_inited) {
us_ticker_init();
@@ -179,12 +191,19 @@
// Account for an unserviced interrupt
if (flag1) {
+ // Clear peripheral interrupt flag; leaving NVIC pending set
+ TMR32_ClearFlag(US_TIMER);
+ // Advance global count
+ inc_current_cnt(cmp + cnt);
+
current_cnt1 += cmp;
}
current_cnt1 += cnt;
- return (current_cnt1 / ticks_per_us);
+ assert(last <= (current_cnt1 / ticks_per_us));
+ last = (current_cnt1 / ticks_per_us);
+ return last;
}
//******************************************************************************
@@ -228,9 +247,10 @@
TMR32_Start(US_TIMER);
}
+//******************************************************************************
void us_ticker_fire_interrupt(void)
{
- NVIC_SetPendingIRQ(US_TIMER_IRQn);
+ TMR32_SetCompare(US_TIMER, 1);
}
//******************************************************************************
--- a/targets/TARGET_Maxim/TARGET_MAX32630/us_ticker.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_Maxim/TARGET_MAX32630/us_ticker.c Tue Mar 20 16:56:18 2018 +0000
@@ -230,7 +230,7 @@
void us_ticker_fire_interrupt(void)
{
- NVIC_SetPendingIRQ(US_TIMER_IRQn);
+ TMR32_SetCompare(US_TIMER, 1);
}
//******************************************************************************
--- a/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/us_ticker.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NORDIC/TARGET_MCU_NRF51822/us_ticker.c Tue Mar 20 16:56:18 2018 +0000
@@ -20,6 +20,7 @@
#include "PeripheralNames.h"
#include "nrf_delay.h"
#include "mbed_toolchain.h"
+#include "mbed_critical.h"
/*
* Note: The micro-second timer API on the nRF51 platform is implemented using
@@ -52,6 +53,8 @@
#define RTC_UNITS_TO_MICROSECONDS(RTC_UNITS) (((RTC_UNITS) * (uint64_t)1000000) / RTC_CLOCK_FREQ)
#define MICROSECONDS_TO_RTC_UNITS(MICROS) ((((uint64_t)(MICROS) * RTC_CLOCK_FREQ) + 999999) / 1000000)
+#define US_TICKER_SW_IRQ_MASK 0x1
+
static bool us_ticker_inited = false;
static volatile uint32_t overflowCount; /**< The number of times the 24-bit RTC counter has overflowed. */
static volatile bool us_ticker_callbackPending = false;
@@ -62,6 +65,9 @@
*/
static uint32_t previous_tick_cc_value = 0;
+// us ticker fire interrupt flag for IRQ handler
+volatile uint8_t m_common_sw_irq_flag = 0;
+
/*
RTX provide the following definitions which are used by the tick code:
* os_trv: The number (minus 1) of clock cycle between two tick.
@@ -181,6 +187,11 @@
*/
void us_ticker_handler(void)
{
+ if (m_common_sw_irq_flag & US_TICKER_SW_IRQ_MASK) {
+ m_common_sw_irq_flag &= ~US_TICKER_SW_IRQ_MASK;
+ us_ticker_irq_handler();
+ }
+
if (NRF_RTC1->EVENTS_OVRFLW) {
overflowCount++;
NRF_RTC1->EVENTS_OVRFLW = 0;
@@ -287,7 +298,10 @@
void us_ticker_fire_interrupt(void)
{
+ core_util_critical_section_enter();
+ m_common_sw_irq_flag |= US_TICKER_SW_IRQ_MASK;
NVIC_SetPendingIRQ(RTC1_IRQn);
+ core_util_critical_section_exit();
}
void us_ticker_disable_interrupt(void)
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TARGET_OSHCHIP/PinNames.h Tue Mar 20 16:56:18 2018 +0000
@@ -0,0 +1,216 @@
+/*
+ * Copyright (c) 2013 Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
+ * integrated circuit in a product or a software update for such product, must reproduce
+ * the above copyright notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
+ * used to endorse or promote products derived from this software without specific prior
+ * written permission.
+ *
+ * 4. This software, with or without modification, must only be used with a
+ * Nordic Semiconductor ASA integrated circuit.
+ *
+ * 5. Any software provided in binary or object form under this license must not be reverse
+ * engineered, decompiled, modified and/or disassembled.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PIN_INPUT,
+ PIN_OUTPUT
+} PinDirection;
+
+#define PORT_SHIFT 3
+
+typedef enum {
+ p0 = 0,
+ p1 = 1,
+ p2 = 2,
+ p3 = 3,
+ p4 = 4,
+ p5 = 5,
+ p6 = 6,
+ p7 = 7,
+ p8 = 8,
+ p9 = 9,
+ p10 = 10,
+ p11 = 11,
+ p12 = 12,
+ p13 = 13,
+ p14 = 14,
+ p15 = 15,
+ p16 = 16,
+ p17 = 17,
+ p18 = 18,
+ p19 = 19,
+ p20 = 20,
+ p21 = 21,
+ p22 = 22,
+ p23 = 23,
+ p24 = 24,
+ p25 = 25,
+ p26 = 26,
+ p27 = 27,
+ p28 = 28,
+ p29 = 29,
+ p30 = 30,
+
+ P0_0 = p0,
+ P0_1 = p1,
+ P0_2 = p2,
+ P0_3 = p3,
+ P0_4 = p4,
+ P0_5 = p5,
+ P0_6 = p6,
+ P0_7 = p7,
+
+ P0_8 = p8,
+ P0_9 = p9,
+ P0_10 = p10,
+ P0_11 = p11,
+ P0_12 = p12,
+ P0_13 = p13,
+ P0_14 = p14,
+ P0_15 = p15,
+
+ P0_16 = p16,
+ P0_17 = p17,
+ P0_18 = p18,
+ P0_19 = p19,
+ P0_20 = p20,
+ P0_21 = p21,
+ P0_22 = p22,
+ P0_23 = p23,
+
+ P0_24 = p24,
+ P0_25 = p25,
+ P0_26 = p26,
+ P0_27 = p27,
+ P0_28 = p28,
+ P0_29 = p29,
+ P0_30 = p30,
+ /*
+ ââââââââââââ
+UARTâ¬ââ TX D0 â¶â¨ 1 ââ 16 â â´ VCC
+ âââ RX D1 â¶â¨ 2 ââ 15 â â´ D8 SCL ââ¬I²C
+ D2 â¶â¨ 3 14 â â´ D7 SDA ââ
+ SPI⬠MOSI D3 â¶â¨ 4 13 â â´ A0
+ â MISO D4 â¶â¨ 5 ââââ12 â â´ A1
+ â SEL D5 â¶â¨ 6 ââââ11 â â´ D9 AREF
+ ââ CLK D4 â¶â¨ 7 10 â â´ A2
+ GND â¶â¨ 8 :: 9 â â´ A3
+ ââââââââââââ
+ */
+
+ OSHCHIP_PIN_1 = p20,
+ OSHCHIP_PIN_2 = p18,
+ OSHCHIP_PIN_3 = p16,
+ OSHCHIP_PIN_4 = p15,
+ OSHCHIP_PIN_5 = p12,
+ OSHCHIP_PIN_6 = p11,
+ OSHCHIP_PIN_7 = p9,
+ OSHCHIP_PIN_9 = p1,
+ OSHCHIP_PIN_10 = p2,
+ OSHCHIP_PIN_11 = p0,
+ OSHCHIP_PIN_12 = p27,
+ OSHCHIP_PIN_13 = p26,
+ OSHCHIP_PIN_14 = p24,
+ OSHCHIP_PIN_15 = p21,
+
+ LED1 = p8,
+ LED2 = p5,
+ LED3 = p3,
+
+ LED_RED = LED1,
+ LED_GREEN = LED2,
+ LED_BLUE = LED3,
+
+ RX_PIN_NUMBER = OSHCHIP_PIN_2,
+ TX_PIN_NUMBER = OSHCHIP_PIN_1,
+ CTS_PIN_NUMBER = (int)0xFFFFFFFF, //no connection
+ RTS_PIN_NUMBER = (int)0xFFFFFFFF, //no connection
+
+ // mBed interface Pins
+ USBTX = TX_PIN_NUMBER,
+ USBRX = RX_PIN_NUMBER,
+
+ SPI_PSELMOSI0 = OSHCHIP_PIN_4,
+ SPI_PSELMISO0 = OSHCHIP_PIN_5,
+ SPI_PSELSS0 = OSHCHIP_PIN_6,
+ SPI_PSELSCK0 = OSHCHIP_PIN_7,
+
+ SPI_PSELMOSI1 = OSHCHIP_PIN_4,
+ SPI_PSELMISO1 = OSHCHIP_PIN_5,
+ SPI_PSELSS1 = OSHCHIP_PIN_6,
+ SPI_PSELSCK1 = OSHCHIP_PIN_7,
+
+ SPIS_PSELMOSI = OSHCHIP_PIN_4,
+ SPIS_PSELMISO = OSHCHIP_PIN_5,
+ SPIS_PSELSS = OSHCHIP_PIN_6,
+ SPIS_PSELSCK = OSHCHIP_PIN_7,
+
+ I2C_SDA0 = OSHCHIP_PIN_14,
+ I2C_SCL0 = OSHCHIP_PIN_15,
+
+ D0 = OSHCHIP_PIN_1,
+ D1 = OSHCHIP_PIN_2,
+ D2 = OSHCHIP_PIN_3,
+ D3 = OSHCHIP_PIN_4,
+ D4 = OSHCHIP_PIN_5,
+ D5 = OSHCHIP_PIN_6,
+ D6 = OSHCHIP_PIN_7,
+ D7 = OSHCHIP_PIN_15,
+ D8 = OSHCHIP_PIN_14,
+ D9 = OSHCHIP_PIN_11,
+
+ A0 = OSHCHIP_PIN_13,
+ A1 = OSHCHIP_PIN_12,
+ A2 = OSHCHIP_PIN_10,
+ A3 = OSHCHIP_PIN_9,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF
+} PinName;
+
+typedef enum {
+ PullNone = 0,
+ PullDown = 1,
+ PullUp = 3,
+ PullDefault = PullUp
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF51822_UNIFIED/TARGET_OSHCHIP/device.h Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,23 @@ +// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. +// Check the 'features' section of the target description in 'targets.json' for more details. +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#include "objects.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_MTB_LAIRD_BL652/PinNames.h Tue Mar 20 16:56:18 2018 +0000
@@ -0,0 +1,243 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2013 Nordic Semiconductor
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ PIN_INPUT,
+ PIN_OUTPUT
+} PinDirection;
+
+#define PORT_SHIFT 3
+
+typedef enum {
+ p0 = 0,
+ p1 = 1,
+ p2 = 2,
+ p3 = 3,
+ p4 = 4,
+ p5 = 5,
+ p6 = 6,
+ p7 = 7,
+ p8 = 8,
+ p9 = 9,
+ p10 = 10,
+ p11 = 11,
+ p12 = 12,
+ p13 = 13,
+ p14 = 14,
+ p15 = 15,
+ p16 = 16,
+ p17 = 17,
+ p18 = 18,
+ p19 = 19,
+ p20 = 20,
+ p21 = 21,
+ p22 = 22,
+ p23 = 23,
+ p24 = 24,
+ p25 = 25,
+ p26 = 26,
+ p27 = 27,
+ p28 = 28,
+ p29 = 29,
+ p30 = 30,
+ p31 = 31,
+
+
+ P0_0 = p0,
+ P0_1 = p1,
+ P0_2 = p2,
+ P0_3 = p3,
+ P0_4 = p4,
+ P0_5 = p5,
+ P0_6 = p6,
+ P0_7 = p7,
+
+ P0_8 = p8,
+ P0_9 = p9,
+ P0_10 = p10,
+ P0_11 = p11,
+ P0_12 = p12,
+ P0_13 = p13,
+ P0_14 = p14,
+ P0_15 = p15,
+
+ P0_16 = p16,
+ P0_17 = p17,
+ P0_18 = p18,
+ P0_19 = p19,
+ P0_20 = p20,
+ P0_21 = p21,
+ P0_22 = p22,
+ P0_23 = p23,
+
+ P0_24 = p24,
+ P0_25 = p25,
+ P0_26 = p26,
+ P0_27 = p27,
+ P0_28 = p28,
+ P0_29 = p29,
+ P0_30 = p30,
+ P0_31 = p31,
+
+ // Module pins. Refer datasheet for pin numbers.
+ SIO_1 = P0_1,
+ SIO_2 = P0_2,
+ SIO_3 = P0_3,
+ SIO_4 = P0_4,
+ SIO_5 = P0_5,
+ SIO_6 = P0_6,
+ SIO_7 = P0_7,
+ SIO_8 = P0_8,
+ SIO_9 = P0_9, //NFC1
+ SIO_10 = P0_10, //NFC2
+ SIO_11 = P0_11,
+ SIO_12 = P0_12,
+ SIO_13 = P0_13,
+ SIO_14 = P0_14,
+ SIO_15 = P0_15,
+ SIO_16 = P0_16,
+ SIO_17 = P0_17,
+ SIO_18 = P0_18,
+ SIO_19 = P0_19,
+ SIO_20 = P0_20,
+
+ SIO_22 = P0_22,
+ SIO_23 = P0_23,
+ SIO_24 = P0_24,
+ SIO_25 = P0_25,
+ SIO_26 = P0_26,
+ SIO_27 = P0_27,
+ SIO_28 = P0_28,
+ SIO_29 = P0_29,
+ SIO_30 = P0_30,
+ SIO_31 = P0_31,
+ SIO_0 = P0_0,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF,
+
+ //Mbed MTB pin defines.
+ P_1 = NC,
+ P_2 = SIO_24, //MISO
+ P_3 = SIO_23, //MOSI
+ P_4 = SIO_22,
+// P_5 = SWDIO,
+// P_6 = SWDCLK,
+// P_7 = NRST,
+ P_8 = SIO_20,
+ P_9 = SIO_18,
+ P_10 = SIO_16,
+ P_11 = SIO_14,
+ P_12 = SIO_12,
+ P_13 = SIO_11,
+ P_14 = SIO_10,
+ P_15 = SIO_9,
+ P_16 = NC,
+ P_17 = SIO_8,
+ P_18 = SIO_7,
+ P_19 = SIO_6,
+ P_20 = SIO_5,
+ P_21 = SIO_4,
+ P_22 = SIO_3,
+ P_23 = SIO_2,
+ P_24 = SIO_1,
+ P_25 = SIO_0,
+ P_26 = NC,
+ P_27 = NC,
+ P_28 = SIO_13,
+ P_29 = SIO_15,
+ P_30 = SIO_17,
+ P_31 = SIO_19,
+ P_32 = SIO_31,
+ P_33 = SIO_30,
+ P_34 = SIO_29,
+ P_35 = SIO_28,
+ P_36 = SIO_27,
+ P_37 = SIO_26,
+ P_38 = SIO_25,
+ P_39 = NC,
+
+ //LEDs
+ LED1 = SIO_28,
+ LED2 = SIO_29,
+ LED3 = SIO_30,
+ LED_RED = LED1,
+ LED_GREEN = LED2,
+ LED_BLUE = LED3,
+
+ GP0 = SIO_11,
+ //Standardized button name
+ BUTTON1 = GP0,
+
+ //Nordic SDK pin names
+ RX_PIN_NUMBER = SIO_8,
+ TX_PIN_NUMBER = SIO_6,
+ CTS_PIN_NUMBER = SIO_7,
+ RTS_PIN_NUMBER = SIO_5,
+
+ // mBed interface Pins
+ USBTX = TX_PIN_NUMBER,
+ USBRX = RX_PIN_NUMBER,
+
+ SPI_MOSI = SIO_23,
+ SPI_MISO = SIO_24,
+ SPI_SS0 = SIO_17, //CS for LCD on MTB
+ SPI_SS1 = SIO_10, //CS for SD card on MTB
+ SPI_SCK1 = SIO_25,
+ SPI_SCK2 = SIO_31,
+
+ //Default SPI
+ SPI_SCK = SPI_SCK1,
+ SPI_CS = SPI_SS1,
+
+ I2C_SDA = SIO_26,
+ I2C_SCL = SIO_27,
+
+ //MTB aliases
+ GP1 = SIO_13,
+ AIN0 = SIO_2,
+ AIN1 = SIO_3,
+ AIN2 = SIO_4,
+ GP2 = SIO_10,
+ GP3 = SIO_9,
+ GP4 = SIO_22,
+ GP5 = SIO_19, //A0 for LCD on MTB
+ GP6 = SIO_18, //RESET for LCD on MTB
+ GP7 = SIO_17,
+ GP8 = SIO_15,
+
+} PinName;
+
+typedef enum {
+ PullNone = 0,
+ PullDown = 1,
+ PullUp = 3,
+ PullDefault = PullUp
+} PinMode;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/TARGET_MTB_LAIRD_BL652/device.h Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,23 @@ +// The 'features' section in 'target.json' is now used to create the device's hardware preprocessor switches. +// Check the 'features' section of the target description in 'targets.json' for more details. +/* mbed Microcontroller Library + * Copyright (c) 2006-2013 ARM Limited + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ +#ifndef MBED_DEVICE_H +#define MBED_DEVICE_H + +#include "objects.h" + +#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/device/TOOLCHAIN_ARM_STD/startup_nrf52832.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,245 @@ +;/* Copyright (c) 2012 ARM LIMITED +; +; All rights reserved. +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; - Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; - Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; - Neither the name of ARM nor the names of its contributors may be used +; to endorse or promote products derived from this software without +; specific prior written permission. +; * +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +; ---------------------------------------------------------------------------*/ + +__initial_sp EQU 0x20010000 + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler + DCD NMI_Handler + DCD HardFault_Handler + DCD MemoryManagement_Handler + DCD BusFault_Handler + DCD UsageFault_Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler + DCD DebugMonitor_Handler + DCD 0 ; Reserved + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD POWER_CLOCK_IRQHandler + DCD RADIO_IRQHandler + DCD UARTE0_UART0_IRQHandler_v + DCD SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v + DCD SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v + DCD NFCT_IRQHandler_v + DCD GPIOTE_IRQHandler_v + DCD SAADC_IRQHandler_v + DCD TIMER0_IRQHandler_v + DCD TIMER1_IRQHandler_v + DCD TIMER2_IRQHandler_v + DCD RTC0_IRQHandler + DCD TEMP_IRQHandler_v + DCD RNG_IRQHandler + DCD ECB_IRQHandler + DCD CCM_AAR_IRQHandler + DCD WDT_IRQHandler_v + DCD RTC1_IRQHandler_v + DCD QDEC_IRQHandler_v + DCD COMP_LPCOMP_IRQHandler_v + DCD SWI0_EGU0_IRQHandler_v + DCD SWI1_EGU1_IRQHandler_v + DCD SWI2_EGU2_IRQHandler_v + DCD SWI3_EGU3_IRQHandler_v + DCD SWI4_EGU4_IRQHandler + DCD SWI5_EGU5_IRQHandler + DCD TIMER3_IRQHandler_v + DCD TIMER4_IRQHandler_v + DCD PWM0_IRQHandler_v + DCD PDM_IRQHandler_v + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD MWU_IRQHandler + DCD PWM1_IRQHandler_v + DCD PWM2_IRQHandler_v + DCD SPIM2_SPIS2_SPI2_IRQHandler_v + DCD RTC2_IRQHandler_v + DCD I2S_IRQHandler_v + DCD FPU_IRQHandler_v + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset Handler + + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + IMPORT nrf_reloc_vector_table + + + LDR R0, =SystemInit + BLX R0 + LDR R0, =nrf_reloc_vector_table + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemoryManagement_Handler\ + PROC + EXPORT MemoryManagement_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMonitor_Handler\ + PROC + EXPORT DebugMonitor_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT POWER_CLOCK_IRQHandler [WEAK] + EXPORT RADIO_IRQHandler [WEAK] + EXPORT UARTE0_UART0_IRQHandler_v [WEAK] + EXPORT SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v [WEAK] + EXPORT SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v [WEAK] + EXPORT NFCT_IRQHandler_v [WEAK] + EXPORT GPIOTE_IRQHandler_v [WEAK] + EXPORT SAADC_IRQHandler_v [WEAK] + EXPORT TIMER0_IRQHandler_v [WEAK] + EXPORT TIMER1_IRQHandler_v [WEAK] + EXPORT TIMER2_IRQHandler_v [WEAK] + EXPORT RTC0_IRQHandler [WEAK] + EXPORT TEMP_IRQHandler_v [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT ECB_IRQHandler [WEAK] + EXPORT CCM_AAR_IRQHandler [WEAK] + EXPORT WDT_IRQHandler_v [WEAK] + EXPORT RTC1_IRQHandler_v [WEAK] + EXPORT QDEC_IRQHandler_v [WEAK] + EXPORT COMP_LPCOMP_IRQHandler_v [WEAK] + EXPORT SWI0_EGU0_IRQHandler_v [WEAK] + EXPORT SWI1_EGU1_IRQHandler_v [WEAK] + EXPORT SWI2_EGU2_IRQHandler_v [WEAK] + EXPORT SWI3_EGU3_IRQHandler_v [WEAK] + EXPORT SWI4_EGU4_IRQHandler [WEAK] + EXPORT SWI5_EGU5_IRQHandler [WEAK] + EXPORT TIMER3_IRQHandler_v [WEAK] + EXPORT TIMER4_IRQHandler_v [WEAK] + EXPORT PWM0_IRQHandler_v [WEAK] + EXPORT PDM_IRQHandler_v [WEAK] + EXPORT MWU_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler_v [WEAK] + EXPORT PWM2_IRQHandler_v [WEAK] + EXPORT SPIM2_SPIS2_SPI2_IRQHandler_v [WEAK] + EXPORT RTC2_IRQHandler_v [WEAK] + EXPORT I2S_IRQHandler_v [WEAK] + EXPORT FPU_IRQHandler_v [WEAK] +POWER_CLOCK_IRQHandler +RADIO_IRQHandler +UARTE0_UART0_IRQHandler_v +SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v +SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v +NFCT_IRQHandler_v +GPIOTE_IRQHandler_v +SAADC_IRQHandler_v +TIMER0_IRQHandler_v +TIMER1_IRQHandler_v +TIMER2_IRQHandler_v +RTC0_IRQHandler +TEMP_IRQHandler_v +RNG_IRQHandler +ECB_IRQHandler +CCM_AAR_IRQHandler +WDT_IRQHandler_v +RTC1_IRQHandler_v +QDEC_IRQHandler_v +COMP_LPCOMP_IRQHandler_v +SWI0_EGU0_IRQHandler_v +SWI1_EGU1_IRQHandler_v +SWI2_EGU2_IRQHandler_v +SWI3_EGU3_IRQHandler_v +SWI4_EGU4_IRQHandler +SWI5_EGU5_IRQHandler +TIMER3_IRQHandler_v +TIMER4_IRQHandler_v +PWM0_IRQHandler_v +PDM_IRQHandler_v +MWU_IRQHandler +PWM1_IRQHandler_v +PWM2_IRQHandler_v +SPIM2_SPIS2_SPI2_IRQHandler_v +RTC2_IRQHandler_v +I2S_IRQHandler_v +FPU_IRQHandler_v + B . + ENDP + ALIGN + END
--- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/device/TOOLCHAIN_ARM_STD/startup_nrf52832.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,245 +0,0 @@ -;/* Copyright (c) 2012 ARM LIMITED -; -; All rights reserved. -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; - Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; - Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; - Neither the name of ARM nor the names of its contributors may be used -; to endorse or promote products derived from this software without -; specific prior written permission. -; * -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE -; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; POSSIBILITY OF SUCH DAMAGE. -; ---------------------------------------------------------------------------*/ - -__initial_sp EQU 0x20010000 - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler - DCD NMI_Handler - DCD HardFault_Handler - DCD MemoryManagement_Handler - DCD BusFault_Handler - DCD UsageFault_Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler - DCD DebugMonitor_Handler - DCD 0 ; Reserved - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD POWER_CLOCK_IRQHandler - DCD RADIO_IRQHandler - DCD UARTE0_UART0_IRQHandler_v - DCD SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v - DCD SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v - DCD NFCT_IRQHandler_v - DCD GPIOTE_IRQHandler_v - DCD SAADC_IRQHandler_v - DCD TIMER0_IRQHandler_v - DCD TIMER1_IRQHandler_v - DCD TIMER2_IRQHandler_v - DCD RTC0_IRQHandler - DCD TEMP_IRQHandler_v - DCD RNG_IRQHandler - DCD ECB_IRQHandler - DCD CCM_AAR_IRQHandler - DCD WDT_IRQHandler_v - DCD RTC1_IRQHandler_v - DCD QDEC_IRQHandler_v - DCD COMP_LPCOMP_IRQHandler_v - DCD SWI0_EGU0_IRQHandler_v - DCD SWI1_EGU1_IRQHandler_v - DCD SWI2_EGU2_IRQHandler_v - DCD SWI3_EGU3_IRQHandler_v - DCD SWI4_EGU4_IRQHandler - DCD SWI5_EGU5_IRQHandler - DCD TIMER3_IRQHandler_v - DCD TIMER4_IRQHandler_v - DCD PWM0_IRQHandler_v - DCD PDM_IRQHandler_v - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD MWU_IRQHandler - DCD PWM1_IRQHandler_v - DCD PWM2_IRQHandler_v - DCD SPIM2_SPIS2_SPI2_IRQHandler_v - DCD RTC2_IRQHandler_v - DCD I2S_IRQHandler_v - DCD FPU_IRQHandler_v - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset Handler - - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - IMPORT nrf_reloc_vector_table - - - LDR R0, =SystemInit - BLX R0 - LDR R0, =nrf_reloc_vector_table - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemoryManagement_Handler\ - PROC - EXPORT MemoryManagement_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMonitor_Handler\ - PROC - EXPORT DebugMonitor_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT POWER_CLOCK_IRQHandler [WEAK] - EXPORT RADIO_IRQHandler [WEAK] - EXPORT UARTE0_UART0_IRQHandler_v [WEAK] - EXPORT SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v [WEAK] - EXPORT SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v [WEAK] - EXPORT NFCT_IRQHandler_v [WEAK] - EXPORT GPIOTE_IRQHandler_v [WEAK] - EXPORT SAADC_IRQHandler_v [WEAK] - EXPORT TIMER0_IRQHandler_v [WEAK] - EXPORT TIMER1_IRQHandler_v [WEAK] - EXPORT TIMER2_IRQHandler_v [WEAK] - EXPORT RTC0_IRQHandler [WEAK] - EXPORT TEMP_IRQHandler_v [WEAK] - EXPORT RNG_IRQHandler [WEAK] - EXPORT ECB_IRQHandler [WEAK] - EXPORT CCM_AAR_IRQHandler [WEAK] - EXPORT WDT_IRQHandler_v [WEAK] - EXPORT RTC1_IRQHandler_v [WEAK] - EXPORT QDEC_IRQHandler_v [WEAK] - EXPORT COMP_LPCOMP_IRQHandler_v [WEAK] - EXPORT SWI0_EGU0_IRQHandler_v [WEAK] - EXPORT SWI1_EGU1_IRQHandler_v [WEAK] - EXPORT SWI2_EGU2_IRQHandler_v [WEAK] - EXPORT SWI3_EGU3_IRQHandler_v [WEAK] - EXPORT SWI4_EGU4_IRQHandler [WEAK] - EXPORT SWI5_EGU5_IRQHandler [WEAK] - EXPORT TIMER3_IRQHandler_v [WEAK] - EXPORT TIMER4_IRQHandler_v [WEAK] - EXPORT PWM0_IRQHandler_v [WEAK] - EXPORT PDM_IRQHandler_v [WEAK] - EXPORT MWU_IRQHandler [WEAK] - EXPORT PWM1_IRQHandler_v [WEAK] - EXPORT PWM2_IRQHandler_v [WEAK] - EXPORT SPIM2_SPIS2_SPI2_IRQHandler_v [WEAK] - EXPORT RTC2_IRQHandler_v [WEAK] - EXPORT I2S_IRQHandler_v [WEAK] - EXPORT FPU_IRQHandler_v [WEAK] -POWER_CLOCK_IRQHandler -RADIO_IRQHandler -UARTE0_UART0_IRQHandler_v -SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v -SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v -NFCT_IRQHandler_v -GPIOTE_IRQHandler_v -SAADC_IRQHandler_v -TIMER0_IRQHandler_v -TIMER1_IRQHandler_v -TIMER2_IRQHandler_v -RTC0_IRQHandler -TEMP_IRQHandler_v -RNG_IRQHandler -ECB_IRQHandler -CCM_AAR_IRQHandler -WDT_IRQHandler_v -RTC1_IRQHandler_v -QDEC_IRQHandler_v -COMP_LPCOMP_IRQHandler_v -SWI0_EGU0_IRQHandler_v -SWI1_EGU1_IRQHandler_v -SWI2_EGU2_IRQHandler_v -SWI3_EGU3_IRQHandler_v -SWI4_EGU4_IRQHandler -SWI5_EGU5_IRQHandler -TIMER3_IRQHandler_v -TIMER4_IRQHandler_v -PWM0_IRQHandler_v -PDM_IRQHandler_v -MWU_IRQHandler -PWM1_IRQHandler_v -PWM2_IRQHandler_v -SPIM2_SPIS2_SPI2_IRQHandler_v -RTC2_IRQHandler_v -I2S_IRQHandler_v -FPU_IRQHandler_v - B . - ENDP - ALIGN - END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/device/TOOLCHAIN_IAR/startup_NRF52832_IAR.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,381 @@ +;/* Copyright (c) 2012 ARM LIMITED +; +; All rights reserved. +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; - Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; - Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; - Neither the name of ARM nor the names of its contributors may be used +; to endorse or promote products derived from this software without +; specific prior written permission. +; * +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +; ---------------------------------------------------------------------------*/ + + +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. + + + + MODULE ?cstartup + + ;; Stack size default : Defined in *.icf (linker file). Can be modified inside EW. + ;; Heap size default : Defined in *.icf (linker file). Can be modified inside EW. + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + EXTERN nrf_reloc_vector_table + PUBLIC __vector_table + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + DCD NMI_Handler + DCD HardFault_Handler + DCD MemoryManagement_Handler + DCD BusFault_Handler + DCD UsageFault_Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler + DCD DebugMonitor_Handler + DCD 0 ; Reserved + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD POWER_CLOCK_IRQHandler + DCD RADIO_IRQHandler + DCD UARTE0_UART0_IRQHandler_v + DCD SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v + DCD SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v + DCD NFCT_IRQHandler_v + DCD GPIOTE_IRQHandler_v + DCD SAADC_IRQHandler_v + DCD TIMER0_IRQHandler_v + DCD TIMER1_IRQHandler_v + DCD TIMER2_IRQHandler_v + DCD RTC0_IRQHandler + DCD TEMP_IRQHandler_v + DCD RNG_IRQHandler + DCD ECB_IRQHandler + DCD CCM_AAR_IRQHandler + DCD WDT_IRQHandler_v + DCD RTC1_IRQHandler_v + DCD QDEC_IRQHandler_v + DCD COMP_LPCOMP_IRQHandler_v + DCD SWI0_EGU0_IRQHandler_v + DCD SWI1_EGU1_IRQHandler_v + DCD SWI2_EGU2_IRQHandler_v + DCD SWI3_EGU3_IRQHandler_v + DCD SWI4_EGU4_IRQHandler + DCD SWI5_EGU5_IRQHandler + DCD TIMER3_IRQHandler_v + DCD TIMER4_IRQHandler_v + DCD PWM0_IRQHandler_v + DCD PDM_IRQHandler_v + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD MWU_IRQHandler + DCD PWM1_IRQHandler_v + DCD PWM2_IRQHandler_v + DCD SPIM2_SPIS2_SPI2_IRQHandler_v + DCD RTC2_IRQHandler_v + DCD I2S_IRQHandler_v + DCD FPU_IRQHandler_v + + +__Vectors_End +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +; Default handlers. + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =nrf_reloc_vector_table + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + ; Dummy exception handlers + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK MemoryManagement_Handler + SECTION .text:CODE:NOROOT(1) +MemoryManagement_Handler + B . + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT(1) +BusFault_Handler + B . + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT(1) +UsageFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT(1) +SVC_Handler + B . + + PUBWEAK DebugMonitor_Handler + SECTION .text:CODE:NOROOT(1) +DebugMonitor_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT(1) +SysTick_Handler + B . + + + ; Dummy interrupt handlers + + PUBWEAK POWER_CLOCK_IRQHandler + SECTION .text:CODE:NOROOT(1) +POWER_CLOCK_IRQHandler + B . + + PUBWEAK RADIO_IRQHandler + SECTION .text:CODE:NOROOT(1) +RADIO_IRQHandler + B . + + PUBWEAK UARTE0_UART0_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +UARTE0_UART0_IRQHandler_v + B . + + PUBWEAK SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v + B . + + PUBWEAK SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v + B . + + PUBWEAK NFCT_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +NFCT_IRQHandler_v + B . + + PUBWEAK GPIOTE_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +GPIOTE_IRQHandler_v + B . + + PUBWEAK SAADC_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +SAADC_IRQHandler_v + B . + + PUBWEAK TIMER0_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +TIMER0_IRQHandler_v + B . + + PUBWEAK TIMER1_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +TIMER1_IRQHandler_v + B . + + PUBWEAK TIMER2_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +TIMER2_IRQHandler_v + B . + + PUBWEAK RTC0_IRQHandler + SECTION .text:CODE:NOROOT(1) +RTC0_IRQHandler + B . + + PUBWEAK TEMP_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +TEMP_IRQHandler_v + B . + + PUBWEAK RNG_IRQHandler + SECTION .text:CODE:NOROOT(1) +RNG_IRQHandler + B . + + PUBWEAK ECB_IRQHandler + SECTION .text:CODE:NOROOT(1) +ECB_IRQHandler + B . + + PUBWEAK CCM_AAR_IRQHandler + SECTION .text:CODE:NOROOT(1) +CCM_AAR_IRQHandler + B . + + PUBWEAK WDT_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +WDT_IRQHandler_v + B . + + PUBWEAK RTC1_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +RTC1_IRQHandler_v + B . + + PUBWEAK QDEC_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +QDEC_IRQHandler_v + B . + + PUBWEAK COMP_LPCOMP_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +COMP_LPCOMP_IRQHandler_v + B . + + PUBWEAK SWI0_EGU0_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +SWI0_EGU0_IRQHandler_v + B . + + PUBWEAK SWI1_EGU1_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +SWI1_EGU1_IRQHandler_v + B . + + PUBWEAK SWI2_EGU2_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +SWI2_EGU2_IRQHandler_v + B . + + PUBWEAK SWI3_EGU3_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +SWI3_EGU3_IRQHandler_v + B . + + PUBWEAK SWI4_EGU4_IRQHandler + SECTION .text:CODE:NOROOT(1) +SWI4_EGU4_IRQHandler + B . + + PUBWEAK SWI5_EGU5_IRQHandler + SECTION .text:CODE:NOROOT(1) +SWI5_EGU5_IRQHandler + B . + + PUBWEAK TIMER3_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +TIMER3_IRQHandler_v + B . + + PUBWEAK TIMER4_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +TIMER4_IRQHandler_v + B . + + PUBWEAK PWM0_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +PWM0_IRQHandler_v + B . + + PUBWEAK PDM_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +PDM_IRQHandler_v + B . + + PUBWEAK MWU_IRQHandler + SECTION .text:CODE:NOROOT(1) +MWU_IRQHandler + B . + + PUBWEAK PWM1_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +PWM1_IRQHandler_v + B . + + PUBWEAK PWM2_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +PWM2_IRQHandler_v + B . + + PUBWEAK SPIM2_SPIS2_SPI2_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +SPIM2_SPIS2_SPI2_IRQHandler_v + B . + + PUBWEAK RTC2_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +RTC2_IRQHandler_v + B . + + PUBWEAK I2S_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +I2S_IRQHandler_v + B . + + PUBWEAK FPU_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +FPU_IRQHandler_v + B . + + + END + +
--- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/device/TOOLCHAIN_IAR/startup_NRF52832_IAR.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,381 +0,0 @@ -;/* Copyright (c) 2012 ARM LIMITED -; -; All rights reserved. -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; - Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; - Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; - Neither the name of ARM nor the names of its contributors may be used -; to endorse or promote products derived from this software without -; specific prior written permission. -; * -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE -; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; POSSIBILITY OF SUCH DAMAGE. -; ---------------------------------------------------------------------------*/ - - -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. - - - - MODULE ?cstartup - - ;; Stack size default : Defined in *.icf (linker file). Can be modified inside EW. - ;; Heap size default : Defined in *.icf (linker file). Can be modified inside EW. - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - EXTERN nrf_reloc_vector_table - PUBLIC __vector_table - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - DCD NMI_Handler - DCD HardFault_Handler - DCD MemoryManagement_Handler - DCD BusFault_Handler - DCD UsageFault_Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler - DCD DebugMonitor_Handler - DCD 0 ; Reserved - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD POWER_CLOCK_IRQHandler - DCD RADIO_IRQHandler - DCD UARTE0_UART0_IRQHandler_v - DCD SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v - DCD SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v - DCD NFCT_IRQHandler_v - DCD GPIOTE_IRQHandler_v - DCD SAADC_IRQHandler_v - DCD TIMER0_IRQHandler_v - DCD TIMER1_IRQHandler_v - DCD TIMER2_IRQHandler_v - DCD RTC0_IRQHandler - DCD TEMP_IRQHandler_v - DCD RNG_IRQHandler - DCD ECB_IRQHandler - DCD CCM_AAR_IRQHandler - DCD WDT_IRQHandler_v - DCD RTC1_IRQHandler_v - DCD QDEC_IRQHandler_v - DCD COMP_LPCOMP_IRQHandler_v - DCD SWI0_EGU0_IRQHandler_v - DCD SWI1_EGU1_IRQHandler_v - DCD SWI2_EGU2_IRQHandler_v - DCD SWI3_EGU3_IRQHandler_v - DCD SWI4_EGU4_IRQHandler - DCD SWI5_EGU5_IRQHandler - DCD TIMER3_IRQHandler_v - DCD TIMER4_IRQHandler_v - DCD PWM0_IRQHandler_v - DCD PDM_IRQHandler_v - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD MWU_IRQHandler - DCD PWM1_IRQHandler_v - DCD PWM2_IRQHandler_v - DCD SPIM2_SPIS2_SPI2_IRQHandler_v - DCD RTC2_IRQHandler_v - DCD I2S_IRQHandler_v - DCD FPU_IRQHandler_v - - -__Vectors_End -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -; Default handlers. - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:NOROOT(2) -Reset_Handler - - LDR R0, =SystemInit - BLX R0 - LDR R0, =nrf_reloc_vector_table - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - ; Dummy exception handlers - - - PUBWEAK NMI_Handler - SECTION .text:CODE:NOROOT(1) -NMI_Handler - B . - - PUBWEAK HardFault_Handler - SECTION .text:CODE:NOROOT(1) -HardFault_Handler - B . - - PUBWEAK MemoryManagement_Handler - SECTION .text:CODE:NOROOT(1) -MemoryManagement_Handler - B . - - PUBWEAK BusFault_Handler - SECTION .text:CODE:NOROOT(1) -BusFault_Handler - B . - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:NOROOT(1) -UsageFault_Handler - B . - - PUBWEAK SVC_Handler - SECTION .text:CODE:NOROOT(1) -SVC_Handler - B . - - PUBWEAK DebugMonitor_Handler - SECTION .text:CODE:NOROOT(1) -DebugMonitor_Handler - B . - - PUBWEAK PendSV_Handler - SECTION .text:CODE:NOROOT(1) -PendSV_Handler - B . - - PUBWEAK SysTick_Handler - SECTION .text:CODE:NOROOT(1) -SysTick_Handler - B . - - - ; Dummy interrupt handlers - - PUBWEAK POWER_CLOCK_IRQHandler - SECTION .text:CODE:NOROOT(1) -POWER_CLOCK_IRQHandler - B . - - PUBWEAK RADIO_IRQHandler - SECTION .text:CODE:NOROOT(1) -RADIO_IRQHandler - B . - - PUBWEAK UARTE0_UART0_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -UARTE0_UART0_IRQHandler_v - B . - - PUBWEAK SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v - B . - - PUBWEAK SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v - B . - - PUBWEAK NFCT_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -NFCT_IRQHandler_v - B . - - PUBWEAK GPIOTE_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -GPIOTE_IRQHandler_v - B . - - PUBWEAK SAADC_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -SAADC_IRQHandler_v - B . - - PUBWEAK TIMER0_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -TIMER0_IRQHandler_v - B . - - PUBWEAK TIMER1_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -TIMER1_IRQHandler_v - B . - - PUBWEAK TIMER2_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -TIMER2_IRQHandler_v - B . - - PUBWEAK RTC0_IRQHandler - SECTION .text:CODE:NOROOT(1) -RTC0_IRQHandler - B . - - PUBWEAK TEMP_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -TEMP_IRQHandler_v - B . - - PUBWEAK RNG_IRQHandler - SECTION .text:CODE:NOROOT(1) -RNG_IRQHandler - B . - - PUBWEAK ECB_IRQHandler - SECTION .text:CODE:NOROOT(1) -ECB_IRQHandler - B . - - PUBWEAK CCM_AAR_IRQHandler - SECTION .text:CODE:NOROOT(1) -CCM_AAR_IRQHandler - B . - - PUBWEAK WDT_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -WDT_IRQHandler_v - B . - - PUBWEAK RTC1_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -RTC1_IRQHandler_v - B . - - PUBWEAK QDEC_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -QDEC_IRQHandler_v - B . - - PUBWEAK COMP_LPCOMP_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -COMP_LPCOMP_IRQHandler_v - B . - - PUBWEAK SWI0_EGU0_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -SWI0_EGU0_IRQHandler_v - B . - - PUBWEAK SWI1_EGU1_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -SWI1_EGU1_IRQHandler_v - B . - - PUBWEAK SWI2_EGU2_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -SWI2_EGU2_IRQHandler_v - B . - - PUBWEAK SWI3_EGU3_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -SWI3_EGU3_IRQHandler_v - B . - - PUBWEAK SWI4_EGU4_IRQHandler - SECTION .text:CODE:NOROOT(1) -SWI4_EGU4_IRQHandler - B . - - PUBWEAK SWI5_EGU5_IRQHandler - SECTION .text:CODE:NOROOT(1) -SWI5_EGU5_IRQHandler - B . - - PUBWEAK TIMER3_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -TIMER3_IRQHandler_v - B . - - PUBWEAK TIMER4_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -TIMER4_IRQHandler_v - B . - - PUBWEAK PWM0_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -PWM0_IRQHandler_v - B . - - PUBWEAK PDM_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -PDM_IRQHandler_v - B . - - PUBWEAK MWU_IRQHandler - SECTION .text:CODE:NOROOT(1) -MWU_IRQHandler - B . - - PUBWEAK PWM1_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -PWM1_IRQHandler_v - B . - - PUBWEAK PWM2_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -PWM2_IRQHandler_v - B . - - PUBWEAK SPIM2_SPIS2_SPI2_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -SPIM2_SPIS2_SPI2_IRQHandler_v - B . - - PUBWEAK RTC2_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -RTC2_IRQHandler_v - B . - - PUBWEAK I2S_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -I2S_IRQHandler_v - B . - - PUBWEAK FPU_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -FPU_IRQHandler_v - B . - - - END - -
--- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/nrf_drv_config.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52832/sdk/nrf_drv_config.h Tue Mar 20 16:56:18 2018 +0000 @@ -171,7 +171,7 @@ #define NRF_MAXIMUM_LATENCY_US 2000 /* RNG */ -#define RNG_ENABLED 0 +#define RNG_ENABLED 1 #if (RNG_ENABLED == 1) #define RNG_CONFIG_ERROR_CORRECTION true
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM_STD/startup_nrf52832.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,269 @@ +;/* Copyright (c) 2012 ARM LIMITED +; +; All rights reserved. +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; - Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; - Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; - Neither the name of ARM nor the names of its contributors may be used +; to endorse or promote products derived from this software without +; specific prior written permission. +; * +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +; ---------------------------------------------------------------------------*/ + +__initial_sp EQU 0x20040000 + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler + DCD NMI_Handler + DCD HardFault_Handler + DCD MemoryManagement_Handler + DCD BusFault_Handler + DCD UsageFault_Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler + DCD DebugMonitor_Handler + DCD 0 ; Reserved + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD POWER_CLOCK_IRQHandler + DCD RADIO_IRQHandler + DCD UARTE0_UART0_IRQHandler_v + DCD SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v + DCD SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v + DCD NFCT_IRQHandler_v + DCD GPIOTE_IRQHandler_v + DCD SAADC_IRQHandler_v + DCD TIMER0_IRQHandler_v + DCD TIMER1_IRQHandler_v + DCD TIMER2_IRQHandler_v + DCD RTC0_IRQHandler + DCD TEMP_IRQHandler_v + DCD RNG_IRQHandler + DCD ECB_IRQHandler + DCD CCM_AAR_IRQHandler + DCD WDT_IRQHandler_v + DCD RTC1_IRQHandler_v + DCD QDEC_IRQHandler_v + DCD COMP_LPCOMP_IRQHandler_v + DCD SWI0_EGU0_IRQHandler_v + DCD SWI1_EGU1_IRQHandler_v + DCD SWI2_EGU2_IRQHandler_v + DCD SWI3_EGU3_IRQHandler_v + DCD SWI4_EGU4_IRQHandler + DCD SWI5_EGU5_IRQHandler + DCD TIMER3_IRQHandler_v + DCD TIMER4_IRQHandler_v + DCD PWM0_IRQHandler_v + DCD PDM_IRQHandler_v + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD MWU_IRQHandler + DCD PWM1_IRQHandler_v + DCD PWM2_IRQHandler_v + DCD SPIM2_SPIS2_SPI2_IRQHandler_v + DCD RTC2_IRQHandler_v + DCD I2S_IRQHandler_v + DCD FPU_IRQHandler_v + DCD USBD_IRQHandler_v + DCD UARTE1_IRQHandler_v + DCD QSPI_IRQHandler_v + DCD CRYPTOCELL_IRQHandler_v + DCD SPIM3_IRQHandler_v + DCD 0 ; Reserved + DCD PWM3_IRQHandler_v + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset Handler + + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + IMPORT nrf_reloc_vector_table + + + LDR R0, =SystemInit + BLX R0 + LDR R0, =nrf_reloc_vector_table + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemoryManagement_Handler\ + PROC + EXPORT MemoryManagement_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMonitor_Handler\ + PROC + EXPORT DebugMonitor_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT POWER_CLOCK_IRQHandler [WEAK] + EXPORT RADIO_IRQHandler [WEAK] + EXPORT UARTE0_UART0_IRQHandler_v [WEAK] + EXPORT SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v [WEAK] + EXPORT SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v [WEAK] + EXPORT NFCT_IRQHandler_v [WEAK] + EXPORT GPIOTE_IRQHandler_v [WEAK] + EXPORT SAADC_IRQHandler_v [WEAK] + EXPORT TIMER0_IRQHandler_v [WEAK] + EXPORT TIMER1_IRQHandler_v [WEAK] + EXPORT TIMER2_IRQHandler_v [WEAK] + EXPORT RTC0_IRQHandler [WEAK] + EXPORT TEMP_IRQHandler_v [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT ECB_IRQHandler [WEAK] + EXPORT CCM_AAR_IRQHandler [WEAK] + EXPORT WDT_IRQHandler_v [WEAK] + EXPORT RTC1_IRQHandler_v [WEAK] + EXPORT QDEC_IRQHandler_v [WEAK] + EXPORT COMP_LPCOMP_IRQHandler_v [WEAK] + EXPORT SWI0_EGU0_IRQHandler_v [WEAK] + EXPORT SWI1_EGU1_IRQHandler_v [WEAK] + EXPORT SWI2_EGU2_IRQHandler_v [WEAK] + EXPORT SWI3_EGU3_IRQHandler_v [WEAK] + EXPORT SWI4_EGU4_IRQHandler [WEAK] + EXPORT SWI5_EGU5_IRQHandler [WEAK] + EXPORT TIMER3_IRQHandler_v [WEAK] + EXPORT TIMER4_IRQHandler_v [WEAK] + EXPORT PWM0_IRQHandler_v [WEAK] + EXPORT PDM_IRQHandler_v [WEAK] + EXPORT MWU_IRQHandler [WEAK] + EXPORT PWM1_IRQHandler_v [WEAK] + EXPORT PWM2_IRQHandler_v [WEAK] + EXPORT SPIM2_SPIS2_SPI2_IRQHandler_v [WEAK] + EXPORT RTC2_IRQHandler_v [WEAK] + EXPORT I2S_IRQHandler_v [WEAK] + EXPORT FPU_IRQHandler_v [WEAK] + EXPORT USBD_IRQHandler_v [WEAK] + EXPORT UARTE1_IRQHandler_v [WEAK] + EXPORT QSPI_IRQHandler_v [WEAK] + EXPORT CRYPTOCELL_IRQHandler_v [WEAK] + EXPORT SPIM3_IRQHandler_v [WEAK] + EXPORT PWM3_IRQHandler_v [WEAK] + + + + +POWER_CLOCK_IRQHandler +RADIO_IRQHandler +UARTE0_UART0_IRQHandler_v +SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v +SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v +NFCT_IRQHandler_v +GPIOTE_IRQHandler_v +SAADC_IRQHandler_v +TIMER0_IRQHandler_v +TIMER1_IRQHandler_v +TIMER2_IRQHandler_v +RTC0_IRQHandler +TEMP_IRQHandler_v +RNG_IRQHandler +ECB_IRQHandler +CCM_AAR_IRQHandler +WDT_IRQHandler_v +RTC1_IRQHandler_v +QDEC_IRQHandler_v +COMP_LPCOMP_IRQHandler_v +SWI0_EGU0_IRQHandler_v +SWI1_EGU1_IRQHandler_v +SWI2_EGU2_IRQHandler_v +SWI3_EGU3_IRQHandler_v +SWI4_EGU4_IRQHandler +SWI5_EGU5_IRQHandler +TIMER3_IRQHandler_v +TIMER4_IRQHandler_v +PWM0_IRQHandler_v +PDM_IRQHandler_v +MWU_IRQHandler +PWM1_IRQHandler_v +PWM2_IRQHandler_v +SPIM2_SPIS2_SPI2_IRQHandler_v +RTC2_IRQHandler_v +I2S_IRQHandler_v +FPU_IRQHandler_v +USBD_IRQHandler_v +UARTE1_IRQHandler_v +QSPI_IRQHandler_v +CRYPTOCELL_IRQHandler_v +SPIM3_IRQHandler_v +PWM3_IRQHandler_v + + B . + ENDP + ALIGN + END
--- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_ARM_STD/startup_nrf52832.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,269 +0,0 @@ -;/* Copyright (c) 2012 ARM LIMITED -; -; All rights reserved. -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; - Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; - Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; - Neither the name of ARM nor the names of its contributors may be used -; to endorse or promote products derived from this software without -; specific prior written permission. -; * -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE -; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; POSSIBILITY OF SUCH DAMAGE. -; ---------------------------------------------------------------------------*/ - -__initial_sp EQU 0x20040000 - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler - DCD NMI_Handler - DCD HardFault_Handler - DCD MemoryManagement_Handler - DCD BusFault_Handler - DCD UsageFault_Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler - DCD DebugMonitor_Handler - DCD 0 ; Reserved - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD POWER_CLOCK_IRQHandler - DCD RADIO_IRQHandler - DCD UARTE0_UART0_IRQHandler_v - DCD SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v - DCD SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v - DCD NFCT_IRQHandler_v - DCD GPIOTE_IRQHandler_v - DCD SAADC_IRQHandler_v - DCD TIMER0_IRQHandler_v - DCD TIMER1_IRQHandler_v - DCD TIMER2_IRQHandler_v - DCD RTC0_IRQHandler - DCD TEMP_IRQHandler_v - DCD RNG_IRQHandler - DCD ECB_IRQHandler - DCD CCM_AAR_IRQHandler - DCD WDT_IRQHandler_v - DCD RTC1_IRQHandler_v - DCD QDEC_IRQHandler_v - DCD COMP_LPCOMP_IRQHandler_v - DCD SWI0_EGU0_IRQHandler_v - DCD SWI1_EGU1_IRQHandler_v - DCD SWI2_EGU2_IRQHandler_v - DCD SWI3_EGU3_IRQHandler_v - DCD SWI4_EGU4_IRQHandler - DCD SWI5_EGU5_IRQHandler - DCD TIMER3_IRQHandler_v - DCD TIMER4_IRQHandler_v - DCD PWM0_IRQHandler_v - DCD PDM_IRQHandler_v - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD MWU_IRQHandler - DCD PWM1_IRQHandler_v - DCD PWM2_IRQHandler_v - DCD SPIM2_SPIS2_SPI2_IRQHandler_v - DCD RTC2_IRQHandler_v - DCD I2S_IRQHandler_v - DCD FPU_IRQHandler_v - DCD USBD_IRQHandler_v - DCD UARTE1_IRQHandler_v - DCD QSPI_IRQHandler_v - DCD CRYPTOCELL_IRQHandler_v - DCD SPIM3_IRQHandler_v - DCD 0 ; Reserved - DCD PWM3_IRQHandler_v - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset Handler - - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - IMPORT nrf_reloc_vector_table - - - LDR R0, =SystemInit - BLX R0 - LDR R0, =nrf_reloc_vector_table - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemoryManagement_Handler\ - PROC - EXPORT MemoryManagement_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMonitor_Handler\ - PROC - EXPORT DebugMonitor_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT POWER_CLOCK_IRQHandler [WEAK] - EXPORT RADIO_IRQHandler [WEAK] - EXPORT UARTE0_UART0_IRQHandler_v [WEAK] - EXPORT SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v [WEAK] - EXPORT SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v [WEAK] - EXPORT NFCT_IRQHandler_v [WEAK] - EXPORT GPIOTE_IRQHandler_v [WEAK] - EXPORT SAADC_IRQHandler_v [WEAK] - EXPORT TIMER0_IRQHandler_v [WEAK] - EXPORT TIMER1_IRQHandler_v [WEAK] - EXPORT TIMER2_IRQHandler_v [WEAK] - EXPORT RTC0_IRQHandler [WEAK] - EXPORT TEMP_IRQHandler_v [WEAK] - EXPORT RNG_IRQHandler [WEAK] - EXPORT ECB_IRQHandler [WEAK] - EXPORT CCM_AAR_IRQHandler [WEAK] - EXPORT WDT_IRQHandler_v [WEAK] - EXPORT RTC1_IRQHandler_v [WEAK] - EXPORT QDEC_IRQHandler_v [WEAK] - EXPORT COMP_LPCOMP_IRQHandler_v [WEAK] - EXPORT SWI0_EGU0_IRQHandler_v [WEAK] - EXPORT SWI1_EGU1_IRQHandler_v [WEAK] - EXPORT SWI2_EGU2_IRQHandler_v [WEAK] - EXPORT SWI3_EGU3_IRQHandler_v [WEAK] - EXPORT SWI4_EGU4_IRQHandler [WEAK] - EXPORT SWI5_EGU5_IRQHandler [WEAK] - EXPORT TIMER3_IRQHandler_v [WEAK] - EXPORT TIMER4_IRQHandler_v [WEAK] - EXPORT PWM0_IRQHandler_v [WEAK] - EXPORT PDM_IRQHandler_v [WEAK] - EXPORT MWU_IRQHandler [WEAK] - EXPORT PWM1_IRQHandler_v [WEAK] - EXPORT PWM2_IRQHandler_v [WEAK] - EXPORT SPIM2_SPIS2_SPI2_IRQHandler_v [WEAK] - EXPORT RTC2_IRQHandler_v [WEAK] - EXPORT I2S_IRQHandler_v [WEAK] - EXPORT FPU_IRQHandler_v [WEAK] - EXPORT USBD_IRQHandler_v [WEAK] - EXPORT UARTE1_IRQHandler_v [WEAK] - EXPORT QSPI_IRQHandler_v [WEAK] - EXPORT CRYPTOCELL_IRQHandler_v [WEAK] - EXPORT SPIM3_IRQHandler_v [WEAK] - EXPORT PWM3_IRQHandler_v [WEAK] - - - - -POWER_CLOCK_IRQHandler -RADIO_IRQHandler -UARTE0_UART0_IRQHandler_v -SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v -SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v -NFCT_IRQHandler_v -GPIOTE_IRQHandler_v -SAADC_IRQHandler_v -TIMER0_IRQHandler_v -TIMER1_IRQHandler_v -TIMER2_IRQHandler_v -RTC0_IRQHandler -TEMP_IRQHandler_v -RNG_IRQHandler -ECB_IRQHandler -CCM_AAR_IRQHandler -WDT_IRQHandler_v -RTC1_IRQHandler_v -QDEC_IRQHandler_v -COMP_LPCOMP_IRQHandler_v -SWI0_EGU0_IRQHandler_v -SWI1_EGU1_IRQHandler_v -SWI2_EGU2_IRQHandler_v -SWI3_EGU3_IRQHandler_v -SWI4_EGU4_IRQHandler -SWI5_EGU5_IRQHandler -TIMER3_IRQHandler_v -TIMER4_IRQHandler_v -PWM0_IRQHandler_v -PDM_IRQHandler_v -MWU_IRQHandler -PWM1_IRQHandler_v -PWM2_IRQHandler_v -SPIM2_SPIS2_SPI2_IRQHandler_v -RTC2_IRQHandler_v -I2S_IRQHandler_v -FPU_IRQHandler_v -USBD_IRQHandler_v -UARTE1_IRQHandler_v -QSPI_IRQHandler_v -CRYPTOCELL_IRQHandler_v -SPIM3_IRQHandler_v -PWM3_IRQHandler_v - - B . - ENDP - ALIGN - END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_IAR/startup_NRF52832_IAR.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,417 @@ +;/* Copyright (c) 2012 ARM LIMITED +; +; All rights reserved. +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; - Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; - Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; - Neither the name of ARM nor the names of its contributors may be used +; to endorse or promote products derived from this software without +; specific prior written permission. +; * +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +; ---------------------------------------------------------------------------*/ + + +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. + + + + MODULE ?cstartup + + ;; Stack size default : Defined in *.icf (linker file). Can be modified inside EW. + ;; Heap size default : Defined in *.icf (linker file). Can be modified inside EW. + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + EXTERN nrf_reloc_vector_table + PUBLIC __vector_table + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + DCD NMI_Handler + DCD HardFault_Handler + DCD MemoryManagement_Handler + DCD BusFault_Handler + DCD UsageFault_Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler + DCD DebugMonitor_Handler + DCD 0 ; Reserved + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD POWER_CLOCK_IRQHandler + DCD RADIO_IRQHandler + DCD UARTE0_UART0_IRQHandler_v + DCD SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v + DCD SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v + DCD NFCT_IRQHandler_v + DCD GPIOTE_IRQHandler_v + DCD SAADC_IRQHandler_v + DCD TIMER0_IRQHandler_v + DCD TIMER1_IRQHandler_v + DCD TIMER2_IRQHandler_v + DCD RTC0_IRQHandler + DCD TEMP_IRQHandler_v + DCD RNG_IRQHandler + DCD ECB_IRQHandler + DCD CCM_AAR_IRQHandler + DCD WDT_IRQHandler_v + DCD RTC1_IRQHandler_v + DCD QDEC_IRQHandler_v + DCD COMP_LPCOMP_IRQHandler_v + DCD SWI0_EGU0_IRQHandler_v + DCD SWI1_EGU1_IRQHandler_v + DCD SWI2_EGU2_IRQHandler_v + DCD SWI3_EGU3_IRQHandler_v + DCD SWI4_EGU4_IRQHandler + DCD SWI5_EGU5_IRQHandler + DCD TIMER3_IRQHandler_v + DCD TIMER4_IRQHandler_v + DCD PWM0_IRQHandler_v + DCD PDM_IRQHandler_v + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD MWU_IRQHandler + DCD PWM1_IRQHandler_v + DCD PWM2_IRQHandler_v + DCD SPIM2_SPIS2_SPI2_IRQHandler_v + DCD RTC2_IRQHandler_v + DCD I2S_IRQHandler_v + DCD FPU_IRQHandler_v + DCD USBD_IRQHandler_v + DCD UARTE1_IRQHandler_v + DCD QSPI_IRQHandler_v + DCD CRYPTOCELL_IRQHandler_v + DCD SPIM3_IRQHandler_v + DCD 0 /*Reserved */ + DCD PWM3_IRQHandler_v + +__Vectors_End +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +; Default handlers. + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =nrf_reloc_vector_table + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + ; Dummy exception handlers + + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK MemoryManagement_Handler + SECTION .text:CODE:NOROOT(1) +MemoryManagement_Handler + B . + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT(1) +BusFault_Handler + B . + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT(1) +UsageFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT(1) +SVC_Handler + B . + + PUBWEAK DebugMonitor_Handler + SECTION .text:CODE:NOROOT(1) +DebugMonitor_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT(1) +SysTick_Handler + B . + + + ; Dummy interrupt handlers + + PUBWEAK POWER_CLOCK_IRQHandler + SECTION .text:CODE:NOROOT(1) +POWER_CLOCK_IRQHandler + B . + + PUBWEAK RADIO_IRQHandler + SECTION .text:CODE:NOROOT(1) +RADIO_IRQHandler + B . + + PUBWEAK UARTE0_UART0_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +UARTE0_UART0_IRQHandler_v + B . + + PUBWEAK SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v + B . + + PUBWEAK SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v + B . + + PUBWEAK NFCT_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +NFCT_IRQHandler_v + B . + + PUBWEAK GPIOTE_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +GPIOTE_IRQHandler_v + B . + + PUBWEAK SAADC_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +SAADC_IRQHandler_v + B . + + PUBWEAK TIMER0_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +TIMER0_IRQHandler_v + B . + + PUBWEAK TIMER1_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +TIMER1_IRQHandler_v + B . + + PUBWEAK TIMER2_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +TIMER2_IRQHandler_v + B . + + PUBWEAK RTC0_IRQHandler + SECTION .text:CODE:NOROOT(1) +RTC0_IRQHandler + B . + + PUBWEAK TEMP_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +TEMP_IRQHandler_v + B . + + PUBWEAK RNG_IRQHandler + SECTION .text:CODE:NOROOT(1) +RNG_IRQHandler + B . + + PUBWEAK ECB_IRQHandler + SECTION .text:CODE:NOROOT(1) +ECB_IRQHandler + B . + + PUBWEAK CCM_AAR_IRQHandler + SECTION .text:CODE:NOROOT(1) +CCM_AAR_IRQHandler + B . + + PUBWEAK WDT_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +WDT_IRQHandler_v + B . + + PUBWEAK RTC1_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +RTC1_IRQHandler_v + B . + + PUBWEAK QDEC_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +QDEC_IRQHandler_v + B . + + PUBWEAK COMP_LPCOMP_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +COMP_LPCOMP_IRQHandler_v + B . + + PUBWEAK SWI0_EGU0_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +SWI0_EGU0_IRQHandler_v + B . + + PUBWEAK SWI1_EGU1_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +SWI1_EGU1_IRQHandler_v + B . + + PUBWEAK SWI2_EGU2_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +SWI2_EGU2_IRQHandler_v + B . + + PUBWEAK SWI3_EGU3_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +SWI3_EGU3_IRQHandler_v + B . + + PUBWEAK SWI4_EGU4_IRQHandler + SECTION .text:CODE:NOROOT(1) +SWI4_EGU4_IRQHandler + B . + + PUBWEAK SWI5_EGU5_IRQHandler + SECTION .text:CODE:NOROOT(1) +SWI5_EGU5_IRQHandler + B . + + PUBWEAK TIMER3_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +TIMER3_IRQHandler_v + B . + + PUBWEAK TIMER4_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +TIMER4_IRQHandler_v + B . + + PUBWEAK PWM0_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +PWM0_IRQHandler_v + B . + + PUBWEAK PDM_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +PDM_IRQHandler_v + B . + + PUBWEAK MWU_IRQHandler + SECTION .text:CODE:NOROOT(1) +MWU_IRQHandler + B . + + PUBWEAK PWM1_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +PWM1_IRQHandler_v + B . + + PUBWEAK PWM2_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +PWM2_IRQHandler_v + B . + + PUBWEAK SPIM2_SPIS2_SPI2_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +SPIM2_SPIS2_SPI2_IRQHandler_v + B . + + PUBWEAK RTC2_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +RTC2_IRQHandler_v + B . + + PUBWEAK I2S_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +I2S_IRQHandler_v + B . + + PUBWEAK FPU_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +FPU_IRQHandler_v + B . + + PUBWEAK USBD_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +USBD_IRQHandler_v + B . + + PUBWEAK UARTE1_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +UARTE1_IRQHandler_v + B . + + PUBWEAK QSPI_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +QSPI_IRQHandler_v + B . + + PUBWEAK CRYPTOCELL_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +CRYPTOCELL_IRQHandler_v + B . + + PUBWEAK SPIM3_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +SPIM3_IRQHandler_v + B . + + PUBWEAK PWM3_IRQHandler_v + SECTION .text:CODE:NOROOT(1) +PWM3_IRQHandler_v + B . + + + END + +
--- a/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_MCU_NRF52840/device/TOOLCHAIN_IAR/startup_NRF52832_IAR.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,417 +0,0 @@ -;/* Copyright (c) 2012 ARM LIMITED -; -; All rights reserved. -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; - Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; - Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; - Neither the name of ARM nor the names of its contributors may be used -; to endorse or promote products derived from this software without -; specific prior written permission. -; * -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE -; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; POSSIBILITY OF SUCH DAMAGE. -; ---------------------------------------------------------------------------*/ - - -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. - - - - MODULE ?cstartup - - ;; Stack size default : Defined in *.icf (linker file). Can be modified inside EW. - ;; Heap size default : Defined in *.icf (linker file). Can be modified inside EW. - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - EXTERN nrf_reloc_vector_table - PUBLIC __vector_table - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - DCD NMI_Handler - DCD HardFault_Handler - DCD MemoryManagement_Handler - DCD BusFault_Handler - DCD UsageFault_Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler - DCD DebugMonitor_Handler - DCD 0 ; Reserved - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD POWER_CLOCK_IRQHandler - DCD RADIO_IRQHandler - DCD UARTE0_UART0_IRQHandler_v - DCD SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v - DCD SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v - DCD NFCT_IRQHandler_v - DCD GPIOTE_IRQHandler_v - DCD SAADC_IRQHandler_v - DCD TIMER0_IRQHandler_v - DCD TIMER1_IRQHandler_v - DCD TIMER2_IRQHandler_v - DCD RTC0_IRQHandler - DCD TEMP_IRQHandler_v - DCD RNG_IRQHandler - DCD ECB_IRQHandler - DCD CCM_AAR_IRQHandler - DCD WDT_IRQHandler_v - DCD RTC1_IRQHandler_v - DCD QDEC_IRQHandler_v - DCD COMP_LPCOMP_IRQHandler_v - DCD SWI0_EGU0_IRQHandler_v - DCD SWI1_EGU1_IRQHandler_v - DCD SWI2_EGU2_IRQHandler_v - DCD SWI3_EGU3_IRQHandler_v - DCD SWI4_EGU4_IRQHandler - DCD SWI5_EGU5_IRQHandler - DCD TIMER3_IRQHandler_v - DCD TIMER4_IRQHandler_v - DCD PWM0_IRQHandler_v - DCD PDM_IRQHandler_v - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD MWU_IRQHandler - DCD PWM1_IRQHandler_v - DCD PWM2_IRQHandler_v - DCD SPIM2_SPIS2_SPI2_IRQHandler_v - DCD RTC2_IRQHandler_v - DCD I2S_IRQHandler_v - DCD FPU_IRQHandler_v - DCD USBD_IRQHandler_v - DCD UARTE1_IRQHandler_v - DCD QSPI_IRQHandler_v - DCD CRYPTOCELL_IRQHandler_v - DCD SPIM3_IRQHandler_v - DCD 0 /*Reserved */ - DCD PWM3_IRQHandler_v - -__Vectors_End -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -; Default handlers. - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:NOROOT(2) -Reset_Handler - - LDR R0, =SystemInit - BLX R0 - LDR R0, =nrf_reloc_vector_table - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - ; Dummy exception handlers - - - PUBWEAK NMI_Handler - SECTION .text:CODE:NOROOT(1) -NMI_Handler - B . - - PUBWEAK HardFault_Handler - SECTION .text:CODE:NOROOT(1) -HardFault_Handler - B . - - PUBWEAK MemoryManagement_Handler - SECTION .text:CODE:NOROOT(1) -MemoryManagement_Handler - B . - - PUBWEAK BusFault_Handler - SECTION .text:CODE:NOROOT(1) -BusFault_Handler - B . - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:NOROOT(1) -UsageFault_Handler - B . - - PUBWEAK SVC_Handler - SECTION .text:CODE:NOROOT(1) -SVC_Handler - B . - - PUBWEAK DebugMonitor_Handler - SECTION .text:CODE:NOROOT(1) -DebugMonitor_Handler - B . - - PUBWEAK PendSV_Handler - SECTION .text:CODE:NOROOT(1) -PendSV_Handler - B . - - PUBWEAK SysTick_Handler - SECTION .text:CODE:NOROOT(1) -SysTick_Handler - B . - - - ; Dummy interrupt handlers - - PUBWEAK POWER_CLOCK_IRQHandler - SECTION .text:CODE:NOROOT(1) -POWER_CLOCK_IRQHandler - B . - - PUBWEAK RADIO_IRQHandler - SECTION .text:CODE:NOROOT(1) -RADIO_IRQHandler - B . - - PUBWEAK UARTE0_UART0_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -UARTE0_UART0_IRQHandler_v - B . - - PUBWEAK SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -SPIM0_SPIS0_TWIM0_TWIS0_SPI0_TWI0_IRQHandler_v - B . - - PUBWEAK SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -SPIM1_SPIS1_TWIM1_TWIS1_SPI1_TWI1_IRQHandler_v - B . - - PUBWEAK NFCT_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -NFCT_IRQHandler_v - B . - - PUBWEAK GPIOTE_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -GPIOTE_IRQHandler_v - B . - - PUBWEAK SAADC_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -SAADC_IRQHandler_v - B . - - PUBWEAK TIMER0_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -TIMER0_IRQHandler_v - B . - - PUBWEAK TIMER1_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -TIMER1_IRQHandler_v - B . - - PUBWEAK TIMER2_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -TIMER2_IRQHandler_v - B . - - PUBWEAK RTC0_IRQHandler - SECTION .text:CODE:NOROOT(1) -RTC0_IRQHandler - B . - - PUBWEAK TEMP_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -TEMP_IRQHandler_v - B . - - PUBWEAK RNG_IRQHandler - SECTION .text:CODE:NOROOT(1) -RNG_IRQHandler - B . - - PUBWEAK ECB_IRQHandler - SECTION .text:CODE:NOROOT(1) -ECB_IRQHandler - B . - - PUBWEAK CCM_AAR_IRQHandler - SECTION .text:CODE:NOROOT(1) -CCM_AAR_IRQHandler - B . - - PUBWEAK WDT_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -WDT_IRQHandler_v - B . - - PUBWEAK RTC1_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -RTC1_IRQHandler_v - B . - - PUBWEAK QDEC_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -QDEC_IRQHandler_v - B . - - PUBWEAK COMP_LPCOMP_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -COMP_LPCOMP_IRQHandler_v - B . - - PUBWEAK SWI0_EGU0_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -SWI0_EGU0_IRQHandler_v - B . - - PUBWEAK SWI1_EGU1_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -SWI1_EGU1_IRQHandler_v - B . - - PUBWEAK SWI2_EGU2_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -SWI2_EGU2_IRQHandler_v - B . - - PUBWEAK SWI3_EGU3_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -SWI3_EGU3_IRQHandler_v - B . - - PUBWEAK SWI4_EGU4_IRQHandler - SECTION .text:CODE:NOROOT(1) -SWI4_EGU4_IRQHandler - B . - - PUBWEAK SWI5_EGU5_IRQHandler - SECTION .text:CODE:NOROOT(1) -SWI5_EGU5_IRQHandler - B . - - PUBWEAK TIMER3_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -TIMER3_IRQHandler_v - B . - - PUBWEAK TIMER4_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -TIMER4_IRQHandler_v - B . - - PUBWEAK PWM0_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -PWM0_IRQHandler_v - B . - - PUBWEAK PDM_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -PDM_IRQHandler_v - B . - - PUBWEAK MWU_IRQHandler - SECTION .text:CODE:NOROOT(1) -MWU_IRQHandler - B . - - PUBWEAK PWM1_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -PWM1_IRQHandler_v - B . - - PUBWEAK PWM2_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -PWM2_IRQHandler_v - B . - - PUBWEAK SPIM2_SPIS2_SPI2_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -SPIM2_SPIS2_SPI2_IRQHandler_v - B . - - PUBWEAK RTC2_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -RTC2_IRQHandler_v - B . - - PUBWEAK I2S_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -I2S_IRQHandler_v - B . - - PUBWEAK FPU_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -FPU_IRQHandler_v - B . - - PUBWEAK USBD_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -USBD_IRQHandler_v - B . - - PUBWEAK UARTE1_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -UARTE1_IRQHandler_v - B . - - PUBWEAK QSPI_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -QSPI_IRQHandler_v - B . - - PUBWEAK CRYPTOCELL_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -CRYPTOCELL_IRQHandler_v - B . - - PUBWEAK SPIM3_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -SPIM3_IRQHandler_v - B . - - PUBWEAK PWM3_IRQHandler_v - SECTION .text:CODE:NOROOT(1) -PWM3_IRQHandler_v - B . - - - END - -
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/hal/nrf_rng.h Tue Mar 20 16:56:18 2018 +0000
@@ -0,0 +1,281 @@
+/*
+ * Copyright (c) 2014 Nordic Semiconductor ASA
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * 2. Redistributions in binary form, except as embedded into a Nordic Semiconductor ASA
+ * integrated circuit in a product or a software update for such product, must reproduce
+ * the above copyright notice, this list of conditions and the following disclaimer in
+ * the documentation and/or other materials provided with the distribution.
+ *
+ * 3. Neither the name of Nordic Semiconductor ASA nor the names of its contributors may be
+ * used to endorse or promote products derived from this software without specific prior
+ * written permission.
+ *
+ * 4. This software, with or without modification, must only be used with a
+ * Nordic Semiconductor ASA integrated circuit.
+ *
+ * 5. Any software provided in binary or object form under this license must not be reverse
+ * engineered, decompiled, modified and/or disassembled.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ */
+
+/**
+ * @file
+ * @brief RNG HAL API.
+ */
+
+#ifndef NRF_RNG_H__
+#define NRF_RNG_H__
+/**
+ * @defgroup nrf_rng_hal RNG HAL
+ * @{
+ * @ingroup nrf_rng
+ * @brief Hardware access layer for managing the random number generator (RNG).
+ */
+
+#include <stdint.h>
+#include <stddef.h>
+#include <stdbool.h>
+#include "nrf.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#define NRF_RNG_TASK_SET (1UL)
+#define NRF_RNG_EVENT_CLEAR (0UL)
+/**
+ * @enum nrf_rng_task_t
+ * @brief RNG tasks.
+ */
+typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
+{
+ NRF_RNG_TASK_START = offsetof(NRF_RNG_Type, TASKS_START), /**< Start the random number generator. */
+ NRF_RNG_TASK_STOP = offsetof(NRF_RNG_Type, TASKS_STOP) /**< Stop the random number generator. */
+} nrf_rng_task_t; /*lint -restore */
+
+/**
+ * @enum nrf_rng_event_t
+ * @brief RNG events.
+ */
+typedef enum /*lint -save -e30 -esym(628,__INTADDR__) */
+{
+ NRF_RNG_EVENT_VALRDY = offsetof(NRF_RNG_Type, EVENTS_VALRDY) /**< New random number generated event. */
+} nrf_rng_event_t; /*lint -restore */
+
+/**
+ * @enum nrf_rng_int_mask_t
+ * @brief RNG interrupts.
+ */
+typedef enum
+{
+ NRF_RNG_INT_VALRDY_MASK = RNG_INTENSET_VALRDY_Msk /**< Mask for enabling or disabling an interrupt on VALRDY event. */
+} nrf_rng_int_mask_t;
+
+/**
+ * @enum nrf_rng_short_mask_t
+ * @brief Types of RNG shortcuts.
+ */
+typedef enum
+{
+ NRF_RNG_SHORT_VALRDY_STOP_MASK = RNG_SHORTS_VALRDY_STOP_Msk /**< Mask for setting shortcut between EVENT_VALRDY and TASK_STOP. */
+} nrf_rng_short_mask_t;
+
+/**
+ * @brief Function for enabling interrupts.
+ *
+ * @param[in] rng_int_mask Mask of interrupts.
+ */
+__STATIC_INLINE void nrf_rng_int_enable(uint32_t rng_int_mask);
+
+/**
+ * @brief Function for disabling interrupts.
+ *
+ * @param[in] rng_int_mask Mask of interrupts.
+ */
+__STATIC_INLINE void nrf_rng_int_disable(uint32_t rng_int_mask);
+
+/**
+ * @brief Function for getting the state of a specific interrupt.
+ *
+ * @param[in] rng_int_mask Interrupt.
+ *
+ * @retval true If the interrupt is not enabled.
+ * @retval false If the interrupt is enabled.
+ */
+__STATIC_INLINE bool nrf_rng_int_get(nrf_rng_int_mask_t rng_int_mask);
+
+/**
+ * @brief Function for getting the address of a specific task.
+ *
+ * This function can be used by the PPI module.
+ *
+ * @param[in] rng_task Task.
+ */
+__STATIC_INLINE uint32_t * nrf_rng_task_address_get(nrf_rng_task_t rng_task);
+
+/**
+ * @brief Function for setting a specific task.
+ *
+ * @param[in] rng_task Task.
+ */
+__STATIC_INLINE void nrf_rng_task_trigger(nrf_rng_task_t rng_task);
+
+/**
+ * @brief Function for getting address of a specific event.
+ *
+ * This function can be used by the PPI module.
+ *
+ * @param[in] rng_event Event.
+ */
+__STATIC_INLINE uint32_t * nrf_rng_event_address_get(nrf_rng_event_t rng_event);
+
+/**
+ * @brief Function for clearing a specific event.
+ *
+ * @param[in] rng_event Event.
+ */
+__STATIC_INLINE void nrf_rng_event_clear(nrf_rng_event_t rng_event);
+
+/**
+ * @brief Function for getting the state of a specific event.
+ *
+ * @param[in] rng_event Event.
+ *
+ * @retval true If the event is not set.
+ * @retval false If the event is set.
+ */
+__STATIC_INLINE bool nrf_rng_event_get(nrf_rng_event_t rng_event);
+
+/**
+ * @brief Function for setting shortcuts.
+ *
+ * @param[in] rng_short_mask Mask of shortcuts.
+ *
+ */
+__STATIC_INLINE void nrf_rng_shorts_enable(uint32_t rng_short_mask);
+
+/**
+ * @brief Function for clearing shortcuts.
+ *
+ * @param[in] rng_short_mask Mask of shortcuts.
+ *
+ */
+__STATIC_INLINE void nrf_rng_shorts_disable(uint32_t rng_short_mask);
+
+/**
+ * @brief Function for getting the previously generated random value.
+ *
+ * @return Previously generated random value.
+ */
+__STATIC_INLINE uint8_t nrf_rng_random_value_get(void);
+
+/**
+ * @brief Function for enabling digital error correction.
+ */
+__STATIC_INLINE void nrf_rng_error_correction_enable(void);
+
+/**
+ * @brief Function for disabling digital error correction.
+ */
+__STATIC_INLINE void nrf_rng_error_correction_disable(void);
+
+/**
+ *@}
+ **/
+
+#ifndef SUPPRESS_INLINE_IMPLEMENTATION
+
+__STATIC_INLINE void nrf_rng_int_enable(uint32_t rng_int_mask)
+{
+ NRF_RNG->INTENSET = rng_int_mask;
+}
+
+__STATIC_INLINE void nrf_rng_int_disable(uint32_t rng_int_mask)
+{
+ NRF_RNG->INTENCLR = rng_int_mask;
+}
+
+__STATIC_INLINE bool nrf_rng_int_get(nrf_rng_int_mask_t rng_int_mask)
+{
+ return (bool)(NRF_RNG->INTENCLR & rng_int_mask);
+}
+
+__STATIC_INLINE uint32_t * nrf_rng_task_address_get(nrf_rng_task_t rng_task)
+{
+ return (uint32_t *)((uint8_t *)NRF_RNG + rng_task);
+}
+
+__STATIC_INLINE void nrf_rng_task_trigger(nrf_rng_task_t rng_task)
+{
+ *((volatile uint32_t *)((uint8_t *)NRF_RNG + rng_task)) = NRF_RNG_TASK_SET;
+}
+
+__STATIC_INLINE uint32_t * nrf_rng_event_address_get(nrf_rng_event_t rng_event)
+{
+ return (uint32_t *)((uint8_t *)NRF_RNG + rng_event);
+}
+
+__STATIC_INLINE void nrf_rng_event_clear(nrf_rng_event_t rng_event)
+{
+ *((volatile uint32_t *)((uint8_t *)NRF_RNG + rng_event)) = NRF_RNG_EVENT_CLEAR;
+#if __CORTEX_M == 0x04
+ volatile uint32_t dummy = *((volatile uint32_t *)((uint8_t *)NRF_RNG + rng_event));
+ (void)dummy;
+#endif
+}
+
+__STATIC_INLINE bool nrf_rng_event_get(nrf_rng_event_t rng_event)
+{
+ return (bool) * ((volatile uint32_t *)((uint8_t *)NRF_RNG + rng_event));
+}
+
+__STATIC_INLINE void nrf_rng_shorts_enable(uint32_t rng_short_mask)
+{
+ NRF_RNG->SHORTS |= rng_short_mask;
+}
+
+__STATIC_INLINE void nrf_rng_shorts_disable(uint32_t rng_short_mask)
+{
+ NRF_RNG->SHORTS &= ~rng_short_mask;
+}
+
+__STATIC_INLINE uint8_t nrf_rng_random_value_get(void)
+{
+ return (uint8_t)(NRF_RNG->VALUE & RNG_VALUE_VALUE_Msk);
+}
+
+__STATIC_INLINE void nrf_rng_error_correction_enable(void)
+{
+ NRF_RNG->CONFIG |= RNG_CONFIG_DERCEN_Msk;
+}
+
+__STATIC_INLINE void nrf_rng_error_correction_disable(void)
+{
+ NRF_RNG->CONFIG &= ~RNG_CONFIG_DERCEN_Msk;
+}
+
+#endif
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* NRF_RNG_H__ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/rng/nrf_drv_rng.c Tue Mar 20 16:56:18 2018 +0000
@@ -0,0 +1,250 @@
+/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+#include <stdint.h>
+#include <stddef.h>
+
+#include "nrf_drv_rng.h"
+#include "nrf_assert.h"
+#include "nrf_drv_common.h"
+#include "nordic_common.h"
+#include "nrf_error.h"
+#include "nrf_assert.h"
+#ifdef SOFTDEVICE_PRESENT
+#include "nrf_sdm.h"
+#include "nrf_soc.h"
+#else
+#include "app_fifo.h"
+#include "app_util_platform.h"
+
+static __INLINE uint32_t fifo_length(app_fifo_t * p_fifo)
+{
+ uint32_t tmp = p_fifo->read_pos;
+ return p_fifo->write_pos - tmp;
+}
+
+#define FIFO_LENGTH(fifo) fifo_length(&(fifo)) /**< Macro for calculating the FIFO length. */
+
+#endif // SOFTDEVICE_PRESENT
+typedef struct
+{
+ nrf_drv_state_t state;
+#ifndef SOFTDEVICE_PRESENT
+ app_fifo_t rand_pool;
+ uint8_t buffer[RNG_CONFIG_POOL_SIZE];
+#endif // SOFTDEVICE_PRESENT
+} nrf_drv_rng_cb_t;
+
+static nrf_drv_rng_cb_t m_rng_cb;
+#ifndef SOFTDEVICE_PRESENT
+static const nrf_drv_rng_config_t m_default_config = NRF_DRV_RNG_DEFAULT_CONFIG;
+static void rng_start(void)
+{
+ if (FIFO_LENGTH(m_rng_cb.rand_pool) <= m_rng_cb.rand_pool.buf_size_mask)
+ {
+ nrf_rng_event_clear(NRF_RNG_EVENT_VALRDY);
+ nrf_rng_int_enable(NRF_RNG_INT_VALRDY_MASK);
+ nrf_rng_task_trigger(NRF_RNG_TASK_START);
+ }
+}
+
+
+static void rng_stop(void)
+{
+ nrf_rng_int_disable(NRF_RNG_INT_VALRDY_MASK);
+ nrf_rng_task_trigger(NRF_RNG_TASK_STOP);
+}
+
+
+#endif // SOFTDEVICE_PRESENT
+
+
+ret_code_t nrf_drv_rng_init(nrf_drv_rng_config_t const * p_config)
+{
+ uint32_t result;
+
+ if (m_rng_cb.state == NRF_DRV_STATE_UNINITIALIZED)
+ {
+#ifndef SOFTDEVICE_PRESENT
+
+ result = app_fifo_init(&m_rng_cb.rand_pool, m_rng_cb.buffer, RNG_CONFIG_POOL_SIZE);
+
+ if (p_config == NULL)
+ {
+ p_config = &m_default_config;
+ }
+
+ if (result == NRF_SUCCESS)
+ {
+ if (p_config->error_correction)
+ {
+ nrf_rng_error_correction_enable();
+ }
+
+ nrf_drv_common_irq_enable(RNG_IRQn, p_config->interrupt_priority);
+
+ nrf_rng_shorts_disable(NRF_RNG_SHORT_VALRDY_STOP_MASK);
+
+ rng_start();
+ m_rng_cb.state = NRF_DRV_STATE_INITIALIZED;
+ }
+#else
+ UNUSED_VARIABLE(p_config);
+ uint8_t softdevice_is_enabled;
+ result = sd_softdevice_is_enabled(&softdevice_is_enabled);
+
+ if (softdevice_is_enabled)
+ {
+ m_rng_cb.state = NRF_DRV_STATE_INITIALIZED;
+ }
+ else
+ {
+ result = NRF_ERROR_SOFTDEVICE_NOT_ENABLED;
+ }
+#endif // SOFTDEVICE_PRESENT
+ }
+ else
+ {
+ result = NRF_ERROR_INVALID_STATE;
+ }
+ return result;
+}
+
+
+void nrf_drv_rng_uninit(void)
+{
+ ASSERT(m_rng_cb.state == NRF_DRV_STATE_INITIALIZED);
+
+ m_rng_cb.state = NRF_DRV_STATE_UNINITIALIZED;
+#ifndef SOFTDEVICE_PRESENT
+ rng_stop();
+ nrf_drv_common_irq_disable(RNG_IRQn);
+#endif // SOFTDEVICE_PRESENT
+}
+
+ret_code_t nrf_drv_rng_bytes_available(uint8_t * p_bytes_available)
+{
+ ret_code_t result;
+ ASSERT(m_rng_cb.state == NRF_DRV_STATE_INITIALIZED);
+
+#ifndef SOFTDEVICE_PRESENT
+
+ result = NRF_SUCCESS;
+ *p_bytes_available = FIFO_LENGTH(m_rng_cb.rand_pool);
+
+#else
+
+ result = sd_rand_application_bytes_available_get(p_bytes_available);
+
+#endif // SOFTDEVICE_PRESENT
+
+ return result;
+}
+
+ret_code_t nrf_drv_rng_pool_capacity(uint8_t * p_pool_capacity)
+{
+ ret_code_t result;
+ ASSERT(m_rng_cb.state == NRF_DRV_STATE_INITIALIZED);
+
+#ifndef SOFTDEVICE_PRESENT
+
+ result = NRF_SUCCESS;
+ *p_pool_capacity = RNG_CONFIG_POOL_SIZE;
+
+#else
+
+ result = sd_rand_application_pool_capacity_get(p_pool_capacity);
+
+#endif // SOFTDEVICE_PRESENT
+ return result;
+}
+
+ret_code_t nrf_drv_rng_rand(uint8_t * p_buff, uint8_t length)
+{
+ ret_code_t result;
+
+ ASSERT(m_rng_cb.state == NRF_DRV_STATE_INITIALIZED);
+
+#ifndef SOFTDEVICE_PRESENT
+ if (FIFO_LENGTH(m_rng_cb.rand_pool) >= length)
+ {
+ result = NRF_SUCCESS;
+
+ for (uint32_t i = 0; (i < length) && (result == NRF_SUCCESS); i++)
+ {
+ result = app_fifo_get(&(m_rng_cb.rand_pool), &p_buff[i]);
+ }
+ rng_start();
+ }
+ else
+ {
+ result = NRF_ERROR_NO_MEM;
+ }
+#else
+
+ result = sd_rand_application_vector_get(p_buff, length);
+
+#endif // SOFTDEVICE_PRESENT
+
+
+ return result;
+}
+
+ret_code_t nrf_drv_rng_block_rand(uint8_t * p_buff, uint32_t length)
+{
+ uint32_t count = 0, poolsz = 0;
+ ret_code_t result;
+ ASSERT(m_rng_cb.state == NRF_DRV_STATE_INITIALIZED);
+
+ result = nrf_drv_rng_pool_capacity((uint8_t *) &poolsz);
+ if(result != NRF_SUCCESS)
+ {
+ return result;
+ }
+
+ while(length)
+ {
+ uint32_t len = length >= poolsz ? poolsz : length;
+ while((result = nrf_drv_rng_rand(&p_buff[count], len)) != NRF_SUCCESS)
+ {
+#ifndef SOFTDEVICE_PRESENT
+ ASSERT(result == NRF_ERROR_NO_MEM);
+#else
+ ASSERT(result == NRF_ERROR_SOC_RAND_NOT_ENOUGH_VALUES);
+#endif
+ }
+
+ length -= len;
+ count += len;
+ }
+
+ return result;
+}
+
+
+#ifndef SOFTDEVICE_PRESENT
+void RNG_IRQHandler(void)
+{
+ if (nrf_rng_event_get(NRF_RNG_EVENT_VALRDY) &&
+ nrf_rng_int_get(NRF_RNG_INT_VALRDY_MASK))
+ {
+ nrf_rng_event_clear(NRF_RNG_EVENT_VALRDY);
+ uint32_t nrf_error = app_fifo_put(&m_rng_cb.rand_pool, nrf_rng_random_value_get());
+
+ if ((FIFO_LENGTH(m_rng_cb.rand_pool) > m_rng_cb.rand_pool.buf_size_mask) || (nrf_error == NRF_ERROR_NO_MEM))
+ {
+ rng_stop();
+ }
+ }
+}
+
+#endif // SOFTDEVICE_PRESENT
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/TARGET_SDK11/drivers_nrf/rng/nrf_drv_rng.h Tue Mar 20 16:56:18 2018 +0000
@@ -0,0 +1,115 @@
+/* Copyright (c) 2015 Nordic Semiconductor. All Rights Reserved.
+ *
+ * The information contained herein is property of Nordic Semiconductor ASA.
+ * Terms and conditions of usage are described in detail in NORDIC
+ * SEMICONDUCTOR STANDARD SOFTWARE LICENSE AGREEMENT.
+ *
+ * Licensees are granted free, non-transferable use of the information. NO
+ * WARRANTY of ANY KIND is provided. This heading must NOT be removed from
+ * the file.
+ *
+ */
+
+#ifndef NRF_DRV_RNG_H__
+#define NRF_DRV_RNG_H__
+
+#include <stdbool.h>
+#include <stdint.h>
+
+#include "nrf_rng.h"
+#include "sdk_errors.h"
+#include "nrf_drv_config.h"
+
+/**
+ * @addtogroup nrf_rng RNG HAL and driver
+ * @ingroup nrf_drivers
+ * @brief Random number generator (RNG) APIs.
+ * @details The RNG HAL provides basic APIs for accessing the registers of the random number generator.
+ * The RNG driver provides APIs on a higher level.
+ *
+ * @defgroup nrf_drv_rng RNG driver
+ * @{
+ * @ingroup nrf_rng
+ * @brief Driver for managing the random number generator (RNG).
+ */
+
+/**@brief Struct for RNG configuration. */
+typedef struct
+{
+ bool error_correction; /**< Error correction flag. */
+ uint8_t interrupt_priority; /**< interrupt priority */
+} nrf_drv_rng_config_t;
+
+/**@brief RNG default configuration. */
+#define NRF_DRV_RNG_DEFAULT_CONFIG \
+ { \
+ .error_correction = RNG_CONFIG_ERROR_CORRECTION, \
+ .interrupt_priority = RNG_CONFIG_IRQ_PRIORITY, \
+ }
+
+/**
+ * @brief Function for initializing the nrf_drv_rng module.
+ *
+ * @param[in] p_config Initial configuration. Default configuration used if NULL.
+ *
+ * @retval NRF_SUCCESS Driver was successfully initialized.
+ * @retval NRF_ERROR_INVALID_STATE Driver was already initialized.
+ * @retval NRF_ERROR_INVALID_LENGTH Pool size have to be a power of 2.
+ * @retval NRF_ERROR_SOFTDEVICE_NOT_ENABLED SoftDevice is present, but not enabled.
+ */
+ret_code_t nrf_drv_rng_init(nrf_drv_rng_config_t const * p_config);
+
+/**
+ * @brief Function for uninitializing the nrf_drv_rng module.
+ */
+void nrf_drv_rng_uninit(void);
+
+/**
+ * @brief Function for getting the number of currently available random bytes.
+ *
+ * @param[out] p_bytes_available The number of bytes currently available in the pool.
+ *
+ * @retval NRF_SUCCESS If the number of available random bytes was written to p_bytes_available.
+ */
+ret_code_t nrf_drv_rng_bytes_available(uint8_t * p_bytes_available);
+
+/**
+ * @brief Function for querying the capacity of the application random pool.
+ *
+ * @param[out] p_pool_capacity The capacity of the pool.
+ *
+ * @retval NRF_SUCCESS If the capacity of the pool was written to p_pool_capacity.
+ */
+ret_code_t nrf_drv_rng_pool_capacity(uint8_t * p_pool_capacity);
+
+/**
+ * @brief Function for getting the vector of random numbers.
+ *
+ * @param[out] p_buff Pointer to uint8_t buffer for storing the bytes.
+ * @param[in] length Number of bytes to take from the pool and place in p_buff.
+ *
+ * @retval NRF_SUCCESS If the requested bytes were written to p_buff.
+ * @retval NRF_ERROR_NO_MEM If no bytes were written to the buffer
+ * because there were not enough bytes available in p_buff.
+ * @retval NRF_ERROR_SOC_RAND_NOT_ENOUGH_VALUES If no bytes were written to the buffer
+ * because there were not enough bytes available in the pool.
+ */
+ret_code_t nrf_drv_rng_rand(uint8_t * p_buff, uint8_t length);
+
+/**
+ * @brief Blocking function for getting an arbitrary array of random numbers.
+ *
+ * @note This function may execute for a substantial amount of time depending on the length of the buffer
+ * required and on the state of the current internal pool of random numbers.
+ *
+ * @param[out] p_buff Pointer to uint8_t buffer for storing the bytes.
+ * @param[in] length Number of bytes place in p_buff.
+ *
+ * @retval NRF_SUCCESS If the requested bytes were written to p_buff.
+ */
+ret_code_t nrf_drv_rng_block_rand(uint8_t * p_buff, uint32_t length);
+
+/**
+ *@}
+ **/
+#endif // NRF_DRV_RNG_H__
--- a/targets/TARGET_NORDIC/TARGET_NRF5/common_rtc.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/common_rtc.h Tue Mar 20 16:56:18 2018 +0000
@@ -33,6 +33,9 @@
#define OS_TICK_CC_CHANNEL 1
#define LP_TICKER_CC_CHANNEL 2
+#define US_TICKER_SW_IRQ_MASK 0x1
+#define LP_TICKER_SW_IRQ_MASK 0x2
+
#define COMMON_RTC_EVENT_COMPARE(channel) \
CONCAT_2(NRF_RTC_EVENT_COMPARE_, channel)
#define COMMON_RTC_INT_COMPARE_MASK(channel) \
@@ -47,6 +50,7 @@
extern bool m_common_rtc_enabled;
extern uint32_t volatile m_common_rtc_overflows;
+extern uint8_t volatile m_common_sw_irq_flag;
void common_rtc_init(void);
uint32_t common_rtc_32bit_ticks_get(void);
--- a/targets/TARGET_NORDIC/TARGET_NRF5/flash_api.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/flash_api.c Tue Mar 20 16:56:18 2018 +0000
@@ -36,56 +36,134 @@
*
*/
-#include "flash_api.h"
+#if DEVICE_FLASH
+
+#include "hal/flash_api.h"
+#include "hal/lp_ticker_api.h"
+
+#include "nrf_drv_common.h"
#include "nrf_nvmc.h"
#include "nrf_soc.h"
-#include "nrf_sdm.h"
+
+#define WORD_WRITE_TIMEOUT_US (1 * 1000) // Max. value from datasheet: 338 us
+#define PAGE_ERASE_TIMEOUT_US (200 * 1000) // Max. value from datasheet: 89.7 ms
-#if DEVICE_FLASH
+/* Macro for testing if the SoftDevice is active, regardless of whether the
+ * application is build with the SoftDevice or not.
+ */
+#if defined(SOFTDEVICE_PRESENT)
+#include "nrf_sdm.h"
+static uint8_t wrapper(void) {
+ uint8_t softdevice_is_enabled;
+ ret_code_t result = sd_softdevice_is_enabled(&softdevice_is_enabled);
+ return ((result == NRF_SUCCESS) && (softdevice_is_enabled == 1));
+}
+#define NRF_HAL_SD_IS_ENABLED() wrapper()
+#else
+#define NRF_HAL_SD_IS_ENABLED() 0
+#endif
int32_t flash_init(flash_t *obj)
{
(void)(obj);
- uint8_t sd_enabled;
- if ((sd_softdevice_is_enabled(&sd_enabled) == NRF_SUCCESS) && sd_enabled == 1) {
- return -1;
+
+ /* Initialize low power ticker. Used for timeouts. */
+ static bool first_init = true;
+
+ if (first_init) {
+ first_init = false;
+ lp_ticker_init();
}
+
return 0;
}
int32_t flash_free(flash_t *obj)
{
(void)(obj);
+
return 0;
}
int32_t flash_erase_sector(flash_t *obj, uint32_t address)
{
(void)(obj);
- uint8_t sd_enabled;
- if ((sd_softdevice_is_enabled(&sd_enabled) == NRF_SUCCESS) && sd_enabled == 1) {
- return -1;
+
+ /* Return value defaults to error. */
+ uint32_t result = NRF_ERROR_BUSY;
+
+ if (NRF_HAL_SD_IS_ENABLED()) {
+
+ /* Convert address to page number. */
+ uint32_t page_number = address / NRF_FICR->CODEPAGESIZE;
+
+ /* Setup stop watch for timeout. */
+ uint32_t start_us = lp_ticker_read();
+ uint32_t now_us = start_us;
+
+ /* Retry if flash is busy until timeout is reached. */
+ while (((now_us - start_us) < PAGE_ERASE_TIMEOUT_US) &&
+ (result == NRF_ERROR_BUSY)) {
+
+ result = sd_flash_page_erase(page_number);
+
+ /* Read timeout timer. */
+ now_us = lp_ticker_read();
+ }
+
+ } else {
+
+ /* Raw API doesn't return error code, assume success. */
+ nrf_nvmc_page_erase(address);
+ result = NRF_SUCCESS;
}
- nrf_nvmc_page_erase(address);
- return 0;
+
+ /* Convert Nordic error code to mbed HAL error code. */
+ return (result == NRF_SUCCESS) ? 0 : -1;
}
int32_t flash_program_page(flash_t *obj, uint32_t address, const uint8_t *data, uint32_t size)
{
- uint8_t sd_enabled;
- if ((sd_softdevice_is_enabled(&sd_enabled) == NRF_SUCCESS) && sd_enabled == 1) {
- return -1;
+ (void)(obj);
+
+ /* Return value defaults to error. */
+ uint32_t result = NRF_ERROR_BUSY;
+
+ /* Convert size to words. */
+ uint32_t words = size / sizeof(uint32_t);
+
+ if (NRF_HAL_SD_IS_ENABLED()) {
+
+ /* Setup stop watch for timeout. */
+ uint32_t start_us = lp_ticker_read();
+ uint32_t now_us = start_us;
+
+ /* Retry if flash is busy until timeout is reached. */
+ while (((now_us - start_us) < (words * WORD_WRITE_TIMEOUT_US)) &&
+ (result == NRF_ERROR_BUSY)) {
+
+ result = sd_flash_write((uint32_t *) address, (const uint32_t *) data, words);
+
+ /* Read timeout timer. */
+ now_us = lp_ticker_read();
+ }
+
+ } else {
+ /* We will use *_words function to speed up flashing code. Word means 32bit -> 4B
+ * or sizeof(uint32_t).
+ */
+ nrf_nvmc_write_words(address, (const uint32_t *) data, words);
+ result = NRF_SUCCESS;
}
- /* We will use *_words function to speed up flashing code. Word means 32bit -> 4B
- * or sizeof(uint32_t).
- */
- nrf_nvmc_write_words(address, (const uint32_t *) data, (size / sizeof(uint32_t)));
- return 0;
+
+ /* Convert Nordic error code to mbed HAL error code. */
+ return (result == NRF_SUCCESS) ? 0 : -1;
}
uint32_t flash_get_size(const flash_t *obj)
{
(void)(obj);
+
/* Just count flash size. */
return NRF_FICR->CODESIZE * NRF_FICR->CODEPAGESIZE;
}
@@ -93,10 +171,12 @@
uint32_t flash_get_sector_size(const flash_t *obj, uint32_t address)
{
(void)(obj);
+
/* Test if passed address is in flash space. */
if (address < flash_get_size(obj)) {
return NRF_FICR->CODEPAGESIZE;
}
+
/* Something goes wrong, return invalid size error code. */
return MBED_FLASH_INVALID_SIZE;
}
@@ -104,11 +184,15 @@
uint32_t flash_get_page_size(const flash_t *obj)
{
(void)(obj);
- return NRF_FICR->CODEPAGESIZE;
+
+ /* Return minimum writeable size. Note that this is different from the erase page size. */
+ return 4;
}
uint32_t flash_get_start_address(const flash_t *obj)
{
+ (void)(obj);
+
return 0;
}
--- a/targets/TARGET_NORDIC/TARGET_NRF5/gpio_api.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/gpio_api.c Tue Mar 20 16:56:18 2018 +0000
@@ -112,7 +112,7 @@
if ((m_gpio_cfg[pin].direction == PIN_OUTPUT) && (!m_gpio_cfg[pin].used_as_irq)) {
nrf_drv_gpiote_out_uninit(pin);
}
- else {
+ else if (m_gpio_cfg[pin].used_as_irq) {
nrf_drv_gpiote_in_uninit(pin);
}
}
--- a/targets/TARGET_NORDIC/TARGET_NRF5/lp_ticker.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/lp_ticker.c Tue Mar 20 16:56:18 2018 +0000
@@ -18,6 +18,7 @@
#if DEVICE_LOWPOWERTIMER
#include "common_rtc.h"
+#include "mbed_critical.h"
void lp_ticker_init(void)
{
@@ -37,10 +38,10 @@
void lp_ticker_fire_interrupt(void)
{
- uint32_t closest_safe_compare = common_rtc_32bit_ticks_get() + 2;
-
- nrf_rtc_cc_set(COMMON_RTC_INSTANCE, LP_TICKER_CC_CHANNEL, RTC_WRAP(closest_safe_compare));
- nrf_rtc_event_enable(COMMON_RTC_INSTANCE, LP_TICKER_INT_MASK);
+ core_util_critical_section_enter();
+ m_common_sw_irq_flag |= LP_TICKER_SW_IRQ_MASK;
+ NVIC_SetPendingIRQ(RTC1_IRQn);
+ core_util_critical_section_exit();
}
void lp_ticker_disable_interrupt(void)
--- a/targets/TARGET_NORDIC/TARGET_NRF5/trng_api.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/trng_api.c Tue Mar 20 16:56:18 2018 +0000
@@ -37,54 +37,146 @@
*/
#if defined(DEVICE_TRNG)
-#include "trng_api.h"
+
+#include "hal/trng_api.h"
+#include "hal/lp_ticker_api.h"
+
#include "nrf_drv_rng.h"
+#define DEFAULT_TIMEOUT_US (1000*1000)
+
+/* Macro for testing if the SoftDevice is active, regardless of whether the
+ * application is build with the SoftDevice or not.
+ */
+#if defined(SOFTDEVICE_PRESENT)
+#include "nrf_sdm.h"
+static uint8_t wrapper(void) {
+ uint8_t softdevice_is_enabled;
+ ret_code_t result = sd_softdevice_is_enabled(&softdevice_is_enabled);
+ return ((result == NRF_SUCCESS) && (softdevice_is_enabled == 1));
+}
+#define NRF_HAL_SD_IS_ENABLED() wrapper()
+#else
+#define NRF_HAL_SD_IS_ENABLED() 0
+#endif
+
+/** Initialize the TRNG peripheral
+ *
+ * @param obj The TRNG object
+ */
void trng_init(trng_t *obj)
{
(void) obj;
- (void)nrf_drv_rng_init(NULL);
+ /* Initialize low power ticker. Used for timeouts. */
+ static bool first_init = true;
+
+ if (first_init) {
+ first_init = false;
+ lp_ticker_init();
+ }
}
+/** Deinitialize the TRNG peripheral
+ *
+ * @param obj The TRNG object
+ */
void trng_free(trng_t *obj)
{
(void) obj;
-
- nrf_drv_rng_uninit();
}
-/* Get random data from NRF5x TRNG peripheral.
+/** Get random data from TRNG peripheral
*
- * This implementation returns num of random bytes in range <1, length>.
- * For parameters description see trng_api.h file.
+ * @param obj The TRNG object
+ * @param output The pointer to an output array
+ * @param length The size of output data, to avoid buffer overwrite
+ * @param output_length The length of generated data
+ * @return 0 success, -1 fail
*/
int trng_get_bytes(trng_t *obj, uint8_t *output, size_t length, size_t *output_length)
{
- uint8_t bytes_available;
-
(void) obj;
- nrf_drv_rng_bytes_available(&bytes_available);
+ /* Use SDK RNG driver if SoftDevice is enabled. */
+ if (NRF_HAL_SD_IS_ENABLED()) {
+
+ /* Initialize driver once. */
+ static bool nordic_driver_init = true;
+
+ if (nordic_driver_init) {
+ nordic_driver_init = false;
+ nrf_drv_rng_init(NULL);
+ }
+
+ /* Query how many bytes are available. */
+ uint8_t bytes_available;
+ nrf_drv_rng_bytes_available(&bytes_available);
- if (bytes_available == 0) {
- nrf_drv_rng_block_rand(output, 1);
- *output_length = 1;
+ /* If no bytes are cached, block until at least 1 byte is available. */
+ if (bytes_available == 0) {
+ nrf_drv_rng_block_rand(output, 1);
+ *output_length = 1;
+ } else {
+
+ /* Get up to the requested number of bytes. */
+ if (bytes_available > length) {
+ bytes_available = length;
+ }
+
+ ret_code_t result = nrf_drv_rng_rand(output, bytes_available);
+
+ /* Set output length with available bytes. */
+ if (result == NRF_SUCCESS) {
+ *output_length = bytes_available;
+ } else {
+ *output_length = 0;
+ }
+ }
} else {
- if (bytes_available > length) {
- bytes_available = length;
+ /* Initialize low-level registers once. */
+ static bool nordic_register_init = true;
+
+ if (nordic_register_init) {
+ nordic_register_init = false;
+
+ /* Enable RNG */
+ nrf_rng_error_correction_enable();
+ nrf_rng_task_trigger(NRF_RNG_TASK_START);
}
- if (nrf_drv_rng_rand(output, bytes_available) != NRF_SUCCESS) {
- *output_length = 0;
- return -1;
- } else {
- *output_length = bytes_available;
+ /* Copy out one byte at a time. */
+ size_t index = 0;
+ for ( ; index < length; index++) {
+
+ /* Setup stop watch for timeout. */
+ uint32_t start_us = lp_ticker_read();
+ uint32_t now_us = start_us;
+
+ /* Block until timeout or random numer is ready. */
+ while (((now_us - start_us) < DEFAULT_TIMEOUT_US) &&
+ !nrf_rng_event_get(NRF_RNG_EVENT_VALRDY)) {
+ now_us = lp_ticker_read();
+ }
+
+ /* Abort if timeout was reached. */
+ if ((now_us - start_us) >= DEFAULT_TIMEOUT_US) {
+ break;
+ } else {
+
+ /* Read random byte and clear event in preparation for the next byte. */
+ nrf_rng_event_clear(NRF_RNG_EVENT_VALRDY);
+ output[index] = nrf_rng_random_value_get();
+ }
}
+
+ /* Set output length with available bytes. */
+ *output_length = index;
}
- return 0;
+ /* Set return value based on how many bytes was read. */
+ return (*output_length == 0) ? -1 : 0;
}
#endif
--- a/targets/TARGET_NORDIC/TARGET_NRF5/us_ticker.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NORDIC/TARGET_NRF5/us_ticker.c Tue Mar 20 16:56:18 2018 +0000
@@ -55,6 +55,9 @@
bool m_common_rtc_enabled = false;
uint32_t volatile m_common_rtc_overflows = 0;
+// lp/us ticker fire interrupt flag for IRQ handler
+volatile uint8_t m_common_sw_irq_flag = 0;
+
__STATIC_INLINE void rtc_ovf_event_check(void)
{
if (nrf_rtc_event_pending(COMMON_RTC_INSTANCE, NRF_RTC_EVENT_OVERFLOW)) {
@@ -74,11 +77,15 @@
rtc_ovf_event_check();
- if (nrf_rtc_event_pending(COMMON_RTC_INSTANCE, US_TICKER_EVENT)) {
+ if ((m_common_sw_irq_flag & US_TICKER_SW_IRQ_MASK) || nrf_rtc_event_pending(COMMON_RTC_INSTANCE, US_TICKER_EVENT)) {
us_ticker_irq_handler();
}
#if DEVICE_LOWPOWERTIMER
+ if (m_common_sw_irq_flag & LP_TICKER_SW_IRQ_MASK) {
+ m_common_sw_irq_flag &= ~LP_TICKER_SW_IRQ_MASK;
+ lp_ticker_irq_handler();
+ }
if (nrf_rtc_event_pending(COMMON_RTC_INSTANCE, LP_TICKER_EVENT)) {
lp_ticker_irq_handler();
@@ -273,10 +280,10 @@
void us_ticker_fire_interrupt(void)
{
- uint32_t closest_safe_compare = common_rtc_32bit_ticks_get() + 2;
-
- nrf_rtc_cc_set(COMMON_RTC_INSTANCE, US_TICKER_CC_CHANNEL, RTC_WRAP(closest_safe_compare));
- nrf_rtc_event_enable(COMMON_RTC_INSTANCE, US_TICKER_INT_MASK);
+ core_util_critical_section_enter();
+ m_common_sw_irq_flag |= US_TICKER_SW_IRQ_MASK;
+ NVIC_SetPendingIRQ(RTC1_IRQn);
+ core_util_critical_section_exit();
}
void us_ticker_disable_interrupt(void)
@@ -286,6 +293,7 @@
void us_ticker_clear_interrupt(void)
{
+ m_common_sw_irq_flag &= ~US_TICKER_SW_IRQ_MASK;
nrf_rtc_event_clear(COMMON_RTC_INSTANCE, US_TICKER_EVENT);
}
--- a/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PinNames.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M451/TARGET_NUMAKER_PFM_M453/PinNames.h Tue Mar 20 16:56:18 2018 +0000
@@ -104,13 +104,18 @@
D13 = PC_5,
D14 = PE_5,
D15 = PE_4,
+
+ I2C_SCL = D15,
+ I2C_SDA = D14,
- // FIXME: other board-specific naming
+ // NOTE: board-specific naming
// UART naming
USBTX = PA_8,
USBRX = PA_9,
STDIO_UART_TX = USBTX,
STDIO_UART_RX = USBRX,
+ SERIAL_TX = USBTX,
+ SERIAL_RX = USBRX,
// LED naming
LED1 = PD_2,
LED2 = PD_3,
--- a/targets/TARGET_NUVOTON/TARGET_M451/lp_ticker.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M451/lp_ticker.c Tue Mar 20 16:56:18 2018 +0000
@@ -13,209 +13,147 @@
* See the License for the specific language governing permissions and
* limitations under the License.
*/
-
+
#include "lp_ticker_api.h"
#if DEVICE_LOWPOWERTIMER
#include "sleep_api.h"
+#include "mbed_wait_api.h"
+#include "mbed_assert.h"
#include "nu_modutil.h"
#include "nu_miscutil.h"
-#include "mbed_critical.h"
-
-// lp_ticker tick = us = timestamp
-#define US_PER_TICK (1)
-#define US_PER_SEC (1000 * 1000)
-
-#define US_PER_TMR2_INT (US_PER_SEC * 10)
-#define TMR2_CLK_PER_SEC (__LXT)
-#define TMR2_CLK_PER_TMR2_INT ((uint32_t) ((uint64_t) US_PER_TMR2_INT * TMR2_CLK_PER_SEC / US_PER_SEC))
-#define TMR3_CLK_PER_SEC (__LXT)
-static void tmr2_vec(void);
-static void tmr3_vec(void);
-static void lp_ticker_arm_cd(void);
+/* Micro seconds per second */
+#define NU_US_PER_SEC 1000000
+/* Timer clock per lp_ticker tick */
+#define NU_TMRCLK_PER_TICK 1
+/* Timer clock per second */
+#define NU_TMRCLK_PER_SEC (__LXT)
+/* Timer max counter bit size */
+#define NU_TMR_MAXCNT_BITSIZE 24
+/* Timer max counter */
+#define NU_TMR_MAXCNT ((1 << NU_TMR_MAXCNT_BITSIZE) - 1)
-static int lp_ticker_inited = 0;
-static volatile uint32_t counter_major = 0;
-static volatile uint32_t cd_major_minor_clks = 0;
-static volatile uint32_t cd_minor_clks = 0;
-static volatile uint32_t wakeup_tick = (uint32_t) -1;
+static void tmr1_vec(void);
-// NOTE: To wake the system from power down mode, timer clock source must be ether LXT or LIRC.
-// NOTE: TIMER_2 for normal counting and TIMER_3 for scheduled wakeup
-static const struct nu_modinit_s timer2_modinit = {TIMER_2, TMR2_MODULE, CLK_CLKSEL1_TMR2SEL_LXT, 0, TMR2_RST, TMR2_IRQn, (void *) tmr2_vec};
-static const struct nu_modinit_s timer3_modinit = {TIMER_3, TMR3_MODULE, CLK_CLKSEL1_TMR3SEL_LXT, 0, TMR3_RST, TMR3_IRQn, (void *) tmr3_vec};
+/* NOTE: To wake the system from power down mode, timer clock source must be ether LXT or LIRC. */
+static const struct nu_modinit_s timer1_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_LXT, 0, TMR1_RST, TMR1_IRQn, (void *) tmr1_vec};
+
+#define TIMER_MODINIT timer1_modinit
+
+static int ticker_inited = 0;
#define TMR_CMP_MIN 2
#define TMR_CMP_MAX 0xFFFFFFu
void lp_ticker_init(void)
{
- if (lp_ticker_inited) {
+ if (ticker_inited) {
return;
}
- lp_ticker_inited = 1;
-
- counter_major = 0;
- cd_major_minor_clks = 0;
- cd_minor_clks = 0;
- wakeup_tick = (uint32_t) -1;
+ ticker_inited = 1;
// Reset module
- SYS_ResetModule(timer2_modinit.rsetidx);
- SYS_ResetModule(timer3_modinit.rsetidx);
-
+ SYS_ResetModule(TIMER_MODINIT.rsetidx);
+
// Select IP clock source
- CLK_SetModuleClock(timer2_modinit.clkidx, timer2_modinit.clksrc, timer2_modinit.clkdiv);
- CLK_SetModuleClock(timer3_modinit.clkidx, timer3_modinit.clksrc, timer3_modinit.clkdiv);
+ CLK_SetModuleClock(TIMER_MODINIT.clkidx, TIMER_MODINIT.clksrc, TIMER_MODINIT.clkdiv);
+
// Enable IP clock
- CLK_EnableModuleClock(timer2_modinit.clkidx);
- CLK_EnableModuleClock(timer3_modinit.clkidx);
+ CLK_EnableModuleClock(TIMER_MODINIT.clkidx);
// Configure clock
- uint32_t clk_timer2 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
- uint32_t prescale_timer2 = clk_timer2 / TMR2_CLK_PER_SEC - 1;
- MBED_ASSERT((prescale_timer2 != (uint32_t) -1) && prescale_timer2 <= 127);
- MBED_ASSERT((clk_timer2 % TMR2_CLK_PER_SEC) == 0);
- uint32_t cmp_timer2 = TMR2_CLK_PER_TMR2_INT;
- MBED_ASSERT(cmp_timer2 >= TMR_CMP_MIN && cmp_timer2 <= TMR_CMP_MAX);
+ uint32_t clk_timer = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+ uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1;
+ MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127);
+ MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0);
+ uint32_t cmp_timer = TMR_CMP_MAX;
+ MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX);
// Continuous mode
// NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451. In M451, TIMER_CNT is updated continuously by default.
- ((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CTL = TIMER_PERIODIC_MODE | prescale_timer2/* | TIMER_CTL_CNTDATEN_Msk*/;
- ((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CMP = cmp_timer2;
-
+ ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CTL = TIMER_CONTINUOUS_MODE | prescale_timer/* | TIMER_CTL_CNTDATEN_Msk*/;
+ ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CMP = cmp_timer;
+
// Set vector
- NVIC_SetVector(timer2_modinit.irq_n, (uint32_t) timer2_modinit.var);
- NVIC_SetVector(timer3_modinit.irq_n, (uint32_t) timer3_modinit.var);
-
- NVIC_EnableIRQ(timer2_modinit.irq_n);
- NVIC_EnableIRQ(timer3_modinit.irq_n);
-
- TIMER_EnableInt((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
- TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
-
- // NOTE: TIMER_Start() first and then lp_ticker_set_interrupt(); otherwise, we may get stuck in lp_ticker_read() because
- // timer is not running.
-
- // Start timer
- TIMER_Start((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
-
- // Schedule wakeup to match semantics of lp_ticker_get_compare_match()
- lp_ticker_set_interrupt(wakeup_tick);
+ NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var);
+
+ NVIC_EnableIRQ(TIMER_MODINIT.irq_n);
+
+ TIMER_EnableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+ TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+ /* NOTE: When engine is clocked by low power clock source (LXT/LIRC), we need to wait for 3 engine clocks. */
+ wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+ TIMER_Start((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
}
timestamp_t lp_ticker_read()
-{
- if (! lp_ticker_inited) {
+{
+ if (! ticker_inited) {
lp_ticker_init();
}
-
- TIMER_T * timer2_base = (TIMER_T *) NU_MODBASE(timer2_modinit.modname);
-
- do {
- uint64_t major_minor_clks;
- uint32_t minor_clks;
-
- // NOTE: As TIMER_CNT = TIMER_CMP and counter_major has increased by one, TIMER_CNT doesn't change to 0 for one tick time.
- // NOTE: As TIMER_CNT = TIMER_CMP or TIMER_CNT = 0, counter_major (ISR) may not sync with TIMER_CNT. So skip and fetch stable one at the cost of 1 clock delay on this read.
- do {
- core_util_critical_section_enter();
-
- // NOTE: Order of reading minor_us/carry here is significant.
- minor_clks = TIMER_GetCounter(timer2_base);
- uint32_t carry = (timer2_base->INTSTS & TIMER_INTSTS_TIF_Msk) ? 1 : 0;
- // When TIMER_CNT approaches TIMER_CMP and will wrap soon, we may get carry but TIMER_CNT not wrapped. Hanlde carefully carry == 1 && TIMER_CNT is near TIMER_CMP.
- if (carry && minor_clks > (TMR2_CLK_PER_TMR2_INT / 2)) {
- major_minor_clks = (counter_major + 1) * TMR2_CLK_PER_TMR2_INT;
- }
- else {
- major_minor_clks = (counter_major + carry) * TMR2_CLK_PER_TMR2_INT + minor_clks;
- }
-
- core_util_critical_section_exit();
- }
- while (minor_clks == 0 || minor_clks == TMR2_CLK_PER_TMR2_INT);
- // Add power-down compensation
- return ((uint64_t) major_minor_clks * US_PER_SEC / TMR2_CLK_PER_SEC / US_PER_TICK);
- }
- while (0);
+ TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
+
+ return (TIMER_GetCounter(timer_base) / NU_TMRCLK_PER_TICK);
}
void lp_ticker_set_interrupt(timestamp_t timestamp)
{
- uint32_t delta = timestamp - lp_ticker_read();
- wakeup_tick = timestamp;
-
- TIMER_Stop((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
-
- cd_major_minor_clks = (uint64_t) delta * US_PER_TICK * TMR3_CLK_PER_SEC / US_PER_SEC;
- lp_ticker_arm_cd();
-}
+ /* In continuous mode, counter will be reset to zero with the following sequence:
+ * 1. Stop counting
+ * 2. Configure new CMP value
+ * 3. Restart counting
+ *
+ * This behavior is not what we want. To fix it, we could configure new CMP value
+ * without stopping counting first.
+ */
+ TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
-void lp_ticker_fire_interrupt(void)
-{
- cd_major_minor_clks = cd_minor_clks = 0;
- /**
- * This event was in the past. Set the interrupt as pending, but don't process it here.
- * This prevents a recurive loop under heavy load which can lead to a stack overflow.
- */
- NVIC_SetPendingIRQ(timer3_modinit.irq_n);
+ /* NOTE: Because H/W timer requests min compare value, our implementation would have alarm delay of
+ * (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */
+ uint32_t cmp_timer = timestamp * NU_TMRCLK_PER_TICK;
+ cmp_timer = NU_CLAMP(cmp_timer, TMR_CMP_MIN, TMR_CMP_MAX);
+ timer_base->CMP = cmp_timer;
+
+ /* NOTE: When engine is clocked by low power clock source (LXT/LIRC), we need to wait for 3 engine clocks. */
+ wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+ TIMER_Start(timer_base);
}
void lp_ticker_disable_interrupt(void)
{
- TIMER_DisableInt((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
+ TIMER_DisableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
}
void lp_ticker_clear_interrupt(void)
{
- TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
-}
-
-static void tmr2_vec(void)
-{
- TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
- TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
- counter_major ++;
+ TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
}
-static void tmr3_vec(void)
+void lp_ticker_fire_interrupt(void)
{
- TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
- TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
- cd_major_minor_clks = (cd_major_minor_clks > cd_minor_clks) ? (cd_major_minor_clks - cd_minor_clks) : 0;
- if (cd_major_minor_clks == 0) {
- // NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler();
- lp_ticker_irq_handler();
- }
- else {
- lp_ticker_arm_cd();
- }
+ // NOTE: This event was in the past. Set the interrupt as pending, but don't process it here.
+ // This prevents a recursive loop under heavy load which can lead to a stack overflow.
+ NVIC_SetPendingIRQ(TIMER_MODINIT.irq_n);
}
-static void lp_ticker_arm_cd(void)
+const ticker_info_t* lp_ticker_get_info()
{
- TIMER_T * timer3_base = (TIMER_T *) NU_MODBASE(timer3_modinit.modname);
+ static const ticker_info_t info = {
+ NU_TMRCLK_PER_SEC / NU_TMRCLK_PER_TICK,
+ NU_TMR_MAXCNT_BITSIZE
+ };
+ return &info;
+}
+
+static void tmr1_vec(void)
+{
+ TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+ TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
- // Reset 8-bit PSC counter, 24-bit up counter value and CNTEN bit
- timer3_base->CTL |= TIMER_CTL_RSTCNT_Msk;
- // One-shot mode, Clock = 1 KHz
- uint32_t clk_timer3 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
- uint32_t prescale_timer3 = clk_timer3 / TMR3_CLK_PER_SEC - 1;
- MBED_ASSERT((prescale_timer3 != (uint32_t) -1) && prescale_timer3 <= 127);
- MBED_ASSERT((clk_timer3 % TMR3_CLK_PER_SEC) == 0);
- // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451. In M451, TIMER_CNT is updated continuously by default.
- timer3_base->CTL &= ~(TIMER_CTL_OPMODE_Msk | TIMER_CTL_PSC_Msk/* | TIMER_CTL_CNTDATEN_Msk*/);
- timer3_base->CTL |= TIMER_ONESHOT_MODE | prescale_timer3/* | TIMER_CTL_CNTDATEN_Msk*/;
-
- cd_minor_clks = cd_major_minor_clks;
- cd_minor_clks = NU_CLAMP(cd_minor_clks, TMR_CMP_MIN, TMR_CMP_MAX);
- timer3_base->CMP = cd_minor_clks;
-
- TIMER_EnableInt(timer3_base);
- TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
- TIMER_Start(timer3_base);
+ // NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler();
+ lp_ticker_irq_handler();
}
+
#endif
--- a/targets/TARGET_NUVOTON/TARGET_M451/us_ticker.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M451/us_ticker.c Tue Mar 20 16:56:18 2018 +0000
@@ -13,198 +13,130 @@
* See the License for the specific language governing permissions and
* limitations under the License.
*/
-
+
#include "us_ticker_api.h"
#include "sleep_api.h"
#include "mbed_assert.h"
#include "nu_modutil.h"
#include "nu_miscutil.h"
-#include "mbed_critical.h"
-// us_ticker tick = us = timestamp
-#define US_PER_TICK 1
-#define US_PER_SEC (1000 * 1000)
-
-#define TMR0HIRES_CLK_PER_SEC (1000 * 1000)
-#define TMR1HIRES_CLK_PER_SEC (1000 * 1000)
-
-#define US_PER_TMR0HIRES_CLK (US_PER_SEC / TMR0HIRES_CLK_PER_SEC)
-#define US_PER_TMR1HIRES_CLK (US_PER_SEC / TMR1HIRES_CLK_PER_SEC)
-
-#define US_PER_TMR0HIRES_INT (1000 * 1000 * 10)
-#define TMR0HIRES_CLK_PER_TMR0HIRES_INT ((uint32_t) ((uint64_t) US_PER_TMR0HIRES_INT * TMR0HIRES_CLK_PER_SEC / US_PER_SEC))
-
+/* Micro seconds per second */
+#define NU_US_PER_SEC 1000000
+/* Timer clock per us_ticker tick */
+#define NU_TMRCLK_PER_TICK 1
+/* Timer clock per second */
+#define NU_TMRCLK_PER_SEC (1000 * 1000)
+/* Timer max counter bit size */
+#define NU_TMR_MAXCNT_BITSIZE 24
+/* Timer max counter */
+#define NU_TMR_MAXCNT ((1 << NU_TMR_MAXCNT_BITSIZE) - 1)
static void tmr0_vec(void);
-static void tmr1_vec(void);
-static void us_ticker_arm_cd(void);
-static int us_ticker_inited = 0;
-static volatile uint32_t counter_major = 0;
-static volatile uint32_t cd_major_minor_us = 0;
-static volatile uint32_t cd_minor_us = 0;
+static const struct nu_modinit_s timer0_modinit = {TIMER_0, TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_PCLK0, 0, TMR0_RST, TMR0_IRQn, (void *) tmr0_vec};
-// NOTE: PCLK is set up in mbed_sdk_init(), invocation of which must be before C++ global object constructor. See init_api.c for details.
-// NOTE: Choose clock source of timer:
-// 1. HIRC: Be the most accurate but might cause unknown HardFault.
-// 2. HXT: Less accurate and cannot pass mbed-drivers test.
-// 3. PCLK(HXT): Less accurate but can pass mbed-drivers test.
-// NOTE: TIMER_0 for normal counter, TIMER_1 for countdown.
-static const struct nu_modinit_s timer0hires_modinit = {TIMER_0, TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_PCLK0, 0, TMR0_RST, TMR0_IRQn, (void *) tmr0_vec};
-static const struct nu_modinit_s timer1hires_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_PCLK0, 0, TMR1_RST, TMR1_IRQn, (void *) tmr1_vec};
+#define TIMER_MODINIT timer0_modinit
+
+static int ticker_inited = 0;
#define TMR_CMP_MIN 2
#define TMR_CMP_MAX 0xFFFFFFu
void us_ticker_init(void)
{
- if (us_ticker_inited) {
+ if (ticker_inited) {
return;
}
-
- counter_major = 0;
- cd_major_minor_us = 0;
- cd_minor_us = 0;
- us_ticker_inited = 1;
-
+ ticker_inited = 1;
+
// Reset IP
- SYS_ResetModule(timer0hires_modinit.rsetidx);
- SYS_ResetModule(timer1hires_modinit.rsetidx);
-
+ SYS_ResetModule(TIMER_MODINIT.rsetidx);
+
// Select IP clock source
- CLK_SetModuleClock(timer0hires_modinit.clkidx, timer0hires_modinit.clksrc, timer0hires_modinit.clkdiv);
- CLK_SetModuleClock(timer1hires_modinit.clkidx, timer1hires_modinit.clksrc, timer1hires_modinit.clkdiv);
+ CLK_SetModuleClock(TIMER_MODINIT.clkidx, TIMER_MODINIT.clksrc, TIMER_MODINIT.clkdiv);
+
// Enable IP clock
- CLK_EnableModuleClock(timer0hires_modinit.clkidx);
- CLK_EnableModuleClock(timer1hires_modinit.clkidx);
+ CLK_EnableModuleClock(TIMER_MODINIT.clkidx);
// Timer for normal counter
- uint32_t clk_timer0 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
- uint32_t prescale_timer0 = clk_timer0 / TMR0HIRES_CLK_PER_SEC - 1;
- MBED_ASSERT((prescale_timer0 != (uint32_t) -1) && prescale_timer0 <= 127);
- MBED_ASSERT((clk_timer0 % TMR0HIRES_CLK_PER_SEC) == 0);
- uint32_t cmp_timer0 = TMR0HIRES_CLK_PER_TMR0HIRES_INT;
- MBED_ASSERT(cmp_timer0 >= TMR_CMP_MIN && cmp_timer0 <= TMR_CMP_MAX);
+ uint32_t clk_timer = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+ uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1;
+ MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127);
+ MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0);
+ uint32_t cmp_timer = TMR_CMP_MAX;
+ MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX);
// NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451. In M451, TIMER_CNT is updated continuously by default.
- ((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname))->CTL = TIMER_PERIODIC_MODE | prescale_timer0/* | TIMER_CTL_CNTDATEN_Msk*/;
- ((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname))->CMP = cmp_timer0;
-
- NVIC_SetVector(timer0hires_modinit.irq_n, (uint32_t) timer0hires_modinit.var);
- NVIC_SetVector(timer1hires_modinit.irq_n, (uint32_t) timer1hires_modinit.var);
-
- NVIC_EnableIRQ(timer0hires_modinit.irq_n);
- NVIC_EnableIRQ(timer1hires_modinit.irq_n);
-
- TIMER_EnableInt((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
- TIMER_Start((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
+ ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CTL = TIMER_CONTINUOUS_MODE | prescale_timer/* | TIMER_CTL_CNTDATEN_Msk*/;
+ ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CMP = cmp_timer;
+
+ NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var);
+
+ NVIC_EnableIRQ(TIMER_MODINIT.irq_n);
+
+ TIMER_EnableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+ TIMER_Start((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
}
uint32_t us_ticker_read()
{
- if (! us_ticker_inited) {
+ if (! ticker_inited) {
us_ticker_init();
}
-
- TIMER_T * timer0_base = (TIMER_T *) NU_MODBASE(timer0hires_modinit.modname);
-
- do {
- uint32_t major_minor_us;
- uint32_t minor_us;
- // NOTE: As TIMER_CNT = TIMER_CMP and counter_major has increased by one, TIMER_CNT doesn't change to 0 for one tick time.
- // NOTE: As TIMER_CNT = TIMER_CMP or TIMER_CNT = 0, counter_major (ISR) may not sync with TIMER_CNT. So skip and fetch stable one at the cost of 1 clock delay on this read.
- do {
- core_util_critical_section_enter();
-
- // NOTE: Order of reading minor_us/carry here is significant.
- minor_us = TIMER_GetCounter(timer0_base) * US_PER_TMR0HIRES_CLK;
- uint32_t carry = (timer0_base->INTSTS & TIMER_INTSTS_TIF_Msk) ? 1 : 0;
- // When TIMER_CNT approaches TIMER_CMP and will wrap soon, we may get carry but TIMER_CNT not wrapped. Hanlde carefully carry == 1 && TIMER_CNT is near TIMER_CMP.
- if (carry && minor_us > (US_PER_TMR0HIRES_INT / 2)) {
- major_minor_us = (counter_major + 1) * US_PER_TMR0HIRES_INT;
- }
- else {
- major_minor_us = (counter_major + carry) * US_PER_TMR0HIRES_INT + minor_us;
- }
-
- core_util_critical_section_exit();
- }
- while (minor_us == 0 || minor_us == US_PER_TMR0HIRES_INT);
-
- return (major_minor_us / US_PER_TICK);
- }
- while (0);
-}
+ TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
-void us_ticker_disable_interrupt(void)
-{
- TIMER_DisableInt((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname));
-}
-
-void us_ticker_clear_interrupt(void)
-{
- TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname));
+ return (TIMER_GetCounter(timer_base) / NU_TMRCLK_PER_TICK);
}
void us_ticker_set_interrupt(timestamp_t timestamp)
{
- TIMER_Stop((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname));
-
- uint32_t delta = timestamp - us_ticker_read();
- cd_major_minor_us = delta * US_PER_TICK;
- us_ticker_arm_cd();
+ /* In continuous mode, counter will be reset to zero with the following sequence:
+ * 1. Stop counting
+ * 2. Configure new CMP value
+ * 3. Restart counting
+ *
+ * This behavior is not what we want. To fix it, we could configure new CMP value
+ * without stopping counting first.
+ */
+ TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
+
+ /* NOTE: Because H/W timer requests min compare value, our implementation would have alarm delay of
+ * (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */
+ uint32_t cmp_timer = timestamp * NU_TMRCLK_PER_TICK;
+ cmp_timer = NU_CLAMP(cmp_timer, TMR_CMP_MIN, TMR_CMP_MAX);
+ timer_base->CMP = cmp_timer;
+}
+
+void us_ticker_disable_interrupt(void)
+{
+ TIMER_DisableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+}
+
+void us_ticker_clear_interrupt(void)
+{
+ TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
}
void us_ticker_fire_interrupt(void)
{
- cd_major_minor_us = cd_minor_us = 0;
- /**
- * This event was in the past. Set the interrupt as pending, but don't process it here.
- * This prevents a recurive loop under heavy load which can lead to a stack overflow.
- */
- NVIC_SetPendingIRQ(timer1hires_modinit.irq_n);
+ // NOTE: This event was in the past. Set the interrupt as pending, but don't process it here.
+ // This prevents a recursive loop under heavy load which can lead to a stack overflow.
+ NVIC_SetPendingIRQ(TIMER_MODINIT.irq_n);
+}
+
+const ticker_info_t* us_ticker_get_info()
+{
+ static const ticker_info_t info = {
+ NU_TMRCLK_PER_SEC / NU_TMRCLK_PER_TICK,
+ NU_TMR_MAXCNT_BITSIZE
+ };
+ return &info;
}
static void tmr0_vec(void)
{
- TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
- counter_major ++;
-}
-
-static void tmr1_vec(void)
-{
- TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname));
- cd_major_minor_us = (cd_major_minor_us > cd_minor_us) ? (cd_major_minor_us - cd_minor_us) : 0;
- if (cd_major_minor_us == 0) {
- // NOTE: us_ticker_set_interrupt() may get called in us_ticker_irq_handler();
- us_ticker_irq_handler();
- }
- else {
- us_ticker_arm_cd();
- }
-}
-
-static void us_ticker_arm_cd(void)
-{
- TIMER_T * timer1_base = (TIMER_T *) NU_MODBASE(timer1hires_modinit.modname);
+ TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
- cd_minor_us = cd_major_minor_us;
-
- // Reset 8-bit PSC counter, 24-bit up counter value and CNTEN bit
- timer1_base->CTL |= TIMER_CTL_RSTCNT_Msk;
- // One-shot mode, Clock = 1 MHz
- uint32_t clk_timer1 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname));
- uint32_t prescale_timer1 = clk_timer1 / TMR1HIRES_CLK_PER_SEC - 1;
- MBED_ASSERT((prescale_timer1 != (uint32_t) -1) && prescale_timer1 <= 127);
- MBED_ASSERT((clk_timer1 % TMR1HIRES_CLK_PER_SEC) == 0);
- // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451. In M451, TIMER_CNT is updated continuously by default.
- timer1_base->CTL &= ~(TIMER_CTL_OPMODE_Msk | TIMER_CTL_PSC_Msk/* | TIMER_CTL_CNTDATEN_Msk*/);
- timer1_base->CTL |= TIMER_ONESHOT_MODE | prescale_timer1/* | TIMER_CTL_CNTDATEN_Msk*/;
-
- uint32_t cmp_timer1 = cd_minor_us / US_PER_TMR1HIRES_CLK;
- cmp_timer1 = NU_CLAMP(cmp_timer1, TMR_CMP_MIN, TMR_CMP_MAX);
- timer1_base->CMP = cmp_timer1;
-
- TIMER_EnableInt(timer1_base);
- TIMER_Start(timer1_base);
+ // NOTE: us_ticker_set_interrupt() may get called in us_ticker_irq_handler();
+ us_ticker_irq_handler();
}
--- a/targets/TARGET_NUVOTON/TARGET_M480/TARGET_NUMAKER_PFM_M487/PinNames.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/TARGET_NUMAKER_PFM_M487/PinNames.h Tue Mar 20 16:56:18 2018 +0000
@@ -105,12 +105,17 @@
D14 = PG_3,
D15 = PG_2,
+ I2C_SCL = D15,
+ I2C_SDA = D14,
+
// Note: board-specific
// UART naming
USBTX = PD_3,
USBRX = PD_2,
STDIO_UART_TX = USBTX,
STDIO_UART_RX = USBRX,
+ SERIAL_TX = USBTX,
+ SERIAL_RX = USBRX,
// LED naming
LED_RED = PH_0,
LED_YELLOW = PH_1,
--- a/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.c Tue Mar 20 16:56:18 2018 +0000
@@ -30,6 +30,8 @@
static uint16_t crypto_des_avail = 1;
/* Track if SHA H/W is available */
static uint16_t crypto_sha_avail = 1;
+/* Track if ECC H/W is available */
+static uint16_t crypto_ecc_avail = 1;
/* Crypto (AES, DES, SHA, etc.) init counter. Crypto's keeps active as it is non-zero. */
static uint16_t crypto_init_counter = 0U;
@@ -37,12 +39,18 @@
static bool crypto_submodule_acquire(uint16_t *submodule_avail);
static void crypto_submodule_release(uint16_t *submodule_avail);
+/* Crypto done flags */
+#define CRYPTO_DONE_OK BIT0 /* Done with OK */
+#define CRYPTO_DONE_ERR BIT1 /* Done with error */
+
/* Track if PRNG H/W operation is done */
static volatile uint16_t crypto_prng_done;
/* Track if AES H/W operation is done */
static volatile uint16_t crypto_aes_done;
/* Track if DES H/W operation is done */
static volatile uint16_t crypto_des_done;
+/* Track if ECC H/W operation is done */
+static volatile uint16_t crypto_ecc_done;
static void crypto_submodule_prestart(volatile uint16_t *submodule_done);
static bool crypto_submodule_wait(volatile uint16_t *submodule_done);
@@ -96,7 +104,16 @@
/* Implementation that should never be optimized out by the compiler */
void crypto_zeroize(void *v, size_t n)
{
- volatile unsigned char *p = (unsigned char*) v;
+ volatile unsigned char *p = (volatile unsigned char*) v;
+ while (n--) {
+ *p++ = 0;
+ }
+}
+
+/* Implementation that should never be optimized out by the compiler */
+void crypto_zeroize32(uint32_t *v, size_t n)
+{
+ volatile uint32_t *p = (volatile uint32_t*) v;
while (n--) {
*p++ = 0;
}
@@ -132,6 +149,16 @@
crypto_submodule_release(&crypto_sha_avail);
}
+bool crypto_ecc_acquire(void)
+{
+ return crypto_submodule_acquire(&crypto_ecc_avail);
+}
+
+void crypto_ecc_release(void)
+{
+ crypto_submodule_release(&crypto_ecc_avail);
+}
+
void crypto_prng_prestart(void)
{
crypto_submodule_prestart(&crypto_prng_done);
@@ -162,6 +189,16 @@
return crypto_submodule_wait(&crypto_des_done);
}
+void crypto_ecc_prestart(void)
+{
+ crypto_submodule_prestart(&crypto_ecc_done);
+}
+
+bool crypto_ecc_wait(void)
+{
+ return crypto_submodule_wait(&crypto_ecc_done);
+}
+
bool crypto_dma_buff_compat(const void *buff, size_t buff_size, size_t size_aligned_to)
{
uint32_t buff_ = (uint32_t) buff;
@@ -236,20 +273,47 @@
/* Ensure while loop above and subsequent code are not reordered */
__DSB();
- return true;
+ if ((*submodule_done & CRYPTO_DONE_OK)) {
+ /* Done with OK */
+ return true;
+ } else if ((*submodule_done & CRYPTO_DONE_ERR)) {
+ /* Done with error */
+ return false;
+ }
+
+ return false;
}
/* Crypto interrupt handler */
void CRYPTO_IRQHandler()
{
- if (PRNG_GET_INT_FLAG()) {
- crypto_prng_done = 1;
+ uint32_t intsts;
+
+ if ((intsts = PRNG_GET_INT_FLAG()) != 0) {
+ /* Done with OK */
+ crypto_prng_done |= CRYPTO_DONE_OK;
+ /* Clear interrupt flag */
PRNG_CLR_INT_FLAG();
- } else if (AES_GET_INT_FLAG()) {
- crypto_aes_done = 1;
+ } else if ((intsts = AES_GET_INT_FLAG()) != 0) {
+ /* Done with OK */
+ crypto_aes_done |= CRYPTO_DONE_OK;
+ /* Clear interrupt flag */
AES_CLR_INT_FLAG();
- } else if (TDES_GET_INT_FLAG()) {
- crypto_des_done = 1;
+ } else if ((intsts = TDES_GET_INT_FLAG()) != 0) {
+ /* Done with OK */
+ crypto_des_done |= CRYPTO_DONE_OK;
+ /* Clear interrupt flag */
TDES_CLR_INT_FLAG();
+ } else if ((intsts = ECC_GET_INT_FLAG()) != 0) {
+ /* Check interrupt flags */
+ if (intsts & CRPT_INTSTS_ECCIF_Msk) {
+ /* Done with OK */
+ crypto_ecc_done |= CRYPTO_DONE_OK;
+ } else if (intsts & CRPT_INTSTS_ECCEIF_Msk) {
+ /* Done with error */
+ crypto_ecc_done |= CRYPTO_DONE_ERR;
+ }
+ /* Clear interrupt flag */
+ ECC_CLR_INT_FLAG();
}
}
--- a/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_NUVOTON/TARGET_M480/crypto/crypto-misc.h Tue Mar 20 16:56:18 2018 +0000 @@ -30,6 +30,7 @@ /* Clear buffer to zero * Implementation that should never be optimized out by the compiler */ void crypto_zeroize(void *v, size_t n); +void crypto_zeroize32(uint32_t *v, size_t n); /* Acquire/release ownership of AES H/W */ /* NOTE: If "acquire" succeeds, "release" must be done to pair it. */ @@ -46,6 +47,11 @@ bool crypto_sha_acquire(void); void crypto_sha_release(void); +/* Acquire/release ownership of ECC H/W */ +/* NOTE: If "acquire" succeeds, "release" must be done to pair it. */ +bool crypto_ecc_acquire(void); +void crypto_ecc_release(void); + /* Flow control between crypto/xxx start and crypto/xxx ISR * * crypto_xxx_prestart/crypto_xxx_wait encapsulate control flow between crypto/xxx start and crypto/xxx ISR. @@ -67,6 +73,8 @@ bool crypto_aes_wait(void); void crypto_des_prestart(void); bool crypto_des_wait(void); +void crypto_ecc_prestart(void); +bool crypto_ecc_wait(void); /* Check if buffer can be used for crypto DMA. It has the following requirements:
--- a/targets/TARGET_NUVOTON/TARGET_M480/lp_ticker.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/lp_ticker.c Tue Mar 20 16:56:18 2018 +0000
@@ -19,200 +19,141 @@
#if DEVICE_LOWPOWERTIMER
#include "sleep_api.h"
+#include "mbed_wait_api.h"
+#include "mbed_assert.h"
#include "nu_modutil.h"
#include "nu_miscutil.h"
-#include "mbed_critical.h"
-
-// lp_ticker tick = us = timestamp
-#define US_PER_TICK (1)
-#define US_PER_SEC (1000 * 1000)
-
-#define US_PER_TMR2_INT (US_PER_SEC * 10)
-#define TMR2_CLK_PER_SEC (__LXT)
-#define TMR2_CLK_PER_TMR2_INT ((uint32_t) ((uint64_t) US_PER_TMR2_INT * TMR2_CLK_PER_SEC / US_PER_SEC))
-#define TMR3_CLK_PER_SEC (__LXT)
-static void tmr2_vec(void);
-static void tmr3_vec(void);
-static void lp_ticker_arm_cd(void);
+/* Micro seconds per second */
+#define NU_US_PER_SEC 1000000
+/* Timer clock per lp_ticker tick */
+#define NU_TMRCLK_PER_TICK 1
+/* Timer clock per second */
+#define NU_TMRCLK_PER_SEC (__LXT)
+/* Timer max counter bit size */
+#define NU_TMR_MAXCNT_BITSIZE 24
+/* Timer max counter */
+#define NU_TMR_MAXCNT ((1 << NU_TMR_MAXCNT_BITSIZE) - 1)
-static int lp_ticker_inited = 0;
-static volatile uint32_t counter_major = 0;
-static volatile uint32_t cd_major_minor_clks = 0;
-static volatile uint32_t cd_minor_clks = 0;
-static volatile uint32_t wakeup_tick = (uint32_t) -1;
+static void tmr1_vec(void);
-// NOTE: To wake the system from power down mode, timer clock source must be ether LXT or LIRC.
-// NOTE: TIMER_2 for normal counting and TIMER_3 for scheduled wakeup
-static const struct nu_modinit_s timer2_modinit = {TIMER_2, TMR2_MODULE, CLK_CLKSEL1_TMR2SEL_LXT, 0, TMR2_RST, TMR2_IRQn, (void *) tmr2_vec};
-static const struct nu_modinit_s timer3_modinit = {TIMER_3, TMR3_MODULE, CLK_CLKSEL1_TMR3SEL_LXT, 0, TMR3_RST, TMR3_IRQn, (void *) tmr3_vec};
+/* NOTE: To wake the system from power down mode, timer clock source must be ether LXT or LIRC. */
+static const struct nu_modinit_s timer1_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_LXT, 0, TMR1_RST, TMR1_IRQn, (void *) tmr1_vec};
+
+#define TIMER_MODINIT timer1_modinit
+
+static int ticker_inited = 0;
#define TMR_CMP_MIN 2
#define TMR_CMP_MAX 0xFFFFFFu
void lp_ticker_init(void)
{
- if (lp_ticker_inited) {
+ if (ticker_inited) {
return;
}
- lp_ticker_inited = 1;
-
- counter_major = 0;
- cd_major_minor_clks = 0;
- cd_minor_clks = 0;
- wakeup_tick = (uint32_t) -1;
+ ticker_inited = 1;
// Reset module
- SYS_ResetModule(timer2_modinit.rsetidx);
- SYS_ResetModule(timer3_modinit.rsetidx);
+ SYS_ResetModule(TIMER_MODINIT.rsetidx);
// Select IP clock source
- CLK_SetModuleClock(timer2_modinit.clkidx, timer2_modinit.clksrc, timer2_modinit.clkdiv);
- CLK_SetModuleClock(timer3_modinit.clkidx, timer3_modinit.clksrc, timer3_modinit.clkdiv);
+ CLK_SetModuleClock(TIMER_MODINIT.clkidx, TIMER_MODINIT.clksrc, TIMER_MODINIT.clkdiv);
+
// Enable IP clock
- CLK_EnableModuleClock(timer2_modinit.clkidx);
- CLK_EnableModuleClock(timer3_modinit.clkidx);
+ CLK_EnableModuleClock(TIMER_MODINIT.clkidx);
// Configure clock
- uint32_t clk_timer2 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
- uint32_t prescale_timer2 = clk_timer2 / TMR2_CLK_PER_SEC - 1;
- MBED_ASSERT((prescale_timer2 != (uint32_t) -1) && prescale_timer2 <= 127);
- MBED_ASSERT((clk_timer2 % TMR2_CLK_PER_SEC) == 0);
- uint32_t cmp_timer2 = TMR2_CLK_PER_TMR2_INT;
- MBED_ASSERT(cmp_timer2 >= TMR_CMP_MIN && cmp_timer2 <= TMR_CMP_MAX);
+ uint32_t clk_timer = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+ uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1;
+ MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127);
+ MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0);
+ uint32_t cmp_timer = TMR_CMP_MAX;
+ MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX);
// Continuous mode
// NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451/M480. In M451/M480, TIMER_CNT is updated continuously by default.
- ((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CTL = TIMER_PERIODIC_MODE | prescale_timer2/* | TIMER_CTL_CNTDATEN_Msk*/;
- ((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CMP = cmp_timer2;
+ ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CTL = TIMER_CONTINUOUS_MODE | prescale_timer/* | TIMER_CTL_CNTDATEN_Msk*/;
+ ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CMP = cmp_timer;
// Set vector
- NVIC_SetVector(timer2_modinit.irq_n, (uint32_t) timer2_modinit.var);
- NVIC_SetVector(timer3_modinit.irq_n, (uint32_t) timer3_modinit.var);
+ NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var);
- NVIC_EnableIRQ(timer2_modinit.irq_n);
- NVIC_EnableIRQ(timer3_modinit.irq_n);
-
- TIMER_EnableInt((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
- TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
+ NVIC_EnableIRQ(TIMER_MODINIT.irq_n);
- // NOTE: TIMER_Start() first and then lp_ticker_set_interrupt(); otherwise, we may get stuck in lp_ticker_read() because
- // timer is not running.
-
- // Start timer
- TIMER_Start((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
-
- // Schedule wakeup to match semantics of lp_ticker_get_compare_match()
- lp_ticker_set_interrupt(wakeup_tick);
+ TIMER_EnableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+ TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+ /* NOTE: When engine is clocked by low power clock source (LXT/LIRC), we need to wait for 3 engine clocks. */
+ wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+ TIMER_Start((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
}
timestamp_t lp_ticker_read()
{
- if (! lp_ticker_inited) {
+ if (! ticker_inited) {
lp_ticker_init();
}
- TIMER_T * timer2_base = (TIMER_T *) NU_MODBASE(timer2_modinit.modname);
-
- do {
- uint64_t major_minor_clks;
- uint32_t minor_clks;
-
- // NOTE: As TIMER_CNT = TIMER_CMP and counter_major has increased by one, TIMER_CNT doesn't change to 0 for one tick time.
- // NOTE: As TIMER_CNT = TIMER_CMP or TIMER_CNT = 0, counter_major (ISR) may not sync with TIMER_CNT. So skip and fetch stable one at the cost of 1 clock delay on this read.
- do {
- core_util_critical_section_enter();
+ TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
- // NOTE: Order of reading minor_us/carry here is significant.
- minor_clks = TIMER_GetCounter(timer2_base);
- uint32_t carry = (timer2_base->INTSTS & TIMER_INTSTS_TIF_Msk) ? 1 : 0;
- // When TIMER_CNT approaches TIMER_CMP and will wrap soon, we may get carry but TIMER_CNT not wrapped. Handle carefully carry == 1 && TIMER_CNT is near TIMER_CMP.
- if (carry && minor_clks > (TMR2_CLK_PER_TMR2_INT / 2)) {
- major_minor_clks = (counter_major + 1) * TMR2_CLK_PER_TMR2_INT;
- } else {
- major_minor_clks = (counter_major + carry) * TMR2_CLK_PER_TMR2_INT + minor_clks;
- }
-
- core_util_critical_section_exit();
- } while (minor_clks == 0 || minor_clks == TMR2_CLK_PER_TMR2_INT);
-
- // Add power-down compensation
- return ((uint64_t) major_minor_clks * US_PER_SEC / TMR2_CLK_PER_SEC / US_PER_TICK);
- } while (0);
+ return (TIMER_GetCounter(timer_base) / NU_TMRCLK_PER_TICK);
}
void lp_ticker_set_interrupt(timestamp_t timestamp)
{
- uint32_t delta = timestamp - lp_ticker_read();
- wakeup_tick = timestamp;
+ /* In continuous mode, counter will be reset to zero with the following sequence:
+ * 1. Stop counting
+ * 2. Configure new CMP value
+ * 3. Restart counting
+ *
+ * This behavior is not what we want. To fix it, we could configure new CMP value
+ * without stopping counting first.
+ */
+ TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
- TIMER_Stop((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
+ /* NOTE: Because H/W timer requests min compare value, our implementation would have alarm delay of
+ * (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */
+ uint32_t cmp_timer = timestamp * NU_TMRCLK_PER_TICK;
+ cmp_timer = NU_CLAMP(cmp_timer, TMR_CMP_MIN, TMR_CMP_MAX);
+ timer_base->CMP = cmp_timer;
- cd_major_minor_clks = (uint64_t) delta * US_PER_TICK * TMR3_CLK_PER_SEC / US_PER_SEC;
- lp_ticker_arm_cd();
+ /* NOTE: When engine is clocked by low power clock source (LXT/LIRC), we need to wait for 3 engine clocks. */
+ wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+ TIMER_Start(timer_base);
+}
+
+void lp_ticker_disable_interrupt(void)
+{
+ TIMER_DisableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+}
+
+void lp_ticker_clear_interrupt(void)
+{
+ TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
}
void lp_ticker_fire_interrupt(void)
{
// NOTE: This event was in the past. Set the interrupt as pending, but don't process it here.
// This prevents a recursive loop under heavy load which can lead to a stack overflow.
- cd_major_minor_clks = cd_minor_clks = 0;
- NVIC_SetPendingIRQ(timer3_modinit.irq_n);
-}
-
-void lp_ticker_disable_interrupt(void)
-{
- TIMER_DisableInt((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
-}
-
-void lp_ticker_clear_interrupt(void)
-{
- TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
-}
-
-static void tmr2_vec(void)
-{
- TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
- TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
- counter_major ++;
+ NVIC_SetPendingIRQ(TIMER_MODINIT.irq_n);
}
-static void tmr3_vec(void)
+const ticker_info_t* lp_ticker_get_info()
{
- TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
- TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
- cd_major_minor_clks = (cd_major_minor_clks > cd_minor_clks) ? (cd_major_minor_clks - cd_minor_clks) : 0;
- if (cd_major_minor_clks == 0) {
- // NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler();
- lp_ticker_irq_handler();
- } else {
- lp_ticker_arm_cd();
- }
+ static const ticker_info_t info = {
+ NU_TMRCLK_PER_SEC / NU_TMRCLK_PER_TICK,
+ NU_TMR_MAXCNT_BITSIZE
+ };
+ return &info;
}
-static void lp_ticker_arm_cd(void)
+static void tmr1_vec(void)
{
- TIMER_T * timer3_base = (TIMER_T *) NU_MODBASE(timer3_modinit.modname);
+ TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+ TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+
+ // NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler();
+ lp_ticker_irq_handler();
+}
- // Reset 8-bit PSC counter, 24-bit up counter value and CNTEN bit
- // NUC472/M451: See TIMER_CTL_RSTCNT_Msk
- // M480
- timer3_base->CNT = 0;
- while (timer3_base->CNT & TIMER_CNT_RSTACT_Msk);
- // One-shot mode, Clock = 1 KHz
- uint32_t clk_timer3 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
- uint32_t prescale_timer3 = clk_timer3 / TMR3_CLK_PER_SEC - 1;
- MBED_ASSERT((prescale_timer3 != (uint32_t) -1) && prescale_timer3 <= 127);
- MBED_ASSERT((clk_timer3 % TMR3_CLK_PER_SEC) == 0);
- // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451/M480. In M451/M480, TIMER_CNT is updated continuously by default.
- timer3_base->CTL &= ~(TIMER_CTL_OPMODE_Msk | TIMER_CTL_PSC_Msk/* | TIMER_CTL_CNTDATEN_Msk*/);
- timer3_base->CTL |= TIMER_ONESHOT_MODE | prescale_timer3/* | TIMER_CTL_CNTDATEN_Msk*/;
-
- cd_minor_clks = cd_major_minor_clks;
- cd_minor_clks = NU_CLAMP(cd_minor_clks, TMR_CMP_MIN, TMR_CMP_MAX);
- timer3_base->CMP = cd_minor_clks;
-
- TIMER_EnableInt(timer3_base);
- TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
- TIMER_Start(timer3_base);
-}
#endif
--- a/targets/TARGET_NUVOTON/TARGET_M480/us_ticker.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_M480/us_ticker.c Tue Mar 20 16:56:18 2018 +0000
@@ -19,189 +19,124 @@
#include "mbed_assert.h"
#include "nu_modutil.h"
#include "nu_miscutil.h"
-#include "mbed_critical.h"
-// us_ticker tick = us = timestamp
-#define US_PER_TICK 1
-#define US_PER_SEC (1000 * 1000)
-
-#define TMR0HIRES_CLK_PER_SEC (1000 * 1000)
-#define TMR1HIRES_CLK_PER_SEC (1000 * 1000)
-
-#define US_PER_TMR0HIRES_CLK (US_PER_SEC / TMR0HIRES_CLK_PER_SEC)
-#define US_PER_TMR1HIRES_CLK (US_PER_SEC / TMR1HIRES_CLK_PER_SEC)
-
-#define US_PER_TMR0HIRES_INT (1000 * 1000 * 10)
-#define TMR0HIRES_CLK_PER_TMR0HIRES_INT ((uint32_t) ((uint64_t) US_PER_TMR0HIRES_INT * TMR0HIRES_CLK_PER_SEC / US_PER_SEC))
-
+/* Micro seconds per second */
+#define NU_US_PER_SEC 1000000
+/* Timer clock per us_ticker tick */
+#define NU_TMRCLK_PER_TICK 1
+/* Timer clock per second */
+#define NU_TMRCLK_PER_SEC (1000 * 1000)
+/* Timer max counter bit size */
+#define NU_TMR_MAXCNT_BITSIZE 24
+/* Timer max counter */
+#define NU_TMR_MAXCNT ((1 << NU_TMR_MAXCNT_BITSIZE) - 1)
static void tmr0_vec(void);
-static void tmr1_vec(void);
-static void us_ticker_arm_cd(void);
-static int us_ticker_inited = 0;
-static volatile uint32_t counter_major = 0;
-static volatile uint32_t cd_major_minor_us = 0;
-static volatile uint32_t cd_minor_us = 0;
+static const struct nu_modinit_s timer0_modinit = {TIMER_0, TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_PCLK0, 0, TMR0_RST, TMR0_IRQn, (void *) tmr0_vec};
-// NOTE: PCLK is set up in mbed_sdk_init(), invocation of which must be before C++ global object constructor. See init_api.c for details.
-// NOTE: Choose clock source of timer:
-// 1. HIRC: Be the most accurate but might cause unknown HardFault.
-// 2. HXT: Less accurate and cannot pass mbed-drivers test.
-// 3. PCLK(HXT): Less accurate but can pass mbed-drivers test.
-// NOTE: TIMER_0 for normal counter, TIMER_1 for countdown.
-static const struct nu_modinit_s timer0hires_modinit = {TIMER_0, TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_PCLK0, 0, TMR0_RST, TMR0_IRQn, (void *) tmr0_vec};
-static const struct nu_modinit_s timer1hires_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_PCLK0, 0, TMR1_RST, TMR1_IRQn, (void *) tmr1_vec};
+#define TIMER_MODINIT timer0_modinit
+
+static int ticker_inited = 0;
#define TMR_CMP_MIN 2
#define TMR_CMP_MAX 0xFFFFFFu
void us_ticker_init(void)
{
- if (us_ticker_inited) {
+ if (ticker_inited) {
return;
}
-
- counter_major = 0;
- cd_major_minor_us = 0;
- cd_minor_us = 0;
- us_ticker_inited = 1;
+ ticker_inited = 1;
// Reset IP
- SYS_ResetModule(timer0hires_modinit.rsetidx);
- SYS_ResetModule(timer1hires_modinit.rsetidx);
+ SYS_ResetModule(TIMER_MODINIT.rsetidx);
// Select IP clock source
- CLK_SetModuleClock(timer0hires_modinit.clkidx, timer0hires_modinit.clksrc, timer0hires_modinit.clkdiv);
- CLK_SetModuleClock(timer1hires_modinit.clkidx, timer1hires_modinit.clksrc, timer1hires_modinit.clkdiv);
+ CLK_SetModuleClock(TIMER_MODINIT.clkidx, TIMER_MODINIT.clksrc, TIMER_MODINIT.clkdiv);
+
// Enable IP clock
- CLK_EnableModuleClock(timer0hires_modinit.clkidx);
- CLK_EnableModuleClock(timer1hires_modinit.clkidx);
+ CLK_EnableModuleClock(TIMER_MODINIT.clkidx);
// Timer for normal counter
- uint32_t clk_timer0 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
- uint32_t prescale_timer0 = clk_timer0 / TMR0HIRES_CLK_PER_SEC - 1;
- MBED_ASSERT((prescale_timer0 != (uint32_t) -1) && prescale_timer0 <= 127);
- MBED_ASSERT((clk_timer0 % TMR0HIRES_CLK_PER_SEC) == 0);
- uint32_t cmp_timer0 = TMR0HIRES_CLK_PER_TMR0HIRES_INT;
- MBED_ASSERT(cmp_timer0 >= TMR_CMP_MIN && cmp_timer0 <= TMR_CMP_MAX);
+ uint32_t clk_timer = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+ uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1;
+ MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127);
+ MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0);
+ uint32_t cmp_timer = TMR_CMP_MAX;
+ MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX);
// NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451/M480. In M451/M480, TIMER_CNT is updated continuously by default.
- ((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname))->CTL = TIMER_PERIODIC_MODE | prescale_timer0/* | TIMER_CTL_CNTDATEN_Msk*/;
- ((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname))->CMP = cmp_timer0;
+ ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CTL = TIMER_CONTINUOUS_MODE | prescale_timer/* | TIMER_CTL_CNTDATEN_Msk*/;
+ ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CMP = cmp_timer;
- NVIC_SetVector(timer0hires_modinit.irq_n, (uint32_t) timer0hires_modinit.var);
- NVIC_SetVector(timer1hires_modinit.irq_n, (uint32_t) timer1hires_modinit.var);
+ NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var);
- NVIC_EnableIRQ(timer0hires_modinit.irq_n);
- NVIC_EnableIRQ(timer1hires_modinit.irq_n);
+ NVIC_EnableIRQ(TIMER_MODINIT.irq_n);
- TIMER_EnableInt((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
- TIMER_Start((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
+ TIMER_EnableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+ TIMER_Start((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
}
uint32_t us_ticker_read()
{
- if (! us_ticker_inited) {
+ if (! ticker_inited) {
us_ticker_init();
}
- TIMER_T * timer0_base = (TIMER_T *) NU_MODBASE(timer0hires_modinit.modname);
+ TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
- do {
- uint32_t major_minor_us;
- uint32_t minor_us;
-
- // NOTE: As TIMER_CNT = TIMER_CMP and counter_major has increased by one, TIMER_CNT doesn't change to 0 for one tick time.
- // NOTE: As TIMER_CNT = TIMER_CMP or TIMER_CNT = 0, counter_major (ISR) may not sync with TIMER_CNT. So skip and fetch stable one at the cost of 1 clock delay on this read.
- do {
- core_util_critical_section_enter();
+ return (TIMER_GetCounter(timer_base) / NU_TMRCLK_PER_TICK);
+}
- // NOTE: Order of reading minor_us/carry here is significant.
- minor_us = TIMER_GetCounter(timer0_base) * US_PER_TMR0HIRES_CLK;
- uint32_t carry = (timer0_base->INTSTS & TIMER_INTSTS_TIF_Msk) ? 1 : 0;
- // When TIMER_CNT approaches TIMER_CMP and will wrap soon, we may get carry but TIMER_CNT not wrapped. Hanlde carefully carry == 1 && TIMER_CNT is near TIMER_CMP.
- if (carry && minor_us > (US_PER_TMR0HIRES_INT / 2)) {
- major_minor_us = (counter_major + 1) * US_PER_TMR0HIRES_INT;
- } else {
- major_minor_us = (counter_major + carry) * US_PER_TMR0HIRES_INT + minor_us;
- }
+void us_ticker_set_interrupt(timestamp_t timestamp)
+{
+ /* In continuous mode, counter will be reset to zero with the following sequence:
+ * 1. Stop counting
+ * 2. Configure new CMP value
+ * 3. Restart counting
+ *
+ * This behavior is not what we want. To fix it, we could configure new CMP value
+ * without stopping counting first.
+ */
+ TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
- core_util_critical_section_exit();
- } while (minor_us == 0 || minor_us == US_PER_TMR0HIRES_INT);
-
- return (major_minor_us / US_PER_TICK);
- } while (0);
+ /* NOTE: Because H/W timer requests min compare value, our implementation would have alarm delay of
+ * (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */
+ uint32_t cmp_timer = timestamp * NU_TMRCLK_PER_TICK;
+ cmp_timer = NU_CLAMP(cmp_timer, TMR_CMP_MIN, TMR_CMP_MAX);
+ timer_base->CMP = cmp_timer;
}
void us_ticker_disable_interrupt(void)
{
- TIMER_DisableInt((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname));
+ TIMER_DisableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
}
void us_ticker_clear_interrupt(void)
{
- TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname));
-}
-
-void us_ticker_set_interrupt(timestamp_t timestamp)
-{
- TIMER_Stop((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname));
-
- uint32_t delta = timestamp - us_ticker_read();
- cd_major_minor_us = delta * US_PER_TICK;
- us_ticker_arm_cd();
+ TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
}
void us_ticker_fire_interrupt(void)
{
// NOTE: This event was in the past. Set the interrupt as pending, but don't process it here.
// This prevents a recursive loop under heavy load which can lead to a stack overflow.
- cd_major_minor_us = cd_minor_us = 0;
- NVIC_SetPendingIRQ(timer1hires_modinit.irq_n);
+ NVIC_SetPendingIRQ(TIMER_MODINIT.irq_n);
+}
+
+const ticker_info_t* us_ticker_get_info()
+{
+ static const ticker_info_t info = {
+ NU_TMRCLK_PER_SEC / NU_TMRCLK_PER_TICK,
+ NU_TMR_MAXCNT_BITSIZE
+ };
+ return &info;
}
static void tmr0_vec(void)
{
- TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
- counter_major ++;
-}
-
-static void tmr1_vec(void)
-{
- TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname));
- cd_major_minor_us = (cd_major_minor_us > cd_minor_us) ? (cd_major_minor_us - cd_minor_us) : 0;
- if (cd_major_minor_us == 0) {
- // NOTE: us_ticker_set_interrupt() may get called in us_ticker_irq_handler();
- us_ticker_irq_handler();
- } else {
- us_ticker_arm_cd();
- }
+ TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+
+ // NOTE: us_ticker_set_interrupt() may get called in us_ticker_irq_handler();
+ us_ticker_irq_handler();
}
-
-static void us_ticker_arm_cd(void)
-{
- TIMER_T * timer1_base = (TIMER_T *) NU_MODBASE(timer1hires_modinit.modname);
-
- cd_minor_us = cd_major_minor_us;
-
- // Reset 8-bit PSC counter, 24-bit up counter value and CNTEN bit
- // NUC472/M451: See TIMER_CTL_RSTCNT_Msk
- // M480
- timer1_base->CNT = 0;
- while (timer1_base->CNT & TIMER_CNT_RSTACT_Msk);
- // One-shot mode, Clock = 1 MHz
- uint32_t clk_timer1 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname));
- uint32_t prescale_timer1 = clk_timer1 / TMR1HIRES_CLK_PER_SEC - 1;
- MBED_ASSERT((prescale_timer1 != (uint32_t) -1) && prescale_timer1 <= 127);
- MBED_ASSERT((clk_timer1 % TMR1HIRES_CLK_PER_SEC) == 0);
- // NOTE: TIMER_CTL_CNTDATEN_Msk exists in NUC472, but not in M451/M480. In M451/M480, TIMER_CNT is updated continuously by default.
- timer1_base->CTL &= ~(TIMER_CTL_OPMODE_Msk | TIMER_CTL_PSC_Msk/* | TIMER_CTL_CNTDATEN_Msk*/);
- timer1_base->CTL |= TIMER_ONESHOT_MODE | prescale_timer1/* | TIMER_CTL_CNTDATEN_Msk*/;
-
- uint32_t cmp_timer1 = cd_minor_us / US_PER_TMR1HIRES_CLK;
- cmp_timer1 = NU_CLAMP(cmp_timer1, TMR_CMP_MIN, TMR_CMP_MAX);
- timer1_base->CMP = cmp_timer1;
-
- TIMER_EnableInt(timer1_base);
- TIMER_Start(timer1_base);
-}
--- a/targets/TARGET_NUVOTON/TARGET_NANO100/TARGET_NUMAKER_PFM_NANO130/PinNames.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/TARGET_NUMAKER_PFM_NANO130/PinNames.h Tue Mar 20 16:56:18 2018 +0000
@@ -102,13 +102,18 @@
D13 = PC_1,
D14 = PC_8,
D15 = PC_9,
-
+
+ I2C_SCL = D15,
+ I2C_SDA = D14,
+
// NOTE: other board-specific naming
// UART naming
USBTX = PB_1,
USBRX = PB_0,
STDIO_UART_TX = USBTX,
STDIO_UART_RX = USBRX,
+ SERIAL_TX = USBTX,
+ SERIAL_RX = USBRX,
// LED naming
LED1 = PE_11,
LED2 = PE_10,
--- a/targets/TARGET_NUVOTON/TARGET_NANO100/lp_ticker.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/lp_ticker.c Tue Mar 20 16:56:18 2018 +0000
@@ -13,215 +13,149 @@
* See the License for the specific language governing permissions and
* limitations under the License.
*/
-
+
#include "lp_ticker_api.h"
#if DEVICE_LOWPOWERTIMER
#include "sleep_api.h"
+#include "mbed_wait_api.h"
+#include "mbed_assert.h"
#include "nu_modutil.h"
#include "nu_miscutil.h"
-#include "mbed_critical.h"
-#include "mbed_wait_api.h"
-
-// lp_ticker tick = us = timestamp
-#define US_PER_TICK (1)
-#define US_PER_SEC (1000 * 1000)
-
-#define US_PER_TMR2_INT (US_PER_SEC * 10)
-#define TMR2_CLK_PER_SEC (__LXT)
-#define TMR2_CLK_PER_TMR2_INT ((uint32_t) ((uint64_t) US_PER_TMR2_INT * TMR2_CLK_PER_SEC / US_PER_SEC))
-#define TMR3_CLK_PER_SEC (__LXT)
-void TMR2_IRQHandler(void);
-void TMR3_IRQHandler(void);
-static void lp_ticker_arm_cd(void);
+/* Micro seconds per second */
+#define NU_US_PER_SEC 1000000
+/* Timer clock per lp_ticker tick */
+#define NU_TMRCLK_PER_TICK 1
+/* Timer clock per second */
+#define NU_TMRCLK_PER_SEC (__LXT)
+/* Timer max counter bit size */
+#define NU_TMR_MAXCNT_BITSIZE 24
+/* Timer max counter */
+#define NU_TMR_MAXCNT ((1 << NU_TMR_MAXCNT_BITSIZE) - 1)
-static int lp_ticker_inited = 0;
-static volatile uint32_t counter_major = 0;
-static volatile uint32_t cd_major_minor_clks = 0;
-static volatile uint32_t cd_minor_clks = 0;
-static volatile uint32_t wakeup_tick = (uint32_t) -1;
+/* NOTE: Don't add static modifier here. These IRQ handler symbols are for linking.
+ Vector table relocation is not actually supported for low-resource target. */
+void TMR1_IRQHandler(void);
-// NOTE: To wake the system from power down mode, timer clock source must be ether LXT or LIRC.
-// NOTE: TIMER_2 for normal counting and TIMER_3 for scheduled wakeup
-static const struct nu_modinit_s timer2_modinit = {TIMER_2, TMR2_MODULE, CLK_CLKSEL2_TMR2_S_LXT, 0, TMR2_RST, TMR2_IRQn, (void *) TMR2_IRQHandler};
-static const struct nu_modinit_s timer3_modinit = {TIMER_3, TMR3_MODULE, CLK_CLKSEL2_TMR3_S_LXT, 0, TMR3_RST, TMR3_IRQn, (void *) TMR3_IRQHandler};
+/* NOTE: To wake the system from power down mode, timer clock source must be ether LXT or LIRC. */
+static const struct nu_modinit_s timer1_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1_S_LXT, 0, TMR1_RST, TMR1_IRQn, (void *) TMR1_IRQHandler};
+
+#define TIMER_MODINIT timer1_modinit
+
+static int ticker_inited = 0;
#define TMR_CMP_MIN 2
#define TMR_CMP_MAX 0xFFFFFFu
void lp_ticker_init(void)
{
- if (lp_ticker_inited) {
+ if (ticker_inited) {
return;
}
- lp_ticker_inited = 1;
-
- counter_major = 0;
- cd_major_minor_clks = 0;
- cd_minor_clks = 0;
- wakeup_tick = (uint32_t) -1;
+ ticker_inited = 1;
// Reset module
- SYS_ResetModule(timer2_modinit.rsetidx);
- SYS_ResetModule(timer3_modinit.rsetidx);
-
+ SYS_ResetModule(TIMER_MODINIT.rsetidx);
+
// Select IP clock source
- CLK_SetModuleClock(timer2_modinit.clkidx, timer2_modinit.clksrc, timer2_modinit.clkdiv);
- CLK_SetModuleClock(timer3_modinit.clkidx, timer3_modinit.clksrc, timer3_modinit.clkdiv);
+ CLK_SetModuleClock(TIMER_MODINIT.clkidx, TIMER_MODINIT.clksrc, TIMER_MODINIT.clkdiv);
+
// Enable IP clock
- CLK_EnableModuleClock(timer2_modinit.clkidx);
- CLK_EnableModuleClock(timer3_modinit.clkidx);
+ CLK_EnableModuleClock(TIMER_MODINIT.clkidx);
// Configure clock
- uint32_t clk_timer2 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
- uint32_t prescale_timer2 = clk_timer2 / TMR2_CLK_PER_SEC - 1;
- MBED_ASSERT((prescale_timer2 != (uint32_t) -1) && prescale_timer2 <= 127);
- MBED_ASSERT((clk_timer2 % TMR2_CLK_PER_SEC) == 0);
- uint32_t cmp_timer2 = TMR2_CLK_PER_TMR2_INT;
- MBED_ASSERT(cmp_timer2 >= TMR_CMP_MIN && cmp_timer2 <= TMR_CMP_MAX);
+ uint32_t clk_timer = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+ uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1;
+ MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127);
+ MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0);
+ uint32_t cmp_timer = TMR_CMP_MAX;
+ MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX);
// Continuous mode
- ((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CTL = TIMER_PERIODIC_MODE;
- ((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->PRECNT = prescale_timer2;
- ((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CMPR = cmp_timer2;
-
+ ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CTL = TIMER_CONTINUOUS_MODE;
+ ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->PRECNT = prescale_timer;
+ ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CMPR = cmp_timer;
+
// Set vector
- NVIC_SetVector(timer2_modinit.irq_n, (uint32_t) timer2_modinit.var);
- NVIC_SetVector(timer3_modinit.irq_n, (uint32_t) timer3_modinit.var);
-
- NVIC_EnableIRQ(timer2_modinit.irq_n);
- NVIC_EnableIRQ(timer3_modinit.irq_n);
-
- TIMER_EnableInt((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
- TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
-
- // NOTE: TIMER_Start() first and then lp_ticker_set_interrupt(); otherwise, we may get stuck in lp_ticker_read() because
- // timer is not running.
+ NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var);
+
+ NVIC_EnableIRQ(TIMER_MODINIT.irq_n);
- // Wait 3 cycles of engine clock to ensure previous CTL write action is finish
- nu_nop(SystemCoreClock / __LXT * 3);
- // Start timer
- TIMER_Start((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
-
- // Schedule wakeup to match semantics of lp_ticker_get_compare_match()
- lp_ticker_set_interrupt(wakeup_tick);
+ TIMER_EnableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+ TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+ /* NOTE: When engine is clocked by low power clock source (LXT/LIRC), we need to wait for 3 engine clocks. */
+ wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+ TIMER_Start((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
}
timestamp_t lp_ticker_read()
-{
- if (! lp_ticker_inited) {
+{
+ if (! ticker_inited) {
lp_ticker_init();
}
-
- TIMER_T * timer2_base = (TIMER_T *) NU_MODBASE(timer2_modinit.modname);
-
- do {
- uint64_t major_minor_clks;
- uint32_t minor_clks;
-
- // NOTE: As TIMER_DR = TIMER_CMPR and counter_major has increased by one, TIMER_DR doesn't change to 0 for one tick time.
- // NOTE: As TIMER_DR = TIMER_CMPR or TIMER_DR = 0, counter_major (ISR) may not sync with TIMER_DR. So skip and fetch stable one at the cost of 1 clock delay on this read.
- do {
- core_util_critical_section_enter();
-
- // NOTE: Order of reading minor_us/carry here is significant.
- minor_clks = TIMER_GetCounter(timer2_base);
- uint32_t carry = (timer2_base->ISR & TIMER_ISR_TMR_IS_Msk) ? 1 : 0;
- // When TIMER_DR approaches TIMER_CMPR and will wrap soon, we may get carry but TIMER_DR not wrapped. Hanlde carefully carry == 1 && TIMER_DR is near TIMER_CMPR.
- if (carry && minor_clks > (TMR2_CLK_PER_TMR2_INT / 2)) {
- major_minor_clks = (counter_major + 1) * TMR2_CLK_PER_TMR2_INT;
- }
- else {
- major_minor_clks = (counter_major + carry) * TMR2_CLK_PER_TMR2_INT + minor_clks;
- }
-
- core_util_critical_section_exit();
- }
- while (minor_clks == 0 || minor_clks == TMR2_CLK_PER_TMR2_INT);
- // Add power-down compensation
- return ((uint64_t) major_minor_clks * US_PER_SEC / TMR2_CLK_PER_SEC / US_PER_TICK);
- }
- while (0);
+ TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
+
+ return (TIMER_GetCounter(timer_base) / NU_TMRCLK_PER_TICK);
}
void lp_ticker_set_interrupt(timestamp_t timestamp)
{
- uint32_t delta = timestamp - lp_ticker_read();
- wakeup_tick = timestamp;
-
- TIMER_Stop((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
- cd_major_minor_clks = (uint64_t) delta * US_PER_TICK * TMR3_CLK_PER_SEC / US_PER_SEC;
- lp_ticker_arm_cd();
-
-}
+ /* In continuous mode, counter will be reset to zero with the following sequence:
+ * 1. Stop counting
+ * 2. Configure new CMP value
+ * 3. Restart counting
+ *
+ * This behavior is not what we want. To fix it, we could configure new CMP value
+ * without stopping counting first.
+ */
+ TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
-void lp_ticker_fire_interrupt(void)
-{
- cd_major_minor_clks = cd_minor_clks = 0;
- /**
- * This event was in the past. Set the interrupt as pending, but don't process it here.
- * This prevents a recurive loop under heavy load which can lead to a stack overflow.
- */
- NVIC_SetPendingIRQ(timer3_modinit.irq_n);
+ /* NOTE: Because H/W timer requests min compare value, our implementation would have alarm delay of
+ * (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */
+ uint32_t cmp_timer = timestamp * NU_TMRCLK_PER_TICK;
+ cmp_timer = NU_CLAMP(cmp_timer, TMR_CMP_MIN, TMR_CMP_MAX);
+ timer_base->CMPR = cmp_timer;
+
+ /* NOTE: When engine is clocked by low power clock source (LXT/LIRC), we need to wait for 3 engine clocks. */
+ wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+ TIMER_Start(timer_base);
}
void lp_ticker_disable_interrupt(void)
{
- TIMER_DisableInt((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
+ TIMER_DisableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
}
void lp_ticker_clear_interrupt(void)
{
- TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
-}
-
-void TMR2_IRQHandler(void)
-{
- TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
- TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
- counter_major ++;
+ TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
}
-void TMR3_IRQHandler(void)
+void lp_ticker_fire_interrupt(void)
{
- TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
- TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
- cd_major_minor_clks = (cd_major_minor_clks > cd_minor_clks) ? (cd_major_minor_clks - cd_minor_clks) : 0;
- if (cd_major_minor_clks == 0) {
- // NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler();
- lp_ticker_irq_handler();
- }
- else {
- lp_ticker_arm_cd();
- }
+ // NOTE: This event was in the past. Set the interrupt as pending, but don't process it here.
+ // This prevents a recursive loop under heavy load which can lead to a stack overflow.
+ NVIC_SetPendingIRQ(TIMER_MODINIT.irq_n);
}
-static void lp_ticker_arm_cd(void)
+const ticker_info_t* lp_ticker_get_info()
{
- TIMER_T * timer3_base = (TIMER_T *) NU_MODBASE(timer3_modinit.modname);
+ static const ticker_info_t info = {
+ NU_TMRCLK_PER_SEC / NU_TMRCLK_PER_TICK,
+ NU_TMR_MAXCNT_BITSIZE
+ };
+ return &info;
+}
+
+void TMR1_IRQHandler(void)
+{
+ TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+ TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
- // Reset Timer's pre-scale counter, internal 24-bit up-counter and TMR_CTL [TMR_EN] bit
- timer3_base->CTL |= TIMER_CTL_SW_RST_Msk;
- // One-shot mode, Clock = 1 KHz
- uint32_t clk_timer3 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
- uint32_t prescale_timer3 = clk_timer3 / TMR3_CLK_PER_SEC - 1;
- MBED_ASSERT((prescale_timer3 != (uint32_t) -1) && prescale_timer3 <= 127);
- MBED_ASSERT((clk_timer3 % TMR3_CLK_PER_SEC) == 0);
- uint32_t ctl_timer3 = timer3_base->CTL;
- ctl_timer3 &= ~TIMER_CTL_MODE_SEL_Msk;
- ctl_timer3 |= TIMER_ONESHOT_MODE;
- timer3_base->PRECNT = prescale_timer3;
-
- cd_minor_clks = cd_major_minor_clks;
- cd_minor_clks = NU_CLAMP(cd_minor_clks, TMR_CMP_MIN, TMR_CMP_MAX);
- timer3_base->CMPR = cd_minor_clks;
-
- TIMER_EnableInt(timer3_base);
- TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
- // Wait 2 cycles of engine clock to ensure previous CTL write action is finish
- wait_us(30 * 2);
- timer3_base->CTL |= ctl_timer3 | TIMER_CTL_TMR_EN_Msk;
+ // NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler();
+ lp_ticker_irq_handler();
}
+
#endif
--- a/targets/TARGET_NUVOTON/TARGET_NANO100/us_ticker.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NANO100/us_ticker.c Tue Mar 20 16:56:18 2018 +0000
@@ -13,192 +13,132 @@
* See the License for the specific language governing permissions and
* limitations under the License.
*/
-
+
#include "us_ticker_api.h"
#include "sleep_api.h"
#include "mbed_assert.h"
#include "nu_modutil.h"
#include "nu_miscutil.h"
-#include "mbed_critical.h"
-
-// us_ticker tick = us = timestamp
-#define US_PER_TICK 1
-#define US_PER_SEC (1000 * 1000)
-
-#define TMR0HIRES_CLK_PER_SEC (1000 * 1000)
-#define TMR1HIRES_CLK_PER_SEC (1000 * 1000)
-
-#define US_PER_TMR0HIRES_CLK (US_PER_SEC / TMR0HIRES_CLK_PER_SEC)
-#define US_PER_TMR1HIRES_CLK (US_PER_SEC / TMR1HIRES_CLK_PER_SEC)
-
-#define US_PER_TMR0HIRES_INT (1000 * 1000 * 10)
-#define TMR0HIRES_CLK_PER_TMR0HIRES_INT ((uint32_t) ((uint64_t) US_PER_TMR0HIRES_INT * TMR0HIRES_CLK_PER_SEC / US_PER_SEC))
-
-void TMR0_IRQHandler(void);
-void TMR1_IRQHandler(void);
-static void us_ticker_arm_cd(void);
+/* Micro seconds per second */
+#define NU_US_PER_SEC 1000000
+/* Timer clock per us_ticker tick */
+#define NU_TMRCLK_PER_TICK 1
+/* Timer clock per second */
+#define NU_TMRCLK_PER_SEC (1000 * 1000)
+/* Timer max counter bit size */
+#define NU_TMR_MAXCNT_BITSIZE 24
+/* Timer max counter */
+#define NU_TMR_MAXCNT ((1 << NU_TMR_MAXCNT_BITSIZE) - 1)
-static int us_ticker_inited = 0;
-static volatile uint32_t counter_major = 0;
-static volatile uint32_t cd_major_minor_us = 0;
-static volatile uint32_t cd_minor_us = 0;
+/* NOTE: Don't add static modifier here. These IRQ handler symbols are for linking.
+ Vector table relocation is not actually supported for low-resource target. */
+void TMR0_IRQHandler(void);
-// NOTE: Choose clock source of timer:
-// 1. HIRC: Be the most accurate but might cause unknown HardFault.
-// 2. HXT: Less accurate and cannot pass mbed-drivers test.
-// NOTE: TIMER_0 for normal counter, TIMER_1 for countdown.
-static const struct nu_modinit_s timer0hires_modinit = {TIMER_0, TMR0_MODULE, CLK_CLKSEL1_TMR0_S_HXT, 0, TMR0_RST, TMR0_IRQn, (void *) TMR0_IRQHandler};
-static const struct nu_modinit_s timer1hires_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1_S_HXT, 0, TMR1_RST, TMR1_IRQn, (void *) TMR1_IRQHandler};
+static const struct nu_modinit_s timer0_modinit = {TIMER_0, TMR0_MODULE, CLK_CLKSEL1_TMR0_S_HXT, 0, TMR0_RST, TMR0_IRQn, (void *) TMR0_IRQHandler};
+
+#define TIMER_MODINIT timer0_modinit
+
+static int ticker_inited = 0;
#define TMR_CMP_MIN 2
#define TMR_CMP_MAX 0xFFFFFFu
void us_ticker_init(void)
{
- if (us_ticker_inited) {
+ if (ticker_inited) {
return;
}
-
- counter_major = 0;
- cd_major_minor_us = 0;
- cd_minor_us = 0;
- us_ticker_inited = 1;
-
+ ticker_inited = 1;
+
// Reset IP
- SYS_ResetModule(timer0hires_modinit.rsetidx);
- SYS_ResetModule(timer1hires_modinit.rsetidx);
-
+ SYS_ResetModule(TIMER_MODINIT.rsetidx);
+
// Select IP clock source
- CLK_SetModuleClock(timer0hires_modinit.clkidx, timer0hires_modinit.clksrc, timer0hires_modinit.clkdiv);
- CLK_SetModuleClock(timer1hires_modinit.clkidx, timer1hires_modinit.clksrc, timer1hires_modinit.clkdiv);
+ CLK_SetModuleClock(TIMER_MODINIT.clkidx, TIMER_MODINIT.clksrc, TIMER_MODINIT.clkdiv);
+
// Enable IP clock
- CLK_EnableModuleClock(timer0hires_modinit.clkidx);
- CLK_EnableModuleClock(timer1hires_modinit.clkidx);
+ CLK_EnableModuleClock(TIMER_MODINIT.clkidx);
// Timer for normal counter
- uint32_t clk_timer0 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
- uint32_t prescale_timer0 = clk_timer0 / TMR0HIRES_CLK_PER_SEC - 1;
- MBED_ASSERT((prescale_timer0 != (uint32_t) -1) && prescale_timer0 <= 127);
- MBED_ASSERT((clk_timer0 % TMR0HIRES_CLK_PER_SEC) == 0);
- uint32_t cmp_timer0 = TMR0HIRES_CLK_PER_TMR0HIRES_INT;
- MBED_ASSERT(cmp_timer0 >= TMR_CMP_MIN && cmp_timer0 <= TMR_CMP_MAX);
- ((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname))->CTL = TIMER_PERIODIC_MODE;
- ((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname))->PRECNT = prescale_timer0;
- ((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname))->CMPR = cmp_timer0;
-
- NVIC_SetVector(timer0hires_modinit.irq_n, (uint32_t) timer0hires_modinit.var);
- NVIC_SetVector(timer1hires_modinit.irq_n, (uint32_t) timer1hires_modinit.var);
-
- NVIC_EnableIRQ(timer0hires_modinit.irq_n);
- NVIC_EnableIRQ(timer1hires_modinit.irq_n);
-
- TIMER_EnableInt((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
- TIMER_Start((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
+ uint32_t clk_timer = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+ uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1;
+ MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127);
+ MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0);
+ uint32_t cmp_timer = TMR_CMP_MAX;
+ MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX);
+ ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CTL = TIMER_CONTINUOUS_MODE;
+ ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->PRECNT = prescale_timer;
+ ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CMPR = cmp_timer;
+
+ NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var);
+
+ NVIC_EnableIRQ(TIMER_MODINIT.irq_n);
+
+ TIMER_EnableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+ TIMER_Start((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
}
uint32_t us_ticker_read()
{
- if (! us_ticker_inited) {
+ if (! ticker_inited) {
us_ticker_init();
}
-
- TIMER_T * timer0_base = (TIMER_T *) NU_MODBASE(timer0hires_modinit.modname);
-
- do {
- uint32_t major_minor_us;
- uint32_t minor_us;
- // NOTE: As TIMER_DR = TIMER_CMPR and counter_major has increased by one, TIMER_DR doesn't change to 0 for one tick time.
- // NOTE: As TIMER_DR = TIMER_CMPR or TIMER_DR = 0, counter_major (ISR) may not sync with TIMER_DR. So skip and fetch stable one at the cost of 1 clock delay on this read.
- do {
- core_util_critical_section_enter();
-
- // NOTE: Order of reading minor_us/carry here is significant.
- minor_us = TIMER_GetCounter(timer0_base) * US_PER_TMR0HIRES_CLK;
- uint32_t carry = (timer0_base->ISR & TIMER_ISR_TMR_IS_Msk) ? 1 : 0;
- // When TIMER_DR approaches TIMER_CMPR and will wrap soon, we may get carry but TIMER_DR not wrapped. Hanlde carefully carry == 1 && TIMER_DR is near TIMER_CMPR.
- if (carry && minor_us > (US_PER_TMR0HIRES_INT / 2)) {
- major_minor_us = (counter_major + 1) * US_PER_TMR0HIRES_INT;
- }
- else {
- major_minor_us = (counter_major + carry) * US_PER_TMR0HIRES_INT + minor_us;
- }
-
- core_util_critical_section_exit();
- }
- while (minor_us == 0 || minor_us == US_PER_TMR0HIRES_INT);
-
- return (major_minor_us / US_PER_TICK);
- }
- while (0);
-}
+ TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
-void us_ticker_disable_interrupt(void)
-{
- TIMER_DisableInt((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname));
-}
-
-void us_ticker_clear_interrupt(void)
-{
- TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname));
+ return (TIMER_GetCounter(timer_base) / NU_TMRCLK_PER_TICK);
}
void us_ticker_set_interrupt(timestamp_t timestamp)
{
- TIMER_Stop((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname));
-
- uint32_t delta = timestamp - us_ticker_read();
- cd_major_minor_us = delta * US_PER_TICK;
- us_ticker_arm_cd();
+ /* In continuous mode, counter will be reset to zero with the following sequence:
+ * 1. Stop counting
+ * 2. Configure new CMP value
+ * 3. Restart counting
+ *
+ * This behavior is not what we want. To fix it, we could configure new CMP value
+ * without stopping counting first.
+ */
+ TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
+
+ /* NOTE: Because H/W timer requests min compare value, our implementation would have alarm delay of
+ * (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */
+ uint32_t cmp_timer = timestamp * NU_TMRCLK_PER_TICK;
+ cmp_timer = NU_CLAMP(cmp_timer, TMR_CMP_MIN, TMR_CMP_MAX);
+ timer_base->CMPR = cmp_timer;
+}
+
+void us_ticker_disable_interrupt(void)
+{
+ TIMER_DisableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+}
+
+void us_ticker_clear_interrupt(void)
+{
+ TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
}
void us_ticker_fire_interrupt(void)
{
- cd_major_minor_us = cd_minor_us = 0;
- NVIC_SetPendingIRQ(timer1hires_modinit.irq_n);
+ // NOTE: This event was in the past. Set the interrupt as pending, but don't process it here.
+ // This prevents a recursive loop under heavy load which can lead to a stack overflow.
+ NVIC_SetPendingIRQ(TIMER_MODINIT.irq_n);
+}
+
+const ticker_info_t* us_ticker_get_info()
+{
+ static const ticker_info_t info = {
+ NU_TMRCLK_PER_SEC / NU_TMRCLK_PER_TICK,
+ NU_TMR_MAXCNT_BITSIZE
+ };
+ return &info;
}
void TMR0_IRQHandler(void)
{
- TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
- counter_major ++;
-}
-
-void TMR1_IRQHandler(void)
-{
- TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname));
- cd_major_minor_us = (cd_major_minor_us > cd_minor_us) ? (cd_major_minor_us - cd_minor_us) : 0;
- if (cd_major_minor_us == 0) {
- // NOTE: us_ticker_set_interrupt() may get called in us_ticker_irq_handler();
- us_ticker_irq_handler();
- }
- else {
- us_ticker_arm_cd();
- }
-}
-
-static void us_ticker_arm_cd(void)
-{
- TIMER_T * timer1_base = (TIMER_T *) NU_MODBASE(timer1hires_modinit.modname);
+ TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
- cd_minor_us = cd_major_minor_us;
-
- // Reset Timer's pre-scale counter, internal 24-bit up-counter and TMR_CTL [TMR_EN] bit
- timer1_base->CTL |= TIMER_CTL_SW_RST_Msk;
- // One-shot mode, Clock = 1 MHz
- uint32_t clk_timer1 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname));
- uint32_t prescale_timer1 = clk_timer1 / TMR1HIRES_CLK_PER_SEC - 1;
- MBED_ASSERT((prescale_timer1 != (uint32_t) -1) && prescale_timer1 <= 127);
- MBED_ASSERT((clk_timer1 % TMR1HIRES_CLK_PER_SEC) == 0);
- timer1_base->CTL &= ~TIMER_CTL_MODE_SEL_Msk;
- timer1_base->CTL |= TIMER_ONESHOT_MODE;
- timer1_base->PRECNT = prescale_timer1;
-
- uint32_t cmp_timer1 = cd_minor_us / US_PER_TMR1HIRES_CLK;
- cmp_timer1 = NU_CLAMP(cmp_timer1, TMR_CMP_MIN, TMR_CMP_MAX);
- timer1_base->CMPR = cmp_timer1;
-
- TIMER_EnableInt(timer1_base);
- TIMER_Start(timer1_base);
+ // NOTE: us_ticker_set_interrupt() may get called in us_ticker_irq_handler();
+ us_ticker_irq_handler();
}
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/PinNames.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/TARGET_NUMAKER_PFM_NUC472/PinNames.h Tue Mar 20 16:56:18 2018 +0000
@@ -107,13 +107,18 @@
D13 = PD_0,
D14 = PD_12,
D15 = PD_10,
-
- // FIXME: other board-specific naming
+
+ I2C_SCL = D15,
+ I2C_SDA = D14,
+
+ // NOTE: other board-specific naming
// UART naming
USBTX = PD_5,
USBRX = PD_4,
STDIO_UART_TX = USBTX,
STDIO_UART_RX = USBRX,
+ SERIAL_TX = USBTX,
+ SERIAL_RX = USBRX,
// LED naming
LED1 = PD_9,
LED2 = PA_4,
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/crypto/crypto-misc.c Tue Mar 20 16:56:18 2018 +0000
@@ -37,6 +37,10 @@
static bool crypto_submodule_acquire(uint16_t *submodule_avail);
static void crypto_submodule_release(uint16_t *submodule_avail);
+/* Crypto done flags */
+#define CRYPTO_DONE_OK BIT0 /* Done with OK */
+#define CRYPTO_DONE_ERR BIT1 /* Done with error */
+
/* Track if PRNG H/W operation is done */
static volatile uint16_t crypto_prng_done;
/* Track if AES H/W operation is done */
@@ -96,7 +100,7 @@
/* Implementation that should never be optimized out by the compiler */
void crypto_zeroize(void *v, size_t n)
{
- volatile unsigned char *p = (unsigned char*) v;
+ volatile unsigned char *p = (volatile unsigned char*) v;
while (n--) {
*p++ = 0;
}
@@ -236,20 +240,36 @@
/* Ensure while loop above and subsequent code are not reordered */
__DSB();
- return true;
+ if ((*submodule_done & CRYPTO_DONE_OK)) {
+ /* Done with OK */
+ return true;
+ } else if ((*submodule_done & CRYPTO_DONE_ERR)) {
+ /* Done with error */
+ return false;
+ }
+
+ return false;
}
/* Crypto interrupt handler */
void CRYPTO_IRQHandler()
{
- if (PRNG_GET_INT_FLAG()) {
- crypto_prng_done = 1;
+ uint32_t intsts;
+
+ if ((intsts = PRNG_GET_INT_FLAG()) != 0) {
+ /* Done with OK */
+ crypto_prng_done |= CRYPTO_DONE_OK;
+ /* Clear interrupt flag */
PRNG_CLR_INT_FLAG();
- } else if (AES_GET_INT_FLAG()) {
- crypto_aes_done = 1;
+ } else if ((intsts = AES_GET_INT_FLAG()) != 0) {
+ /* Done with OK */
+ crypto_aes_done |= CRYPTO_DONE_OK;
+ /* Clear interrupt flag */
AES_CLR_INT_FLAG();
- } else if (TDES_GET_INT_FLAG()) {
- crypto_des_done = 1;
+ } else if ((intsts = TDES_GET_INT_FLAG()) != 0) {
+ /* Done with OK */
+ crypto_des_done |= CRYPTO_DONE_OK;
+ /* Clear interrupt flag */
TDES_CLR_INT_FLAG();
}
}
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/lp_ticker.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/lp_ticker.c Tue Mar 20 16:56:18 2018 +0000
@@ -13,207 +13,146 @@
* See the License for the specific language governing permissions and
* limitations under the License.
*/
-
+
#include "lp_ticker_api.h"
#if DEVICE_LOWPOWERTIMER
#include "sleep_api.h"
+#include "mbed_wait_api.h"
+#include "mbed_assert.h"
#include "nu_modutil.h"
#include "nu_miscutil.h"
-#include "mbed_critical.h"
-
-// lp_ticker tick = us = timestamp
-#define US_PER_TICK (1)
-#define US_PER_SEC (1000 * 1000)
-
-#define US_PER_TMR2_INT (US_PER_SEC * 10)
-#define TMR2_CLK_PER_SEC (__LXT)
-#define TMR2_CLK_PER_TMR2_INT ((uint32_t) ((uint64_t) US_PER_TMR2_INT * TMR2_CLK_PER_SEC / US_PER_SEC))
-#define TMR3_CLK_PER_SEC (__LXT)
-static void tmr2_vec(void);
-static void tmr3_vec(void);
-static void lp_ticker_arm_cd(void);
+/* Micro seconds per second */
+#define NU_US_PER_SEC 1000000
+/* Timer clock per lp_ticker tick */
+#define NU_TMRCLK_PER_TICK 1
+/* Timer clock per second */
+#define NU_TMRCLK_PER_SEC (__LXT)
+/* Timer max counter bit size */
+#define NU_TMR_MAXCNT_BITSIZE 24
+/* Timer max counter */
+#define NU_TMR_MAXCNT ((1 << NU_TMR_MAXCNT_BITSIZE) - 1)
-static int lp_ticker_inited = 0;
-static volatile uint32_t counter_major = 0;
-static volatile uint32_t cd_major_minor_clks = 0;
-static volatile uint32_t cd_minor_clks = 0;
-static volatile uint32_t wakeup_tick = (uint32_t) -1;
+static void tmr1_vec(void);
-// NOTE: To wake the system from power down mode, timer clock source must be ether LXT or LIRC.
-// NOTE: TIMER_2 for normal counting and TIMER_3 for scheduled wakeup
-static const struct nu_modinit_s timer2_modinit = {TIMER_2, TMR2_MODULE, CLK_CLKSEL1_TMR2SEL_LXT, 0, TMR2_RST, TMR2_IRQn, (void *) tmr2_vec};
-static const struct nu_modinit_s timer3_modinit = {TIMER_3, TMR3_MODULE, CLK_CLKSEL1_TMR3SEL_LXT, 0, TMR3_RST, TMR3_IRQn, (void *) tmr3_vec};
+/* NOTE: To wake the system from power down mode, timer clock source must be ether LXT or LIRC. */
+static const struct nu_modinit_s timer1_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_LXT, 0, TMR1_RST, TMR1_IRQn, (void *) tmr1_vec};
+
+#define TIMER_MODINIT timer1_modinit
+
+static int ticker_inited = 0;
#define TMR_CMP_MIN 2
#define TMR_CMP_MAX 0xFFFFFFu
void lp_ticker_init(void)
{
- if (lp_ticker_inited) {
+ if (ticker_inited) {
return;
}
- lp_ticker_inited = 1;
-
- counter_major = 0;
- cd_major_minor_clks = 0;
- cd_minor_clks = 0;
- wakeup_tick = (uint32_t) -1;
+ ticker_inited = 1;
// Reset module
- SYS_ResetModule(timer2_modinit.rsetidx);
- SYS_ResetModule(timer3_modinit.rsetidx);
-
+ SYS_ResetModule(TIMER_MODINIT.rsetidx);
+
// Select IP clock source
- CLK_SetModuleClock(timer2_modinit.clkidx, timer2_modinit.clksrc, timer2_modinit.clkdiv);
- CLK_SetModuleClock(timer3_modinit.clkidx, timer3_modinit.clksrc, timer3_modinit.clkdiv);
+ CLK_SetModuleClock(TIMER_MODINIT.clkidx, TIMER_MODINIT.clksrc, TIMER_MODINIT.clkdiv);
+
// Enable IP clock
- CLK_EnableModuleClock(timer2_modinit.clkidx);
- CLK_EnableModuleClock(timer3_modinit.clkidx);
+ CLK_EnableModuleClock(TIMER_MODINIT.clkidx);
// Configure clock
- uint32_t clk_timer2 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
- uint32_t prescale_timer2 = clk_timer2 / TMR2_CLK_PER_SEC - 1;
- MBED_ASSERT((prescale_timer2 != (uint32_t) -1) && prescale_timer2 <= 127);
- MBED_ASSERT((clk_timer2 % TMR2_CLK_PER_SEC) == 0);
- uint32_t cmp_timer2 = TMR2_CLK_PER_TMR2_INT;
- MBED_ASSERT(cmp_timer2 >= TMR_CMP_MIN && cmp_timer2 <= TMR_CMP_MAX);
+ uint32_t clk_timer = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+ uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1;
+ MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127);
+ MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0);
+ uint32_t cmp_timer = TMR_CMP_MAX;
+ MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX);
// Continuous mode
- ((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CTL = TIMER_PERIODIC_MODE | prescale_timer2 | TIMER_CTL_CNTDATEN_Msk;
- ((TIMER_T *) NU_MODBASE(timer2_modinit.modname))->CMP = cmp_timer2;
-
+ ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CTL = TIMER_CONTINUOUS_MODE | prescale_timer | TIMER_CTL_CNTDATEN_Msk;
+ ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CMP = cmp_timer;
+
// Set vector
- NVIC_SetVector(timer2_modinit.irq_n, (uint32_t) timer2_modinit.var);
- NVIC_SetVector(timer3_modinit.irq_n, (uint32_t) timer3_modinit.var);
-
- NVIC_EnableIRQ(timer2_modinit.irq_n);
- NVIC_EnableIRQ(timer3_modinit.irq_n);
-
- TIMER_EnableInt((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
- TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
-
- // NOTE: TIMER_Start() first and then lp_ticker_set_interrupt(); otherwise, we may get stuck in lp_ticker_read() because
- // timer is not running.
-
- // Start timer
- TIMER_Start((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
-
- // Schedule wakeup to match semantics of lp_ticker_get_compare_match()
- lp_ticker_set_interrupt(wakeup_tick);
+ NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var);
+
+ NVIC_EnableIRQ(TIMER_MODINIT.irq_n);
+
+ TIMER_EnableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+ TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+ /* NOTE: When engine is clocked by low power clock source (LXT/LIRC), we need to wait for 3 engine clocks. */
+ wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+ TIMER_Start((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
}
timestamp_t lp_ticker_read()
-{
- if (! lp_ticker_inited) {
+{
+ if (! ticker_inited) {
lp_ticker_init();
}
-
- TIMER_T * timer2_base = (TIMER_T *) NU_MODBASE(timer2_modinit.modname);
-
- do {
- uint64_t major_minor_clks;
- uint32_t minor_clks;
-
- // NOTE: As TIMER_CNT = TIMER_CMP and counter_major has increased by one, TIMER_CNT doesn't change to 0 for one tick time.
- // NOTE: As TIMER_CNT = TIMER_CMP or TIMER_CNT = 0, counter_major (ISR) may not sync with TIMER_CNT. So skip and fetch stable one at the cost of 1 clock delay on this read.
- do {
- core_util_critical_section_enter();
-
- // NOTE: Order of reading minor_us/carry here is significant.
- minor_clks = TIMER_GetCounter(timer2_base);
- uint32_t carry = (timer2_base->INTSTS & TIMER_INTSTS_TIF_Msk) ? 1 : 0;
- // When TIMER_CNT approaches TIMER_CMP and will wrap soon, we may get carry but TIMER_CNT not wrapped. Hanlde carefully carry == 1 && TIMER_CNT is near TIMER_CMP.
- if (carry && minor_clks > (TMR2_CLK_PER_TMR2_INT / 2)) {
- major_minor_clks = (counter_major + 1) * TMR2_CLK_PER_TMR2_INT;
- }
- else {
- major_minor_clks = (counter_major + carry) * TMR2_CLK_PER_TMR2_INT + minor_clks;
- }
-
- core_util_critical_section_exit();
- }
- while (minor_clks == 0 || minor_clks == TMR2_CLK_PER_TMR2_INT);
- // Add power-down compensation
- return ((uint64_t) major_minor_clks * US_PER_SEC / TMR2_CLK_PER_SEC / US_PER_TICK);
- }
- while (0);
+ TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
+
+ return (TIMER_GetCounter(timer_base) / NU_TMRCLK_PER_TICK);
}
void lp_ticker_set_interrupt(timestamp_t timestamp)
{
- uint32_t delta = timestamp - lp_ticker_read();
- wakeup_tick = timestamp;
-
- TIMER_Stop((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
- cd_major_minor_clks = (uint64_t) delta * US_PER_TICK * TMR3_CLK_PER_SEC / US_PER_SEC;
- lp_ticker_arm_cd();
-
-}
+ /* In continuous mode, counter will be reset to zero with the following sequence:
+ * 1. Stop counting
+ * 2. Configure new CMP value
+ * 3. Restart counting
+ *
+ * This behavior is not what we want. To fix it, we could configure new CMP value
+ * without stopping counting first.
+ */
+ TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
-void lp_ticker_fire_interrupt(void)
-{
- cd_major_minor_clks = cd_minor_clks = 0;
- /**
- * This event was in the past. Set the interrupt as pending, but don't process it here.
- * This prevents a recurive loop under heavy load which can lead to a stack overflow.
- */
- NVIC_SetPendingIRQ(timer3_modinit.irq_n);
+ /* NOTE: Because H/W timer requests min compare value, our implementation would have alarm delay of
+ * (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */
+ uint32_t cmp_timer = timestamp * NU_TMRCLK_PER_TICK;
+ cmp_timer = NU_CLAMP(cmp_timer, TMR_CMP_MIN, TMR_CMP_MAX);
+ timer_base->CMP = cmp_timer;
+
+ /* NOTE: When engine is clocked by low power clock source (LXT/LIRC), we need to wait for 3 engine clocks. */
+ wait_us((NU_US_PER_SEC / NU_TMRCLK_PER_SEC) * 3);
+ TIMER_Start(timer_base);
}
void lp_ticker_disable_interrupt(void)
{
- TIMER_DisableInt((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
+ TIMER_DisableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
}
void lp_ticker_clear_interrupt(void)
{
- TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
-}
-
-static void tmr2_vec(void)
-{
- TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
- TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(timer2_modinit.modname));
- counter_major ++;
+ TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
}
-static void tmr3_vec(void)
+void lp_ticker_fire_interrupt(void)
{
- TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
- TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
- cd_major_minor_clks = (cd_major_minor_clks > cd_minor_clks) ? (cd_major_minor_clks - cd_minor_clks) : 0;
- if (cd_major_minor_clks == 0) {
- // NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler();
- lp_ticker_irq_handler();
- }
- else {
- lp_ticker_arm_cd();
- }
+ // NOTE: This event was in the past. Set the interrupt as pending, but don't process it here.
+ // This prevents a recursive loop under heavy load which can lead to a stack overflow.
+ NVIC_SetPendingIRQ(TIMER_MODINIT.irq_n);
}
-static void lp_ticker_arm_cd(void)
+const ticker_info_t* lp_ticker_get_info()
{
- TIMER_T * timer3_base = (TIMER_T *) NU_MODBASE(timer3_modinit.modname);
+ static const ticker_info_t info = {
+ NU_TMRCLK_PER_SEC / NU_TMRCLK_PER_TICK,
+ NU_TMR_MAXCNT_BITSIZE
+ };
+ return &info;
+}
+
+static void tmr1_vec(void)
+{
+ TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+ TIMER_ClearWakeupFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
- // Reset 8-bit PSC counter, 24-bit up counter value and CNTEN bit
- timer3_base->CTL |= TIMER_CTL_RSTCNT_Msk;
- // One-shot mode, Clock = 1 KHz
- uint32_t clk_timer3 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
- uint32_t prescale_timer3 = clk_timer3 / TMR3_CLK_PER_SEC - 1;
- MBED_ASSERT((prescale_timer3 != (uint32_t) -1) && prescale_timer3 <= 127);
- MBED_ASSERT((clk_timer3 % TMR3_CLK_PER_SEC) == 0);
- timer3_base->CTL &= ~(TIMER_CTL_OPMODE_Msk | TIMER_CTL_PSC_Msk | TIMER_CTL_CNTDATEN_Msk);
- timer3_base->CTL |= TIMER_ONESHOT_MODE | prescale_timer3 | TIMER_CTL_CNTDATEN_Msk;
-
- cd_minor_clks = cd_major_minor_clks;
- cd_minor_clks = NU_CLAMP(cd_minor_clks, TMR_CMP_MIN, TMR_CMP_MAX);
- timer3_base->CMP = cd_minor_clks;
-
- TIMER_EnableInt(timer3_base);
- TIMER_EnableWakeup((TIMER_T *) NU_MODBASE(timer3_modinit.modname));
- TIMER_Start(timer3_base);
+ // NOTE: lp_ticker_set_interrupt() may get called in lp_ticker_irq_handler();
+ lp_ticker_irq_handler();
}
+
#endif
--- a/targets/TARGET_NUVOTON/TARGET_NUC472/us_ticker.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NUVOTON/TARGET_NUC472/us_ticker.c Tue Mar 20 16:56:18 2018 +0000
@@ -13,192 +13,129 @@
* See the License for the specific language governing permissions and
* limitations under the License.
*/
-
+
#include "us_ticker_api.h"
#include "sleep_api.h"
#include "mbed_assert.h"
#include "nu_modutil.h"
#include "nu_miscutil.h"
-#include "mbed_critical.h"
-// us_ticker tick = us = timestamp
-#define US_PER_TICK 1
-#define US_PER_SEC (1000 * 1000)
-
-#define TMR0HIRES_CLK_PER_SEC (1000 * 1000)
-#define TMR1HIRES_CLK_PER_SEC (1000 * 1000)
-
-#define US_PER_TMR0HIRES_CLK (US_PER_SEC / TMR0HIRES_CLK_PER_SEC)
-#define US_PER_TMR1HIRES_CLK (US_PER_SEC / TMR1HIRES_CLK_PER_SEC)
-
-#define US_PER_TMR0HIRES_INT (1000 * 1000 * 10)
-#define TMR0HIRES_CLK_PER_TMR0HIRES_INT ((uint32_t) ((uint64_t) US_PER_TMR0HIRES_INT * TMR0HIRES_CLK_PER_SEC / US_PER_SEC))
-
+/* Micro seconds per second */
+#define NU_US_PER_SEC 1000000
+/* Timer clock per us_ticker tick */
+#define NU_TMRCLK_PER_TICK 1
+/* Timer clock per second */
+#define NU_TMRCLK_PER_SEC (1000 * 1000)
+/* Timer max counter bit size */
+#define NU_TMR_MAXCNT_BITSIZE 24
+/* Timer max counter */
+#define NU_TMR_MAXCNT ((1 << NU_TMR_MAXCNT_BITSIZE) - 1)
static void tmr0_vec(void);
-static void tmr1_vec(void);
-static void us_ticker_arm_cd(void);
-static int us_ticker_inited = 0;
-static volatile uint32_t counter_major = 0;
-static volatile uint32_t cd_major_minor_us = 0;
-static volatile uint32_t cd_minor_us = 0;
+static const struct nu_modinit_s timer0_modinit = {TIMER_0, TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_PCLK, 0, TMR0_RST, TMR0_IRQn, (void *) tmr0_vec};
-// NOTE: PCLK is set up in mbed_sdk_init(), invocation of which must be before C++ global object constructor. See init_api.c for details.
-// NOTE: Choose clock source of timer:
-// 1. HIRC: Be the most accurate but might cause unknown HardFault.
-// 2. HXT: Less accurate and cannot pass mbed-drivers test.
-// 3. PCLK(HXT): Less accurate but can pass mbed-drivers test.
-// NOTE: TIMER_0 for normal counter, TIMER_1 for countdown.
-static const struct nu_modinit_s timer0hires_modinit = {TIMER_0, TMR0_MODULE, CLK_CLKSEL1_TMR0SEL_PCLK, 0, TMR0_RST, TMR0_IRQn, (void *) tmr0_vec};
-static const struct nu_modinit_s timer1hires_modinit = {TIMER_1, TMR1_MODULE, CLK_CLKSEL1_TMR1SEL_PCLK, 0, TMR1_RST, TMR1_IRQn, (void *) tmr1_vec};
+#define TIMER_MODINIT timer0_modinit
+
+static int ticker_inited = 0;
#define TMR_CMP_MIN 2
#define TMR_CMP_MAX 0xFFFFFFu
void us_ticker_init(void)
{
- if (us_ticker_inited) {
+ if (ticker_inited) {
return;
}
-
- counter_major = 0;
- cd_major_minor_us = 0;
- cd_minor_us = 0;
- us_ticker_inited = 1;
-
+ ticker_inited = 1;
+
// Reset IP
- SYS_ResetModule(timer0hires_modinit.rsetidx);
- SYS_ResetModule(timer1hires_modinit.rsetidx);
-
+ SYS_ResetModule(TIMER_MODINIT.rsetidx);
+
// Select IP clock source
- CLK_SetModuleClock(timer0hires_modinit.clkidx, timer0hires_modinit.clksrc, timer0hires_modinit.clkdiv);
- CLK_SetModuleClock(timer1hires_modinit.clkidx, timer1hires_modinit.clksrc, timer1hires_modinit.clkdiv);
+ CLK_SetModuleClock(TIMER_MODINIT.clkidx, TIMER_MODINIT.clksrc, TIMER_MODINIT.clkdiv);
+
// Enable IP clock
- CLK_EnableModuleClock(timer0hires_modinit.clkidx);
- CLK_EnableModuleClock(timer1hires_modinit.clkidx);
+ CLK_EnableModuleClock(TIMER_MODINIT.clkidx);
// Timer for normal counter
- uint32_t clk_timer0 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
- uint32_t prescale_timer0 = clk_timer0 / TMR0HIRES_CLK_PER_SEC - 1;
- MBED_ASSERT((prescale_timer0 != (uint32_t) -1) && prescale_timer0 <= 127);
- MBED_ASSERT((clk_timer0 % TMR0HIRES_CLK_PER_SEC) == 0);
- uint32_t cmp_timer0 = TMR0HIRES_CLK_PER_TMR0HIRES_INT;
- MBED_ASSERT(cmp_timer0 >= TMR_CMP_MIN && cmp_timer0 <= TMR_CMP_MAX);
- ((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname))->CTL = TIMER_PERIODIC_MODE | prescale_timer0 | TIMER_CTL_CNTDATEN_Msk;
- ((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname))->CMP = cmp_timer0;
-
- NVIC_SetVector(timer0hires_modinit.irq_n, (uint32_t) timer0hires_modinit.var);
- NVIC_SetVector(timer1hires_modinit.irq_n, (uint32_t) timer1hires_modinit.var);
-
- NVIC_EnableIRQ(timer0hires_modinit.irq_n);
- NVIC_EnableIRQ(timer1hires_modinit.irq_n);
-
- TIMER_EnableInt((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
- TIMER_Start((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
+ uint32_t clk_timer = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+ uint32_t prescale_timer = clk_timer / NU_TMRCLK_PER_SEC - 1;
+ MBED_ASSERT((prescale_timer != (uint32_t) -1) && prescale_timer <= 127);
+ MBED_ASSERT((clk_timer % NU_TMRCLK_PER_SEC) == 0);
+ uint32_t cmp_timer = TMR_CMP_MAX;
+ MBED_ASSERT(cmp_timer >= TMR_CMP_MIN && cmp_timer <= TMR_CMP_MAX);
+ ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CTL = TIMER_CONTINUOUS_MODE | prescale_timer | TIMER_CTL_CNTDATEN_Msk;
+ ((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname))->CMP = cmp_timer;
+
+ NVIC_SetVector(TIMER_MODINIT.irq_n, (uint32_t) TIMER_MODINIT.var);
+
+ NVIC_EnableIRQ(TIMER_MODINIT.irq_n);
+
+ TIMER_EnableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+ TIMER_Start((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
}
uint32_t us_ticker_read()
{
- if (! us_ticker_inited) {
+ if (! ticker_inited) {
us_ticker_init();
}
-
- TIMER_T * timer0_base = (TIMER_T *) NU_MODBASE(timer0hires_modinit.modname);
-
- do {
- uint32_t major_minor_us;
- uint32_t minor_us;
- // NOTE: As TIMER_CNT = TIMER_CMP and counter_major has increased by one, TIMER_CNT doesn't change to 0 for one tick time.
- // NOTE: As TIMER_CNT = TIMER_CMP or TIMER_CNT = 0, counter_major (ISR) may not sync with TIMER_CNT. So skip and fetch stable one at the cost of 1 clock delay on this read.
- do {
- core_util_critical_section_enter();
-
- // NOTE: Order of reading minor_us/carry here is significant.
- minor_us = TIMER_GetCounter(timer0_base) * US_PER_TMR0HIRES_CLK;
- uint32_t carry = (timer0_base->INTSTS & TIMER_INTSTS_TIF_Msk) ? 1 : 0;
- // When TIMER_CNT approaches TIMER_CMP and will wrap soon, we may get carry but TIMER_CNT not wrapped. Hanlde carefully carry == 1 && TIMER_CNT is near TIMER_CMP.
- if (carry && minor_us > (US_PER_TMR0HIRES_INT / 2)) {
- major_minor_us = (counter_major + 1) * US_PER_TMR0HIRES_INT;
- }
- else {
- major_minor_us = (counter_major + carry) * US_PER_TMR0HIRES_INT + minor_us;
- }
-
- core_util_critical_section_exit();
- }
- while (minor_us == 0 || minor_us == US_PER_TMR0HIRES_INT);
-
- return (major_minor_us / US_PER_TICK);
- }
- while (0);
-}
+ TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
-void us_ticker_disable_interrupt(void)
-{
- TIMER_DisableInt((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname));
-}
-
-void us_ticker_clear_interrupt(void)
-{
- TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname));
+ return (TIMER_GetCounter(timer_base) / NU_TMRCLK_PER_TICK);
}
void us_ticker_set_interrupt(timestamp_t timestamp)
{
- TIMER_Stop((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname));
-
- uint32_t delta = timestamp - us_ticker_read();
- cd_major_minor_us = delta * US_PER_TICK;
- us_ticker_arm_cd();
+ /* In continuous mode, counter will be reset to zero with the following sequence:
+ * 1. Stop counting
+ * 2. Configure new CMP value
+ * 3. Restart counting
+ *
+ * This behavior is not what we want. To fix it, we could configure new CMP value
+ * without stopping counting first.
+ */
+ TIMER_T * timer_base = (TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname);
+
+ /* NOTE: Because H/W timer requests min compare value, our implementation would have alarm delay of
+ * (TMR_CMP_MIN - interval_clk) clocks when interval_clk is between [1, TMR_CMP_MIN). */
+ uint32_t cmp_timer = timestamp * NU_TMRCLK_PER_TICK;
+ cmp_timer = NU_CLAMP(cmp_timer, TMR_CMP_MIN, TMR_CMP_MAX);
+ timer_base->CMP = cmp_timer;
+}
+
+void us_ticker_disable_interrupt(void)
+{
+ TIMER_DisableInt((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+}
+
+void us_ticker_clear_interrupt(void)
+{
+ TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
}
void us_ticker_fire_interrupt(void)
{
- cd_major_minor_us = cd_minor_us = 0;
- NVIC_SetPendingIRQ(timer1hires_modinit.irq_n);
+ // NOTE: This event was in the past. Set the interrupt as pending, but don't process it here.
+ // This prevents a recursive loop under heavy load which can lead to a stack overflow.
+ NVIC_SetPendingIRQ(TIMER_MODINIT.irq_n);
+}
+
+const ticker_info_t* us_ticker_get_info()
+{
+ static const ticker_info_t info = {
+ NU_TMRCLK_PER_SEC / NU_TMRCLK_PER_TICK,
+ NU_TMR_MAXCNT_BITSIZE
+ };
+ return &info;
}
static void tmr0_vec(void)
{
- TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer0hires_modinit.modname));
- counter_major ++;
-}
-
-static void tmr1_vec(void)
-{
- TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname));
- cd_major_minor_us = (cd_major_minor_us > cd_minor_us) ? (cd_major_minor_us - cd_minor_us) : 0;
- if (cd_major_minor_us == 0) {
- // NOTE: us_ticker_set_interrupt() may get called in us_ticker_irq_handler();
- us_ticker_irq_handler();
- }
- else {
- us_ticker_arm_cd();
- }
+ TIMER_ClearIntFlag((TIMER_T *) NU_MODBASE(TIMER_MODINIT.modname));
+
+ // NOTE: us_ticker_set_interrupt() may get called in us_ticker_irq_handler();
+ us_ticker_irq_handler();
}
-
-static void us_ticker_arm_cd(void)
-{
- TIMER_T * timer1_base = (TIMER_T *) NU_MODBASE(timer1hires_modinit.modname);
-
- cd_minor_us = cd_major_minor_us;
-
- // Reset 8-bit PSC counter, 24-bit up counter value and CNTEN bit
- timer1_base->CTL |= TIMER_CTL_RSTCNT_Msk;
- // One-shot mode, Clock = 1 MHz
- uint32_t clk_timer1 = TIMER_GetModuleClock((TIMER_T *) NU_MODBASE(timer1hires_modinit.modname));
- uint32_t prescale_timer1 = clk_timer1 / TMR1HIRES_CLK_PER_SEC - 1;
- MBED_ASSERT((prescale_timer1 != (uint32_t) -1) && prescale_timer1 <= 127);
- MBED_ASSERT((clk_timer1 % TMR1HIRES_CLK_PER_SEC) == 0);
- timer1_base->CTL &= ~(TIMER_CTL_OPMODE_Msk | TIMER_CTL_PSC_Msk | TIMER_CTL_CNTDATEN_Msk);
- timer1_base->CTL |= TIMER_ONESHOT_MODE | prescale_timer1 | TIMER_CTL_CNTDATEN_Msk;
-
- uint32_t cmp_timer1 = cd_minor_us / US_PER_TMR1HIRES_CLK;
- cmp_timer1 = NU_CLAMP(cmp_timer1, TMR_CMP_MIN, TMR_CMP_MAX);
- timer1_base->CMP = cmp_timer1;
-
- TIMER_EnableInt(timer1_base);
- TIMER_Start(timer1_base);
-}
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/us_ticker.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_IMX/us_ticker.c Tue Mar 20 16:56:18 2018 +0000
@@ -87,10 +87,14 @@
void us_ticker_set_interrupt(timestamp_t timestamp)
{
- uint32_t delta = timestamp - us_ticker_read();
+ uint32_t now_us, delta_us;
+
+ now_us = us_ticker_read();
+ delta_us = timestamp >= now_us ? timestamp - now_us : (uint32_t)((uint64_t)timestamp + 0xFFFFFFFF - now_us);
+
PIT_StopTimer(PIT, kPIT_Chnl_3);
PIT_StopTimer(PIT, kPIT_Chnl_2);
- PIT_SetTimerPeriod(PIT, kPIT_Chnl_3, (uint32_t)delta);
+ PIT_SetTimerPeriod(PIT, kPIT_Chnl_3, (uint32_t)delta_us);
PIT_EnableInterrupts(PIT, kPIT_Chnl_3, kPIT_TimerInterruptEnable);
PIT_StartTimer(PIT, kPIT_Chnl_3);
PIT_StartTimer(PIT, kPIT_Chnl_2);
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/TARGET_LPCXpresso/mbed_overrides.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC54114/TARGET_LPCXpresso/mbed_overrides.c Tue Mar 20 16:56:18 2018 +0000
@@ -41,7 +41,6 @@
POWER_DisablePD(kPDRUNCFG_PD_TEMPS); /* Power on the temperature sensor. */
/* Enable the clock. */
- CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);
CLOCK_EnableClock(kCLOCK_Adc0);
}
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/clock_config.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/clock_config.c Tue Mar 20 16:56:18 2018 +0000
@@ -1,9 +1,12 @@
/*
+ * The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
+ * All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -45,11 +49,11 @@
/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
!!ClocksProfile
product: Clocks v1.0
-processor: LPC54618J512
-package_id: LPC54618J512ET180
+processor: LPC54628J512
+package_id: LPC54628J512ET180
mcu_data: ksdk2_0
processor_version: 0.0.0
-board: LPCXpresso54618
+board: LPCXpresso54628
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
#include "fsl_power.h"
@@ -244,5 +248,65 @@
CLOCK_AttachClk(kSYS_PLL_to_MAIN_CLK); /*!< Switch System clock to SYS PLL 180MHz */
/* Set SystemCoreClock variable. */
- SystemCoreClock = BOARD_BootClockPLL180M_CORE_CLOCK;
+ SystemCoreClock = BOARD_BOOTCLOCKPLL180M_CORE_CLOCK;
}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL220M *********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockPLL220M
+called_from_default_init: true
+outputs:
+- {id: FRO12M_clock.outFreq, value: 12 MHz}
+- {id: FROHF_clock.outFreq, value: 48 MHz}
+- {id: MAIN_clock.outFreq, value: 220 MHz}
+- {id: SYSPLL_clock.outFreq, value: 220 MHz}
+- {id: System_clock.outFreq, value: 220 MHz}
+settings:
+- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL_BYPASS}
+- {id: SYSCON.M_MULT.scale, value: '110', locked: true}
+- {id: SYSCON.N_DIV.scale, value: '3', locked: true}
+- {id: SYSCON.PDEC.scale, value: '2', locked: true}
+- {id: SYSCON_PDRUNCFG0_PDEN_SYS_PLL_CFG, value: Power_up}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockPLL220M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockPLL220M configuration
+ ******************************************************************************/
+void BOARD_BootClockPLL220M(void)
+{
+ /*!< Set up the clock sources */
+ /*!< Set up FRO */
+ POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */
+ CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally
+ being below the voltage for current speed */
+ POWER_SetVoltageForFreq(220000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+ CLOCK_SetFLASHAccessCyclesForFreq(220000000U); /*!< Set FLASH wait states for core */
+
+ /*!< Set up SYS PLL */
+ const pll_setup_t pllSetup = {
+ .pllctrl = SYSCON_SYSPLLCTRL_SELI(34U) | SYSCON_SYSPLLCTRL_SELP(31U) | SYSCON_SYSPLLCTRL_SELR(0U),
+ .pllmdec = (SYSCON_SYSPLLMDEC_MDEC(13243U)),
+ .pllndec = (SYSCON_SYSPLLNDEC_NDEC(1U)),
+ .pllpdec = (SYSCON_SYSPLLPDEC_PDEC(98U)),
+ .pllRate = 220000000U,
+ .flags = PLL_SETUPFLAG_WAITLOCK | PLL_SETUPFLAG_POWERUP
+ };
+ CLOCK_AttachClk(kFRO12M_to_SYS_PLL); /*!< Set sys pll clock source*/
+ CLOCK_SetPLLFreq(&pllSetup); /*!< Configure PLL to the desired value */
+
+ /*!< Set up dividers */
+ CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */
+
+ /*!< Set up clock selectors - Attach clocks to the peripheries */
+ CLOCK_AttachClk(kSYS_PLL_to_MAIN_CLK); /*!< Switch MAIN_CLK to SYS_PLL */
+ SYSCON->MAINCLKSELA = ((SYSCON->MAINCLKSELA & ~SYSCON_MAINCLKSELA_SEL_MASK) | SYSCON_MAINCLKSELA_SEL(0U)); /*!< Switch MAINCLKSELA to FRO12M even it is not used for MAINCLKSELB */
+ /* Set SystemCoreClock variable. */
+ SystemCoreClock = BOARD_BOOTCLOCKPLL220M_CORE_CLOCK;
+}
+
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/clock_config.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/clock_config.h Tue Mar 20 16:56:18 2018 +0000
@@ -1,9 +1,12 @@
/*
+ * The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
+ * All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -122,7 +126,7 @@
/*******************************************************************************
* Definitions for BOARD_BootClockPLL180M configuration
******************************************************************************/
-#define BOARD_BootClockPLL180M_CORE_CLOCK 180000000U /*!< Core clock frequency:180000000Hz */
+#define BOARD_BOOTCLOCKPLL180M_CORE_CLOCK 180000000U /*!< Core clock frequency:180000000Hz */
/*******************************************************************************
* API for BOARD_BootClockPLL180M configuration
@@ -140,5 +144,30 @@
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL220M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL220M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKPLL220M_CORE_CLOCK 220000000U /*!< Core clock frequency:220000000Hz */
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL220M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL220M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
#endif /* _CLOCK_CONFIG_H_ */
-
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/mbed_overrides.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_FF_LPC546XX/mbed_overrides.c Tue Mar 20 16:56:18 2018 +0000
@@ -40,7 +40,12 @@
// called before main
void mbed_sdk_init()
{
- BOARD_BootClockFROHF48M();
+ if (SYSCON->DEVICE_ID0 == 0xFFF54628) {
+ /* LPC54628 runs at a higher core speed */
+ BOARD_BootClockPLL220M();
+ } else {
+ BOARD_BootClockFROHF48M();
+ }
}
// Change the NMI pin to an input. This allows NMI pin to
@@ -68,8 +73,6 @@
POWER_DisablePD(kPDRUNCFG_PD_VREFP); /* Power on the reference voltage source. */
POWER_DisablePD(kPDRUNCFG_PD_TS); /* Power on the temperature sensor. */
- /* Enable the clock. */
- CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);
/* CLOCK_AttachClk(kMAIN_CLK_to_ADC_CLK); */
/* Sync clock source is not used. Using sync clock source and would be divided by 2.
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/clock_config.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/clock_config.c Tue Mar 20 16:56:18 2018 +0000
@@ -1,9 +1,12 @@
/*
+ * The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
+ * All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -45,11 +49,11 @@
/* TEXT BELOW IS USED AS SETTING FOR THE CLOCKS TOOL *****************************
!!ClocksProfile
product: Clocks v1.0
-processor: LPC54618J512
-package_id: LPC54618J512ET180
+processor: LPC54628J512
+package_id: LPC54628J512ET180
mcu_data: ksdk2_0
processor_version: 0.0.0
-board: LPCXpresso54618
+board: LPCXpresso54628
* BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR THE CLOCKS TOOL **/
#include "fsl_power.h"
@@ -244,5 +248,65 @@
CLOCK_AttachClk(kSYS_PLL_to_MAIN_CLK); /*!< Switch System clock to SYS PLL 180MHz */
/* Set SystemCoreClock variable. */
- SystemCoreClock = BOARD_BootClockPLL180M_CORE_CLOCK;
+ SystemCoreClock = BOARD_BOOTCLOCKPLL180M_CORE_CLOCK;
}
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL220M *********************
+ ******************************************************************************/
+/* TEXT BELOW IS USED AS SETTING FOR TOOLS *************************************
+!!Configuration
+name: BOARD_BootClockPLL220M
+called_from_default_init: true
+outputs:
+- {id: FRO12M_clock.outFreq, value: 12 MHz}
+- {id: FROHF_clock.outFreq, value: 48 MHz}
+- {id: MAIN_clock.outFreq, value: 220 MHz}
+- {id: SYSPLL_clock.outFreq, value: 220 MHz}
+- {id: System_clock.outFreq, value: 220 MHz}
+settings:
+- {id: SYSCON.MAINCLKSELB.sel, value: SYSCON.PLL_BYPASS}
+- {id: SYSCON.M_MULT.scale, value: '110', locked: true}
+- {id: SYSCON.N_DIV.scale, value: '3', locked: true}
+- {id: SYSCON.PDEC.scale, value: '2', locked: true}
+- {id: SYSCON_PDRUNCFG0_PDEN_SYS_PLL_CFG, value: Power_up}
+ * BE CAREFUL MODIFYING THIS COMMENT - IT IS YAML SETTINGS FOR TOOLS **********/
+
+/*******************************************************************************
+ * Variables for BOARD_BootClockPLL220M configuration
+ ******************************************************************************/
+/*******************************************************************************
+ * Code for BOARD_BootClockPLL220M configuration
+ ******************************************************************************/
+void BOARD_BootClockPLL220M(void)
+{
+ /*!< Set up the clock sources */
+ /*!< Set up FRO */
+ POWER_DisablePD(kPDRUNCFG_PD_FRO_EN); /*!< Ensure FRO is on */
+ CLOCK_AttachClk(kFRO12M_to_MAIN_CLK); /*!< Switch to FRO 12MHz first to ensure we can change voltage without accidentally
+ being below the voltage for current speed */
+ POWER_SetVoltageForFreq(220000000U); /*!< Set voltage for the one of the fastest clock outputs: System clock output */
+ CLOCK_SetFLASHAccessCyclesForFreq(220000000U); /*!< Set FLASH wait states for core */
+
+ /*!< Set up SYS PLL */
+ const pll_setup_t pllSetup = {
+ .pllctrl = SYSCON_SYSPLLCTRL_SELI(34U) | SYSCON_SYSPLLCTRL_SELP(31U) | SYSCON_SYSPLLCTRL_SELR(0U),
+ .pllmdec = (SYSCON_SYSPLLMDEC_MDEC(13243U)),
+ .pllndec = (SYSCON_SYSPLLNDEC_NDEC(1U)),
+ .pllpdec = (SYSCON_SYSPLLPDEC_PDEC(98U)),
+ .pllRate = 220000000U,
+ .flags = PLL_SETUPFLAG_WAITLOCK | PLL_SETUPFLAG_POWERUP
+ };
+ CLOCK_AttachClk(kFRO12M_to_SYS_PLL); /*!< Set sys pll clock source*/
+ CLOCK_SetPLLFreq(&pllSetup); /*!< Configure PLL to the desired value */
+
+ /*!< Set up dividers */
+ CLOCK_SetClkDiv(kCLOCK_DivAhbClk, 1U, false); /*!< Reset divider counter and set divider to value 1 */
+
+ /*!< Set up clock selectors - Attach clocks to the peripheries */
+ CLOCK_AttachClk(kSYS_PLL_to_MAIN_CLK); /*!< Switch MAIN_CLK to SYS_PLL */
+ SYSCON->MAINCLKSELA = ((SYSCON->MAINCLKSELA & ~SYSCON_MAINCLKSELA_SEL_MASK) | SYSCON_MAINCLKSELA_SEL(0U)); /*!< Switch MAINCLKSELA to FRO12M even it is not used for MAINCLKSELB */
+ /* Set SystemCoreClock variable. */
+ SystemCoreClock = BOARD_BOOTCLOCKPLL220M_CORE_CLOCK;
+}
+
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/clock_config.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/clock_config.h Tue Mar 20 16:56:18 2018 +0000
@@ -1,9 +1,12 @@
/*
+ * The Clear BSD License
* Copyright (c) 2015, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
+ * All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -122,7 +126,7 @@
/*******************************************************************************
* Definitions for BOARD_BootClockPLL180M configuration
******************************************************************************/
-#define BOARD_BootClockPLL180M_CORE_CLOCK 180000000U /*!< Core clock frequency:180000000Hz */
+#define BOARD_BOOTCLOCKPLL180M_CORE_CLOCK 180000000U /*!< Core clock frequency:180000000Hz */
/*******************************************************************************
* API for BOARD_BootClockPLL180M configuration
@@ -140,5 +144,30 @@
#if defined(__cplusplus)
}
#endif /* __cplusplus*/
+
+/*******************************************************************************
+ ******************** Configuration BOARD_BootClockPLL220M *********************
+ ******************************************************************************/
+/*******************************************************************************
+ * Definitions for BOARD_BootClockPLL220M configuration
+ ******************************************************************************/
+#define BOARD_BOOTCLOCKPLL220M_CORE_CLOCK 220000000U /*!< Core clock frequency:220000000Hz */
+
+/*******************************************************************************
+ * API for BOARD_BootClockPLL220M configuration
+ ******************************************************************************/
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus*/
+
+/*!
+ * @brief This function executes configuration of clocks.
+ *
+ */
+void BOARD_BootClockPLL220M(void);
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus*/
+
#endif /* _CLOCK_CONFIG_H_ */
-
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/mbed_overrides.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/TARGET_LPCXpresso/mbed_overrides.c Tue Mar 20 16:56:18 2018 +0000
@@ -56,7 +56,12 @@
// called before main
void mbed_sdk_init()
{
- BOARD_BootClockFROHF48M();
+ if (SYSCON->DEVICE_ID0 == 0xFFF54628) {
+ /* LPC54628 runs at a higher core speed */
+ BOARD_BootClockPLL220M();
+ } else {
+ BOARD_BootClockFROHF48M();
+ }
}
// Change the NMI pin to an input. This allows NMI pin to
@@ -116,8 +121,6 @@
POWER_DisablePD(kPDRUNCFG_PD_VREFP); /* Power on the reference voltage source. */
POWER_DisablePD(kPDRUNCFG_PD_TS); /* Power on the temperature sensor. */
- /* Enable the clock. */
- CLOCK_AttachClk(kFRO12M_to_MAIN_CLK);
/* CLOCK_AttachClk(kMAIN_CLK_to_ADC_CLK); */
/* Sync clock source is not used. Using sync clock source and would be divided by 2.
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/LPC54618.h Fri Feb 16 16:09:33 2018 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,12410 +0,0 @@
-/*
-** ###################################################################
-** Processors: LPC54618J512BD208
-** LPC54618J512ET180
-**
-** Compilers: Keil ARM C/C++ Compiler
-** GNU C Compiler
-** IAR ANSI C/C++ Compiler for ARM
-** MCUXpresso Compiler
-**
-** Reference manual: LPC54S60x/LPC5460x User manual Rev.0.9 7 Nov 2016
-** Version: rev. 1.1, 2016-11-25
-** Build: b170214
-**
-** Abstract:
-** CMSIS Peripheral Access Layer for LPC54618
-**
-** Copyright 1997-2016 Freescale Semiconductor, Inc.
-** Copyright 2016-2017 NXP
-** Redistribution and use in source and binary forms, with or without modification,
-** are permitted provided that the following conditions are met:
-**
-** o Redistributions of source code must retain the above copyright notice, this list
-** of conditions and the following disclaimer.
-**
-** o Redistributions in binary form must reproduce the above copyright notice, this
-** list of conditions and the following disclaimer in the documentation and/or
-** other materials provided with the distribution.
-**
-** o Neither the name of the copyright holder nor the names of its
-** contributors may be used to endorse or promote products derived from this
-** software without specific prior written permission.
-**
-** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-**
-** http: www.nxp.com
-** mail: support@nxp.com
-**
-** Revisions:
-** - rev. 1.0 (2016-08-12)
-** Initial version.
-** - rev. 1.1 (2016-11-25)
-** Update CANFD and Classic CAN register.
-** Add MAC TIMERSTAMP registers.
-**
-** ###################################################################
-*/
-
-/*!
- * @file LPC54618.h
- * @version 1.1
- * @date 2016-11-25
- * @brief CMSIS Peripheral Access Layer for LPC54618
- *
- * CMSIS Peripheral Access Layer for LPC54618
- */
-
-#ifndef _LPC54618_H_
-#define _LPC54618_H_ /**< Symbol preventing repeated inclusion */
-
-/** Memory map major version (memory maps with equal major version number are
- * compatible) */
-#define MCU_MEM_MAP_VERSION 0x0100U
-/** Memory map minor version */
-#define MCU_MEM_MAP_VERSION_MINOR 0x0001U
-
-
-/* ----------------------------------------------------------------------------
- -- Interrupt vector numbers
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
- * @{
- */
-
-/** Interrupt Number Definitions */
-#define NUMBER_OF_INT_VECTORS 73 /**< Number of interrupts in the Vector table */
-
-typedef enum IRQn {
- /* Auxiliary constants */
- NotAvail_IRQn = -128, /**< Not available device specific interrupt */
-
- /* Core interrupts */
- NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
- HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
- MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
- BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
- UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
- SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
- DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
- PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
- SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
-
- /* Device specific interrupts */
- WDT_BOD_IRQn = 0, /**< Windowed watchdog timer, Brownout detect */
- DMA0_IRQn = 1, /**< DMA controller */
- GINT0_IRQn = 2, /**< GPIO group 0 */
- GINT1_IRQn = 3, /**< GPIO group 1 */
- PIN_INT0_IRQn = 4, /**< Pin interrupt 0 or pattern match engine slice 0 */
- PIN_INT1_IRQn = 5, /**< Pin interrupt 1or pattern match engine slice 1 */
- PIN_INT2_IRQn = 6, /**< Pin interrupt 2 or pattern match engine slice 2 */
- PIN_INT3_IRQn = 7, /**< Pin interrupt 3 or pattern match engine slice 3 */
- UTICK0_IRQn = 8, /**< Micro-tick Timer */
- MRT0_IRQn = 9, /**< Multi-rate timer */
- CTIMER0_IRQn = 10, /**< Standard counter/timer CTIMER0 */
- CTIMER1_IRQn = 11, /**< Standard counter/timer CTIMER1 */
- SCT0_IRQn = 12, /**< SCTimer/PWM */
- CTIMER3_IRQn = 13, /**< Standard counter/timer CTIMER3 */
- FLEXCOMM0_IRQn = 14, /**< Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) */
- FLEXCOMM1_IRQn = 15, /**< Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) */
- FLEXCOMM2_IRQn = 16, /**< Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) */
- FLEXCOMM3_IRQn = 17, /**< Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) */
- FLEXCOMM4_IRQn = 18, /**< Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) */
- FLEXCOMM5_IRQn = 19, /**< Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM) */
- FLEXCOMM6_IRQn = 20, /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM) */
- FLEXCOMM7_IRQn = 21, /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM) */
- ADC0_SEQA_IRQn = 22, /**< ADC0 sequence A completion. */
- ADC0_SEQB_IRQn = 23, /**< ADC0 sequence B completion. */
- ADC0_THCMP_IRQn = 24, /**< ADC0 threshold compare and error. */
- DMIC0_IRQn = 25, /**< Digital microphone and DMIC subsystem */
- HWVAD0_IRQn = 26, /**< Hardware Voice Activity Detector */
- USB0_NEEDCLK_IRQn = 27, /**< USB Activity Wake-up Interrupt */
- USB0_IRQn = 28, /**< USB device */
- RTC_IRQn = 29, /**< RTC alarm and wake-up interrupts */
- Reserved46_IRQn = 30, /**< Reserved interrupt */
- Reserved47_IRQn = 31, /**< Reserved interrupt */
- PIN_INT4_IRQn = 32, /**< Pin interrupt 4 or pattern match engine slice 4 int */
- PIN_INT5_IRQn = 33, /**< Pin interrupt 5 or pattern match engine slice 5 int */
- PIN_INT6_IRQn = 34, /**< Pin interrupt 6 or pattern match engine slice 6 int */
- PIN_INT7_IRQn = 35, /**< Pin interrupt 7 or pattern match engine slice 7 int */
- CTIMER2_IRQn = 36, /**< Standard counter/timer CTIMER2 */
- CTIMER4_IRQn = 37, /**< Standard counter/timer CTIMER4 */
- RIT_IRQn = 38, /**< Repetitive Interrupt Timer */
- SPIFI0_IRQn = 39, /**< SPI flash interface */
- FLEXCOMM8_IRQn = 40, /**< Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM) */
- FLEXCOMM9_IRQn = 41, /**< Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM) */
- SDIO_IRQn = 42, /**< SD/MMC */
- CAN0_IRQ0_IRQn = 43, /**< CAN0 interrupt0 */
- CAN0_IRQ1_IRQn = 44, /**< CAN0 interrupt1 */
- CAN1_IRQ0_IRQn = 45, /**< CAN1 interrupt0 */
- CAN1_IRQ1_IRQn = 46, /**< CAN1 interrupt1 */
- USB1_IRQn = 47, /**< USB1 interrupt */
- USB1_NEEDCLK_IRQn = 48, /**< USB1 activity */
- ETHERNET_IRQn = 49, /**< Ethernet */
- ETHERNET_PMT_IRQn = 50, /**< Ethernet power management interrupt */
- ETHERNET_MACLP_IRQn = 51, /**< Ethernet MAC interrupt */
- EEPROM_IRQn = 52, /**< EEPROM interrupt */
- LCD_IRQn = 53, /**< LCD interrupt */
- SHA_IRQn = 54, /**< SHA interrupt */
- SMARTCARD0_IRQn = 55, /**< Smart card 0 interrupt */
- SMARTCARD1_IRQn = 56 /**< Smart card 1 interrupt */
-} IRQn_Type;
-
-/*!
- * @}
- */ /* end of group Interrupt_vector_numbers */
-
-
-/* ----------------------------------------------------------------------------
- -- Cortex M4 Core Configuration
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
- * @{
- */
-
-#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */
-#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */
-#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
-#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
-
-#include "core_cm4.h" /* Core Peripheral Access Layer */
-#include "system_LPC54618.h" /* Device specific configuration file */
-
-/*!
- * @}
- */ /* end of group Cortex_Core_Configuration */
-
-
-/* ----------------------------------------------------------------------------
- -- Mapping Information
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup Mapping_Information Mapping Information
- * @{
- */
-
-/** Mapping Information */
-
-/*!
- * @}
- */ /* end of group Mapping_Information */
-
-
-/* ----------------------------------------------------------------------------
- -- Device Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
- * @{
- */
-
-
-/*
-** Start of section using anonymous unions
-*/
-
-#if defined(__ARMCC_VERSION)
- #pragma push
- #pragma anon_unions
-#elif defined(__GNUC__)
- /* anonymous unions are enabled by default */
-#elif defined(__IAR_SYSTEMS_ICC__)
- #pragma language=extended
-#else
- #error Not supported compiler type
-#endif
-
-/* ----------------------------------------------------------------------------
- -- ADC Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
- * @{
- */
-
-/** ADC - Register Layout Typedef */
-typedef struct {
- __IO uint32_t CTRL; /**< ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls., offset: 0x0 */
- __IO uint32_t INSEL; /**< Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0., offset: 0x4 */
- __IO uint32_t SEQ_CTRL[2]; /**< ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n., array offset: 0x8, array step: 0x4 */
- __I uint32_t SEQ_GDAT[2]; /**< ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n., array offset: 0x10, array step: 0x4 */
- uint8_t RESERVED_0[8];
- __I uint32_t DAT[12]; /**< ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0., array offset: 0x20, array step: 0x4 */
- __IO uint32_t THR0_LOW; /**< ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x50 */
- __IO uint32_t THR1_LOW; /**< ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x54 */
- __IO uint32_t THR0_HIGH; /**< ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x58 */
- __IO uint32_t THR1_HIGH; /**< ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x5C */
- __IO uint32_t CHAN_THRSEL; /**< ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel, offset: 0x60 */
- __IO uint32_t INTEN; /**< ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated., offset: 0x64 */
- __IO uint32_t FLAGS; /**< ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers)., offset: 0x68 */
- __IO uint32_t STARTUP; /**< ADC Startup register., offset: 0x6C */
- __IO uint32_t CALIB; /**< ADC Calibration register., offset: 0x70 */
-} ADC_Type;
-
-/* ----------------------------------------------------------------------------
- -- ADC Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup ADC_Register_Masks ADC Register Masks
- * @{
- */
-
-/*! @name CTRL - ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls. */
-#define ADC_CTRL_CLKDIV_MASK (0xFFU)
-#define ADC_CTRL_CLKDIV_SHIFT (0U)
-#define ADC_CTRL_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CLKDIV_SHIFT)) & ADC_CTRL_CLKDIV_MASK)
-#define ADC_CTRL_ASYNMODE_MASK (0x100U)
-#define ADC_CTRL_ASYNMODE_SHIFT (8U)
-#define ADC_CTRL_ASYNMODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ASYNMODE_SHIFT)) & ADC_CTRL_ASYNMODE_MASK)
-#define ADC_CTRL_RESOL_MASK (0x600U)
-#define ADC_CTRL_RESOL_SHIFT (9U)
-#define ADC_CTRL_RESOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RESOL_SHIFT)) & ADC_CTRL_RESOL_MASK)
-#define ADC_CTRL_BYPASSCAL_MASK (0x800U)
-#define ADC_CTRL_BYPASSCAL_SHIFT (11U)
-#define ADC_CTRL_BYPASSCAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_BYPASSCAL_SHIFT)) & ADC_CTRL_BYPASSCAL_MASK)
-#define ADC_CTRL_TSAMP_MASK (0x7000U)
-#define ADC_CTRL_TSAMP_SHIFT (12U)
-#define ADC_CTRL_TSAMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_TSAMP_SHIFT)) & ADC_CTRL_TSAMP_MASK)
-
-/*! @name INSEL - Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0. */
-#define ADC_INSEL_SEL_MASK (0x3U)
-#define ADC_INSEL_SEL_SHIFT (0U)
-#define ADC_INSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_INSEL_SEL_SHIFT)) & ADC_INSEL_SEL_MASK)
-
-/*! @name SEQ_CTRL - ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n. */
-#define ADC_SEQ_CTRL_CHANNELS_MASK (0xFFFU)
-#define ADC_SEQ_CTRL_CHANNELS_SHIFT (0U)
-#define ADC_SEQ_CTRL_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_CHANNELS_SHIFT)) & ADC_SEQ_CTRL_CHANNELS_MASK)
-#define ADC_SEQ_CTRL_TRIGGER_MASK (0x3F000U)
-#define ADC_SEQ_CTRL_TRIGGER_SHIFT (12U)
-#define ADC_SEQ_CTRL_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGGER_SHIFT)) & ADC_SEQ_CTRL_TRIGGER_MASK)
-#define ADC_SEQ_CTRL_TRIGPOL_MASK (0x40000U)
-#define ADC_SEQ_CTRL_TRIGPOL_SHIFT (18U)
-#define ADC_SEQ_CTRL_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGPOL_SHIFT)) & ADC_SEQ_CTRL_TRIGPOL_MASK)
-#define ADC_SEQ_CTRL_SYNCBYPASS_MASK (0x80000U)
-#define ADC_SEQ_CTRL_SYNCBYPASS_SHIFT (19U)
-#define ADC_SEQ_CTRL_SYNCBYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SYNCBYPASS_SHIFT)) & ADC_SEQ_CTRL_SYNCBYPASS_MASK)
-#define ADC_SEQ_CTRL_START_MASK (0x4000000U)
-#define ADC_SEQ_CTRL_START_SHIFT (26U)
-#define ADC_SEQ_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_START_SHIFT)) & ADC_SEQ_CTRL_START_MASK)
-#define ADC_SEQ_CTRL_BURST_MASK (0x8000000U)
-#define ADC_SEQ_CTRL_BURST_SHIFT (27U)
-#define ADC_SEQ_CTRL_BURST(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_BURST_SHIFT)) & ADC_SEQ_CTRL_BURST_MASK)
-#define ADC_SEQ_CTRL_SINGLESTEP_MASK (0x10000000U)
-#define ADC_SEQ_CTRL_SINGLESTEP_SHIFT (28U)
-#define ADC_SEQ_CTRL_SINGLESTEP(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SINGLESTEP_SHIFT)) & ADC_SEQ_CTRL_SINGLESTEP_MASK)
-#define ADC_SEQ_CTRL_LOWPRIO_MASK (0x20000000U)
-#define ADC_SEQ_CTRL_LOWPRIO_SHIFT (29U)
-#define ADC_SEQ_CTRL_LOWPRIO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_LOWPRIO_SHIFT)) & ADC_SEQ_CTRL_LOWPRIO_MASK)
-#define ADC_SEQ_CTRL_MODE_MASK (0x40000000U)
-#define ADC_SEQ_CTRL_MODE_SHIFT (30U)
-#define ADC_SEQ_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_MODE_SHIFT)) & ADC_SEQ_CTRL_MODE_MASK)
-#define ADC_SEQ_CTRL_SEQ_ENA_MASK (0x80000000U)
-#define ADC_SEQ_CTRL_SEQ_ENA_SHIFT (31U)
-#define ADC_SEQ_CTRL_SEQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SEQ_ENA_SHIFT)) & ADC_SEQ_CTRL_SEQ_ENA_MASK)
-
-/* The count of ADC_SEQ_CTRL */
-#define ADC_SEQ_CTRL_COUNT (2U)
-
-/*! @name SEQ_GDAT - ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n. */
-#define ADC_SEQ_GDAT_RESULT_MASK (0xFFF0U)
-#define ADC_SEQ_GDAT_RESULT_SHIFT (4U)
-#define ADC_SEQ_GDAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_RESULT_SHIFT)) & ADC_SEQ_GDAT_RESULT_MASK)
-#define ADC_SEQ_GDAT_THCMPRANGE_MASK (0x30000U)
-#define ADC_SEQ_GDAT_THCMPRANGE_SHIFT (16U)
-#define ADC_SEQ_GDAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPRANGE_SHIFT)) & ADC_SEQ_GDAT_THCMPRANGE_MASK)
-#define ADC_SEQ_GDAT_THCMPCROSS_MASK (0xC0000U)
-#define ADC_SEQ_GDAT_THCMPCROSS_SHIFT (18U)
-#define ADC_SEQ_GDAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPCROSS_SHIFT)) & ADC_SEQ_GDAT_THCMPCROSS_MASK)
-#define ADC_SEQ_GDAT_CHN_MASK (0x3C000000U)
-#define ADC_SEQ_GDAT_CHN_SHIFT (26U)
-#define ADC_SEQ_GDAT_CHN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_CHN_SHIFT)) & ADC_SEQ_GDAT_CHN_MASK)
-#define ADC_SEQ_GDAT_OVERRUN_MASK (0x40000000U)
-#define ADC_SEQ_GDAT_OVERRUN_SHIFT (30U)
-#define ADC_SEQ_GDAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_OVERRUN_SHIFT)) & ADC_SEQ_GDAT_OVERRUN_MASK)
-#define ADC_SEQ_GDAT_DATAVALID_MASK (0x80000000U)
-#define ADC_SEQ_GDAT_DATAVALID_SHIFT (31U)
-#define ADC_SEQ_GDAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_DATAVALID_SHIFT)) & ADC_SEQ_GDAT_DATAVALID_MASK)
-
-/* The count of ADC_SEQ_GDAT */
-#define ADC_SEQ_GDAT_COUNT (2U)
-
-/*! @name DAT - ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0. */
-#define ADC_DAT_RESULT_MASK (0xFFF0U)
-#define ADC_DAT_RESULT_SHIFT (4U)
-#define ADC_DAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_RESULT_SHIFT)) & ADC_DAT_RESULT_MASK)
-#define ADC_DAT_THCMPRANGE_MASK (0x30000U)
-#define ADC_DAT_THCMPRANGE_SHIFT (16U)
-#define ADC_DAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPRANGE_SHIFT)) & ADC_DAT_THCMPRANGE_MASK)
-#define ADC_DAT_THCMPCROSS_MASK (0xC0000U)
-#define ADC_DAT_THCMPCROSS_SHIFT (18U)
-#define ADC_DAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPCROSS_SHIFT)) & ADC_DAT_THCMPCROSS_MASK)
-#define ADC_DAT_CHANNEL_MASK (0x3C000000U)
-#define ADC_DAT_CHANNEL_SHIFT (26U)
-#define ADC_DAT_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_CHANNEL_SHIFT)) & ADC_DAT_CHANNEL_MASK)
-#define ADC_DAT_OVERRUN_MASK (0x40000000U)
-#define ADC_DAT_OVERRUN_SHIFT (30U)
-#define ADC_DAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_OVERRUN_SHIFT)) & ADC_DAT_OVERRUN_MASK)
-#define ADC_DAT_DATAVALID_MASK (0x80000000U)
-#define ADC_DAT_DATAVALID_SHIFT (31U)
-#define ADC_DAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_DATAVALID_SHIFT)) & ADC_DAT_DATAVALID_MASK)
-
-/* The count of ADC_DAT */
-#define ADC_DAT_COUNT (12U)
-
-/*! @name THR0_LOW - ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */
-#define ADC_THR0_LOW_THRLOW_MASK (0xFFF0U)
-#define ADC_THR0_LOW_THRLOW_SHIFT (4U)
-#define ADC_THR0_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_LOW_THRLOW_SHIFT)) & ADC_THR0_LOW_THRLOW_MASK)
-
-/*! @name THR1_LOW - ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */
-#define ADC_THR1_LOW_THRLOW_MASK (0xFFF0U)
-#define ADC_THR1_LOW_THRLOW_SHIFT (4U)
-#define ADC_THR1_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_LOW_THRLOW_SHIFT)) & ADC_THR1_LOW_THRLOW_MASK)
-
-/*! @name THR0_HIGH - ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */
-#define ADC_THR0_HIGH_THRHIGH_MASK (0xFFF0U)
-#define ADC_THR0_HIGH_THRHIGH_SHIFT (4U)
-#define ADC_THR0_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_HIGH_THRHIGH_SHIFT)) & ADC_THR0_HIGH_THRHIGH_MASK)
-
-/*! @name THR1_HIGH - ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */
-#define ADC_THR1_HIGH_THRHIGH_MASK (0xFFF0U)
-#define ADC_THR1_HIGH_THRHIGH_SHIFT (4U)
-#define ADC_THR1_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_HIGH_THRHIGH_SHIFT)) & ADC_THR1_HIGH_THRHIGH_MASK)
-
-/*! @name CHAN_THRSEL - ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel */
-#define ADC_CHAN_THRSEL_CH0_THRSEL_MASK (0x1U)
-#define ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT (0U)
-#define ADC_CHAN_THRSEL_CH0_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH0_THRSEL_MASK)
-#define ADC_CHAN_THRSEL_CH1_THRSEL_MASK (0x2U)
-#define ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT (1U)
-#define ADC_CHAN_THRSEL_CH1_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH1_THRSEL_MASK)
-#define ADC_CHAN_THRSEL_CH2_THRSEL_MASK (0x4U)
-#define ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT (2U)
-#define ADC_CHAN_THRSEL_CH2_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH2_THRSEL_MASK)
-#define ADC_CHAN_THRSEL_CH3_THRSEL_MASK (0x8U)
-#define ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT (3U)
-#define ADC_CHAN_THRSEL_CH3_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH3_THRSEL_MASK)
-#define ADC_CHAN_THRSEL_CH4_THRSEL_MASK (0x10U)
-#define ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT (4U)
-#define ADC_CHAN_THRSEL_CH4_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH4_THRSEL_MASK)
-#define ADC_CHAN_THRSEL_CH5_THRSEL_MASK (0x20U)
-#define ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT (5U)
-#define ADC_CHAN_THRSEL_CH5_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH5_THRSEL_MASK)
-#define ADC_CHAN_THRSEL_CH6_THRSEL_MASK (0x40U)
-#define ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT (6U)
-#define ADC_CHAN_THRSEL_CH6_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH6_THRSEL_MASK)
-#define ADC_CHAN_THRSEL_CH7_THRSEL_MASK (0x80U)
-#define ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT (7U)
-#define ADC_CHAN_THRSEL_CH7_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH7_THRSEL_MASK)
-#define ADC_CHAN_THRSEL_CH8_THRSEL_MASK (0x100U)
-#define ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT (8U)
-#define ADC_CHAN_THRSEL_CH8_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH8_THRSEL_MASK)
-#define ADC_CHAN_THRSEL_CH9_THRSEL_MASK (0x200U)
-#define ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT (9U)
-#define ADC_CHAN_THRSEL_CH9_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH9_THRSEL_MASK)
-#define ADC_CHAN_THRSEL_CH10_THRSEL_MASK (0x400U)
-#define ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT (10U)
-#define ADC_CHAN_THRSEL_CH10_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH10_THRSEL_MASK)
-#define ADC_CHAN_THRSEL_CH11_THRSEL_MASK (0x800U)
-#define ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT (11U)
-#define ADC_CHAN_THRSEL_CH11_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH11_THRSEL_MASK)
-
-/*! @name INTEN - ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated. */
-#define ADC_INTEN_SEQA_INTEN_MASK (0x1U)
-#define ADC_INTEN_SEQA_INTEN_SHIFT (0U)
-#define ADC_INTEN_SEQA_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQA_INTEN_SHIFT)) & ADC_INTEN_SEQA_INTEN_MASK)
-#define ADC_INTEN_SEQB_INTEN_MASK (0x2U)
-#define ADC_INTEN_SEQB_INTEN_SHIFT (1U)
-#define ADC_INTEN_SEQB_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQB_INTEN_SHIFT)) & ADC_INTEN_SEQB_INTEN_MASK)
-#define ADC_INTEN_OVR_INTEN_MASK (0x4U)
-#define ADC_INTEN_OVR_INTEN_SHIFT (2U)
-#define ADC_INTEN_OVR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_OVR_INTEN_SHIFT)) & ADC_INTEN_OVR_INTEN_MASK)
-#define ADC_INTEN_ADCMPINTEN0_MASK (0x18U)
-#define ADC_INTEN_ADCMPINTEN0_SHIFT (3U)
-#define ADC_INTEN_ADCMPINTEN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN0_SHIFT)) & ADC_INTEN_ADCMPINTEN0_MASK)
-#define ADC_INTEN_ADCMPINTEN1_MASK (0x60U)
-#define ADC_INTEN_ADCMPINTEN1_SHIFT (5U)
-#define ADC_INTEN_ADCMPINTEN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN1_SHIFT)) & ADC_INTEN_ADCMPINTEN1_MASK)
-#define ADC_INTEN_ADCMPINTEN2_MASK (0x180U)
-#define ADC_INTEN_ADCMPINTEN2_SHIFT (7U)
-#define ADC_INTEN_ADCMPINTEN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN2_SHIFT)) & ADC_INTEN_ADCMPINTEN2_MASK)
-#define ADC_INTEN_ADCMPINTEN3_MASK (0x600U)
-#define ADC_INTEN_ADCMPINTEN3_SHIFT (9U)
-#define ADC_INTEN_ADCMPINTEN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN3_SHIFT)) & ADC_INTEN_ADCMPINTEN3_MASK)
-#define ADC_INTEN_ADCMPINTEN4_MASK (0x1800U)
-#define ADC_INTEN_ADCMPINTEN4_SHIFT (11U)
-#define ADC_INTEN_ADCMPINTEN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN4_SHIFT)) & ADC_INTEN_ADCMPINTEN4_MASK)
-#define ADC_INTEN_ADCMPINTEN5_MASK (0x6000U)
-#define ADC_INTEN_ADCMPINTEN5_SHIFT (13U)
-#define ADC_INTEN_ADCMPINTEN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN5_SHIFT)) & ADC_INTEN_ADCMPINTEN5_MASK)
-#define ADC_INTEN_ADCMPINTEN6_MASK (0x18000U)
-#define ADC_INTEN_ADCMPINTEN6_SHIFT (15U)
-#define ADC_INTEN_ADCMPINTEN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN6_SHIFT)) & ADC_INTEN_ADCMPINTEN6_MASK)
-#define ADC_INTEN_ADCMPINTEN7_MASK (0x60000U)
-#define ADC_INTEN_ADCMPINTEN7_SHIFT (17U)
-#define ADC_INTEN_ADCMPINTEN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN7_SHIFT)) & ADC_INTEN_ADCMPINTEN7_MASK)
-#define ADC_INTEN_ADCMPINTEN8_MASK (0x180000U)
-#define ADC_INTEN_ADCMPINTEN8_SHIFT (19U)
-#define ADC_INTEN_ADCMPINTEN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN8_SHIFT)) & ADC_INTEN_ADCMPINTEN8_MASK)
-#define ADC_INTEN_ADCMPINTEN9_MASK (0x600000U)
-#define ADC_INTEN_ADCMPINTEN9_SHIFT (21U)
-#define ADC_INTEN_ADCMPINTEN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN9_SHIFT)) & ADC_INTEN_ADCMPINTEN9_MASK)
-#define ADC_INTEN_ADCMPINTEN10_MASK (0x1800000U)
-#define ADC_INTEN_ADCMPINTEN10_SHIFT (23U)
-#define ADC_INTEN_ADCMPINTEN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN10_SHIFT)) & ADC_INTEN_ADCMPINTEN10_MASK)
-#define ADC_INTEN_ADCMPINTEN11_MASK (0x6000000U)
-#define ADC_INTEN_ADCMPINTEN11_SHIFT (25U)
-#define ADC_INTEN_ADCMPINTEN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN11_SHIFT)) & ADC_INTEN_ADCMPINTEN11_MASK)
-
-/*! @name FLAGS - ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers). */
-#define ADC_FLAGS_THCMP0_MASK (0x1U)
-#define ADC_FLAGS_THCMP0_SHIFT (0U)
-#define ADC_FLAGS_THCMP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP0_SHIFT)) & ADC_FLAGS_THCMP0_MASK)
-#define ADC_FLAGS_THCMP1_MASK (0x2U)
-#define ADC_FLAGS_THCMP1_SHIFT (1U)
-#define ADC_FLAGS_THCMP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP1_SHIFT)) & ADC_FLAGS_THCMP1_MASK)
-#define ADC_FLAGS_THCMP2_MASK (0x4U)
-#define ADC_FLAGS_THCMP2_SHIFT (2U)
-#define ADC_FLAGS_THCMP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP2_SHIFT)) & ADC_FLAGS_THCMP2_MASK)
-#define ADC_FLAGS_THCMP3_MASK (0x8U)
-#define ADC_FLAGS_THCMP3_SHIFT (3U)
-#define ADC_FLAGS_THCMP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP3_SHIFT)) & ADC_FLAGS_THCMP3_MASK)
-#define ADC_FLAGS_THCMP4_MASK (0x10U)
-#define ADC_FLAGS_THCMP4_SHIFT (4U)
-#define ADC_FLAGS_THCMP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP4_SHIFT)) & ADC_FLAGS_THCMP4_MASK)
-#define ADC_FLAGS_THCMP5_MASK (0x20U)
-#define ADC_FLAGS_THCMP5_SHIFT (5U)
-#define ADC_FLAGS_THCMP5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP5_SHIFT)) & ADC_FLAGS_THCMP5_MASK)
-#define ADC_FLAGS_THCMP6_MASK (0x40U)
-#define ADC_FLAGS_THCMP6_SHIFT (6U)
-#define ADC_FLAGS_THCMP6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP6_SHIFT)) & ADC_FLAGS_THCMP6_MASK)
-#define ADC_FLAGS_THCMP7_MASK (0x80U)
-#define ADC_FLAGS_THCMP7_SHIFT (7U)
-#define ADC_FLAGS_THCMP7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP7_SHIFT)) & ADC_FLAGS_THCMP7_MASK)
-#define ADC_FLAGS_THCMP8_MASK (0x100U)
-#define ADC_FLAGS_THCMP8_SHIFT (8U)
-#define ADC_FLAGS_THCMP8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP8_SHIFT)) & ADC_FLAGS_THCMP8_MASK)
-#define ADC_FLAGS_THCMP9_MASK (0x200U)
-#define ADC_FLAGS_THCMP9_SHIFT (9U)
-#define ADC_FLAGS_THCMP9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP9_SHIFT)) & ADC_FLAGS_THCMP9_MASK)
-#define ADC_FLAGS_THCMP10_MASK (0x400U)
-#define ADC_FLAGS_THCMP10_SHIFT (10U)
-#define ADC_FLAGS_THCMP10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP10_SHIFT)) & ADC_FLAGS_THCMP10_MASK)
-#define ADC_FLAGS_THCMP11_MASK (0x800U)
-#define ADC_FLAGS_THCMP11_SHIFT (11U)
-#define ADC_FLAGS_THCMP11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP11_SHIFT)) & ADC_FLAGS_THCMP11_MASK)
-#define ADC_FLAGS_OVERRUN0_MASK (0x1000U)
-#define ADC_FLAGS_OVERRUN0_SHIFT (12U)
-#define ADC_FLAGS_OVERRUN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN0_SHIFT)) & ADC_FLAGS_OVERRUN0_MASK)
-#define ADC_FLAGS_OVERRUN1_MASK (0x2000U)
-#define ADC_FLAGS_OVERRUN1_SHIFT (13U)
-#define ADC_FLAGS_OVERRUN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN1_SHIFT)) & ADC_FLAGS_OVERRUN1_MASK)
-#define ADC_FLAGS_OVERRUN2_MASK (0x4000U)
-#define ADC_FLAGS_OVERRUN2_SHIFT (14U)
-#define ADC_FLAGS_OVERRUN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN2_SHIFT)) & ADC_FLAGS_OVERRUN2_MASK)
-#define ADC_FLAGS_OVERRUN3_MASK (0x8000U)
-#define ADC_FLAGS_OVERRUN3_SHIFT (15U)
-#define ADC_FLAGS_OVERRUN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN3_SHIFT)) & ADC_FLAGS_OVERRUN3_MASK)
-#define ADC_FLAGS_OVERRUN4_MASK (0x10000U)
-#define ADC_FLAGS_OVERRUN4_SHIFT (16U)
-#define ADC_FLAGS_OVERRUN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN4_SHIFT)) & ADC_FLAGS_OVERRUN4_MASK)
-#define ADC_FLAGS_OVERRUN5_MASK (0x20000U)
-#define ADC_FLAGS_OVERRUN5_SHIFT (17U)
-#define ADC_FLAGS_OVERRUN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN5_SHIFT)) & ADC_FLAGS_OVERRUN5_MASK)
-#define ADC_FLAGS_OVERRUN6_MASK (0x40000U)
-#define ADC_FLAGS_OVERRUN6_SHIFT (18U)
-#define ADC_FLAGS_OVERRUN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN6_SHIFT)) & ADC_FLAGS_OVERRUN6_MASK)
-#define ADC_FLAGS_OVERRUN7_MASK (0x80000U)
-#define ADC_FLAGS_OVERRUN7_SHIFT (19U)
-#define ADC_FLAGS_OVERRUN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN7_SHIFT)) & ADC_FLAGS_OVERRUN7_MASK)
-#define ADC_FLAGS_OVERRUN8_MASK (0x100000U)
-#define ADC_FLAGS_OVERRUN8_SHIFT (20U)
-#define ADC_FLAGS_OVERRUN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN8_SHIFT)) & ADC_FLAGS_OVERRUN8_MASK)
-#define ADC_FLAGS_OVERRUN9_MASK (0x200000U)
-#define ADC_FLAGS_OVERRUN9_SHIFT (21U)
-#define ADC_FLAGS_OVERRUN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN9_SHIFT)) & ADC_FLAGS_OVERRUN9_MASK)
-#define ADC_FLAGS_OVERRUN10_MASK (0x400000U)
-#define ADC_FLAGS_OVERRUN10_SHIFT (22U)
-#define ADC_FLAGS_OVERRUN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN10_SHIFT)) & ADC_FLAGS_OVERRUN10_MASK)
-#define ADC_FLAGS_OVERRUN11_MASK (0x800000U)
-#define ADC_FLAGS_OVERRUN11_SHIFT (23U)
-#define ADC_FLAGS_OVERRUN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN11_SHIFT)) & ADC_FLAGS_OVERRUN11_MASK)
-#define ADC_FLAGS_SEQA_OVR_MASK (0x1000000U)
-#define ADC_FLAGS_SEQA_OVR_SHIFT (24U)
-#define ADC_FLAGS_SEQA_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_OVR_SHIFT)) & ADC_FLAGS_SEQA_OVR_MASK)
-#define ADC_FLAGS_SEQB_OVR_MASK (0x2000000U)
-#define ADC_FLAGS_SEQB_OVR_SHIFT (25U)
-#define ADC_FLAGS_SEQB_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_OVR_SHIFT)) & ADC_FLAGS_SEQB_OVR_MASK)
-#define ADC_FLAGS_SEQA_INT_MASK (0x10000000U)
-#define ADC_FLAGS_SEQA_INT_SHIFT (28U)
-#define ADC_FLAGS_SEQA_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_INT_SHIFT)) & ADC_FLAGS_SEQA_INT_MASK)
-#define ADC_FLAGS_SEQB_INT_MASK (0x20000000U)
-#define ADC_FLAGS_SEQB_INT_SHIFT (29U)
-#define ADC_FLAGS_SEQB_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_INT_SHIFT)) & ADC_FLAGS_SEQB_INT_MASK)
-#define ADC_FLAGS_THCMP_INT_MASK (0x40000000U)
-#define ADC_FLAGS_THCMP_INT_SHIFT (30U)
-#define ADC_FLAGS_THCMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP_INT_SHIFT)) & ADC_FLAGS_THCMP_INT_MASK)
-#define ADC_FLAGS_OVR_INT_MASK (0x80000000U)
-#define ADC_FLAGS_OVR_INT_SHIFT (31U)
-#define ADC_FLAGS_OVR_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVR_INT_SHIFT)) & ADC_FLAGS_OVR_INT_MASK)
-
-/*! @name STARTUP - ADC Startup register. */
-#define ADC_STARTUP_ADC_ENA_MASK (0x1U)
-#define ADC_STARTUP_ADC_ENA_SHIFT (0U)
-#define ADC_STARTUP_ADC_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_ENA_SHIFT)) & ADC_STARTUP_ADC_ENA_MASK)
-#define ADC_STARTUP_ADC_INIT_MASK (0x2U)
-#define ADC_STARTUP_ADC_INIT_SHIFT (1U)
-#define ADC_STARTUP_ADC_INIT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_INIT_SHIFT)) & ADC_STARTUP_ADC_INIT_MASK)
-
-/*! @name CALIB - ADC Calibration register. */
-#define ADC_CALIB_CALIB_MASK (0x1U)
-#define ADC_CALIB_CALIB_SHIFT (0U)
-#define ADC_CALIB_CALIB(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALIB_SHIFT)) & ADC_CALIB_CALIB_MASK)
-#define ADC_CALIB_CALREQD_MASK (0x2U)
-#define ADC_CALIB_CALREQD_SHIFT (1U)
-#define ADC_CALIB_CALREQD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALREQD_SHIFT)) & ADC_CALIB_CALREQD_MASK)
-#define ADC_CALIB_CALVALUE_MASK (0x1FCU)
-#define ADC_CALIB_CALVALUE_SHIFT (2U)
-#define ADC_CALIB_CALVALUE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALVALUE_SHIFT)) & ADC_CALIB_CALVALUE_MASK)
-
-
-/*!
- * @}
- */ /* end of group ADC_Register_Masks */
-
-
-/* ADC - Peripheral instance base addresses */
-/** Peripheral ADC0 base address */
-#define ADC0_BASE (0x400A0000u)
-/** Peripheral ADC0 base pointer */
-#define ADC0 ((ADC_Type *)ADC0_BASE)
-/** Array initializer of ADC peripheral base addresses */
-#define ADC_BASE_ADDRS { ADC0_BASE }
-/** Array initializer of ADC peripheral base pointers */
-#define ADC_BASE_PTRS { ADC0 }
-/** Interrupt vectors for the ADC peripheral type */
-#define ADC_SEQ_IRQS { ADC0_SEQA_IRQn, ADC0_SEQB_IRQn }
-#define ADC_THCMP_IRQS { ADC0_THCMP_IRQn }
-
-/*!
- * @}
- */ /* end of group ADC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- ASYNC_SYSCON Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup ASYNC_SYSCON_Peripheral_Access_Layer ASYNC_SYSCON Peripheral Access Layer
- * @{
- */
-
-/** ASYNC_SYSCON - Register Layout Typedef */
-typedef struct {
- __IO uint32_t ASYNCPRESETCTRL; /**< Async peripheral reset control, offset: 0x0 */
- __O uint32_t ASYNCPRESETCTRLSET; /**< Set bits in ASYNCPRESETCTRL, offset: 0x4 */
- __O uint32_t ASYNCPRESETCTRLCLR; /**< Clear bits in ASYNCPRESETCTRL, offset: 0x8 */
- uint8_t RESERVED_0[4];
- __IO uint32_t ASYNCAPBCLKCTRL; /**< Async peripheral clock control, offset: 0x10 */
- __O uint32_t ASYNCAPBCLKCTRLSET; /**< Set bits in ASYNCAPBCLKCTRL, offset: 0x14 */
- __O uint32_t ASYNCAPBCLKCTRLCLR; /**< Clear bits in ASYNCAPBCLKCTRL, offset: 0x18 */
- uint8_t RESERVED_1[4];
- __IO uint32_t ASYNCAPBCLKSELA; /**< Async APB clock source select A, offset: 0x20 */
-} ASYNC_SYSCON_Type;
-
-/* ----------------------------------------------------------------------------
- -- ASYNC_SYSCON Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup ASYNC_SYSCON_Register_Masks ASYNC_SYSCON Register Masks
- * @{
- */
-
-/*! @name ASYNCPRESETCTRL - Async peripheral reset control */
-#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK (0x2000U)
-#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT (13U)
-#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK)
-#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK (0x4000U)
-#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT (14U)
-#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK)
-
-/*! @name ASYNCPRESETCTRLSET - Set bits in ASYNCPRESETCTRL */
-#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK (0xFFFFFFFFU)
-#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT (0U)
-#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK)
-
-/*! @name ASYNCPRESETCTRLCLR - Clear bits in ASYNCPRESETCTRL */
-#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK (0xFFFFFFFFU)
-#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT (0U)
-#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK)
-
-/*! @name ASYNCAPBCLKCTRL - Async peripheral clock control */
-#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK (0x2000U)
-#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT (13U)
-#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK)
-#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK (0x4000U)
-#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT (14U)
-#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK)
-
-/*! @name ASYNCAPBCLKCTRLSET - Set bits in ASYNCAPBCLKCTRL */
-#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK (0xFFFFFFFFU)
-#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT (0U)
-#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK)
-
-/*! @name ASYNCAPBCLKCTRLCLR - Clear bits in ASYNCAPBCLKCTRL */
-#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK (0xFFFFFFFFU)
-#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT (0U)
-#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK)
-
-/*! @name ASYNCAPBCLKSELA - Async APB clock source select A */
-#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK (0x3U)
-#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT (0U)
-#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK)
-
-
-/*!
- * @}
- */ /* end of group ASYNC_SYSCON_Register_Masks */
-
-
-/* ASYNC_SYSCON - Peripheral instance base addresses */
-/** Peripheral ASYNC_SYSCON base address */
-#define ASYNC_SYSCON_BASE (0x40040000u)
-/** Peripheral ASYNC_SYSCON base pointer */
-#define ASYNC_SYSCON ((ASYNC_SYSCON_Type *)ASYNC_SYSCON_BASE)
-/** Array initializer of ASYNC_SYSCON peripheral base addresses */
-#define ASYNC_SYSCON_BASE_ADDRS { ASYNC_SYSCON_BASE }
-/** Array initializer of ASYNC_SYSCON peripheral base pointers */
-#define ASYNC_SYSCON_BASE_PTRS { ASYNC_SYSCON }
-
-/*!
- * @}
- */ /* end of group ASYNC_SYSCON_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- CAN Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
- * @{
- */
-
-/** CAN - Register Layout Typedef */
-typedef struct {
- uint8_t RESERVED_0[12];
- __IO uint32_t DBTP; /**< Data Bit Timing Prescaler Register, offset: 0xC */
- __IO uint32_t TEST; /**< Test Register, offset: 0x10 */
- uint8_t RESERVED_1[4];
- __IO uint32_t CCCR; /**< CC Control Register, offset: 0x18 */
- __IO uint32_t NBTP; /**< Nominal Bit Timing and Prescaler Register, offset: 0x1C */
- __IO uint32_t TSCC; /**< Timestamp Counter Configuration, offset: 0x20 */
- __IO uint32_t TSCV; /**< Timestamp Counter Value, offset: 0x24 */
- __IO uint32_t TOCC; /**< Timeout Counter Configuration, offset: 0x28 */
- __I uint32_t TOCV; /**< Timeout Counter Value, offset: 0x2C */
- uint8_t RESERVED_2[16];
- __I uint32_t ECR; /**< Error Counter Register, offset: 0x40 */
- __I uint32_t PSR; /**< Protocol Status Register, offset: 0x44 */
- __IO uint32_t TDCR; /**< Transmitter Delay Compensator Register, offset: 0x48 */
- uint8_t RESERVED_3[4];
- __IO uint32_t IR; /**< Interrupt Register, offset: 0x50 */
- __IO uint32_t IE; /**< Interrupt Enable, offset: 0x54 */
- __IO uint32_t ILS; /**< Interrupt Line Select, offset: 0x58 */
- __IO uint32_t ILE; /**< Interrupt Line Enable, offset: 0x5C */
- uint8_t RESERVED_4[32];
- __IO uint32_t GFC; /**< Global Filter Configuration, offset: 0x80 */
- __IO uint32_t SIDFC; /**< Standard ID Filter Configuration, offset: 0x84 */
- __IO uint32_t XIDFC; /**< Extended ID Filter Configuration, offset: 0x88 */
- uint8_t RESERVED_5[4];
- __IO uint32_t XIDAM; /**< Extended ID AND Mask, offset: 0x90 */
- __I uint32_t HPMS; /**< High Priority Message Status, offset: 0x94 */
- __IO uint32_t NDAT1; /**< New Data 1, offset: 0x98 */
- __IO uint32_t NDAT2; /**< New Data 2, offset: 0x9C */
- __IO uint32_t RXF0C; /**< Rx FIFO 0 Configuration, offset: 0xA0 */
- __IO uint32_t RXF0S; /**< Rx FIFO 0 Status, offset: 0xA4 */
- __IO uint32_t RXF0A; /**< Rx FIFO 0 Acknowledge, offset: 0xA8 */
- __IO uint32_t RXBC; /**< Rx Buffer Configuration, offset: 0xAC */
- __IO uint32_t RXF1C; /**< Rx FIFO 1 Configuration, offset: 0xB0 */
- __I uint32_t RXF1S; /**< Rx FIFO 1 Status, offset: 0xB4 */
- __IO uint32_t RXF1A; /**< Rx FIFO 1 Acknowledge, offset: 0xB8 */
- __IO uint32_t RXESC; /**< Rx Buffer and FIFO Element Size Configuration, offset: 0xBC */
- __IO uint32_t TXBC; /**< Tx Buffer Configuration, offset: 0xC0 */
- __IO uint32_t TXFQS; /**< Tx FIFO/Queue Status, offset: 0xC4 */
- __IO uint32_t TXESC; /**< Tx Buffer Element Size Configuration, offset: 0xC8 */
- __IO uint32_t TXBRP; /**< Tx Buffer Request Pending, offset: 0xCC */
- __IO uint32_t TXBAR; /**< Tx Buffer Add Request, offset: 0xD0 */
- __IO uint32_t TXBCR; /**< Tx Buffer Cancellation Request, offset: 0xD4 */
- __IO uint32_t TXBTO; /**< Tx Buffer Transmission Occurred, offset: 0xD8 */
- __IO uint32_t TXBCF; /**< Tx Buffer Cancellation Finished, offset: 0xDC */
- __IO uint32_t TXBTIE; /**< Tx Buffer Transmission Interrupt Enable, offset: 0xE0 */
- __IO uint32_t TXBCIE; /**< Tx Buffer Cancellation Finished Interrupt Enable, offset: 0xE4 */
- uint8_t RESERVED_6[8];
- __IO uint32_t TXEFC; /**< Tx Event FIFO Configuration, offset: 0xF0 */
- __I uint32_t TXEFS; /**< Tx Event FIFO Status, offset: 0xF4 */
- __IO uint32_t TXEFA; /**< Tx Event FIFO Acknowledge, offset: 0xF8 */
- uint8_t RESERVED_7[260];
- __IO uint32_t MRBA; /**< CAN Message RAM Base Address, offset: 0x200 */
- uint8_t RESERVED_8[508];
- __IO uint32_t ETSCC; /**< External Timestamp Counter Configuration, offset: 0x400 */
- uint8_t RESERVED_9[508];
- __IO uint32_t ETSCV; /**< External Timestamp Counter Value, offset: 0x600 */
-} CAN_Type;
-
-/* ----------------------------------------------------------------------------
- -- CAN Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CAN_Register_Masks CAN Register Masks
- * @{
- */
-
-/*! @name DBTP - Data Bit Timing Prescaler Register */
-#define CAN_DBTP_DSJW_MASK (0xFU)
-#define CAN_DBTP_DSJW_SHIFT (0U)
-#define CAN_DBTP_DSJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DSJW_SHIFT)) & CAN_DBTP_DSJW_MASK)
-#define CAN_DBTP_DTSEG2_MASK (0xF0U)
-#define CAN_DBTP_DTSEG2_SHIFT (4U)
-#define CAN_DBTP_DTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG2_SHIFT)) & CAN_DBTP_DTSEG2_MASK)
-#define CAN_DBTP_DTSEG1_MASK (0x1F00U)
-#define CAN_DBTP_DTSEG1_SHIFT (8U)
-#define CAN_DBTP_DTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG1_SHIFT)) & CAN_DBTP_DTSEG1_MASK)
-#define CAN_DBTP_DBRP_MASK (0x1F0000U)
-#define CAN_DBTP_DBRP_SHIFT (16U)
-#define CAN_DBTP_DBRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DBRP_SHIFT)) & CAN_DBTP_DBRP_MASK)
-#define CAN_DBTP_TDC_MASK (0x800000U)
-#define CAN_DBTP_TDC_SHIFT (23U)
-#define CAN_DBTP_TDC(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_TDC_SHIFT)) & CAN_DBTP_TDC_MASK)
-
-/*! @name TEST - Test Register */
-#define CAN_TEST_LBCK_MASK (0x10U)
-#define CAN_TEST_LBCK_SHIFT (4U)
-#define CAN_TEST_LBCK(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_LBCK_SHIFT)) & CAN_TEST_LBCK_MASK)
-#define CAN_TEST_TX_MASK (0x60U)
-#define CAN_TEST_TX_SHIFT (5U)
-#define CAN_TEST_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_TX_SHIFT)) & CAN_TEST_TX_MASK)
-#define CAN_TEST_RX_MASK (0x80U)
-#define CAN_TEST_RX_SHIFT (7U)
-#define CAN_TEST_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_RX_SHIFT)) & CAN_TEST_RX_MASK)
-
-/*! @name CCCR - CC Control Register */
-#define CAN_CCCR_INIT_MASK (0x1U)
-#define CAN_CCCR_INIT_SHIFT (0U)
-#define CAN_CCCR_INIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_INIT_SHIFT)) & CAN_CCCR_INIT_MASK)
-#define CAN_CCCR_CCE_MASK (0x2U)
-#define CAN_CCCR_CCE_SHIFT (1U)
-#define CAN_CCCR_CCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CCE_SHIFT)) & CAN_CCCR_CCE_MASK)
-#define CAN_CCCR_ASM_MASK (0x4U)
-#define CAN_CCCR_ASM_SHIFT (2U)
-#define CAN_CCCR_ASM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_ASM_SHIFT)) & CAN_CCCR_ASM_MASK)
-#define CAN_CCCR_CSA_MASK (0x8U)
-#define CAN_CCCR_CSA_SHIFT (3U)
-#define CAN_CCCR_CSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSA_SHIFT)) & CAN_CCCR_CSA_MASK)
-#define CAN_CCCR_CSR_MASK (0x10U)
-#define CAN_CCCR_CSR_SHIFT (4U)
-#define CAN_CCCR_CSR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSR_SHIFT)) & CAN_CCCR_CSR_MASK)
-#define CAN_CCCR_MON_MASK (0x20U)
-#define CAN_CCCR_MON_SHIFT (5U)
-#define CAN_CCCR_MON(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_MON_SHIFT)) & CAN_CCCR_MON_MASK)
-#define CAN_CCCR_DAR_MASK (0x40U)
-#define CAN_CCCR_DAR_SHIFT (6U)
-#define CAN_CCCR_DAR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_DAR_SHIFT)) & CAN_CCCR_DAR_MASK)
-#define CAN_CCCR_TEST_MASK (0x80U)
-#define CAN_CCCR_TEST_SHIFT (7U)
-#define CAN_CCCR_TEST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TEST_SHIFT)) & CAN_CCCR_TEST_MASK)
-#define CAN_CCCR_FDOE_MASK (0x100U)
-#define CAN_CCCR_FDOE_SHIFT (8U)
-#define CAN_CCCR_FDOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_FDOE_SHIFT)) & CAN_CCCR_FDOE_MASK)
-#define CAN_CCCR_BRSE_MASK (0x200U)
-#define CAN_CCCR_BRSE_SHIFT (9U)
-#define CAN_CCCR_BRSE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_BRSE_SHIFT)) & CAN_CCCR_BRSE_MASK)
-#define CAN_CCCR_PXHD_MASK (0x1000U)
-#define CAN_CCCR_PXHD_SHIFT (12U)
-#define CAN_CCCR_PXHD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_PXHD_SHIFT)) & CAN_CCCR_PXHD_MASK)
-#define CAN_CCCR_EFBI_MASK (0x2000U)
-#define CAN_CCCR_EFBI_SHIFT (13U)
-#define CAN_CCCR_EFBI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_EFBI_SHIFT)) & CAN_CCCR_EFBI_MASK)
-#define CAN_CCCR_TXP_MASK (0x4000U)
-#define CAN_CCCR_TXP_SHIFT (14U)
-#define CAN_CCCR_TXP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TXP_SHIFT)) & CAN_CCCR_TXP_MASK)
-#define CAN_CCCR_NISO_MASK (0x8000U)
-#define CAN_CCCR_NISO_SHIFT (15U)
-#define CAN_CCCR_NISO(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_NISO_SHIFT)) & CAN_CCCR_NISO_MASK)
-
-/*! @name NBTP - Nominal Bit Timing and Prescaler Register */
-#define CAN_NBTP_NTSEG2_MASK (0x7FU)
-#define CAN_NBTP_NTSEG2_SHIFT (0U)
-#define CAN_NBTP_NTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG2_SHIFT)) & CAN_NBTP_NTSEG2_MASK)
-#define CAN_NBTP_NTSEG1_MASK (0xFF00U)
-#define CAN_NBTP_NTSEG1_SHIFT (8U)
-#define CAN_NBTP_NTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG1_SHIFT)) & CAN_NBTP_NTSEG1_MASK)
-#define CAN_NBTP_NBRP_MASK (0x1FF0000U)
-#define CAN_NBTP_NBRP_SHIFT (16U)
-#define CAN_NBTP_NBRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NBRP_SHIFT)) & CAN_NBTP_NBRP_MASK)
-#define CAN_NBTP_NSJW_MASK (0xFE000000U)
-#define CAN_NBTP_NSJW_SHIFT (25U)
-#define CAN_NBTP_NSJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NSJW_SHIFT)) & CAN_NBTP_NSJW_MASK)
-
-/*! @name TSCC - Timestamp Counter Configuration */
-#define CAN_TSCC_TSS_MASK (0x3U)
-#define CAN_TSCC_TSS_SHIFT (0U)
-#define CAN_TSCC_TSS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TSS_SHIFT)) & CAN_TSCC_TSS_MASK)
-#define CAN_TSCC_TCP_MASK (0xF0000U)
-#define CAN_TSCC_TCP_SHIFT (16U)
-#define CAN_TSCC_TCP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TCP_SHIFT)) & CAN_TSCC_TCP_MASK)
-
-/*! @name TSCV - Timestamp Counter Value */
-#define CAN_TSCV_TSC_MASK (0xFFFFU)
-#define CAN_TSCV_TSC_SHIFT (0U)
-#define CAN_TSCV_TSC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCV_TSC_SHIFT)) & CAN_TSCV_TSC_MASK)
-
-/*! @name TOCC - Timeout Counter Configuration */
-#define CAN_TOCC_ETOC_MASK (0x1U)
-#define CAN_TOCC_ETOC_SHIFT (0U)
-#define CAN_TOCC_ETOC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_ETOC_SHIFT)) & CAN_TOCC_ETOC_MASK)
-#define CAN_TOCC_TOS_MASK (0x6U)
-#define CAN_TOCC_TOS_SHIFT (1U)
-#define CAN_TOCC_TOS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOS_SHIFT)) & CAN_TOCC_TOS_MASK)
-#define CAN_TOCC_TOP_MASK (0xFFFF0000U)
-#define CAN_TOCC_TOP_SHIFT (16U)
-#define CAN_TOCC_TOP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOP_SHIFT)) & CAN_TOCC_TOP_MASK)
-
-/*! @name TOCV - Timeout Counter Value */
-#define CAN_TOCV_TOC_MASK (0xFFFFU)
-#define CAN_TOCV_TOC_SHIFT (0U)
-#define CAN_TOCV_TOC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCV_TOC_SHIFT)) & CAN_TOCV_TOC_MASK)
-
-/*! @name ECR - Error Counter Register */
-#define CAN_ECR_TEC_MASK (0xFFU)
-#define CAN_ECR_TEC_SHIFT (0U)
-#define CAN_ECR_TEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TEC_SHIFT)) & CAN_ECR_TEC_MASK)
-#define CAN_ECR_REC_MASK (0x7F00U)
-#define CAN_ECR_REC_SHIFT (8U)
-#define CAN_ECR_REC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_REC_SHIFT)) & CAN_ECR_REC_MASK)
-#define CAN_ECR_RP_MASK (0x8000U)
-#define CAN_ECR_RP_SHIFT (15U)
-#define CAN_ECR_RP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RP_SHIFT)) & CAN_ECR_RP_MASK)
-#define CAN_ECR_CEL_MASK (0xFF0000U)
-#define CAN_ECR_CEL_SHIFT (16U)
-#define CAN_ECR_CEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_CEL_SHIFT)) & CAN_ECR_CEL_MASK)
-
-/*! @name PSR - Protocol Status Register */
-#define CAN_PSR_LEC_MASK (0x7U)
-#define CAN_PSR_LEC_SHIFT (0U)
-#define CAN_PSR_LEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_LEC_SHIFT)) & CAN_PSR_LEC_MASK)
-#define CAN_PSR_ACT_MASK (0x18U)
-#define CAN_PSR_ACT_SHIFT (3U)
-#define CAN_PSR_ACT(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_ACT_SHIFT)) & CAN_PSR_ACT_MASK)
-#define CAN_PSR_EP_MASK (0x20U)
-#define CAN_PSR_EP_SHIFT (5U)
-#define CAN_PSR_EP(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EP_SHIFT)) & CAN_PSR_EP_MASK)
-#define CAN_PSR_EW_MASK (0x40U)
-#define CAN_PSR_EW_SHIFT (6U)
-#define CAN_PSR_EW(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EW_SHIFT)) & CAN_PSR_EW_MASK)
-#define CAN_PSR_BO_MASK (0x80U)
-#define CAN_PSR_BO_SHIFT (7U)
-#define CAN_PSR_BO(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_BO_SHIFT)) & CAN_PSR_BO_MASK)
-#define CAN_PSR_DLEC_MASK (0x700U)
-#define CAN_PSR_DLEC_SHIFT (8U)
-#define CAN_PSR_DLEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_DLEC_SHIFT)) & CAN_PSR_DLEC_MASK)
-#define CAN_PSR_RESI_MASK (0x800U)
-#define CAN_PSR_RESI_SHIFT (11U)
-#define CAN_PSR_RESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RESI_SHIFT)) & CAN_PSR_RESI_MASK)
-#define CAN_PSR_RBRS_MASK (0x1000U)
-#define CAN_PSR_RBRS_SHIFT (12U)
-#define CAN_PSR_RBRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RBRS_SHIFT)) & CAN_PSR_RBRS_MASK)
-#define CAN_PSR_RFDF_MASK (0x2000U)
-#define CAN_PSR_RFDF_SHIFT (13U)
-#define CAN_PSR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RFDF_SHIFT)) & CAN_PSR_RFDF_MASK)
-#define CAN_PSR_PXE_MASK (0x4000U)
-#define CAN_PSR_PXE_SHIFT (14U)
-#define CAN_PSR_PXE(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_PXE_SHIFT)) & CAN_PSR_PXE_MASK)
-#define CAN_PSR_TDCV_MASK (0x7F0000U)
-#define CAN_PSR_TDCV_SHIFT (16U)
-#define CAN_PSR_TDCV(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_TDCV_SHIFT)) & CAN_PSR_TDCV_MASK)
-
-/*! @name TDCR - Transmitter Delay Compensator Register */
-#define CAN_TDCR_TDCF_MASK (0x7FU)
-#define CAN_TDCR_TDCF_SHIFT (0U)
-#define CAN_TDCR_TDCF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCF_SHIFT)) & CAN_TDCR_TDCF_MASK)
-#define CAN_TDCR_TDCO_MASK (0x7F00U)
-#define CAN_TDCR_TDCO_SHIFT (8U)
-#define CAN_TDCR_TDCO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCO_SHIFT)) & CAN_TDCR_TDCO_MASK)
-
-/*! @name IR - Interrupt Register */
-#define CAN_IR_RF0N_MASK (0x1U)
-#define CAN_IR_RF0N_SHIFT (0U)
-#define CAN_IR_RF0N(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0N_SHIFT)) & CAN_IR_RF0N_MASK)
-#define CAN_IR_RF0W_MASK (0x2U)
-#define CAN_IR_RF0W_SHIFT (1U)
-#define CAN_IR_RF0W(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0W_SHIFT)) & CAN_IR_RF0W_MASK)
-#define CAN_IR_RF0F_MASK (0x4U)
-#define CAN_IR_RF0F_SHIFT (2U)
-#define CAN_IR_RF0F(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0F_SHIFT)) & CAN_IR_RF0F_MASK)
-#define CAN_IR_RF0L_MASK (0x8U)
-#define CAN_IR_RF0L_SHIFT (3U)
-#define CAN_IR_RF0L(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0L_SHIFT)) & CAN_IR_RF0L_MASK)
-#define CAN_IR_RF1N_MASK (0x10U)
-#define CAN_IR_RF1N_SHIFT (4U)
-#define CAN_IR_RF1N(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1N_SHIFT)) & CAN_IR_RF1N_MASK)
-#define CAN_IR_RF1W_MASK (0x20U)
-#define CAN_IR_RF1W_SHIFT (5U)
-#define CAN_IR_RF1W(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1W_SHIFT)) & CAN_IR_RF1W_MASK)
-#define CAN_IR_RF1F_MASK (0x40U)
-#define CAN_IR_RF1F_SHIFT (6U)
-#define CAN_IR_RF1F(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1F_SHIFT)) & CAN_IR_RF1F_MASK)
-#define CAN_IR_RF1L_MASK (0x80U)
-#define CAN_IR_RF1L_SHIFT (7U)
-#define CAN_IR_RF1L(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1L_SHIFT)) & CAN_IR_RF1L_MASK)
-#define CAN_IR_HPM_MASK (0x100U)
-#define CAN_IR_HPM_SHIFT (8U)
-#define CAN_IR_HPM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_HPM_SHIFT)) & CAN_IR_HPM_MASK)
-#define CAN_IR_TC_MASK (0x200U)
-#define CAN_IR_TC_SHIFT (9U)
-#define CAN_IR_TC(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TC_SHIFT)) & CAN_IR_TC_MASK)
-#define CAN_IR_TCF_MASK (0x400U)
-#define CAN_IR_TCF_SHIFT (10U)
-#define CAN_IR_TCF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TCF_SHIFT)) & CAN_IR_TCF_MASK)
-#define CAN_IR_TFE_MASK (0x800U)
-#define CAN_IR_TFE_SHIFT (11U)
-#define CAN_IR_TFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TFE_SHIFT)) & CAN_IR_TFE_MASK)
-#define CAN_IR_TEFN_MASK (0x1000U)
-#define CAN_IR_TEFN_SHIFT (12U)
-#define CAN_IR_TEFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFN_SHIFT)) & CAN_IR_TEFN_MASK)
-#define CAN_IR_TEFW_MASK (0x2000U)
-#define CAN_IR_TEFW_SHIFT (13U)
-#define CAN_IR_TEFW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFW_SHIFT)) & CAN_IR_TEFW_MASK)
-#define CAN_IR_TEFF_MASK (0x4000U)
-#define CAN_IR_TEFF_SHIFT (14U)
-#define CAN_IR_TEFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFF_SHIFT)) & CAN_IR_TEFF_MASK)
-#define CAN_IR_TEFL_MASK (0x8000U)
-#define CAN_IR_TEFL_SHIFT (15U)
-#define CAN_IR_TEFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFL_SHIFT)) & CAN_IR_TEFL_MASK)
-#define CAN_IR_TSW_MASK (0x10000U)
-#define CAN_IR_TSW_SHIFT (16U)
-#define CAN_IR_TSW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TSW_SHIFT)) & CAN_IR_TSW_MASK)
-#define CAN_IR_MRAF_MASK (0x20000U)
-#define CAN_IR_MRAF_SHIFT (17U)
-#define CAN_IR_MRAF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_MRAF_SHIFT)) & CAN_IR_MRAF_MASK)
-#define CAN_IR_TOO_MASK (0x40000U)
-#define CAN_IR_TOO_SHIFT (18U)
-#define CAN_IR_TOO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TOO_SHIFT)) & CAN_IR_TOO_MASK)
-#define CAN_IR_DRX_MASK (0x80000U)
-#define CAN_IR_DRX_SHIFT (19U)
-#define CAN_IR_DRX(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_DRX_SHIFT)) & CAN_IR_DRX_MASK)
-#define CAN_IR_BEC_MASK (0x100000U)
-#define CAN_IR_BEC_SHIFT (20U)
-#define CAN_IR_BEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEC_SHIFT)) & CAN_IR_BEC_MASK)
-#define CAN_IR_BEU_MASK (0x200000U)
-#define CAN_IR_BEU_SHIFT (21U)
-#define CAN_IR_BEU(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEU_SHIFT)) & CAN_IR_BEU_MASK)
-#define CAN_IR_ELO_MASK (0x400000U)
-#define CAN_IR_ELO_SHIFT (22U)
-#define CAN_IR_ELO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_ELO_SHIFT)) & CAN_IR_ELO_MASK)
-#define CAN_IR_EP_MASK (0x800000U)
-#define CAN_IR_EP_SHIFT (23U)
-#define CAN_IR_EP(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_EP_SHIFT)) & CAN_IR_EP_MASK)
-#define CAN_IR_EW_MASK (0x1000000U)
-#define CAN_IR_EW_SHIFT (24U)
-#define CAN_IR_EW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_EW_SHIFT)) & CAN_IR_EW_MASK)
-#define CAN_IR_BO_MASK (0x2000000U)
-#define CAN_IR_BO_SHIFT (25U)
-#define CAN_IR_BO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BO_SHIFT)) & CAN_IR_BO_MASK)
-#define CAN_IR_WDI_MASK (0x4000000U)
-#define CAN_IR_WDI_SHIFT (26U)
-#define CAN_IR_WDI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_WDI_SHIFT)) & CAN_IR_WDI_MASK)
-#define CAN_IR_PEA_MASK (0x8000000U)
-#define CAN_IR_PEA_SHIFT (27U)
-#define CAN_IR_PEA(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_PEA_SHIFT)) & CAN_IR_PEA_MASK)
-#define CAN_IR_PED_MASK (0x10000000U)
-#define CAN_IR_PED_SHIFT (28U)
-#define CAN_IR_PED(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_PED_SHIFT)) & CAN_IR_PED_MASK)
-#define CAN_IR_ARA_MASK (0x20000000U)
-#define CAN_IR_ARA_SHIFT (29U)
-#define CAN_IR_ARA(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_ARA_SHIFT)) & CAN_IR_ARA_MASK)
-
-/*! @name IE - Interrupt Enable */
-#define CAN_IE_RF0NE_MASK (0x1U)
-#define CAN_IE_RF0NE_SHIFT (0U)
-#define CAN_IE_RF0NE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0NE_SHIFT)) & CAN_IE_RF0NE_MASK)
-#define CAN_IE_RF0WE_MASK (0x2U)
-#define CAN_IE_RF0WE_SHIFT (1U)
-#define CAN_IE_RF0WE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0WE_SHIFT)) & CAN_IE_RF0WE_MASK)
-#define CAN_IE_RF0FE_MASK (0x4U)
-#define CAN_IE_RF0FE_SHIFT (2U)
-#define CAN_IE_RF0FE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0FE_SHIFT)) & CAN_IE_RF0FE_MASK)
-#define CAN_IE_RF0LE_MASK (0x8U)
-#define CAN_IE_RF0LE_SHIFT (3U)
-#define CAN_IE_RF0LE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0LE_SHIFT)) & CAN_IE_RF0LE_MASK)
-#define CAN_IE_RF1NE_MASK (0x10U)
-#define CAN_IE_RF1NE_SHIFT (4U)
-#define CAN_IE_RF1NE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1NE_SHIFT)) & CAN_IE_RF1NE_MASK)
-#define CAN_IE_RF1WE_MASK (0x20U)
-#define CAN_IE_RF1WE_SHIFT (5U)
-#define CAN_IE_RF1WE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1WE_SHIFT)) & CAN_IE_RF1WE_MASK)
-#define CAN_IE_RF1FE_MASK (0x40U)
-#define CAN_IE_RF1FE_SHIFT (6U)
-#define CAN_IE_RF1FE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1FE_SHIFT)) & CAN_IE_RF1FE_MASK)
-#define CAN_IE_RF1LE_MASK (0x80U)
-#define CAN_IE_RF1LE_SHIFT (7U)
-#define CAN_IE_RF1LE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1LE_SHIFT)) & CAN_IE_RF1LE_MASK)
-#define CAN_IE_HPME_MASK (0x100U)
-#define CAN_IE_HPME_SHIFT (8U)
-#define CAN_IE_HPME(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_HPME_SHIFT)) & CAN_IE_HPME_MASK)
-#define CAN_IE_TCE_MASK (0x200U)
-#define CAN_IE_TCE_SHIFT (9U)
-#define CAN_IE_TCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCE_SHIFT)) & CAN_IE_TCE_MASK)
-#define CAN_IE_TCFE_MASK (0x400U)
-#define CAN_IE_TCFE_SHIFT (10U)
-#define CAN_IE_TCFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCFE_SHIFT)) & CAN_IE_TCFE_MASK)
-#define CAN_IE_TFEE_MASK (0x800U)
-#define CAN_IE_TFEE_SHIFT (11U)
-#define CAN_IE_TFEE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TFEE_SHIFT)) & CAN_IE_TFEE_MASK)
-#define CAN_IE_TEFNE_MASK (0x1000U)
-#define CAN_IE_TEFNE_SHIFT (12U)
-#define CAN_IE_TEFNE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFNE_SHIFT)) & CAN_IE_TEFNE_MASK)
-#define CAN_IE_TEFWE_MASK (0x2000U)
-#define CAN_IE_TEFWE_SHIFT (13U)
-#define CAN_IE_TEFWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFWE_SHIFT)) & CAN_IE_TEFWE_MASK)
-#define CAN_IE_TEFFE_MASK (0x4000U)
-#define CAN_IE_TEFFE_SHIFT (14U)
-#define CAN_IE_TEFFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFFE_SHIFT)) & CAN_IE_TEFFE_MASK)
-#define CAN_IE_TEFLE_MASK (0x8000U)
-#define CAN_IE_TEFLE_SHIFT (15U)
-#define CAN_IE_TEFLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFLE_SHIFT)) & CAN_IE_TEFLE_MASK)
-#define CAN_IE_TSWE_MASK (0x10000U)
-#define CAN_IE_TSWE_SHIFT (16U)
-#define CAN_IE_TSWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TSWE_SHIFT)) & CAN_IE_TSWE_MASK)
-#define CAN_IE_MRAFE_MASK (0x20000U)
-#define CAN_IE_MRAFE_SHIFT (17U)
-#define CAN_IE_MRAFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_MRAFE_SHIFT)) & CAN_IE_MRAFE_MASK)
-#define CAN_IE_TOOE_MASK (0x40000U)
-#define CAN_IE_TOOE_SHIFT (18U)
-#define CAN_IE_TOOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TOOE_SHIFT)) & CAN_IE_TOOE_MASK)
-#define CAN_IE_DRXE_MASK (0x80000U)
-#define CAN_IE_DRXE_SHIFT (19U)
-#define CAN_IE_DRXE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_DRXE_SHIFT)) & CAN_IE_DRXE_MASK)
-#define CAN_IE_BECE_MASK (0x100000U)
-#define CAN_IE_BECE_SHIFT (20U)
-#define CAN_IE_BECE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BECE_SHIFT)) & CAN_IE_BECE_MASK)
-#define CAN_IE_BEUE_MASK (0x200000U)
-#define CAN_IE_BEUE_SHIFT (21U)
-#define CAN_IE_BEUE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BEUE_SHIFT)) & CAN_IE_BEUE_MASK)
-#define CAN_IE_ELOE_MASK (0x400000U)
-#define CAN_IE_ELOE_SHIFT (22U)
-#define CAN_IE_ELOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_ELOE_SHIFT)) & CAN_IE_ELOE_MASK)
-#define CAN_IE_EPE_MASK (0x800000U)
-#define CAN_IE_EPE_SHIFT (23U)
-#define CAN_IE_EPE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_EPE_SHIFT)) & CAN_IE_EPE_MASK)
-#define CAN_IE_EWE_MASK (0x1000000U)
-#define CAN_IE_EWE_SHIFT (24U)
-#define CAN_IE_EWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_EWE_SHIFT)) & CAN_IE_EWE_MASK)
-#define CAN_IE_BOE_MASK (0x2000000U)
-#define CAN_IE_BOE_SHIFT (25U)
-#define CAN_IE_BOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BOE_SHIFT)) & CAN_IE_BOE_MASK)
-#define CAN_IE_WDIE_MASK (0x4000000U)
-#define CAN_IE_WDIE_SHIFT (26U)
-#define CAN_IE_WDIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_WDIE_SHIFT)) & CAN_IE_WDIE_MASK)
-#define CAN_IE_PEAE_MASK (0x8000000U)
-#define CAN_IE_PEAE_SHIFT (27U)
-#define CAN_IE_PEAE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEAE_SHIFT)) & CAN_IE_PEAE_MASK)
-#define CAN_IE_PEDE_MASK (0x10000000U)
-#define CAN_IE_PEDE_SHIFT (28U)
-#define CAN_IE_PEDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEDE_SHIFT)) & CAN_IE_PEDE_MASK)
-#define CAN_IE_ARAE_MASK (0x20000000U)
-#define CAN_IE_ARAE_SHIFT (29U)
-#define CAN_IE_ARAE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_ARAE_SHIFT)) & CAN_IE_ARAE_MASK)
-
-/*! @name ILS - Interrupt Line Select */
-#define CAN_ILS_RF0NL_MASK (0x1U)
-#define CAN_ILS_RF0NL_SHIFT (0U)
-#define CAN_ILS_RF0NL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0NL_SHIFT)) & CAN_ILS_RF0NL_MASK)
-#define CAN_ILS_RF0WL_MASK (0x2U)
-#define CAN_ILS_RF0WL_SHIFT (1U)
-#define CAN_ILS_RF0WL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0WL_SHIFT)) & CAN_ILS_RF0WL_MASK)
-#define CAN_ILS_RF0FL_MASK (0x4U)
-#define CAN_ILS_RF0FL_SHIFT (2U)
-#define CAN_ILS_RF0FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0FL_SHIFT)) & CAN_ILS_RF0FL_MASK)
-#define CAN_ILS_RF0LL_MASK (0x8U)
-#define CAN_ILS_RF0LL_SHIFT (3U)
-#define CAN_ILS_RF0LL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0LL_SHIFT)) & CAN_ILS_RF0LL_MASK)
-#define CAN_ILS_RF1NL_MASK (0x10U)
-#define CAN_ILS_RF1NL_SHIFT (4U)
-#define CAN_ILS_RF1NL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1NL_SHIFT)) & CAN_ILS_RF1NL_MASK)
-#define CAN_ILS_RF1WL_MASK (0x20U)
-#define CAN_ILS_RF1WL_SHIFT (5U)
-#define CAN_ILS_RF1WL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1WL_SHIFT)) & CAN_ILS_RF1WL_MASK)
-#define CAN_ILS_RF1FL_MASK (0x40U)
-#define CAN_ILS_RF1FL_SHIFT (6U)
-#define CAN_ILS_RF1FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1FL_SHIFT)) & CAN_ILS_RF1FL_MASK)
-#define CAN_ILS_RF1LL_MASK (0x80U)
-#define CAN_ILS_RF1LL_SHIFT (7U)
-#define CAN_ILS_RF1LL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1LL_SHIFT)) & CAN_ILS_RF1LL_MASK)
-#define CAN_ILS_HPML_MASK (0x100U)
-#define CAN_ILS_HPML_SHIFT (8U)
-#define CAN_ILS_HPML(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_HPML_SHIFT)) & CAN_ILS_HPML_MASK)
-#define CAN_ILS_TCL_MASK (0x200U)
-#define CAN_ILS_TCL_SHIFT (9U)
-#define CAN_ILS_TCL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCL_SHIFT)) & CAN_ILS_TCL_MASK)
-#define CAN_ILS_TCFL_MASK (0x400U)
-#define CAN_ILS_TCFL_SHIFT (10U)
-#define CAN_ILS_TCFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCFL_SHIFT)) & CAN_ILS_TCFL_MASK)
-#define CAN_ILS_TFEL_MASK (0x800U)
-#define CAN_ILS_TFEL_SHIFT (11U)
-#define CAN_ILS_TFEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TFEL_SHIFT)) & CAN_ILS_TFEL_MASK)
-#define CAN_ILS_TEFNL_MASK (0x1000U)
-#define CAN_ILS_TEFNL_SHIFT (12U)
-#define CAN_ILS_TEFNL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFNL_SHIFT)) & CAN_ILS_TEFNL_MASK)
-#define CAN_ILS_TEFWL_MASK (0x2000U)
-#define CAN_ILS_TEFWL_SHIFT (13U)
-#define CAN_ILS_TEFWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFWL_SHIFT)) & CAN_ILS_TEFWL_MASK)
-#define CAN_ILS_TEFFL_MASK (0x4000U)
-#define CAN_ILS_TEFFL_SHIFT (14U)
-#define CAN_ILS_TEFFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFFL_SHIFT)) & CAN_ILS_TEFFL_MASK)
-#define CAN_ILS_TEFLL_MASK (0x8000U)
-#define CAN_ILS_TEFLL_SHIFT (15U)
-#define CAN_ILS_TEFLL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFLL_SHIFT)) & CAN_ILS_TEFLL_MASK)
-#define CAN_ILS_TSWL_MASK (0x10000U)
-#define CAN_ILS_TSWL_SHIFT (16U)
-#define CAN_ILS_TSWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TSWL_SHIFT)) & CAN_ILS_TSWL_MASK)
-#define CAN_ILS_MRAFL_MASK (0x20000U)
-#define CAN_ILS_MRAFL_SHIFT (17U)
-#define CAN_ILS_MRAFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_MRAFL_SHIFT)) & CAN_ILS_MRAFL_MASK)
-#define CAN_ILS_TOOL_MASK (0x40000U)
-#define CAN_ILS_TOOL_SHIFT (18U)
-#define CAN_ILS_TOOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TOOL_SHIFT)) & CAN_ILS_TOOL_MASK)
-#define CAN_ILS_DRXL_MASK (0x80000U)
-#define CAN_ILS_DRXL_SHIFT (19U)
-#define CAN_ILS_DRXL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_DRXL_SHIFT)) & CAN_ILS_DRXL_MASK)
-#define CAN_ILS_BECL_MASK (0x100000U)
-#define CAN_ILS_BECL_SHIFT (20U)
-#define CAN_ILS_BECL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BECL_SHIFT)) & CAN_ILS_BECL_MASK)
-#define CAN_ILS_BEUL_MASK (0x200000U)
-#define CAN_ILS_BEUL_SHIFT (21U)
-#define CAN_ILS_BEUL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BEUL_SHIFT)) & CAN_ILS_BEUL_MASK)
-#define CAN_ILS_ELOL_MASK (0x400000U)
-#define CAN_ILS_ELOL_SHIFT (22U)
-#define CAN_ILS_ELOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ELOL_SHIFT)) & CAN_ILS_ELOL_MASK)
-#define CAN_ILS_EPL_MASK (0x800000U)
-#define CAN_ILS_EPL_SHIFT (23U)
-#define CAN_ILS_EPL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EPL_SHIFT)) & CAN_ILS_EPL_MASK)
-#define CAN_ILS_EWL_MASK (0x1000000U)
-#define CAN_ILS_EWL_SHIFT (24U)
-#define CAN_ILS_EWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EWL_SHIFT)) & CAN_ILS_EWL_MASK)
-#define CAN_ILS_BOL_MASK (0x2000000U)
-#define CAN_ILS_BOL_SHIFT (25U)
-#define CAN_ILS_BOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BOL_SHIFT)) & CAN_ILS_BOL_MASK)
-#define CAN_ILS_WDIL_MASK (0x4000000U)
-#define CAN_ILS_WDIL_SHIFT (26U)
-#define CAN_ILS_WDIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_WDIL_SHIFT)) & CAN_ILS_WDIL_MASK)
-#define CAN_ILS_PEAL_MASK (0x8000000U)
-#define CAN_ILS_PEAL_SHIFT (27U)
-#define CAN_ILS_PEAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEAL_SHIFT)) & CAN_ILS_PEAL_MASK)
-#define CAN_ILS_PEDL_MASK (0x10000000U)
-#define CAN_ILS_PEDL_SHIFT (28U)
-#define CAN_ILS_PEDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEDL_SHIFT)) & CAN_ILS_PEDL_MASK)
-#define CAN_ILS_ARAL_MASK (0x20000000U)
-#define CAN_ILS_ARAL_SHIFT (29U)
-#define CAN_ILS_ARAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ARAL_SHIFT)) & CAN_ILS_ARAL_MASK)
-
-/*! @name ILE - Interrupt Line Enable */
-#define CAN_ILE_EINT0_MASK (0x1U)
-#define CAN_ILE_EINT0_SHIFT (0U)
-#define CAN_ILE_EINT0(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT0_SHIFT)) & CAN_ILE_EINT0_MASK)
-#define CAN_ILE_EINT1_MASK (0x2U)
-#define CAN_ILE_EINT1_SHIFT (1U)
-#define CAN_ILE_EINT1(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT1_SHIFT)) & CAN_ILE_EINT1_MASK)
-
-/*! @name GFC - Global Filter Configuration */
-#define CAN_GFC_RRFE_MASK (0x1U)
-#define CAN_GFC_RRFE_SHIFT (0U)
-#define CAN_GFC_RRFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFE_SHIFT)) & CAN_GFC_RRFE_MASK)
-#define CAN_GFC_RRFS_MASK (0x2U)
-#define CAN_GFC_RRFS_SHIFT (1U)
-#define CAN_GFC_RRFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFS_SHIFT)) & CAN_GFC_RRFS_MASK)
-#define CAN_GFC_ANFE_MASK (0xCU)
-#define CAN_GFC_ANFE_SHIFT (2U)
-#define CAN_GFC_ANFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFE_SHIFT)) & CAN_GFC_ANFE_MASK)
-#define CAN_GFC_ANFS_MASK (0x30U)
-#define CAN_GFC_ANFS_SHIFT (4U)
-#define CAN_GFC_ANFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFS_SHIFT)) & CAN_GFC_ANFS_MASK)
-
-/*! @name SIDFC - Standard ID Filter Configuration */
-#define CAN_SIDFC_FLSSA_MASK (0xFFFCU)
-#define CAN_SIDFC_FLSSA_SHIFT (2U)
-#define CAN_SIDFC_FLSSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_FLSSA_SHIFT)) & CAN_SIDFC_FLSSA_MASK)
-#define CAN_SIDFC_LSS_MASK (0xFF0000U)
-#define CAN_SIDFC_LSS_SHIFT (16U)
-#define CAN_SIDFC_LSS(x) (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_LSS_SHIFT)) & CAN_SIDFC_LSS_MASK)
-
-/*! @name XIDFC - Extended ID Filter Configuration */
-#define CAN_XIDFC_FLESA_MASK (0xFFFCU)
-#define CAN_XIDFC_FLESA_SHIFT (2U)
-#define CAN_XIDFC_FLESA(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_FLESA_SHIFT)) & CAN_XIDFC_FLESA_MASK)
-#define CAN_XIDFC_LSE_MASK (0xFF0000U)
-#define CAN_XIDFC_LSE_SHIFT (16U)
-#define CAN_XIDFC_LSE(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_LSE_SHIFT)) & CAN_XIDFC_LSE_MASK)
-
-/*! @name XIDAM - Extended ID AND Mask */
-#define CAN_XIDAM_EIDM_MASK (0x1FFFFFFFU)
-#define CAN_XIDAM_EIDM_SHIFT (0U)
-#define CAN_XIDAM_EIDM(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDAM_EIDM_SHIFT)) & CAN_XIDAM_EIDM_MASK)
-
-/*! @name HPMS - High Priority Message Status */
-#define CAN_HPMS_BIDX_MASK (0x3FU)
-#define CAN_HPMS_BIDX_SHIFT (0U)
-#define CAN_HPMS_BIDX(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_BIDX_SHIFT)) & CAN_HPMS_BIDX_MASK)
-#define CAN_HPMS_MSI_MASK (0xC0U)
-#define CAN_HPMS_MSI_SHIFT (6U)
-#define CAN_HPMS_MSI(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_MSI_SHIFT)) & CAN_HPMS_MSI_MASK)
-#define CAN_HPMS_FIDX_MASK (0x7F00U)
-#define CAN_HPMS_FIDX_SHIFT (8U)
-#define CAN_HPMS_FIDX(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FIDX_SHIFT)) & CAN_HPMS_FIDX_MASK)
-#define CAN_HPMS_FLST_MASK (0x8000U)
-#define CAN_HPMS_FLST_SHIFT (15U)
-#define CAN_HPMS_FLST(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FLST_SHIFT)) & CAN_HPMS_FLST_MASK)
-
-/*! @name NDAT1 - New Data 1 */
-#define CAN_NDAT1_ND_MASK (0xFFFFFFFFU)
-#define CAN_NDAT1_ND_SHIFT (0U)
-#define CAN_NDAT1_ND(x) (((uint32_t)(((uint32_t)(x)) << CAN_NDAT1_ND_SHIFT)) & CAN_NDAT1_ND_MASK)
-
-/*! @name NDAT2 - New Data 2 */
-#define CAN_NDAT2_ND_MASK (0xFFFFFFFFU)
-#define CAN_NDAT2_ND_SHIFT (0U)
-#define CAN_NDAT2_ND(x) (((uint32_t)(((uint32_t)(x)) << CAN_NDAT2_ND_SHIFT)) & CAN_NDAT2_ND_MASK)
-
-/*! @name RXF0C - Rx FIFO 0 Configuration */
-#define CAN_RXF0C_F0SA_MASK (0xFFFCU)
-#define CAN_RXF0C_F0SA_SHIFT (2U)
-#define CAN_RXF0C_F0SA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0SA_SHIFT)) & CAN_RXF0C_F0SA_MASK)
-#define CAN_RXF0C_F0S_MASK (0x7F0000U)
-#define CAN_RXF0C_F0S_SHIFT (16U)
-#define CAN_RXF0C_F0S(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0S_SHIFT)) & CAN_RXF0C_F0S_MASK)
-#define CAN_RXF0C_F0WM_MASK (0x7F000000U)
-#define CAN_RXF0C_F0WM_SHIFT (24U)
-#define CAN_RXF0C_F0WM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0WM_SHIFT)) & CAN_RXF0C_F0WM_MASK)
-#define CAN_RXF0C_F0OM_MASK (0x80000000U)
-#define CAN_RXF0C_F0OM_SHIFT (31U)
-#define CAN_RXF0C_F0OM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0OM_SHIFT)) & CAN_RXF0C_F0OM_MASK)
-
-/*! @name RXF0S - Rx FIFO 0 Status */
-#define CAN_RXF0S_F0FL_MASK (0x7FU)
-#define CAN_RXF0S_F0FL_SHIFT (0U)
-#define CAN_RXF0S_F0FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0FL_SHIFT)) & CAN_RXF0S_F0FL_MASK)
-#define CAN_RXF0S_F0GI_MASK (0x3F00U)
-#define CAN_RXF0S_F0GI_SHIFT (8U)
-#define CAN_RXF0S_F0GI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0GI_SHIFT)) & CAN_RXF0S_F0GI_MASK)
-#define CAN_RXF0S_F0PI_MASK (0x3F0000U)
-#define CAN_RXF0S_F0PI_SHIFT (16U)
-#define CAN_RXF0S_F0PI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0PI_SHIFT)) & CAN_RXF0S_F0PI_MASK)
-#define CAN_RXF0S_F0F_MASK (0x1000000U)
-#define CAN_RXF0S_F0F_SHIFT (24U)
-#define CAN_RXF0S_F0F(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0F_SHIFT)) & CAN_RXF0S_F0F_MASK)
-#define CAN_RXF0S_RF0L_MASK (0x2000000U)
-#define CAN_RXF0S_RF0L_SHIFT (25U)
-#define CAN_RXF0S_RF0L(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_RF0L_SHIFT)) & CAN_RXF0S_RF0L_MASK)
-
-/*! @name RXF0A - Rx FIFO 0 Acknowledge */
-#define CAN_RXF0A_F0AI_MASK (0x3FU)
-#define CAN_RXF0A_F0AI_SHIFT (0U)
-#define CAN_RXF0A_F0AI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0A_F0AI_SHIFT)) & CAN_RXF0A_F0AI_MASK)
-
-/*! @name RXBC - Rx Buffer Configuration */
-#define CAN_RXBC_RBSA_MASK (0xFFFCU)
-#define CAN_RXBC_RBSA_SHIFT (2U)
-#define CAN_RXBC_RBSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXBC_RBSA_SHIFT)) & CAN_RXBC_RBSA_MASK)
-
-/*! @name RXF1C - Rx FIFO 1 Configuration */
-#define CAN_RXF1C_F1SA_MASK (0xFFFCU)
-#define CAN_RXF1C_F1SA_SHIFT (2U)
-#define CAN_RXF1C_F1SA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1SA_SHIFT)) & CAN_RXF1C_F1SA_MASK)
-#define CAN_RXF1C_F1S_MASK (0x7F0000U)
-#define CAN_RXF1C_F1S_SHIFT (16U)
-#define CAN_RXF1C_F1S(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1S_SHIFT)) & CAN_RXF1C_F1S_MASK)
-#define CAN_RXF1C_F1WM_MASK (0x7F000000U)
-#define CAN_RXF1C_F1WM_SHIFT (24U)
-#define CAN_RXF1C_F1WM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1WM_SHIFT)) & CAN_RXF1C_F1WM_MASK)
-#define CAN_RXF1C_F1OM_MASK (0x80000000U)
-#define CAN_RXF1C_F1OM_SHIFT (31U)
-#define CAN_RXF1C_F1OM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1OM_SHIFT)) & CAN_RXF1C_F1OM_MASK)
-
-/*! @name RXF1S - Rx FIFO 1 Status */
-#define CAN_RXF1S_F1FL_MASK (0x7FU)
-#define CAN_RXF1S_F1FL_SHIFT (0U)
-#define CAN_RXF1S_F1FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1FL_SHIFT)) & CAN_RXF1S_F1FL_MASK)
-#define CAN_RXF1S_F1GI_MASK (0x3F00U)
-#define CAN_RXF1S_F1GI_SHIFT (8U)
-#define CAN_RXF1S_F1GI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1GI_SHIFT)) & CAN_RXF1S_F1GI_MASK)
-#define CAN_RXF1S_F1PI_MASK (0x3F0000U)
-#define CAN_RXF1S_F1PI_SHIFT (16U)
-#define CAN_RXF1S_F1PI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1PI_SHIFT)) & CAN_RXF1S_F1PI_MASK)
-#define CAN_RXF1S_F1F_MASK (0x1000000U)
-#define CAN_RXF1S_F1F_SHIFT (24U)
-#define CAN_RXF1S_F1F(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1F_SHIFT)) & CAN_RXF1S_F1F_MASK)
-#define CAN_RXF1S_RF1L_MASK (0x2000000U)
-#define CAN_RXF1S_RF1L_SHIFT (25U)
-#define CAN_RXF1S_RF1L(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_RF1L_SHIFT)) & CAN_RXF1S_RF1L_MASK)
-
-/*! @name RXF1A - Rx FIFO 1 Acknowledge */
-#define CAN_RXF1A_F1AI_MASK (0x3FU)
-#define CAN_RXF1A_F1AI_SHIFT (0U)
-#define CAN_RXF1A_F1AI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1A_F1AI_SHIFT)) & CAN_RXF1A_F1AI_MASK)
-
-/*! @name RXESC - Rx Buffer and FIFO Element Size Configuration */
-#define CAN_RXESC_F0DS_MASK (0x7U)
-#define CAN_RXESC_F0DS_SHIFT (0U)
-#define CAN_RXESC_F0DS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F0DS_SHIFT)) & CAN_RXESC_F0DS_MASK)
-#define CAN_RXESC_F1DS_MASK (0x70U)
-#define CAN_RXESC_F1DS_SHIFT (4U)
-#define CAN_RXESC_F1DS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F1DS_SHIFT)) & CAN_RXESC_F1DS_MASK)
-#define CAN_RXESC_RBDS_MASK (0x700U)
-#define CAN_RXESC_RBDS_SHIFT (8U)
-#define CAN_RXESC_RBDS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_RBDS_SHIFT)) & CAN_RXESC_RBDS_MASK)
-
-/*! @name TXBC - Tx Buffer Configuration */
-#define CAN_TXBC_TBSA_MASK (0xFFFCU)
-#define CAN_TXBC_TBSA_SHIFT (2U)
-#define CAN_TXBC_TBSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TBSA_SHIFT)) & CAN_TXBC_TBSA_MASK)
-#define CAN_TXBC_NDTB_MASK (0x3F0000U)
-#define CAN_TXBC_NDTB_SHIFT (16U)
-#define CAN_TXBC_NDTB(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_NDTB_SHIFT)) & CAN_TXBC_NDTB_MASK)
-#define CAN_TXBC_TFQS_MASK (0x3F000000U)
-#define CAN_TXBC_TFQS_SHIFT (24U)
-#define CAN_TXBC_TFQS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQS_SHIFT)) & CAN_TXBC_TFQS_MASK)
-#define CAN_TXBC_TFQM_MASK (0x40000000U)
-#define CAN_TXBC_TFQM_SHIFT (30U)
-#define CAN_TXBC_TFQM(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQM_SHIFT)) & CAN_TXBC_TFQM_MASK)
-
-/*! @name TXFQS - Tx FIFO/Queue Status */
-#define CAN_TXFQS_TFGI_MASK (0x1F00U)
-#define CAN_TXFQS_TFGI_SHIFT (8U)
-#define CAN_TXFQS_TFGI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFGI_SHIFT)) & CAN_TXFQS_TFGI_MASK)
-#define CAN_TXFQS_TFQPI_MASK (0x1F0000U)
-#define CAN_TXFQS_TFQPI_SHIFT (16U)
-#define CAN_TXFQS_TFQPI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQPI_SHIFT)) & CAN_TXFQS_TFQPI_MASK)
-#define CAN_TXFQS_TFQF_MASK (0x200000U)
-#define CAN_TXFQS_TFQF_SHIFT (21U)
-#define CAN_TXFQS_TFQF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQF_SHIFT)) & CAN_TXFQS_TFQF_MASK)
-
-/*! @name TXESC - Tx Buffer Element Size Configuration */
-#define CAN_TXESC_TBDS_MASK (0x7U)
-#define CAN_TXESC_TBDS_SHIFT (0U)
-#define CAN_TXESC_TBDS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXESC_TBDS_SHIFT)) & CAN_TXESC_TBDS_MASK)
-
-/*! @name TXBRP - Tx Buffer Request Pending */
-#define CAN_TXBRP_TRP_MASK (0xFFFFFFFFU)
-#define CAN_TXBRP_TRP_SHIFT (0U)
-#define CAN_TXBRP_TRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBRP_TRP_SHIFT)) & CAN_TXBRP_TRP_MASK)
-
-/*! @name TXBAR - Tx Buffer Add Request */
-#define CAN_TXBAR_AR_MASK (0xFFFFFFFFU)
-#define CAN_TXBAR_AR_SHIFT (0U)
-#define CAN_TXBAR_AR(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBAR_AR_SHIFT)) & CAN_TXBAR_AR_MASK)
-
-/*! @name TXBCR - Tx Buffer Cancellation Request */
-#define CAN_TXBCR_CR_MASK (0xFFFFFFFFU)
-#define CAN_TXBCR_CR_SHIFT (0U)
-#define CAN_TXBCR_CR(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCR_CR_SHIFT)) & CAN_TXBCR_CR_MASK)
-
-/*! @name TXBTO - Tx Buffer Transmission Occurred */
-#define CAN_TXBTO_TO_MASK (0xFFFFFFFFU)
-#define CAN_TXBTO_TO_SHIFT (0U)
-#define CAN_TXBTO_TO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBTO_TO_SHIFT)) & CAN_TXBTO_TO_MASK)
-
-/*! @name TXBCF - Tx Buffer Cancellation Finished */
-#define CAN_TXBCF_TO_MASK (0xFFFFFFFFU)
-#define CAN_TXBCF_TO_SHIFT (0U)
-#define CAN_TXBCF_TO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCF_TO_SHIFT)) & CAN_TXBCF_TO_MASK)
-
-/*! @name TXBTIE - Tx Buffer Transmission Interrupt Enable */
-#define CAN_TXBTIE_TIE_MASK (0xFFFFFFFFU)
-#define CAN_TXBTIE_TIE_SHIFT (0U)
-#define CAN_TXBTIE_TIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBTIE_TIE_SHIFT)) & CAN_TXBTIE_TIE_MASK)
-
-/*! @name TXBCIE - Tx Buffer Cancellation Finished Interrupt Enable */
-#define CAN_TXBCIE_CFIE_MASK (0xFFFFFFFFU)
-#define CAN_TXBCIE_CFIE_SHIFT (0U)
-#define CAN_TXBCIE_CFIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCIE_CFIE_SHIFT)) & CAN_TXBCIE_CFIE_MASK)
-
-/*! @name TXEFC - Tx Event FIFO Configuration */
-#define CAN_TXEFC_EFSA_MASK (0xFFFCU)
-#define CAN_TXEFC_EFSA_SHIFT (2U)
-#define CAN_TXEFC_EFSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFSA_SHIFT)) & CAN_TXEFC_EFSA_MASK)
-#define CAN_TXEFC_EFS_MASK (0x3F0000U)
-#define CAN_TXEFC_EFS_SHIFT (16U)
-#define CAN_TXEFC_EFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFS_SHIFT)) & CAN_TXEFC_EFS_MASK)
-#define CAN_TXEFC_EFWM_MASK (0x3F000000U)
-#define CAN_TXEFC_EFWM_SHIFT (24U)
-#define CAN_TXEFC_EFWM(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFWM_SHIFT)) & CAN_TXEFC_EFWM_MASK)
-
-/*! @name TXEFS - Tx Event FIFO Status */
-#define CAN_TXEFS_EFFL_MASK (0x3FU)
-#define CAN_TXEFS_EFFL_SHIFT (0U)
-#define CAN_TXEFS_EFFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFFL_SHIFT)) & CAN_TXEFS_EFFL_MASK)
-#define CAN_TXEFS_EFGI_MASK (0x1F00U)
-#define CAN_TXEFS_EFGI_SHIFT (8U)
-#define CAN_TXEFS_EFGI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFGI_SHIFT)) & CAN_TXEFS_EFGI_MASK)
-#define CAN_TXEFS_EFPI_MASK (0x3F0000U)
-#define CAN_TXEFS_EFPI_SHIFT (16U)
-#define CAN_TXEFS_EFPI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFPI_SHIFT)) & CAN_TXEFS_EFPI_MASK)
-#define CAN_TXEFS_EFF_MASK (0x1000000U)
-#define CAN_TXEFS_EFF_SHIFT (24U)
-#define CAN_TXEFS_EFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFF_SHIFT)) & CAN_TXEFS_EFF_MASK)
-#define CAN_TXEFS_TEFL_MASK (0x2000000U)
-#define CAN_TXEFS_TEFL_SHIFT (25U)
-#define CAN_TXEFS_TEFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_TEFL_SHIFT)) & CAN_TXEFS_TEFL_MASK)
-
-/*! @name TXEFA - Tx Event FIFO Acknowledge */
-#define CAN_TXEFA_EFAI_MASK (0x1FU)
-#define CAN_TXEFA_EFAI_SHIFT (0U)
-#define CAN_TXEFA_EFAI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFA_EFAI_SHIFT)) & CAN_TXEFA_EFAI_MASK)
-
-/*! @name MRBA - CAN Message RAM Base Address */
-#define CAN_MRBA_BA_MASK (0xFFFFFFFFU)
-#define CAN_MRBA_BA_SHIFT (0U)
-#define CAN_MRBA_BA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MRBA_BA_SHIFT)) & CAN_MRBA_BA_MASK)
-
-/*! @name ETSCC - External Timestamp Counter Configuration */
-#define CAN_ETSCC_ETCP_MASK (0x7FFU)
-#define CAN_ETSCC_ETCP_SHIFT (0U)
-#define CAN_ETSCC_ETCP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCP_SHIFT)) & CAN_ETSCC_ETCP_MASK)
-#define CAN_ETSCC_ETCE_MASK (0x80000000U)
-#define CAN_ETSCC_ETCE_SHIFT (31U)
-#define CAN_ETSCC_ETCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCE_SHIFT)) & CAN_ETSCC_ETCE_MASK)
-
-/*! @name ETSCV - External Timestamp Counter Value */
-#define CAN_ETSCV_ETSC_MASK (0xFFFFU)
-#define CAN_ETSCV_ETSC_SHIFT (0U)
-#define CAN_ETSCV_ETSC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCV_ETSC_SHIFT)) & CAN_ETSCV_ETSC_MASK)
-
-
-/*!
- * @}
- */ /* end of group CAN_Register_Masks */
-
-
-/* CAN - Peripheral instance base addresses */
-/** Peripheral CAN0 base address */
-#define CAN0_BASE (0x4009D000u)
-/** Peripheral CAN0 base pointer */
-#define CAN0 ((CAN_Type *)CAN0_BASE)
-/** Peripheral CAN1 base address */
-#define CAN1_BASE (0x4009E000u)
-/** Peripheral CAN1 base pointer */
-#define CAN1 ((CAN_Type *)CAN1_BASE)
-/** Array initializer of CAN peripheral base addresses */
-#define CAN_BASE_ADDRS { CAN0_BASE, CAN1_BASE }
-/** Array initializer of CAN peripheral base pointers */
-#define CAN_BASE_PTRS { CAN0, CAN1 }
-/** Interrupt vectors for the CAN peripheral type */
-#define CAN_IRQS { { CAN0_IRQ0_IRQn, CAN0_IRQ1_IRQn }, { CAN1_IRQ0_IRQn, CAN1_IRQ1_IRQn } }
-
-/*!
- * @}
- */ /* end of group CAN_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- CRC Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
- * @{
- */
-
-/** CRC - Register Layout Typedef */
-typedef struct {
- __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */
- __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */
- union { /* offset: 0x8 */
- __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */
- __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */
- };
-} CRC_Type;
-
-/* ----------------------------------------------------------------------------
- -- CRC Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CRC_Register_Masks CRC Register Masks
- * @{
- */
-
-/*! @name MODE - CRC mode register */
-#define CRC_MODE_CRC_POLY_MASK (0x3U)
-#define CRC_MODE_CRC_POLY_SHIFT (0U)
-#define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK)
-#define CRC_MODE_BIT_RVS_WR_MASK (0x4U)
-#define CRC_MODE_BIT_RVS_WR_SHIFT (2U)
-#define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK)
-#define CRC_MODE_CMPL_WR_MASK (0x8U)
-#define CRC_MODE_CMPL_WR_SHIFT (3U)
-#define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK)
-#define CRC_MODE_BIT_RVS_SUM_MASK (0x10U)
-#define CRC_MODE_BIT_RVS_SUM_SHIFT (4U)
-#define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK)
-#define CRC_MODE_CMPL_SUM_MASK (0x20U)
-#define CRC_MODE_CMPL_SUM_SHIFT (5U)
-#define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK)
-
-/*! @name SEED - CRC seed register */
-#define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU)
-#define CRC_SEED_CRC_SEED_SHIFT (0U)
-#define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK)
-
-/*! @name SUM - CRC checksum register */
-#define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU)
-#define CRC_SUM_CRC_SUM_SHIFT (0U)
-#define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK)
-
-/*! @name WR_DATA - CRC data register */
-#define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU)
-#define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U)
-#define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK)
-
-
-/*!
- * @}
- */ /* end of group CRC_Register_Masks */
-
-
-/* CRC - Peripheral instance base addresses */
-/** Peripheral CRC_ENGINE base address */
-#define CRC_ENGINE_BASE (0x40095000u)
-/** Peripheral CRC_ENGINE base pointer */
-#define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE)
-/** Array initializer of CRC peripheral base addresses */
-#define CRC_BASE_ADDRS { CRC_ENGINE_BASE }
-/** Array initializer of CRC peripheral base pointers */
-#define CRC_BASE_PTRS { CRC_ENGINE }
-
-/*!
- * @}
- */ /* end of group CRC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- CTIMER Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer
- * @{
- */
-
-/** CTIMER - Register Layout Typedef */
-typedef struct {
- __IO uint32_t IR; /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */
- __IO uint32_t TCR; /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */
- __IO uint32_t TC; /**< Timer Counter, offset: 0x8 */
- __IO uint32_t PR; /**< Prescale Register, offset: 0xC */
- __IO uint32_t PC; /**< Prescale Counter, offset: 0x10 */
- __IO uint32_t MCR; /**< Match Control Register, offset: 0x14 */
- __IO uint32_t MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */
- __IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */
- __I uint32_t CR[4]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */
- __IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */
- uint8_t RESERVED_0[48];
- __IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */
- __IO uint32_t PWMC; /**< PWM Control Register. The PWMCON enables PWM mode for the external match pins., offset: 0x74 */
- __IO uint32_t MSR[4]; /**< Match Shadow Register, array offset: 0x78, array step: 0x4 */
-} CTIMER_Type;
-
-/* ----------------------------------------------------------------------------
- -- CTIMER Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup CTIMER_Register_Masks CTIMER Register Masks
- * @{
- */
-
-/*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
-#define CTIMER_IR_MR0INT_MASK (0x1U)
-#define CTIMER_IR_MR0INT_SHIFT (0U)
-#define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK)
-#define CTIMER_IR_MR1INT_MASK (0x2U)
-#define CTIMER_IR_MR1INT_SHIFT (1U)
-#define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK)
-#define CTIMER_IR_MR2INT_MASK (0x4U)
-#define CTIMER_IR_MR2INT_SHIFT (2U)
-#define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK)
-#define CTIMER_IR_MR3INT_MASK (0x8U)
-#define CTIMER_IR_MR3INT_SHIFT (3U)
-#define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK)
-#define CTIMER_IR_CR0INT_MASK (0x10U)
-#define CTIMER_IR_CR0INT_SHIFT (4U)
-#define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK)
-#define CTIMER_IR_CR1INT_MASK (0x20U)
-#define CTIMER_IR_CR1INT_SHIFT (5U)
-#define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK)
-#define CTIMER_IR_CR2INT_MASK (0x40U)
-#define CTIMER_IR_CR2INT_SHIFT (6U)
-#define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK)
-#define CTIMER_IR_CR3INT_MASK (0x80U)
-#define CTIMER_IR_CR3INT_SHIFT (7U)
-#define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK)
-
-/*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
-#define CTIMER_TCR_CEN_MASK (0x1U)
-#define CTIMER_TCR_CEN_SHIFT (0U)
-#define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK)
-#define CTIMER_TCR_CRST_MASK (0x2U)
-#define CTIMER_TCR_CRST_SHIFT (1U)
-#define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK)
-
-/*! @name TC - Timer Counter */
-#define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU)
-#define CTIMER_TC_TCVAL_SHIFT (0U)
-#define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK)
-
-/*! @name PR - Prescale Register */
-#define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU)
-#define CTIMER_PR_PRVAL_SHIFT (0U)
-#define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK)
-
-/*! @name PC - Prescale Counter */
-#define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU)
-#define CTIMER_PC_PCVAL_SHIFT (0U)
-#define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK)
-
-/*! @name MCR - Match Control Register */
-#define CTIMER_MCR_MR0I_MASK (0x1U)
-#define CTIMER_MCR_MR0I_SHIFT (0U)
-#define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
-#define CTIMER_MCR_MR0R_MASK (0x2U)
-#define CTIMER_MCR_MR0R_SHIFT (1U)
-#define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK)
-#define CTIMER_MCR_MR0S_MASK (0x4U)
-#define CTIMER_MCR_MR0S_SHIFT (2U)
-#define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK)
-#define CTIMER_MCR_MR1I_MASK (0x8U)
-#define CTIMER_MCR_MR1I_SHIFT (3U)
-#define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK)
-#define CTIMER_MCR_MR1R_MASK (0x10U)
-#define CTIMER_MCR_MR1R_SHIFT (4U)
-#define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK)
-#define CTIMER_MCR_MR1S_MASK (0x20U)
-#define CTIMER_MCR_MR1S_SHIFT (5U)
-#define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK)
-#define CTIMER_MCR_MR2I_MASK (0x40U)
-#define CTIMER_MCR_MR2I_SHIFT (6U)
-#define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK)
-#define CTIMER_MCR_MR2R_MASK (0x80U)
-#define CTIMER_MCR_MR2R_SHIFT (7U)
-#define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK)
-#define CTIMER_MCR_MR2S_MASK (0x100U)
-#define CTIMER_MCR_MR2S_SHIFT (8U)
-#define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK)
-#define CTIMER_MCR_MR3I_MASK (0x200U)
-#define CTIMER_MCR_MR3I_SHIFT (9U)
-#define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK)
-#define CTIMER_MCR_MR3R_MASK (0x400U)
-#define CTIMER_MCR_MR3R_SHIFT (10U)
-#define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK)
-#define CTIMER_MCR_MR3S_MASK (0x800U)
-#define CTIMER_MCR_MR3S_SHIFT (11U)
-#define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK)
-#define CTIMER_MCR_MR0RL_MASK (0x1000000U)
-#define CTIMER_MCR_MR0RL_SHIFT (24U)
-#define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK)
-#define CTIMER_MCR_MR1RL_MASK (0x2000000U)
-#define CTIMER_MCR_MR1RL_SHIFT (25U)
-#define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK)
-#define CTIMER_MCR_MR2RL_MASK (0x4000000U)
-#define CTIMER_MCR_MR2RL_SHIFT (26U)
-#define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK)
-#define CTIMER_MCR_MR3RL_MASK (0x8000000U)
-#define CTIMER_MCR_MR3RL_SHIFT (27U)
-#define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK)
-
-/*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
-#define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU)
-#define CTIMER_MR_MATCH_SHIFT (0U)
-#define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK)
-
-/* The count of CTIMER_MR */
-#define CTIMER_MR_COUNT (4U)
-
-/*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
-#define CTIMER_CCR_CAP0RE_MASK (0x1U)
-#define CTIMER_CCR_CAP0RE_SHIFT (0U)
-#define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK)
-#define CTIMER_CCR_CAP0FE_MASK (0x2U)
-#define CTIMER_CCR_CAP0FE_SHIFT (1U)
-#define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK)
-#define CTIMER_CCR_CAP0I_MASK (0x4U)
-#define CTIMER_CCR_CAP0I_SHIFT (2U)
-#define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
-#define CTIMER_CCR_CAP1RE_MASK (0x8U)
-#define CTIMER_CCR_CAP1RE_SHIFT (3U)
-#define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK)
-#define CTIMER_CCR_CAP1FE_MASK (0x10U)
-#define CTIMER_CCR_CAP1FE_SHIFT (4U)
-#define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK)
-#define CTIMER_CCR_CAP1I_MASK (0x20U)
-#define CTIMER_CCR_CAP1I_SHIFT (5U)
-#define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK)
-#define CTIMER_CCR_CAP2RE_MASK (0x40U)
-#define CTIMER_CCR_CAP2RE_SHIFT (6U)
-#define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK)
-#define CTIMER_CCR_CAP2FE_MASK (0x80U)
-#define CTIMER_CCR_CAP2FE_SHIFT (7U)
-#define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK)
-#define CTIMER_CCR_CAP2I_MASK (0x100U)
-#define CTIMER_CCR_CAP2I_SHIFT (8U)
-#define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK)
-#define CTIMER_CCR_CAP3RE_MASK (0x200U)
-#define CTIMER_CCR_CAP3RE_SHIFT (9U)
-#define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK)
-#define CTIMER_CCR_CAP3FE_MASK (0x400U)
-#define CTIMER_CCR_CAP3FE_SHIFT (10U)
-#define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK)
-#define CTIMER_CCR_CAP3I_MASK (0x800U)
-#define CTIMER_CCR_CAP3I_SHIFT (11U)
-#define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK)
-
-/*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */
-#define CTIMER_CR_CAP_MASK (0xFFFFFFFFU)
-#define CTIMER_CR_CAP_SHIFT (0U)
-#define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK)
-
-/* The count of CTIMER_CR */
-#define CTIMER_CR_COUNT (4U)
-
-/*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */
-#define CTIMER_EMR_EM0_MASK (0x1U)
-#define CTIMER_EMR_EM0_SHIFT (0U)
-#define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK)
-#define CTIMER_EMR_EM1_MASK (0x2U)
-#define CTIMER_EMR_EM1_SHIFT (1U)
-#define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK)
-#define CTIMER_EMR_EM2_MASK (0x4U)
-#define CTIMER_EMR_EM2_SHIFT (2U)
-#define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK)
-#define CTIMER_EMR_EM3_MASK (0x8U)
-#define CTIMER_EMR_EM3_SHIFT (3U)
-#define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK)
-#define CTIMER_EMR_EMC0_MASK (0x30U)
-#define CTIMER_EMR_EMC0_SHIFT (4U)
-#define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK)
-#define CTIMER_EMR_EMC1_MASK (0xC0U)
-#define CTIMER_EMR_EMC1_SHIFT (6U)
-#define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK)
-#define CTIMER_EMR_EMC2_MASK (0x300U)
-#define CTIMER_EMR_EMC2_SHIFT (8U)
-#define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK)
-#define CTIMER_EMR_EMC3_MASK (0xC00U)
-#define CTIMER_EMR_EMC3_SHIFT (10U)
-#define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK)
-
-/*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
-#define CTIMER_CTCR_CTMODE_MASK (0x3U)
-#define CTIMER_CTCR_CTMODE_SHIFT (0U)
-#define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK)
-#define CTIMER_CTCR_CINSEL_MASK (0xCU)
-#define CTIMER_CTCR_CINSEL_SHIFT (2U)
-#define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK)
-#define CTIMER_CTCR_ENCC_MASK (0x10U)
-#define CTIMER_CTCR_ENCC_SHIFT (4U)
-#define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK)
-#define CTIMER_CTCR_SELCC_MASK (0xE0U)
-#define CTIMER_CTCR_SELCC_SHIFT (5U)
-#define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK)
-
-/*! @name PWMC - PWM Control Register. The PWMCON enables PWM mode for the external match pins. */
-#define CTIMER_PWMC_PWMEN0_MASK (0x1U)
-#define CTIMER_PWMC_PWMEN0_SHIFT (0U)
-#define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK)
-#define CTIMER_PWMC_PWMEN1_MASK (0x2U)
-#define CTIMER_PWMC_PWMEN1_SHIFT (1U)
-#define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK)
-#define CTIMER_PWMC_PWMEN2_MASK (0x4U)
-#define CTIMER_PWMC_PWMEN2_SHIFT (2U)
-#define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK)
-#define CTIMER_PWMC_PWMEN3_MASK (0x8U)
-#define CTIMER_PWMC_PWMEN3_SHIFT (3U)
-#define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK)
-
-/*! @name MSR - Match Shadow Register */
-#define CTIMER_MSR_SHADOWW_MASK (0xFFFFFFFFU)
-#define CTIMER_MSR_SHADOWW_SHIFT (0U)
-#define CTIMER_MSR_SHADOWW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_SHADOWW_SHIFT)) & CTIMER_MSR_SHADOWW_MASK)
-
-/* The count of CTIMER_MSR */
-#define CTIMER_MSR_COUNT (4U)
-
-
-/*!
- * @}
- */ /* end of group CTIMER_Register_Masks */
-
-
-/* CTIMER - Peripheral instance base addresses */
-/** Peripheral CTIMER0 base address */
-#define CTIMER0_BASE (0x40008000u)
-/** Peripheral CTIMER0 base pointer */
-#define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE)
-/** Peripheral CTIMER1 base address */
-#define CTIMER1_BASE (0x40009000u)
-/** Peripheral CTIMER1 base pointer */
-#define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE)
-/** Peripheral CTIMER2 base address */
-#define CTIMER2_BASE (0x40028000u)
-/** Peripheral CTIMER2 base pointer */
-#define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE)
-/** Peripheral CTIMER3 base address */
-#define CTIMER3_BASE (0x40048000u)
-/** Peripheral CTIMER3 base pointer */
-#define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE)
-/** Peripheral CTIMER4 base address */
-#define CTIMER4_BASE (0x40049000u)
-/** Peripheral CTIMER4 base pointer */
-#define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE)
-/** Array initializer of CTIMER peripheral base addresses */
-#define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE }
-/** Array initializer of CTIMER peripheral base pointers */
-#define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 }
-/** Interrupt vectors for the CTIMER peripheral type */
-#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn }
-
-/*!
- * @}
- */ /* end of group CTIMER_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- DMA Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
- * @{
- */
-
-/** DMA - Register Layout Typedef */
-typedef struct {
- __IO uint32_t CTRL; /**< DMA control., offset: 0x0 */
- __I uint32_t INTSTAT; /**< Interrupt status., offset: 0x4 */
- __IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table., offset: 0x8 */
- uint8_t RESERVED_0[20];
- struct { /* offset: 0x20, array step: 0x5C */
- __IO uint32_t ENABLESET; /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */
- uint8_t RESERVED_0[4];
- __O uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */
- uint8_t RESERVED_1[4];
- __I uint32_t ACTIVE; /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */
- uint8_t RESERVED_2[4];
- __I uint32_t BUSY; /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */
- uint8_t RESERVED_3[4];
- __IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */
- uint8_t RESERVED_4[4];
- __IO uint32_t INTENSET; /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */
- uint8_t RESERVED_5[4];
- __O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */
- uint8_t RESERVED_6[4];
- __IO uint32_t INTA; /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */
- uint8_t RESERVED_7[4];
- __IO uint32_t INTB; /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */
- uint8_t RESERVED_8[4];
- __O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */
- uint8_t RESERVED_9[4];
- __O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */
- uint8_t RESERVED_10[4];
- __O uint32_t ABORT; /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */
- } COMMON[1];
- uint8_t RESERVED_1[900];
- struct { /* offset: 0x400, array step: 0x10 */
- __IO uint32_t CFG; /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */
- __I uint32_t CTLSTAT; /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */
- __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */
- uint8_t RESERVED_0[4];
- } CHANNEL[30];
-} DMA_Type;
-
-/* ----------------------------------------------------------------------------
- -- DMA Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DMA_Register_Masks DMA Register Masks
- * @{
- */
-
-/*! @name CTRL - DMA control. */
-#define DMA_CTRL_ENABLE_MASK (0x1U)
-#define DMA_CTRL_ENABLE_SHIFT (0U)
-#define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK)
-
-/*! @name INTSTAT - Interrupt status. */
-#define DMA_INTSTAT_ACTIVEINT_MASK (0x2U)
-#define DMA_INTSTAT_ACTIVEINT_SHIFT (1U)
-#define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK)
-#define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U)
-#define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U)
-#define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK)
-
-/*! @name SRAMBASE - SRAM address of the channel configuration table. */
-#define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U)
-#define DMA_SRAMBASE_OFFSET_SHIFT (9U)
-#define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK)
-
-/*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */
-#define DMA_COMMON_ENABLESET_ENA_MASK (0xFFFFFFFFU)
-#define DMA_COMMON_ENABLESET_ENA_SHIFT (0U)
-#define DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK)
-
-/* The count of DMA_COMMON_ENABLESET */
-#define DMA_COMMON_ENABLESET_COUNT (1U)
-
-/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */
-#define DMA_COMMON_ENABLECLR_CLR_MASK (0xFFFFFFFFU)
-#define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U)
-#define DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK)
-
-/* The count of DMA_COMMON_ENABLECLR */
-#define DMA_COMMON_ENABLECLR_COUNT (1U)
-
-/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */
-#define DMA_COMMON_ACTIVE_ACT_MASK (0xFFFFFFFFU)
-#define DMA_COMMON_ACTIVE_ACT_SHIFT (0U)
-#define DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK)
-
-/* The count of DMA_COMMON_ACTIVE */
-#define DMA_COMMON_ACTIVE_COUNT (1U)
-
-/*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */
-#define DMA_COMMON_BUSY_BSY_MASK (0xFFFFFFFFU)
-#define DMA_COMMON_BUSY_BSY_SHIFT (0U)
-#define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK)
-
-/* The count of DMA_COMMON_BUSY */
-#define DMA_COMMON_BUSY_COUNT (1U)
-
-/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */
-#define DMA_COMMON_ERRINT_ERR_MASK (0xFFFFFFFFU)
-#define DMA_COMMON_ERRINT_ERR_SHIFT (0U)
-#define DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK)
-
-/* The count of DMA_COMMON_ERRINT */
-#define DMA_COMMON_ERRINT_COUNT (1U)
-
-/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */
-#define DMA_COMMON_INTENSET_INTEN_MASK (0xFFFFFFFFU)
-#define DMA_COMMON_INTENSET_INTEN_SHIFT (0U)
-#define DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK)
-
-/* The count of DMA_COMMON_INTENSET */
-#define DMA_COMMON_INTENSET_COUNT (1U)
-
-/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */
-#define DMA_COMMON_INTENCLR_CLR_MASK (0xFFFFFFFFU)
-#define DMA_COMMON_INTENCLR_CLR_SHIFT (0U)
-#define DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK)
-
-/* The count of DMA_COMMON_INTENCLR */
-#define DMA_COMMON_INTENCLR_COUNT (1U)
-
-/*! @name COMMON_INTA - Interrupt A status for all DMA channels. */
-#define DMA_COMMON_INTA_IA_MASK (0xFFFFFFFFU)
-#define DMA_COMMON_INTA_IA_SHIFT (0U)
-#define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK)
-
-/* The count of DMA_COMMON_INTA */
-#define DMA_COMMON_INTA_COUNT (1U)
-
-/*! @name COMMON_INTB - Interrupt B status for all DMA channels. */
-#define DMA_COMMON_INTB_IB_MASK (0xFFFFFFFFU)
-#define DMA_COMMON_INTB_IB_SHIFT (0U)
-#define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK)
-
-/* The count of DMA_COMMON_INTB */
-#define DMA_COMMON_INTB_COUNT (1U)
-
-/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */
-#define DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU)
-#define DMA_COMMON_SETVALID_SV_SHIFT (0U)
-#define DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK)
-
-/* The count of DMA_COMMON_SETVALID */
-#define DMA_COMMON_SETVALID_COUNT (1U)
-
-/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */
-#define DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU)
-#define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U)
-#define DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK)
-
-/* The count of DMA_COMMON_SETTRIG */
-#define DMA_COMMON_SETTRIG_COUNT (1U)
-
-/*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */
-#define DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU)
-#define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U)
-#define DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK)
-
-/* The count of DMA_COMMON_ABORT */
-#define DMA_COMMON_ABORT_COUNT (1U)
-
-/*! @name CHANNEL_CFG - Configuration register for DMA channel . */
-#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U)
-#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U)
-#define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK)
-#define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U)
-#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U)
-#define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK)
-#define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U)
-#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U)
-#define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK)
-#define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U)
-#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U)
-#define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK)
-#define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U)
-#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U)
-#define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK)
-#define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U)
-#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U)
-#define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK)
-#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U)
-#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U)
-#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK)
-#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U)
-#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U)
-#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK)
-#define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U)
-#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U)
-#define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK)
-
-/* The count of DMA_CHANNEL_CFG */
-#define DMA_CHANNEL_CFG_COUNT (30U)
-
-/*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */
-#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U)
-#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U)
-#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK)
-#define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U)
-#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U)
-#define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK)
-
-/* The count of DMA_CHANNEL_CTLSTAT */
-#define DMA_CHANNEL_CTLSTAT_COUNT (30U)
-
-/*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */
-#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U)
-#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U)
-#define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK)
-#define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U)
-#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U)
-#define DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK)
-#define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U)
-#define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U)
-#define DMA_CHANNEL_XFERCFG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK)
-#define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U)
-#define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U)
-#define DMA_CHANNEL_XFERCFG_CLRTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK)
-#define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U)
-#define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U)
-#define DMA_CHANNEL_XFERCFG_SETINTA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK)
-#define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U)
-#define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U)
-#define DMA_CHANNEL_XFERCFG_SETINTB(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK)
-#define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U)
-#define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U)
-#define DMA_CHANNEL_XFERCFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK)
-#define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U)
-#define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U)
-#define DMA_CHANNEL_XFERCFG_SRCINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK)
-#define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U)
-#define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U)
-#define DMA_CHANNEL_XFERCFG_DSTINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK)
-#define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U)
-#define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U)
-#define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK)
-
-/* The count of DMA_CHANNEL_XFERCFG */
-#define DMA_CHANNEL_XFERCFG_COUNT (30U)
-
-
-/*!
- * @}
- */ /* end of group DMA_Register_Masks */
-
-
-/* DMA - Peripheral instance base addresses */
-/** Peripheral DMA0 base address */
-#define DMA0_BASE (0x40082000u)
-/** Peripheral DMA0 base pointer */
-#define DMA0 ((DMA_Type *)DMA0_BASE)
-/** Array initializer of DMA peripheral base addresses */
-#define DMA_BASE_ADDRS { DMA0_BASE }
-/** Array initializer of DMA peripheral base pointers */
-#define DMA_BASE_PTRS { DMA0 }
-/** Interrupt vectors for the DMA peripheral type */
-#define DMA_IRQS { DMA0_IRQn }
-
-/*!
- * @}
- */ /* end of group DMA_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- DMIC Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DMIC_Peripheral_Access_Layer DMIC Peripheral Access Layer
- * @{
- */
-
-/** DMIC - Register Layout Typedef */
-typedef struct {
- struct { /* offset: 0x0, array step: 0x100 */
- __IO uint32_t OSR; /**< Oversample Rate register 0, array offset: 0x0, array step: 0x100 */
- __IO uint32_t DIVHFCLK; /**< DMIC Clock Register 0, array offset: 0x4, array step: 0x100 */
- __IO uint32_t PREAC2FSCOEF; /**< Pre-Emphasis Filter Coefficient for 2 FS register, array offset: 0x8, array step: 0x100 */
- __IO uint32_t PREAC4FSCOEF; /**< Pre-Emphasis Filter Coefficient for 4 FS register, array offset: 0xC, array step: 0x100 */
- __IO uint32_t GAINSHIFT; /**< Decimator Gain Shift register, array offset: 0x10, array step: 0x100 */
- uint8_t RESERVED_0[108];
- __IO uint32_t FIFO_CTRL; /**< FIFO Control register 0, array offset: 0x80, array step: 0x100 */
- __IO uint32_t FIFO_STATUS; /**< FIFO Status register 0, array offset: 0x84, array step: 0x100 */
- __IO uint32_t FIFO_DATA; /**< FIFO Data Register 0, array offset: 0x88, array step: 0x100 */
- __IO uint32_t PHY_CTRL; /**< PDM Source Configuration register 0, array offset: 0x8C, array step: 0x100 */
- __IO uint32_t DC_CTRL; /**< DC Control register 0, array offset: 0x90, array step: 0x100 */
- uint8_t RESERVED_1[108];
- } CHANNEL[2];
- uint8_t RESERVED_0[3328];
- __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */
- uint8_t RESERVED_1[8];
- __IO uint32_t IOCFG; /**< I/O Configuration register, offset: 0xF0C */
- __IO uint32_t USE2FS; /**< Use 2FS register, offset: 0xF10 */
- uint8_t RESERVED_2[108];
- __IO uint32_t HWVADGAIN; /**< HWVAD input gain register, offset: 0xF80 */
- __IO uint32_t HWVADHPFS; /**< HWVAD filter control register, offset: 0xF84 */
- __IO uint32_t HWVADST10; /**< HWVAD control register, offset: 0xF88 */
- __IO uint32_t HWVADRSTT; /**< HWVAD filter reset register, offset: 0xF8C */
- __IO uint32_t HWVADTHGN; /**< HWVAD noise estimator gain register, offset: 0xF90 */
- __IO uint32_t HWVADTHGS; /**< HWVAD signal estimator gain register, offset: 0xF94 */
- __I uint32_t HWVADLOWZ; /**< HWVAD noise envelope estimator register, offset: 0xF98 */
- uint8_t RESERVED_3[96];
- __I uint32_t ID; /**< Module Identification register, offset: 0xFFC */
-} DMIC_Type;
-
-/* ----------------------------------------------------------------------------
- -- DMIC Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup DMIC_Register_Masks DMIC Register Masks
- * @{
- */
-
-/*! @name CHANNEL_OSR - Oversample Rate register 0 */
-#define DMIC_CHANNEL_OSR_OSR_MASK (0xFFU)
-#define DMIC_CHANNEL_OSR_OSR_SHIFT (0U)
-#define DMIC_CHANNEL_OSR_OSR(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_OSR_OSR_SHIFT)) & DMIC_CHANNEL_OSR_OSR_MASK)
-
-/* The count of DMIC_CHANNEL_OSR */
-#define DMIC_CHANNEL_OSR_COUNT (2U)
-
-/*! @name CHANNEL_DIVHFCLK - DMIC Clock Register 0 */
-#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK (0xFU)
-#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT (0U)
-#define DMIC_CHANNEL_DIVHFCLK_PDMDIV(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT)) & DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK)
-
-/* The count of DMIC_CHANNEL_DIVHFCLK */
-#define DMIC_CHANNEL_DIVHFCLK_COUNT (2U)
-
-/*! @name CHANNEL_PREAC2FSCOEF - Pre-Emphasis Filter Coefficient for 2 FS register */
-#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK (0x3U)
-#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT (0U)
-#define DMIC_CHANNEL_PREAC2FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK)
-
-/* The count of DMIC_CHANNEL_PREAC2FSCOEF */
-#define DMIC_CHANNEL_PREAC2FSCOEF_COUNT (2U)
-
-/*! @name CHANNEL_PREAC4FSCOEF - Pre-Emphasis Filter Coefficient for 4 FS register */
-#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK (0x3U)
-#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT (0U)
-#define DMIC_CHANNEL_PREAC4FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK)
-
-/* The count of DMIC_CHANNEL_PREAC4FSCOEF */
-#define DMIC_CHANNEL_PREAC4FSCOEF_COUNT (2U)
-
-/*! @name CHANNEL_GAINSHIFT - Decimator Gain Shift register */
-#define DMIC_CHANNEL_GAINSHIFT_GAIN_MASK (0x3FU)
-#define DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT (0U)
-#define DMIC_CHANNEL_GAINSHIFT_GAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT)) & DMIC_CHANNEL_GAINSHIFT_GAIN_MASK)
-
-/* The count of DMIC_CHANNEL_GAINSHIFT */
-#define DMIC_CHANNEL_GAINSHIFT_COUNT (2U)
-
-/*! @name CHANNEL_FIFO_CTRL - FIFO Control register 0 */
-#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK (0x1U)
-#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT (0U)
-#define DMIC_CHANNEL_FIFO_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK)
-#define DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK (0x2U)
-#define DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT (1U)
-#define DMIC_CHANNEL_FIFO_CTRL_RESETN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK)
-#define DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK (0x4U)
-#define DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT (2U)
-#define DMIC_CHANNEL_FIFO_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK)
-#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK (0x8U)
-#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT (3U)
-#define DMIC_CHANNEL_FIFO_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK)
-#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK (0x1F0000U)
-#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT (16U)
-#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK)
-
-/* The count of DMIC_CHANNEL_FIFO_CTRL */
-#define DMIC_CHANNEL_FIFO_CTRL_COUNT (2U)
-
-/*! @name CHANNEL_FIFO_STATUS - FIFO Status register 0 */
-#define DMIC_CHANNEL_FIFO_STATUS_INT_MASK (0x1U)
-#define DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT (0U)
-#define DMIC_CHANNEL_FIFO_STATUS_INT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_INT_MASK)
-#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK (0x2U)
-#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT (1U)
-#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK)
-#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK (0x4U)
-#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT (2U)
-#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK)
-
-/* The count of DMIC_CHANNEL_FIFO_STATUS */
-#define DMIC_CHANNEL_FIFO_STATUS_COUNT (2U)
-
-/*! @name CHANNEL_FIFO_DATA - FIFO Data Register 0 */
-#define DMIC_CHANNEL_FIFO_DATA_DATA_MASK (0xFFFFFFU)
-#define DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT (0U)
-#define DMIC_CHANNEL_FIFO_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT)) & DMIC_CHANNEL_FIFO_DATA_DATA_MASK)
-
-/* The count of DMIC_CHANNEL_FIFO_DATA */
-#define DMIC_CHANNEL_FIFO_DATA_COUNT (2U)
-
-/*! @name CHANNEL_PHY_CTRL - PDM Source Configuration register 0 */
-#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK (0x1U)
-#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT (0U)
-#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK)
-#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK (0x2U)
-#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT (1U)
-#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK)
-
-/* The count of DMIC_CHANNEL_PHY_CTRL */
-#define DMIC_CHANNEL_PHY_CTRL_COUNT (2U)
-
-/*! @name CHANNEL_DC_CTRL - DC Control register 0 */
-#define DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK (0x3U)
-#define DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT (0U)
-#define DMIC_CHANNEL_DC_CTRL_DCPOLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK)
-#define DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK (0xF0U)
-#define DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT (4U)
-#define DMIC_CHANNEL_DC_CTRL_DCGAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK)
-#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK (0x100U)
-#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT (8U)
-#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT)) & DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK)
-
-/* The count of DMIC_CHANNEL_DC_CTRL */
-#define DMIC_CHANNEL_DC_CTRL_COUNT (2U)
-
-/*! @name CHANEN - Channel Enable register */
-#define DMIC_CHANEN_EN_CH0_MASK (0x1U)
-#define DMIC_CHANEN_EN_CH0_SHIFT (0U)
-#define DMIC_CHANEN_EN_CH0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH0_SHIFT)) & DMIC_CHANEN_EN_CH0_MASK)
-#define DMIC_CHANEN_EN_CH1_MASK (0x2U)
-#define DMIC_CHANEN_EN_CH1_SHIFT (1U)
-#define DMIC_CHANEN_EN_CH1(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH1_SHIFT)) & DMIC_CHANEN_EN_CH1_MASK)
-
-/*! @name IOCFG - I/O Configuration register */
-#define DMIC_IOCFG_CLK_BYPASS0_MASK (0x1U)
-#define DMIC_IOCFG_CLK_BYPASS0_SHIFT (0U)
-#define DMIC_IOCFG_CLK_BYPASS0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS0_SHIFT)) & DMIC_IOCFG_CLK_BYPASS0_MASK)
-#define DMIC_IOCFG_CLK_BYPASS1_MASK (0x2U)
-#define DMIC_IOCFG_CLK_BYPASS1_SHIFT (1U)
-#define DMIC_IOCFG_CLK_BYPASS1(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS1_SHIFT)) & DMIC_IOCFG_CLK_BYPASS1_MASK)
-#define DMIC_IOCFG_STEREO_DATA0_MASK (0x4U)
-#define DMIC_IOCFG_STEREO_DATA0_SHIFT (2U)
-#define DMIC_IOCFG_STEREO_DATA0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_STEREO_DATA0_SHIFT)) & DMIC_IOCFG_STEREO_DATA0_MASK)
-
-/*! @name USE2FS - Use 2FS register */
-#define DMIC_USE2FS_USE2FS_MASK (0x1U)
-#define DMIC_USE2FS_USE2FS_SHIFT (0U)
-#define DMIC_USE2FS_USE2FS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_USE2FS_USE2FS_SHIFT)) & DMIC_USE2FS_USE2FS_MASK)
-
-/*! @name HWVADGAIN - HWVAD input gain register */
-#define DMIC_HWVADGAIN_INPUTGAIN_MASK (0xFU)
-#define DMIC_HWVADGAIN_INPUTGAIN_SHIFT (0U)
-#define DMIC_HWVADGAIN_INPUTGAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADGAIN_INPUTGAIN_SHIFT)) & DMIC_HWVADGAIN_INPUTGAIN_MASK)
-
-/*! @name HWVADHPFS - HWVAD filter control register */
-#define DMIC_HWVADHPFS_HPFS_MASK (0x3U)
-#define DMIC_HWVADHPFS_HPFS_SHIFT (0U)
-#define DMIC_HWVADHPFS_HPFS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADHPFS_HPFS_SHIFT)) & DMIC_HWVADHPFS_HPFS_MASK)
-
-/*! @name HWVADST10 - HWVAD control register */
-#define DMIC_HWVADST10_ST10_MASK (0x1U)
-#define DMIC_HWVADST10_ST10_SHIFT (0U)
-#define DMIC_HWVADST10_ST10(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADST10_ST10_SHIFT)) & DMIC_HWVADST10_ST10_MASK)
-
-/*! @name HWVADRSTT - HWVAD filter reset register */
-#define DMIC_HWVADRSTT_RSTT_MASK (0x1U)
-#define DMIC_HWVADRSTT_RSTT_SHIFT (0U)
-#define DMIC_HWVADRSTT_RSTT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADRSTT_RSTT_SHIFT)) & DMIC_HWVADRSTT_RSTT_MASK)
-
-/*! @name HWVADTHGN - HWVAD noise estimator gain register */
-#define DMIC_HWVADTHGN_THGN_MASK (0xFU)
-#define DMIC_HWVADTHGN_THGN_SHIFT (0U)
-#define DMIC_HWVADTHGN_THGN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGN_THGN_SHIFT)) & DMIC_HWVADTHGN_THGN_MASK)
-
-/*! @name HWVADTHGS - HWVAD signal estimator gain register */
-#define DMIC_HWVADTHGS_THGS_MASK (0xFU)
-#define DMIC_HWVADTHGS_THGS_SHIFT (0U)
-#define DMIC_HWVADTHGS_THGS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGS_THGS_SHIFT)) & DMIC_HWVADTHGS_THGS_MASK)
-
-/*! @name HWVADLOWZ - HWVAD noise envelope estimator register */
-#define DMIC_HWVADLOWZ_LOWZ_MASK (0xFFFFU)
-#define DMIC_HWVADLOWZ_LOWZ_SHIFT (0U)
-#define DMIC_HWVADLOWZ_LOWZ(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADLOWZ_LOWZ_SHIFT)) & DMIC_HWVADLOWZ_LOWZ_MASK)
-
-/*! @name ID - Module Identification register */
-#define DMIC_ID_ID_MASK (0xFFFFFFFFU)
-#define DMIC_ID_ID_SHIFT (0U)
-#define DMIC_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DMIC_ID_ID_SHIFT)) & DMIC_ID_ID_MASK)
-
-
-/*!
- * @}
- */ /* end of group DMIC_Register_Masks */
-
-
-/* DMIC - Peripheral instance base addresses */
-/** Peripheral DMIC0 base address */
-#define DMIC0_BASE (0x40090000u)
-/** Peripheral DMIC0 base pointer */
-#define DMIC0 ((DMIC_Type *)DMIC0_BASE)
-/** Array initializer of DMIC peripheral base addresses */
-#define DMIC_BASE_ADDRS { DMIC0_BASE }
-/** Array initializer of DMIC peripheral base pointers */
-#define DMIC_BASE_PTRS { DMIC0 }
-/** Interrupt vectors for the DMIC peripheral type */
-#define DMIC_IRQS { DMIC0_IRQn }
-#define DMIC_HWVAD_IRQS { HWVAD0_IRQn }
-
-/*!
- * @}
- */ /* end of group DMIC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- EEPROM Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup EEPROM_Peripheral_Access_Layer EEPROM Peripheral Access Layer
- * @{
- */
-
-/** EEPROM - Register Layout Typedef */
-typedef struct {
- __IO uint32_t CMD; /**< EEPROM command register, offset: 0x0 */
- uint8_t RESERVED_0[4];
- __IO uint32_t RWSTATE; /**< EEPROM read wait state register, offset: 0x8 */
- __IO uint32_t AUTOPROG; /**< EEPROM auto programming register, offset: 0xC */
- __IO uint32_t WSTATE; /**< EEPROM wait state register, offset: 0x10 */
- __IO uint32_t CLKDIV; /**< EEPROM clock divider register, offset: 0x14 */
- __IO uint32_t PWRDWN; /**< EEPROM power-down register, offset: 0x18 */
- uint8_t RESERVED_1[4028];
- __O uint32_t INTENCLR; /**< EEPROM interrupt enable clear, offset: 0xFD8 */
- __O uint32_t INTENSET; /**< EEPROM interrupt enable set, offset: 0xFDC */
- __I uint32_t INTSTAT; /**< EEPROM interrupt status, offset: 0xFE0 */
- __I uint32_t INTEN; /**< EEPROM interrupt enable, offset: 0xFE4 */
- __O uint32_t INTSTATCLR; /**< EEPROM interrupt status clear, offset: 0xFE8 */
- __O uint32_t INTSTATSET; /**< EEPROM interrupt status set, offset: 0xFEC */
-} EEPROM_Type;
-
-/* ----------------------------------------------------------------------------
- -- EEPROM Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup EEPROM_Register_Masks EEPROM Register Masks
- * @{
- */
-
-/*! @name CMD - EEPROM command register */
-#define EEPROM_CMD_CMD_MASK (0x7U)
-#define EEPROM_CMD_CMD_SHIFT (0U)
-#define EEPROM_CMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_CMD_CMD_SHIFT)) & EEPROM_CMD_CMD_MASK)
-
-/*! @name RWSTATE - EEPROM read wait state register */
-#define EEPROM_RWSTATE_RPHASE2_MASK (0xFFU)
-#define EEPROM_RWSTATE_RPHASE2_SHIFT (0U)
-#define EEPROM_RWSTATE_RPHASE2(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_RWSTATE_RPHASE2_SHIFT)) & EEPROM_RWSTATE_RPHASE2_MASK)
-#define EEPROM_RWSTATE_RPHASE1_MASK (0xFF00U)
-#define EEPROM_RWSTATE_RPHASE1_SHIFT (8U)
-#define EEPROM_RWSTATE_RPHASE1(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_RWSTATE_RPHASE1_SHIFT)) & EEPROM_RWSTATE_RPHASE1_MASK)
-
-/*! @name AUTOPROG - EEPROM auto programming register */
-#define EEPROM_AUTOPROG_AUTOPROG_MASK (0x3U)
-#define EEPROM_AUTOPROG_AUTOPROG_SHIFT (0U)
-#define EEPROM_AUTOPROG_AUTOPROG(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_AUTOPROG_AUTOPROG_SHIFT)) & EEPROM_AUTOPROG_AUTOPROG_MASK)
-
-/*! @name WSTATE - EEPROM wait state register */
-#define EEPROM_WSTATE_PHASE3_MASK (0xFFU)
-#define EEPROM_WSTATE_PHASE3_SHIFT (0U)
-#define EEPROM_WSTATE_PHASE3(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_WSTATE_PHASE3_SHIFT)) & EEPROM_WSTATE_PHASE3_MASK)
-#define EEPROM_WSTATE_PHASE2_MASK (0xFF00U)
-#define EEPROM_WSTATE_PHASE2_SHIFT (8U)
-#define EEPROM_WSTATE_PHASE2(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_WSTATE_PHASE2_SHIFT)) & EEPROM_WSTATE_PHASE2_MASK)
-#define EEPROM_WSTATE_PHASE1_MASK (0xFF0000U)
-#define EEPROM_WSTATE_PHASE1_SHIFT (16U)
-#define EEPROM_WSTATE_PHASE1(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_WSTATE_PHASE1_SHIFT)) & EEPROM_WSTATE_PHASE1_MASK)
-#define EEPROM_WSTATE_LCK_PARWEP_MASK (0x80000000U)
-#define EEPROM_WSTATE_LCK_PARWEP_SHIFT (31U)
-#define EEPROM_WSTATE_LCK_PARWEP(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_WSTATE_LCK_PARWEP_SHIFT)) & EEPROM_WSTATE_LCK_PARWEP_MASK)
-
-/*! @name CLKDIV - EEPROM clock divider register */
-#define EEPROM_CLKDIV_CLKDIV_MASK (0xFFFFU)
-#define EEPROM_CLKDIV_CLKDIV_SHIFT (0U)
-#define EEPROM_CLKDIV_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_CLKDIV_CLKDIV_SHIFT)) & EEPROM_CLKDIV_CLKDIV_MASK)
-
-/*! @name PWRDWN - EEPROM power-down register */
-#define EEPROM_PWRDWN_PWRDWN_MASK (0x1U)
-#define EEPROM_PWRDWN_PWRDWN_SHIFT (0U)
-#define EEPROM_PWRDWN_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_PWRDWN_PWRDWN_SHIFT)) & EEPROM_PWRDWN_PWRDWN_MASK)
-
-/*! @name INTENCLR - EEPROM interrupt enable clear */
-#define EEPROM_INTENCLR_PROG_CLR_EN_MASK (0x4U)
-#define EEPROM_INTENCLR_PROG_CLR_EN_SHIFT (2U)
-#define EEPROM_INTENCLR_PROG_CLR_EN(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTENCLR_PROG_CLR_EN_SHIFT)) & EEPROM_INTENCLR_PROG_CLR_EN_MASK)
-
-/*! @name INTENSET - EEPROM interrupt enable set */
-#define EEPROM_INTENSET_PROG_SET_EN_MASK (0x4U)
-#define EEPROM_INTENSET_PROG_SET_EN_SHIFT (2U)
-#define EEPROM_INTENSET_PROG_SET_EN(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTENSET_PROG_SET_EN_SHIFT)) & EEPROM_INTENSET_PROG_SET_EN_MASK)
-
-/*! @name INTSTAT - EEPROM interrupt status */
-#define EEPROM_INTSTAT_END_OF_PROG_MASK (0x4U)
-#define EEPROM_INTSTAT_END_OF_PROG_SHIFT (2U)
-#define EEPROM_INTSTAT_END_OF_PROG(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTSTAT_END_OF_PROG_SHIFT)) & EEPROM_INTSTAT_END_OF_PROG_MASK)
-
-/*! @name INTEN - EEPROM interrupt enable */
-#define EEPROM_INTEN_EE_PROG_DONE_MASK (0x4U)
-#define EEPROM_INTEN_EE_PROG_DONE_SHIFT (2U)
-#define EEPROM_INTEN_EE_PROG_DONE(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTEN_EE_PROG_DONE_SHIFT)) & EEPROM_INTEN_EE_PROG_DONE_MASK)
-
-/*! @name INTSTATCLR - EEPROM interrupt status clear */
-#define EEPROM_INTSTATCLR_PROG_CLR_ST_MASK (0x4U)
-#define EEPROM_INTSTATCLR_PROG_CLR_ST_SHIFT (2U)
-#define EEPROM_INTSTATCLR_PROG_CLR_ST(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTSTATCLR_PROG_CLR_ST_SHIFT)) & EEPROM_INTSTATCLR_PROG_CLR_ST_MASK)
-
-/*! @name INTSTATSET - EEPROM interrupt status set */
-#define EEPROM_INTSTATSET_PROG_SET_ST_MASK (0x4U)
-#define EEPROM_INTSTATSET_PROG_SET_ST_SHIFT (2U)
-#define EEPROM_INTSTATSET_PROG_SET_ST(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTSTATSET_PROG_SET_ST_SHIFT)) & EEPROM_INTSTATSET_PROG_SET_ST_MASK)
-
-
-/*!
- * @}
- */ /* end of group EEPROM_Register_Masks */
-
-
-/* EEPROM - Peripheral instance base addresses */
-/** Peripheral EEPROM base address */
-#define EEPROM_BASE (0x40014000u)
-/** Peripheral EEPROM base pointer */
-#define EEPROM ((EEPROM_Type *)EEPROM_BASE)
-/** Array initializer of EEPROM peripheral base addresses */
-#define EEPROM_BASE_ADDRS { EEPROM_BASE }
-/** Array initializer of EEPROM peripheral base pointers */
-#define EEPROM_BASE_PTRS { EEPROM }
-/** Interrupt vectors for the EEPROM peripheral type */
-#define EEPROM_IRQS { EEPROM_IRQn }
-
-/*!
- * @}
- */ /* end of group EEPROM_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- EMC Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup EMC_Peripheral_Access_Layer EMC Peripheral Access Layer
- * @{
- */
-
-/** EMC - Register Layout Typedef */
-typedef struct {
- __IO uint32_t CONTROL; /**< Controls operation of the memory controller, offset: 0x0 */
- __I uint32_t STATUS; /**< Provides EMC status information, offset: 0x4 */
- __IO uint32_t CONFIG; /**< Configures operation of the memory controller, offset: 0x8 */
- uint8_t RESERVED_0[20];
- __IO uint32_t DYNAMICCONTROL; /**< Controls dynamic memory operation, offset: 0x20 */
- __IO uint32_t DYNAMICREFRESH; /**< Configures dynamic memory refresh, offset: 0x24 */
- __IO uint32_t DYNAMICREADCONFIG; /**< Configures dynamic memory read strategy, offset: 0x28 */
- uint8_t RESERVED_1[4];
- __IO uint32_t DYNAMICRP; /**< Precharge command period, offset: 0x30 */
- __IO uint32_t DYNAMICRAS; /**< Active to precharge command period, offset: 0x34 */
- __IO uint32_t DYNAMICSREX; /**< Self-refresh exit time, offset: 0x38 */
- __IO uint32_t DYNAMICAPR; /**< Last-data-out to active command time, offset: 0x3C */
- __IO uint32_t DYNAMICDAL; /**< Data-in to active command time, offset: 0x40 */
- __IO uint32_t DYNAMICWR; /**< Write recovery time, offset: 0x44 */
- __IO uint32_t DYNAMICRC; /**< Selects the active to active command period, offset: 0x48 */
- __IO uint32_t DYNAMICRFC; /**< Selects the auto-refresh period, offset: 0x4C */
- __IO uint32_t DYNAMICXSR; /**< Time for exit self-refresh to active command, offset: 0x50 */
- __IO uint32_t DYNAMICRRD; /**< Latency for active bank A to active bank B, offset: 0x54 */
- __IO uint32_t DYNAMICMRD; /**< Time for load mode register to active command, offset: 0x58 */
- uint8_t RESERVED_2[36];
- __IO uint32_t STATICEXTENDEDWAIT; /**< Time for long static memory read and write transfers, offset: 0x80 */
- uint8_t RESERVED_3[124];
- struct { /* offset: 0x100, array step: 0x20 */
- __IO uint32_t DYNAMICCONFIG; /**< Configuration information for EMC_DYCSx, array offset: 0x100, array step: 0x20 */
- __IO uint32_t DYNAMICRASCAS; /**< RAS and CAS latencies for EMC_DYCSx, array offset: 0x104, array step: 0x20 */
- uint8_t RESERVED_0[24];
- } DYNAMIC[4];
- uint8_t RESERVED_4[128];
- struct { /* offset: 0x200, array step: 0x20 */
- __IO uint32_t STATICCONFIG; /**< Configuration for EMC_CSx, array offset: 0x200, array step: 0x20 */
- __IO uint32_t STATICWAITWEN; /**< Delay from EMC_CSx to write enable, array offset: 0x204, array step: 0x20 */
- __IO uint32_t STATICWAITOEN; /**< Delay from EMC_CSx or address change, whichever is later, to output enable, array offset: 0x208, array step: 0x20 */
- __IO uint32_t STATICWAITRD; /**< Delay from EMC_CSx to a read access, array offset: 0x20C, array step: 0x20 */
- __IO uint32_t STATICWAITPAGE; /**< Delay for asynchronous page mode sequential accesses for EMC_CSx, array offset: 0x210, array step: 0x20 */
- __IO uint32_t STATICWAITWR; /**< Delay from EMC_CSx to a write access, array offset: 0x214, array step: 0x20 */
- __IO uint32_t STATICWAITTURN; /**< Number of bus turnaround cycles EMC_CSx, array offset: 0x218, array step: 0x20 */
- uint8_t RESERVED_0[4];
- } STATIC[4];
-} EMC_Type;
-
-/* ----------------------------------------------------------------------------
- -- EMC Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup EMC_Register_Masks EMC Register Masks
- * @{
- */
-
-/*! @name CONTROL - Controls operation of the memory controller */
-#define EMC_CONTROL_E_MASK (0x1U)
-#define EMC_CONTROL_E_SHIFT (0U)
-#define EMC_CONTROL_E(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_E_SHIFT)) & EMC_CONTROL_E_MASK)
-#define EMC_CONTROL_M_MASK (0x2U)
-#define EMC_CONTROL_M_SHIFT (1U)
-#define EMC_CONTROL_M(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_M_SHIFT)) & EMC_CONTROL_M_MASK)
-#define EMC_CONTROL_L_MASK (0x4U)
-#define EMC_CONTROL_L_SHIFT (2U)
-#define EMC_CONTROL_L(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_L_SHIFT)) & EMC_CONTROL_L_MASK)
-
-/*! @name STATUS - Provides EMC status information */
-#define EMC_STATUS_B_MASK (0x1U)
-#define EMC_STATUS_B_SHIFT (0U)
-#define EMC_STATUS_B(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_B_SHIFT)) & EMC_STATUS_B_MASK)
-#define EMC_STATUS_S_MASK (0x2U)
-#define EMC_STATUS_S_SHIFT (1U)
-#define EMC_STATUS_S(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_S_SHIFT)) & EMC_STATUS_S_MASK)
-#define EMC_STATUS_SA_MASK (0x4U)
-#define EMC_STATUS_SA_SHIFT (2U)
-#define EMC_STATUS_SA(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_SA_SHIFT)) & EMC_STATUS_SA_MASK)
-
-/*! @name CONFIG - Configures operation of the memory controller */
-#define EMC_CONFIG_EM_MASK (0x1U)
-#define EMC_CONFIG_EM_SHIFT (0U)
-#define EMC_CONFIG_EM(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONFIG_EM_SHIFT)) & EMC_CONFIG_EM_MASK)
-#define EMC_CONFIG_CLKR_MASK (0x100U)
-#define EMC_CONFIG_CLKR_SHIFT (8U)
-#define EMC_CONFIG_CLKR(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONFIG_CLKR_SHIFT)) & EMC_CONFIG_CLKR_MASK)
-
-/*! @name DYNAMICCONTROL - Controls dynamic memory operation */
-#define EMC_DYNAMICCONTROL_CE_MASK (0x1U)
-#define EMC_DYNAMICCONTROL_CE_SHIFT (0U)
-#define EMC_DYNAMICCONTROL_CE(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_CE_SHIFT)) & EMC_DYNAMICCONTROL_CE_MASK)
-#define EMC_DYNAMICCONTROL_CS_MASK (0x2U)
-#define EMC_DYNAMICCONTROL_CS_SHIFT (1U)
-#define EMC_DYNAMICCONTROL_CS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_CS_SHIFT)) & EMC_DYNAMICCONTROL_CS_MASK)
-#define EMC_DYNAMICCONTROL_SR_MASK (0x4U)
-#define EMC_DYNAMICCONTROL_SR_SHIFT (2U)
-#define EMC_DYNAMICCONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_SR_SHIFT)) & EMC_DYNAMICCONTROL_SR_MASK)
-#define EMC_DYNAMICCONTROL_MMC_MASK (0x20U)
-#define EMC_DYNAMICCONTROL_MMC_SHIFT (5U)
-#define EMC_DYNAMICCONTROL_MMC(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_MMC_SHIFT)) & EMC_DYNAMICCONTROL_MMC_MASK)
-#define EMC_DYNAMICCONTROL_I_MASK (0x180U)
-#define EMC_DYNAMICCONTROL_I_SHIFT (7U)
-#define EMC_DYNAMICCONTROL_I(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_I_SHIFT)) & EMC_DYNAMICCONTROL_I_MASK)
-
-/*! @name DYNAMICREFRESH - Configures dynamic memory refresh */
-#define EMC_DYNAMICREFRESH_REFRESH_MASK (0x7FFU)
-#define EMC_DYNAMICREFRESH_REFRESH_SHIFT (0U)
-#define EMC_DYNAMICREFRESH_REFRESH(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICREFRESH_REFRESH_SHIFT)) & EMC_DYNAMICREFRESH_REFRESH_MASK)
-
-/*! @name DYNAMICREADCONFIG - Configures dynamic memory read strategy */
-#define EMC_DYNAMICREADCONFIG_RD_MASK (0x3U)
-#define EMC_DYNAMICREADCONFIG_RD_SHIFT (0U)
-#define EMC_DYNAMICREADCONFIG_RD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICREADCONFIG_RD_SHIFT)) & EMC_DYNAMICREADCONFIG_RD_MASK)
-
-/*! @name DYNAMICRP - Precharge command period */
-#define EMC_DYNAMICRP_TRP_MASK (0xFU)
-#define EMC_DYNAMICRP_TRP_SHIFT (0U)
-#define EMC_DYNAMICRP_TRP(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRP_TRP_SHIFT)) & EMC_DYNAMICRP_TRP_MASK)
-
-/*! @name DYNAMICRAS - Active to precharge command period */
-#define EMC_DYNAMICRAS_TRAS_MASK (0xFU)
-#define EMC_DYNAMICRAS_TRAS_SHIFT (0U)
-#define EMC_DYNAMICRAS_TRAS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRAS_TRAS_SHIFT)) & EMC_DYNAMICRAS_TRAS_MASK)
-
-/*! @name DYNAMICSREX - Self-refresh exit time */
-#define EMC_DYNAMICSREX_TSREX_MASK (0xFU)
-#define EMC_DYNAMICSREX_TSREX_SHIFT (0U)
-#define EMC_DYNAMICSREX_TSREX(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICSREX_TSREX_SHIFT)) & EMC_DYNAMICSREX_TSREX_MASK)
-
-/*! @name DYNAMICAPR - Last-data-out to active command time */
-#define EMC_DYNAMICAPR_TAPR_MASK (0xFU)
-#define EMC_DYNAMICAPR_TAPR_SHIFT (0U)
-#define EMC_DYNAMICAPR_TAPR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICAPR_TAPR_SHIFT)) & EMC_DYNAMICAPR_TAPR_MASK)
-
-/*! @name DYNAMICDAL - Data-in to active command time */
-#define EMC_DYNAMICDAL_TDAL_MASK (0xFU)
-#define EMC_DYNAMICDAL_TDAL_SHIFT (0U)
-#define EMC_DYNAMICDAL_TDAL(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICDAL_TDAL_SHIFT)) & EMC_DYNAMICDAL_TDAL_MASK)
-
-/*! @name DYNAMICWR - Write recovery time */
-#define EMC_DYNAMICWR_TWR_MASK (0xFU)
-#define EMC_DYNAMICWR_TWR_SHIFT (0U)
-#define EMC_DYNAMICWR_TWR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICWR_TWR_SHIFT)) & EMC_DYNAMICWR_TWR_MASK)
-
-/*! @name DYNAMICRC - Selects the active to active command period */
-#define EMC_DYNAMICRC_TRC_MASK (0x1FU)
-#define EMC_DYNAMICRC_TRC_SHIFT (0U)
-#define EMC_DYNAMICRC_TRC(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRC_TRC_SHIFT)) & EMC_DYNAMICRC_TRC_MASK)
-
-/*! @name DYNAMICRFC - Selects the auto-refresh period */
-#define EMC_DYNAMICRFC_TRFC_MASK (0x1FU)
-#define EMC_DYNAMICRFC_TRFC_SHIFT (0U)
-#define EMC_DYNAMICRFC_TRFC(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRFC_TRFC_SHIFT)) & EMC_DYNAMICRFC_TRFC_MASK)
-
-/*! @name DYNAMICXSR - Time for exit self-refresh to active command */
-#define EMC_DYNAMICXSR_TXSR_MASK (0x1FU)
-#define EMC_DYNAMICXSR_TXSR_SHIFT (0U)
-#define EMC_DYNAMICXSR_TXSR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICXSR_TXSR_SHIFT)) & EMC_DYNAMICXSR_TXSR_MASK)
-
-/*! @name DYNAMICRRD - Latency for active bank A to active bank B */
-#define EMC_DYNAMICRRD_TRRD_MASK (0xFU)
-#define EMC_DYNAMICRRD_TRRD_SHIFT (0U)
-#define EMC_DYNAMICRRD_TRRD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRRD_TRRD_SHIFT)) & EMC_DYNAMICRRD_TRRD_MASK)
-
-/*! @name DYNAMICMRD - Time for load mode register to active command */
-#define EMC_DYNAMICMRD_TMRD_MASK (0xFU)
-#define EMC_DYNAMICMRD_TMRD_SHIFT (0U)
-#define EMC_DYNAMICMRD_TMRD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICMRD_TMRD_SHIFT)) & EMC_DYNAMICMRD_TMRD_MASK)
-
-/*! @name STATICEXTENDEDWAIT - Time for long static memory read and write transfers */
-#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_MASK (0x3FFU)
-#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_SHIFT (0U)
-#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_SHIFT)) & EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_MASK)
-
-/*! @name DYNAMIC_DYNAMICCONFIG - Configuration information for EMC_DYCSx */
-#define EMC_DYNAMIC_DYNAMICCONFIG_MD_MASK (0x18U)
-#define EMC_DYNAMIC_DYNAMICCONFIG_MD_SHIFT (3U)
-#define EMC_DYNAMIC_DYNAMICCONFIG_MD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_MD_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_MD_MASK)
-#define EMC_DYNAMIC_DYNAMICCONFIG_AM0_MASK (0x1F80U)
-#define EMC_DYNAMIC_DYNAMICCONFIG_AM0_SHIFT (7U)
-#define EMC_DYNAMIC_DYNAMICCONFIG_AM0(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_AM0_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_AM0_MASK)
-#define EMC_DYNAMIC_DYNAMICCONFIG_AM1_MASK (0x4000U)
-#define EMC_DYNAMIC_DYNAMICCONFIG_AM1_SHIFT (14U)
-#define EMC_DYNAMIC_DYNAMICCONFIG_AM1(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_AM1_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_AM1_MASK)
-#define EMC_DYNAMIC_DYNAMICCONFIG_B_MASK (0x80000U)
-#define EMC_DYNAMIC_DYNAMICCONFIG_B_SHIFT (19U)
-#define EMC_DYNAMIC_DYNAMICCONFIG_B(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_B_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_B_MASK)
-#define EMC_DYNAMIC_DYNAMICCONFIG_P_MASK (0x100000U)
-#define EMC_DYNAMIC_DYNAMICCONFIG_P_SHIFT (20U)
-#define EMC_DYNAMIC_DYNAMICCONFIG_P(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_P_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_P_MASK)
-
-/* The count of EMC_DYNAMIC_DYNAMICCONFIG */
-#define EMC_DYNAMIC_DYNAMICCONFIG_COUNT (4U)
-
-/*! @name DYNAMIC_DYNAMICRASCAS - RAS and CAS latencies for EMC_DYCSx */
-#define EMC_DYNAMIC_DYNAMICRASCAS_RAS_MASK (0x3U)
-#define EMC_DYNAMIC_DYNAMICRASCAS_RAS_SHIFT (0U)
-#define EMC_DYNAMIC_DYNAMICRASCAS_RAS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICRASCAS_RAS_SHIFT)) & EMC_DYNAMIC_DYNAMICRASCAS_RAS_MASK)
-#define EMC_DYNAMIC_DYNAMICRASCAS_CAS_MASK (0x300U)
-#define EMC_DYNAMIC_DYNAMICRASCAS_CAS_SHIFT (8U)
-#define EMC_DYNAMIC_DYNAMICRASCAS_CAS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICRASCAS_CAS_SHIFT)) & EMC_DYNAMIC_DYNAMICRASCAS_CAS_MASK)
-
-/* The count of EMC_DYNAMIC_DYNAMICRASCAS */
-#define EMC_DYNAMIC_DYNAMICRASCAS_COUNT (4U)
-
-/*! @name STATIC_STATICCONFIG - Configuration for EMC_CSx */
-#define EMC_STATIC_STATICCONFIG_MW_MASK (0x3U)
-#define EMC_STATIC_STATICCONFIG_MW_SHIFT (0U)
-#define EMC_STATIC_STATICCONFIG_MW(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_MW_SHIFT)) & EMC_STATIC_STATICCONFIG_MW_MASK)
-#define EMC_STATIC_STATICCONFIG_PM_MASK (0x8U)
-#define EMC_STATIC_STATICCONFIG_PM_SHIFT (3U)
-#define EMC_STATIC_STATICCONFIG_PM(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PM_SHIFT)) & EMC_STATIC_STATICCONFIG_PM_MASK)
-#define EMC_STATIC_STATICCONFIG_PC_MASK (0x40U)
-#define EMC_STATIC_STATICCONFIG_PC_SHIFT (6U)
-#define EMC_STATIC_STATICCONFIG_PC(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PC_SHIFT)) & EMC_STATIC_STATICCONFIG_PC_MASK)
-#define EMC_STATIC_STATICCONFIG_PB_MASK (0x80U)
-#define EMC_STATIC_STATICCONFIG_PB_SHIFT (7U)
-#define EMC_STATIC_STATICCONFIG_PB(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PB_SHIFT)) & EMC_STATIC_STATICCONFIG_PB_MASK)
-#define EMC_STATIC_STATICCONFIG_EW_MASK (0x100U)
-#define EMC_STATIC_STATICCONFIG_EW_SHIFT (8U)
-#define EMC_STATIC_STATICCONFIG_EW(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_EW_SHIFT)) & EMC_STATIC_STATICCONFIG_EW_MASK)
-#define EMC_STATIC_STATICCONFIG_B_MASK (0x80000U)
-#define EMC_STATIC_STATICCONFIG_B_SHIFT (19U)
-#define EMC_STATIC_STATICCONFIG_B(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_B_SHIFT)) & EMC_STATIC_STATICCONFIG_B_MASK)
-#define EMC_STATIC_STATICCONFIG_P_MASK (0x100000U)
-#define EMC_STATIC_STATICCONFIG_P_SHIFT (20U)
-#define EMC_STATIC_STATICCONFIG_P(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_P_SHIFT)) & EMC_STATIC_STATICCONFIG_P_MASK)
-
-/* The count of EMC_STATIC_STATICCONFIG */
-#define EMC_STATIC_STATICCONFIG_COUNT (4U)
-
-/*! @name STATIC_STATICWAITWEN - Delay from EMC_CSx to write enable */
-#define EMC_STATIC_STATICWAITWEN_WAITWEN_MASK (0xFU)
-#define EMC_STATIC_STATICWAITWEN_WAITWEN_SHIFT (0U)
-#define EMC_STATIC_STATICWAITWEN_WAITWEN(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITWEN_WAITWEN_SHIFT)) & EMC_STATIC_STATICWAITWEN_WAITWEN_MASK)
-
-/* The count of EMC_STATIC_STATICWAITWEN */
-#define EMC_STATIC_STATICWAITWEN_COUNT (4U)
-
-/*! @name STATIC_STATICWAITOEN - Delay from EMC_CSx or address change, whichever is later, to output enable */
-#define EMC_STATIC_STATICWAITOEN_WAITOEN_MASK (0xFU)
-#define EMC_STATIC_STATICWAITOEN_WAITOEN_SHIFT (0U)
-#define EMC_STATIC_STATICWAITOEN_WAITOEN(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITOEN_WAITOEN_SHIFT)) & EMC_STATIC_STATICWAITOEN_WAITOEN_MASK)
-
-/* The count of EMC_STATIC_STATICWAITOEN */
-#define EMC_STATIC_STATICWAITOEN_COUNT (4U)
-
-/*! @name STATIC_STATICWAITRD - Delay from EMC_CSx to a read access */
-#define EMC_STATIC_STATICWAITRD_WAITRD_MASK (0x1FU)
-#define EMC_STATIC_STATICWAITRD_WAITRD_SHIFT (0U)
-#define EMC_STATIC_STATICWAITRD_WAITRD(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITRD_WAITRD_SHIFT)) & EMC_STATIC_STATICWAITRD_WAITRD_MASK)
-
-/* The count of EMC_STATIC_STATICWAITRD */
-#define EMC_STATIC_STATICWAITRD_COUNT (4U)
-
-/*! @name STATIC_STATICWAITPAGE - Delay for asynchronous page mode sequential accesses for EMC_CSx */
-#define EMC_STATIC_STATICWAITPAGE_WAITPAGE_MASK (0x1FU)
-#define EMC_STATIC_STATICWAITPAGE_WAITPAGE_SHIFT (0U)
-#define EMC_STATIC_STATICWAITPAGE_WAITPAGE(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITPAGE_WAITPAGE_SHIFT)) & EMC_STATIC_STATICWAITPAGE_WAITPAGE_MASK)
-
-/* The count of EMC_STATIC_STATICWAITPAGE */
-#define EMC_STATIC_STATICWAITPAGE_COUNT (4U)
-
-/*! @name STATIC_STATICWAITWR - Delay from EMC_CSx to a write access */
-#define EMC_STATIC_STATICWAITWR_WAITWR_MASK (0x1FU)
-#define EMC_STATIC_STATICWAITWR_WAITWR_SHIFT (0U)
-#define EMC_STATIC_STATICWAITWR_WAITWR(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITWR_WAITWR_SHIFT)) & EMC_STATIC_STATICWAITWR_WAITWR_MASK)
-
-/* The count of EMC_STATIC_STATICWAITWR */
-#define EMC_STATIC_STATICWAITWR_COUNT (4U)
-
-/*! @name STATIC_STATICWAITTURN - Number of bus turnaround cycles EMC_CSx */
-#define EMC_STATIC_STATICWAITTURN_WAITTURN_MASK (0xFU)
-#define EMC_STATIC_STATICWAITTURN_WAITTURN_SHIFT (0U)
-#define EMC_STATIC_STATICWAITTURN_WAITTURN(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITTURN_WAITTURN_SHIFT)) & EMC_STATIC_STATICWAITTURN_WAITTURN_MASK)
-
-/* The count of EMC_STATIC_STATICWAITTURN */
-#define EMC_STATIC_STATICWAITTURN_COUNT (4U)
-
-
-/*!
- * @}
- */ /* end of group EMC_Register_Masks */
-
-
-/* EMC - Peripheral instance base addresses */
-/** Peripheral EMC base address */
-#define EMC_BASE (0x40081000u)
-/** Peripheral EMC base pointer */
-#define EMC ((EMC_Type *)EMC_BASE)
-/** Array initializer of EMC peripheral base addresses */
-#define EMC_BASE_ADDRS { EMC_BASE }
-/** Array initializer of EMC peripheral base pointers */
-#define EMC_BASE_PTRS { EMC }
-
-/*!
- * @}
- */ /* end of group EMC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- ENET Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
- * @{
- */
-
-/** ENET - Register Layout Typedef */
-typedef struct {
- __IO uint32_t MAC_CONFIG; /**< MAC configuration register, offset: 0x0 */
- __IO uint32_t MAC_EXT_CONFIG; /**< , offset: 0x4 */
- __IO uint32_t MAC_FRAME_FILTER; /**< MAC frame filter register, offset: 0x8 */
- __IO uint32_t MAC_WD_TIMEROUT; /**< MAC watchdog Timeout register, offset: 0xC */
- uint8_t RESERVED_0[64];
- __IO uint32_t MAC_VLAN_TAG; /**< MAC vlan tag register, offset: 0x50 */
- uint8_t RESERVED_1[28];
- __IO uint32_t MAC_TX_FLOW_CTRL_Q[2]; /**< Transmit flow control register, array offset: 0x70, array step: 0x4 */
- uint8_t RESERVED_2[24];
- __IO uint32_t MAC_RX_FLOW_CTRL; /**< Receive flow control register, offset: 0x90 */
- uint8_t RESERVED_3[4];
- __IO uint32_t MAC_TXQ_PRIO_MAP; /**< , offset: 0x98 */
- uint8_t RESERVED_4[4];
- __IO uint32_t MAC_RXQ_CTRL[3]; /**< Receive Queue Control 0 register 0x0000, array offset: 0xA0, array step: 0x4 */
- uint8_t RESERVED_5[4];
- __I uint32_t MAC_INTR_STAT; /**< Interrupt status register 0x0000, offset: 0xB0 */
- __IO uint32_t MAC_INTR_EN; /**< Interrupt enable register 0x0000, offset: 0xB4 */
- __I uint32_t MAC_RXTX_STAT; /**< Receive Transmit Status register, offset: 0xB8 */
- uint8_t RESERVED_6[4];
- __IO uint32_t MAC_PMT_CRTL_STAT; /**< , offset: 0xC0 */
- __IO uint32_t MAC_RWAKE_FRFLT; /**< Remote wake-up frame filter, offset: 0xC4 */
- uint8_t RESERVED_7[8];
- __IO uint32_t MAC_LPI_CTRL_STAT; /**< LPI Control and Status Register, offset: 0xD0 */
- __IO uint32_t MAC_LPI_TIMER_CTRL; /**< LPI Timers Control register, offset: 0xD4 */
- __IO uint32_t MAC_LPI_ENTR_TIMR; /**< LPI entry Timer register, offset: 0xD8 */
- __IO uint32_t MAC_1US_TIC_COUNTR; /**< , offset: 0xDC */
- uint8_t RESERVED_8[48];
- __IO uint32_t MAC_VERSION; /**< MAC version register, offset: 0x110 */
- __I uint32_t MAC_DBG; /**< MAC debug register, offset: 0x114 */
- uint8_t RESERVED_9[4];
- __IO uint32_t MAC_HW_FEAT[3]; /**< MAC hardware feature register 0x0201, array offset: 0x11C, array step: 0x4 */
- uint8_t RESERVED_10[216];
- __IO uint32_t MAC_MDIO_ADDR; /**< MIDO address Register, offset: 0x200 */
- __IO uint32_t MAC_MDIO_DATA; /**< MDIO Data register, offset: 0x204 */
- uint8_t RESERVED_11[248];
- __IO uint32_t MAC_ADDR_HIGH; /**< MAC address0 high register, offset: 0x300 */
- __IO uint32_t MAC_ADDR_LOW; /**< MAC address0 low register, offset: 0x304 */
- uint8_t RESERVED_12[2040];
- __IO uint32_t MAC_TIMESTAMP_CTRL; /**< Time stamp control register, offset: 0xB00 */
- __IO uint32_t MAC_SUB_SCND_INCR; /**< Sub-second increment register, offset: 0xB04 */
- __I uint32_t MAC_SYS_TIME_SCND; /**< System time seconds register, offset: 0xB08 */
- __I uint32_t MAC_SYS_TIME_NSCND; /**< System time nanoseconds register, offset: 0xB0C */
- __IO uint32_t MAC_SYS_TIME_SCND_UPD; /**< , offset: 0xB10 */
- __IO uint32_t MAC_SYS_TIME_NSCND_UPD; /**< , offset: 0xB14 */
- __IO uint32_t MAC_SYS_TIMESTMP_ADDEND; /**< Time stamp addend register, offset: 0xB18 */
- __IO uint32_t MAC_SYS_TIME_HWORD_SCND; /**< , offset: 0xB1C */
- __I uint32_t MAC_SYS_TIMESTMP_STAT; /**< Time stamp status register, offset: 0xB20 */
- uint8_t RESERVED_13[12];
- __I uint32_t MAC_TX_TIMESTAMP_STATUS_NANOSECONDS; /**< Tx timestamp status nanoseconds, offset: 0xB30 */
- __I uint32_t MAC_TX_TIMESTAMP_STATUS_SECONDS; /**< Tx timestamp status seconds, offset: 0xB34 */
- uint8_t RESERVED_14[32];
- __IO uint32_t MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND; /**< Timestamp ingress correction, offset: 0xB58 */
- __IO uint32_t MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND; /**< Timestamp egress correction, offset: 0xB5C */
- uint8_t RESERVED_15[160];
- __IO uint32_t MTL_OP_MODE; /**< MTL Operation Mode Register, offset: 0xC00 */
- uint8_t RESERVED_16[28];
- __I uint32_t MTL_INTR_STAT; /**< MTL Interrupt Status register, offset: 0xC20 */
- uint8_t RESERVED_17[12];
- __IO uint32_t MTL_RXQ_DMA_MAP; /**< MTL Receive Queue and DMA Channel Mapping register, offset: 0xC30 */
- uint8_t RESERVED_18[204];
- struct { /* offset: 0xD00, array step: 0x40 */
- __IO uint32_t MTL_TXQX_OP_MODE; /**< MTL TxQx Operation Mode register, array offset: 0xD00, array step: 0x40 */
- __I uint32_t MTL_TXQX_UNDRFLW; /**< MTL TxQx Underflow register, array offset: 0xD04, array step: 0x40 */
- __I uint32_t MTL_TXQX_DBG; /**< MTL TxQx Debug register, array offset: 0xD08, array step: 0x40 */
- uint8_t RESERVED_0[4];
- __IO uint32_t MTL_TXQX_ETS_CTRL; /**< MTL TxQx ETS control register, only TxQ1 support, array offset: 0xD10, array step: 0x40 */
- __IO uint32_t MTL_TXQX_ETS_STAT; /**< MTL TxQx ETS Status register, array offset: 0xD14, array step: 0x40 */
- __IO uint32_t MTL_TXQX_QNTM_WGHT; /**< , array offset: 0xD18, array step: 0x40 */
- __IO uint32_t MTL_TXQX_SNDSLP_CRDT; /**< MTL TxQx SendSlopCredit register, only TxQ1 support, array offset: 0xD1C, array step: 0x40 */
- __IO uint32_t MTL_TXQX_HI_CRDT; /**< MTL TxQx hiCredit register, only TxQ1 support, array offset: 0xD20, array step: 0x40 */
- __IO uint32_t MTL_TXQX_LO_CRDT; /**< MTL TxQx loCredit register, only TxQ1 support, array offset: 0xD24, array step: 0x40 */
- uint8_t RESERVED_1[4];
- __IO uint32_t MTL_TXQX_INTCTRL_STAT; /**< , array offset: 0xD2C, array step: 0x40 */
- __IO uint32_t MTL_RXQX_OP_MODE; /**< MTL RxQx Operation Mode register, array offset: 0xD30, array step: 0x40 */
- __IO uint32_t MTL_RXQX_MISSPKT_OVRFLW_CNT; /**< MTL RxQx Missed Packet Overflow Counter register, array offset: 0xD34, array step: 0x40 */
- __IO uint32_t MTL_RXQX_DBG; /**< MTL RxQx Debug register, array offset: 0xD38, array step: 0x40 */
- __IO uint32_t MTL_RXQX_CTRL; /**< MTL RxQx Control register, array offset: 0xD3C, array step: 0x40 */
- } MTL_QUEUE[2];
- uint8_t RESERVED_19[640];
- __IO uint32_t DMA_MODE; /**< DMA mode register, offset: 0x1000 */
- __IO uint32_t DMA_SYSBUS_MODE; /**< DMA System Bus mode, offset: 0x1004 */
- __IO uint32_t DMA_INTR_STAT; /**< DMA Interrupt status, offset: 0x1008 */
- __IO uint32_t DMA_DBG_STAT; /**< DMA Debug Status, offset: 0x100C */
- uint8_t RESERVED_20[240];
- struct { /* offset: 0x1100, array step: 0x80 */
- __IO uint32_t DMA_CHX_CTRL; /**< DMA Channelx Control, array offset: 0x1100, array step: 0x80 */
- __IO uint32_t DMA_CHX_TX_CTRL; /**< DMA Channelx Transmit Control, array offset: 0x1104, array step: 0x80 */
- __IO uint32_t DMA_CHX_RX_CTRL; /**< DMA Channelx Receive Control, array offset: 0x1108, array step: 0x80 */
- uint8_t RESERVED_0[8];
- __IO uint32_t DMA_CHX_TXDESC_LIST_ADDR; /**< , array offset: 0x1114, array step: 0x80 */
- uint8_t RESERVED_1[4];
- __IO uint32_t DMA_CHX_RXDESC_LIST_ADDR; /**< , array offset: 0x111C, array step: 0x80 */
- __IO uint32_t DMA_CHX_TXDESC_TAIL_PTR; /**< , array offset: 0x1120, array step: 0x80 */
- uint8_t RESERVED_2[4];
- __IO uint32_t DMA_CHX_RXDESC_TAIL_PTR; /**< , array offset: 0x1128, array step: 0x80 */
- __IO uint32_t DMA_CHX_TXDESC_RING_LENGTH; /**< , array offset: 0x112C, array step: 0x80 */
- __IO uint32_t DMA_CHX_RXDESC_RING_LENGTH; /**< Channelx Rx descriptor Ring Length, array offset: 0x1130, array step: 0x80 */
- __IO uint32_t DMA_CHX_INT_EN; /**< Channelx Interrupt Enable, array offset: 0x1134, array step: 0x80 */
- __IO uint32_t DMA_CHX_RX_INT_WDTIMER; /**< Receive Interrupt Watchdog Timer, array offset: 0x1138, array step: 0x80 */
- __IO uint32_t DMA_CHX_SLOT_FUNC_CTRL_STAT; /**< Slot Function Control and Status, array offset: 0x113C, array step: 0x80 */
- uint8_t RESERVED_3[4];
- __I uint32_t DMA_CHX_CUR_HST_TXDESC; /**< Channelx Current Host Transmit descriptor, array offset: 0x1144, array step: 0x80 */
- uint8_t RESERVED_4[4];
- __I uint32_t DMA_CHX_CUR_HST_RXDESC; /**< , array offset: 0x114C, array step: 0x80 */
- uint8_t RESERVED_5[4];
- __I uint32_t DMA_CHX_CUR_HST_TXBUF; /**< , array offset: 0x1154, array step: 0x80 */
- uint8_t RESERVED_6[4];
- __I uint32_t DMA_CHX_CUR_HST_RXBUF; /**< Channelx Current Application Receive Buffer Address, array offset: 0x115C, array step: 0x80 */
- __IO uint32_t DMA_CHX_STAT; /**< Channelx DMA status register, array offset: 0x1160, array step: 0x80 */
- uint8_t RESERVED_7[28];
- } DMA_CH[2];
-} ENET_Type;
-
-/* ----------------------------------------------------------------------------
- -- ENET Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup ENET_Register_Masks ENET Register Masks
- * @{
- */
-
-/*! @name MAC_CONFIG - MAC configuration register */
-#define ENET_MAC_CONFIG_RE_MASK (0x1U)
-#define ENET_MAC_CONFIG_RE_SHIFT (0U)
-#define ENET_MAC_CONFIG_RE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_RE_SHIFT)) & ENET_MAC_CONFIG_RE_MASK)
-#define ENET_MAC_CONFIG_TE_MASK (0x2U)
-#define ENET_MAC_CONFIG_TE_SHIFT (1U)
-#define ENET_MAC_CONFIG_TE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_TE_SHIFT)) & ENET_MAC_CONFIG_TE_MASK)
-#define ENET_MAC_CONFIG_PRELEN_MASK (0xCU)
-#define ENET_MAC_CONFIG_PRELEN_SHIFT (2U)
-#define ENET_MAC_CONFIG_PRELEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_PRELEN_SHIFT)) & ENET_MAC_CONFIG_PRELEN_MASK)
-#define ENET_MAC_CONFIG_DC_MASK (0x10U)
-#define ENET_MAC_CONFIG_DC_SHIFT (4U)
-#define ENET_MAC_CONFIG_DC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DC_SHIFT)) & ENET_MAC_CONFIG_DC_MASK)
-#define ENET_MAC_CONFIG_BL_MASK (0x60U)
-#define ENET_MAC_CONFIG_BL_SHIFT (5U)
-#define ENET_MAC_CONFIG_BL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_BL_SHIFT)) & ENET_MAC_CONFIG_BL_MASK)
-#define ENET_MAC_CONFIG_DR_MASK (0x100U)
-#define ENET_MAC_CONFIG_DR_SHIFT (8U)
-#define ENET_MAC_CONFIG_DR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DR_SHIFT)) & ENET_MAC_CONFIG_DR_MASK)
-#define ENET_MAC_CONFIG_DCRS_MASK (0x200U)
-#define ENET_MAC_CONFIG_DCRS_SHIFT (9U)
-#define ENET_MAC_CONFIG_DCRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DCRS_SHIFT)) & ENET_MAC_CONFIG_DCRS_MASK)
-#define ENET_MAC_CONFIG_DO_MASK (0x400U)
-#define ENET_MAC_CONFIG_DO_SHIFT (10U)
-#define ENET_MAC_CONFIG_DO(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DO_SHIFT)) & ENET_MAC_CONFIG_DO_MASK)
-#define ENET_MAC_CONFIG_ECRSFD_MASK (0x800U)
-#define ENET_MAC_CONFIG_ECRSFD_SHIFT (11U)
-#define ENET_MAC_CONFIG_ECRSFD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_ECRSFD_SHIFT)) & ENET_MAC_CONFIG_ECRSFD_MASK)
-#define ENET_MAC_CONFIG_LM_MASK (0x1000U)
-#define ENET_MAC_CONFIG_LM_SHIFT (12U)
-#define ENET_MAC_CONFIG_LM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_LM_SHIFT)) & ENET_MAC_CONFIG_LM_MASK)
-#define ENET_MAC_CONFIG_DM_MASK (0x2000U)
-#define ENET_MAC_CONFIG_DM_SHIFT (13U)
-#define ENET_MAC_CONFIG_DM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DM_SHIFT)) & ENET_MAC_CONFIG_DM_MASK)
-#define ENET_MAC_CONFIG_FES_MASK (0x4000U)
-#define ENET_MAC_CONFIG_FES_SHIFT (14U)
-#define ENET_MAC_CONFIG_FES(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_FES_SHIFT)) & ENET_MAC_CONFIG_FES_MASK)
-#define ENET_MAC_CONFIG_PS_MASK (0x8000U)
-#define ENET_MAC_CONFIG_PS_SHIFT (15U)
-#define ENET_MAC_CONFIG_PS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_PS_SHIFT)) & ENET_MAC_CONFIG_PS_MASK)
-#define ENET_MAC_CONFIG_JE_MASK (0x10000U)
-#define ENET_MAC_CONFIG_JE_SHIFT (16U)
-#define ENET_MAC_CONFIG_JE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_JE_SHIFT)) & ENET_MAC_CONFIG_JE_MASK)
-#define ENET_MAC_CONFIG_JD_MASK (0x20000U)
-#define ENET_MAC_CONFIG_JD_SHIFT (17U)
-#define ENET_MAC_CONFIG_JD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_JD_SHIFT)) & ENET_MAC_CONFIG_JD_MASK)
-#define ENET_MAC_CONFIG_BE_MASK (0x40000U)
-#define ENET_MAC_CONFIG_BE_SHIFT (18U)
-#define ENET_MAC_CONFIG_BE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_BE_SHIFT)) & ENET_MAC_CONFIG_BE_MASK)
-#define ENET_MAC_CONFIG_WD_MASK (0x80000U)
-#define ENET_MAC_CONFIG_WD_SHIFT (19U)
-#define ENET_MAC_CONFIG_WD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_WD_SHIFT)) & ENET_MAC_CONFIG_WD_MASK)
-#define ENET_MAC_CONFIG_ACS_MASK (0x100000U)
-#define ENET_MAC_CONFIG_ACS_SHIFT (20U)
-#define ENET_MAC_CONFIG_ACS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_ACS_SHIFT)) & ENET_MAC_CONFIG_ACS_MASK)
-#define ENET_MAC_CONFIG_CST_MASK (0x200000U)
-#define ENET_MAC_CONFIG_CST_SHIFT (21U)
-#define ENET_MAC_CONFIG_CST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_CST_SHIFT)) & ENET_MAC_CONFIG_CST_MASK)
-#define ENET_MAC_CONFIG_S2KP_MASK (0x400000U)
-#define ENET_MAC_CONFIG_S2KP_SHIFT (22U)
-#define ENET_MAC_CONFIG_S2KP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_S2KP_SHIFT)) & ENET_MAC_CONFIG_S2KP_MASK)
-#define ENET_MAC_CONFIG_GPSLCE_MASK (0x800000U)
-#define ENET_MAC_CONFIG_GPSLCE_SHIFT (23U)
-#define ENET_MAC_CONFIG_GPSLCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_GPSLCE_SHIFT)) & ENET_MAC_CONFIG_GPSLCE_MASK)
-#define ENET_MAC_CONFIG_IPG_MASK (0x7000000U)
-#define ENET_MAC_CONFIG_IPG_SHIFT (24U)
-#define ENET_MAC_CONFIG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_IPG_SHIFT)) & ENET_MAC_CONFIG_IPG_MASK)
-#define ENET_MAC_CONFIG_IPC_MASK (0x8000000U)
-#define ENET_MAC_CONFIG_IPC_SHIFT (27U)
-#define ENET_MAC_CONFIG_IPC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_IPC_SHIFT)) & ENET_MAC_CONFIG_IPC_MASK)
-
-/*! @name MAC_EXT_CONFIG - */
-#define ENET_MAC_EXT_CONFIG_GPSL_MASK (0x3FFFU)
-#define ENET_MAC_EXT_CONFIG_GPSL_SHIFT (0U)
-#define ENET_MAC_EXT_CONFIG_GPSL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_GPSL_SHIFT)) & ENET_MAC_EXT_CONFIG_GPSL_MASK)
-#define ENET_MAC_EXT_CONFIG_DCRCC_MASK (0x10000U)
-#define ENET_MAC_EXT_CONFIG_DCRCC_SHIFT (16U)
-#define ENET_MAC_EXT_CONFIG_DCRCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_DCRCC_SHIFT)) & ENET_MAC_EXT_CONFIG_DCRCC_MASK)
-#define ENET_MAC_EXT_CONFIG_SPEN_MASK (0x20000U)
-#define ENET_MAC_EXT_CONFIG_SPEN_SHIFT (17U)
-#define ENET_MAC_EXT_CONFIG_SPEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_SPEN_SHIFT)) & ENET_MAC_EXT_CONFIG_SPEN_MASK)
-#define ENET_MAC_EXT_CONFIG_USP_MASK (0x40000U)
-#define ENET_MAC_EXT_CONFIG_USP_SHIFT (18U)
-#define ENET_MAC_EXT_CONFIG_USP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_USP_SHIFT)) & ENET_MAC_EXT_CONFIG_USP_MASK)
-
-/*! @name MAC_FRAME_FILTER - MAC frame filter register */
-#define ENET_MAC_FRAME_FILTER_PR_MASK (0x1U)
-#define ENET_MAC_FRAME_FILTER_PR_SHIFT (0U)
-#define ENET_MAC_FRAME_FILTER_PR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PR_SHIFT)) & ENET_MAC_FRAME_FILTER_PR_MASK)
-#define ENET_MAC_FRAME_FILTER_DAIF_MASK (0x8U)
-#define ENET_MAC_FRAME_FILTER_DAIF_SHIFT (3U)
-#define ENET_MAC_FRAME_FILTER_DAIF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_DAIF_SHIFT)) & ENET_MAC_FRAME_FILTER_DAIF_MASK)
-#define ENET_MAC_FRAME_FILTER_PM_MASK (0x10U)
-#define ENET_MAC_FRAME_FILTER_PM_SHIFT (4U)
-#define ENET_MAC_FRAME_FILTER_PM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PM_SHIFT)) & ENET_MAC_FRAME_FILTER_PM_MASK)
-#define ENET_MAC_FRAME_FILTER_DBF_MASK (0x20U)
-#define ENET_MAC_FRAME_FILTER_DBF_SHIFT (5U)
-#define ENET_MAC_FRAME_FILTER_DBF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_DBF_SHIFT)) & ENET_MAC_FRAME_FILTER_DBF_MASK)
-#define ENET_MAC_FRAME_FILTER_PCF_MASK (0xC0U)
-#define ENET_MAC_FRAME_FILTER_PCF_SHIFT (6U)
-#define ENET_MAC_FRAME_FILTER_PCF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PCF_SHIFT)) & ENET_MAC_FRAME_FILTER_PCF_MASK)
-#define ENET_MAC_FRAME_FILTER_SAIF_MASK (0x100U)
-#define ENET_MAC_FRAME_FILTER_SAIF_SHIFT (8U)
-#define ENET_MAC_FRAME_FILTER_SAIF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_SAIF_SHIFT)) & ENET_MAC_FRAME_FILTER_SAIF_MASK)
-#define ENET_MAC_FRAME_FILTER_SAF_MASK (0x200U)
-#define ENET_MAC_FRAME_FILTER_SAF_SHIFT (9U)
-#define ENET_MAC_FRAME_FILTER_SAF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_SAF_SHIFT)) & ENET_MAC_FRAME_FILTER_SAF_MASK)
-#define ENET_MAC_FRAME_FILTER_RA_MASK (0x80000000U)
-#define ENET_MAC_FRAME_FILTER_RA_SHIFT (31U)
-#define ENET_MAC_FRAME_FILTER_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_RA_SHIFT)) & ENET_MAC_FRAME_FILTER_RA_MASK)
-
-/*! @name MAC_WD_TIMEROUT - MAC watchdog Timeout register */
-#define ENET_MAC_WD_TIMEROUT_WTO_MASK (0xFU)
-#define ENET_MAC_WD_TIMEROUT_WTO_SHIFT (0U)
-#define ENET_MAC_WD_TIMEROUT_WTO(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_WD_TIMEROUT_WTO_SHIFT)) & ENET_MAC_WD_TIMEROUT_WTO_MASK)
-#define ENET_MAC_WD_TIMEROUT_PWE_MASK (0x100U)
-#define ENET_MAC_WD_TIMEROUT_PWE_SHIFT (8U)
-#define ENET_MAC_WD_TIMEROUT_PWE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_WD_TIMEROUT_PWE_SHIFT)) & ENET_MAC_WD_TIMEROUT_PWE_MASK)
-
-/*! @name MAC_VLAN_TAG - MAC vlan tag register */
-#define ENET_MAC_VLAN_TAG_VL_MASK (0xFFFFU)
-#define ENET_MAC_VLAN_TAG_VL_SHIFT (0U)
-#define ENET_MAC_VLAN_TAG_VL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VL_SHIFT)) & ENET_MAC_VLAN_TAG_VL_MASK)
-#define ENET_MAC_VLAN_TAG_ETV_MASK (0x10000U)
-#define ENET_MAC_VLAN_TAG_ETV_SHIFT (16U)
-#define ENET_MAC_VLAN_TAG_ETV(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ETV_SHIFT)) & ENET_MAC_VLAN_TAG_ETV_MASK)
-#define ENET_MAC_VLAN_TAG_VTIM_MASK (0x20000U)
-#define ENET_MAC_VLAN_TAG_VTIM_SHIFT (17U)
-#define ENET_MAC_VLAN_TAG_VTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VTIM_SHIFT)) & ENET_MAC_VLAN_TAG_VTIM_MASK)
-#define ENET_MAC_VLAN_TAG_ESVL_MASK (0x40000U)
-#define ENET_MAC_VLAN_TAG_ESVL_SHIFT (18U)
-#define ENET_MAC_VLAN_TAG_ESVL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ESVL_SHIFT)) & ENET_MAC_VLAN_TAG_ESVL_MASK)
-#define ENET_MAC_VLAN_TAG_ERSVLM_MASK (0x80000U)
-#define ENET_MAC_VLAN_TAG_ERSVLM_SHIFT (19U)
-#define ENET_MAC_VLAN_TAG_ERSVLM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ERSVLM_SHIFT)) & ENET_MAC_VLAN_TAG_ERSVLM_MASK)
-#define ENET_MAC_VLAN_TAG_DOVLTC_MASK (0x100000U)
-#define ENET_MAC_VLAN_TAG_DOVLTC_SHIFT (20U)
-#define ENET_MAC_VLAN_TAG_DOVLTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_DOVLTC_SHIFT)) & ENET_MAC_VLAN_TAG_DOVLTC_MASK)
-#define ENET_MAC_VLAN_TAG_EVLS_MASK (0x600000U)
-#define ENET_MAC_VLAN_TAG_EVLS_SHIFT (21U)
-#define ENET_MAC_VLAN_TAG_EVLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EVLS_SHIFT)) & ENET_MAC_VLAN_TAG_EVLS_MASK)
-#define ENET_MAC_VLAN_TAG_EVLRXS_MASK (0x1000000U)
-#define ENET_MAC_VLAN_TAG_EVLRXS_SHIFT (24U)
-#define ENET_MAC_VLAN_TAG_EVLRXS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EVLRXS_SHIFT)) & ENET_MAC_VLAN_TAG_EVLRXS_MASK)
-#define ENET_MAC_VLAN_TAG_VTHM_MASK (0x2000000U)
-#define ENET_MAC_VLAN_TAG_VTHM_SHIFT (25U)
-#define ENET_MAC_VLAN_TAG_VTHM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VTHM_SHIFT)) & ENET_MAC_VLAN_TAG_VTHM_MASK)
-#define ENET_MAC_VLAN_TAG_EDVLP_MASK (0x4000000U)
-#define ENET_MAC_VLAN_TAG_EDVLP_SHIFT (26U)
-#define ENET_MAC_VLAN_TAG_EDVLP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EDVLP_SHIFT)) & ENET_MAC_VLAN_TAG_EDVLP_MASK)
-#define ENET_MAC_VLAN_TAG_ERIVLT_MASK (0x8000000U)
-#define ENET_MAC_VLAN_TAG_ERIVLT_SHIFT (27U)
-#define ENET_MAC_VLAN_TAG_ERIVLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ERIVLT_SHIFT)) & ENET_MAC_VLAN_TAG_ERIVLT_MASK)
-#define ENET_MAC_VLAN_TAG_EIVLS_MASK (0x30000000U)
-#define ENET_MAC_VLAN_TAG_EIVLS_SHIFT (28U)
-#define ENET_MAC_VLAN_TAG_EIVLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EIVLS_SHIFT)) & ENET_MAC_VLAN_TAG_EIVLS_MASK)
-#define ENET_MAC_VLAN_TAG_EIVLRXS_MASK (0x80000000U)
-#define ENET_MAC_VLAN_TAG_EIVLRXS_SHIFT (31U)
-#define ENET_MAC_VLAN_TAG_EIVLRXS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EIVLRXS_SHIFT)) & ENET_MAC_VLAN_TAG_EIVLRXS_MASK)
-
-/*! @name MAC_TX_FLOW_CTRL_Q - Transmit flow control register */
-#define ENET_MAC_TX_FLOW_CTRL_Q_FCB_MASK (0x1U)
-#define ENET_MAC_TX_FLOW_CTRL_Q_FCB_SHIFT (0U)
-#define ENET_MAC_TX_FLOW_CTRL_Q_FCB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_FCB_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_FCB_MASK)
-#define ENET_MAC_TX_FLOW_CTRL_Q_TFE_MASK (0x2U)
-#define ENET_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT (1U)
-#define ENET_MAC_TX_FLOW_CTRL_Q_TFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_TFE_MASK)
-#define ENET_MAC_TX_FLOW_CTRL_Q_PLT_MASK (0x70U)
-#define ENET_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT (4U)
-#define ENET_MAC_TX_FLOW_CTRL_Q_PLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_PLT_MASK)
-#define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK (0x80U)
-#define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT (7U)
-#define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK)
-#define ENET_MAC_TX_FLOW_CTRL_Q_PT_MASK (0xFFFF0000U)
-#define ENET_MAC_TX_FLOW_CTRL_Q_PT_SHIFT (16U)
-#define ENET_MAC_TX_FLOW_CTRL_Q_PT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_PT_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_PT_MASK)
-
-/* The count of ENET_MAC_TX_FLOW_CTRL_Q */
-#define ENET_MAC_TX_FLOW_CTRL_Q_COUNT (2U)
-
-/*! @name MAC_RX_FLOW_CTRL - Receive flow control register */
-#define ENET_MAC_RX_FLOW_CTRL_RFE_MASK (0x1U)
-#define ENET_MAC_RX_FLOW_CTRL_RFE_SHIFT (0U)
-#define ENET_MAC_RX_FLOW_CTRL_RFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_FLOW_CTRL_RFE_SHIFT)) & ENET_MAC_RX_FLOW_CTRL_RFE_MASK)
-#define ENET_MAC_RX_FLOW_CTRL_UP_MASK (0x2U)
-#define ENET_MAC_RX_FLOW_CTRL_UP_SHIFT (1U)
-#define ENET_MAC_RX_FLOW_CTRL_UP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_FLOW_CTRL_UP_SHIFT)) & ENET_MAC_RX_FLOW_CTRL_UP_MASK)
-
-/*! @name MAC_TXQ_PRIO_MAP - */
-#define ENET_MAC_TXQ_PRIO_MAP_PSTQ0_MASK (0xFFU)
-#define ENET_MAC_TXQ_PRIO_MAP_PSTQ0_SHIFT (0U)
-#define ENET_MAC_TXQ_PRIO_MAP_PSTQ0(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TXQ_PRIO_MAP_PSTQ0_SHIFT)) & ENET_MAC_TXQ_PRIO_MAP_PSTQ0_MASK)
-#define ENET_MAC_TXQ_PRIO_MAP_PSTQ1_MASK (0xFF00U)
-#define ENET_MAC_TXQ_PRIO_MAP_PSTQ1_SHIFT (8U)
-#define ENET_MAC_TXQ_PRIO_MAP_PSTQ1(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TXQ_PRIO_MAP_PSTQ1_SHIFT)) & ENET_MAC_TXQ_PRIO_MAP_PSTQ1_MASK)
-
-/*! @name MAC_RXQ_CTRL - Receive Queue Control 0 register 0x0000 */
-#define ENET_MAC_RXQ_CTRL_RXQ0EN_MASK (0x3U)
-#define ENET_MAC_RXQ_CTRL_RXQ0EN_SHIFT (0U)
-#define ENET_MAC_RXQ_CTRL_RXQ0EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_RXQ0EN_SHIFT)) & ENET_MAC_RXQ_CTRL_RXQ0EN_MASK)
-#define ENET_MAC_RXQ_CTRL_PSRQ0_MASK (0xFFU)
-#define ENET_MAC_RXQ_CTRL_PSRQ0_SHIFT (0U)
-#define ENET_MAC_RXQ_CTRL_PSRQ0(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ0_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ0_MASK)
-#define ENET_MAC_RXQ_CTRL_AVCPQ_MASK (0x7U)
-#define ENET_MAC_RXQ_CTRL_AVCPQ_SHIFT (0U)
-#define ENET_MAC_RXQ_CTRL_AVCPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_AVCPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_AVCPQ_MASK)
-#define ENET_MAC_RXQ_CTRL_RXQ1EN_MASK (0xCU)
-#define ENET_MAC_RXQ_CTRL_RXQ1EN_SHIFT (2U)
-#define ENET_MAC_RXQ_CTRL_RXQ1EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_RXQ1EN_SHIFT)) & ENET_MAC_RXQ_CTRL_RXQ1EN_MASK)
-#define ENET_MAC_RXQ_CTRL_AVPTPQ_MASK (0x70U)
-#define ENET_MAC_RXQ_CTRL_AVPTPQ_SHIFT (4U)
-#define ENET_MAC_RXQ_CTRL_AVPTPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_AVPTPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_AVPTPQ_MASK)
-#define ENET_MAC_RXQ_CTRL_PSRQ1_MASK (0xFF00U)
-#define ENET_MAC_RXQ_CTRL_PSRQ1_SHIFT (8U)
-#define ENET_MAC_RXQ_CTRL_PSRQ1(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ1_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ1_MASK)
-#define ENET_MAC_RXQ_CTRL_UPQ_MASK (0x7000U)
-#define ENET_MAC_RXQ_CTRL_UPQ_SHIFT (12U)
-#define ENET_MAC_RXQ_CTRL_UPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_UPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_UPQ_MASK)
-#define ENET_MAC_RXQ_CTRL_PSRQ2_MASK (0xFF0000U)
-#define ENET_MAC_RXQ_CTRL_PSRQ2_SHIFT (16U)
-#define ENET_MAC_RXQ_CTRL_PSRQ2(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ2_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ2_MASK)
-#define ENET_MAC_RXQ_CTRL_MCBCQ_MASK (0x70000U)
-#define ENET_MAC_RXQ_CTRL_MCBCQ_SHIFT (16U)
-#define ENET_MAC_RXQ_CTRL_MCBCQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_MCBCQ_SHIFT)) & ENET_MAC_RXQ_CTRL_MCBCQ_MASK)
-#define ENET_MAC_RXQ_CTRL_MCBCQEN_MASK (0x100000U)
-#define ENET_MAC_RXQ_CTRL_MCBCQEN_SHIFT (20U)
-#define ENET_MAC_RXQ_CTRL_MCBCQEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_MCBCQEN_SHIFT)) & ENET_MAC_RXQ_CTRL_MCBCQEN_MASK)
-#define ENET_MAC_RXQ_CTRL_PSRQ3_MASK (0xFF000000U)
-#define ENET_MAC_RXQ_CTRL_PSRQ3_SHIFT (24U)
-#define ENET_MAC_RXQ_CTRL_PSRQ3(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ3_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ3_MASK)
-
-/* The count of ENET_MAC_RXQ_CTRL */
-#define ENET_MAC_RXQ_CTRL_COUNT (3U)
-
-/*! @name MAC_INTR_STAT - Interrupt status register 0x0000 */
-#define ENET_MAC_INTR_STAT_PHYIS_MASK (0x8U)
-#define ENET_MAC_INTR_STAT_PHYIS_SHIFT (3U)
-#define ENET_MAC_INTR_STAT_PHYIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_PHYIS_SHIFT)) & ENET_MAC_INTR_STAT_PHYIS_MASK)
-#define ENET_MAC_INTR_STAT_PMTIS_MASK (0x10U)
-#define ENET_MAC_INTR_STAT_PMTIS_SHIFT (4U)
-#define ENET_MAC_INTR_STAT_PMTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_PMTIS_SHIFT)) & ENET_MAC_INTR_STAT_PMTIS_MASK)
-#define ENET_MAC_INTR_STAT_LPIIS_MASK (0x20U)
-#define ENET_MAC_INTR_STAT_LPIIS_SHIFT (5U)
-#define ENET_MAC_INTR_STAT_LPIIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_LPIIS_SHIFT)) & ENET_MAC_INTR_STAT_LPIIS_MASK)
-#define ENET_MAC_INTR_STAT_TSIS_MASK (0x1000U)
-#define ENET_MAC_INTR_STAT_TSIS_SHIFT (12U)
-#define ENET_MAC_INTR_STAT_TSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_TSIS_SHIFT)) & ENET_MAC_INTR_STAT_TSIS_MASK)
-#define ENET_MAC_INTR_STAT_TXSTSIS_MASK (0x2000U)
-#define ENET_MAC_INTR_STAT_TXSTSIS_SHIFT (13U)
-#define ENET_MAC_INTR_STAT_TXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_TXSTSIS_SHIFT)) & ENET_MAC_INTR_STAT_TXSTSIS_MASK)
-#define ENET_MAC_INTR_STAT_RXSTSIS_MASK (0x4000U)
-#define ENET_MAC_INTR_STAT_RXSTSIS_SHIFT (14U)
-#define ENET_MAC_INTR_STAT_RXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_RXSTSIS_SHIFT)) & ENET_MAC_INTR_STAT_RXSTSIS_MASK)
-
-/*! @name MAC_INTR_EN - Interrupt enable register 0x0000 */
-#define ENET_MAC_INTR_EN_PHYIE_MASK (0x8U)
-#define ENET_MAC_INTR_EN_PHYIE_SHIFT (3U)
-#define ENET_MAC_INTR_EN_PHYIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_PHYIE_SHIFT)) & ENET_MAC_INTR_EN_PHYIE_MASK)
-#define ENET_MAC_INTR_EN_PMTIE_MASK (0x10U)
-#define ENET_MAC_INTR_EN_PMTIE_SHIFT (4U)
-#define ENET_MAC_INTR_EN_PMTIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_PMTIE_SHIFT)) & ENET_MAC_INTR_EN_PMTIE_MASK)
-#define ENET_MAC_INTR_EN_LPIIE_MASK (0x20U)
-#define ENET_MAC_INTR_EN_LPIIE_SHIFT (5U)
-#define ENET_MAC_INTR_EN_LPIIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_LPIIE_SHIFT)) & ENET_MAC_INTR_EN_LPIIE_MASK)
-#define ENET_MAC_INTR_EN_TSIE_MASK (0x1000U)
-#define ENET_MAC_INTR_EN_TSIE_SHIFT (12U)
-#define ENET_MAC_INTR_EN_TSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_TSIE_SHIFT)) & ENET_MAC_INTR_EN_TSIE_MASK)
-#define ENET_MAC_INTR_EN_TXSTSIE_MASK (0x2000U)
-#define ENET_MAC_INTR_EN_TXSTSIE_SHIFT (13U)
-#define ENET_MAC_INTR_EN_TXSTSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_TXSTSIE_SHIFT)) & ENET_MAC_INTR_EN_TXSTSIE_MASK)
-#define ENET_MAC_INTR_EN_RXSTSIS_MASK (0x4000U)
-#define ENET_MAC_INTR_EN_RXSTSIS_SHIFT (14U)
-#define ENET_MAC_INTR_EN_RXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_RXSTSIS_SHIFT)) & ENET_MAC_INTR_EN_RXSTSIS_MASK)
-
-/*! @name MAC_RXTX_STAT - Receive Transmit Status register */
-#define ENET_MAC_RXTX_STAT_TJT_MASK (0x1U)
-#define ENET_MAC_RXTX_STAT_TJT_SHIFT (0U)
-#define ENET_MAC_RXTX_STAT_TJT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_TJT_SHIFT)) & ENET_MAC_RXTX_STAT_TJT_MASK)
-#define ENET_MAC_RXTX_STAT_NCARR_MASK (0x2U)
-#define ENET_MAC_RXTX_STAT_NCARR_SHIFT (1U)
-#define ENET_MAC_RXTX_STAT_NCARR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_NCARR_SHIFT)) & ENET_MAC_RXTX_STAT_NCARR_MASK)
-#define ENET_MAC_RXTX_STAT_LCARR_MASK (0x4U)
-#define ENET_MAC_RXTX_STAT_LCARR_SHIFT (2U)
-#define ENET_MAC_RXTX_STAT_LCARR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_LCARR_SHIFT)) & ENET_MAC_RXTX_STAT_LCARR_MASK)
-#define ENET_MAC_RXTX_STAT_EXDEF_MASK (0x8U)
-#define ENET_MAC_RXTX_STAT_EXDEF_SHIFT (3U)
-#define ENET_MAC_RXTX_STAT_EXDEF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_EXDEF_SHIFT)) & ENET_MAC_RXTX_STAT_EXDEF_MASK)
-#define ENET_MAC_RXTX_STAT_LCOL_MASK (0x10U)
-#define ENET_MAC_RXTX_STAT_LCOL_SHIFT (4U)
-#define ENET_MAC_RXTX_STAT_LCOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_LCOL_SHIFT)) & ENET_MAC_RXTX_STAT_LCOL_MASK)
-#define ENET_MAC_RXTX_STAT_EXCOL_MASK (0x20U)
-#define ENET_MAC_RXTX_STAT_EXCOL_SHIFT (5U)
-#define ENET_MAC_RXTX_STAT_EXCOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_EXCOL_SHIFT)) & ENET_MAC_RXTX_STAT_EXCOL_MASK)
-#define ENET_MAC_RXTX_STAT_RWT_MASK (0x100U)
-#define ENET_MAC_RXTX_STAT_RWT_SHIFT (8U)
-#define ENET_MAC_RXTX_STAT_RWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_RWT_SHIFT)) & ENET_MAC_RXTX_STAT_RWT_MASK)
-
-/*! @name MAC_PMT_CRTL_STAT - */
-#define ENET_MAC_PMT_CRTL_STAT_PWRDWN_MASK (0x1U)
-#define ENET_MAC_PMT_CRTL_STAT_PWRDWN_SHIFT (0U)
-#define ENET_MAC_PMT_CRTL_STAT_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_PWRDWN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_PWRDWN_MASK)
-#define ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_MASK (0x2U)
-#define ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_SHIFT (1U)
-#define ENET_MAC_PMT_CRTL_STAT_MGKPKTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_MASK)
-#define ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_MASK (0x4U)
-#define ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_SHIFT (2U)
-#define ENET_MAC_PMT_CRTL_STAT_RWKPKTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_MASK)
-#define ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_MASK (0x20U)
-#define ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_SHIFT (5U)
-#define ENET_MAC_PMT_CRTL_STAT_MGKPRCVD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_MASK)
-#define ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_MASK (0x40U)
-#define ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_SHIFT (6U)
-#define ENET_MAC_PMT_CRTL_STAT_RWKPRCVD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_MASK)
-#define ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_MASK (0x200U)
-#define ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_SHIFT (9U)
-#define ENET_MAC_PMT_CRTL_STAT_GLBLUCAST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_MASK)
-#define ENET_MAC_PMT_CRTL_STAT_RWKPFE_MASK (0x400U)
-#define ENET_MAC_PMT_CRTL_STAT_RWKPFE_SHIFT (10U)
-#define ENET_MAC_PMT_CRTL_STAT_RWKPFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPFE_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPFE_MASK)
-#define ENET_MAC_PMT_CRTL_STAT_RWKPTR_MASK (0x1F000000U)
-#define ENET_MAC_PMT_CRTL_STAT_RWKPTR_SHIFT (24U)
-#define ENET_MAC_PMT_CRTL_STAT_RWKPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPTR_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPTR_MASK)
-#define ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_MASK (0x80000000U)
-#define ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_SHIFT (31U)
-#define ENET_MAC_PMT_CRTL_STAT_RWKFILTRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_MASK)
-
-/*! @name MAC_RWAKE_FRFLT - Remote wake-up frame filter */
-#define ENET_MAC_RWAKE_FRFLT_ADDR_MASK (0xFFFFFFFFU)
-#define ENET_MAC_RWAKE_FRFLT_ADDR_SHIFT (0U)
-#define ENET_MAC_RWAKE_FRFLT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RWAKE_FRFLT_ADDR_SHIFT)) & ENET_MAC_RWAKE_FRFLT_ADDR_MASK)
-
-/*! @name MAC_LPI_CTRL_STAT - LPI Control and Status Register */
-#define ENET_MAC_LPI_CTRL_STAT_TLPIEN_MASK (0x1U)
-#define ENET_MAC_LPI_CTRL_STAT_TLPIEN_SHIFT (0U)
-#define ENET_MAC_LPI_CTRL_STAT_TLPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIEN_MASK)
-#define ENET_MAC_LPI_CTRL_STAT_TLPIEX_MASK (0x2U)
-#define ENET_MAC_LPI_CTRL_STAT_TLPIEX_SHIFT (1U)
-#define ENET_MAC_LPI_CTRL_STAT_TLPIEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIEX_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIEX_MASK)
-#define ENET_MAC_LPI_CTRL_STAT_RLPIEN_MASK (0x4U)
-#define ENET_MAC_LPI_CTRL_STAT_RLPIEN_SHIFT (2U)
-#define ENET_MAC_LPI_CTRL_STAT_RLPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIEN_MASK)
-#define ENET_MAC_LPI_CTRL_STAT_RLPIEX_MASK (0x8U)
-#define ENET_MAC_LPI_CTRL_STAT_RLPIEX_SHIFT (3U)
-#define ENET_MAC_LPI_CTRL_STAT_RLPIEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIEX_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIEX_MASK)
-#define ENET_MAC_LPI_CTRL_STAT_TLPIST_MASK (0x100U)
-#define ENET_MAC_LPI_CTRL_STAT_TLPIST_SHIFT (8U)
-#define ENET_MAC_LPI_CTRL_STAT_TLPIST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIST_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIST_MASK)
-#define ENET_MAC_LPI_CTRL_STAT_RLPIST_MASK (0x200U)
-#define ENET_MAC_LPI_CTRL_STAT_RLPIST_SHIFT (9U)
-#define ENET_MAC_LPI_CTRL_STAT_RLPIST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIST_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIST_MASK)
-#define ENET_MAC_LPI_CTRL_STAT_LPIEN_MASK (0x10000U)
-#define ENET_MAC_LPI_CTRL_STAT_LPIEN_SHIFT (16U)
-#define ENET_MAC_LPI_CTRL_STAT_LPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPIEN_MASK)
-#define ENET_MAC_LPI_CTRL_STAT_PLS_MASK (0x20000U)
-#define ENET_MAC_LPI_CTRL_STAT_PLS_SHIFT (17U)
-#define ENET_MAC_LPI_CTRL_STAT_PLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_PLS_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_PLS_MASK)
-#define ENET_MAC_LPI_CTRL_STAT_LPITXA_MASK (0x80000U)
-#define ENET_MAC_LPI_CTRL_STAT_LPITXA_SHIFT (19U)
-#define ENET_MAC_LPI_CTRL_STAT_LPITXA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPITXA_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPITXA_MASK)
-#define ENET_MAC_LPI_CTRL_STAT_LPIATE_MASK (0x100000U)
-#define ENET_MAC_LPI_CTRL_STAT_LPIATE_SHIFT (20U)
-#define ENET_MAC_LPI_CTRL_STAT_LPIATE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPIATE_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPIATE_MASK)
-#define ENET_MAC_LPI_CTRL_STAT_LPITCSE_MASK (0x200000U)
-#define ENET_MAC_LPI_CTRL_STAT_LPITCSE_SHIFT (21U)
-#define ENET_MAC_LPI_CTRL_STAT_LPITCSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPITCSE_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPITCSE_MASK)
-
-/*! @name MAC_LPI_TIMER_CTRL - LPI Timers Control register */
-#define ENET_MAC_LPI_TIMER_CTRL_TWT_MASK (0xFFFFU)
-#define ENET_MAC_LPI_TIMER_CTRL_TWT_SHIFT (0U)
-#define ENET_MAC_LPI_TIMER_CTRL_TWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_TIMER_CTRL_TWT_SHIFT)) & ENET_MAC_LPI_TIMER_CTRL_TWT_MASK)
-#define ENET_MAC_LPI_TIMER_CTRL_LST_MASK (0x3FF0000U)
-#define ENET_MAC_LPI_TIMER_CTRL_LST_SHIFT (16U)
-#define ENET_MAC_LPI_TIMER_CTRL_LST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_TIMER_CTRL_LST_SHIFT)) & ENET_MAC_LPI_TIMER_CTRL_LST_MASK)
-
-/*! @name MAC_LPI_ENTR_TIMR - LPI entry Timer register */
-#define ENET_MAC_LPI_ENTR_TIMR_LPIET_MASK (0xFFFF8U)
-#define ENET_MAC_LPI_ENTR_TIMR_LPIET_SHIFT (3U)
-#define ENET_MAC_LPI_ENTR_TIMR_LPIET(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_ENTR_TIMR_LPIET_SHIFT)) & ENET_MAC_LPI_ENTR_TIMR_LPIET_MASK)
-
-/*! @name MAC_1US_TIC_COUNTR - */
-#define ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_MASK (0xFFFU)
-#define ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_SHIFT (0U)
-#define ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_SHIFT)) & ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_MASK)
-
-/*! @name MAC_VERSION - MAC version register */
-#define ENET_MAC_VERSION_SNPVER_MASK (0xFFU)
-#define ENET_MAC_VERSION_SNPVER_SHIFT (0U)
-#define ENET_MAC_VERSION_SNPVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VERSION_SNPVER_SHIFT)) & ENET_MAC_VERSION_SNPVER_MASK)
-#define ENET_MAC_VERSION_USERVER_MASK (0xFF00U)
-#define ENET_MAC_VERSION_USERVER_SHIFT (8U)
-#define ENET_MAC_VERSION_USERVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VERSION_USERVER_SHIFT)) & ENET_MAC_VERSION_USERVER_MASK)
-
-/*! @name MAC_DBG - MAC debug register */
-#define ENET_MAC_DBG_REPESTS_MASK (0x1U)
-#define ENET_MAC_DBG_REPESTS_SHIFT (0U)
-#define ENET_MAC_DBG_REPESTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_REPESTS_SHIFT)) & ENET_MAC_DBG_REPESTS_MASK)
-#define ENET_MAC_DBG_RFCFCSTS_MASK (0x6U)
-#define ENET_MAC_DBG_RFCFCSTS_SHIFT (1U)
-#define ENET_MAC_DBG_RFCFCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_RFCFCSTS_SHIFT)) & ENET_MAC_DBG_RFCFCSTS_MASK)
-#define ENET_MAC_DBG_TPESTS_MASK (0x10000U)
-#define ENET_MAC_DBG_TPESTS_SHIFT (16U)
-#define ENET_MAC_DBG_TPESTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_TPESTS_SHIFT)) & ENET_MAC_DBG_TPESTS_MASK)
-#define ENET_MAC_DBG_TFCSTS_MASK (0x60000U)
-#define ENET_MAC_DBG_TFCSTS_SHIFT (17U)
-#define ENET_MAC_DBG_TFCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_TFCSTS_SHIFT)) & ENET_MAC_DBG_TFCSTS_MASK)
-
-/*! @name MAC_HW_FEAT - MAC hardware feature register 0x0201 */
-#define ENET_MAC_HW_FEAT_RXFIFOSIZE_MASK (0x1FU)
-#define ENET_MAC_HW_FEAT_RXFIFOSIZE_SHIFT (0U)
-#define ENET_MAC_HW_FEAT_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXFIFOSIZE_SHIFT)) & ENET_MAC_HW_FEAT_RXFIFOSIZE_MASK)
-#define ENET_MAC_HW_FEAT_RXQCNT_MASK (0xFU)
-#define ENET_MAC_HW_FEAT_RXQCNT_SHIFT (0U)
-#define ENET_MAC_HW_FEAT_RXQCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXQCNT_SHIFT)) & ENET_MAC_HW_FEAT_RXQCNT_MASK)
-#define ENET_MAC_HW_FEAT_MIISEL_MASK (0x1U)
-#define ENET_MAC_HW_FEAT_MIISEL_SHIFT (0U)
-#define ENET_MAC_HW_FEAT_MIISEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MIISEL_SHIFT)) & ENET_MAC_HW_FEAT_MIISEL_MASK)
-#define ENET_MAC_HW_FEAT_HDSEL_MASK (0x4U)
-#define ENET_MAC_HW_FEAT_HDSEL_SHIFT (2U)
-#define ENET_MAC_HW_FEAT_HDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_HDSEL_SHIFT)) & ENET_MAC_HW_FEAT_HDSEL_MASK)
-#define ENET_MAC_HW_FEAT_VLHASH_MASK (0x10U)
-#define ENET_MAC_HW_FEAT_VLHASH_SHIFT (4U)
-#define ENET_MAC_HW_FEAT_VLHASH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_VLHASH_SHIFT)) & ENET_MAC_HW_FEAT_VLHASH_MASK)
-#define ENET_MAC_HW_FEAT_SMASEL_MASK (0x20U)
-#define ENET_MAC_HW_FEAT_SMASEL_SHIFT (5U)
-#define ENET_MAC_HW_FEAT_SMASEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_SMASEL_SHIFT)) & ENET_MAC_HW_FEAT_SMASEL_MASK)
-#define ENET_MAC_HW_FEAT_TXQCNT_MASK (0x3C0U)
-#define ENET_MAC_HW_FEAT_TXQCNT_SHIFT (6U)
-#define ENET_MAC_HW_FEAT_TXQCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXQCNT_SHIFT)) & ENET_MAC_HW_FEAT_TXQCNT_MASK)
-#define ENET_MAC_HW_FEAT_RWKSEL_MASK (0x40U)
-#define ENET_MAC_HW_FEAT_RWKSEL_SHIFT (6U)
-#define ENET_MAC_HW_FEAT_RWKSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RWKSEL_SHIFT)) & ENET_MAC_HW_FEAT_RWKSEL_MASK)
-#define ENET_MAC_HW_FEAT_TXFIFOSIZE_MASK (0x7C0U)
-#define ENET_MAC_HW_FEAT_TXFIFOSIZE_SHIFT (6U)
-#define ENET_MAC_HW_FEAT_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXFIFOSIZE_SHIFT)) & ENET_MAC_HW_FEAT_TXFIFOSIZE_MASK)
-#define ENET_MAC_HW_FEAT_MGKSEL_MASK (0x80U)
-#define ENET_MAC_HW_FEAT_MGKSEL_SHIFT (7U)
-#define ENET_MAC_HW_FEAT_MGKSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MGKSEL_SHIFT)) & ENET_MAC_HW_FEAT_MGKSEL_MASK)
-#define ENET_MAC_HW_FEAT_MMCSEL_MASK (0x100U)
-#define ENET_MAC_HW_FEAT_MMCSEL_SHIFT (8U)
-#define ENET_MAC_HW_FEAT_MMCSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MMCSEL_SHIFT)) & ENET_MAC_HW_FEAT_MMCSEL_MASK)
-#define ENET_MAC_HW_FEAT_ARPOFFSEL_MASK (0x200U)
-#define ENET_MAC_HW_FEAT_ARPOFFSEL_SHIFT (9U)
-#define ENET_MAC_HW_FEAT_ARPOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ARPOFFSEL_SHIFT)) & ENET_MAC_HW_FEAT_ARPOFFSEL_MASK)
-#define ENET_MAC_HW_FEAT_OSTEN_MASK (0x800U)
-#define ENET_MAC_HW_FEAT_OSTEN_SHIFT (11U)
-#define ENET_MAC_HW_FEAT_OSTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_OSTEN_SHIFT)) & ENET_MAC_HW_FEAT_OSTEN_MASK)
-#define ENET_MAC_HW_FEAT_RXCHCNT_MASK (0xF000U)
-#define ENET_MAC_HW_FEAT_RXCHCNT_SHIFT (12U)
-#define ENET_MAC_HW_FEAT_RXCHCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXCHCNT_SHIFT)) & ENET_MAC_HW_FEAT_RXCHCNT_MASK)
-#define ENET_MAC_HW_FEAT_TSSEL_MASK (0x1000U)
-#define ENET_MAC_HW_FEAT_TSSEL_SHIFT (12U)
-#define ENET_MAC_HW_FEAT_TSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSSEL_SHIFT)) & ENET_MAC_HW_FEAT_TSSEL_MASK)
-#define ENET_MAC_HW_FEAT_PTOEN_MASK (0x1000U)
-#define ENET_MAC_HW_FEAT_PTOEN_SHIFT (12U)
-#define ENET_MAC_HW_FEAT_PTOEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_PTOEN_SHIFT)) & ENET_MAC_HW_FEAT_PTOEN_MASK)
-#define ENET_MAC_HW_FEAT_EEESEL_MASK (0x2000U)
-#define ENET_MAC_HW_FEAT_EEESEL_SHIFT (13U)
-#define ENET_MAC_HW_FEAT_EEESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_EEESEL_SHIFT)) & ENET_MAC_HW_FEAT_EEESEL_MASK)
-#define ENET_MAC_HW_FEAT_ADVTHWORD_MASK (0x2000U)
-#define ENET_MAC_HW_FEAT_ADVTHWORD_SHIFT (13U)
-#define ENET_MAC_HW_FEAT_ADVTHWORD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ADVTHWORD_SHIFT)) & ENET_MAC_HW_FEAT_ADVTHWORD_MASK)
-#define ENET_MAC_HW_FEAT_ADDR64_MASK (0xC000U)
-#define ENET_MAC_HW_FEAT_ADDR64_SHIFT (14U)
-#define ENET_MAC_HW_FEAT_ADDR64(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ADDR64_SHIFT)) & ENET_MAC_HW_FEAT_ADDR64_MASK)
-#define ENET_MAC_HW_FEAT_TXCOESEL_MASK (0x4000U)
-#define ENET_MAC_HW_FEAT_TXCOESEL_SHIFT (14U)
-#define ENET_MAC_HW_FEAT_TXCOESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXCOESEL_SHIFT)) & ENET_MAC_HW_FEAT_TXCOESEL_MASK)
-#define ENET_MAC_HW_FEAT_DCBEN_MASK (0x10000U)
-#define ENET_MAC_HW_FEAT_DCBEN_SHIFT (16U)
-#define ENET_MAC_HW_FEAT_DCBEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_DCBEN_SHIFT)) & ENET_MAC_HW_FEAT_DCBEN_MASK)
-#define ENET_MAC_HW_FEAT_RXCOESEL_MASK (0x10000U)
-#define ENET_MAC_HW_FEAT_RXCOESEL_SHIFT (16U)
-#define ENET_MAC_HW_FEAT_RXCOESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXCOESEL_SHIFT)) & ENET_MAC_HW_FEAT_RXCOESEL_MASK)
-#define ENET_MAC_HW_FEAT_SPEN_MASK (0x20000U)
-#define ENET_MAC_HW_FEAT_SPEN_SHIFT (17U)
-#define ENET_MAC_HW_FEAT_SPEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_SPEN_SHIFT)) & ENET_MAC_HW_FEAT_SPEN_MASK)
-#define ENET_MAC_HW_FEAT_TXCHCNT_MASK (0x3C0000U)
-#define ENET_MAC_HW_FEAT_TXCHCNT_SHIFT (18U)
-#define ENET_MAC_HW_FEAT_TXCHCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXCHCNT_SHIFT)) & ENET_MAC_HW_FEAT_TXCHCNT_MASK)
-#define ENET_MAC_HW_FEAT_TSOEN_MASK (0x40000U)
-#define ENET_MAC_HW_FEAT_TSOEN_SHIFT (18U)
-#define ENET_MAC_HW_FEAT_TSOEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSOEN_SHIFT)) & ENET_MAC_HW_FEAT_TSOEN_MASK)
-#define ENET_MAC_HW_FEAT_DBGMEMA_MASK (0x80000U)
-#define ENET_MAC_HW_FEAT_DBGMEMA_SHIFT (19U)
-#define ENET_MAC_HW_FEAT_DBGMEMA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_DBGMEMA_SHIFT)) & ENET_MAC_HW_FEAT_DBGMEMA_MASK)
-#define ENET_MAC_HW_FEAT_AVSEL_MASK (0x100000U)
-#define ENET_MAC_HW_FEAT_AVSEL_SHIFT (20U)
-#define ENET_MAC_HW_FEAT_AVSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_AVSEL_SHIFT)) & ENET_MAC_HW_FEAT_AVSEL_MASK)
-#define ENET_MAC_HW_FEAT_LPMODEEN_MASK (0x800000U)
-#define ENET_MAC_HW_FEAT_LPMODEEN_SHIFT (23U)
-#define ENET_MAC_HW_FEAT_LPMODEEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_LPMODEEN_SHIFT)) & ENET_MAC_HW_FEAT_LPMODEEN_MASK)
-#define ENET_MAC_HW_FEAT_PPSOUTNUM_MASK (0x7000000U)
-#define ENET_MAC_HW_FEAT_PPSOUTNUM_SHIFT (24U)
-#define ENET_MAC_HW_FEAT_PPSOUTNUM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_PPSOUTNUM_SHIFT)) & ENET_MAC_HW_FEAT_PPSOUTNUM_MASK)
-#define ENET_MAC_HW_FEAT_HASHTBLSZ_MASK (0x3000000U)
-#define ENET_MAC_HW_FEAT_HASHTBLSZ_SHIFT (24U)
-#define ENET_MAC_HW_FEAT_HASHTBLSZ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_HASHTBLSZ_SHIFT)) & ENET_MAC_HW_FEAT_HASHTBLSZ_MASK)
-#define ENET_MAC_HW_FEAT_TSSTSSEL_MASK (0x6000000U)
-#define ENET_MAC_HW_FEAT_TSSTSSEL_SHIFT (25U)
-#define ENET_MAC_HW_FEAT_TSSTSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSSTSSEL_SHIFT)) & ENET_MAC_HW_FEAT_TSSTSSEL_MASK)
-#define ENET_MAC_HW_FEAT_L3_L4_FILTER_MASK (0x78000000U)
-#define ENET_MAC_HW_FEAT_L3_L4_FILTER_SHIFT (27U)
-#define ENET_MAC_HW_FEAT_L3_L4_FILTER(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_L3_L4_FILTER_SHIFT)) & ENET_MAC_HW_FEAT_L3_L4_FILTER_MASK)
-#define ENET_MAC_HW_FEAT_AUXSNAPNUM_MASK (0x70000000U)
-#define ENET_MAC_HW_FEAT_AUXSNAPNUM_SHIFT (28U)
-#define ENET_MAC_HW_FEAT_AUXSNAPNUM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_AUXSNAPNUM_SHIFT)) & ENET_MAC_HW_FEAT_AUXSNAPNUM_MASK)
-#define ENET_MAC_HW_FEAT_ACTPHYSEL_MASK (0x70000000U)
-#define ENET_MAC_HW_FEAT_ACTPHYSEL_SHIFT (28U)
-#define ENET_MAC_HW_FEAT_ACTPHYSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ACTPHYSEL_SHIFT)) & ENET_MAC_HW_FEAT_ACTPHYSEL_MASK)
-
-/* The count of ENET_MAC_HW_FEAT */
-#define ENET_MAC_HW_FEAT_COUNT (3U)
-
-/*! @name MAC_MDIO_ADDR - MIDO address Register */
-#define ENET_MAC_MDIO_ADDR_MB_MASK (0x1U)
-#define ENET_MAC_MDIO_ADDR_MB_SHIFT (0U)
-#define ENET_MAC_MDIO_ADDR_MB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_MB_SHIFT)) & ENET_MAC_MDIO_ADDR_MB_MASK)
-#define ENET_MAC_MDIO_ADDR_MOC_MASK (0xCU)
-#define ENET_MAC_MDIO_ADDR_MOC_SHIFT (2U)
-#define ENET_MAC_MDIO_ADDR_MOC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_MOC_SHIFT)) & ENET_MAC_MDIO_ADDR_MOC_MASK)
-#define ENET_MAC_MDIO_ADDR_CR_MASK (0xF00U)
-#define ENET_MAC_MDIO_ADDR_CR_SHIFT (8U)
-#define ENET_MAC_MDIO_ADDR_CR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_CR_SHIFT)) & ENET_MAC_MDIO_ADDR_CR_MASK)
-#define ENET_MAC_MDIO_ADDR_NTC_MASK (0x7000U)
-#define ENET_MAC_MDIO_ADDR_NTC_SHIFT (12U)
-#define ENET_MAC_MDIO_ADDR_NTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_NTC_SHIFT)) & ENET_MAC_MDIO_ADDR_NTC_MASK)
-#define ENET_MAC_MDIO_ADDR_RDA_MASK (0x1F0000U)
-#define ENET_MAC_MDIO_ADDR_RDA_SHIFT (16U)
-#define ENET_MAC_MDIO_ADDR_RDA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_RDA_SHIFT)) & ENET_MAC_MDIO_ADDR_RDA_MASK)
-#define ENET_MAC_MDIO_ADDR_PA_MASK (0x3E00000U)
-#define ENET_MAC_MDIO_ADDR_PA_SHIFT (21U)
-#define ENET_MAC_MDIO_ADDR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_PA_SHIFT)) & ENET_MAC_MDIO_ADDR_PA_MASK)
-#define ENET_MAC_MDIO_ADDR_BTB_MASK (0x4000000U)
-#define ENET_MAC_MDIO_ADDR_BTB_SHIFT (26U)
-#define ENET_MAC_MDIO_ADDR_BTB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_BTB_SHIFT)) & ENET_MAC_MDIO_ADDR_BTB_MASK)
-#define ENET_MAC_MDIO_ADDR_PSE_MASK (0x8000000U)
-#define ENET_MAC_MDIO_ADDR_PSE_SHIFT (27U)
-#define ENET_MAC_MDIO_ADDR_PSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_PSE_SHIFT)) & ENET_MAC_MDIO_ADDR_PSE_MASK)
-
-/*! @name MAC_MDIO_DATA - MDIO Data register */
-#define ENET_MAC_MDIO_DATA_MD_MASK (0xFFFFU)
-#define ENET_MAC_MDIO_DATA_MD_SHIFT (0U)
-#define ENET_MAC_MDIO_DATA_MD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_DATA_MD_SHIFT)) & ENET_MAC_MDIO_DATA_MD_MASK)
-
-/*! @name MAC_ADDR_HIGH - MAC address0 high register */
-#define ENET_MAC_ADDR_HIGH_A47_32_MASK (0xFFFFU)
-#define ENET_MAC_ADDR_HIGH_A47_32_SHIFT (0U)
-#define ENET_MAC_ADDR_HIGH_A47_32(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_A47_32_SHIFT)) & ENET_MAC_ADDR_HIGH_A47_32_MASK)
-#define ENET_MAC_ADDR_HIGH_DCS_MASK (0x10000U)
-#define ENET_MAC_ADDR_HIGH_DCS_SHIFT (16U)
-#define ENET_MAC_ADDR_HIGH_DCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_DCS_SHIFT)) & ENET_MAC_ADDR_HIGH_DCS_MASK)
-#define ENET_MAC_ADDR_HIGH_AE_MASK (0x80000000U)
-#define ENET_MAC_ADDR_HIGH_AE_SHIFT (31U)
-#define ENET_MAC_ADDR_HIGH_AE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_AE_SHIFT)) & ENET_MAC_ADDR_HIGH_AE_MASK)
-
-/*! @name MAC_ADDR_LOW - MAC address0 low register */
-#define ENET_MAC_ADDR_LOW_A31_0_MASK (0xFFFFFFFFU)
-#define ENET_MAC_ADDR_LOW_A31_0_SHIFT (0U)
-#define ENET_MAC_ADDR_LOW_A31_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_LOW_A31_0_SHIFT)) & ENET_MAC_ADDR_LOW_A31_0_MASK)
-
-/*! @name MAC_TIMESTAMP_CTRL - Time stamp control register */
-#define ENET_MAC_TIMESTAMP_CTRL_TSENA_MASK (0x1U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSENA_SHIFT (0U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENA_MASK)
-#define ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_MASK (0x2U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_SHIFT (1U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_MASK)
-#define ENET_MAC_TIMESTAMP_CTRL_TSINIT_MASK (0x4U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSINIT_SHIFT (2U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSINIT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSINIT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSINIT_MASK)
-#define ENET_MAC_TIMESTAMP_CTRL_TSUPDT_MASK (0x8U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSUPDT_SHIFT (3U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSUPDT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSUPDT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSUPDT_MASK)
-#define ENET_MAC_TIMESTAMP_CTRL_TSTRIG_MASK (0x10U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSTRIG_SHIFT (4U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSTRIG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSTRIG_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSTRIG_MASK)
-#define ENET_MAC_TIMESTAMP_CTRL_TADDREG_MASK (0x20U)
-#define ENET_MAC_TIMESTAMP_CTRL_TADDREG_SHIFT (5U)
-#define ENET_MAC_TIMESTAMP_CTRL_TADDREG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TADDREG_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TADDREG_MASK)
-#define ENET_MAC_TIMESTAMP_CTRL_TSENALL_MASK (0x100U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSENALL_SHIFT (8U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSENALL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENALL_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENALL_MASK)
-#define ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK (0x200U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_SHIFT (9U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK)
-#define ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_MASK (0x400U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_SHIFT (10U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_MASK)
-#define ENET_MAC_TIMESTAMP_CTRL_TSIPENA_MASK (0x800U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSIPENA_SHIFT (11U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSIPENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPENA_MASK)
-#define ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_MASK (0x1000U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_SHIFT (12U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_MASK)
-#define ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_MASK (0x2000U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_SHIFT (13U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_MASK)
-#define ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_MASK (0x4000U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_SHIFT (14U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSEVTENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_MASK)
-#define ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_MASK (0x8000U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_SHIFT (15U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_MASK)
-#define ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_MASK (0x30000U)
-#define ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_SHIFT (16U)
-#define ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_MASK)
-#define ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_MASK (0x40000U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_SHIFT (18U)
-#define ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_MASK)
-#define ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_MASK (0x1000000U)
-#define ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_SHIFT (24U)
-#define ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_MASK)
-#define ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_MASK (0x10000000U)
-#define ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_SHIFT (28U)
-#define ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_MASK)
-
-/*! @name MAC_SUB_SCND_INCR - Sub-second increment register */
-#define ENET_MAC_SUB_SCND_INCR_SSINC_MASK (0xFF0000U)
-#define ENET_MAC_SUB_SCND_INCR_SSINC_SHIFT (16U)
-#define ENET_MAC_SUB_SCND_INCR_SSINC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SUB_SCND_INCR_SSINC_SHIFT)) & ENET_MAC_SUB_SCND_INCR_SSINC_MASK)
-
-/*! @name MAC_SYS_TIME_SCND - System time seconds register */
-#define ENET_MAC_SYS_TIME_SCND_TSS_MASK (0xFFFFFFFFU)
-#define ENET_MAC_SYS_TIME_SCND_TSS_SHIFT (0U)
-#define ENET_MAC_SYS_TIME_SCND_TSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_SCND_TSS_SHIFT)) & ENET_MAC_SYS_TIME_SCND_TSS_MASK)
-
-/*! @name MAC_SYS_TIME_NSCND - System time nanoseconds register */
-#define ENET_MAC_SYS_TIME_NSCND_TSSS_MASK (0x7FFFFFFFU)
-#define ENET_MAC_SYS_TIME_NSCND_TSSS_SHIFT (0U)
-#define ENET_MAC_SYS_TIME_NSCND_TSSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_TSSS_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_TSSS_MASK)
-
-/*! @name MAC_SYS_TIME_SCND_UPD - */
-#define ENET_MAC_SYS_TIME_SCND_UPD_TSS_MASK (0xFFFFFFFFU)
-#define ENET_MAC_SYS_TIME_SCND_UPD_TSS_SHIFT (0U)
-#define ENET_MAC_SYS_TIME_SCND_UPD_TSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_SCND_UPD_TSS_SHIFT)) & ENET_MAC_SYS_TIME_SCND_UPD_TSS_MASK)
-
-/*! @name MAC_SYS_TIME_NSCND_UPD - */
-#define ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_MASK (0x7FFFFFFFU)
-#define ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_SHIFT (0U)
-#define ENET_MAC_SYS_TIME_NSCND_UPD_TSSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_MASK)
-#define ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_MASK (0x80000000U)
-#define ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_SHIFT (31U)
-#define ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_MASK)
-
-/*! @name MAC_SYS_TIMESTMP_ADDEND - Time stamp addend register */
-#define ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_MASK (0xFFFFFFFFU)
-#define ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_SHIFT (0U)
-#define ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_SHIFT)) & ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_MASK)
-
-/*! @name MAC_SYS_TIME_HWORD_SCND - */
-#define ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_MASK (0xFFFFU)
-#define ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_SHIFT (0U)
-#define ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_SHIFT)) & ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_MASK)
-
-/*! @name MAC_SYS_TIMESTMP_STAT - Time stamp status register */
-#define ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_MASK (0x1U)
-#define ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_SHIFT (0U)
-#define ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_SHIFT)) & ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_MASK)
-
-/*! @name MAC_TX_TIMESTAMP_STATUS_NANOSECONDS - Tx timestamp status nanoseconds */
-#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_MASK (0x7FFFFFFFU)
-#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_SHIFT (0U)
-#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_MASK)
-#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_MASK (0x80000000U)
-#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_SHIFT (31U)
-#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_MASK)
-
-/*! @name MAC_TX_TIMESTAMP_STATUS_SECONDS - Tx timestamp status seconds */
-#define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_MASK (0xFFFFFFFFU)
-#define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_SHIFT (0U)
-#define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_MASK)
-
-/*! @name MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND - Timestamp ingress correction */
-#define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK (0xFFFFFFFFU)
-#define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT (0U)
-#define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT)) & ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK)
-
-/*! @name MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND - Timestamp egress correction */
-#define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK (0xFFFFFFFFU)
-#define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT (0U)
-#define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT)) & ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK)
-
-/*! @name MTL_OP_MODE - MTL Operation Mode Register */
-#define ENET_MTL_OP_MODE_DTXSTS_MASK (0x2U)
-#define ENET_MTL_OP_MODE_DTXSTS_SHIFT (1U)
-#define ENET_MTL_OP_MODE_DTXSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_DTXSTS_SHIFT)) & ENET_MTL_OP_MODE_DTXSTS_MASK)
-#define ENET_MTL_OP_MODE_RAA_MASK (0x4U)
-#define ENET_MTL_OP_MODE_RAA_SHIFT (2U)
-#define ENET_MTL_OP_MODE_RAA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_RAA_SHIFT)) & ENET_MTL_OP_MODE_RAA_MASK)
-#define ENET_MTL_OP_MODE_SCHALG_MASK (0x60U)
-#define ENET_MTL_OP_MODE_SCHALG_SHIFT (5U)
-#define ENET_MTL_OP_MODE_SCHALG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_SCHALG_SHIFT)) & ENET_MTL_OP_MODE_SCHALG_MASK)
-#define ENET_MTL_OP_MODE_CNTPRST_MASK (0x100U)
-#define ENET_MTL_OP_MODE_CNTPRST_SHIFT (8U)
-#define ENET_MTL_OP_MODE_CNTPRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_CNTPRST_SHIFT)) & ENET_MTL_OP_MODE_CNTPRST_MASK)
-#define ENET_MTL_OP_MODE_CNTCLR_MASK (0x200U)
-#define ENET_MTL_OP_MODE_CNTCLR_SHIFT (9U)
-#define ENET_MTL_OP_MODE_CNTCLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_CNTCLR_SHIFT)) & ENET_MTL_OP_MODE_CNTCLR_MASK)
-
-/*! @name MTL_INTR_STAT - MTL Interrupt Status register */
-#define ENET_MTL_INTR_STAT_Q0IS_MASK (0x1U)
-#define ENET_MTL_INTR_STAT_Q0IS_SHIFT (0U)
-#define ENET_MTL_INTR_STAT_Q0IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_INTR_STAT_Q0IS_SHIFT)) & ENET_MTL_INTR_STAT_Q0IS_MASK)
-#define ENET_MTL_INTR_STAT_Q1IS_MASK (0x2U)
-#define ENET_MTL_INTR_STAT_Q1IS_SHIFT (1U)
-#define ENET_MTL_INTR_STAT_Q1IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_INTR_STAT_Q1IS_SHIFT)) & ENET_MTL_INTR_STAT_Q1IS_MASK)
-
-/*! @name MTL_RXQ_DMA_MAP - MTL Receive Queue and DMA Channel Mapping register */
-#define ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_MASK (0x1U)
-#define ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_SHIFT (0U)
-#define ENET_MTL_RXQ_DMA_MAP_Q0MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_MASK)
-#define ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_MASK (0x10U)
-#define ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_SHIFT (4U)
-#define ENET_MTL_RXQ_DMA_MAP_Q0DDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_MASK)
-#define ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_MASK (0x100U)
-#define ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_SHIFT (8U)
-#define ENET_MTL_RXQ_DMA_MAP_Q1MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_MASK)
-#define ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_MASK (0x1000U)
-#define ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_SHIFT (12U)
-#define ENET_MTL_RXQ_DMA_MAP_Q1DDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_MASK)
-
-/*! @name MTL_QUEUE_MTL_TXQX_OP_MODE - MTL TxQx Operation Mode register */
-#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_MASK (0x1U)
-#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_SHIFT (0U)
-#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_MASK)
-#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_MASK (0x2U)
-#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_SHIFT (1U)
-#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_MASK)
-#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_MASK (0xCU)
-#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_SHIFT (2U)
-#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_MASK)
-#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_MASK (0x70U)
-#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_SHIFT (4U)
-#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_MASK)
-#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_MASK (0x70000U)
-#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_SHIFT (16U)
-#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_MASK)
-
-/* The count of ENET_MTL_QUEUE_MTL_TXQX_OP_MODE */
-#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_COUNT (2U)
-
-/*! @name MTL_QUEUE_MTL_TXQX_UNDRFLW - MTL TxQx Underflow register */
-#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK (0x7FFU)
-#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT (0U)
-#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK)
-#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK (0x800U)
-#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT (11U)
-#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK)
-
-/* The count of ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW */
-#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_COUNT (2U)
-
-/*! @name MTL_QUEUE_MTL_TXQX_DBG - MTL TxQx Debug register */
-#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_MASK (0x1U)
-#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_SHIFT (0U)
-#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_MASK)
-#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_MASK (0x6U)
-#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_SHIFT (1U)
-#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_MASK)
-#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_MASK (0x8U)
-#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_SHIFT (3U)
-#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_MASK)
-#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_MASK (0x10U)
-#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_SHIFT (4U)
-#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_MASK)
-#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_MASK (0x20U)
-#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_SHIFT (5U)
-#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_MASK)
-#define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_MASK (0x70000U)
-#define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_SHIFT (16U)
-#define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_MASK)
-#define ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_MASK (0x700000U)
-#define ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_SHIFT (20U)
-#define ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_MASK)
-
-/* The count of ENET_MTL_QUEUE_MTL_TXQX_DBG */
-#define ENET_MTL_QUEUE_MTL_TXQX_DBG_COUNT (2U)
-
-/*! @name MTL_QUEUE_MTL_TXQX_ETS_CTRL - MTL TxQx ETS control register, only TxQ1 support */
-#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_MASK (0x4U)
-#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_SHIFT (2U)
-#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_MASK)
-#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_MASK (0x8U)
-#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_SHIFT (3U)
-#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_MASK)
-#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_MASK (0x70U)
-#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_SHIFT (4U)
-#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_MASK)
-
-/* The count of ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL */
-#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_COUNT (2U)
-
-/*! @name MTL_QUEUE_MTL_TXQX_ETS_STAT - MTL TxQx ETS Status register */
-#define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_MASK (0xFFFFFFU)
-#define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_SHIFT (0U)
-#define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_MASK)
-
-/* The count of ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT */
-#define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_COUNT (2U)
-
-/*! @name MTL_QUEUE_MTL_TXQX_QNTM_WGHT - */
-#define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_MASK (0x1FFFFFU)
-#define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT (0U)
-#define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_MASK)
-
-/* The count of ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT */
-#define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_COUNT (2U)
-
-/*! @name MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT - MTL TxQx SendSlopCredit register, only TxQ1 support */
-#define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_MASK (0x3FFFU)
-#define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT (0U)
-#define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_MASK)
-
-/* The count of ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT */
-#define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_COUNT (2U)
-
-/*! @name MTL_QUEUE_MTL_TXQX_HI_CRDT - MTL TxQx hiCredit register, only TxQ1 support */
-#define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_MASK (0x1FFFFFFFU)
-#define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_SHIFT (0U)
-#define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_MASK)
-
-/* The count of ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT */
-#define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_COUNT (2U)
-
-/*! @name MTL_QUEUE_MTL_TXQX_LO_CRDT - MTL TxQx loCredit register, only TxQ1 support */
-#define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_MASK (0x1FFFFFFFU)
-#define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_SHIFT (0U)
-#define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_MASK)
-
-/* The count of ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT */
-#define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_COUNT (2U)
-
-/*! @name MTL_QUEUE_MTL_TXQX_INTCTRL_STAT - */
-#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_MASK (0x1U)
-#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT (0U)
-#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_MASK)
-#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK (0x2U)
-#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT (1U)
-#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK)
-#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_MASK (0x100U)
-#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_SHIFT (8U)
-#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_MASK)
-#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_MASK (0x200U)
-#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_SHIFT (9U)
-#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_MASK)
-#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_MASK (0x10000U)
-#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT (16U)
-#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_MASK)
-#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_MASK (0x1000000U)
-#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_SHIFT (24U)
-#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_MASK)
-
-/* The count of ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT */
-#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_COUNT (2U)
-
-/*! @name MTL_QUEUE_MTL_RXQX_OP_MODE - MTL RxQx Operation Mode register */
-#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_MASK (0x3U)
-#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_SHIFT (0U)
-#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_MASK)
-#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_MASK (0x8U)
-#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_SHIFT (3U)
-#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_MASK)
-#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_MASK (0x10U)
-#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_SHIFT (4U)
-#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_MASK)
-#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_MASK (0x20U)
-#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_SHIFT (5U)
-#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_MASK)
-#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK (0x40U)
-#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT (6U)
-#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK)
-#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_MASK (0x700000U)
-#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_SHIFT (20U)
-#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_MASK)
-
-/* The count of ENET_MTL_QUEUE_MTL_RXQX_OP_MODE */
-#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_COUNT (2U)
-
-/*! @name MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT - MTL RxQx Missed Packet Overflow Counter register */
-#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK (0x7FFU)
-#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT (0U)
-#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK)
-#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK (0x800U)
-#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT (11U)
-#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK)
-
-/* The count of ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT */
-#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_COUNT (2U)
-
-/*! @name MTL_QUEUE_MTL_RXQX_DBG - MTL RxQx Debug register */
-#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_MASK (0x1U)
-#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_SHIFT (0U)
-#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_MASK)
-#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_MASK (0x6U)
-#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_SHIFT (1U)
-#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_MASK)
-#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_MASK (0x30U)
-#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_SHIFT (4U)
-#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_MASK)
-#define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_MASK (0x3FFF0000U)
-#define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_SHIFT (16U)
-#define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_MASK)
-
-/* The count of ENET_MTL_QUEUE_MTL_RXQX_DBG */
-#define ENET_MTL_QUEUE_MTL_RXQX_DBG_COUNT (2U)
-
-/*! @name MTL_QUEUE_MTL_RXQX_CTRL - MTL RxQx Control register */
-#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_MASK (0x7U)
-#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT (0U)
-#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_MASK)
-#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK (0x8U)
-#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT (3U)
-#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK)
-
-/* The count of ENET_MTL_QUEUE_MTL_RXQX_CTRL */
-#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_COUNT (2U)
-
-/*! @name DMA_MODE - DMA mode register */
-#define ENET_DMA_MODE_SWR_MASK (0x1U)
-#define ENET_DMA_MODE_SWR_SHIFT (0U)
-#define ENET_DMA_MODE_SWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_SWR_SHIFT)) & ENET_DMA_MODE_SWR_MASK)
-#define ENET_DMA_MODE_DA_MASK (0x2U)
-#define ENET_DMA_MODE_DA_SHIFT (1U)
-#define ENET_DMA_MODE_DA(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_DA_SHIFT)) & ENET_DMA_MODE_DA_MASK)
-#define ENET_DMA_MODE_TAA_MASK (0x1CU)
-#define ENET_DMA_MODE_TAA_SHIFT (2U)
-#define ENET_DMA_MODE_TAA(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_TAA_SHIFT)) & ENET_DMA_MODE_TAA_MASK)
-#define ENET_DMA_MODE_TXPR_MASK (0x800U)
-#define ENET_DMA_MODE_TXPR_SHIFT (11U)
-#define ENET_DMA_MODE_TXPR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_TXPR_SHIFT)) & ENET_DMA_MODE_TXPR_MASK)
-#define ENET_DMA_MODE_PR_MASK (0x7000U)
-#define ENET_DMA_MODE_PR_SHIFT (12U)
-#define ENET_DMA_MODE_PR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_PR_SHIFT)) & ENET_DMA_MODE_PR_MASK)
-
-/*! @name DMA_SYSBUS_MODE - DMA System Bus mode */
-#define ENET_DMA_SYSBUS_MODE_FB_MASK (0x1U)
-#define ENET_DMA_SYSBUS_MODE_FB_SHIFT (0U)
-#define ENET_DMA_SYSBUS_MODE_FB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_FB_SHIFT)) & ENET_DMA_SYSBUS_MODE_FB_MASK)
-#define ENET_DMA_SYSBUS_MODE_AAL_MASK (0x1000U)
-#define ENET_DMA_SYSBUS_MODE_AAL_SHIFT (12U)
-#define ENET_DMA_SYSBUS_MODE_AAL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_AAL_SHIFT)) & ENET_DMA_SYSBUS_MODE_AAL_MASK)
-#define ENET_DMA_SYSBUS_MODE_MB_MASK (0x4000U)
-#define ENET_DMA_SYSBUS_MODE_MB_SHIFT (14U)
-#define ENET_DMA_SYSBUS_MODE_MB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_MB_SHIFT)) & ENET_DMA_SYSBUS_MODE_MB_MASK)
-#define ENET_DMA_SYSBUS_MODE_RB_MASK (0x8000U)
-#define ENET_DMA_SYSBUS_MODE_RB_SHIFT (15U)
-#define ENET_DMA_SYSBUS_MODE_RB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_RB_SHIFT)) & ENET_DMA_SYSBUS_MODE_RB_MASK)
-
-/*! @name DMA_INTR_STAT - DMA Interrupt status */
-#define ENET_DMA_INTR_STAT_DC0IS_MASK (0x1U)
-#define ENET_DMA_INTR_STAT_DC0IS_SHIFT (0U)
-#define ENET_DMA_INTR_STAT_DC0IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_DC0IS_SHIFT)) & ENET_DMA_INTR_STAT_DC0IS_MASK)
-#define ENET_DMA_INTR_STAT_DC1IS_MASK (0x2U)
-#define ENET_DMA_INTR_STAT_DC1IS_SHIFT (1U)
-#define ENET_DMA_INTR_STAT_DC1IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_DC1IS_SHIFT)) & ENET_DMA_INTR_STAT_DC1IS_MASK)
-#define ENET_DMA_INTR_STAT_MTLIS_MASK (0x10000U)
-#define ENET_DMA_INTR_STAT_MTLIS_SHIFT (16U)
-#define ENET_DMA_INTR_STAT_MTLIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_MTLIS_SHIFT)) & ENET_DMA_INTR_STAT_MTLIS_MASK)
-#define ENET_DMA_INTR_STAT_MACIS_MASK (0x20000U)
-#define ENET_DMA_INTR_STAT_MACIS_SHIFT (17U)
-#define ENET_DMA_INTR_STAT_MACIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_MACIS_SHIFT)) & ENET_DMA_INTR_STAT_MACIS_MASK)
-
-/*! @name DMA_DBG_STAT - DMA Debug Status */
-#define ENET_DMA_DBG_STAT_AHSTS_MASK (0x1U)
-#define ENET_DMA_DBG_STAT_AHSTS_SHIFT (0U)
-#define ENET_DMA_DBG_STAT_AHSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_AHSTS_SHIFT)) & ENET_DMA_DBG_STAT_AHSTS_MASK)
-#define ENET_DMA_DBG_STAT_RPS0_MASK (0xF00U)
-#define ENET_DMA_DBG_STAT_RPS0_SHIFT (8U)
-#define ENET_DMA_DBG_STAT_RPS0(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_RPS0_SHIFT)) & ENET_DMA_DBG_STAT_RPS0_MASK)
-#define ENET_DMA_DBG_STAT_TPS0_MASK (0xF000U)
-#define ENET_DMA_DBG_STAT_TPS0_SHIFT (12U)
-#define ENET_DMA_DBG_STAT_TPS0(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_TPS0_SHIFT)) & ENET_DMA_DBG_STAT_TPS0_MASK)
-#define ENET_DMA_DBG_STAT_RPS1_MASK (0xF0000U)
-#define ENET_DMA_DBG_STAT_RPS1_SHIFT (16U)
-#define ENET_DMA_DBG_STAT_RPS1(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_RPS1_SHIFT)) & ENET_DMA_DBG_STAT_RPS1_MASK)
-#define ENET_DMA_DBG_STAT_TPS1_MASK (0xF00000U)
-#define ENET_DMA_DBG_STAT_TPS1_SHIFT (20U)
-#define ENET_DMA_DBG_STAT_TPS1(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_TPS1_SHIFT)) & ENET_DMA_DBG_STAT_TPS1_MASK)
-
-/*! @name DMA_CH_DMA_CHX_CTRL - DMA Channelx Control */
-#define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_MASK (0x10000U)
-#define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_SHIFT (16U)
-#define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_SHIFT)) & ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_MASK)
-#define ENET_DMA_CH_DMA_CHX_CTRL_DSL_MASK (0x1C0000U)
-#define ENET_DMA_CH_DMA_CHX_CTRL_DSL_SHIFT (18U)
-#define ENET_DMA_CH_DMA_CHX_CTRL_DSL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CTRL_DSL_SHIFT)) & ENET_DMA_CH_DMA_CHX_CTRL_DSL_MASK)
-
-/* The count of ENET_DMA_CH_DMA_CHX_CTRL */
-#define ENET_DMA_CH_DMA_CHX_CTRL_COUNT (2U)
-
-/*! @name DMA_CH_DMA_CHX_TX_CTRL - DMA Channelx Transmit Control */
-#define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK (0x1U)
-#define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_SHIFT (0U)
-#define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK)
-#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_MASK (0xEU)
-#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_SHIFT (1U)
-#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_MASK)
-#define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_MASK (0x10U)
-#define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_SHIFT (4U)
-#define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_MASK)
-#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_MASK (0x3F0000U)
-#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_SHIFT (16U)
-#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_MASK)
-
-/* The count of ENET_DMA_CH_DMA_CHX_TX_CTRL */
-#define ENET_DMA_CH_DMA_CHX_TX_CTRL_COUNT (2U)
-
-/*! @name DMA_CH_DMA_CHX_RX_CTRL - DMA Channelx Receive Control */
-#define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_MASK (0x1U)
-#define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_SHIFT (0U)
-#define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_MASK)
-#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_MASK (0x7FF8U)
-#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_SHIFT (3U)
-#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_MASK)
-#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_MASK (0x3F0000U)
-#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_SHIFT (16U)
-#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_MASK)
-#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_MASK (0x80000000U)
-#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_SHIFT (31U)
-#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_MASK)
-
-/* The count of ENET_DMA_CH_DMA_CHX_RX_CTRL */
-#define ENET_DMA_CH_DMA_CHX_RX_CTRL_COUNT (2U)
-
-/*! @name DMA_CH_DMA_CHX_TXDESC_LIST_ADDR - */
-#define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_MASK (0xFFFFFFFCU)
-#define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_SHIFT (2U)
-#define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_MASK)
-
-/* The count of ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR */
-#define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_COUNT (2U)
-
-/*! @name DMA_CH_DMA_CHX_RXDESC_LIST_ADDR - */
-#define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_MASK (0xFFFFFFFCU)
-#define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_SHIFT (2U)
-#define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_MASK)
-
-/* The count of ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR */
-#define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_COUNT (2U)
-
-/*! @name DMA_CH_DMA_CHX_TXDESC_TAIL_PTR - */
-#define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK (0xFFFFFFFCU)
-#define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT (2U)
-#define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK)
-
-/* The count of ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR */
-#define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_COUNT (2U)
-
-/*! @name DMA_CH_DMA_CHX_RXDESC_TAIL_PTR - */
-#define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK (0xFFFFFFFCU)
-#define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT (2U)
-#define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK)
-
-/* The count of ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR */
-#define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_COUNT (2U)
-
-/*! @name DMA_CH_DMA_CHX_TXDESC_RING_LENGTH - */
-#define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK (0x3FFU)
-#define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT (0U)
-#define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK)
-
-/* The count of ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH */
-#define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_COUNT (2U)
-
-/*! @name DMA_CH_DMA_CHX_RXDESC_RING_LENGTH - Channelx Rx descriptor Ring Length */
-#define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK (0x3FFU)
-#define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_SHIFT (0U)
-#define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK)
-
-/* The count of ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH */
-#define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_COUNT (2U)
-
-/*! @name DMA_CH_DMA_CHX_INT_EN - Channelx Interrupt Enable */
-#define ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK (0x1U)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_TIE_SHIFT (0U)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_TSE_MASK (0x2U)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_TSE_SHIFT (1U)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_TSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TSE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TSE_MASK)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_MASK (0x4U)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_SHIFT (2U)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_MASK)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK (0x40U)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_RIE_SHIFT (6U)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_RIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_MASK (0x80U)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_SHIFT (7U)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_MASK)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_RSE_MASK (0x100U)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_RSE_SHIFT (8U)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_RSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RSE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RSE_MASK)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_MASK (0x200U)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_SHIFT (9U)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_MASK)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_MASK (0x400U)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_SHIFT (10U)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_MASK)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_MASK (0x800U)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_SHIFT (11U)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_MASK)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_MASK (0x1000U)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_SHIFT (12U)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_MASK)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_AIE_MASK (0x4000U)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_AIE_SHIFT (14U)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_AIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_AIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_AIE_MASK)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_NIE_MASK (0x8000U)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_NIE_SHIFT (15U)
-#define ENET_DMA_CH_DMA_CHX_INT_EN_NIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_NIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_NIE_MASK)
-
-/* The count of ENET_DMA_CH_DMA_CHX_INT_EN */
-#define ENET_DMA_CH_DMA_CHX_INT_EN_COUNT (2U)
-
-/*! @name DMA_CH_DMA_CHX_RX_INT_WDTIMER - Receive Interrupt Watchdog Timer */
-#define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_MASK (0xFFU)
-#define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_SHIFT (0U)
-#define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_MASK)
-
-/* The count of ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER */
-#define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_COUNT (2U)
-
-/*! @name DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT - Slot Function Control and Status */
-#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK (0x1U)
-#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT (0U)
-#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK)
-#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK (0x2U)
-#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT (1U)
-#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK)
-#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK (0xF0000U)
-#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT (16U)
-#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK)
-
-/* The count of ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT */
-#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_COUNT (2U)
-
-/*! @name DMA_CH_DMA_CHX_CUR_HST_TXDESC - Channelx Current Host Transmit descriptor */
-#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_MASK (0xFFFFFFFFU)
-#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_SHIFT (0U)
-#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_MASK)
-
-/* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC */
-#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_COUNT (2U)
-
-/*! @name DMA_CH_DMA_CHX_CUR_HST_RXDESC - */
-#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_MASK (0xFFFFFFFFU)
-#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_SHIFT (0U)
-#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_MASK)
-
-/* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC */
-#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_COUNT (2U)
-
-/*! @name DMA_CH_DMA_CHX_CUR_HST_TXBUF - */
-#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_MASK (0xFFFFFFFFU)
-#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_SHIFT (0U)
-#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_MASK)
-
-/* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF */
-#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_COUNT (2U)
-
-/*! @name DMA_CH_DMA_CHX_CUR_HST_RXBUF - Channelx Current Application Receive Buffer Address */
-#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_MASK (0xFFFFFFFFU)
-#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_SHIFT (0U)
-#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_MASK)
-
-/* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF */
-#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_COUNT (2U)
-
-/*! @name DMA_CH_DMA_CHX_STAT - Channelx DMA status register */
-#define ENET_DMA_CH_DMA_CHX_STAT_TI_MASK (0x1U)
-#define ENET_DMA_CH_DMA_CHX_STAT_TI_SHIFT (0U)
-#define ENET_DMA_CH_DMA_CHX_STAT_TI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TI_MASK)
-#define ENET_DMA_CH_DMA_CHX_STAT_TPS_MASK (0x2U)
-#define ENET_DMA_CH_DMA_CHX_STAT_TPS_SHIFT (1U)
-#define ENET_DMA_CH_DMA_CHX_STAT_TPS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TPS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TPS_MASK)
-#define ENET_DMA_CH_DMA_CHX_STAT_TBU_MASK (0x4U)
-#define ENET_DMA_CH_DMA_CHX_STAT_TBU_SHIFT (2U)
-#define ENET_DMA_CH_DMA_CHX_STAT_TBU(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TBU_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TBU_MASK)
-#define ENET_DMA_CH_DMA_CHX_STAT_RI_MASK (0x40U)
-#define ENET_DMA_CH_DMA_CHX_STAT_RI_SHIFT (6U)
-#define ENET_DMA_CH_DMA_CHX_STAT_RI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RI_MASK)
-#define ENET_DMA_CH_DMA_CHX_STAT_RBU_MASK (0x80U)
-#define ENET_DMA_CH_DMA_CHX_STAT_RBU_SHIFT (7U)
-#define ENET_DMA_CH_DMA_CHX_STAT_RBU(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RBU_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RBU_MASK)
-#define ENET_DMA_CH_DMA_CHX_STAT_RPS_MASK (0x100U)
-#define ENET_DMA_CH_DMA_CHX_STAT_RPS_SHIFT (8U)
-#define ENET_DMA_CH_DMA_CHX_STAT_RPS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RPS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RPS_MASK)
-#define ENET_DMA_CH_DMA_CHX_STAT_RWT_MASK (0x200U)
-#define ENET_DMA_CH_DMA_CHX_STAT_RWT_SHIFT (9U)
-#define ENET_DMA_CH_DMA_CHX_STAT_RWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RWT_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RWT_MASK)
-#define ENET_DMA_CH_DMA_CHX_STAT_ETI_MASK (0x400U)
-#define ENET_DMA_CH_DMA_CHX_STAT_ETI_SHIFT (10U)
-#define ENET_DMA_CH_DMA_CHX_STAT_ETI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_ETI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_ETI_MASK)
-#define ENET_DMA_CH_DMA_CHX_STAT_ERI_MASK (0x800U)
-#define ENET_DMA_CH_DMA_CHX_STAT_ERI_SHIFT (11U)
-#define ENET_DMA_CH_DMA_CHX_STAT_ERI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_ERI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_ERI_MASK)
-#define ENET_DMA_CH_DMA_CHX_STAT_FBE_MASK (0x1000U)
-#define ENET_DMA_CH_DMA_CHX_STAT_FBE_SHIFT (12U)
-#define ENET_DMA_CH_DMA_CHX_STAT_FBE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_FBE_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_FBE_MASK)
-#define ENET_DMA_CH_DMA_CHX_STAT_AIS_MASK (0x4000U)
-#define ENET_DMA_CH_DMA_CHX_STAT_AIS_SHIFT (14U)
-#define ENET_DMA_CH_DMA_CHX_STAT_AIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_AIS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_AIS_MASK)
-#define ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK (0x8000U)
-#define ENET_DMA_CH_DMA_CHX_STAT_NIS_SHIFT (15U)
-#define ENET_DMA_CH_DMA_CHX_STAT_NIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_NIS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK)
-#define ENET_DMA_CH_DMA_CHX_STAT_EB_MASK (0x70000U)
-#define ENET_DMA_CH_DMA_CHX_STAT_EB_SHIFT (16U)
-#define ENET_DMA_CH_DMA_CHX_STAT_EB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_EB_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_EB_MASK)
-
-/* The count of ENET_DMA_CH_DMA_CHX_STAT */
-#define ENET_DMA_CH_DMA_CHX_STAT_COUNT (2U)
-
-
-/*!
- * @}
- */ /* end of group ENET_Register_Masks */
-
-
-/* ENET - Peripheral instance base addresses */
-/** Peripheral ENET base address */
-#define ENET_BASE (0x40092000u)
-/** Peripheral ENET base pointer */
-#define ENET ((ENET_Type *)ENET_BASE)
-/** Array initializer of ENET peripheral base addresses */
-#define ENET_BASE_ADDRS { ENET_BASE }
-/** Array initializer of ENET peripheral base pointers */
-#define ENET_BASE_PTRS { ENET }
-/** Interrupt vectors for the ENET peripheral type */
-#define ENET_IRQS { ETHERNET_IRQn }
-#define ENET_PMT_IRQS { ETHERNET_PMT_IRQn }
-#define ENET_MACLP_IRQS { ETHERNET_MACLP_IRQn }
-
-/*!
- * @}
- */ /* end of group ENET_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- FLEXCOMM Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FLEXCOMM_Peripheral_Access_Layer FLEXCOMM Peripheral Access Layer
- * @{
- */
-
-/** FLEXCOMM - Register Layout Typedef */
-typedef struct {
- uint8_t RESERVED_0[4088];
- __IO uint32_t PSELID; /**< Peripheral Select and Flexcomm ID register., offset: 0xFF8 */
- __IO uint32_t PID; /**< Peripheral identification register., offset: 0xFFC */
-} FLEXCOMM_Type;
-
-/* ----------------------------------------------------------------------------
- -- FLEXCOMM Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FLEXCOMM_Register_Masks FLEXCOMM Register Masks
- * @{
- */
-
-/*! @name PSELID - Peripheral Select and Flexcomm ID register. */
-#define FLEXCOMM_PSELID_PERSEL_MASK (0x7U)
-#define FLEXCOMM_PSELID_PERSEL_SHIFT (0U)
-#define FLEXCOMM_PSELID_PERSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK)
-#define FLEXCOMM_PSELID_LOCK_MASK (0x8U)
-#define FLEXCOMM_PSELID_LOCK_SHIFT (3U)
-#define FLEXCOMM_PSELID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK)
-#define FLEXCOMM_PSELID_USARTPRESENT_MASK (0x10U)
-#define FLEXCOMM_PSELID_USARTPRESENT_SHIFT (4U)
-#define FLEXCOMM_PSELID_USARTPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK)
-#define FLEXCOMM_PSELID_SPIPRESENT_MASK (0x20U)
-#define FLEXCOMM_PSELID_SPIPRESENT_SHIFT (5U)
-#define FLEXCOMM_PSELID_SPIPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK)
-#define FLEXCOMM_PSELID_I2CPRESENT_MASK (0x40U)
-#define FLEXCOMM_PSELID_I2CPRESENT_SHIFT (6U)
-#define FLEXCOMM_PSELID_I2CPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK)
-#define FLEXCOMM_PSELID_I2SPRESENT_MASK (0x80U)
-#define FLEXCOMM_PSELID_I2SPRESENT_SHIFT (7U)
-#define FLEXCOMM_PSELID_I2SPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK)
-#define FLEXCOMM_PSELID_ID_MASK (0xFFFFF000U)
-#define FLEXCOMM_PSELID_ID_SHIFT (12U)
-#define FLEXCOMM_PSELID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK)
-
-/*! @name PID - Peripheral identification register. */
-#define FLEXCOMM_PID_Minor_Rev_MASK (0xF00U)
-#define FLEXCOMM_PID_Minor_Rev_SHIFT (8U)
-#define FLEXCOMM_PID_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Minor_Rev_SHIFT)) & FLEXCOMM_PID_Minor_Rev_MASK)
-#define FLEXCOMM_PID_Major_Rev_MASK (0xF000U)
-#define FLEXCOMM_PID_Major_Rev_SHIFT (12U)
-#define FLEXCOMM_PID_Major_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Major_Rev_SHIFT)) & FLEXCOMM_PID_Major_Rev_MASK)
-#define FLEXCOMM_PID_ID_MASK (0xFFFF0000U)
-#define FLEXCOMM_PID_ID_SHIFT (16U)
-#define FLEXCOMM_PID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK)
-
-
-/*!
- * @}
- */ /* end of group FLEXCOMM_Register_Masks */
-
-
-/* FLEXCOMM - Peripheral instance base addresses */
-/** Peripheral FLEXCOMM0 base address */
-#define FLEXCOMM0_BASE (0x40086000u)
-/** Peripheral FLEXCOMM0 base pointer */
-#define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE)
-/** Peripheral FLEXCOMM1 base address */
-#define FLEXCOMM1_BASE (0x40087000u)
-/** Peripheral FLEXCOMM1 base pointer */
-#define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE)
-/** Peripheral FLEXCOMM2 base address */
-#define FLEXCOMM2_BASE (0x40088000u)
-/** Peripheral FLEXCOMM2 base pointer */
-#define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE)
-/** Peripheral FLEXCOMM3 base address */
-#define FLEXCOMM3_BASE (0x40089000u)
-/** Peripheral FLEXCOMM3 base pointer */
-#define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE)
-/** Peripheral FLEXCOMM4 base address */
-#define FLEXCOMM4_BASE (0x4008A000u)
-/** Peripheral FLEXCOMM4 base pointer */
-#define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE)
-/** Peripheral FLEXCOMM5 base address */
-#define FLEXCOMM5_BASE (0x40096000u)
-/** Peripheral FLEXCOMM5 base pointer */
-#define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE)
-/** Peripheral FLEXCOMM6 base address */
-#define FLEXCOMM6_BASE (0x40097000u)
-/** Peripheral FLEXCOMM6 base pointer */
-#define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE)
-/** Peripheral FLEXCOMM7 base address */
-#define FLEXCOMM7_BASE (0x40098000u)
-/** Peripheral FLEXCOMM7 base pointer */
-#define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE)
-/** Peripheral FLEXCOMM8 base address */
-#define FLEXCOMM8_BASE (0x40099000u)
-/** Peripheral FLEXCOMM8 base pointer */
-#define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE)
-/** Peripheral FLEXCOMM9 base address */
-#define FLEXCOMM9_BASE (0x4009A000u)
-/** Peripheral FLEXCOMM9 base pointer */
-#define FLEXCOMM9 ((FLEXCOMM_Type *)FLEXCOMM9_BASE)
-/** Array initializer of FLEXCOMM peripheral base addresses */
-#define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE, FLEXCOMM9_BASE }
-/** Array initializer of FLEXCOMM peripheral base pointers */
-#define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, FLEXCOMM9 }
-/** Interrupt vectors for the FLEXCOMM peripheral type */
-#define FLEXCOMM_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn }
-
-/*!
- * @}
- */ /* end of group FLEXCOMM_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- FMC Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
- * @{
- */
-
-/** FMC - Register Layout Typedef */
-typedef struct {
- __IO uint32_t FCTR; /**< Control register, offset: 0x0 */
- uint8_t RESERVED_0[12];
- __IO uint32_t FBWST; /**< Wait state register, offset: 0x10 */
- uint8_t RESERVED_1[12];
- __IO uint32_t FMSSTART; /**< Signature start address register, offset: 0x20 */
- __IO uint32_t FMSSTOP; /**< Signature stop-address register, offset: 0x24 */
- uint8_t RESERVED_2[4];
- __I uint32_t FMSW[4]; /**< Words of 128-bit signature word, array offset: 0x2C, array step: 0x4 */
- uint8_t RESERVED_3[4004];
- __I uint32_t FMSTAT; /**< Signature generation status register, offset: 0xFE0 */
- uint8_t RESERVED_4[4];
- __O uint32_t FMSTATCLR; /**< Signature generation status clear register, offset: 0xFE8 */
-} FMC_Type;
-
-/* ----------------------------------------------------------------------------
- -- FMC Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup FMC_Register_Masks FMC Register Masks
- * @{
- */
-
-/*! @name FCTR - Control register */
-#define FMC_FCTR_FS_RD0_MASK (0x8U)
-#define FMC_FCTR_FS_RD0_SHIFT (3U)
-#define FMC_FCTR_FS_RD0(x) (((uint32_t)(((uint32_t)(x)) << FMC_FCTR_FS_RD0_SHIFT)) & FMC_FCTR_FS_RD0_MASK)
-#define FMC_FCTR_FS_RD1_MASK (0x10U)
-#define FMC_FCTR_FS_RD1_SHIFT (4U)
-#define FMC_FCTR_FS_RD1(x) (((uint32_t)(((uint32_t)(x)) << FMC_FCTR_FS_RD1_SHIFT)) & FMC_FCTR_FS_RD1_MASK)
-
-/*! @name FBWST - Wait state register */
-#define FMC_FBWST_WAITSTATES_MASK (0xFFU)
-#define FMC_FBWST_WAITSTATES_SHIFT (0U)
-#define FMC_FBWST_WAITSTATES(x) (((uint32_t)(((uint32_t)(x)) << FMC_FBWST_WAITSTATES_SHIFT)) & FMC_FBWST_WAITSTATES_MASK)
-
-/*! @name FMSSTART - Signature start address register */
-#define FMC_FMSSTART_START_MASK (0x1FFFFU)
-#define FMC_FMSSTART_START_SHIFT (0U)
-#define FMC_FMSSTART_START(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSSTART_START_SHIFT)) & FMC_FMSSTART_START_MASK)
-
-/*! @name FMSSTOP - Signature stop-address register */
-#define FMC_FMSSTOP_STOP_MASK (0x1FFFFU)
-#define FMC_FMSSTOP_STOP_SHIFT (0U)
-#define FMC_FMSSTOP_STOP(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSSTOP_STOP_SHIFT)) & FMC_FMSSTOP_STOP_MASK)
-#define FMC_FMSSTOP_SIG_START_MASK (0x20000U)
-#define FMC_FMSSTOP_SIG_START_SHIFT (17U)
-#define FMC_FMSSTOP_SIG_START(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSSTOP_SIG_START_SHIFT)) & FMC_FMSSTOP_SIG_START_MASK)
-
-/*! @name FMSW - Words of 128-bit signature word */
-#define FMC_FMSW_SW_MASK (0xFFFFFFFFU)
-#define FMC_FMSW_SW_SHIFT (0U)
-#define FMC_FMSW_SW(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSW_SW_SHIFT)) & FMC_FMSW_SW_MASK)
-
-/* The count of FMC_FMSW */
-#define FMC_FMSW_COUNT (4U)
-
-/*! @name FMSTAT - Signature generation status register */
-#define FMC_FMSTAT_SIG_DONE_MASK (0x4U)
-#define FMC_FMSTAT_SIG_DONE_SHIFT (2U)
-#define FMC_FMSTAT_SIG_DONE(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSTAT_SIG_DONE_SHIFT)) & FMC_FMSTAT_SIG_DONE_MASK)
-
-/*! @name FMSTATCLR - Signature generation status clear register */
-#define FMC_FMSTATCLR_SIG_DONE_CLR_MASK (0x4U)
-#define FMC_FMSTATCLR_SIG_DONE_CLR_SHIFT (2U)
-#define FMC_FMSTATCLR_SIG_DONE_CLR(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSTATCLR_SIG_DONE_CLR_SHIFT)) & FMC_FMSTATCLR_SIG_DONE_CLR_MASK)
-
-
-/*!
- * @}
- */ /* end of group FMC_Register_Masks */
-
-
-/* FMC - Peripheral instance base addresses */
-/** Peripheral FMC base address */
-#define FMC_BASE (0x40034000u)
-/** Peripheral FMC base pointer */
-#define FMC ((FMC_Type *)FMC_BASE)
-/** Array initializer of FMC peripheral base addresses */
-#define FMC_BASE_ADDRS { FMC_BASE }
-/** Array initializer of FMC peripheral base pointers */
-#define FMC_BASE_PTRS { FMC }
-
-/*!
- * @}
- */ /* end of group FMC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- GINT Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup GINT_Peripheral_Access_Layer GINT Peripheral Access Layer
- * @{
- */
-
-/** GINT - Register Layout Typedef */
-typedef struct {
- __IO uint32_t CTRL; /**< GPIO grouped interrupt control register, offset: 0x0 */
- uint8_t RESERVED_0[28];
- __IO uint32_t PORT_POL[2]; /**< GPIO grouped interrupt port 0 polarity register, array offset: 0x20, array step: 0x4 */
- uint8_t RESERVED_1[24];
- __IO uint32_t PORT_ENA[2]; /**< GPIO grouped interrupt port 0 enable register, array offset: 0x40, array step: 0x4 */
-} GINT_Type;
-
-/* ----------------------------------------------------------------------------
- -- GINT Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup GINT_Register_Masks GINT Register Masks
- * @{
- */
-
-/*! @name CTRL - GPIO grouped interrupt control register */
-#define GINT_CTRL_INT_MASK (0x1U)
-#define GINT_CTRL_INT_SHIFT (0U)
-#define GINT_CTRL_INT(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK)
-#define GINT_CTRL_COMB_MASK (0x2U)
-#define GINT_CTRL_COMB_SHIFT (1U)
-#define GINT_CTRL_COMB(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_COMB_SHIFT)) & GINT_CTRL_COMB_MASK)
-#define GINT_CTRL_TRIG_MASK (0x4U)
-#define GINT_CTRL_TRIG_SHIFT (2U)
-#define GINT_CTRL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_TRIG_SHIFT)) & GINT_CTRL_TRIG_MASK)
-
-/*! @name PORT_POL - GPIO grouped interrupt port 0 polarity register */
-#define GINT_PORT_POL_POL_MASK (0xFFFFFFFFU)
-#define GINT_PORT_POL_POL_SHIFT (0U)
-#define GINT_PORT_POL_POL(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL_SHIFT)) & GINT_PORT_POL_POL_MASK)
-
-/* The count of GINT_PORT_POL */
-#define GINT_PORT_POL_COUNT (2U)
-
-/*! @name PORT_ENA - GPIO grouped interrupt port 0 enable register */
-#define GINT_PORT_ENA_ENA_MASK (0xFFFFFFFFU)
-#define GINT_PORT_ENA_ENA_SHIFT (0U)
-#define GINT_PORT_ENA_ENA(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA_SHIFT)) & GINT_PORT_ENA_ENA_MASK)
-
-/* The count of GINT_PORT_ENA */
-#define GINT_PORT_ENA_COUNT (2U)
-
-
-/*!
- * @}
- */ /* end of group GINT_Register_Masks */
-
-
-/* GINT - Peripheral instance base addresses */
-/** Peripheral GINT0 base address */
-#define GINT0_BASE (0x40002000u)
-/** Peripheral GINT0 base pointer */
-#define GINT0 ((GINT_Type *)GINT0_BASE)
-/** Peripheral GINT1 base address */
-#define GINT1_BASE (0x40003000u)
-/** Peripheral GINT1 base pointer */
-#define GINT1 ((GINT_Type *)GINT1_BASE)
-/** Array initializer of GINT peripheral base addresses */
-#define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE }
-/** Array initializer of GINT peripheral base pointers */
-#define GINT_BASE_PTRS { GINT0, GINT1 }
-/** Interrupt vectors for the GINT peripheral type */
-#define GINT_IRQS { GINT0_IRQn, GINT1_IRQn }
-
-/*!
- * @}
- */ /* end of group GINT_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- GPIO Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
- * @{
- */
-
-/** GPIO - Register Layout Typedef */
-typedef struct {
- __IO uint8_t B[6][32]; /**< Byte pin registers for all port 0 and 1 GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */
- uint8_t RESERVED_0[3904];
- __IO uint32_t W[6][32]; /**< Word pin registers for all port 0 and 1 GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */
- uint8_t RESERVED_1[3328];
- __IO uint32_t DIR[6]; /**< Direction registers, array offset: 0x2000, array step: 0x4 */
- uint8_t RESERVED_2[104];
- __IO uint32_t MASK[6]; /**< Mask register, array offset: 0x2080, array step: 0x4 */
- uint8_t RESERVED_3[104];
- __IO uint32_t PIN[6]; /**< Port pin register, array offset: 0x2100, array step: 0x4 */
- uint8_t RESERVED_4[104];
- __IO uint32_t MPIN[6]; /**< Masked port register, array offset: 0x2180, array step: 0x4 */
- uint8_t RESERVED_5[104];
- __IO uint32_t SET[6]; /**< Write: Set register for port Read: output bits for port, array offset: 0x2200, array step: 0x4 */
- uint8_t RESERVED_6[104];
- __O uint32_t CLR[6]; /**< Clear port, array offset: 0x2280, array step: 0x4 */
- uint8_t RESERVED_7[104];
- __O uint32_t NOT[6]; /**< Toggle port, array offset: 0x2300, array step: 0x4 */
- uint8_t RESERVED_8[104];
- __O uint32_t DIRSET[6]; /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */
- uint8_t RESERVED_9[104];
- __O uint32_t DIRCLR[6]; /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */
- uint8_t RESERVED_10[104];
- __O uint32_t DIRNOT[6]; /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */
-} GPIO_Type;
-
-/* ----------------------------------------------------------------------------
- -- GPIO Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup GPIO_Register_Masks GPIO Register Masks
- * @{
- */
-
-/*! @name B - Byte pin registers for all port 0 and 1 GPIO pins */
-#define GPIO_B_PBYTE_MASK (0x1U)
-#define GPIO_B_PBYTE_SHIFT (0U)
-#define GPIO_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK)
-
-/* The count of GPIO_B */
-#define GPIO_B_COUNT (6U)
-
-/* The count of GPIO_B */
-#define GPIO_B_COUNT2 (32U)
-
-/*! @name W - Word pin registers for all port 0 and 1 GPIO pins */
-#define GPIO_W_PWORD_MASK (0xFFFFFFFFU)
-#define GPIO_W_PWORD_SHIFT (0U)
-#define GPIO_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK)
-
-/* The count of GPIO_W */
-#define GPIO_W_COUNT (6U)
-
-/* The count of GPIO_W */
-#define GPIO_W_COUNT2 (32U)
-
-/*! @name DIR - Direction registers */
-#define GPIO_DIR_DIRP_MASK (0xFFFFFFFFU)
-#define GPIO_DIR_DIRP_SHIFT (0U)
-#define GPIO_DIR_DIRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK)
-
-/* The count of GPIO_DIR */
-#define GPIO_DIR_COUNT (6U)
-
-/*! @name MASK - Mask register */
-#define GPIO_MASK_MASKP_MASK (0xFFFFFFFFU)
-#define GPIO_MASK_MASKP_SHIFT (0U)
-#define GPIO_MASK_MASKP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK)
-
-/* The count of GPIO_MASK */
-#define GPIO_MASK_COUNT (6U)
-
-/*! @name PIN - Port pin register */
-#define GPIO_PIN_PORT_MASK (0xFFFFFFFFU)
-#define GPIO_PIN_PORT_SHIFT (0U)
-#define GPIO_PIN_PORT(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK)
-
-/* The count of GPIO_PIN */
-#define GPIO_PIN_COUNT (6U)
-
-/*! @name MPIN - Masked port register */
-#define GPIO_MPIN_MPORTP_MASK (0xFFFFFFFFU)
-#define GPIO_MPIN_MPORTP_SHIFT (0U)
-#define GPIO_MPIN_MPORTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK)
-
-/* The count of GPIO_MPIN */
-#define GPIO_MPIN_COUNT (6U)
-
-/*! @name SET - Write: Set register for port Read: output bits for port */
-#define GPIO_SET_SETP_MASK (0xFFFFFFFFU)
-#define GPIO_SET_SETP_SHIFT (0U)
-#define GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK)
-
-/* The count of GPIO_SET */
-#define GPIO_SET_COUNT (6U)
-
-/*! @name CLR - Clear port */
-#define GPIO_CLR_CLRP_MASK (0xFFFFFFFFU)
-#define GPIO_CLR_CLRP_SHIFT (0U)
-#define GPIO_CLR_CLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK)
-
-/* The count of GPIO_CLR */
-#define GPIO_CLR_COUNT (6U)
-
-/*! @name NOT - Toggle port */
-#define GPIO_NOT_NOTP_MASK (0xFFFFFFFFU)
-#define GPIO_NOT_NOTP_SHIFT (0U)
-#define GPIO_NOT_NOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK)
-
-/* The count of GPIO_NOT */
-#define GPIO_NOT_COUNT (6U)
-
-/*! @name DIRSET - Set pin direction bits for port */
-#define GPIO_DIRSET_DIRSETP_MASK (0x1FFFFFFFU)
-#define GPIO_DIRSET_DIRSETP_SHIFT (0U)
-#define GPIO_DIRSET_DIRSETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK)
-
-/* The count of GPIO_DIRSET */
-#define GPIO_DIRSET_COUNT (6U)
-
-/*! @name DIRCLR - Clear pin direction bits for port */
-#define GPIO_DIRCLR_DIRCLRP_MASK (0x1FFFFFFFU)
-#define GPIO_DIRCLR_DIRCLRP_SHIFT (0U)
-#define GPIO_DIRCLR_DIRCLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK)
-
-/* The count of GPIO_DIRCLR */
-#define GPIO_DIRCLR_COUNT (6U)
-
-/*! @name DIRNOT - Toggle pin direction bits for port */
-#define GPIO_DIRNOT_DIRNOTP_MASK (0x1FFFFFFFU)
-#define GPIO_DIRNOT_DIRNOTP_SHIFT (0U)
-#define GPIO_DIRNOT_DIRNOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK)
-
-/* The count of GPIO_DIRNOT */
-#define GPIO_DIRNOT_COUNT (6U)
-
-
-/*!
- * @}
- */ /* end of group GPIO_Register_Masks */
-
-
-/* GPIO - Peripheral instance base addresses */
-/** Peripheral GPIO base address */
-#define GPIO_BASE (0x4008C000u)
-/** Peripheral GPIO base pointer */
-#define GPIO ((GPIO_Type *)GPIO_BASE)
-/** Array initializer of GPIO peripheral base addresses */
-#define GPIO_BASE_ADDRS { GPIO_BASE }
-/** Array initializer of GPIO peripheral base pointers */
-#define GPIO_BASE_PTRS { GPIO }
-
-/*!
- * @}
- */ /* end of group GPIO_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- I2C Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
- * @{
- */
-
-/** I2C - Register Layout Typedef */
-typedef struct {
- uint8_t RESERVED_0[2048];
- __IO uint32_t CFG; /**< Configuration for shared functions., offset: 0x800 */
- __IO uint32_t STAT; /**< Status register for Master, Slave, and Monitor functions., offset: 0x804 */
- __IO uint32_t INTENSET; /**< Interrupt Enable Set and read register., offset: 0x808 */
- __O uint32_t INTENCLR; /**< Interrupt Enable Clear register., offset: 0x80C */
- __IO uint32_t TIMEOUT; /**< Time-out value register., offset: 0x810 */
- __IO uint32_t CLKDIV; /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function., offset: 0x814 */
- __I uint32_t INTSTAT; /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x818 */
- uint8_t RESERVED_1[4];
- __IO uint32_t MSTCTL; /**< Master control register., offset: 0x820 */
- __IO uint32_t MSTTIME; /**< Master timing configuration., offset: 0x824 */
- __IO uint32_t MSTDAT; /**< Combined Master receiver and transmitter data register., offset: 0x828 */
- uint8_t RESERVED_2[20];
- __IO uint32_t SLVCTL; /**< Slave control register., offset: 0x840 */
- __IO uint32_t SLVDAT; /**< Combined Slave receiver and transmitter data register., offset: 0x844 */
- __IO uint32_t SLVADR[4]; /**< Slave address register., array offset: 0x848, array step: 0x4 */
- __IO uint32_t SLVQUAL0; /**< Slave Qualification for address 0., offset: 0x858 */
- uint8_t RESERVED_3[36];
- __I uint32_t MONRXDAT; /**< Monitor receiver data register., offset: 0x880 */
- uint8_t RESERVED_4[1912];
- __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */
-} I2C_Type;
-
-/* ----------------------------------------------------------------------------
- -- I2C Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup I2C_Register_Masks I2C Register Masks
- * @{
- */
-
-/*! @name CFG - Configuration for shared functions. */
-#define I2C_CFG_MSTEN_MASK (0x1U)
-#define I2C_CFG_MSTEN_SHIFT (0U)
-#define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK)
-#define I2C_CFG_SLVEN_MASK (0x2U)
-#define I2C_CFG_SLVEN_SHIFT (1U)
-#define I2C_CFG_SLVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK)
-#define I2C_CFG_MONEN_MASK (0x4U)
-#define I2C_CFG_MONEN_SHIFT (2U)
-#define I2C_CFG_MONEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK)
-#define I2C_CFG_TIMEOUTEN_MASK (0x8U)
-#define I2C_CFG_TIMEOUTEN_SHIFT (3U)
-#define I2C_CFG_TIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK)
-#define I2C_CFG_MONCLKSTR_MASK (0x10U)
-#define I2C_CFG_MONCLKSTR_SHIFT (4U)
-#define I2C_CFG_MONCLKSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK)
-#define I2C_CFG_HSCAPABLE_MASK (0x20U)
-#define I2C_CFG_HSCAPABLE_SHIFT (5U)
-#define I2C_CFG_HSCAPABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_HSCAPABLE_SHIFT)) & I2C_CFG_HSCAPABLE_MASK)
-
-/*! @name STAT - Status register for Master, Slave, and Monitor functions. */
-#define I2C_STAT_MSTPENDING_MASK (0x1U)
-#define I2C_STAT_MSTPENDING_SHIFT (0U)
-#define I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK)
-#define I2C_STAT_MSTSTATE_MASK (0xEU)
-#define I2C_STAT_MSTSTATE_SHIFT (1U)
-#define I2C_STAT_MSTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK)
-#define I2C_STAT_MSTARBLOSS_MASK (0x10U)
-#define I2C_STAT_MSTARBLOSS_SHIFT (4U)
-#define I2C_STAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK)
-#define I2C_STAT_MSTSTSTPERR_MASK (0x40U)
-#define I2C_STAT_MSTSTSTPERR_SHIFT (6U)
-#define I2C_STAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK)
-#define I2C_STAT_SLVPENDING_MASK (0x100U)
-#define I2C_STAT_SLVPENDING_SHIFT (8U)
-#define I2C_STAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK)
-#define I2C_STAT_SLVSTATE_MASK (0x600U)
-#define I2C_STAT_SLVSTATE_SHIFT (9U)
-#define I2C_STAT_SLVSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK)
-#define I2C_STAT_SLVNOTSTR_MASK (0x800U)
-#define I2C_STAT_SLVNOTSTR_SHIFT (11U)
-#define I2C_STAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK)
-#define I2C_STAT_SLVIDX_MASK (0x3000U)
-#define I2C_STAT_SLVIDX_SHIFT (12U)
-#define I2C_STAT_SLVIDX(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK)
-#define I2C_STAT_SLVSEL_MASK (0x4000U)
-#define I2C_STAT_SLVSEL_SHIFT (14U)
-#define I2C_STAT_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK)
-#define I2C_STAT_SLVDESEL_MASK (0x8000U)
-#define I2C_STAT_SLVDESEL_SHIFT (15U)
-#define I2C_STAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK)
-#define I2C_STAT_MONRDY_MASK (0x10000U)
-#define I2C_STAT_MONRDY_SHIFT (16U)
-#define I2C_STAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK)
-#define I2C_STAT_MONOV_MASK (0x20000U)
-#define I2C_STAT_MONOV_SHIFT (17U)
-#define I2C_STAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK)
-#define I2C_STAT_MONACTIVE_MASK (0x40000U)
-#define I2C_STAT_MONACTIVE_SHIFT (18U)
-#define I2C_STAT_MONACTIVE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK)
-#define I2C_STAT_MONIDLE_MASK (0x80000U)
-#define I2C_STAT_MONIDLE_SHIFT (19U)
-#define I2C_STAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK)
-#define I2C_STAT_EVENTTIMEOUT_MASK (0x1000000U)
-#define I2C_STAT_EVENTTIMEOUT_SHIFT (24U)
-#define I2C_STAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK)
-#define I2C_STAT_SCLTIMEOUT_MASK (0x2000000U)
-#define I2C_STAT_SCLTIMEOUT_SHIFT (25U)
-#define I2C_STAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK)
-
-/*! @name INTENSET - Interrupt Enable Set and read register. */
-#define I2C_INTENSET_MSTPENDINGEN_MASK (0x1U)
-#define I2C_INTENSET_MSTPENDINGEN_SHIFT (0U)
-#define I2C_INTENSET_MSTPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK)
-#define I2C_INTENSET_MSTARBLOSSEN_MASK (0x10U)
-#define I2C_INTENSET_MSTARBLOSSEN_SHIFT (4U)
-#define I2C_INTENSET_MSTARBLOSSEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK)
-#define I2C_INTENSET_MSTSTSTPERREN_MASK (0x40U)
-#define I2C_INTENSET_MSTSTSTPERREN_SHIFT (6U)
-#define I2C_INTENSET_MSTSTSTPERREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK)
-#define I2C_INTENSET_SLVPENDINGEN_MASK (0x100U)
-#define I2C_INTENSET_SLVPENDINGEN_SHIFT (8U)
-#define I2C_INTENSET_SLVPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK)
-#define I2C_INTENSET_SLVNOTSTREN_MASK (0x800U)
-#define I2C_INTENSET_SLVNOTSTREN_SHIFT (11U)
-#define I2C_INTENSET_SLVNOTSTREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK)
-#define I2C_INTENSET_SLVDESELEN_MASK (0x8000U)
-#define I2C_INTENSET_SLVDESELEN_SHIFT (15U)
-#define I2C_INTENSET_SLVDESELEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK)
-#define I2C_INTENSET_MONRDYEN_MASK (0x10000U)
-#define I2C_INTENSET_MONRDYEN_SHIFT (16U)
-#define I2C_INTENSET_MONRDYEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK)
-#define I2C_INTENSET_MONOVEN_MASK (0x20000U)
-#define I2C_INTENSET_MONOVEN_SHIFT (17U)
-#define I2C_INTENSET_MONOVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK)
-#define I2C_INTENSET_MONIDLEEN_MASK (0x80000U)
-#define I2C_INTENSET_MONIDLEEN_SHIFT (19U)
-#define I2C_INTENSET_MONIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK)
-#define I2C_INTENSET_EVENTTIMEOUTEN_MASK (0x1000000U)
-#define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT (24U)
-#define I2C_INTENSET_EVENTTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK)
-#define I2C_INTENSET_SCLTIMEOUTEN_MASK (0x2000000U)
-#define I2C_INTENSET_SCLTIMEOUTEN_SHIFT (25U)
-#define I2C_INTENSET_SCLTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK)
-
-/*! @name INTENCLR - Interrupt Enable Clear register. */
-#define I2C_INTENCLR_MSTPENDINGCLR_MASK (0x1U)
-#define I2C_INTENCLR_MSTPENDINGCLR_SHIFT (0U)
-#define I2C_INTENCLR_MSTPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK)
-#define I2C_INTENCLR_MSTARBLOSSCLR_MASK (0x10U)
-#define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT (4U)
-#define I2C_INTENCLR_MSTARBLOSSCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK)
-#define I2C_INTENCLR_MSTSTSTPERRCLR_MASK (0x40U)
-#define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT (6U)
-#define I2C_INTENCLR_MSTSTSTPERRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK)
-#define I2C_INTENCLR_SLVPENDINGCLR_MASK (0x100U)
-#define I2C_INTENCLR_SLVPENDINGCLR_SHIFT (8U)
-#define I2C_INTENCLR_SLVPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK)
-#define I2C_INTENCLR_SLVNOTSTRCLR_MASK (0x800U)
-#define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT (11U)
-#define I2C_INTENCLR_SLVNOTSTRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK)
-#define I2C_INTENCLR_SLVDESELCLR_MASK (0x8000U)
-#define I2C_INTENCLR_SLVDESELCLR_SHIFT (15U)
-#define I2C_INTENCLR_SLVDESELCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK)
-#define I2C_INTENCLR_MONRDYCLR_MASK (0x10000U)
-#define I2C_INTENCLR_MONRDYCLR_SHIFT (16U)
-#define I2C_INTENCLR_MONRDYCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK)
-#define I2C_INTENCLR_MONOVCLR_MASK (0x20000U)
-#define I2C_INTENCLR_MONOVCLR_SHIFT (17U)
-#define I2C_INTENCLR_MONOVCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK)
-#define I2C_INTENCLR_MONIDLECLR_MASK (0x80000U)
-#define I2C_INTENCLR_MONIDLECLR_SHIFT (19U)
-#define I2C_INTENCLR_MONIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK)
-#define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK (0x1000000U)
-#define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT (24U)
-#define I2C_INTENCLR_EVENTTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK)
-#define I2C_INTENCLR_SCLTIMEOUTCLR_MASK (0x2000000U)
-#define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT (25U)
-#define I2C_INTENCLR_SCLTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK)
-
-/*! @name TIMEOUT - Time-out value register. */
-#define I2C_TIMEOUT_TOMIN_MASK (0xFU)
-#define I2C_TIMEOUT_TOMIN_SHIFT (0U)
-#define I2C_TIMEOUT_TOMIN(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK)
-#define I2C_TIMEOUT_TO_MASK (0xFFF0U)
-#define I2C_TIMEOUT_TO_SHIFT (4U)
-#define I2C_TIMEOUT_TO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK)
-
-/*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. */
-#define I2C_CLKDIV_DIVVAL_MASK (0xFFFFU)
-#define I2C_CLKDIV_DIVVAL_SHIFT (0U)
-#define I2C_CLKDIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK)
-
-/*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */
-#define I2C_INTSTAT_MSTPENDING_MASK (0x1U)
-#define I2C_INTSTAT_MSTPENDING_SHIFT (0U)
-#define I2C_INTSTAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK)
-#define I2C_INTSTAT_MSTARBLOSS_MASK (0x10U)
-#define I2C_INTSTAT_MSTARBLOSS_SHIFT (4U)
-#define I2C_INTSTAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK)
-#define I2C_INTSTAT_MSTSTSTPERR_MASK (0x40U)
-#define I2C_INTSTAT_MSTSTSTPERR_SHIFT (6U)
-#define I2C_INTSTAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK)
-#define I2C_INTSTAT_SLVPENDING_MASK (0x100U)
-#define I2C_INTSTAT_SLVPENDING_SHIFT (8U)
-#define I2C_INTSTAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK)
-#define I2C_INTSTAT_SLVNOTSTR_MASK (0x800U)
-#define I2C_INTSTAT_SLVNOTSTR_SHIFT (11U)
-#define I2C_INTSTAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK)
-#define I2C_INTSTAT_SLVDESEL_MASK (0x8000U)
-#define I2C_INTSTAT_SLVDESEL_SHIFT (15U)
-#define I2C_INTSTAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK)
-#define I2C_INTSTAT_MONRDY_MASK (0x10000U)
-#define I2C_INTSTAT_MONRDY_SHIFT (16U)
-#define I2C_INTSTAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK)
-#define I2C_INTSTAT_MONOV_MASK (0x20000U)
-#define I2C_INTSTAT_MONOV_SHIFT (17U)
-#define I2C_INTSTAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK)
-#define I2C_INTSTAT_MONIDLE_MASK (0x80000U)
-#define I2C_INTSTAT_MONIDLE_SHIFT (19U)
-#define I2C_INTSTAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK)
-#define I2C_INTSTAT_EVENTTIMEOUT_MASK (0x1000000U)
-#define I2C_INTSTAT_EVENTTIMEOUT_SHIFT (24U)
-#define I2C_INTSTAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK)
-#define I2C_INTSTAT_SCLTIMEOUT_MASK (0x2000000U)
-#define I2C_INTSTAT_SCLTIMEOUT_SHIFT (25U)
-#define I2C_INTSTAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK)
-
-/*! @name MSTCTL - Master control register. */
-#define I2C_MSTCTL_MSTCONTINUE_MASK (0x1U)
-#define I2C_MSTCTL_MSTCONTINUE_SHIFT (0U)
-#define I2C_MSTCTL_MSTCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK)
-#define I2C_MSTCTL_MSTSTART_MASK (0x2U)
-#define I2C_MSTCTL_MSTSTART_SHIFT (1U)
-#define I2C_MSTCTL_MSTSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK)
-#define I2C_MSTCTL_MSTSTOP_MASK (0x4U)
-#define I2C_MSTCTL_MSTSTOP_SHIFT (2U)
-#define I2C_MSTCTL_MSTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK)
-#define I2C_MSTCTL_MSTDMA_MASK (0x8U)
-#define I2C_MSTCTL_MSTDMA_SHIFT (3U)
-#define I2C_MSTCTL_MSTDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK)
-
-/*! @name MSTTIME - Master timing configuration. */
-#define I2C_MSTTIME_MSTSCLLOW_MASK (0x7U)
-#define I2C_MSTTIME_MSTSCLLOW_SHIFT (0U)
-#define I2C_MSTTIME_MSTSCLLOW(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK)
-#define I2C_MSTTIME_MSTSCLHIGH_MASK (0x70U)
-#define I2C_MSTTIME_MSTSCLHIGH_SHIFT (4U)
-#define I2C_MSTTIME_MSTSCLHIGH(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK)
-
-/*! @name MSTDAT - Combined Master receiver and transmitter data register. */
-#define I2C_MSTDAT_DATA_MASK (0xFFU)
-#define I2C_MSTDAT_DATA_SHIFT (0U)
-#define I2C_MSTDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK)
-
-/*! @name SLVCTL - Slave control register. */
-#define I2C_SLVCTL_SLVCONTINUE_MASK (0x1U)
-#define I2C_SLVCTL_SLVCONTINUE_SHIFT (0U)
-#define I2C_SLVCTL_SLVCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK)
-#define I2C_SLVCTL_SLVNACK_MASK (0x2U)
-#define I2C_SLVCTL_SLVNACK_SHIFT (1U)
-#define I2C_SLVCTL_SLVNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK)
-#define I2C_SLVCTL_SLVDMA_MASK (0x8U)
-#define I2C_SLVCTL_SLVDMA_SHIFT (3U)
-#define I2C_SLVCTL_SLVDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK)
-#define I2C_SLVCTL_AUTOACK_MASK (0x100U)
-#define I2C_SLVCTL_AUTOACK_SHIFT (8U)
-#define I2C_SLVCTL_AUTOACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOACK_SHIFT)) & I2C_SLVCTL_AUTOACK_MASK)
-#define I2C_SLVCTL_AUTOMATCHREAD_MASK (0x200U)
-#define I2C_SLVCTL_AUTOMATCHREAD_SHIFT (9U)
-#define I2C_SLVCTL_AUTOMATCHREAD(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOMATCHREAD_SHIFT)) & I2C_SLVCTL_AUTOMATCHREAD_MASK)
-
-/*! @name SLVDAT - Combined Slave receiver and transmitter data register. */
-#define I2C_SLVDAT_DATA_MASK (0xFFU)
-#define I2C_SLVDAT_DATA_SHIFT (0U)
-#define I2C_SLVDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK)
-
-/*! @name SLVADR - Slave address register. */
-#define I2C_SLVADR_SADISABLE_MASK (0x1U)
-#define I2C_SLVADR_SADISABLE_SHIFT (0U)
-#define I2C_SLVADR_SADISABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK)
-#define I2C_SLVADR_SLVADR_MASK (0xFEU)
-#define I2C_SLVADR_SLVADR_SHIFT (1U)
-#define I2C_SLVADR_SLVADR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK)
-#define I2C_SLVADR_AUTONACK_MASK (0x8000U)
-#define I2C_SLVADR_AUTONACK_SHIFT (15U)
-#define I2C_SLVADR_AUTONACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_AUTONACK_SHIFT)) & I2C_SLVADR_AUTONACK_MASK)
-
-/* The count of I2C_SLVADR */
-#define I2C_SLVADR_COUNT (4U)
-
-/*! @name SLVQUAL0 - Slave Qualification for address 0. */
-#define I2C_SLVQUAL0_QUALMODE0_MASK (0x1U)
-#define I2C_SLVQUAL0_QUALMODE0_SHIFT (0U)
-#define I2C_SLVQUAL0_QUALMODE0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK)
-#define I2C_SLVQUAL0_SLVQUAL0_MASK (0xFEU)
-#define I2C_SLVQUAL0_SLVQUAL0_SHIFT (1U)
-#define I2C_SLVQUAL0_SLVQUAL0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK)
-
-/*! @name MONRXDAT - Monitor receiver data register. */
-#define I2C_MONRXDAT_MONRXDAT_MASK (0xFFU)
-#define I2C_MONRXDAT_MONRXDAT_SHIFT (0U)
-#define I2C_MONRXDAT_MONRXDAT(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK)
-#define I2C_MONRXDAT_MONSTART_MASK (0x100U)
-#define I2C_MONRXDAT_MONSTART_SHIFT (8U)
-#define I2C_MONRXDAT_MONSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK)
-#define I2C_MONRXDAT_MONRESTART_MASK (0x200U)
-#define I2C_MONRXDAT_MONRESTART_SHIFT (9U)
-#define I2C_MONRXDAT_MONRESTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK)
-#define I2C_MONRXDAT_MONNACK_MASK (0x400U)
-#define I2C_MONRXDAT_MONNACK_SHIFT (10U)
-#define I2C_MONRXDAT_MONNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK)
-
-/*! @name ID - Peripheral identification register. */
-#define I2C_ID_APERTURE_MASK (0xFFU)
-#define I2C_ID_APERTURE_SHIFT (0U)
-#define I2C_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_APERTURE_SHIFT)) & I2C_ID_APERTURE_MASK)
-#define I2C_ID_MINOR_REV_MASK (0xF00U)
-#define I2C_ID_MINOR_REV_SHIFT (8U)
-#define I2C_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MINOR_REV_SHIFT)) & I2C_ID_MINOR_REV_MASK)
-#define I2C_ID_MAJOR_REV_MASK (0xF000U)
-#define I2C_ID_MAJOR_REV_SHIFT (12U)
-#define I2C_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MAJOR_REV_SHIFT)) & I2C_ID_MAJOR_REV_MASK)
-#define I2C_ID_ID_MASK (0xFFFF0000U)
-#define I2C_ID_ID_SHIFT (16U)
-#define I2C_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_ID_SHIFT)) & I2C_ID_ID_MASK)
-
-
-/*!
- * @}
- */ /* end of group I2C_Register_Masks */
-
-
-/* I2C - Peripheral instance base addresses */
-/** Peripheral I2C0 base address */
-#define I2C0_BASE (0x40086000u)
-/** Peripheral I2C0 base pointer */
-#define I2C0 ((I2C_Type *)I2C0_BASE)
-/** Peripheral I2C1 base address */
-#define I2C1_BASE (0x40087000u)
-/** Peripheral I2C1 base pointer */
-#define I2C1 ((I2C_Type *)I2C1_BASE)
-/** Peripheral I2C2 base address */
-#define I2C2_BASE (0x40088000u)
-/** Peripheral I2C2 base pointer */
-#define I2C2 ((I2C_Type *)I2C2_BASE)
-/** Peripheral I2C3 base address */
-#define I2C3_BASE (0x40089000u)
-/** Peripheral I2C3 base pointer */
-#define I2C3 ((I2C_Type *)I2C3_BASE)
-/** Peripheral I2C4 base address */
-#define I2C4_BASE (0x4008A000u)
-/** Peripheral I2C4 base pointer */
-#define I2C4 ((I2C_Type *)I2C4_BASE)
-/** Peripheral I2C5 base address */
-#define I2C5_BASE (0x40096000u)
-/** Peripheral I2C5 base pointer */
-#define I2C5 ((I2C_Type *)I2C5_BASE)
-/** Peripheral I2C6 base address */
-#define I2C6_BASE (0x40097000u)
-/** Peripheral I2C6 base pointer */
-#define I2C6 ((I2C_Type *)I2C6_BASE)
-/** Peripheral I2C7 base address */
-#define I2C7_BASE (0x40098000u)
-/** Peripheral I2C7 base pointer */
-#define I2C7 ((I2C_Type *)I2C7_BASE)
-/** Peripheral I2C8 base address */
-#define I2C8_BASE (0x40099000u)
-/** Peripheral I2C8 base pointer */
-#define I2C8 ((I2C_Type *)I2C8_BASE)
-/** Peripheral I2C9 base address */
-#define I2C9_BASE (0x4009A000u)
-/** Peripheral I2C9 base pointer */
-#define I2C9 ((I2C_Type *)I2C9_BASE)
-/** Array initializer of I2C peripheral base addresses */
-#define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE, I2C8_BASE, I2C9_BASE }
-/** Array initializer of I2C peripheral base pointers */
-#define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7, I2C8, I2C9 }
-/** Interrupt vectors for the I2C peripheral type */
-#define I2C_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn }
-
-/*!
- * @}
- */ /* end of group I2C_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- I2S Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
- * @{
- */
-
-/** I2S - Register Layout Typedef */
-typedef struct {
- uint8_t RESERVED_0[32];
- struct { /* offset: 0x20, array step: 0x20 */
- __IO uint32_t PCFG1; /**< Configuration register 1 for channel pair, array offset: 0x20, array step: 0x20 */
- __IO uint32_t PCFG2; /**< Configuration register 2 for channel pair, array offset: 0x24, array step: 0x20 */
- __IO uint32_t PSTAT; /**< Status register for channel pair, array offset: 0x28, array step: 0x20 */
- uint8_t RESERVED_0[20];
- } SECCHANNEL[3];
- uint8_t RESERVED_1[2944];
- __IO uint32_t CFG1; /**< Configuration register 1 for the primary channel pair., offset: 0xC00 */
- __IO uint32_t CFG2; /**< Configuration register 2 for the primary channel pair., offset: 0xC04 */
- __IO uint32_t STAT; /**< Status register for the primary channel pair., offset: 0xC08 */
- uint8_t RESERVED_2[16];
- __IO uint32_t DIV; /**< Clock divider, used by all channel pairs., offset: 0xC1C */
- uint8_t RESERVED_3[480];
- __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */
- __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */
- __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */
- uint8_t RESERVED_4[4];
- __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */
- __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */
- __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */
- uint8_t RESERVED_5[4];
- __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */
- __O uint32_t FIFOWR48H; /**< FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE24 */
- uint8_t RESERVED_6[8];
- __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */
- __I uint32_t FIFORD48H; /**< FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE34 */
- uint8_t RESERVED_7[8];
- __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */
- __I uint32_t FIFORD48HNOPOP; /**< FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE44 */
- uint8_t RESERVED_8[4020];
- __I uint32_t ID; /**< I2S Module identification, offset: 0x1DFC */
-} I2S_Type;
-
-/* ----------------------------------------------------------------------------
- -- I2S Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup I2S_Register_Masks I2S Register Masks
- * @{
- */
-
-/*! @name SECCHANNEL_PCFG1 - Configuration register 1 for channel pair */
-#define I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK (0x1U)
-#define I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT (0U)
-#define I2S_SECCHANNEL_PCFG1_PAIRENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT)) & I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK)
-#define I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK (0x400U)
-#define I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT (10U)
-#define I2S_SECCHANNEL_PCFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT)) & I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK)
-
-/* The count of I2S_SECCHANNEL_PCFG1 */
-#define I2S_SECCHANNEL_PCFG1_COUNT (3U)
-
-/*! @name SECCHANNEL_PCFG2 - Configuration register 2 for channel pair */
-#define I2S_SECCHANNEL_PCFG2_POSITION_MASK (0x1FF0000U)
-#define I2S_SECCHANNEL_PCFG2_POSITION_SHIFT (16U)
-#define I2S_SECCHANNEL_PCFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG2_POSITION_SHIFT)) & I2S_SECCHANNEL_PCFG2_POSITION_MASK)
-
-/* The count of I2S_SECCHANNEL_PCFG2 */
-#define I2S_SECCHANNEL_PCFG2_COUNT (3U)
-
-/*! @name SECCHANNEL_PSTAT - Status register for channel pair */
-#define I2S_SECCHANNEL_PSTAT_BUSY_MASK (0x1U)
-#define I2S_SECCHANNEL_PSTAT_BUSY_SHIFT (0U)
-#define I2S_SECCHANNEL_PSTAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_BUSY_SHIFT)) & I2S_SECCHANNEL_PSTAT_BUSY_MASK)
-#define I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK (0x2U)
-#define I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT (1U)
-#define I2S_SECCHANNEL_PSTAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT)) & I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK)
-#define I2S_SECCHANNEL_PSTAT_LR_MASK (0x4U)
-#define I2S_SECCHANNEL_PSTAT_LR_SHIFT (2U)
-#define I2S_SECCHANNEL_PSTAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_LR_SHIFT)) & I2S_SECCHANNEL_PSTAT_LR_MASK)
-#define I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK (0x8U)
-#define I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT (3U)
-#define I2S_SECCHANNEL_PSTAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT)) & I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK)
-
-/* The count of I2S_SECCHANNEL_PSTAT */
-#define I2S_SECCHANNEL_PSTAT_COUNT (3U)
-
-/*! @name CFG1 - Configuration register 1 for the primary channel pair. */
-#define I2S_CFG1_MAINENABLE_MASK (0x1U)
-#define I2S_CFG1_MAINENABLE_SHIFT (0U)
-#define I2S_CFG1_MAINENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MAINENABLE_SHIFT)) & I2S_CFG1_MAINENABLE_MASK)
-#define I2S_CFG1_DATAPAUSE_MASK (0x2U)
-#define I2S_CFG1_DATAPAUSE_SHIFT (1U)
-#define I2S_CFG1_DATAPAUSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATAPAUSE_SHIFT)) & I2S_CFG1_DATAPAUSE_MASK)
-#define I2S_CFG1_PAIRCOUNT_MASK (0xCU)
-#define I2S_CFG1_PAIRCOUNT_SHIFT (2U)
-#define I2S_CFG1_PAIRCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PAIRCOUNT_SHIFT)) & I2S_CFG1_PAIRCOUNT_MASK)
-#define I2S_CFG1_MSTSLVCFG_MASK (0x30U)
-#define I2S_CFG1_MSTSLVCFG_SHIFT (4U)
-#define I2S_CFG1_MSTSLVCFG(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MSTSLVCFG_SHIFT)) & I2S_CFG1_MSTSLVCFG_MASK)
-#define I2S_CFG1_MODE_MASK (0xC0U)
-#define I2S_CFG1_MODE_SHIFT (6U)
-#define I2S_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MODE_SHIFT)) & I2S_CFG1_MODE_MASK)
-#define I2S_CFG1_RIGHTLOW_MASK (0x100U)
-#define I2S_CFG1_RIGHTLOW_SHIFT (8U)
-#define I2S_CFG1_RIGHTLOW(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_RIGHTLOW_SHIFT)) & I2S_CFG1_RIGHTLOW_MASK)
-#define I2S_CFG1_LEFTJUST_MASK (0x200U)
-#define I2S_CFG1_LEFTJUST_SHIFT (9U)
-#define I2S_CFG1_LEFTJUST(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_LEFTJUST_SHIFT)) & I2S_CFG1_LEFTJUST_MASK)
-#define I2S_CFG1_ONECHANNEL_MASK (0x400U)
-#define I2S_CFG1_ONECHANNEL_SHIFT (10U)
-#define I2S_CFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK)
-#define I2S_CFG1_PDMDATA_MASK (0x800U)
-#define I2S_CFG1_PDMDATA_SHIFT (11U)
-#define I2S_CFG1_PDMDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PDMDATA_SHIFT)) & I2S_CFG1_PDMDATA_MASK)
-#define I2S_CFG1_SCK_POL_MASK (0x1000U)
-#define I2S_CFG1_SCK_POL_SHIFT (12U)
-#define I2S_CFG1_SCK_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_SCK_POL_SHIFT)) & I2S_CFG1_SCK_POL_MASK)
-#define I2S_CFG1_WS_POL_MASK (0x2000U)
-#define I2S_CFG1_WS_POL_SHIFT (13U)
-#define I2S_CFG1_WS_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_WS_POL_SHIFT)) & I2S_CFG1_WS_POL_MASK)
-#define I2S_CFG1_DATALEN_MASK (0x1F0000U)
-#define I2S_CFG1_DATALEN_SHIFT (16U)
-#define I2S_CFG1_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATALEN_SHIFT)) & I2S_CFG1_DATALEN_MASK)
-
-/*! @name CFG2 - Configuration register 2 for the primary channel pair. */
-#define I2S_CFG2_FRAMELEN_MASK (0x1FFU)
-#define I2S_CFG2_FRAMELEN_SHIFT (0U)
-#define I2S_CFG2_FRAMELEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_FRAMELEN_SHIFT)) & I2S_CFG2_FRAMELEN_MASK)
-#define I2S_CFG2_POSITION_MASK (0x1FF0000U)
-#define I2S_CFG2_POSITION_SHIFT (16U)
-#define I2S_CFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_POSITION_SHIFT)) & I2S_CFG2_POSITION_MASK)
-
-/*! @name STAT - Status register for the primary channel pair. */
-#define I2S_STAT_BUSY_MASK (0x1U)
-#define I2S_STAT_BUSY_SHIFT (0U)
-#define I2S_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_BUSY_SHIFT)) & I2S_STAT_BUSY_MASK)
-#define I2S_STAT_SLVFRMERR_MASK (0x2U)
-#define I2S_STAT_SLVFRMERR_SHIFT (1U)
-#define I2S_STAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_SLVFRMERR_SHIFT)) & I2S_STAT_SLVFRMERR_MASK)
-#define I2S_STAT_LR_MASK (0x4U)
-#define I2S_STAT_LR_SHIFT (2U)
-#define I2S_STAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_LR_SHIFT)) & I2S_STAT_LR_MASK)
-#define I2S_STAT_DATAPAUSED_MASK (0x8U)
-#define I2S_STAT_DATAPAUSED_SHIFT (3U)
-#define I2S_STAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_DATAPAUSED_SHIFT)) & I2S_STAT_DATAPAUSED_MASK)
-
-/*! @name DIV - Clock divider, used by all channel pairs. */
-#define I2S_DIV_DIV_MASK (0xFFFU)
-#define I2S_DIV_DIV_SHIFT (0U)
-#define I2S_DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_DIV_DIV_SHIFT)) & I2S_DIV_DIV_MASK)
-
-/*! @name FIFOCFG - FIFO configuration and enable register. */
-#define I2S_FIFOCFG_ENABLETX_MASK (0x1U)
-#define I2S_FIFOCFG_ENABLETX_SHIFT (0U)
-#define I2S_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLETX_SHIFT)) & I2S_FIFOCFG_ENABLETX_MASK)
-#define I2S_FIFOCFG_ENABLERX_MASK (0x2U)
-#define I2S_FIFOCFG_ENABLERX_SHIFT (1U)
-#define I2S_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLERX_SHIFT)) & I2S_FIFOCFG_ENABLERX_MASK)
-#define I2S_FIFOCFG_TXI2SE0_MASK (0x4U)
-#define I2S_FIFOCFG_TXI2SE0_SHIFT (2U)
-#define I2S_FIFOCFG_TXI2SE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK)
-#define I2S_FIFOCFG_PACK48_MASK (0x8U)
-#define I2S_FIFOCFG_PACK48_SHIFT (3U)
-#define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK)
-#define I2S_FIFOCFG_SIZE_MASK (0x30U)
-#define I2S_FIFOCFG_SIZE_SHIFT (4U)
-#define I2S_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_SIZE_SHIFT)) & I2S_FIFOCFG_SIZE_MASK)
-#define I2S_FIFOCFG_DMATX_MASK (0x1000U)
-#define I2S_FIFOCFG_DMATX_SHIFT (12U)
-#define I2S_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMATX_SHIFT)) & I2S_FIFOCFG_DMATX_MASK)
-#define I2S_FIFOCFG_DMARX_MASK (0x2000U)
-#define I2S_FIFOCFG_DMARX_SHIFT (13U)
-#define I2S_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMARX_SHIFT)) & I2S_FIFOCFG_DMARX_MASK)
-#define I2S_FIFOCFG_WAKETX_MASK (0x4000U)
-#define I2S_FIFOCFG_WAKETX_SHIFT (14U)
-#define I2S_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKETX_SHIFT)) & I2S_FIFOCFG_WAKETX_MASK)
-#define I2S_FIFOCFG_WAKERX_MASK (0x8000U)
-#define I2S_FIFOCFG_WAKERX_SHIFT (15U)
-#define I2S_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKERX_SHIFT)) & I2S_FIFOCFG_WAKERX_MASK)
-#define I2S_FIFOCFG_EMPTYTX_MASK (0x10000U)
-#define I2S_FIFOCFG_EMPTYTX_SHIFT (16U)
-#define I2S_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYTX_SHIFT)) & I2S_FIFOCFG_EMPTYTX_MASK)
-#define I2S_FIFOCFG_EMPTYRX_MASK (0x20000U)
-#define I2S_FIFOCFG_EMPTYRX_SHIFT (17U)
-#define I2S_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYRX_SHIFT)) & I2S_FIFOCFG_EMPTYRX_MASK)
-#define I2S_FIFOCFG_POPDBG_MASK (0x40000U)
-#define I2S_FIFOCFG_POPDBG_SHIFT (18U)
-#define I2S_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_POPDBG_SHIFT)) & I2S_FIFOCFG_POPDBG_MASK)
-
-/*! @name FIFOSTAT - FIFO status register. */
-#define I2S_FIFOSTAT_TXERR_MASK (0x1U)
-#define I2S_FIFOSTAT_TXERR_SHIFT (0U)
-#define I2S_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXERR_SHIFT)) & I2S_FIFOSTAT_TXERR_MASK)
-#define I2S_FIFOSTAT_RXERR_MASK (0x2U)
-#define I2S_FIFOSTAT_RXERR_SHIFT (1U)
-#define I2S_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXERR_SHIFT)) & I2S_FIFOSTAT_RXERR_MASK)
-#define I2S_FIFOSTAT_PERINT_MASK (0x8U)
-#define I2S_FIFOSTAT_PERINT_SHIFT (3U)
-#define I2S_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_PERINT_SHIFT)) & I2S_FIFOSTAT_PERINT_MASK)
-#define I2S_FIFOSTAT_TXEMPTY_MASK (0x10U)
-#define I2S_FIFOSTAT_TXEMPTY_SHIFT (4U)
-#define I2S_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXEMPTY_SHIFT)) & I2S_FIFOSTAT_TXEMPTY_MASK)
-#define I2S_FIFOSTAT_TXNOTFULL_MASK (0x20U)
-#define I2S_FIFOSTAT_TXNOTFULL_SHIFT (5U)
-#define I2S_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXNOTFULL_SHIFT)) & I2S_FIFOSTAT_TXNOTFULL_MASK)
-#define I2S_FIFOSTAT_RXNOTEMPTY_MASK (0x40U)
-#define I2S_FIFOSTAT_RXNOTEMPTY_SHIFT (6U)
-#define I2S_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXNOTEMPTY_SHIFT)) & I2S_FIFOSTAT_RXNOTEMPTY_MASK)
-#define I2S_FIFOSTAT_RXFULL_MASK (0x80U)
-#define I2S_FIFOSTAT_RXFULL_SHIFT (7U)
-#define I2S_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXFULL_SHIFT)) & I2S_FIFOSTAT_RXFULL_MASK)
-#define I2S_FIFOSTAT_TXLVL_MASK (0x1F00U)
-#define I2S_FIFOSTAT_TXLVL_SHIFT (8U)
-#define I2S_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXLVL_SHIFT)) & I2S_FIFOSTAT_TXLVL_MASK)
-#define I2S_FIFOSTAT_RXLVL_MASK (0x1F0000U)
-#define I2S_FIFOSTAT_RXLVL_SHIFT (16U)
-#define I2S_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXLVL_SHIFT)) & I2S_FIFOSTAT_RXLVL_MASK)
-
-/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */
-#define I2S_FIFOTRIG_TXLVLENA_MASK (0x1U)
-#define I2S_FIFOTRIG_TXLVLENA_SHIFT (0U)
-#define I2S_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVLENA_SHIFT)) & I2S_FIFOTRIG_TXLVLENA_MASK)
-#define I2S_FIFOTRIG_RXLVLENA_MASK (0x2U)
-#define I2S_FIFOTRIG_RXLVLENA_SHIFT (1U)
-#define I2S_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVLENA_SHIFT)) & I2S_FIFOTRIG_RXLVLENA_MASK)
-#define I2S_FIFOTRIG_TXLVL_MASK (0xF00U)
-#define I2S_FIFOTRIG_TXLVL_SHIFT (8U)
-#define I2S_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVL_SHIFT)) & I2S_FIFOTRIG_TXLVL_MASK)
-#define I2S_FIFOTRIG_RXLVL_MASK (0xF0000U)
-#define I2S_FIFOTRIG_RXLVL_SHIFT (16U)
-#define I2S_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVL_SHIFT)) & I2S_FIFOTRIG_RXLVL_MASK)
-
-/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */
-#define I2S_FIFOINTENSET_TXERR_MASK (0x1U)
-#define I2S_FIFOINTENSET_TXERR_SHIFT (0U)
-#define I2S_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXERR_SHIFT)) & I2S_FIFOINTENSET_TXERR_MASK)
-#define I2S_FIFOINTENSET_RXERR_MASK (0x2U)
-#define I2S_FIFOINTENSET_RXERR_SHIFT (1U)
-#define I2S_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXERR_SHIFT)) & I2S_FIFOINTENSET_RXERR_MASK)
-#define I2S_FIFOINTENSET_TXLVL_MASK (0x4U)
-#define I2S_FIFOINTENSET_TXLVL_SHIFT (2U)
-#define I2S_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXLVL_SHIFT)) & I2S_FIFOINTENSET_TXLVL_MASK)
-#define I2S_FIFOINTENSET_RXLVL_MASK (0x8U)
-#define I2S_FIFOINTENSET_RXLVL_SHIFT (3U)
-#define I2S_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXLVL_SHIFT)) & I2S_FIFOINTENSET_RXLVL_MASK)
-
-/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */
-#define I2S_FIFOINTENCLR_TXERR_MASK (0x1U)
-#define I2S_FIFOINTENCLR_TXERR_SHIFT (0U)
-#define I2S_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXERR_SHIFT)) & I2S_FIFOINTENCLR_TXERR_MASK)
-#define I2S_FIFOINTENCLR_RXERR_MASK (0x2U)
-#define I2S_FIFOINTENCLR_RXERR_SHIFT (1U)
-#define I2S_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXERR_SHIFT)) & I2S_FIFOINTENCLR_RXERR_MASK)
-#define I2S_FIFOINTENCLR_TXLVL_MASK (0x4U)
-#define I2S_FIFOINTENCLR_TXLVL_SHIFT (2U)
-#define I2S_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXLVL_SHIFT)) & I2S_FIFOINTENCLR_TXLVL_MASK)
-#define I2S_FIFOINTENCLR_RXLVL_MASK (0x8U)
-#define I2S_FIFOINTENCLR_RXLVL_SHIFT (3U)
-#define I2S_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXLVL_SHIFT)) & I2S_FIFOINTENCLR_RXLVL_MASK)
-
-/*! @name FIFOINTSTAT - FIFO interrupt status register. */
-#define I2S_FIFOINTSTAT_TXERR_MASK (0x1U)
-#define I2S_FIFOINTSTAT_TXERR_SHIFT (0U)
-#define I2S_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXERR_SHIFT)) & I2S_FIFOINTSTAT_TXERR_MASK)
-#define I2S_FIFOINTSTAT_RXERR_MASK (0x2U)
-#define I2S_FIFOINTSTAT_RXERR_SHIFT (1U)
-#define I2S_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXERR_SHIFT)) & I2S_FIFOINTSTAT_RXERR_MASK)
-#define I2S_FIFOINTSTAT_TXLVL_MASK (0x4U)
-#define I2S_FIFOINTSTAT_TXLVL_SHIFT (2U)
-#define I2S_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXLVL_SHIFT)) & I2S_FIFOINTSTAT_TXLVL_MASK)
-#define I2S_FIFOINTSTAT_RXLVL_MASK (0x8U)
-#define I2S_FIFOINTSTAT_RXLVL_SHIFT (3U)
-#define I2S_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXLVL_SHIFT)) & I2S_FIFOINTSTAT_RXLVL_MASK)
-#define I2S_FIFOINTSTAT_PERINT_MASK (0x10U)
-#define I2S_FIFOINTSTAT_PERINT_SHIFT (4U)
-#define I2S_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_PERINT_SHIFT)) & I2S_FIFOINTSTAT_PERINT_MASK)
-
-/*! @name FIFOWR - FIFO write data. */
-#define I2S_FIFOWR_TXDATA_MASK (0xFFFFFFFFU)
-#define I2S_FIFOWR_TXDATA_SHIFT (0U)
-#define I2S_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR_TXDATA_SHIFT)) & I2S_FIFOWR_TXDATA_MASK)
-
-/*! @name FIFOWR48H - FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */
-#define I2S_FIFOWR48H_TXDATA_MASK (0xFFFFFFU)
-#define I2S_FIFOWR48H_TXDATA_SHIFT (0U)
-#define I2S_FIFOWR48H_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR48H_TXDATA_SHIFT)) & I2S_FIFOWR48H_TXDATA_MASK)
-
-/*! @name FIFORD - FIFO read data. */
-#define I2S_FIFORD_RXDATA_MASK (0xFFFFFFFFU)
-#define I2S_FIFORD_RXDATA_SHIFT (0U)
-#define I2S_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD_RXDATA_SHIFT)) & I2S_FIFORD_RXDATA_MASK)
-
-/*! @name FIFORD48H - FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */
-#define I2S_FIFORD48H_RXDATA_MASK (0xFFFFFFU)
-#define I2S_FIFORD48H_RXDATA_SHIFT (0U)
-#define I2S_FIFORD48H_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48H_RXDATA_SHIFT)) & I2S_FIFORD48H_RXDATA_MASK)
-
-/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */
-#define I2S_FIFORDNOPOP_RXDATA_MASK (0xFFFFFFFFU)
-#define I2S_FIFORDNOPOP_RXDATA_SHIFT (0U)
-#define I2S_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORDNOPOP_RXDATA_SHIFT)) & I2S_FIFORDNOPOP_RXDATA_MASK)
-
-/*! @name FIFORD48HNOPOP - FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */
-#define I2S_FIFORD48HNOPOP_RXDATA_MASK (0xFFFFFFU)
-#define I2S_FIFORD48HNOPOP_RXDATA_SHIFT (0U)
-#define I2S_FIFORD48HNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48HNOPOP_RXDATA_SHIFT)) & I2S_FIFORD48HNOPOP_RXDATA_MASK)
-
-/*! @name ID - I2S Module identification */
-#define I2S_ID_Aperture_MASK (0xFFU)
-#define I2S_ID_Aperture_SHIFT (0U)
-#define I2S_ID_Aperture(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Aperture_SHIFT)) & I2S_ID_Aperture_MASK)
-#define I2S_ID_Minor_Rev_MASK (0xF00U)
-#define I2S_ID_Minor_Rev_SHIFT (8U)
-#define I2S_ID_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Minor_Rev_SHIFT)) & I2S_ID_Minor_Rev_MASK)
-#define I2S_ID_Major_Rev_MASK (0xF000U)
-#define I2S_ID_Major_Rev_SHIFT (12U)
-#define I2S_ID_Major_Rev(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Major_Rev_SHIFT)) & I2S_ID_Major_Rev_MASK)
-#define I2S_ID_ID_MASK (0xFFFF0000U)
-#define I2S_ID_ID_SHIFT (16U)
-#define I2S_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_ID_SHIFT)) & I2S_ID_ID_MASK)
-
-
-/*!
- * @}
- */ /* end of group I2S_Register_Masks */
-
-
-/* I2S - Peripheral instance base addresses */
-/** Peripheral I2S0 base address */
-#define I2S0_BASE (0x40097000u)
-/** Peripheral I2S0 base pointer */
-#define I2S0 ((I2S_Type *)I2S0_BASE)
-/** Peripheral I2S1 base address */
-#define I2S1_BASE (0x40098000u)
-/** Peripheral I2S1 base pointer */
-#define I2S1 ((I2S_Type *)I2S1_BASE)
-/** Array initializer of I2S peripheral base addresses */
-#define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE }
-/** Array initializer of I2S peripheral base pointers */
-#define I2S_BASE_PTRS { I2S0, I2S1 }
-/** Interrupt vectors for the I2S peripheral type */
-#define I2S_IRQS { FLEXCOMM6_IRQn, FLEXCOMM7_IRQn }
-
-/*!
- * @}
- */ /* end of group I2S_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- INPUTMUX Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer
- * @{
- */
-
-/** INPUTMUX - Register Layout Typedef */
-typedef struct {
- __IO uint32_t SCT0_INMUX[7]; /**< Trigger select register for DMA channel, array offset: 0x0, array step: 0x4 */
- uint8_t RESERVED_0[164];
- __IO uint32_t PINTSEL[8]; /**< Pin interrupt select register, array offset: 0xC0, array step: 0x4 */
- __IO uint32_t DMA_ITRIG_INMUX[30]; /**< Trigger select register for DMA channel, array offset: 0xE0, array step: 0x4 */
- uint8_t RESERVED_1[8];
- __IO uint32_t DMA_OTRIG_INMUX[4]; /**< DMA output trigger selection to become DMA trigger, array offset: 0x160, array step: 0x4 */
- uint8_t RESERVED_2[16];
- __IO uint32_t FREQMEAS_REF; /**< Selection for frequency measurement reference clock, offset: 0x180 */
- __IO uint32_t FREQMEAS_TARGET; /**< Selection for frequency measurement target clock, offset: 0x184 */
-} INPUTMUX_Type;
-
-/* ----------------------------------------------------------------------------
- -- INPUTMUX Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks
- * @{
- */
-
-/*! @name SCT0_INMUX - Trigger select register for DMA channel */
-#define INPUTMUX_SCT0_INMUX_INP_N_MASK (0x1FU)
-#define INPUTMUX_SCT0_INMUX_INP_N_SHIFT (0U)
-#define INPUTMUX_SCT0_INMUX_INP_N(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SCT0_INMUX_INP_N_SHIFT)) & INPUTMUX_SCT0_INMUX_INP_N_MASK)
-
-/* The count of INPUTMUX_SCT0_INMUX */
-#define INPUTMUX_SCT0_INMUX_COUNT (7U)
-
-/*! @name PINTSEL - Pin interrupt select register */
-#define INPUTMUX_PINTSEL_INTPIN_MASK (0xFFU)
-#define INPUTMUX_PINTSEL_INTPIN_SHIFT (0U)
-#define INPUTMUX_PINTSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSEL_INTPIN_MASK)
-
-/* The count of INPUTMUX_PINTSEL */
-#define INPUTMUX_PINTSEL_COUNT (8U)
-
-/*! @name DMA_ITRIG_INMUX - Trigger select register for DMA channel */
-#define INPUTMUX_DMA_ITRIG_INMUX_INP_MASK (0x1FU)
-#define INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT (0U)
-#define INPUTMUX_DMA_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_ITRIG_INMUX_INP_MASK)
-
-/* The count of INPUTMUX_DMA_ITRIG_INMUX */
-#define INPUTMUX_DMA_ITRIG_INMUX_COUNT (30U)
-
-/*! @name DMA_OTRIG_INMUX - DMA output trigger selection to become DMA trigger */
-#define INPUTMUX_DMA_OTRIG_INMUX_INP_MASK (0x1FU)
-#define INPUTMUX_DMA_OTRIG_INMUX_INP_SHIFT (0U)
-#define INPUTMUX_DMA_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_OTRIG_INMUX_INP_MASK)
-
-/* The count of INPUTMUX_DMA_OTRIG_INMUX */
-#define INPUTMUX_DMA_OTRIG_INMUX_COUNT (4U)
-
-/*! @name FREQMEAS_REF - Selection for frequency measurement reference clock */
-#define INPUTMUX_FREQMEAS_REF_CLKIN_MASK (0x1FU)
-#define INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT (0U)
-#define INPUTMUX_FREQMEAS_REF_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_REF_CLKIN_MASK)
-
-/*! @name FREQMEAS_TARGET - Selection for frequency measurement target clock */
-#define INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK (0x1FU)
-#define INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT (0U)
-#define INPUTMUX_FREQMEAS_TARGET_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK)
-
-
-/*!
- * @}
- */ /* end of group INPUTMUX_Register_Masks */
-
-
-/* INPUTMUX - Peripheral instance base addresses */
-/** Peripheral INPUTMUX base address */
-#define INPUTMUX_BASE (0x40005000u)
-/** Peripheral INPUTMUX base pointer */
-#define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE)
-/** Array initializer of INPUTMUX peripheral base addresses */
-#define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE }
-/** Array initializer of INPUTMUX peripheral base pointers */
-#define INPUTMUX_BASE_PTRS { INPUTMUX }
-
-/*!
- * @}
- */ /* end of group INPUTMUX_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- IOCON Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup IOCON_Peripheral_Access_Layer IOCON Peripheral Access Layer
- * @{
- */
-
-/** IOCON - Register Layout Typedef */
-typedef struct {
- __IO uint32_t PIO[6][32]; /**< Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 5 pins PIO5_31, array offset: 0x0, array step: index*0x80, index2*0x4 */
-} IOCON_Type;
-
-/* ----------------------------------------------------------------------------
- -- IOCON Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup IOCON_Register_Masks IOCON Register Masks
- * @{
- */
-
-/*! @name PIO - Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 5 pins PIO5_31 */
-#define IOCON_PIO_FUNC_MASK (0xFU)
-#define IOCON_PIO_FUNC_SHIFT (0U)
-#define IOCON_PIO_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FUNC_SHIFT)) & IOCON_PIO_FUNC_MASK)
-#define IOCON_PIO_MODE_MASK (0x30U)
-#define IOCON_PIO_MODE_SHIFT (4U)
-#define IOCON_PIO_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK)
-#define IOCON_PIO_I2CSLEW_MASK (0x40U)
-#define IOCON_PIO_I2CSLEW_SHIFT (6U)
-#define IOCON_PIO_I2CSLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CSLEW_SHIFT)) & IOCON_PIO_I2CSLEW_MASK)
-#define IOCON_PIO_INVERT_MASK (0x80U)
-#define IOCON_PIO_INVERT_SHIFT (7U)
-#define IOCON_PIO_INVERT(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INVERT_SHIFT)) & IOCON_PIO_INVERT_MASK)
-#define IOCON_PIO_DIGIMODE_MASK (0x100U)
-#define IOCON_PIO_DIGIMODE_SHIFT (8U)
-#define IOCON_PIO_DIGIMODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DIGIMODE_SHIFT)) & IOCON_PIO_DIGIMODE_MASK)
-#define IOCON_PIO_FILTEROFF_MASK (0x200U)
-#define IOCON_PIO_FILTEROFF_SHIFT (9U)
-#define IOCON_PIO_FILTEROFF(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FILTEROFF_SHIFT)) & IOCON_PIO_FILTEROFF_MASK)
-#define IOCON_PIO_I2CDRIVE_MASK (0x400U)
-#define IOCON_PIO_I2CDRIVE_SHIFT (10U)
-#define IOCON_PIO_I2CDRIVE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CDRIVE_SHIFT)) & IOCON_PIO_I2CDRIVE_MASK)
-#define IOCON_PIO_SLEW_MASK (0x400U)
-#define IOCON_PIO_SLEW_SHIFT (10U)
-#define IOCON_PIO_SLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SLEW_SHIFT)) & IOCON_PIO_SLEW_MASK)
-#define IOCON_PIO_OD_MASK (0x800U)
-#define IOCON_PIO_OD_SHIFT (11U)
-#define IOCON_PIO_OD(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK)
-#define IOCON_PIO_I2CFILTER_MASK (0x800U)
-#define IOCON_PIO_I2CFILTER_SHIFT (11U)
-#define IOCON_PIO_I2CFILTER(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CFILTER_SHIFT)) & IOCON_PIO_I2CFILTER_MASK)
-
-/* The count of IOCON_PIO */
-#define IOCON_PIO_COUNT (6U)
-
-/* The count of IOCON_PIO */
-#define IOCON_PIO_COUNT2 (32U)
-
-
-/*!
- * @}
- */ /* end of group IOCON_Register_Masks */
-
-
-/* IOCON - Peripheral instance base addresses */
-/** Peripheral IOCON base address */
-#define IOCON_BASE (0x40001000u)
-/** Peripheral IOCON base pointer */
-#define IOCON ((IOCON_Type *)IOCON_BASE)
-/** Array initializer of IOCON peripheral base addresses */
-#define IOCON_BASE_ADDRS { IOCON_BASE }
-/** Array initializer of IOCON peripheral base pointers */
-#define IOCON_BASE_PTRS { IOCON }
-
-/*!
- * @}
- */ /* end of group IOCON_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- LCD Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup LCD_Peripheral_Access_Layer LCD Peripheral Access Layer
- * @{
- */
-
-/** LCD - Register Layout Typedef */
-typedef struct {
- __IO uint32_t TIMH; /**< Horizontal Timing Control register, offset: 0x0 */
- __IO uint32_t TIMV; /**< Vertical Timing Control register, offset: 0x4 */
- __IO uint32_t POL; /**< Clock and Signal Polarity Control register, offset: 0x8 */
- __IO uint32_t LE; /**< Line End Control register, offset: 0xC */
- __IO uint32_t UPBASE; /**< Upper Panel Frame Base Address register, offset: 0x10 */
- __IO uint32_t LPBASE; /**< Lower Panel Frame Base Address register, offset: 0x14 */
- __IO uint32_t CTRL; /**< LCD Control register, offset: 0x18 */
- __IO uint32_t INTMSK; /**< Interrupt Mask register, offset: 0x1C */
- __I uint32_t INTRAW; /**< Raw Interrupt Status register, offset: 0x20 */
- __I uint32_t INTSTAT; /**< Masked Interrupt Status register, offset: 0x24 */
- __IO uint32_t INTCLR; /**< Interrupt Clear register, offset: 0x28 */
- __I uint32_t UPCURR; /**< Upper Panel Current Address Value register, offset: 0x2C */
- __I uint32_t LPCURR; /**< Lower Panel Current Address Value register, offset: 0x30 */
- uint8_t RESERVED_0[460];
- __IO uint32_t PAL[128]; /**< 256x16-bit Color Palette registers, array offset: 0x200, array step: 0x4 */
- uint8_t RESERVED_1[1024];
- __IO uint32_t CRSR_IMG[256]; /**< Cursor Image registers, array offset: 0x800, array step: 0x4 */
- __IO uint32_t CRSR_CTRL; /**< Cursor Control register, offset: 0xC00 */
- __IO uint32_t CRSR_CFG; /**< Cursor Configuration register, offset: 0xC04 */
- __IO uint32_t CRSR_PAL0; /**< Cursor Palette register 0, offset: 0xC08 */
- __IO uint32_t CRSR_PAL1; /**< Cursor Palette register 1, offset: 0xC0C */
- __IO uint32_t CRSR_XY; /**< Cursor XY Position register, offset: 0xC10 */
- __IO uint32_t CRSR_CLIP; /**< Cursor Clip Position register, offset: 0xC14 */
- uint8_t RESERVED_2[8];
- __IO uint32_t CRSR_INTMSK; /**< Cursor Interrupt Mask register, offset: 0xC20 */
- __O uint32_t CRSR_INTCLR; /**< Cursor Interrupt Clear register, offset: 0xC24 */
- __I uint32_t CRSR_INTRAW; /**< Cursor Raw Interrupt Status register, offset: 0xC28 */
- __I uint32_t CRSR_INTSTAT; /**< Cursor Masked Interrupt Status register, offset: 0xC2C */
-} LCD_Type;
-
-/* ----------------------------------------------------------------------------
- -- LCD Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup LCD_Register_Masks LCD Register Masks
- * @{
- */
-
-/*! @name TIMH - Horizontal Timing Control register */
-#define LCD_TIMH_PPL_MASK (0xFCU)
-#define LCD_TIMH_PPL_SHIFT (2U)
-#define LCD_TIMH_PPL(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMH_PPL_SHIFT)) & LCD_TIMH_PPL_MASK)
-#define LCD_TIMH_HSW_MASK (0xFF00U)
-#define LCD_TIMH_HSW_SHIFT (8U)
-#define LCD_TIMH_HSW(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMH_HSW_SHIFT)) & LCD_TIMH_HSW_MASK)
-#define LCD_TIMH_HFP_MASK (0xFF0000U)
-#define LCD_TIMH_HFP_SHIFT (16U)
-#define LCD_TIMH_HFP(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMH_HFP_SHIFT)) & LCD_TIMH_HFP_MASK)
-#define LCD_TIMH_HBP_MASK (0xFF000000U)
-#define LCD_TIMH_HBP_SHIFT (24U)
-#define LCD_TIMH_HBP(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMH_HBP_SHIFT)) & LCD_TIMH_HBP_MASK)
-
-/*! @name TIMV - Vertical Timing Control register */
-#define LCD_TIMV_LPP_MASK (0x3FFU)
-#define LCD_TIMV_LPP_SHIFT (0U)
-#define LCD_TIMV_LPP(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMV_LPP_SHIFT)) & LCD_TIMV_LPP_MASK)
-#define LCD_TIMV_VSW_MASK (0xFC00U)
-#define LCD_TIMV_VSW_SHIFT (10U)
-#define LCD_TIMV_VSW(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMV_VSW_SHIFT)) & LCD_TIMV_VSW_MASK)
-#define LCD_TIMV_VFP_MASK (0xFF0000U)
-#define LCD_TIMV_VFP_SHIFT (16U)
-#define LCD_TIMV_VFP(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMV_VFP_SHIFT)) & LCD_TIMV_VFP_MASK)
-#define LCD_TIMV_VBP_MASK (0xFF000000U)
-#define LCD_TIMV_VBP_SHIFT (24U)
-#define LCD_TIMV_VBP(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMV_VBP_SHIFT)) & LCD_TIMV_VBP_MASK)
-
-/*! @name POL - Clock and Signal Polarity Control register */
-#define LCD_POL_PCD_LO_MASK (0x1FU)
-#define LCD_POL_PCD_LO_SHIFT (0U)
-#define LCD_POL_PCD_LO(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_PCD_LO_SHIFT)) & LCD_POL_PCD_LO_MASK)
-#define LCD_POL_ACB_MASK (0x7C0U)
-#define LCD_POL_ACB_SHIFT (6U)
-#define LCD_POL_ACB(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_ACB_SHIFT)) & LCD_POL_ACB_MASK)
-#define LCD_POL_IVS_MASK (0x800U)
-#define LCD_POL_IVS_SHIFT (11U)
-#define LCD_POL_IVS(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_IVS_SHIFT)) & LCD_POL_IVS_MASK)
-#define LCD_POL_IHS_MASK (0x1000U)
-#define LCD_POL_IHS_SHIFT (12U)
-#define LCD_POL_IHS(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_IHS_SHIFT)) & LCD_POL_IHS_MASK)
-#define LCD_POL_IPC_MASK (0x2000U)
-#define LCD_POL_IPC_SHIFT (13U)
-#define LCD_POL_IPC(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_IPC_SHIFT)) & LCD_POL_IPC_MASK)
-#define LCD_POL_IOE_MASK (0x4000U)
-#define LCD_POL_IOE_SHIFT (14U)
-#define LCD_POL_IOE(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_IOE_SHIFT)) & LCD_POL_IOE_MASK)
-#define LCD_POL_CPL_MASK (0x3FF0000U)
-#define LCD_POL_CPL_SHIFT (16U)
-#define LCD_POL_CPL(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_CPL_SHIFT)) & LCD_POL_CPL_MASK)
-#define LCD_POL_BCD_MASK (0x4000000U)
-#define LCD_POL_BCD_SHIFT (26U)
-#define LCD_POL_BCD(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_BCD_SHIFT)) & LCD_POL_BCD_MASK)
-#define LCD_POL_PCD_HI_MASK (0xF8000000U)
-#define LCD_POL_PCD_HI_SHIFT (27U)
-#define LCD_POL_PCD_HI(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_PCD_HI_SHIFT)) & LCD_POL_PCD_HI_MASK)
-
-/*! @name LE - Line End Control register */
-#define LCD_LE_LED_MASK (0x7FU)
-#define LCD_LE_LED_SHIFT (0U)
-#define LCD_LE_LED(x) (((uint32_t)(((uint32_t)(x)) << LCD_LE_LED_SHIFT)) & LCD_LE_LED_MASK)
-#define LCD_LE_LEE_MASK (0x10000U)
-#define LCD_LE_LEE_SHIFT (16U)
-#define LCD_LE_LEE(x) (((uint32_t)(((uint32_t)(x)) << LCD_LE_LEE_SHIFT)) & LCD_LE_LEE_MASK)
-
-/*! @name UPBASE - Upper Panel Frame Base Address register */
-#define LCD_UPBASE_LCDUPBASE_MASK (0xFFFFFFF8U)
-#define LCD_UPBASE_LCDUPBASE_SHIFT (3U)
-#define LCD_UPBASE_LCDUPBASE(x) (((uint32_t)(((uint32_t)(x)) << LCD_UPBASE_LCDUPBASE_SHIFT)) & LCD_UPBASE_LCDUPBASE_MASK)
-
-/*! @name LPBASE - Lower Panel Frame Base Address register */
-#define LCD_LPBASE_LCDLPBASE_MASK (0xFFFFFFF8U)
-#define LCD_LPBASE_LCDLPBASE_SHIFT (3U)
-#define LCD_LPBASE_LCDLPBASE(x) (((uint32_t)(((uint32_t)(x)) << LCD_LPBASE_LCDLPBASE_SHIFT)) & LCD_LPBASE_LCDLPBASE_MASK)
-
-/*! @name CTRL - LCD Control register */
-#define LCD_CTRL_LCDEN_MASK (0x1U)
-#define LCD_CTRL_LCDEN_SHIFT (0U)
-#define LCD_CTRL_LCDEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDEN_SHIFT)) & LCD_CTRL_LCDEN_MASK)
-#define LCD_CTRL_LCDBPP_MASK (0xEU)
-#define LCD_CTRL_LCDBPP_SHIFT (1U)
-#define LCD_CTRL_LCDBPP(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDBPP_SHIFT)) & LCD_CTRL_LCDBPP_MASK)
-#define LCD_CTRL_LCDBW_MASK (0x10U)
-#define LCD_CTRL_LCDBW_SHIFT (4U)
-#define LCD_CTRL_LCDBW(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDBW_SHIFT)) & LCD_CTRL_LCDBW_MASK)
-#define LCD_CTRL_LCDTFT_MASK (0x20U)
-#define LCD_CTRL_LCDTFT_SHIFT (5U)
-#define LCD_CTRL_LCDTFT(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDTFT_SHIFT)) & LCD_CTRL_LCDTFT_MASK)
-#define LCD_CTRL_LCDMONO8_MASK (0x40U)
-#define LCD_CTRL_LCDMONO8_SHIFT (6U)
-#define LCD_CTRL_LCDMONO8(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDMONO8_SHIFT)) & LCD_CTRL_LCDMONO8_MASK)
-#define LCD_CTRL_LCDDUAL_MASK (0x80U)
-#define LCD_CTRL_LCDDUAL_SHIFT (7U)
-#define LCD_CTRL_LCDDUAL(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDDUAL_SHIFT)) & LCD_CTRL_LCDDUAL_MASK)
-#define LCD_CTRL_BGR_MASK (0x100U)
-#define LCD_CTRL_BGR_SHIFT (8U)
-#define LCD_CTRL_BGR(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_BGR_SHIFT)) & LCD_CTRL_BGR_MASK)
-#define LCD_CTRL_BEBO_MASK (0x200U)
-#define LCD_CTRL_BEBO_SHIFT (9U)
-#define LCD_CTRL_BEBO(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_BEBO_SHIFT)) & LCD_CTRL_BEBO_MASK)
-#define LCD_CTRL_BEPO_MASK (0x400U)
-#define LCD_CTRL_BEPO_SHIFT (10U)
-#define LCD_CTRL_BEPO(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_BEPO_SHIFT)) & LCD_CTRL_BEPO_MASK)
-#define LCD_CTRL_LCDPWR_MASK (0x800U)
-#define LCD_CTRL_LCDPWR_SHIFT (11U)
-#define LCD_CTRL_LCDPWR(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDPWR_SHIFT)) & LCD_CTRL_LCDPWR_MASK)
-#define LCD_CTRL_LCDVCOMP_MASK (0x3000U)
-#define LCD_CTRL_LCDVCOMP_SHIFT (12U)
-#define LCD_CTRL_LCDVCOMP(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDVCOMP_SHIFT)) & LCD_CTRL_LCDVCOMP_MASK)
-#define LCD_CTRL_WATERMARK_MASK (0x10000U)
-#define LCD_CTRL_WATERMARK_SHIFT (16U)
-#define LCD_CTRL_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_WATERMARK_SHIFT)) & LCD_CTRL_WATERMARK_MASK)
-
-/*! @name INTMSK - Interrupt Mask register */
-#define LCD_INTMSK_FUFIM_MASK (0x2U)
-#define LCD_INTMSK_FUFIM_SHIFT (1U)
-#define LCD_INTMSK_FUFIM(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTMSK_FUFIM_SHIFT)) & LCD_INTMSK_FUFIM_MASK)
-#define LCD_INTMSK_LNBUIM_MASK (0x4U)
-#define LCD_INTMSK_LNBUIM_SHIFT (2U)
-#define LCD_INTMSK_LNBUIM(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTMSK_LNBUIM_SHIFT)) & LCD_INTMSK_LNBUIM_MASK)
-#define LCD_INTMSK_VCOMPIM_MASK (0x8U)
-#define LCD_INTMSK_VCOMPIM_SHIFT (3U)
-#define LCD_INTMSK_VCOMPIM(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTMSK_VCOMPIM_SHIFT)) & LCD_INTMSK_VCOMPIM_MASK)
-#define LCD_INTMSK_BERIM_MASK (0x10U)
-#define LCD_INTMSK_BERIM_SHIFT (4U)
-#define LCD_INTMSK_BERIM(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTMSK_BERIM_SHIFT)) & LCD_INTMSK_BERIM_MASK)
-
-/*! @name INTRAW - Raw Interrupt Status register */
-#define LCD_INTRAW_FUFRIS_MASK (0x2U)
-#define LCD_INTRAW_FUFRIS_SHIFT (1U)
-#define LCD_INTRAW_FUFRIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTRAW_FUFRIS_SHIFT)) & LCD_INTRAW_FUFRIS_MASK)
-#define LCD_INTRAW_LNBURIS_MASK (0x4U)
-#define LCD_INTRAW_LNBURIS_SHIFT (2U)
-#define LCD_INTRAW_LNBURIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTRAW_LNBURIS_SHIFT)) & LCD_INTRAW_LNBURIS_MASK)
-#define LCD_INTRAW_VCOMPRIS_MASK (0x8U)
-#define LCD_INTRAW_VCOMPRIS_SHIFT (3U)
-#define LCD_INTRAW_VCOMPRIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTRAW_VCOMPRIS_SHIFT)) & LCD_INTRAW_VCOMPRIS_MASK)
-#define LCD_INTRAW_BERRAW_MASK (0x10U)
-#define LCD_INTRAW_BERRAW_SHIFT (4U)
-#define LCD_INTRAW_BERRAW(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTRAW_BERRAW_SHIFT)) & LCD_INTRAW_BERRAW_MASK)
-
-/*! @name INTSTAT - Masked Interrupt Status register */
-#define LCD_INTSTAT_FUFMIS_MASK (0x2U)
-#define LCD_INTSTAT_FUFMIS_SHIFT (1U)
-#define LCD_INTSTAT_FUFMIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTSTAT_FUFMIS_SHIFT)) & LCD_INTSTAT_FUFMIS_MASK)
-#define LCD_INTSTAT_LNBUMIS_MASK (0x4U)
-#define LCD_INTSTAT_LNBUMIS_SHIFT (2U)
-#define LCD_INTSTAT_LNBUMIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTSTAT_LNBUMIS_SHIFT)) & LCD_INTSTAT_LNBUMIS_MASK)
-#define LCD_INTSTAT_VCOMPMIS_MASK (0x8U)
-#define LCD_INTSTAT_VCOMPMIS_SHIFT (3U)
-#define LCD_INTSTAT_VCOMPMIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTSTAT_VCOMPMIS_SHIFT)) & LCD_INTSTAT_VCOMPMIS_MASK)
-#define LCD_INTSTAT_BERMIS_MASK (0x10U)
-#define LCD_INTSTAT_BERMIS_SHIFT (4U)
-#define LCD_INTSTAT_BERMIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTSTAT_BERMIS_SHIFT)) & LCD_INTSTAT_BERMIS_MASK)
-
-/*! @name INTCLR - Interrupt Clear register */
-#define LCD_INTCLR_FUFIC_MASK (0x2U)
-#define LCD_INTCLR_FUFIC_SHIFT (1U)
-#define LCD_INTCLR_FUFIC(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTCLR_FUFIC_SHIFT)) & LCD_INTCLR_FUFIC_MASK)
-#define LCD_INTCLR_LNBUIC_MASK (0x4U)
-#define LCD_INTCLR_LNBUIC_SHIFT (2U)
-#define LCD_INTCLR_LNBUIC(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTCLR_LNBUIC_SHIFT)) & LCD_INTCLR_LNBUIC_MASK)
-#define LCD_INTCLR_VCOMPIC_MASK (0x8U)
-#define LCD_INTCLR_VCOMPIC_SHIFT (3U)
-#define LCD_INTCLR_VCOMPIC(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTCLR_VCOMPIC_SHIFT)) & LCD_INTCLR_VCOMPIC_MASK)
-#define LCD_INTCLR_BERIC_MASK (0x10U)
-#define LCD_INTCLR_BERIC_SHIFT (4U)
-#define LCD_INTCLR_BERIC(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTCLR_BERIC_SHIFT)) & LCD_INTCLR_BERIC_MASK)
-
-/*! @name UPCURR - Upper Panel Current Address Value register */
-#define LCD_UPCURR_LCDUPCURR_MASK (0xFFFFFFFFU)
-#define LCD_UPCURR_LCDUPCURR_SHIFT (0U)
-#define LCD_UPCURR_LCDUPCURR(x) (((uint32_t)(((uint32_t)(x)) << LCD_UPCURR_LCDUPCURR_SHIFT)) & LCD_UPCURR_LCDUPCURR_MASK)
-
-/*! @name LPCURR - Lower Panel Current Address Value register */
-#define LCD_LPCURR_LCDLPCURR_MASK (0xFFFFFFFFU)
-#define LCD_LPCURR_LCDLPCURR_SHIFT (0U)
-#define LCD_LPCURR_LCDLPCURR(x) (((uint32_t)(((uint32_t)(x)) << LCD_LPCURR_LCDLPCURR_SHIFT)) & LCD_LPCURR_LCDLPCURR_MASK)
-
-/*! @name PAL - 256x16-bit Color Palette registers */
-#define LCD_PAL_R04_0_MASK (0x1FU)
-#define LCD_PAL_R04_0_SHIFT (0U)
-#define LCD_PAL_R04_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_R04_0_SHIFT)) & LCD_PAL_R04_0_MASK)
-#define LCD_PAL_G04_0_MASK (0x3E0U)
-#define LCD_PAL_G04_0_SHIFT (5U)
-#define LCD_PAL_G04_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_G04_0_SHIFT)) & LCD_PAL_G04_0_MASK)
-#define LCD_PAL_B04_0_MASK (0x7C00U)
-#define LCD_PAL_B04_0_SHIFT (10U)
-#define LCD_PAL_B04_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_B04_0_SHIFT)) & LCD_PAL_B04_0_MASK)
-#define LCD_PAL_I0_MASK (0x8000U)
-#define LCD_PAL_I0_SHIFT (15U)
-#define LCD_PAL_I0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_I0_SHIFT)) & LCD_PAL_I0_MASK)
-#define LCD_PAL_R14_0_MASK (0x1F0000U)
-#define LCD_PAL_R14_0_SHIFT (16U)
-#define LCD_PAL_R14_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_R14_0_SHIFT)) & LCD_PAL_R14_0_MASK)
-#define LCD_PAL_G14_0_MASK (0x3E00000U)
-#define LCD_PAL_G14_0_SHIFT (21U)
-#define LCD_PAL_G14_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_G14_0_SHIFT)) & LCD_PAL_G14_0_MASK)
-#define LCD_PAL_B14_0_MASK (0x7C000000U)
-#define LCD_PAL_B14_0_SHIFT (26U)
-#define LCD_PAL_B14_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_B14_0_SHIFT)) & LCD_PAL_B14_0_MASK)
-#define LCD_PAL_I1_MASK (0x80000000U)
-#define LCD_PAL_I1_SHIFT (31U)
-#define LCD_PAL_I1(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_I1_SHIFT)) & LCD_PAL_I1_MASK)
-
-/* The count of LCD_PAL */
-#define LCD_PAL_COUNT (128U)
-
-/*! @name CRSR_IMG - Cursor Image registers */
-#define LCD_CRSR_IMG_CRSR_IMG_MASK (0xFFFFFFFFU)
-#define LCD_CRSR_IMG_CRSR_IMG_SHIFT (0U)
-#define LCD_CRSR_IMG_CRSR_IMG(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_IMG_CRSR_IMG_SHIFT)) & LCD_CRSR_IMG_CRSR_IMG_MASK)
-
-/* The count of LCD_CRSR_IMG */
-#define LCD_CRSR_IMG_COUNT (256U)
-
-/*! @name CRSR_CTRL - Cursor Control register */
-#define LCD_CRSR_CTRL_CRSRON_MASK (0x1U)
-#define LCD_CRSR_CTRL_CRSRON_SHIFT (0U)
-#define LCD_CRSR_CTRL_CRSRON(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CTRL_CRSRON_SHIFT)) & LCD_CRSR_CTRL_CRSRON_MASK)
-#define LCD_CRSR_CTRL_CRSRNUM1_0_MASK (0x30U)
-#define LCD_CRSR_CTRL_CRSRNUM1_0_SHIFT (4U)
-#define LCD_CRSR_CTRL_CRSRNUM1_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CTRL_CRSRNUM1_0_SHIFT)) & LCD_CRSR_CTRL_CRSRNUM1_0_MASK)
-
-/*! @name CRSR_CFG - Cursor Configuration register */
-#define LCD_CRSR_CFG_CRSRSIZE_MASK (0x1U)
-#define LCD_CRSR_CFG_CRSRSIZE_SHIFT (0U)
-#define LCD_CRSR_CFG_CRSRSIZE(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CFG_CRSRSIZE_SHIFT)) & LCD_CRSR_CFG_CRSRSIZE_MASK)
-#define LCD_CRSR_CFG_FRAMESYNC_MASK (0x2U)
-#define LCD_CRSR_CFG_FRAMESYNC_SHIFT (1U)
-#define LCD_CRSR_CFG_FRAMESYNC(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CFG_FRAMESYNC_SHIFT)) & LCD_CRSR_CFG_FRAMESYNC_MASK)
-
-/*! @name CRSR_PAL0 - Cursor Palette register 0 */
-#define LCD_CRSR_PAL0_RED_MASK (0xFFU)
-#define LCD_CRSR_PAL0_RED_SHIFT (0U)
-#define LCD_CRSR_PAL0_RED(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL0_RED_SHIFT)) & LCD_CRSR_PAL0_RED_MASK)
-#define LCD_CRSR_PAL0_GREEN_MASK (0xFF00U)
-#define LCD_CRSR_PAL0_GREEN_SHIFT (8U)
-#define LCD_CRSR_PAL0_GREEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL0_GREEN_SHIFT)) & LCD_CRSR_PAL0_GREEN_MASK)
-#define LCD_CRSR_PAL0_BLUE_MASK (0xFF0000U)
-#define LCD_CRSR_PAL0_BLUE_SHIFT (16U)
-#define LCD_CRSR_PAL0_BLUE(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL0_BLUE_SHIFT)) & LCD_CRSR_PAL0_BLUE_MASK)
-
-/*! @name CRSR_PAL1 - Cursor Palette register 1 */
-#define LCD_CRSR_PAL1_RED_MASK (0xFFU)
-#define LCD_CRSR_PAL1_RED_SHIFT (0U)
-#define LCD_CRSR_PAL1_RED(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL1_RED_SHIFT)) & LCD_CRSR_PAL1_RED_MASK)
-#define LCD_CRSR_PAL1_GREEN_MASK (0xFF00U)
-#define LCD_CRSR_PAL1_GREEN_SHIFT (8U)
-#define LCD_CRSR_PAL1_GREEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL1_GREEN_SHIFT)) & LCD_CRSR_PAL1_GREEN_MASK)
-#define LCD_CRSR_PAL1_BLUE_MASK (0xFF0000U)
-#define LCD_CRSR_PAL1_BLUE_SHIFT (16U)
-#define LCD_CRSR_PAL1_BLUE(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL1_BLUE_SHIFT)) & LCD_CRSR_PAL1_BLUE_MASK)
-
-/*! @name CRSR_XY - Cursor XY Position register */
-#define LCD_CRSR_XY_CRSRX_MASK (0x3FFU)
-#define LCD_CRSR_XY_CRSRX_SHIFT (0U)
-#define LCD_CRSR_XY_CRSRX(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_XY_CRSRX_SHIFT)) & LCD_CRSR_XY_CRSRX_MASK)
-#define LCD_CRSR_XY_CRSRY_MASK (0x3FF0000U)
-#define LCD_CRSR_XY_CRSRY_SHIFT (16U)
-#define LCD_CRSR_XY_CRSRY(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_XY_CRSRY_SHIFT)) & LCD_CRSR_XY_CRSRY_MASK)
-
-/*! @name CRSR_CLIP - Cursor Clip Position register */
-#define LCD_CRSR_CLIP_CRSRCLIPX_MASK (0x3FU)
-#define LCD_CRSR_CLIP_CRSRCLIPX_SHIFT (0U)
-#define LCD_CRSR_CLIP_CRSRCLIPX(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CLIP_CRSRCLIPX_SHIFT)) & LCD_CRSR_CLIP_CRSRCLIPX_MASK)
-#define LCD_CRSR_CLIP_CRSRCLIPY_MASK (0x3F00U)
-#define LCD_CRSR_CLIP_CRSRCLIPY_SHIFT (8U)
-#define LCD_CRSR_CLIP_CRSRCLIPY(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CLIP_CRSRCLIPY_SHIFT)) & LCD_CRSR_CLIP_CRSRCLIPY_MASK)
-
-/*! @name CRSR_INTMSK - Cursor Interrupt Mask register */
-#define LCD_CRSR_INTMSK_CRSRIM_MASK (0x1U)
-#define LCD_CRSR_INTMSK_CRSRIM_SHIFT (0U)
-#define LCD_CRSR_INTMSK_CRSRIM(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_INTMSK_CRSRIM_SHIFT)) & LCD_CRSR_INTMSK_CRSRIM_MASK)
-
-/*! @name CRSR_INTCLR - Cursor Interrupt Clear register */
-#define LCD_CRSR_INTCLR_CRSRIC_MASK (0x1U)
-#define LCD_CRSR_INTCLR_CRSRIC_SHIFT (0U)
-#define LCD_CRSR_INTCLR_CRSRIC(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_INTCLR_CRSRIC_SHIFT)) & LCD_CRSR_INTCLR_CRSRIC_MASK)
-
-/*! @name CRSR_INTRAW - Cursor Raw Interrupt Status register */
-#define LCD_CRSR_INTRAW_CRSRRIS_MASK (0x1U)
-#define LCD_CRSR_INTRAW_CRSRRIS_SHIFT (0U)
-#define LCD_CRSR_INTRAW_CRSRRIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_INTRAW_CRSRRIS_SHIFT)) & LCD_CRSR_INTRAW_CRSRRIS_MASK)
-
-/*! @name CRSR_INTSTAT - Cursor Masked Interrupt Status register */
-#define LCD_CRSR_INTSTAT_CRSRMIS_MASK (0x1U)
-#define LCD_CRSR_INTSTAT_CRSRMIS_SHIFT (0U)
-#define LCD_CRSR_INTSTAT_CRSRMIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_INTSTAT_CRSRMIS_SHIFT)) & LCD_CRSR_INTSTAT_CRSRMIS_MASK)
-
-
-/*!
- * @}
- */ /* end of group LCD_Register_Masks */
-
-
-/* LCD - Peripheral instance base addresses */
-/** Peripheral LCD base address */
-#define LCD_BASE (0x40083000u)
-/** Peripheral LCD base pointer */
-#define LCD ((LCD_Type *)LCD_BASE)
-/** Array initializer of LCD peripheral base addresses */
-#define LCD_BASE_ADDRS { LCD_BASE }
-/** Array initializer of LCD peripheral base pointers */
-#define LCD_BASE_PTRS { LCD }
-/** Interrupt vectors for the LCD peripheral type */
-#define LCD_IRQS { LCD_IRQn }
-
-/*!
- * @}
- */ /* end of group LCD_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- MRT Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer
- * @{
- */
-
-/** MRT - Register Layout Typedef */
-typedef struct {
- struct { /* offset: 0x0, array step: 0x10 */
- __IO uint32_t INTVAL; /**< MRT Time interval value register. This value is loaded into the TIMER register., array offset: 0x0, array step: 0x10 */
- __I uint32_t TIMER; /**< MRT Timer register. This register reads the value of the down-counter., array offset: 0x4, array step: 0x10 */
- __IO uint32_t CTRL; /**< MRT Control register. This register controls the MRT modes., array offset: 0x8, array step: 0x10 */
- __IO uint32_t STAT; /**< MRT Status register., array offset: 0xC, array step: 0x10 */
- } CHANNEL[4];
- uint8_t RESERVED_0[176];
- __IO uint32_t MODCFG; /**< Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature., offset: 0xF0 */
- __I uint32_t IDLE_CH; /**< Idle channel register. This register returns the number of the first idle channel., offset: 0xF4 */
- __IO uint32_t IRQ_FLAG; /**< Global interrupt flag register, offset: 0xF8 */
-} MRT_Type;
-
-/* ----------------------------------------------------------------------------
- -- MRT Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup MRT_Register_Masks MRT Register Masks
- * @{
- */
-
-/*! @name CHANNEL_INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. */
-#define MRT_CHANNEL_INTVAL_IVALUE_MASK (0xFFFFFFU)
-#define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U)
-#define MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK)
-#define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U)
-#define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U)
-#define MRT_CHANNEL_INTVAL_LOAD(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK)
-
-/* The count of MRT_CHANNEL_INTVAL */
-#define MRT_CHANNEL_INTVAL_COUNT (4U)
-
-/*! @name CHANNEL_TIMER - MRT Timer register. This register reads the value of the down-counter. */
-#define MRT_CHANNEL_TIMER_VALUE_MASK (0xFFFFFFU)
-#define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U)
-#define MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK)
-
-/* The count of MRT_CHANNEL_TIMER */
-#define MRT_CHANNEL_TIMER_COUNT (4U)
-
-/*! @name CHANNEL_CTRL - MRT Control register. This register controls the MRT modes. */
-#define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U)
-#define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U)
-#define MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK)
-#define MRT_CHANNEL_CTRL_MODE_MASK (0x6U)
-#define MRT_CHANNEL_CTRL_MODE_SHIFT (1U)
-#define MRT_CHANNEL_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK)
-
-/* The count of MRT_CHANNEL_CTRL */
-#define MRT_CHANNEL_CTRL_COUNT (4U)
-
-/*! @name CHANNEL_STAT - MRT Status register. */
-#define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U)
-#define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U)
-#define MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK)
-#define MRT_CHANNEL_STAT_RUN_MASK (0x2U)
-#define MRT_CHANNEL_STAT_RUN_SHIFT (1U)
-#define MRT_CHANNEL_STAT_RUN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK)
-#define MRT_CHANNEL_STAT_INUSE_MASK (0x4U)
-#define MRT_CHANNEL_STAT_INUSE_SHIFT (2U)
-#define MRT_CHANNEL_STAT_INUSE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK)
-
-/* The count of MRT_CHANNEL_STAT */
-#define MRT_CHANNEL_STAT_COUNT (4U)
-
-/*! @name MODCFG - Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature. */
-#define MRT_MODCFG_NOC_MASK (0xFU)
-#define MRT_MODCFG_NOC_SHIFT (0U)
-#define MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK)
-#define MRT_MODCFG_NOB_MASK (0x1F0U)
-#define MRT_MODCFG_NOB_SHIFT (4U)
-#define MRT_MODCFG_NOB(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK)
-#define MRT_MODCFG_MULTITASK_MASK (0x80000000U)
-#define MRT_MODCFG_MULTITASK_SHIFT (31U)
-#define MRT_MODCFG_MULTITASK(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK)
-
-/*! @name IDLE_CH - Idle channel register. This register returns the number of the first idle channel. */
-#define MRT_IDLE_CH_CHAN_MASK (0xF0U)
-#define MRT_IDLE_CH_CHAN_SHIFT (4U)
-#define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK)
-
-/*! @name IRQ_FLAG - Global interrupt flag register */
-#define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U)
-#define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U)
-#define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK)
-#define MRT_IRQ_FLAG_GFLAG1_MASK (0x2U)
-#define MRT_IRQ_FLAG_GFLAG1_SHIFT (1U)
-#define MRT_IRQ_FLAG_GFLAG1(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK)
-#define MRT_IRQ_FLAG_GFLAG2_MASK (0x4U)
-#define MRT_IRQ_FLAG_GFLAG2_SHIFT (2U)
-#define MRT_IRQ_FLAG_GFLAG2(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK)
-#define MRT_IRQ_FLAG_GFLAG3_MASK (0x8U)
-#define MRT_IRQ_FLAG_GFLAG3_SHIFT (3U)
-#define MRT_IRQ_FLAG_GFLAG3(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK)
-
-
-/*!
- * @}
- */ /* end of group MRT_Register_Masks */
-
-
-/* MRT - Peripheral instance base addresses */
-/** Peripheral MRT0 base address */
-#define MRT0_BASE (0x4000D000u)
-/** Peripheral MRT0 base pointer */
-#define MRT0 ((MRT_Type *)MRT0_BASE)
-/** Array initializer of MRT peripheral base addresses */
-#define MRT_BASE_ADDRS { MRT0_BASE }
-/** Array initializer of MRT peripheral base pointers */
-#define MRT_BASE_PTRS { MRT0 }
-/** Interrupt vectors for the MRT peripheral type */
-#define MRT_IRQS { MRT0_IRQn }
-
-/*!
- * @}
- */ /* end of group MRT_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- OTPC Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup OTPC_Peripheral_Access_Layer OTPC Peripheral Access Layer
- * @{
- */
-
-/** OTPC - Register Layout Typedef */
-typedef struct {
- uint8_t RESERVED_0[16];
- __I uint32_t AESKEY[8]; /**< Register for reading the AES key., array offset: 0x10, array step: 0x4 */
- __I uint32_t ECRP; /**< ECRP options., offset: 0x30 */
- uint8_t RESERVED_1[4];
- __I uint32_t USER0; /**< User application specific options., offset: 0x38 */
- __I uint32_t USER1; /**< User application specific options., offset: 0x3C */
-} OTPC_Type;
-
-/* ----------------------------------------------------------------------------
- -- OTPC Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup OTPC_Register_Masks OTPC Register Masks
- * @{
- */
-
-/*! @name AESKEY - Register for reading the AES key. */
-#define OTPC_AESKEY_KEY_MASK (0xFFFFFFFFU)
-#define OTPC_AESKEY_KEY_SHIFT (0U)
-#define OTPC_AESKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << OTPC_AESKEY_KEY_SHIFT)) & OTPC_AESKEY_KEY_MASK)
-
-/* The count of OTPC_AESKEY */
-#define OTPC_AESKEY_COUNT (8U)
-
-/*! @name ECRP - ECRP options. */
-#define OTPC_ECRP_CRP_MASS_ERASE_DISABLE_MASK (0x10U)
-#define OTPC_ECRP_CRP_MASS_ERASE_DISABLE_SHIFT (4U)
-#define OTPC_ECRP_CRP_MASS_ERASE_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_CRP_MASS_ERASE_DISABLE_SHIFT)) & OTPC_ECRP_CRP_MASS_ERASE_DISABLE_MASK)
-#define OTPC_ECRP_IAP_PROTECTION_ENABLE_MASK (0x20U)
-#define OTPC_ECRP_IAP_PROTECTION_ENABLE_SHIFT (5U)
-#define OTPC_ECRP_IAP_PROTECTION_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_IAP_PROTECTION_ENABLE_SHIFT)) & OTPC_ECRP_IAP_PROTECTION_ENABLE_MASK)
-#define OTPC_ECRP_CRP_ISP_DISABLE_PIN_MASK (0x40U)
-#define OTPC_ECRP_CRP_ISP_DISABLE_PIN_SHIFT (6U)
-#define OTPC_ECRP_CRP_ISP_DISABLE_PIN(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_CRP_ISP_DISABLE_PIN_SHIFT)) & OTPC_ECRP_CRP_ISP_DISABLE_PIN_MASK)
-#define OTPC_ECRP_CRP_ISP_DISABLE_IAP_MASK (0x80U)
-#define OTPC_ECRP_CRP_ISP_DISABLE_IAP_SHIFT (7U)
-#define OTPC_ECRP_CRP_ISP_DISABLE_IAP(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_CRP_ISP_DISABLE_IAP_SHIFT)) & OTPC_ECRP_CRP_ISP_DISABLE_IAP_MASK)
-#define OTPC_ECRP_CRP_ALLOW_ZERO_MASK (0x200U)
-#define OTPC_ECRP_CRP_ALLOW_ZERO_SHIFT (9U)
-#define OTPC_ECRP_CRP_ALLOW_ZERO(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_CRP_ALLOW_ZERO_SHIFT)) & OTPC_ECRP_CRP_ALLOW_ZERO_MASK)
-#define OTPC_ECRP_JTAG_DISABLE_MASK (0x80000000U)
-#define OTPC_ECRP_JTAG_DISABLE_SHIFT (31U)
-#define OTPC_ECRP_JTAG_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_JTAG_DISABLE_SHIFT)) & OTPC_ECRP_JTAG_DISABLE_MASK)
-
-/*! @name USER0 - User application specific options. */
-#define OTPC_USER0_USER0_MASK (0xFFFFFFFFU)
-#define OTPC_USER0_USER0_SHIFT (0U)
-#define OTPC_USER0_USER0(x) (((uint32_t)(((uint32_t)(x)) << OTPC_USER0_USER0_SHIFT)) & OTPC_USER0_USER0_MASK)
-
-/*! @name USER1 - User application specific options. */
-#define OTPC_USER1_USER1_MASK (0xFFFFFFFFU)
-#define OTPC_USER1_USER1_SHIFT (0U)
-#define OTPC_USER1_USER1(x) (((uint32_t)(((uint32_t)(x)) << OTPC_USER1_USER1_SHIFT)) & OTPC_USER1_USER1_MASK)
-
-
-/*!
- * @}
- */ /* end of group OTPC_Register_Masks */
-
-
-/* OTPC - Peripheral instance base addresses */
-/** Peripheral OTPC base address */
-#define OTPC_BASE (0x40015000u)
-/** Peripheral OTPC base pointer */
-#define OTPC ((OTPC_Type *)OTPC_BASE)
-/** Array initializer of OTPC peripheral base addresses */
-#define OTPC_BASE_ADDRS { OTPC_BASE }
-/** Array initializer of OTPC peripheral base pointers */
-#define OTPC_BASE_PTRS { OTPC }
-
-/*!
- * @}
- */ /* end of group OTPC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- PINT Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer
- * @{
- */
-
-/** PINT - Register Layout Typedef */
-typedef struct {
- __IO uint32_t ISEL; /**< Pin Interrupt Mode register, offset: 0x0 */
- __IO uint32_t IENR; /**< Pin interrupt level or rising edge interrupt enable register, offset: 0x4 */
- __O uint32_t SIENR; /**< Pin interrupt level or rising edge interrupt set register, offset: 0x8 */
- __O uint32_t CIENR; /**< Pin interrupt level (rising edge interrupt) clear register, offset: 0xC */
- __IO uint32_t IENF; /**< Pin interrupt active level or falling edge interrupt enable register, offset: 0x10 */
- __O uint32_t SIENF; /**< Pin interrupt active level or falling edge interrupt set register, offset: 0x14 */
- __O uint32_t CIENF; /**< Pin interrupt active level or falling edge interrupt clear register, offset: 0x18 */
- __IO uint32_t RISE; /**< Pin interrupt rising edge register, offset: 0x1C */
- __IO uint32_t FALL; /**< Pin interrupt falling edge register, offset: 0x20 */
- __IO uint32_t IST; /**< Pin interrupt status register, offset: 0x24 */
- __IO uint32_t PMCTRL; /**< Pattern match interrupt control register, offset: 0x28 */
- __IO uint32_t PMSRC; /**< Pattern match interrupt bit-slice source register, offset: 0x2C */
- __IO uint32_t PMCFG; /**< Pattern match interrupt bit slice configuration register, offset: 0x30 */
-} PINT_Type;
-
-/* ----------------------------------------------------------------------------
- -- PINT Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup PINT_Register_Masks PINT Register Masks
- * @{
- */
-
-/*! @name ISEL - Pin Interrupt Mode register */
-#define PINT_ISEL_PMODE_MASK (0xFFU)
-#define PINT_ISEL_PMODE_SHIFT (0U)
-#define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK)
-
-/*! @name IENR - Pin interrupt level or rising edge interrupt enable register */
-#define PINT_IENR_ENRL_MASK (0xFFU)
-#define PINT_IENR_ENRL_SHIFT (0U)
-#define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK)
-
-/*! @name SIENR - Pin interrupt level or rising edge interrupt set register */
-#define PINT_SIENR_SETENRL_MASK (0xFFU)
-#define PINT_SIENR_SETENRL_SHIFT (0U)
-#define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK)
-
-/*! @name CIENR - Pin interrupt level (rising edge interrupt) clear register */
-#define PINT_CIENR_CENRL_MASK (0xFFU)
-#define PINT_CIENR_CENRL_SHIFT (0U)
-#define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK)
-
-/*! @name IENF - Pin interrupt active level or falling edge interrupt enable register */
-#define PINT_IENF_ENAF_MASK (0xFFU)
-#define PINT_IENF_ENAF_SHIFT (0U)
-#define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK)
-
-/*! @name SIENF - Pin interrupt active level or falling edge interrupt set register */
-#define PINT_SIENF_SETENAF_MASK (0xFFU)
-#define PINT_SIENF_SETENAF_SHIFT (0U)
-#define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK)
-
-/*! @name CIENF - Pin interrupt active level or falling edge interrupt clear register */
-#define PINT_CIENF_CENAF_MASK (0xFFU)
-#define PINT_CIENF_CENAF_SHIFT (0U)
-#define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK)
-
-/*! @name RISE - Pin interrupt rising edge register */
-#define PINT_RISE_RDET_MASK (0xFFU)
-#define PINT_RISE_RDET_SHIFT (0U)
-#define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK)
-
-/*! @name FALL - Pin interrupt falling edge register */
-#define PINT_FALL_FDET_MASK (0xFFU)
-#define PINT_FALL_FDET_SHIFT (0U)
-#define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK)
-
-/*! @name IST - Pin interrupt status register */
-#define PINT_IST_PSTAT_MASK (0xFFU)
-#define PINT_IST_PSTAT_SHIFT (0U)
-#define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK)
-
-/*! @name PMCTRL - Pattern match interrupt control register */
-#define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U)
-#define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U)
-#define PINT_PMCTRL_SEL_PMATCH(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK)
-#define PINT_PMCTRL_ENA_RXEV_MASK (0x2U)
-#define PINT_PMCTRL_ENA_RXEV_SHIFT (1U)
-#define PINT_PMCTRL_ENA_RXEV(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK)
-#define PINT_PMCTRL_PMAT_MASK (0xFF000000U)
-#define PINT_PMCTRL_PMAT_SHIFT (24U)
-#define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK)
-
-/*! @name PMSRC - Pattern match interrupt bit-slice source register */
-#define PINT_PMSRC_SRC0_MASK (0x700U)
-#define PINT_PMSRC_SRC0_SHIFT (8U)
-#define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK)
-#define PINT_PMSRC_SRC1_MASK (0x3800U)
-#define PINT_PMSRC_SRC1_SHIFT (11U)
-#define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK)
-#define PINT_PMSRC_SRC2_MASK (0x1C000U)
-#define PINT_PMSRC_SRC2_SHIFT (14U)
-#define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK)
-#define PINT_PMSRC_SRC3_MASK (0xE0000U)
-#define PINT_PMSRC_SRC3_SHIFT (17U)
-#define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK)
-#define PINT_PMSRC_SRC4_MASK (0x700000U)
-#define PINT_PMSRC_SRC4_SHIFT (20U)
-#define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK)
-#define PINT_PMSRC_SRC5_MASK (0x3800000U)
-#define PINT_PMSRC_SRC5_SHIFT (23U)
-#define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK)
-#define PINT_PMSRC_SRC6_MASK (0x1C000000U)
-#define PINT_PMSRC_SRC6_SHIFT (26U)
-#define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK)
-#define PINT_PMSRC_SRC7_MASK (0xE0000000U)
-#define PINT_PMSRC_SRC7_SHIFT (29U)
-#define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK)
-
-/*! @name PMCFG - Pattern match interrupt bit slice configuration register */
-#define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U)
-#define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U)
-#define PINT_PMCFG_PROD_ENDPTS0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK)
-#define PINT_PMCFG_PROD_ENDPTS1_MASK (0x2U)
-#define PINT_PMCFG_PROD_ENDPTS1_SHIFT (1U)
-#define PINT_PMCFG_PROD_ENDPTS1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK)
-#define PINT_PMCFG_PROD_ENDPTS2_MASK (0x4U)
-#define PINT_PMCFG_PROD_ENDPTS2_SHIFT (2U)
-#define PINT_PMCFG_PROD_ENDPTS2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK)
-#define PINT_PMCFG_PROD_ENDPTS3_MASK (0x8U)
-#define PINT_PMCFG_PROD_ENDPTS3_SHIFT (3U)
-#define PINT_PMCFG_PROD_ENDPTS3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK)
-#define PINT_PMCFG_PROD_ENDPTS4_MASK (0x10U)
-#define PINT_PMCFG_PROD_ENDPTS4_SHIFT (4U)
-#define PINT_PMCFG_PROD_ENDPTS4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK)
-#define PINT_PMCFG_PROD_ENDPTS5_MASK (0x20U)
-#define PINT_PMCFG_PROD_ENDPTS5_SHIFT (5U)
-#define PINT_PMCFG_PROD_ENDPTS5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK)
-#define PINT_PMCFG_PROD_ENDPTS6_MASK (0x40U)
-#define PINT_PMCFG_PROD_ENDPTS6_SHIFT (6U)
-#define PINT_PMCFG_PROD_ENDPTS6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK)
-#define PINT_PMCFG_CFG0_MASK (0x700U)
-#define PINT_PMCFG_CFG0_SHIFT (8U)
-#define PINT_PMCFG_CFG0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK)
-#define PINT_PMCFG_CFG1_MASK (0x3800U)
-#define PINT_PMCFG_CFG1_SHIFT (11U)
-#define PINT_PMCFG_CFG1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK)
-#define PINT_PMCFG_CFG2_MASK (0x1C000U)
-#define PINT_PMCFG_CFG2_SHIFT (14U)
-#define PINT_PMCFG_CFG2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK)
-#define PINT_PMCFG_CFG3_MASK (0xE0000U)
-#define PINT_PMCFG_CFG3_SHIFT (17U)
-#define PINT_PMCFG_CFG3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK)
-#define PINT_PMCFG_CFG4_MASK (0x700000U)
-#define PINT_PMCFG_CFG4_SHIFT (20U)
-#define PINT_PMCFG_CFG4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK)
-#define PINT_PMCFG_CFG5_MASK (0x3800000U)
-#define PINT_PMCFG_CFG5_SHIFT (23U)
-#define PINT_PMCFG_CFG5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK)
-#define PINT_PMCFG_CFG6_MASK (0x1C000000U)
-#define PINT_PMCFG_CFG6_SHIFT (26U)
-#define PINT_PMCFG_CFG6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK)
-#define PINT_PMCFG_CFG7_MASK (0xE0000000U)
-#define PINT_PMCFG_CFG7_SHIFT (29U)
-#define PINT_PMCFG_CFG7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK)
-
-
-/*!
- * @}
- */ /* end of group PINT_Register_Masks */
-
-
-/* PINT - Peripheral instance base addresses */
-/** Peripheral PINT base address */
-#define PINT_BASE (0x40004000u)
-/** Peripheral PINT base pointer */
-#define PINT ((PINT_Type *)PINT_BASE)
-/** Array initializer of PINT peripheral base addresses */
-#define PINT_BASE_ADDRS { PINT_BASE }
-/** Array initializer of PINT peripheral base pointers */
-#define PINT_BASE_PTRS { PINT }
-/** Interrupt vectors for the PINT peripheral type */
-#define PINT_IRQS { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn, PIN_INT4_IRQn, PIN_INT5_IRQn, PIN_INT6_IRQn, PIN_INT7_IRQn }
-
-/*!
- * @}
- */ /* end of group PINT_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- RIT Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RIT_Peripheral_Access_Layer RIT Peripheral Access Layer
- * @{
- */
-
-/** RIT - Register Layout Typedef */
-typedef struct {
- __IO uint32_t COMPVAL; /**< Compare value LSB register, offset: 0x0 */
- __IO uint32_t MASK; /**< Mask LSB register, offset: 0x4 */
- __IO uint32_t CTRL; /**< Control register, offset: 0x8 */
- __IO uint32_t COUNTER; /**< Counter LSB register, offset: 0xC */
- __IO uint32_t COMPVAL_H; /**< Compare value MSB register, offset: 0x10 */
- __IO uint32_t MASK_H; /**< Mask MSB register, offset: 0x14 */
- uint8_t RESERVED_0[4];
- __IO uint32_t COUNTER_H; /**< Counter MSB register, offset: 0x1C */
-} RIT_Type;
-
-/* ----------------------------------------------------------------------------
- -- RIT Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RIT_Register_Masks RIT Register Masks
- * @{
- */
-
-/*! @name COMPVAL - Compare value LSB register */
-#define RIT_COMPVAL_RICOMP_MASK (0xFFFFFFFFU)
-#define RIT_COMPVAL_RICOMP_SHIFT (0U)
-#define RIT_COMPVAL_RICOMP(x) (((uint32_t)(((uint32_t)(x)) << RIT_COMPVAL_RICOMP_SHIFT)) & RIT_COMPVAL_RICOMP_MASK)
-
-/*! @name MASK - Mask LSB register */
-#define RIT_MASK_RIMASK_MASK (0xFFFFFFFFU)
-#define RIT_MASK_RIMASK_SHIFT (0U)
-#define RIT_MASK_RIMASK(x) (((uint32_t)(((uint32_t)(x)) << RIT_MASK_RIMASK_SHIFT)) & RIT_MASK_RIMASK_MASK)
-
-/*! @name CTRL - Control register */
-#define RIT_CTRL_RITINT_MASK (0x1U)
-#define RIT_CTRL_RITINT_SHIFT (0U)
-#define RIT_CTRL_RITINT(x) (((uint32_t)(((uint32_t)(x)) << RIT_CTRL_RITINT_SHIFT)) & RIT_CTRL_RITINT_MASK)
-#define RIT_CTRL_RITENCLR_MASK (0x2U)
-#define RIT_CTRL_RITENCLR_SHIFT (1U)
-#define RIT_CTRL_RITENCLR(x) (((uint32_t)(((uint32_t)(x)) << RIT_CTRL_RITENCLR_SHIFT)) & RIT_CTRL_RITENCLR_MASK)
-#define RIT_CTRL_RITENBR_MASK (0x4U)
-#define RIT_CTRL_RITENBR_SHIFT (2U)
-#define RIT_CTRL_RITENBR(x) (((uint32_t)(((uint32_t)(x)) << RIT_CTRL_RITENBR_SHIFT)) & RIT_CTRL_RITENBR_MASK)
-#define RIT_CTRL_RITEN_MASK (0x8U)
-#define RIT_CTRL_RITEN_SHIFT (3U)
-#define RIT_CTRL_RITEN(x) (((uint32_t)(((uint32_t)(x)) << RIT_CTRL_RITEN_SHIFT)) & RIT_CTRL_RITEN_MASK)
-
-/*! @name COUNTER - Counter LSB register */
-#define RIT_COUNTER_RICOUNTER_MASK (0xFFFFFFFFU)
-#define RIT_COUNTER_RICOUNTER_SHIFT (0U)
-#define RIT_COUNTER_RICOUNTER(x) (((uint32_t)(((uint32_t)(x)) << RIT_COUNTER_RICOUNTER_SHIFT)) & RIT_COUNTER_RICOUNTER_MASK)
-
-/*! @name COMPVAL_H - Compare value MSB register */
-#define RIT_COMPVAL_H_RICOMP_MASK (0xFFFFU)
-#define RIT_COMPVAL_H_RICOMP_SHIFT (0U)
-#define RIT_COMPVAL_H_RICOMP(x) (((uint32_t)(((uint32_t)(x)) << RIT_COMPVAL_H_RICOMP_SHIFT)) & RIT_COMPVAL_H_RICOMP_MASK)
-
-/*! @name MASK_H - Mask MSB register */
-#define RIT_MASK_H_RIMASK_MASK (0xFFFFU)
-#define RIT_MASK_H_RIMASK_SHIFT (0U)
-#define RIT_MASK_H_RIMASK(x) (((uint32_t)(((uint32_t)(x)) << RIT_MASK_H_RIMASK_SHIFT)) & RIT_MASK_H_RIMASK_MASK)
-
-/*! @name COUNTER_H - Counter MSB register */
-#define RIT_COUNTER_H_RICOUNTER_MASK (0xFFFFU)
-#define RIT_COUNTER_H_RICOUNTER_SHIFT (0U)
-#define RIT_COUNTER_H_RICOUNTER(x) (((uint32_t)(((uint32_t)(x)) << RIT_COUNTER_H_RICOUNTER_SHIFT)) & RIT_COUNTER_H_RICOUNTER_MASK)
-
-
-/*!
- * @}
- */ /* end of group RIT_Register_Masks */
-
-
-/* RIT - Peripheral instance base addresses */
-/** Peripheral RIT base address */
-#define RIT_BASE (0x4002D000u)
-/** Peripheral RIT base pointer */
-#define RIT ((RIT_Type *)RIT_BASE)
-/** Array initializer of RIT peripheral base addresses */
-#define RIT_BASE_ADDRS { RIT_BASE }
-/** Array initializer of RIT peripheral base pointers */
-#define RIT_BASE_PTRS { RIT }
-/** Interrupt vectors for the RIT peripheral type */
-#define RIT_IRQS { RIT_IRQn }
-
-/*!
- * @}
- */ /* end of group RIT_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- RTC Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
- * @{
- */
-
-/** RTC - Register Layout Typedef */
-typedef struct {
- __IO uint32_t CTRL; /**< RTC control register, offset: 0x0 */
- __IO uint32_t MATCH; /**< RTC match register, offset: 0x4 */
- __IO uint32_t COUNT; /**< RTC counter register, offset: 0x8 */
- __IO uint32_t WAKE; /**< High-resolution/wake-up timer control register, offset: 0xC */
- uint8_t RESERVED_0[48];
- __IO uint32_t GPREG[8]; /**< General Purpose register, array offset: 0x40, array step: 0x4 */
-} RTC_Type;
-
-/* ----------------------------------------------------------------------------
- -- RTC Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup RTC_Register_Masks RTC Register Masks
- * @{
- */
-
-/*! @name CTRL - RTC control register */
-#define RTC_CTRL_SWRESET_MASK (0x1U)
-#define RTC_CTRL_SWRESET_SHIFT (0U)
-#define RTC_CTRL_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_SWRESET_SHIFT)) & RTC_CTRL_SWRESET_MASK)
-#define RTC_CTRL_ALARM1HZ_MASK (0x4U)
-#define RTC_CTRL_ALARM1HZ_SHIFT (2U)
-#define RTC_CTRL_ALARM1HZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARM1HZ_SHIFT)) & RTC_CTRL_ALARM1HZ_MASK)
-#define RTC_CTRL_WAKE1KHZ_MASK (0x8U)
-#define RTC_CTRL_WAKE1KHZ_SHIFT (3U)
-#define RTC_CTRL_WAKE1KHZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKE1KHZ_SHIFT)) & RTC_CTRL_WAKE1KHZ_MASK)
-#define RTC_CTRL_ALARMDPD_EN_MASK (0x10U)
-#define RTC_CTRL_ALARMDPD_EN_SHIFT (4U)
-#define RTC_CTRL_ALARMDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARMDPD_EN_SHIFT)) & RTC_CTRL_ALARMDPD_EN_MASK)
-#define RTC_CTRL_WAKEDPD_EN_MASK (0x20U)
-#define RTC_CTRL_WAKEDPD_EN_SHIFT (5U)
-#define RTC_CTRL_WAKEDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKEDPD_EN_SHIFT)) & RTC_CTRL_WAKEDPD_EN_MASK)
-#define RTC_CTRL_RTC1KHZ_EN_MASK (0x40U)
-#define RTC_CTRL_RTC1KHZ_EN_SHIFT (6U)
-#define RTC_CTRL_RTC1KHZ_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC1KHZ_EN_SHIFT)) & RTC_CTRL_RTC1KHZ_EN_MASK)
-#define RTC_CTRL_RTC_EN_MASK (0x80U)
-#define RTC_CTRL_RTC_EN_SHIFT (7U)
-#define RTC_CTRL_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_EN_SHIFT)) & RTC_CTRL_RTC_EN_MASK)
-#define RTC_CTRL_RTC_OSC_PD_MASK (0x100U)
-#define RTC_CTRL_RTC_OSC_PD_SHIFT (8U)
-#define RTC_CTRL_RTC_OSC_PD(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_PD_SHIFT)) & RTC_CTRL_RTC_OSC_PD_MASK)
-
-/*! @name MATCH - RTC match register */
-#define RTC_MATCH_MATVAL_MASK (0xFFFFFFFFU)
-#define RTC_MATCH_MATVAL_SHIFT (0U)
-#define RTC_MATCH_MATVAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_MATCH_MATVAL_SHIFT)) & RTC_MATCH_MATVAL_MASK)
-
-/*! @name COUNT - RTC counter register */
-#define RTC_COUNT_VAL_MASK (0xFFFFFFFFU)
-#define RTC_COUNT_VAL_SHIFT (0U)
-#define RTC_COUNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_COUNT_VAL_SHIFT)) & RTC_COUNT_VAL_MASK)
-
-/*! @name WAKE - High-resolution/wake-up timer control register */
-#define RTC_WAKE_VAL_MASK (0xFFFFU)
-#define RTC_WAKE_VAL_SHIFT (0U)
-#define RTC_WAKE_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_VAL_SHIFT)) & RTC_WAKE_VAL_MASK)
-
-/*! @name GPREG - General Purpose register */
-#define RTC_GPREG_GPDATA_MASK (0xFFFFFFFFU)
-#define RTC_GPREG_GPDATA_SHIFT (0U)
-#define RTC_GPREG_GPDATA(x) (((uint32_t)(((uint32_t)(x)) << RTC_GPREG_GPDATA_SHIFT)) & RTC_GPREG_GPDATA_MASK)
-
-/* The count of RTC_GPREG */
-#define RTC_GPREG_COUNT (8U)
-
-
-/*!
- * @}
- */ /* end of group RTC_Register_Masks */
-
-
-/* RTC - Peripheral instance base addresses */
-/** Peripheral RTC base address */
-#define RTC_BASE (0x4002C000u)
-/** Peripheral RTC base pointer */
-#define RTC ((RTC_Type *)RTC_BASE)
-/** Array initializer of RTC peripheral base addresses */
-#define RTC_BASE_ADDRS { RTC_BASE }
-/** Array initializer of RTC peripheral base pointers */
-#define RTC_BASE_PTRS { RTC }
-/** Interrupt vectors for the RTC peripheral type */
-#define RTC_IRQS { RTC_IRQn }
-
-/*!
- * @}
- */ /* end of group RTC_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- SCT Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SCT_Peripheral_Access_Layer SCT Peripheral Access Layer
- * @{
- */
-
-/** SCT - Register Layout Typedef */
-typedef struct {
- __IO uint32_t CONFIG; /**< SCT configuration register, offset: 0x0 */
- __IO uint32_t CTRL; /**< SCT control register, offset: 0x4 */
- __IO uint32_t LIMIT; /**< SCT limit event select register, offset: 0x8 */
- __IO uint32_t HALT; /**< SCT halt event select register, offset: 0xC */
- __IO uint32_t STOP; /**< SCT stop event select register, offset: 0x10 */
- __IO uint32_t START; /**< SCT start event select register, offset: 0x14 */
- uint8_t RESERVED_0[40];
- __IO uint32_t COUNT; /**< SCT counter register, offset: 0x40 */
- __IO uint32_t STATE; /**< SCT state register, offset: 0x44 */
- __I uint32_t INPUT; /**< SCT input register, offset: 0x48 */
- __IO uint32_t REGMODE; /**< SCT match/capture mode register, offset: 0x4C */
- __IO uint32_t OUTPUT; /**< SCT output register, offset: 0x50 */
- __IO uint32_t OUTPUTDIRCTRL; /**< SCT output counter direction control register, offset: 0x54 */
- __IO uint32_t RES; /**< SCT conflict resolution register, offset: 0x58 */
- __IO uint32_t DMA0REQUEST; /**< SCT DMA request 0 register, offset: 0x5C */
- __IO uint32_t DMA1REQUEST; /**< SCT DMA request 1 register, offset: 0x60 */
- uint8_t RESERVED_1[140];
- __IO uint32_t EVEN; /**< SCT event interrupt enable register, offset: 0xF0 */
- __IO uint32_t EVFLAG; /**< SCT event flag register, offset: 0xF4 */
- __IO uint32_t CONEN; /**< SCT conflict interrupt enable register, offset: 0xF8 */
- __IO uint32_t CONFLAG; /**< SCT conflict flag register, offset: 0xFC */
- union { /* offset: 0x100 */
- __IO uint32_t SCTCAP[10]; /**< SCT capture register of capture channel, array offset: 0x100, array step: 0x4 */
- __IO uint32_t SCTMATCH[10]; /**< SCT match value register of match channels, array offset: 0x100, array step: 0x4 */
- };
- uint8_t RESERVED_2[216];
- union { /* offset: 0x200 */
- __IO uint32_t SCTCAPCTRL[10]; /**< SCT capture control register, array offset: 0x200, array step: 0x4 */
- __IO uint32_t SCTMATCHREL[10]; /**< SCT match reload value register, array offset: 0x200, array step: 0x4 */
- };
- uint8_t RESERVED_3[216];
- struct { /* offset: 0x300, array step: 0x8 */
- __IO uint32_t STATE; /**< SCT event state register 0, array offset: 0x300, array step: 0x8 */
- __IO uint32_t CTRL; /**< SCT event control register 0, array offset: 0x304, array step: 0x8 */
- } EVENT[10];
- uint8_t RESERVED_4[432];
- struct { /* offset: 0x500, array step: 0x8 */
- __IO uint32_t SET; /**< SCT output 0 set register, array offset: 0x500, array step: 0x8 */
- __IO uint32_t CLR; /**< SCT output 0 clear register, array offset: 0x504, array step: 0x8 */
- } OUT[10];
-} SCT_Type;
-
-/* ----------------------------------------------------------------------------
- -- SCT Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SCT_Register_Masks SCT Register Masks
- * @{
- */
-
-/*! @name CONFIG - SCT configuration register */
-#define SCT_CONFIG_UNIFY_MASK (0x1U)
-#define SCT_CONFIG_UNIFY_SHIFT (0U)
-#define SCT_CONFIG_UNIFY(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK)
-#define SCT_CONFIG_CLKMODE_MASK (0x6U)
-#define SCT_CONFIG_CLKMODE_SHIFT (1U)
-#define SCT_CONFIG_CLKMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK)
-#define SCT_CONFIG_CKSEL_MASK (0x78U)
-#define SCT_CONFIG_CKSEL_SHIFT (3U)
-#define SCT_CONFIG_CKSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK)
-#define SCT_CONFIG_NORELAOD_L_MASK (0x80U)
-#define SCT_CONFIG_NORELAOD_L_SHIFT (7U)
-#define SCT_CONFIG_NORELAOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELAOD_L_SHIFT)) & SCT_CONFIG_NORELAOD_L_MASK)
-#define SCT_CONFIG_NORELOAD_H_MASK (0x100U)
-#define SCT_CONFIG_NORELOAD_H_SHIFT (8U)
-#define SCT_CONFIG_NORELOAD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK)
-#define SCT_CONFIG_INSYNC_MASK (0x1E00U)
-#define SCT_CONFIG_INSYNC_SHIFT (9U)
-#define SCT_CONFIG_INSYNC(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK)
-#define SCT_CONFIG_AUTOLIMIT_L_MASK (0x20000U)
-#define SCT_CONFIG_AUTOLIMIT_L_SHIFT (17U)
-#define SCT_CONFIG_AUTOLIMIT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK)
-#define SCT_CONFIG_AUTOLIMIT_H_MASK (0x40000U)
-#define SCT_CONFIG_AUTOLIMIT_H_SHIFT (18U)
-#define SCT_CONFIG_AUTOLIMIT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK)
-
-/*! @name CTRL - SCT control register */
-#define SCT_CTRL_DOWN_L_MASK (0x1U)
-#define SCT_CTRL_DOWN_L_SHIFT (0U)
-#define SCT_CTRL_DOWN_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK)
-#define SCT_CTRL_STOP_L_MASK (0x2U)
-#define SCT_CTRL_STOP_L_SHIFT (1U)
-#define SCT_CTRL_STOP_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK)
-#define SCT_CTRL_HALT_L_MASK (0x4U)
-#define SCT_CTRL_HALT_L_SHIFT (2U)
-#define SCT_CTRL_HALT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK)
-#define SCT_CTRL_CLRCTR_L_MASK (0x8U)
-#define SCT_CTRL_CLRCTR_L_SHIFT (3U)
-#define SCT_CTRL_CLRCTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK)
-#define SCT_CTRL_BIDIR_L_MASK (0x10U)
-#define SCT_CTRL_BIDIR_L_SHIFT (4U)
-#define SCT_CTRL_BIDIR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK)
-#define SCT_CTRL_PRE_L_MASK (0x1FE0U)
-#define SCT_CTRL_PRE_L_SHIFT (5U)
-#define SCT_CTRL_PRE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK)
-#define SCT_CTRL_DOWN_H_MASK (0x10000U)
-#define SCT_CTRL_DOWN_H_SHIFT (16U)
-#define SCT_CTRL_DOWN_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK)
-#define SCT_CTRL_STOP_H_MASK (0x20000U)
-#define SCT_CTRL_STOP_H_SHIFT (17U)
-#define SCT_CTRL_STOP_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK)
-#define SCT_CTRL_HALT_H_MASK (0x40000U)
-#define SCT_CTRL_HALT_H_SHIFT (18U)
-#define SCT_CTRL_HALT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK)
-#define SCT_CTRL_CLRCTR_H_MASK (0x80000U)
-#define SCT_CTRL_CLRCTR_H_SHIFT (19U)
-#define SCT_CTRL_CLRCTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK)
-#define SCT_CTRL_BIDIR_H_MASK (0x100000U)
-#define SCT_CTRL_BIDIR_H_SHIFT (20U)
-#define SCT_CTRL_BIDIR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK)
-#define SCT_CTRL_PRE_H_MASK (0x1FE00000U)
-#define SCT_CTRL_PRE_H_SHIFT (21U)
-#define SCT_CTRL_PRE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK)
-
-/*! @name LIMIT - SCT limit event select register */
-#define SCT_LIMIT_LIMMSK_L_MASK (0xFFFFU)
-#define SCT_LIMIT_LIMMSK_L_SHIFT (0U)
-#define SCT_LIMIT_LIMMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK)
-#define SCT_LIMIT_LIMMSK_H_MASK (0xFFFF0000U)
-#define SCT_LIMIT_LIMMSK_H_SHIFT (16U)
-#define SCT_LIMIT_LIMMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK)
-
-/*! @name HALT - SCT halt event select register */
-#define SCT_HALT_HALTMSK_L_MASK (0xFFFFU)
-#define SCT_HALT_HALTMSK_L_SHIFT (0U)
-#define SCT_HALT_HALTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK)
-#define SCT_HALT_HALTMSK_H_MASK (0xFFFF0000U)
-#define SCT_HALT_HALTMSK_H_SHIFT (16U)
-#define SCT_HALT_HALTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK)
-
-/*! @name STOP - SCT stop event select register */
-#define SCT_STOP_STOPMSK_L_MASK (0xFFFFU)
-#define SCT_STOP_STOPMSK_L_SHIFT (0U)
-#define SCT_STOP_STOPMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK)
-#define SCT_STOP_STOPMSK_H_MASK (0xFFFF0000U)
-#define SCT_STOP_STOPMSK_H_SHIFT (16U)
-#define SCT_STOP_STOPMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK)
-
-/*! @name START - SCT start event select register */
-#define SCT_START_STARTMSK_L_MASK (0xFFFFU)
-#define SCT_START_STARTMSK_L_SHIFT (0U)
-#define SCT_START_STARTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK)
-#define SCT_START_STARTMSK_H_MASK (0xFFFF0000U)
-#define SCT_START_STARTMSK_H_SHIFT (16U)
-#define SCT_START_STARTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK)
-
-/*! @name COUNT - SCT counter register */
-#define SCT_COUNT_CTR_L_MASK (0xFFFFU)
-#define SCT_COUNT_CTR_L_SHIFT (0U)
-#define SCT_COUNT_CTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK)
-#define SCT_COUNT_CTR_H_MASK (0xFFFF0000U)
-#define SCT_COUNT_CTR_H_SHIFT (16U)
-#define SCT_COUNT_CTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK)
-
-/*! @name STATE - SCT state register */
-#define SCT_STATE_STATE_L_MASK (0x1FU)
-#define SCT_STATE_STATE_L_SHIFT (0U)
-#define SCT_STATE_STATE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK)
-#define SCT_STATE_STATE_H_MASK (0x1F0000U)
-#define SCT_STATE_STATE_H_SHIFT (16U)
-#define SCT_STATE_STATE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK)
-
-/*! @name INPUT - SCT input register */
-#define SCT_INPUT_AIN0_MASK (0x1U)
-#define SCT_INPUT_AIN0_SHIFT (0U)
-#define SCT_INPUT_AIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK)
-#define SCT_INPUT_AIN1_MASK (0x2U)
-#define SCT_INPUT_AIN1_SHIFT (1U)
-#define SCT_INPUT_AIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK)
-#define SCT_INPUT_AIN2_MASK (0x4U)
-#define SCT_INPUT_AIN2_SHIFT (2U)
-#define SCT_INPUT_AIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK)
-#define SCT_INPUT_AIN3_MASK (0x8U)
-#define SCT_INPUT_AIN3_SHIFT (3U)
-#define SCT_INPUT_AIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK)
-#define SCT_INPUT_AIN4_MASK (0x10U)
-#define SCT_INPUT_AIN4_SHIFT (4U)
-#define SCT_INPUT_AIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK)
-#define SCT_INPUT_AIN5_MASK (0x20U)
-#define SCT_INPUT_AIN5_SHIFT (5U)
-#define SCT_INPUT_AIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK)
-#define SCT_INPUT_AIN6_MASK (0x40U)
-#define SCT_INPUT_AIN6_SHIFT (6U)
-#define SCT_INPUT_AIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK)
-#define SCT_INPUT_AIN7_MASK (0x80U)
-#define SCT_INPUT_AIN7_SHIFT (7U)
-#define SCT_INPUT_AIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK)
-#define SCT_INPUT_AIN8_MASK (0x100U)
-#define SCT_INPUT_AIN8_SHIFT (8U)
-#define SCT_INPUT_AIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK)
-#define SCT_INPUT_AIN9_MASK (0x200U)
-#define SCT_INPUT_AIN9_SHIFT (9U)
-#define SCT_INPUT_AIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK)
-#define SCT_INPUT_AIN10_MASK (0x400U)
-#define SCT_INPUT_AIN10_SHIFT (10U)
-#define SCT_INPUT_AIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK)
-#define SCT_INPUT_AIN11_MASK (0x800U)
-#define SCT_INPUT_AIN11_SHIFT (11U)
-#define SCT_INPUT_AIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK)
-#define SCT_INPUT_AIN12_MASK (0x1000U)
-#define SCT_INPUT_AIN12_SHIFT (12U)
-#define SCT_INPUT_AIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK)
-#define SCT_INPUT_AIN13_MASK (0x2000U)
-#define SCT_INPUT_AIN13_SHIFT (13U)
-#define SCT_INPUT_AIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK)
-#define SCT_INPUT_AIN14_MASK (0x4000U)
-#define SCT_INPUT_AIN14_SHIFT (14U)
-#define SCT_INPUT_AIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK)
-#define SCT_INPUT_AIN15_MASK (0x8000U)
-#define SCT_INPUT_AIN15_SHIFT (15U)
-#define SCT_INPUT_AIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK)
-#define SCT_INPUT_SIN0_MASK (0x10000U)
-#define SCT_INPUT_SIN0_SHIFT (16U)
-#define SCT_INPUT_SIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK)
-#define SCT_INPUT_SIN1_MASK (0x20000U)
-#define SCT_INPUT_SIN1_SHIFT (17U)
-#define SCT_INPUT_SIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK)
-#define SCT_INPUT_SIN2_MASK (0x40000U)
-#define SCT_INPUT_SIN2_SHIFT (18U)
-#define SCT_INPUT_SIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK)
-#define SCT_INPUT_SIN3_MASK (0x80000U)
-#define SCT_INPUT_SIN3_SHIFT (19U)
-#define SCT_INPUT_SIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK)
-#define SCT_INPUT_SIN4_MASK (0x100000U)
-#define SCT_INPUT_SIN4_SHIFT (20U)
-#define SCT_INPUT_SIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK)
-#define SCT_INPUT_SIN5_MASK (0x200000U)
-#define SCT_INPUT_SIN5_SHIFT (21U)
-#define SCT_INPUT_SIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK)
-#define SCT_INPUT_SIN6_MASK (0x400000U)
-#define SCT_INPUT_SIN6_SHIFT (22U)
-#define SCT_INPUT_SIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK)
-#define SCT_INPUT_SIN7_MASK (0x800000U)
-#define SCT_INPUT_SIN7_SHIFT (23U)
-#define SCT_INPUT_SIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK)
-#define SCT_INPUT_SIN8_MASK (0x1000000U)
-#define SCT_INPUT_SIN8_SHIFT (24U)
-#define SCT_INPUT_SIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK)
-#define SCT_INPUT_SIN9_MASK (0x2000000U)
-#define SCT_INPUT_SIN9_SHIFT (25U)
-#define SCT_INPUT_SIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK)
-#define SCT_INPUT_SIN10_MASK (0x4000000U)
-#define SCT_INPUT_SIN10_SHIFT (26U)
-#define SCT_INPUT_SIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK)
-#define SCT_INPUT_SIN11_MASK (0x8000000U)
-#define SCT_INPUT_SIN11_SHIFT (27U)
-#define SCT_INPUT_SIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK)
-#define SCT_INPUT_SIN12_MASK (0x10000000U)
-#define SCT_INPUT_SIN12_SHIFT (28U)
-#define SCT_INPUT_SIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK)
-#define SCT_INPUT_SIN13_MASK (0x20000000U)
-#define SCT_INPUT_SIN13_SHIFT (29U)
-#define SCT_INPUT_SIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK)
-#define SCT_INPUT_SIN14_MASK (0x40000000U)
-#define SCT_INPUT_SIN14_SHIFT (30U)
-#define SCT_INPUT_SIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK)
-#define SCT_INPUT_SIN15_MASK (0x80000000U)
-#define SCT_INPUT_SIN15_SHIFT (31U)
-#define SCT_INPUT_SIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK)
-
-/*! @name REGMODE - SCT match/capture mode register */
-#define SCT_REGMODE_REGMOD_L_MASK (0xFFFFU)
-#define SCT_REGMODE_REGMOD_L_SHIFT (0U)
-#define SCT_REGMODE_REGMOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK)
-#define SCT_REGMODE_REGMOD_H_MASK (0xFFFF0000U)
-#define SCT_REGMODE_REGMOD_H_SHIFT (16U)
-#define SCT_REGMODE_REGMOD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK)
-
-/*! @name OUTPUT - SCT output register */
-#define SCT_OUTPUT_OUT_MASK (0xFFFFU)
-#define SCT_OUTPUT_OUT_SHIFT (0U)
-#define SCT_OUTPUT_OUT(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT_SHIFT)) & SCT_OUTPUT_OUT_MASK)
-
-/*! @name OUTPUTDIRCTRL - SCT output counter direction control register */
-#define SCT_OUTPUTDIRCTRL_SETCLR0_MASK (0x3U)
-#define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT (0U)
-#define SCT_OUTPUTDIRCTRL_SETCLR0(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK)
-#define SCT_OUTPUTDIRCTRL_SETCLR1_MASK (0xCU)
-#define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT (2U)
-#define SCT_OUTPUTDIRCTRL_SETCLR1(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK)
-#define SCT_OUTPUTDIRCTRL_SETCLR2_MASK (0x30U)
-#define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT (4U)
-#define SCT_OUTPUTDIRCTRL_SETCLR2(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK)
-#define SCT_OUTPUTDIRCTRL_SETCLR3_MASK (0xC0U)
-#define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT (6U)
-#define SCT_OUTPUTDIRCTRL_SETCLR3(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK)
-#define SCT_OUTPUTDIRCTRL_SETCLR4_MASK (0x300U)
-#define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT (8U)
-#define SCT_OUTPUTDIRCTRL_SETCLR4(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK)
-#define SCT_OUTPUTDIRCTRL_SETCLR5_MASK (0xC00U)
-#define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT (10U)
-#define SCT_OUTPUTDIRCTRL_SETCLR5(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK)
-#define SCT_OUTPUTDIRCTRL_SETCLR6_MASK (0x3000U)
-#define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT (12U)
-#define SCT_OUTPUTDIRCTRL_SETCLR6(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK)
-#define SCT_OUTPUTDIRCTRL_SETCLR7_MASK (0xC000U)
-#define SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT (14U)
-#define SCT_OUTPUTDIRCTRL_SETCLR7(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK)
-#define SCT_OUTPUTDIRCTRL_SETCLR8_MASK (0x30000U)
-#define SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT (16U)
-#define SCT_OUTPUTDIRCTRL_SETCLR8(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK)
-#define SCT_OUTPUTDIRCTRL_SETCLR9_MASK (0xC0000U)
-#define SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT (18U)
-#define SCT_OUTPUTDIRCTRL_SETCLR9(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK)
-#define SCT_OUTPUTDIRCTRL_SETCLR10_MASK (0x300000U)
-#define SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT (20U)
-#define SCT_OUTPUTDIRCTRL_SETCLR10(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR10_MASK)
-#define SCT_OUTPUTDIRCTRL_SETCLR11_MASK (0xC00000U)
-#define SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT (22U)
-#define SCT_OUTPUTDIRCTRL_SETCLR11(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR11_MASK)
-#define SCT_OUTPUTDIRCTRL_SETCLR12_MASK (0x3000000U)
-#define SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT (24U)
-#define SCT_OUTPUTDIRCTRL_SETCLR12(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR12_MASK)
-#define SCT_OUTPUTDIRCTRL_SETCLR13_MASK (0xC000000U)
-#define SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT (26U)
-#define SCT_OUTPUTDIRCTRL_SETCLR13(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR13_MASK)
-#define SCT_OUTPUTDIRCTRL_SETCLR14_MASK (0x30000000U)
-#define SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT (28U)
-#define SCT_OUTPUTDIRCTRL_SETCLR14(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR14_MASK)
-#define SCT_OUTPUTDIRCTRL_SETCLR15_MASK (0xC0000000U)
-#define SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT (30U)
-#define SCT_OUTPUTDIRCTRL_SETCLR15(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR15_MASK)
-
-/*! @name RES - SCT conflict resolution register */
-#define SCT_RES_O0RES_MASK (0x3U)
-#define SCT_RES_O0RES_SHIFT (0U)
-#define SCT_RES_O0RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK)
-#define SCT_RES_O1RES_MASK (0xCU)
-#define SCT_RES_O1RES_SHIFT (2U)
-#define SCT_RES_O1RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK)
-#define SCT_RES_O2RES_MASK (0x30U)
-#define SCT_RES_O2RES_SHIFT (4U)
-#define SCT_RES_O2RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK)
-#define SCT_RES_O3RES_MASK (0xC0U)
-#define SCT_RES_O3RES_SHIFT (6U)
-#define SCT_RES_O3RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK)
-#define SCT_RES_O4RES_MASK (0x300U)
-#define SCT_RES_O4RES_SHIFT (8U)
-#define SCT_RES_O4RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK)
-#define SCT_RES_O5RES_MASK (0xC00U)
-#define SCT_RES_O5RES_SHIFT (10U)
-#define SCT_RES_O5RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK)
-#define SCT_RES_O6RES_MASK (0x3000U)
-#define SCT_RES_O6RES_SHIFT (12U)
-#define SCT_RES_O6RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK)
-#define SCT_RES_O7RES_MASK (0xC000U)
-#define SCT_RES_O7RES_SHIFT (14U)
-#define SCT_RES_O7RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK)
-#define SCT_RES_O8RES_MASK (0x30000U)
-#define SCT_RES_O8RES_SHIFT (16U)
-#define SCT_RES_O8RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK)
-#define SCT_RES_O9RES_MASK (0xC0000U)
-#define SCT_RES_O9RES_SHIFT (18U)
-#define SCT_RES_O9RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK)
-#define SCT_RES_O10RES_MASK (0x300000U)
-#define SCT_RES_O10RES_SHIFT (20U)
-#define SCT_RES_O10RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O10RES_SHIFT)) & SCT_RES_O10RES_MASK)
-#define SCT_RES_O11RES_MASK (0xC00000U)
-#define SCT_RES_O11RES_SHIFT (22U)
-#define SCT_RES_O11RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O11RES_SHIFT)) & SCT_RES_O11RES_MASK)
-#define SCT_RES_O12RES_MASK (0x3000000U)
-#define SCT_RES_O12RES_SHIFT (24U)
-#define SCT_RES_O12RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O12RES_SHIFT)) & SCT_RES_O12RES_MASK)
-#define SCT_RES_O13RES_MASK (0xC000000U)
-#define SCT_RES_O13RES_SHIFT (26U)
-#define SCT_RES_O13RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O13RES_SHIFT)) & SCT_RES_O13RES_MASK)
-#define SCT_RES_O14RES_MASK (0x30000000U)
-#define SCT_RES_O14RES_SHIFT (28U)
-#define SCT_RES_O14RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O14RES_SHIFT)) & SCT_RES_O14RES_MASK)
-#define SCT_RES_O15RES_MASK (0xC0000000U)
-#define SCT_RES_O15RES_SHIFT (30U)
-#define SCT_RES_O15RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O15RES_SHIFT)) & SCT_RES_O15RES_MASK)
-
-/*! @name DMA0REQUEST - SCT DMA request 0 register */
-#define SCT_DMA0REQUEST_DEV_0_MASK (0xFFFFU)
-#define SCT_DMA0REQUEST_DEV_0_SHIFT (0U)
-#define SCT_DMA0REQUEST_DEV_0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DEV_0_SHIFT)) & SCT_DMA0REQUEST_DEV_0_MASK)
-#define SCT_DMA0REQUEST_DRL0_MASK (0x40000000U)
-#define SCT_DMA0REQUEST_DRL0_SHIFT (30U)
-#define SCT_DMA0REQUEST_DRL0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DRL0_SHIFT)) & SCT_DMA0REQUEST_DRL0_MASK)
-#define SCT_DMA0REQUEST_DRQ0_MASK (0x80000000U)
-#define SCT_DMA0REQUEST_DRQ0_SHIFT (31U)
-#define SCT_DMA0REQUEST_DRQ0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DRQ0_SHIFT)) & SCT_DMA0REQUEST_DRQ0_MASK)
-
-/*! @name DMA1REQUEST - SCT DMA request 1 register */
-#define SCT_DMA1REQUEST_DEV_1_MASK (0xFFFFU)
-#define SCT_DMA1REQUEST_DEV_1_SHIFT (0U)
-#define SCT_DMA1REQUEST_DEV_1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DEV_1_SHIFT)) & SCT_DMA1REQUEST_DEV_1_MASK)
-#define SCT_DMA1REQUEST_DRL1_MASK (0x40000000U)
-#define SCT_DMA1REQUEST_DRL1_SHIFT (30U)
-#define SCT_DMA1REQUEST_DRL1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DRL1_SHIFT)) & SCT_DMA1REQUEST_DRL1_MASK)
-#define SCT_DMA1REQUEST_DRQ1_MASK (0x80000000U)
-#define SCT_DMA1REQUEST_DRQ1_SHIFT (31U)
-#define SCT_DMA1REQUEST_DRQ1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DRQ1_SHIFT)) & SCT_DMA1REQUEST_DRQ1_MASK)
-
-/*! @name EVEN - SCT event interrupt enable register */
-#define SCT_EVEN_IEN_MASK (0xFFFFU)
-#define SCT_EVEN_IEN_SHIFT (0U)
-#define SCT_EVEN_IEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN_SHIFT)) & SCT_EVEN_IEN_MASK)
-
-/*! @name EVFLAG - SCT event flag register */
-#define SCT_EVFLAG_FLAG_MASK (0xFFFFU)
-#define SCT_EVFLAG_FLAG_SHIFT (0U)
-#define SCT_EVFLAG_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG_SHIFT)) & SCT_EVFLAG_FLAG_MASK)
-
-/*! @name CONEN - SCT conflict interrupt enable register */
-#define SCT_CONEN_NCEN_MASK (0xFFFFU)
-#define SCT_CONEN_NCEN_SHIFT (0U)
-#define SCT_CONEN_NCEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN_SHIFT)) & SCT_CONEN_NCEN_MASK)
-
-/*! @name CONFLAG - SCT conflict flag register */
-#define SCT_CONFLAG_NCFLAG_MASK (0xFFFFU)
-#define SCT_CONFLAG_NCFLAG_SHIFT (0U)
-#define SCT_CONFLAG_NCFLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG_SHIFT)) & SCT_CONFLAG_NCFLAG_MASK)
-#define SCT_CONFLAG_BUSERRL_MASK (0x40000000U)
-#define SCT_CONFLAG_BUSERRL_SHIFT (30U)
-#define SCT_CONFLAG_BUSERRL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK)
-#define SCT_CONFLAG_BUSERRH_MASK (0x80000000U)
-#define SCT_CONFLAG_BUSERRH_SHIFT (31U)
-#define SCT_CONFLAG_BUSERRH(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK)
-
-/*! @name SCTCAP - SCT capture register of capture channel */
-#define SCT_SCTCAP_CAPn_L_MASK (0xFFFFU)
-#define SCT_SCTCAP_CAPn_L_SHIFT (0U)
-#define SCT_SCTCAP_CAPn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_L_SHIFT)) & SCT_SCTCAP_CAPn_L_MASK)
-#define SCT_SCTCAP_CAPn_H_MASK (0xFFFF0000U)
-#define SCT_SCTCAP_CAPn_H_SHIFT (16U)
-#define SCT_SCTCAP_CAPn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_H_SHIFT)) & SCT_SCTCAP_CAPn_H_MASK)
-
-/* The count of SCT_SCTCAP */
-#define SCT_SCTCAP_COUNT (10U)
-
-/*! @name SCTMATCH - SCT match value register of match channels */
-#define SCT_SCTMATCH_MATCHn_L_MASK (0xFFFFU)
-#define SCT_SCTMATCH_MATCHn_L_SHIFT (0U)
-#define SCT_SCTMATCH_MATCHn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_L_SHIFT)) & SCT_SCTMATCH_MATCHn_L_MASK)
-#define SCT_SCTMATCH_MATCHn_H_MASK (0xFFFF0000U)
-#define SCT_SCTMATCH_MATCHn_H_SHIFT (16U)
-#define SCT_SCTMATCH_MATCHn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_H_SHIFT)) & SCT_SCTMATCH_MATCHn_H_MASK)
-
-/* The count of SCT_SCTMATCH */
-#define SCT_SCTMATCH_COUNT (10U)
-
-/*! @name SCTCAPCTRL - SCT capture control register */
-#define SCT_SCTCAPCTRL_CAPCONn_L_MASK (0xFFFFU)
-#define SCT_SCTCAPCTRL_CAPCONn_L_SHIFT (0U)
-#define SCT_SCTCAPCTRL_CAPCONn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_L_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_L_MASK)
-#define SCT_SCTCAPCTRL_CAPCONn_H_MASK (0xFFFF0000U)
-#define SCT_SCTCAPCTRL_CAPCONn_H_SHIFT (16U)
-#define SCT_SCTCAPCTRL_CAPCONn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_H_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_H_MASK)
-
-/* The count of SCT_SCTCAPCTRL */
-#define SCT_SCTCAPCTRL_COUNT (10U)
-
-/*! @name SCTMATCHREL - SCT match reload value register */
-#define SCT_SCTMATCHREL_RELOADn_L_MASK (0xFFFFU)
-#define SCT_SCTMATCHREL_RELOADn_L_SHIFT (0U)
-#define SCT_SCTMATCHREL_RELOADn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_L_SHIFT)) & SCT_SCTMATCHREL_RELOADn_L_MASK)
-#define SCT_SCTMATCHREL_RELOADn_H_MASK (0xFFFF0000U)
-#define SCT_SCTMATCHREL_RELOADn_H_SHIFT (16U)
-#define SCT_SCTMATCHREL_RELOADn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_H_SHIFT)) & SCT_SCTMATCHREL_RELOADn_H_MASK)
-
-/* The count of SCT_SCTMATCHREL */
-#define SCT_SCTMATCHREL_COUNT (10U)
-
-/*! @name EVENT_STATE - SCT event state register 0 */
-#define SCT_EVENT_STATE_STATEMSKn_MASK (0xFFFFU)
-#define SCT_EVENT_STATE_STATEMSKn_SHIFT (0U)
-#define SCT_EVENT_STATE_STATEMSKn(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_STATE_STATEMSKn_SHIFT)) & SCT_EVENT_STATE_STATEMSKn_MASK)
-
-/* The count of SCT_EVENT_STATE */
-#define SCT_EVENT_STATE_COUNT (10U)
-
-/*! @name EVENT_CTRL - SCT event control register 0 */
-#define SCT_EVENT_CTRL_MATCHSEL_MASK (0xFU)
-#define SCT_EVENT_CTRL_MATCHSEL_SHIFT (0U)
-#define SCT_EVENT_CTRL_MATCHSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_MATCHSEL_SHIFT)) & SCT_EVENT_CTRL_MATCHSEL_MASK)
-#define SCT_EVENT_CTRL_HEVENT_MASK (0x10U)
-#define SCT_EVENT_CTRL_HEVENT_SHIFT (4U)
-#define SCT_EVENT_CTRL_HEVENT(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_HEVENT_SHIFT)) & SCT_EVENT_CTRL_HEVENT_MASK)
-#define SCT_EVENT_CTRL_OUTSEL_MASK (0x20U)
-#define SCT_EVENT_CTRL_OUTSEL_SHIFT (5U)
-#define SCT_EVENT_CTRL_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_OUTSEL_SHIFT)) & SCT_EVENT_CTRL_OUTSEL_MASK)
-#define SCT_EVENT_CTRL_IOSEL_MASK (0x3C0U)
-#define SCT_EVENT_CTRL_IOSEL_SHIFT (6U)
-#define SCT_EVENT_CTRL_IOSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_IOSEL_SHIFT)) & SCT_EVENT_CTRL_IOSEL_MASK)
-#define SCT_EVENT_CTRL_IOCOND_MASK (0xC00U)
-#define SCT_EVENT_CTRL_IOCOND_SHIFT (10U)
-#define SCT_EVENT_CTRL_IOCOND(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_IOCOND_SHIFT)) & SCT_EVENT_CTRL_IOCOND_MASK)
-#define SCT_EVENT_CTRL_COMBMODE_MASK (0x3000U)
-#define SCT_EVENT_CTRL_COMBMODE_SHIFT (12U)
-#define SCT_EVENT_CTRL_COMBMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_COMBMODE_SHIFT)) & SCT_EVENT_CTRL_COMBMODE_MASK)
-#define SCT_EVENT_CTRL_STATELD_MASK (0x4000U)
-#define SCT_EVENT_CTRL_STATELD_SHIFT (14U)
-#define SCT_EVENT_CTRL_STATELD(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_STATELD_SHIFT)) & SCT_EVENT_CTRL_STATELD_MASK)
-#define SCT_EVENT_CTRL_STATEV_MASK (0xF8000U)
-#define SCT_EVENT_CTRL_STATEV_SHIFT (15U)
-#define SCT_EVENT_CTRL_STATEV(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_STATEV_SHIFT)) & SCT_EVENT_CTRL_STATEV_MASK)
-#define SCT_EVENT_CTRL_MATCHMEM_MASK (0x100000U)
-#define SCT_EVENT_CTRL_MATCHMEM_SHIFT (20U)
-#define SCT_EVENT_CTRL_MATCHMEM(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_MATCHMEM_SHIFT)) & SCT_EVENT_CTRL_MATCHMEM_MASK)
-#define SCT_EVENT_CTRL_DIRECTION_MASK (0x600000U)
-#define SCT_EVENT_CTRL_DIRECTION_SHIFT (21U)
-#define SCT_EVENT_CTRL_DIRECTION(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_DIRECTION_SHIFT)) & SCT_EVENT_CTRL_DIRECTION_MASK)
-
-/* The count of SCT_EVENT_CTRL */
-#define SCT_EVENT_CTRL_COUNT (10U)
-
-/*! @name OUT_SET - SCT output 0 set register */
-#define SCT_OUT_SET_SET_MASK (0xFFFFU)
-#define SCT_OUT_SET_SET_SHIFT (0U)
-#define SCT_OUT_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK)
-
-/* The count of SCT_OUT_SET */
-#define SCT_OUT_SET_COUNT (10U)
-
-/*! @name OUT_CLR - SCT output 0 clear register */
-#define SCT_OUT_CLR_CLR_MASK (0xFFFFU)
-#define SCT_OUT_CLR_CLR_SHIFT (0U)
-#define SCT_OUT_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK)
-
-/* The count of SCT_OUT_CLR */
-#define SCT_OUT_CLR_COUNT (10U)
-
-
-/*!
- * @}
- */ /* end of group SCT_Register_Masks */
-
-
-/* SCT - Peripheral instance base addresses */
-/** Peripheral SCT0 base address */
-#define SCT0_BASE (0x40085000u)
-/** Peripheral SCT0 base pointer */
-#define SCT0 ((SCT_Type *)SCT0_BASE)
-/** Array initializer of SCT peripheral base addresses */
-#define SCT_BASE_ADDRS { SCT0_BASE }
-/** Array initializer of SCT peripheral base pointers */
-#define SCT_BASE_PTRS { SCT0 }
-/** Interrupt vectors for the SCT peripheral type */
-#define SCT_IRQS { SCT0_IRQn }
-
-/*!
- * @}
- */ /* end of group SCT_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- SDIF Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SDIF_Peripheral_Access_Layer SDIF Peripheral Access Layer
- * @{
- */
-
-/** SDIF - Register Layout Typedef */
-typedef struct {
- __IO uint32_t CTRL; /**< Control register, offset: 0x0 */
- __IO uint32_t PWREN; /**< Power Enable register, offset: 0x4 */
- __IO uint32_t CLKDIV; /**< Clock Divider register, offset: 0x8 */
- uint8_t RESERVED_0[4];
- __IO uint32_t CLKENA; /**< Clock Enable register, offset: 0x10 */
- __IO uint32_t TMOUT; /**< Time-out register, offset: 0x14 */
- __IO uint32_t CTYPE; /**< Card Type register, offset: 0x18 */
- __IO uint32_t BLKSIZ; /**< Block Size register, offset: 0x1C */
- __IO uint32_t BYTCNT; /**< Byte Count register, offset: 0x20 */
- __IO uint32_t INTMASK; /**< Interrupt Mask register, offset: 0x24 */
- __IO uint32_t CMDARG; /**< Command Argument register, offset: 0x28 */
- __IO uint32_t CMD; /**< Command register, offset: 0x2C */
- __IO uint32_t RESP[4]; /**< Response register, array offset: 0x30, array step: 0x4 */
- __IO uint32_t MINTSTS; /**< Masked Interrupt Status register, offset: 0x40 */
- __IO uint32_t RINTSTS; /**< Raw Interrupt Status register, offset: 0x44 */
- __IO uint32_t STATUS; /**< Status register, offset: 0x48 */
- __IO uint32_t FIFOTH; /**< FIFO Threshold Watermark register, offset: 0x4C */
- __IO uint32_t CDETECT; /**< Card Detect register, offset: 0x50 */
- __IO uint32_t WRTPRT; /**< Write Protect register, offset: 0x54 */
- uint8_t RESERVED_1[4];
- __IO uint32_t TCBCNT; /**< Transferred CIU Card Byte Count register, offset: 0x5C */
- __IO uint32_t TBBCNT; /**< Transferred Host to BIU-FIFO Byte Count register, offset: 0x60 */
- __IO uint32_t DEBNCE; /**< Debounce Count register, offset: 0x64 */
- uint8_t RESERVED_2[16];
- __IO uint32_t RST_N; /**< Hardware Reset, offset: 0x78 */
- uint8_t RESERVED_3[4];
- __IO uint32_t BMOD; /**< Bus Mode register, offset: 0x80 */
- __IO uint32_t PLDMND; /**< Poll Demand register, offset: 0x84 */
- __IO uint32_t DBADDR; /**< Descriptor List Base Address register, offset: 0x88 */
- __IO uint32_t IDSTS; /**< Internal DMAC Status register, offset: 0x8C */
- __IO uint32_t IDINTEN; /**< Internal DMAC Interrupt Enable register, offset: 0x90 */
- __IO uint32_t DSCADDR; /**< Current Host Descriptor Address register, offset: 0x94 */
- __IO uint32_t BUFADDR; /**< Current Buffer Descriptor Address register, offset: 0x98 */
- uint8_t RESERVED_4[100];
- __IO uint32_t CARDTHRCTL; /**< Card Threshold Control, offset: 0x100 */
- __IO uint32_t BACKENDPWR; /**< Power control, offset: 0x104 */
- uint8_t RESERVED_5[248];
- __IO uint32_t FIFO[64]; /**< SDIF FIFO, array offset: 0x200, array step: 0x4 */
-} SDIF_Type;
-
-/* ----------------------------------------------------------------------------
- -- SDIF Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SDIF_Register_Masks SDIF Register Masks
- * @{
- */
-
-/*! @name CTRL - Control register */
-#define SDIF_CTRL_CONTROLLER_RESET_MASK (0x1U)
-#define SDIF_CTRL_CONTROLLER_RESET_SHIFT (0U)
-#define SDIF_CTRL_CONTROLLER_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CONTROLLER_RESET_SHIFT)) & SDIF_CTRL_CONTROLLER_RESET_MASK)
-#define SDIF_CTRL_FIFO_RESET_MASK (0x2U)
-#define SDIF_CTRL_FIFO_RESET_SHIFT (1U)
-#define SDIF_CTRL_FIFO_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_FIFO_RESET_SHIFT)) & SDIF_CTRL_FIFO_RESET_MASK)
-#define SDIF_CTRL_DMA_RESET_MASK (0x4U)
-#define SDIF_CTRL_DMA_RESET_SHIFT (2U)
-#define SDIF_CTRL_DMA_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK)
-#define SDIF_CTRL_INT_ENABLE_MASK (0x10U)
-#define SDIF_CTRL_INT_ENABLE_SHIFT (4U)
-#define SDIF_CTRL_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_INT_ENABLE_SHIFT)) & SDIF_CTRL_INT_ENABLE_MASK)
-#define SDIF_CTRL_READ_WAIT_MASK (0x40U)
-#define SDIF_CTRL_READ_WAIT_SHIFT (6U)
-#define SDIF_CTRL_READ_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_READ_WAIT_SHIFT)) & SDIF_CTRL_READ_WAIT_MASK)
-#define SDIF_CTRL_SEND_IRQ_RESPONSE_MASK (0x80U)
-#define SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT (7U)
-#define SDIF_CTRL_SEND_IRQ_RESPONSE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT)) & SDIF_CTRL_SEND_IRQ_RESPONSE_MASK)
-#define SDIF_CTRL_ABORT_READ_DATA_MASK (0x100U)
-#define SDIF_CTRL_ABORT_READ_DATA_SHIFT (8U)
-#define SDIF_CTRL_ABORT_READ_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_ABORT_READ_DATA_SHIFT)) & SDIF_CTRL_ABORT_READ_DATA_MASK)
-#define SDIF_CTRL_SEND_CCSD_MASK (0x200U)
-#define SDIF_CTRL_SEND_CCSD_SHIFT (9U)
-#define SDIF_CTRL_SEND_CCSD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_CCSD_SHIFT)) & SDIF_CTRL_SEND_CCSD_MASK)
-#define SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK (0x400U)
-#define SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT (10U)
-#define SDIF_CTRL_SEND_AUTO_STOP_CCSD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT)) & SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK)
-#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK (0x800U)
-#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT (11U)
-#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT)) & SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK)
-#define SDIF_CTRL_CARD_VOLTAGE_A0_MASK (0x10000U)
-#define SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT (16U)
-#define SDIF_CTRL_CARD_VOLTAGE_A0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A0_MASK)
-#define SDIF_CTRL_CARD_VOLTAGE_A1_MASK (0x20000U)
-#define SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT (17U)
-#define SDIF_CTRL_CARD_VOLTAGE_A1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A1_MASK)
-#define SDIF_CTRL_CARD_VOLTAGE_A2_MASK (0x40000U)
-#define SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT (18U)
-#define SDIF_CTRL_CARD_VOLTAGE_A2(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A2_MASK)
-#define SDIF_CTRL_USE_INTERNAL_DMAC_MASK (0x2000000U)
-#define SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT (25U)
-#define SDIF_CTRL_USE_INTERNAL_DMAC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT)) & SDIF_CTRL_USE_INTERNAL_DMAC_MASK)
-
-/*! @name PWREN - Power Enable register */
-#define SDIF_PWREN_POWER_ENABLE_MASK (0x1U)
-#define SDIF_PWREN_POWER_ENABLE_SHIFT (0U)
-#define SDIF_PWREN_POWER_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PWREN_POWER_ENABLE_SHIFT)) & SDIF_PWREN_POWER_ENABLE_MASK)
-
-/*! @name CLKDIV - Clock Divider register */
-#define SDIF_CLKDIV_CLK_DIVIDER0_MASK (0xFFU)
-#define SDIF_CLKDIV_CLK_DIVIDER0_SHIFT (0U)
-#define SDIF_CLKDIV_CLK_DIVIDER0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKDIV_CLK_DIVIDER0_SHIFT)) & SDIF_CLKDIV_CLK_DIVIDER0_MASK)
-
-/*! @name CLKENA - Clock Enable register */
-#define SDIF_CLKENA_CCLK_ENABLE_MASK (0x1U)
-#define SDIF_CLKENA_CCLK_ENABLE_SHIFT (0U)
-#define SDIF_CLKENA_CCLK_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK_ENABLE_SHIFT)) & SDIF_CLKENA_CCLK_ENABLE_MASK)
-#define SDIF_CLKENA_CCLK_LOW_POWER_MASK (0x10000U)
-#define SDIF_CLKENA_CCLK_LOW_POWER_SHIFT (16U)
-#define SDIF_CLKENA_CCLK_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK_LOW_POWER_SHIFT)) & SDIF_CLKENA_CCLK_LOW_POWER_MASK)
-
-/*! @name TMOUT - Time-out register */
-#define SDIF_TMOUT_RESPONSE_TIMEOUT_MASK (0xFFU)
-#define SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT (0U)
-#define SDIF_TMOUT_RESPONSE_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT)) & SDIF_TMOUT_RESPONSE_TIMEOUT_MASK)
-#define SDIF_TMOUT_DATA_TIMEOUT_MASK (0xFFFFFF00U)
-#define SDIF_TMOUT_DATA_TIMEOUT_SHIFT (8U)
-#define SDIF_TMOUT_DATA_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_DATA_TIMEOUT_SHIFT)) & SDIF_TMOUT_DATA_TIMEOUT_MASK)
-
-/*! @name CTYPE - Card Type register */
-#define SDIF_CTYPE_CARD_WIDTH0_MASK (0x1U)
-#define SDIF_CTYPE_CARD_WIDTH0_SHIFT (0U)
-#define SDIF_CTYPE_CARD_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD_WIDTH0_SHIFT)) & SDIF_CTYPE_CARD_WIDTH0_MASK)
-#define SDIF_CTYPE_CARD_WIDTH1_MASK (0x10000U)
-#define SDIF_CTYPE_CARD_WIDTH1_SHIFT (16U)
-#define SDIF_CTYPE_CARD_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD_WIDTH1_SHIFT)) & SDIF_CTYPE_CARD_WIDTH1_MASK)
-
-/*! @name BLKSIZ - Block Size register */
-#define SDIF_BLKSIZ_BLOCK_SIZE_MASK (0xFFFFU)
-#define SDIF_BLKSIZ_BLOCK_SIZE_SHIFT (0U)
-#define SDIF_BLKSIZ_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BLKSIZ_BLOCK_SIZE_SHIFT)) & SDIF_BLKSIZ_BLOCK_SIZE_MASK)
-
-/*! @name BYTCNT - Byte Count register */
-#define SDIF_BYTCNT_BYTE_COUNT_MASK (0xFFFFFFFFU)
-#define SDIF_BYTCNT_BYTE_COUNT_SHIFT (0U)
-#define SDIF_BYTCNT_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BYTCNT_BYTE_COUNT_SHIFT)) & SDIF_BYTCNT_BYTE_COUNT_MASK)
-
-/*! @name INTMASK - Interrupt Mask register */
-#define SDIF_INTMASK_CDET_MASK (0x1U)
-#define SDIF_INTMASK_CDET_SHIFT (0U)
-#define SDIF_INTMASK_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDET_SHIFT)) & SDIF_INTMASK_CDET_MASK)
-#define SDIF_INTMASK_RE_MASK (0x2U)
-#define SDIF_INTMASK_RE_SHIFT (1U)
-#define SDIF_INTMASK_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RE_SHIFT)) & SDIF_INTMASK_RE_MASK)
-#define SDIF_INTMASK_CDONE_MASK (0x4U)
-#define SDIF_INTMASK_CDONE_SHIFT (2U)
-#define SDIF_INTMASK_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDONE_SHIFT)) & SDIF_INTMASK_CDONE_MASK)
-#define SDIF_INTMASK_DTO_MASK (0x8U)
-#define SDIF_INTMASK_DTO_SHIFT (3U)
-#define SDIF_INTMASK_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DTO_SHIFT)) & SDIF_INTMASK_DTO_MASK)
-#define SDIF_INTMASK_TXDR_MASK (0x10U)
-#define SDIF_INTMASK_TXDR_SHIFT (4U)
-#define SDIF_INTMASK_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_TXDR_SHIFT)) & SDIF_INTMASK_TXDR_MASK)
-#define SDIF_INTMASK_RXDR_MASK (0x20U)
-#define SDIF_INTMASK_RXDR_SHIFT (5U)
-#define SDIF_INTMASK_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RXDR_SHIFT)) & SDIF_INTMASK_RXDR_MASK)
-#define SDIF_INTMASK_RCRC_MASK (0x40U)
-#define SDIF_INTMASK_RCRC_SHIFT (6U)
-#define SDIF_INTMASK_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RCRC_SHIFT)) & SDIF_INTMASK_RCRC_MASK)
-#define SDIF_INTMASK_DCRC_MASK (0x80U)
-#define SDIF_INTMASK_DCRC_SHIFT (7U)
-#define SDIF_INTMASK_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DCRC_SHIFT)) & SDIF_INTMASK_DCRC_MASK)
-#define SDIF_INTMASK_RTO_MASK (0x100U)
-#define SDIF_INTMASK_RTO_SHIFT (8U)
-#define SDIF_INTMASK_RTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RTO_SHIFT)) & SDIF_INTMASK_RTO_MASK)
-#define SDIF_INTMASK_DRTO_MASK (0x200U)
-#define SDIF_INTMASK_DRTO_SHIFT (9U)
-#define SDIF_INTMASK_DRTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DRTO_SHIFT)) & SDIF_INTMASK_DRTO_MASK)
-#define SDIF_INTMASK_HTO_MASK (0x400U)
-#define SDIF_INTMASK_HTO_SHIFT (10U)
-#define SDIF_INTMASK_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HTO_SHIFT)) & SDIF_INTMASK_HTO_MASK)
-#define SDIF_INTMASK_FRUN_MASK (0x800U)
-#define SDIF_INTMASK_FRUN_SHIFT (11U)
-#define SDIF_INTMASK_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_FRUN_SHIFT)) & SDIF_INTMASK_FRUN_MASK)
-#define SDIF_INTMASK_HLE_MASK (0x1000U)
-#define SDIF_INTMASK_HLE_SHIFT (12U)
-#define SDIF_INTMASK_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HLE_SHIFT)) & SDIF_INTMASK_HLE_MASK)
-#define SDIF_INTMASK_SBE_MASK (0x2000U)
-#define SDIF_INTMASK_SBE_SHIFT (13U)
-#define SDIF_INTMASK_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SBE_SHIFT)) & SDIF_INTMASK_SBE_MASK)
-#define SDIF_INTMASK_ACD_MASK (0x4000U)
-#define SDIF_INTMASK_ACD_SHIFT (14U)
-#define SDIF_INTMASK_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_ACD_SHIFT)) & SDIF_INTMASK_ACD_MASK)
-#define SDIF_INTMASK_EBE_MASK (0x8000U)
-#define SDIF_INTMASK_EBE_SHIFT (15U)
-#define SDIF_INTMASK_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_EBE_SHIFT)) & SDIF_INTMASK_EBE_MASK)
-#define SDIF_INTMASK_SDIO_INT_MASK_MASK (0x10000U)
-#define SDIF_INTMASK_SDIO_INT_MASK_SHIFT (16U)
-#define SDIF_INTMASK_SDIO_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SDIO_INT_MASK_SHIFT)) & SDIF_INTMASK_SDIO_INT_MASK_MASK)
-
-/*! @name CMDARG - Command Argument register */
-#define SDIF_CMDARG_CMD_ARG_MASK (0xFFFFFFFFU)
-#define SDIF_CMDARG_CMD_ARG_SHIFT (0U)
-#define SDIF_CMDARG_CMD_ARG(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMDARG_CMD_ARG_SHIFT)) & SDIF_CMDARG_CMD_ARG_MASK)
-
-/*! @name CMD - Command register */
-#define SDIF_CMD_CMD_INDEX_MASK (0x3FU)
-#define SDIF_CMD_CMD_INDEX_SHIFT (0U)
-#define SDIF_CMD_CMD_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CMD_INDEX_SHIFT)) & SDIF_CMD_CMD_INDEX_MASK)
-#define SDIF_CMD_RESPONSE_EXPECT_MASK (0x40U)
-#define SDIF_CMD_RESPONSE_EXPECT_SHIFT (6U)
-#define SDIF_CMD_RESPONSE_EXPECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_EXPECT_SHIFT)) & SDIF_CMD_RESPONSE_EXPECT_MASK)
-#define SDIF_CMD_RESPONSE_LENGTH_MASK (0x80U)
-#define SDIF_CMD_RESPONSE_LENGTH_SHIFT (7U)
-#define SDIF_CMD_RESPONSE_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_LENGTH_SHIFT)) & SDIF_CMD_RESPONSE_LENGTH_MASK)
-#define SDIF_CMD_CHECK_RESPONSE_CRC_MASK (0x100U)
-#define SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT (8U)
-#define SDIF_CMD_CHECK_RESPONSE_CRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT)) & SDIF_CMD_CHECK_RESPONSE_CRC_MASK)
-#define SDIF_CMD_DATA_EXPECTED_MASK (0x200U)
-#define SDIF_CMD_DATA_EXPECTED_SHIFT (9U)
-#define SDIF_CMD_DATA_EXPECTED(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DATA_EXPECTED_SHIFT)) & SDIF_CMD_DATA_EXPECTED_MASK)
-#define SDIF_CMD_READ_WRITE_MASK (0x400U)
-#define SDIF_CMD_READ_WRITE_SHIFT (10U)
-#define SDIF_CMD_READ_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_WRITE_SHIFT)) & SDIF_CMD_READ_WRITE_MASK)
-#define SDIF_CMD_TRANSFER_MODE_MASK (0x800U)
-#define SDIF_CMD_TRANSFER_MODE_SHIFT (11U)
-#define SDIF_CMD_TRANSFER_MODE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_TRANSFER_MODE_SHIFT)) & SDIF_CMD_TRANSFER_MODE_MASK)
-#define SDIF_CMD_SEND_AUTO_STOP_MASK (0x1000U)
-#define SDIF_CMD_SEND_AUTO_STOP_SHIFT (12U)
-#define SDIF_CMD_SEND_AUTO_STOP(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_AUTO_STOP_SHIFT)) & SDIF_CMD_SEND_AUTO_STOP_MASK)
-#define SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK (0x2000U)
-#define SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT (13U)
-#define SDIF_CMD_WAIT_PRVDATA_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT)) & SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK)
-#define SDIF_CMD_STOP_ABORT_CMD_MASK (0x4000U)
-#define SDIF_CMD_STOP_ABORT_CMD_SHIFT (14U)
-#define SDIF_CMD_STOP_ABORT_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_STOP_ABORT_CMD_SHIFT)) & SDIF_CMD_STOP_ABORT_CMD_MASK)
-#define SDIF_CMD_SEND_INITIALIZATION_MASK (0x8000U)
-#define SDIF_CMD_SEND_INITIALIZATION_SHIFT (15U)
-#define SDIF_CMD_SEND_INITIALIZATION(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_INITIALIZATION_SHIFT)) & SDIF_CMD_SEND_INITIALIZATION_MASK)
-#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK (0x200000U)
-#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT (21U)
-#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT)) & SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK)
-#define SDIF_CMD_READ_CEATA_DEVICE_MASK (0x400000U)
-#define SDIF_CMD_READ_CEATA_DEVICE_SHIFT (22U)
-#define SDIF_CMD_READ_CEATA_DEVICE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_CEATA_DEVICE_SHIFT)) & SDIF_CMD_READ_CEATA_DEVICE_MASK)
-#define SDIF_CMD_CCS_EXPECTED_MASK (0x800000U)
-#define SDIF_CMD_CCS_EXPECTED_SHIFT (23U)
-#define SDIF_CMD_CCS_EXPECTED(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CCS_EXPECTED_SHIFT)) & SDIF_CMD_CCS_EXPECTED_MASK)
-#define SDIF_CMD_ENABLE_BOOT_MASK (0x1000000U)
-#define SDIF_CMD_ENABLE_BOOT_SHIFT (24U)
-#define SDIF_CMD_ENABLE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_ENABLE_BOOT_SHIFT)) & SDIF_CMD_ENABLE_BOOT_MASK)
-#define SDIF_CMD_EXPECT_BOOT_ACK_MASK (0x2000000U)
-#define SDIF_CMD_EXPECT_BOOT_ACK_SHIFT (25U)
-#define SDIF_CMD_EXPECT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_EXPECT_BOOT_ACK_SHIFT)) & SDIF_CMD_EXPECT_BOOT_ACK_MASK)
-#define SDIF_CMD_DISABLE_BOOT_MASK (0x4000000U)
-#define SDIF_CMD_DISABLE_BOOT_SHIFT (26U)
-#define SDIF_CMD_DISABLE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DISABLE_BOOT_SHIFT)) & SDIF_CMD_DISABLE_BOOT_MASK)
-#define SDIF_CMD_BOOT_MODE_MASK (0x8000000U)
-#define SDIF_CMD_BOOT_MODE_SHIFT (27U)
-#define SDIF_CMD_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_BOOT_MODE_SHIFT)) & SDIF_CMD_BOOT_MODE_MASK)
-#define SDIF_CMD_VOLT_SWITCH_MASK (0x10000000U)
-#define SDIF_CMD_VOLT_SWITCH_SHIFT (28U)
-#define SDIF_CMD_VOLT_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_VOLT_SWITCH_SHIFT)) & SDIF_CMD_VOLT_SWITCH_MASK)
-#define SDIF_CMD_USE_HOLD_REG_MASK (0x20000000U)
-#define SDIF_CMD_USE_HOLD_REG_SHIFT (29U)
-#define SDIF_CMD_USE_HOLD_REG(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_USE_HOLD_REG_SHIFT)) & SDIF_CMD_USE_HOLD_REG_MASK)
-#define SDIF_CMD_START_CMD_MASK (0x80000000U)
-#define SDIF_CMD_START_CMD_SHIFT (31U)
-#define SDIF_CMD_START_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_START_CMD_SHIFT)) & SDIF_CMD_START_CMD_MASK)
-
-/*! @name RESP - Response register */
-#define SDIF_RESP_RESPONSE_MASK (0xFFFFFFFFU)
-#define SDIF_RESP_RESPONSE_SHIFT (0U)
-#define SDIF_RESP_RESPONSE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RESP_RESPONSE_SHIFT)) & SDIF_RESP_RESPONSE_MASK)
-
-/* The count of SDIF_RESP */
-#define SDIF_RESP_COUNT (4U)
-
-/*! @name MINTSTS - Masked Interrupt Status register */
-#define SDIF_MINTSTS_CDET_MASK (0x1U)
-#define SDIF_MINTSTS_CDET_SHIFT (0U)
-#define SDIF_MINTSTS_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDET_SHIFT)) & SDIF_MINTSTS_CDET_MASK)
-#define SDIF_MINTSTS_RE_MASK (0x2U)
-#define SDIF_MINTSTS_RE_SHIFT (1U)
-#define SDIF_MINTSTS_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RE_SHIFT)) & SDIF_MINTSTS_RE_MASK)
-#define SDIF_MINTSTS_CDONE_MASK (0x4U)
-#define SDIF_MINTSTS_CDONE_SHIFT (2U)
-#define SDIF_MINTSTS_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDONE_SHIFT)) & SDIF_MINTSTS_CDONE_MASK)
-#define SDIF_MINTSTS_DTO_MASK (0x8U)
-#define SDIF_MINTSTS_DTO_SHIFT (3U)
-#define SDIF_MINTSTS_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DTO_SHIFT)) & SDIF_MINTSTS_DTO_MASK)
-#define SDIF_MINTSTS_TXDR_MASK (0x10U)
-#define SDIF_MINTSTS_TXDR_SHIFT (4U)
-#define SDIF_MINTSTS_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_TXDR_SHIFT)) & SDIF_MINTSTS_TXDR_MASK)
-#define SDIF_MINTSTS_RXDR_MASK (0x20U)
-#define SDIF_MINTSTS_RXDR_SHIFT (5U)
-#define SDIF_MINTSTS_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RXDR_SHIFT)) & SDIF_MINTSTS_RXDR_MASK)
-#define SDIF_MINTSTS_RCRC_MASK (0x40U)
-#define SDIF_MINTSTS_RCRC_SHIFT (6U)
-#define SDIF_MINTSTS_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RCRC_SHIFT)) & SDIF_MINTSTS_RCRC_MASK)
-#define SDIF_MINTSTS_DCRC_MASK (0x80U)
-#define SDIF_MINTSTS_DCRC_SHIFT (7U)
-#define SDIF_MINTSTS_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DCRC_SHIFT)) & SDIF_MINTSTS_DCRC_MASK)
-#define SDIF_MINTSTS_RTO_MASK (0x100U)
-#define SDIF_MINTSTS_RTO_SHIFT (8U)
-#define SDIF_MINTSTS_RTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RTO_SHIFT)) & SDIF_MINTSTS_RTO_MASK)
-#define SDIF_MINTSTS_DRTO_MASK (0x200U)
-#define SDIF_MINTSTS_DRTO_SHIFT (9U)
-#define SDIF_MINTSTS_DRTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DRTO_SHIFT)) & SDIF_MINTSTS_DRTO_MASK)
-#define SDIF_MINTSTS_HTO_MASK (0x400U)
-#define SDIF_MINTSTS_HTO_SHIFT (10U)
-#define SDIF_MINTSTS_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HTO_SHIFT)) & SDIF_MINTSTS_HTO_MASK)
-#define SDIF_MINTSTS_FRUN_MASK (0x800U)
-#define SDIF_MINTSTS_FRUN_SHIFT (11U)
-#define SDIF_MINTSTS_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_FRUN_SHIFT)) & SDIF_MINTSTS_FRUN_MASK)
-#define SDIF_MINTSTS_HLE_MASK (0x1000U)
-#define SDIF_MINTSTS_HLE_SHIFT (12U)
-#define SDIF_MINTSTS_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HLE_SHIFT)) & SDIF_MINTSTS_HLE_MASK)
-#define SDIF_MINTSTS_SBE_MASK (0x2000U)
-#define SDIF_MINTSTS_SBE_SHIFT (13U)
-#define SDIF_MINTSTS_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SBE_SHIFT)) & SDIF_MINTSTS_SBE_MASK)
-#define SDIF_MINTSTS_ACD_MASK (0x4000U)
-#define SDIF_MINTSTS_ACD_SHIFT (14U)
-#define SDIF_MINTSTS_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_ACD_SHIFT)) & SDIF_MINTSTS_ACD_MASK)
-#define SDIF_MINTSTS_EBE_MASK (0x8000U)
-#define SDIF_MINTSTS_EBE_SHIFT (15U)
-#define SDIF_MINTSTS_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_EBE_SHIFT)) & SDIF_MINTSTS_EBE_MASK)
-#define SDIF_MINTSTS_SDIO_INTERRUPT_MASK (0x10000U)
-#define SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT (16U)
-#define SDIF_MINTSTS_SDIO_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_MINTSTS_SDIO_INTERRUPT_MASK)
-
-/*! @name RINTSTS - Raw Interrupt Status register */
-#define SDIF_RINTSTS_CDET_MASK (0x1U)
-#define SDIF_RINTSTS_CDET_SHIFT (0U)
-#define SDIF_RINTSTS_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDET_SHIFT)) & SDIF_RINTSTS_CDET_MASK)
-#define SDIF_RINTSTS_RE_MASK (0x2U)
-#define SDIF_RINTSTS_RE_SHIFT (1U)
-#define SDIF_RINTSTS_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RE_SHIFT)) & SDIF_RINTSTS_RE_MASK)
-#define SDIF_RINTSTS_CDONE_MASK (0x4U)
-#define SDIF_RINTSTS_CDONE_SHIFT (2U)
-#define SDIF_RINTSTS_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDONE_SHIFT)) & SDIF_RINTSTS_CDONE_MASK)
-#define SDIF_RINTSTS_DTO_MASK (0x8U)
-#define SDIF_RINTSTS_DTO_SHIFT (3U)
-#define SDIF_RINTSTS_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DTO_SHIFT)) & SDIF_RINTSTS_DTO_MASK)
-#define SDIF_RINTSTS_TXDR_MASK (0x10U)
-#define SDIF_RINTSTS_TXDR_SHIFT (4U)
-#define SDIF_RINTSTS_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_TXDR_SHIFT)) & SDIF_RINTSTS_TXDR_MASK)
-#define SDIF_RINTSTS_RXDR_MASK (0x20U)
-#define SDIF_RINTSTS_RXDR_SHIFT (5U)
-#define SDIF_RINTSTS_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RXDR_SHIFT)) & SDIF_RINTSTS_RXDR_MASK)
-#define SDIF_RINTSTS_RCRC_MASK (0x40U)
-#define SDIF_RINTSTS_RCRC_SHIFT (6U)
-#define SDIF_RINTSTS_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RCRC_SHIFT)) & SDIF_RINTSTS_RCRC_MASK)
-#define SDIF_RINTSTS_DCRC_MASK (0x80U)
-#define SDIF_RINTSTS_DCRC_SHIFT (7U)
-#define SDIF_RINTSTS_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DCRC_SHIFT)) & SDIF_RINTSTS_DCRC_MASK)
-#define SDIF_RINTSTS_RTO_BAR_MASK (0x100U)
-#define SDIF_RINTSTS_RTO_BAR_SHIFT (8U)
-#define SDIF_RINTSTS_RTO_BAR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RTO_BAR_SHIFT)) & SDIF_RINTSTS_RTO_BAR_MASK)
-#define SDIF_RINTSTS_DRTO_BDS_MASK (0x200U)
-#define SDIF_RINTSTS_DRTO_BDS_SHIFT (9U)
-#define SDIF_RINTSTS_DRTO_BDS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DRTO_BDS_SHIFT)) & SDIF_RINTSTS_DRTO_BDS_MASK)
-#define SDIF_RINTSTS_HTO_MASK (0x400U)
-#define SDIF_RINTSTS_HTO_SHIFT (10U)
-#define SDIF_RINTSTS_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HTO_SHIFT)) & SDIF_RINTSTS_HTO_MASK)
-#define SDIF_RINTSTS_FRUN_MASK (0x800U)
-#define SDIF_RINTSTS_FRUN_SHIFT (11U)
-#define SDIF_RINTSTS_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_FRUN_SHIFT)) & SDIF_RINTSTS_FRUN_MASK)
-#define SDIF_RINTSTS_HLE_MASK (0x1000U)
-#define SDIF_RINTSTS_HLE_SHIFT (12U)
-#define SDIF_RINTSTS_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HLE_SHIFT)) & SDIF_RINTSTS_HLE_MASK)
-#define SDIF_RINTSTS_SBE_MASK (0x2000U)
-#define SDIF_RINTSTS_SBE_SHIFT (13U)
-#define SDIF_RINTSTS_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SBE_SHIFT)) & SDIF_RINTSTS_SBE_MASK)
-#define SDIF_RINTSTS_ACD_MASK (0x4000U)
-#define SDIF_RINTSTS_ACD_SHIFT (14U)
-#define SDIF_RINTSTS_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_ACD_SHIFT)) & SDIF_RINTSTS_ACD_MASK)
-#define SDIF_RINTSTS_EBE_MASK (0x8000U)
-#define SDIF_RINTSTS_EBE_SHIFT (15U)
-#define SDIF_RINTSTS_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_EBE_SHIFT)) & SDIF_RINTSTS_EBE_MASK)
-#define SDIF_RINTSTS_SDIO_INTERRUPT_MASK (0x10000U)
-#define SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT (16U)
-#define SDIF_RINTSTS_SDIO_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_RINTSTS_SDIO_INTERRUPT_MASK)
-
-/*! @name STATUS - Status register */
-#define SDIF_STATUS_FIFO_RX_WATERMARK_MASK (0x1U)
-#define SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT (0U)
-#define SDIF_STATUS_FIFO_RX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_RX_WATERMARK_MASK)
-#define SDIF_STATUS_FIFO_TX_WATERMARK_MASK (0x2U)
-#define SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT (1U)
-#define SDIF_STATUS_FIFO_TX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_TX_WATERMARK_MASK)
-#define SDIF_STATUS_FIFO_EMPTY_MASK (0x4U)
-#define SDIF_STATUS_FIFO_EMPTY_SHIFT (2U)
-#define SDIF_STATUS_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_EMPTY_SHIFT)) & SDIF_STATUS_FIFO_EMPTY_MASK)
-#define SDIF_STATUS_FIFO_FULL_MASK (0x8U)
-#define SDIF_STATUS_FIFO_FULL_SHIFT (3U)
-#define SDIF_STATUS_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_FULL_SHIFT)) & SDIF_STATUS_FIFO_FULL_MASK)
-#define SDIF_STATUS_CMDFSMSTATES_MASK (0xF0U)
-#define SDIF_STATUS_CMDFSMSTATES_SHIFT (4U)
-#define SDIF_STATUS_CMDFSMSTATES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_CMDFSMSTATES_SHIFT)) & SDIF_STATUS_CMDFSMSTATES_MASK)
-#define SDIF_STATUS_DATA_3_STATUS_MASK (0x100U)
-#define SDIF_STATUS_DATA_3_STATUS_SHIFT (8U)
-#define SDIF_STATUS_DATA_3_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_3_STATUS_SHIFT)) & SDIF_STATUS_DATA_3_STATUS_MASK)
-#define SDIF_STATUS_DATA_BUSY_MASK (0x200U)
-#define SDIF_STATUS_DATA_BUSY_SHIFT (9U)
-#define SDIF_STATUS_DATA_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_BUSY_SHIFT)) & SDIF_STATUS_DATA_BUSY_MASK)
-#define SDIF_STATUS_DATA_STATE_MC_BUSY_MASK (0x400U)
-#define SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT (10U)
-#define SDIF_STATUS_DATA_STATE_MC_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT)) & SDIF_STATUS_DATA_STATE_MC_BUSY_MASK)
-#define SDIF_STATUS_RESPONSE_INDEX_MASK (0x1F800U)
-#define SDIF_STATUS_RESPONSE_INDEX_SHIFT (11U)
-#define SDIF_STATUS_RESPONSE_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK)
-#define SDIF_STATUS_FIFO_COUNT_MASK (0x3FFE0000U)
-#define SDIF_STATUS_FIFO_COUNT_SHIFT (17U)
-#define SDIF_STATUS_FIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_COUNT_SHIFT)) & SDIF_STATUS_FIFO_COUNT_MASK)
-#define SDIF_STATUS_DMA_ACK_MASK (0x40000000U)
-#define SDIF_STATUS_DMA_ACK_SHIFT (30U)
-#define SDIF_STATUS_DMA_ACK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_ACK_SHIFT)) & SDIF_STATUS_DMA_ACK_MASK)
-#define SDIF_STATUS_DMA_REQ_MASK (0x80000000U)
-#define SDIF_STATUS_DMA_REQ_SHIFT (31U)
-#define SDIF_STATUS_DMA_REQ(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_REQ_SHIFT)) & SDIF_STATUS_DMA_REQ_MASK)
-
-/*! @name FIFOTH - FIFO Threshold Watermark register */
-#define SDIF_FIFOTH_TX_WMARK_MASK (0xFFFU)
-#define SDIF_FIFOTH_TX_WMARK_SHIFT (0U)
-#define SDIF_FIFOTH_TX_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_TX_WMARK_SHIFT)) & SDIF_FIFOTH_TX_WMARK_MASK)
-#define SDIF_FIFOTH_RX_WMARK_MASK (0xFFF0000U)
-#define SDIF_FIFOTH_RX_WMARK_SHIFT (16U)
-#define SDIF_FIFOTH_RX_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_RX_WMARK_SHIFT)) & SDIF_FIFOTH_RX_WMARK_MASK)
-#define SDIF_FIFOTH_DMA_MTS_MASK (0x70000000U)
-#define SDIF_FIFOTH_DMA_MTS_SHIFT (28U)
-#define SDIF_FIFOTH_DMA_MTS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_DMA_MTS_SHIFT)) & SDIF_FIFOTH_DMA_MTS_MASK)
-
-/*! @name CDETECT - Card Detect register */
-#define SDIF_CDETECT_CARD_DETECT_MASK (0x1U)
-#define SDIF_CDETECT_CARD_DETECT_SHIFT (0U)
-#define SDIF_CDETECT_CARD_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CDETECT_CARD_DETECT_SHIFT)) & SDIF_CDETECT_CARD_DETECT_MASK)
-
-/*! @name WRTPRT - Write Protect register */
-#define SDIF_WRTPRT_WRITE_PROTECT_MASK (0x1U)
-#define SDIF_WRTPRT_WRITE_PROTECT_SHIFT (0U)
-#define SDIF_WRTPRT_WRITE_PROTECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_WRTPRT_WRITE_PROTECT_SHIFT)) & SDIF_WRTPRT_WRITE_PROTECT_MASK)
-
-/*! @name TCBCNT - Transferred CIU Card Byte Count register */
-#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK (0xFFFFFFFFU)
-#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT (0U)
-#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT)) & SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK)
-
-/*! @name TBBCNT - Transferred Host to BIU-FIFO Byte Count register */
-#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK (0xFFFFFFFFU)
-#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT (0U)
-#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT)) & SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK)
-
-/*! @name DEBNCE - Debounce Count register */
-#define SDIF_DEBNCE_DEBOUNCE_COUNT_MASK (0xFFFFFFU)
-#define SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT (0U)
-#define SDIF_DEBNCE_DEBOUNCE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT)) & SDIF_DEBNCE_DEBOUNCE_COUNT_MASK)
-
-/*! @name RST_N - Hardware Reset */
-#define SDIF_RST_N_CARD_RESET_MASK (0x1U)
-#define SDIF_RST_N_CARD_RESET_SHIFT (0U)
-#define SDIF_RST_N_CARD_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RST_N_CARD_RESET_SHIFT)) & SDIF_RST_N_CARD_RESET_MASK)
-
-/*! @name BMOD - Bus Mode register */
-#define SDIF_BMOD_SWR_MASK (0x1U)
-#define SDIF_BMOD_SWR_SHIFT (0U)
-#define SDIF_BMOD_SWR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_SWR_SHIFT)) & SDIF_BMOD_SWR_MASK)
-#define SDIF_BMOD_FB_MASK (0x2U)
-#define SDIF_BMOD_FB_SHIFT (1U)
-#define SDIF_BMOD_FB(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_FB_SHIFT)) & SDIF_BMOD_FB_MASK)
-#define SDIF_BMOD_DSL_MASK (0x7CU)
-#define SDIF_BMOD_DSL_SHIFT (2U)
-#define SDIF_BMOD_DSL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DSL_SHIFT)) & SDIF_BMOD_DSL_MASK)
-#define SDIF_BMOD_DE_MASK (0x80U)
-#define SDIF_BMOD_DE_SHIFT (7U)
-#define SDIF_BMOD_DE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DE_SHIFT)) & SDIF_BMOD_DE_MASK)
-#define SDIF_BMOD_PBL_MASK (0x700U)
-#define SDIF_BMOD_PBL_SHIFT (8U)
-#define SDIF_BMOD_PBL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_PBL_SHIFT)) & SDIF_BMOD_PBL_MASK)
-
-/*! @name PLDMND - Poll Demand register */
-#define SDIF_PLDMND_PD_MASK (0xFFFFFFFFU)
-#define SDIF_PLDMND_PD_SHIFT (0U)
-#define SDIF_PLDMND_PD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PLDMND_PD_SHIFT)) & SDIF_PLDMND_PD_MASK)
-
-/*! @name DBADDR - Descriptor List Base Address register */
-#define SDIF_DBADDR_SDL_MASK (0xFFFFFFFFU)
-#define SDIF_DBADDR_SDL_SHIFT (0U)
-#define SDIF_DBADDR_SDL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DBADDR_SDL_SHIFT)) & SDIF_DBADDR_SDL_MASK)
-
-/*! @name IDSTS - Internal DMAC Status register */
-#define SDIF_IDSTS_TI_MASK (0x1U)
-#define SDIF_IDSTS_TI_SHIFT (0U)
-#define SDIF_IDSTS_TI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_TI_SHIFT)) & SDIF_IDSTS_TI_MASK)
-#define SDIF_IDSTS_RI_MASK (0x2U)
-#define SDIF_IDSTS_RI_SHIFT (1U)
-#define SDIF_IDSTS_RI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_RI_SHIFT)) & SDIF_IDSTS_RI_MASK)
-#define SDIF_IDSTS_FBE_MASK (0x4U)
-#define SDIF_IDSTS_FBE_SHIFT (2U)
-#define SDIF_IDSTS_FBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FBE_SHIFT)) & SDIF_IDSTS_FBE_MASK)
-#define SDIF_IDSTS_DU_MASK (0x10U)
-#define SDIF_IDSTS_DU_SHIFT (4U)
-#define SDIF_IDSTS_DU(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_DU_SHIFT)) & SDIF_IDSTS_DU_MASK)
-#define SDIF_IDSTS_CES_MASK (0x20U)
-#define SDIF_IDSTS_CES_SHIFT (5U)
-#define SDIF_IDSTS_CES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_CES_SHIFT)) & SDIF_IDSTS_CES_MASK)
-#define SDIF_IDSTS_NIS_MASK (0x100U)
-#define SDIF_IDSTS_NIS_SHIFT (8U)
-#define SDIF_IDSTS_NIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_NIS_SHIFT)) & SDIF_IDSTS_NIS_MASK)
-#define SDIF_IDSTS_AIS_MASK (0x200U)
-#define SDIF_IDSTS_AIS_SHIFT (9U)
-#define SDIF_IDSTS_AIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_AIS_SHIFT)) & SDIF_IDSTS_AIS_MASK)
-#define SDIF_IDSTS_EB_MASK (0x1C00U)
-#define SDIF_IDSTS_EB_SHIFT (10U)
-#define SDIF_IDSTS_EB(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_EB_SHIFT)) & SDIF_IDSTS_EB_MASK)
-#define SDIF_IDSTS_FSM_MASK (0x1E000U)
-#define SDIF_IDSTS_FSM_SHIFT (13U)
-#define SDIF_IDSTS_FSM(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FSM_SHIFT)) & SDIF_IDSTS_FSM_MASK)
-
-/*! @name IDINTEN - Internal DMAC Interrupt Enable register */
-#define SDIF_IDINTEN_TI_MASK (0x1U)
-#define SDIF_IDINTEN_TI_SHIFT (0U)
-#define SDIF_IDINTEN_TI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_TI_SHIFT)) & SDIF_IDINTEN_TI_MASK)
-#define SDIF_IDINTEN_RI_MASK (0x2U)
-#define SDIF_IDINTEN_RI_SHIFT (1U)
-#define SDIF_IDINTEN_RI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_RI_SHIFT)) & SDIF_IDINTEN_RI_MASK)
-#define SDIF_IDINTEN_FBE_MASK (0x4U)
-#define SDIF_IDINTEN_FBE_SHIFT (2U)
-#define SDIF_IDINTEN_FBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_FBE_SHIFT)) & SDIF_IDINTEN_FBE_MASK)
-#define SDIF_IDINTEN_DU_MASK (0x10U)
-#define SDIF_IDINTEN_DU_SHIFT (4U)
-#define SDIF_IDINTEN_DU(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_DU_SHIFT)) & SDIF_IDINTEN_DU_MASK)
-#define SDIF_IDINTEN_CES_MASK (0x20U)
-#define SDIF_IDINTEN_CES_SHIFT (5U)
-#define SDIF_IDINTEN_CES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_CES_SHIFT)) & SDIF_IDINTEN_CES_MASK)
-#define SDIF_IDINTEN_NIS_MASK (0x100U)
-#define SDIF_IDINTEN_NIS_SHIFT (8U)
-#define SDIF_IDINTEN_NIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_NIS_SHIFT)) & SDIF_IDINTEN_NIS_MASK)
-#define SDIF_IDINTEN_AIS_MASK (0x200U)
-#define SDIF_IDINTEN_AIS_SHIFT (9U)
-#define SDIF_IDINTEN_AIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_AIS_SHIFT)) & SDIF_IDINTEN_AIS_MASK)
-
-/*! @name DSCADDR - Current Host Descriptor Address register */
-#define SDIF_DSCADDR_HDA_MASK (0xFFFFFFFFU)
-#define SDIF_DSCADDR_HDA_SHIFT (0U)
-#define SDIF_DSCADDR_HDA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DSCADDR_HDA_SHIFT)) & SDIF_DSCADDR_HDA_MASK)
-
-/*! @name BUFADDR - Current Buffer Descriptor Address register */
-#define SDIF_BUFADDR_HBA_MASK (0xFFFFFFFFU)
-#define SDIF_BUFADDR_HBA_SHIFT (0U)
-#define SDIF_BUFADDR_HBA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BUFADDR_HBA_SHIFT)) & SDIF_BUFADDR_HBA_MASK)
-
-/*! @name CARDTHRCTL - Card Threshold Control */
-#define SDIF_CARDTHRCTL_CARDRDTHREN_MASK (0x1U)
-#define SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT (0U)
-#define SDIF_CARDTHRCTL_CARDRDTHREN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT)) & SDIF_CARDTHRCTL_CARDRDTHREN_MASK)
-#define SDIF_CARDTHRCTL_BSYCLRINTEN_MASK (0x2U)
-#define SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT (1U)
-#define SDIF_CARDTHRCTL_BSYCLRINTEN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT)) & SDIF_CARDTHRCTL_BSYCLRINTEN_MASK)
-#define SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK (0xFF0000U)
-#define SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT (16U)
-#define SDIF_CARDTHRCTL_CARDTHRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT)) & SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK)
-
-/*! @name BACKENDPWR - Power control */
-#define SDIF_BACKENDPWR_BACKENDPWR_MASK (0x1U)
-#define SDIF_BACKENDPWR_BACKENDPWR_SHIFT (0U)
-#define SDIF_BACKENDPWR_BACKENDPWR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BACKENDPWR_BACKENDPWR_SHIFT)) & SDIF_BACKENDPWR_BACKENDPWR_MASK)
-
-/*! @name FIFO - SDIF FIFO */
-#define SDIF_FIFO_DATA_MASK (0xFFFFFFFFU)
-#define SDIF_FIFO_DATA_SHIFT (0U)
-#define SDIF_FIFO_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFO_DATA_SHIFT)) & SDIF_FIFO_DATA_MASK)
-
-/* The count of SDIF_FIFO */
-#define SDIF_FIFO_COUNT (64U)
-
-
-/*!
- * @}
- */ /* end of group SDIF_Register_Masks */
-
-
-/* SDIF - Peripheral instance base addresses */
-/** Peripheral SDIF base address */
-#define SDIF_BASE (0x4009B000u)
-/** Peripheral SDIF base pointer */
-#define SDIF ((SDIF_Type *)SDIF_BASE)
-/** Array initializer of SDIF peripheral base addresses */
-#define SDIF_BASE_ADDRS { SDIF_BASE }
-/** Array initializer of SDIF peripheral base pointers */
-#define SDIF_BASE_PTRS { SDIF }
-/** Interrupt vectors for the SDIF peripheral type */
-#define SDIF_IRQS { SDIO_IRQn }
-
-/*!
- * @}
- */ /* end of group SDIF_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- SMARTCARD Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SMARTCARD_Peripheral_Access_Layer SMARTCARD Peripheral Access Layer
- * @{
- */
-
-/** SMARTCARD - Register Layout Typedef */
-typedef struct {
- union { /* offset: 0x0 */
- __IO uint32_t DLL; /**< Divisor Latch LSB, offset: 0x0 */
- __I uint32_t RBR; /**< Receiver Buffer Register, offset: 0x0 */
- __O uint32_t THR; /**< Transmit Holding Register, offset: 0x0 */
- };
- union { /* offset: 0x4 */
- __IO uint32_t DLM; /**< Divisor Latch MSB, offset: 0x4 */
- __IO uint32_t IER; /**< Interrupt Enable Register, offset: 0x4 */
- };
- union { /* offset: 0x8 */
- __O uint32_t FCR; /**< FIFO Control Register, offset: 0x8 */
- __I uint32_t IIR; /**< Interrupt ID Register, offset: 0x8 */
- };
- __IO uint32_t LCR; /**< Line Control Register, offset: 0xC */
- uint8_t RESERVED_0[4];
- __I uint32_t LSR; /**< Line Status Register, offset: 0x14 */
- uint8_t RESERVED_1[4];
- __IO uint32_t SCR; /**< Scratch Pad Register, offset: 0x1C */
- uint8_t RESERVED_2[12];
- __IO uint32_t OSR; /**< Oversampling register, offset: 0x2C */
- uint8_t RESERVED_3[24];
- __IO uint32_t SCICTRL; /**< Smart Card Interface control register, offset: 0x48 */
-} SMARTCARD_Type;
-
-/* ----------------------------------------------------------------------------
- -- SMARTCARD Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SMARTCARD_Register_Masks SMARTCARD Register Masks
- * @{
- */
-
-/*! @name DLL - Divisor Latch LSB */
-#define SMARTCARD_DLL_DLLSB_MASK (0xFFU)
-#define SMARTCARD_DLL_DLLSB_SHIFT (0U)
-#define SMARTCARD_DLL_DLLSB(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_DLL_DLLSB_SHIFT)) & SMARTCARD_DLL_DLLSB_MASK)
-
-/*! @name RBR - Receiver Buffer Register */
-#define SMARTCARD_RBR_RBR_MASK (0xFFU)
-#define SMARTCARD_RBR_RBR_SHIFT (0U)
-#define SMARTCARD_RBR_RBR(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_RBR_RBR_SHIFT)) & SMARTCARD_RBR_RBR_MASK)
-
-/*! @name THR - Transmit Holding Register */
-#define SMARTCARD_THR_THR_MASK (0xFFU)
-#define SMARTCARD_THR_THR_SHIFT (0U)
-#define SMARTCARD_THR_THR(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_THR_THR_SHIFT)) & SMARTCARD_THR_THR_MASK)
-
-/*! @name DLM - Divisor Latch MSB */
-#define SMARTCARD_DLM_DLMSB_MASK (0xFFU)
-#define SMARTCARD_DLM_DLMSB_SHIFT (0U)
-#define SMARTCARD_DLM_DLMSB(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_DLM_DLMSB_SHIFT)) & SMARTCARD_DLM_DLMSB_MASK)
-
-/*! @name IER - Interrupt Enable Register */
-#define SMARTCARD_IER_RBRIE_MASK (0x1U)
-#define SMARTCARD_IER_RBRIE_SHIFT (0U)
-#define SMARTCARD_IER_RBRIE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IER_RBRIE_SHIFT)) & SMARTCARD_IER_RBRIE_MASK)
-#define SMARTCARD_IER_THREIE_MASK (0x2U)
-#define SMARTCARD_IER_THREIE_SHIFT (1U)
-#define SMARTCARD_IER_THREIE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IER_THREIE_SHIFT)) & SMARTCARD_IER_THREIE_MASK)
-#define SMARTCARD_IER_RXIE_MASK (0x4U)
-#define SMARTCARD_IER_RXIE_SHIFT (2U)
-#define SMARTCARD_IER_RXIE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IER_RXIE_SHIFT)) & SMARTCARD_IER_RXIE_MASK)
-
-/*! @name FCR - FIFO Control Register */
-#define SMARTCARD_FCR_FIFOEN_MASK (0x1U)
-#define SMARTCARD_FCR_FIFOEN_SHIFT (0U)
-#define SMARTCARD_FCR_FIFOEN(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_FIFOEN_SHIFT)) & SMARTCARD_FCR_FIFOEN_MASK)
-#define SMARTCARD_FCR_RXFIFORES_MASK (0x2U)
-#define SMARTCARD_FCR_RXFIFORES_SHIFT (1U)
-#define SMARTCARD_FCR_RXFIFORES(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_RXFIFORES_SHIFT)) & SMARTCARD_FCR_RXFIFORES_MASK)
-#define SMARTCARD_FCR_TXFIFORES_MASK (0x4U)
-#define SMARTCARD_FCR_TXFIFORES_SHIFT (2U)
-#define SMARTCARD_FCR_TXFIFORES(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_TXFIFORES_SHIFT)) & SMARTCARD_FCR_TXFIFORES_MASK)
-#define SMARTCARD_FCR_DMAMODE_MASK (0x8U)
-#define SMARTCARD_FCR_DMAMODE_SHIFT (3U)
-#define SMARTCARD_FCR_DMAMODE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_DMAMODE_SHIFT)) & SMARTCARD_FCR_DMAMODE_MASK)
-#define SMARTCARD_FCR_RXTRIGLVL_MASK (0xC0U)
-#define SMARTCARD_FCR_RXTRIGLVL_SHIFT (6U)
-#define SMARTCARD_FCR_RXTRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_RXTRIGLVL_SHIFT)) & SMARTCARD_FCR_RXTRIGLVL_MASK)
-
-/*! @name IIR - Interrupt ID Register */
-#define SMARTCARD_IIR_INTSTATUS_MASK (0x1U)
-#define SMARTCARD_IIR_INTSTATUS_SHIFT (0U)
-#define SMARTCARD_IIR_INTSTATUS(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IIR_INTSTATUS_SHIFT)) & SMARTCARD_IIR_INTSTATUS_MASK)
-#define SMARTCARD_IIR_INTID_MASK (0xEU)
-#define SMARTCARD_IIR_INTID_SHIFT (1U)
-#define SMARTCARD_IIR_INTID(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IIR_INTID_SHIFT)) & SMARTCARD_IIR_INTID_MASK)
-#define SMARTCARD_IIR_FIFOENABLE_MASK (0xC0U)
-#define SMARTCARD_IIR_FIFOENABLE_SHIFT (6U)
-#define SMARTCARD_IIR_FIFOENABLE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IIR_FIFOENABLE_SHIFT)) & SMARTCARD_IIR_FIFOENABLE_MASK)
-
-/*! @name LCR - Line Control Register */
-#define SMARTCARD_LCR_WLS_MASK (0x3U)
-#define SMARTCARD_LCR_WLS_SHIFT (0U)
-#define SMARTCARD_LCR_WLS(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_WLS_SHIFT)) & SMARTCARD_LCR_WLS_MASK)
-#define SMARTCARD_LCR_SBS_MASK (0x4U)
-#define SMARTCARD_LCR_SBS_SHIFT (2U)
-#define SMARTCARD_LCR_SBS(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_SBS_SHIFT)) & SMARTCARD_LCR_SBS_MASK)
-#define SMARTCARD_LCR_PE_MASK (0x8U)
-#define SMARTCARD_LCR_PE_SHIFT (3U)
-#define SMARTCARD_LCR_PE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_PE_SHIFT)) & SMARTCARD_LCR_PE_MASK)
-#define SMARTCARD_LCR_PS_MASK (0x30U)
-#define SMARTCARD_LCR_PS_SHIFT (4U)
-#define SMARTCARD_LCR_PS(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_PS_SHIFT)) & SMARTCARD_LCR_PS_MASK)
-#define SMARTCARD_LCR_DLAB_MASK (0x80U)
-#define SMARTCARD_LCR_DLAB_SHIFT (7U)
-#define SMARTCARD_LCR_DLAB(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_DLAB_SHIFT)) & SMARTCARD_LCR_DLAB_MASK)
-
-/*! @name LSR - Line Status Register */
-#define SMARTCARD_LSR_RDR_MASK (0x1U)
-#define SMARTCARD_LSR_RDR_SHIFT (0U)
-#define SMARTCARD_LSR_RDR(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_RDR_SHIFT)) & SMARTCARD_LSR_RDR_MASK)
-#define SMARTCARD_LSR_OE_MASK (0x2U)
-#define SMARTCARD_LSR_OE_SHIFT (1U)
-#define SMARTCARD_LSR_OE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_OE_SHIFT)) & SMARTCARD_LSR_OE_MASK)
-#define SMARTCARD_LSR_PE_MASK (0x4U)
-#define SMARTCARD_LSR_PE_SHIFT (2U)
-#define SMARTCARD_LSR_PE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_PE_SHIFT)) & SMARTCARD_LSR_PE_MASK)
-#define SMARTCARD_LSR_FE_MASK (0x8U)
-#define SMARTCARD_LSR_FE_SHIFT (3U)
-#define SMARTCARD_LSR_FE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_FE_SHIFT)) & SMARTCARD_LSR_FE_MASK)
-#define SMARTCARD_LSR_THRE_MASK (0x20U)
-#define SMARTCARD_LSR_THRE_SHIFT (5U)
-#define SMARTCARD_LSR_THRE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_THRE_SHIFT)) & SMARTCARD_LSR_THRE_MASK)
-#define SMARTCARD_LSR_TEMT_MASK (0x40U)
-#define SMARTCARD_LSR_TEMT_SHIFT (6U)
-#define SMARTCARD_LSR_TEMT(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_TEMT_SHIFT)) & SMARTCARD_LSR_TEMT_MASK)
-#define SMARTCARD_LSR_RXFE_MASK (0x80U)
-#define SMARTCARD_LSR_RXFE_SHIFT (7U)
-#define SMARTCARD_LSR_RXFE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_RXFE_SHIFT)) & SMARTCARD_LSR_RXFE_MASK)
-
-/*! @name SCR - Scratch Pad Register */
-#define SMARTCARD_SCR_PAD_MASK (0xFFU)
-#define SMARTCARD_SCR_PAD_SHIFT (0U)
-#define SMARTCARD_SCR_PAD(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCR_PAD_SHIFT)) & SMARTCARD_SCR_PAD_MASK)
-
-/*! @name OSR - Oversampling register */
-#define SMARTCARD_OSR_OSFRAC_MASK (0xEU)
-#define SMARTCARD_OSR_OSFRAC_SHIFT (1U)
-#define SMARTCARD_OSR_OSFRAC(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_OSR_OSFRAC_SHIFT)) & SMARTCARD_OSR_OSFRAC_MASK)
-#define SMARTCARD_OSR_OSINT_MASK (0xF0U)
-#define SMARTCARD_OSR_OSINT_SHIFT (4U)
-#define SMARTCARD_OSR_OSINT(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_OSR_OSINT_SHIFT)) & SMARTCARD_OSR_OSINT_MASK)
-#define SMARTCARD_OSR_FDINT_MASK (0x7F00U)
-#define SMARTCARD_OSR_FDINT_SHIFT (8U)
-#define SMARTCARD_OSR_FDINT(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_OSR_FDINT_SHIFT)) & SMARTCARD_OSR_FDINT_MASK)
-
-/*! @name SCICTRL - Smart Card Interface control register */
-#define SMARTCARD_SCICTRL_SCIEN_MASK (0x1U)
-#define SMARTCARD_SCICTRL_SCIEN_SHIFT (0U)
-#define SMARTCARD_SCICTRL_SCIEN(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_SCIEN_SHIFT)) & SMARTCARD_SCICTRL_SCIEN_MASK)
-#define SMARTCARD_SCICTRL_NACKDIS_MASK (0x2U)
-#define SMARTCARD_SCICTRL_NACKDIS_SHIFT (1U)
-#define SMARTCARD_SCICTRL_NACKDIS(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_NACKDIS_SHIFT)) & SMARTCARD_SCICTRL_NACKDIS_MASK)
-#define SMARTCARD_SCICTRL_PROTSEL_MASK (0x4U)
-#define SMARTCARD_SCICTRL_PROTSEL_SHIFT (2U)
-#define SMARTCARD_SCICTRL_PROTSEL(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_PROTSEL_SHIFT)) & SMARTCARD_SCICTRL_PROTSEL_MASK)
-#define SMARTCARD_SCICTRL_TXRETRY_MASK (0xE0U)
-#define SMARTCARD_SCICTRL_TXRETRY_SHIFT (5U)
-#define SMARTCARD_SCICTRL_TXRETRY(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_TXRETRY_SHIFT)) & SMARTCARD_SCICTRL_TXRETRY_MASK)
-#define SMARTCARD_SCICTRL_GUARDTIME_MASK (0xFF00U)
-#define SMARTCARD_SCICTRL_GUARDTIME_SHIFT (8U)
-#define SMARTCARD_SCICTRL_GUARDTIME(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_GUARDTIME_SHIFT)) & SMARTCARD_SCICTRL_GUARDTIME_MASK)
-
-
-/*!
- * @}
- */ /* end of group SMARTCARD_Register_Masks */
-
-
-/* SMARTCARD - Peripheral instance base addresses */
-/** Peripheral SMARTCARD0 base address */
-#define SMARTCARD0_BASE (0x40036000u)
-/** Peripheral SMARTCARD0 base pointer */
-#define SMARTCARD0 ((SMARTCARD_Type *)SMARTCARD0_BASE)
-/** Peripheral SMARTCARD1 base address */
-#define SMARTCARD1_BASE (0x40037000u)
-/** Peripheral SMARTCARD1 base pointer */
-#define SMARTCARD1 ((SMARTCARD_Type *)SMARTCARD1_BASE)
-/** Array initializer of SMARTCARD peripheral base addresses */
-#define SMARTCARD_BASE_ADDRS { SMARTCARD0_BASE, SMARTCARD1_BASE }
-/** Array initializer of SMARTCARD peripheral base pointers */
-#define SMARTCARD_BASE_PTRS { SMARTCARD0, SMARTCARD1 }
-/** Interrupt vectors for the SMARTCARD peripheral type */
-#define SMARTCARD_IRQS { SMARTCARD0_IRQn, SMARTCARD1_IRQn }
-
-/*!
- * @}
- */ /* end of group SMARTCARD_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- SPI Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
- * @{
- */
-
-/** SPI - Register Layout Typedef */
-typedef struct {
- uint8_t RESERVED_0[1024];
- __IO uint32_t CFG; /**< SPI Configuration register, offset: 0x400 */
- __IO uint32_t DLY; /**< SPI Delay register, offset: 0x404 */
- __IO uint32_t STAT; /**< SPI Status. Some status flags can be cleared by writing a 1 to that bit position., offset: 0x408 */
- __IO uint32_t INTENSET; /**< SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0x40C */
- __O uint32_t INTENCLR; /**< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared., offset: 0x410 */
- uint8_t RESERVED_1[16];
- __IO uint32_t DIV; /**< SPI clock Divider, offset: 0x424 */
- __I uint32_t INTSTAT; /**< SPI Interrupt Status, offset: 0x428 */
- uint8_t RESERVED_2[2516];
- __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */
- __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */
- __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */
- uint8_t RESERVED_3[4];
- __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */
- __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */
- __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */
- uint8_t RESERVED_4[4];
- __IO uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */
- uint8_t RESERVED_5[12];
- __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */
- uint8_t RESERVED_6[12];
- __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */
- uint8_t RESERVED_7[440];
- __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */
-} SPI_Type;
-
-/* ----------------------------------------------------------------------------
- -- SPI Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SPI_Register_Masks SPI Register Masks
- * @{
- */
-
-/*! @name CFG - SPI Configuration register */
-#define SPI_CFG_ENABLE_MASK (0x1U)
-#define SPI_CFG_ENABLE_SHIFT (0U)
-#define SPI_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK)
-#define SPI_CFG_MASTER_MASK (0x4U)
-#define SPI_CFG_MASTER_SHIFT (2U)
-#define SPI_CFG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK)
-#define SPI_CFG_LSBF_MASK (0x8U)
-#define SPI_CFG_LSBF_SHIFT (3U)
-#define SPI_CFG_LSBF(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK)
-#define SPI_CFG_CPHA_MASK (0x10U)
-#define SPI_CFG_CPHA_SHIFT (4U)
-#define SPI_CFG_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK)
-#define SPI_CFG_CPOL_MASK (0x20U)
-#define SPI_CFG_CPOL_SHIFT (5U)
-#define SPI_CFG_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK)
-#define SPI_CFG_LOOP_MASK (0x80U)
-#define SPI_CFG_LOOP_SHIFT (7U)
-#define SPI_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK)
-#define SPI_CFG_SPOL0_MASK (0x100U)
-#define SPI_CFG_SPOL0_SHIFT (8U)
-#define SPI_CFG_SPOL0(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK)
-#define SPI_CFG_SPOL1_MASK (0x200U)
-#define SPI_CFG_SPOL1_SHIFT (9U)
-#define SPI_CFG_SPOL1(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK)
-#define SPI_CFG_SPOL2_MASK (0x400U)
-#define SPI_CFG_SPOL2_SHIFT (10U)
-#define SPI_CFG_SPOL2(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK)
-#define SPI_CFG_SPOL3_MASK (0x800U)
-#define SPI_CFG_SPOL3_SHIFT (11U)
-#define SPI_CFG_SPOL3(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL3_SHIFT)) & SPI_CFG_SPOL3_MASK)
-
-/*! @name DLY - SPI Delay register */
-#define SPI_DLY_PRE_DELAY_MASK (0xFU)
-#define SPI_DLY_PRE_DELAY_SHIFT (0U)
-#define SPI_DLY_PRE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK)
-#define SPI_DLY_POST_DELAY_MASK (0xF0U)
-#define SPI_DLY_POST_DELAY_SHIFT (4U)
-#define SPI_DLY_POST_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK)
-#define SPI_DLY_FRAME_DELAY_MASK (0xF00U)
-#define SPI_DLY_FRAME_DELAY_SHIFT (8U)
-#define SPI_DLY_FRAME_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK)
-#define SPI_DLY_TRANSFER_DELAY_MASK (0xF000U)
-#define SPI_DLY_TRANSFER_DELAY_SHIFT (12U)
-#define SPI_DLY_TRANSFER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK)
-
-/*! @name STAT - SPI Status. Some status flags can be cleared by writing a 1 to that bit position. */
-#define SPI_STAT_SSA_MASK (0x10U)
-#define SPI_STAT_SSA_SHIFT (4U)
-#define SPI_STAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK)
-#define SPI_STAT_SSD_MASK (0x20U)
-#define SPI_STAT_SSD_SHIFT (5U)
-#define SPI_STAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK)
-#define SPI_STAT_STALLED_MASK (0x40U)
-#define SPI_STAT_STALLED_SHIFT (6U)
-#define SPI_STAT_STALLED(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK)
-#define SPI_STAT_ENDTRANSFER_MASK (0x80U)
-#define SPI_STAT_ENDTRANSFER_SHIFT (7U)
-#define SPI_STAT_ENDTRANSFER(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK)
-#define SPI_STAT_MSTIDLE_MASK (0x100U)
-#define SPI_STAT_MSTIDLE_SHIFT (8U)
-#define SPI_STAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK)
-
-/*! @name INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */
-#define SPI_INTENSET_SSAEN_MASK (0x10U)
-#define SPI_INTENSET_SSAEN_SHIFT (4U)
-#define SPI_INTENSET_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK)
-#define SPI_INTENSET_SSDEN_MASK (0x20U)
-#define SPI_INTENSET_SSDEN_SHIFT (5U)
-#define SPI_INTENSET_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK)
-#define SPI_INTENSET_MSTIDLEEN_MASK (0x100U)
-#define SPI_INTENSET_MSTIDLEEN_SHIFT (8U)
-#define SPI_INTENSET_MSTIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK)
-
-/*! @name INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. */
-#define SPI_INTENCLR_SSAEN_MASK (0x10U)
-#define SPI_INTENCLR_SSAEN_SHIFT (4U)
-#define SPI_INTENCLR_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK)
-#define SPI_INTENCLR_SSDEN_MASK (0x20U)
-#define SPI_INTENCLR_SSDEN_SHIFT (5U)
-#define SPI_INTENCLR_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK)
-#define SPI_INTENCLR_MSTIDLE_MASK (0x100U)
-#define SPI_INTENCLR_MSTIDLE_SHIFT (8U)
-#define SPI_INTENCLR_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK)
-
-/*! @name DIV - SPI clock Divider */
-#define SPI_DIV_DIVVAL_MASK (0xFFFFU)
-#define SPI_DIV_DIVVAL_SHIFT (0U)
-#define SPI_DIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK)
-
-/*! @name INTSTAT - SPI Interrupt Status */
-#define SPI_INTSTAT_SSA_MASK (0x10U)
-#define SPI_INTSTAT_SSA_SHIFT (4U)
-#define SPI_INTSTAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK)
-#define SPI_INTSTAT_SSD_MASK (0x20U)
-#define SPI_INTSTAT_SSD_SHIFT (5U)
-#define SPI_INTSTAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK)
-#define SPI_INTSTAT_MSTIDLE_MASK (0x100U)
-#define SPI_INTSTAT_MSTIDLE_SHIFT (8U)
-#define SPI_INTSTAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK)
-
-/*! @name FIFOCFG - FIFO configuration and enable register. */
-#define SPI_FIFOCFG_ENABLETX_MASK (0x1U)
-#define SPI_FIFOCFG_ENABLETX_SHIFT (0U)
-#define SPI_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK)
-#define SPI_FIFOCFG_ENABLERX_MASK (0x2U)
-#define SPI_FIFOCFG_ENABLERX_SHIFT (1U)
-#define SPI_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLERX_SHIFT)) & SPI_FIFOCFG_ENABLERX_MASK)
-#define SPI_FIFOCFG_SIZE_MASK (0x30U)
-#define SPI_FIFOCFG_SIZE_SHIFT (4U)
-#define SPI_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_SIZE_SHIFT)) & SPI_FIFOCFG_SIZE_MASK)
-#define SPI_FIFOCFG_DMATX_MASK (0x1000U)
-#define SPI_FIFOCFG_DMATX_SHIFT (12U)
-#define SPI_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMATX_SHIFT)) & SPI_FIFOCFG_DMATX_MASK)
-#define SPI_FIFOCFG_DMARX_MASK (0x2000U)
-#define SPI_FIFOCFG_DMARX_SHIFT (13U)
-#define SPI_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMARX_SHIFT)) & SPI_FIFOCFG_DMARX_MASK)
-#define SPI_FIFOCFG_WAKETX_MASK (0x4000U)
-#define SPI_FIFOCFG_WAKETX_SHIFT (14U)
-#define SPI_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKETX_SHIFT)) & SPI_FIFOCFG_WAKETX_MASK)
-#define SPI_FIFOCFG_WAKERX_MASK (0x8000U)
-#define SPI_FIFOCFG_WAKERX_SHIFT (15U)
-#define SPI_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKERX_SHIFT)) & SPI_FIFOCFG_WAKERX_MASK)
-#define SPI_FIFOCFG_EMPTYTX_MASK (0x10000U)
-#define SPI_FIFOCFG_EMPTYTX_SHIFT (16U)
-#define SPI_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYTX_SHIFT)) & SPI_FIFOCFG_EMPTYTX_MASK)
-#define SPI_FIFOCFG_EMPTYRX_MASK (0x20000U)
-#define SPI_FIFOCFG_EMPTYRX_SHIFT (17U)
-#define SPI_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK)
-#define SPI_FIFOCFG_POPDBG_MASK (0x40000U)
-#define SPI_FIFOCFG_POPDBG_SHIFT (18U)
-#define SPI_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_POPDBG_SHIFT)) & SPI_FIFOCFG_POPDBG_MASK)
-
-/*! @name FIFOSTAT - FIFO status register. */
-#define SPI_FIFOSTAT_TXERR_MASK (0x1U)
-#define SPI_FIFOSTAT_TXERR_SHIFT (0U)
-#define SPI_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXERR_SHIFT)) & SPI_FIFOSTAT_TXERR_MASK)
-#define SPI_FIFOSTAT_RXERR_MASK (0x2U)
-#define SPI_FIFOSTAT_RXERR_SHIFT (1U)
-#define SPI_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXERR_SHIFT)) & SPI_FIFOSTAT_RXERR_MASK)
-#define SPI_FIFOSTAT_PERINT_MASK (0x8U)
-#define SPI_FIFOSTAT_PERINT_SHIFT (3U)
-#define SPI_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_PERINT_SHIFT)) & SPI_FIFOSTAT_PERINT_MASK)
-#define SPI_FIFOSTAT_TXEMPTY_MASK (0x10U)
-#define SPI_FIFOSTAT_TXEMPTY_SHIFT (4U)
-#define SPI_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXEMPTY_SHIFT)) & SPI_FIFOSTAT_TXEMPTY_MASK)
-#define SPI_FIFOSTAT_TXNOTFULL_MASK (0x20U)
-#define SPI_FIFOSTAT_TXNOTFULL_SHIFT (5U)
-#define SPI_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXNOTFULL_SHIFT)) & SPI_FIFOSTAT_TXNOTFULL_MASK)
-#define SPI_FIFOSTAT_RXNOTEMPTY_MASK (0x40U)
-#define SPI_FIFOSTAT_RXNOTEMPTY_SHIFT (6U)
-#define SPI_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXNOTEMPTY_SHIFT)) & SPI_FIFOSTAT_RXNOTEMPTY_MASK)
-#define SPI_FIFOSTAT_RXFULL_MASK (0x80U)
-#define SPI_FIFOSTAT_RXFULL_SHIFT (7U)
-#define SPI_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXFULL_SHIFT)) & SPI_FIFOSTAT_RXFULL_MASK)
-#define SPI_FIFOSTAT_TXLVL_MASK (0x1F00U)
-#define SPI_FIFOSTAT_TXLVL_SHIFT (8U)
-#define SPI_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXLVL_SHIFT)) & SPI_FIFOSTAT_TXLVL_MASK)
-#define SPI_FIFOSTAT_RXLVL_MASK (0x1F0000U)
-#define SPI_FIFOSTAT_RXLVL_SHIFT (16U)
-#define SPI_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXLVL_SHIFT)) & SPI_FIFOSTAT_RXLVL_MASK)
-
-/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */
-#define SPI_FIFOTRIG_TXLVLENA_MASK (0x1U)
-#define SPI_FIFOTRIG_TXLVLENA_SHIFT (0U)
-#define SPI_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVLENA_SHIFT)) & SPI_FIFOTRIG_TXLVLENA_MASK)
-#define SPI_FIFOTRIG_RXLVLENA_MASK (0x2U)
-#define SPI_FIFOTRIG_RXLVLENA_SHIFT (1U)
-#define SPI_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVLENA_SHIFT)) & SPI_FIFOTRIG_RXLVLENA_MASK)
-#define SPI_FIFOTRIG_TXLVL_MASK (0xF00U)
-#define SPI_FIFOTRIG_TXLVL_SHIFT (8U)
-#define SPI_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVL_SHIFT)) & SPI_FIFOTRIG_TXLVL_MASK)
-#define SPI_FIFOTRIG_RXLVL_MASK (0xF0000U)
-#define SPI_FIFOTRIG_RXLVL_SHIFT (16U)
-#define SPI_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVL_SHIFT)) & SPI_FIFOTRIG_RXLVL_MASK)
-
-/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */
-#define SPI_FIFOINTENSET_TXERR_MASK (0x1U)
-#define SPI_FIFOINTENSET_TXERR_SHIFT (0U)
-#define SPI_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXERR_SHIFT)) & SPI_FIFOINTENSET_TXERR_MASK)
-#define SPI_FIFOINTENSET_RXERR_MASK (0x2U)
-#define SPI_FIFOINTENSET_RXERR_SHIFT (1U)
-#define SPI_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXERR_SHIFT)) & SPI_FIFOINTENSET_RXERR_MASK)
-#define SPI_FIFOINTENSET_TXLVL_MASK (0x4U)
-#define SPI_FIFOINTENSET_TXLVL_SHIFT (2U)
-#define SPI_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXLVL_SHIFT)) & SPI_FIFOINTENSET_TXLVL_MASK)
-#define SPI_FIFOINTENSET_RXLVL_MASK (0x8U)
-#define SPI_FIFOINTENSET_RXLVL_SHIFT (3U)
-#define SPI_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXLVL_SHIFT)) & SPI_FIFOINTENSET_RXLVL_MASK)
-
-/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */
-#define SPI_FIFOINTENCLR_TXERR_MASK (0x1U)
-#define SPI_FIFOINTENCLR_TXERR_SHIFT (0U)
-#define SPI_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXERR_SHIFT)) & SPI_FIFOINTENCLR_TXERR_MASK)
-#define SPI_FIFOINTENCLR_RXERR_MASK (0x2U)
-#define SPI_FIFOINTENCLR_RXERR_SHIFT (1U)
-#define SPI_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXERR_SHIFT)) & SPI_FIFOINTENCLR_RXERR_MASK)
-#define SPI_FIFOINTENCLR_TXLVL_MASK (0x4U)
-#define SPI_FIFOINTENCLR_TXLVL_SHIFT (2U)
-#define SPI_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXLVL_SHIFT)) & SPI_FIFOINTENCLR_TXLVL_MASK)
-#define SPI_FIFOINTENCLR_RXLVL_MASK (0x8U)
-#define SPI_FIFOINTENCLR_RXLVL_SHIFT (3U)
-#define SPI_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXLVL_SHIFT)) & SPI_FIFOINTENCLR_RXLVL_MASK)
-
-/*! @name FIFOINTSTAT - FIFO interrupt status register. */
-#define SPI_FIFOINTSTAT_TXERR_MASK (0x1U)
-#define SPI_FIFOINTSTAT_TXERR_SHIFT (0U)
-#define SPI_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXERR_SHIFT)) & SPI_FIFOINTSTAT_TXERR_MASK)
-#define SPI_FIFOINTSTAT_RXERR_MASK (0x2U)
-#define SPI_FIFOINTSTAT_RXERR_SHIFT (1U)
-#define SPI_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXERR_SHIFT)) & SPI_FIFOINTSTAT_RXERR_MASK)
-#define SPI_FIFOINTSTAT_TXLVL_MASK (0x4U)
-#define SPI_FIFOINTSTAT_TXLVL_SHIFT (2U)
-#define SPI_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXLVL_SHIFT)) & SPI_FIFOINTSTAT_TXLVL_MASK)
-#define SPI_FIFOINTSTAT_RXLVL_MASK (0x8U)
-#define SPI_FIFOINTSTAT_RXLVL_SHIFT (3U)
-#define SPI_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXLVL_SHIFT)) & SPI_FIFOINTSTAT_RXLVL_MASK)
-#define SPI_FIFOINTSTAT_PERINT_MASK (0x10U)
-#define SPI_FIFOINTSTAT_PERINT_SHIFT (4U)
-#define SPI_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_PERINT_SHIFT)) & SPI_FIFOINTSTAT_PERINT_MASK)
-
-/*! @name FIFOWR - FIFO write data. */
-#define SPI_FIFOWR_TXDATA_MASK (0xFFFFU)
-#define SPI_FIFOWR_TXDATA_SHIFT (0U)
-#define SPI_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXDATA_SHIFT)) & SPI_FIFOWR_TXDATA_MASK)
-#define SPI_FIFOWR_TXSSEL0_N_MASK (0x10000U)
-#define SPI_FIFOWR_TXSSEL0_N_SHIFT (16U)
-#define SPI_FIFOWR_TXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL0_N_SHIFT)) & SPI_FIFOWR_TXSSEL0_N_MASK)
-#define SPI_FIFOWR_TXSSEL1_N_MASK (0x20000U)
-#define SPI_FIFOWR_TXSSEL1_N_SHIFT (17U)
-#define SPI_FIFOWR_TXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL1_N_SHIFT)) & SPI_FIFOWR_TXSSEL1_N_MASK)
-#define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U)
-#define SPI_FIFOWR_TXSSEL2_N_SHIFT (18U)
-#define SPI_FIFOWR_TXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK)
-#define SPI_FIFOWR_TXSSEL3_N_MASK (0x80000U)
-#define SPI_FIFOWR_TXSSEL3_N_SHIFT (19U)
-#define SPI_FIFOWR_TXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL3_N_SHIFT)) & SPI_FIFOWR_TXSSEL3_N_MASK)
-#define SPI_FIFOWR_EOT_MASK (0x100000U)
-#define SPI_FIFOWR_EOT_SHIFT (20U)
-#define SPI_FIFOWR_EOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOT_SHIFT)) & SPI_FIFOWR_EOT_MASK)
-#define SPI_FIFOWR_EOF_MASK (0x200000U)
-#define SPI_FIFOWR_EOF_SHIFT (21U)
-#define SPI_FIFOWR_EOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOF_SHIFT)) & SPI_FIFOWR_EOF_MASK)
-#define SPI_FIFOWR_RXIGNORE_MASK (0x400000U)
-#define SPI_FIFOWR_RXIGNORE_SHIFT (22U)
-#define SPI_FIFOWR_RXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_RXIGNORE_SHIFT)) & SPI_FIFOWR_RXIGNORE_MASK)
-#define SPI_FIFOWR_LEN_MASK (0xF000000U)
-#define SPI_FIFOWR_LEN_SHIFT (24U)
-#define SPI_FIFOWR_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_LEN_SHIFT)) & SPI_FIFOWR_LEN_MASK)
-
-/*! @name FIFORD - FIFO read data. */
-#define SPI_FIFORD_RXDATA_MASK (0xFFFFU)
-#define SPI_FIFORD_RXDATA_SHIFT (0U)
-#define SPI_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXDATA_SHIFT)) & SPI_FIFORD_RXDATA_MASK)
-#define SPI_FIFORD_RXSSEL0_N_MASK (0x10000U)
-#define SPI_FIFORD_RXSSEL0_N_SHIFT (16U)
-#define SPI_FIFORD_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL0_N_SHIFT)) & SPI_FIFORD_RXSSEL0_N_MASK)
-#define SPI_FIFORD_RXSSEL1_N_MASK (0x20000U)
-#define SPI_FIFORD_RXSSEL1_N_SHIFT (17U)
-#define SPI_FIFORD_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL1_N_SHIFT)) & SPI_FIFORD_RXSSEL1_N_MASK)
-#define SPI_FIFORD_RXSSEL2_N_MASK (0x40000U)
-#define SPI_FIFORD_RXSSEL2_N_SHIFT (18U)
-#define SPI_FIFORD_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL2_N_SHIFT)) & SPI_FIFORD_RXSSEL2_N_MASK)
-#define SPI_FIFORD_RXSSEL3_N_MASK (0x80000U)
-#define SPI_FIFORD_RXSSEL3_N_SHIFT (19U)
-#define SPI_FIFORD_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL3_N_SHIFT)) & SPI_FIFORD_RXSSEL3_N_MASK)
-#define SPI_FIFORD_SOT_MASK (0x100000U)
-#define SPI_FIFORD_SOT_SHIFT (20U)
-#define SPI_FIFORD_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_SOT_SHIFT)) & SPI_FIFORD_SOT_MASK)
-
-/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */
-#define SPI_FIFORDNOPOP_RXDATA_MASK (0xFFFFU)
-#define SPI_FIFORDNOPOP_RXDATA_SHIFT (0U)
-#define SPI_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXDATA_SHIFT)) & SPI_FIFORDNOPOP_RXDATA_MASK)
-#define SPI_FIFORDNOPOP_RXSSEL0_N_MASK (0x10000U)
-#define SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT (16U)
-#define SPI_FIFORDNOPOP_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL0_N_MASK)
-#define SPI_FIFORDNOPOP_RXSSEL1_N_MASK (0x20000U)
-#define SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT (17U)
-#define SPI_FIFORDNOPOP_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL1_N_MASK)
-#define SPI_FIFORDNOPOP_RXSSEL2_N_MASK (0x40000U)
-#define SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT (18U)
-#define SPI_FIFORDNOPOP_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL2_N_MASK)
-#define SPI_FIFORDNOPOP_RXSSEL3_N_MASK (0x80000U)
-#define SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT (19U)
-#define SPI_FIFORDNOPOP_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL3_N_MASK)
-#define SPI_FIFORDNOPOP_SOT_MASK (0x100000U)
-#define SPI_FIFORDNOPOP_SOT_SHIFT (20U)
-#define SPI_FIFORDNOPOP_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK)
-
-/*! @name ID - Peripheral identification register. */
-#define SPI_ID_APERTURE_MASK (0xFFU)
-#define SPI_ID_APERTURE_SHIFT (0U)
-#define SPI_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_APERTURE_SHIFT)) & SPI_ID_APERTURE_MASK)
-#define SPI_ID_MINOR_REV_MASK (0xF00U)
-#define SPI_ID_MINOR_REV_SHIFT (8U)
-#define SPI_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MINOR_REV_SHIFT)) & SPI_ID_MINOR_REV_MASK)
-#define SPI_ID_MAJOR_REV_MASK (0xF000U)
-#define SPI_ID_MAJOR_REV_SHIFT (12U)
-#define SPI_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MAJOR_REV_SHIFT)) & SPI_ID_MAJOR_REV_MASK)
-#define SPI_ID_ID_MASK (0xFFFF0000U)
-#define SPI_ID_ID_SHIFT (16U)
-#define SPI_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_ID_SHIFT)) & SPI_ID_ID_MASK)
-
-
-/*!
- * @}
- */ /* end of group SPI_Register_Masks */
-
-
-/* SPI - Peripheral instance base addresses */
-/** Peripheral SPI0 base address */
-#define SPI0_BASE (0x40086000u)
-/** Peripheral SPI0 base pointer */
-#define SPI0 ((SPI_Type *)SPI0_BASE)
-/** Peripheral SPI1 base address */
-#define SPI1_BASE (0x40087000u)
-/** Peripheral SPI1 base pointer */
-#define SPI1 ((SPI_Type *)SPI1_BASE)
-/** Peripheral SPI2 base address */
-#define SPI2_BASE (0x40088000u)
-/** Peripheral SPI2 base pointer */
-#define SPI2 ((SPI_Type *)SPI2_BASE)
-/** Peripheral SPI3 base address */
-#define SPI3_BASE (0x40089000u)
-/** Peripheral SPI3 base pointer */
-#define SPI3 ((SPI_Type *)SPI3_BASE)
-/** Peripheral SPI4 base address */
-#define SPI4_BASE (0x4008A000u)
-/** Peripheral SPI4 base pointer */
-#define SPI4 ((SPI_Type *)SPI4_BASE)
-/** Peripheral SPI5 base address */
-#define SPI5_BASE (0x40096000u)
-/** Peripheral SPI5 base pointer */
-#define SPI5 ((SPI_Type *)SPI5_BASE)
-/** Peripheral SPI6 base address */
-#define SPI6_BASE (0x40097000u)
-/** Peripheral SPI6 base pointer */
-#define SPI6 ((SPI_Type *)SPI6_BASE)
-/** Peripheral SPI7 base address */
-#define SPI7_BASE (0x40098000u)
-/** Peripheral SPI7 base pointer */
-#define SPI7 ((SPI_Type *)SPI7_BASE)
-/** Peripheral SPI8 base address */
-#define SPI8_BASE (0x40099000u)
-/** Peripheral SPI8 base pointer */
-#define SPI8 ((SPI_Type *)SPI8_BASE)
-/** Peripheral SPI9 base address */
-#define SPI9_BASE (0x4009A000u)
-/** Peripheral SPI9 base pointer */
-#define SPI9 ((SPI_Type *)SPI9_BASE)
-/** Array initializer of SPI peripheral base addresses */
-#define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE, SPI9_BASE }
-/** Array initializer of SPI peripheral base pointers */
-#define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8, SPI9 }
-/** Interrupt vectors for the SPI peripheral type */
-#define SPI_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn }
-
-/*!
- * @}
- */ /* end of group SPI_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- SPIFI Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SPIFI_Peripheral_Access_Layer SPIFI Peripheral Access Layer
- * @{
- */
-
-/** SPIFI - Register Layout Typedef */
-typedef struct {
- __IO uint32_t CTRL; /**< SPIFI control register, offset: 0x0 */
- __IO uint32_t CMD; /**< SPIFI command register, offset: 0x4 */
- __IO uint32_t ADDR; /**< SPIFI address register, offset: 0x8 */
- __IO uint32_t IDATA; /**< SPIFI intermediate data register, offset: 0xC */
- __IO uint32_t CLIMIT; /**< SPIFI limit register, offset: 0x10 */
- __IO uint32_t DATA; /**< SPIFI data register, offset: 0x14 */
- __IO uint32_t MCMD; /**< SPIFI memory command register, offset: 0x18 */
- __IO uint32_t STAT; /**< SPIFI status register, offset: 0x1C */
-} SPIFI_Type;
-
-/* ----------------------------------------------------------------------------
- -- SPIFI Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SPIFI_Register_Masks SPIFI Register Masks
- * @{
- */
-
-/*! @name CTRL - SPIFI control register */
-#define SPIFI_CTRL_TIMEOUT_MASK (0xFFFFU)
-#define SPIFI_CTRL_TIMEOUT_SHIFT (0U)
-#define SPIFI_CTRL_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_TIMEOUT_SHIFT)) & SPIFI_CTRL_TIMEOUT_MASK)
-#define SPIFI_CTRL_CSHIGH_MASK (0xF0000U)
-#define SPIFI_CTRL_CSHIGH_SHIFT (16U)
-#define SPIFI_CTRL_CSHIGH(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_CSHIGH_SHIFT)) & SPIFI_CTRL_CSHIGH_MASK)
-#define SPIFI_CTRL_D_PRFTCH_DIS_MASK (0x200000U)
-#define SPIFI_CTRL_D_PRFTCH_DIS_SHIFT (21U)
-#define SPIFI_CTRL_D_PRFTCH_DIS(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_D_PRFTCH_DIS_SHIFT)) & SPIFI_CTRL_D_PRFTCH_DIS_MASK)
-#define SPIFI_CTRL_INTEN_MASK (0x400000U)
-#define SPIFI_CTRL_INTEN_SHIFT (22U)
-#define SPIFI_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_INTEN_SHIFT)) & SPIFI_CTRL_INTEN_MASK)
-#define SPIFI_CTRL_MODE3_MASK (0x800000U)
-#define SPIFI_CTRL_MODE3_SHIFT (23U)
-#define SPIFI_CTRL_MODE3(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_MODE3_SHIFT)) & SPIFI_CTRL_MODE3_MASK)
-#define SPIFI_CTRL_PRFTCH_DIS_MASK (0x8000000U)
-#define SPIFI_CTRL_PRFTCH_DIS_SHIFT (27U)
-#define SPIFI_CTRL_PRFTCH_DIS(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_PRFTCH_DIS_SHIFT)) & SPIFI_CTRL_PRFTCH_DIS_MASK)
-#define SPIFI_CTRL_DUAL_MASK (0x10000000U)
-#define SPIFI_CTRL_DUAL_SHIFT (28U)
-#define SPIFI_CTRL_DUAL(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_DUAL_SHIFT)) & SPIFI_CTRL_DUAL_MASK)
-#define SPIFI_CTRL_RFCLK_MASK (0x20000000U)
-#define SPIFI_CTRL_RFCLK_SHIFT (29U)
-#define SPIFI_CTRL_RFCLK(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_RFCLK_SHIFT)) & SPIFI_CTRL_RFCLK_MASK)
-#define SPIFI_CTRL_FBCLK_MASK (0x40000000U)
-#define SPIFI_CTRL_FBCLK_SHIFT (30U)
-#define SPIFI_CTRL_FBCLK(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_FBCLK_SHIFT)) & SPIFI_CTRL_FBCLK_MASK)
-#define SPIFI_CTRL_DMAEN_MASK (0x80000000U)
-#define SPIFI_CTRL_DMAEN_SHIFT (31U)
-#define SPIFI_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_DMAEN_SHIFT)) & SPIFI_CTRL_DMAEN_MASK)
-
-/*! @name CMD - SPIFI command register */
-#define SPIFI_CMD_DATALEN_MASK (0x3FFFU)
-#define SPIFI_CMD_DATALEN_SHIFT (0U)
-#define SPIFI_CMD_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_DATALEN_SHIFT)) & SPIFI_CMD_DATALEN_MASK)
-#define SPIFI_CMD_POLL_MASK (0x4000U)
-#define SPIFI_CMD_POLL_SHIFT (14U)
-#define SPIFI_CMD_POLL(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_POLL_SHIFT)) & SPIFI_CMD_POLL_MASK)
-#define SPIFI_CMD_DOUT_MASK (0x8000U)
-#define SPIFI_CMD_DOUT_SHIFT (15U)
-#define SPIFI_CMD_DOUT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_DOUT_SHIFT)) & SPIFI_CMD_DOUT_MASK)
-#define SPIFI_CMD_INTLEN_MASK (0x70000U)
-#define SPIFI_CMD_INTLEN_SHIFT (16U)
-#define SPIFI_CMD_INTLEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_INTLEN_SHIFT)) & SPIFI_CMD_INTLEN_MASK)
-#define SPIFI_CMD_FIELDFORM_MASK (0x180000U)
-#define SPIFI_CMD_FIELDFORM_SHIFT (19U)
-#define SPIFI_CMD_FIELDFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_FIELDFORM_SHIFT)) & SPIFI_CMD_FIELDFORM_MASK)
-#define SPIFI_CMD_FRAMEFORM_MASK (0xE00000U)
-#define SPIFI_CMD_FRAMEFORM_SHIFT (21U)
-#define SPIFI_CMD_FRAMEFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_FRAMEFORM_SHIFT)) & SPIFI_CMD_FRAMEFORM_MASK)
-#define SPIFI_CMD_OPCODE_MASK (0xFF000000U)
-#define SPIFI_CMD_OPCODE_SHIFT (24U)
-#define SPIFI_CMD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_OPCODE_SHIFT)) & SPIFI_CMD_OPCODE_MASK)
-
-/*! @name ADDR - SPIFI address register */
-#define SPIFI_ADDR_ADDRESS_MASK (0xFFFFFFFFU)
-#define SPIFI_ADDR_ADDRESS_SHIFT (0U)
-#define SPIFI_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_ADDR_ADDRESS_SHIFT)) & SPIFI_ADDR_ADDRESS_MASK)
-
-/*! @name IDATA - SPIFI intermediate data register */
-#define SPIFI_IDATA_IDATA_MASK (0xFFFFFFFFU)
-#define SPIFI_IDATA_IDATA_SHIFT (0U)
-#define SPIFI_IDATA_IDATA(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_IDATA_IDATA_SHIFT)) & SPIFI_IDATA_IDATA_MASK)
-
-/*! @name CLIMIT - SPIFI limit register */
-#define SPIFI_CLIMIT_CLIMIT_MASK (0xFFFFFFFFU)
-#define SPIFI_CLIMIT_CLIMIT_SHIFT (0U)
-#define SPIFI_CLIMIT_CLIMIT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CLIMIT_CLIMIT_SHIFT)) & SPIFI_CLIMIT_CLIMIT_MASK)
-
-/*! @name DATA - SPIFI data register */
-#define SPIFI_DATA_DATA_MASK (0xFFFFFFFFU)
-#define SPIFI_DATA_DATA_SHIFT (0U)
-#define SPIFI_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_DATA_DATA_SHIFT)) & SPIFI_DATA_DATA_MASK)
-
-/*! @name MCMD - SPIFI memory command register */
-#define SPIFI_MCMD_POLL_MASK (0x4000U)
-#define SPIFI_MCMD_POLL_SHIFT (14U)
-#define SPIFI_MCMD_POLL(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_POLL_SHIFT)) & SPIFI_MCMD_POLL_MASK)
-#define SPIFI_MCMD_DOUT_MASK (0x8000U)
-#define SPIFI_MCMD_DOUT_SHIFT (15U)
-#define SPIFI_MCMD_DOUT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_DOUT_SHIFT)) & SPIFI_MCMD_DOUT_MASK)
-#define SPIFI_MCMD_INTLEN_MASK (0x70000U)
-#define SPIFI_MCMD_INTLEN_SHIFT (16U)
-#define SPIFI_MCMD_INTLEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_INTLEN_SHIFT)) & SPIFI_MCMD_INTLEN_MASK)
-#define SPIFI_MCMD_FIELDFORM_MASK (0x180000U)
-#define SPIFI_MCMD_FIELDFORM_SHIFT (19U)
-#define SPIFI_MCMD_FIELDFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_FIELDFORM_SHIFT)) & SPIFI_MCMD_FIELDFORM_MASK)
-#define SPIFI_MCMD_FRAMEFORM_MASK (0xE00000U)
-#define SPIFI_MCMD_FRAMEFORM_SHIFT (21U)
-#define SPIFI_MCMD_FRAMEFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_FRAMEFORM_SHIFT)) & SPIFI_MCMD_FRAMEFORM_MASK)
-#define SPIFI_MCMD_OPCODE_MASK (0xFF000000U)
-#define SPIFI_MCMD_OPCODE_SHIFT (24U)
-#define SPIFI_MCMD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_OPCODE_SHIFT)) & SPIFI_MCMD_OPCODE_MASK)
-
-/*! @name STAT - SPIFI status register */
-#define SPIFI_STAT_MCINIT_MASK (0x1U)
-#define SPIFI_STAT_MCINIT_SHIFT (0U)
-#define SPIFI_STAT_MCINIT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_MCINIT_SHIFT)) & SPIFI_STAT_MCINIT_MASK)
-#define SPIFI_STAT_CMD_MASK (0x2U)
-#define SPIFI_STAT_CMD_SHIFT (1U)
-#define SPIFI_STAT_CMD(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_CMD_SHIFT)) & SPIFI_STAT_CMD_MASK)
-#define SPIFI_STAT_RESET_MASK (0x10U)
-#define SPIFI_STAT_RESET_SHIFT (4U)
-#define SPIFI_STAT_RESET(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_RESET_SHIFT)) & SPIFI_STAT_RESET_MASK)
-#define SPIFI_STAT_INTRQ_MASK (0x20U)
-#define SPIFI_STAT_INTRQ_SHIFT (5U)
-#define SPIFI_STAT_INTRQ(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_INTRQ_SHIFT)) & SPIFI_STAT_INTRQ_MASK)
-
-
-/*!
- * @}
- */ /* end of group SPIFI_Register_Masks */
-
-
-/* SPIFI - Peripheral instance base addresses */
-/** Peripheral SPIFI0 base address */
-#define SPIFI0_BASE (0x40080000u)
-/** Peripheral SPIFI0 base pointer */
-#define SPIFI0 ((SPIFI_Type *)SPIFI0_BASE)
-/** Array initializer of SPIFI peripheral base addresses */
-#define SPIFI_BASE_ADDRS { SPIFI0_BASE }
-/** Array initializer of SPIFI peripheral base pointers */
-#define SPIFI_BASE_PTRS { SPIFI0 }
-/** Interrupt vectors for the SPIFI peripheral type */
-#define SPIFI_IRQS { SPIFI0_IRQn }
-
-/*!
- * @}
- */ /* end of group SPIFI_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- SYSCON Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer
- * @{
- */
-
-/** SYSCON - Register Layout Typedef */
-typedef struct {
- uint8_t RESERVED_0[16];
- __IO uint32_t AHBMATPRIO; /**< AHB multilayer matrix priority control, offset: 0x10 */
- uint8_t RESERVED_1[44];
- __IO uint32_t SYSTCKCAL; /**< System tick counter calibration, offset: 0x40 */
- uint8_t RESERVED_2[4];
- __IO uint32_t NMISRC; /**< NMI Source Select, offset: 0x48 */
- __IO uint32_t ASYNCAPBCTRL; /**< Asynchronous APB Control, offset: 0x4C */
- uint8_t RESERVED_3[112];
- __I uint32_t PIOPORCAP[2]; /**< POR captured value of port n, array offset: 0xC0, array step: 0x4 */
- uint8_t RESERVED_4[8];
- __I uint32_t PIORESCAP[2]; /**< Reset captured value of port n, array offset: 0xD0, array step: 0x4 */
- uint8_t RESERVED_5[40];
- __IO uint32_t PRESETCTRL[3]; /**< Peripheral reset control n, array offset: 0x100, array step: 0x4 */
- uint8_t RESERVED_6[20];
- __O uint32_t PRESETCTRLSET[3]; /**< Set bits in PRESETCTRLn, array offset: 0x120, array step: 0x4 */
- uint8_t RESERVED_7[20];
- __O uint32_t PRESETCTRLCLR[3]; /**< Clear bits in PRESETCTRLn, array offset: 0x140, array step: 0x4 */
- uint8_t RESERVED_8[164];
- __IO uint32_t SYSRSTSTAT; /**< System reset status register, offset: 0x1F0 */
- uint8_t RESERVED_9[12];
- __IO uint32_t AHBCLKCTRL[3]; /**< AHB Clock control n, array offset: 0x200, array step: 0x4 */
- uint8_t RESERVED_10[20];
- __O uint32_t AHBCLKCTRLSET[3]; /**< Set bits in AHBCLKCTRLn, array offset: 0x220, array step: 0x4 */
- uint8_t RESERVED_11[20];
- __O uint32_t AHBCLKCTRLCLR[3]; /**< Clear bits in AHBCLKCTRLn, array offset: 0x240, array step: 0x4 */
- uint8_t RESERVED_12[52];
- __IO uint32_t MAINCLKSELA; /**< Main clock source select A, offset: 0x280 */
- __IO uint32_t MAINCLKSELB; /**< Main clock source select B, offset: 0x284 */
- __IO uint32_t CLKOUTSELA; /**< CLKOUT clock source select A, offset: 0x288 */
- uint8_t RESERVED_13[4];
- __IO uint32_t SYSPLLCLKSEL; /**< PLL clock source select, offset: 0x290 */
- uint8_t RESERVED_14[4];
- __IO uint32_t AUDPLLCLKSEL; /**< Audio PLL clock source select, offset: 0x298 */
- uint8_t RESERVED_15[4];
- __IO uint32_t SPIFICLKSEL; /**< SPIFI clock source select, offset: 0x2A0 */
- __IO uint32_t ADCCLKSEL; /**< ADC clock source select, offset: 0x2A4 */
- __IO uint32_t USB0CLKSEL; /**< USB0 clock source select, offset: 0x2A8 */
- __IO uint32_t USB1CLKSEL; /**< USB1 clock source select, offset: 0x2AC */
- __IO uint32_t FCLKSEL[10]; /**< Flexcomm 0 clock source select, array offset: 0x2B0, array step: 0x4 */
- uint8_t RESERVED_16[8];
- __IO uint32_t MCLKCLKSEL; /**< MCLK clock source select, offset: 0x2E0 */
- uint8_t RESERVED_17[4];
- __IO uint32_t FRGCLKSEL; /**< Fractional Rate Generator clock source select, offset: 0x2E8 */
- __IO uint32_t DMICCLKSEL; /**< Digital microphone (DMIC) subsystem clock select, offset: 0x2EC */
- __IO uint32_t SCTCLKSEL; /**< SCTimer/PWM clock source select, offset: 0x2F0 */
- __IO uint32_t LCDCLKSEL; /**< LCD clock source select, offset: 0x2F4 */
- __IO uint32_t SDIOCLKSEL; /**< SDIO clock source select, offset: 0x2F8 */
- uint8_t RESERVED_18[4];
- __IO uint32_t SYSTICKCLKDIV; /**< SYSTICK clock divider, offset: 0x300 */
- __IO uint32_t ARMTRACECLKDIV; /**< ARM Trace clock divider, offset: 0x304 */
- __IO uint32_t CAN0CLKDIV; /**< MCAN0 clock divider, offset: 0x308 */
- __IO uint32_t CAN1CLKDIV; /**< MCAN1 clock divider, offset: 0x30C */
- __IO uint32_t SC0CLKDIV; /**< Smartcard0 clock divider, offset: 0x310 */
- __IO uint32_t SC1CLKDIV; /**< Smartcard1 clock divider, offset: 0x314 */
- uint8_t RESERVED_19[104];
- __IO uint32_t AHBCLKDIV; /**< AHB clock divider, offset: 0x380 */
- __IO uint32_t CLKOUTDIV; /**< CLKOUT clock divider, offset: 0x384 */
- __IO uint32_t FROHFCLKDIV; /**< FROHF clock divider, offset: 0x388 */
- uint8_t RESERVED_20[4];
- __IO uint32_t SPIFICLKDIV; /**< SPIFI clock divider, offset: 0x390 */
- __IO uint32_t ADCCLKDIV; /**< ADC clock divider, offset: 0x394 */
- __IO uint32_t USB0CLKDIV; /**< USB0 clock divider, offset: 0x398 */
- __IO uint32_t USB1CLKDIV; /**< USB1 clock divider, offset: 0x39C */
- __IO uint32_t FRGCTRL; /**< Fractional rate divider, offset: 0x3A0 */
- uint8_t RESERVED_21[4];
- __IO uint32_t DMICCLKDIV; /**< DMIC clock divider, offset: 0x3A8 */
- __IO uint32_t MCLKDIV; /**< I2S MCLK clock divider, offset: 0x3AC */
- __IO uint32_t LCDCLKDIV; /**< LCD clock divider, offset: 0x3B0 */
- __IO uint32_t SCTCLKDIV; /**< SCT/PWM clock divider, offset: 0x3B4 */
- __IO uint32_t EMCCLKDIV; /**< EMC clock divider, offset: 0x3B8 */
- __IO uint32_t SDIOCLKDIV; /**< SDIO clock divider, offset: 0x3BC */
- uint8_t RESERVED_22[64];
- __IO uint32_t FLASHCFG; /**< Flash wait states configuration, offset: 0x400 */
- uint8_t RESERVED_23[8];
- __IO uint32_t USB0CLKCTRL; /**< USB0 clock control, offset: 0x40C */
- __IO uint32_t USB0CLKSTAT; /**< USB0 clock status, offset: 0x410 */
- uint8_t RESERVED_24[4];
- __IO uint32_t FREQMECTRL; /**< Frequency measure register, offset: 0x418 */
- uint8_t RESERVED_25[4];
- __IO uint32_t MCLKIO; /**< MCLK input/output control, offset: 0x420 */
- __IO uint32_t USB1CLKCTRL; /**< USB1 clock control, offset: 0x424 */
- __IO uint32_t USB1CLKSTAT; /**< USB1 clock status, offset: 0x428 */
- uint8_t RESERVED_26[24];
- __IO uint32_t EMCSYSCTRL; /**< EMC system control, offset: 0x444 */
- __IO uint32_t EMCDLYCTRL; /**< EMC clock delay control, offset: 0x448 */
- __IO uint32_t EMCDLYCAL; /**< EMC delay chain calibration control, offset: 0x44C */
- __IO uint32_t ETHPHYSEL; /**< Ethernet PHY Selection, offset: 0x450 */
- __IO uint32_t ETHSBDCTRL; /**< Ethernet SBD flow control, offset: 0x454 */
- uint8_t RESERVED_27[8];
- __IO uint32_t SDIOCLKCTRL; /**< SDIO CCLKIN phase and delay control, offset: 0x460 */
- uint8_t RESERVED_28[156];
- __IO uint32_t FROCTRL; /**< FRO oscillator control, offset: 0x500 */
- __IO uint32_t SYSOSCCTRL; /**< System oscillator control, offset: 0x504 */
- __IO uint32_t WDTOSCCTRL; /**< Watchdog oscillator control, offset: 0x508 */
- __IO uint32_t RTCOSCCTRL; /**< RTC oscillator 32 kHz output control, offset: 0x50C */
- uint8_t RESERVED_29[12];
- __IO uint32_t USBPLLCTRL; /**< USB PLL control, offset: 0x51C */
- __IO uint32_t USBPLLSTAT; /**< USB PLL status, offset: 0x520 */
- uint8_t RESERVED_30[92];
- __IO uint32_t SYSPLLCTRL; /**< System PLL control, offset: 0x580 */
- __IO uint32_t SYSPLLSTAT; /**< PLL status, offset: 0x584 */
- __IO uint32_t SYSPLLNDEC; /**< PLL N divider, offset: 0x588 */
- __IO uint32_t SYSPLLPDEC; /**< PLL P divider, offset: 0x58C */
- __IO uint32_t SYSPLLMDEC; /**< System PLL M divider, offset: 0x590 */
- uint8_t RESERVED_31[12];
- __IO uint32_t AUDPLLCTRL; /**< Audio PLL control, offset: 0x5A0 */
- __IO uint32_t AUDPLLSTAT; /**< Audio PLL status, offset: 0x5A4 */
- __IO uint32_t AUDPLLNDEC; /**< Audio PLL N divider, offset: 0x5A8 */
- __IO uint32_t AUDPLLPDEC; /**< Audio PLL P divider, offset: 0x5AC */
- __IO uint32_t AUDPLLMDEC; /**< Audio PLL M divider, offset: 0x5B0 */
- __IO uint32_t AUDPLLFRAC; /**< Audio PLL fractional divider control, offset: 0x5B4 */
- uint8_t RESERVED_32[72];
- __IO uint32_t PDSLEEPCFG[2]; /**< Power configuration register 0, array offset: 0x600, array step: 0x4 */
- uint8_t RESERVED_33[8];
- __IO uint32_t PDRUNCFG[2]; /**< Power configuration register 0, array offset: 0x610, array step: 0x4 */
- uint8_t RESERVED_34[8];
- __IO uint32_t PDRUNCFGSET[2]; /**< Set bits in PDRUNCFG0, array offset: 0x620, array step: 0x4 */
- uint8_t RESERVED_35[8];
- __IO uint32_t PDRUNCFGCLR[2]; /**< Clear bits in PDRUNCFG0, array offset: 0x630, array step: 0x4 */
- uint8_t RESERVED_36[72];
- __IO uint32_t STARTER[2]; /**< Start logic 0 wake-up enable register, array offset: 0x680, array step: 0x4 */
- uint8_t RESERVED_37[24];
- __O uint32_t STARTERSET[2]; /**< Set bits in STARTER, array offset: 0x6A0, array step: 0x4 */
- uint8_t RESERVED_38[24];
- __O uint32_t STARTERCLR[2]; /**< Clear bits in STARTER0, array offset: 0x6C0, array step: 0x4 */
- uint8_t RESERVED_39[184];
- __IO uint32_t HWWAKE; /**< Configures special cases of hardware wake-up, offset: 0x780 */
- uint8_t RESERVED_40[1664];
- __IO uint32_t AUTOCGOR; /**< Auto Clock-Gate Override Register, offset: 0xE04 */
- uint8_t RESERVED_41[492];
- __I uint32_t JTAGIDCODE; /**< JTAG ID code register, offset: 0xFF4 */
- __I uint32_t DEVICE_ID0; /**< Part ID register, offset: 0xFF8 */
- __I uint32_t DEVICE_ID1; /**< Boot ROM and die revision register, offset: 0xFFC */
- uint8_t RESERVED_42[127044];
- __IO uint32_t BODCTRL; /**< Brown-Out Detect control, offset: 0x20044 */
-} SYSCON_Type;
-
-/* ----------------------------------------------------------------------------
- -- SYSCON Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SYSCON_Register_Masks SYSCON Register Masks
- * @{
- */
-
-/*! @name AHBMATPRIO - AHB multilayer matrix priority control */
-#define SYSCON_AHBMATPRIO_PRI_ICODE_MASK (0x3U)
-#define SYSCON_AHBMATPRIO_PRI_ICODE_SHIFT (0U)
-#define SYSCON_AHBMATPRIO_PRI_ICODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_ICODE_SHIFT)) & SYSCON_AHBMATPRIO_PRI_ICODE_MASK)
-#define SYSCON_AHBMATPRIO_PRI_DCODE_MASK (0xCU)
-#define SYSCON_AHBMATPRIO_PRI_DCODE_SHIFT (2U)
-#define SYSCON_AHBMATPRIO_PRI_DCODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_DCODE_SHIFT)) & SYSCON_AHBMATPRIO_PRI_DCODE_MASK)
-#define SYSCON_AHBMATPRIO_PRI_SYS_MASK (0x30U)
-#define SYSCON_AHBMATPRIO_PRI_SYS_SHIFT (4U)
-#define SYSCON_AHBMATPRIO_PRI_SYS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SYS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SYS_MASK)
-#define SYSCON_AHBMATPRIO_PRI_DMA_MASK (0x3C0U)
-#define SYSCON_AHBMATPRIO_PRI_DMA_SHIFT (6U)
-#define SYSCON_AHBMATPRIO_PRI_DMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_DMA_SHIFT)) & SYSCON_AHBMATPRIO_PRI_DMA_MASK)
-#define SYSCON_AHBMATPRIO_PRI_ETH_MASK (0xC00U)
-#define SYSCON_AHBMATPRIO_PRI_ETH_SHIFT (10U)
-#define SYSCON_AHBMATPRIO_PRI_ETH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_ETH_SHIFT)) & SYSCON_AHBMATPRIO_PRI_ETH_MASK)
-#define SYSCON_AHBMATPRIO_PRI_LCD_MASK (0x3000U)
-#define SYSCON_AHBMATPRIO_PRI_LCD_SHIFT (12U)
-#define SYSCON_AHBMATPRIO_PRI_LCD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_LCD_SHIFT)) & SYSCON_AHBMATPRIO_PRI_LCD_MASK)
-#define SYSCON_AHBMATPRIO_PRI_USB0_MASK (0xC000U)
-#define SYSCON_AHBMATPRIO_PRI_USB0_SHIFT (14U)
-#define SYSCON_AHBMATPRIO_PRI_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB0_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB0_MASK)
-#define SYSCON_AHBMATPRIO_PRI_USB1_MASK (0x30000U)
-#define SYSCON_AHBMATPRIO_PRI_USB1_SHIFT (16U)
-#define SYSCON_AHBMATPRIO_PRI_USB1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB1_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB1_MASK)
-#define SYSCON_AHBMATPRIO_PRI_SDIO_MASK (0xC0000U)
-#define SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT (18U)
-#define SYSCON_AHBMATPRIO_PRI_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDIO_MASK)
-#define SYSCON_AHBMATPRIO_PRI_MCAN1_MASK (0x300000U)
-#define SYSCON_AHBMATPRIO_PRI_MCAN1_SHIFT (20U)
-#define SYSCON_AHBMATPRIO_PRI_MCAN1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_MCAN1_SHIFT)) & SYSCON_AHBMATPRIO_PRI_MCAN1_MASK)
-#define SYSCON_AHBMATPRIO_PRI_MCAN2_MASK (0xC00000U)
-#define SYSCON_AHBMATPRIO_PRI_MCAN2_SHIFT (22U)
-#define SYSCON_AHBMATPRIO_PRI_MCAN2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_MCAN2_SHIFT)) & SYSCON_AHBMATPRIO_PRI_MCAN2_MASK)
-#define SYSCON_AHBMATPRIO_PRI_SHA_MASK (0x3000000U)
-#define SYSCON_AHBMATPRIO_PRI_SHA_SHIFT (24U)
-#define SYSCON_AHBMATPRIO_PRI_SHA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SHA_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SHA_MASK)
-
-/*! @name SYSTCKCAL - System tick counter calibration */
-#define SYSCON_SYSTCKCAL_CAL_MASK (0xFFFFFFU)
-#define SYSCON_SYSTCKCAL_CAL_SHIFT (0U)
-#define SYSCON_SYSTCKCAL_CAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_CAL_SHIFT)) & SYSCON_SYSTCKCAL_CAL_MASK)
-#define SYSCON_SYSTCKCAL_SKEW_MASK (0x1000000U)
-#define SYSCON_SYSTCKCAL_SKEW_SHIFT (24U)
-#define SYSCON_SYSTCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_SKEW_SHIFT)) & SYSCON_SYSTCKCAL_SKEW_MASK)
-#define SYSCON_SYSTCKCAL_NOREF_MASK (0x2000000U)
-#define SYSCON_SYSTCKCAL_NOREF_SHIFT (25U)
-#define SYSCON_SYSTCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_NOREF_SHIFT)) & SYSCON_SYSTCKCAL_NOREF_MASK)
-
-/*! @name NMISRC - NMI Source Select */
-#define SYSCON_NMISRC_IRQM4_MASK (0x3FU)
-#define SYSCON_NMISRC_IRQM4_SHIFT (0U)
-#define SYSCON_NMISRC_IRQM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQM4_SHIFT)) & SYSCON_NMISRC_IRQM4_MASK)
-#define SYSCON_NMISRC_NMIENM4_MASK (0x80000000U)
-#define SYSCON_NMISRC_NMIENM4_SHIFT (31U)
-#define SYSCON_NMISRC_NMIENM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENM4_SHIFT)) & SYSCON_NMISRC_NMIENM4_MASK)
-
-/*! @name ASYNCAPBCTRL - Asynchronous APB Control */
-#define SYSCON_ASYNCAPBCTRL_ENABLE_MASK (0x1U)
-#define SYSCON_ASYNCAPBCTRL_ENABLE_SHIFT (0U)
-#define SYSCON_ASYNCAPBCTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ASYNCAPBCTRL_ENABLE_SHIFT)) & SYSCON_ASYNCAPBCTRL_ENABLE_MASK)
-
-/*! @name PIOPORCAP - POR captured value of port n */
-#define SYSCON_PIOPORCAP_PIOPORCAP_MASK (0xFFFFFFFFU)
-#define SYSCON_PIOPORCAP_PIOPORCAP_SHIFT (0U)
-#define SYSCON_PIOPORCAP_PIOPORCAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PIOPORCAP_PIOPORCAP_SHIFT)) & SYSCON_PIOPORCAP_PIOPORCAP_MASK)
-
-/* The count of SYSCON_PIOPORCAP */
-#define SYSCON_PIOPORCAP_COUNT (2U)
-
-/*! @name PIORESCAP - Reset captured value of port n */
-#define SYSCON_PIORESCAP_PIORESCAP_MASK (0xFFFFFFFFU)
-#define SYSCON_PIORESCAP_PIORESCAP_SHIFT (0U)
-#define SYSCON_PIORESCAP_PIORESCAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PIORESCAP_PIORESCAP_SHIFT)) & SYSCON_PIORESCAP_PIORESCAP_MASK)
-
-/* The count of SYSCON_PIORESCAP */
-#define SYSCON_PIORESCAP_COUNT (2U)
-
-/*! @name PRESETCTRL - Peripheral reset control n */
-#define SYSCON_PRESETCTRL_MRT_RST_MASK (0x1U)
-#define SYSCON_PRESETCTRL_MRT_RST_SHIFT (0U)
-#define SYSCON_PRESETCTRL_MRT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MRT_RST_SHIFT)) & SYSCON_PRESETCTRL_MRT_RST_MASK)
-#define SYSCON_PRESETCTRL_SCT0_RST_MASK (0x4U)
-#define SYSCON_PRESETCTRL_SCT0_RST_SHIFT (2U)
-#define SYSCON_PRESETCTRL_SCT0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SCT0_RST_SHIFT)) & SYSCON_PRESETCTRL_SCT0_RST_MASK)
-#define SYSCON_PRESETCTRL_LCD_RST_MASK (0x4U)
-#define SYSCON_PRESETCTRL_LCD_RST_SHIFT (2U)
-#define SYSCON_PRESETCTRL_LCD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_LCD_RST_SHIFT)) & SYSCON_PRESETCTRL_LCD_RST_MASK)
-#define SYSCON_PRESETCTRL_SDIO_RST_MASK (0x8U)
-#define SYSCON_PRESETCTRL_SDIO_RST_SHIFT (3U)
-#define SYSCON_PRESETCTRL_SDIO_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SDIO_RST_SHIFT)) & SYSCON_PRESETCTRL_SDIO_RST_MASK)
-#define SYSCON_PRESETCTRL_USB1H_RST_MASK (0x10U)
-#define SYSCON_PRESETCTRL_USB1H_RST_SHIFT (4U)
-#define SYSCON_PRESETCTRL_USB1H_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB1H_RST_SHIFT)) & SYSCON_PRESETCTRL_USB1H_RST_MASK)
-#define SYSCON_PRESETCTRL_USB1D_RST_MASK (0x20U)
-#define SYSCON_PRESETCTRL_USB1D_RST_SHIFT (5U)
-#define SYSCON_PRESETCTRL_USB1D_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB1D_RST_SHIFT)) & SYSCON_PRESETCTRL_USB1D_RST_MASK)
-#define SYSCON_PRESETCTRL_USB1RAM_RST_MASK (0x40U)
-#define SYSCON_PRESETCTRL_USB1RAM_RST_SHIFT (6U)
-#define SYSCON_PRESETCTRL_USB1RAM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB1RAM_RST_SHIFT)) & SYSCON_PRESETCTRL_USB1RAM_RST_MASK)
-#define SYSCON_PRESETCTRL_EMC_RESET_MASK (0x80U)
-#define SYSCON_PRESETCTRL_EMC_RESET_SHIFT (7U)
-#define SYSCON_PRESETCTRL_EMC_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_EMC_RESET_SHIFT)) & SYSCON_PRESETCTRL_EMC_RESET_MASK)
-#define SYSCON_PRESETCTRL_FLASH_RST_MASK (0x80U)
-#define SYSCON_PRESETCTRL_FLASH_RST_SHIFT (7U)
-#define SYSCON_PRESETCTRL_FLASH_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FLASH_RST_SHIFT)) & SYSCON_PRESETCTRL_FLASH_RST_MASK)
-#define SYSCON_PRESETCTRL_MCAN0_RST_MASK (0x80U)
-#define SYSCON_PRESETCTRL_MCAN0_RST_SHIFT (7U)
-#define SYSCON_PRESETCTRL_MCAN0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MCAN0_RST_SHIFT)) & SYSCON_PRESETCTRL_MCAN0_RST_MASK)
-#define SYSCON_PRESETCTRL_FMC_RST_MASK (0x100U)
-#define SYSCON_PRESETCTRL_FMC_RST_SHIFT (8U)
-#define SYSCON_PRESETCTRL_FMC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FMC_RST_SHIFT)) & SYSCON_PRESETCTRL_FMC_RST_MASK)
-#define SYSCON_PRESETCTRL_ETH_RST_MASK (0x100U)
-#define SYSCON_PRESETCTRL_ETH_RST_SHIFT (8U)
-#define SYSCON_PRESETCTRL_ETH_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_ETH_RST_SHIFT)) & SYSCON_PRESETCTRL_ETH_RST_MASK)
-#define SYSCON_PRESETCTRL_MCAN1_RST_MASK (0x100U)
-#define SYSCON_PRESETCTRL_MCAN1_RST_SHIFT (8U)
-#define SYSCON_PRESETCTRL_MCAN1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MCAN1_RST_SHIFT)) & SYSCON_PRESETCTRL_MCAN1_RST_MASK)
-#define SYSCON_PRESETCTRL_GPIO4_RST_MASK (0x200U)
-#define SYSCON_PRESETCTRL_GPIO4_RST_SHIFT (9U)
-#define SYSCON_PRESETCTRL_GPIO4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO4_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO4_RST_MASK)
-#define SYSCON_PRESETCTRL_EEPROM_RST_MASK (0x200U)
-#define SYSCON_PRESETCTRL_EEPROM_RST_SHIFT (9U)
-#define SYSCON_PRESETCTRL_EEPROM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_EEPROM_RST_SHIFT)) & SYSCON_PRESETCTRL_EEPROM_RST_MASK)
-#define SYSCON_PRESETCTRL_GPIO5_RST_MASK (0x400U)
-#define SYSCON_PRESETCTRL_GPIO5_RST_SHIFT (10U)
-#define SYSCON_PRESETCTRL_GPIO5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO5_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO5_RST_MASK)
-#define SYSCON_PRESETCTRL_UTICK_RST_MASK (0x400U)
-#define SYSCON_PRESETCTRL_UTICK_RST_SHIFT (10U)
-#define SYSCON_PRESETCTRL_UTICK_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_UTICK_RST_SHIFT)) & SYSCON_PRESETCTRL_UTICK_RST_MASK)
-#define SYSCON_PRESETCTRL_SPIFI_RST_MASK (0x400U)
-#define SYSCON_PRESETCTRL_SPIFI_RST_SHIFT (10U)
-#define SYSCON_PRESETCTRL_SPIFI_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SPIFI_RST_SHIFT)) & SYSCON_PRESETCTRL_SPIFI_RST_MASK)
-#define SYSCON_PRESETCTRL_AES_RST_MASK (0x800U)
-#define SYSCON_PRESETCTRL_AES_RST_SHIFT (11U)
-#define SYSCON_PRESETCTRL_AES_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_AES_RST_SHIFT)) & SYSCON_PRESETCTRL_AES_RST_MASK)
-#define SYSCON_PRESETCTRL_MUX_RST_MASK (0x800U)
-#define SYSCON_PRESETCTRL_MUX_RST_SHIFT (11U)
-#define SYSCON_PRESETCTRL_MUX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MUX_RST_SHIFT)) & SYSCON_PRESETCTRL_MUX_RST_MASK)
-#define SYSCON_PRESETCTRL_FC0_RST_MASK (0x800U)
-#define SYSCON_PRESETCTRL_FC0_RST_SHIFT (11U)
-#define SYSCON_PRESETCTRL_FC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL_FC0_RST_MASK)
-#define SYSCON_PRESETCTRL_OTP_RST_MASK (0x1000U)
-#define SYSCON_PRESETCTRL_OTP_RST_SHIFT (12U)
-#define SYSCON_PRESETCTRL_OTP_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_OTP_RST_SHIFT)) & SYSCON_PRESETCTRL_OTP_RST_MASK)
-#define SYSCON_PRESETCTRL_FC1_RST_MASK (0x1000U)
-#define SYSCON_PRESETCTRL_FC1_RST_SHIFT (12U)
-#define SYSCON_PRESETCTRL_FC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL_FC1_RST_MASK)
-#define SYSCON_PRESETCTRL_IOCON_RST_MASK (0x2000U)
-#define SYSCON_PRESETCTRL_IOCON_RST_SHIFT (13U)
-#define SYSCON_PRESETCTRL_IOCON_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_IOCON_RST_SHIFT)) & SYSCON_PRESETCTRL_IOCON_RST_MASK)
-#define SYSCON_PRESETCTRL_RNG_RST_MASK (0x2000U)
-#define SYSCON_PRESETCTRL_RNG_RST_SHIFT (13U)
-#define SYSCON_PRESETCTRL_RNG_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_RNG_RST_SHIFT)) & SYSCON_PRESETCTRL_RNG_RST_MASK)
-#define SYSCON_PRESETCTRL_FC2_RST_MASK (0x2000U)
-#define SYSCON_PRESETCTRL_FC2_RST_SHIFT (13U)
-#define SYSCON_PRESETCTRL_FC2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC2_RST_SHIFT)) & SYSCON_PRESETCTRL_FC2_RST_MASK)
-#define SYSCON_PRESETCTRL_FC8_RST_MASK (0x4000U)
-#define SYSCON_PRESETCTRL_FC8_RST_SHIFT (14U)
-#define SYSCON_PRESETCTRL_FC8_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC8_RST_SHIFT)) & SYSCON_PRESETCTRL_FC8_RST_MASK)
-#define SYSCON_PRESETCTRL_FC3_RST_MASK (0x4000U)
-#define SYSCON_PRESETCTRL_FC3_RST_SHIFT (14U)
-#define SYSCON_PRESETCTRL_FC3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC3_RST_SHIFT)) & SYSCON_PRESETCTRL_FC3_RST_MASK)
-#define SYSCON_PRESETCTRL_GPIO0_RST_MASK (0x4000U)
-#define SYSCON_PRESETCTRL_GPIO0_RST_SHIFT (14U)
-#define SYSCON_PRESETCTRL_GPIO0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO0_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO0_RST_MASK)
-#define SYSCON_PRESETCTRL_GPIO1_RST_MASK (0x8000U)
-#define SYSCON_PRESETCTRL_GPIO1_RST_SHIFT (15U)
-#define SYSCON_PRESETCTRL_GPIO1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO1_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO1_RST_MASK)
-#define SYSCON_PRESETCTRL_FC9_RST_MASK (0x8000U)
-#define SYSCON_PRESETCTRL_FC9_RST_SHIFT (15U)
-#define SYSCON_PRESETCTRL_FC9_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC9_RST_SHIFT)) & SYSCON_PRESETCTRL_FC9_RST_MASK)
-#define SYSCON_PRESETCTRL_FC4_RST_MASK (0x8000U)
-#define SYSCON_PRESETCTRL_FC4_RST_SHIFT (15U)
-#define SYSCON_PRESETCTRL_FC4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC4_RST_SHIFT)) & SYSCON_PRESETCTRL_FC4_RST_MASK)
-#define SYSCON_PRESETCTRL_USB0HMR_RST_MASK (0x10000U)
-#define SYSCON_PRESETCTRL_USB0HMR_RST_SHIFT (16U)
-#define SYSCON_PRESETCTRL_USB0HMR_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB0HMR_RST_SHIFT)) & SYSCON_PRESETCTRL_USB0HMR_RST_MASK)
-#define SYSCON_PRESETCTRL_GPIO2_RST_MASK (0x10000U)
-#define SYSCON_PRESETCTRL_GPIO2_RST_SHIFT (16U)
-#define SYSCON_PRESETCTRL_GPIO2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO2_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO2_RST_MASK)
-#define SYSCON_PRESETCTRL_FC5_RST_MASK (0x10000U)
-#define SYSCON_PRESETCTRL_FC5_RST_SHIFT (16U)
-#define SYSCON_PRESETCTRL_FC5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC5_RST_SHIFT)) & SYSCON_PRESETCTRL_FC5_RST_MASK)
-#define SYSCON_PRESETCTRL_GPIO3_RST_MASK (0x20000U)
-#define SYSCON_PRESETCTRL_GPIO3_RST_SHIFT (17U)
-#define SYSCON_PRESETCTRL_GPIO3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO3_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO3_RST_MASK)
-#define SYSCON_PRESETCTRL_FC6_RST_MASK (0x20000U)
-#define SYSCON_PRESETCTRL_FC6_RST_SHIFT (17U)
-#define SYSCON_PRESETCTRL_FC6_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC6_RST_SHIFT)) & SYSCON_PRESETCTRL_FC6_RST_MASK)
-#define SYSCON_PRESETCTRL_USB0HSL_RST_MASK (0x20000U)
-#define SYSCON_PRESETCTRL_USB0HSL_RST_SHIFT (17U)
-#define SYSCON_PRESETCTRL_USB0HSL_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB0HSL_RST_SHIFT)) & SYSCON_PRESETCTRL_USB0HSL_RST_MASK)
-#define SYSCON_PRESETCTRL_FC7_RST_MASK (0x40000U)
-#define SYSCON_PRESETCTRL_FC7_RST_SHIFT (18U)
-#define SYSCON_PRESETCTRL_FC7_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC7_RST_SHIFT)) & SYSCON_PRESETCTRL_FC7_RST_MASK)
-#define SYSCON_PRESETCTRL_SHA_RST_MASK (0x40000U)
-#define SYSCON_PRESETCTRL_SHA_RST_SHIFT (18U)
-#define SYSCON_PRESETCTRL_SHA_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SHA_RST_SHIFT)) & SYSCON_PRESETCTRL_SHA_RST_MASK)
-#define SYSCON_PRESETCTRL_PINT_RST_MASK (0x40000U)
-#define SYSCON_PRESETCTRL_PINT_RST_SHIFT (18U)
-#define SYSCON_PRESETCTRL_PINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL_PINT_RST_MASK)
-#define SYSCON_PRESETCTRL_DMIC_RST_MASK (0x80000U)
-#define SYSCON_PRESETCTRL_DMIC_RST_SHIFT (19U)
-#define SYSCON_PRESETCTRL_DMIC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_DMIC_RST_SHIFT)) & SYSCON_PRESETCTRL_DMIC_RST_MASK)
-#define SYSCON_PRESETCTRL_SC0_RST_MASK (0x80000U)
-#define SYSCON_PRESETCTRL_SC0_RST_SHIFT (19U)
-#define SYSCON_PRESETCTRL_SC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SC0_RST_SHIFT)) & SYSCON_PRESETCTRL_SC0_RST_MASK)
-#define SYSCON_PRESETCTRL_GINT_RST_MASK (0x80000U)
-#define SYSCON_PRESETCTRL_GINT_RST_SHIFT (19U)
-#define SYSCON_PRESETCTRL_GINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GINT_RST_SHIFT)) & SYSCON_PRESETCTRL_GINT_RST_MASK)
-#define SYSCON_PRESETCTRL_SC1_RST_MASK (0x100000U)
-#define SYSCON_PRESETCTRL_SC1_RST_SHIFT (20U)
-#define SYSCON_PRESETCTRL_SC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SC1_RST_SHIFT)) & SYSCON_PRESETCTRL_SC1_RST_MASK)
-#define SYSCON_PRESETCTRL_DMA0_RST_MASK (0x100000U)
-#define SYSCON_PRESETCTRL_DMA0_RST_SHIFT (20U)
-#define SYSCON_PRESETCTRL_DMA0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_DMA0_RST_SHIFT)) & SYSCON_PRESETCTRL_DMA0_RST_MASK)
-#define SYSCON_PRESETCTRL_CRC_RST_MASK (0x200000U)
-#define SYSCON_PRESETCTRL_CRC_RST_SHIFT (21U)
-#define SYSCON_PRESETCTRL_CRC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CRC_RST_SHIFT)) & SYSCON_PRESETCTRL_CRC_RST_MASK)
-#define SYSCON_PRESETCTRL_CTIMER2_RST_MASK (0x400000U)
-#define SYSCON_PRESETCTRL_CTIMER2_RST_SHIFT (22U)
-#define SYSCON_PRESETCTRL_CTIMER2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER2_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER2_RST_MASK)
-#define SYSCON_PRESETCTRL_WWDT_RST_MASK (0x400000U)
-#define SYSCON_PRESETCTRL_WWDT_RST_SHIFT (22U)
-#define SYSCON_PRESETCTRL_WWDT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_WWDT_RST_SHIFT)) & SYSCON_PRESETCTRL_WWDT_RST_MASK)
-#define SYSCON_PRESETCTRL_USB0D_RST_MASK (0x2000000U)
-#define SYSCON_PRESETCTRL_USB0D_RST_SHIFT (25U)
-#define SYSCON_PRESETCTRL_USB0D_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB0D_RST_SHIFT)) & SYSCON_PRESETCTRL_USB0D_RST_MASK)
-#define SYSCON_PRESETCTRL_CTIMER0_RST_MASK (0x4000000U)
-#define SYSCON_PRESETCTRL_CTIMER0_RST_SHIFT (26U)
-#define SYSCON_PRESETCTRL_CTIMER0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER0_RST_MASK)
-#define SYSCON_PRESETCTRL_ADC0_RST_MASK (0x8000000U)
-#define SYSCON_PRESETCTRL_ADC0_RST_SHIFT (27U)
-#define SYSCON_PRESETCTRL_ADC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_ADC0_RST_SHIFT)) & SYSCON_PRESETCTRL_ADC0_RST_MASK)
-#define SYSCON_PRESETCTRL_CTIMER1_RST_MASK (0x8000000U)
-#define SYSCON_PRESETCTRL_CTIMER1_RST_SHIFT (27U)
-#define SYSCON_PRESETCTRL_CTIMER1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER1_RST_MASK)
-
-/* The count of SYSCON_PRESETCTRL */
-#define SYSCON_PRESETCTRL_COUNT (3U)
-
-/*! @name PRESETCTRLSET - Set bits in PRESETCTRLn */
-#define SYSCON_PRESETCTRLSET_RST_SET_MASK (0xFFFFFFFFU)
-#define SYSCON_PRESETCTRLSET_RST_SET_SHIFT (0U)
-#define SYSCON_PRESETCTRLSET_RST_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_RST_SET_SHIFT)) & SYSCON_PRESETCTRLSET_RST_SET_MASK)
-
-/* The count of SYSCON_PRESETCTRLSET */
-#define SYSCON_PRESETCTRLSET_COUNT (3U)
-
-/*! @name PRESETCTRLCLR - Clear bits in PRESETCTRLn */
-#define SYSCON_PRESETCTRLCLR_RST_CLR_MASK (0xFFFFFFFFU)
-#define SYSCON_PRESETCTRLCLR_RST_CLR_SHIFT (0U)
-#define SYSCON_PRESETCTRLCLR_RST_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_RST_CLR_SHIFT)) & SYSCON_PRESETCTRLCLR_RST_CLR_MASK)
-
-/* The count of SYSCON_PRESETCTRLCLR */
-#define SYSCON_PRESETCTRLCLR_COUNT (3U)
-
-/*! @name SYSRSTSTAT - System reset status register */
-#define SYSCON_SYSRSTSTAT_POR_MASK (0x1U)
-#define SYSCON_SYSRSTSTAT_POR_SHIFT (0U)
-#define SYSCON_SYSRSTSTAT_POR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_POR_SHIFT)) & SYSCON_SYSRSTSTAT_POR_MASK)
-#define SYSCON_SYSRSTSTAT_EXTRST_MASK (0x2U)
-#define SYSCON_SYSRSTSTAT_EXTRST_SHIFT (1U)
-#define SYSCON_SYSRSTSTAT_EXTRST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_EXTRST_SHIFT)) & SYSCON_SYSRSTSTAT_EXTRST_MASK)
-#define SYSCON_SYSRSTSTAT_WDT_MASK (0x4U)
-#define SYSCON_SYSRSTSTAT_WDT_SHIFT (2U)
-#define SYSCON_SYSRSTSTAT_WDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_WDT_SHIFT)) & SYSCON_SYSRSTSTAT_WDT_MASK)
-#define SYSCON_SYSRSTSTAT_BOD_MASK (0x8U)
-#define SYSCON_SYSRSTSTAT_BOD_SHIFT (3U)
-#define SYSCON_SYSRSTSTAT_BOD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_BOD_SHIFT)) & SYSCON_SYSRSTSTAT_BOD_MASK)
-#define SYSCON_SYSRSTSTAT_SYSRST_MASK (0x10U)
-#define SYSCON_SYSRSTSTAT_SYSRST_SHIFT (4U)
-#define SYSCON_SYSRSTSTAT_SYSRST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_SYSRST_SHIFT)) & SYSCON_SYSRSTSTAT_SYSRST_MASK)
-
-/*! @name AHBCLKCTRL - AHB Clock control n */
-#define SYSCON_AHBCLKCTRL_MRT_MASK (0x1U)
-#define SYSCON_AHBCLKCTRL_MRT_SHIFT (0U)
-#define SYSCON_AHBCLKCTRL_MRT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MRT_SHIFT)) & SYSCON_AHBCLKCTRL_MRT_MASK)
-#define SYSCON_AHBCLKCTRL_RIT_MASK (0x2U)
-#define SYSCON_AHBCLKCTRL_RIT_SHIFT (1U)
-#define SYSCON_AHBCLKCTRL_RIT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_RIT_SHIFT)) & SYSCON_AHBCLKCTRL_RIT_MASK)
-#define SYSCON_AHBCLKCTRL_ROM_MASK (0x2U)
-#define SYSCON_AHBCLKCTRL_ROM_SHIFT (1U)
-#define SYSCON_AHBCLKCTRL_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ROM_SHIFT)) & SYSCON_AHBCLKCTRL_ROM_MASK)
-#define SYSCON_AHBCLKCTRL_SCT0_MASK (0x4U)
-#define SYSCON_AHBCLKCTRL_SCT0_SHIFT (2U)
-#define SYSCON_AHBCLKCTRL_SCT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SCT0_SHIFT)) & SYSCON_AHBCLKCTRL_SCT0_MASK)
-#define SYSCON_AHBCLKCTRL_LCD_MASK (0x4U)
-#define SYSCON_AHBCLKCTRL_LCD_SHIFT (2U)
-#define SYSCON_AHBCLKCTRL_LCD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_LCD_SHIFT)) & SYSCON_AHBCLKCTRL_LCD_MASK)
-#define SYSCON_AHBCLKCTRL_SRAM1_MASK (0x8U)
-#define SYSCON_AHBCLKCTRL_SRAM1_SHIFT (3U)
-#define SYSCON_AHBCLKCTRL_SRAM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM1_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM1_MASK)
-#define SYSCON_AHBCLKCTRL_SDIO_MASK (0x8U)
-#define SYSCON_AHBCLKCTRL_SDIO_SHIFT (3U)
-#define SYSCON_AHBCLKCTRL_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SDIO_SHIFT)) & SYSCON_AHBCLKCTRL_SDIO_MASK)
-#define SYSCON_AHBCLKCTRL_SRAM2_MASK (0x10U)
-#define SYSCON_AHBCLKCTRL_SRAM2_SHIFT (4U)
-#define SYSCON_AHBCLKCTRL_SRAM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM2_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM2_MASK)
-#define SYSCON_AHBCLKCTRL_USB1H_MASK (0x10U)
-#define SYSCON_AHBCLKCTRL_USB1H_SHIFT (4U)
-#define SYSCON_AHBCLKCTRL_USB1H(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB1H_SHIFT)) & SYSCON_AHBCLKCTRL_USB1H_MASK)
-#define SYSCON_AHBCLKCTRL_SRAM3_MASK (0x20U)
-#define SYSCON_AHBCLKCTRL_SRAM3_SHIFT (5U)
-#define SYSCON_AHBCLKCTRL_SRAM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM3_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM3_MASK)
-#define SYSCON_AHBCLKCTRL_USB1D_MASK (0x20U)
-#define SYSCON_AHBCLKCTRL_USB1D_SHIFT (5U)
-#define SYSCON_AHBCLKCTRL_USB1D(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB1D_SHIFT)) & SYSCON_AHBCLKCTRL_USB1D_MASK)
-#define SYSCON_AHBCLKCTRL_USB1RAM_MASK (0x40U)
-#define SYSCON_AHBCLKCTRL_USB1RAM_SHIFT (6U)
-#define SYSCON_AHBCLKCTRL_USB1RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB1RAM_SHIFT)) & SYSCON_AHBCLKCTRL_USB1RAM_MASK)
-#define SYSCON_AHBCLKCTRL_FLASH_MASK (0x80U)
-#define SYSCON_AHBCLKCTRL_FLASH_SHIFT (7U)
-#define SYSCON_AHBCLKCTRL_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLASH_SHIFT)) & SYSCON_AHBCLKCTRL_FLASH_MASK)
-#define SYSCON_AHBCLKCTRL_EMC_MASK (0x80U)
-#define SYSCON_AHBCLKCTRL_EMC_SHIFT (7U)
-#define SYSCON_AHBCLKCTRL_EMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_EMC_SHIFT)) & SYSCON_AHBCLKCTRL_EMC_MASK)
-#define SYSCON_AHBCLKCTRL_MCAN0_MASK (0x80U)
-#define SYSCON_AHBCLKCTRL_MCAN0_SHIFT (7U)
-#define SYSCON_AHBCLKCTRL_MCAN0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MCAN0_SHIFT)) & SYSCON_AHBCLKCTRL_MCAN0_MASK)
-#define SYSCON_AHBCLKCTRL_FMC_MASK (0x100U)
-#define SYSCON_AHBCLKCTRL_FMC_SHIFT (8U)
-#define SYSCON_AHBCLKCTRL_FMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FMC_SHIFT)) & SYSCON_AHBCLKCTRL_FMC_MASK)
-#define SYSCON_AHBCLKCTRL_ETH_MASK (0x100U)
-#define SYSCON_AHBCLKCTRL_ETH_SHIFT (8U)
-#define SYSCON_AHBCLKCTRL_ETH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ETH_SHIFT)) & SYSCON_AHBCLKCTRL_ETH_MASK)
-#define SYSCON_AHBCLKCTRL_MCAN1_MASK (0x100U)
-#define SYSCON_AHBCLKCTRL_MCAN1_SHIFT (8U)
-#define SYSCON_AHBCLKCTRL_MCAN1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MCAN1_SHIFT)) & SYSCON_AHBCLKCTRL_MCAN1_MASK)
-#define SYSCON_AHBCLKCTRL_EEPROM_MASK (0x200U)
-#define SYSCON_AHBCLKCTRL_EEPROM_SHIFT (9U)
-#define SYSCON_AHBCLKCTRL_EEPROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_EEPROM_SHIFT)) & SYSCON_AHBCLKCTRL_EEPROM_MASK)
-#define SYSCON_AHBCLKCTRL_GPIO4_MASK (0x200U)
-#define SYSCON_AHBCLKCTRL_GPIO4_SHIFT (9U)
-#define SYSCON_AHBCLKCTRL_GPIO4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO4_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO4_MASK)
-#define SYSCON_AHBCLKCTRL_GPIO5_MASK (0x400U)
-#define SYSCON_AHBCLKCTRL_GPIO5_SHIFT (10U)
-#define SYSCON_AHBCLKCTRL_GPIO5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO5_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO5_MASK)
-#define SYSCON_AHBCLKCTRL_UTICK_MASK (0x400U)
-#define SYSCON_AHBCLKCTRL_UTICK_SHIFT (10U)
-#define SYSCON_AHBCLKCTRL_UTICK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_UTICK_SHIFT)) & SYSCON_AHBCLKCTRL_UTICK_MASK)
-#define SYSCON_AHBCLKCTRL_SPIFI_MASK (0x400U)
-#define SYSCON_AHBCLKCTRL_SPIFI_SHIFT (10U)
-#define SYSCON_AHBCLKCTRL_SPIFI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SPIFI_SHIFT)) & SYSCON_AHBCLKCTRL_SPIFI_MASK)
-#define SYSCON_AHBCLKCTRL_INPUTMUX_MASK (0x800U)
-#define SYSCON_AHBCLKCTRL_INPUTMUX_SHIFT (11U)
-#define SYSCON_AHBCLKCTRL_INPUTMUX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_INPUTMUX_SHIFT)) & SYSCON_AHBCLKCTRL_INPUTMUX_MASK)
-#define SYSCON_AHBCLKCTRL_AES_MASK (0x800U)
-#define SYSCON_AHBCLKCTRL_AES_SHIFT (11U)
-#define SYSCON_AHBCLKCTRL_AES(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_AES_SHIFT)) & SYSCON_AHBCLKCTRL_AES_MASK)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM0_MASK (0x800U)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM0_SHIFT (11U)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM0_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM0_MASK)
-#define SYSCON_AHBCLKCTRL_OTP_MASK (0x1000U)
-#define SYSCON_AHBCLKCTRL_OTP_SHIFT (12U)
-#define SYSCON_AHBCLKCTRL_OTP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_OTP_SHIFT)) & SYSCON_AHBCLKCTRL_OTP_MASK)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM1_MASK (0x1000U)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM1_SHIFT (12U)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM1_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM1_MASK)
-#define SYSCON_AHBCLKCTRL_RNG_MASK (0x2000U)
-#define SYSCON_AHBCLKCTRL_RNG_SHIFT (13U)
-#define SYSCON_AHBCLKCTRL_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_RNG_SHIFT)) & SYSCON_AHBCLKCTRL_RNG_MASK)
-#define SYSCON_AHBCLKCTRL_IOCON_MASK (0x2000U)
-#define SYSCON_AHBCLKCTRL_IOCON_SHIFT (13U)
-#define SYSCON_AHBCLKCTRL_IOCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_IOCON_SHIFT)) & SYSCON_AHBCLKCTRL_IOCON_MASK)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM2_MASK (0x2000U)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM2_SHIFT (13U)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM2_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM2_MASK)
-#define SYSCON_AHBCLKCTRL_GPIO0_MASK (0x4000U)
-#define SYSCON_AHBCLKCTRL_GPIO0_SHIFT (14U)
-#define SYSCON_AHBCLKCTRL_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO0_MASK)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM3_MASK (0x4000U)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM3_SHIFT (14U)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM3_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM3_MASK)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM8_MASK (0x4000U)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM8_SHIFT (14U)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM8(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM8_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM8_MASK)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM9_MASK (0x8000U)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM9_SHIFT (15U)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM9(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM9_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM9_MASK)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM4_MASK (0x8000U)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM4_SHIFT (15U)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM4_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM4_MASK)
-#define SYSCON_AHBCLKCTRL_GPIO1_MASK (0x8000U)
-#define SYSCON_AHBCLKCTRL_GPIO1_SHIFT (15U)
-#define SYSCON_AHBCLKCTRL_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO1_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO1_MASK)
-#define SYSCON_AHBCLKCTRL_GPIO2_MASK (0x10000U)
-#define SYSCON_AHBCLKCTRL_GPIO2_SHIFT (16U)
-#define SYSCON_AHBCLKCTRL_GPIO2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO2_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO2_MASK)
-#define SYSCON_AHBCLKCTRL_USB0HMR_MASK (0x10000U)
-#define SYSCON_AHBCLKCTRL_USB0HMR_SHIFT (16U)
-#define SYSCON_AHBCLKCTRL_USB0HMR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB0HMR_SHIFT)) & SYSCON_AHBCLKCTRL_USB0HMR_MASK)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM5_MASK (0x10000U)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM5_SHIFT (16U)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM5_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM5_MASK)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM6_MASK (0x20000U)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM6_SHIFT (17U)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM6_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM6_MASK)
-#define SYSCON_AHBCLKCTRL_GPIO3_MASK (0x20000U)
-#define SYSCON_AHBCLKCTRL_GPIO3_SHIFT (17U)
-#define SYSCON_AHBCLKCTRL_GPIO3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO3_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO3_MASK)
-#define SYSCON_AHBCLKCTRL_USB0HSL_MASK (0x20000U)
-#define SYSCON_AHBCLKCTRL_USB0HSL_SHIFT (17U)
-#define SYSCON_AHBCLKCTRL_USB0HSL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB0HSL_SHIFT)) & SYSCON_AHBCLKCTRL_USB0HSL_MASK)
-#define SYSCON_AHBCLKCTRL_PINT_MASK (0x40000U)
-#define SYSCON_AHBCLKCTRL_PINT_SHIFT (18U)
-#define SYSCON_AHBCLKCTRL_PINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_PINT_SHIFT)) & SYSCON_AHBCLKCTRL_PINT_MASK)
-#define SYSCON_AHBCLKCTRL_SHA0_MASK (0x40000U)
-#define SYSCON_AHBCLKCTRL_SHA0_SHIFT (18U)
-#define SYSCON_AHBCLKCTRL_SHA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SHA0_SHIFT)) & SYSCON_AHBCLKCTRL_SHA0_MASK)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM7_MASK (0x40000U)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM7_SHIFT (18U)
-#define SYSCON_AHBCLKCTRL_FLEXCOMM7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM7_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM7_MASK)
-#define SYSCON_AHBCLKCTRL_DMIC_MASK (0x80000U)
-#define SYSCON_AHBCLKCTRL_DMIC_SHIFT (19U)
-#define SYSCON_AHBCLKCTRL_DMIC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_DMIC_SHIFT)) & SYSCON_AHBCLKCTRL_DMIC_MASK)
-#define SYSCON_AHBCLKCTRL_GINT_MASK (0x80000U)
-#define SYSCON_AHBCLKCTRL_GINT_SHIFT (19U)
-#define SYSCON_AHBCLKCTRL_GINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GINT_SHIFT)) & SYSCON_AHBCLKCTRL_GINT_MASK)
-#define SYSCON_AHBCLKCTRL_SC0_MASK (0x80000U)
-#define SYSCON_AHBCLKCTRL_SC0_SHIFT (19U)
-#define SYSCON_AHBCLKCTRL_SC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SC0_SHIFT)) & SYSCON_AHBCLKCTRL_SC0_MASK)
-#define SYSCON_AHBCLKCTRL_SC1_MASK (0x100000U)
-#define SYSCON_AHBCLKCTRL_SC1_SHIFT (20U)
-#define SYSCON_AHBCLKCTRL_SC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SC1_SHIFT)) & SYSCON_AHBCLKCTRL_SC1_MASK)
-#define SYSCON_AHBCLKCTRL_DMA_MASK (0x100000U)
-#define SYSCON_AHBCLKCTRL_DMA_SHIFT (20U)
-#define SYSCON_AHBCLKCTRL_DMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_DMA_SHIFT)) & SYSCON_AHBCLKCTRL_DMA_MASK)
-#define SYSCON_AHBCLKCTRL_CRC_MASK (0x200000U)
-#define SYSCON_AHBCLKCTRL_CRC_SHIFT (21U)
-#define SYSCON_AHBCLKCTRL_CRC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CRC_SHIFT)) & SYSCON_AHBCLKCTRL_CRC_MASK)
-#define SYSCON_AHBCLKCTRL_WWDT_MASK (0x400000U)
-#define SYSCON_AHBCLKCTRL_WWDT_SHIFT (22U)
-#define SYSCON_AHBCLKCTRL_WWDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_WWDT_SHIFT)) & SYSCON_AHBCLKCTRL_WWDT_MASK)
-#define SYSCON_AHBCLKCTRL_CTIMER2_MASK (0x400000U)
-#define SYSCON_AHBCLKCTRL_CTIMER2_SHIFT (22U)
-#define SYSCON_AHBCLKCTRL_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER2_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER2_MASK)
-#define SYSCON_AHBCLKCTRL_RTC_MASK (0x800000U)
-#define SYSCON_AHBCLKCTRL_RTC_SHIFT (23U)
-#define SYSCON_AHBCLKCTRL_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_RTC_SHIFT)) & SYSCON_AHBCLKCTRL_RTC_MASK)
-#define SYSCON_AHBCLKCTRL_USB0D_MASK (0x2000000U)
-#define SYSCON_AHBCLKCTRL_USB0D_SHIFT (25U)
-#define SYSCON_AHBCLKCTRL_USB0D(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB0D_SHIFT)) & SYSCON_AHBCLKCTRL_USB0D_MASK)
-#define SYSCON_AHBCLKCTRL_CTIMER0_MASK (0x4000000U)
-#define SYSCON_AHBCLKCTRL_CTIMER0_SHIFT (26U)
-#define SYSCON_AHBCLKCTRL_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER0_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER0_MASK)
-#define SYSCON_AHBCLKCTRL_CTIMER1_MASK (0x8000000U)
-#define SYSCON_AHBCLKCTRL_CTIMER1_SHIFT (27U)
-#define SYSCON_AHBCLKCTRL_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER1_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER1_MASK)
-#define SYSCON_AHBCLKCTRL_ADC0_MASK (0x8000000U)
-#define SYSCON_AHBCLKCTRL_ADC0_SHIFT (27U)
-#define SYSCON_AHBCLKCTRL_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ADC0_SHIFT)) & SYSCON_AHBCLKCTRL_ADC0_MASK)
-
-/* The count of SYSCON_AHBCLKCTRL */
-#define SYSCON_AHBCLKCTRL_COUNT (3U)
-
-/*! @name AHBCLKCTRLSET - Set bits in AHBCLKCTRLn */
-#define SYSCON_AHBCLKCTRLSET_CLK_SET_MASK (0xFFFFFFFFU)
-#define SYSCON_AHBCLKCTRLSET_CLK_SET_SHIFT (0U)
-#define SYSCON_AHBCLKCTRLSET_CLK_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_CLK_SET_SHIFT)) & SYSCON_AHBCLKCTRLSET_CLK_SET_MASK)
-
-/* The count of SYSCON_AHBCLKCTRLSET */
-#define SYSCON_AHBCLKCTRLSET_COUNT (3U)
-
-/*! @name AHBCLKCTRLCLR - Clear bits in AHBCLKCTRLn */
-#define SYSCON_AHBCLKCTRLCLR_CLK_CLR_MASK (0xFFFFFFFFU)
-#define SYSCON_AHBCLKCTRLCLR_CLK_CLR_SHIFT (0U)
-#define SYSCON_AHBCLKCTRLCLR_CLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_CLK_CLR_SHIFT)) & SYSCON_AHBCLKCTRLCLR_CLK_CLR_MASK)
-
-/* The count of SYSCON_AHBCLKCTRLCLR */
-#define SYSCON_AHBCLKCTRLCLR_COUNT (3U)
-
-/*! @name MAINCLKSELA - Main clock source select A */
-#define SYSCON_MAINCLKSELA_SEL_MASK (0x3U)
-#define SYSCON_MAINCLKSELA_SEL_SHIFT (0U)
-#define SYSCON_MAINCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELA_SEL_SHIFT)) & SYSCON_MAINCLKSELA_SEL_MASK)
-
-/*! @name MAINCLKSELB - Main clock source select B */
-#define SYSCON_MAINCLKSELB_SEL_MASK (0x3U)
-#define SYSCON_MAINCLKSELB_SEL_SHIFT (0U)
-#define SYSCON_MAINCLKSELB_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELB_SEL_SHIFT)) & SYSCON_MAINCLKSELB_SEL_MASK)
-
-/*! @name CLKOUTSELA - CLKOUT clock source select A */
-#define SYSCON_CLKOUTSELA_SEL_MASK (0x7U)
-#define SYSCON_CLKOUTSELA_SEL_SHIFT (0U)
-#define SYSCON_CLKOUTSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSELA_SEL_SHIFT)) & SYSCON_CLKOUTSELA_SEL_MASK)
-
-/*! @name SYSPLLCLKSEL - PLL clock source select */
-#define SYSCON_SYSPLLCLKSEL_SEL_MASK (0x7U)
-#define SYSCON_SYSPLLCLKSEL_SEL_SHIFT (0U)
-#define SYSCON_SYSPLLCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCLKSEL_SEL_SHIFT)) & SYSCON_SYSPLLCLKSEL_SEL_MASK)
-
-/*! @name AUDPLLCLKSEL - Audio PLL clock source select */
-#define SYSCON_AUDPLLCLKSEL_SEL_MASK (0x7U)
-#define SYSCON_AUDPLLCLKSEL_SEL_SHIFT (0U)
-#define SYSCON_AUDPLLCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCLKSEL_SEL_SHIFT)) & SYSCON_AUDPLLCLKSEL_SEL_MASK)
-
-/*! @name SPIFICLKSEL - SPIFI clock source select */
-#define SYSCON_SPIFICLKSEL_SEL_MASK (0x7U)
-#define SYSCON_SPIFICLKSEL_SEL_SHIFT (0U)
-#define SYSCON_SPIFICLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKSEL_SEL_SHIFT)) & SYSCON_SPIFICLKSEL_SEL_MASK)
-
-/*! @name ADCCLKSEL - ADC clock source select */
-#define SYSCON_ADCCLKSEL_SEL_MASK (0x7U)
-#define SYSCON_ADCCLKSEL_SEL_SHIFT (0U)
-#define SYSCON_ADCCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKSEL_SEL_SHIFT)) & SYSCON_ADCCLKSEL_SEL_MASK)
-
-/*! @name USB0CLKSEL - USB0 clock source select */
-#define SYSCON_USB0CLKSEL_SEL_MASK (0x7U)
-#define SYSCON_USB0CLKSEL_SEL_SHIFT (0U)
-#define SYSCON_USB0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSEL_SEL_SHIFT)) & SYSCON_USB0CLKSEL_SEL_MASK)
-
-/*! @name USB1CLKSEL - USB1 clock source select */
-#define SYSCON_USB1CLKSEL_SEL_MASK (0x7U)
-#define SYSCON_USB1CLKSEL_SEL_SHIFT (0U)
-#define SYSCON_USB1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSEL_SEL_SHIFT)) & SYSCON_USB1CLKSEL_SEL_MASK)
-
-/*! @name FCLKSEL - Flexcomm 0 clock source select */
-#define SYSCON_FCLKSEL_SEL_MASK (0x7U)
-#define SYSCON_FCLKSEL_SEL_SHIFT (0U)
-#define SYSCON_FCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCLKSEL_SEL_SHIFT)) & SYSCON_FCLKSEL_SEL_MASK)
-
-/* The count of SYSCON_FCLKSEL */
-#define SYSCON_FCLKSEL_COUNT (10U)
-
-/*! @name MCLKCLKSEL - MCLK clock source select */
-#define SYSCON_MCLKCLKSEL_SEL_MASK (0x7U)
-#define SYSCON_MCLKCLKSEL_SEL_SHIFT (0U)
-#define SYSCON_MCLKCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKCLKSEL_SEL_SHIFT)) & SYSCON_MCLKCLKSEL_SEL_MASK)
-
-/*! @name FRGCLKSEL - Fractional Rate Generator clock source select */
-#define SYSCON_FRGCLKSEL_SEL_MASK (0x7U)
-#define SYSCON_FRGCLKSEL_SEL_SHIFT (0U)
-#define SYSCON_FRGCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCLKSEL_SEL_SHIFT)) & SYSCON_FRGCLKSEL_SEL_MASK)
-
-/*! @name DMICCLKSEL - Digital microphone (DMIC) subsystem clock select */
-#define SYSCON_DMICCLKSEL_SEL_MASK (0x7U)
-#define SYSCON_DMICCLKSEL_SEL_SHIFT (0U)
-#define SYSCON_DMICCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKSEL_SEL_SHIFT)) & SYSCON_DMICCLKSEL_SEL_MASK)
-
-/*! @name SCTCLKSEL - SCTimer/PWM clock source select */
-#define SYSCON_SCTCLKSEL_SEL_MASK (0x7U)
-#define SYSCON_SCTCLKSEL_SEL_SHIFT (0U)
-#define SYSCON_SCTCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKSEL_SEL_SHIFT)) & SYSCON_SCTCLKSEL_SEL_MASK)
-
-/*! @name LCDCLKSEL - LCD clock source select */
-#define SYSCON_LCDCLKSEL_SEL_MASK (0x3U)
-#define SYSCON_LCDCLKSEL_SEL_SHIFT (0U)
-#define SYSCON_LCDCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKSEL_SEL_SHIFT)) & SYSCON_LCDCLKSEL_SEL_MASK)
-
-/*! @name SDIOCLKSEL - SDIO clock source select */
-#define SYSCON_SDIOCLKSEL_SEL_MASK (0x7U)
-#define SYSCON_SDIOCLKSEL_SEL_SHIFT (0U)
-#define SYSCON_SDIOCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKSEL_SEL_SHIFT)) & SYSCON_SDIOCLKSEL_SEL_MASK)
-
-/*! @name SYSTICKCLKDIV - SYSTICK clock divider */
-#define SYSCON_SYSTICKCLKDIV_DIV_MASK (0xFFU)
-#define SYSCON_SYSTICKCLKDIV_DIV_SHIFT (0U)
-#define SYSCON_SYSTICKCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV_DIV_MASK)
-#define SYSCON_SYSTICKCLKDIV_RESET_MASK (0x20000000U)
-#define SYSCON_SYSTICKCLKDIV_RESET_SHIFT (29U)
-#define SYSCON_SYSTICKCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV_RESET_MASK)
-#define SYSCON_SYSTICKCLKDIV_HALT_MASK (0x40000000U)
-#define SYSCON_SYSTICKCLKDIV_HALT_SHIFT (30U)
-#define SYSCON_SYSTICKCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV_HALT_MASK)
-#define SYSCON_SYSTICKCLKDIV_REQFLAG_MASK (0x80000000U)
-#define SYSCON_SYSTICKCLKDIV_REQFLAG_SHIFT (31U)
-#define SYSCON_SYSTICKCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_REQFLAG_SHIFT)) & SYSCON_SYSTICKCLKDIV_REQFLAG_MASK)
-
-/*! @name ARMTRACECLKDIV - ARM Trace clock divider */
-#define SYSCON_ARMTRACECLKDIV_DIV_MASK (0xFFU)
-#define SYSCON_ARMTRACECLKDIV_DIV_SHIFT (0U)
-#define SYSCON_ARMTRACECLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ARMTRACECLKDIV_DIV_SHIFT)) & SYSCON_ARMTRACECLKDIV_DIV_MASK)
-#define SYSCON_ARMTRACECLKDIV_RESET_MASK (0x20000000U)
-#define SYSCON_ARMTRACECLKDIV_RESET_SHIFT (29U)
-#define SYSCON_ARMTRACECLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ARMTRACECLKDIV_RESET_SHIFT)) & SYSCON_ARMTRACECLKDIV_RESET_MASK)
-#define SYSCON_ARMTRACECLKDIV_HALT_MASK (0x40000000U)
-#define SYSCON_ARMTRACECLKDIV_HALT_SHIFT (30U)
-#define SYSCON_ARMTRACECLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ARMTRACECLKDIV_HALT_SHIFT)) & SYSCON_ARMTRACECLKDIV_HALT_MASK)
-#define SYSCON_ARMTRACECLKDIV_REQFLAG_MASK (0x80000000U)
-#define SYSCON_ARMTRACECLKDIV_REQFLAG_SHIFT (31U)
-#define SYSCON_ARMTRACECLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ARMTRACECLKDIV_REQFLAG_SHIFT)) & SYSCON_ARMTRACECLKDIV_REQFLAG_MASK)
-
-/*! @name CAN0CLKDIV - MCAN0 clock divider */
-#define SYSCON_CAN0CLKDIV_DIV_MASK (0xFFU)
-#define SYSCON_CAN0CLKDIV_DIV_SHIFT (0U)
-#define SYSCON_CAN0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN0CLKDIV_DIV_SHIFT)) & SYSCON_CAN0CLKDIV_DIV_MASK)
-#define SYSCON_CAN0CLKDIV_RESET_MASK (0x20000000U)
-#define SYSCON_CAN0CLKDIV_RESET_SHIFT (29U)
-#define SYSCON_CAN0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN0CLKDIV_RESET_SHIFT)) & SYSCON_CAN0CLKDIV_RESET_MASK)
-#define SYSCON_CAN0CLKDIV_HALT_MASK (0x40000000U)
-#define SYSCON_CAN0CLKDIV_HALT_SHIFT (30U)
-#define SYSCON_CAN0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN0CLKDIV_HALT_SHIFT)) & SYSCON_CAN0CLKDIV_HALT_MASK)
-#define SYSCON_CAN0CLKDIV_REQFLAG_MASK (0x80000000U)
-#define SYSCON_CAN0CLKDIV_REQFLAG_SHIFT (31U)
-#define SYSCON_CAN0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN0CLKDIV_REQFLAG_SHIFT)) & SYSCON_CAN0CLKDIV_REQFLAG_MASK)
-
-/*! @name CAN1CLKDIV - MCAN1 clock divider */
-#define SYSCON_CAN1CLKDIV_DIV_MASK (0xFFU)
-#define SYSCON_CAN1CLKDIV_DIV_SHIFT (0U)
-#define SYSCON_CAN1CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN1CLKDIV_DIV_SHIFT)) & SYSCON_CAN1CLKDIV_DIV_MASK)
-#define SYSCON_CAN1CLKDIV_RESET_MASK (0x20000000U)
-#define SYSCON_CAN1CLKDIV_RESET_SHIFT (29U)
-#define SYSCON_CAN1CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN1CLKDIV_RESET_SHIFT)) & SYSCON_CAN1CLKDIV_RESET_MASK)
-#define SYSCON_CAN1CLKDIV_HALT_MASK (0x40000000U)
-#define SYSCON_CAN1CLKDIV_HALT_SHIFT (30U)
-#define SYSCON_CAN1CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN1CLKDIV_HALT_SHIFT)) & SYSCON_CAN1CLKDIV_HALT_MASK)
-#define SYSCON_CAN1CLKDIV_REQFLAG_MASK (0x80000000U)
-#define SYSCON_CAN1CLKDIV_REQFLAG_SHIFT (31U)
-#define SYSCON_CAN1CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN1CLKDIV_REQFLAG_SHIFT)) & SYSCON_CAN1CLKDIV_REQFLAG_MASK)
-
-/*! @name SC0CLKDIV - Smartcard0 clock divider */
-#define SYSCON_SC0CLKDIV_DIV_MASK (0xFFU)
-#define SYSCON_SC0CLKDIV_DIV_SHIFT (0U)
-#define SYSCON_SC0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC0CLKDIV_DIV_SHIFT)) & SYSCON_SC0CLKDIV_DIV_MASK)
-#define SYSCON_SC0CLKDIV_RESET_MASK (0x20000000U)
-#define SYSCON_SC0CLKDIV_RESET_SHIFT (29U)
-#define SYSCON_SC0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC0CLKDIV_RESET_SHIFT)) & SYSCON_SC0CLKDIV_RESET_MASK)
-#define SYSCON_SC0CLKDIV_HALT_MASK (0x40000000U)
-#define SYSCON_SC0CLKDIV_HALT_SHIFT (30U)
-#define SYSCON_SC0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC0CLKDIV_HALT_SHIFT)) & SYSCON_SC0CLKDIV_HALT_MASK)
-#define SYSCON_SC0CLKDIV_REQFLAG_MASK (0x80000000U)
-#define SYSCON_SC0CLKDIV_REQFLAG_SHIFT (31U)
-#define SYSCON_SC0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC0CLKDIV_REQFLAG_SHIFT)) & SYSCON_SC0CLKDIV_REQFLAG_MASK)
-
-/*! @name SC1CLKDIV - Smartcard1 clock divider */
-#define SYSCON_SC1CLKDIV_DIV_MASK (0xFFU)
-#define SYSCON_SC1CLKDIV_DIV_SHIFT (0U)
-#define SYSCON_SC1CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC1CLKDIV_DIV_SHIFT)) & SYSCON_SC1CLKDIV_DIV_MASK)
-#define SYSCON_SC1CLKDIV_RESET_MASK (0x20000000U)
-#define SYSCON_SC1CLKDIV_RESET_SHIFT (29U)
-#define SYSCON_SC1CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC1CLKDIV_RESET_SHIFT)) & SYSCON_SC1CLKDIV_RESET_MASK)
-#define SYSCON_SC1CLKDIV_HALT_MASK (0x40000000U)
-#define SYSCON_SC1CLKDIV_HALT_SHIFT (30U)
-#define SYSCON_SC1CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC1CLKDIV_HALT_SHIFT)) & SYSCON_SC1CLKDIV_HALT_MASK)
-#define SYSCON_SC1CLKDIV_REQFLAG_MASK (0x80000000U)
-#define SYSCON_SC1CLKDIV_REQFLAG_SHIFT (31U)
-#define SYSCON_SC1CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC1CLKDIV_REQFLAG_SHIFT)) & SYSCON_SC1CLKDIV_REQFLAG_MASK)
-
-/*! @name AHBCLKDIV - AHB clock divider */
-#define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU)
-#define SYSCON_AHBCLKDIV_DIV_SHIFT (0U)
-#define SYSCON_AHBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK)
-#define SYSCON_AHBCLKDIV_REQFLAG_MASK (0x80000000U)
-#define SYSCON_AHBCLKDIV_REQFLAG_SHIFT (31U)
-#define SYSCON_AHBCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_REQFLAG_SHIFT)) & SYSCON_AHBCLKDIV_REQFLAG_MASK)
-
-/*! @name CLKOUTDIV - CLKOUT clock divider */
-#define SYSCON_CLKOUTDIV_DIV_MASK (0xFFU)
-#define SYSCON_CLKOUTDIV_DIV_SHIFT (0U)
-#define SYSCON_CLKOUTDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK)
-#define SYSCON_CLKOUTDIV_RESET_MASK (0x20000000U)
-#define SYSCON_CLKOUTDIV_RESET_SHIFT (29U)
-#define SYSCON_CLKOUTDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_RESET_SHIFT)) & SYSCON_CLKOUTDIV_RESET_MASK)
-#define SYSCON_CLKOUTDIV_HALT_MASK (0x40000000U)
-#define SYSCON_CLKOUTDIV_HALT_SHIFT (30U)
-#define SYSCON_CLKOUTDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_HALT_SHIFT)) & SYSCON_CLKOUTDIV_HALT_MASK)
-#define SYSCON_CLKOUTDIV_REQFLAG_MASK (0x80000000U)
-#define SYSCON_CLKOUTDIV_REQFLAG_SHIFT (31U)
-#define SYSCON_CLKOUTDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_REQFLAG_SHIFT)) & SYSCON_CLKOUTDIV_REQFLAG_MASK)
-
-/*! @name FROHFCLKDIV - FROHF clock divider */
-#define SYSCON_FROHFCLKDIV_DIV_MASK (0xFFU)
-#define SYSCON_FROHFCLKDIV_DIV_SHIFT (0U)
-#define SYSCON_FROHFCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFCLKDIV_DIV_SHIFT)) & SYSCON_FROHFCLKDIV_DIV_MASK)
-#define SYSCON_FROHFCLKDIV_RESET_MASK (0x20000000U)
-#define SYSCON_FROHFCLKDIV_RESET_SHIFT (29U)
-#define SYSCON_FROHFCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFCLKDIV_RESET_SHIFT)) & SYSCON_FROHFCLKDIV_RESET_MASK)
-#define SYSCON_FROHFCLKDIV_HALT_MASK (0x40000000U)
-#define SYSCON_FROHFCLKDIV_HALT_SHIFT (30U)
-#define SYSCON_FROHFCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFCLKDIV_HALT_SHIFT)) & SYSCON_FROHFCLKDIV_HALT_MASK)
-#define SYSCON_FROHFCLKDIV_REQFLAG_MASK (0x80000000U)
-#define SYSCON_FROHFCLKDIV_REQFLAG_SHIFT (31U)
-#define SYSCON_FROHFCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFCLKDIV_REQFLAG_SHIFT)) & SYSCON_FROHFCLKDIV_REQFLAG_MASK)
-
-/*! @name SPIFICLKDIV - SPIFI clock divider */
-#define SYSCON_SPIFICLKDIV_DIV_MASK (0xFFU)
-#define SYSCON_SPIFICLKDIV_DIV_SHIFT (0U)
-#define SYSCON_SPIFICLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_DIV_SHIFT)) & SYSCON_SPIFICLKDIV_DIV_MASK)
-#define SYSCON_SPIFICLKDIV_RESET_MASK (0x20000000U)
-#define SYSCON_SPIFICLKDIV_RESET_SHIFT (29U)
-#define SYSCON_SPIFICLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_RESET_SHIFT)) & SYSCON_SPIFICLKDIV_RESET_MASK)
-#define SYSCON_SPIFICLKDIV_HALT_MASK (0x40000000U)
-#define SYSCON_SPIFICLKDIV_HALT_SHIFT (30U)
-#define SYSCON_SPIFICLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_HALT_SHIFT)) & SYSCON_SPIFICLKDIV_HALT_MASK)
-#define SYSCON_SPIFICLKDIV_REQFLAG_MASK (0x80000000U)
-#define SYSCON_SPIFICLKDIV_REQFLAG_SHIFT (31U)
-#define SYSCON_SPIFICLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_REQFLAG_SHIFT)) & SYSCON_SPIFICLKDIV_REQFLAG_MASK)
-
-/*! @name ADCCLKDIV - ADC clock divider */
-#define SYSCON_ADCCLKDIV_DIV_MASK (0xFFU)
-#define SYSCON_ADCCLKDIV_DIV_SHIFT (0U)
-#define SYSCON_ADCCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_DIV_SHIFT)) & SYSCON_ADCCLKDIV_DIV_MASK)
-#define SYSCON_ADCCLKDIV_RESET_MASK (0x20000000U)
-#define SYSCON_ADCCLKDIV_RESET_SHIFT (29U)
-#define SYSCON_ADCCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_RESET_SHIFT)) & SYSCON_ADCCLKDIV_RESET_MASK)
-#define SYSCON_ADCCLKDIV_HALT_MASK (0x40000000U)
-#define SYSCON_ADCCLKDIV_HALT_SHIFT (30U)
-#define SYSCON_ADCCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_HALT_SHIFT)) & SYSCON_ADCCLKDIV_HALT_MASK)
-#define SYSCON_ADCCLKDIV_REQFLAG_MASK (0x80000000U)
-#define SYSCON_ADCCLKDIV_REQFLAG_SHIFT (31U)
-#define SYSCON_ADCCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_REQFLAG_SHIFT)) & SYSCON_ADCCLKDIV_REQFLAG_MASK)
-
-/*! @name USB0CLKDIV - USB0 clock divider */
-#define SYSCON_USB0CLKDIV_DIV_MASK (0xFFU)
-#define SYSCON_USB0CLKDIV_DIV_SHIFT (0U)
-#define SYSCON_USB0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_DIV_SHIFT)) & SYSCON_USB0CLKDIV_DIV_MASK)
-#define SYSCON_USB0CLKDIV_RESET_MASK (0x20000000U)
-#define SYSCON_USB0CLKDIV_RESET_SHIFT (29U)
-#define SYSCON_USB0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_RESET_SHIFT)) & SYSCON_USB0CLKDIV_RESET_MASK)
-#define SYSCON_USB0CLKDIV_HALT_MASK (0x40000000U)
-#define SYSCON_USB0CLKDIV_HALT_SHIFT (30U)
-#define SYSCON_USB0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_HALT_SHIFT)) & SYSCON_USB0CLKDIV_HALT_MASK)
-#define SYSCON_USB0CLKDIV_REQFLAG_MASK (0x80000000U)
-#define SYSCON_USB0CLKDIV_REQFLAG_SHIFT (31U)
-#define SYSCON_USB0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_REQFLAG_SHIFT)) & SYSCON_USB0CLKDIV_REQFLAG_MASK)
-
-/*! @name USB1CLKDIV - USB1 clock divider */
-#define SYSCON_USB1CLKDIV_DIV_MASK (0xFFU)
-#define SYSCON_USB1CLKDIV_DIV_SHIFT (0U)
-#define SYSCON_USB1CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKDIV_DIV_SHIFT)) & SYSCON_USB1CLKDIV_DIV_MASK)
-#define SYSCON_USB1CLKDIV_RESET_MASK (0x20000000U)
-#define SYSCON_USB1CLKDIV_RESET_SHIFT (29U)
-#define SYSCON_USB1CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKDIV_RESET_SHIFT)) & SYSCON_USB1CLKDIV_RESET_MASK)
-#define SYSCON_USB1CLKDIV_HALT_MASK (0x40000000U)
-#define SYSCON_USB1CLKDIV_HALT_SHIFT (30U)
-#define SYSCON_USB1CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKDIV_HALT_SHIFT)) & SYSCON_USB1CLKDIV_HALT_MASK)
-#define SYSCON_USB1CLKDIV_REQFLAG_MASK (0x80000000U)
-#define SYSCON_USB1CLKDIV_REQFLAG_SHIFT (31U)
-#define SYSCON_USB1CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKDIV_REQFLAG_SHIFT)) & SYSCON_USB1CLKDIV_REQFLAG_MASK)
-
-/*! @name FRGCTRL - Fractional rate divider */
-#define SYSCON_FRGCTRL_DIV_MASK (0xFFU)
-#define SYSCON_FRGCTRL_DIV_SHIFT (0U)
-#define SYSCON_FRGCTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_DIV_SHIFT)) & SYSCON_FRGCTRL_DIV_MASK)
-#define SYSCON_FRGCTRL_MULT_MASK (0xFF00U)
-#define SYSCON_FRGCTRL_MULT_SHIFT (8U)
-#define SYSCON_FRGCTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_MULT_SHIFT)) & SYSCON_FRGCTRL_MULT_MASK)
-
-/*! @name DMICCLKDIV - DMIC clock divider */
-#define SYSCON_DMICCLKDIV_DIV_MASK (0xFFU)
-#define SYSCON_DMICCLKDIV_DIV_SHIFT (0U)
-#define SYSCON_DMICCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_DIV_SHIFT)) & SYSCON_DMICCLKDIV_DIV_MASK)
-#define SYSCON_DMICCLKDIV_RESET_MASK (0x20000000U)
-#define SYSCON_DMICCLKDIV_RESET_SHIFT (29U)
-#define SYSCON_DMICCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_RESET_SHIFT)) & SYSCON_DMICCLKDIV_RESET_MASK)
-#define SYSCON_DMICCLKDIV_HALT_MASK (0x40000000U)
-#define SYSCON_DMICCLKDIV_HALT_SHIFT (30U)
-#define SYSCON_DMICCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_HALT_SHIFT)) & SYSCON_DMICCLKDIV_HALT_MASK)
-#define SYSCON_DMICCLKDIV_REQFLAG_MASK (0x80000000U)
-#define SYSCON_DMICCLKDIV_REQFLAG_SHIFT (31U)
-#define SYSCON_DMICCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_REQFLAG_SHIFT)) & SYSCON_DMICCLKDIV_REQFLAG_MASK)
-
-/*! @name MCLKDIV - I2S MCLK clock divider */
-#define SYSCON_MCLKDIV_DIV_MASK (0xFFU)
-#define SYSCON_MCLKDIV_DIV_SHIFT (0U)
-#define SYSCON_MCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_DIV_SHIFT)) & SYSCON_MCLKDIV_DIV_MASK)
-#define SYSCON_MCLKDIV_RESET_MASK (0x20000000U)
-#define SYSCON_MCLKDIV_RESET_SHIFT (29U)
-#define SYSCON_MCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_RESET_SHIFT)) & SYSCON_MCLKDIV_RESET_MASK)
-#define SYSCON_MCLKDIV_HALT_MASK (0x40000000U)
-#define SYSCON_MCLKDIV_HALT_SHIFT (30U)
-#define SYSCON_MCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_HALT_SHIFT)) & SYSCON_MCLKDIV_HALT_MASK)
-#define SYSCON_MCLKDIV_REQFLAG_MASK (0x80000000U)
-#define SYSCON_MCLKDIV_REQFLAG_SHIFT (31U)
-#define SYSCON_MCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_REQFLAG_SHIFT)) & SYSCON_MCLKDIV_REQFLAG_MASK)
-
-/*! @name LCDCLKDIV - LCD clock divider */
-#define SYSCON_LCDCLKDIV_DIV_MASK (0xFFU)
-#define SYSCON_LCDCLKDIV_DIV_SHIFT (0U)
-#define SYSCON_LCDCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKDIV_DIV_SHIFT)) & SYSCON_LCDCLKDIV_DIV_MASK)
-#define SYSCON_LCDCLKDIV_RESET_MASK (0x20000000U)
-#define SYSCON_LCDCLKDIV_RESET_SHIFT (29U)
-#define SYSCON_LCDCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKDIV_RESET_SHIFT)) & SYSCON_LCDCLKDIV_RESET_MASK)
-#define SYSCON_LCDCLKDIV_HALT_MASK (0x40000000U)
-#define SYSCON_LCDCLKDIV_HALT_SHIFT (30U)
-#define SYSCON_LCDCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKDIV_HALT_SHIFT)) & SYSCON_LCDCLKDIV_HALT_MASK)
-#define SYSCON_LCDCLKDIV_REQFLAG_MASK (0x80000000U)
-#define SYSCON_LCDCLKDIV_REQFLAG_SHIFT (31U)
-#define SYSCON_LCDCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKDIV_REQFLAG_SHIFT)) & SYSCON_LCDCLKDIV_REQFLAG_MASK)
-
-/*! @name SCTCLKDIV - SCT/PWM clock divider */
-#define SYSCON_SCTCLKDIV_DIV_MASK (0xFFU)
-#define SYSCON_SCTCLKDIV_DIV_SHIFT (0U)
-#define SYSCON_SCTCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_DIV_SHIFT)) & SYSCON_SCTCLKDIV_DIV_MASK)
-#define SYSCON_SCTCLKDIV_RESET_MASK (0x20000000U)
-#define SYSCON_SCTCLKDIV_RESET_SHIFT (29U)
-#define SYSCON_SCTCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_RESET_SHIFT)) & SYSCON_SCTCLKDIV_RESET_MASK)
-#define SYSCON_SCTCLKDIV_HALT_MASK (0x40000000U)
-#define SYSCON_SCTCLKDIV_HALT_SHIFT (30U)
-#define SYSCON_SCTCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_HALT_SHIFT)) & SYSCON_SCTCLKDIV_HALT_MASK)
-#define SYSCON_SCTCLKDIV_REQFLAG_MASK (0x80000000U)
-#define SYSCON_SCTCLKDIV_REQFLAG_SHIFT (31U)
-#define SYSCON_SCTCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_REQFLAG_SHIFT)) & SYSCON_SCTCLKDIV_REQFLAG_MASK)
-
-/*! @name EMCCLKDIV - EMC clock divider */
-#define SYSCON_EMCCLKDIV_DIV_MASK (0xFFU)
-#define SYSCON_EMCCLKDIV_DIV_SHIFT (0U)
-#define SYSCON_EMCCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCLKDIV_DIV_SHIFT)) & SYSCON_EMCCLKDIV_DIV_MASK)
-#define SYSCON_EMCCLKDIV_RESET_MASK (0x20000000U)
-#define SYSCON_EMCCLKDIV_RESET_SHIFT (29U)
-#define SYSCON_EMCCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCLKDIV_RESET_SHIFT)) & SYSCON_EMCCLKDIV_RESET_MASK)
-#define SYSCON_EMCCLKDIV_HALT_MASK (0x40000000U)
-#define SYSCON_EMCCLKDIV_HALT_SHIFT (30U)
-#define SYSCON_EMCCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCLKDIV_HALT_SHIFT)) & SYSCON_EMCCLKDIV_HALT_MASK)
-#define SYSCON_EMCCLKDIV_REQFLAG_MASK (0x80000000U)
-#define SYSCON_EMCCLKDIV_REQFLAG_SHIFT (31U)
-#define SYSCON_EMCCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCLKDIV_REQFLAG_SHIFT)) & SYSCON_EMCCLKDIV_REQFLAG_MASK)
-
-/*! @name SDIOCLKDIV - SDIO clock divider */
-#define SYSCON_SDIOCLKDIV_DIV_MASK (0xFFU)
-#define SYSCON_SDIOCLKDIV_DIV_SHIFT (0U)
-#define SYSCON_SDIOCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_DIV_SHIFT)) & SYSCON_SDIOCLKDIV_DIV_MASK)
-#define SYSCON_SDIOCLKDIV_RESET_MASK (0x20000000U)
-#define SYSCON_SDIOCLKDIV_RESET_SHIFT (29U)
-#define SYSCON_SDIOCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_RESET_SHIFT)) & SYSCON_SDIOCLKDIV_RESET_MASK)
-#define SYSCON_SDIOCLKDIV_HALT_MASK (0x40000000U)
-#define SYSCON_SDIOCLKDIV_HALT_SHIFT (30U)
-#define SYSCON_SDIOCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_HALT_SHIFT)) & SYSCON_SDIOCLKDIV_HALT_MASK)
-#define SYSCON_SDIOCLKDIV_REQFLAG_MASK (0x80000000U)
-#define SYSCON_SDIOCLKDIV_REQFLAG_SHIFT (31U)
-#define SYSCON_SDIOCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_REQFLAG_SHIFT)) & SYSCON_SDIOCLKDIV_REQFLAG_MASK)
-
-/*! @name FLASHCFG - Flash wait states configuration */
-#define SYSCON_FLASHCFG_FETCHCFG_MASK (0x3U)
-#define SYSCON_FLASHCFG_FETCHCFG_SHIFT (0U)
-#define SYSCON_FLASHCFG_FETCHCFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_FETCHCFG_SHIFT)) & SYSCON_FLASHCFG_FETCHCFG_MASK)
-#define SYSCON_FLASHCFG_DATACFG_MASK (0xCU)
-#define SYSCON_FLASHCFG_DATACFG_SHIFT (2U)
-#define SYSCON_FLASHCFG_DATACFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_DATACFG_SHIFT)) & SYSCON_FLASHCFG_DATACFG_MASK)
-#define SYSCON_FLASHCFG_ACCEL_MASK (0x10U)
-#define SYSCON_FLASHCFG_ACCEL_SHIFT (4U)
-#define SYSCON_FLASHCFG_ACCEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_ACCEL_SHIFT)) & SYSCON_FLASHCFG_ACCEL_MASK)
-#define SYSCON_FLASHCFG_PREFEN_MASK (0x20U)
-#define SYSCON_FLASHCFG_PREFEN_SHIFT (5U)
-#define SYSCON_FLASHCFG_PREFEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_PREFEN_SHIFT)) & SYSCON_FLASHCFG_PREFEN_MASK)
-#define SYSCON_FLASHCFG_PREFOVR_MASK (0x40U)
-#define SYSCON_FLASHCFG_PREFOVR_SHIFT (6U)
-#define SYSCON_FLASHCFG_PREFOVR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_PREFOVR_SHIFT)) & SYSCON_FLASHCFG_PREFOVR_MASK)
-#define SYSCON_FLASHCFG_FLASHTIM_MASK (0xF000U)
-#define SYSCON_FLASHCFG_FLASHTIM_SHIFT (12U)
-#define SYSCON_FLASHCFG_FLASHTIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_FLASHTIM_SHIFT)) & SYSCON_FLASHCFG_FLASHTIM_MASK)
-
-/*! @name USB0CLKCTRL - USB0 clock control */
-#define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_MASK (0x1U)
-#define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_SHIFT (0U)
-#define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_MASK)
-#define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_MASK (0x2U)
-#define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_SHIFT (1U)
-#define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_MASK)
-#define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_MASK (0x4U)
-#define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_SHIFT (2U)
-#define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_MASK)
-#define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_MASK (0x8U)
-#define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_SHIFT (3U)
-#define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_MASK)
-#define SYSCON_USB0CLKCTRL_PU_DISABLE_MASK (0x10U)
-#define SYSCON_USB0CLKCTRL_PU_DISABLE_SHIFT (4U)
-#define SYSCON_USB0CLKCTRL_PU_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_PU_DISABLE_SHIFT)) & SYSCON_USB0CLKCTRL_PU_DISABLE_MASK)
-
-/*! @name USB0CLKSTAT - USB0 clock status */
-#define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_MASK (0x1U)
-#define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_SHIFT (0U)
-#define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_SHIFT)) & SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_MASK)
-#define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_MASK (0x2U)
-#define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_SHIFT (1U)
-#define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_SHIFT)) & SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_MASK)
-
-/*! @name FREQMECTRL - Frequency measure register */
-#define SYSCON_FREQMECTRL_CAPVAL_MASK (0x3FFFU)
-#define SYSCON_FREQMECTRL_CAPVAL_SHIFT (0U)
-#define SYSCON_FREQMECTRL_CAPVAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FREQMECTRL_CAPVAL_SHIFT)) & SYSCON_FREQMECTRL_CAPVAL_MASK)
-#define SYSCON_FREQMECTRL_PROG_MASK (0x80000000U)
-#define SYSCON_FREQMECTRL_PROG_SHIFT (31U)
-#define SYSCON_FREQMECTRL_PROG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FREQMECTRL_PROG_SHIFT)) & SYSCON_FREQMECTRL_PROG_MASK)
-
-/*! @name MCLKIO - MCLK input/output control */
-#define SYSCON_MCLKIO_DIR_MASK (0x1U)
-#define SYSCON_MCLKIO_DIR_SHIFT (0U)
-#define SYSCON_MCLKIO_DIR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKIO_DIR_SHIFT)) & SYSCON_MCLKIO_DIR_MASK)
-
-/*! @name USB1CLKCTRL - USB1 clock control */
-#define SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK_MASK (0x1U)
-#define SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK_SHIFT (0U)
-#define SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK_MASK)
-#define SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK_MASK (0x2U)
-#define SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK_SHIFT (1U)
-#define SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK_MASK)
-#define SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK_MASK (0x4U)
-#define SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK_SHIFT (2U)
-#define SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK_MASK)
-#define SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK_MASK (0x8U)
-#define SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK_SHIFT (3U)
-#define SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK_MASK)
-#define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_MASK (0x10U)
-#define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_SHIFT (4U)
-#define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_SHIFT)) & SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_MASK)
-
-/*! @name USB1CLKSTAT - USB1 clock status */
-#define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_MASK (0x1U)
-#define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_SHIFT (0U)
-#define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_SHIFT)) & SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_MASK)
-#define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_MASK (0x2U)
-#define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_SHIFT (1U)
-#define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_SHIFT)) & SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_MASK)
-
-/*! @name EMCSYSCTRL - EMC system control */
-#define SYSCON_EMCSYSCTRL_EMCSC_MASK (0x1U)
-#define SYSCON_EMCSYSCTRL_EMCSC_SHIFT (0U)
-#define SYSCON_EMCSYSCTRL_EMCSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCSYSCTRL_EMCSC_SHIFT)) & SYSCON_EMCSYSCTRL_EMCSC_MASK)
-#define SYSCON_EMCSYSCTRL_EMCRD_MASK (0x2U)
-#define SYSCON_EMCSYSCTRL_EMCRD_SHIFT (1U)
-#define SYSCON_EMCSYSCTRL_EMCRD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCSYSCTRL_EMCRD_SHIFT)) & SYSCON_EMCSYSCTRL_EMCRD_MASK)
-#define SYSCON_EMCSYSCTRL_EMCBC_MASK (0x4U)
-#define SYSCON_EMCSYSCTRL_EMCBC_SHIFT (2U)
-#define SYSCON_EMCSYSCTRL_EMCBC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCSYSCTRL_EMCBC_SHIFT)) & SYSCON_EMCSYSCTRL_EMCBC_MASK)
-#define SYSCON_EMCSYSCTRL_EMCFBCLKINSEL_MASK (0x8U)
-#define SYSCON_EMCSYSCTRL_EMCFBCLKINSEL_SHIFT (3U)
-#define SYSCON_EMCSYSCTRL_EMCFBCLKINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCSYSCTRL_EMCFBCLKINSEL_SHIFT)) & SYSCON_EMCSYSCTRL_EMCFBCLKINSEL_MASK)
-
-/*! @name EMCDLYCTRL - EMC clock delay control */
-#define SYSCON_EMCDLYCTRL_CMD_DELAY_MASK (0x1FU)
-#define SYSCON_EMCDLYCTRL_CMD_DELAY_SHIFT (0U)
-#define SYSCON_EMCDLYCTRL_CMD_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCDLYCTRL_CMD_DELAY_SHIFT)) & SYSCON_EMCDLYCTRL_CMD_DELAY_MASK)
-#define SYSCON_EMCDLYCTRL_FBCLK_DELAY_MASK (0x1F00U)
-#define SYSCON_EMCDLYCTRL_FBCLK_DELAY_SHIFT (8U)
-#define SYSCON_EMCDLYCTRL_FBCLK_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCDLYCTRL_FBCLK_DELAY_SHIFT)) & SYSCON_EMCDLYCTRL_FBCLK_DELAY_MASK)
-
-/*! @name EMCDLYCAL - EMC delay chain calibration control */
-#define SYSCON_EMCDLYCAL_CALVALUE_MASK (0xFFU)
-#define SYSCON_EMCDLYCAL_CALVALUE_SHIFT (0U)
-#define SYSCON_EMCDLYCAL_CALVALUE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCDLYCAL_CALVALUE_SHIFT)) & SYSCON_EMCDLYCAL_CALVALUE_MASK)
-#define SYSCON_EMCDLYCAL_START_MASK (0x4000U)
-#define SYSCON_EMCDLYCAL_START_SHIFT (14U)
-#define SYSCON_EMCDLYCAL_START(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCDLYCAL_START_SHIFT)) & SYSCON_EMCDLYCAL_START_MASK)
-#define SYSCON_EMCDLYCAL_DONE_MASK (0x8000U)
-#define SYSCON_EMCDLYCAL_DONE_SHIFT (15U)
-#define SYSCON_EMCDLYCAL_DONE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCDLYCAL_DONE_SHIFT)) & SYSCON_EMCDLYCAL_DONE_MASK)
-
-/*! @name ETHPHYSEL - Ethernet PHY Selection */
-#define SYSCON_ETHPHYSEL_PHY_SEL_MASK (0x4U)
-#define SYSCON_ETHPHYSEL_PHY_SEL_SHIFT (2U)
-#define SYSCON_ETHPHYSEL_PHY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ETHPHYSEL_PHY_SEL_SHIFT)) & SYSCON_ETHPHYSEL_PHY_SEL_MASK)
-
-/*! @name ETHSBDCTRL - Ethernet SBD flow control */
-#define SYSCON_ETHSBDCTRL_SBD_CTRL_MASK (0x3U)
-#define SYSCON_ETHSBDCTRL_SBD_CTRL_SHIFT (0U)
-#define SYSCON_ETHSBDCTRL_SBD_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ETHSBDCTRL_SBD_CTRL_SHIFT)) & SYSCON_ETHSBDCTRL_SBD_CTRL_MASK)
-
-/*! @name SDIOCLKCTRL - SDIO CCLKIN phase and delay control */
-#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK (0x3U)
-#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT (0U)
-#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK)
-#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (0xCU)
-#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT (2U)
-#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK)
-#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK (0x80U)
-#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT (7U)
-#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK)
-#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK (0x1F0000U)
-#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT (16U)
-#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK)
-#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK (0x800000U)
-#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT (23U)
-#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK)
-#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK (0x1F000000U)
-#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT (24U)
-#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK)
-#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK (0x80000000U)
-#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT (31U)
-#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK)
-
-/*! @name FROCTRL - FRO oscillator control */
-#define SYSCON_FROCTRL_TRIM_MASK (0x3FFFU)
-#define SYSCON_FROCTRL_TRIM_SHIFT (0U)
-#define SYSCON_FROCTRL_TRIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_TRIM_SHIFT)) & SYSCON_FROCTRL_TRIM_MASK)
-#define SYSCON_FROCTRL_SEL_MASK (0x4000U)
-#define SYSCON_FROCTRL_SEL_SHIFT (14U)
-#define SYSCON_FROCTRL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_SEL_SHIFT)) & SYSCON_FROCTRL_SEL_MASK)
-#define SYSCON_FROCTRL_FREQTRIM_MASK (0xFF0000U)
-#define SYSCON_FROCTRL_FREQTRIM_SHIFT (16U)
-#define SYSCON_FROCTRL_FREQTRIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_FREQTRIM_SHIFT)) & SYSCON_FROCTRL_FREQTRIM_MASK)
-#define SYSCON_FROCTRL_USBCLKADJ_MASK (0x1000000U)
-#define SYSCON_FROCTRL_USBCLKADJ_SHIFT (24U)
-#define SYSCON_FROCTRL_USBCLKADJ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_USBCLKADJ_SHIFT)) & SYSCON_FROCTRL_USBCLKADJ_MASK)
-#define SYSCON_FROCTRL_USBMODCHG_MASK (0x2000000U)
-#define SYSCON_FROCTRL_USBMODCHG_SHIFT (25U)
-#define SYSCON_FROCTRL_USBMODCHG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_USBMODCHG_SHIFT)) & SYSCON_FROCTRL_USBMODCHG_MASK)
-#define SYSCON_FROCTRL_HSPDCLK_MASK (0x40000000U)
-#define SYSCON_FROCTRL_HSPDCLK_SHIFT (30U)
-#define SYSCON_FROCTRL_HSPDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_HSPDCLK_SHIFT)) & SYSCON_FROCTRL_HSPDCLK_MASK)
-#define SYSCON_FROCTRL_WRTRIM_MASK (0x80000000U)
-#define SYSCON_FROCTRL_WRTRIM_SHIFT (31U)
-#define SYSCON_FROCTRL_WRTRIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_WRTRIM_SHIFT)) & SYSCON_FROCTRL_WRTRIM_MASK)
-
-/*! @name SYSOSCCTRL - System oscillator control */
-#define SYSCON_SYSOSCCTRL_BYPASS_MASK (0x1U)
-#define SYSCON_SYSOSCCTRL_BYPASS_SHIFT (0U)
-#define SYSCON_SYSOSCCTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSOSCCTRL_BYPASS_SHIFT)) & SYSCON_SYSOSCCTRL_BYPASS_MASK)
-#define SYSCON_SYSOSCCTRL_FREQRANGE_MASK (0x2U)
-#define SYSCON_SYSOSCCTRL_FREQRANGE_SHIFT (1U)
-#define SYSCON_SYSOSCCTRL_FREQRANGE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSOSCCTRL_FREQRANGE_SHIFT)) & SYSCON_SYSOSCCTRL_FREQRANGE_MASK)
-
-/*! @name WDTOSCCTRL - Watchdog oscillator control */
-#define SYSCON_WDTOSCCTRL_DIVSEL_MASK (0x1FU)
-#define SYSCON_WDTOSCCTRL_DIVSEL_SHIFT (0U)
-#define SYSCON_WDTOSCCTRL_DIVSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_DIVSEL_SHIFT)) & SYSCON_WDTOSCCTRL_DIVSEL_MASK)
-#define SYSCON_WDTOSCCTRL_FREQSEL_MASK (0x3E0U)
-#define SYSCON_WDTOSCCTRL_FREQSEL_SHIFT (5U)
-#define SYSCON_WDTOSCCTRL_FREQSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)) & SYSCON_WDTOSCCTRL_FREQSEL_MASK)
-
-/*! @name RTCOSCCTRL - RTC oscillator 32 kHz output control */
-#define SYSCON_RTCOSCCTRL_EN_MASK (0x1U)
-#define SYSCON_RTCOSCCTRL_EN_SHIFT (0U)
-#define SYSCON_RTCOSCCTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_RTCOSCCTRL_EN_SHIFT)) & SYSCON_RTCOSCCTRL_EN_MASK)
-
-/*! @name USBPLLCTRL - USB PLL control */
-#define SYSCON_USBPLLCTRL_MSEL_MASK (0xFFU)
-#define SYSCON_USBPLLCTRL_MSEL_SHIFT (0U)
-#define SYSCON_USBPLLCTRL_MSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_MSEL_SHIFT)) & SYSCON_USBPLLCTRL_MSEL_MASK)
-#define SYSCON_USBPLLCTRL_PSEL_MASK (0x300U)
-#define SYSCON_USBPLLCTRL_PSEL_SHIFT (8U)
-#define SYSCON_USBPLLCTRL_PSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_PSEL_SHIFT)) & SYSCON_USBPLLCTRL_PSEL_MASK)
-#define SYSCON_USBPLLCTRL_NSEL_MASK (0xC00U)
-#define SYSCON_USBPLLCTRL_NSEL_SHIFT (10U)
-#define SYSCON_USBPLLCTRL_NSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_NSEL_SHIFT)) & SYSCON_USBPLLCTRL_NSEL_MASK)
-#define SYSCON_USBPLLCTRL_DIRECT_MASK (0x1000U)
-#define SYSCON_USBPLLCTRL_DIRECT_SHIFT (12U)
-#define SYSCON_USBPLLCTRL_DIRECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_DIRECT_SHIFT)) & SYSCON_USBPLLCTRL_DIRECT_MASK)
-#define SYSCON_USBPLLCTRL_BYPASS_MASK (0x2000U)
-#define SYSCON_USBPLLCTRL_BYPASS_SHIFT (13U)
-#define SYSCON_USBPLLCTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_BYPASS_SHIFT)) & SYSCON_USBPLLCTRL_BYPASS_MASK)
-#define SYSCON_USBPLLCTRL_FBSEL_MASK (0x4000U)
-#define SYSCON_USBPLLCTRL_FBSEL_SHIFT (14U)
-#define SYSCON_USBPLLCTRL_FBSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_FBSEL_SHIFT)) & SYSCON_USBPLLCTRL_FBSEL_MASK)
-
-/*! @name USBPLLSTAT - USB PLL status */
-#define SYSCON_USBPLLSTAT_LOCK_MASK (0x1U)
-#define SYSCON_USBPLLSTAT_LOCK_SHIFT (0U)
-#define SYSCON_USBPLLSTAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLSTAT_LOCK_SHIFT)) & SYSCON_USBPLLSTAT_LOCK_MASK)
-
-/*! @name SYSPLLCTRL - System PLL control */
-#define SYSCON_SYSPLLCTRL_SELR_MASK (0xFU)
-#define SYSCON_SYSPLLCTRL_SELR_SHIFT (0U)
-#define SYSCON_SYSPLLCTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELR_SHIFT)) & SYSCON_SYSPLLCTRL_SELR_MASK)
-#define SYSCON_SYSPLLCTRL_SELI_MASK (0x3F0U)
-#define SYSCON_SYSPLLCTRL_SELI_SHIFT (4U)
-#define SYSCON_SYSPLLCTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELI_SHIFT)) & SYSCON_SYSPLLCTRL_SELI_MASK)
-#define SYSCON_SYSPLLCTRL_SELP_MASK (0x7C00U)
-#define SYSCON_SYSPLLCTRL_SELP_SHIFT (10U)
-#define SYSCON_SYSPLLCTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELP_SHIFT)) & SYSCON_SYSPLLCTRL_SELP_MASK)
-#define SYSCON_SYSPLLCTRL_BYPASS_MASK (0x8000U)
-#define SYSCON_SYSPLLCTRL_BYPASS_SHIFT (15U)
-#define SYSCON_SYSPLLCTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_BYPASS_SHIFT)) & SYSCON_SYSPLLCTRL_BYPASS_MASK)
-#define SYSCON_SYSPLLCTRL_UPLIMOFF_MASK (0x20000U)
-#define SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT (17U)
-#define SYSCON_SYSPLLCTRL_UPLIMOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT)) & SYSCON_SYSPLLCTRL_UPLIMOFF_MASK)
-#define SYSCON_SYSPLLCTRL_DIRECTI_MASK (0x80000U)
-#define SYSCON_SYSPLLCTRL_DIRECTI_SHIFT (19U)
-#define SYSCON_SYSPLLCTRL_DIRECTI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_DIRECTI_SHIFT)) & SYSCON_SYSPLLCTRL_DIRECTI_MASK)
-#define SYSCON_SYSPLLCTRL_DIRECTO_MASK (0x100000U)
-#define SYSCON_SYSPLLCTRL_DIRECTO_SHIFT (20U)
-#define SYSCON_SYSPLLCTRL_DIRECTO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_DIRECTO_SHIFT)) & SYSCON_SYSPLLCTRL_DIRECTO_MASK)
-
-/*! @name SYSPLLSTAT - PLL status */
-#define SYSCON_SYSPLLSTAT_LOCK_MASK (0x1U)
-#define SYSCON_SYSPLLSTAT_LOCK_SHIFT (0U)
-#define SYSCON_SYSPLLSTAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSTAT_LOCK_SHIFT)) & SYSCON_SYSPLLSTAT_LOCK_MASK)
-
-/*! @name SYSPLLNDEC - PLL N divider */
-#define SYSCON_SYSPLLNDEC_NDEC_MASK (0x3FFU)
-#define SYSCON_SYSPLLNDEC_NDEC_SHIFT (0U)
-#define SYSCON_SYSPLLNDEC_NDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLNDEC_NDEC_SHIFT)) & SYSCON_SYSPLLNDEC_NDEC_MASK)
-#define SYSCON_SYSPLLNDEC_NREQ_MASK (0x400U)
-#define SYSCON_SYSPLLNDEC_NREQ_SHIFT (10U)
-#define SYSCON_SYSPLLNDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLNDEC_NREQ_SHIFT)) & SYSCON_SYSPLLNDEC_NREQ_MASK)
-
-/*! @name SYSPLLPDEC - PLL P divider */
-#define SYSCON_SYSPLLPDEC_PDEC_MASK (0x7FU)
-#define SYSCON_SYSPLLPDEC_PDEC_SHIFT (0U)
-#define SYSCON_SYSPLLPDEC_PDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLPDEC_PDEC_SHIFT)) & SYSCON_SYSPLLPDEC_PDEC_MASK)
-#define SYSCON_SYSPLLPDEC_PREQ_MASK (0x80U)
-#define SYSCON_SYSPLLPDEC_PREQ_SHIFT (7U)
-#define SYSCON_SYSPLLPDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLPDEC_PREQ_SHIFT)) & SYSCON_SYSPLLPDEC_PREQ_MASK)
-
-/*! @name SYSPLLMDEC - System PLL M divider */
-#define SYSCON_SYSPLLMDEC_MDEC_MASK (0x1FFFFU)
-#define SYSCON_SYSPLLMDEC_MDEC_SHIFT (0U)
-#define SYSCON_SYSPLLMDEC_MDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLMDEC_MDEC_SHIFT)) & SYSCON_SYSPLLMDEC_MDEC_MASK)
-#define SYSCON_SYSPLLMDEC_MREQ_MASK (0x20000U)
-#define SYSCON_SYSPLLMDEC_MREQ_SHIFT (17U)
-#define SYSCON_SYSPLLMDEC_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLMDEC_MREQ_SHIFT)) & SYSCON_SYSPLLMDEC_MREQ_MASK)
-
-/*! @name AUDPLLCTRL - Audio PLL control */
-#define SYSCON_AUDPLLCTRL_SELR_MASK (0xFU)
-#define SYSCON_AUDPLLCTRL_SELR_SHIFT (0U)
-#define SYSCON_AUDPLLCTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_SELR_SHIFT)) & SYSCON_AUDPLLCTRL_SELR_MASK)
-#define SYSCON_AUDPLLCTRL_SELI_MASK (0x3F0U)
-#define SYSCON_AUDPLLCTRL_SELI_SHIFT (4U)
-#define SYSCON_AUDPLLCTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_SELI_SHIFT)) & SYSCON_AUDPLLCTRL_SELI_MASK)
-#define SYSCON_AUDPLLCTRL_SELP_MASK (0x7C00U)
-#define SYSCON_AUDPLLCTRL_SELP_SHIFT (10U)
-#define SYSCON_AUDPLLCTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_SELP_SHIFT)) & SYSCON_AUDPLLCTRL_SELP_MASK)
-#define SYSCON_AUDPLLCTRL_BYPASS_MASK (0x8000U)
-#define SYSCON_AUDPLLCTRL_BYPASS_SHIFT (15U)
-#define SYSCON_AUDPLLCTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_BYPASS_SHIFT)) & SYSCON_AUDPLLCTRL_BYPASS_MASK)
-#define SYSCON_AUDPLLCTRL_UPLIMOFF_MASK (0x20000U)
-#define SYSCON_AUDPLLCTRL_UPLIMOFF_SHIFT (17U)
-#define SYSCON_AUDPLLCTRL_UPLIMOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_UPLIMOFF_SHIFT)) & SYSCON_AUDPLLCTRL_UPLIMOFF_MASK)
-#define SYSCON_AUDPLLCTRL_DIRECTI_MASK (0x80000U)
-#define SYSCON_AUDPLLCTRL_DIRECTI_SHIFT (19U)
-#define SYSCON_AUDPLLCTRL_DIRECTI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_DIRECTI_SHIFT)) & SYSCON_AUDPLLCTRL_DIRECTI_MASK)
-#define SYSCON_AUDPLLCTRL_DIRECTO_MASK (0x100000U)
-#define SYSCON_AUDPLLCTRL_DIRECTO_SHIFT (20U)
-#define SYSCON_AUDPLLCTRL_DIRECTO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_DIRECTO_SHIFT)) & SYSCON_AUDPLLCTRL_DIRECTO_MASK)
-
-/*! @name AUDPLLSTAT - Audio PLL status */
-#define SYSCON_AUDPLLSTAT_LOCK_MASK (0x1U)
-#define SYSCON_AUDPLLSTAT_LOCK_SHIFT (0U)
-#define SYSCON_AUDPLLSTAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLSTAT_LOCK_SHIFT)) & SYSCON_AUDPLLSTAT_LOCK_MASK)
-
-/*! @name AUDPLLNDEC - Audio PLL N divider */
-#define SYSCON_AUDPLLNDEC_NDEC_MASK (0x3FFU)
-#define SYSCON_AUDPLLNDEC_NDEC_SHIFT (0U)
-#define SYSCON_AUDPLLNDEC_NDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLNDEC_NDEC_SHIFT)) & SYSCON_AUDPLLNDEC_NDEC_MASK)
-#define SYSCON_AUDPLLNDEC_NREQ_MASK (0x400U)
-#define SYSCON_AUDPLLNDEC_NREQ_SHIFT (10U)
-#define SYSCON_AUDPLLNDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLNDEC_NREQ_SHIFT)) & SYSCON_AUDPLLNDEC_NREQ_MASK)
-
-/*! @name AUDPLLPDEC - Audio PLL P divider */
-#define SYSCON_AUDPLLPDEC_PDEC_MASK (0x7FU)
-#define SYSCON_AUDPLLPDEC_PDEC_SHIFT (0U)
-#define SYSCON_AUDPLLPDEC_PDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLPDEC_PDEC_SHIFT)) & SYSCON_AUDPLLPDEC_PDEC_MASK)
-#define SYSCON_AUDPLLPDEC_PREQ_MASK (0x80U)
-#define SYSCON_AUDPLLPDEC_PREQ_SHIFT (7U)
-#define SYSCON_AUDPLLPDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLPDEC_PREQ_SHIFT)) & SYSCON_AUDPLLPDEC_PREQ_MASK)
-
-/*! @name AUDPLLMDEC - Audio PLL M divider */
-#define SYSCON_AUDPLLMDEC_MDEC_MASK (0x1FFFFU)
-#define SYSCON_AUDPLLMDEC_MDEC_SHIFT (0U)
-#define SYSCON_AUDPLLMDEC_MDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLMDEC_MDEC_SHIFT)) & SYSCON_AUDPLLMDEC_MDEC_MASK)
-#define SYSCON_AUDPLLMDEC_MREQ_MASK (0x20000U)
-#define SYSCON_AUDPLLMDEC_MREQ_SHIFT (17U)
-#define SYSCON_AUDPLLMDEC_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLMDEC_MREQ_SHIFT)) & SYSCON_AUDPLLMDEC_MREQ_MASK)
-
-/*! @name AUDPLLFRAC - Audio PLL fractional divider control */
-#define SYSCON_AUDPLLFRAC_CTRL_MASK (0x3FFFFFU)
-#define SYSCON_AUDPLLFRAC_CTRL_SHIFT (0U)
-#define SYSCON_AUDPLLFRAC_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLFRAC_CTRL_SHIFT)) & SYSCON_AUDPLLFRAC_CTRL_MASK)
-#define SYSCON_AUDPLLFRAC_REQ_MASK (0x400000U)
-#define SYSCON_AUDPLLFRAC_REQ_SHIFT (22U)
-#define SYSCON_AUDPLLFRAC_REQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLFRAC_REQ_SHIFT)) & SYSCON_AUDPLLFRAC_REQ_MASK)
-#define SYSCON_AUDPLLFRAC_SEL_EXT_MASK (0x800000U)
-#define SYSCON_AUDPLLFRAC_SEL_EXT_SHIFT (23U)
-#define SYSCON_AUDPLLFRAC_SEL_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLFRAC_SEL_EXT_SHIFT)) & SYSCON_AUDPLLFRAC_SEL_EXT_MASK)
-
-/*! @name PDSLEEPCFG - Power configuration register 0 */
-#define SYSCON_PDSLEEPCFG_PDEN_USB1_PHY_MASK (0x1U)
-#define SYSCON_PDSLEEPCFG_PDEN_USB1_PHY_SHIFT (0U)
-#define SYSCON_PDSLEEPCFG_PDEN_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_USB1_PHY_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_USB1_PHY_MASK)
-#define SYSCON_PDSLEEPCFG_PDEN_USB1_PLL_MASK (0x2U)
-#define SYSCON_PDSLEEPCFG_PDEN_USB1_PLL_SHIFT (1U)
-#define SYSCON_PDSLEEPCFG_PDEN_USB1_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_USB1_PLL_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_USB1_PLL_MASK)
-#define SYSCON_PDSLEEPCFG_PDEN_AUD_PLL_MASK (0x4U)
-#define SYSCON_PDSLEEPCFG_PDEN_AUD_PLL_SHIFT (2U)
-#define SYSCON_PDSLEEPCFG_PDEN_AUD_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_AUD_PLL_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_AUD_PLL_MASK)
-#define SYSCON_PDSLEEPCFG_PDEN_SYSOSC_MASK (0x8U)
-#define SYSCON_PDSLEEPCFG_PDEN_SYSOSC_SHIFT (3U)
-#define SYSCON_PDSLEEPCFG_PDEN_SYSOSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SYSOSC_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SYSOSC_MASK)
-#define SYSCON_PDSLEEPCFG_PDEN_FRO_MASK (0x10U)
-#define SYSCON_PDSLEEPCFG_PDEN_FRO_SHIFT (4U)
-#define SYSCON_PDSLEEPCFG_PDEN_FRO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_FRO_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_FRO_MASK)
-#define SYSCON_PDSLEEPCFG_PDEN_EEPROM_MASK (0x20U)
-#define SYSCON_PDSLEEPCFG_PDEN_EEPROM_SHIFT (5U)
-#define SYSCON_PDSLEEPCFG_PDEN_EEPROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_EEPROM_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_EEPROM_MASK)
-#define SYSCON_PDSLEEPCFG_PDEN_TS_MASK (0x40U)
-#define SYSCON_PDSLEEPCFG_PDEN_TS_SHIFT (6U)
-#define SYSCON_PDSLEEPCFG_PDEN_TS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_TS_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_TS_MASK)
-#define SYSCON_PDSLEEPCFG_PDEN_BOD_RST_MASK (0x80U)
-#define SYSCON_PDSLEEPCFG_PDEN_BOD_RST_SHIFT (7U)
-#define SYSCON_PDSLEEPCFG_PDEN_BOD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_BOD_RST_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_BOD_RST_MASK)
-#define SYSCON_PDSLEEPCFG_PDEN_RNG_MASK (0x80U)
-#define SYSCON_PDSLEEPCFG_PDEN_RNG_SHIFT (7U)
-#define SYSCON_PDSLEEPCFG_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_RNG_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_RNG_MASK)
-#define SYSCON_PDSLEEPCFG_PDEN_BOD_INTR_MASK (0x100U)
-#define SYSCON_PDSLEEPCFG_PDEN_BOD_INTR_SHIFT (8U)
-#define SYSCON_PDSLEEPCFG_PDEN_BOD_INTR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_BOD_INTR_MASK)
-#define SYSCON_PDSLEEPCFG_PDEN_VD2_ANA_MASK (0x200U)
-#define SYSCON_PDSLEEPCFG_PDEN_VD2_ANA_SHIFT (9U)
-#define SYSCON_PDSLEEPCFG_PDEN_VD2_ANA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD2_ANA_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD2_ANA_MASK)
-#define SYSCON_PDSLEEPCFG_PDEN_ADC0_MASK (0x400U)
-#define SYSCON_PDSLEEPCFG_PDEN_ADC0_SHIFT (10U)
-#define SYSCON_PDSLEEPCFG_PDEN_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_ADC0_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_ADC0_MASK)
-#define SYSCON_PDSLEEPCFG_PDEN_SRAMX_MASK (0x2000U)
-#define SYSCON_PDSLEEPCFG_PDEN_SRAMX_SHIFT (13U)
-#define SYSCON_PDSLEEPCFG_PDEN_SRAMX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SRAMX_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SRAMX_MASK)
-#define SYSCON_PDSLEEPCFG_PDEN_SRAM0_MASK (0x4000U)
-#define SYSCON_PDSLEEPCFG_PDEN_SRAM0_SHIFT (14U)
-#define SYSCON_PDSLEEPCFG_PDEN_SRAM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SRAM0_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SRAM0_MASK)
-#define SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3_MASK (0x8000U)
-#define SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3_SHIFT (15U)
-#define SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3_MASK)
-#define SYSCON_PDSLEEPCFG_PDEN_USB_RAM_MASK (0x10000U)
-#define SYSCON_PDSLEEPCFG_PDEN_USB_RAM_SHIFT (16U)
-#define SYSCON_PDSLEEPCFG_PDEN_USB_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_USB_RAM_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_USB_RAM_MASK)
-#define SYSCON_PDSLEEPCFG_PDEN_ROM_MASK (0x20000U)
-#define SYSCON_PDSLEEPCFG_PDEN_ROM_SHIFT (17U)
-#define SYSCON_PDSLEEPCFG_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_ROM_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_ROM_MASK)
-#define SYSCON_PDSLEEPCFG_PDEN_VDDA_MASK (0x80000U)
-#define SYSCON_PDSLEEPCFG_PDEN_VDDA_SHIFT (19U)
-#define SYSCON_PDSLEEPCFG_PDEN_VDDA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VDDA_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VDDA_MASK)
-#define SYSCON_PDSLEEPCFG_PDEN_WDT_OSC_MASK (0x100000U)
-#define SYSCON_PDSLEEPCFG_PDEN_WDT_OSC_SHIFT (20U)
-#define SYSCON_PDSLEEPCFG_PDEN_WDT_OSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_WDT_OSC_MASK)
-#define SYSCON_PDSLEEPCFG_PDEN_USB0_PHY_MASK (0x200000U)
-#define SYSCON_PDSLEEPCFG_PDEN_USB0_PHY_SHIFT (21U)
-#define SYSCON_PDSLEEPCFG_PDEN_USB0_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_USB0_PHY_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_USB0_PHY_MASK)
-#define SYSCON_PDSLEEPCFG_PDEN_SYS_PLL_MASK (0x400000U)
-#define SYSCON_PDSLEEPCFG_PDEN_SYS_PLL_SHIFT (22U)
-#define SYSCON_PDSLEEPCFG_PDEN_SYS_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SYS_PLL_MASK)
-#define SYSCON_PDSLEEPCFG_PDEN_VREFP_MASK (0x800000U)
-#define SYSCON_PDSLEEPCFG_PDEN_VREFP_SHIFT (23U)
-#define SYSCON_PDSLEEPCFG_PDEN_VREFP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VREFP_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VREFP_MASK)
-#define SYSCON_PDSLEEPCFG_PDEN_VD3_MASK (0x4000000U)
-#define SYSCON_PDSLEEPCFG_PDEN_VD3_SHIFT (26U)
-#define SYSCON_PDSLEEPCFG_PDEN_VD3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD3_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD3_MASK)
-#define SYSCON_PDSLEEPCFG_PDEN_VD4_MASK (0x8000000U)
-#define SYSCON_PDSLEEPCFG_PDEN_VD4_SHIFT (27U)
-#define SYSCON_PDSLEEPCFG_PDEN_VD4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD4_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD4_MASK)
-#define SYSCON_PDSLEEPCFG_PDEN_VD5_MASK (0x10000000U)
-#define SYSCON_PDSLEEPCFG_PDEN_VD5_SHIFT (28U)
-#define SYSCON_PDSLEEPCFG_PDEN_VD5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD5_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD5_MASK)
-#define SYSCON_PDSLEEPCFG_PDEN_VD6_MASK (0x20000000U)
-#define SYSCON_PDSLEEPCFG_PDEN_VD6_SHIFT (29U)
-#define SYSCON_PDSLEEPCFG_PDEN_VD6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD6_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD6_MASK)
-
-/* The count of SYSCON_PDSLEEPCFG */
-#define SYSCON_PDSLEEPCFG_COUNT (2U)
-
-/*! @name PDRUNCFG - Power configuration register 0 */
-#define SYSCON_PDRUNCFG_PDEN_USB1_PHY_MASK (0x1U)
-#define SYSCON_PDRUNCFG_PDEN_USB1_PHY_SHIFT (0U)
-#define SYSCON_PDRUNCFG_PDEN_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB1_PHY_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB1_PHY_MASK)
-#define SYSCON_PDRUNCFG_PDEN_USB1_PLL_MASK (0x2U)
-#define SYSCON_PDRUNCFG_PDEN_USB1_PLL_SHIFT (1U)
-#define SYSCON_PDRUNCFG_PDEN_USB1_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB1_PLL_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB1_PLL_MASK)
-#define SYSCON_PDRUNCFG_PDEN_AUD_PLL_MASK (0x4U)
-#define SYSCON_PDRUNCFG_PDEN_AUD_PLL_SHIFT (2U)
-#define SYSCON_PDRUNCFG_PDEN_AUD_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_AUD_PLL_SHIFT)) & SYSCON_PDRUNCFG_PDEN_AUD_PLL_MASK)
-#define SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK (0x8U)
-#define SYSCON_PDRUNCFG_PDEN_SYSOSC_SHIFT (3U)
-#define SYSCON_PDRUNCFG_PDEN_SYSOSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SYSOSC_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK)
-#define SYSCON_PDRUNCFG_PDEN_FRO_MASK (0x10U)
-#define SYSCON_PDRUNCFG_PDEN_FRO_SHIFT (4U)
-#define SYSCON_PDRUNCFG_PDEN_FRO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_FRO_SHIFT)) & SYSCON_PDRUNCFG_PDEN_FRO_MASK)
-#define SYSCON_PDRUNCFG_PDEN_EEPROM_MASK (0x20U)
-#define SYSCON_PDRUNCFG_PDEN_EEPROM_SHIFT (5U)
-#define SYSCON_PDRUNCFG_PDEN_EEPROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_EEPROM_SHIFT)) & SYSCON_PDRUNCFG_PDEN_EEPROM_MASK)
-#define SYSCON_PDRUNCFG_PDEN_TS_MASK (0x40U)
-#define SYSCON_PDRUNCFG_PDEN_TS_SHIFT (6U)
-#define SYSCON_PDRUNCFG_PDEN_TS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_TS_SHIFT)) & SYSCON_PDRUNCFG_PDEN_TS_MASK)
-#define SYSCON_PDRUNCFG_PDEN_BOD_RST_MASK (0x80U)
-#define SYSCON_PDRUNCFG_PDEN_BOD_RST_SHIFT (7U)
-#define SYSCON_PDRUNCFG_PDEN_BOD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_BOD_RST_SHIFT)) & SYSCON_PDRUNCFG_PDEN_BOD_RST_MASK)
-#define SYSCON_PDRUNCFG_PDEN_RNG_MASK (0x80U)
-#define SYSCON_PDRUNCFG_PDEN_RNG_SHIFT (7U)
-#define SYSCON_PDRUNCFG_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_RNG_SHIFT)) & SYSCON_PDRUNCFG_PDEN_RNG_MASK)
-#define SYSCON_PDRUNCFG_PDEN_BOD_INTR_MASK (0x100U)
-#define SYSCON_PDRUNCFG_PDEN_BOD_INTR_SHIFT (8U)
-#define SYSCON_PDRUNCFG_PDEN_BOD_INTR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDRUNCFG_PDEN_BOD_INTR_MASK)
-#define SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK (0x200U)
-#define SYSCON_PDRUNCFG_PDEN_VD2_ANA_SHIFT (9U)
-#define SYSCON_PDRUNCFG_PDEN_VD2_ANA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD2_ANA_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK)
-#define SYSCON_PDRUNCFG_PDEN_ADC0_MASK (0x400U)
-#define SYSCON_PDRUNCFG_PDEN_ADC0_SHIFT (10U)
-#define SYSCON_PDRUNCFG_PDEN_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_ADC0_SHIFT)) & SYSCON_PDRUNCFG_PDEN_ADC0_MASK)
-#define SYSCON_PDRUNCFG_PDEN_SRAMX_MASK (0x2000U)
-#define SYSCON_PDRUNCFG_PDEN_SRAMX_SHIFT (13U)
-#define SYSCON_PDRUNCFG_PDEN_SRAMX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAMX_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAMX_MASK)
-#define SYSCON_PDRUNCFG_PDEN_SRAM0_MASK (0x4000U)
-#define SYSCON_PDRUNCFG_PDEN_SRAM0_SHIFT (14U)
-#define SYSCON_PDRUNCFG_PDEN_SRAM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAM0_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAM0_MASK)
-#define SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_MASK (0x8000U)
-#define SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_SHIFT (15U)
-#define SYSCON_PDRUNCFG_PDEN_SRAM1_2_3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_MASK)
-#define SYSCON_PDRUNCFG_PDEN_USB_RAM_MASK (0x10000U)
-#define SYSCON_PDRUNCFG_PDEN_USB_RAM_SHIFT (16U)
-#define SYSCON_PDRUNCFG_PDEN_USB_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB_RAM_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB_RAM_MASK)
-#define SYSCON_PDRUNCFG_PDEN_ROM_MASK (0x20000U)
-#define SYSCON_PDRUNCFG_PDEN_ROM_SHIFT (17U)
-#define SYSCON_PDRUNCFG_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_ROM_SHIFT)) & SYSCON_PDRUNCFG_PDEN_ROM_MASK)
-#define SYSCON_PDRUNCFG_PDEN_VDDA_MASK (0x80000U)
-#define SYSCON_PDRUNCFG_PDEN_VDDA_SHIFT (19U)
-#define SYSCON_PDRUNCFG_PDEN_VDDA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VDDA_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VDDA_MASK)
-#define SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK (0x100000U)
-#define SYSCON_PDRUNCFG_PDEN_WDT_OSC_SHIFT (20U)
-#define SYSCON_PDRUNCFG_PDEN_WDT_OSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK)
-#define SYSCON_PDRUNCFG_PDEN_USB0_PHY_MASK (0x200000U)
-#define SYSCON_PDRUNCFG_PDEN_USB0_PHY_SHIFT (21U)
-#define SYSCON_PDRUNCFG_PDEN_USB0_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB0_PHY_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB0_PHY_MASK)
-#define SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK (0x400000U)
-#define SYSCON_PDRUNCFG_PDEN_SYS_PLL_SHIFT (22U)
-#define SYSCON_PDRUNCFG_PDEN_SYS_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK)
-#define SYSCON_PDRUNCFG_PDEN_VREFP_MASK (0x800000U)
-#define SYSCON_PDRUNCFG_PDEN_VREFP_SHIFT (23U)
-#define SYSCON_PDRUNCFG_PDEN_VREFP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VREFP_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VREFP_MASK)
-#define SYSCON_PDRUNCFG_PDEN_VD3_MASK (0x4000000U)
-#define SYSCON_PDRUNCFG_PDEN_VD3_SHIFT (26U)
-#define SYSCON_PDRUNCFG_PDEN_VD3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD3_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD3_MASK)
-#define SYSCON_PDRUNCFG_PDEN_VD4_MASK (0x8000000U)
-#define SYSCON_PDRUNCFG_PDEN_VD4_SHIFT (27U)
-#define SYSCON_PDRUNCFG_PDEN_VD4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD4_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD4_MASK)
-#define SYSCON_PDRUNCFG_PDEN_VD5_MASK (0x10000000U)
-#define SYSCON_PDRUNCFG_PDEN_VD5_SHIFT (28U)
-#define SYSCON_PDRUNCFG_PDEN_VD5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD5_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD5_MASK)
-#define SYSCON_PDRUNCFG_PDEN_VD6_MASK (0x20000000U)
-#define SYSCON_PDRUNCFG_PDEN_VD6_SHIFT (29U)
-#define SYSCON_PDRUNCFG_PDEN_VD6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD6_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD6_MASK)
-
-/* The count of SYSCON_PDRUNCFG */
-#define SYSCON_PDRUNCFG_COUNT (2U)
-
-/*! @name PDRUNCFGSET - Set bits in PDRUNCFG0 */
-#define SYSCON_PDRUNCFGSET_PDEN_USB1_PHY_MASK (0x1U)
-#define SYSCON_PDRUNCFGSET_PDEN_USB1_PHY_SHIFT (0U)
-#define SYSCON_PDRUNCFGSET_PDEN_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_USB1_PHY_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_USB1_PHY_MASK)
-#define SYSCON_PDRUNCFGSET_PDEN_USB1_PLL_MASK (0x2U)
-#define SYSCON_PDRUNCFGSET_PDEN_USB1_PLL_SHIFT (1U)
-#define SYSCON_PDRUNCFGSET_PDEN_USB1_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_USB1_PLL_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_USB1_PLL_MASK)
-#define SYSCON_PDRUNCFGSET_PDEN_AUD_PLL_MASK (0x4U)
-#define SYSCON_PDRUNCFGSET_PDEN_AUD_PLL_SHIFT (2U)
-#define SYSCON_PDRUNCFGSET_PDEN_AUD_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_AUD_PLL_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_AUD_PLL_MASK)
-#define SYSCON_PDRUNCFGSET_PDEN_SYSOSC_MASK (0x8U)
-#define SYSCON_PDRUNCFGSET_PDEN_SYSOSC_SHIFT (3U)
-#define SYSCON_PDRUNCFGSET_PDEN_SYSOSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SYSOSC_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SYSOSC_MASK)
-#define SYSCON_PDRUNCFGSET_PDEN_FRO_MASK (0x10U)
-#define SYSCON_PDRUNCFGSET_PDEN_FRO_SHIFT (4U)
-#define SYSCON_PDRUNCFGSET_PDEN_FRO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_FRO_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_FRO_MASK)
-#define SYSCON_PDRUNCFGSET_PDEN_EEPROM_MASK (0x20U)
-#define SYSCON_PDRUNCFGSET_PDEN_EEPROM_SHIFT (5U)
-#define SYSCON_PDRUNCFGSET_PDEN_EEPROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_EEPROM_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_EEPROM_MASK)
-#define SYSCON_PDRUNCFGSET_PDEN_TS_MASK (0x40U)
-#define SYSCON_PDRUNCFGSET_PDEN_TS_SHIFT (6U)
-#define SYSCON_PDRUNCFGSET_PDEN_TS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_TS_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_TS_MASK)
-#define SYSCON_PDRUNCFGSET_PDEN_BOD_RST_MASK (0x80U)
-#define SYSCON_PDRUNCFGSET_PDEN_BOD_RST_SHIFT (7U)
-#define SYSCON_PDRUNCFGSET_PDEN_BOD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_BOD_RST_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_BOD_RST_MASK)
-#define SYSCON_PDRUNCFGSET_PDEN_RNG_MASK (0x80U)
-#define SYSCON_PDRUNCFGSET_PDEN_RNG_SHIFT (7U)
-#define SYSCON_PDRUNCFGSET_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_RNG_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_RNG_MASK)
-#define SYSCON_PDRUNCFGSET_PDEN_BOD_INTR_MASK (0x100U)
-#define SYSCON_PDRUNCFGSET_PDEN_BOD_INTR_SHIFT (8U)
-#define SYSCON_PDRUNCFGSET_PDEN_BOD_INTR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_BOD_INTR_MASK)
-#define SYSCON_PDRUNCFGSET_PDEN_VD2_ANA_MASK (0x200U)
-#define SYSCON_PDRUNCFGSET_PDEN_VD2_ANA_SHIFT (9U)
-#define SYSCON_PDRUNCFGSET_PDEN_VD2_ANA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD2_ANA_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD2_ANA_MASK)
-#define SYSCON_PDRUNCFGSET_PDEN_ADC0_MASK (0x400U)
-#define SYSCON_PDRUNCFGSET_PDEN_ADC0_SHIFT (10U)
-#define SYSCON_PDRUNCFGSET_PDEN_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_ADC0_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_ADC0_MASK)
-#define SYSCON_PDRUNCFGSET_PDEN_SRAMX_MASK (0x2000U)
-#define SYSCON_PDRUNCFGSET_PDEN_SRAMX_SHIFT (13U)
-#define SYSCON_PDRUNCFGSET_PDEN_SRAMX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SRAMX_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SRAMX_MASK)
-#define SYSCON_PDRUNCFGSET_PDEN_SRAM0_MASK (0x4000U)
-#define SYSCON_PDRUNCFGSET_PDEN_SRAM0_SHIFT (14U)
-#define SYSCON_PDRUNCFGSET_PDEN_SRAM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SRAM0_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SRAM0_MASK)
-#define SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3_MASK (0x8000U)
-#define SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3_SHIFT (15U)
-#define SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3_MASK)
-#define SYSCON_PDRUNCFGSET_PDEN_USB_RAM_MASK (0x10000U)
-#define SYSCON_PDRUNCFGSET_PDEN_USB_RAM_SHIFT (16U)
-#define SYSCON_PDRUNCFGSET_PDEN_USB_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_USB_RAM_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_USB_RAM_MASK)
-#define SYSCON_PDRUNCFGSET_PDEN_ROM_MASK (0x20000U)
-#define SYSCON_PDRUNCFGSET_PDEN_ROM_SHIFT (17U)
-#define SYSCON_PDRUNCFGSET_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_ROM_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_ROM_MASK)
-#define SYSCON_PDRUNCFGSET_PDEN_VDDA_MASK (0x80000U)
-#define SYSCON_PDRUNCFGSET_PDEN_VDDA_SHIFT (19U)
-#define SYSCON_PDRUNCFGSET_PDEN_VDDA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VDDA_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VDDA_MASK)
-#define SYSCON_PDRUNCFGSET_PDEN_WDT_OSC_MASK (0x100000U)
-#define SYSCON_PDRUNCFGSET_PDEN_WDT_OSC_SHIFT (20U)
-#define SYSCON_PDRUNCFGSET_PDEN_WDT_OSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_WDT_OSC_MASK)
-#define SYSCON_PDRUNCFGSET_PDEN_USB0_PHY_MASK (0x200000U)
-#define SYSCON_PDRUNCFGSET_PDEN_USB0_PHY_SHIFT (21U)
-#define SYSCON_PDRUNCFGSET_PDEN_USB0_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_USB0_PHY_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_USB0_PHY_MASK)
-#define SYSCON_PDRUNCFGSET_PDEN_SYS_PLL_MASK (0x400000U)
-#define SYSCON_PDRUNCFGSET_PDEN_SYS_PLL_SHIFT (22U)
-#define SYSCON_PDRUNCFGSET_PDEN_SYS_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SYS_PLL_MASK)
-#define SYSCON_PDRUNCFGSET_PDEN_VREFP_MASK (0x800000U)
-#define SYSCON_PDRUNCFGSET_PDEN_VREFP_SHIFT (23U)
-#define SYSCON_PDRUNCFGSET_PDEN_VREFP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VREFP_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VREFP_MASK)
-#define SYSCON_PDRUNCFGSET_PDEN_VD3_MASK (0x4000000U)
-#define SYSCON_PDRUNCFGSET_PDEN_VD3_SHIFT (26U)
-#define SYSCON_PDRUNCFGSET_PDEN_VD3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD3_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD3_MASK)
-#define SYSCON_PDRUNCFGSET_PDEN_VD4_MASK (0x8000000U)
-#define SYSCON_PDRUNCFGSET_PDEN_VD4_SHIFT (27U)
-#define SYSCON_PDRUNCFGSET_PDEN_VD4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD4_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD4_MASK)
-#define SYSCON_PDRUNCFGSET_PDEN_VD5_MASK (0x10000000U)
-#define SYSCON_PDRUNCFGSET_PDEN_VD5_SHIFT (28U)
-#define SYSCON_PDRUNCFGSET_PDEN_VD5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD5_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD5_MASK)
-#define SYSCON_PDRUNCFGSET_PDEN_VD6_MASK (0x20000000U)
-#define SYSCON_PDRUNCFGSET_PDEN_VD6_SHIFT (29U)
-#define SYSCON_PDRUNCFGSET_PDEN_VD6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD6_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD6_MASK)
-
-/* The count of SYSCON_PDRUNCFGSET */
-#define SYSCON_PDRUNCFGSET_COUNT (2U)
-
-/*! @name PDRUNCFGCLR - Clear bits in PDRUNCFG0 */
-#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY_MASK (0x1U)
-#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY_SHIFT (0U)
-#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY_MASK)
-#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL_MASK (0x2U)
-#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL_SHIFT (1U)
-#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL_MASK)
-#define SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL_MASK (0x4U)
-#define SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL_SHIFT (2U)
-#define SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL_MASK)
-#define SYSCON_PDRUNCFGCLR_PDEN_SYSOSC_MASK (0x8U)
-#define SYSCON_PDRUNCFGCLR_PDEN_SYSOSC_SHIFT (3U)
-#define SYSCON_PDRUNCFGCLR_PDEN_SYSOSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SYSOSC_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SYSOSC_MASK)
-#define SYSCON_PDRUNCFGCLR_PDEN_FRO_MASK (0x10U)
-#define SYSCON_PDRUNCFGCLR_PDEN_FRO_SHIFT (4U)
-#define SYSCON_PDRUNCFGCLR_PDEN_FRO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_FRO_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_FRO_MASK)
-#define SYSCON_PDRUNCFGCLR_PDEN_EEPROM_MASK (0x20U)
-#define SYSCON_PDRUNCFGCLR_PDEN_EEPROM_SHIFT (5U)
-#define SYSCON_PDRUNCFGCLR_PDEN_EEPROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_EEPROM_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_EEPROM_MASK)
-#define SYSCON_PDRUNCFGCLR_PDEN_TS_MASK (0x40U)
-#define SYSCON_PDRUNCFGCLR_PDEN_TS_SHIFT (6U)
-#define SYSCON_PDRUNCFGCLR_PDEN_TS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_TS_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_TS_MASK)
-#define SYSCON_PDRUNCFGCLR_PDEN_BOD_RST_MASK (0x80U)
-#define SYSCON_PDRUNCFGCLR_PDEN_BOD_RST_SHIFT (7U)
-#define SYSCON_PDRUNCFGCLR_PDEN_BOD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_BOD_RST_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_BOD_RST_MASK)
-#define SYSCON_PDRUNCFGCLR_PDEN_RNG_MASK (0x80U)
-#define SYSCON_PDRUNCFGCLR_PDEN_RNG_SHIFT (7U)
-#define SYSCON_PDRUNCFGCLR_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_RNG_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_RNG_MASK)
-#define SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR_MASK (0x100U)
-#define SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR_SHIFT (8U)
-#define SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR_MASK)
-#define SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA_MASK (0x200U)
-#define SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA_SHIFT (9U)
-#define SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA_MASK)
-#define SYSCON_PDRUNCFGCLR_PDEN_ADC0_MASK (0x400U)
-#define SYSCON_PDRUNCFGCLR_PDEN_ADC0_SHIFT (10U)
-#define SYSCON_PDRUNCFGCLR_PDEN_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_ADC0_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_ADC0_MASK)
-#define SYSCON_PDRUNCFGCLR_PDEN_SRAMX_MASK (0x2000U)
-#define SYSCON_PDRUNCFGCLR_PDEN_SRAMX_SHIFT (13U)
-#define SYSCON_PDRUNCFGCLR_PDEN_SRAMX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SRAMX_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SRAMX_MASK)
-#define SYSCON_PDRUNCFGCLR_PDEN_SRAM0_MASK (0x4000U)
-#define SYSCON_PDRUNCFGCLR_PDEN_SRAM0_SHIFT (14U)
-#define SYSCON_PDRUNCFGCLR_PDEN_SRAM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SRAM0_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SRAM0_MASK)
-#define SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3_MASK (0x8000U)
-#define SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3_SHIFT (15U)
-#define SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3_MASK)
-#define SYSCON_PDRUNCFGCLR_PDEN_USB_RAM_MASK (0x10000U)
-#define SYSCON_PDRUNCFGCLR_PDEN_USB_RAM_SHIFT (16U)
-#define SYSCON_PDRUNCFGCLR_PDEN_USB_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_USB_RAM_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_USB_RAM_MASK)
-#define SYSCON_PDRUNCFGCLR_PDEN_ROM_MASK (0x20000U)
-#define SYSCON_PDRUNCFGCLR_PDEN_ROM_SHIFT (17U)
-#define SYSCON_PDRUNCFGCLR_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_ROM_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_ROM_MASK)
-#define SYSCON_PDRUNCFGCLR_PDEN_VDDA_MASK (0x80000U)
-#define SYSCON_PDRUNCFGCLR_PDEN_VDDA_SHIFT (19U)
-#define SYSCON_PDRUNCFGCLR_PDEN_VDDA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VDDA_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VDDA_MASK)
-#define SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC_MASK (0x100000U)
-#define SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC_SHIFT (20U)
-#define SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC_MASK)
-#define SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY_MASK (0x200000U)
-#define SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY_SHIFT (21U)
-#define SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY_MASK)
-#define SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL_MASK (0x400000U)
-#define SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL_SHIFT (22U)
-#define SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL_MASK)
-#define SYSCON_PDRUNCFGCLR_PDEN_VREFP_MASK (0x800000U)
-#define SYSCON_PDRUNCFGCLR_PDEN_VREFP_SHIFT (23U)
-#define SYSCON_PDRUNCFGCLR_PDEN_VREFP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VREFP_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VREFP_MASK)
-#define SYSCON_PDRUNCFGCLR_PDEN_VD3_MASK (0x4000000U)
-#define SYSCON_PDRUNCFGCLR_PDEN_VD3_SHIFT (26U)
-#define SYSCON_PDRUNCFGCLR_PDEN_VD3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD3_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD3_MASK)
-#define SYSCON_PDRUNCFGCLR_PDEN_VD4_MASK (0x8000000U)
-#define SYSCON_PDRUNCFGCLR_PDEN_VD4_SHIFT (27U)
-#define SYSCON_PDRUNCFGCLR_PDEN_VD4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD4_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD4_MASK)
-#define SYSCON_PDRUNCFGCLR_PDEN_VD5_MASK (0x10000000U)
-#define SYSCON_PDRUNCFGCLR_PDEN_VD5_SHIFT (28U)
-#define SYSCON_PDRUNCFGCLR_PDEN_VD5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD5_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD5_MASK)
-#define SYSCON_PDRUNCFGCLR_PDEN_VD6_MASK (0x20000000U)
-#define SYSCON_PDRUNCFGCLR_PDEN_VD6_SHIFT (29U)
-#define SYSCON_PDRUNCFGCLR_PDEN_VD6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD6_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD6_MASK)
-
-/* The count of SYSCON_PDRUNCFGCLR */
-#define SYSCON_PDRUNCFGCLR_COUNT (2U)
-
-/*! @name STARTER - Start logic 0 wake-up enable register */
-#define SYSCON_STARTER_WDT_BOD_MASK (0x1U)
-#define SYSCON_STARTER_WDT_BOD_SHIFT (0U)
-#define SYSCON_STARTER_WDT_BOD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_WDT_BOD_SHIFT)) & SYSCON_STARTER_WDT_BOD_MASK)
-#define SYSCON_STARTER_PINT4_MASK (0x1U)
-#define SYSCON_STARTER_PINT4_SHIFT (0U)
-#define SYSCON_STARTER_PINT4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PINT4_SHIFT)) & SYSCON_STARTER_PINT4_MASK)
-#define SYSCON_STARTER_PINT5_MASK (0x2U)
-#define SYSCON_STARTER_PINT5_SHIFT (1U)
-#define SYSCON_STARTER_PINT5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PINT5_SHIFT)) & SYSCON_STARTER_PINT5_MASK)
-#define SYSCON_STARTER_DMA_MASK (0x2U)
-#define SYSCON_STARTER_DMA_SHIFT (1U)
-#define SYSCON_STARTER_DMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_DMA_SHIFT)) & SYSCON_STARTER_DMA_MASK)
-#define SYSCON_STARTER_GINT0_MASK (0x4U)
-#define SYSCON_STARTER_GINT0_SHIFT (2U)
-#define SYSCON_STARTER_GINT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GINT0_SHIFT)) & SYSCON_STARTER_GINT0_MASK)
-#define SYSCON_STARTER_PINT6_MASK (0x4U)
-#define SYSCON_STARTER_PINT6_SHIFT (2U)
-#define SYSCON_STARTER_PINT6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PINT6_SHIFT)) & SYSCON_STARTER_PINT6_MASK)
-#define SYSCON_STARTER_GINT1_MASK (0x8U)
-#define SYSCON_STARTER_GINT1_SHIFT (3U)
-#define SYSCON_STARTER_GINT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GINT1_SHIFT)) & SYSCON_STARTER_GINT1_MASK)
-#define SYSCON_STARTER_PINT7_MASK (0x8U)
-#define SYSCON_STARTER_PINT7_SHIFT (3U)
-#define SYSCON_STARTER_PINT7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PINT7_SHIFT)) & SYSCON_STARTER_PINT7_MASK)
-#define SYSCON_STARTER_CTIMER2_MASK (0x10U)
-#define SYSCON_STARTER_CTIMER2_SHIFT (4U)
-#define SYSCON_STARTER_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER2_SHIFT)) & SYSCON_STARTER_CTIMER2_MASK)
-#define SYSCON_STARTER_PIN_INT0_MASK (0x10U)
-#define SYSCON_STARTER_PIN_INT0_SHIFT (4U)
-#define SYSCON_STARTER_PIN_INT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT0_SHIFT)) & SYSCON_STARTER_PIN_INT0_MASK)
-#define SYSCON_STARTER_CTIMER4_MASK (0x20U)
-#define SYSCON_STARTER_CTIMER4_SHIFT (5U)
-#define SYSCON_STARTER_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER4_SHIFT)) & SYSCON_STARTER_CTIMER4_MASK)
-#define SYSCON_STARTER_PIN_INT1_MASK (0x20U)
-#define SYSCON_STARTER_PIN_INT1_SHIFT (5U)
-#define SYSCON_STARTER_PIN_INT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT1_SHIFT)) & SYSCON_STARTER_PIN_INT1_MASK)
-#define SYSCON_STARTER_PIN_INT2_MASK (0x40U)
-#define SYSCON_STARTER_PIN_INT2_SHIFT (6U)
-#define SYSCON_STARTER_PIN_INT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT2_SHIFT)) & SYSCON_STARTER_PIN_INT2_MASK)
-#define SYSCON_STARTER_PIN_INT3_MASK (0x80U)
-#define SYSCON_STARTER_PIN_INT3_SHIFT (7U)
-#define SYSCON_STARTER_PIN_INT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT3_SHIFT)) & SYSCON_STARTER_PIN_INT3_MASK)
-#define SYSCON_STARTER_SPIFI_MASK (0x80U)
-#define SYSCON_STARTER_SPIFI_SHIFT (7U)
-#define SYSCON_STARTER_SPIFI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SPIFI_SHIFT)) & SYSCON_STARTER_SPIFI_MASK)
-#define SYSCON_STARTER_FLEXCOMM8_MASK (0x100U)
-#define SYSCON_STARTER_FLEXCOMM8_SHIFT (8U)
-#define SYSCON_STARTER_FLEXCOMM8(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM8_SHIFT)) & SYSCON_STARTER_FLEXCOMM8_MASK)
-#define SYSCON_STARTER_UTICK_MASK (0x100U)
-#define SYSCON_STARTER_UTICK_SHIFT (8U)
-#define SYSCON_STARTER_UTICK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_UTICK_SHIFT)) & SYSCON_STARTER_UTICK_MASK)
-#define SYSCON_STARTER_MRT_MASK (0x200U)
-#define SYSCON_STARTER_MRT_SHIFT (9U)
-#define SYSCON_STARTER_MRT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_MRT_SHIFT)) & SYSCON_STARTER_MRT_MASK)
-#define SYSCON_STARTER_FLEXCOMM9_MASK (0x200U)
-#define SYSCON_STARTER_FLEXCOMM9_SHIFT (9U)
-#define SYSCON_STARTER_FLEXCOMM9(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM9_SHIFT)) & SYSCON_STARTER_FLEXCOMM9_MASK)
-#define SYSCON_STARTER_CTIMER0_MASK (0x400U)
-#define SYSCON_STARTER_CTIMER0_SHIFT (10U)
-#define SYSCON_STARTER_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER0_SHIFT)) & SYSCON_STARTER_CTIMER0_MASK)
-#define SYSCON_STARTER_CTIMER1_MASK (0x800U)
-#define SYSCON_STARTER_CTIMER1_SHIFT (11U)
-#define SYSCON_STARTER_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER1_SHIFT)) & SYSCON_STARTER_CTIMER1_MASK)
-#define SYSCON_STARTER_SCT0_MASK (0x1000U)
-#define SYSCON_STARTER_SCT0_SHIFT (12U)
-#define SYSCON_STARTER_SCT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SCT0_SHIFT)) & SYSCON_STARTER_SCT0_MASK)
-#define SYSCON_STARTER_CTIMER3_MASK (0x2000U)
-#define SYSCON_STARTER_CTIMER3_SHIFT (13U)
-#define SYSCON_STARTER_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER3_SHIFT)) & SYSCON_STARTER_CTIMER3_MASK)
-#define SYSCON_STARTER_FLEXCOMM0_MASK (0x4000U)
-#define SYSCON_STARTER_FLEXCOMM0_SHIFT (14U)
-#define SYSCON_STARTER_FLEXCOMM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM0_SHIFT)) & SYSCON_STARTER_FLEXCOMM0_MASK)
-#define SYSCON_STARTER_FLEXCOMM1_MASK (0x8000U)
-#define SYSCON_STARTER_FLEXCOMM1_SHIFT (15U)
-#define SYSCON_STARTER_FLEXCOMM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM1_SHIFT)) & SYSCON_STARTER_FLEXCOMM1_MASK)
-#define SYSCON_STARTER_USB1_MASK (0x8000U)
-#define SYSCON_STARTER_USB1_SHIFT (15U)
-#define SYSCON_STARTER_USB1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB1_SHIFT)) & SYSCON_STARTER_USB1_MASK)
-#define SYSCON_STARTER_FLEXCOMM2_MASK (0x10000U)
-#define SYSCON_STARTER_FLEXCOMM2_SHIFT (16U)
-#define SYSCON_STARTER_FLEXCOMM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM2_SHIFT)) & SYSCON_STARTER_FLEXCOMM2_MASK)
-#define SYSCON_STARTER_USB1_ACT_MASK (0x10000U)
-#define SYSCON_STARTER_USB1_ACT_SHIFT (16U)
-#define SYSCON_STARTER_USB1_ACT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB1_ACT_SHIFT)) & SYSCON_STARTER_USB1_ACT_MASK)
-#define SYSCON_STARTER_ENET_INT1_MASK (0x20000U)
-#define SYSCON_STARTER_ENET_INT1_SHIFT (17U)
-#define SYSCON_STARTER_ENET_INT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ENET_INT1_SHIFT)) & SYSCON_STARTER_ENET_INT1_MASK)
-#define SYSCON_STARTER_FLEXCOMM3_MASK (0x20000U)
-#define SYSCON_STARTER_FLEXCOMM3_SHIFT (17U)
-#define SYSCON_STARTER_FLEXCOMM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM3_SHIFT)) & SYSCON_STARTER_FLEXCOMM3_MASK)
-#define SYSCON_STARTER_ENET_INT2_MASK (0x40000U)
-#define SYSCON_STARTER_ENET_INT2_SHIFT (18U)
-#define SYSCON_STARTER_ENET_INT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ENET_INT2_SHIFT)) & SYSCON_STARTER_ENET_INT2_MASK)
-#define SYSCON_STARTER_FLEXCOMM4_MASK (0x40000U)
-#define SYSCON_STARTER_FLEXCOMM4_SHIFT (18U)
-#define SYSCON_STARTER_FLEXCOMM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM4_SHIFT)) & SYSCON_STARTER_FLEXCOMM4_MASK)
-#define SYSCON_STARTER_ENET_INT0_MASK (0x80000U)
-#define SYSCON_STARTER_ENET_INT0_SHIFT (19U)
-#define SYSCON_STARTER_ENET_INT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ENET_INT0_SHIFT)) & SYSCON_STARTER_ENET_INT0_MASK)
-#define SYSCON_STARTER_FLEXCOMM5_MASK (0x80000U)
-#define SYSCON_STARTER_FLEXCOMM5_SHIFT (19U)
-#define SYSCON_STARTER_FLEXCOMM5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM5_SHIFT)) & SYSCON_STARTER_FLEXCOMM5_MASK)
-#define SYSCON_STARTER_FLEXCOMM6_MASK (0x100000U)
-#define SYSCON_STARTER_FLEXCOMM6_SHIFT (20U)
-#define SYSCON_STARTER_FLEXCOMM6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM6_SHIFT)) & SYSCON_STARTER_FLEXCOMM6_MASK)
-#define SYSCON_STARTER_FLEXCOMM7_MASK (0x200000U)
-#define SYSCON_STARTER_FLEXCOMM7_SHIFT (21U)
-#define SYSCON_STARTER_FLEXCOMM7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM7_SHIFT)) & SYSCON_STARTER_FLEXCOMM7_MASK)
-#define SYSCON_STARTER_ADC0_SEQA_MASK (0x400000U)
-#define SYSCON_STARTER_ADC0_SEQA_SHIFT (22U)
-#define SYSCON_STARTER_ADC0_SEQA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ADC0_SEQA_SHIFT)) & SYSCON_STARTER_ADC0_SEQA_MASK)
-#define SYSCON_STARTER_SMARTCARD0_MASK (0x800000U)
-#define SYSCON_STARTER_SMARTCARD0_SHIFT (23U)
-#define SYSCON_STARTER_SMARTCARD0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SMARTCARD0_SHIFT)) & SYSCON_STARTER_SMARTCARD0_MASK)
-#define SYSCON_STARTER_ADC0_SEQB_MASK (0x800000U)
-#define SYSCON_STARTER_ADC0_SEQB_SHIFT (23U)
-#define SYSCON_STARTER_ADC0_SEQB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ADC0_SEQB_SHIFT)) & SYSCON_STARTER_ADC0_SEQB_MASK)
-#define SYSCON_STARTER_ADC0_THCMP_MASK (0x1000000U)
-#define SYSCON_STARTER_ADC0_THCMP_SHIFT (24U)
-#define SYSCON_STARTER_ADC0_THCMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ADC0_THCMP_SHIFT)) & SYSCON_STARTER_ADC0_THCMP_MASK)
-#define SYSCON_STARTER_SMARTCARD1_MASK (0x1000000U)
-#define SYSCON_STARTER_SMARTCARD1_SHIFT (24U)
-#define SYSCON_STARTER_SMARTCARD1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SMARTCARD1_SHIFT)) & SYSCON_STARTER_SMARTCARD1_MASK)
-#define SYSCON_STARTER_DMIC_MASK (0x2000000U)
-#define SYSCON_STARTER_DMIC_SHIFT (25U)
-#define SYSCON_STARTER_DMIC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_DMIC_SHIFT)) & SYSCON_STARTER_DMIC_MASK)
-#define SYSCON_STARTER_HWVAD_MASK (0x4000000U)
-#define SYSCON_STARTER_HWVAD_SHIFT (26U)
-#define SYSCON_STARTER_HWVAD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_HWVAD_SHIFT)) & SYSCON_STARTER_HWVAD_MASK)
-#define SYSCON_STARTER_USB0_NEEDCLK_MASK (0x8000000U)
-#define SYSCON_STARTER_USB0_NEEDCLK_SHIFT (27U)
-#define SYSCON_STARTER_USB0_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB0_NEEDCLK_SHIFT)) & SYSCON_STARTER_USB0_NEEDCLK_MASK)
-#define SYSCON_STARTER_USB0_MASK (0x10000000U)
-#define SYSCON_STARTER_USB0_SHIFT (28U)
-#define SYSCON_STARTER_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB0_SHIFT)) & SYSCON_STARTER_USB0_MASK)
-#define SYSCON_STARTER_RTC_MASK (0x20000000U)
-#define SYSCON_STARTER_RTC_SHIFT (29U)
-#define SYSCON_STARTER_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_RTC_SHIFT)) & SYSCON_STARTER_RTC_MASK)
-
-/* The count of SYSCON_STARTER */
-#define SYSCON_STARTER_COUNT (2U)
-
-/*! @name STARTERSET - Set bits in STARTER */
-#define SYSCON_STARTERSET_START_SET_MASK (0xFFFFFFFFU)
-#define SYSCON_STARTERSET_START_SET_SHIFT (0U)
-#define SYSCON_STARTERSET_START_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_START_SET_SHIFT)) & SYSCON_STARTERSET_START_SET_MASK)
-
-/* The count of SYSCON_STARTERSET */
-#define SYSCON_STARTERSET_COUNT (2U)
-
-/*! @name STARTERCLR - Clear bits in STARTER0 */
-#define SYSCON_STARTERCLR_START_CLR_MASK (0xFFFFFFFFU)
-#define SYSCON_STARTERCLR_START_CLR_SHIFT (0U)
-#define SYSCON_STARTERCLR_START_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_START_CLR_SHIFT)) & SYSCON_STARTERCLR_START_CLR_MASK)
-
-/* The count of SYSCON_STARTERCLR */
-#define SYSCON_STARTERCLR_COUNT (2U)
-
-/*! @name HWWAKE - Configures special cases of hardware wake-up */
-#define SYSCON_HWWAKE_FORCEWAKE_MASK (0x1U)
-#define SYSCON_HWWAKE_FORCEWAKE_SHIFT (0U)
-#define SYSCON_HWWAKE_FORCEWAKE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_FORCEWAKE_SHIFT)) & SYSCON_HWWAKE_FORCEWAKE_MASK)
-#define SYSCON_HWWAKE_FCWAKE_MASK (0x2U)
-#define SYSCON_HWWAKE_FCWAKE_SHIFT (1U)
-#define SYSCON_HWWAKE_FCWAKE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_FCWAKE_SHIFT)) & SYSCON_HWWAKE_FCWAKE_MASK)
-#define SYSCON_HWWAKE_WAKEDMIC_MASK (0x4U)
-#define SYSCON_HWWAKE_WAKEDMIC_SHIFT (2U)
-#define SYSCON_HWWAKE_WAKEDMIC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_WAKEDMIC_SHIFT)) & SYSCON_HWWAKE_WAKEDMIC_MASK)
-#define SYSCON_HWWAKE_WAKEDMA_MASK (0x8U)
-#define SYSCON_HWWAKE_WAKEDMA_SHIFT (3U)
-#define SYSCON_HWWAKE_WAKEDMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_WAKEDMA_SHIFT)) & SYSCON_HWWAKE_WAKEDMA_MASK)
-
-/*! @name AUTOCGOR - Auto Clock-Gate Override Register */
-#define SYSCON_AUTOCGOR_RAM0X_MASK (0x2U)
-#define SYSCON_AUTOCGOR_RAM0X_SHIFT (1U)
-#define SYSCON_AUTOCGOR_RAM0X(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM0X_SHIFT)) & SYSCON_AUTOCGOR_RAM0X_MASK)
-#define SYSCON_AUTOCGOR_RAM1_MASK (0x4U)
-#define SYSCON_AUTOCGOR_RAM1_SHIFT (2U)
-#define SYSCON_AUTOCGOR_RAM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM1_SHIFT)) & SYSCON_AUTOCGOR_RAM1_MASK)
-#define SYSCON_AUTOCGOR_RAM2_MASK (0x8U)
-#define SYSCON_AUTOCGOR_RAM2_SHIFT (3U)
-#define SYSCON_AUTOCGOR_RAM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM2_SHIFT)) & SYSCON_AUTOCGOR_RAM2_MASK)
-#define SYSCON_AUTOCGOR_RAM3_MASK (0x10U)
-#define SYSCON_AUTOCGOR_RAM3_SHIFT (4U)
-#define SYSCON_AUTOCGOR_RAM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM3_SHIFT)) & SYSCON_AUTOCGOR_RAM3_MASK)
-
-/*! @name JTAGIDCODE - JTAG ID code register */
-#define SYSCON_JTAGIDCODE_JTAGID_MASK (0xFFFFFFFFU)
-#define SYSCON_JTAGIDCODE_JTAGID_SHIFT (0U)
-#define SYSCON_JTAGIDCODE_JTAGID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_JTAGIDCODE_JTAGID_SHIFT)) & SYSCON_JTAGIDCODE_JTAGID_MASK)
-
-/*! @name DEVICE_ID0 - Part ID register */
-#define SYSCON_DEVICE_ID0_PARTID_MASK (0xFFFFFFFFU)
-#define SYSCON_DEVICE_ID0_PARTID_SHIFT (0U)
-#define SYSCON_DEVICE_ID0_PARTID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_PARTID_SHIFT)) & SYSCON_DEVICE_ID0_PARTID_MASK)
-
-/*! @name DEVICE_ID1 - Boot ROM and die revision register */
-#define SYSCON_DEVICE_ID1_REVID_MASK (0xFFFFFFFFU)
-#define SYSCON_DEVICE_ID1_REVID_SHIFT (0U)
-#define SYSCON_DEVICE_ID1_REVID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID1_REVID_SHIFT)) & SYSCON_DEVICE_ID1_REVID_MASK)
-
-/*! @name BODCTRL - Brown-Out Detect control */
-#define SYSCON_BODCTRL_BODRSTLEV_MASK (0x3U)
-#define SYSCON_BODCTRL_BODRSTLEV_SHIFT (0U)
-#define SYSCON_BODCTRL_BODRSTLEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTLEV_SHIFT)) & SYSCON_BODCTRL_BODRSTLEV_MASK)
-#define SYSCON_BODCTRL_BODRSTENA_MASK (0x4U)
-#define SYSCON_BODCTRL_BODRSTENA_SHIFT (2U)
-#define SYSCON_BODCTRL_BODRSTENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTENA_SHIFT)) & SYSCON_BODCTRL_BODRSTENA_MASK)
-#define SYSCON_BODCTRL_BODINTLEV_MASK (0x18U)
-#define SYSCON_BODCTRL_BODINTLEV_SHIFT (3U)
-#define SYSCON_BODCTRL_BODINTLEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTLEV_SHIFT)) & SYSCON_BODCTRL_BODINTLEV_MASK)
-#define SYSCON_BODCTRL_BODINTENA_MASK (0x20U)
-#define SYSCON_BODCTRL_BODINTENA_SHIFT (5U)
-#define SYSCON_BODCTRL_BODINTENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTENA_SHIFT)) & SYSCON_BODCTRL_BODINTENA_MASK)
-#define SYSCON_BODCTRL_BODRSTSTAT_MASK (0x40U)
-#define SYSCON_BODCTRL_BODRSTSTAT_SHIFT (6U)
-#define SYSCON_BODCTRL_BODRSTSTAT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTSTAT_SHIFT)) & SYSCON_BODCTRL_BODRSTSTAT_MASK)
-#define SYSCON_BODCTRL_BODINTSTAT_MASK (0x80U)
-#define SYSCON_BODCTRL_BODINTSTAT_SHIFT (7U)
-#define SYSCON_BODCTRL_BODINTSTAT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTSTAT_SHIFT)) & SYSCON_BODCTRL_BODINTSTAT_MASK)
-
-
-/*!
- * @}
- */ /* end of group SYSCON_Register_Masks */
-
-
-/* SYSCON - Peripheral instance base addresses */
-/** Peripheral SYSCON base address */
-#define SYSCON_BASE (0x40000000u)
-/** Peripheral SYSCON base pointer */
-#define SYSCON ((SYSCON_Type *)SYSCON_BASE)
-/** Array initializer of SYSCON peripheral base addresses */
-#define SYSCON_BASE_ADDRS { SYSCON_BASE }
-/** Array initializer of SYSCON peripheral base pointers */
-#define SYSCON_BASE_PTRS { SYSCON }
-
-/*!
- * @}
- */ /* end of group SYSCON_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- USART Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup USART_Peripheral_Access_Layer USART Peripheral Access Layer
- * @{
- */
-
-/** USART - Register Layout Typedef */
-typedef struct {
- __IO uint32_t CFG; /**< USART Configuration register. Basic USART configuration settings that typically are not changed during operation., offset: 0x0 */
- __IO uint32_t CTL; /**< USART Control register. USART control settings that are more likely to change during operation., offset: 0x4 */
- __IO uint32_t STAT; /**< USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them., offset: 0x8 */
- __IO uint32_t INTENSET; /**< Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0xC */
- __O uint32_t INTENCLR; /**< Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared., offset: 0x10 */
- uint8_t RESERVED_0[12];
- __IO uint32_t BRG; /**< Baud Rate Generator register. 16-bit integer baud rate divisor value., offset: 0x20 */
- __I uint32_t INTSTAT; /**< Interrupt status register. Reflects interrupts that are currently enabled., offset: 0x24 */
- __IO uint32_t OSR; /**< Oversample selection register for asynchronous communication., offset: 0x28 */
- __IO uint32_t ADDR; /**< Address register for automatic address matching., offset: 0x2C */
- uint8_t RESERVED_1[3536];
- __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */
- __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */
- __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */
- uint8_t RESERVED_2[4];
- __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */
- __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */
- __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */
- uint8_t RESERVED_3[4];
- __IO uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */
- uint8_t RESERVED_4[12];
- __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */
- uint8_t RESERVED_5[12];
- __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */
- uint8_t RESERVED_6[440];
- __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */
-} USART_Type;
-
-/* ----------------------------------------------------------------------------
- -- USART Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup USART_Register_Masks USART Register Masks
- * @{
- */
-
-/*! @name CFG - USART Configuration register. Basic USART configuration settings that typically are not changed during operation. */
-#define USART_CFG_ENABLE_MASK (0x1U)
-#define USART_CFG_ENABLE_SHIFT (0U)
-#define USART_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK)
-#define USART_CFG_DATALEN_MASK (0xCU)
-#define USART_CFG_DATALEN_SHIFT (2U)
-#define USART_CFG_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_DATALEN_SHIFT)) & USART_CFG_DATALEN_MASK)
-#define USART_CFG_PARITYSEL_MASK (0x30U)
-#define USART_CFG_PARITYSEL_SHIFT (4U)
-#define USART_CFG_PARITYSEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_PARITYSEL_SHIFT)) & USART_CFG_PARITYSEL_MASK)
-#define USART_CFG_STOPLEN_MASK (0x40U)
-#define USART_CFG_STOPLEN_SHIFT (6U)
-#define USART_CFG_STOPLEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_STOPLEN_SHIFT)) & USART_CFG_STOPLEN_MASK)
-#define USART_CFG_MODE32K_MASK (0x80U)
-#define USART_CFG_MODE32K_SHIFT (7U)
-#define USART_CFG_MODE32K(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_MODE32K_SHIFT)) & USART_CFG_MODE32K_MASK)
-#define USART_CFG_LINMODE_MASK (0x100U)
-#define USART_CFG_LINMODE_SHIFT (8U)
-#define USART_CFG_LINMODE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LINMODE_SHIFT)) & USART_CFG_LINMODE_MASK)
-#define USART_CFG_CTSEN_MASK (0x200U)
-#define USART_CFG_CTSEN_SHIFT (9U)
-#define USART_CFG_CTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CTSEN_SHIFT)) & USART_CFG_CTSEN_MASK)
-#define USART_CFG_SYNCEN_MASK (0x800U)
-#define USART_CFG_SYNCEN_SHIFT (11U)
-#define USART_CFG_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCEN_SHIFT)) & USART_CFG_SYNCEN_MASK)
-#define USART_CFG_CLKPOL_MASK (0x1000U)
-#define USART_CFG_CLKPOL_SHIFT (12U)
-#define USART_CFG_CLKPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CLKPOL_SHIFT)) & USART_CFG_CLKPOL_MASK)
-#define USART_CFG_SYNCMST_MASK (0x4000U)
-#define USART_CFG_SYNCMST_SHIFT (14U)
-#define USART_CFG_SYNCMST(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCMST_SHIFT)) & USART_CFG_SYNCMST_MASK)
-#define USART_CFG_LOOP_MASK (0x8000U)
-#define USART_CFG_LOOP_SHIFT (15U)
-#define USART_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LOOP_SHIFT)) & USART_CFG_LOOP_MASK)
-#define USART_CFG_OETA_MASK (0x40000U)
-#define USART_CFG_OETA_SHIFT (18U)
-#define USART_CFG_OETA(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OETA_SHIFT)) & USART_CFG_OETA_MASK)
-#define USART_CFG_AUTOADDR_MASK (0x80000U)
-#define USART_CFG_AUTOADDR_SHIFT (19U)
-#define USART_CFG_AUTOADDR(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_AUTOADDR_SHIFT)) & USART_CFG_AUTOADDR_MASK)
-#define USART_CFG_OESEL_MASK (0x100000U)
-#define USART_CFG_OESEL_SHIFT (20U)
-#define USART_CFG_OESEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OESEL_SHIFT)) & USART_CFG_OESEL_MASK)
-#define USART_CFG_OEPOL_MASK (0x200000U)
-#define USART_CFG_OEPOL_SHIFT (21U)
-#define USART_CFG_OEPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OEPOL_SHIFT)) & USART_CFG_OEPOL_MASK)
-#define USART_CFG_RXPOL_MASK (0x400000U)
-#define USART_CFG_RXPOL_SHIFT (22U)
-#define USART_CFG_RXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_RXPOL_SHIFT)) & USART_CFG_RXPOL_MASK)
-#define USART_CFG_TXPOL_MASK (0x800000U)
-#define USART_CFG_TXPOL_SHIFT (23U)
-#define USART_CFG_TXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_TXPOL_SHIFT)) & USART_CFG_TXPOL_MASK)
-
-/*! @name CTL - USART Control register. USART control settings that are more likely to change during operation. */
-#define USART_CTL_TXBRKEN_MASK (0x2U)
-#define USART_CTL_TXBRKEN_SHIFT (1U)
-#define USART_CTL_TXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK)
-#define USART_CTL_ADDRDET_MASK (0x4U)
-#define USART_CTL_ADDRDET_SHIFT (2U)
-#define USART_CTL_ADDRDET(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_ADDRDET_SHIFT)) & USART_CTL_ADDRDET_MASK)
-#define USART_CTL_TXDIS_MASK (0x40U)
-#define USART_CTL_TXDIS_SHIFT (6U)
-#define USART_CTL_TXDIS(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXDIS_SHIFT)) & USART_CTL_TXDIS_MASK)
-#define USART_CTL_CC_MASK (0x100U)
-#define USART_CTL_CC_SHIFT (8U)
-#define USART_CTL_CC(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CC_SHIFT)) & USART_CTL_CC_MASK)
-#define USART_CTL_CLRCCONRX_MASK (0x200U)
-#define USART_CTL_CLRCCONRX_SHIFT (9U)
-#define USART_CTL_CLRCCONRX(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CLRCCONRX_SHIFT)) & USART_CTL_CLRCCONRX_MASK)
-#define USART_CTL_AUTOBAUD_MASK (0x10000U)
-#define USART_CTL_AUTOBAUD_SHIFT (16U)
-#define USART_CTL_AUTOBAUD(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_AUTOBAUD_SHIFT)) & USART_CTL_AUTOBAUD_MASK)
-
-/*! @name STAT - USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. */
-#define USART_STAT_RXIDLE_MASK (0x2U)
-#define USART_STAT_RXIDLE_SHIFT (1U)
-#define USART_STAT_RXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK)
-#define USART_STAT_TXIDLE_MASK (0x8U)
-#define USART_STAT_TXIDLE_SHIFT (3U)
-#define USART_STAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXIDLE_SHIFT)) & USART_STAT_TXIDLE_MASK)
-#define USART_STAT_CTS_MASK (0x10U)
-#define USART_STAT_CTS_SHIFT (4U)
-#define USART_STAT_CTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_CTS_SHIFT)) & USART_STAT_CTS_MASK)
-#define USART_STAT_DELTACTS_MASK (0x20U)
-#define USART_STAT_DELTACTS_SHIFT (5U)
-#define USART_STAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTACTS_SHIFT)) & USART_STAT_DELTACTS_MASK)
-#define USART_STAT_TXDISSTAT_MASK (0x40U)
-#define USART_STAT_TXDISSTAT_SHIFT (6U)
-#define USART_STAT_TXDISSTAT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXDISSTAT_SHIFT)) & USART_STAT_TXDISSTAT_MASK)
-#define USART_STAT_RXBRK_MASK (0x400U)
-#define USART_STAT_RXBRK_SHIFT (10U)
-#define USART_STAT_RXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXBRK_SHIFT)) & USART_STAT_RXBRK_MASK)
-#define USART_STAT_DELTARXBRK_MASK (0x800U)
-#define USART_STAT_DELTARXBRK_SHIFT (11U)
-#define USART_STAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTARXBRK_SHIFT)) & USART_STAT_DELTARXBRK_MASK)
-#define USART_STAT_START_MASK (0x1000U)
-#define USART_STAT_START_SHIFT (12U)
-#define USART_STAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_START_SHIFT)) & USART_STAT_START_MASK)
-#define USART_STAT_FRAMERRINT_MASK (0x2000U)
-#define USART_STAT_FRAMERRINT_SHIFT (13U)
-#define USART_STAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_FRAMERRINT_SHIFT)) & USART_STAT_FRAMERRINT_MASK)
-#define USART_STAT_PARITYERRINT_MASK (0x4000U)
-#define USART_STAT_PARITYERRINT_SHIFT (14U)
-#define USART_STAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_PARITYERRINT_SHIFT)) & USART_STAT_PARITYERRINT_MASK)
-#define USART_STAT_RXNOISEINT_MASK (0x8000U)
-#define USART_STAT_RXNOISEINT_SHIFT (15U)
-#define USART_STAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXNOISEINT_SHIFT)) & USART_STAT_RXNOISEINT_MASK)
-#define USART_STAT_ABERR_MASK (0x10000U)
-#define USART_STAT_ABERR_SHIFT (16U)
-#define USART_STAT_ABERR(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK)
-
-/*! @name INTENSET - Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */
-#define USART_INTENSET_TXIDLEEN_MASK (0x8U)
-#define USART_INTENSET_TXIDLEEN_SHIFT (3U)
-#define USART_INTENSET_TXIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK)
-#define USART_INTENSET_DELTACTSEN_MASK (0x20U)
-#define USART_INTENSET_DELTACTSEN_SHIFT (5U)
-#define USART_INTENSET_DELTACTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTACTSEN_SHIFT)) & USART_INTENSET_DELTACTSEN_MASK)
-#define USART_INTENSET_TXDISEN_MASK (0x40U)
-#define USART_INTENSET_TXDISEN_SHIFT (6U)
-#define USART_INTENSET_TXDISEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXDISEN_SHIFT)) & USART_INTENSET_TXDISEN_MASK)
-#define USART_INTENSET_DELTARXBRKEN_MASK (0x800U)
-#define USART_INTENSET_DELTARXBRKEN_SHIFT (11U)
-#define USART_INTENSET_DELTARXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTARXBRKEN_SHIFT)) & USART_INTENSET_DELTARXBRKEN_MASK)
-#define USART_INTENSET_STARTEN_MASK (0x1000U)
-#define USART_INTENSET_STARTEN_SHIFT (12U)
-#define USART_INTENSET_STARTEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_STARTEN_SHIFT)) & USART_INTENSET_STARTEN_MASK)
-#define USART_INTENSET_FRAMERREN_MASK (0x2000U)
-#define USART_INTENSET_FRAMERREN_SHIFT (13U)
-#define USART_INTENSET_FRAMERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_FRAMERREN_SHIFT)) & USART_INTENSET_FRAMERREN_MASK)
-#define USART_INTENSET_PARITYERREN_MASK (0x4000U)
-#define USART_INTENSET_PARITYERREN_SHIFT (14U)
-#define USART_INTENSET_PARITYERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_PARITYERREN_SHIFT)) & USART_INTENSET_PARITYERREN_MASK)
-#define USART_INTENSET_RXNOISEEN_MASK (0x8000U)
-#define USART_INTENSET_RXNOISEEN_SHIFT (15U)
-#define USART_INTENSET_RXNOISEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXNOISEEN_SHIFT)) & USART_INTENSET_RXNOISEEN_MASK)
-#define USART_INTENSET_ABERREN_MASK (0x10000U)
-#define USART_INTENSET_ABERREN_SHIFT (16U)
-#define USART_INTENSET_ABERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK)
-
-/*! @name INTENCLR - Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. */
-#define USART_INTENCLR_TXIDLECLR_MASK (0x8U)
-#define USART_INTENCLR_TXIDLECLR_SHIFT (3U)
-#define USART_INTENCLR_TXIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK)
-#define USART_INTENCLR_DELTACTSCLR_MASK (0x20U)
-#define USART_INTENCLR_DELTACTSCLR_SHIFT (5U)
-#define USART_INTENCLR_DELTACTSCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTACTSCLR_SHIFT)) & USART_INTENCLR_DELTACTSCLR_MASK)
-#define USART_INTENCLR_TXDISCLR_MASK (0x40U)
-#define USART_INTENCLR_TXDISCLR_SHIFT (6U)
-#define USART_INTENCLR_TXDISCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXDISCLR_SHIFT)) & USART_INTENCLR_TXDISCLR_MASK)
-#define USART_INTENCLR_DELTARXBRKCLR_MASK (0x800U)
-#define USART_INTENCLR_DELTARXBRKCLR_SHIFT (11U)
-#define USART_INTENCLR_DELTARXBRKCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTARXBRKCLR_SHIFT)) & USART_INTENCLR_DELTARXBRKCLR_MASK)
-#define USART_INTENCLR_STARTCLR_MASK (0x1000U)
-#define USART_INTENCLR_STARTCLR_SHIFT (12U)
-#define USART_INTENCLR_STARTCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_STARTCLR_SHIFT)) & USART_INTENCLR_STARTCLR_MASK)
-#define USART_INTENCLR_FRAMERRCLR_MASK (0x2000U)
-#define USART_INTENCLR_FRAMERRCLR_SHIFT (13U)
-#define USART_INTENCLR_FRAMERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_FRAMERRCLR_SHIFT)) & USART_INTENCLR_FRAMERRCLR_MASK)
-#define USART_INTENCLR_PARITYERRCLR_MASK (0x4000U)
-#define USART_INTENCLR_PARITYERRCLR_SHIFT (14U)
-#define USART_INTENCLR_PARITYERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_PARITYERRCLR_SHIFT)) & USART_INTENCLR_PARITYERRCLR_MASK)
-#define USART_INTENCLR_RXNOISECLR_MASK (0x8000U)
-#define USART_INTENCLR_RXNOISECLR_SHIFT (15U)
-#define USART_INTENCLR_RXNOISECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXNOISECLR_SHIFT)) & USART_INTENCLR_RXNOISECLR_MASK)
-#define USART_INTENCLR_ABERRCLR_MASK (0x10000U)
-#define USART_INTENCLR_ABERRCLR_SHIFT (16U)
-#define USART_INTENCLR_ABERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK)
-
-/*! @name BRG - Baud Rate Generator register. 16-bit integer baud rate divisor value. */
-#define USART_BRG_BRGVAL_MASK (0xFFFFU)
-#define USART_BRG_BRGVAL_SHIFT (0U)
-#define USART_BRG_BRGVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK)
-
-/*! @name INTSTAT - Interrupt status register. Reflects interrupts that are currently enabled. */
-#define USART_INTSTAT_TXIDLE_MASK (0x8U)
-#define USART_INTSTAT_TXIDLE_SHIFT (3U)
-#define USART_INTSTAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK)
-#define USART_INTSTAT_DELTACTS_MASK (0x20U)
-#define USART_INTSTAT_DELTACTS_SHIFT (5U)
-#define USART_INTSTAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTACTS_SHIFT)) & USART_INTSTAT_DELTACTS_MASK)
-#define USART_INTSTAT_TXDISINT_MASK (0x40U)
-#define USART_INTSTAT_TXDISINT_SHIFT (6U)
-#define USART_INTSTAT_TXDISINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXDISINT_SHIFT)) & USART_INTSTAT_TXDISINT_MASK)
-#define USART_INTSTAT_DELTARXBRK_MASK (0x800U)
-#define USART_INTSTAT_DELTARXBRK_SHIFT (11U)
-#define USART_INTSTAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTARXBRK_SHIFT)) & USART_INTSTAT_DELTARXBRK_MASK)
-#define USART_INTSTAT_START_MASK (0x1000U)
-#define USART_INTSTAT_START_SHIFT (12U)
-#define USART_INTSTAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_START_SHIFT)) & USART_INTSTAT_START_MASK)
-#define USART_INTSTAT_FRAMERRINT_MASK (0x2000U)
-#define USART_INTSTAT_FRAMERRINT_SHIFT (13U)
-#define USART_INTSTAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_FRAMERRINT_SHIFT)) & USART_INTSTAT_FRAMERRINT_MASK)
-#define USART_INTSTAT_PARITYERRINT_MASK (0x4000U)
-#define USART_INTSTAT_PARITYERRINT_SHIFT (14U)
-#define USART_INTSTAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_PARITYERRINT_SHIFT)) & USART_INTSTAT_PARITYERRINT_MASK)
-#define USART_INTSTAT_RXNOISEINT_MASK (0x8000U)
-#define USART_INTSTAT_RXNOISEINT_SHIFT (15U)
-#define USART_INTSTAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXNOISEINT_SHIFT)) & USART_INTSTAT_RXNOISEINT_MASK)
-#define USART_INTSTAT_ABERRINT_MASK (0x10000U)
-#define USART_INTSTAT_ABERRINT_SHIFT (16U)
-#define USART_INTSTAT_ABERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERRINT_SHIFT)) & USART_INTSTAT_ABERRINT_MASK)
-
-/*! @name OSR - Oversample selection register for asynchronous communication. */
-#define USART_OSR_OSRVAL_MASK (0xFU)
-#define USART_OSR_OSRVAL_SHIFT (0U)
-#define USART_OSR_OSRVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK)
-
-/*! @name ADDR - Address register for automatic address matching. */
-#define USART_ADDR_ADDRESS_MASK (0xFFU)
-#define USART_ADDR_ADDRESS_SHIFT (0U)
-#define USART_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK)
-
-/*! @name FIFOCFG - FIFO configuration and enable register. */
-#define USART_FIFOCFG_ENABLETX_MASK (0x1U)
-#define USART_FIFOCFG_ENABLETX_SHIFT (0U)
-#define USART_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLETX_SHIFT)) & USART_FIFOCFG_ENABLETX_MASK)
-#define USART_FIFOCFG_ENABLERX_MASK (0x2U)
-#define USART_FIFOCFG_ENABLERX_SHIFT (1U)
-#define USART_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLERX_SHIFT)) & USART_FIFOCFG_ENABLERX_MASK)
-#define USART_FIFOCFG_SIZE_MASK (0x30U)
-#define USART_FIFOCFG_SIZE_SHIFT (4U)
-#define USART_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_SIZE_SHIFT)) & USART_FIFOCFG_SIZE_MASK)
-#define USART_FIFOCFG_DMATX_MASK (0x1000U)
-#define USART_FIFOCFG_DMATX_SHIFT (12U)
-#define USART_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMATX_SHIFT)) & USART_FIFOCFG_DMATX_MASK)
-#define USART_FIFOCFG_DMARX_MASK (0x2000U)
-#define USART_FIFOCFG_DMARX_SHIFT (13U)
-#define USART_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMARX_SHIFT)) & USART_FIFOCFG_DMARX_MASK)
-#define USART_FIFOCFG_WAKETX_MASK (0x4000U)
-#define USART_FIFOCFG_WAKETX_SHIFT (14U)
-#define USART_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKETX_SHIFT)) & USART_FIFOCFG_WAKETX_MASK)
-#define USART_FIFOCFG_WAKERX_MASK (0x8000U)
-#define USART_FIFOCFG_WAKERX_SHIFT (15U)
-#define USART_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKERX_SHIFT)) & USART_FIFOCFG_WAKERX_MASK)
-#define USART_FIFOCFG_EMPTYTX_MASK (0x10000U)
-#define USART_FIFOCFG_EMPTYTX_SHIFT (16U)
-#define USART_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYTX_SHIFT)) & USART_FIFOCFG_EMPTYTX_MASK)
-#define USART_FIFOCFG_EMPTYRX_MASK (0x20000U)
-#define USART_FIFOCFG_EMPTYRX_SHIFT (17U)
-#define USART_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK)
-#define USART_FIFOCFG_POPDBG_MASK (0x40000U)
-#define USART_FIFOCFG_POPDBG_SHIFT (18U)
-#define USART_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_POPDBG_SHIFT)) & USART_FIFOCFG_POPDBG_MASK)
-
-/*! @name FIFOSTAT - FIFO status register. */
-#define USART_FIFOSTAT_TXERR_MASK (0x1U)
-#define USART_FIFOSTAT_TXERR_SHIFT (0U)
-#define USART_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXERR_SHIFT)) & USART_FIFOSTAT_TXERR_MASK)
-#define USART_FIFOSTAT_RXERR_MASK (0x2U)
-#define USART_FIFOSTAT_RXERR_SHIFT (1U)
-#define USART_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXERR_SHIFT)) & USART_FIFOSTAT_RXERR_MASK)
-#define USART_FIFOSTAT_PERINT_MASK (0x8U)
-#define USART_FIFOSTAT_PERINT_SHIFT (3U)
-#define USART_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_PERINT_SHIFT)) & USART_FIFOSTAT_PERINT_MASK)
-#define USART_FIFOSTAT_TXEMPTY_MASK (0x10U)
-#define USART_FIFOSTAT_TXEMPTY_SHIFT (4U)
-#define USART_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXEMPTY_SHIFT)) & USART_FIFOSTAT_TXEMPTY_MASK)
-#define USART_FIFOSTAT_TXNOTFULL_MASK (0x20U)
-#define USART_FIFOSTAT_TXNOTFULL_SHIFT (5U)
-#define USART_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXNOTFULL_SHIFT)) & USART_FIFOSTAT_TXNOTFULL_MASK)
-#define USART_FIFOSTAT_RXNOTEMPTY_MASK (0x40U)
-#define USART_FIFOSTAT_RXNOTEMPTY_SHIFT (6U)
-#define USART_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXNOTEMPTY_SHIFT)) & USART_FIFOSTAT_RXNOTEMPTY_MASK)
-#define USART_FIFOSTAT_RXFULL_MASK (0x80U)
-#define USART_FIFOSTAT_RXFULL_SHIFT (7U)
-#define USART_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXFULL_SHIFT)) & USART_FIFOSTAT_RXFULL_MASK)
-#define USART_FIFOSTAT_TXLVL_MASK (0x1F00U)
-#define USART_FIFOSTAT_TXLVL_SHIFT (8U)
-#define USART_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXLVL_SHIFT)) & USART_FIFOSTAT_TXLVL_MASK)
-#define USART_FIFOSTAT_RXLVL_MASK (0x1F0000U)
-#define USART_FIFOSTAT_RXLVL_SHIFT (16U)
-#define USART_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXLVL_SHIFT)) & USART_FIFOSTAT_RXLVL_MASK)
-
-/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */
-#define USART_FIFOTRIG_TXLVLENA_MASK (0x1U)
-#define USART_FIFOTRIG_TXLVLENA_SHIFT (0U)
-#define USART_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVLENA_SHIFT)) & USART_FIFOTRIG_TXLVLENA_MASK)
-#define USART_FIFOTRIG_RXLVLENA_MASK (0x2U)
-#define USART_FIFOTRIG_RXLVLENA_SHIFT (1U)
-#define USART_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVLENA_SHIFT)) & USART_FIFOTRIG_RXLVLENA_MASK)
-#define USART_FIFOTRIG_TXLVL_MASK (0xF00U)
-#define USART_FIFOTRIG_TXLVL_SHIFT (8U)
-#define USART_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVL_SHIFT)) & USART_FIFOTRIG_TXLVL_MASK)
-#define USART_FIFOTRIG_RXLVL_MASK (0xF0000U)
-#define USART_FIFOTRIG_RXLVL_SHIFT (16U)
-#define USART_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVL_SHIFT)) & USART_FIFOTRIG_RXLVL_MASK)
-
-/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */
-#define USART_FIFOINTENSET_TXERR_MASK (0x1U)
-#define USART_FIFOINTENSET_TXERR_SHIFT (0U)
-#define USART_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXERR_SHIFT)) & USART_FIFOINTENSET_TXERR_MASK)
-#define USART_FIFOINTENSET_RXERR_MASK (0x2U)
-#define USART_FIFOINTENSET_RXERR_SHIFT (1U)
-#define USART_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXERR_SHIFT)) & USART_FIFOINTENSET_RXERR_MASK)
-#define USART_FIFOINTENSET_TXLVL_MASK (0x4U)
-#define USART_FIFOINTENSET_TXLVL_SHIFT (2U)
-#define USART_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXLVL_SHIFT)) & USART_FIFOINTENSET_TXLVL_MASK)
-#define USART_FIFOINTENSET_RXLVL_MASK (0x8U)
-#define USART_FIFOINTENSET_RXLVL_SHIFT (3U)
-#define USART_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXLVL_SHIFT)) & USART_FIFOINTENSET_RXLVL_MASK)
-
-/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */
-#define USART_FIFOINTENCLR_TXERR_MASK (0x1U)
-#define USART_FIFOINTENCLR_TXERR_SHIFT (0U)
-#define USART_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXERR_SHIFT)) & USART_FIFOINTENCLR_TXERR_MASK)
-#define USART_FIFOINTENCLR_RXERR_MASK (0x2U)
-#define USART_FIFOINTENCLR_RXERR_SHIFT (1U)
-#define USART_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXERR_SHIFT)) & USART_FIFOINTENCLR_RXERR_MASK)
-#define USART_FIFOINTENCLR_TXLVL_MASK (0x4U)
-#define USART_FIFOINTENCLR_TXLVL_SHIFT (2U)
-#define USART_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXLVL_SHIFT)) & USART_FIFOINTENCLR_TXLVL_MASK)
-#define USART_FIFOINTENCLR_RXLVL_MASK (0x8U)
-#define USART_FIFOINTENCLR_RXLVL_SHIFT (3U)
-#define USART_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXLVL_SHIFT)) & USART_FIFOINTENCLR_RXLVL_MASK)
-
-/*! @name FIFOINTSTAT - FIFO interrupt status register. */
-#define USART_FIFOINTSTAT_TXERR_MASK (0x1U)
-#define USART_FIFOINTSTAT_TXERR_SHIFT (0U)
-#define USART_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXERR_SHIFT)) & USART_FIFOINTSTAT_TXERR_MASK)
-#define USART_FIFOINTSTAT_RXERR_MASK (0x2U)
-#define USART_FIFOINTSTAT_RXERR_SHIFT (1U)
-#define USART_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXERR_SHIFT)) & USART_FIFOINTSTAT_RXERR_MASK)
-#define USART_FIFOINTSTAT_TXLVL_MASK (0x4U)
-#define USART_FIFOINTSTAT_TXLVL_SHIFT (2U)
-#define USART_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXLVL_SHIFT)) & USART_FIFOINTSTAT_TXLVL_MASK)
-#define USART_FIFOINTSTAT_RXLVL_MASK (0x8U)
-#define USART_FIFOINTSTAT_RXLVL_SHIFT (3U)
-#define USART_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXLVL_SHIFT)) & USART_FIFOINTSTAT_RXLVL_MASK)
-#define USART_FIFOINTSTAT_PERINT_MASK (0x10U)
-#define USART_FIFOINTSTAT_PERINT_SHIFT (4U)
-#define USART_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_PERINT_SHIFT)) & USART_FIFOINTSTAT_PERINT_MASK)
-
-/*! @name FIFOWR - FIFO write data. */
-#define USART_FIFOWR_TXDATA_MASK (0x1FFU)
-#define USART_FIFOWR_TXDATA_SHIFT (0U)
-#define USART_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOWR_TXDATA_SHIFT)) & USART_FIFOWR_TXDATA_MASK)
-
-/*! @name FIFORD - FIFO read data. */
-#define USART_FIFORD_RXDATA_MASK (0x1FFU)
-#define USART_FIFORD_RXDATA_SHIFT (0U)
-#define USART_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXDATA_SHIFT)) & USART_FIFORD_RXDATA_MASK)
-#define USART_FIFORD_FRAMERR_MASK (0x2000U)
-#define USART_FIFORD_FRAMERR_SHIFT (13U)
-#define USART_FIFORD_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_FRAMERR_SHIFT)) & USART_FIFORD_FRAMERR_MASK)
-#define USART_FIFORD_PARITYERR_MASK (0x4000U)
-#define USART_FIFORD_PARITYERR_SHIFT (14U)
-#define USART_FIFORD_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_PARITYERR_SHIFT)) & USART_FIFORD_PARITYERR_MASK)
-#define USART_FIFORD_RXNOISE_MASK (0x8000U)
-#define USART_FIFORD_RXNOISE_SHIFT (15U)
-#define USART_FIFORD_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXNOISE_SHIFT)) & USART_FIFORD_RXNOISE_MASK)
-
-/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */
-#define USART_FIFORDNOPOP_RXDATA_MASK (0x1FFU)
-#define USART_FIFORDNOPOP_RXDATA_SHIFT (0U)
-#define USART_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXDATA_SHIFT)) & USART_FIFORDNOPOP_RXDATA_MASK)
-#define USART_FIFORDNOPOP_FRAMERR_MASK (0x2000U)
-#define USART_FIFORDNOPOP_FRAMERR_SHIFT (13U)
-#define USART_FIFORDNOPOP_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_FRAMERR_SHIFT)) & USART_FIFORDNOPOP_FRAMERR_MASK)
-#define USART_FIFORDNOPOP_PARITYERR_MASK (0x4000U)
-#define USART_FIFORDNOPOP_PARITYERR_SHIFT (14U)
-#define USART_FIFORDNOPOP_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_PARITYERR_SHIFT)) & USART_FIFORDNOPOP_PARITYERR_MASK)
-#define USART_FIFORDNOPOP_RXNOISE_MASK (0x8000U)
-#define USART_FIFORDNOPOP_RXNOISE_SHIFT (15U)
-#define USART_FIFORDNOPOP_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK)
-
-/*! @name ID - Peripheral identification register. */
-#define USART_ID_APERTURE_MASK (0xFFU)
-#define USART_ID_APERTURE_SHIFT (0U)
-#define USART_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_APERTURE_SHIFT)) & USART_ID_APERTURE_MASK)
-#define USART_ID_MINOR_REV_MASK (0xF00U)
-#define USART_ID_MINOR_REV_SHIFT (8U)
-#define USART_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MINOR_REV_SHIFT)) & USART_ID_MINOR_REV_MASK)
-#define USART_ID_MAJOR_REV_MASK (0xF000U)
-#define USART_ID_MAJOR_REV_SHIFT (12U)
-#define USART_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MAJOR_REV_SHIFT)) & USART_ID_MAJOR_REV_MASK)
-#define USART_ID_ID_MASK (0xFFFF0000U)
-#define USART_ID_ID_SHIFT (16U)
-#define USART_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_ID_SHIFT)) & USART_ID_ID_MASK)
-
-
-/*!
- * @}
- */ /* end of group USART_Register_Masks */
-
-
-/* USART - Peripheral instance base addresses */
-/** Peripheral USART0 base address */
-#define USART0_BASE (0x40086000u)
-/** Peripheral USART0 base pointer */
-#define USART0 ((USART_Type *)USART0_BASE)
-/** Peripheral USART1 base address */
-#define USART1_BASE (0x40087000u)
-/** Peripheral USART1 base pointer */
-#define USART1 ((USART_Type *)USART1_BASE)
-/** Peripheral USART2 base address */
-#define USART2_BASE (0x40088000u)
-/** Peripheral USART2 base pointer */
-#define USART2 ((USART_Type *)USART2_BASE)
-/** Peripheral USART3 base address */
-#define USART3_BASE (0x40089000u)
-/** Peripheral USART3 base pointer */
-#define USART3 ((USART_Type *)USART3_BASE)
-/** Peripheral USART4 base address */
-#define USART4_BASE (0x4008A000u)
-/** Peripheral USART4 base pointer */
-#define USART4 ((USART_Type *)USART4_BASE)
-/** Peripheral USART5 base address */
-#define USART5_BASE (0x40096000u)
-/** Peripheral USART5 base pointer */
-#define USART5 ((USART_Type *)USART5_BASE)
-/** Peripheral USART6 base address */
-#define USART6_BASE (0x40097000u)
-/** Peripheral USART6 base pointer */
-#define USART6 ((USART_Type *)USART6_BASE)
-/** Peripheral USART7 base address */
-#define USART7_BASE (0x40098000u)
-/** Peripheral USART7 base pointer */
-#define USART7 ((USART_Type *)USART7_BASE)
-/** Peripheral USART8 base address */
-#define USART8_BASE (0x40099000u)
-/** Peripheral USART8 base pointer */
-#define USART8 ((USART_Type *)USART8_BASE)
-/** Peripheral USART9 base address */
-#define USART9_BASE (0x4009A000u)
-/** Peripheral USART9 base pointer */
-#define USART9 ((USART_Type *)USART9_BASE)
-/** Array initializer of USART peripheral base addresses */
-#define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE, USART8_BASE, USART9_BASE }
-/** Array initializer of USART peripheral base pointers */
-#define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7, USART8, USART9 }
-/** Interrupt vectors for the USART peripheral type */
-#define USART_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn }
-
-/*!
- * @}
- */ /* end of group USART_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- USB Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
- * @{
- */
-
-/** USB - Register Layout Typedef */
-typedef struct {
- __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */
- __IO uint32_t INFO; /**< USB Info register, offset: 0x4 */
- __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */
- __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */
- __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */
- __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */
- __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */
- __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */
- __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */
- __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */
- __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */
- uint8_t RESERVED_0[8];
- __IO uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */
-} USB_Type;
-
-/* ----------------------------------------------------------------------------
- -- USB Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup USB_Register_Masks USB Register Masks
- * @{
- */
-
-/*! @name DEVCMDSTAT - USB Device Command/Status register */
-#define USB_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU)
-#define USB_DEVCMDSTAT_DEV_ADDR_SHIFT (0U)
-#define USB_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USB_DEVCMDSTAT_DEV_ADDR_MASK)
-#define USB_DEVCMDSTAT_DEV_EN_MASK (0x80U)
-#define USB_DEVCMDSTAT_DEV_EN_SHIFT (7U)
-#define USB_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_EN_SHIFT)) & USB_DEVCMDSTAT_DEV_EN_MASK)
-#define USB_DEVCMDSTAT_SETUP_MASK (0x100U)
-#define USB_DEVCMDSTAT_SETUP_SHIFT (8U)
-#define USB_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_SETUP_SHIFT)) & USB_DEVCMDSTAT_SETUP_MASK)
-#define USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U)
-#define USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U)
-#define USB_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK)
-#define USB_DEVCMDSTAT_LPM_SUP_MASK (0x800U)
-#define USB_DEVCMDSTAT_LPM_SUP_SHIFT (11U)
-#define USB_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUP_SHIFT)) & USB_DEVCMDSTAT_LPM_SUP_MASK)
-#define USB_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U)
-#define USB_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U)
-#define USB_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AO_MASK)
-#define USB_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U)
-#define USB_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U)
-#define USB_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AI_MASK)
-#define USB_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U)
-#define USB_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U)
-#define USB_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CO_MASK)
-#define USB_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U)
-#define USB_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U)
-#define USB_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CI_MASK)
-#define USB_DEVCMDSTAT_DCON_MASK (0x10000U)
-#define USB_DEVCMDSTAT_DCON_SHIFT (16U)
-#define USB_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_SHIFT)) & USB_DEVCMDSTAT_DCON_MASK)
-#define USB_DEVCMDSTAT_DSUS_MASK (0x20000U)
-#define USB_DEVCMDSTAT_DSUS_SHIFT (17U)
-#define USB_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_SHIFT)) & USB_DEVCMDSTAT_DSUS_MASK)
-#define USB_DEVCMDSTAT_LPM_SUS_MASK (0x80000U)
-#define USB_DEVCMDSTAT_LPM_SUS_SHIFT (19U)
-#define USB_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUS_SHIFT)) & USB_DEVCMDSTAT_LPM_SUS_MASK)
-#define USB_DEVCMDSTAT_LPM_REWP_MASK (0x100000U)
-#define USB_DEVCMDSTAT_LPM_REWP_SHIFT (20U)
-#define USB_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_REWP_SHIFT)) & USB_DEVCMDSTAT_LPM_REWP_MASK)
-#define USB_DEVCMDSTAT_DCON_C_MASK (0x1000000U)
-#define USB_DEVCMDSTAT_DCON_C_SHIFT (24U)
-#define USB_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_C_SHIFT)) & USB_DEVCMDSTAT_DCON_C_MASK)
-#define USB_DEVCMDSTAT_DSUS_C_MASK (0x2000000U)
-#define USB_DEVCMDSTAT_DSUS_C_SHIFT (25U)
-#define USB_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_C_SHIFT)) & USB_DEVCMDSTAT_DSUS_C_MASK)
-#define USB_DEVCMDSTAT_DRES_C_MASK (0x4000000U)
-#define USB_DEVCMDSTAT_DRES_C_SHIFT (26U)
-#define USB_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DRES_C_SHIFT)) & USB_DEVCMDSTAT_DRES_C_MASK)
-#define USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK (0x10000000U)
-#define USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT (28U)
-#define USB_DEVCMDSTAT_VBUSDEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT)) & USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK)
-
-/*! @name INFO - USB Info register */
-#define USB_INFO_FRAME_NR_MASK (0x7FFU)
-#define USB_INFO_FRAME_NR_SHIFT (0U)
-#define USB_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_FRAME_NR_SHIFT)) & USB_INFO_FRAME_NR_MASK)
-#define USB_INFO_ERR_CODE_MASK (0x7800U)
-#define USB_INFO_ERR_CODE_SHIFT (11U)
-#define USB_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_ERR_CODE_SHIFT)) & USB_INFO_ERR_CODE_MASK)
-#define USB_INFO_MINREV_MASK (0xFF0000U)
-#define USB_INFO_MINREV_SHIFT (16U)
-#define USB_INFO_MINREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MINREV_SHIFT)) & USB_INFO_MINREV_MASK)
-#define USB_INFO_MAJREV_MASK (0xFF000000U)
-#define USB_INFO_MAJREV_SHIFT (24U)
-#define USB_INFO_MAJREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MAJREV_SHIFT)) & USB_INFO_MAJREV_MASK)
-
-/*! @name EPLISTSTART - USB EP Command/Status List start address */
-#define USB_EPLISTSTART_EP_LIST_MASK (0xFFFFFF00U)
-#define USB_EPLISTSTART_EP_LIST_SHIFT (8U)
-#define USB_EPLISTSTART_EP_LIST(x) (((uint32_t)(((uint32_t)(x)) << USB_EPLISTSTART_EP_LIST_SHIFT)) & USB_EPLISTSTART_EP_LIST_MASK)
-
-/*! @name DATABUFSTART - USB Data buffer start address */
-#define USB_DATABUFSTART_DA_BUF_MASK (0xFFC00000U)
-#define USB_DATABUFSTART_DA_BUF_SHIFT (22U)
-#define USB_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_DATABUFSTART_DA_BUF_SHIFT)) & USB_DATABUFSTART_DA_BUF_MASK)
-
-/*! @name LPM - USB Link Power Management register */
-#define USB_LPM_HIRD_HW_MASK (0xFU)
-#define USB_LPM_HIRD_HW_SHIFT (0U)
-#define USB_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_HW_SHIFT)) & USB_LPM_HIRD_HW_MASK)
-#define USB_LPM_HIRD_SW_MASK (0xF0U)
-#define USB_LPM_HIRD_SW_SHIFT (4U)
-#define USB_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_SW_SHIFT)) & USB_LPM_HIRD_SW_MASK)
-#define USB_LPM_DATA_PENDING_MASK (0x100U)
-#define USB_LPM_DATA_PENDING_SHIFT (8U)
-#define USB_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_DATA_PENDING_SHIFT)) & USB_LPM_DATA_PENDING_MASK)
-
-/*! @name EPSKIP - USB Endpoint skip */
-#define USB_EPSKIP_SKIP_MASK (0x3FFU)
-#define USB_EPSKIP_SKIP_SHIFT (0U)
-#define USB_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USB_EPSKIP_SKIP_SHIFT)) & USB_EPSKIP_SKIP_MASK)
-
-/*! @name EPINUSE - USB Endpoint Buffer in use */
-#define USB_EPINUSE_BUF_MASK (0x3FCU)
-#define USB_EPINUSE_BUF_SHIFT (2U)
-#define USB_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_EPINUSE_BUF_SHIFT)) & USB_EPINUSE_BUF_MASK)
-
-/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */
-#define USB_EPBUFCFG_BUF_SB_MASK (0x3FCU)
-#define USB_EPBUFCFG_BUF_SB_SHIFT (2U)
-#define USB_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USB_EPBUFCFG_BUF_SB_SHIFT)) & USB_EPBUFCFG_BUF_SB_MASK)
-
-/*! @name INTSTAT - USB interrupt status register */
-#define USB_INTSTAT_EP0OUT_MASK (0x1U)
-#define USB_INTSTAT_EP0OUT_SHIFT (0U)
-#define USB_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0OUT_SHIFT)) & USB_INTSTAT_EP0OUT_MASK)
-#define USB_INTSTAT_EP0IN_MASK (0x2U)
-#define USB_INTSTAT_EP0IN_SHIFT (1U)
-#define USB_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0IN_SHIFT)) & USB_INTSTAT_EP0IN_MASK)
-#define USB_INTSTAT_EP1OUT_MASK (0x4U)
-#define USB_INTSTAT_EP1OUT_SHIFT (2U)
-#define USB_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1OUT_SHIFT)) & USB_INTSTAT_EP1OUT_MASK)
-#define USB_INTSTAT_EP1IN_MASK (0x8U)
-#define USB_INTSTAT_EP1IN_SHIFT (3U)
-#define USB_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1IN_SHIFT)) & USB_INTSTAT_EP1IN_MASK)
-#define USB_INTSTAT_EP2OUT_MASK (0x10U)
-#define USB_INTSTAT_EP2OUT_SHIFT (4U)
-#define USB_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2OUT_SHIFT)) & USB_INTSTAT_EP2OUT_MASK)
-#define USB_INTSTAT_EP2IN_MASK (0x20U)
-#define USB_INTSTAT_EP2IN_SHIFT (5U)
-#define USB_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2IN_SHIFT)) & USB_INTSTAT_EP2IN_MASK)
-#define USB_INTSTAT_EP3OUT_MASK (0x40U)
-#define USB_INTSTAT_EP3OUT_SHIFT (6U)
-#define USB_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3OUT_SHIFT)) & USB_INTSTAT_EP3OUT_MASK)
-#define USB_INTSTAT_EP3IN_MASK (0x80U)
-#define USB_INTSTAT_EP3IN_SHIFT (7U)
-#define USB_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3IN_SHIFT)) & USB_INTSTAT_EP3IN_MASK)
-#define USB_INTSTAT_EP4OUT_MASK (0x100U)
-#define USB_INTSTAT_EP4OUT_SHIFT (8U)
-#define USB_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4OUT_SHIFT)) & USB_INTSTAT_EP4OUT_MASK)
-#define USB_INTSTAT_EP4IN_MASK (0x200U)
-#define USB_INTSTAT_EP4IN_SHIFT (9U)
-#define USB_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4IN_SHIFT)) & USB_INTSTAT_EP4IN_MASK)
-#define USB_INTSTAT_FRAME_INT_MASK (0x40000000U)
-#define USB_INTSTAT_FRAME_INT_SHIFT (30U)
-#define USB_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_FRAME_INT_SHIFT)) & USB_INTSTAT_FRAME_INT_MASK)
-#define USB_INTSTAT_DEV_INT_MASK (0x80000000U)
-#define USB_INTSTAT_DEV_INT_SHIFT (31U)
-#define USB_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_DEV_INT_SHIFT)) & USB_INTSTAT_DEV_INT_MASK)
-
-/*! @name INTEN - USB interrupt enable register */
-#define USB_INTEN_EP_INT_EN_MASK (0x3FFU)
-#define USB_INTEN_EP_INT_EN_SHIFT (0U)
-#define USB_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_EP_INT_EN_SHIFT)) & USB_INTEN_EP_INT_EN_MASK)
-#define USB_INTEN_FRAME_INT_EN_MASK (0x40000000U)
-#define USB_INTEN_FRAME_INT_EN_SHIFT (30U)
-#define USB_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_FRAME_INT_EN_SHIFT)) & USB_INTEN_FRAME_INT_EN_MASK)
-#define USB_INTEN_DEV_INT_EN_MASK (0x80000000U)
-#define USB_INTEN_DEV_INT_EN_SHIFT (31U)
-#define USB_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_DEV_INT_EN_SHIFT)) & USB_INTEN_DEV_INT_EN_MASK)
-
-/*! @name INTSETSTAT - USB set interrupt status register */
-#define USB_INTSETSTAT_EP_SET_INT_MASK (0x3FFU)
-#define USB_INTSETSTAT_EP_SET_INT_SHIFT (0U)
-#define USB_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_EP_SET_INT_SHIFT)) & USB_INTSETSTAT_EP_SET_INT_MASK)
-#define USB_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U)
-#define USB_INTSETSTAT_FRAME_SET_INT_SHIFT (30U)
-#define USB_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USB_INTSETSTAT_FRAME_SET_INT_MASK)
-#define USB_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U)
-#define USB_INTSETSTAT_DEV_SET_INT_SHIFT (31U)
-#define USB_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_DEV_SET_INT_SHIFT)) & USB_INTSETSTAT_DEV_SET_INT_MASK)
-
-/*! @name EPTOGGLE - USB Endpoint toggle register */
-#define USB_EPTOGGLE_TOGGLE_MASK (0x3FFU)
-#define USB_EPTOGGLE_TOGGLE_SHIFT (0U)
-#define USB_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USB_EPTOGGLE_TOGGLE_SHIFT)) & USB_EPTOGGLE_TOGGLE_MASK)
-
-
-/*!
- * @}
- */ /* end of group USB_Register_Masks */
-
-
-/* USB - Peripheral instance base addresses */
-/** Peripheral USB0 base address */
-#define USB0_BASE (0x40084000u)
-/** Peripheral USB0 base pointer */
-#define USB0 ((USB_Type *)USB0_BASE)
-/** Array initializer of USB peripheral base addresses */
-#define USB_BASE_ADDRS { USB0_BASE }
-/** Array initializer of USB peripheral base pointers */
-#define USB_BASE_PTRS { USB0 }
-/** Interrupt vectors for the USB peripheral type */
-#define USB_IRQS { USB0_IRQn }
-#define USB_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn }
-
-/*!
- * @}
- */ /* end of group USB_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- USBFSH Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup USBFSH_Peripheral_Access_Layer USBFSH Peripheral Access Layer
- * @{
- */
-
-/** USBFSH - Register Layout Typedef */
-typedef struct {
- __I uint32_t HCREVISION; /**< BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC), offset: 0x0 */
- __IO uint32_t HCCONTROL; /**< Defines the operating modes of the HC, offset: 0x4 */
- __IO uint32_t HCCOMMANDSTATUS; /**< This register is used to receive the commands from the Host Controller Driver (HCD), offset: 0x8 */
- __IO uint32_t HCINTERRUPTSTATUS; /**< Indicates the status on various events that cause hardware interrupts by setting the appropriate bits, offset: 0xC */
- __IO uint32_t HCINTERRUPTENABLE; /**< Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt, offset: 0x10 */
- __IO uint32_t HCINTERRUPTDISABLE; /**< The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt, offset: 0x14 */
- __IO uint32_t HCHCCA; /**< Contains the physical address of the host controller communication area, offset: 0x18 */
- __IO uint32_t HCPERIODCURRENTED; /**< Contains the physical address of the current isochronous or interrupt endpoint descriptor, offset: 0x1C */
- __IO uint32_t HCCONTROLHEADED; /**< Contains the physical address of the first endpoint descriptor of the control list, offset: 0x20 */
- __IO uint32_t HCCONTROLCURRENTED; /**< Contains the physical address of the current endpoint descriptor of the control list, offset: 0x24 */
- __IO uint32_t HCBULKHEADED; /**< Contains the physical address of the first endpoint descriptor of the bulk list, offset: 0x28 */
- __IO uint32_t HCBULKCURRENTED; /**< Contains the physical address of the current endpoint descriptor of the bulk list, offset: 0x2C */
- __IO uint32_t HCDONEHEAD; /**< Contains the physical address of the last transfer descriptor added to the 'Done' queue, offset: 0x30 */
- __IO uint32_t HCFMINTERVAL; /**< Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun, offset: 0x34 */
- __IO uint32_t HCFMREMAINING; /**< A 14-bit counter showing the bit time remaining in the current frame, offset: 0x38 */
- __IO uint32_t HCFMNUMBER; /**< Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD, offset: 0x3C */
- __IO uint32_t HCPERIODICSTART; /**< Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list, offset: 0x40 */
- __IO uint32_t HCLSTHRESHOLD; /**< Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF, offset: 0x44 */
- __IO uint32_t HCRHDESCRIPTORA; /**< First of the two registers which describes the characteristics of the root hub, offset: 0x48 */
- __IO uint32_t HCRHDESCRIPTORB; /**< Second of the two registers which describes the characteristics of the Root Hub, offset: 0x4C */
- __IO uint32_t HCRHSTATUS; /**< This register is divided into two parts, offset: 0x50 */
- __IO uint32_t HCRHPORTSTATUS; /**< Controls and reports the port events on a per-port basis, offset: 0x54 */
- uint8_t RESERVED_0[4];
- __IO uint32_t PORTMODE; /**< Controls the port if it is attached to the host block or the device block, offset: 0x5C */
-} USBFSH_Type;
-
-/* ----------------------------------------------------------------------------
- -- USBFSH Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup USBFSH_Register_Masks USBFSH Register Masks
- * @{
- */
-
-/*! @name HCREVISION - BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC) */
-#define USBFSH_HCREVISION_REV_MASK (0xFFU)
-#define USBFSH_HCREVISION_REV_SHIFT (0U)
-#define USBFSH_HCREVISION_REV(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCREVISION_REV_SHIFT)) & USBFSH_HCREVISION_REV_MASK)
-
-/*! @name HCCONTROL - Defines the operating modes of the HC */
-#define USBFSH_HCCONTROL_CBSR_MASK (0x3U)
-#define USBFSH_HCCONTROL_CBSR_SHIFT (0U)
-#define USBFSH_HCCONTROL_CBSR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CBSR_SHIFT)) & USBFSH_HCCONTROL_CBSR_MASK)
-#define USBFSH_HCCONTROL_PLE_MASK (0x4U)
-#define USBFSH_HCCONTROL_PLE_SHIFT (2U)
-#define USBFSH_HCCONTROL_PLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_PLE_SHIFT)) & USBFSH_HCCONTROL_PLE_MASK)
-#define USBFSH_HCCONTROL_IE_MASK (0x8U)
-#define USBFSH_HCCONTROL_IE_SHIFT (3U)
-#define USBFSH_HCCONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IE_SHIFT)) & USBFSH_HCCONTROL_IE_MASK)
-#define USBFSH_HCCONTROL_CLE_MASK (0x10U)
-#define USBFSH_HCCONTROL_CLE_SHIFT (4U)
-#define USBFSH_HCCONTROL_CLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CLE_SHIFT)) & USBFSH_HCCONTROL_CLE_MASK)
-#define USBFSH_HCCONTROL_BLE_MASK (0x20U)
-#define USBFSH_HCCONTROL_BLE_SHIFT (5U)
-#define USBFSH_HCCONTROL_BLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_BLE_SHIFT)) & USBFSH_HCCONTROL_BLE_MASK)
-#define USBFSH_HCCONTROL_HCFS_MASK (0xC0U)
-#define USBFSH_HCCONTROL_HCFS_SHIFT (6U)
-#define USBFSH_HCCONTROL_HCFS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_HCFS_SHIFT)) & USBFSH_HCCONTROL_HCFS_MASK)
-#define USBFSH_HCCONTROL_IR_MASK (0x100U)
-#define USBFSH_HCCONTROL_IR_SHIFT (8U)
-#define USBFSH_HCCONTROL_IR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IR_SHIFT)) & USBFSH_HCCONTROL_IR_MASK)
-#define USBFSH_HCCONTROL_RWC_MASK (0x200U)
-#define USBFSH_HCCONTROL_RWC_SHIFT (9U)
-#define USBFSH_HCCONTROL_RWC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWC_SHIFT)) & USBFSH_HCCONTROL_RWC_MASK)
-#define USBFSH_HCCONTROL_RWE_MASK (0x400U)
-#define USBFSH_HCCONTROL_RWE_SHIFT (10U)
-#define USBFSH_HCCONTROL_RWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWE_SHIFT)) & USBFSH_HCCONTROL_RWE_MASK)
-
-/*! @name HCCOMMANDSTATUS - This register is used to receive the commands from the Host Controller Driver (HCD) */
-#define USBFSH_HCCOMMANDSTATUS_HCR_MASK (0x1U)
-#define USBFSH_HCCOMMANDSTATUS_HCR_SHIFT (0U)
-#define USBFSH_HCCOMMANDSTATUS_HCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_HCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_HCR_MASK)
-#define USBFSH_HCCOMMANDSTATUS_CLF_MASK (0x2U)
-#define USBFSH_HCCOMMANDSTATUS_CLF_SHIFT (1U)
-#define USBFSH_HCCOMMANDSTATUS_CLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_CLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_CLF_MASK)
-#define USBFSH_HCCOMMANDSTATUS_BLF_MASK (0x4U)
-#define USBFSH_HCCOMMANDSTATUS_BLF_SHIFT (2U)
-#define USBFSH_HCCOMMANDSTATUS_BLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_BLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_BLF_MASK)
-#define USBFSH_HCCOMMANDSTATUS_OCR_MASK (0x8U)
-#define USBFSH_HCCOMMANDSTATUS_OCR_SHIFT (3U)
-#define USBFSH_HCCOMMANDSTATUS_OCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_OCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_OCR_MASK)
-#define USBFSH_HCCOMMANDSTATUS_SOC_MASK (0xC0U)
-#define USBFSH_HCCOMMANDSTATUS_SOC_SHIFT (6U)
-#define USBFSH_HCCOMMANDSTATUS_SOC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_SOC_SHIFT)) & USBFSH_HCCOMMANDSTATUS_SOC_MASK)
-
-/*! @name HCINTERRUPTSTATUS - Indicates the status on various events that cause hardware interrupts by setting the appropriate bits */
-#define USBFSH_HCINTERRUPTSTATUS_SO_MASK (0x1U)
-#define USBFSH_HCINTERRUPTSTATUS_SO_SHIFT (0U)
-#define USBFSH_HCINTERRUPTSTATUS_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SO_MASK)
-#define USBFSH_HCINTERRUPTSTATUS_WDH_MASK (0x2U)
-#define USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT (1U)
-#define USBFSH_HCINTERRUPTSTATUS_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_WDH_MASK)
-#define USBFSH_HCINTERRUPTSTATUS_SF_MASK (0x4U)
-#define USBFSH_HCINTERRUPTSTATUS_SF_SHIFT (2U)
-#define USBFSH_HCINTERRUPTSTATUS_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SF_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SF_MASK)
-#define USBFSH_HCINTERRUPTSTATUS_RD_MASK (0x8U)
-#define USBFSH_HCINTERRUPTSTATUS_RD_SHIFT (3U)
-#define USBFSH_HCINTERRUPTSTATUS_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RD_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RD_MASK)
-#define USBFSH_HCINTERRUPTSTATUS_UE_MASK (0x10U)
-#define USBFSH_HCINTERRUPTSTATUS_UE_SHIFT (4U)
-#define USBFSH_HCINTERRUPTSTATUS_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_UE_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_UE_MASK)
-#define USBFSH_HCINTERRUPTSTATUS_FNO_MASK (0x20U)
-#define USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT (5U)
-#define USBFSH_HCINTERRUPTSTATUS_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_FNO_MASK)
-#define USBFSH_HCINTERRUPTSTATUS_RHSC_MASK (0x40U)
-#define USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT (6U)
-#define USBFSH_HCINTERRUPTSTATUS_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RHSC_MASK)
-#define USBFSH_HCINTERRUPTSTATUS_OC_MASK (0xFFFFFC00U)
-#define USBFSH_HCINTERRUPTSTATUS_OC_SHIFT (10U)
-#define USBFSH_HCINTERRUPTSTATUS_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_OC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_OC_MASK)
-
-/*! @name HCINTERRUPTENABLE - Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt */
-#define USBFSH_HCINTERRUPTENABLE_SO_MASK (0x1U)
-#define USBFSH_HCINTERRUPTENABLE_SO_SHIFT (0U)
-#define USBFSH_HCINTERRUPTENABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SO_MASK)
-#define USBFSH_HCINTERRUPTENABLE_WDH_MASK (0x2U)
-#define USBFSH_HCINTERRUPTENABLE_WDH_SHIFT (1U)
-#define USBFSH_HCINTERRUPTENABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTENABLE_WDH_MASK)
-#define USBFSH_HCINTERRUPTENABLE_SF_MASK (0x4U)
-#define USBFSH_HCINTERRUPTENABLE_SF_SHIFT (2U)
-#define USBFSH_HCINTERRUPTENABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SF_MASK)
-#define USBFSH_HCINTERRUPTENABLE_RD_MASK (0x8U)
-#define USBFSH_HCINTERRUPTENABLE_RD_SHIFT (3U)
-#define USBFSH_HCINTERRUPTENABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RD_MASK)
-#define USBFSH_HCINTERRUPTENABLE_UE_MASK (0x10U)
-#define USBFSH_HCINTERRUPTENABLE_UE_SHIFT (4U)
-#define USBFSH_HCINTERRUPTENABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_UE_MASK)
-#define USBFSH_HCINTERRUPTENABLE_FNO_MASK (0x20U)
-#define USBFSH_HCINTERRUPTENABLE_FNO_SHIFT (5U)
-#define USBFSH_HCINTERRUPTENABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_FNO_MASK)
-#define USBFSH_HCINTERRUPTENABLE_RHSC_MASK (0x40U)
-#define USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT (6U)
-#define USBFSH_HCINTERRUPTENABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RHSC_MASK)
-#define USBFSH_HCINTERRUPTENABLE_OC_MASK (0x40000000U)
-#define USBFSH_HCINTERRUPTENABLE_OC_SHIFT (30U)
-#define USBFSH_HCINTERRUPTENABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_OC_MASK)
-#define USBFSH_HCINTERRUPTENABLE_MIE_MASK (0x80000000U)
-#define USBFSH_HCINTERRUPTENABLE_MIE_SHIFT (31U)
-#define USBFSH_HCINTERRUPTENABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_MIE_MASK)
-
-/*! @name HCINTERRUPTDISABLE - The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt */
-#define USBFSH_HCINTERRUPTDISABLE_SO_MASK (0x1U)
-#define USBFSH_HCINTERRUPTDISABLE_SO_SHIFT (0U)
-#define USBFSH_HCINTERRUPTDISABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SO_MASK)
-#define USBFSH_HCINTERRUPTDISABLE_WDH_MASK (0x2U)
-#define USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT (1U)
-#define USBFSH_HCINTERRUPTDISABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_WDH_MASK)
-#define USBFSH_HCINTERRUPTDISABLE_SF_MASK (0x4U)
-#define USBFSH_HCINTERRUPTDISABLE_SF_SHIFT (2U)
-#define USBFSH_HCINTERRUPTDISABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SF_MASK)
-#define USBFSH_HCINTERRUPTDISABLE_RD_MASK (0x8U)
-#define USBFSH_HCINTERRUPTDISABLE_RD_SHIFT (3U)
-#define USBFSH_HCINTERRUPTDISABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RD_MASK)
-#define USBFSH_HCINTERRUPTDISABLE_UE_MASK (0x10U)
-#define USBFSH_HCINTERRUPTDISABLE_UE_SHIFT (4U)
-#define USBFSH_HCINTERRUPTDISABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_UE_MASK)
-#define USBFSH_HCINTERRUPTDISABLE_FNO_MASK (0x20U)
-#define USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT (5U)
-#define USBFSH_HCINTERRUPTDISABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_FNO_MASK)
-#define USBFSH_HCINTERRUPTDISABLE_RHSC_MASK (0x40U)
-#define USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT (6U)
-#define USBFSH_HCINTERRUPTDISABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RHSC_MASK)
-#define USBFSH_HCINTERRUPTDISABLE_OC_MASK (0x40000000U)
-#define USBFSH_HCINTERRUPTDISABLE_OC_SHIFT (30U)
-#define USBFSH_HCINTERRUPTDISABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_OC_MASK)
-#define USBFSH_HCINTERRUPTDISABLE_MIE_MASK (0x80000000U)
-#define USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT (31U)
-#define USBFSH_HCINTERRUPTDISABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_MIE_MASK)
-
-/*! @name HCHCCA - Contains the physical address of the host controller communication area */
-#define USBFSH_HCHCCA_HCCA_MASK (0xFFFFFF00U)
-#define USBFSH_HCHCCA_HCCA_SHIFT (8U)
-#define USBFSH_HCHCCA_HCCA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCHCCA_HCCA_SHIFT)) & USBFSH_HCHCCA_HCCA_MASK)
-
-/*! @name HCPERIODCURRENTED - Contains the physical address of the current isochronous or interrupt endpoint descriptor */
-#define USBFSH_HCPERIODCURRENTED_PCED_MASK (0xFFFFFFF0U)
-#define USBFSH_HCPERIODCURRENTED_PCED_SHIFT (4U)
-#define USBFSH_HCPERIODCURRENTED_PCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODCURRENTED_PCED_SHIFT)) & USBFSH_HCPERIODCURRENTED_PCED_MASK)
-
-/*! @name HCCONTROLHEADED - Contains the physical address of the first endpoint descriptor of the control list */
-#define USBFSH_HCCONTROLHEADED_CHED_MASK (0xFFFFFFF0U)
-#define USBFSH_HCCONTROLHEADED_CHED_SHIFT (4U)
-#define USBFSH_HCCONTROLHEADED_CHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLHEADED_CHED_SHIFT)) & USBFSH_HCCONTROLHEADED_CHED_MASK)
-
-/*! @name HCCONTROLCURRENTED - Contains the physical address of the current endpoint descriptor of the control list */
-#define USBFSH_HCCONTROLCURRENTED_CCED_MASK (0xFFFFFFF0U)
-#define USBFSH_HCCONTROLCURRENTED_CCED_SHIFT (4U)
-#define USBFSH_HCCONTROLCURRENTED_CCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLCURRENTED_CCED_SHIFT)) & USBFSH_HCCONTROLCURRENTED_CCED_MASK)
-
-/*! @name HCBULKHEADED - Contains the physical address of the first endpoint descriptor of the bulk list */
-#define USBFSH_HCBULKHEADED_BHED_MASK (0xFFFFFFF0U)
-#define USBFSH_HCBULKHEADED_BHED_SHIFT (4U)
-#define USBFSH_HCBULKHEADED_BHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKHEADED_BHED_SHIFT)) & USBFSH_HCBULKHEADED_BHED_MASK)
-
-/*! @name HCBULKCURRENTED - Contains the physical address of the current endpoint descriptor of the bulk list */
-#define USBFSH_HCBULKCURRENTED_BCED_MASK (0xFFFFFFF0U)
-#define USBFSH_HCBULKCURRENTED_BCED_SHIFT (4U)
-#define USBFSH_HCBULKCURRENTED_BCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKCURRENTED_BCED_SHIFT)) & USBFSH_HCBULKCURRENTED_BCED_MASK)
-
-/*! @name HCDONEHEAD - Contains the physical address of the last transfer descriptor added to the 'Done' queue */
-#define USBFSH_HCDONEHEAD_DH_MASK (0xFFFFFFF0U)
-#define USBFSH_HCDONEHEAD_DH_SHIFT (4U)
-#define USBFSH_HCDONEHEAD_DH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCDONEHEAD_DH_SHIFT)) & USBFSH_HCDONEHEAD_DH_MASK)
-
-/*! @name HCFMINTERVAL - Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun */
-#define USBFSH_HCFMINTERVAL_FI_MASK (0x3FFFU)
-#define USBFSH_HCFMINTERVAL_FI_SHIFT (0U)
-#define USBFSH_HCFMINTERVAL_FI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FI_SHIFT)) & USBFSH_HCFMINTERVAL_FI_MASK)
-#define USBFSH_HCFMINTERVAL_FSMPS_MASK (0x7FFF0000U)
-#define USBFSH_HCFMINTERVAL_FSMPS_SHIFT (16U)
-#define USBFSH_HCFMINTERVAL_FSMPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FSMPS_SHIFT)) & USBFSH_HCFMINTERVAL_FSMPS_MASK)
-#define USBFSH_HCFMINTERVAL_FIT_MASK (0x80000000U)
-#define USBFSH_HCFMINTERVAL_FIT_SHIFT (31U)
-#define USBFSH_HCFMINTERVAL_FIT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FIT_SHIFT)) & USBFSH_HCFMINTERVAL_FIT_MASK)
-
-/*! @name HCFMREMAINING - A 14-bit counter showing the bit time remaining in the current frame */
-#define USBFSH_HCFMREMAINING_FR_MASK (0x3FFFU)
-#define USBFSH_HCFMREMAINING_FR_SHIFT (0U)
-#define USBFSH_HCFMREMAINING_FR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FR_SHIFT)) & USBFSH_HCFMREMAINING_FR_MASK)
-#define USBFSH_HCFMREMAINING_FRT_MASK (0x80000000U)
-#define USBFSH_HCFMREMAINING_FRT_SHIFT (31U)
-#define USBFSH_HCFMREMAINING_FRT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FRT_SHIFT)) & USBFSH_HCFMREMAINING_FRT_MASK)
-
-/*! @name HCFMNUMBER - Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD */
-#define USBFSH_HCFMNUMBER_FN_MASK (0xFFFFU)
-#define USBFSH_HCFMNUMBER_FN_SHIFT (0U)
-#define USBFSH_HCFMNUMBER_FN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMNUMBER_FN_SHIFT)) & USBFSH_HCFMNUMBER_FN_MASK)
-
-/*! @name HCPERIODICSTART - Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list */
-#define USBFSH_HCPERIODICSTART_PS_MASK (0x3FFFU)
-#define USBFSH_HCPERIODICSTART_PS_SHIFT (0U)
-#define USBFSH_HCPERIODICSTART_PS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODICSTART_PS_SHIFT)) & USBFSH_HCPERIODICSTART_PS_MASK)
-
-/*! @name HCLSTHRESHOLD - Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF */
-#define USBFSH_HCLSTHRESHOLD_LST_MASK (0xFFFU)
-#define USBFSH_HCLSTHRESHOLD_LST_SHIFT (0U)
-#define USBFSH_HCLSTHRESHOLD_LST(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCLSTHRESHOLD_LST_SHIFT)) & USBFSH_HCLSTHRESHOLD_LST_MASK)
-
-/*! @name HCRHDESCRIPTORA - First of the two registers which describes the characteristics of the root hub */
-#define USBFSH_HCRHDESCRIPTORA_NDP_MASK (0xFFU)
-#define USBFSH_HCRHDESCRIPTORA_NDP_SHIFT (0U)
-#define USBFSH_HCRHDESCRIPTORA_NDP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NDP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NDP_MASK)
-#define USBFSH_HCRHDESCRIPTORA_PSM_MASK (0x100U)
-#define USBFSH_HCRHDESCRIPTORA_PSM_SHIFT (8U)
-#define USBFSH_HCRHDESCRIPTORA_PSM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_PSM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_PSM_MASK)
-#define USBFSH_HCRHDESCRIPTORA_NPS_MASK (0x200U)
-#define USBFSH_HCRHDESCRIPTORA_NPS_SHIFT (9U)
-#define USBFSH_HCRHDESCRIPTORA_NPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NPS_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NPS_MASK)
-#define USBFSH_HCRHDESCRIPTORA_DT_MASK (0x400U)
-#define USBFSH_HCRHDESCRIPTORA_DT_SHIFT (10U)
-#define USBFSH_HCRHDESCRIPTORA_DT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_DT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_DT_MASK)
-#define USBFSH_HCRHDESCRIPTORA_OCPM_MASK (0x800U)
-#define USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT (11U)
-#define USBFSH_HCRHDESCRIPTORA_OCPM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_OCPM_MASK)
-#define USBFSH_HCRHDESCRIPTORA_NOCP_MASK (0x1000U)
-#define USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT (12U)
-#define USBFSH_HCRHDESCRIPTORA_NOCP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NOCP_MASK)
-#define USBFSH_HCRHDESCRIPTORA_POTPGT_MASK (0xFF000000U)
-#define USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT (24U)
-#define USBFSH_HCRHDESCRIPTORA_POTPGT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_POTPGT_MASK)
-
-/*! @name HCRHDESCRIPTORB - Second of the two registers which describes the characteristics of the Root Hub */
-#define USBFSH_HCRHDESCRIPTORB_DR_MASK (0xFFFFU)
-#define USBFSH_HCRHDESCRIPTORB_DR_SHIFT (0U)
-#define USBFSH_HCRHDESCRIPTORB_DR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_DR_SHIFT)) & USBFSH_HCRHDESCRIPTORB_DR_MASK)
-#define USBFSH_HCRHDESCRIPTORB_PPCM_MASK (0xFFFF0000U)
-#define USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT (16U)
-#define USBFSH_HCRHDESCRIPTORB_PPCM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT)) & USBFSH_HCRHDESCRIPTORB_PPCM_MASK)
-
-/*! @name HCRHSTATUS - This register is divided into two parts */
-#define USBFSH_HCRHSTATUS_LPS_MASK (0x1U)
-#define USBFSH_HCRHSTATUS_LPS_SHIFT (0U)
-#define USBFSH_HCRHSTATUS_LPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPS_SHIFT)) & USBFSH_HCRHSTATUS_LPS_MASK)
-#define USBFSH_HCRHSTATUS_OCI_MASK (0x2U)
-#define USBFSH_HCRHSTATUS_OCI_SHIFT (1U)
-#define USBFSH_HCRHSTATUS_OCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCI_SHIFT)) & USBFSH_HCRHSTATUS_OCI_MASK)
-#define USBFSH_HCRHSTATUS_DRWE_MASK (0x8000U)
-#define USBFSH_HCRHSTATUS_DRWE_SHIFT (15U)
-#define USBFSH_HCRHSTATUS_DRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_DRWE_SHIFT)) & USBFSH_HCRHSTATUS_DRWE_MASK)
-#define USBFSH_HCRHSTATUS_LPSC_MASK (0x10000U)
-#define USBFSH_HCRHSTATUS_LPSC_SHIFT (16U)
-#define USBFSH_HCRHSTATUS_LPSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPSC_SHIFT)) & USBFSH_HCRHSTATUS_LPSC_MASK)
-#define USBFSH_HCRHSTATUS_OCIC_MASK (0x20000U)
-#define USBFSH_HCRHSTATUS_OCIC_SHIFT (17U)
-#define USBFSH_HCRHSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCIC_SHIFT)) & USBFSH_HCRHSTATUS_OCIC_MASK)
-#define USBFSH_HCRHSTATUS_CRWE_MASK (0x80000000U)
-#define USBFSH_HCRHSTATUS_CRWE_SHIFT (31U)
-#define USBFSH_HCRHSTATUS_CRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_CRWE_SHIFT)) & USBFSH_HCRHSTATUS_CRWE_MASK)
-
-/*! @name HCRHPORTSTATUS - Controls and reports the port events on a per-port basis */
-#define USBFSH_HCRHPORTSTATUS_CCS_MASK (0x1U)
-#define USBFSH_HCRHPORTSTATUS_CCS_SHIFT (0U)
-#define USBFSH_HCRHPORTSTATUS_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CCS_SHIFT)) & USBFSH_HCRHPORTSTATUS_CCS_MASK)
-#define USBFSH_HCRHPORTSTATUS_PES_MASK (0x2U)
-#define USBFSH_HCRHPORTSTATUS_PES_SHIFT (1U)
-#define USBFSH_HCRHPORTSTATUS_PES(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PES_SHIFT)) & USBFSH_HCRHPORTSTATUS_PES_MASK)
-#define USBFSH_HCRHPORTSTATUS_PSS_MASK (0x4U)
-#define USBFSH_HCRHPORTSTATUS_PSS_SHIFT (2U)
-#define USBFSH_HCRHPORTSTATUS_PSS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSS_MASK)
-#define USBFSH_HCRHPORTSTATUS_POCI_MASK (0x8U)
-#define USBFSH_HCRHPORTSTATUS_POCI_SHIFT (3U)
-#define USBFSH_HCRHPORTSTATUS_POCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_POCI_SHIFT)) & USBFSH_HCRHPORTSTATUS_POCI_MASK)
-#define USBFSH_HCRHPORTSTATUS_PRS_MASK (0x10U)
-#define USBFSH_HCRHPORTSTATUS_PRS_SHIFT (4U)
-#define USBFSH_HCRHPORTSTATUS_PRS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRS_MASK)
-#define USBFSH_HCRHPORTSTATUS_PPS_MASK (0x100U)
-#define USBFSH_HCRHPORTSTATUS_PPS_SHIFT (8U)
-#define USBFSH_HCRHPORTSTATUS_PPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PPS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PPS_MASK)
-#define USBFSH_HCRHPORTSTATUS_LSDA_MASK (0x200U)
-#define USBFSH_HCRHPORTSTATUS_LSDA_SHIFT (9U)
-#define USBFSH_HCRHPORTSTATUS_LSDA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_LSDA_SHIFT)) & USBFSH_HCRHPORTSTATUS_LSDA_MASK)
-#define USBFSH_HCRHPORTSTATUS_CSC_MASK (0x10000U)
-#define USBFSH_HCRHPORTSTATUS_CSC_SHIFT (16U)
-#define USBFSH_HCRHPORTSTATUS_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_CSC_MASK)
-#define USBFSH_HCRHPORTSTATUS_PESC_MASK (0x20000U)
-#define USBFSH_HCRHPORTSTATUS_PESC_SHIFT (17U)
-#define USBFSH_HCRHPORTSTATUS_PESC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PESC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PESC_MASK)
-#define USBFSH_HCRHPORTSTATUS_PSSC_MASK (0x40000U)
-#define USBFSH_HCRHPORTSTATUS_PSSC_SHIFT (18U)
-#define USBFSH_HCRHPORTSTATUS_PSSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSSC_MASK)
-#define USBFSH_HCRHPORTSTATUS_OCIC_MASK (0x80000U)
-#define USBFSH_HCRHPORTSTATUS_OCIC_SHIFT (19U)
-#define USBFSH_HCRHPORTSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_OCIC_SHIFT)) & USBFSH_HCRHPORTSTATUS_OCIC_MASK)
-#define USBFSH_HCRHPORTSTATUS_PRSC_MASK (0x100000U)
-#define USBFSH_HCRHPORTSTATUS_PRSC_SHIFT (20U)
-#define USBFSH_HCRHPORTSTATUS_PRSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRSC_MASK)
-
-/*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */
-#define USBFSH_PORTMODE_ID_MASK (0x1U)
-#define USBFSH_PORTMODE_ID_SHIFT (0U)
-#define USBFSH_PORTMODE_ID(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_SHIFT)) & USBFSH_PORTMODE_ID_MASK)
-#define USBFSH_PORTMODE_ID_EN_MASK (0x100U)
-#define USBFSH_PORTMODE_ID_EN_SHIFT (8U)
-#define USBFSH_PORTMODE_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_EN_SHIFT)) & USBFSH_PORTMODE_ID_EN_MASK)
-#define USBFSH_PORTMODE_DEV_ENABLE_MASK (0x10000U)
-#define USBFSH_PORTMODE_DEV_ENABLE_SHIFT (16U)
-#define USBFSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBFSH_PORTMODE_DEV_ENABLE_MASK)
-
-
-/*!
- * @}
- */ /* end of group USBFSH_Register_Masks */
-
-
-/* USBFSH - Peripheral instance base addresses */
-/** Peripheral USBFSH base address */
-#define USBFSH_BASE (0x400A2000u)
-/** Peripheral USBFSH base pointer */
-#define USBFSH ((USBFSH_Type *)USBFSH_BASE)
-/** Array initializer of USBFSH peripheral base addresses */
-#define USBFSH_BASE_ADDRS { USBFSH_BASE }
-/** Array initializer of USBFSH peripheral base pointers */
-#define USBFSH_BASE_PTRS { USBFSH }
-/** Interrupt vectors for the USBFSH peripheral type */
-#define USBFSH_IRQS { USB0_IRQn }
-#define USBFSH_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn }
-
-/*!
- * @}
- */ /* end of group USBFSH_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- USBHSD Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup USBHSD_Peripheral_Access_Layer USBHSD Peripheral Access Layer
- * @{
- */
-
-/** USBHSD - Register Layout Typedef */
-typedef struct {
- __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */
- __I uint32_t INFO; /**< USB Info register, offset: 0x4 */
- __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */
- __I uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */
- __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */
- __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */
- __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */
- __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */
- __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */
- __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */
- __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */
- uint8_t RESERVED_0[8];
- __I uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */
- uint8_t RESERVED_1[4];
- __IO uint32_t ULPIDEBUG; /**< UTMI/ULPI debug register, offset: 0x3C */
-} USBHSD_Type;
-
-/* ----------------------------------------------------------------------------
- -- USBHSD Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup USBHSD_Register_Masks USBHSD Register Masks
- * @{
- */
-
-/*! @name DEVCMDSTAT - USB Device Command/Status register */
-#define USBHSD_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU)
-#define USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT (0U)
-#define USBHSD_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_ADDR_MASK)
-#define USBHSD_DEVCMDSTAT_DEV_EN_MASK (0x80U)
-#define USBHSD_DEVCMDSTAT_DEV_EN_SHIFT (7U)
-#define USBHSD_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_EN_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_EN_MASK)
-#define USBHSD_DEVCMDSTAT_SETUP_MASK (0x100U)
-#define USBHSD_DEVCMDSTAT_SETUP_SHIFT (8U)
-#define USBHSD_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_SETUP_SHIFT)) & USBHSD_DEVCMDSTAT_SETUP_MASK)
-#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U)
-#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U)
-#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK)
-#define USBHSD_DEVCMDSTAT_FORCE_VBUS_MASK (0x400U)
-#define USBHSD_DEVCMDSTAT_FORCE_VBUS_SHIFT (10U)
-#define USBHSD_DEVCMDSTAT_FORCE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_VBUS_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_VBUS_MASK)
-#define USBHSD_DEVCMDSTAT_LPM_SUP_MASK (0x800U)
-#define USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT (11U)
-#define USBHSD_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUP_MASK)
-#define USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U)
-#define USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U)
-#define USBHSD_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK)
-#define USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U)
-#define USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U)
-#define USBHSD_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK)
-#define USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U)
-#define USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U)
-#define USBHSD_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK)
-#define USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U)
-#define USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U)
-#define USBHSD_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK)
-#define USBHSD_DEVCMDSTAT_DCON_MASK (0x10000U)
-#define USBHSD_DEVCMDSTAT_DCON_SHIFT (16U)
-#define USBHSD_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_MASK)
-#define USBHSD_DEVCMDSTAT_DSUS_MASK (0x20000U)
-#define USBHSD_DEVCMDSTAT_DSUS_SHIFT (17U)
-#define USBHSD_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_MASK)
-#define USBHSD_DEVCMDSTAT_LPM_SUS_MASK (0x80000U)
-#define USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT (19U)
-#define USBHSD_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUS_MASK)
-#define USBHSD_DEVCMDSTAT_LPM_REWP_MASK (0x100000U)
-#define USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT (20U)
-#define USBHSD_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_REWP_MASK)
-#define USBHSD_DEVCMDSTAT_Speed_MASK (0xC00000U)
-#define USBHSD_DEVCMDSTAT_Speed_SHIFT (22U)
-#define USBHSD_DEVCMDSTAT_Speed(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_Speed_SHIFT)) & USBHSD_DEVCMDSTAT_Speed_MASK)
-#define USBHSD_DEVCMDSTAT_DCON_C_MASK (0x1000000U)
-#define USBHSD_DEVCMDSTAT_DCON_C_SHIFT (24U)
-#define USBHSD_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_C_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_C_MASK)
-#define USBHSD_DEVCMDSTAT_DSUS_C_MASK (0x2000000U)
-#define USBHSD_DEVCMDSTAT_DSUS_C_SHIFT (25U)
-#define USBHSD_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_C_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_C_MASK)
-#define USBHSD_DEVCMDSTAT_DRES_C_MASK (0x4000000U)
-#define USBHSD_DEVCMDSTAT_DRES_C_SHIFT (26U)
-#define USBHSD_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DRES_C_SHIFT)) & USBHSD_DEVCMDSTAT_DRES_C_MASK)
-#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK (0x10000000U)
-#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT (28U)
-#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT)) & USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK)
-#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK (0xE0000000U)
-#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT (29U)
-#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT)) & USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK)
-
-/*! @name INFO - USB Info register */
-#define USBHSD_INFO_FRAME_NR_MASK (0x7FFU)
-#define USBHSD_INFO_FRAME_NR_SHIFT (0U)
-#define USBHSD_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_FRAME_NR_SHIFT)) & USBHSD_INFO_FRAME_NR_MASK)
-#define USBHSD_INFO_ERR_CODE_MASK (0x7800U)
-#define USBHSD_INFO_ERR_CODE_SHIFT (11U)
-#define USBHSD_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_ERR_CODE_SHIFT)) & USBHSD_INFO_ERR_CODE_MASK)
-#define USBHSD_INFO_Minrev_MASK (0xFF0000U)
-#define USBHSD_INFO_Minrev_SHIFT (16U)
-#define USBHSD_INFO_Minrev(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_Minrev_SHIFT)) & USBHSD_INFO_Minrev_MASK)
-#define USBHSD_INFO_Majrev_MASK (0xFF000000U)
-#define USBHSD_INFO_Majrev_SHIFT (24U)
-#define USBHSD_INFO_Majrev(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_Majrev_SHIFT)) & USBHSD_INFO_Majrev_MASK)
-
-/*! @name EPLISTSTART - USB EP Command/Status List start address */
-#define USBHSD_EPLISTSTART_EP_LIST_PRG_MASK (0xFFF00U)
-#define USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT (8U)
-#define USBHSD_EPLISTSTART_EP_LIST_PRG(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_PRG_MASK)
-#define USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK (0xFFF00000U)
-#define USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT (20U)
-#define USBHSD_EPLISTSTART_EP_LIST_FIXED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK)
-
-/*! @name DATABUFSTART - USB Data buffer start address */
-#define USBHSD_DATABUFSTART_DA_BUF_MASK (0xFFFFFFFFU)
-#define USBHSD_DATABUFSTART_DA_BUF_SHIFT (0U)
-#define USBHSD_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DATABUFSTART_DA_BUF_SHIFT)) & USBHSD_DATABUFSTART_DA_BUF_MASK)
-
-/*! @name LPM - USB Link Power Management register */
-#define USBHSD_LPM_HIRD_HW_MASK (0xFU)
-#define USBHSD_LPM_HIRD_HW_SHIFT (0U)
-#define USBHSD_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_HW_SHIFT)) & USBHSD_LPM_HIRD_HW_MASK)
-#define USBHSD_LPM_HIRD_SW_MASK (0xF0U)
-#define USBHSD_LPM_HIRD_SW_SHIFT (4U)
-#define USBHSD_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_SW_SHIFT)) & USBHSD_LPM_HIRD_SW_MASK)
-#define USBHSD_LPM_DATA_PENDING_MASK (0x100U)
-#define USBHSD_LPM_DATA_PENDING_SHIFT (8U)
-#define USBHSD_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_DATA_PENDING_SHIFT)) & USBHSD_LPM_DATA_PENDING_MASK)
-
-/*! @name EPSKIP - USB Endpoint skip */
-#define USBHSD_EPSKIP_SKIP_MASK (0xFFFU)
-#define USBHSD_EPSKIP_SKIP_SHIFT (0U)
-#define USBHSD_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPSKIP_SKIP_SHIFT)) & USBHSD_EPSKIP_SKIP_MASK)
-
-/*! @name EPINUSE - USB Endpoint Buffer in use */
-#define USBHSD_EPINUSE_BUF_MASK (0xFFCU)
-#define USBHSD_EPINUSE_BUF_SHIFT (2U)
-#define USBHSD_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPINUSE_BUF_SHIFT)) & USBHSD_EPINUSE_BUF_MASK)
-
-/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */
-#define USBHSD_EPBUFCFG_BUF_SB_MASK (0xFFCU)
-#define USBHSD_EPBUFCFG_BUF_SB_SHIFT (2U)
-#define USBHSD_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPBUFCFG_BUF_SB_SHIFT)) & USBHSD_EPBUFCFG_BUF_SB_MASK)
-
-/*! @name INTSTAT - USB interrupt status register */
-#define USBHSD_INTSTAT_EP0OUT_MASK (0x1U)
-#define USBHSD_INTSTAT_EP0OUT_SHIFT (0U)
-#define USBHSD_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0OUT_SHIFT)) & USBHSD_INTSTAT_EP0OUT_MASK)
-#define USBHSD_INTSTAT_EP0IN_MASK (0x2U)
-#define USBHSD_INTSTAT_EP0IN_SHIFT (1U)
-#define USBHSD_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0IN_SHIFT)) & USBHSD_INTSTAT_EP0IN_MASK)
-#define USBHSD_INTSTAT_EP1OUT_MASK (0x4U)
-#define USBHSD_INTSTAT_EP1OUT_SHIFT (2U)
-#define USBHSD_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1OUT_SHIFT)) & USBHSD_INTSTAT_EP1OUT_MASK)
-#define USBHSD_INTSTAT_EP1IN_MASK (0x8U)
-#define USBHSD_INTSTAT_EP1IN_SHIFT (3U)
-#define USBHSD_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1IN_SHIFT)) & USBHSD_INTSTAT_EP1IN_MASK)
-#define USBHSD_INTSTAT_EP2OUT_MASK (0x10U)
-#define USBHSD_INTSTAT_EP2OUT_SHIFT (4U)
-#define USBHSD_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2OUT_SHIFT)) & USBHSD_INTSTAT_EP2OUT_MASK)
-#define USBHSD_INTSTAT_EP2IN_MASK (0x20U)
-#define USBHSD_INTSTAT_EP2IN_SHIFT (5U)
-#define USBHSD_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2IN_SHIFT)) & USBHSD_INTSTAT_EP2IN_MASK)
-#define USBHSD_INTSTAT_EP3OUT_MASK (0x40U)
-#define USBHSD_INTSTAT_EP3OUT_SHIFT (6U)
-#define USBHSD_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3OUT_SHIFT)) & USBHSD_INTSTAT_EP3OUT_MASK)
-#define USBHSD_INTSTAT_EP3IN_MASK (0x80U)
-#define USBHSD_INTSTAT_EP3IN_SHIFT (7U)
-#define USBHSD_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3IN_SHIFT)) & USBHSD_INTSTAT_EP3IN_MASK)
-#define USBHSD_INTSTAT_EP4OUT_MASK (0x100U)
-#define USBHSD_INTSTAT_EP4OUT_SHIFT (8U)
-#define USBHSD_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4OUT_SHIFT)) & USBHSD_INTSTAT_EP4OUT_MASK)
-#define USBHSD_INTSTAT_EP4IN_MASK (0x200U)
-#define USBHSD_INTSTAT_EP4IN_SHIFT (9U)
-#define USBHSD_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4IN_SHIFT)) & USBHSD_INTSTAT_EP4IN_MASK)
-#define USBHSD_INTSTAT_EP5OUT_MASK (0x400U)
-#define USBHSD_INTSTAT_EP5OUT_SHIFT (10U)
-#define USBHSD_INTSTAT_EP5OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5OUT_SHIFT)) & USBHSD_INTSTAT_EP5OUT_MASK)
-#define USBHSD_INTSTAT_EP5IN_MASK (0x800U)
-#define USBHSD_INTSTAT_EP5IN_SHIFT (11U)
-#define USBHSD_INTSTAT_EP5IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5IN_SHIFT)) & USBHSD_INTSTAT_EP5IN_MASK)
-#define USBHSD_INTSTAT_FRAME_INT_MASK (0x40000000U)
-#define USBHSD_INTSTAT_FRAME_INT_SHIFT (30U)
-#define USBHSD_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_FRAME_INT_SHIFT)) & USBHSD_INTSTAT_FRAME_INT_MASK)
-#define USBHSD_INTSTAT_DEV_INT_MASK (0x80000000U)
-#define USBHSD_INTSTAT_DEV_INT_SHIFT (31U)
-#define USBHSD_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_DEV_INT_SHIFT)) & USBHSD_INTSTAT_DEV_INT_MASK)
-
-/*! @name INTEN - USB interrupt enable register */
-#define USBHSD_INTEN_EP_INT_EN_MASK (0xFFFU)
-#define USBHSD_INTEN_EP_INT_EN_SHIFT (0U)
-#define USBHSD_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_EP_INT_EN_SHIFT)) & USBHSD_INTEN_EP_INT_EN_MASK)
-#define USBHSD_INTEN_FRAME_INT_EN_MASK (0x40000000U)
-#define USBHSD_INTEN_FRAME_INT_EN_SHIFT (30U)
-#define USBHSD_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_FRAME_INT_EN_SHIFT)) & USBHSD_INTEN_FRAME_INT_EN_MASK)
-#define USBHSD_INTEN_DEV_INT_EN_MASK (0x80000000U)
-#define USBHSD_INTEN_DEV_INT_EN_SHIFT (31U)
-#define USBHSD_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_DEV_INT_EN_SHIFT)) & USBHSD_INTEN_DEV_INT_EN_MASK)
-
-/*! @name INTSETSTAT - USB set interrupt status register */
-#define USBHSD_INTSETSTAT_EP_SET_INT_MASK (0xFFFU)
-#define USBHSD_INTSETSTAT_EP_SET_INT_SHIFT (0U)
-#define USBHSD_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_EP_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_EP_SET_INT_MASK)
-#define USBHSD_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U)
-#define USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT (30U)
-#define USBHSD_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_FRAME_SET_INT_MASK)
-#define USBHSD_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U)
-#define USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT (31U)
-#define USBHSD_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_DEV_SET_INT_MASK)
-
-/*! @name EPTOGGLE - USB Endpoint toggle register */
-#define USBHSD_EPTOGGLE_TOGGLE_MASK (0x3FFFFFFFU)
-#define USBHSD_EPTOGGLE_TOGGLE_SHIFT (0U)
-#define USBHSD_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPTOGGLE_TOGGLE_SHIFT)) & USBHSD_EPTOGGLE_TOGGLE_MASK)
-
-/*! @name ULPIDEBUG - UTMI/ULPI debug register */
-#define USBHSD_ULPIDEBUG_PHY_ADDR_MASK (0xFFU)
-#define USBHSD_ULPIDEBUG_PHY_ADDR_SHIFT (0U)
-#define USBHSD_ULPIDEBUG_PHY_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_ADDR_SHIFT)) & USBHSD_ULPIDEBUG_PHY_ADDR_MASK)
-#define USBHSD_ULPIDEBUG_PHY_WDATA_MASK (0xFF00U)
-#define USBHSD_ULPIDEBUG_PHY_WDATA_SHIFT (8U)
-#define USBHSD_ULPIDEBUG_PHY_WDATA(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_WDATA_SHIFT)) & USBHSD_ULPIDEBUG_PHY_WDATA_MASK)
-#define USBHSD_ULPIDEBUG_PHY_RDATA_MASK (0xFF0000U)
-#define USBHSD_ULPIDEBUG_PHY_RDATA_SHIFT (16U)
-#define USBHSD_ULPIDEBUG_PHY_RDATA(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_RDATA_SHIFT)) & USBHSD_ULPIDEBUG_PHY_RDATA_MASK)
-#define USBHSD_ULPIDEBUG_PHY_RW_MASK (0x1000000U)
-#define USBHSD_ULPIDEBUG_PHY_RW_SHIFT (24U)
-#define USBHSD_ULPIDEBUG_PHY_RW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_RW_SHIFT)) & USBHSD_ULPIDEBUG_PHY_RW_MASK)
-#define USBHSD_ULPIDEBUG_PHY_ACCESS_MASK (0x2000000U)
-#define USBHSD_ULPIDEBUG_PHY_ACCESS_SHIFT (25U)
-#define USBHSD_ULPIDEBUG_PHY_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_ACCESS_SHIFT)) & USBHSD_ULPIDEBUG_PHY_ACCESS_MASK)
-#define USBHSD_ULPIDEBUG_PHY_MODE_MASK (0x80000000U)
-#define USBHSD_ULPIDEBUG_PHY_MODE_SHIFT (31U)
-#define USBHSD_ULPIDEBUG_PHY_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_MODE_SHIFT)) & USBHSD_ULPIDEBUG_PHY_MODE_MASK)
-
-
-/*!
- * @}
- */ /* end of group USBHSD_Register_Masks */
-
-
-/* USBHSD - Peripheral instance base addresses */
-/** Peripheral USBHSD base address */
-#define USBHSD_BASE (0x40094000u)
-/** Peripheral USBHSD base pointer */
-#define USBHSD ((USBHSD_Type *)USBHSD_BASE)
-/** Array initializer of USBHSD peripheral base addresses */
-#define USBHSD_BASE_ADDRS { USBHSD_BASE }
-/** Array initializer of USBHSD peripheral base pointers */
-#define USBHSD_BASE_PTRS { USBHSD }
-/** Interrupt vectors for the USBHSD peripheral type */
-#define USBHSD_IRQS { USB1_IRQn }
-#define USBHSD_NEEDCLK_IRQS { USB1_NEEDCLK_IRQn }
-
-/*!
- * @}
- */ /* end of group USBHSD_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- USBHSH Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup USBHSH_Peripheral_Access_Layer USBHSH Peripheral Access Layer
- * @{
- */
-
-/** USBHSH - Register Layout Typedef */
-typedef struct {
- __I uint32_t CAPLENGTH_CHIPID; /**< This register contains the offset value towards the start of the operational register space and the version number of the IP block, offset: 0x0 */
- __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x4 */
- __I uint32_t HCCPARAMS; /**< Host Controller Capability Parameters, offset: 0x8 */
- __IO uint32_t FLADJ_FRINDEX; /**< Frame Length Adjustment, offset: 0xC */
- __IO uint32_t ATL_PTD_BASE_ADDR; /**< Memory base address where ATL PTD0 is stored, offset: 0x10 */
- __IO uint32_t ISO_PTD_BASE_ADDR; /**< Memory base address where ISO PTD0 is stored, offset: 0x14 */
- __IO uint32_t INT_PTD_BASE_ADDR; /**< Memory base address where INT PTD0 is stored, offset: 0x18 */
- __IO uint32_t DATA_PAYLOAD_BASE_ADDR; /**< Memory base address that indicates the start of the data payload buffers, offset: 0x1C */
- __IO uint32_t USBCMD; /**< USB Command register, offset: 0x20 */
- __IO uint32_t USBSTS; /**< USB Interrupt Status register, offset: 0x24 */
- __IO uint32_t USBINTR; /**< USB Interrupt Enable register, offset: 0x28 */
- __IO uint32_t PORTSC1; /**< Port Status and Control register, offset: 0x2C */
- __IO uint32_t ATL_PTD_DONE_MAP; /**< Done map for each ATL PTD, offset: 0x30 */
- __IO uint32_t ATL_PTD_SKIP_MAP; /**< Skip map for each ATL PTD, offset: 0x34 */
- __IO uint32_t ISO_PTD_DONE_MAP; /**< Done map for each ISO PTD, offset: 0x38 */
- __IO uint32_t ISO_PTD_SKIP_MAP; /**< Skip map for each ISO PTD, offset: 0x3C */
- __IO uint32_t INT_PTD_DONE_MAP; /**< Done map for each INT PTD, offset: 0x40 */
- __IO uint32_t INT_PTD_SKIP_MAP; /**< Skip map for each INT PTD, offset: 0x44 */
- __IO uint32_t LAST_PTD_INUSE; /**< Marks the last PTD in the list for ISO, INT and ATL, offset: 0x48 */
- __IO uint32_t UTMIPLUS_ULPI_DEBUG; /**< Register to read/write registers in the attached USB PHY, offset: 0x4C */
- __IO uint32_t PORTMODE; /**< Controls the port if it is attached to the host block or the device block, offset: 0x50 */
-} USBHSH_Type;
-
-/* ----------------------------------------------------------------------------
- -- USBHSH Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup USBHSH_Register_Masks USBHSH Register Masks
- * @{
- */
-
-/*! @name CAPLENGTH_CHIPID - This register contains the offset value towards the start of the operational register space and the version number of the IP block */
-#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK (0xFFU)
-#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT (0U)
-#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK)
-#define USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK (0xFFFF0000U)
-#define USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT (16U)
-#define USBHSH_CAPLENGTH_CHIPID_CHIPID(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK)
-
-/*! @name HCSPARAMS - Host Controller Structural Parameters */
-#define USBHSH_HCSPARAMS_N_PORTS_MASK (0xFU)
-#define USBHSH_HCSPARAMS_N_PORTS_SHIFT (0U)
-#define USBHSH_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_N_PORTS_SHIFT)) & USBHSH_HCSPARAMS_N_PORTS_MASK)
-#define USBHSH_HCSPARAMS_PPC_MASK (0x10U)
-#define USBHSH_HCSPARAMS_PPC_SHIFT (4U)
-#define USBHSH_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_PPC_SHIFT)) & USBHSH_HCSPARAMS_PPC_MASK)
-#define USBHSH_HCSPARAMS_P_INDICATOR_MASK (0x10000U)
-#define USBHSH_HCSPARAMS_P_INDICATOR_SHIFT (16U)
-#define USBHSH_HCSPARAMS_P_INDICATOR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_P_INDICATOR_SHIFT)) & USBHSH_HCSPARAMS_P_INDICATOR_MASK)
-
-/*! @name HCCPARAMS - Host Controller Capability Parameters */
-#define USBHSH_HCCPARAMS_LPMC_MASK (0x20000U)
-#define USBHSH_HCCPARAMS_LPMC_SHIFT (17U)
-#define USBHSH_HCCPARAMS_LPMC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCCPARAMS_LPMC_SHIFT)) & USBHSH_HCCPARAMS_LPMC_MASK)
-
-/*! @name FLADJ_FRINDEX - Frame Length Adjustment */
-#define USBHSH_FLADJ_FRINDEX_FLADJ_MASK (0x3FU)
-#define USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT (0U)
-#define USBHSH_FLADJ_FRINDEX_FLADJ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT)) & USBHSH_FLADJ_FRINDEX_FLADJ_MASK)
-#define USBHSH_FLADJ_FRINDEX_FRINDEX_MASK (0x3FFF0000U)
-#define USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT (16U)
-#define USBHSH_FLADJ_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT)) & USBHSH_FLADJ_FRINDEX_FRINDEX_MASK)
-
-/*! @name ATL_PTD_BASE_ADDR - Memory base address where ATL PTD0 is stored */
-#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_MASK (0x1F0U)
-#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_SHIFT (4U)
-#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_SHIFT)) & USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_MASK)
-#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_MASK (0xFFFFFE00U)
-#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_SHIFT (9U)
-#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_SHIFT)) & USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_MASK)
-
-/*! @name ISO_PTD_BASE_ADDR - Memory base address where ISO PTD0 is stored */
-#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_MASK (0x3E0U)
-#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_SHIFT (5U)
-#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_SHIFT)) & USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_MASK)
-#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_MASK (0xFFFFFC00U)
-#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_SHIFT (10U)
-#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_SHIFT)) & USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_MASK)
-
-/*! @name INT_PTD_BASE_ADDR - Memory base address where INT PTD0 is stored */
-#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_MASK (0x3E0U)
-#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_SHIFT (5U)
-#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_SHIFT)) & USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_MASK)
-#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE_MASK (0xFFFFFC00U)
-#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE_SHIFT (10U)
-#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_BASE_ADDR_INT_BASE_SHIFT)) & USBHSH_INT_PTD_BASE_ADDR_INT_BASE_MASK)
-
-/*! @name DATA_PAYLOAD_BASE_ADDR - Memory base address that indicates the start of the data payload buffers */
-#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_MASK (0xFFFF0000U)
-#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_SHIFT (16U)
-#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_SHIFT)) & USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_MASK)
-
-/*! @name USBCMD - USB Command register */
-#define USBHSH_USBCMD_RS_MASK (0x1U)
-#define USBHSH_USBCMD_RS_SHIFT (0U)
-#define USBHSH_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_RS_SHIFT)) & USBHSH_USBCMD_RS_MASK)
-#define USBHSH_USBCMD_HCRESET_MASK (0x2U)
-#define USBHSH_USBCMD_HCRESET_SHIFT (1U)
-#define USBHSH_USBCMD_HCRESET(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HCRESET_SHIFT)) & USBHSH_USBCMD_HCRESET_MASK)
-#define USBHSH_USBCMD_FLS_MASK (0xCU)
-#define USBHSH_USBCMD_FLS_SHIFT (2U)
-#define USBHSH_USBCMD_FLS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_FLS_SHIFT)) & USBHSH_USBCMD_FLS_MASK)
-#define USBHSH_USBCMD_LHCR_MASK (0x80U)
-#define USBHSH_USBCMD_LHCR_SHIFT (7U)
-#define USBHSH_USBCMD_LHCR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_LHCR_SHIFT)) & USBHSH_USBCMD_LHCR_MASK)
-#define USBHSH_USBCMD_ATL_EN_MASK (0x100U)
-#define USBHSH_USBCMD_ATL_EN_SHIFT (8U)
-#define USBHSH_USBCMD_ATL_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ATL_EN_SHIFT)) & USBHSH_USBCMD_ATL_EN_MASK)
-#define USBHSH_USBCMD_ISO_EN_MASK (0x200U)
-#define USBHSH_USBCMD_ISO_EN_SHIFT (9U)
-#define USBHSH_USBCMD_ISO_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ISO_EN_SHIFT)) & USBHSH_USBCMD_ISO_EN_MASK)
-#define USBHSH_USBCMD_INT_EN_MASK (0x400U)
-#define USBHSH_USBCMD_INT_EN_SHIFT (10U)
-#define USBHSH_USBCMD_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_INT_EN_SHIFT)) & USBHSH_USBCMD_INT_EN_MASK)
-#define USBHSH_USBCMD_HIRD_MASK (0xF000000U)
-#define USBHSH_USBCMD_HIRD_SHIFT (24U)
-#define USBHSH_USBCMD_HIRD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HIRD_SHIFT)) & USBHSH_USBCMD_HIRD_MASK)
-#define USBHSH_USBCMD_LPM_RWU_MASK (0x10000000U)
-#define USBHSH_USBCMD_LPM_RWU_SHIFT (28U)
-#define USBHSH_USBCMD_LPM_RWU(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_LPM_RWU_SHIFT)) & USBHSH_USBCMD_LPM_RWU_MASK)
-
-/*! @name USBSTS - USB Interrupt Status register */
-#define USBHSH_USBSTS_PCD_MASK (0x4U)
-#define USBHSH_USBSTS_PCD_SHIFT (2U)
-#define USBHSH_USBSTS_PCD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_PCD_SHIFT)) & USBHSH_USBSTS_PCD_MASK)
-#define USBHSH_USBSTS_FLR_MASK (0x8U)
-#define USBHSH_USBSTS_FLR_SHIFT (3U)
-#define USBHSH_USBSTS_FLR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_FLR_SHIFT)) & USBHSH_USBSTS_FLR_MASK)
-#define USBHSH_USBSTS_ATL_IRQ_MASK (0x10000U)
-#define USBHSH_USBSTS_ATL_IRQ_SHIFT (16U)
-#define USBHSH_USBSTS_ATL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ATL_IRQ_SHIFT)) & USBHSH_USBSTS_ATL_IRQ_MASK)
-#define USBHSH_USBSTS_ISO_IRQ_MASK (0x20000U)
-#define USBHSH_USBSTS_ISO_IRQ_SHIFT (17U)
-#define USBHSH_USBSTS_ISO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ISO_IRQ_SHIFT)) & USBHSH_USBSTS_ISO_IRQ_MASK)
-#define USBHSH_USBSTS_INT_IRQ_MASK (0x40000U)
-#define USBHSH_USBSTS_INT_IRQ_SHIFT (18U)
-#define USBHSH_USBSTS_INT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_INT_IRQ_SHIFT)) & USBHSH_USBSTS_INT_IRQ_MASK)
-#define USBHSH_USBSTS_SOF_IRQ_MASK (0x80000U)
-#define USBHSH_USBSTS_SOF_IRQ_SHIFT (19U)
-#define USBHSH_USBSTS_SOF_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_SOF_IRQ_SHIFT)) & USBHSH_USBSTS_SOF_IRQ_MASK)
-
-/*! @name USBINTR - USB Interrupt Enable register */
-#define USBHSH_USBINTR_PCDE_MASK (0x4U)
-#define USBHSH_USBINTR_PCDE_SHIFT (2U)
-#define USBHSH_USBINTR_PCDE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_PCDE_SHIFT)) & USBHSH_USBINTR_PCDE_MASK)
-#define USBHSH_USBINTR_FLRE_MASK (0x8U)
-#define USBHSH_USBINTR_FLRE_SHIFT (3U)
-#define USBHSH_USBINTR_FLRE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_FLRE_SHIFT)) & USBHSH_USBINTR_FLRE_MASK)
-#define USBHSH_USBINTR_ATL_IRQ_E_MASK (0x10000U)
-#define USBHSH_USBINTR_ATL_IRQ_E_SHIFT (16U)
-#define USBHSH_USBINTR_ATL_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ATL_IRQ_E_SHIFT)) & USBHSH_USBINTR_ATL_IRQ_E_MASK)
-#define USBHSH_USBINTR_ISO_IRQ_E_MASK (0x20000U)
-#define USBHSH_USBINTR_ISO_IRQ_E_SHIFT (17U)
-#define USBHSH_USBINTR_ISO_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ISO_IRQ_E_SHIFT)) & USBHSH_USBINTR_ISO_IRQ_E_MASK)
-#define USBHSH_USBINTR_INT_IRQ_E_MASK (0x40000U)
-#define USBHSH_USBINTR_INT_IRQ_E_SHIFT (18U)
-#define USBHSH_USBINTR_INT_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_INT_IRQ_E_SHIFT)) & USBHSH_USBINTR_INT_IRQ_E_MASK)
-#define USBHSH_USBINTR_SOF_E_MASK (0x80000U)
-#define USBHSH_USBINTR_SOF_E_SHIFT (19U)
-#define USBHSH_USBINTR_SOF_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_SOF_E_SHIFT)) & USBHSH_USBINTR_SOF_E_MASK)
-
-/*! @name PORTSC1 - Port Status and Control register */
-#define USBHSH_PORTSC1_CCS_MASK (0x1U)
-#define USBHSH_PORTSC1_CCS_SHIFT (0U)
-#define USBHSH_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CCS_SHIFT)) & USBHSH_PORTSC1_CCS_MASK)
-#define USBHSH_PORTSC1_CSC_MASK (0x2U)
-#define USBHSH_PORTSC1_CSC_SHIFT (1U)
-#define USBHSH_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CSC_SHIFT)) & USBHSH_PORTSC1_CSC_MASK)
-#define USBHSH_PORTSC1_PED_MASK (0x4U)
-#define USBHSH_PORTSC1_PED_SHIFT (2U)
-#define USBHSH_PORTSC1_PED(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PED_SHIFT)) & USBHSH_PORTSC1_PED_MASK)
-#define USBHSH_PORTSC1_PEDC_MASK (0x8U)
-#define USBHSH_PORTSC1_PEDC_SHIFT (3U)
-#define USBHSH_PORTSC1_PEDC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PEDC_SHIFT)) & USBHSH_PORTSC1_PEDC_MASK)
-#define USBHSH_PORTSC1_OCA_MASK (0x10U)
-#define USBHSH_PORTSC1_OCA_SHIFT (4U)
-#define USBHSH_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCA_SHIFT)) & USBHSH_PORTSC1_OCA_MASK)
-#define USBHSH_PORTSC1_OCC_MASK (0x20U)
-#define USBHSH_PORTSC1_OCC_SHIFT (5U)
-#define USBHSH_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCC_SHIFT)) & USBHSH_PORTSC1_OCC_MASK)
-#define USBHSH_PORTSC1_FPR_MASK (0x40U)
-#define USBHSH_PORTSC1_FPR_SHIFT (6U)
-#define USBHSH_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_FPR_SHIFT)) & USBHSH_PORTSC1_FPR_MASK)
-#define USBHSH_PORTSC1_SUSP_MASK (0x80U)
-#define USBHSH_PORTSC1_SUSP_SHIFT (7U)
-#define USBHSH_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUSP_SHIFT)) & USBHSH_PORTSC1_SUSP_MASK)
-#define USBHSH_PORTSC1_PR_MASK (0x100U)
-#define USBHSH_PORTSC1_PR_SHIFT (8U)
-#define USBHSH_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PR_SHIFT)) & USBHSH_PORTSC1_PR_MASK)
-#define USBHSH_PORTSC1_SUS_L1_MASK (0x200U)
-#define USBHSH_PORTSC1_SUS_L1_SHIFT (9U)
-#define USBHSH_PORTSC1_SUS_L1(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUS_L1_SHIFT)) & USBHSH_PORTSC1_SUS_L1_MASK)
-#define USBHSH_PORTSC1_LS_MASK (0xC00U)
-#define USBHSH_PORTSC1_LS_SHIFT (10U)
-#define USBHSH_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_LS_SHIFT)) & USBHSH_PORTSC1_LS_MASK)
-#define USBHSH_PORTSC1_PP_MASK (0x1000U)
-#define USBHSH_PORTSC1_PP_SHIFT (12U)
-#define USBHSH_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PP_SHIFT)) & USBHSH_PORTSC1_PP_MASK)
-#define USBHSH_PORTSC1_PIC_MASK (0xC000U)
-#define USBHSH_PORTSC1_PIC_SHIFT (14U)
-#define USBHSH_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PIC_SHIFT)) & USBHSH_PORTSC1_PIC_MASK)
-#define USBHSH_PORTSC1_PTC_MASK (0xF0000U)
-#define USBHSH_PORTSC1_PTC_SHIFT (16U)
-#define USBHSH_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PTC_SHIFT)) & USBHSH_PORTSC1_PTC_MASK)
-#define USBHSH_PORTSC1_PSPD_MASK (0x300000U)
-#define USBHSH_PORTSC1_PSPD_SHIFT (20U)
-#define USBHSH_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PSPD_SHIFT)) & USBHSH_PORTSC1_PSPD_MASK)
-#define USBHSH_PORTSC1_WOO_MASK (0x400000U)
-#define USBHSH_PORTSC1_WOO_SHIFT (22U)
-#define USBHSH_PORTSC1_WOO(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_WOO_SHIFT)) & USBHSH_PORTSC1_WOO_MASK)
-#define USBHSH_PORTSC1_SUS_STAT_MASK (0x1800000U)
-#define USBHSH_PORTSC1_SUS_STAT_SHIFT (23U)
-#define USBHSH_PORTSC1_SUS_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUS_STAT_SHIFT)) & USBHSH_PORTSC1_SUS_STAT_MASK)
-#define USBHSH_PORTSC1_DEV_ADD_MASK (0xFE000000U)
-#define USBHSH_PORTSC1_DEV_ADD_SHIFT (25U)
-#define USBHSH_PORTSC1_DEV_ADD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_DEV_ADD_SHIFT)) & USBHSH_PORTSC1_DEV_ADD_MASK)
-
-/*! @name ATL_PTD_DONE_MAP - Done map for each ATL PTD */
-#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_MASK (0xFFFFFFFFU)
-#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_SHIFT (0U)
-#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_SHIFT)) & USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_MASK)
-
-/*! @name ATL_PTD_SKIP_MAP - Skip map for each ATL PTD */
-#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_MASK (0xFFFFFFFFU)
-#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_SHIFT (0U)
-#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_SHIFT)) & USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_MASK)
-
-/*! @name ISO_PTD_DONE_MAP - Done map for each ISO PTD */
-#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_MASK (0xFFFFFFFFU)
-#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_SHIFT (0U)
-#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_SHIFT)) & USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_MASK)
-
-/*! @name ISO_PTD_SKIP_MAP - Skip map for each ISO PTD */
-#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_MASK (0xFFFFFFFFU)
-#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_SHIFT (0U)
-#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_SHIFT)) & USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_MASK)
-
-/*! @name INT_PTD_DONE_MAP - Done map for each INT PTD */
-#define USBHSH_INT_PTD_DONE_MAP_INT_DONE_MASK (0xFFFFFFFFU)
-#define USBHSH_INT_PTD_DONE_MAP_INT_DONE_SHIFT (0U)
-#define USBHSH_INT_PTD_DONE_MAP_INT_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_DONE_MAP_INT_DONE_SHIFT)) & USBHSH_INT_PTD_DONE_MAP_INT_DONE_MASK)
-
-/*! @name INT_PTD_SKIP_MAP - Skip map for each INT PTD */
-#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_MASK (0xFFFFFFFFU)
-#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_SHIFT (0U)
-#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_SHIFT)) & USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_MASK)
-
-/*! @name LAST_PTD_INUSE - Marks the last PTD in the list for ISO, INT and ATL */
-#define USBHSH_LAST_PTD_INUSE_ATL_LAST_MASK (0x1FU)
-#define USBHSH_LAST_PTD_INUSE_ATL_LAST_SHIFT (0U)
-#define USBHSH_LAST_PTD_INUSE_ATL_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LAST_PTD_INUSE_ATL_LAST_SHIFT)) & USBHSH_LAST_PTD_INUSE_ATL_LAST_MASK)
-#define USBHSH_LAST_PTD_INUSE_ISO_LAST_MASK (0x1F00U)
-#define USBHSH_LAST_PTD_INUSE_ISO_LAST_SHIFT (8U)
-#define USBHSH_LAST_PTD_INUSE_ISO_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LAST_PTD_INUSE_ISO_LAST_SHIFT)) & USBHSH_LAST_PTD_INUSE_ISO_LAST_MASK)
-#define USBHSH_LAST_PTD_INUSE_INT_LAST_MASK (0x1F0000U)
-#define USBHSH_LAST_PTD_INUSE_INT_LAST_SHIFT (16U)
-#define USBHSH_LAST_PTD_INUSE_INT_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LAST_PTD_INUSE_INT_LAST_SHIFT)) & USBHSH_LAST_PTD_INUSE_INT_LAST_MASK)
-
-/*! @name UTMIPLUS_ULPI_DEBUG - Register to read/write registers in the attached USB PHY */
-#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_MASK (0xFFU)
-#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_SHIFT (0U)
-#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_MASK)
-#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_MASK (0xFF00U)
-#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_SHIFT (8U)
-#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_MASK)
-#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_MASK (0xFF0000U)
-#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_SHIFT (16U)
-#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_MASK)
-#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_MASK (0x1000000U)
-#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_SHIFT (24U)
-#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_MASK)
-#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_MASK (0x2000000U)
-#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_SHIFT (25U)
-#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_MASK)
-#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_MASK (0x80000000U)
-#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_SHIFT (31U)
-#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_MASK)
-
-/*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */
-#define USBHSH_PORTMODE_ID0_MASK (0x1U)
-#define USBHSH_PORTMODE_ID0_SHIFT (0U)
-#define USBHSH_PORTMODE_ID0(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_ID0_SHIFT)) & USBHSH_PORTMODE_ID0_MASK)
-#define USBHSH_PORTMODE_ID0_EN_MASK (0x100U)
-#define USBHSH_PORTMODE_ID0_EN_SHIFT (8U)
-#define USBHSH_PORTMODE_ID0_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_ID0_EN_SHIFT)) & USBHSH_PORTMODE_ID0_EN_MASK)
-#define USBHSH_PORTMODE_DEV_ENABLE_MASK (0x10000U)
-#define USBHSH_PORTMODE_DEV_ENABLE_SHIFT (16U)
-#define USBHSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBHSH_PORTMODE_DEV_ENABLE_MASK)
-#define USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK (0x40000U)
-#define USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT (18U)
-#define USBHSH_PORTMODE_SW_CTRL_PDCOM(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK)
-#define USBHSH_PORTMODE_SW_PDCOM_MASK (0x80000U)
-#define USBHSH_PORTMODE_SW_PDCOM_SHIFT (19U)
-#define USBHSH_PORTMODE_SW_PDCOM(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_PDCOM_MASK)
-
-
-/*!
- * @}
- */ /* end of group USBHSH_Register_Masks */
-
-
-/* USBHSH - Peripheral instance base addresses */
-/** Peripheral USBHSH base address */
-#define USBHSH_BASE (0x400A3000u)
-/** Peripheral USBHSH base pointer */
-#define USBHSH ((USBHSH_Type *)USBHSH_BASE)
-/** Array initializer of USBHSH peripheral base addresses */
-#define USBHSH_BASE_ADDRS { USBHSH_BASE }
-/** Array initializer of USBHSH peripheral base pointers */
-#define USBHSH_BASE_PTRS { USBHSH }
-/** Interrupt vectors for the USBHSH peripheral type */
-#define USBHSH_IRQS { USB1_IRQn }
-#define USBHSH_NEEDCLK_IRQS { USB1_NEEDCLK_IRQn }
-
-/*!
- * @}
- */ /* end of group USBHSH_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- UTICK Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer
- * @{
- */
-
-/** UTICK - Register Layout Typedef */
-typedef struct {
- __IO uint32_t CTRL; /**< Control register., offset: 0x0 */
- __IO uint32_t STAT; /**< Status register., offset: 0x4 */
- __IO uint32_t CFG; /**< Capture configuration register., offset: 0x8 */
- __O uint32_t CAPCLR; /**< Capture clear register., offset: 0xC */
- __I uint32_t CAP[4]; /**< Capture register ., array offset: 0x10, array step: 0x4 */
-} UTICK_Type;
-
-/* ----------------------------------------------------------------------------
- -- UTICK Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup UTICK_Register_Masks UTICK Register Masks
- * @{
- */
-
-/*! @name CTRL - Control register. */
-#define UTICK_CTRL_DELAYVAL_MASK (0x7FFFFFFFU)
-#define UTICK_CTRL_DELAYVAL_SHIFT (0U)
-#define UTICK_CTRL_DELAYVAL(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK)
-#define UTICK_CTRL_REPEAT_MASK (0x80000000U)
-#define UTICK_CTRL_REPEAT_SHIFT (31U)
-#define UTICK_CTRL_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK)
-
-/*! @name STAT - Status register. */
-#define UTICK_STAT_INTR_MASK (0x1U)
-#define UTICK_STAT_INTR_SHIFT (0U)
-#define UTICK_STAT_INTR(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK)
-#define UTICK_STAT_ACTIVE_MASK (0x2U)
-#define UTICK_STAT_ACTIVE_SHIFT (1U)
-#define UTICK_STAT_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK)
-
-/*! @name CFG - Capture configuration register. */
-#define UTICK_CFG_CAPEN0_MASK (0x1U)
-#define UTICK_CFG_CAPEN0_SHIFT (0U)
-#define UTICK_CFG_CAPEN0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK)
-#define UTICK_CFG_CAPEN1_MASK (0x2U)
-#define UTICK_CFG_CAPEN1_SHIFT (1U)
-#define UTICK_CFG_CAPEN1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK)
-#define UTICK_CFG_CAPEN2_MASK (0x4U)
-#define UTICK_CFG_CAPEN2_SHIFT (2U)
-#define UTICK_CFG_CAPEN2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK)
-#define UTICK_CFG_CAPEN3_MASK (0x8U)
-#define UTICK_CFG_CAPEN3_SHIFT (3U)
-#define UTICK_CFG_CAPEN3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK)
-#define UTICK_CFG_CAPPOL0_MASK (0x100U)
-#define UTICK_CFG_CAPPOL0_SHIFT (8U)
-#define UTICK_CFG_CAPPOL0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK)
-#define UTICK_CFG_CAPPOL1_MASK (0x200U)
-#define UTICK_CFG_CAPPOL1_SHIFT (9U)
-#define UTICK_CFG_CAPPOL1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK)
-#define UTICK_CFG_CAPPOL2_MASK (0x400U)
-#define UTICK_CFG_CAPPOL2_SHIFT (10U)
-#define UTICK_CFG_CAPPOL2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK)
-#define UTICK_CFG_CAPPOL3_MASK (0x800U)
-#define UTICK_CFG_CAPPOL3_SHIFT (11U)
-#define UTICK_CFG_CAPPOL3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK)
-
-/*! @name CAPCLR - Capture clear register. */
-#define UTICK_CAPCLR_CAPCLR0_MASK (0x1U)
-#define UTICK_CAPCLR_CAPCLR0_SHIFT (0U)
-#define UTICK_CAPCLR_CAPCLR0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK)
-#define UTICK_CAPCLR_CAPCLR1_MASK (0x2U)
-#define UTICK_CAPCLR_CAPCLR1_SHIFT (1U)
-#define UTICK_CAPCLR_CAPCLR1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK)
-#define UTICK_CAPCLR_CAPCLR2_MASK (0x4U)
-#define UTICK_CAPCLR_CAPCLR2_SHIFT (2U)
-#define UTICK_CAPCLR_CAPCLR2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK)
-#define UTICK_CAPCLR_CAPCLR3_MASK (0x8U)
-#define UTICK_CAPCLR_CAPCLR3_SHIFT (3U)
-#define UTICK_CAPCLR_CAPCLR3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK)
-
-/*! @name CAP - Capture register . */
-#define UTICK_CAP_CAP_VALUE_MASK (0x7FFFFFFFU)
-#define UTICK_CAP_CAP_VALUE_SHIFT (0U)
-#define UTICK_CAP_CAP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK)
-#define UTICK_CAP_VALID_MASK (0x80000000U)
-#define UTICK_CAP_VALID_SHIFT (31U)
-#define UTICK_CAP_VALID(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK)
-
-/* The count of UTICK_CAP */
-#define UTICK_CAP_COUNT (4U)
-
-
-/*!
- * @}
- */ /* end of group UTICK_Register_Masks */
-
-
-/* UTICK - Peripheral instance base addresses */
-/** Peripheral UTICK0 base address */
-#define UTICK0_BASE (0x4000E000u)
-/** Peripheral UTICK0 base pointer */
-#define UTICK0 ((UTICK_Type *)UTICK0_BASE)
-/** Array initializer of UTICK peripheral base addresses */
-#define UTICK_BASE_ADDRS { UTICK0_BASE }
-/** Array initializer of UTICK peripheral base pointers */
-#define UTICK_BASE_PTRS { UTICK0 }
-/** Interrupt vectors for the UTICK peripheral type */
-#define UTICK_IRQS { UTICK0_IRQn }
-
-/*!
- * @}
- */ /* end of group UTICK_Peripheral_Access_Layer */
-
-
-/* ----------------------------------------------------------------------------
- -- WWDT Peripheral Access Layer
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer
- * @{
- */
-
-/** WWDT - Register Layout Typedef */
-typedef struct {
- __IO uint32_t MOD; /**< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer., offset: 0x0 */
- __IO uint32_t TC; /**< Watchdog timer constant register. This 24-bit register determines the time-out value., offset: 0x4 */
- __O uint32_t FEED; /**< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC., offset: 0x8 */
- __I uint32_t TV; /**< Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer., offset: 0xC */
- uint8_t RESERVED_0[4];
- __IO uint32_t WARNINT; /**< Watchdog Warning Interrupt compare value., offset: 0x14 */
- __IO uint32_t WINDOW; /**< Watchdog Window compare value., offset: 0x18 */
-} WWDT_Type;
-
-/* ----------------------------------------------------------------------------
- -- WWDT Register Masks
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup WWDT_Register_Masks WWDT Register Masks
- * @{
- */
-
-/*! @name MOD - Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
-#define WWDT_MOD_WDEN_MASK (0x1U)
-#define WWDT_MOD_WDEN_SHIFT (0U)
-#define WWDT_MOD_WDEN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK)
-#define WWDT_MOD_WDRESET_MASK (0x2U)
-#define WWDT_MOD_WDRESET_SHIFT (1U)
-#define WWDT_MOD_WDRESET(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK)
-#define WWDT_MOD_WDTOF_MASK (0x4U)
-#define WWDT_MOD_WDTOF_SHIFT (2U)
-#define WWDT_MOD_WDTOF(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK)
-#define WWDT_MOD_WDINT_MASK (0x8U)
-#define WWDT_MOD_WDINT_SHIFT (3U)
-#define WWDT_MOD_WDINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK)
-#define WWDT_MOD_WDPROTECT_MASK (0x10U)
-#define WWDT_MOD_WDPROTECT_SHIFT (4U)
-#define WWDT_MOD_WDPROTECT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK)
-#define WWDT_MOD_LOCK_MASK (0x20U)
-#define WWDT_MOD_LOCK_SHIFT (5U)
-#define WWDT_MOD_LOCK(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_LOCK_SHIFT)) & WWDT_MOD_LOCK_MASK)
-
-/*! @name TC - Watchdog timer constant register. This 24-bit register determines the time-out value. */
-#define WWDT_TC_COUNT_MASK (0xFFFFFFU)
-#define WWDT_TC_COUNT_SHIFT (0U)
-#define WWDT_TC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK)
-
-/*! @name FEED - Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. */
-#define WWDT_FEED_FEED_MASK (0xFFU)
-#define WWDT_FEED_FEED_SHIFT (0U)
-#define WWDT_FEED_FEED(x) (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK)
-
-/*! @name TV - Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */
-#define WWDT_TV_COUNT_MASK (0xFFFFFFU)
-#define WWDT_TV_COUNT_SHIFT (0U)
-#define WWDT_TV_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK)
-
-/*! @name WARNINT - Watchdog Warning Interrupt compare value. */
-#define WWDT_WARNINT_WARNINT_MASK (0x3FFU)
-#define WWDT_WARNINT_WARNINT_SHIFT (0U)
-#define WWDT_WARNINT_WARNINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK)
-
-/*! @name WINDOW - Watchdog Window compare value. */
-#define WWDT_WINDOW_WINDOW_MASK (0xFFFFFFU)
-#define WWDT_WINDOW_WINDOW_SHIFT (0U)
-#define WWDT_WINDOW_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK)
-
-
-/*!
- * @}
- */ /* end of group WWDT_Register_Masks */
-
-
-/* WWDT - Peripheral instance base addresses */
-/** Peripheral WWDT base address */
-#define WWDT_BASE (0x4000C000u)
-/** Peripheral WWDT base pointer */
-#define WWDT ((WWDT_Type *)WWDT_BASE)
-/** Array initializer of WWDT peripheral base addresses */
-#define WWDT_BASE_ADDRS { WWDT_BASE }
-/** Array initializer of WWDT peripheral base pointers */
-#define WWDT_BASE_PTRS { WWDT }
-/** Interrupt vectors for the WWDT peripheral type */
-#define WWDT_IRQS { WDT_BOD_IRQn }
-
-/*!
- * @}
- */ /* end of group WWDT_Peripheral_Access_Layer */
-
-
-/*
-** End of section using anonymous unions
-*/
-
-#if defined(__ARMCC_VERSION)
- #pragma pop
-#elif defined(__GNUC__)
- /* leave anonymous unions enabled */
-#elif defined(__IAR_SYSTEMS_ICC__)
- #pragma language=default
-#else
- #error Not supported compiler type
-#endif
-
-/*!
- * @}
- */ /* end of group Peripheral_access_layer */
-
-
-/* ----------------------------------------------------------------------------
- -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
- * @{
- */
-
-#if defined(__ARMCC_VERSION)
- #if (__ARMCC_VERSION >= 6010050)
- #pragma clang system_header
- #endif
-#elif defined(__IAR_SYSTEMS_ICC__)
- #pragma system_include
-#endif
-
-/**
- * @brief Mask and left-shift a bit field value for use in a register bit range.
- * @param field Name of the register bit field.
- * @param value Value of the bit field.
- * @return Masked and shifted value.
- */
-#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK))
-/**
- * @brief Mask and right-shift a register value to extract a bit field value.
- * @param field Name of the register bit field.
- * @param value Value of the register.
- * @return Masked and shifted bit field value.
- */
-#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT))
-
-/*!
- * @}
- */ /* end of group Bit_Field_Generic_Macros */
-
-
-/* ----------------------------------------------------------------------------
- -- SDK Compatibility
- ---------------------------------------------------------------------------- */
-
-/*!
- * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
- * @{
- */
-
-/** EMC CS base address */
-#define EMC_CS0_BASE (0x80000000u)
-#define EMC_CS1_BASE (0x90000000u)
-#define EMC_CS2_BASE (0x98000000u)
-#define EMC_CS3_BASE (0x9C000000u)
-#define EMC_DYCS0_BASE (0xA0000000u)
-#define EMC_DYCS1_BASE (0xB0000000u)
-#define EMC_DYCS2_BASE (0xC0000000u)
-#define EMC_DYCS3_BASE (0xD0000000u)
-#define EMC_CS_ADDRESS {EMC_CS0_BASE, EMC_CS1_BASE, EMC_CS2_BASE, EMC_CS3_BASE}
-#define EMC_DYCS_ADDRESS {EMC_DYCS0_BASE, EMC_DYCS1_BASE, EMC_DYCS2_BASE, EMC_DYCS3_BASE}
-
-/** OTP API */
-typedef struct {
- uint32_t (*otpInit)(void); /** Initializes OTP controller */
- uint32_t (*otpEnableBankWriteMask)(uint32_t bankMask); /** Unlock one or more OTP banks for write access */
- uint32_t (*otpDisableBankWriteMask)(uint32_t bankMask); /** Lock one or more OTP banks for write access */
- uint32_t (*otpEnableBankWriteLock)(uint32_t bankIndex, uint32_t regEnableMask, uint32_t regDisableMask,
- uint32_t lockWrite); /** Locks or unlocks write access to a register of an OTP bank and the write lock */
- uint32_t (*otpEnableBankReadLock)(uint32_t bankIndex, uint32_t regEnableMask, uint32_t regDisableMask,
- uint32_t lockWrite); /** Locks or unlocks read access to a register of an OTP bank and the write lock */
- uint32_t (*otpProgramReg)(uint32_t bankIndex, uint32_t regIndex, uint32_t value); /** Program a single register in an OTP bank */
- uint32_t RESERVED_0[5];
- uint32_t (*rngRead)(void); /** Returns 32-bit number from hardware random number generator */
- uint32_t (*otpGetDriverVersion)(void); /** Returns the version of the OTP driver in ROM */
-} OTP_API_Type;
-
-/** ROM API */
-typedef struct {
- __I uint32_t usbdApiBase; /** USB API Base */
- uint32_t RESERVED_0[13];
- __I OTP_API_Type *otpApiBase; /** OTP API Base */
- __I uint32_t aesApiBase; /** AES API Base */
- __I uint32_t secureApiBase; /** Secure API Base */
-} ROM_API_Type;
-
-/** ROM API base address */
-#define ROM_API_BASE (0x03000200u)
-/** ROM API base pointer */
-#define ROM_API (*(ROM_API_Type**) ROM_API_BASE)
-/** OTP API base pointer */
-#define OTP_API (ROM_API->otpApiBase)
-
-/*!
- * @}
- */ /* end of group SDK_Compatibility_Symbols */
-
-
-#endif /* _LPC54618_H_ */
-
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/LPC54618_features.h Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,231 +0,0 @@ -/* -** ################################################################### -** Version: rev. 1.1, 2016-11-25 -** Build: b170112 -** -** Abstract: -** Chip specific module features. -** -** Copyright (c) 2016 Freescale Semiconductor, Inc. -** Copyright 2016 - 2017 NXP -** Redistribution and use in source and binary forms, with or without modification, -** are permitted provided that the following conditions are met: -** -** o Redistributions of source code must retain the above copyright notice, this list -** of conditions and the following disclaimer. -** -** o Redistributions in binary form must reproduce the above copyright notice, this -** list of conditions and the following disclaimer in the documentation and/or -** other materials provided with the distribution. -** -** o Neither the name of the copyright holder nor the names of its -** contributors may be used to endorse or promote products derived from this -** software without specific prior written permission. -** -** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -** -** http: www.nxp.com -** mail: support@nxp.com -** -** Revisions: -** - rev. 1.0 (2016-08-12) -** Initial version. -** - rev. 1.1 (2016-11-25) -** Update CANFD and Classic CAN register. -** Add MAC TIMERSTAMP registers. -** -** ################################################################### -*/ - -#ifndef _LPC54618_FEATURES_H_ -#define _LPC54618_FEATURES_H_ - -/* SOC module features */ - -/* @brief ADC availability on the SoC. */ -#define FSL_FEATURE_SOC_ADC_COUNT (1) -/* @brief ASYNC_SYSCON availability on the SoC. */ -#define FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT (1) -/* @brief CRC availability on the SoC. */ -#define FSL_FEATURE_SOC_CRC_COUNT (1) -/* @brief DMA availability on the SoC. */ -#define FSL_FEATURE_SOC_DMA_COUNT (1) -/* @brief DMIC availability on the SoC. */ -#define FSL_FEATURE_SOC_DMIC_COUNT (1) -/* @brief FLEXCOMM availability on the SoC. */ -#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (10) -/* @brief GINT availability on the SoC. */ -#define FSL_FEATURE_SOC_GINT_COUNT (2) -/* @brief GPIO availability on the SoC. */ -#define FSL_FEATURE_SOC_GPIO_COUNT (1) -/* @brief I2C availability on the SoC. */ -#define FSL_FEATURE_SOC_I2C_COUNT (10) -/* @brief I2S availability on the SoC. */ -#define FSL_FEATURE_SOC_I2S_COUNT (2) -/* @brief INPUTMUX availability on the SoC. */ -#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) -/* @brief IOCON availability on the SoC. */ -#define FSL_FEATURE_SOC_IOCON_COUNT (1) -/* @brief MRT availability on the SoC. */ -#define FSL_FEATURE_SOC_MRT_COUNT (1) -/* @brief PINT availability on the SoC. */ -#define FSL_FEATURE_SOC_PINT_COUNT (1) -/* @brief RTC availability on the SoC. */ -#define FSL_FEATURE_SOC_RTC_COUNT (1) -/* @brief SCT availability on the SoC. */ -#define FSL_FEATURE_SOC_SCT_COUNT (1) -/* @brief SPI availability on the SoC. */ -#define FSL_FEATURE_SOC_SPI_COUNT (10) -/* @brief SPIFI availability on the SoC. */ -#define FSL_FEATURE_SOC_SPIFI_COUNT (1) -/* @brief SYSCON availability on the SoC. */ -#define FSL_FEATURE_SOC_SYSCON_COUNT (1) -/* @brief CTIMER availability on the SoC. */ -#define FSL_FEATURE_SOC_CTIMER_COUNT (5) -/* @brief USART availability on the SoC. */ -#define FSL_FEATURE_SOC_USART_COUNT (10) -/* @brief USB availability on the SoC. */ -#define FSL_FEATURE_SOC_USB_COUNT (1) -/* @brief UTICK availability on the SoC. */ -#define FSL_FEATURE_SOC_UTICK_COUNT (1) -/* @brief WWDT availability on the SoC. */ -#define FSL_FEATURE_SOC_WWDT_COUNT (1) -/* @brief USBFSH availability on the SoC. */ -#define FSL_FEATURE_SOC_USBFSH_COUNT (1) -/* @brief USBHSD availability on the SoC. */ -#define FSL_FEATURE_SOC_USBHSD_COUNT (1) -/* @brief USBHSH availability on the SoC. */ -#define FSL_FEATURE_SOC_USBHSH_COUNT (1) -/* @brief EEPROM availability on the SoC. */ -#define FSL_FEATURE_SOC_EEPROM_COUNT (1) -/* @brief EMC availability on the SoC. */ -#define FSL_FEATURE_SOC_EMC_COUNT (1) -/* @brief ENET availability on the SoC. */ -#define FSL_FEATURE_SOC_LPC_ENET_COUNT (1) -/* @brief SDIF availability on the SoC. */ -#define FSL_FEATURE_SOC_SDIF_COUNT (1) -/* @brief SMARTCARD availability on the SoC. */ -#define FSL_FEATURE_SOC_SMARTCARD_COUNT (2) -/* @brief LCD availability on the SoC. */ -#define FSL_FEATURE_SOC_LCD_COUNT (1) -/* @brief CAN availability on the SoC. */ -#define FSL_FEATURE_SOC_LPC_CAN_COUNT (2) -/* @brief SHA availability on the SoC. */ -#define FSL_FEATURE_SOC_SHA_COUNT (0) -/* @brief AES availability on the SoC. */ -#define FSL_FEATURE_SOC_AES_COUNT (0) -/* @brief RIT availability on the SoC. */ -#define FSL_FEATURE_SOC_RIT_COUNT (1) -/* @brief FMC availability on the SoC. */ -#define FSL_FEATURE_SOC_FMC_COUNT (1) -/* @brief RNG availability on the SoC. */ -#define FSL_FEATURE_SOC_LPC_RNG_COUNT (1) - -/* CAN module features */ - -/* @brief Support CANFD or not */ -#define FSL_FEATURE_CAN_SUPPORT_CANFD (1) - -/* DMA module features */ - -/* @brief Number of channels */ -#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (30) - -/* EEPROM module features */ - -/* @brief Size of the EEPROM */ -#define FSL_FEATURE_EEPROM_SIZE (0x00004000) -/* @brief Base address of the EEPROM */ -#define FSL_FEATURE_EEPROM_BASE_ADDRESS (0x40108000) -/* @brief Page count of the EEPROM */ -#define FSL_FEATURE_EEPROM_PAGE_COUNT (128) -/* @brief Command number for eeprom program */ -#define FSL_FEATURE_EEPROM_PROGRAM_CMD (6) -/* @brief EEPROM internal clock freqency */ -#define FSL_FEATURE_EEPROM_INTERNAL_FREQ (1500000) - -/* IOCON module features */ - -/* @brief Func bit field width */ -#define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4) - -/* PINT module features */ - -/* @brief Number of connected outputs */ -#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) - -/* SCT module features */ - -/* @brief Number of events */ -#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (10) -/* @brief Number of states */ -#define FSL_FEATURE_SCT_NUMBER_OF_STATES (10) -/* @brief Number of match capture */ -#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (10) - -/* SDIF module features */ - -/* @brief FIFO depth, every location is a WORD */ -#define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS (64) -/* @brief Max DMA buffer size */ -#define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE (4096) -/* @brief Max source clock in HZ */ -#define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK (52000000) - -/* SPIFI module features */ - -/* @brief SPIFI start address */ -#define FSL_FEATURE_SPIFI_START_ADDR (0x10000000) -/* @brief SPIFI end address */ -#define FSL_FEATURE_SPIFI_END_ADDR (0x17FFFFFF) - -/* SYSCON module features */ - -/* @brief Pointer to ROM IAP entry functions */ -#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205) -/* @brief Flash page size in bytes */ -#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (256) -/* @brief Flash sector size in bytes */ -#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768) -/* @brief Flash size in bytes */ -#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (524288) - -/* USB module features */ - -/* @brief Size of the USB dedicated RAM */ -#define FSL_FEATURE_USB_USB_RAM (0x00002000) -/* @brief Base address of the USB dedicated RAM */ -#define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (0x40100000) - -/* USBFSH module features */ - -/* @brief Size of the USB dedicated RAM */ -#define FSL_FEATURE_USBFSH_USB_RAM (0x00002000) -/* @brief Base address of the USB dedicated RAM */ -#define FSL_FEATURE_USBFSH_USB_RAM_BASE_ADDRESS (0x40100000) - -/* USBHSD module features */ - -/* @brief Size of the USB dedicated RAM */ -#define FSL_FEATURE_USBHSD_USB_RAM (0x00002000) -/* @brief Base address of the USB dedicated RAM */ -#define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x40100000) - -/* USBHSH module features */ - -/* @brief Size of the USB dedicated RAM */ -#define FSL_FEATURE_USBHSH_USB_RAM (0x00002000) -/* @brief Base address of the USB dedicated RAM */ -#define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000) - -#endif /* _LPC54618_FEATURES_H_ */ -
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/LPC54628.h Tue Mar 20 16:56:18 2018 +0000
@@ -0,0 +1,12527 @@
+/*
+** ###################################################################
+** Processor: LPC54628J512ET180
+** Compilers: Keil ARM C/C++ Compiler
+** GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+** MCUXpresso Compiler
+**
+** Reference manual: LPC546xx User manual Rev.1.9 5 June 2017
+** Version: rev. 1.2, 2017-06-08
+** Build: b170609
+**
+** Abstract:
+** CMSIS Peripheral Access Layer for LPC54628
+**
+** Copyright 1997-2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2017 NXP
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** 1. Redistributions of source code must retain the above copyright notice, this list
+** of conditions and the following disclaimer.
+**
+** 2. Redistributions in binary form must reproduce the above copyright notice, this
+** list of conditions and the following disclaimer in the documentation and/or
+** other materials provided with the distribution.
+**
+** 3. Neither the name of the copyright holder nor the names of its
+** contributors may be used to endorse or promote products derived from this
+** software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** Revisions:
+** - rev. 1.0 (2016-08-12)
+** Initial version.
+** - rev. 1.1 (2016-11-25)
+** Update CANFD and Classic CAN register.
+** Add MAC TIMERSTAMP registers.
+** - rev. 1.2 (2017-06-08)
+** Remove RTC_CTRL_RTC_OSC_BYPASS.
+** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV.
+** Remove RESET and HALT from SYSCON_AHBCLKDIV.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file LPC54628.h
+ * @version 1.2
+ * @date 2017-06-08
+ * @brief CMSIS Peripheral Access Layer for LPC54628
+ *
+ * CMSIS Peripheral Access Layer for LPC54628
+ */
+
+#ifndef _LPC54628_H_
+#define _LPC54628_H_ /**< Symbol preventing repeated inclusion */
+
+/** Memory map major version (memory maps with equal major version number are
+ * compatible) */
+#define MCU_MEM_MAP_VERSION 0x0100U
+/** Memory map minor version */
+#define MCU_MEM_MAP_VERSION_MINOR 0x0002U
+
+
+/* ----------------------------------------------------------------------------
+ -- Interrupt vector numbers
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Interrupt_vector_numbers Interrupt vector numbers
+ * @{
+ */
+
+/** Interrupt Number Definitions */
+#define NUMBER_OF_INT_VECTORS 73 /**< Number of interrupts in the Vector table */
+
+typedef enum IRQn {
+ /* Auxiliary constants */
+ NotAvail_IRQn = -128, /**< Not available device specific interrupt */
+
+ /* Core interrupts */
+ NonMaskableInt_IRQn = -14, /**< Non Maskable Interrupt */
+ HardFault_IRQn = -13, /**< Cortex-M4 SV Hard Fault Interrupt */
+ MemoryManagement_IRQn = -12, /**< Cortex-M4 Memory Management Interrupt */
+ BusFault_IRQn = -11, /**< Cortex-M4 Bus Fault Interrupt */
+ UsageFault_IRQn = -10, /**< Cortex-M4 Usage Fault Interrupt */
+ SVCall_IRQn = -5, /**< Cortex-M4 SV Call Interrupt */
+ DebugMonitor_IRQn = -4, /**< Cortex-M4 Debug Monitor Interrupt */
+ PendSV_IRQn = -2, /**< Cortex-M4 Pend SV Interrupt */
+ SysTick_IRQn = -1, /**< Cortex-M4 System Tick Interrupt */
+
+ /* Device specific interrupts */
+ WDT_BOD_IRQn = 0, /**< Windowed watchdog timer, Brownout detect */
+ DMA0_IRQn = 1, /**< DMA controller */
+ GINT0_IRQn = 2, /**< GPIO group 0 */
+ GINT1_IRQn = 3, /**< GPIO group 1 */
+ PIN_INT0_IRQn = 4, /**< Pin interrupt 0 or pattern match engine slice 0 */
+ PIN_INT1_IRQn = 5, /**< Pin interrupt 1or pattern match engine slice 1 */
+ PIN_INT2_IRQn = 6, /**< Pin interrupt 2 or pattern match engine slice 2 */
+ PIN_INT3_IRQn = 7, /**< Pin interrupt 3 or pattern match engine slice 3 */
+ UTICK0_IRQn = 8, /**< Micro-tick Timer */
+ MRT0_IRQn = 9, /**< Multi-rate timer */
+ CTIMER0_IRQn = 10, /**< Standard counter/timer CTIMER0 */
+ CTIMER1_IRQn = 11, /**< Standard counter/timer CTIMER1 */
+ SCT0_IRQn = 12, /**< SCTimer/PWM */
+ CTIMER3_IRQn = 13, /**< Standard counter/timer CTIMER3 */
+ FLEXCOMM0_IRQn = 14, /**< Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) */
+ FLEXCOMM1_IRQn = 15, /**< Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) */
+ FLEXCOMM2_IRQn = 16, /**< Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) */
+ FLEXCOMM3_IRQn = 17, /**< Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) */
+ FLEXCOMM4_IRQn = 18, /**< Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) */
+ FLEXCOMM5_IRQn = 19, /**< Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM) */
+ FLEXCOMM6_IRQn = 20, /**< Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM) */
+ FLEXCOMM7_IRQn = 21, /**< Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM) */
+ ADC0_SEQA_IRQn = 22, /**< ADC0 sequence A completion. */
+ ADC0_SEQB_IRQn = 23, /**< ADC0 sequence B completion. */
+ ADC0_THCMP_IRQn = 24, /**< ADC0 threshold compare and error. */
+ DMIC0_IRQn = 25, /**< Digital microphone and DMIC subsystem */
+ HWVAD0_IRQn = 26, /**< Hardware Voice Activity Detector */
+ USB0_NEEDCLK_IRQn = 27, /**< USB Activity Wake-up Interrupt */
+ USB0_IRQn = 28, /**< USB device */
+ RTC_IRQn = 29, /**< RTC alarm and wake-up interrupts */
+ Reserved46_IRQn = 30, /**< Reserved interrupt */
+ Reserved47_IRQn = 31, /**< Reserved interrupt */
+ PIN_INT4_IRQn = 32, /**< Pin interrupt 4 or pattern match engine slice 4 int */
+ PIN_INT5_IRQn = 33, /**< Pin interrupt 5 or pattern match engine slice 5 int */
+ PIN_INT6_IRQn = 34, /**< Pin interrupt 6 or pattern match engine slice 6 int */
+ PIN_INT7_IRQn = 35, /**< Pin interrupt 7 or pattern match engine slice 7 int */
+ CTIMER2_IRQn = 36, /**< Standard counter/timer CTIMER2 */
+ CTIMER4_IRQn = 37, /**< Standard counter/timer CTIMER4 */
+ RIT_IRQn = 38, /**< Repetitive Interrupt Timer */
+ SPIFI0_IRQn = 39, /**< SPI flash interface */
+ FLEXCOMM8_IRQn = 40, /**< Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM) */
+ FLEXCOMM9_IRQn = 41, /**< Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM) */
+ SDIO_IRQn = 42, /**< SD/MMC */
+ CAN0_IRQ0_IRQn = 43, /**< CAN0 interrupt0 */
+ CAN0_IRQ1_IRQn = 44, /**< CAN0 interrupt1 */
+ CAN1_IRQ0_IRQn = 45, /**< CAN1 interrupt0 */
+ CAN1_IRQ1_IRQn = 46, /**< CAN1 interrupt1 */
+ USB1_IRQn = 47, /**< USB1 interrupt */
+ USB1_NEEDCLK_IRQn = 48, /**< USB1 activity */
+ ETHERNET_IRQn = 49, /**< Ethernet */
+ ETHERNET_PMT_IRQn = 50, /**< Ethernet power management interrupt */
+ ETHERNET_MACLP_IRQn = 51, /**< Ethernet MAC interrupt */
+ EEPROM_IRQn = 52, /**< EEPROM interrupt */
+ LCD_IRQn = 53, /**< LCD interrupt */
+ SHA_IRQn = 54, /**< SHA interrupt */
+ SMARTCARD0_IRQn = 55, /**< Smart card 0 interrupt */
+ SMARTCARD1_IRQn = 56 /**< Smart card 1 interrupt */
+} IRQn_Type;
+
+/*!
+ * @}
+ */ /* end of group Interrupt_vector_numbers */
+
+
+/* ----------------------------------------------------------------------------
+ -- Cortex M4 Core Configuration
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Cortex_Core_Configuration Cortex M4 Core Configuration
+ * @{
+ */
+
+#define __MPU_PRESENT 1 /**< Defines if an MPU is present or not */
+#define __NVIC_PRIO_BITS 3 /**< Number of priority bits implemented in the NVIC */
+#define __Vendor_SysTickConfig 0 /**< Vendor specific implementation of SysTickConfig is defined */
+#define __FPU_PRESENT 1 /**< Defines if an FPU is present or not */
+
+#include "core_cm4.h" /* Core Peripheral Access Layer */
+#include "system_LPC54628.h" /* Device specific configuration file */
+
+/*!
+ * @}
+ */ /* end of group Cortex_Core_Configuration */
+
+
+/* ----------------------------------------------------------------------------
+ -- Device Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Peripheral_access_layer Device Peripheral Access Layer
+ * @{
+ */
+
+
+/*
+** Start of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+ #pragma push
+ #pragma anon_unions
+#elif defined(__GNUC__)
+ /* anonymous unions are enabled by default */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma language=extended
+#else
+ #error Not supported compiler type
+#endif
+
+/* ----------------------------------------------------------------------------
+ -- ADC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Peripheral_Access_Layer ADC Peripheral Access Layer
+ * @{
+ */
+
+/** ADC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CTRL; /**< ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls., offset: 0x0 */
+ __IO uint32_t INSEL; /**< Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0., offset: 0x4 */
+ __IO uint32_t SEQ_CTRL[2]; /**< ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n., array offset: 0x8, array step: 0x4 */
+ __I uint32_t SEQ_GDAT[2]; /**< ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n., array offset: 0x10, array step: 0x4 */
+ uint8_t RESERVED_0[8];
+ __I uint32_t DAT[12]; /**< ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0., array offset: 0x20, array step: 0x4 */
+ __IO uint32_t THR0_LOW; /**< ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x50 */
+ __IO uint32_t THR1_LOW; /**< ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x54 */
+ __IO uint32_t THR0_HIGH; /**< ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0., offset: 0x58 */
+ __IO uint32_t THR1_HIGH; /**< ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1., offset: 0x5C */
+ __IO uint32_t CHAN_THRSEL; /**< ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel, offset: 0x60 */
+ __IO uint32_t INTEN; /**< ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated., offset: 0x64 */
+ __IO uint32_t FLAGS; /**< ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers)., offset: 0x68 */
+ __IO uint32_t STARTUP; /**< ADC Startup register., offset: 0x6C */
+ __IO uint32_t CALIB; /**< ADC Calibration register., offset: 0x70 */
+} ADC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- ADC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ADC_Register_Masks ADC Register Masks
+ * @{
+ */
+
+/*! @name CTRL - ADC Control register. Contains the clock divide value, resolution selection, sampling time selection, and mode controls. */
+#define ADC_CTRL_CLKDIV_MASK (0xFFU)
+#define ADC_CTRL_CLKDIV_SHIFT (0U)
+#define ADC_CTRL_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_CLKDIV_SHIFT)) & ADC_CTRL_CLKDIV_MASK)
+#define ADC_CTRL_ASYNMODE_MASK (0x100U)
+#define ADC_CTRL_ASYNMODE_SHIFT (8U)
+#define ADC_CTRL_ASYNMODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_ASYNMODE_SHIFT)) & ADC_CTRL_ASYNMODE_MASK)
+#define ADC_CTRL_RESOL_MASK (0x600U)
+#define ADC_CTRL_RESOL_SHIFT (9U)
+#define ADC_CTRL_RESOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_RESOL_SHIFT)) & ADC_CTRL_RESOL_MASK)
+#define ADC_CTRL_BYPASSCAL_MASK (0x800U)
+#define ADC_CTRL_BYPASSCAL_SHIFT (11U)
+#define ADC_CTRL_BYPASSCAL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_BYPASSCAL_SHIFT)) & ADC_CTRL_BYPASSCAL_MASK)
+#define ADC_CTRL_TSAMP_MASK (0x7000U)
+#define ADC_CTRL_TSAMP_SHIFT (12U)
+#define ADC_CTRL_TSAMP(x) (((uint32_t)(((uint32_t)(x)) << ADC_CTRL_TSAMP_SHIFT)) & ADC_CTRL_TSAMP_MASK)
+
+/*! @name INSEL - Input Select. Allows selection of the temperature sensor as an alternate input to ADC channel 0. */
+#define ADC_INSEL_SEL_MASK (0x3U)
+#define ADC_INSEL_SEL_SHIFT (0U)
+#define ADC_INSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_INSEL_SEL_SHIFT)) & ADC_INSEL_SEL_MASK)
+
+/*! @name SEQ_CTRL - ADC Conversion Sequence-n control register: Controls triggering and channel selection for conversion sequence-n. Also specifies interrupt mode for sequence-n. */
+#define ADC_SEQ_CTRL_CHANNELS_MASK (0xFFFU)
+#define ADC_SEQ_CTRL_CHANNELS_SHIFT (0U)
+#define ADC_SEQ_CTRL_CHANNELS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_CHANNELS_SHIFT)) & ADC_SEQ_CTRL_CHANNELS_MASK)
+#define ADC_SEQ_CTRL_TRIGGER_MASK (0x3F000U)
+#define ADC_SEQ_CTRL_TRIGGER_SHIFT (12U)
+#define ADC_SEQ_CTRL_TRIGGER(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGGER_SHIFT)) & ADC_SEQ_CTRL_TRIGGER_MASK)
+#define ADC_SEQ_CTRL_TRIGPOL_MASK (0x40000U)
+#define ADC_SEQ_CTRL_TRIGPOL_SHIFT (18U)
+#define ADC_SEQ_CTRL_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_TRIGPOL_SHIFT)) & ADC_SEQ_CTRL_TRIGPOL_MASK)
+#define ADC_SEQ_CTRL_SYNCBYPASS_MASK (0x80000U)
+#define ADC_SEQ_CTRL_SYNCBYPASS_SHIFT (19U)
+#define ADC_SEQ_CTRL_SYNCBYPASS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SYNCBYPASS_SHIFT)) & ADC_SEQ_CTRL_SYNCBYPASS_MASK)
+#define ADC_SEQ_CTRL_START_MASK (0x4000000U)
+#define ADC_SEQ_CTRL_START_SHIFT (26U)
+#define ADC_SEQ_CTRL_START(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_START_SHIFT)) & ADC_SEQ_CTRL_START_MASK)
+#define ADC_SEQ_CTRL_BURST_MASK (0x8000000U)
+#define ADC_SEQ_CTRL_BURST_SHIFT (27U)
+#define ADC_SEQ_CTRL_BURST(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_BURST_SHIFT)) & ADC_SEQ_CTRL_BURST_MASK)
+#define ADC_SEQ_CTRL_SINGLESTEP_MASK (0x10000000U)
+#define ADC_SEQ_CTRL_SINGLESTEP_SHIFT (28U)
+#define ADC_SEQ_CTRL_SINGLESTEP(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SINGLESTEP_SHIFT)) & ADC_SEQ_CTRL_SINGLESTEP_MASK)
+#define ADC_SEQ_CTRL_LOWPRIO_MASK (0x20000000U)
+#define ADC_SEQ_CTRL_LOWPRIO_SHIFT (29U)
+#define ADC_SEQ_CTRL_LOWPRIO(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_LOWPRIO_SHIFT)) & ADC_SEQ_CTRL_LOWPRIO_MASK)
+#define ADC_SEQ_CTRL_MODE_MASK (0x40000000U)
+#define ADC_SEQ_CTRL_MODE_SHIFT (30U)
+#define ADC_SEQ_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_MODE_SHIFT)) & ADC_SEQ_CTRL_MODE_MASK)
+#define ADC_SEQ_CTRL_SEQ_ENA_MASK (0x80000000U)
+#define ADC_SEQ_CTRL_SEQ_ENA_SHIFT (31U)
+#define ADC_SEQ_CTRL_SEQ_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_CTRL_SEQ_ENA_SHIFT)) & ADC_SEQ_CTRL_SEQ_ENA_MASK)
+
+/* The count of ADC_SEQ_CTRL */
+#define ADC_SEQ_CTRL_COUNT (2U)
+
+/*! @name SEQ_GDAT - ADC Sequence-n Global Data register. This register contains the result of the most recent ADC conversion performed under sequence-n. */
+#define ADC_SEQ_GDAT_RESULT_MASK (0xFFF0U)
+#define ADC_SEQ_GDAT_RESULT_SHIFT (4U)
+#define ADC_SEQ_GDAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_RESULT_SHIFT)) & ADC_SEQ_GDAT_RESULT_MASK)
+#define ADC_SEQ_GDAT_THCMPRANGE_MASK (0x30000U)
+#define ADC_SEQ_GDAT_THCMPRANGE_SHIFT (16U)
+#define ADC_SEQ_GDAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPRANGE_SHIFT)) & ADC_SEQ_GDAT_THCMPRANGE_MASK)
+#define ADC_SEQ_GDAT_THCMPCROSS_MASK (0xC0000U)
+#define ADC_SEQ_GDAT_THCMPCROSS_SHIFT (18U)
+#define ADC_SEQ_GDAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_THCMPCROSS_SHIFT)) & ADC_SEQ_GDAT_THCMPCROSS_MASK)
+#define ADC_SEQ_GDAT_CHN_MASK (0x3C000000U)
+#define ADC_SEQ_GDAT_CHN_SHIFT (26U)
+#define ADC_SEQ_GDAT_CHN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_CHN_SHIFT)) & ADC_SEQ_GDAT_CHN_MASK)
+#define ADC_SEQ_GDAT_OVERRUN_MASK (0x40000000U)
+#define ADC_SEQ_GDAT_OVERRUN_SHIFT (30U)
+#define ADC_SEQ_GDAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_OVERRUN_SHIFT)) & ADC_SEQ_GDAT_OVERRUN_MASK)
+#define ADC_SEQ_GDAT_DATAVALID_MASK (0x80000000U)
+#define ADC_SEQ_GDAT_DATAVALID_SHIFT (31U)
+#define ADC_SEQ_GDAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_SEQ_GDAT_DATAVALID_SHIFT)) & ADC_SEQ_GDAT_DATAVALID_MASK)
+
+/* The count of ADC_SEQ_GDAT */
+#define ADC_SEQ_GDAT_COUNT (2U)
+
+/*! @name DAT - ADC Channel 0 Data register. This register contains the result of the most recent conversion completed on channel 0. */
+#define ADC_DAT_RESULT_MASK (0xFFF0U)
+#define ADC_DAT_RESULT_SHIFT (4U)
+#define ADC_DAT_RESULT(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_RESULT_SHIFT)) & ADC_DAT_RESULT_MASK)
+#define ADC_DAT_THCMPRANGE_MASK (0x30000U)
+#define ADC_DAT_THCMPRANGE_SHIFT (16U)
+#define ADC_DAT_THCMPRANGE(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPRANGE_SHIFT)) & ADC_DAT_THCMPRANGE_MASK)
+#define ADC_DAT_THCMPCROSS_MASK (0xC0000U)
+#define ADC_DAT_THCMPCROSS_SHIFT (18U)
+#define ADC_DAT_THCMPCROSS(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_THCMPCROSS_SHIFT)) & ADC_DAT_THCMPCROSS_MASK)
+#define ADC_DAT_CHANNEL_MASK (0x3C000000U)
+#define ADC_DAT_CHANNEL_SHIFT (26U)
+#define ADC_DAT_CHANNEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_CHANNEL_SHIFT)) & ADC_DAT_CHANNEL_MASK)
+#define ADC_DAT_OVERRUN_MASK (0x40000000U)
+#define ADC_DAT_OVERRUN_SHIFT (30U)
+#define ADC_DAT_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_OVERRUN_SHIFT)) & ADC_DAT_OVERRUN_MASK)
+#define ADC_DAT_DATAVALID_MASK (0x80000000U)
+#define ADC_DAT_DATAVALID_SHIFT (31U)
+#define ADC_DAT_DATAVALID(x) (((uint32_t)(((uint32_t)(x)) << ADC_DAT_DATAVALID_SHIFT)) & ADC_DAT_DATAVALID_MASK)
+
+/* The count of ADC_DAT */
+#define ADC_DAT_COUNT (12U)
+
+/*! @name THR0_LOW - ADC Low Compare Threshold register 0: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */
+#define ADC_THR0_LOW_THRLOW_MASK (0xFFF0U)
+#define ADC_THR0_LOW_THRLOW_SHIFT (4U)
+#define ADC_THR0_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_LOW_THRLOW_SHIFT)) & ADC_THR0_LOW_THRLOW_MASK)
+
+/*! @name THR1_LOW - ADC Low Compare Threshold register 1: Contains the lower threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */
+#define ADC_THR1_LOW_THRLOW_MASK (0xFFF0U)
+#define ADC_THR1_LOW_THRLOW_SHIFT (4U)
+#define ADC_THR1_LOW_THRLOW(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_LOW_THRLOW_SHIFT)) & ADC_THR1_LOW_THRLOW_MASK)
+
+/*! @name THR0_HIGH - ADC High Compare Threshold register 0: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 0. */
+#define ADC_THR0_HIGH_THRHIGH_MASK (0xFFF0U)
+#define ADC_THR0_HIGH_THRHIGH_SHIFT (4U)
+#define ADC_THR0_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR0_HIGH_THRHIGH_SHIFT)) & ADC_THR0_HIGH_THRHIGH_MASK)
+
+/*! @name THR1_HIGH - ADC High Compare Threshold register 1: Contains the upper threshold level for automatic threshold comparison for any channels linked to threshold pair 1. */
+#define ADC_THR1_HIGH_THRHIGH_MASK (0xFFF0U)
+#define ADC_THR1_HIGH_THRHIGH_SHIFT (4U)
+#define ADC_THR1_HIGH_THRHIGH(x) (((uint32_t)(((uint32_t)(x)) << ADC_THR1_HIGH_THRHIGH_SHIFT)) & ADC_THR1_HIGH_THRHIGH_MASK)
+
+/*! @name CHAN_THRSEL - ADC Channel-Threshold Select register. Specifies which set of threshold compare registers are to be used for each channel */
+#define ADC_CHAN_THRSEL_CH0_THRSEL_MASK (0x1U)
+#define ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT (0U)
+#define ADC_CHAN_THRSEL_CH0_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH0_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH0_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH1_THRSEL_MASK (0x2U)
+#define ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT (1U)
+#define ADC_CHAN_THRSEL_CH1_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH1_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH1_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH2_THRSEL_MASK (0x4U)
+#define ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT (2U)
+#define ADC_CHAN_THRSEL_CH2_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH2_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH2_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH3_THRSEL_MASK (0x8U)
+#define ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT (3U)
+#define ADC_CHAN_THRSEL_CH3_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH3_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH3_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH4_THRSEL_MASK (0x10U)
+#define ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT (4U)
+#define ADC_CHAN_THRSEL_CH4_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH4_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH4_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH5_THRSEL_MASK (0x20U)
+#define ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT (5U)
+#define ADC_CHAN_THRSEL_CH5_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH5_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH5_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH6_THRSEL_MASK (0x40U)
+#define ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT (6U)
+#define ADC_CHAN_THRSEL_CH6_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH6_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH6_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH7_THRSEL_MASK (0x80U)
+#define ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT (7U)
+#define ADC_CHAN_THRSEL_CH7_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH7_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH7_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH8_THRSEL_MASK (0x100U)
+#define ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT (8U)
+#define ADC_CHAN_THRSEL_CH8_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH8_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH8_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH9_THRSEL_MASK (0x200U)
+#define ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT (9U)
+#define ADC_CHAN_THRSEL_CH9_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH9_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH9_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH10_THRSEL_MASK (0x400U)
+#define ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT (10U)
+#define ADC_CHAN_THRSEL_CH10_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH10_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH10_THRSEL_MASK)
+#define ADC_CHAN_THRSEL_CH11_THRSEL_MASK (0x800U)
+#define ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT (11U)
+#define ADC_CHAN_THRSEL_CH11_THRSEL(x) (((uint32_t)(((uint32_t)(x)) << ADC_CHAN_THRSEL_CH11_THRSEL_SHIFT)) & ADC_CHAN_THRSEL_CH11_THRSEL_MASK)
+
+/*! @name INTEN - ADC Interrupt Enable register. This register contains enable bits that enable the sequence-A, sequence-B, threshold compare and data overrun interrupts to be generated. */
+#define ADC_INTEN_SEQA_INTEN_MASK (0x1U)
+#define ADC_INTEN_SEQA_INTEN_SHIFT (0U)
+#define ADC_INTEN_SEQA_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQA_INTEN_SHIFT)) & ADC_INTEN_SEQA_INTEN_MASK)
+#define ADC_INTEN_SEQB_INTEN_MASK (0x2U)
+#define ADC_INTEN_SEQB_INTEN_SHIFT (1U)
+#define ADC_INTEN_SEQB_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_SEQB_INTEN_SHIFT)) & ADC_INTEN_SEQB_INTEN_MASK)
+#define ADC_INTEN_OVR_INTEN_MASK (0x4U)
+#define ADC_INTEN_OVR_INTEN_SHIFT (2U)
+#define ADC_INTEN_OVR_INTEN(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_OVR_INTEN_SHIFT)) & ADC_INTEN_OVR_INTEN_MASK)
+#define ADC_INTEN_ADCMPINTEN0_MASK (0x18U)
+#define ADC_INTEN_ADCMPINTEN0_SHIFT (3U)
+#define ADC_INTEN_ADCMPINTEN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN0_SHIFT)) & ADC_INTEN_ADCMPINTEN0_MASK)
+#define ADC_INTEN_ADCMPINTEN1_MASK (0x60U)
+#define ADC_INTEN_ADCMPINTEN1_SHIFT (5U)
+#define ADC_INTEN_ADCMPINTEN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN1_SHIFT)) & ADC_INTEN_ADCMPINTEN1_MASK)
+#define ADC_INTEN_ADCMPINTEN2_MASK (0x180U)
+#define ADC_INTEN_ADCMPINTEN2_SHIFT (7U)
+#define ADC_INTEN_ADCMPINTEN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN2_SHIFT)) & ADC_INTEN_ADCMPINTEN2_MASK)
+#define ADC_INTEN_ADCMPINTEN3_MASK (0x600U)
+#define ADC_INTEN_ADCMPINTEN3_SHIFT (9U)
+#define ADC_INTEN_ADCMPINTEN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN3_SHIFT)) & ADC_INTEN_ADCMPINTEN3_MASK)
+#define ADC_INTEN_ADCMPINTEN4_MASK (0x1800U)
+#define ADC_INTEN_ADCMPINTEN4_SHIFT (11U)
+#define ADC_INTEN_ADCMPINTEN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN4_SHIFT)) & ADC_INTEN_ADCMPINTEN4_MASK)
+#define ADC_INTEN_ADCMPINTEN5_MASK (0x6000U)
+#define ADC_INTEN_ADCMPINTEN5_SHIFT (13U)
+#define ADC_INTEN_ADCMPINTEN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN5_SHIFT)) & ADC_INTEN_ADCMPINTEN5_MASK)
+#define ADC_INTEN_ADCMPINTEN6_MASK (0x18000U)
+#define ADC_INTEN_ADCMPINTEN6_SHIFT (15U)
+#define ADC_INTEN_ADCMPINTEN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN6_SHIFT)) & ADC_INTEN_ADCMPINTEN6_MASK)
+#define ADC_INTEN_ADCMPINTEN7_MASK (0x60000U)
+#define ADC_INTEN_ADCMPINTEN7_SHIFT (17U)
+#define ADC_INTEN_ADCMPINTEN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN7_SHIFT)) & ADC_INTEN_ADCMPINTEN7_MASK)
+#define ADC_INTEN_ADCMPINTEN8_MASK (0x180000U)
+#define ADC_INTEN_ADCMPINTEN8_SHIFT (19U)
+#define ADC_INTEN_ADCMPINTEN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN8_SHIFT)) & ADC_INTEN_ADCMPINTEN8_MASK)
+#define ADC_INTEN_ADCMPINTEN9_MASK (0x600000U)
+#define ADC_INTEN_ADCMPINTEN9_SHIFT (21U)
+#define ADC_INTEN_ADCMPINTEN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN9_SHIFT)) & ADC_INTEN_ADCMPINTEN9_MASK)
+#define ADC_INTEN_ADCMPINTEN10_MASK (0x1800000U)
+#define ADC_INTEN_ADCMPINTEN10_SHIFT (23U)
+#define ADC_INTEN_ADCMPINTEN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN10_SHIFT)) & ADC_INTEN_ADCMPINTEN10_MASK)
+#define ADC_INTEN_ADCMPINTEN11_MASK (0x6000000U)
+#define ADC_INTEN_ADCMPINTEN11_SHIFT (25U)
+#define ADC_INTEN_ADCMPINTEN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_INTEN_ADCMPINTEN11_SHIFT)) & ADC_INTEN_ADCMPINTEN11_MASK)
+
+/*! @name FLAGS - ADC Flags register. Contains the four interrupt/DMA trigger flags and the individual component overrun and threshold-compare flags. (The overrun bits replicate information stored in the result registers). */
+#define ADC_FLAGS_THCMP0_MASK (0x1U)
+#define ADC_FLAGS_THCMP0_SHIFT (0U)
+#define ADC_FLAGS_THCMP0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP0_SHIFT)) & ADC_FLAGS_THCMP0_MASK)
+#define ADC_FLAGS_THCMP1_MASK (0x2U)
+#define ADC_FLAGS_THCMP1_SHIFT (1U)
+#define ADC_FLAGS_THCMP1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP1_SHIFT)) & ADC_FLAGS_THCMP1_MASK)
+#define ADC_FLAGS_THCMP2_MASK (0x4U)
+#define ADC_FLAGS_THCMP2_SHIFT (2U)
+#define ADC_FLAGS_THCMP2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP2_SHIFT)) & ADC_FLAGS_THCMP2_MASK)
+#define ADC_FLAGS_THCMP3_MASK (0x8U)
+#define ADC_FLAGS_THCMP3_SHIFT (3U)
+#define ADC_FLAGS_THCMP3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP3_SHIFT)) & ADC_FLAGS_THCMP3_MASK)
+#define ADC_FLAGS_THCMP4_MASK (0x10U)
+#define ADC_FLAGS_THCMP4_SHIFT (4U)
+#define ADC_FLAGS_THCMP4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP4_SHIFT)) & ADC_FLAGS_THCMP4_MASK)
+#define ADC_FLAGS_THCMP5_MASK (0x20U)
+#define ADC_FLAGS_THCMP5_SHIFT (5U)
+#define ADC_FLAGS_THCMP5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP5_SHIFT)) & ADC_FLAGS_THCMP5_MASK)
+#define ADC_FLAGS_THCMP6_MASK (0x40U)
+#define ADC_FLAGS_THCMP6_SHIFT (6U)
+#define ADC_FLAGS_THCMP6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP6_SHIFT)) & ADC_FLAGS_THCMP6_MASK)
+#define ADC_FLAGS_THCMP7_MASK (0x80U)
+#define ADC_FLAGS_THCMP7_SHIFT (7U)
+#define ADC_FLAGS_THCMP7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP7_SHIFT)) & ADC_FLAGS_THCMP7_MASK)
+#define ADC_FLAGS_THCMP8_MASK (0x100U)
+#define ADC_FLAGS_THCMP8_SHIFT (8U)
+#define ADC_FLAGS_THCMP8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP8_SHIFT)) & ADC_FLAGS_THCMP8_MASK)
+#define ADC_FLAGS_THCMP9_MASK (0x200U)
+#define ADC_FLAGS_THCMP9_SHIFT (9U)
+#define ADC_FLAGS_THCMP9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP9_SHIFT)) & ADC_FLAGS_THCMP9_MASK)
+#define ADC_FLAGS_THCMP10_MASK (0x400U)
+#define ADC_FLAGS_THCMP10_SHIFT (10U)
+#define ADC_FLAGS_THCMP10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP10_SHIFT)) & ADC_FLAGS_THCMP10_MASK)
+#define ADC_FLAGS_THCMP11_MASK (0x800U)
+#define ADC_FLAGS_THCMP11_SHIFT (11U)
+#define ADC_FLAGS_THCMP11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP11_SHIFT)) & ADC_FLAGS_THCMP11_MASK)
+#define ADC_FLAGS_OVERRUN0_MASK (0x1000U)
+#define ADC_FLAGS_OVERRUN0_SHIFT (12U)
+#define ADC_FLAGS_OVERRUN0(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN0_SHIFT)) & ADC_FLAGS_OVERRUN0_MASK)
+#define ADC_FLAGS_OVERRUN1_MASK (0x2000U)
+#define ADC_FLAGS_OVERRUN1_SHIFT (13U)
+#define ADC_FLAGS_OVERRUN1(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN1_SHIFT)) & ADC_FLAGS_OVERRUN1_MASK)
+#define ADC_FLAGS_OVERRUN2_MASK (0x4000U)
+#define ADC_FLAGS_OVERRUN2_SHIFT (14U)
+#define ADC_FLAGS_OVERRUN2(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN2_SHIFT)) & ADC_FLAGS_OVERRUN2_MASK)
+#define ADC_FLAGS_OVERRUN3_MASK (0x8000U)
+#define ADC_FLAGS_OVERRUN3_SHIFT (15U)
+#define ADC_FLAGS_OVERRUN3(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN3_SHIFT)) & ADC_FLAGS_OVERRUN3_MASK)
+#define ADC_FLAGS_OVERRUN4_MASK (0x10000U)
+#define ADC_FLAGS_OVERRUN4_SHIFT (16U)
+#define ADC_FLAGS_OVERRUN4(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN4_SHIFT)) & ADC_FLAGS_OVERRUN4_MASK)
+#define ADC_FLAGS_OVERRUN5_MASK (0x20000U)
+#define ADC_FLAGS_OVERRUN5_SHIFT (17U)
+#define ADC_FLAGS_OVERRUN5(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN5_SHIFT)) & ADC_FLAGS_OVERRUN5_MASK)
+#define ADC_FLAGS_OVERRUN6_MASK (0x40000U)
+#define ADC_FLAGS_OVERRUN6_SHIFT (18U)
+#define ADC_FLAGS_OVERRUN6(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN6_SHIFT)) & ADC_FLAGS_OVERRUN6_MASK)
+#define ADC_FLAGS_OVERRUN7_MASK (0x80000U)
+#define ADC_FLAGS_OVERRUN7_SHIFT (19U)
+#define ADC_FLAGS_OVERRUN7(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN7_SHIFT)) & ADC_FLAGS_OVERRUN7_MASK)
+#define ADC_FLAGS_OVERRUN8_MASK (0x100000U)
+#define ADC_FLAGS_OVERRUN8_SHIFT (20U)
+#define ADC_FLAGS_OVERRUN8(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN8_SHIFT)) & ADC_FLAGS_OVERRUN8_MASK)
+#define ADC_FLAGS_OVERRUN9_MASK (0x200000U)
+#define ADC_FLAGS_OVERRUN9_SHIFT (21U)
+#define ADC_FLAGS_OVERRUN9(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN9_SHIFT)) & ADC_FLAGS_OVERRUN9_MASK)
+#define ADC_FLAGS_OVERRUN10_MASK (0x400000U)
+#define ADC_FLAGS_OVERRUN10_SHIFT (22U)
+#define ADC_FLAGS_OVERRUN10(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN10_SHIFT)) & ADC_FLAGS_OVERRUN10_MASK)
+#define ADC_FLAGS_OVERRUN11_MASK (0x800000U)
+#define ADC_FLAGS_OVERRUN11_SHIFT (23U)
+#define ADC_FLAGS_OVERRUN11(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVERRUN11_SHIFT)) & ADC_FLAGS_OVERRUN11_MASK)
+#define ADC_FLAGS_SEQA_OVR_MASK (0x1000000U)
+#define ADC_FLAGS_SEQA_OVR_SHIFT (24U)
+#define ADC_FLAGS_SEQA_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_OVR_SHIFT)) & ADC_FLAGS_SEQA_OVR_MASK)
+#define ADC_FLAGS_SEQB_OVR_MASK (0x2000000U)
+#define ADC_FLAGS_SEQB_OVR_SHIFT (25U)
+#define ADC_FLAGS_SEQB_OVR(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_OVR_SHIFT)) & ADC_FLAGS_SEQB_OVR_MASK)
+#define ADC_FLAGS_SEQA_INT_MASK (0x10000000U)
+#define ADC_FLAGS_SEQA_INT_SHIFT (28U)
+#define ADC_FLAGS_SEQA_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQA_INT_SHIFT)) & ADC_FLAGS_SEQA_INT_MASK)
+#define ADC_FLAGS_SEQB_INT_MASK (0x20000000U)
+#define ADC_FLAGS_SEQB_INT_SHIFT (29U)
+#define ADC_FLAGS_SEQB_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_SEQB_INT_SHIFT)) & ADC_FLAGS_SEQB_INT_MASK)
+#define ADC_FLAGS_THCMP_INT_MASK (0x40000000U)
+#define ADC_FLAGS_THCMP_INT_SHIFT (30U)
+#define ADC_FLAGS_THCMP_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_THCMP_INT_SHIFT)) & ADC_FLAGS_THCMP_INT_MASK)
+#define ADC_FLAGS_OVR_INT_MASK (0x80000000U)
+#define ADC_FLAGS_OVR_INT_SHIFT (31U)
+#define ADC_FLAGS_OVR_INT(x) (((uint32_t)(((uint32_t)(x)) << ADC_FLAGS_OVR_INT_SHIFT)) & ADC_FLAGS_OVR_INT_MASK)
+
+/*! @name STARTUP - ADC Startup register. */
+#define ADC_STARTUP_ADC_ENA_MASK (0x1U)
+#define ADC_STARTUP_ADC_ENA_SHIFT (0U)
+#define ADC_STARTUP_ADC_ENA(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_ENA_SHIFT)) & ADC_STARTUP_ADC_ENA_MASK)
+#define ADC_STARTUP_ADC_INIT_MASK (0x2U)
+#define ADC_STARTUP_ADC_INIT_SHIFT (1U)
+#define ADC_STARTUP_ADC_INIT(x) (((uint32_t)(((uint32_t)(x)) << ADC_STARTUP_ADC_INIT_SHIFT)) & ADC_STARTUP_ADC_INIT_MASK)
+
+/*! @name CALIB - ADC Calibration register. */
+#define ADC_CALIB_CALIB_MASK (0x1U)
+#define ADC_CALIB_CALIB_SHIFT (0U)
+#define ADC_CALIB_CALIB(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALIB_SHIFT)) & ADC_CALIB_CALIB_MASK)
+#define ADC_CALIB_CALREQD_MASK (0x2U)
+#define ADC_CALIB_CALREQD_SHIFT (1U)
+#define ADC_CALIB_CALREQD(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALREQD_SHIFT)) & ADC_CALIB_CALREQD_MASK)
+#define ADC_CALIB_CALVALUE_MASK (0x1FCU)
+#define ADC_CALIB_CALVALUE_SHIFT (2U)
+#define ADC_CALIB_CALVALUE(x) (((uint32_t)(((uint32_t)(x)) << ADC_CALIB_CALVALUE_SHIFT)) & ADC_CALIB_CALVALUE_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group ADC_Register_Masks */
+
+
+/* ADC - Peripheral instance base addresses */
+/** Peripheral ADC0 base address */
+#define ADC0_BASE (0x400A0000u)
+/** Peripheral ADC0 base pointer */
+#define ADC0 ((ADC_Type *)ADC0_BASE)
+/** Array initializer of ADC peripheral base addresses */
+#define ADC_BASE_ADDRS { ADC0_BASE }
+/** Array initializer of ADC peripheral base pointers */
+#define ADC_BASE_PTRS { ADC0 }
+/** Interrupt vectors for the ADC peripheral type */
+#define ADC_SEQ_IRQS { ADC0_SEQA_IRQn, ADC0_SEQB_IRQn }
+#define ADC_THCMP_IRQS { ADC0_THCMP_IRQn }
+
+/*!
+ * @}
+ */ /* end of group ADC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- ASYNC_SYSCON Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ASYNC_SYSCON_Peripheral_Access_Layer ASYNC_SYSCON Peripheral Access Layer
+ * @{
+ */
+
+/** ASYNC_SYSCON - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t ASYNCPRESETCTRL; /**< Async peripheral reset control, offset: 0x0 */
+ __O uint32_t ASYNCPRESETCTRLSET; /**< Set bits in ASYNCPRESETCTRL, offset: 0x4 */
+ __O uint32_t ASYNCPRESETCTRLCLR; /**< Clear bits in ASYNCPRESETCTRL, offset: 0x8 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t ASYNCAPBCLKCTRL; /**< Async peripheral clock control, offset: 0x10 */
+ __O uint32_t ASYNCAPBCLKCTRLSET; /**< Set bits in ASYNCAPBCLKCTRL, offset: 0x14 */
+ __O uint32_t ASYNCAPBCLKCTRLCLR; /**< Clear bits in ASYNCAPBCLKCTRL, offset: 0x18 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t ASYNCAPBCLKSELA; /**< Async APB clock source select A, offset: 0x20 */
+} ASYNC_SYSCON_Type;
+
+/* ----------------------------------------------------------------------------
+ -- ASYNC_SYSCON Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ASYNC_SYSCON_Register_Masks ASYNC_SYSCON Register Masks
+ * @{
+ */
+
+/*! @name ASYNCPRESETCTRL - Async peripheral reset control */
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK (0x2000U)
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT (13U)
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER3_MASK)
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK (0x4000U)
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT (14U)
+#define ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRL_CTIMER4_MASK)
+
+/*! @name ASYNCPRESETCTRLSET - Set bits in ASYNCPRESETCTRL */
+#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK (0xFFFFFFFFU)
+#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT (0U)
+#define ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLSET_ARST_SET_MASK)
+
+/*! @name ASYNCPRESETCTRLCLR - Clear bits in ASYNCPRESETCTRL */
+#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK (0xFFFFFFFFU)
+#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT (0U)
+#define ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCPRESETCTRLCLR_ARST_CLR_MASK)
+
+/*! @name ASYNCAPBCLKCTRL - Async peripheral clock control */
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK (0x2000U)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT (13U)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER3_MASK)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK (0x4000U)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT (14U)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRL_CTIMER4_MASK)
+
+/*! @name ASYNCAPBCLKCTRLSET - Set bits in ASYNCAPBCLKCTRL */
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK (0xFFFFFFFFU)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT (0U)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLSET_ACLK_SET_MASK)
+
+/*! @name ASYNCAPBCLKCTRLCLR - Clear bits in ASYNCAPBCLKCTRL */
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK (0xFFFFFFFFU)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT (0U)
+#define ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKCTRLCLR_ACLK_CLR_MASK)
+
+/*! @name ASYNCAPBCLKSELA - Async APB clock source select A */
+#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK (0x3U)
+#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT (0U)
+#define ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_SHIFT)) & ASYNC_SYSCON_ASYNCAPBCLKSELA_SEL_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group ASYNC_SYSCON_Register_Masks */
+
+
+/* ASYNC_SYSCON - Peripheral instance base addresses */
+/** Peripheral ASYNC_SYSCON base address */
+#define ASYNC_SYSCON_BASE (0x40040000u)
+/** Peripheral ASYNC_SYSCON base pointer */
+#define ASYNC_SYSCON ((ASYNC_SYSCON_Type *)ASYNC_SYSCON_BASE)
+/** Array initializer of ASYNC_SYSCON peripheral base addresses */
+#define ASYNC_SYSCON_BASE_ADDRS { ASYNC_SYSCON_BASE }
+/** Array initializer of ASYNC_SYSCON peripheral base pointers */
+#define ASYNC_SYSCON_BASE_PTRS { ASYNC_SYSCON }
+
+/*!
+ * @}
+ */ /* end of group ASYNC_SYSCON_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CAN Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Peripheral_Access_Layer CAN Peripheral Access Layer
+ * @{
+ */
+
+/** CAN - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[12];
+ __IO uint32_t DBTP; /**< Data Bit Timing Prescaler Register, offset: 0xC */
+ __IO uint32_t TEST; /**< Test Register, offset: 0x10 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t CCCR; /**< CC Control Register, offset: 0x18 */
+ __IO uint32_t NBTP; /**< Nominal Bit Timing and Prescaler Register, offset: 0x1C */
+ __IO uint32_t TSCC; /**< Timestamp Counter Configuration, offset: 0x20 */
+ __IO uint32_t TSCV; /**< Timestamp Counter Value, offset: 0x24 */
+ __IO uint32_t TOCC; /**< Timeout Counter Configuration, offset: 0x28 */
+ __I uint32_t TOCV; /**< Timeout Counter Value, offset: 0x2C */
+ uint8_t RESERVED_2[16];
+ __I uint32_t ECR; /**< Error Counter Register, offset: 0x40 */
+ __I uint32_t PSR; /**< Protocol Status Register, offset: 0x44 */
+ __IO uint32_t TDCR; /**< Transmitter Delay Compensator Register, offset: 0x48 */
+ uint8_t RESERVED_3[4];
+ __IO uint32_t IR; /**< Interrupt Register, offset: 0x50 */
+ __IO uint32_t IE; /**< Interrupt Enable, offset: 0x54 */
+ __IO uint32_t ILS; /**< Interrupt Line Select, offset: 0x58 */
+ __IO uint32_t ILE; /**< Interrupt Line Enable, offset: 0x5C */
+ uint8_t RESERVED_4[32];
+ __IO uint32_t GFC; /**< Global Filter Configuration, offset: 0x80 */
+ __IO uint32_t SIDFC; /**< Standard ID Filter Configuration, offset: 0x84 */
+ __IO uint32_t XIDFC; /**< Extended ID Filter Configuration, offset: 0x88 */
+ uint8_t RESERVED_5[4];
+ __IO uint32_t XIDAM; /**< Extended ID AND Mask, offset: 0x90 */
+ __I uint32_t HPMS; /**< High Priority Message Status, offset: 0x94 */
+ __IO uint32_t NDAT1; /**< New Data 1, offset: 0x98 */
+ __IO uint32_t NDAT2; /**< New Data 2, offset: 0x9C */
+ __IO uint32_t RXF0C; /**< Rx FIFO 0 Configuration, offset: 0xA0 */
+ __IO uint32_t RXF0S; /**< Rx FIFO 0 Status, offset: 0xA4 */
+ __IO uint32_t RXF0A; /**< Rx FIFO 0 Acknowledge, offset: 0xA8 */
+ __IO uint32_t RXBC; /**< Rx Buffer Configuration, offset: 0xAC */
+ __IO uint32_t RXF1C; /**< Rx FIFO 1 Configuration, offset: 0xB0 */
+ __I uint32_t RXF1S; /**< Rx FIFO 1 Status, offset: 0xB4 */
+ __IO uint32_t RXF1A; /**< Rx FIFO 1 Acknowledge, offset: 0xB8 */
+ __IO uint32_t RXESC; /**< Rx Buffer and FIFO Element Size Configuration, offset: 0xBC */
+ __IO uint32_t TXBC; /**< Tx Buffer Configuration, offset: 0xC0 */
+ __IO uint32_t TXFQS; /**< Tx FIFO/Queue Status, offset: 0xC4 */
+ __IO uint32_t TXESC; /**< Tx Buffer Element Size Configuration, offset: 0xC8 */
+ __IO uint32_t TXBRP; /**< Tx Buffer Request Pending, offset: 0xCC */
+ __IO uint32_t TXBAR; /**< Tx Buffer Add Request, offset: 0xD0 */
+ __IO uint32_t TXBCR; /**< Tx Buffer Cancellation Request, offset: 0xD4 */
+ __IO uint32_t TXBTO; /**< Tx Buffer Transmission Occurred, offset: 0xD8 */
+ __IO uint32_t TXBCF; /**< Tx Buffer Cancellation Finished, offset: 0xDC */
+ __IO uint32_t TXBTIE; /**< Tx Buffer Transmission Interrupt Enable, offset: 0xE0 */
+ __IO uint32_t TXBCIE; /**< Tx Buffer Cancellation Finished Interrupt Enable, offset: 0xE4 */
+ uint8_t RESERVED_6[8];
+ __IO uint32_t TXEFC; /**< Tx Event FIFO Configuration, offset: 0xF0 */
+ __I uint32_t TXEFS; /**< Tx Event FIFO Status, offset: 0xF4 */
+ __IO uint32_t TXEFA; /**< Tx Event FIFO Acknowledge, offset: 0xF8 */
+ uint8_t RESERVED_7[260];
+ __IO uint32_t MRBA; /**< CAN Message RAM Base Address, offset: 0x200 */
+ uint8_t RESERVED_8[508];
+ __IO uint32_t ETSCC; /**< External Timestamp Counter Configuration, offset: 0x400 */
+ uint8_t RESERVED_9[508];
+ __IO uint32_t ETSCV; /**< External Timestamp Counter Value, offset: 0x600 */
+} CAN_Type;
+
+/* ----------------------------------------------------------------------------
+ -- CAN Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CAN_Register_Masks CAN Register Masks
+ * @{
+ */
+
+/*! @name DBTP - Data Bit Timing Prescaler Register */
+#define CAN_DBTP_DSJW_MASK (0xFU)
+#define CAN_DBTP_DSJW_SHIFT (0U)
+#define CAN_DBTP_DSJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DSJW_SHIFT)) & CAN_DBTP_DSJW_MASK)
+#define CAN_DBTP_DTSEG2_MASK (0xF0U)
+#define CAN_DBTP_DTSEG2_SHIFT (4U)
+#define CAN_DBTP_DTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG2_SHIFT)) & CAN_DBTP_DTSEG2_MASK)
+#define CAN_DBTP_DTSEG1_MASK (0x1F00U)
+#define CAN_DBTP_DTSEG1_SHIFT (8U)
+#define CAN_DBTP_DTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DTSEG1_SHIFT)) & CAN_DBTP_DTSEG1_MASK)
+#define CAN_DBTP_DBRP_MASK (0x1F0000U)
+#define CAN_DBTP_DBRP_SHIFT (16U)
+#define CAN_DBTP_DBRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_DBRP_SHIFT)) & CAN_DBTP_DBRP_MASK)
+#define CAN_DBTP_TDC_MASK (0x800000U)
+#define CAN_DBTP_TDC_SHIFT (23U)
+#define CAN_DBTP_TDC(x) (((uint32_t)(((uint32_t)(x)) << CAN_DBTP_TDC_SHIFT)) & CAN_DBTP_TDC_MASK)
+
+/*! @name TEST - Test Register */
+#define CAN_TEST_LBCK_MASK (0x10U)
+#define CAN_TEST_LBCK_SHIFT (4U)
+#define CAN_TEST_LBCK(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_LBCK_SHIFT)) & CAN_TEST_LBCK_MASK)
+#define CAN_TEST_TX_MASK (0x60U)
+#define CAN_TEST_TX_SHIFT (5U)
+#define CAN_TEST_TX(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_TX_SHIFT)) & CAN_TEST_TX_MASK)
+#define CAN_TEST_RX_MASK (0x80U)
+#define CAN_TEST_RX_SHIFT (7U)
+#define CAN_TEST_RX(x) (((uint32_t)(((uint32_t)(x)) << CAN_TEST_RX_SHIFT)) & CAN_TEST_RX_MASK)
+
+/*! @name CCCR - CC Control Register */
+#define CAN_CCCR_INIT_MASK (0x1U)
+#define CAN_CCCR_INIT_SHIFT (0U)
+#define CAN_CCCR_INIT(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_INIT_SHIFT)) & CAN_CCCR_INIT_MASK)
+#define CAN_CCCR_CCE_MASK (0x2U)
+#define CAN_CCCR_CCE_SHIFT (1U)
+#define CAN_CCCR_CCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CCE_SHIFT)) & CAN_CCCR_CCE_MASK)
+#define CAN_CCCR_ASM_MASK (0x4U)
+#define CAN_CCCR_ASM_SHIFT (2U)
+#define CAN_CCCR_ASM(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_ASM_SHIFT)) & CAN_CCCR_ASM_MASK)
+#define CAN_CCCR_CSA_MASK (0x8U)
+#define CAN_CCCR_CSA_SHIFT (3U)
+#define CAN_CCCR_CSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSA_SHIFT)) & CAN_CCCR_CSA_MASK)
+#define CAN_CCCR_CSR_MASK (0x10U)
+#define CAN_CCCR_CSR_SHIFT (4U)
+#define CAN_CCCR_CSR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_CSR_SHIFT)) & CAN_CCCR_CSR_MASK)
+#define CAN_CCCR_MON_MASK (0x20U)
+#define CAN_CCCR_MON_SHIFT (5U)
+#define CAN_CCCR_MON(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_MON_SHIFT)) & CAN_CCCR_MON_MASK)
+#define CAN_CCCR_DAR_MASK (0x40U)
+#define CAN_CCCR_DAR_SHIFT (6U)
+#define CAN_CCCR_DAR(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_DAR_SHIFT)) & CAN_CCCR_DAR_MASK)
+#define CAN_CCCR_TEST_MASK (0x80U)
+#define CAN_CCCR_TEST_SHIFT (7U)
+#define CAN_CCCR_TEST(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TEST_SHIFT)) & CAN_CCCR_TEST_MASK)
+#define CAN_CCCR_FDOE_MASK (0x100U)
+#define CAN_CCCR_FDOE_SHIFT (8U)
+#define CAN_CCCR_FDOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_FDOE_SHIFT)) & CAN_CCCR_FDOE_MASK)
+#define CAN_CCCR_BRSE_MASK (0x200U)
+#define CAN_CCCR_BRSE_SHIFT (9U)
+#define CAN_CCCR_BRSE(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_BRSE_SHIFT)) & CAN_CCCR_BRSE_MASK)
+#define CAN_CCCR_PXHD_MASK (0x1000U)
+#define CAN_CCCR_PXHD_SHIFT (12U)
+#define CAN_CCCR_PXHD(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_PXHD_SHIFT)) & CAN_CCCR_PXHD_MASK)
+#define CAN_CCCR_EFBI_MASK (0x2000U)
+#define CAN_CCCR_EFBI_SHIFT (13U)
+#define CAN_CCCR_EFBI(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_EFBI_SHIFT)) & CAN_CCCR_EFBI_MASK)
+#define CAN_CCCR_TXP_MASK (0x4000U)
+#define CAN_CCCR_TXP_SHIFT (14U)
+#define CAN_CCCR_TXP(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_TXP_SHIFT)) & CAN_CCCR_TXP_MASK)
+#define CAN_CCCR_NISO_MASK (0x8000U)
+#define CAN_CCCR_NISO_SHIFT (15U)
+#define CAN_CCCR_NISO(x) (((uint32_t)(((uint32_t)(x)) << CAN_CCCR_NISO_SHIFT)) & CAN_CCCR_NISO_MASK)
+
+/*! @name NBTP - Nominal Bit Timing and Prescaler Register */
+#define CAN_NBTP_NTSEG2_MASK (0x7FU)
+#define CAN_NBTP_NTSEG2_SHIFT (0U)
+#define CAN_NBTP_NTSEG2(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG2_SHIFT)) & CAN_NBTP_NTSEG2_MASK)
+#define CAN_NBTP_NTSEG1_MASK (0xFF00U)
+#define CAN_NBTP_NTSEG1_SHIFT (8U)
+#define CAN_NBTP_NTSEG1(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NTSEG1_SHIFT)) & CAN_NBTP_NTSEG1_MASK)
+#define CAN_NBTP_NBRP_MASK (0x1FF0000U)
+#define CAN_NBTP_NBRP_SHIFT (16U)
+#define CAN_NBTP_NBRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NBRP_SHIFT)) & CAN_NBTP_NBRP_MASK)
+#define CAN_NBTP_NSJW_MASK (0xFE000000U)
+#define CAN_NBTP_NSJW_SHIFT (25U)
+#define CAN_NBTP_NSJW(x) (((uint32_t)(((uint32_t)(x)) << CAN_NBTP_NSJW_SHIFT)) & CAN_NBTP_NSJW_MASK)
+
+/*! @name TSCC - Timestamp Counter Configuration */
+#define CAN_TSCC_TSS_MASK (0x3U)
+#define CAN_TSCC_TSS_SHIFT (0U)
+#define CAN_TSCC_TSS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TSS_SHIFT)) & CAN_TSCC_TSS_MASK)
+#define CAN_TSCC_TCP_MASK (0xF0000U)
+#define CAN_TSCC_TCP_SHIFT (16U)
+#define CAN_TSCC_TCP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCC_TCP_SHIFT)) & CAN_TSCC_TCP_MASK)
+
+/*! @name TSCV - Timestamp Counter Value */
+#define CAN_TSCV_TSC_MASK (0xFFFFU)
+#define CAN_TSCV_TSC_SHIFT (0U)
+#define CAN_TSCV_TSC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TSCV_TSC_SHIFT)) & CAN_TSCV_TSC_MASK)
+
+/*! @name TOCC - Timeout Counter Configuration */
+#define CAN_TOCC_ETOC_MASK (0x1U)
+#define CAN_TOCC_ETOC_SHIFT (0U)
+#define CAN_TOCC_ETOC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_ETOC_SHIFT)) & CAN_TOCC_ETOC_MASK)
+#define CAN_TOCC_TOS_MASK (0x6U)
+#define CAN_TOCC_TOS_SHIFT (1U)
+#define CAN_TOCC_TOS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOS_SHIFT)) & CAN_TOCC_TOS_MASK)
+#define CAN_TOCC_TOP_MASK (0xFFFF0000U)
+#define CAN_TOCC_TOP_SHIFT (16U)
+#define CAN_TOCC_TOP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCC_TOP_SHIFT)) & CAN_TOCC_TOP_MASK)
+
+/*! @name TOCV - Timeout Counter Value */
+#define CAN_TOCV_TOC_MASK (0xFFFFU)
+#define CAN_TOCV_TOC_SHIFT (0U)
+#define CAN_TOCV_TOC(x) (((uint32_t)(((uint32_t)(x)) << CAN_TOCV_TOC_SHIFT)) & CAN_TOCV_TOC_MASK)
+
+/*! @name ECR - Error Counter Register */
+#define CAN_ECR_TEC_MASK (0xFFU)
+#define CAN_ECR_TEC_SHIFT (0U)
+#define CAN_ECR_TEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_TEC_SHIFT)) & CAN_ECR_TEC_MASK)
+#define CAN_ECR_REC_MASK (0x7F00U)
+#define CAN_ECR_REC_SHIFT (8U)
+#define CAN_ECR_REC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_REC_SHIFT)) & CAN_ECR_REC_MASK)
+#define CAN_ECR_RP_MASK (0x8000U)
+#define CAN_ECR_RP_SHIFT (15U)
+#define CAN_ECR_RP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_RP_SHIFT)) & CAN_ECR_RP_MASK)
+#define CAN_ECR_CEL_MASK (0xFF0000U)
+#define CAN_ECR_CEL_SHIFT (16U)
+#define CAN_ECR_CEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ECR_CEL_SHIFT)) & CAN_ECR_CEL_MASK)
+
+/*! @name PSR - Protocol Status Register */
+#define CAN_PSR_LEC_MASK (0x7U)
+#define CAN_PSR_LEC_SHIFT (0U)
+#define CAN_PSR_LEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_LEC_SHIFT)) & CAN_PSR_LEC_MASK)
+#define CAN_PSR_ACT_MASK (0x18U)
+#define CAN_PSR_ACT_SHIFT (3U)
+#define CAN_PSR_ACT(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_ACT_SHIFT)) & CAN_PSR_ACT_MASK)
+#define CAN_PSR_EP_MASK (0x20U)
+#define CAN_PSR_EP_SHIFT (5U)
+#define CAN_PSR_EP(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EP_SHIFT)) & CAN_PSR_EP_MASK)
+#define CAN_PSR_EW_MASK (0x40U)
+#define CAN_PSR_EW_SHIFT (6U)
+#define CAN_PSR_EW(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_EW_SHIFT)) & CAN_PSR_EW_MASK)
+#define CAN_PSR_BO_MASK (0x80U)
+#define CAN_PSR_BO_SHIFT (7U)
+#define CAN_PSR_BO(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_BO_SHIFT)) & CAN_PSR_BO_MASK)
+#define CAN_PSR_DLEC_MASK (0x700U)
+#define CAN_PSR_DLEC_SHIFT (8U)
+#define CAN_PSR_DLEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_DLEC_SHIFT)) & CAN_PSR_DLEC_MASK)
+#define CAN_PSR_RESI_MASK (0x800U)
+#define CAN_PSR_RESI_SHIFT (11U)
+#define CAN_PSR_RESI(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RESI_SHIFT)) & CAN_PSR_RESI_MASK)
+#define CAN_PSR_RBRS_MASK (0x1000U)
+#define CAN_PSR_RBRS_SHIFT (12U)
+#define CAN_PSR_RBRS(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RBRS_SHIFT)) & CAN_PSR_RBRS_MASK)
+#define CAN_PSR_RFDF_MASK (0x2000U)
+#define CAN_PSR_RFDF_SHIFT (13U)
+#define CAN_PSR_RFDF(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_RFDF_SHIFT)) & CAN_PSR_RFDF_MASK)
+#define CAN_PSR_PXE_MASK (0x4000U)
+#define CAN_PSR_PXE_SHIFT (14U)
+#define CAN_PSR_PXE(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_PXE_SHIFT)) & CAN_PSR_PXE_MASK)
+#define CAN_PSR_TDCV_MASK (0x7F0000U)
+#define CAN_PSR_TDCV_SHIFT (16U)
+#define CAN_PSR_TDCV(x) (((uint32_t)(((uint32_t)(x)) << CAN_PSR_TDCV_SHIFT)) & CAN_PSR_TDCV_MASK)
+
+/*! @name TDCR - Transmitter Delay Compensator Register */
+#define CAN_TDCR_TDCF_MASK (0x7FU)
+#define CAN_TDCR_TDCF_SHIFT (0U)
+#define CAN_TDCR_TDCF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCF_SHIFT)) & CAN_TDCR_TDCF_MASK)
+#define CAN_TDCR_TDCO_MASK (0x7F00U)
+#define CAN_TDCR_TDCO_SHIFT (8U)
+#define CAN_TDCR_TDCO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TDCR_TDCO_SHIFT)) & CAN_TDCR_TDCO_MASK)
+
+/*! @name IR - Interrupt Register */
+#define CAN_IR_RF0N_MASK (0x1U)
+#define CAN_IR_RF0N_SHIFT (0U)
+#define CAN_IR_RF0N(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0N_SHIFT)) & CAN_IR_RF0N_MASK)
+#define CAN_IR_RF0W_MASK (0x2U)
+#define CAN_IR_RF0W_SHIFT (1U)
+#define CAN_IR_RF0W(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0W_SHIFT)) & CAN_IR_RF0W_MASK)
+#define CAN_IR_RF0F_MASK (0x4U)
+#define CAN_IR_RF0F_SHIFT (2U)
+#define CAN_IR_RF0F(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0F_SHIFT)) & CAN_IR_RF0F_MASK)
+#define CAN_IR_RF0L_MASK (0x8U)
+#define CAN_IR_RF0L_SHIFT (3U)
+#define CAN_IR_RF0L(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF0L_SHIFT)) & CAN_IR_RF0L_MASK)
+#define CAN_IR_RF1N_MASK (0x10U)
+#define CAN_IR_RF1N_SHIFT (4U)
+#define CAN_IR_RF1N(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1N_SHIFT)) & CAN_IR_RF1N_MASK)
+#define CAN_IR_RF1W_MASK (0x20U)
+#define CAN_IR_RF1W_SHIFT (5U)
+#define CAN_IR_RF1W(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1W_SHIFT)) & CAN_IR_RF1W_MASK)
+#define CAN_IR_RF1F_MASK (0x40U)
+#define CAN_IR_RF1F_SHIFT (6U)
+#define CAN_IR_RF1F(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1F_SHIFT)) & CAN_IR_RF1F_MASK)
+#define CAN_IR_RF1L_MASK (0x80U)
+#define CAN_IR_RF1L_SHIFT (7U)
+#define CAN_IR_RF1L(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_RF1L_SHIFT)) & CAN_IR_RF1L_MASK)
+#define CAN_IR_HPM_MASK (0x100U)
+#define CAN_IR_HPM_SHIFT (8U)
+#define CAN_IR_HPM(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_HPM_SHIFT)) & CAN_IR_HPM_MASK)
+#define CAN_IR_TC_MASK (0x200U)
+#define CAN_IR_TC_SHIFT (9U)
+#define CAN_IR_TC(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TC_SHIFT)) & CAN_IR_TC_MASK)
+#define CAN_IR_TCF_MASK (0x400U)
+#define CAN_IR_TCF_SHIFT (10U)
+#define CAN_IR_TCF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TCF_SHIFT)) & CAN_IR_TCF_MASK)
+#define CAN_IR_TFE_MASK (0x800U)
+#define CAN_IR_TFE_SHIFT (11U)
+#define CAN_IR_TFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TFE_SHIFT)) & CAN_IR_TFE_MASK)
+#define CAN_IR_TEFN_MASK (0x1000U)
+#define CAN_IR_TEFN_SHIFT (12U)
+#define CAN_IR_TEFN(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFN_SHIFT)) & CAN_IR_TEFN_MASK)
+#define CAN_IR_TEFW_MASK (0x2000U)
+#define CAN_IR_TEFW_SHIFT (13U)
+#define CAN_IR_TEFW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFW_SHIFT)) & CAN_IR_TEFW_MASK)
+#define CAN_IR_TEFF_MASK (0x4000U)
+#define CAN_IR_TEFF_SHIFT (14U)
+#define CAN_IR_TEFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFF_SHIFT)) & CAN_IR_TEFF_MASK)
+#define CAN_IR_TEFL_MASK (0x8000U)
+#define CAN_IR_TEFL_SHIFT (15U)
+#define CAN_IR_TEFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TEFL_SHIFT)) & CAN_IR_TEFL_MASK)
+#define CAN_IR_TSW_MASK (0x10000U)
+#define CAN_IR_TSW_SHIFT (16U)
+#define CAN_IR_TSW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TSW_SHIFT)) & CAN_IR_TSW_MASK)
+#define CAN_IR_MRAF_MASK (0x20000U)
+#define CAN_IR_MRAF_SHIFT (17U)
+#define CAN_IR_MRAF(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_MRAF_SHIFT)) & CAN_IR_MRAF_MASK)
+#define CAN_IR_TOO_MASK (0x40000U)
+#define CAN_IR_TOO_SHIFT (18U)
+#define CAN_IR_TOO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_TOO_SHIFT)) & CAN_IR_TOO_MASK)
+#define CAN_IR_DRX_MASK (0x80000U)
+#define CAN_IR_DRX_SHIFT (19U)
+#define CAN_IR_DRX(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_DRX_SHIFT)) & CAN_IR_DRX_MASK)
+#define CAN_IR_BEC_MASK (0x100000U)
+#define CAN_IR_BEC_SHIFT (20U)
+#define CAN_IR_BEC(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEC_SHIFT)) & CAN_IR_BEC_MASK)
+#define CAN_IR_BEU_MASK (0x200000U)
+#define CAN_IR_BEU_SHIFT (21U)
+#define CAN_IR_BEU(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BEU_SHIFT)) & CAN_IR_BEU_MASK)
+#define CAN_IR_ELO_MASK (0x400000U)
+#define CAN_IR_ELO_SHIFT (22U)
+#define CAN_IR_ELO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_ELO_SHIFT)) & CAN_IR_ELO_MASK)
+#define CAN_IR_EP_MASK (0x800000U)
+#define CAN_IR_EP_SHIFT (23U)
+#define CAN_IR_EP(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_EP_SHIFT)) & CAN_IR_EP_MASK)
+#define CAN_IR_EW_MASK (0x1000000U)
+#define CAN_IR_EW_SHIFT (24U)
+#define CAN_IR_EW(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_EW_SHIFT)) & CAN_IR_EW_MASK)
+#define CAN_IR_BO_MASK (0x2000000U)
+#define CAN_IR_BO_SHIFT (25U)
+#define CAN_IR_BO(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_BO_SHIFT)) & CAN_IR_BO_MASK)
+#define CAN_IR_WDI_MASK (0x4000000U)
+#define CAN_IR_WDI_SHIFT (26U)
+#define CAN_IR_WDI(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_WDI_SHIFT)) & CAN_IR_WDI_MASK)
+#define CAN_IR_PEA_MASK (0x8000000U)
+#define CAN_IR_PEA_SHIFT (27U)
+#define CAN_IR_PEA(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_PEA_SHIFT)) & CAN_IR_PEA_MASK)
+#define CAN_IR_PED_MASK (0x10000000U)
+#define CAN_IR_PED_SHIFT (28U)
+#define CAN_IR_PED(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_PED_SHIFT)) & CAN_IR_PED_MASK)
+#define CAN_IR_ARA_MASK (0x20000000U)
+#define CAN_IR_ARA_SHIFT (29U)
+#define CAN_IR_ARA(x) (((uint32_t)(((uint32_t)(x)) << CAN_IR_ARA_SHIFT)) & CAN_IR_ARA_MASK)
+
+/*! @name IE - Interrupt Enable */
+#define CAN_IE_RF0NE_MASK (0x1U)
+#define CAN_IE_RF0NE_SHIFT (0U)
+#define CAN_IE_RF0NE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0NE_SHIFT)) & CAN_IE_RF0NE_MASK)
+#define CAN_IE_RF0WE_MASK (0x2U)
+#define CAN_IE_RF0WE_SHIFT (1U)
+#define CAN_IE_RF0WE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0WE_SHIFT)) & CAN_IE_RF0WE_MASK)
+#define CAN_IE_RF0FE_MASK (0x4U)
+#define CAN_IE_RF0FE_SHIFT (2U)
+#define CAN_IE_RF0FE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0FE_SHIFT)) & CAN_IE_RF0FE_MASK)
+#define CAN_IE_RF0LE_MASK (0x8U)
+#define CAN_IE_RF0LE_SHIFT (3U)
+#define CAN_IE_RF0LE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF0LE_SHIFT)) & CAN_IE_RF0LE_MASK)
+#define CAN_IE_RF1NE_MASK (0x10U)
+#define CAN_IE_RF1NE_SHIFT (4U)
+#define CAN_IE_RF1NE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1NE_SHIFT)) & CAN_IE_RF1NE_MASK)
+#define CAN_IE_RF1WE_MASK (0x20U)
+#define CAN_IE_RF1WE_SHIFT (5U)
+#define CAN_IE_RF1WE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1WE_SHIFT)) & CAN_IE_RF1WE_MASK)
+#define CAN_IE_RF1FE_MASK (0x40U)
+#define CAN_IE_RF1FE_SHIFT (6U)
+#define CAN_IE_RF1FE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1FE_SHIFT)) & CAN_IE_RF1FE_MASK)
+#define CAN_IE_RF1LE_MASK (0x80U)
+#define CAN_IE_RF1LE_SHIFT (7U)
+#define CAN_IE_RF1LE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_RF1LE_SHIFT)) & CAN_IE_RF1LE_MASK)
+#define CAN_IE_HPME_MASK (0x100U)
+#define CAN_IE_HPME_SHIFT (8U)
+#define CAN_IE_HPME(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_HPME_SHIFT)) & CAN_IE_HPME_MASK)
+#define CAN_IE_TCE_MASK (0x200U)
+#define CAN_IE_TCE_SHIFT (9U)
+#define CAN_IE_TCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCE_SHIFT)) & CAN_IE_TCE_MASK)
+#define CAN_IE_TCFE_MASK (0x400U)
+#define CAN_IE_TCFE_SHIFT (10U)
+#define CAN_IE_TCFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TCFE_SHIFT)) & CAN_IE_TCFE_MASK)
+#define CAN_IE_TFEE_MASK (0x800U)
+#define CAN_IE_TFEE_SHIFT (11U)
+#define CAN_IE_TFEE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TFEE_SHIFT)) & CAN_IE_TFEE_MASK)
+#define CAN_IE_TEFNE_MASK (0x1000U)
+#define CAN_IE_TEFNE_SHIFT (12U)
+#define CAN_IE_TEFNE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFNE_SHIFT)) & CAN_IE_TEFNE_MASK)
+#define CAN_IE_TEFWE_MASK (0x2000U)
+#define CAN_IE_TEFWE_SHIFT (13U)
+#define CAN_IE_TEFWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFWE_SHIFT)) & CAN_IE_TEFWE_MASK)
+#define CAN_IE_TEFFE_MASK (0x4000U)
+#define CAN_IE_TEFFE_SHIFT (14U)
+#define CAN_IE_TEFFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFFE_SHIFT)) & CAN_IE_TEFFE_MASK)
+#define CAN_IE_TEFLE_MASK (0x8000U)
+#define CAN_IE_TEFLE_SHIFT (15U)
+#define CAN_IE_TEFLE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TEFLE_SHIFT)) & CAN_IE_TEFLE_MASK)
+#define CAN_IE_TSWE_MASK (0x10000U)
+#define CAN_IE_TSWE_SHIFT (16U)
+#define CAN_IE_TSWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TSWE_SHIFT)) & CAN_IE_TSWE_MASK)
+#define CAN_IE_MRAFE_MASK (0x20000U)
+#define CAN_IE_MRAFE_SHIFT (17U)
+#define CAN_IE_MRAFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_MRAFE_SHIFT)) & CAN_IE_MRAFE_MASK)
+#define CAN_IE_TOOE_MASK (0x40000U)
+#define CAN_IE_TOOE_SHIFT (18U)
+#define CAN_IE_TOOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_TOOE_SHIFT)) & CAN_IE_TOOE_MASK)
+#define CAN_IE_DRXE_MASK (0x80000U)
+#define CAN_IE_DRXE_SHIFT (19U)
+#define CAN_IE_DRXE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_DRXE_SHIFT)) & CAN_IE_DRXE_MASK)
+#define CAN_IE_BECE_MASK (0x100000U)
+#define CAN_IE_BECE_SHIFT (20U)
+#define CAN_IE_BECE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BECE_SHIFT)) & CAN_IE_BECE_MASK)
+#define CAN_IE_BEUE_MASK (0x200000U)
+#define CAN_IE_BEUE_SHIFT (21U)
+#define CAN_IE_BEUE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BEUE_SHIFT)) & CAN_IE_BEUE_MASK)
+#define CAN_IE_ELOE_MASK (0x400000U)
+#define CAN_IE_ELOE_SHIFT (22U)
+#define CAN_IE_ELOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_ELOE_SHIFT)) & CAN_IE_ELOE_MASK)
+#define CAN_IE_EPE_MASK (0x800000U)
+#define CAN_IE_EPE_SHIFT (23U)
+#define CAN_IE_EPE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_EPE_SHIFT)) & CAN_IE_EPE_MASK)
+#define CAN_IE_EWE_MASK (0x1000000U)
+#define CAN_IE_EWE_SHIFT (24U)
+#define CAN_IE_EWE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_EWE_SHIFT)) & CAN_IE_EWE_MASK)
+#define CAN_IE_BOE_MASK (0x2000000U)
+#define CAN_IE_BOE_SHIFT (25U)
+#define CAN_IE_BOE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_BOE_SHIFT)) & CAN_IE_BOE_MASK)
+#define CAN_IE_WDIE_MASK (0x4000000U)
+#define CAN_IE_WDIE_SHIFT (26U)
+#define CAN_IE_WDIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_WDIE_SHIFT)) & CAN_IE_WDIE_MASK)
+#define CAN_IE_PEAE_MASK (0x8000000U)
+#define CAN_IE_PEAE_SHIFT (27U)
+#define CAN_IE_PEAE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEAE_SHIFT)) & CAN_IE_PEAE_MASK)
+#define CAN_IE_PEDE_MASK (0x10000000U)
+#define CAN_IE_PEDE_SHIFT (28U)
+#define CAN_IE_PEDE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_PEDE_SHIFT)) & CAN_IE_PEDE_MASK)
+#define CAN_IE_ARAE_MASK (0x20000000U)
+#define CAN_IE_ARAE_SHIFT (29U)
+#define CAN_IE_ARAE(x) (((uint32_t)(((uint32_t)(x)) << CAN_IE_ARAE_SHIFT)) & CAN_IE_ARAE_MASK)
+
+/*! @name ILS - Interrupt Line Select */
+#define CAN_ILS_RF0NL_MASK (0x1U)
+#define CAN_ILS_RF0NL_SHIFT (0U)
+#define CAN_ILS_RF0NL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0NL_SHIFT)) & CAN_ILS_RF0NL_MASK)
+#define CAN_ILS_RF0WL_MASK (0x2U)
+#define CAN_ILS_RF0WL_SHIFT (1U)
+#define CAN_ILS_RF0WL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0WL_SHIFT)) & CAN_ILS_RF0WL_MASK)
+#define CAN_ILS_RF0FL_MASK (0x4U)
+#define CAN_ILS_RF0FL_SHIFT (2U)
+#define CAN_ILS_RF0FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0FL_SHIFT)) & CAN_ILS_RF0FL_MASK)
+#define CAN_ILS_RF0LL_MASK (0x8U)
+#define CAN_ILS_RF0LL_SHIFT (3U)
+#define CAN_ILS_RF0LL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF0LL_SHIFT)) & CAN_ILS_RF0LL_MASK)
+#define CAN_ILS_RF1NL_MASK (0x10U)
+#define CAN_ILS_RF1NL_SHIFT (4U)
+#define CAN_ILS_RF1NL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1NL_SHIFT)) & CAN_ILS_RF1NL_MASK)
+#define CAN_ILS_RF1WL_MASK (0x20U)
+#define CAN_ILS_RF1WL_SHIFT (5U)
+#define CAN_ILS_RF1WL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1WL_SHIFT)) & CAN_ILS_RF1WL_MASK)
+#define CAN_ILS_RF1FL_MASK (0x40U)
+#define CAN_ILS_RF1FL_SHIFT (6U)
+#define CAN_ILS_RF1FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1FL_SHIFT)) & CAN_ILS_RF1FL_MASK)
+#define CAN_ILS_RF1LL_MASK (0x80U)
+#define CAN_ILS_RF1LL_SHIFT (7U)
+#define CAN_ILS_RF1LL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_RF1LL_SHIFT)) & CAN_ILS_RF1LL_MASK)
+#define CAN_ILS_HPML_MASK (0x100U)
+#define CAN_ILS_HPML_SHIFT (8U)
+#define CAN_ILS_HPML(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_HPML_SHIFT)) & CAN_ILS_HPML_MASK)
+#define CAN_ILS_TCL_MASK (0x200U)
+#define CAN_ILS_TCL_SHIFT (9U)
+#define CAN_ILS_TCL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCL_SHIFT)) & CAN_ILS_TCL_MASK)
+#define CAN_ILS_TCFL_MASK (0x400U)
+#define CAN_ILS_TCFL_SHIFT (10U)
+#define CAN_ILS_TCFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TCFL_SHIFT)) & CAN_ILS_TCFL_MASK)
+#define CAN_ILS_TFEL_MASK (0x800U)
+#define CAN_ILS_TFEL_SHIFT (11U)
+#define CAN_ILS_TFEL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TFEL_SHIFT)) & CAN_ILS_TFEL_MASK)
+#define CAN_ILS_TEFNL_MASK (0x1000U)
+#define CAN_ILS_TEFNL_SHIFT (12U)
+#define CAN_ILS_TEFNL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFNL_SHIFT)) & CAN_ILS_TEFNL_MASK)
+#define CAN_ILS_TEFWL_MASK (0x2000U)
+#define CAN_ILS_TEFWL_SHIFT (13U)
+#define CAN_ILS_TEFWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFWL_SHIFT)) & CAN_ILS_TEFWL_MASK)
+#define CAN_ILS_TEFFL_MASK (0x4000U)
+#define CAN_ILS_TEFFL_SHIFT (14U)
+#define CAN_ILS_TEFFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFFL_SHIFT)) & CAN_ILS_TEFFL_MASK)
+#define CAN_ILS_TEFLL_MASK (0x8000U)
+#define CAN_ILS_TEFLL_SHIFT (15U)
+#define CAN_ILS_TEFLL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TEFLL_SHIFT)) & CAN_ILS_TEFLL_MASK)
+#define CAN_ILS_TSWL_MASK (0x10000U)
+#define CAN_ILS_TSWL_SHIFT (16U)
+#define CAN_ILS_TSWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TSWL_SHIFT)) & CAN_ILS_TSWL_MASK)
+#define CAN_ILS_MRAFL_MASK (0x20000U)
+#define CAN_ILS_MRAFL_SHIFT (17U)
+#define CAN_ILS_MRAFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_MRAFL_SHIFT)) & CAN_ILS_MRAFL_MASK)
+#define CAN_ILS_TOOL_MASK (0x40000U)
+#define CAN_ILS_TOOL_SHIFT (18U)
+#define CAN_ILS_TOOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_TOOL_SHIFT)) & CAN_ILS_TOOL_MASK)
+#define CAN_ILS_DRXL_MASK (0x80000U)
+#define CAN_ILS_DRXL_SHIFT (19U)
+#define CAN_ILS_DRXL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_DRXL_SHIFT)) & CAN_ILS_DRXL_MASK)
+#define CAN_ILS_BECL_MASK (0x100000U)
+#define CAN_ILS_BECL_SHIFT (20U)
+#define CAN_ILS_BECL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BECL_SHIFT)) & CAN_ILS_BECL_MASK)
+#define CAN_ILS_BEUL_MASK (0x200000U)
+#define CAN_ILS_BEUL_SHIFT (21U)
+#define CAN_ILS_BEUL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BEUL_SHIFT)) & CAN_ILS_BEUL_MASK)
+#define CAN_ILS_ELOL_MASK (0x400000U)
+#define CAN_ILS_ELOL_SHIFT (22U)
+#define CAN_ILS_ELOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ELOL_SHIFT)) & CAN_ILS_ELOL_MASK)
+#define CAN_ILS_EPL_MASK (0x800000U)
+#define CAN_ILS_EPL_SHIFT (23U)
+#define CAN_ILS_EPL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EPL_SHIFT)) & CAN_ILS_EPL_MASK)
+#define CAN_ILS_EWL_MASK (0x1000000U)
+#define CAN_ILS_EWL_SHIFT (24U)
+#define CAN_ILS_EWL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_EWL_SHIFT)) & CAN_ILS_EWL_MASK)
+#define CAN_ILS_BOL_MASK (0x2000000U)
+#define CAN_ILS_BOL_SHIFT (25U)
+#define CAN_ILS_BOL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_BOL_SHIFT)) & CAN_ILS_BOL_MASK)
+#define CAN_ILS_WDIL_MASK (0x4000000U)
+#define CAN_ILS_WDIL_SHIFT (26U)
+#define CAN_ILS_WDIL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_WDIL_SHIFT)) & CAN_ILS_WDIL_MASK)
+#define CAN_ILS_PEAL_MASK (0x8000000U)
+#define CAN_ILS_PEAL_SHIFT (27U)
+#define CAN_ILS_PEAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEAL_SHIFT)) & CAN_ILS_PEAL_MASK)
+#define CAN_ILS_PEDL_MASK (0x10000000U)
+#define CAN_ILS_PEDL_SHIFT (28U)
+#define CAN_ILS_PEDL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_PEDL_SHIFT)) & CAN_ILS_PEDL_MASK)
+#define CAN_ILS_ARAL_MASK (0x20000000U)
+#define CAN_ILS_ARAL_SHIFT (29U)
+#define CAN_ILS_ARAL(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILS_ARAL_SHIFT)) & CAN_ILS_ARAL_MASK)
+
+/*! @name ILE - Interrupt Line Enable */
+#define CAN_ILE_EINT0_MASK (0x1U)
+#define CAN_ILE_EINT0_SHIFT (0U)
+#define CAN_ILE_EINT0(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT0_SHIFT)) & CAN_ILE_EINT0_MASK)
+#define CAN_ILE_EINT1_MASK (0x2U)
+#define CAN_ILE_EINT1_SHIFT (1U)
+#define CAN_ILE_EINT1(x) (((uint32_t)(((uint32_t)(x)) << CAN_ILE_EINT1_SHIFT)) & CAN_ILE_EINT1_MASK)
+
+/*! @name GFC - Global Filter Configuration */
+#define CAN_GFC_RRFE_MASK (0x1U)
+#define CAN_GFC_RRFE_SHIFT (0U)
+#define CAN_GFC_RRFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFE_SHIFT)) & CAN_GFC_RRFE_MASK)
+#define CAN_GFC_RRFS_MASK (0x2U)
+#define CAN_GFC_RRFS_SHIFT (1U)
+#define CAN_GFC_RRFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_RRFS_SHIFT)) & CAN_GFC_RRFS_MASK)
+#define CAN_GFC_ANFE_MASK (0xCU)
+#define CAN_GFC_ANFE_SHIFT (2U)
+#define CAN_GFC_ANFE(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFE_SHIFT)) & CAN_GFC_ANFE_MASK)
+#define CAN_GFC_ANFS_MASK (0x30U)
+#define CAN_GFC_ANFS_SHIFT (4U)
+#define CAN_GFC_ANFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_GFC_ANFS_SHIFT)) & CAN_GFC_ANFS_MASK)
+
+/*! @name SIDFC - Standard ID Filter Configuration */
+#define CAN_SIDFC_FLSSA_MASK (0xFFFCU)
+#define CAN_SIDFC_FLSSA_SHIFT (2U)
+#define CAN_SIDFC_FLSSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_FLSSA_SHIFT)) & CAN_SIDFC_FLSSA_MASK)
+#define CAN_SIDFC_LSS_MASK (0xFF0000U)
+#define CAN_SIDFC_LSS_SHIFT (16U)
+#define CAN_SIDFC_LSS(x) (((uint32_t)(((uint32_t)(x)) << CAN_SIDFC_LSS_SHIFT)) & CAN_SIDFC_LSS_MASK)
+
+/*! @name XIDFC - Extended ID Filter Configuration */
+#define CAN_XIDFC_FLESA_MASK (0xFFFCU)
+#define CAN_XIDFC_FLESA_SHIFT (2U)
+#define CAN_XIDFC_FLESA(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_FLESA_SHIFT)) & CAN_XIDFC_FLESA_MASK)
+#define CAN_XIDFC_LSE_MASK (0xFF0000U)
+#define CAN_XIDFC_LSE_SHIFT (16U)
+#define CAN_XIDFC_LSE(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDFC_LSE_SHIFT)) & CAN_XIDFC_LSE_MASK)
+
+/*! @name XIDAM - Extended ID AND Mask */
+#define CAN_XIDAM_EIDM_MASK (0x1FFFFFFFU)
+#define CAN_XIDAM_EIDM_SHIFT (0U)
+#define CAN_XIDAM_EIDM(x) (((uint32_t)(((uint32_t)(x)) << CAN_XIDAM_EIDM_SHIFT)) & CAN_XIDAM_EIDM_MASK)
+
+/*! @name HPMS - High Priority Message Status */
+#define CAN_HPMS_BIDX_MASK (0x3FU)
+#define CAN_HPMS_BIDX_SHIFT (0U)
+#define CAN_HPMS_BIDX(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_BIDX_SHIFT)) & CAN_HPMS_BIDX_MASK)
+#define CAN_HPMS_MSI_MASK (0xC0U)
+#define CAN_HPMS_MSI_SHIFT (6U)
+#define CAN_HPMS_MSI(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_MSI_SHIFT)) & CAN_HPMS_MSI_MASK)
+#define CAN_HPMS_FIDX_MASK (0x7F00U)
+#define CAN_HPMS_FIDX_SHIFT (8U)
+#define CAN_HPMS_FIDX(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FIDX_SHIFT)) & CAN_HPMS_FIDX_MASK)
+#define CAN_HPMS_FLST_MASK (0x8000U)
+#define CAN_HPMS_FLST_SHIFT (15U)
+#define CAN_HPMS_FLST(x) (((uint32_t)(((uint32_t)(x)) << CAN_HPMS_FLST_SHIFT)) & CAN_HPMS_FLST_MASK)
+
+/*! @name NDAT1 - New Data 1 */
+#define CAN_NDAT1_ND_MASK (0xFFFFFFFFU)
+#define CAN_NDAT1_ND_SHIFT (0U)
+#define CAN_NDAT1_ND(x) (((uint32_t)(((uint32_t)(x)) << CAN_NDAT1_ND_SHIFT)) & CAN_NDAT1_ND_MASK)
+
+/*! @name NDAT2 - New Data 2 */
+#define CAN_NDAT2_ND_MASK (0xFFFFFFFFU)
+#define CAN_NDAT2_ND_SHIFT (0U)
+#define CAN_NDAT2_ND(x) (((uint32_t)(((uint32_t)(x)) << CAN_NDAT2_ND_SHIFT)) & CAN_NDAT2_ND_MASK)
+
+/*! @name RXF0C - Rx FIFO 0 Configuration */
+#define CAN_RXF0C_F0SA_MASK (0xFFFCU)
+#define CAN_RXF0C_F0SA_SHIFT (2U)
+#define CAN_RXF0C_F0SA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0SA_SHIFT)) & CAN_RXF0C_F0SA_MASK)
+#define CAN_RXF0C_F0S_MASK (0x7F0000U)
+#define CAN_RXF0C_F0S_SHIFT (16U)
+#define CAN_RXF0C_F0S(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0S_SHIFT)) & CAN_RXF0C_F0S_MASK)
+#define CAN_RXF0C_F0WM_MASK (0x7F000000U)
+#define CAN_RXF0C_F0WM_SHIFT (24U)
+#define CAN_RXF0C_F0WM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0WM_SHIFT)) & CAN_RXF0C_F0WM_MASK)
+#define CAN_RXF0C_F0OM_MASK (0x80000000U)
+#define CAN_RXF0C_F0OM_SHIFT (31U)
+#define CAN_RXF0C_F0OM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0C_F0OM_SHIFT)) & CAN_RXF0C_F0OM_MASK)
+
+/*! @name RXF0S - Rx FIFO 0 Status */
+#define CAN_RXF0S_F0FL_MASK (0x7FU)
+#define CAN_RXF0S_F0FL_SHIFT (0U)
+#define CAN_RXF0S_F0FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0FL_SHIFT)) & CAN_RXF0S_F0FL_MASK)
+#define CAN_RXF0S_F0GI_MASK (0x3F00U)
+#define CAN_RXF0S_F0GI_SHIFT (8U)
+#define CAN_RXF0S_F0GI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0GI_SHIFT)) & CAN_RXF0S_F0GI_MASK)
+#define CAN_RXF0S_F0PI_MASK (0x3F0000U)
+#define CAN_RXF0S_F0PI_SHIFT (16U)
+#define CAN_RXF0S_F0PI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0PI_SHIFT)) & CAN_RXF0S_F0PI_MASK)
+#define CAN_RXF0S_F0F_MASK (0x1000000U)
+#define CAN_RXF0S_F0F_SHIFT (24U)
+#define CAN_RXF0S_F0F(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_F0F_SHIFT)) & CAN_RXF0S_F0F_MASK)
+#define CAN_RXF0S_RF0L_MASK (0x2000000U)
+#define CAN_RXF0S_RF0L_SHIFT (25U)
+#define CAN_RXF0S_RF0L(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0S_RF0L_SHIFT)) & CAN_RXF0S_RF0L_MASK)
+
+/*! @name RXF0A - Rx FIFO 0 Acknowledge */
+#define CAN_RXF0A_F0AI_MASK (0x3FU)
+#define CAN_RXF0A_F0AI_SHIFT (0U)
+#define CAN_RXF0A_F0AI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF0A_F0AI_SHIFT)) & CAN_RXF0A_F0AI_MASK)
+
+/*! @name RXBC - Rx Buffer Configuration */
+#define CAN_RXBC_RBSA_MASK (0xFFFCU)
+#define CAN_RXBC_RBSA_SHIFT (2U)
+#define CAN_RXBC_RBSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXBC_RBSA_SHIFT)) & CAN_RXBC_RBSA_MASK)
+
+/*! @name RXF1C - Rx FIFO 1 Configuration */
+#define CAN_RXF1C_F1SA_MASK (0xFFFCU)
+#define CAN_RXF1C_F1SA_SHIFT (2U)
+#define CAN_RXF1C_F1SA(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1SA_SHIFT)) & CAN_RXF1C_F1SA_MASK)
+#define CAN_RXF1C_F1S_MASK (0x7F0000U)
+#define CAN_RXF1C_F1S_SHIFT (16U)
+#define CAN_RXF1C_F1S(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1S_SHIFT)) & CAN_RXF1C_F1S_MASK)
+#define CAN_RXF1C_F1WM_MASK (0x7F000000U)
+#define CAN_RXF1C_F1WM_SHIFT (24U)
+#define CAN_RXF1C_F1WM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1WM_SHIFT)) & CAN_RXF1C_F1WM_MASK)
+#define CAN_RXF1C_F1OM_MASK (0x80000000U)
+#define CAN_RXF1C_F1OM_SHIFT (31U)
+#define CAN_RXF1C_F1OM(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1C_F1OM_SHIFT)) & CAN_RXF1C_F1OM_MASK)
+
+/*! @name RXF1S - Rx FIFO 1 Status */
+#define CAN_RXF1S_F1FL_MASK (0x7FU)
+#define CAN_RXF1S_F1FL_SHIFT (0U)
+#define CAN_RXF1S_F1FL(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1FL_SHIFT)) & CAN_RXF1S_F1FL_MASK)
+#define CAN_RXF1S_F1GI_MASK (0x3F00U)
+#define CAN_RXF1S_F1GI_SHIFT (8U)
+#define CAN_RXF1S_F1GI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1GI_SHIFT)) & CAN_RXF1S_F1GI_MASK)
+#define CAN_RXF1S_F1PI_MASK (0x3F0000U)
+#define CAN_RXF1S_F1PI_SHIFT (16U)
+#define CAN_RXF1S_F1PI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1PI_SHIFT)) & CAN_RXF1S_F1PI_MASK)
+#define CAN_RXF1S_F1F_MASK (0x1000000U)
+#define CAN_RXF1S_F1F_SHIFT (24U)
+#define CAN_RXF1S_F1F(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_F1F_SHIFT)) & CAN_RXF1S_F1F_MASK)
+#define CAN_RXF1S_RF1L_MASK (0x2000000U)
+#define CAN_RXF1S_RF1L_SHIFT (25U)
+#define CAN_RXF1S_RF1L(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1S_RF1L_SHIFT)) & CAN_RXF1S_RF1L_MASK)
+
+/*! @name RXF1A - Rx FIFO 1 Acknowledge */
+#define CAN_RXF1A_F1AI_MASK (0x3FU)
+#define CAN_RXF1A_F1AI_SHIFT (0U)
+#define CAN_RXF1A_F1AI(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXF1A_F1AI_SHIFT)) & CAN_RXF1A_F1AI_MASK)
+
+/*! @name RXESC - Rx Buffer and FIFO Element Size Configuration */
+#define CAN_RXESC_F0DS_MASK (0x7U)
+#define CAN_RXESC_F0DS_SHIFT (0U)
+#define CAN_RXESC_F0DS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F0DS_SHIFT)) & CAN_RXESC_F0DS_MASK)
+#define CAN_RXESC_F1DS_MASK (0x70U)
+#define CAN_RXESC_F1DS_SHIFT (4U)
+#define CAN_RXESC_F1DS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_F1DS_SHIFT)) & CAN_RXESC_F1DS_MASK)
+#define CAN_RXESC_RBDS_MASK (0x700U)
+#define CAN_RXESC_RBDS_SHIFT (8U)
+#define CAN_RXESC_RBDS(x) (((uint32_t)(((uint32_t)(x)) << CAN_RXESC_RBDS_SHIFT)) & CAN_RXESC_RBDS_MASK)
+
+/*! @name TXBC - Tx Buffer Configuration */
+#define CAN_TXBC_TBSA_MASK (0xFFFCU)
+#define CAN_TXBC_TBSA_SHIFT (2U)
+#define CAN_TXBC_TBSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TBSA_SHIFT)) & CAN_TXBC_TBSA_MASK)
+#define CAN_TXBC_NDTB_MASK (0x3F0000U)
+#define CAN_TXBC_NDTB_SHIFT (16U)
+#define CAN_TXBC_NDTB(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_NDTB_SHIFT)) & CAN_TXBC_NDTB_MASK)
+#define CAN_TXBC_TFQS_MASK (0x3F000000U)
+#define CAN_TXBC_TFQS_SHIFT (24U)
+#define CAN_TXBC_TFQS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQS_SHIFT)) & CAN_TXBC_TFQS_MASK)
+#define CAN_TXBC_TFQM_MASK (0x40000000U)
+#define CAN_TXBC_TFQM_SHIFT (30U)
+#define CAN_TXBC_TFQM(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBC_TFQM_SHIFT)) & CAN_TXBC_TFQM_MASK)
+
+/*! @name TXFQS - Tx FIFO/Queue Status */
+#define CAN_TXFQS_TFGI_MASK (0x1F00U)
+#define CAN_TXFQS_TFGI_SHIFT (8U)
+#define CAN_TXFQS_TFGI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFGI_SHIFT)) & CAN_TXFQS_TFGI_MASK)
+#define CAN_TXFQS_TFQPI_MASK (0x1F0000U)
+#define CAN_TXFQS_TFQPI_SHIFT (16U)
+#define CAN_TXFQS_TFQPI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQPI_SHIFT)) & CAN_TXFQS_TFQPI_MASK)
+#define CAN_TXFQS_TFQF_MASK (0x200000U)
+#define CAN_TXFQS_TFQF_SHIFT (21U)
+#define CAN_TXFQS_TFQF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXFQS_TFQF_SHIFT)) & CAN_TXFQS_TFQF_MASK)
+
+/*! @name TXESC - Tx Buffer Element Size Configuration */
+#define CAN_TXESC_TBDS_MASK (0x7U)
+#define CAN_TXESC_TBDS_SHIFT (0U)
+#define CAN_TXESC_TBDS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXESC_TBDS_SHIFT)) & CAN_TXESC_TBDS_MASK)
+
+/*! @name TXBRP - Tx Buffer Request Pending */
+#define CAN_TXBRP_TRP_MASK (0xFFFFFFFFU)
+#define CAN_TXBRP_TRP_SHIFT (0U)
+#define CAN_TXBRP_TRP(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBRP_TRP_SHIFT)) & CAN_TXBRP_TRP_MASK)
+
+/*! @name TXBAR - Tx Buffer Add Request */
+#define CAN_TXBAR_AR_MASK (0xFFFFFFFFU)
+#define CAN_TXBAR_AR_SHIFT (0U)
+#define CAN_TXBAR_AR(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBAR_AR_SHIFT)) & CAN_TXBAR_AR_MASK)
+
+/*! @name TXBCR - Tx Buffer Cancellation Request */
+#define CAN_TXBCR_CR_MASK (0xFFFFFFFFU)
+#define CAN_TXBCR_CR_SHIFT (0U)
+#define CAN_TXBCR_CR(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCR_CR_SHIFT)) & CAN_TXBCR_CR_MASK)
+
+/*! @name TXBTO - Tx Buffer Transmission Occurred */
+#define CAN_TXBTO_TO_MASK (0xFFFFFFFFU)
+#define CAN_TXBTO_TO_SHIFT (0U)
+#define CAN_TXBTO_TO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBTO_TO_SHIFT)) & CAN_TXBTO_TO_MASK)
+
+/*! @name TXBCF - Tx Buffer Cancellation Finished */
+#define CAN_TXBCF_TO_MASK (0xFFFFFFFFU)
+#define CAN_TXBCF_TO_SHIFT (0U)
+#define CAN_TXBCF_TO(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCF_TO_SHIFT)) & CAN_TXBCF_TO_MASK)
+
+/*! @name TXBTIE - Tx Buffer Transmission Interrupt Enable */
+#define CAN_TXBTIE_TIE_MASK (0xFFFFFFFFU)
+#define CAN_TXBTIE_TIE_SHIFT (0U)
+#define CAN_TXBTIE_TIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBTIE_TIE_SHIFT)) & CAN_TXBTIE_TIE_MASK)
+
+/*! @name TXBCIE - Tx Buffer Cancellation Finished Interrupt Enable */
+#define CAN_TXBCIE_CFIE_MASK (0xFFFFFFFFU)
+#define CAN_TXBCIE_CFIE_SHIFT (0U)
+#define CAN_TXBCIE_CFIE(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXBCIE_CFIE_SHIFT)) & CAN_TXBCIE_CFIE_MASK)
+
+/*! @name TXEFC - Tx Event FIFO Configuration */
+#define CAN_TXEFC_EFSA_MASK (0xFFFCU)
+#define CAN_TXEFC_EFSA_SHIFT (2U)
+#define CAN_TXEFC_EFSA(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFSA_SHIFT)) & CAN_TXEFC_EFSA_MASK)
+#define CAN_TXEFC_EFS_MASK (0x3F0000U)
+#define CAN_TXEFC_EFS_SHIFT (16U)
+#define CAN_TXEFC_EFS(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFS_SHIFT)) & CAN_TXEFC_EFS_MASK)
+#define CAN_TXEFC_EFWM_MASK (0x3F000000U)
+#define CAN_TXEFC_EFWM_SHIFT (24U)
+#define CAN_TXEFC_EFWM(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFC_EFWM_SHIFT)) & CAN_TXEFC_EFWM_MASK)
+
+/*! @name TXEFS - Tx Event FIFO Status */
+#define CAN_TXEFS_EFFL_MASK (0x3FU)
+#define CAN_TXEFS_EFFL_SHIFT (0U)
+#define CAN_TXEFS_EFFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFFL_SHIFT)) & CAN_TXEFS_EFFL_MASK)
+#define CAN_TXEFS_EFGI_MASK (0x1F00U)
+#define CAN_TXEFS_EFGI_SHIFT (8U)
+#define CAN_TXEFS_EFGI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFGI_SHIFT)) & CAN_TXEFS_EFGI_MASK)
+#define CAN_TXEFS_EFPI_MASK (0x3F0000U)
+#define CAN_TXEFS_EFPI_SHIFT (16U)
+#define CAN_TXEFS_EFPI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFPI_SHIFT)) & CAN_TXEFS_EFPI_MASK)
+#define CAN_TXEFS_EFF_MASK (0x1000000U)
+#define CAN_TXEFS_EFF_SHIFT (24U)
+#define CAN_TXEFS_EFF(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_EFF_SHIFT)) & CAN_TXEFS_EFF_MASK)
+#define CAN_TXEFS_TEFL_MASK (0x2000000U)
+#define CAN_TXEFS_TEFL_SHIFT (25U)
+#define CAN_TXEFS_TEFL(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFS_TEFL_SHIFT)) & CAN_TXEFS_TEFL_MASK)
+
+/*! @name TXEFA - Tx Event FIFO Acknowledge */
+#define CAN_TXEFA_EFAI_MASK (0x1FU)
+#define CAN_TXEFA_EFAI_SHIFT (0U)
+#define CAN_TXEFA_EFAI(x) (((uint32_t)(((uint32_t)(x)) << CAN_TXEFA_EFAI_SHIFT)) & CAN_TXEFA_EFAI_MASK)
+
+/*! @name MRBA - CAN Message RAM Base Address */
+#define CAN_MRBA_BA_MASK (0xFFFFFFFFU)
+#define CAN_MRBA_BA_SHIFT (0U)
+#define CAN_MRBA_BA(x) (((uint32_t)(((uint32_t)(x)) << CAN_MRBA_BA_SHIFT)) & CAN_MRBA_BA_MASK)
+
+/*! @name ETSCC - External Timestamp Counter Configuration */
+#define CAN_ETSCC_ETCP_MASK (0x7FFU)
+#define CAN_ETSCC_ETCP_SHIFT (0U)
+#define CAN_ETSCC_ETCP(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCP_SHIFT)) & CAN_ETSCC_ETCP_MASK)
+#define CAN_ETSCC_ETCE_MASK (0x80000000U)
+#define CAN_ETSCC_ETCE_SHIFT (31U)
+#define CAN_ETSCC_ETCE(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCC_ETCE_SHIFT)) & CAN_ETSCC_ETCE_MASK)
+
+/*! @name ETSCV - External Timestamp Counter Value */
+#define CAN_ETSCV_ETSC_MASK (0xFFFFU)
+#define CAN_ETSCV_ETSC_SHIFT (0U)
+#define CAN_ETSCV_ETSC(x) (((uint32_t)(((uint32_t)(x)) << CAN_ETSCV_ETSC_SHIFT)) & CAN_ETSCV_ETSC_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group CAN_Register_Masks */
+
+
+/* CAN - Peripheral instance base addresses */
+/** Peripheral CAN0 base address */
+#define CAN0_BASE (0x4009D000u)
+/** Peripheral CAN0 base pointer */
+#define CAN0 ((CAN_Type *)CAN0_BASE)
+/** Peripheral CAN1 base address */
+#define CAN1_BASE (0x4009E000u)
+/** Peripheral CAN1 base pointer */
+#define CAN1 ((CAN_Type *)CAN1_BASE)
+/** Array initializer of CAN peripheral base addresses */
+#define CAN_BASE_ADDRS { CAN0_BASE, CAN1_BASE }
+/** Array initializer of CAN peripheral base pointers */
+#define CAN_BASE_PTRS { CAN0, CAN1 }
+/** Interrupt vectors for the CAN peripheral type */
+#define CAN_IRQS { { CAN0_IRQ0_IRQn, CAN0_IRQ1_IRQn }, { CAN1_IRQ0_IRQn, CAN1_IRQ1_IRQn } }
+
+/*!
+ * @}
+ */ /* end of group CAN_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CRC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Peripheral_Access_Layer CRC Peripheral Access Layer
+ * @{
+ */
+
+/** CRC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MODE; /**< CRC mode register, offset: 0x0 */
+ __IO uint32_t SEED; /**< CRC seed register, offset: 0x4 */
+ union { /* offset: 0x8 */
+ __I uint32_t SUM; /**< CRC checksum register, offset: 0x8 */
+ __O uint32_t WR_DATA; /**< CRC data register, offset: 0x8 */
+ };
+} CRC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- CRC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CRC_Register_Masks CRC Register Masks
+ * @{
+ */
+
+/*! @name MODE - CRC mode register */
+#define CRC_MODE_CRC_POLY_MASK (0x3U)
+#define CRC_MODE_CRC_POLY_SHIFT (0U)
+#define CRC_MODE_CRC_POLY(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CRC_POLY_SHIFT)) & CRC_MODE_CRC_POLY_MASK)
+#define CRC_MODE_BIT_RVS_WR_MASK (0x4U)
+#define CRC_MODE_BIT_RVS_WR_SHIFT (2U)
+#define CRC_MODE_BIT_RVS_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_WR_SHIFT)) & CRC_MODE_BIT_RVS_WR_MASK)
+#define CRC_MODE_CMPL_WR_MASK (0x8U)
+#define CRC_MODE_CMPL_WR_SHIFT (3U)
+#define CRC_MODE_CMPL_WR(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_WR_SHIFT)) & CRC_MODE_CMPL_WR_MASK)
+#define CRC_MODE_BIT_RVS_SUM_MASK (0x10U)
+#define CRC_MODE_BIT_RVS_SUM_SHIFT (4U)
+#define CRC_MODE_BIT_RVS_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_BIT_RVS_SUM_SHIFT)) & CRC_MODE_BIT_RVS_SUM_MASK)
+#define CRC_MODE_CMPL_SUM_MASK (0x20U)
+#define CRC_MODE_CMPL_SUM_SHIFT (5U)
+#define CRC_MODE_CMPL_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_MODE_CMPL_SUM_SHIFT)) & CRC_MODE_CMPL_SUM_MASK)
+
+/*! @name SEED - CRC seed register */
+#define CRC_SEED_CRC_SEED_MASK (0xFFFFFFFFU)
+#define CRC_SEED_CRC_SEED_SHIFT (0U)
+#define CRC_SEED_CRC_SEED(x) (((uint32_t)(((uint32_t)(x)) << CRC_SEED_CRC_SEED_SHIFT)) & CRC_SEED_CRC_SEED_MASK)
+
+/*! @name SUM - CRC checksum register */
+#define CRC_SUM_CRC_SUM_MASK (0xFFFFFFFFU)
+#define CRC_SUM_CRC_SUM_SHIFT (0U)
+#define CRC_SUM_CRC_SUM(x) (((uint32_t)(((uint32_t)(x)) << CRC_SUM_CRC_SUM_SHIFT)) & CRC_SUM_CRC_SUM_MASK)
+
+/*! @name WR_DATA - CRC data register */
+#define CRC_WR_DATA_CRC_WR_DATA_MASK (0xFFFFFFFFU)
+#define CRC_WR_DATA_CRC_WR_DATA_SHIFT (0U)
+#define CRC_WR_DATA_CRC_WR_DATA(x) (((uint32_t)(((uint32_t)(x)) << CRC_WR_DATA_CRC_WR_DATA_SHIFT)) & CRC_WR_DATA_CRC_WR_DATA_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group CRC_Register_Masks */
+
+
+/* CRC - Peripheral instance base addresses */
+/** Peripheral CRC_ENGINE base address */
+#define CRC_ENGINE_BASE (0x40095000u)
+/** Peripheral CRC_ENGINE base pointer */
+#define CRC_ENGINE ((CRC_Type *)CRC_ENGINE_BASE)
+/** Array initializer of CRC peripheral base addresses */
+#define CRC_BASE_ADDRS { CRC_ENGINE_BASE }
+/** Array initializer of CRC peripheral base pointers */
+#define CRC_BASE_PTRS { CRC_ENGINE }
+
+/*!
+ * @}
+ */ /* end of group CRC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- CTIMER Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CTIMER_Peripheral_Access_Layer CTIMER Peripheral Access Layer
+ * @{
+ */
+
+/** CTIMER - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t IR; /**< Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending., offset: 0x0 */
+ __IO uint32_t TCR; /**< Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR., offset: 0x4 */
+ __IO uint32_t TC; /**< Timer Counter, offset: 0x8 */
+ __IO uint32_t PR; /**< Prescale Register, offset: 0xC */
+ __IO uint32_t PC; /**< Prescale Counter, offset: 0x10 */
+ __IO uint32_t MCR; /**< Match Control Register, offset: 0x14 */
+ __IO uint32_t MR[4]; /**< Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC., array offset: 0x18, array step: 0x4 */
+ __IO uint32_t CCR; /**< Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place., offset: 0x28 */
+ __I uint32_t CR[4]; /**< Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input., array offset: 0x2C, array step: 0x4 */
+ __IO uint32_t EMR; /**< External Match Register. The EMR controls the match function and the external match pins., offset: 0x3C */
+ uint8_t RESERVED_0[48];
+ __IO uint32_t CTCR; /**< Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting., offset: 0x70 */
+ __IO uint32_t PWMC; /**< PWM Control Register. The PWMCON enables PWM mode for the external match pins., offset: 0x74 */
+ __IO uint32_t MSR[4]; /**< Match Shadow Register, array offset: 0x78, array step: 0x4 */
+} CTIMER_Type;
+
+/* ----------------------------------------------------------------------------
+ -- CTIMER Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup CTIMER_Register_Masks CTIMER Register Masks
+ * @{
+ */
+
+/*! @name IR - Interrupt Register. The IR can be written to clear interrupts. The IR can be read to identify which of eight possible interrupt sources are pending. */
+#define CTIMER_IR_MR0INT_MASK (0x1U)
+#define CTIMER_IR_MR0INT_SHIFT (0U)
+#define CTIMER_IR_MR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR0INT_SHIFT)) & CTIMER_IR_MR0INT_MASK)
+#define CTIMER_IR_MR1INT_MASK (0x2U)
+#define CTIMER_IR_MR1INT_SHIFT (1U)
+#define CTIMER_IR_MR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR1INT_SHIFT)) & CTIMER_IR_MR1INT_MASK)
+#define CTIMER_IR_MR2INT_MASK (0x4U)
+#define CTIMER_IR_MR2INT_SHIFT (2U)
+#define CTIMER_IR_MR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR2INT_SHIFT)) & CTIMER_IR_MR2INT_MASK)
+#define CTIMER_IR_MR3INT_MASK (0x8U)
+#define CTIMER_IR_MR3INT_SHIFT (3U)
+#define CTIMER_IR_MR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_MR3INT_SHIFT)) & CTIMER_IR_MR3INT_MASK)
+#define CTIMER_IR_CR0INT_MASK (0x10U)
+#define CTIMER_IR_CR0INT_SHIFT (4U)
+#define CTIMER_IR_CR0INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR0INT_SHIFT)) & CTIMER_IR_CR0INT_MASK)
+#define CTIMER_IR_CR1INT_MASK (0x20U)
+#define CTIMER_IR_CR1INT_SHIFT (5U)
+#define CTIMER_IR_CR1INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR1INT_SHIFT)) & CTIMER_IR_CR1INT_MASK)
+#define CTIMER_IR_CR2INT_MASK (0x40U)
+#define CTIMER_IR_CR2INT_SHIFT (6U)
+#define CTIMER_IR_CR2INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR2INT_SHIFT)) & CTIMER_IR_CR2INT_MASK)
+#define CTIMER_IR_CR3INT_MASK (0x80U)
+#define CTIMER_IR_CR3INT_SHIFT (7U)
+#define CTIMER_IR_CR3INT(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_IR_CR3INT_SHIFT)) & CTIMER_IR_CR3INT_MASK)
+
+/*! @name TCR - Timer Control Register. The TCR is used to control the Timer Counter functions. The Timer Counter can be disabled or reset through the TCR. */
+#define CTIMER_TCR_CEN_MASK (0x1U)
+#define CTIMER_TCR_CEN_SHIFT (0U)
+#define CTIMER_TCR_CEN(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CEN_SHIFT)) & CTIMER_TCR_CEN_MASK)
+#define CTIMER_TCR_CRST_MASK (0x2U)
+#define CTIMER_TCR_CRST_SHIFT (1U)
+#define CTIMER_TCR_CRST(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TCR_CRST_SHIFT)) & CTIMER_TCR_CRST_MASK)
+
+/*! @name TC - Timer Counter */
+#define CTIMER_TC_TCVAL_MASK (0xFFFFFFFFU)
+#define CTIMER_TC_TCVAL_SHIFT (0U)
+#define CTIMER_TC_TCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_TC_TCVAL_SHIFT)) & CTIMER_TC_TCVAL_MASK)
+
+/*! @name PR - Prescale Register */
+#define CTIMER_PR_PRVAL_MASK (0xFFFFFFFFU)
+#define CTIMER_PR_PRVAL_SHIFT (0U)
+#define CTIMER_PR_PRVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PR_PRVAL_SHIFT)) & CTIMER_PR_PRVAL_MASK)
+
+/*! @name PC - Prescale Counter */
+#define CTIMER_PC_PCVAL_MASK (0xFFFFFFFFU)
+#define CTIMER_PC_PCVAL_SHIFT (0U)
+#define CTIMER_PC_PCVAL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PC_PCVAL_SHIFT)) & CTIMER_PC_PCVAL_MASK)
+
+/*! @name MCR - Match Control Register */
+#define CTIMER_MCR_MR0I_MASK (0x1U)
+#define CTIMER_MCR_MR0I_SHIFT (0U)
+#define CTIMER_MCR_MR0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0I_SHIFT)) & CTIMER_MCR_MR0I_MASK)
+#define CTIMER_MCR_MR0R_MASK (0x2U)
+#define CTIMER_MCR_MR0R_SHIFT (1U)
+#define CTIMER_MCR_MR0R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0R_SHIFT)) & CTIMER_MCR_MR0R_MASK)
+#define CTIMER_MCR_MR0S_MASK (0x4U)
+#define CTIMER_MCR_MR0S_SHIFT (2U)
+#define CTIMER_MCR_MR0S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0S_SHIFT)) & CTIMER_MCR_MR0S_MASK)
+#define CTIMER_MCR_MR1I_MASK (0x8U)
+#define CTIMER_MCR_MR1I_SHIFT (3U)
+#define CTIMER_MCR_MR1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1I_SHIFT)) & CTIMER_MCR_MR1I_MASK)
+#define CTIMER_MCR_MR1R_MASK (0x10U)
+#define CTIMER_MCR_MR1R_SHIFT (4U)
+#define CTIMER_MCR_MR1R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1R_SHIFT)) & CTIMER_MCR_MR1R_MASK)
+#define CTIMER_MCR_MR1S_MASK (0x20U)
+#define CTIMER_MCR_MR1S_SHIFT (5U)
+#define CTIMER_MCR_MR1S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1S_SHIFT)) & CTIMER_MCR_MR1S_MASK)
+#define CTIMER_MCR_MR2I_MASK (0x40U)
+#define CTIMER_MCR_MR2I_SHIFT (6U)
+#define CTIMER_MCR_MR2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2I_SHIFT)) & CTIMER_MCR_MR2I_MASK)
+#define CTIMER_MCR_MR2R_MASK (0x80U)
+#define CTIMER_MCR_MR2R_SHIFT (7U)
+#define CTIMER_MCR_MR2R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2R_SHIFT)) & CTIMER_MCR_MR2R_MASK)
+#define CTIMER_MCR_MR2S_MASK (0x100U)
+#define CTIMER_MCR_MR2S_SHIFT (8U)
+#define CTIMER_MCR_MR2S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2S_SHIFT)) & CTIMER_MCR_MR2S_MASK)
+#define CTIMER_MCR_MR3I_MASK (0x200U)
+#define CTIMER_MCR_MR3I_SHIFT (9U)
+#define CTIMER_MCR_MR3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3I_SHIFT)) & CTIMER_MCR_MR3I_MASK)
+#define CTIMER_MCR_MR3R_MASK (0x400U)
+#define CTIMER_MCR_MR3R_SHIFT (10U)
+#define CTIMER_MCR_MR3R(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3R_SHIFT)) & CTIMER_MCR_MR3R_MASK)
+#define CTIMER_MCR_MR3S_MASK (0x800U)
+#define CTIMER_MCR_MR3S_SHIFT (11U)
+#define CTIMER_MCR_MR3S(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3S_SHIFT)) & CTIMER_MCR_MR3S_MASK)
+#define CTIMER_MCR_MR0RL_MASK (0x1000000U)
+#define CTIMER_MCR_MR0RL_SHIFT (24U)
+#define CTIMER_MCR_MR0RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR0RL_SHIFT)) & CTIMER_MCR_MR0RL_MASK)
+#define CTIMER_MCR_MR1RL_MASK (0x2000000U)
+#define CTIMER_MCR_MR1RL_SHIFT (25U)
+#define CTIMER_MCR_MR1RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR1RL_SHIFT)) & CTIMER_MCR_MR1RL_MASK)
+#define CTIMER_MCR_MR2RL_MASK (0x4000000U)
+#define CTIMER_MCR_MR2RL_SHIFT (26U)
+#define CTIMER_MCR_MR2RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR2RL_SHIFT)) & CTIMER_MCR_MR2RL_MASK)
+#define CTIMER_MCR_MR3RL_MASK (0x8000000U)
+#define CTIMER_MCR_MR3RL_SHIFT (27U)
+#define CTIMER_MCR_MR3RL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MCR_MR3RL_SHIFT)) & CTIMER_MCR_MR3RL_MASK)
+
+/*! @name MR - Match Register . MR can be enabled through the MCR to reset the TC, stop both the TC and PC, and/or generate an interrupt every time MR matches the TC. */
+#define CTIMER_MR_MATCH_MASK (0xFFFFFFFFU)
+#define CTIMER_MR_MATCH_SHIFT (0U)
+#define CTIMER_MR_MATCH(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MR_MATCH_SHIFT)) & CTIMER_MR_MATCH_MASK)
+
+/* The count of CTIMER_MR */
+#define CTIMER_MR_COUNT (4U)
+
+/*! @name CCR - Capture Control Register. The CCR controls which edges of the capture inputs are used to load the Capture Registers and whether or not an interrupt is generated when a capture takes place. */
+#define CTIMER_CCR_CAP0RE_MASK (0x1U)
+#define CTIMER_CCR_CAP0RE_SHIFT (0U)
+#define CTIMER_CCR_CAP0RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0RE_SHIFT)) & CTIMER_CCR_CAP0RE_MASK)
+#define CTIMER_CCR_CAP0FE_MASK (0x2U)
+#define CTIMER_CCR_CAP0FE_SHIFT (1U)
+#define CTIMER_CCR_CAP0FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0FE_SHIFT)) & CTIMER_CCR_CAP0FE_MASK)
+#define CTIMER_CCR_CAP0I_MASK (0x4U)
+#define CTIMER_CCR_CAP0I_SHIFT (2U)
+#define CTIMER_CCR_CAP0I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP0I_SHIFT)) & CTIMER_CCR_CAP0I_MASK)
+#define CTIMER_CCR_CAP1RE_MASK (0x8U)
+#define CTIMER_CCR_CAP1RE_SHIFT (3U)
+#define CTIMER_CCR_CAP1RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1RE_SHIFT)) & CTIMER_CCR_CAP1RE_MASK)
+#define CTIMER_CCR_CAP1FE_MASK (0x10U)
+#define CTIMER_CCR_CAP1FE_SHIFT (4U)
+#define CTIMER_CCR_CAP1FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1FE_SHIFT)) & CTIMER_CCR_CAP1FE_MASK)
+#define CTIMER_CCR_CAP1I_MASK (0x20U)
+#define CTIMER_CCR_CAP1I_SHIFT (5U)
+#define CTIMER_CCR_CAP1I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP1I_SHIFT)) & CTIMER_CCR_CAP1I_MASK)
+#define CTIMER_CCR_CAP2RE_MASK (0x40U)
+#define CTIMER_CCR_CAP2RE_SHIFT (6U)
+#define CTIMER_CCR_CAP2RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2RE_SHIFT)) & CTIMER_CCR_CAP2RE_MASK)
+#define CTIMER_CCR_CAP2FE_MASK (0x80U)
+#define CTIMER_CCR_CAP2FE_SHIFT (7U)
+#define CTIMER_CCR_CAP2FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2FE_SHIFT)) & CTIMER_CCR_CAP2FE_MASK)
+#define CTIMER_CCR_CAP2I_MASK (0x100U)
+#define CTIMER_CCR_CAP2I_SHIFT (8U)
+#define CTIMER_CCR_CAP2I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP2I_SHIFT)) & CTIMER_CCR_CAP2I_MASK)
+#define CTIMER_CCR_CAP3RE_MASK (0x200U)
+#define CTIMER_CCR_CAP3RE_SHIFT (9U)
+#define CTIMER_CCR_CAP3RE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3RE_SHIFT)) & CTIMER_CCR_CAP3RE_MASK)
+#define CTIMER_CCR_CAP3FE_MASK (0x400U)
+#define CTIMER_CCR_CAP3FE_SHIFT (10U)
+#define CTIMER_CCR_CAP3FE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3FE_SHIFT)) & CTIMER_CCR_CAP3FE_MASK)
+#define CTIMER_CCR_CAP3I_MASK (0x800U)
+#define CTIMER_CCR_CAP3I_SHIFT (11U)
+#define CTIMER_CCR_CAP3I(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CCR_CAP3I_SHIFT)) & CTIMER_CCR_CAP3I_MASK)
+
+/*! @name CR - Capture Register . CR is loaded with the value of TC when there is an event on the CAPn. input. */
+#define CTIMER_CR_CAP_MASK (0xFFFFFFFFU)
+#define CTIMER_CR_CAP_SHIFT (0U)
+#define CTIMER_CR_CAP(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CR_CAP_SHIFT)) & CTIMER_CR_CAP_MASK)
+
+/* The count of CTIMER_CR */
+#define CTIMER_CR_COUNT (4U)
+
+/*! @name EMR - External Match Register. The EMR controls the match function and the external match pins. */
+#define CTIMER_EMR_EM0_MASK (0x1U)
+#define CTIMER_EMR_EM0_SHIFT (0U)
+#define CTIMER_EMR_EM0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM0_SHIFT)) & CTIMER_EMR_EM0_MASK)
+#define CTIMER_EMR_EM1_MASK (0x2U)
+#define CTIMER_EMR_EM1_SHIFT (1U)
+#define CTIMER_EMR_EM1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM1_SHIFT)) & CTIMER_EMR_EM1_MASK)
+#define CTIMER_EMR_EM2_MASK (0x4U)
+#define CTIMER_EMR_EM2_SHIFT (2U)
+#define CTIMER_EMR_EM2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM2_SHIFT)) & CTIMER_EMR_EM2_MASK)
+#define CTIMER_EMR_EM3_MASK (0x8U)
+#define CTIMER_EMR_EM3_SHIFT (3U)
+#define CTIMER_EMR_EM3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EM3_SHIFT)) & CTIMER_EMR_EM3_MASK)
+#define CTIMER_EMR_EMC0_MASK (0x30U)
+#define CTIMER_EMR_EMC0_SHIFT (4U)
+#define CTIMER_EMR_EMC0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC0_SHIFT)) & CTIMER_EMR_EMC0_MASK)
+#define CTIMER_EMR_EMC1_MASK (0xC0U)
+#define CTIMER_EMR_EMC1_SHIFT (6U)
+#define CTIMER_EMR_EMC1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC1_SHIFT)) & CTIMER_EMR_EMC1_MASK)
+#define CTIMER_EMR_EMC2_MASK (0x300U)
+#define CTIMER_EMR_EMC2_SHIFT (8U)
+#define CTIMER_EMR_EMC2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC2_SHIFT)) & CTIMER_EMR_EMC2_MASK)
+#define CTIMER_EMR_EMC3_MASK (0xC00U)
+#define CTIMER_EMR_EMC3_SHIFT (10U)
+#define CTIMER_EMR_EMC3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_EMR_EMC3_SHIFT)) & CTIMER_EMR_EMC3_MASK)
+
+/*! @name CTCR - Count Control Register. The CTCR selects between Timer and Counter mode, and in Counter mode selects the signal and edge(s) for counting. */
+#define CTIMER_CTCR_CTMODE_MASK (0x3U)
+#define CTIMER_CTCR_CTMODE_SHIFT (0U)
+#define CTIMER_CTCR_CTMODE(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CTMODE_SHIFT)) & CTIMER_CTCR_CTMODE_MASK)
+#define CTIMER_CTCR_CINSEL_MASK (0xCU)
+#define CTIMER_CTCR_CINSEL_SHIFT (2U)
+#define CTIMER_CTCR_CINSEL(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_CINSEL_SHIFT)) & CTIMER_CTCR_CINSEL_MASK)
+#define CTIMER_CTCR_ENCC_MASK (0x10U)
+#define CTIMER_CTCR_ENCC_SHIFT (4U)
+#define CTIMER_CTCR_ENCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_ENCC_SHIFT)) & CTIMER_CTCR_ENCC_MASK)
+#define CTIMER_CTCR_SELCC_MASK (0xE0U)
+#define CTIMER_CTCR_SELCC_SHIFT (5U)
+#define CTIMER_CTCR_SELCC(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_CTCR_SELCC_SHIFT)) & CTIMER_CTCR_SELCC_MASK)
+
+/*! @name PWMC - PWM Control Register. The PWMCON enables PWM mode for the external match pins. */
+#define CTIMER_PWMC_PWMEN0_MASK (0x1U)
+#define CTIMER_PWMC_PWMEN0_SHIFT (0U)
+#define CTIMER_PWMC_PWMEN0(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN0_SHIFT)) & CTIMER_PWMC_PWMEN0_MASK)
+#define CTIMER_PWMC_PWMEN1_MASK (0x2U)
+#define CTIMER_PWMC_PWMEN1_SHIFT (1U)
+#define CTIMER_PWMC_PWMEN1(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN1_SHIFT)) & CTIMER_PWMC_PWMEN1_MASK)
+#define CTIMER_PWMC_PWMEN2_MASK (0x4U)
+#define CTIMER_PWMC_PWMEN2_SHIFT (2U)
+#define CTIMER_PWMC_PWMEN2(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN2_SHIFT)) & CTIMER_PWMC_PWMEN2_MASK)
+#define CTIMER_PWMC_PWMEN3_MASK (0x8U)
+#define CTIMER_PWMC_PWMEN3_SHIFT (3U)
+#define CTIMER_PWMC_PWMEN3(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_PWMC_PWMEN3_SHIFT)) & CTIMER_PWMC_PWMEN3_MASK)
+
+/*! @name MSR - Match Shadow Register */
+#define CTIMER_MSR_SHADOWW_MASK (0xFFFFFFFFU)
+#define CTIMER_MSR_SHADOWW_SHIFT (0U)
+#define CTIMER_MSR_SHADOWW(x) (((uint32_t)(((uint32_t)(x)) << CTIMER_MSR_SHADOWW_SHIFT)) & CTIMER_MSR_SHADOWW_MASK)
+
+/* The count of CTIMER_MSR */
+#define CTIMER_MSR_COUNT (4U)
+
+
+/*!
+ * @}
+ */ /* end of group CTIMER_Register_Masks */
+
+
+/* CTIMER - Peripheral instance base addresses */
+/** Peripheral CTIMER0 base address */
+#define CTIMER0_BASE (0x40008000u)
+/** Peripheral CTIMER0 base pointer */
+#define CTIMER0 ((CTIMER_Type *)CTIMER0_BASE)
+/** Peripheral CTIMER1 base address */
+#define CTIMER1_BASE (0x40009000u)
+/** Peripheral CTIMER1 base pointer */
+#define CTIMER1 ((CTIMER_Type *)CTIMER1_BASE)
+/** Peripheral CTIMER2 base address */
+#define CTIMER2_BASE (0x40028000u)
+/** Peripheral CTIMER2 base pointer */
+#define CTIMER2 ((CTIMER_Type *)CTIMER2_BASE)
+/** Peripheral CTIMER3 base address */
+#define CTIMER3_BASE (0x40048000u)
+/** Peripheral CTIMER3 base pointer */
+#define CTIMER3 ((CTIMER_Type *)CTIMER3_BASE)
+/** Peripheral CTIMER4 base address */
+#define CTIMER4_BASE (0x40049000u)
+/** Peripheral CTIMER4 base pointer */
+#define CTIMER4 ((CTIMER_Type *)CTIMER4_BASE)
+/** Array initializer of CTIMER peripheral base addresses */
+#define CTIMER_BASE_ADDRS { CTIMER0_BASE, CTIMER1_BASE, CTIMER2_BASE, CTIMER3_BASE, CTIMER4_BASE }
+/** Array initializer of CTIMER peripheral base pointers */
+#define CTIMER_BASE_PTRS { CTIMER0, CTIMER1, CTIMER2, CTIMER3, CTIMER4 }
+/** Interrupt vectors for the CTIMER peripheral type */
+#define CTIMER_IRQS { CTIMER0_IRQn, CTIMER1_IRQn, CTIMER2_IRQn, CTIMER3_IRQn, CTIMER4_IRQn }
+
+/*!
+ * @}
+ */ /* end of group CTIMER_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMA Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Peripheral_Access_Layer DMA Peripheral Access Layer
+ * @{
+ */
+
+/** DMA - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CTRL; /**< DMA control., offset: 0x0 */
+ __I uint32_t INTSTAT; /**< Interrupt status., offset: 0x4 */
+ __IO uint32_t SRAMBASE; /**< SRAM address of the channel configuration table., offset: 0x8 */
+ uint8_t RESERVED_0[20];
+ struct { /* offset: 0x20, array step: 0x5C */
+ __IO uint32_t ENABLESET; /**< Channel Enable read and Set for all DMA channels., array offset: 0x20, array step: 0x5C */
+ uint8_t RESERVED_0[4];
+ __O uint32_t ENABLECLR; /**< Channel Enable Clear for all DMA channels., array offset: 0x28, array step: 0x5C */
+ uint8_t RESERVED_1[4];
+ __I uint32_t ACTIVE; /**< Channel Active status for all DMA channels., array offset: 0x30, array step: 0x5C */
+ uint8_t RESERVED_2[4];
+ __I uint32_t BUSY; /**< Channel Busy status for all DMA channels., array offset: 0x38, array step: 0x5C */
+ uint8_t RESERVED_3[4];
+ __IO uint32_t ERRINT; /**< Error Interrupt status for all DMA channels., array offset: 0x40, array step: 0x5C */
+ uint8_t RESERVED_4[4];
+ __IO uint32_t INTENSET; /**< Interrupt Enable read and Set for all DMA channels., array offset: 0x48, array step: 0x5C */
+ uint8_t RESERVED_5[4];
+ __O uint32_t INTENCLR; /**< Interrupt Enable Clear for all DMA channels., array offset: 0x50, array step: 0x5C */
+ uint8_t RESERVED_6[4];
+ __IO uint32_t INTA; /**< Interrupt A status for all DMA channels., array offset: 0x58, array step: 0x5C */
+ uint8_t RESERVED_7[4];
+ __IO uint32_t INTB; /**< Interrupt B status for all DMA channels., array offset: 0x60, array step: 0x5C */
+ uint8_t RESERVED_8[4];
+ __O uint32_t SETVALID; /**< Set ValidPending control bits for all DMA channels., array offset: 0x68, array step: 0x5C */
+ uint8_t RESERVED_9[4];
+ __O uint32_t SETTRIG; /**< Set Trigger control bits for all DMA channels., array offset: 0x70, array step: 0x5C */
+ uint8_t RESERVED_10[4];
+ __O uint32_t ABORT; /**< Channel Abort control for all DMA channels., array offset: 0x78, array step: 0x5C */
+ } COMMON[1];
+ uint8_t RESERVED_1[900];
+ struct { /* offset: 0x400, array step: 0x10 */
+ __IO uint32_t CFG; /**< Configuration register for DMA channel ., array offset: 0x400, array step: 0x10 */
+ __I uint32_t CTLSTAT; /**< Control and status register for DMA channel ., array offset: 0x404, array step: 0x10 */
+ __IO uint32_t XFERCFG; /**< Transfer configuration register for DMA channel ., array offset: 0x408, array step: 0x10 */
+ uint8_t RESERVED_0[4];
+ } CHANNEL[30];
+} DMA_Type;
+
+/* ----------------------------------------------------------------------------
+ -- DMA Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMA_Register_Masks DMA Register Masks
+ * @{
+ */
+
+/*! @name CTRL - DMA control. */
+#define DMA_CTRL_ENABLE_MASK (0x1U)
+#define DMA_CTRL_ENABLE_SHIFT (0U)
+#define DMA_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CTRL_ENABLE_SHIFT)) & DMA_CTRL_ENABLE_MASK)
+
+/*! @name INTSTAT - Interrupt status. */
+#define DMA_INTSTAT_ACTIVEINT_MASK (0x2U)
+#define DMA_INTSTAT_ACTIVEINT_SHIFT (1U)
+#define DMA_INTSTAT_ACTIVEINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEINT_SHIFT)) & DMA_INTSTAT_ACTIVEINT_MASK)
+#define DMA_INTSTAT_ACTIVEERRINT_MASK (0x4U)
+#define DMA_INTSTAT_ACTIVEERRINT_SHIFT (2U)
+#define DMA_INTSTAT_ACTIVEERRINT(x) (((uint32_t)(((uint32_t)(x)) << DMA_INTSTAT_ACTIVEERRINT_SHIFT)) & DMA_INTSTAT_ACTIVEERRINT_MASK)
+
+/*! @name SRAMBASE - SRAM address of the channel configuration table. */
+#define DMA_SRAMBASE_OFFSET_MASK (0xFFFFFE00U)
+#define DMA_SRAMBASE_OFFSET_SHIFT (9U)
+#define DMA_SRAMBASE_OFFSET(x) (((uint32_t)(((uint32_t)(x)) << DMA_SRAMBASE_OFFSET_SHIFT)) & DMA_SRAMBASE_OFFSET_MASK)
+
+/*! @name COMMON_ENABLESET - Channel Enable read and Set for all DMA channels. */
+#define DMA_COMMON_ENABLESET_ENA_MASK (0xFFFFFFFFU)
+#define DMA_COMMON_ENABLESET_ENA_SHIFT (0U)
+#define DMA_COMMON_ENABLESET_ENA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLESET_ENA_SHIFT)) & DMA_COMMON_ENABLESET_ENA_MASK)
+
+/* The count of DMA_COMMON_ENABLESET */
+#define DMA_COMMON_ENABLESET_COUNT (1U)
+
+/*! @name COMMON_ENABLECLR - Channel Enable Clear for all DMA channels. */
+#define DMA_COMMON_ENABLECLR_CLR_MASK (0xFFFFFFFFU)
+#define DMA_COMMON_ENABLECLR_CLR_SHIFT (0U)
+#define DMA_COMMON_ENABLECLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ENABLECLR_CLR_SHIFT)) & DMA_COMMON_ENABLECLR_CLR_MASK)
+
+/* The count of DMA_COMMON_ENABLECLR */
+#define DMA_COMMON_ENABLECLR_COUNT (1U)
+
+/*! @name COMMON_ACTIVE - Channel Active status for all DMA channels. */
+#define DMA_COMMON_ACTIVE_ACT_MASK (0xFFFFFFFFU)
+#define DMA_COMMON_ACTIVE_ACT_SHIFT (0U)
+#define DMA_COMMON_ACTIVE_ACT(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ACTIVE_ACT_SHIFT)) & DMA_COMMON_ACTIVE_ACT_MASK)
+
+/* The count of DMA_COMMON_ACTIVE */
+#define DMA_COMMON_ACTIVE_COUNT (1U)
+
+/*! @name COMMON_BUSY - Channel Busy status for all DMA channels. */
+#define DMA_COMMON_BUSY_BSY_MASK (0xFFFFFFFFU)
+#define DMA_COMMON_BUSY_BSY_SHIFT (0U)
+#define DMA_COMMON_BUSY_BSY(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_BUSY_BSY_SHIFT)) & DMA_COMMON_BUSY_BSY_MASK)
+
+/* The count of DMA_COMMON_BUSY */
+#define DMA_COMMON_BUSY_COUNT (1U)
+
+/*! @name COMMON_ERRINT - Error Interrupt status for all DMA channels. */
+#define DMA_COMMON_ERRINT_ERR_MASK (0xFFFFFFFFU)
+#define DMA_COMMON_ERRINT_ERR_SHIFT (0U)
+#define DMA_COMMON_ERRINT_ERR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ERRINT_ERR_SHIFT)) & DMA_COMMON_ERRINT_ERR_MASK)
+
+/* The count of DMA_COMMON_ERRINT */
+#define DMA_COMMON_ERRINT_COUNT (1U)
+
+/*! @name COMMON_INTENSET - Interrupt Enable read and Set for all DMA channels. */
+#define DMA_COMMON_INTENSET_INTEN_MASK (0xFFFFFFFFU)
+#define DMA_COMMON_INTENSET_INTEN_SHIFT (0U)
+#define DMA_COMMON_INTENSET_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENSET_INTEN_SHIFT)) & DMA_COMMON_INTENSET_INTEN_MASK)
+
+/* The count of DMA_COMMON_INTENSET */
+#define DMA_COMMON_INTENSET_COUNT (1U)
+
+/*! @name COMMON_INTENCLR - Interrupt Enable Clear for all DMA channels. */
+#define DMA_COMMON_INTENCLR_CLR_MASK (0xFFFFFFFFU)
+#define DMA_COMMON_INTENCLR_CLR_SHIFT (0U)
+#define DMA_COMMON_INTENCLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTENCLR_CLR_SHIFT)) & DMA_COMMON_INTENCLR_CLR_MASK)
+
+/* The count of DMA_COMMON_INTENCLR */
+#define DMA_COMMON_INTENCLR_COUNT (1U)
+
+/*! @name COMMON_INTA - Interrupt A status for all DMA channels. */
+#define DMA_COMMON_INTA_IA_MASK (0xFFFFFFFFU)
+#define DMA_COMMON_INTA_IA_SHIFT (0U)
+#define DMA_COMMON_INTA_IA(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTA_IA_SHIFT)) & DMA_COMMON_INTA_IA_MASK)
+
+/* The count of DMA_COMMON_INTA */
+#define DMA_COMMON_INTA_COUNT (1U)
+
+/*! @name COMMON_INTB - Interrupt B status for all DMA channels. */
+#define DMA_COMMON_INTB_IB_MASK (0xFFFFFFFFU)
+#define DMA_COMMON_INTB_IB_SHIFT (0U)
+#define DMA_COMMON_INTB_IB(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_INTB_IB_SHIFT)) & DMA_COMMON_INTB_IB_MASK)
+
+/* The count of DMA_COMMON_INTB */
+#define DMA_COMMON_INTB_COUNT (1U)
+
+/*! @name COMMON_SETVALID - Set ValidPending control bits for all DMA channels. */
+#define DMA_COMMON_SETVALID_SV_MASK (0xFFFFFFFFU)
+#define DMA_COMMON_SETVALID_SV_SHIFT (0U)
+#define DMA_COMMON_SETVALID_SV(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETVALID_SV_SHIFT)) & DMA_COMMON_SETVALID_SV_MASK)
+
+/* The count of DMA_COMMON_SETVALID */
+#define DMA_COMMON_SETVALID_COUNT (1U)
+
+/*! @name COMMON_SETTRIG - Set Trigger control bits for all DMA channels. */
+#define DMA_COMMON_SETTRIG_TRIG_MASK (0xFFFFFFFFU)
+#define DMA_COMMON_SETTRIG_TRIG_SHIFT (0U)
+#define DMA_COMMON_SETTRIG_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_SETTRIG_TRIG_SHIFT)) & DMA_COMMON_SETTRIG_TRIG_MASK)
+
+/* The count of DMA_COMMON_SETTRIG */
+#define DMA_COMMON_SETTRIG_COUNT (1U)
+
+/*! @name COMMON_ABORT - Channel Abort control for all DMA channels. */
+#define DMA_COMMON_ABORT_ABORTCTRL_MASK (0xFFFFFFFFU)
+#define DMA_COMMON_ABORT_ABORTCTRL_SHIFT (0U)
+#define DMA_COMMON_ABORT_ABORTCTRL(x) (((uint32_t)(((uint32_t)(x)) << DMA_COMMON_ABORT_ABORTCTRL_SHIFT)) & DMA_COMMON_ABORT_ABORTCTRL_MASK)
+
+/* The count of DMA_COMMON_ABORT */
+#define DMA_COMMON_ABORT_COUNT (1U)
+
+/*! @name CHANNEL_CFG - Configuration register for DMA channel . */
+#define DMA_CHANNEL_CFG_PERIPHREQEN_MASK (0x1U)
+#define DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT (0U)
+#define DMA_CHANNEL_CFG_PERIPHREQEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_PERIPHREQEN_SHIFT)) & DMA_CHANNEL_CFG_PERIPHREQEN_MASK)
+#define DMA_CHANNEL_CFG_HWTRIGEN_MASK (0x2U)
+#define DMA_CHANNEL_CFG_HWTRIGEN_SHIFT (1U)
+#define DMA_CHANNEL_CFG_HWTRIGEN(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_HWTRIGEN_SHIFT)) & DMA_CHANNEL_CFG_HWTRIGEN_MASK)
+#define DMA_CHANNEL_CFG_TRIGPOL_MASK (0x10U)
+#define DMA_CHANNEL_CFG_TRIGPOL_SHIFT (4U)
+#define DMA_CHANNEL_CFG_TRIGPOL(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGPOL_SHIFT)) & DMA_CHANNEL_CFG_TRIGPOL_MASK)
+#define DMA_CHANNEL_CFG_TRIGTYPE_MASK (0x20U)
+#define DMA_CHANNEL_CFG_TRIGTYPE_SHIFT (5U)
+#define DMA_CHANNEL_CFG_TRIGTYPE(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGTYPE_SHIFT)) & DMA_CHANNEL_CFG_TRIGTYPE_MASK)
+#define DMA_CHANNEL_CFG_TRIGBURST_MASK (0x40U)
+#define DMA_CHANNEL_CFG_TRIGBURST_SHIFT (6U)
+#define DMA_CHANNEL_CFG_TRIGBURST(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_TRIGBURST_SHIFT)) & DMA_CHANNEL_CFG_TRIGBURST_MASK)
+#define DMA_CHANNEL_CFG_BURSTPOWER_MASK (0xF00U)
+#define DMA_CHANNEL_CFG_BURSTPOWER_SHIFT (8U)
+#define DMA_CHANNEL_CFG_BURSTPOWER(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_BURSTPOWER_SHIFT)) & DMA_CHANNEL_CFG_BURSTPOWER_MASK)
+#define DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK (0x4000U)
+#define DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT (14U)
+#define DMA_CHANNEL_CFG_SRCBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_SRCBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK)
+#define DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK (0x8000U)
+#define DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT (15U)
+#define DMA_CHANNEL_CFG_DSTBURSTWRAP(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_DSTBURSTWRAP_SHIFT)) & DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK)
+#define DMA_CHANNEL_CFG_CHPRIORITY_MASK (0x70000U)
+#define DMA_CHANNEL_CFG_CHPRIORITY_SHIFT (16U)
+#define DMA_CHANNEL_CFG_CHPRIORITY(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CFG_CHPRIORITY_SHIFT)) & DMA_CHANNEL_CFG_CHPRIORITY_MASK)
+
+/* The count of DMA_CHANNEL_CFG */
+#define DMA_CHANNEL_CFG_COUNT (30U)
+
+/*! @name CHANNEL_CTLSTAT - Control and status register for DMA channel . */
+#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK (0x1U)
+#define DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT (0U)
+#define DMA_CHANNEL_CTLSTAT_VALIDPENDING(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_VALIDPENDING_SHIFT)) & DMA_CHANNEL_CTLSTAT_VALIDPENDING_MASK)
+#define DMA_CHANNEL_CTLSTAT_TRIG_MASK (0x4U)
+#define DMA_CHANNEL_CTLSTAT_TRIG_SHIFT (2U)
+#define DMA_CHANNEL_CTLSTAT_TRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_CTLSTAT_TRIG_SHIFT)) & DMA_CHANNEL_CTLSTAT_TRIG_MASK)
+
+/* The count of DMA_CHANNEL_CTLSTAT */
+#define DMA_CHANNEL_CTLSTAT_COUNT (30U)
+
+/*! @name CHANNEL_XFERCFG - Transfer configuration register for DMA channel . */
+#define DMA_CHANNEL_XFERCFG_CFGVALID_MASK (0x1U)
+#define DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT (0U)
+#define DMA_CHANNEL_XFERCFG_CFGVALID(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CFGVALID_SHIFT)) & DMA_CHANNEL_XFERCFG_CFGVALID_MASK)
+#define DMA_CHANNEL_XFERCFG_RELOAD_MASK (0x2U)
+#define DMA_CHANNEL_XFERCFG_RELOAD_SHIFT (1U)
+#define DMA_CHANNEL_XFERCFG_RELOAD(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_RELOAD_SHIFT)) & DMA_CHANNEL_XFERCFG_RELOAD_MASK)
+#define DMA_CHANNEL_XFERCFG_SWTRIG_MASK (0x4U)
+#define DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT (2U)
+#define DMA_CHANNEL_XFERCFG_SWTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SWTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_SWTRIG_MASK)
+#define DMA_CHANNEL_XFERCFG_CLRTRIG_MASK (0x8U)
+#define DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT (3U)
+#define DMA_CHANNEL_XFERCFG_CLRTRIG(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_CLRTRIG_SHIFT)) & DMA_CHANNEL_XFERCFG_CLRTRIG_MASK)
+#define DMA_CHANNEL_XFERCFG_SETINTA_MASK (0x10U)
+#define DMA_CHANNEL_XFERCFG_SETINTA_SHIFT (4U)
+#define DMA_CHANNEL_XFERCFG_SETINTA(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTA_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTA_MASK)
+#define DMA_CHANNEL_XFERCFG_SETINTB_MASK (0x20U)
+#define DMA_CHANNEL_XFERCFG_SETINTB_SHIFT (5U)
+#define DMA_CHANNEL_XFERCFG_SETINTB(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SETINTB_SHIFT)) & DMA_CHANNEL_XFERCFG_SETINTB_MASK)
+#define DMA_CHANNEL_XFERCFG_WIDTH_MASK (0x300U)
+#define DMA_CHANNEL_XFERCFG_WIDTH_SHIFT (8U)
+#define DMA_CHANNEL_XFERCFG_WIDTH(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_WIDTH_SHIFT)) & DMA_CHANNEL_XFERCFG_WIDTH_MASK)
+#define DMA_CHANNEL_XFERCFG_SRCINC_MASK (0x3000U)
+#define DMA_CHANNEL_XFERCFG_SRCINC_SHIFT (12U)
+#define DMA_CHANNEL_XFERCFG_SRCINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_SRCINC_SHIFT)) & DMA_CHANNEL_XFERCFG_SRCINC_MASK)
+#define DMA_CHANNEL_XFERCFG_DSTINC_MASK (0xC000U)
+#define DMA_CHANNEL_XFERCFG_DSTINC_SHIFT (14U)
+#define DMA_CHANNEL_XFERCFG_DSTINC(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_DSTINC_SHIFT)) & DMA_CHANNEL_XFERCFG_DSTINC_MASK)
+#define DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK (0x3FF0000U)
+#define DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT (16U)
+#define DMA_CHANNEL_XFERCFG_XFERCOUNT(x) (((uint32_t)(((uint32_t)(x)) << DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)) & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK)
+
+/* The count of DMA_CHANNEL_XFERCFG */
+#define DMA_CHANNEL_XFERCFG_COUNT (30U)
+
+
+/*!
+ * @}
+ */ /* end of group DMA_Register_Masks */
+
+
+/* DMA - Peripheral instance base addresses */
+/** Peripheral DMA0 base address */
+#define DMA0_BASE (0x40082000u)
+/** Peripheral DMA0 base pointer */
+#define DMA0 ((DMA_Type *)DMA0_BASE)
+/** Array initializer of DMA peripheral base addresses */
+#define DMA_BASE_ADDRS { DMA0_BASE }
+/** Array initializer of DMA peripheral base pointers */
+#define DMA_BASE_PTRS { DMA0 }
+/** Interrupt vectors for the DMA peripheral type */
+#define DMA_IRQS { DMA0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group DMA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- DMIC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMIC_Peripheral_Access_Layer DMIC Peripheral Access Layer
+ * @{
+ */
+
+/** DMIC - Register Layout Typedef */
+typedef struct {
+ struct { /* offset: 0x0, array step: 0x100 */
+ __IO uint32_t OSR; /**< Oversample Rate register 0, array offset: 0x0, array step: 0x100 */
+ __IO uint32_t DIVHFCLK; /**< DMIC Clock Register 0, array offset: 0x4, array step: 0x100 */
+ __IO uint32_t PREAC2FSCOEF; /**< Pre-Emphasis Filter Coefficient for 2 FS register, array offset: 0x8, array step: 0x100 */
+ __IO uint32_t PREAC4FSCOEF; /**< Pre-Emphasis Filter Coefficient for 4 FS register, array offset: 0xC, array step: 0x100 */
+ __IO uint32_t GAINSHIFT; /**< Decimator Gain Shift register, array offset: 0x10, array step: 0x100 */
+ uint8_t RESERVED_0[108];
+ __IO uint32_t FIFO_CTRL; /**< FIFO Control register 0, array offset: 0x80, array step: 0x100 */
+ __IO uint32_t FIFO_STATUS; /**< FIFO Status register 0, array offset: 0x84, array step: 0x100 */
+ __IO uint32_t FIFO_DATA; /**< FIFO Data Register 0, array offset: 0x88, array step: 0x100 */
+ __IO uint32_t PHY_CTRL; /**< PDM Source Configuration register 0, array offset: 0x8C, array step: 0x100 */
+ __IO uint32_t DC_CTRL; /**< DC Control register 0, array offset: 0x90, array step: 0x100 */
+ uint8_t RESERVED_1[108];
+ } CHANNEL[2];
+ uint8_t RESERVED_0[3328];
+ __IO uint32_t CHANEN; /**< Channel Enable register, offset: 0xF00 */
+ uint8_t RESERVED_1[8];
+ __IO uint32_t IOCFG; /**< I/O Configuration register, offset: 0xF0C */
+ __IO uint32_t USE2FS; /**< Use 2FS register, offset: 0xF10 */
+ uint8_t RESERVED_2[108];
+ __IO uint32_t HWVADGAIN; /**< HWVAD input gain register, offset: 0xF80 */
+ __IO uint32_t HWVADHPFS; /**< HWVAD filter control register, offset: 0xF84 */
+ __IO uint32_t HWVADST10; /**< HWVAD control register, offset: 0xF88 */
+ __IO uint32_t HWVADRSTT; /**< HWVAD filter reset register, offset: 0xF8C */
+ __IO uint32_t HWVADTHGN; /**< HWVAD noise estimator gain register, offset: 0xF90 */
+ __IO uint32_t HWVADTHGS; /**< HWVAD signal estimator gain register, offset: 0xF94 */
+ __I uint32_t HWVADLOWZ; /**< HWVAD noise envelope estimator register, offset: 0xF98 */
+ uint8_t RESERVED_3[96];
+ __I uint32_t ID; /**< Module Identification register, offset: 0xFFC */
+} DMIC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- DMIC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup DMIC_Register_Masks DMIC Register Masks
+ * @{
+ */
+
+/*! @name CHANNEL_OSR - Oversample Rate register 0 */
+#define DMIC_CHANNEL_OSR_OSR_MASK (0xFFU)
+#define DMIC_CHANNEL_OSR_OSR_SHIFT (0U)
+#define DMIC_CHANNEL_OSR_OSR(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_OSR_OSR_SHIFT)) & DMIC_CHANNEL_OSR_OSR_MASK)
+
+/* The count of DMIC_CHANNEL_OSR */
+#define DMIC_CHANNEL_OSR_COUNT (2U)
+
+/*! @name CHANNEL_DIVHFCLK - DMIC Clock Register 0 */
+#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK (0xFU)
+#define DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT (0U)
+#define DMIC_CHANNEL_DIVHFCLK_PDMDIV(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DIVHFCLK_PDMDIV_SHIFT)) & DMIC_CHANNEL_DIVHFCLK_PDMDIV_MASK)
+
+/* The count of DMIC_CHANNEL_DIVHFCLK */
+#define DMIC_CHANNEL_DIVHFCLK_COUNT (2U)
+
+/*! @name CHANNEL_PREAC2FSCOEF - Pre-Emphasis Filter Coefficient for 2 FS register */
+#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK (0x3U)
+#define DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT (0U)
+#define DMIC_CHANNEL_PREAC2FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC2FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC2FSCOEF_COMP_MASK)
+
+/* The count of DMIC_CHANNEL_PREAC2FSCOEF */
+#define DMIC_CHANNEL_PREAC2FSCOEF_COUNT (2U)
+
+/*! @name CHANNEL_PREAC4FSCOEF - Pre-Emphasis Filter Coefficient for 4 FS register */
+#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK (0x3U)
+#define DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT (0U)
+#define DMIC_CHANNEL_PREAC4FSCOEF_COMP(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PREAC4FSCOEF_COMP_SHIFT)) & DMIC_CHANNEL_PREAC4FSCOEF_COMP_MASK)
+
+/* The count of DMIC_CHANNEL_PREAC4FSCOEF */
+#define DMIC_CHANNEL_PREAC4FSCOEF_COUNT (2U)
+
+/*! @name CHANNEL_GAINSHIFT - Decimator Gain Shift register */
+#define DMIC_CHANNEL_GAINSHIFT_GAIN_MASK (0x3FU)
+#define DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT (0U)
+#define DMIC_CHANNEL_GAINSHIFT_GAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_GAINSHIFT_GAIN_SHIFT)) & DMIC_CHANNEL_GAINSHIFT_GAIN_MASK)
+
+/* The count of DMIC_CHANNEL_GAINSHIFT */
+#define DMIC_CHANNEL_GAINSHIFT_COUNT (2U)
+
+/*! @name CHANNEL_FIFO_CTRL - FIFO Control register 0 */
+#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK (0x1U)
+#define DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT (0U)
+#define DMIC_CHANNEL_FIFO_CTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_ENABLE_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_ENABLE_MASK)
+#define DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK (0x2U)
+#define DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT (1U)
+#define DMIC_CHANNEL_FIFO_CTRL_RESETN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_RESETN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_RESETN_MASK)
+#define DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK (0x4U)
+#define DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT (2U)
+#define DMIC_CHANNEL_FIFO_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_INTEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_INTEN_MASK)
+#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK (0x8U)
+#define DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT (3U)
+#define DMIC_CHANNEL_FIFO_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_DMAEN_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_DMAEN_MASK)
+#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK (0x1F0000U)
+#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT (16U)
+#define DMIC_CHANNEL_FIFO_CTRL_TRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_SHIFT)) & DMIC_CHANNEL_FIFO_CTRL_TRIGLVL_MASK)
+
+/* The count of DMIC_CHANNEL_FIFO_CTRL */
+#define DMIC_CHANNEL_FIFO_CTRL_COUNT (2U)
+
+/*! @name CHANNEL_FIFO_STATUS - FIFO Status register 0 */
+#define DMIC_CHANNEL_FIFO_STATUS_INT_MASK (0x1U)
+#define DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT (0U)
+#define DMIC_CHANNEL_FIFO_STATUS_INT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_INT_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_INT_MASK)
+#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK (0x2U)
+#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT (1U)
+#define DMIC_CHANNEL_FIFO_STATUS_OVERRUN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_OVERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_OVERRUN_MASK)
+#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK (0x4U)
+#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT (2U)
+#define DMIC_CHANNEL_FIFO_STATUS_UNDERRUN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_SHIFT)) & DMIC_CHANNEL_FIFO_STATUS_UNDERRUN_MASK)
+
+/* The count of DMIC_CHANNEL_FIFO_STATUS */
+#define DMIC_CHANNEL_FIFO_STATUS_COUNT (2U)
+
+/*! @name CHANNEL_FIFO_DATA - FIFO Data Register 0 */
+#define DMIC_CHANNEL_FIFO_DATA_DATA_MASK (0xFFFFFFU)
+#define DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT (0U)
+#define DMIC_CHANNEL_FIFO_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_FIFO_DATA_DATA_SHIFT)) & DMIC_CHANNEL_FIFO_DATA_DATA_MASK)
+
+/* The count of DMIC_CHANNEL_FIFO_DATA */
+#define DMIC_CHANNEL_FIFO_DATA_COUNT (2U)
+
+/*! @name CHANNEL_PHY_CTRL - PDM Source Configuration register 0 */
+#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK (0x1U)
+#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT (0U)
+#define DMIC_CHANNEL_PHY_CTRL_PHY_FALL(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_FALL_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_FALL_MASK)
+#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK (0x2U)
+#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT (1U)
+#define DMIC_CHANNEL_PHY_CTRL_PHY_HALF(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_PHY_CTRL_PHY_HALF_SHIFT)) & DMIC_CHANNEL_PHY_CTRL_PHY_HALF_MASK)
+
+/* The count of DMIC_CHANNEL_PHY_CTRL */
+#define DMIC_CHANNEL_PHY_CTRL_COUNT (2U)
+
+/*! @name CHANNEL_DC_CTRL - DC Control register 0 */
+#define DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK (0x3U)
+#define DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT (0U)
+#define DMIC_CHANNEL_DC_CTRL_DCPOLE(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCPOLE_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCPOLE_MASK)
+#define DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK (0xF0U)
+#define DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT (4U)
+#define DMIC_CHANNEL_DC_CTRL_DCGAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_DCGAIN_SHIFT)) & DMIC_CHANNEL_DC_CTRL_DCGAIN_MASK)
+#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK (0x100U)
+#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT (8U)
+#define DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_SHIFT)) & DMIC_CHANNEL_DC_CTRL_SATURATEAT16BIT_MASK)
+
+/* The count of DMIC_CHANNEL_DC_CTRL */
+#define DMIC_CHANNEL_DC_CTRL_COUNT (2U)
+
+/*! @name CHANEN - Channel Enable register */
+#define DMIC_CHANEN_EN_CH0_MASK (0x1U)
+#define DMIC_CHANEN_EN_CH0_SHIFT (0U)
+#define DMIC_CHANEN_EN_CH0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH0_SHIFT)) & DMIC_CHANEN_EN_CH0_MASK)
+#define DMIC_CHANEN_EN_CH1_MASK (0x2U)
+#define DMIC_CHANEN_EN_CH1_SHIFT (1U)
+#define DMIC_CHANEN_EN_CH1(x) (((uint32_t)(((uint32_t)(x)) << DMIC_CHANEN_EN_CH1_SHIFT)) & DMIC_CHANEN_EN_CH1_MASK)
+
+/*! @name IOCFG - I/O Configuration register */
+#define DMIC_IOCFG_CLK_BYPASS0_MASK (0x1U)
+#define DMIC_IOCFG_CLK_BYPASS0_SHIFT (0U)
+#define DMIC_IOCFG_CLK_BYPASS0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS0_SHIFT)) & DMIC_IOCFG_CLK_BYPASS0_MASK)
+#define DMIC_IOCFG_CLK_BYPASS1_MASK (0x2U)
+#define DMIC_IOCFG_CLK_BYPASS1_SHIFT (1U)
+#define DMIC_IOCFG_CLK_BYPASS1(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_CLK_BYPASS1_SHIFT)) & DMIC_IOCFG_CLK_BYPASS1_MASK)
+#define DMIC_IOCFG_STEREO_DATA0_MASK (0x4U)
+#define DMIC_IOCFG_STEREO_DATA0_SHIFT (2U)
+#define DMIC_IOCFG_STEREO_DATA0(x) (((uint32_t)(((uint32_t)(x)) << DMIC_IOCFG_STEREO_DATA0_SHIFT)) & DMIC_IOCFG_STEREO_DATA0_MASK)
+
+/*! @name USE2FS - Use 2FS register */
+#define DMIC_USE2FS_USE2FS_MASK (0x1U)
+#define DMIC_USE2FS_USE2FS_SHIFT (0U)
+#define DMIC_USE2FS_USE2FS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_USE2FS_USE2FS_SHIFT)) & DMIC_USE2FS_USE2FS_MASK)
+
+/*! @name HWVADGAIN - HWVAD input gain register */
+#define DMIC_HWVADGAIN_INPUTGAIN_MASK (0xFU)
+#define DMIC_HWVADGAIN_INPUTGAIN_SHIFT (0U)
+#define DMIC_HWVADGAIN_INPUTGAIN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADGAIN_INPUTGAIN_SHIFT)) & DMIC_HWVADGAIN_INPUTGAIN_MASK)
+
+/*! @name HWVADHPFS - HWVAD filter control register */
+#define DMIC_HWVADHPFS_HPFS_MASK (0x3U)
+#define DMIC_HWVADHPFS_HPFS_SHIFT (0U)
+#define DMIC_HWVADHPFS_HPFS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADHPFS_HPFS_SHIFT)) & DMIC_HWVADHPFS_HPFS_MASK)
+
+/*! @name HWVADST10 - HWVAD control register */
+#define DMIC_HWVADST10_ST10_MASK (0x1U)
+#define DMIC_HWVADST10_ST10_SHIFT (0U)
+#define DMIC_HWVADST10_ST10(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADST10_ST10_SHIFT)) & DMIC_HWVADST10_ST10_MASK)
+
+/*! @name HWVADRSTT - HWVAD filter reset register */
+#define DMIC_HWVADRSTT_RSTT_MASK (0x1U)
+#define DMIC_HWVADRSTT_RSTT_SHIFT (0U)
+#define DMIC_HWVADRSTT_RSTT(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADRSTT_RSTT_SHIFT)) & DMIC_HWVADRSTT_RSTT_MASK)
+
+/*! @name HWVADTHGN - HWVAD noise estimator gain register */
+#define DMIC_HWVADTHGN_THGN_MASK (0xFU)
+#define DMIC_HWVADTHGN_THGN_SHIFT (0U)
+#define DMIC_HWVADTHGN_THGN(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGN_THGN_SHIFT)) & DMIC_HWVADTHGN_THGN_MASK)
+
+/*! @name HWVADTHGS - HWVAD signal estimator gain register */
+#define DMIC_HWVADTHGS_THGS_MASK (0xFU)
+#define DMIC_HWVADTHGS_THGS_SHIFT (0U)
+#define DMIC_HWVADTHGS_THGS(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADTHGS_THGS_SHIFT)) & DMIC_HWVADTHGS_THGS_MASK)
+
+/*! @name HWVADLOWZ - HWVAD noise envelope estimator register */
+#define DMIC_HWVADLOWZ_LOWZ_MASK (0xFFFFU)
+#define DMIC_HWVADLOWZ_LOWZ_SHIFT (0U)
+#define DMIC_HWVADLOWZ_LOWZ(x) (((uint32_t)(((uint32_t)(x)) << DMIC_HWVADLOWZ_LOWZ_SHIFT)) & DMIC_HWVADLOWZ_LOWZ_MASK)
+
+/*! @name ID - Module Identification register */
+#define DMIC_ID_ID_MASK (0xFFFFFFFFU)
+#define DMIC_ID_ID_SHIFT (0U)
+#define DMIC_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << DMIC_ID_ID_SHIFT)) & DMIC_ID_ID_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group DMIC_Register_Masks */
+
+
+/* DMIC - Peripheral instance base addresses */
+/** Peripheral DMIC0 base address */
+#define DMIC0_BASE (0x40090000u)
+/** Peripheral DMIC0 base pointer */
+#define DMIC0 ((DMIC_Type *)DMIC0_BASE)
+/** Array initializer of DMIC peripheral base addresses */
+#define DMIC_BASE_ADDRS { DMIC0_BASE }
+/** Array initializer of DMIC peripheral base pointers */
+#define DMIC_BASE_PTRS { DMIC0 }
+/** Interrupt vectors for the DMIC peripheral type */
+#define DMIC_IRQS { DMIC0_IRQn }
+#define DMIC_HWVAD_IRQS { HWVAD0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group DMIC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- EEPROM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EEPROM_Peripheral_Access_Layer EEPROM Peripheral Access Layer
+ * @{
+ */
+
+/** EEPROM - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CMD; /**< EEPROM command register, offset: 0x0 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t RWSTATE; /**< EEPROM read wait state register, offset: 0x8 */
+ __IO uint32_t AUTOPROG; /**< EEPROM auto programming register, offset: 0xC */
+ __IO uint32_t WSTATE; /**< EEPROM wait state register, offset: 0x10 */
+ __IO uint32_t CLKDIV; /**< EEPROM clock divider register, offset: 0x14 */
+ __IO uint32_t PWRDWN; /**< EEPROM power-down register, offset: 0x18 */
+ uint8_t RESERVED_1[4028];
+ __O uint32_t INTENCLR; /**< EEPROM interrupt enable clear, offset: 0xFD8 */
+ __O uint32_t INTENSET; /**< EEPROM interrupt enable set, offset: 0xFDC */
+ __I uint32_t INTSTAT; /**< EEPROM interrupt status, offset: 0xFE0 */
+ __I uint32_t INTEN; /**< EEPROM interrupt enable, offset: 0xFE4 */
+ __O uint32_t INTSTATCLR; /**< EEPROM interrupt status clear, offset: 0xFE8 */
+ __O uint32_t INTSTATSET; /**< EEPROM interrupt status set, offset: 0xFEC */
+} EEPROM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- EEPROM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EEPROM_Register_Masks EEPROM Register Masks
+ * @{
+ */
+
+/*! @name CMD - EEPROM command register */
+#define EEPROM_CMD_CMD_MASK (0x7U)
+#define EEPROM_CMD_CMD_SHIFT (0U)
+#define EEPROM_CMD_CMD(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_CMD_CMD_SHIFT)) & EEPROM_CMD_CMD_MASK)
+
+/*! @name RWSTATE - EEPROM read wait state register */
+#define EEPROM_RWSTATE_RPHASE2_MASK (0xFFU)
+#define EEPROM_RWSTATE_RPHASE2_SHIFT (0U)
+#define EEPROM_RWSTATE_RPHASE2(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_RWSTATE_RPHASE2_SHIFT)) & EEPROM_RWSTATE_RPHASE2_MASK)
+#define EEPROM_RWSTATE_RPHASE1_MASK (0xFF00U)
+#define EEPROM_RWSTATE_RPHASE1_SHIFT (8U)
+#define EEPROM_RWSTATE_RPHASE1(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_RWSTATE_RPHASE1_SHIFT)) & EEPROM_RWSTATE_RPHASE1_MASK)
+
+/*! @name AUTOPROG - EEPROM auto programming register */
+#define EEPROM_AUTOPROG_AUTOPROG_MASK (0x3U)
+#define EEPROM_AUTOPROG_AUTOPROG_SHIFT (0U)
+#define EEPROM_AUTOPROG_AUTOPROG(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_AUTOPROG_AUTOPROG_SHIFT)) & EEPROM_AUTOPROG_AUTOPROG_MASK)
+
+/*! @name WSTATE - EEPROM wait state register */
+#define EEPROM_WSTATE_PHASE3_MASK (0xFFU)
+#define EEPROM_WSTATE_PHASE3_SHIFT (0U)
+#define EEPROM_WSTATE_PHASE3(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_WSTATE_PHASE3_SHIFT)) & EEPROM_WSTATE_PHASE3_MASK)
+#define EEPROM_WSTATE_PHASE2_MASK (0xFF00U)
+#define EEPROM_WSTATE_PHASE2_SHIFT (8U)
+#define EEPROM_WSTATE_PHASE2(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_WSTATE_PHASE2_SHIFT)) & EEPROM_WSTATE_PHASE2_MASK)
+#define EEPROM_WSTATE_PHASE1_MASK (0xFF0000U)
+#define EEPROM_WSTATE_PHASE1_SHIFT (16U)
+#define EEPROM_WSTATE_PHASE1(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_WSTATE_PHASE1_SHIFT)) & EEPROM_WSTATE_PHASE1_MASK)
+#define EEPROM_WSTATE_LCK_PARWEP_MASK (0x80000000U)
+#define EEPROM_WSTATE_LCK_PARWEP_SHIFT (31U)
+#define EEPROM_WSTATE_LCK_PARWEP(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_WSTATE_LCK_PARWEP_SHIFT)) & EEPROM_WSTATE_LCK_PARWEP_MASK)
+
+/*! @name CLKDIV - EEPROM clock divider register */
+#define EEPROM_CLKDIV_CLKDIV_MASK (0xFFFFU)
+#define EEPROM_CLKDIV_CLKDIV_SHIFT (0U)
+#define EEPROM_CLKDIV_CLKDIV(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_CLKDIV_CLKDIV_SHIFT)) & EEPROM_CLKDIV_CLKDIV_MASK)
+
+/*! @name PWRDWN - EEPROM power-down register */
+#define EEPROM_PWRDWN_PWRDWN_MASK (0x1U)
+#define EEPROM_PWRDWN_PWRDWN_SHIFT (0U)
+#define EEPROM_PWRDWN_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_PWRDWN_PWRDWN_SHIFT)) & EEPROM_PWRDWN_PWRDWN_MASK)
+
+/*! @name INTENCLR - EEPROM interrupt enable clear */
+#define EEPROM_INTENCLR_PROG_CLR_EN_MASK (0x4U)
+#define EEPROM_INTENCLR_PROG_CLR_EN_SHIFT (2U)
+#define EEPROM_INTENCLR_PROG_CLR_EN(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTENCLR_PROG_CLR_EN_SHIFT)) & EEPROM_INTENCLR_PROG_CLR_EN_MASK)
+
+/*! @name INTENSET - EEPROM interrupt enable set */
+#define EEPROM_INTENSET_PROG_SET_EN_MASK (0x4U)
+#define EEPROM_INTENSET_PROG_SET_EN_SHIFT (2U)
+#define EEPROM_INTENSET_PROG_SET_EN(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTENSET_PROG_SET_EN_SHIFT)) & EEPROM_INTENSET_PROG_SET_EN_MASK)
+
+/*! @name INTSTAT - EEPROM interrupt status */
+#define EEPROM_INTSTAT_END_OF_PROG_MASK (0x4U)
+#define EEPROM_INTSTAT_END_OF_PROG_SHIFT (2U)
+#define EEPROM_INTSTAT_END_OF_PROG(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTSTAT_END_OF_PROG_SHIFT)) & EEPROM_INTSTAT_END_OF_PROG_MASK)
+
+/*! @name INTEN - EEPROM interrupt enable */
+#define EEPROM_INTEN_EE_PROG_DONE_MASK (0x4U)
+#define EEPROM_INTEN_EE_PROG_DONE_SHIFT (2U)
+#define EEPROM_INTEN_EE_PROG_DONE(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTEN_EE_PROG_DONE_SHIFT)) & EEPROM_INTEN_EE_PROG_DONE_MASK)
+
+/*! @name INTSTATCLR - EEPROM interrupt status clear */
+#define EEPROM_INTSTATCLR_PROG_CLR_ST_MASK (0x4U)
+#define EEPROM_INTSTATCLR_PROG_CLR_ST_SHIFT (2U)
+#define EEPROM_INTSTATCLR_PROG_CLR_ST(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTSTATCLR_PROG_CLR_ST_SHIFT)) & EEPROM_INTSTATCLR_PROG_CLR_ST_MASK)
+
+/*! @name INTSTATSET - EEPROM interrupt status set */
+#define EEPROM_INTSTATSET_PROG_SET_ST_MASK (0x4U)
+#define EEPROM_INTSTATSET_PROG_SET_ST_SHIFT (2U)
+#define EEPROM_INTSTATSET_PROG_SET_ST(x) (((uint32_t)(((uint32_t)(x)) << EEPROM_INTSTATSET_PROG_SET_ST_SHIFT)) & EEPROM_INTSTATSET_PROG_SET_ST_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group EEPROM_Register_Masks */
+
+
+/* EEPROM - Peripheral instance base addresses */
+/** Peripheral EEPROM base address */
+#define EEPROM_BASE (0x40014000u)
+/** Peripheral EEPROM base pointer */
+#define EEPROM ((EEPROM_Type *)EEPROM_BASE)
+/** Array initializer of EEPROM peripheral base addresses */
+#define EEPROM_BASE_ADDRS { EEPROM_BASE }
+/** Array initializer of EEPROM peripheral base pointers */
+#define EEPROM_BASE_PTRS { EEPROM }
+/** Interrupt vectors for the EEPROM peripheral type */
+#define EEPROM_IRQS { EEPROM_IRQn }
+
+/*!
+ * @}
+ */ /* end of group EEPROM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- EMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EMC_Peripheral_Access_Layer EMC Peripheral Access Layer
+ * @{
+ */
+
+/** EMC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CONTROL; /**< Controls operation of the memory controller, offset: 0x0 */
+ __I uint32_t STATUS; /**< Provides EMC status information, offset: 0x4 */
+ __IO uint32_t CONFIG; /**< Configures operation of the memory controller, offset: 0x8 */
+ uint8_t RESERVED_0[20];
+ __IO uint32_t DYNAMICCONTROL; /**< Controls dynamic memory operation, offset: 0x20 */
+ __IO uint32_t DYNAMICREFRESH; /**< Configures dynamic memory refresh, offset: 0x24 */
+ __IO uint32_t DYNAMICREADCONFIG; /**< Configures dynamic memory read strategy, offset: 0x28 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t DYNAMICRP; /**< Precharge command period, offset: 0x30 */
+ __IO uint32_t DYNAMICRAS; /**< Active to precharge command period, offset: 0x34 */
+ __IO uint32_t DYNAMICSREX; /**< Self-refresh exit time, offset: 0x38 */
+ __IO uint32_t DYNAMICAPR; /**< Last-data-out to active command time, offset: 0x3C */
+ __IO uint32_t DYNAMICDAL; /**< Data-in to active command time, offset: 0x40 */
+ __IO uint32_t DYNAMICWR; /**< Write recovery time, offset: 0x44 */
+ __IO uint32_t DYNAMICRC; /**< Selects the active to active command period, offset: 0x48 */
+ __IO uint32_t DYNAMICRFC; /**< Selects the auto-refresh period, offset: 0x4C */
+ __IO uint32_t DYNAMICXSR; /**< Time for exit self-refresh to active command, offset: 0x50 */
+ __IO uint32_t DYNAMICRRD; /**< Latency for active bank A to active bank B, offset: 0x54 */
+ __IO uint32_t DYNAMICMRD; /**< Time for load mode register to active command, offset: 0x58 */
+ uint8_t RESERVED_2[36];
+ __IO uint32_t STATICEXTENDEDWAIT; /**< Time for long static memory read and write transfers, offset: 0x80 */
+ uint8_t RESERVED_3[124];
+ struct { /* offset: 0x100, array step: 0x20 */
+ __IO uint32_t DYNAMICCONFIG; /**< Configuration information for EMC_DYCSx, array offset: 0x100, array step: 0x20 */
+ __IO uint32_t DYNAMICRASCAS; /**< RAS and CAS latencies for EMC_DYCSx, array offset: 0x104, array step: 0x20 */
+ uint8_t RESERVED_0[24];
+ } DYNAMIC[4];
+ uint8_t RESERVED_4[128];
+ struct { /* offset: 0x200, array step: 0x20 */
+ __IO uint32_t STATICCONFIG; /**< Configuration for EMC_CSx, array offset: 0x200, array step: 0x20 */
+ __IO uint32_t STATICWAITWEN; /**< Delay from EMC_CSx to write enable, array offset: 0x204, array step: 0x20 */
+ __IO uint32_t STATICWAITOEN; /**< Delay from EMC_CSx or address change, whichever is later, to output enable, array offset: 0x208, array step: 0x20 */
+ __IO uint32_t STATICWAITRD; /**< Delay from EMC_CSx to a read access, array offset: 0x20C, array step: 0x20 */
+ __IO uint32_t STATICWAITPAGE; /**< Delay for asynchronous page mode sequential accesses for EMC_CSx, array offset: 0x210, array step: 0x20 */
+ __IO uint32_t STATICWAITWR; /**< Delay from EMC_CSx to a write access, array offset: 0x214, array step: 0x20 */
+ __IO uint32_t STATICWAITTURN; /**< Number of bus turnaround cycles EMC_CSx, array offset: 0x218, array step: 0x20 */
+ uint8_t RESERVED_0[4];
+ } STATIC[4];
+} EMC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- EMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup EMC_Register_Masks EMC Register Masks
+ * @{
+ */
+
+/*! @name CONTROL - Controls operation of the memory controller */
+#define EMC_CONTROL_E_MASK (0x1U)
+#define EMC_CONTROL_E_SHIFT (0U)
+#define EMC_CONTROL_E(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_E_SHIFT)) & EMC_CONTROL_E_MASK)
+#define EMC_CONTROL_M_MASK (0x2U)
+#define EMC_CONTROL_M_SHIFT (1U)
+#define EMC_CONTROL_M(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_M_SHIFT)) & EMC_CONTROL_M_MASK)
+#define EMC_CONTROL_L_MASK (0x4U)
+#define EMC_CONTROL_L_SHIFT (2U)
+#define EMC_CONTROL_L(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONTROL_L_SHIFT)) & EMC_CONTROL_L_MASK)
+
+/*! @name STATUS - Provides EMC status information */
+#define EMC_STATUS_B_MASK (0x1U)
+#define EMC_STATUS_B_SHIFT (0U)
+#define EMC_STATUS_B(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_B_SHIFT)) & EMC_STATUS_B_MASK)
+#define EMC_STATUS_S_MASK (0x2U)
+#define EMC_STATUS_S_SHIFT (1U)
+#define EMC_STATUS_S(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_S_SHIFT)) & EMC_STATUS_S_MASK)
+#define EMC_STATUS_SA_MASK (0x4U)
+#define EMC_STATUS_SA_SHIFT (2U)
+#define EMC_STATUS_SA(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATUS_SA_SHIFT)) & EMC_STATUS_SA_MASK)
+
+/*! @name CONFIG - Configures operation of the memory controller */
+#define EMC_CONFIG_EM_MASK (0x1U)
+#define EMC_CONFIG_EM_SHIFT (0U)
+#define EMC_CONFIG_EM(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONFIG_EM_SHIFT)) & EMC_CONFIG_EM_MASK)
+#define EMC_CONFIG_CLKR_MASK (0x100U)
+#define EMC_CONFIG_CLKR_SHIFT (8U)
+#define EMC_CONFIG_CLKR(x) (((uint32_t)(((uint32_t)(x)) << EMC_CONFIG_CLKR_SHIFT)) & EMC_CONFIG_CLKR_MASK)
+
+/*! @name DYNAMICCONTROL - Controls dynamic memory operation */
+#define EMC_DYNAMICCONTROL_CE_MASK (0x1U)
+#define EMC_DYNAMICCONTROL_CE_SHIFT (0U)
+#define EMC_DYNAMICCONTROL_CE(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_CE_SHIFT)) & EMC_DYNAMICCONTROL_CE_MASK)
+#define EMC_DYNAMICCONTROL_CS_MASK (0x2U)
+#define EMC_DYNAMICCONTROL_CS_SHIFT (1U)
+#define EMC_DYNAMICCONTROL_CS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_CS_SHIFT)) & EMC_DYNAMICCONTROL_CS_MASK)
+#define EMC_DYNAMICCONTROL_SR_MASK (0x4U)
+#define EMC_DYNAMICCONTROL_SR_SHIFT (2U)
+#define EMC_DYNAMICCONTROL_SR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_SR_SHIFT)) & EMC_DYNAMICCONTROL_SR_MASK)
+#define EMC_DYNAMICCONTROL_MMC_MASK (0x20U)
+#define EMC_DYNAMICCONTROL_MMC_SHIFT (5U)
+#define EMC_DYNAMICCONTROL_MMC(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_MMC_SHIFT)) & EMC_DYNAMICCONTROL_MMC_MASK)
+#define EMC_DYNAMICCONTROL_I_MASK (0x180U)
+#define EMC_DYNAMICCONTROL_I_SHIFT (7U)
+#define EMC_DYNAMICCONTROL_I(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICCONTROL_I_SHIFT)) & EMC_DYNAMICCONTROL_I_MASK)
+
+/*! @name DYNAMICREFRESH - Configures dynamic memory refresh */
+#define EMC_DYNAMICREFRESH_REFRESH_MASK (0x7FFU)
+#define EMC_DYNAMICREFRESH_REFRESH_SHIFT (0U)
+#define EMC_DYNAMICREFRESH_REFRESH(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICREFRESH_REFRESH_SHIFT)) & EMC_DYNAMICREFRESH_REFRESH_MASK)
+
+/*! @name DYNAMICREADCONFIG - Configures dynamic memory read strategy */
+#define EMC_DYNAMICREADCONFIG_RD_MASK (0x3U)
+#define EMC_DYNAMICREADCONFIG_RD_SHIFT (0U)
+#define EMC_DYNAMICREADCONFIG_RD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICREADCONFIG_RD_SHIFT)) & EMC_DYNAMICREADCONFIG_RD_MASK)
+
+/*! @name DYNAMICRP - Precharge command period */
+#define EMC_DYNAMICRP_TRP_MASK (0xFU)
+#define EMC_DYNAMICRP_TRP_SHIFT (0U)
+#define EMC_DYNAMICRP_TRP(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRP_TRP_SHIFT)) & EMC_DYNAMICRP_TRP_MASK)
+
+/*! @name DYNAMICRAS - Active to precharge command period */
+#define EMC_DYNAMICRAS_TRAS_MASK (0xFU)
+#define EMC_DYNAMICRAS_TRAS_SHIFT (0U)
+#define EMC_DYNAMICRAS_TRAS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRAS_TRAS_SHIFT)) & EMC_DYNAMICRAS_TRAS_MASK)
+
+/*! @name DYNAMICSREX - Self-refresh exit time */
+#define EMC_DYNAMICSREX_TSREX_MASK (0xFU)
+#define EMC_DYNAMICSREX_TSREX_SHIFT (0U)
+#define EMC_DYNAMICSREX_TSREX(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICSREX_TSREX_SHIFT)) & EMC_DYNAMICSREX_TSREX_MASK)
+
+/*! @name DYNAMICAPR - Last-data-out to active command time */
+#define EMC_DYNAMICAPR_TAPR_MASK (0xFU)
+#define EMC_DYNAMICAPR_TAPR_SHIFT (0U)
+#define EMC_DYNAMICAPR_TAPR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICAPR_TAPR_SHIFT)) & EMC_DYNAMICAPR_TAPR_MASK)
+
+/*! @name DYNAMICDAL - Data-in to active command time */
+#define EMC_DYNAMICDAL_TDAL_MASK (0xFU)
+#define EMC_DYNAMICDAL_TDAL_SHIFT (0U)
+#define EMC_DYNAMICDAL_TDAL(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICDAL_TDAL_SHIFT)) & EMC_DYNAMICDAL_TDAL_MASK)
+
+/*! @name DYNAMICWR - Write recovery time */
+#define EMC_DYNAMICWR_TWR_MASK (0xFU)
+#define EMC_DYNAMICWR_TWR_SHIFT (0U)
+#define EMC_DYNAMICWR_TWR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICWR_TWR_SHIFT)) & EMC_DYNAMICWR_TWR_MASK)
+
+/*! @name DYNAMICRC - Selects the active to active command period */
+#define EMC_DYNAMICRC_TRC_MASK (0x1FU)
+#define EMC_DYNAMICRC_TRC_SHIFT (0U)
+#define EMC_DYNAMICRC_TRC(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRC_TRC_SHIFT)) & EMC_DYNAMICRC_TRC_MASK)
+
+/*! @name DYNAMICRFC - Selects the auto-refresh period */
+#define EMC_DYNAMICRFC_TRFC_MASK (0x1FU)
+#define EMC_DYNAMICRFC_TRFC_SHIFT (0U)
+#define EMC_DYNAMICRFC_TRFC(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRFC_TRFC_SHIFT)) & EMC_DYNAMICRFC_TRFC_MASK)
+
+/*! @name DYNAMICXSR - Time for exit self-refresh to active command */
+#define EMC_DYNAMICXSR_TXSR_MASK (0x1FU)
+#define EMC_DYNAMICXSR_TXSR_SHIFT (0U)
+#define EMC_DYNAMICXSR_TXSR(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICXSR_TXSR_SHIFT)) & EMC_DYNAMICXSR_TXSR_MASK)
+
+/*! @name DYNAMICRRD - Latency for active bank A to active bank B */
+#define EMC_DYNAMICRRD_TRRD_MASK (0xFU)
+#define EMC_DYNAMICRRD_TRRD_SHIFT (0U)
+#define EMC_DYNAMICRRD_TRRD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICRRD_TRRD_SHIFT)) & EMC_DYNAMICRRD_TRRD_MASK)
+
+/*! @name DYNAMICMRD - Time for load mode register to active command */
+#define EMC_DYNAMICMRD_TMRD_MASK (0xFU)
+#define EMC_DYNAMICMRD_TMRD_SHIFT (0U)
+#define EMC_DYNAMICMRD_TMRD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMICMRD_TMRD_SHIFT)) & EMC_DYNAMICMRD_TMRD_MASK)
+
+/*! @name STATICEXTENDEDWAIT - Time for long static memory read and write transfers */
+#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_MASK (0x3FFU)
+#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_SHIFT (0U)
+#define EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_SHIFT)) & EMC_STATICEXTENDEDWAIT_EXTENDEDWAIT_MASK)
+
+/*! @name DYNAMIC_DYNAMICCONFIG - Configuration information for EMC_DYCSx */
+#define EMC_DYNAMIC_DYNAMICCONFIG_MD_MASK (0x18U)
+#define EMC_DYNAMIC_DYNAMICCONFIG_MD_SHIFT (3U)
+#define EMC_DYNAMIC_DYNAMICCONFIG_MD(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_MD_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_MD_MASK)
+#define EMC_DYNAMIC_DYNAMICCONFIG_AM0_MASK (0x1F80U)
+#define EMC_DYNAMIC_DYNAMICCONFIG_AM0_SHIFT (7U)
+#define EMC_DYNAMIC_DYNAMICCONFIG_AM0(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_AM0_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_AM0_MASK)
+#define EMC_DYNAMIC_DYNAMICCONFIG_AM1_MASK (0x4000U)
+#define EMC_DYNAMIC_DYNAMICCONFIG_AM1_SHIFT (14U)
+#define EMC_DYNAMIC_DYNAMICCONFIG_AM1(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_AM1_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_AM1_MASK)
+#define EMC_DYNAMIC_DYNAMICCONFIG_B_MASK (0x80000U)
+#define EMC_DYNAMIC_DYNAMICCONFIG_B_SHIFT (19U)
+#define EMC_DYNAMIC_DYNAMICCONFIG_B(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_B_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_B_MASK)
+#define EMC_DYNAMIC_DYNAMICCONFIG_P_MASK (0x100000U)
+#define EMC_DYNAMIC_DYNAMICCONFIG_P_SHIFT (20U)
+#define EMC_DYNAMIC_DYNAMICCONFIG_P(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICCONFIG_P_SHIFT)) & EMC_DYNAMIC_DYNAMICCONFIG_P_MASK)
+
+/* The count of EMC_DYNAMIC_DYNAMICCONFIG */
+#define EMC_DYNAMIC_DYNAMICCONFIG_COUNT (4U)
+
+/*! @name DYNAMIC_DYNAMICRASCAS - RAS and CAS latencies for EMC_DYCSx */
+#define EMC_DYNAMIC_DYNAMICRASCAS_RAS_MASK (0x3U)
+#define EMC_DYNAMIC_DYNAMICRASCAS_RAS_SHIFT (0U)
+#define EMC_DYNAMIC_DYNAMICRASCAS_RAS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICRASCAS_RAS_SHIFT)) & EMC_DYNAMIC_DYNAMICRASCAS_RAS_MASK)
+#define EMC_DYNAMIC_DYNAMICRASCAS_CAS_MASK (0x300U)
+#define EMC_DYNAMIC_DYNAMICRASCAS_CAS_SHIFT (8U)
+#define EMC_DYNAMIC_DYNAMICRASCAS_CAS(x) (((uint32_t)(((uint32_t)(x)) << EMC_DYNAMIC_DYNAMICRASCAS_CAS_SHIFT)) & EMC_DYNAMIC_DYNAMICRASCAS_CAS_MASK)
+
+/* The count of EMC_DYNAMIC_DYNAMICRASCAS */
+#define EMC_DYNAMIC_DYNAMICRASCAS_COUNT (4U)
+
+/*! @name STATIC_STATICCONFIG - Configuration for EMC_CSx */
+#define EMC_STATIC_STATICCONFIG_MW_MASK (0x3U)
+#define EMC_STATIC_STATICCONFIG_MW_SHIFT (0U)
+#define EMC_STATIC_STATICCONFIG_MW(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_MW_SHIFT)) & EMC_STATIC_STATICCONFIG_MW_MASK)
+#define EMC_STATIC_STATICCONFIG_PM_MASK (0x8U)
+#define EMC_STATIC_STATICCONFIG_PM_SHIFT (3U)
+#define EMC_STATIC_STATICCONFIG_PM(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PM_SHIFT)) & EMC_STATIC_STATICCONFIG_PM_MASK)
+#define EMC_STATIC_STATICCONFIG_PC_MASK (0x40U)
+#define EMC_STATIC_STATICCONFIG_PC_SHIFT (6U)
+#define EMC_STATIC_STATICCONFIG_PC(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PC_SHIFT)) & EMC_STATIC_STATICCONFIG_PC_MASK)
+#define EMC_STATIC_STATICCONFIG_PB_MASK (0x80U)
+#define EMC_STATIC_STATICCONFIG_PB_SHIFT (7U)
+#define EMC_STATIC_STATICCONFIG_PB(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_PB_SHIFT)) & EMC_STATIC_STATICCONFIG_PB_MASK)
+#define EMC_STATIC_STATICCONFIG_EW_MASK (0x100U)
+#define EMC_STATIC_STATICCONFIG_EW_SHIFT (8U)
+#define EMC_STATIC_STATICCONFIG_EW(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_EW_SHIFT)) & EMC_STATIC_STATICCONFIG_EW_MASK)
+#define EMC_STATIC_STATICCONFIG_B_MASK (0x80000U)
+#define EMC_STATIC_STATICCONFIG_B_SHIFT (19U)
+#define EMC_STATIC_STATICCONFIG_B(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_B_SHIFT)) & EMC_STATIC_STATICCONFIG_B_MASK)
+#define EMC_STATIC_STATICCONFIG_P_MASK (0x100000U)
+#define EMC_STATIC_STATICCONFIG_P_SHIFT (20U)
+#define EMC_STATIC_STATICCONFIG_P(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICCONFIG_P_SHIFT)) & EMC_STATIC_STATICCONFIG_P_MASK)
+
+/* The count of EMC_STATIC_STATICCONFIG */
+#define EMC_STATIC_STATICCONFIG_COUNT (4U)
+
+/*! @name STATIC_STATICWAITWEN - Delay from EMC_CSx to write enable */
+#define EMC_STATIC_STATICWAITWEN_WAITWEN_MASK (0xFU)
+#define EMC_STATIC_STATICWAITWEN_WAITWEN_SHIFT (0U)
+#define EMC_STATIC_STATICWAITWEN_WAITWEN(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITWEN_WAITWEN_SHIFT)) & EMC_STATIC_STATICWAITWEN_WAITWEN_MASK)
+
+/* The count of EMC_STATIC_STATICWAITWEN */
+#define EMC_STATIC_STATICWAITWEN_COUNT (4U)
+
+/*! @name STATIC_STATICWAITOEN - Delay from EMC_CSx or address change, whichever is later, to output enable */
+#define EMC_STATIC_STATICWAITOEN_WAITOEN_MASK (0xFU)
+#define EMC_STATIC_STATICWAITOEN_WAITOEN_SHIFT (0U)
+#define EMC_STATIC_STATICWAITOEN_WAITOEN(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITOEN_WAITOEN_SHIFT)) & EMC_STATIC_STATICWAITOEN_WAITOEN_MASK)
+
+/* The count of EMC_STATIC_STATICWAITOEN */
+#define EMC_STATIC_STATICWAITOEN_COUNT (4U)
+
+/*! @name STATIC_STATICWAITRD - Delay from EMC_CSx to a read access */
+#define EMC_STATIC_STATICWAITRD_WAITRD_MASK (0x1FU)
+#define EMC_STATIC_STATICWAITRD_WAITRD_SHIFT (0U)
+#define EMC_STATIC_STATICWAITRD_WAITRD(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITRD_WAITRD_SHIFT)) & EMC_STATIC_STATICWAITRD_WAITRD_MASK)
+
+/* The count of EMC_STATIC_STATICWAITRD */
+#define EMC_STATIC_STATICWAITRD_COUNT (4U)
+
+/*! @name STATIC_STATICWAITPAGE - Delay for asynchronous page mode sequential accesses for EMC_CSx */
+#define EMC_STATIC_STATICWAITPAGE_WAITPAGE_MASK (0x1FU)
+#define EMC_STATIC_STATICWAITPAGE_WAITPAGE_SHIFT (0U)
+#define EMC_STATIC_STATICWAITPAGE_WAITPAGE(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITPAGE_WAITPAGE_SHIFT)) & EMC_STATIC_STATICWAITPAGE_WAITPAGE_MASK)
+
+/* The count of EMC_STATIC_STATICWAITPAGE */
+#define EMC_STATIC_STATICWAITPAGE_COUNT (4U)
+
+/*! @name STATIC_STATICWAITWR - Delay from EMC_CSx to a write access */
+#define EMC_STATIC_STATICWAITWR_WAITWR_MASK (0x1FU)
+#define EMC_STATIC_STATICWAITWR_WAITWR_SHIFT (0U)
+#define EMC_STATIC_STATICWAITWR_WAITWR(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITWR_WAITWR_SHIFT)) & EMC_STATIC_STATICWAITWR_WAITWR_MASK)
+
+/* The count of EMC_STATIC_STATICWAITWR */
+#define EMC_STATIC_STATICWAITWR_COUNT (4U)
+
+/*! @name STATIC_STATICWAITTURN - Number of bus turnaround cycles EMC_CSx */
+#define EMC_STATIC_STATICWAITTURN_WAITTURN_MASK (0xFU)
+#define EMC_STATIC_STATICWAITTURN_WAITTURN_SHIFT (0U)
+#define EMC_STATIC_STATICWAITTURN_WAITTURN(x) (((uint32_t)(((uint32_t)(x)) << EMC_STATIC_STATICWAITTURN_WAITTURN_SHIFT)) & EMC_STATIC_STATICWAITTURN_WAITTURN_MASK)
+
+/* The count of EMC_STATIC_STATICWAITTURN */
+#define EMC_STATIC_STATICWAITTURN_COUNT (4U)
+
+
+/*!
+ * @}
+ */ /* end of group EMC_Register_Masks */
+
+
+/* EMC - Peripheral instance base addresses */
+/** Peripheral EMC base address */
+#define EMC_BASE (0x40081000u)
+/** Peripheral EMC base pointer */
+#define EMC ((EMC_Type *)EMC_BASE)
+/** Array initializer of EMC peripheral base addresses */
+#define EMC_BASE_ADDRS { EMC_BASE }
+/** Array initializer of EMC peripheral base pointers */
+#define EMC_BASE_PTRS { EMC }
+
+/*!
+ * @}
+ */ /* end of group EMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- ENET Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Peripheral_Access_Layer ENET Peripheral Access Layer
+ * @{
+ */
+
+/** ENET - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MAC_CONFIG; /**< MAC configuration register, offset: 0x0 */
+ __IO uint32_t MAC_EXT_CONFIG; /**< , offset: 0x4 */
+ __IO uint32_t MAC_FRAME_FILTER; /**< MAC frame filter register, offset: 0x8 */
+ __IO uint32_t MAC_WD_TIMEROUT; /**< MAC watchdog Timeout register, offset: 0xC */
+ uint8_t RESERVED_0[64];
+ __IO uint32_t MAC_VLAN_TAG; /**< MAC vlan tag register, offset: 0x50 */
+ uint8_t RESERVED_1[28];
+ __IO uint32_t MAC_TX_FLOW_CTRL_Q[2]; /**< Transmit flow control register, array offset: 0x70, array step: 0x4 */
+ uint8_t RESERVED_2[24];
+ __IO uint32_t MAC_RX_FLOW_CTRL; /**< Receive flow control register, offset: 0x90 */
+ uint8_t RESERVED_3[4];
+ __IO uint32_t MAC_TXQ_PRIO_MAP; /**< , offset: 0x98 */
+ uint8_t RESERVED_4[4];
+ __IO uint32_t MAC_RXQ_CTRL[3]; /**< Receive Queue Control 0 register 0x0000, array offset: 0xA0, array step: 0x4 */
+ uint8_t RESERVED_5[4];
+ __I uint32_t MAC_INTR_STAT; /**< Interrupt status register 0x0000, offset: 0xB0 */
+ __IO uint32_t MAC_INTR_EN; /**< Interrupt enable register 0x0000, offset: 0xB4 */
+ __I uint32_t MAC_RXTX_STAT; /**< Receive Transmit Status register, offset: 0xB8 */
+ uint8_t RESERVED_6[4];
+ __IO uint32_t MAC_PMT_CRTL_STAT; /**< , offset: 0xC0 */
+ __IO uint32_t MAC_RWAKE_FRFLT; /**< Remote wake-up frame filter, offset: 0xC4 */
+ uint8_t RESERVED_7[8];
+ __IO uint32_t MAC_LPI_CTRL_STAT; /**< LPI Control and Status Register, offset: 0xD0 */
+ __IO uint32_t MAC_LPI_TIMER_CTRL; /**< LPI Timers Control register, offset: 0xD4 */
+ __IO uint32_t MAC_LPI_ENTR_TIMR; /**< LPI entry Timer register, offset: 0xD8 */
+ __IO uint32_t MAC_1US_TIC_COUNTR; /**< , offset: 0xDC */
+ uint8_t RESERVED_8[48];
+ __IO uint32_t MAC_VERSION; /**< MAC version register, offset: 0x110 */
+ __I uint32_t MAC_DBG; /**< MAC debug register, offset: 0x114 */
+ uint8_t RESERVED_9[4];
+ __IO uint32_t MAC_HW_FEAT[3]; /**< MAC hardware feature register 0x0201, array offset: 0x11C, array step: 0x4 */
+ uint8_t RESERVED_10[216];
+ __IO uint32_t MAC_MDIO_ADDR; /**< MIDO address Register, offset: 0x200 */
+ __IO uint32_t MAC_MDIO_DATA; /**< MDIO Data register, offset: 0x204 */
+ uint8_t RESERVED_11[248];
+ __IO uint32_t MAC_ADDR_HIGH; /**< MAC address0 high register, offset: 0x300 */
+ __IO uint32_t MAC_ADDR_LOW; /**< MAC address0 low register, offset: 0x304 */
+ uint8_t RESERVED_12[2040];
+ __IO uint32_t MAC_TIMESTAMP_CTRL; /**< Time stamp control register, offset: 0xB00 */
+ __IO uint32_t MAC_SUB_SCND_INCR; /**< Sub-second increment register, offset: 0xB04 */
+ __I uint32_t MAC_SYS_TIME_SCND; /**< System time seconds register, offset: 0xB08 */
+ __I uint32_t MAC_SYS_TIME_NSCND; /**< System time nanoseconds register, offset: 0xB0C */
+ __IO uint32_t MAC_SYS_TIME_SCND_UPD; /**< , offset: 0xB10 */
+ __IO uint32_t MAC_SYS_TIME_NSCND_UPD; /**< , offset: 0xB14 */
+ __IO uint32_t MAC_SYS_TIMESTMP_ADDEND; /**< Time stamp addend register, offset: 0xB18 */
+ __IO uint32_t MAC_SYS_TIME_HWORD_SCND; /**< , offset: 0xB1C */
+ __I uint32_t MAC_SYS_TIMESTMP_STAT; /**< Time stamp status register, offset: 0xB20 */
+ uint8_t RESERVED_13[12];
+ __I uint32_t MAC_TX_TIMESTAMP_STATUS_NANOSECONDS; /**< Tx timestamp status nanoseconds, offset: 0xB30 */
+ __I uint32_t MAC_TX_TIMESTAMP_STATUS_SECONDS; /**< Tx timestamp status seconds, offset: 0xB34 */
+ uint8_t RESERVED_14[32];
+ __IO uint32_t MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND; /**< Timestamp ingress correction, offset: 0xB58 */
+ __IO uint32_t MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND; /**< Timestamp egress correction, offset: 0xB5C */
+ uint8_t RESERVED_15[160];
+ __IO uint32_t MTL_OP_MODE; /**< MTL Operation Mode Register, offset: 0xC00 */
+ uint8_t RESERVED_16[28];
+ __I uint32_t MTL_INTR_STAT; /**< MTL Interrupt Status register, offset: 0xC20 */
+ uint8_t RESERVED_17[12];
+ __IO uint32_t MTL_RXQ_DMA_MAP; /**< MTL Receive Queue and DMA Channel Mapping register, offset: 0xC30 */
+ uint8_t RESERVED_18[204];
+ struct { /* offset: 0xD00, array step: 0x40 */
+ __IO uint32_t MTL_TXQX_OP_MODE; /**< MTL TxQx Operation Mode register, array offset: 0xD00, array step: 0x40 */
+ __I uint32_t MTL_TXQX_UNDRFLW; /**< MTL TxQx Underflow register, array offset: 0xD04, array step: 0x40 */
+ __I uint32_t MTL_TXQX_DBG; /**< MTL TxQx Debug register, array offset: 0xD08, array step: 0x40 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t MTL_TXQX_ETS_CTRL; /**< MTL TxQx ETS control register, only TxQ1 support, array offset: 0xD10, array step: 0x40 */
+ __IO uint32_t MTL_TXQX_ETS_STAT; /**< MTL TxQx ETS Status register, array offset: 0xD14, array step: 0x40 */
+ __IO uint32_t MTL_TXQX_QNTM_WGHT; /**< , array offset: 0xD18, array step: 0x40 */
+ __IO uint32_t MTL_TXQX_SNDSLP_CRDT; /**< MTL TxQx SendSlopCredit register, only TxQ1 support, array offset: 0xD1C, array step: 0x40 */
+ __IO uint32_t MTL_TXQX_HI_CRDT; /**< MTL TxQx hiCredit register, only TxQ1 support, array offset: 0xD20, array step: 0x40 */
+ __IO uint32_t MTL_TXQX_LO_CRDT; /**< MTL TxQx loCredit register, only TxQ1 support, array offset: 0xD24, array step: 0x40 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t MTL_TXQX_INTCTRL_STAT; /**< , array offset: 0xD2C, array step: 0x40 */
+ __IO uint32_t MTL_RXQX_OP_MODE; /**< MTL RxQx Operation Mode register, array offset: 0xD30, array step: 0x40 */
+ __IO uint32_t MTL_RXQX_MISSPKT_OVRFLW_CNT; /**< MTL RxQx Missed Packet Overflow Counter register, array offset: 0xD34, array step: 0x40 */
+ __IO uint32_t MTL_RXQX_DBG; /**< MTL RxQx Debug register, array offset: 0xD38, array step: 0x40 */
+ __IO uint32_t MTL_RXQX_CTRL; /**< MTL RxQx Control register, array offset: 0xD3C, array step: 0x40 */
+ } MTL_QUEUE[2];
+ uint8_t RESERVED_19[640];
+ __IO uint32_t DMA_MODE; /**< DMA mode register, offset: 0x1000 */
+ __IO uint32_t DMA_SYSBUS_MODE; /**< DMA System Bus mode, offset: 0x1004 */
+ __IO uint32_t DMA_INTR_STAT; /**< DMA Interrupt status, offset: 0x1008 */
+ __IO uint32_t DMA_DBG_STAT; /**< DMA Debug Status, offset: 0x100C */
+ uint8_t RESERVED_20[240];
+ struct { /* offset: 0x1100, array step: 0x80 */
+ __IO uint32_t DMA_CHX_CTRL; /**< DMA Channelx Control, array offset: 0x1100, array step: 0x80 */
+ __IO uint32_t DMA_CHX_TX_CTRL; /**< DMA Channelx Transmit Control, array offset: 0x1104, array step: 0x80 */
+ __IO uint32_t DMA_CHX_RX_CTRL; /**< DMA Channelx Receive Control, array offset: 0x1108, array step: 0x80 */
+ uint8_t RESERVED_0[8];
+ __IO uint32_t DMA_CHX_TXDESC_LIST_ADDR; /**< , array offset: 0x1114, array step: 0x80 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t DMA_CHX_RXDESC_LIST_ADDR; /**< , array offset: 0x111C, array step: 0x80 */
+ __IO uint32_t DMA_CHX_TXDESC_TAIL_PTR; /**< , array offset: 0x1120, array step: 0x80 */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t DMA_CHX_RXDESC_TAIL_PTR; /**< , array offset: 0x1128, array step: 0x80 */
+ __IO uint32_t DMA_CHX_TXDESC_RING_LENGTH; /**< , array offset: 0x112C, array step: 0x80 */
+ __IO uint32_t DMA_CHX_RXDESC_RING_LENGTH; /**< Channelx Rx descriptor Ring Length, array offset: 0x1130, array step: 0x80 */
+ __IO uint32_t DMA_CHX_INT_EN; /**< Channelx Interrupt Enable, array offset: 0x1134, array step: 0x80 */
+ __IO uint32_t DMA_CHX_RX_INT_WDTIMER; /**< Receive Interrupt Watchdog Timer, array offset: 0x1138, array step: 0x80 */
+ __IO uint32_t DMA_CHX_SLOT_FUNC_CTRL_STAT; /**< Slot Function Control and Status, array offset: 0x113C, array step: 0x80 */
+ uint8_t RESERVED_3[4];
+ __I uint32_t DMA_CHX_CUR_HST_TXDESC; /**< Channelx Current Host Transmit descriptor, array offset: 0x1144, array step: 0x80 */
+ uint8_t RESERVED_4[4];
+ __I uint32_t DMA_CHX_CUR_HST_RXDESC; /**< , array offset: 0x114C, array step: 0x80 */
+ uint8_t RESERVED_5[4];
+ __I uint32_t DMA_CHX_CUR_HST_TXBUF; /**< , array offset: 0x1154, array step: 0x80 */
+ uint8_t RESERVED_6[4];
+ __I uint32_t DMA_CHX_CUR_HST_RXBUF; /**< Channelx Current Application Receive Buffer Address, array offset: 0x115C, array step: 0x80 */
+ __IO uint32_t DMA_CHX_STAT; /**< Channelx DMA status register, array offset: 0x1160, array step: 0x80 */
+ uint8_t RESERVED_7[28];
+ } DMA_CH[2];
+} ENET_Type;
+
+/* ----------------------------------------------------------------------------
+ -- ENET Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup ENET_Register_Masks ENET Register Masks
+ * @{
+ */
+
+/*! @name MAC_CONFIG - MAC configuration register */
+#define ENET_MAC_CONFIG_RE_MASK (0x1U)
+#define ENET_MAC_CONFIG_RE_SHIFT (0U)
+#define ENET_MAC_CONFIG_RE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_RE_SHIFT)) & ENET_MAC_CONFIG_RE_MASK)
+#define ENET_MAC_CONFIG_TE_MASK (0x2U)
+#define ENET_MAC_CONFIG_TE_SHIFT (1U)
+#define ENET_MAC_CONFIG_TE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_TE_SHIFT)) & ENET_MAC_CONFIG_TE_MASK)
+#define ENET_MAC_CONFIG_PRELEN_MASK (0xCU)
+#define ENET_MAC_CONFIG_PRELEN_SHIFT (2U)
+#define ENET_MAC_CONFIG_PRELEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_PRELEN_SHIFT)) & ENET_MAC_CONFIG_PRELEN_MASK)
+#define ENET_MAC_CONFIG_DC_MASK (0x10U)
+#define ENET_MAC_CONFIG_DC_SHIFT (4U)
+#define ENET_MAC_CONFIG_DC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DC_SHIFT)) & ENET_MAC_CONFIG_DC_MASK)
+#define ENET_MAC_CONFIG_BL_MASK (0x60U)
+#define ENET_MAC_CONFIG_BL_SHIFT (5U)
+#define ENET_MAC_CONFIG_BL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_BL_SHIFT)) & ENET_MAC_CONFIG_BL_MASK)
+#define ENET_MAC_CONFIG_DR_MASK (0x100U)
+#define ENET_MAC_CONFIG_DR_SHIFT (8U)
+#define ENET_MAC_CONFIG_DR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DR_SHIFT)) & ENET_MAC_CONFIG_DR_MASK)
+#define ENET_MAC_CONFIG_DCRS_MASK (0x200U)
+#define ENET_MAC_CONFIG_DCRS_SHIFT (9U)
+#define ENET_MAC_CONFIG_DCRS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DCRS_SHIFT)) & ENET_MAC_CONFIG_DCRS_MASK)
+#define ENET_MAC_CONFIG_DO_MASK (0x400U)
+#define ENET_MAC_CONFIG_DO_SHIFT (10U)
+#define ENET_MAC_CONFIG_DO(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DO_SHIFT)) & ENET_MAC_CONFIG_DO_MASK)
+#define ENET_MAC_CONFIG_ECRSFD_MASK (0x800U)
+#define ENET_MAC_CONFIG_ECRSFD_SHIFT (11U)
+#define ENET_MAC_CONFIG_ECRSFD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_ECRSFD_SHIFT)) & ENET_MAC_CONFIG_ECRSFD_MASK)
+#define ENET_MAC_CONFIG_LM_MASK (0x1000U)
+#define ENET_MAC_CONFIG_LM_SHIFT (12U)
+#define ENET_MAC_CONFIG_LM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_LM_SHIFT)) & ENET_MAC_CONFIG_LM_MASK)
+#define ENET_MAC_CONFIG_DM_MASK (0x2000U)
+#define ENET_MAC_CONFIG_DM_SHIFT (13U)
+#define ENET_MAC_CONFIG_DM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_DM_SHIFT)) & ENET_MAC_CONFIG_DM_MASK)
+#define ENET_MAC_CONFIG_FES_MASK (0x4000U)
+#define ENET_MAC_CONFIG_FES_SHIFT (14U)
+#define ENET_MAC_CONFIG_FES(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_FES_SHIFT)) & ENET_MAC_CONFIG_FES_MASK)
+#define ENET_MAC_CONFIG_PS_MASK (0x8000U)
+#define ENET_MAC_CONFIG_PS_SHIFT (15U)
+#define ENET_MAC_CONFIG_PS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_PS_SHIFT)) & ENET_MAC_CONFIG_PS_MASK)
+#define ENET_MAC_CONFIG_JE_MASK (0x10000U)
+#define ENET_MAC_CONFIG_JE_SHIFT (16U)
+#define ENET_MAC_CONFIG_JE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_JE_SHIFT)) & ENET_MAC_CONFIG_JE_MASK)
+#define ENET_MAC_CONFIG_JD_MASK (0x20000U)
+#define ENET_MAC_CONFIG_JD_SHIFT (17U)
+#define ENET_MAC_CONFIG_JD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_JD_SHIFT)) & ENET_MAC_CONFIG_JD_MASK)
+#define ENET_MAC_CONFIG_BE_MASK (0x40000U)
+#define ENET_MAC_CONFIG_BE_SHIFT (18U)
+#define ENET_MAC_CONFIG_BE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_BE_SHIFT)) & ENET_MAC_CONFIG_BE_MASK)
+#define ENET_MAC_CONFIG_WD_MASK (0x80000U)
+#define ENET_MAC_CONFIG_WD_SHIFT (19U)
+#define ENET_MAC_CONFIG_WD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_WD_SHIFT)) & ENET_MAC_CONFIG_WD_MASK)
+#define ENET_MAC_CONFIG_ACS_MASK (0x100000U)
+#define ENET_MAC_CONFIG_ACS_SHIFT (20U)
+#define ENET_MAC_CONFIG_ACS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_ACS_SHIFT)) & ENET_MAC_CONFIG_ACS_MASK)
+#define ENET_MAC_CONFIG_CST_MASK (0x200000U)
+#define ENET_MAC_CONFIG_CST_SHIFT (21U)
+#define ENET_MAC_CONFIG_CST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_CST_SHIFT)) & ENET_MAC_CONFIG_CST_MASK)
+#define ENET_MAC_CONFIG_S2KP_MASK (0x400000U)
+#define ENET_MAC_CONFIG_S2KP_SHIFT (22U)
+#define ENET_MAC_CONFIG_S2KP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_S2KP_SHIFT)) & ENET_MAC_CONFIG_S2KP_MASK)
+#define ENET_MAC_CONFIG_GPSLCE_MASK (0x800000U)
+#define ENET_MAC_CONFIG_GPSLCE_SHIFT (23U)
+#define ENET_MAC_CONFIG_GPSLCE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_GPSLCE_SHIFT)) & ENET_MAC_CONFIG_GPSLCE_MASK)
+#define ENET_MAC_CONFIG_IPG_MASK (0x7000000U)
+#define ENET_MAC_CONFIG_IPG_SHIFT (24U)
+#define ENET_MAC_CONFIG_IPG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_IPG_SHIFT)) & ENET_MAC_CONFIG_IPG_MASK)
+#define ENET_MAC_CONFIG_IPC_MASK (0x8000000U)
+#define ENET_MAC_CONFIG_IPC_SHIFT (27U)
+#define ENET_MAC_CONFIG_IPC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_CONFIG_IPC_SHIFT)) & ENET_MAC_CONFIG_IPC_MASK)
+
+/*! @name MAC_EXT_CONFIG - */
+#define ENET_MAC_EXT_CONFIG_GPSL_MASK (0x3FFFU)
+#define ENET_MAC_EXT_CONFIG_GPSL_SHIFT (0U)
+#define ENET_MAC_EXT_CONFIG_GPSL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_GPSL_SHIFT)) & ENET_MAC_EXT_CONFIG_GPSL_MASK)
+#define ENET_MAC_EXT_CONFIG_DCRCC_MASK (0x10000U)
+#define ENET_MAC_EXT_CONFIG_DCRCC_SHIFT (16U)
+#define ENET_MAC_EXT_CONFIG_DCRCC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_DCRCC_SHIFT)) & ENET_MAC_EXT_CONFIG_DCRCC_MASK)
+#define ENET_MAC_EXT_CONFIG_SPEN_MASK (0x20000U)
+#define ENET_MAC_EXT_CONFIG_SPEN_SHIFT (17U)
+#define ENET_MAC_EXT_CONFIG_SPEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_SPEN_SHIFT)) & ENET_MAC_EXT_CONFIG_SPEN_MASK)
+#define ENET_MAC_EXT_CONFIG_USP_MASK (0x40000U)
+#define ENET_MAC_EXT_CONFIG_USP_SHIFT (18U)
+#define ENET_MAC_EXT_CONFIG_USP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_EXT_CONFIG_USP_SHIFT)) & ENET_MAC_EXT_CONFIG_USP_MASK)
+
+/*! @name MAC_FRAME_FILTER - MAC frame filter register */
+#define ENET_MAC_FRAME_FILTER_PR_MASK (0x1U)
+#define ENET_MAC_FRAME_FILTER_PR_SHIFT (0U)
+#define ENET_MAC_FRAME_FILTER_PR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PR_SHIFT)) & ENET_MAC_FRAME_FILTER_PR_MASK)
+#define ENET_MAC_FRAME_FILTER_DAIF_MASK (0x8U)
+#define ENET_MAC_FRAME_FILTER_DAIF_SHIFT (3U)
+#define ENET_MAC_FRAME_FILTER_DAIF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_DAIF_SHIFT)) & ENET_MAC_FRAME_FILTER_DAIF_MASK)
+#define ENET_MAC_FRAME_FILTER_PM_MASK (0x10U)
+#define ENET_MAC_FRAME_FILTER_PM_SHIFT (4U)
+#define ENET_MAC_FRAME_FILTER_PM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PM_SHIFT)) & ENET_MAC_FRAME_FILTER_PM_MASK)
+#define ENET_MAC_FRAME_FILTER_DBF_MASK (0x20U)
+#define ENET_MAC_FRAME_FILTER_DBF_SHIFT (5U)
+#define ENET_MAC_FRAME_FILTER_DBF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_DBF_SHIFT)) & ENET_MAC_FRAME_FILTER_DBF_MASK)
+#define ENET_MAC_FRAME_FILTER_PCF_MASK (0xC0U)
+#define ENET_MAC_FRAME_FILTER_PCF_SHIFT (6U)
+#define ENET_MAC_FRAME_FILTER_PCF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_PCF_SHIFT)) & ENET_MAC_FRAME_FILTER_PCF_MASK)
+#define ENET_MAC_FRAME_FILTER_SAIF_MASK (0x100U)
+#define ENET_MAC_FRAME_FILTER_SAIF_SHIFT (8U)
+#define ENET_MAC_FRAME_FILTER_SAIF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_SAIF_SHIFT)) & ENET_MAC_FRAME_FILTER_SAIF_MASK)
+#define ENET_MAC_FRAME_FILTER_SAF_MASK (0x200U)
+#define ENET_MAC_FRAME_FILTER_SAF_SHIFT (9U)
+#define ENET_MAC_FRAME_FILTER_SAF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_SAF_SHIFT)) & ENET_MAC_FRAME_FILTER_SAF_MASK)
+#define ENET_MAC_FRAME_FILTER_RA_MASK (0x80000000U)
+#define ENET_MAC_FRAME_FILTER_RA_SHIFT (31U)
+#define ENET_MAC_FRAME_FILTER_RA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_FRAME_FILTER_RA_SHIFT)) & ENET_MAC_FRAME_FILTER_RA_MASK)
+
+/*! @name MAC_WD_TIMEROUT - MAC watchdog Timeout register */
+#define ENET_MAC_WD_TIMEROUT_WTO_MASK (0xFU)
+#define ENET_MAC_WD_TIMEROUT_WTO_SHIFT (0U)
+#define ENET_MAC_WD_TIMEROUT_WTO(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_WD_TIMEROUT_WTO_SHIFT)) & ENET_MAC_WD_TIMEROUT_WTO_MASK)
+#define ENET_MAC_WD_TIMEROUT_PWE_MASK (0x100U)
+#define ENET_MAC_WD_TIMEROUT_PWE_SHIFT (8U)
+#define ENET_MAC_WD_TIMEROUT_PWE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_WD_TIMEROUT_PWE_SHIFT)) & ENET_MAC_WD_TIMEROUT_PWE_MASK)
+
+/*! @name MAC_VLAN_TAG - MAC vlan tag register */
+#define ENET_MAC_VLAN_TAG_VL_MASK (0xFFFFU)
+#define ENET_MAC_VLAN_TAG_VL_SHIFT (0U)
+#define ENET_MAC_VLAN_TAG_VL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VL_SHIFT)) & ENET_MAC_VLAN_TAG_VL_MASK)
+#define ENET_MAC_VLAN_TAG_ETV_MASK (0x10000U)
+#define ENET_MAC_VLAN_TAG_ETV_SHIFT (16U)
+#define ENET_MAC_VLAN_TAG_ETV(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ETV_SHIFT)) & ENET_MAC_VLAN_TAG_ETV_MASK)
+#define ENET_MAC_VLAN_TAG_VTIM_MASK (0x20000U)
+#define ENET_MAC_VLAN_TAG_VTIM_SHIFT (17U)
+#define ENET_MAC_VLAN_TAG_VTIM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VTIM_SHIFT)) & ENET_MAC_VLAN_TAG_VTIM_MASK)
+#define ENET_MAC_VLAN_TAG_ESVL_MASK (0x40000U)
+#define ENET_MAC_VLAN_TAG_ESVL_SHIFT (18U)
+#define ENET_MAC_VLAN_TAG_ESVL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ESVL_SHIFT)) & ENET_MAC_VLAN_TAG_ESVL_MASK)
+#define ENET_MAC_VLAN_TAG_ERSVLM_MASK (0x80000U)
+#define ENET_MAC_VLAN_TAG_ERSVLM_SHIFT (19U)
+#define ENET_MAC_VLAN_TAG_ERSVLM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ERSVLM_SHIFT)) & ENET_MAC_VLAN_TAG_ERSVLM_MASK)
+#define ENET_MAC_VLAN_TAG_DOVLTC_MASK (0x100000U)
+#define ENET_MAC_VLAN_TAG_DOVLTC_SHIFT (20U)
+#define ENET_MAC_VLAN_TAG_DOVLTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_DOVLTC_SHIFT)) & ENET_MAC_VLAN_TAG_DOVLTC_MASK)
+#define ENET_MAC_VLAN_TAG_EVLS_MASK (0x600000U)
+#define ENET_MAC_VLAN_TAG_EVLS_SHIFT (21U)
+#define ENET_MAC_VLAN_TAG_EVLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EVLS_SHIFT)) & ENET_MAC_VLAN_TAG_EVLS_MASK)
+#define ENET_MAC_VLAN_TAG_EVLRXS_MASK (0x1000000U)
+#define ENET_MAC_VLAN_TAG_EVLRXS_SHIFT (24U)
+#define ENET_MAC_VLAN_TAG_EVLRXS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EVLRXS_SHIFT)) & ENET_MAC_VLAN_TAG_EVLRXS_MASK)
+#define ENET_MAC_VLAN_TAG_VTHM_MASK (0x2000000U)
+#define ENET_MAC_VLAN_TAG_VTHM_SHIFT (25U)
+#define ENET_MAC_VLAN_TAG_VTHM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_VTHM_SHIFT)) & ENET_MAC_VLAN_TAG_VTHM_MASK)
+#define ENET_MAC_VLAN_TAG_EDVLP_MASK (0x4000000U)
+#define ENET_MAC_VLAN_TAG_EDVLP_SHIFT (26U)
+#define ENET_MAC_VLAN_TAG_EDVLP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EDVLP_SHIFT)) & ENET_MAC_VLAN_TAG_EDVLP_MASK)
+#define ENET_MAC_VLAN_TAG_ERIVLT_MASK (0x8000000U)
+#define ENET_MAC_VLAN_TAG_ERIVLT_SHIFT (27U)
+#define ENET_MAC_VLAN_TAG_ERIVLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_ERIVLT_SHIFT)) & ENET_MAC_VLAN_TAG_ERIVLT_MASK)
+#define ENET_MAC_VLAN_TAG_EIVLS_MASK (0x30000000U)
+#define ENET_MAC_VLAN_TAG_EIVLS_SHIFT (28U)
+#define ENET_MAC_VLAN_TAG_EIVLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EIVLS_SHIFT)) & ENET_MAC_VLAN_TAG_EIVLS_MASK)
+#define ENET_MAC_VLAN_TAG_EIVLRXS_MASK (0x80000000U)
+#define ENET_MAC_VLAN_TAG_EIVLRXS_SHIFT (31U)
+#define ENET_MAC_VLAN_TAG_EIVLRXS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VLAN_TAG_EIVLRXS_SHIFT)) & ENET_MAC_VLAN_TAG_EIVLRXS_MASK)
+
+/*! @name MAC_TX_FLOW_CTRL_Q - Transmit flow control register */
+#define ENET_MAC_TX_FLOW_CTRL_Q_FCB_MASK (0x1U)
+#define ENET_MAC_TX_FLOW_CTRL_Q_FCB_SHIFT (0U)
+#define ENET_MAC_TX_FLOW_CTRL_Q_FCB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_FCB_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_FCB_MASK)
+#define ENET_MAC_TX_FLOW_CTRL_Q_TFE_MASK (0x2U)
+#define ENET_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT (1U)
+#define ENET_MAC_TX_FLOW_CTRL_Q_TFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_TFE_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_TFE_MASK)
+#define ENET_MAC_TX_FLOW_CTRL_Q_PLT_MASK (0x70U)
+#define ENET_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT (4U)
+#define ENET_MAC_TX_FLOW_CTRL_Q_PLT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_PLT_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_PLT_MASK)
+#define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK (0x80U)
+#define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT (7U)
+#define ENET_MAC_TX_FLOW_CTRL_Q_DZPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_DZPQ_MASK)
+#define ENET_MAC_TX_FLOW_CTRL_Q_PT_MASK (0xFFFF0000U)
+#define ENET_MAC_TX_FLOW_CTRL_Q_PT_SHIFT (16U)
+#define ENET_MAC_TX_FLOW_CTRL_Q_PT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_FLOW_CTRL_Q_PT_SHIFT)) & ENET_MAC_TX_FLOW_CTRL_Q_PT_MASK)
+
+/* The count of ENET_MAC_TX_FLOW_CTRL_Q */
+#define ENET_MAC_TX_FLOW_CTRL_Q_COUNT (2U)
+
+/*! @name MAC_RX_FLOW_CTRL - Receive flow control register */
+#define ENET_MAC_RX_FLOW_CTRL_RFE_MASK (0x1U)
+#define ENET_MAC_RX_FLOW_CTRL_RFE_SHIFT (0U)
+#define ENET_MAC_RX_FLOW_CTRL_RFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_FLOW_CTRL_RFE_SHIFT)) & ENET_MAC_RX_FLOW_CTRL_RFE_MASK)
+#define ENET_MAC_RX_FLOW_CTRL_UP_MASK (0x2U)
+#define ENET_MAC_RX_FLOW_CTRL_UP_SHIFT (1U)
+#define ENET_MAC_RX_FLOW_CTRL_UP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RX_FLOW_CTRL_UP_SHIFT)) & ENET_MAC_RX_FLOW_CTRL_UP_MASK)
+
+/*! @name MAC_TXQ_PRIO_MAP - */
+#define ENET_MAC_TXQ_PRIO_MAP_PSTQ0_MASK (0xFFU)
+#define ENET_MAC_TXQ_PRIO_MAP_PSTQ0_SHIFT (0U)
+#define ENET_MAC_TXQ_PRIO_MAP_PSTQ0(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TXQ_PRIO_MAP_PSTQ0_SHIFT)) & ENET_MAC_TXQ_PRIO_MAP_PSTQ0_MASK)
+#define ENET_MAC_TXQ_PRIO_MAP_PSTQ1_MASK (0xFF00U)
+#define ENET_MAC_TXQ_PRIO_MAP_PSTQ1_SHIFT (8U)
+#define ENET_MAC_TXQ_PRIO_MAP_PSTQ1(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TXQ_PRIO_MAP_PSTQ1_SHIFT)) & ENET_MAC_TXQ_PRIO_MAP_PSTQ1_MASK)
+
+/*! @name MAC_RXQ_CTRL - Receive Queue Control 0 register 0x0000 */
+#define ENET_MAC_RXQ_CTRL_RXQ0EN_MASK (0x3U)
+#define ENET_MAC_RXQ_CTRL_RXQ0EN_SHIFT (0U)
+#define ENET_MAC_RXQ_CTRL_RXQ0EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_RXQ0EN_SHIFT)) & ENET_MAC_RXQ_CTRL_RXQ0EN_MASK)
+#define ENET_MAC_RXQ_CTRL_PSRQ0_MASK (0xFFU)
+#define ENET_MAC_RXQ_CTRL_PSRQ0_SHIFT (0U)
+#define ENET_MAC_RXQ_CTRL_PSRQ0(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ0_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ0_MASK)
+#define ENET_MAC_RXQ_CTRL_AVCPQ_MASK (0x7U)
+#define ENET_MAC_RXQ_CTRL_AVCPQ_SHIFT (0U)
+#define ENET_MAC_RXQ_CTRL_AVCPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_AVCPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_AVCPQ_MASK)
+#define ENET_MAC_RXQ_CTRL_RXQ1EN_MASK (0xCU)
+#define ENET_MAC_RXQ_CTRL_RXQ1EN_SHIFT (2U)
+#define ENET_MAC_RXQ_CTRL_RXQ1EN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_RXQ1EN_SHIFT)) & ENET_MAC_RXQ_CTRL_RXQ1EN_MASK)
+#define ENET_MAC_RXQ_CTRL_AVPTPQ_MASK (0x70U)
+#define ENET_MAC_RXQ_CTRL_AVPTPQ_SHIFT (4U)
+#define ENET_MAC_RXQ_CTRL_AVPTPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_AVPTPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_AVPTPQ_MASK)
+#define ENET_MAC_RXQ_CTRL_PSRQ1_MASK (0xFF00U)
+#define ENET_MAC_RXQ_CTRL_PSRQ1_SHIFT (8U)
+#define ENET_MAC_RXQ_CTRL_PSRQ1(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ1_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ1_MASK)
+#define ENET_MAC_RXQ_CTRL_UPQ_MASK (0x7000U)
+#define ENET_MAC_RXQ_CTRL_UPQ_SHIFT (12U)
+#define ENET_MAC_RXQ_CTRL_UPQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_UPQ_SHIFT)) & ENET_MAC_RXQ_CTRL_UPQ_MASK)
+#define ENET_MAC_RXQ_CTRL_PSRQ2_MASK (0xFF0000U)
+#define ENET_MAC_RXQ_CTRL_PSRQ2_SHIFT (16U)
+#define ENET_MAC_RXQ_CTRL_PSRQ2(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ2_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ2_MASK)
+#define ENET_MAC_RXQ_CTRL_MCBCQ_MASK (0x70000U)
+#define ENET_MAC_RXQ_CTRL_MCBCQ_SHIFT (16U)
+#define ENET_MAC_RXQ_CTRL_MCBCQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_MCBCQ_SHIFT)) & ENET_MAC_RXQ_CTRL_MCBCQ_MASK)
+#define ENET_MAC_RXQ_CTRL_MCBCQEN_MASK (0x100000U)
+#define ENET_MAC_RXQ_CTRL_MCBCQEN_SHIFT (20U)
+#define ENET_MAC_RXQ_CTRL_MCBCQEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_MCBCQEN_SHIFT)) & ENET_MAC_RXQ_CTRL_MCBCQEN_MASK)
+#define ENET_MAC_RXQ_CTRL_PSRQ3_MASK (0xFF000000U)
+#define ENET_MAC_RXQ_CTRL_PSRQ3_SHIFT (24U)
+#define ENET_MAC_RXQ_CTRL_PSRQ3(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXQ_CTRL_PSRQ3_SHIFT)) & ENET_MAC_RXQ_CTRL_PSRQ3_MASK)
+
+/* The count of ENET_MAC_RXQ_CTRL */
+#define ENET_MAC_RXQ_CTRL_COUNT (3U)
+
+/*! @name MAC_INTR_STAT - Interrupt status register 0x0000 */
+#define ENET_MAC_INTR_STAT_PHYIS_MASK (0x8U)
+#define ENET_MAC_INTR_STAT_PHYIS_SHIFT (3U)
+#define ENET_MAC_INTR_STAT_PHYIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_PHYIS_SHIFT)) & ENET_MAC_INTR_STAT_PHYIS_MASK)
+#define ENET_MAC_INTR_STAT_PMTIS_MASK (0x10U)
+#define ENET_MAC_INTR_STAT_PMTIS_SHIFT (4U)
+#define ENET_MAC_INTR_STAT_PMTIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_PMTIS_SHIFT)) & ENET_MAC_INTR_STAT_PMTIS_MASK)
+#define ENET_MAC_INTR_STAT_LPIIS_MASK (0x20U)
+#define ENET_MAC_INTR_STAT_LPIIS_SHIFT (5U)
+#define ENET_MAC_INTR_STAT_LPIIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_LPIIS_SHIFT)) & ENET_MAC_INTR_STAT_LPIIS_MASK)
+#define ENET_MAC_INTR_STAT_TSIS_MASK (0x1000U)
+#define ENET_MAC_INTR_STAT_TSIS_SHIFT (12U)
+#define ENET_MAC_INTR_STAT_TSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_TSIS_SHIFT)) & ENET_MAC_INTR_STAT_TSIS_MASK)
+#define ENET_MAC_INTR_STAT_TXSTSIS_MASK (0x2000U)
+#define ENET_MAC_INTR_STAT_TXSTSIS_SHIFT (13U)
+#define ENET_MAC_INTR_STAT_TXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_TXSTSIS_SHIFT)) & ENET_MAC_INTR_STAT_TXSTSIS_MASK)
+#define ENET_MAC_INTR_STAT_RXSTSIS_MASK (0x4000U)
+#define ENET_MAC_INTR_STAT_RXSTSIS_SHIFT (14U)
+#define ENET_MAC_INTR_STAT_RXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_STAT_RXSTSIS_SHIFT)) & ENET_MAC_INTR_STAT_RXSTSIS_MASK)
+
+/*! @name MAC_INTR_EN - Interrupt enable register 0x0000 */
+#define ENET_MAC_INTR_EN_PHYIE_MASK (0x8U)
+#define ENET_MAC_INTR_EN_PHYIE_SHIFT (3U)
+#define ENET_MAC_INTR_EN_PHYIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_PHYIE_SHIFT)) & ENET_MAC_INTR_EN_PHYIE_MASK)
+#define ENET_MAC_INTR_EN_PMTIE_MASK (0x10U)
+#define ENET_MAC_INTR_EN_PMTIE_SHIFT (4U)
+#define ENET_MAC_INTR_EN_PMTIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_PMTIE_SHIFT)) & ENET_MAC_INTR_EN_PMTIE_MASK)
+#define ENET_MAC_INTR_EN_LPIIE_MASK (0x20U)
+#define ENET_MAC_INTR_EN_LPIIE_SHIFT (5U)
+#define ENET_MAC_INTR_EN_LPIIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_LPIIE_SHIFT)) & ENET_MAC_INTR_EN_LPIIE_MASK)
+#define ENET_MAC_INTR_EN_TSIE_MASK (0x1000U)
+#define ENET_MAC_INTR_EN_TSIE_SHIFT (12U)
+#define ENET_MAC_INTR_EN_TSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_TSIE_SHIFT)) & ENET_MAC_INTR_EN_TSIE_MASK)
+#define ENET_MAC_INTR_EN_TXSTSIE_MASK (0x2000U)
+#define ENET_MAC_INTR_EN_TXSTSIE_SHIFT (13U)
+#define ENET_MAC_INTR_EN_TXSTSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_TXSTSIE_SHIFT)) & ENET_MAC_INTR_EN_TXSTSIE_MASK)
+#define ENET_MAC_INTR_EN_RXSTSIS_MASK (0x4000U)
+#define ENET_MAC_INTR_EN_RXSTSIS_SHIFT (14U)
+#define ENET_MAC_INTR_EN_RXSTSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_INTR_EN_RXSTSIS_SHIFT)) & ENET_MAC_INTR_EN_RXSTSIS_MASK)
+
+/*! @name MAC_RXTX_STAT - Receive Transmit Status register */
+#define ENET_MAC_RXTX_STAT_TJT_MASK (0x1U)
+#define ENET_MAC_RXTX_STAT_TJT_SHIFT (0U)
+#define ENET_MAC_RXTX_STAT_TJT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_TJT_SHIFT)) & ENET_MAC_RXTX_STAT_TJT_MASK)
+#define ENET_MAC_RXTX_STAT_NCARR_MASK (0x2U)
+#define ENET_MAC_RXTX_STAT_NCARR_SHIFT (1U)
+#define ENET_MAC_RXTX_STAT_NCARR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_NCARR_SHIFT)) & ENET_MAC_RXTX_STAT_NCARR_MASK)
+#define ENET_MAC_RXTX_STAT_LCARR_MASK (0x4U)
+#define ENET_MAC_RXTX_STAT_LCARR_SHIFT (2U)
+#define ENET_MAC_RXTX_STAT_LCARR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_LCARR_SHIFT)) & ENET_MAC_RXTX_STAT_LCARR_MASK)
+#define ENET_MAC_RXTX_STAT_EXDEF_MASK (0x8U)
+#define ENET_MAC_RXTX_STAT_EXDEF_SHIFT (3U)
+#define ENET_MAC_RXTX_STAT_EXDEF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_EXDEF_SHIFT)) & ENET_MAC_RXTX_STAT_EXDEF_MASK)
+#define ENET_MAC_RXTX_STAT_LCOL_MASK (0x10U)
+#define ENET_MAC_RXTX_STAT_LCOL_SHIFT (4U)
+#define ENET_MAC_RXTX_STAT_LCOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_LCOL_SHIFT)) & ENET_MAC_RXTX_STAT_LCOL_MASK)
+#define ENET_MAC_RXTX_STAT_EXCOL_MASK (0x20U)
+#define ENET_MAC_RXTX_STAT_EXCOL_SHIFT (5U)
+#define ENET_MAC_RXTX_STAT_EXCOL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_EXCOL_SHIFT)) & ENET_MAC_RXTX_STAT_EXCOL_MASK)
+#define ENET_MAC_RXTX_STAT_RWT_MASK (0x100U)
+#define ENET_MAC_RXTX_STAT_RWT_SHIFT (8U)
+#define ENET_MAC_RXTX_STAT_RWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RXTX_STAT_RWT_SHIFT)) & ENET_MAC_RXTX_STAT_RWT_MASK)
+
+/*! @name MAC_PMT_CRTL_STAT - */
+#define ENET_MAC_PMT_CRTL_STAT_PWRDWN_MASK (0x1U)
+#define ENET_MAC_PMT_CRTL_STAT_PWRDWN_SHIFT (0U)
+#define ENET_MAC_PMT_CRTL_STAT_PWRDWN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_PWRDWN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_PWRDWN_MASK)
+#define ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_MASK (0x2U)
+#define ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_SHIFT (1U)
+#define ENET_MAC_PMT_CRTL_STAT_MGKPKTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_MGKPKTEN_MASK)
+#define ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_MASK (0x4U)
+#define ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_SHIFT (2U)
+#define ENET_MAC_PMT_CRTL_STAT_RWKPKTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPKTEN_MASK)
+#define ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_MASK (0x20U)
+#define ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_SHIFT (5U)
+#define ENET_MAC_PMT_CRTL_STAT_MGKPRCVD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_MGKPRCVD_MASK)
+#define ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_MASK (0x40U)
+#define ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_SHIFT (6U)
+#define ENET_MAC_PMT_CRTL_STAT_RWKPRCVD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPRCVD_MASK)
+#define ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_MASK (0x200U)
+#define ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_SHIFT (9U)
+#define ENET_MAC_PMT_CRTL_STAT_GLBLUCAST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_GLBLUCAST_MASK)
+#define ENET_MAC_PMT_CRTL_STAT_RWKPFE_MASK (0x400U)
+#define ENET_MAC_PMT_CRTL_STAT_RWKPFE_SHIFT (10U)
+#define ENET_MAC_PMT_CRTL_STAT_RWKPFE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPFE_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPFE_MASK)
+#define ENET_MAC_PMT_CRTL_STAT_RWKPTR_MASK (0x1F000000U)
+#define ENET_MAC_PMT_CRTL_STAT_RWKPTR_SHIFT (24U)
+#define ENET_MAC_PMT_CRTL_STAT_RWKPTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKPTR_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKPTR_MASK)
+#define ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_MASK (0x80000000U)
+#define ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_SHIFT (31U)
+#define ENET_MAC_PMT_CRTL_STAT_RWKFILTRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_SHIFT)) & ENET_MAC_PMT_CRTL_STAT_RWKFILTRST_MASK)
+
+/*! @name MAC_RWAKE_FRFLT - Remote wake-up frame filter */
+#define ENET_MAC_RWAKE_FRFLT_ADDR_MASK (0xFFFFFFFFU)
+#define ENET_MAC_RWAKE_FRFLT_ADDR_SHIFT (0U)
+#define ENET_MAC_RWAKE_FRFLT_ADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_RWAKE_FRFLT_ADDR_SHIFT)) & ENET_MAC_RWAKE_FRFLT_ADDR_MASK)
+
+/*! @name MAC_LPI_CTRL_STAT - LPI Control and Status Register */
+#define ENET_MAC_LPI_CTRL_STAT_TLPIEN_MASK (0x1U)
+#define ENET_MAC_LPI_CTRL_STAT_TLPIEN_SHIFT (0U)
+#define ENET_MAC_LPI_CTRL_STAT_TLPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIEN_MASK)
+#define ENET_MAC_LPI_CTRL_STAT_TLPIEX_MASK (0x2U)
+#define ENET_MAC_LPI_CTRL_STAT_TLPIEX_SHIFT (1U)
+#define ENET_MAC_LPI_CTRL_STAT_TLPIEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIEX_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIEX_MASK)
+#define ENET_MAC_LPI_CTRL_STAT_RLPIEN_MASK (0x4U)
+#define ENET_MAC_LPI_CTRL_STAT_RLPIEN_SHIFT (2U)
+#define ENET_MAC_LPI_CTRL_STAT_RLPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIEN_MASK)
+#define ENET_MAC_LPI_CTRL_STAT_RLPIEX_MASK (0x8U)
+#define ENET_MAC_LPI_CTRL_STAT_RLPIEX_SHIFT (3U)
+#define ENET_MAC_LPI_CTRL_STAT_RLPIEX(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIEX_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIEX_MASK)
+#define ENET_MAC_LPI_CTRL_STAT_TLPIST_MASK (0x100U)
+#define ENET_MAC_LPI_CTRL_STAT_TLPIST_SHIFT (8U)
+#define ENET_MAC_LPI_CTRL_STAT_TLPIST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_TLPIST_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_TLPIST_MASK)
+#define ENET_MAC_LPI_CTRL_STAT_RLPIST_MASK (0x200U)
+#define ENET_MAC_LPI_CTRL_STAT_RLPIST_SHIFT (9U)
+#define ENET_MAC_LPI_CTRL_STAT_RLPIST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_RLPIST_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_RLPIST_MASK)
+#define ENET_MAC_LPI_CTRL_STAT_LPIEN_MASK (0x10000U)
+#define ENET_MAC_LPI_CTRL_STAT_LPIEN_SHIFT (16U)
+#define ENET_MAC_LPI_CTRL_STAT_LPIEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPIEN_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPIEN_MASK)
+#define ENET_MAC_LPI_CTRL_STAT_PLS_MASK (0x20000U)
+#define ENET_MAC_LPI_CTRL_STAT_PLS_SHIFT (17U)
+#define ENET_MAC_LPI_CTRL_STAT_PLS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_PLS_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_PLS_MASK)
+#define ENET_MAC_LPI_CTRL_STAT_LPITXA_MASK (0x80000U)
+#define ENET_MAC_LPI_CTRL_STAT_LPITXA_SHIFT (19U)
+#define ENET_MAC_LPI_CTRL_STAT_LPITXA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPITXA_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPITXA_MASK)
+#define ENET_MAC_LPI_CTRL_STAT_LPIATE_MASK (0x100000U)
+#define ENET_MAC_LPI_CTRL_STAT_LPIATE_SHIFT (20U)
+#define ENET_MAC_LPI_CTRL_STAT_LPIATE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPIATE_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPIATE_MASK)
+#define ENET_MAC_LPI_CTRL_STAT_LPITCSE_MASK (0x200000U)
+#define ENET_MAC_LPI_CTRL_STAT_LPITCSE_SHIFT (21U)
+#define ENET_MAC_LPI_CTRL_STAT_LPITCSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_CTRL_STAT_LPITCSE_SHIFT)) & ENET_MAC_LPI_CTRL_STAT_LPITCSE_MASK)
+
+/*! @name MAC_LPI_TIMER_CTRL - LPI Timers Control register */
+#define ENET_MAC_LPI_TIMER_CTRL_TWT_MASK (0xFFFFU)
+#define ENET_MAC_LPI_TIMER_CTRL_TWT_SHIFT (0U)
+#define ENET_MAC_LPI_TIMER_CTRL_TWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_TIMER_CTRL_TWT_SHIFT)) & ENET_MAC_LPI_TIMER_CTRL_TWT_MASK)
+#define ENET_MAC_LPI_TIMER_CTRL_LST_MASK (0x3FF0000U)
+#define ENET_MAC_LPI_TIMER_CTRL_LST_SHIFT (16U)
+#define ENET_MAC_LPI_TIMER_CTRL_LST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_TIMER_CTRL_LST_SHIFT)) & ENET_MAC_LPI_TIMER_CTRL_LST_MASK)
+
+/*! @name MAC_LPI_ENTR_TIMR - LPI entry Timer register */
+#define ENET_MAC_LPI_ENTR_TIMR_LPIET_MASK (0xFFFF8U)
+#define ENET_MAC_LPI_ENTR_TIMR_LPIET_SHIFT (3U)
+#define ENET_MAC_LPI_ENTR_TIMR_LPIET(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_LPI_ENTR_TIMR_LPIET_SHIFT)) & ENET_MAC_LPI_ENTR_TIMR_LPIET_MASK)
+
+/*! @name MAC_1US_TIC_COUNTR - */
+#define ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_MASK (0xFFFU)
+#define ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_SHIFT (0U)
+#define ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_SHIFT)) & ENET_MAC_1US_TIC_COUNTR_TIC_1US_CNTR_MASK)
+
+/*! @name MAC_VERSION - MAC version register */
+#define ENET_MAC_VERSION_SNPVER_MASK (0xFFU)
+#define ENET_MAC_VERSION_SNPVER_SHIFT (0U)
+#define ENET_MAC_VERSION_SNPVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VERSION_SNPVER_SHIFT)) & ENET_MAC_VERSION_SNPVER_MASK)
+#define ENET_MAC_VERSION_USERVER_MASK (0xFF00U)
+#define ENET_MAC_VERSION_USERVER_SHIFT (8U)
+#define ENET_MAC_VERSION_USERVER(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_VERSION_USERVER_SHIFT)) & ENET_MAC_VERSION_USERVER_MASK)
+
+/*! @name MAC_DBG - MAC debug register */
+#define ENET_MAC_DBG_REPESTS_MASK (0x1U)
+#define ENET_MAC_DBG_REPESTS_SHIFT (0U)
+#define ENET_MAC_DBG_REPESTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_REPESTS_SHIFT)) & ENET_MAC_DBG_REPESTS_MASK)
+#define ENET_MAC_DBG_RFCFCSTS_MASK (0x6U)
+#define ENET_MAC_DBG_RFCFCSTS_SHIFT (1U)
+#define ENET_MAC_DBG_RFCFCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_RFCFCSTS_SHIFT)) & ENET_MAC_DBG_RFCFCSTS_MASK)
+#define ENET_MAC_DBG_TPESTS_MASK (0x10000U)
+#define ENET_MAC_DBG_TPESTS_SHIFT (16U)
+#define ENET_MAC_DBG_TPESTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_TPESTS_SHIFT)) & ENET_MAC_DBG_TPESTS_MASK)
+#define ENET_MAC_DBG_TFCSTS_MASK (0x60000U)
+#define ENET_MAC_DBG_TFCSTS_SHIFT (17U)
+#define ENET_MAC_DBG_TFCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_DBG_TFCSTS_SHIFT)) & ENET_MAC_DBG_TFCSTS_MASK)
+
+/*! @name MAC_HW_FEAT - MAC hardware feature register 0x0201 */
+#define ENET_MAC_HW_FEAT_RXFIFOSIZE_MASK (0x1FU)
+#define ENET_MAC_HW_FEAT_RXFIFOSIZE_SHIFT (0U)
+#define ENET_MAC_HW_FEAT_RXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXFIFOSIZE_SHIFT)) & ENET_MAC_HW_FEAT_RXFIFOSIZE_MASK)
+#define ENET_MAC_HW_FEAT_RXQCNT_MASK (0xFU)
+#define ENET_MAC_HW_FEAT_RXQCNT_SHIFT (0U)
+#define ENET_MAC_HW_FEAT_RXQCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXQCNT_SHIFT)) & ENET_MAC_HW_FEAT_RXQCNT_MASK)
+#define ENET_MAC_HW_FEAT_MIISEL_MASK (0x1U)
+#define ENET_MAC_HW_FEAT_MIISEL_SHIFT (0U)
+#define ENET_MAC_HW_FEAT_MIISEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MIISEL_SHIFT)) & ENET_MAC_HW_FEAT_MIISEL_MASK)
+#define ENET_MAC_HW_FEAT_HDSEL_MASK (0x4U)
+#define ENET_MAC_HW_FEAT_HDSEL_SHIFT (2U)
+#define ENET_MAC_HW_FEAT_HDSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_HDSEL_SHIFT)) & ENET_MAC_HW_FEAT_HDSEL_MASK)
+#define ENET_MAC_HW_FEAT_VLHASH_MASK (0x10U)
+#define ENET_MAC_HW_FEAT_VLHASH_SHIFT (4U)
+#define ENET_MAC_HW_FEAT_VLHASH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_VLHASH_SHIFT)) & ENET_MAC_HW_FEAT_VLHASH_MASK)
+#define ENET_MAC_HW_FEAT_SMASEL_MASK (0x20U)
+#define ENET_MAC_HW_FEAT_SMASEL_SHIFT (5U)
+#define ENET_MAC_HW_FEAT_SMASEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_SMASEL_SHIFT)) & ENET_MAC_HW_FEAT_SMASEL_MASK)
+#define ENET_MAC_HW_FEAT_TXQCNT_MASK (0x3C0U)
+#define ENET_MAC_HW_FEAT_TXQCNT_SHIFT (6U)
+#define ENET_MAC_HW_FEAT_TXQCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXQCNT_SHIFT)) & ENET_MAC_HW_FEAT_TXQCNT_MASK)
+#define ENET_MAC_HW_FEAT_RWKSEL_MASK (0x40U)
+#define ENET_MAC_HW_FEAT_RWKSEL_SHIFT (6U)
+#define ENET_MAC_HW_FEAT_RWKSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RWKSEL_SHIFT)) & ENET_MAC_HW_FEAT_RWKSEL_MASK)
+#define ENET_MAC_HW_FEAT_TXFIFOSIZE_MASK (0x7C0U)
+#define ENET_MAC_HW_FEAT_TXFIFOSIZE_SHIFT (6U)
+#define ENET_MAC_HW_FEAT_TXFIFOSIZE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXFIFOSIZE_SHIFT)) & ENET_MAC_HW_FEAT_TXFIFOSIZE_MASK)
+#define ENET_MAC_HW_FEAT_MGKSEL_MASK (0x80U)
+#define ENET_MAC_HW_FEAT_MGKSEL_SHIFT (7U)
+#define ENET_MAC_HW_FEAT_MGKSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MGKSEL_SHIFT)) & ENET_MAC_HW_FEAT_MGKSEL_MASK)
+#define ENET_MAC_HW_FEAT_MMCSEL_MASK (0x100U)
+#define ENET_MAC_HW_FEAT_MMCSEL_SHIFT (8U)
+#define ENET_MAC_HW_FEAT_MMCSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_MMCSEL_SHIFT)) & ENET_MAC_HW_FEAT_MMCSEL_MASK)
+#define ENET_MAC_HW_FEAT_ARPOFFSEL_MASK (0x200U)
+#define ENET_MAC_HW_FEAT_ARPOFFSEL_SHIFT (9U)
+#define ENET_MAC_HW_FEAT_ARPOFFSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ARPOFFSEL_SHIFT)) & ENET_MAC_HW_FEAT_ARPOFFSEL_MASK)
+#define ENET_MAC_HW_FEAT_OSTEN_MASK (0x800U)
+#define ENET_MAC_HW_FEAT_OSTEN_SHIFT (11U)
+#define ENET_MAC_HW_FEAT_OSTEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_OSTEN_SHIFT)) & ENET_MAC_HW_FEAT_OSTEN_MASK)
+#define ENET_MAC_HW_FEAT_RXCHCNT_MASK (0xF000U)
+#define ENET_MAC_HW_FEAT_RXCHCNT_SHIFT (12U)
+#define ENET_MAC_HW_FEAT_RXCHCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXCHCNT_SHIFT)) & ENET_MAC_HW_FEAT_RXCHCNT_MASK)
+#define ENET_MAC_HW_FEAT_TSSEL_MASK (0x1000U)
+#define ENET_MAC_HW_FEAT_TSSEL_SHIFT (12U)
+#define ENET_MAC_HW_FEAT_TSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSSEL_SHIFT)) & ENET_MAC_HW_FEAT_TSSEL_MASK)
+#define ENET_MAC_HW_FEAT_PTOEN_MASK (0x1000U)
+#define ENET_MAC_HW_FEAT_PTOEN_SHIFT (12U)
+#define ENET_MAC_HW_FEAT_PTOEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_PTOEN_SHIFT)) & ENET_MAC_HW_FEAT_PTOEN_MASK)
+#define ENET_MAC_HW_FEAT_EEESEL_MASK (0x2000U)
+#define ENET_MAC_HW_FEAT_EEESEL_SHIFT (13U)
+#define ENET_MAC_HW_FEAT_EEESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_EEESEL_SHIFT)) & ENET_MAC_HW_FEAT_EEESEL_MASK)
+#define ENET_MAC_HW_FEAT_ADVTHWORD_MASK (0x2000U)
+#define ENET_MAC_HW_FEAT_ADVTHWORD_SHIFT (13U)
+#define ENET_MAC_HW_FEAT_ADVTHWORD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ADVTHWORD_SHIFT)) & ENET_MAC_HW_FEAT_ADVTHWORD_MASK)
+#define ENET_MAC_HW_FEAT_ADDR64_MASK (0xC000U)
+#define ENET_MAC_HW_FEAT_ADDR64_SHIFT (14U)
+#define ENET_MAC_HW_FEAT_ADDR64(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ADDR64_SHIFT)) & ENET_MAC_HW_FEAT_ADDR64_MASK)
+#define ENET_MAC_HW_FEAT_TXCOESEL_MASK (0x4000U)
+#define ENET_MAC_HW_FEAT_TXCOESEL_SHIFT (14U)
+#define ENET_MAC_HW_FEAT_TXCOESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXCOESEL_SHIFT)) & ENET_MAC_HW_FEAT_TXCOESEL_MASK)
+#define ENET_MAC_HW_FEAT_DCBEN_MASK (0x10000U)
+#define ENET_MAC_HW_FEAT_DCBEN_SHIFT (16U)
+#define ENET_MAC_HW_FEAT_DCBEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_DCBEN_SHIFT)) & ENET_MAC_HW_FEAT_DCBEN_MASK)
+#define ENET_MAC_HW_FEAT_RXCOESEL_MASK (0x10000U)
+#define ENET_MAC_HW_FEAT_RXCOESEL_SHIFT (16U)
+#define ENET_MAC_HW_FEAT_RXCOESEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_RXCOESEL_SHIFT)) & ENET_MAC_HW_FEAT_RXCOESEL_MASK)
+#define ENET_MAC_HW_FEAT_SPEN_MASK (0x20000U)
+#define ENET_MAC_HW_FEAT_SPEN_SHIFT (17U)
+#define ENET_MAC_HW_FEAT_SPEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_SPEN_SHIFT)) & ENET_MAC_HW_FEAT_SPEN_MASK)
+#define ENET_MAC_HW_FEAT_TXCHCNT_MASK (0x3C0000U)
+#define ENET_MAC_HW_FEAT_TXCHCNT_SHIFT (18U)
+#define ENET_MAC_HW_FEAT_TXCHCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TXCHCNT_SHIFT)) & ENET_MAC_HW_FEAT_TXCHCNT_MASK)
+#define ENET_MAC_HW_FEAT_TSOEN_MASK (0x40000U)
+#define ENET_MAC_HW_FEAT_TSOEN_SHIFT (18U)
+#define ENET_MAC_HW_FEAT_TSOEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSOEN_SHIFT)) & ENET_MAC_HW_FEAT_TSOEN_MASK)
+#define ENET_MAC_HW_FEAT_DBGMEMA_MASK (0x80000U)
+#define ENET_MAC_HW_FEAT_DBGMEMA_SHIFT (19U)
+#define ENET_MAC_HW_FEAT_DBGMEMA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_DBGMEMA_SHIFT)) & ENET_MAC_HW_FEAT_DBGMEMA_MASK)
+#define ENET_MAC_HW_FEAT_AVSEL_MASK (0x100000U)
+#define ENET_MAC_HW_FEAT_AVSEL_SHIFT (20U)
+#define ENET_MAC_HW_FEAT_AVSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_AVSEL_SHIFT)) & ENET_MAC_HW_FEAT_AVSEL_MASK)
+#define ENET_MAC_HW_FEAT_LPMODEEN_MASK (0x800000U)
+#define ENET_MAC_HW_FEAT_LPMODEEN_SHIFT (23U)
+#define ENET_MAC_HW_FEAT_LPMODEEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_LPMODEEN_SHIFT)) & ENET_MAC_HW_FEAT_LPMODEEN_MASK)
+#define ENET_MAC_HW_FEAT_PPSOUTNUM_MASK (0x7000000U)
+#define ENET_MAC_HW_FEAT_PPSOUTNUM_SHIFT (24U)
+#define ENET_MAC_HW_FEAT_PPSOUTNUM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_PPSOUTNUM_SHIFT)) & ENET_MAC_HW_FEAT_PPSOUTNUM_MASK)
+#define ENET_MAC_HW_FEAT_HASHTBLSZ_MASK (0x3000000U)
+#define ENET_MAC_HW_FEAT_HASHTBLSZ_SHIFT (24U)
+#define ENET_MAC_HW_FEAT_HASHTBLSZ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_HASHTBLSZ_SHIFT)) & ENET_MAC_HW_FEAT_HASHTBLSZ_MASK)
+#define ENET_MAC_HW_FEAT_TSSTSSEL_MASK (0x6000000U)
+#define ENET_MAC_HW_FEAT_TSSTSSEL_SHIFT (25U)
+#define ENET_MAC_HW_FEAT_TSSTSSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_TSSTSSEL_SHIFT)) & ENET_MAC_HW_FEAT_TSSTSSEL_MASK)
+#define ENET_MAC_HW_FEAT_L3_L4_FILTER_MASK (0x78000000U)
+#define ENET_MAC_HW_FEAT_L3_L4_FILTER_SHIFT (27U)
+#define ENET_MAC_HW_FEAT_L3_L4_FILTER(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_L3_L4_FILTER_SHIFT)) & ENET_MAC_HW_FEAT_L3_L4_FILTER_MASK)
+#define ENET_MAC_HW_FEAT_AUXSNAPNUM_MASK (0x70000000U)
+#define ENET_MAC_HW_FEAT_AUXSNAPNUM_SHIFT (28U)
+#define ENET_MAC_HW_FEAT_AUXSNAPNUM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_AUXSNAPNUM_SHIFT)) & ENET_MAC_HW_FEAT_AUXSNAPNUM_MASK)
+#define ENET_MAC_HW_FEAT_ACTPHYSEL_MASK (0x70000000U)
+#define ENET_MAC_HW_FEAT_ACTPHYSEL_SHIFT (28U)
+#define ENET_MAC_HW_FEAT_ACTPHYSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_HW_FEAT_ACTPHYSEL_SHIFT)) & ENET_MAC_HW_FEAT_ACTPHYSEL_MASK)
+
+/* The count of ENET_MAC_HW_FEAT */
+#define ENET_MAC_HW_FEAT_COUNT (3U)
+
+/*! @name MAC_MDIO_ADDR - MIDO address Register */
+#define ENET_MAC_MDIO_ADDR_MB_MASK (0x1U)
+#define ENET_MAC_MDIO_ADDR_MB_SHIFT (0U)
+#define ENET_MAC_MDIO_ADDR_MB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_MB_SHIFT)) & ENET_MAC_MDIO_ADDR_MB_MASK)
+#define ENET_MAC_MDIO_ADDR_MOC_MASK (0xCU)
+#define ENET_MAC_MDIO_ADDR_MOC_SHIFT (2U)
+#define ENET_MAC_MDIO_ADDR_MOC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_MOC_SHIFT)) & ENET_MAC_MDIO_ADDR_MOC_MASK)
+#define ENET_MAC_MDIO_ADDR_CR_MASK (0xF00U)
+#define ENET_MAC_MDIO_ADDR_CR_SHIFT (8U)
+#define ENET_MAC_MDIO_ADDR_CR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_CR_SHIFT)) & ENET_MAC_MDIO_ADDR_CR_MASK)
+#define ENET_MAC_MDIO_ADDR_NTC_MASK (0x7000U)
+#define ENET_MAC_MDIO_ADDR_NTC_SHIFT (12U)
+#define ENET_MAC_MDIO_ADDR_NTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_NTC_SHIFT)) & ENET_MAC_MDIO_ADDR_NTC_MASK)
+#define ENET_MAC_MDIO_ADDR_RDA_MASK (0x1F0000U)
+#define ENET_MAC_MDIO_ADDR_RDA_SHIFT (16U)
+#define ENET_MAC_MDIO_ADDR_RDA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_RDA_SHIFT)) & ENET_MAC_MDIO_ADDR_RDA_MASK)
+#define ENET_MAC_MDIO_ADDR_PA_MASK (0x3E00000U)
+#define ENET_MAC_MDIO_ADDR_PA_SHIFT (21U)
+#define ENET_MAC_MDIO_ADDR_PA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_PA_SHIFT)) & ENET_MAC_MDIO_ADDR_PA_MASK)
+#define ENET_MAC_MDIO_ADDR_BTB_MASK (0x4000000U)
+#define ENET_MAC_MDIO_ADDR_BTB_SHIFT (26U)
+#define ENET_MAC_MDIO_ADDR_BTB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_BTB_SHIFT)) & ENET_MAC_MDIO_ADDR_BTB_MASK)
+#define ENET_MAC_MDIO_ADDR_PSE_MASK (0x8000000U)
+#define ENET_MAC_MDIO_ADDR_PSE_SHIFT (27U)
+#define ENET_MAC_MDIO_ADDR_PSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_ADDR_PSE_SHIFT)) & ENET_MAC_MDIO_ADDR_PSE_MASK)
+
+/*! @name MAC_MDIO_DATA - MDIO Data register */
+#define ENET_MAC_MDIO_DATA_MD_MASK (0xFFFFU)
+#define ENET_MAC_MDIO_DATA_MD_SHIFT (0U)
+#define ENET_MAC_MDIO_DATA_MD(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_MDIO_DATA_MD_SHIFT)) & ENET_MAC_MDIO_DATA_MD_MASK)
+
+/*! @name MAC_ADDR_HIGH - MAC address0 high register */
+#define ENET_MAC_ADDR_HIGH_A47_32_MASK (0xFFFFU)
+#define ENET_MAC_ADDR_HIGH_A47_32_SHIFT (0U)
+#define ENET_MAC_ADDR_HIGH_A47_32(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_A47_32_SHIFT)) & ENET_MAC_ADDR_HIGH_A47_32_MASK)
+#define ENET_MAC_ADDR_HIGH_DCS_MASK (0x10000U)
+#define ENET_MAC_ADDR_HIGH_DCS_SHIFT (16U)
+#define ENET_MAC_ADDR_HIGH_DCS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_DCS_SHIFT)) & ENET_MAC_ADDR_HIGH_DCS_MASK)
+#define ENET_MAC_ADDR_HIGH_AE_MASK (0x80000000U)
+#define ENET_MAC_ADDR_HIGH_AE_SHIFT (31U)
+#define ENET_MAC_ADDR_HIGH_AE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_HIGH_AE_SHIFT)) & ENET_MAC_ADDR_HIGH_AE_MASK)
+
+/*! @name MAC_ADDR_LOW - MAC address0 low register */
+#define ENET_MAC_ADDR_LOW_A31_0_MASK (0xFFFFFFFFU)
+#define ENET_MAC_ADDR_LOW_A31_0_SHIFT (0U)
+#define ENET_MAC_ADDR_LOW_A31_0(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_ADDR_LOW_A31_0_SHIFT)) & ENET_MAC_ADDR_LOW_A31_0_MASK)
+
+/*! @name MAC_TIMESTAMP_CTRL - Time stamp control register */
+#define ENET_MAC_TIMESTAMP_CTRL_TSENA_MASK (0x1U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSENA_SHIFT (0U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENA_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_MASK (0x2U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_SHIFT (1U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSCFUPDT_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSINIT_MASK (0x4U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSINIT_SHIFT (2U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSINIT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSINIT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSINIT_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSUPDT_MASK (0x8U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSUPDT_SHIFT (3U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSUPDT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSUPDT_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSUPDT_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSTRIG_MASK (0x10U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSTRIG_SHIFT (4U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSTRIG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSTRIG_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSTRIG_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TADDREG_MASK (0x20U)
+#define ENET_MAC_TIMESTAMP_CTRL_TADDREG_SHIFT (5U)
+#define ENET_MAC_TIMESTAMP_CTRL_TADDREG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TADDREG_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TADDREG_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSENALL_MASK (0x100U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSENALL_SHIFT (8U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSENALL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENALL_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENALL_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK (0x200U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_SHIFT (9U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSCTRLSSR_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_MASK (0x400U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_SHIFT (10U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSVER2ENA_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPENA_MASK (0x800U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPENA_SHIFT (11U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPENA_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_MASK (0x1000U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_SHIFT (12U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPV6ENA_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_MASK (0x2000U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_SHIFT (13U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSIPV4ENA_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_MASK (0x4000U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_SHIFT (14U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSEVTENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSEVTENA_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_MASK (0x8000U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_SHIFT (15U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSMSTRENA_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_MASK (0x30000U)
+#define ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_SHIFT (16U)
+#define ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_SNAPTYPSEL_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_MASK (0x40000U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_SHIFT (18U)
+#define ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TSENMACADDR_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_MASK (0x1000000U)
+#define ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_SHIFT (24U)
+#define ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_TXTTSSTSM_MASK)
+#define ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_MASK (0x10000000U)
+#define ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_SHIFT (28U)
+#define ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_SHIFT)) & ENET_MAC_TIMESTAMP_CTRL_AV8021ASMEN_MASK)
+
+/*! @name MAC_SUB_SCND_INCR - Sub-second increment register */
+#define ENET_MAC_SUB_SCND_INCR_SSINC_MASK (0xFF0000U)
+#define ENET_MAC_SUB_SCND_INCR_SSINC_SHIFT (16U)
+#define ENET_MAC_SUB_SCND_INCR_SSINC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SUB_SCND_INCR_SSINC_SHIFT)) & ENET_MAC_SUB_SCND_INCR_SSINC_MASK)
+
+/*! @name MAC_SYS_TIME_SCND - System time seconds register */
+#define ENET_MAC_SYS_TIME_SCND_TSS_MASK (0xFFFFFFFFU)
+#define ENET_MAC_SYS_TIME_SCND_TSS_SHIFT (0U)
+#define ENET_MAC_SYS_TIME_SCND_TSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_SCND_TSS_SHIFT)) & ENET_MAC_SYS_TIME_SCND_TSS_MASK)
+
+/*! @name MAC_SYS_TIME_NSCND - System time nanoseconds register */
+#define ENET_MAC_SYS_TIME_NSCND_TSSS_MASK (0x7FFFFFFFU)
+#define ENET_MAC_SYS_TIME_NSCND_TSSS_SHIFT (0U)
+#define ENET_MAC_SYS_TIME_NSCND_TSSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_TSSS_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_TSSS_MASK)
+
+/*! @name MAC_SYS_TIME_SCND_UPD - */
+#define ENET_MAC_SYS_TIME_SCND_UPD_TSS_MASK (0xFFFFFFFFU)
+#define ENET_MAC_SYS_TIME_SCND_UPD_TSS_SHIFT (0U)
+#define ENET_MAC_SYS_TIME_SCND_UPD_TSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_SCND_UPD_TSS_SHIFT)) & ENET_MAC_SYS_TIME_SCND_UPD_TSS_MASK)
+
+/*! @name MAC_SYS_TIME_NSCND_UPD - */
+#define ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_MASK (0x7FFFFFFFU)
+#define ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_SHIFT (0U)
+#define ENET_MAC_SYS_TIME_NSCND_UPD_TSSS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_UPD_TSSS_MASK)
+#define ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_MASK (0x80000000U)
+#define ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_SHIFT (31U)
+#define ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_SHIFT)) & ENET_MAC_SYS_TIME_NSCND_UPD_ADDSUB_MASK)
+
+/*! @name MAC_SYS_TIMESTMP_ADDEND - Time stamp addend register */
+#define ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_MASK (0xFFFFFFFFU)
+#define ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_SHIFT (0U)
+#define ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_SHIFT)) & ENET_MAC_SYS_TIMESTMP_ADDEND_TSAR_MASK)
+
+/*! @name MAC_SYS_TIME_HWORD_SCND - */
+#define ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_MASK (0xFFFFU)
+#define ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_SHIFT (0U)
+#define ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_SHIFT)) & ENET_MAC_SYS_TIME_HWORD_SCND_TSHWR_MASK)
+
+/*! @name MAC_SYS_TIMESTMP_STAT - Time stamp status register */
+#define ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_MASK (0x1U)
+#define ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_SHIFT (0U)
+#define ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_SHIFT)) & ENET_MAC_SYS_TIMESTMP_STAT_TSSOVF_MASK)
+
+/*! @name MAC_TX_TIMESTAMP_STATUS_NANOSECONDS - Tx timestamp status nanoseconds */
+#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_MASK (0x7FFFFFFFU)
+#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_SHIFT (0U)
+#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSLO_MASK)
+#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_MASK (0x80000000U)
+#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_SHIFT (31U)
+#define ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_NANOSECONDS_TXTSSTSMIS_MASK)
+
+/*! @name MAC_TX_TIMESTAMP_STATUS_SECONDS - Tx timestamp status seconds */
+#define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_MASK (0xFFFFFFFFU)
+#define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_SHIFT (0U)
+#define ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_SHIFT)) & ENET_MAC_TX_TIMESTAMP_STATUS_SECONDS_TXTSSTSHI_MASK)
+
+/*! @name MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND - Timestamp ingress correction */
+#define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK (0xFFFFFFFFU)
+#define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT (0U)
+#define ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_SHIFT)) & ENET_MAC_TIMESTAMP_INGRESS_CORR_NANOSECOND_TSIC_MASK)
+
+/*! @name MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND - Timestamp egress correction */
+#define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK (0xFFFFFFFFU)
+#define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT (0U)
+#define ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_SHIFT)) & ENET_MAC_TIMESTAMP_EGRESS_CORR_NANOSECOND_TSEC_MASK)
+
+/*! @name MTL_OP_MODE - MTL Operation Mode Register */
+#define ENET_MTL_OP_MODE_DTXSTS_MASK (0x2U)
+#define ENET_MTL_OP_MODE_DTXSTS_SHIFT (1U)
+#define ENET_MTL_OP_MODE_DTXSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_DTXSTS_SHIFT)) & ENET_MTL_OP_MODE_DTXSTS_MASK)
+#define ENET_MTL_OP_MODE_RAA_MASK (0x4U)
+#define ENET_MTL_OP_MODE_RAA_SHIFT (2U)
+#define ENET_MTL_OP_MODE_RAA(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_RAA_SHIFT)) & ENET_MTL_OP_MODE_RAA_MASK)
+#define ENET_MTL_OP_MODE_SCHALG_MASK (0x60U)
+#define ENET_MTL_OP_MODE_SCHALG_SHIFT (5U)
+#define ENET_MTL_OP_MODE_SCHALG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_SCHALG_SHIFT)) & ENET_MTL_OP_MODE_SCHALG_MASK)
+#define ENET_MTL_OP_MODE_CNTPRST_MASK (0x100U)
+#define ENET_MTL_OP_MODE_CNTPRST_SHIFT (8U)
+#define ENET_MTL_OP_MODE_CNTPRST(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_CNTPRST_SHIFT)) & ENET_MTL_OP_MODE_CNTPRST_MASK)
+#define ENET_MTL_OP_MODE_CNTCLR_MASK (0x200U)
+#define ENET_MTL_OP_MODE_CNTCLR_SHIFT (9U)
+#define ENET_MTL_OP_MODE_CNTCLR(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_OP_MODE_CNTCLR_SHIFT)) & ENET_MTL_OP_MODE_CNTCLR_MASK)
+
+/*! @name MTL_INTR_STAT - MTL Interrupt Status register */
+#define ENET_MTL_INTR_STAT_Q0IS_MASK (0x1U)
+#define ENET_MTL_INTR_STAT_Q0IS_SHIFT (0U)
+#define ENET_MTL_INTR_STAT_Q0IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_INTR_STAT_Q0IS_SHIFT)) & ENET_MTL_INTR_STAT_Q0IS_MASK)
+#define ENET_MTL_INTR_STAT_Q1IS_MASK (0x2U)
+#define ENET_MTL_INTR_STAT_Q1IS_SHIFT (1U)
+#define ENET_MTL_INTR_STAT_Q1IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_INTR_STAT_Q1IS_SHIFT)) & ENET_MTL_INTR_STAT_Q1IS_MASK)
+
+/*! @name MTL_RXQ_DMA_MAP - MTL Receive Queue and DMA Channel Mapping register */
+#define ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_MASK (0x1U)
+#define ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_SHIFT (0U)
+#define ENET_MTL_RXQ_DMA_MAP_Q0MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q0MDMACH_MASK)
+#define ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_MASK (0x10U)
+#define ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_SHIFT (4U)
+#define ENET_MTL_RXQ_DMA_MAP_Q0DDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q0DDMACH_MASK)
+#define ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_MASK (0x100U)
+#define ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_SHIFT (8U)
+#define ENET_MTL_RXQ_DMA_MAP_Q1MDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q1MDMACH_MASK)
+#define ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_MASK (0x1000U)
+#define ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_SHIFT (12U)
+#define ENET_MTL_RXQ_DMA_MAP_Q1DDMACH(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_SHIFT)) & ENET_MTL_RXQ_DMA_MAP_Q1DDMACH_MASK)
+
+/*! @name MTL_QUEUE_MTL_TXQX_OP_MODE - MTL TxQx Operation Mode register */
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_MASK (0x1U)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_SHIFT (0U)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_FTQ_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_MASK (0x2U)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_SHIFT (1U)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TSF_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_MASK (0xCU)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_SHIFT (2U)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TXQEN_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_MASK (0x70U)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_SHIFT (4U)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TTC_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_MASK (0x70000U)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_SHIFT (16U)
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_TQS_MASK)
+
+/* The count of ENET_MTL_QUEUE_MTL_TXQX_OP_MODE */
+#define ENET_MTL_QUEUE_MTL_TXQX_OP_MODE_COUNT (2U)
+
+/*! @name MTL_QUEUE_MTL_TXQX_UNDRFLW - MTL TxQx Underflow register */
+#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK (0x7FFU)
+#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT (0U)
+#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFFRMCNT_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK (0x800U)
+#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT (11U)
+#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_UFCNTOVF_MASK)
+
+/* The count of ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW */
+#define ENET_MTL_QUEUE_MTL_TXQX_UNDRFLW_COUNT (2U)
+
+/*! @name MTL_QUEUE_MTL_TXQX_DBG - MTL TxQx Debug register */
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_MASK (0x1U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_SHIFT (0U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQPAUSED_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_MASK (0x6U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_SHIFT (1U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TRCSTS_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_MASK (0x8U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_SHIFT (3U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TWCSTS_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_MASK (0x10U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_SHIFT (4U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXQSTS_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_MASK (0x20U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_SHIFT (5U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_TXSTSFSTS_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_MASK (0x70000U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_SHIFT (16U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_PTXQ_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_MASK (0x700000U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_SHIFT (20U)
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_DBG_STSXSTSF_MASK)
+
+/* The count of ENET_MTL_QUEUE_MTL_TXQX_DBG */
+#define ENET_MTL_QUEUE_MTL_TXQX_DBG_COUNT (2U)
+
+/*! @name MTL_QUEUE_MTL_TXQX_ETS_CTRL - MTL TxQx ETS control register, only TxQ1 support */
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_MASK (0x4U)
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_SHIFT (2U)
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_AVALG_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_MASK (0x8U)
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_SHIFT (3U)
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_CC_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_MASK (0x70U)
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_SHIFT (4U)
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_SLC_MASK)
+
+/* The count of ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL */
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_CTRL_COUNT (2U)
+
+/*! @name MTL_QUEUE_MTL_TXQX_ETS_STAT - MTL TxQx ETS Status register */
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_MASK (0xFFFFFFU)
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_SHIFT (0U)
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_ABS_MASK)
+
+/* The count of ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT */
+#define ENET_MTL_QUEUE_MTL_TXQX_ETS_STAT_COUNT (2U)
+
+/*! @name MTL_QUEUE_MTL_TXQX_QNTM_WGHT - */
+#define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_MASK (0x1FFFFFU)
+#define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT (0U)
+#define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_ISCQW_MASK)
+
+/* The count of ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT */
+#define ENET_MTL_QUEUE_MTL_TXQX_QNTM_WGHT_COUNT (2U)
+
+/*! @name MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT - MTL TxQx SendSlopCredit register, only TxQ1 support */
+#define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_MASK (0x3FFFU)
+#define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT (0U)
+#define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_SSC_MASK)
+
+/* The count of ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT */
+#define ENET_MTL_QUEUE_MTL_TXQX_SNDSLP_CRDT_COUNT (2U)
+
+/*! @name MTL_QUEUE_MTL_TXQX_HI_CRDT - MTL TxQx hiCredit register, only TxQ1 support */
+#define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_MASK (0x1FFFFFFFU)
+#define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_SHIFT (0U)
+#define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_HC_MASK)
+
+/* The count of ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT */
+#define ENET_MTL_QUEUE_MTL_TXQX_HI_CRDT_COUNT (2U)
+
+/*! @name MTL_QUEUE_MTL_TXQX_LO_CRDT - MTL TxQx loCredit register, only TxQ1 support */
+#define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_MASK (0x1FFFFFFFU)
+#define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_SHIFT (0U)
+#define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_LC_MASK)
+
+/* The count of ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT */
+#define ENET_MTL_QUEUE_MTL_TXQX_LO_CRDT_COUNT (2U)
+
+/*! @name MTL_QUEUE_MTL_TXQX_INTCTRL_STAT - */
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_MASK (0x1U)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT (0U)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUNFIS_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK (0x2U)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT (1U)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIS_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_MASK (0x100U)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_SHIFT (8U)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_TXUIE_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_MASK (0x200U)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_SHIFT (9U)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_ABPSIE_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_MASK (0x10000U)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT (16U)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOVFIS_MASK)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_MASK (0x1000000U)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_SHIFT (24U)
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_SHIFT)) & ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_RXOIE_MASK)
+
+/* The count of ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT */
+#define ENET_MTL_QUEUE_MTL_TXQX_INTCTRL_STAT_COUNT (2U)
+
+/*! @name MTL_QUEUE_MTL_RXQX_OP_MODE - MTL RxQx Operation Mode register */
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_MASK (0x3U)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_SHIFT (0U)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RTC_MASK)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_MASK (0x8U)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_SHIFT (3U)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FUP_MASK)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_MASK (0x10U)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_SHIFT (4U)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_FEP_MASK)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_MASK (0x20U)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_SHIFT (5U)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RSF_MASK)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK (0x40U)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT (6U)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_DIS_TCP_EF_MASK)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_MASK (0x700000U)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_SHIFT (20U)
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_RQS_MASK)
+
+/* The count of ENET_MTL_QUEUE_MTL_RXQX_OP_MODE */
+#define ENET_MTL_QUEUE_MTL_RXQX_OP_MODE_COUNT (2U)
+
+/*! @name MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT - MTL RxQx Missed Packet Overflow Counter register */
+#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK (0x7FFU)
+#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT (0U)
+#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFPKTCNT_MASK)
+#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK (0x800U)
+#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT (11U)
+#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_OVFCNTOVF_MASK)
+
+/* The count of ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT */
+#define ENET_MTL_QUEUE_MTL_RXQX_MISSPKT_OVRFLW_CNT_COUNT (2U)
+
+/*! @name MTL_QUEUE_MTL_RXQX_DBG - MTL RxQx Debug register */
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_MASK (0x1U)
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_SHIFT (0U)
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RWCSTS_MASK)
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_MASK (0x6U)
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_SHIFT (1U)
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RRCSTS_MASK)
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_MASK (0x30U)
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_SHIFT (4U)
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_RXQSTS_MASK)
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_MASK (0x3FFF0000U)
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_SHIFT (16U)
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_DBG_PRXQ_MASK)
+
+/* The count of ENET_MTL_QUEUE_MTL_RXQX_DBG */
+#define ENET_MTL_QUEUE_MTL_RXQX_DBG_COUNT (2U)
+
+/*! @name MTL_QUEUE_MTL_RXQX_CTRL - MTL RxQx Control register */
+#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_MASK (0x7U)
+#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT (0U)
+#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_WEGT_MASK)
+#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK (0x8U)
+#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT (3U)
+#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT(x) (((uint32_t)(((uint32_t)(x)) << ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_SHIFT)) & ENET_MTL_QUEUE_MTL_RXQX_CTRL_RXQ_FRM_ARBIT_MASK)
+
+/* The count of ENET_MTL_QUEUE_MTL_RXQX_CTRL */
+#define ENET_MTL_QUEUE_MTL_RXQX_CTRL_COUNT (2U)
+
+/*! @name DMA_MODE - DMA mode register */
+#define ENET_DMA_MODE_SWR_MASK (0x1U)
+#define ENET_DMA_MODE_SWR_SHIFT (0U)
+#define ENET_DMA_MODE_SWR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_SWR_SHIFT)) & ENET_DMA_MODE_SWR_MASK)
+#define ENET_DMA_MODE_DA_MASK (0x2U)
+#define ENET_DMA_MODE_DA_SHIFT (1U)
+#define ENET_DMA_MODE_DA(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_DA_SHIFT)) & ENET_DMA_MODE_DA_MASK)
+#define ENET_DMA_MODE_TAA_MASK (0x1CU)
+#define ENET_DMA_MODE_TAA_SHIFT (2U)
+#define ENET_DMA_MODE_TAA(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_TAA_SHIFT)) & ENET_DMA_MODE_TAA_MASK)
+#define ENET_DMA_MODE_TXPR_MASK (0x800U)
+#define ENET_DMA_MODE_TXPR_SHIFT (11U)
+#define ENET_DMA_MODE_TXPR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_TXPR_SHIFT)) & ENET_DMA_MODE_TXPR_MASK)
+#define ENET_DMA_MODE_PR_MASK (0x7000U)
+#define ENET_DMA_MODE_PR_SHIFT (12U)
+#define ENET_DMA_MODE_PR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_MODE_PR_SHIFT)) & ENET_DMA_MODE_PR_MASK)
+
+/*! @name DMA_SYSBUS_MODE - DMA System Bus mode */
+#define ENET_DMA_SYSBUS_MODE_FB_MASK (0x1U)
+#define ENET_DMA_SYSBUS_MODE_FB_SHIFT (0U)
+#define ENET_DMA_SYSBUS_MODE_FB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_FB_SHIFT)) & ENET_DMA_SYSBUS_MODE_FB_MASK)
+#define ENET_DMA_SYSBUS_MODE_AAL_MASK (0x1000U)
+#define ENET_DMA_SYSBUS_MODE_AAL_SHIFT (12U)
+#define ENET_DMA_SYSBUS_MODE_AAL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_AAL_SHIFT)) & ENET_DMA_SYSBUS_MODE_AAL_MASK)
+#define ENET_DMA_SYSBUS_MODE_MB_MASK (0x4000U)
+#define ENET_DMA_SYSBUS_MODE_MB_SHIFT (14U)
+#define ENET_DMA_SYSBUS_MODE_MB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_MB_SHIFT)) & ENET_DMA_SYSBUS_MODE_MB_MASK)
+#define ENET_DMA_SYSBUS_MODE_RB_MASK (0x8000U)
+#define ENET_DMA_SYSBUS_MODE_RB_SHIFT (15U)
+#define ENET_DMA_SYSBUS_MODE_RB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_SYSBUS_MODE_RB_SHIFT)) & ENET_DMA_SYSBUS_MODE_RB_MASK)
+
+/*! @name DMA_INTR_STAT - DMA Interrupt status */
+#define ENET_DMA_INTR_STAT_DC0IS_MASK (0x1U)
+#define ENET_DMA_INTR_STAT_DC0IS_SHIFT (0U)
+#define ENET_DMA_INTR_STAT_DC0IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_DC0IS_SHIFT)) & ENET_DMA_INTR_STAT_DC0IS_MASK)
+#define ENET_DMA_INTR_STAT_DC1IS_MASK (0x2U)
+#define ENET_DMA_INTR_STAT_DC1IS_SHIFT (1U)
+#define ENET_DMA_INTR_STAT_DC1IS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_DC1IS_SHIFT)) & ENET_DMA_INTR_STAT_DC1IS_MASK)
+#define ENET_DMA_INTR_STAT_MTLIS_MASK (0x10000U)
+#define ENET_DMA_INTR_STAT_MTLIS_SHIFT (16U)
+#define ENET_DMA_INTR_STAT_MTLIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_MTLIS_SHIFT)) & ENET_DMA_INTR_STAT_MTLIS_MASK)
+#define ENET_DMA_INTR_STAT_MACIS_MASK (0x20000U)
+#define ENET_DMA_INTR_STAT_MACIS_SHIFT (17U)
+#define ENET_DMA_INTR_STAT_MACIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_INTR_STAT_MACIS_SHIFT)) & ENET_DMA_INTR_STAT_MACIS_MASK)
+
+/*! @name DMA_DBG_STAT - DMA Debug Status */
+#define ENET_DMA_DBG_STAT_AHSTS_MASK (0x1U)
+#define ENET_DMA_DBG_STAT_AHSTS_SHIFT (0U)
+#define ENET_DMA_DBG_STAT_AHSTS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_AHSTS_SHIFT)) & ENET_DMA_DBG_STAT_AHSTS_MASK)
+#define ENET_DMA_DBG_STAT_RPS0_MASK (0xF00U)
+#define ENET_DMA_DBG_STAT_RPS0_SHIFT (8U)
+#define ENET_DMA_DBG_STAT_RPS0(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_RPS0_SHIFT)) & ENET_DMA_DBG_STAT_RPS0_MASK)
+#define ENET_DMA_DBG_STAT_TPS0_MASK (0xF000U)
+#define ENET_DMA_DBG_STAT_TPS0_SHIFT (12U)
+#define ENET_DMA_DBG_STAT_TPS0(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_TPS0_SHIFT)) & ENET_DMA_DBG_STAT_TPS0_MASK)
+#define ENET_DMA_DBG_STAT_RPS1_MASK (0xF0000U)
+#define ENET_DMA_DBG_STAT_RPS1_SHIFT (16U)
+#define ENET_DMA_DBG_STAT_RPS1(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_RPS1_SHIFT)) & ENET_DMA_DBG_STAT_RPS1_MASK)
+#define ENET_DMA_DBG_STAT_TPS1_MASK (0xF00000U)
+#define ENET_DMA_DBG_STAT_TPS1_SHIFT (20U)
+#define ENET_DMA_DBG_STAT_TPS1(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_DBG_STAT_TPS1_SHIFT)) & ENET_DMA_DBG_STAT_TPS1_MASK)
+
+/*! @name DMA_CH_DMA_CHX_CTRL - DMA Channelx Control */
+#define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_MASK (0x10000U)
+#define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_SHIFT (16U)
+#define ENET_DMA_CH_DMA_CHX_CTRL_PBLx8(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_SHIFT)) & ENET_DMA_CH_DMA_CHX_CTRL_PBLx8_MASK)
+#define ENET_DMA_CH_DMA_CHX_CTRL_DSL_MASK (0x1C0000U)
+#define ENET_DMA_CH_DMA_CHX_CTRL_DSL_SHIFT (18U)
+#define ENET_DMA_CH_DMA_CHX_CTRL_DSL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CTRL_DSL_SHIFT)) & ENET_DMA_CH_DMA_CHX_CTRL_DSL_MASK)
+
+/* The count of ENET_DMA_CH_DMA_CHX_CTRL */
+#define ENET_DMA_CH_DMA_CHX_CTRL_COUNT (2U)
+
+/*! @name DMA_CH_DMA_CHX_TX_CTRL - DMA Channelx Transmit Control */
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK (0x1U)
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_SHIFT (0U)
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_ST(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_ST_MASK)
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_MASK (0xEU)
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_SHIFT (1U)
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_TCW_MASK)
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_MASK (0x10U)
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_SHIFT (4U)
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_OSF_MASK)
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_MASK (0x3F0000U)
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_SHIFT (16U)
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TX_CTRL_TxPBL_MASK)
+
+/* The count of ENET_DMA_CH_DMA_CHX_TX_CTRL */
+#define ENET_DMA_CH_DMA_CHX_TX_CTRL_COUNT (2U)
+
+/*! @name DMA_CH_DMA_CHX_RX_CTRL - DMA Channelx Receive Control */
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_MASK (0x1U)
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_SHIFT (0U)
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_SR(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_SR_MASK)
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_MASK (0x7FF8U)
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_SHIFT (3U)
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RBSZ_MASK)
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_MASK (0x3F0000U)
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_SHIFT (16U)
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RxPBL_MASK)
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_MASK (0x80000000U)
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_SHIFT (31U)
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_CTRL_RPF_MASK)
+
+/* The count of ENET_DMA_CH_DMA_CHX_RX_CTRL */
+#define ENET_DMA_CH_DMA_CHX_RX_CTRL_COUNT (2U)
+
+/*! @name DMA_CH_DMA_CHX_TXDESC_LIST_ADDR - */
+#define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_MASK (0xFFFFFFFCU)
+#define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_SHIFT (2U)
+#define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_STL_MASK)
+
+/* The count of ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR */
+#define ENET_DMA_CH_DMA_CHX_TXDESC_LIST_ADDR_COUNT (2U)
+
+/*! @name DMA_CH_DMA_CHX_RXDESC_LIST_ADDR - */
+#define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_MASK (0xFFFFFFFCU)
+#define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_SHIFT (2U)
+#define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_SRL_MASK)
+
+/* The count of ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR */
+#define ENET_DMA_CH_DMA_CHX_RXDESC_LIST_ADDR_COUNT (2U)
+
+/*! @name DMA_CH_DMA_CHX_TXDESC_TAIL_PTR - */
+#define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK (0xFFFFFFFCU)
+#define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT (2U)
+#define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_TDTP_MASK)
+
+/* The count of ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR */
+#define ENET_DMA_CH_DMA_CHX_TXDESC_TAIL_PTR_COUNT (2U)
+
+/*! @name DMA_CH_DMA_CHX_RXDESC_TAIL_PTR - */
+#define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK (0xFFFFFFFCU)
+#define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT (2U)
+#define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_RDTP_MASK)
+
+/* The count of ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR */
+#define ENET_DMA_CH_DMA_CHX_RXDESC_TAIL_PTR_COUNT (2U)
+
+/*! @name DMA_CH_DMA_CHX_TXDESC_RING_LENGTH - */
+#define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK (0x3FFU)
+#define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT (0U)
+#define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_TDRL_MASK)
+
+/* The count of ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH */
+#define ENET_DMA_CH_DMA_CHX_TXDESC_RING_LENGTH_COUNT (2U)
+
+/*! @name DMA_CH_DMA_CHX_RXDESC_RING_LENGTH - Channelx Rx descriptor Ring Length */
+#define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK (0x3FFU)
+#define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_SHIFT (0U)
+#define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_SHIFT)) & ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_RDRL_MASK)
+
+/* The count of ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH */
+#define ENET_DMA_CH_DMA_CHX_RXDESC_RING_LENGTH_COUNT (2U)
+
+/*! @name DMA_CH_DMA_CHX_INT_EN - Channelx Interrupt Enable */
+#define ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK (0x1U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_TIE_SHIFT (0U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_TIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_TSE_MASK (0x2U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_TSE_SHIFT (1U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_TSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TSE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TSE_MASK)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_MASK (0x4U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_SHIFT (2U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_TBUE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_TBUE_MASK)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK (0x40U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RIE_SHIFT (6U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_MASK (0x80U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_SHIFT (7U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RBUE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RBUE_MASK)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RSE_MASK (0x100U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RSE_SHIFT (8U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RSE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RSE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RSE_MASK)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_MASK (0x200U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_SHIFT (9U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_RWTE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_RWTE_MASK)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_MASK (0x400U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_SHIFT (10U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_ETIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_ETIE_MASK)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_MASK (0x800U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_SHIFT (11U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_ERIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_ERIE_MASK)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_MASK (0x1000U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_SHIFT (12U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_FBEE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_FBEE_MASK)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_AIE_MASK (0x4000U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_AIE_SHIFT (14U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_AIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_AIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_AIE_MASK)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_NIE_MASK (0x8000U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_NIE_SHIFT (15U)
+#define ENET_DMA_CH_DMA_CHX_INT_EN_NIE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_INT_EN_NIE_SHIFT)) & ENET_DMA_CH_DMA_CHX_INT_EN_NIE_MASK)
+
+/* The count of ENET_DMA_CH_DMA_CHX_INT_EN */
+#define ENET_DMA_CH_DMA_CHX_INT_EN_COUNT (2U)
+
+/*! @name DMA_CH_DMA_CHX_RX_INT_WDTIMER - Receive Interrupt Watchdog Timer */
+#define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_MASK (0xFFU)
+#define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_SHIFT (0U)
+#define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_SHIFT)) & ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_RIWT_MASK)
+
+/* The count of ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER */
+#define ENET_DMA_CH_DMA_CHX_RX_INT_WDTIMER_COUNT (2U)
+
+/*! @name DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT - Slot Function Control and Status */
+#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK (0x1U)
+#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT (0U)
+#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ESC_MASK)
+#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK (0x2U)
+#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT (1U)
+#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_ASC_MASK)
+#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK (0xF0000U)
+#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT (16U)
+#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_SHIFT)) & ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_RSN_MASK)
+
+/* The count of ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT */
+#define ENET_DMA_CH_DMA_CHX_SLOT_FUNC_CTRL_STAT_COUNT (2U)
+
+/*! @name DMA_CH_DMA_CHX_CUR_HST_TXDESC - Channelx Current Host Transmit descriptor */
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_MASK (0xFFFFFFFFU)
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_SHIFT (0U)
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_HTD_MASK)
+
+/* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC */
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXDESC_COUNT (2U)
+
+/*! @name DMA_CH_DMA_CHX_CUR_HST_RXDESC - */
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_MASK (0xFFFFFFFFU)
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_SHIFT (0U)
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_HRD_MASK)
+
+/* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC */
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXDESC_COUNT (2U)
+
+/*! @name DMA_CH_DMA_CHX_CUR_HST_TXBUF - */
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_MASK (0xFFFFFFFFU)
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_SHIFT (0U)
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_HTB_MASK)
+
+/* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF */
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_TXBUF_COUNT (2U)
+
+/*! @name DMA_CH_DMA_CHX_CUR_HST_RXBUF - Channelx Current Application Receive Buffer Address */
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_MASK (0xFFFFFFFFU)
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_SHIFT (0U)
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_SHIFT)) & ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_HRB_MASK)
+
+/* The count of ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF */
+#define ENET_DMA_CH_DMA_CHX_CUR_HST_RXBUF_COUNT (2U)
+
+/*! @name DMA_CH_DMA_CHX_STAT - Channelx DMA status register */
+#define ENET_DMA_CH_DMA_CHX_STAT_TI_MASK (0x1U)
+#define ENET_DMA_CH_DMA_CHX_STAT_TI_SHIFT (0U)
+#define ENET_DMA_CH_DMA_CHX_STAT_TI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TI_MASK)
+#define ENET_DMA_CH_DMA_CHX_STAT_TPS_MASK (0x2U)
+#define ENET_DMA_CH_DMA_CHX_STAT_TPS_SHIFT (1U)
+#define ENET_DMA_CH_DMA_CHX_STAT_TPS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TPS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TPS_MASK)
+#define ENET_DMA_CH_DMA_CHX_STAT_TBU_MASK (0x4U)
+#define ENET_DMA_CH_DMA_CHX_STAT_TBU_SHIFT (2U)
+#define ENET_DMA_CH_DMA_CHX_STAT_TBU(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_TBU_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_TBU_MASK)
+#define ENET_DMA_CH_DMA_CHX_STAT_RI_MASK (0x40U)
+#define ENET_DMA_CH_DMA_CHX_STAT_RI_SHIFT (6U)
+#define ENET_DMA_CH_DMA_CHX_STAT_RI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RI_MASK)
+#define ENET_DMA_CH_DMA_CHX_STAT_RBU_MASK (0x80U)
+#define ENET_DMA_CH_DMA_CHX_STAT_RBU_SHIFT (7U)
+#define ENET_DMA_CH_DMA_CHX_STAT_RBU(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RBU_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RBU_MASK)
+#define ENET_DMA_CH_DMA_CHX_STAT_RPS_MASK (0x100U)
+#define ENET_DMA_CH_DMA_CHX_STAT_RPS_SHIFT (8U)
+#define ENET_DMA_CH_DMA_CHX_STAT_RPS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RPS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RPS_MASK)
+#define ENET_DMA_CH_DMA_CHX_STAT_RWT_MASK (0x200U)
+#define ENET_DMA_CH_DMA_CHX_STAT_RWT_SHIFT (9U)
+#define ENET_DMA_CH_DMA_CHX_STAT_RWT(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_RWT_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_RWT_MASK)
+#define ENET_DMA_CH_DMA_CHX_STAT_ETI_MASK (0x400U)
+#define ENET_DMA_CH_DMA_CHX_STAT_ETI_SHIFT (10U)
+#define ENET_DMA_CH_DMA_CHX_STAT_ETI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_ETI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_ETI_MASK)
+#define ENET_DMA_CH_DMA_CHX_STAT_ERI_MASK (0x800U)
+#define ENET_DMA_CH_DMA_CHX_STAT_ERI_SHIFT (11U)
+#define ENET_DMA_CH_DMA_CHX_STAT_ERI(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_ERI_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_ERI_MASK)
+#define ENET_DMA_CH_DMA_CHX_STAT_FBE_MASK (0x1000U)
+#define ENET_DMA_CH_DMA_CHX_STAT_FBE_SHIFT (12U)
+#define ENET_DMA_CH_DMA_CHX_STAT_FBE(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_FBE_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_FBE_MASK)
+#define ENET_DMA_CH_DMA_CHX_STAT_AIS_MASK (0x4000U)
+#define ENET_DMA_CH_DMA_CHX_STAT_AIS_SHIFT (14U)
+#define ENET_DMA_CH_DMA_CHX_STAT_AIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_AIS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_AIS_MASK)
+#define ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK (0x8000U)
+#define ENET_DMA_CH_DMA_CHX_STAT_NIS_SHIFT (15U)
+#define ENET_DMA_CH_DMA_CHX_STAT_NIS(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_NIS_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_NIS_MASK)
+#define ENET_DMA_CH_DMA_CHX_STAT_EB_MASK (0x70000U)
+#define ENET_DMA_CH_DMA_CHX_STAT_EB_SHIFT (16U)
+#define ENET_DMA_CH_DMA_CHX_STAT_EB(x) (((uint32_t)(((uint32_t)(x)) << ENET_DMA_CH_DMA_CHX_STAT_EB_SHIFT)) & ENET_DMA_CH_DMA_CHX_STAT_EB_MASK)
+
+/* The count of ENET_DMA_CH_DMA_CHX_STAT */
+#define ENET_DMA_CH_DMA_CHX_STAT_COUNT (2U)
+
+
+/*!
+ * @}
+ */ /* end of group ENET_Register_Masks */
+
+
+/* ENET - Peripheral instance base addresses */
+/** Peripheral ENET base address */
+#define ENET_BASE (0x40092000u)
+/** Peripheral ENET base pointer */
+#define ENET ((ENET_Type *)ENET_BASE)
+/** Array initializer of ENET peripheral base addresses */
+#define ENET_BASE_ADDRS { ENET_BASE }
+/** Array initializer of ENET peripheral base pointers */
+#define ENET_BASE_PTRS { ENET }
+/** Interrupt vectors for the ENET peripheral type */
+#define ENET_IRQS { ETHERNET_IRQn }
+#define ENET_PMT_IRQS { ETHERNET_PMT_IRQn }
+#define ENET_MACLP_IRQS { ETHERNET_MACLP_IRQn }
+
+/*!
+ * @}
+ */ /* end of group ENET_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FLEXCOMM Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FLEXCOMM_Peripheral_Access_Layer FLEXCOMM Peripheral Access Layer
+ * @{
+ */
+
+/** FLEXCOMM - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[4088];
+ __IO uint32_t PSELID; /**< Peripheral Select and Flexcomm ID register., offset: 0xFF8 */
+ __IO uint32_t PID; /**< Peripheral identification register., offset: 0xFFC */
+} FLEXCOMM_Type;
+
+/* ----------------------------------------------------------------------------
+ -- FLEXCOMM Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FLEXCOMM_Register_Masks FLEXCOMM Register Masks
+ * @{
+ */
+
+/*! @name PSELID - Peripheral Select and Flexcomm ID register. */
+#define FLEXCOMM_PSELID_PERSEL_MASK (0x7U)
+#define FLEXCOMM_PSELID_PERSEL_SHIFT (0U)
+#define FLEXCOMM_PSELID_PERSEL(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_PERSEL_SHIFT)) & FLEXCOMM_PSELID_PERSEL_MASK)
+#define FLEXCOMM_PSELID_LOCK_MASK (0x8U)
+#define FLEXCOMM_PSELID_LOCK_SHIFT (3U)
+#define FLEXCOMM_PSELID_LOCK(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_LOCK_SHIFT)) & FLEXCOMM_PSELID_LOCK_MASK)
+#define FLEXCOMM_PSELID_USARTPRESENT_MASK (0x10U)
+#define FLEXCOMM_PSELID_USARTPRESENT_SHIFT (4U)
+#define FLEXCOMM_PSELID_USARTPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_USARTPRESENT_SHIFT)) & FLEXCOMM_PSELID_USARTPRESENT_MASK)
+#define FLEXCOMM_PSELID_SPIPRESENT_MASK (0x20U)
+#define FLEXCOMM_PSELID_SPIPRESENT_SHIFT (5U)
+#define FLEXCOMM_PSELID_SPIPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_SPIPRESENT_SHIFT)) & FLEXCOMM_PSELID_SPIPRESENT_MASK)
+#define FLEXCOMM_PSELID_I2CPRESENT_MASK (0x40U)
+#define FLEXCOMM_PSELID_I2CPRESENT_SHIFT (6U)
+#define FLEXCOMM_PSELID_I2CPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2CPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2CPRESENT_MASK)
+#define FLEXCOMM_PSELID_I2SPRESENT_MASK (0x80U)
+#define FLEXCOMM_PSELID_I2SPRESENT_SHIFT (7U)
+#define FLEXCOMM_PSELID_I2SPRESENT(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_I2SPRESENT_SHIFT)) & FLEXCOMM_PSELID_I2SPRESENT_MASK)
+#define FLEXCOMM_PSELID_ID_MASK (0xFFFFF000U)
+#define FLEXCOMM_PSELID_ID_SHIFT (12U)
+#define FLEXCOMM_PSELID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PSELID_ID_SHIFT)) & FLEXCOMM_PSELID_ID_MASK)
+
+/*! @name PID - Peripheral identification register. */
+#define FLEXCOMM_PID_Minor_Rev_MASK (0xF00U)
+#define FLEXCOMM_PID_Minor_Rev_SHIFT (8U)
+#define FLEXCOMM_PID_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Minor_Rev_SHIFT)) & FLEXCOMM_PID_Minor_Rev_MASK)
+#define FLEXCOMM_PID_Major_Rev_MASK (0xF000U)
+#define FLEXCOMM_PID_Major_Rev_SHIFT (12U)
+#define FLEXCOMM_PID_Major_Rev(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_Major_Rev_SHIFT)) & FLEXCOMM_PID_Major_Rev_MASK)
+#define FLEXCOMM_PID_ID_MASK (0xFFFF0000U)
+#define FLEXCOMM_PID_ID_SHIFT (16U)
+#define FLEXCOMM_PID_ID(x) (((uint32_t)(((uint32_t)(x)) << FLEXCOMM_PID_ID_SHIFT)) & FLEXCOMM_PID_ID_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group FLEXCOMM_Register_Masks */
+
+
+/* FLEXCOMM - Peripheral instance base addresses */
+/** Peripheral FLEXCOMM0 base address */
+#define FLEXCOMM0_BASE (0x40086000u)
+/** Peripheral FLEXCOMM0 base pointer */
+#define FLEXCOMM0 ((FLEXCOMM_Type *)FLEXCOMM0_BASE)
+/** Peripheral FLEXCOMM1 base address */
+#define FLEXCOMM1_BASE (0x40087000u)
+/** Peripheral FLEXCOMM1 base pointer */
+#define FLEXCOMM1 ((FLEXCOMM_Type *)FLEXCOMM1_BASE)
+/** Peripheral FLEXCOMM2 base address */
+#define FLEXCOMM2_BASE (0x40088000u)
+/** Peripheral FLEXCOMM2 base pointer */
+#define FLEXCOMM2 ((FLEXCOMM_Type *)FLEXCOMM2_BASE)
+/** Peripheral FLEXCOMM3 base address */
+#define FLEXCOMM3_BASE (0x40089000u)
+/** Peripheral FLEXCOMM3 base pointer */
+#define FLEXCOMM3 ((FLEXCOMM_Type *)FLEXCOMM3_BASE)
+/** Peripheral FLEXCOMM4 base address */
+#define FLEXCOMM4_BASE (0x4008A000u)
+/** Peripheral FLEXCOMM4 base pointer */
+#define FLEXCOMM4 ((FLEXCOMM_Type *)FLEXCOMM4_BASE)
+/** Peripheral FLEXCOMM5 base address */
+#define FLEXCOMM5_BASE (0x40096000u)
+/** Peripheral FLEXCOMM5 base pointer */
+#define FLEXCOMM5 ((FLEXCOMM_Type *)FLEXCOMM5_BASE)
+/** Peripheral FLEXCOMM6 base address */
+#define FLEXCOMM6_BASE (0x40097000u)
+/** Peripheral FLEXCOMM6 base pointer */
+#define FLEXCOMM6 ((FLEXCOMM_Type *)FLEXCOMM6_BASE)
+/** Peripheral FLEXCOMM7 base address */
+#define FLEXCOMM7_BASE (0x40098000u)
+/** Peripheral FLEXCOMM7 base pointer */
+#define FLEXCOMM7 ((FLEXCOMM_Type *)FLEXCOMM7_BASE)
+/** Peripheral FLEXCOMM8 base address */
+#define FLEXCOMM8_BASE (0x40099000u)
+/** Peripheral FLEXCOMM8 base pointer */
+#define FLEXCOMM8 ((FLEXCOMM_Type *)FLEXCOMM8_BASE)
+/** Peripheral FLEXCOMM9 base address */
+#define FLEXCOMM9_BASE (0x4009A000u)
+/** Peripheral FLEXCOMM9 base pointer */
+#define FLEXCOMM9 ((FLEXCOMM_Type *)FLEXCOMM9_BASE)
+/** Array initializer of FLEXCOMM peripheral base addresses */
+#define FLEXCOMM_BASE_ADDRS { FLEXCOMM0_BASE, FLEXCOMM1_BASE, FLEXCOMM2_BASE, FLEXCOMM3_BASE, FLEXCOMM4_BASE, FLEXCOMM5_BASE, FLEXCOMM6_BASE, FLEXCOMM7_BASE, FLEXCOMM8_BASE, FLEXCOMM9_BASE }
+/** Array initializer of FLEXCOMM peripheral base pointers */
+#define FLEXCOMM_BASE_PTRS { FLEXCOMM0, FLEXCOMM1, FLEXCOMM2, FLEXCOMM3, FLEXCOMM4, FLEXCOMM5, FLEXCOMM6, FLEXCOMM7, FLEXCOMM8, FLEXCOMM9 }
+/** Interrupt vectors for the FLEXCOMM peripheral type */
+#define FLEXCOMM_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn }
+
+/*!
+ * @}
+ */ /* end of group FLEXCOMM_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- FMC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Peripheral_Access_Layer FMC Peripheral Access Layer
+ * @{
+ */
+
+/** FMC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t FCTR; /**< Control register, offset: 0x0 */
+ uint8_t RESERVED_0[12];
+ __IO uint32_t FBWST; /**< Wait state register, offset: 0x10 */
+ uint8_t RESERVED_1[12];
+ __IO uint32_t FMSSTART; /**< Signature start address register, offset: 0x20 */
+ __IO uint32_t FMSSTOP; /**< Signature stop-address register, offset: 0x24 */
+ uint8_t RESERVED_2[4];
+ __I uint32_t FMSW[4]; /**< Words of 128-bit signature word, array offset: 0x2C, array step: 0x4 */
+ uint8_t RESERVED_3[4004];
+ __I uint32_t FMSTAT; /**< Signature generation status register, offset: 0xFE0 */
+ uint8_t RESERVED_4[4];
+ __O uint32_t FMSTATCLR; /**< Signature generation status clear register, offset: 0xFE8 */
+} FMC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- FMC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup FMC_Register_Masks FMC Register Masks
+ * @{
+ */
+
+/*! @name FCTR - Control register */
+#define FMC_FCTR_FS_RD0_MASK (0x8U)
+#define FMC_FCTR_FS_RD0_SHIFT (3U)
+#define FMC_FCTR_FS_RD0(x) (((uint32_t)(((uint32_t)(x)) << FMC_FCTR_FS_RD0_SHIFT)) & FMC_FCTR_FS_RD0_MASK)
+#define FMC_FCTR_FS_RD1_MASK (0x10U)
+#define FMC_FCTR_FS_RD1_SHIFT (4U)
+#define FMC_FCTR_FS_RD1(x) (((uint32_t)(((uint32_t)(x)) << FMC_FCTR_FS_RD1_SHIFT)) & FMC_FCTR_FS_RD1_MASK)
+
+/*! @name FBWST - Wait state register */
+#define FMC_FBWST_WAITSTATES_MASK (0xFFU)
+#define FMC_FBWST_WAITSTATES_SHIFT (0U)
+#define FMC_FBWST_WAITSTATES(x) (((uint32_t)(((uint32_t)(x)) << FMC_FBWST_WAITSTATES_SHIFT)) & FMC_FBWST_WAITSTATES_MASK)
+
+/*! @name FMSSTART - Signature start address register */
+#define FMC_FMSSTART_START_MASK (0x1FFFFU)
+#define FMC_FMSSTART_START_SHIFT (0U)
+#define FMC_FMSSTART_START(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSSTART_START_SHIFT)) & FMC_FMSSTART_START_MASK)
+
+/*! @name FMSSTOP - Signature stop-address register */
+#define FMC_FMSSTOP_STOP_MASK (0x1FFFFU)
+#define FMC_FMSSTOP_STOP_SHIFT (0U)
+#define FMC_FMSSTOP_STOP(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSSTOP_STOP_SHIFT)) & FMC_FMSSTOP_STOP_MASK)
+#define FMC_FMSSTOP_SIG_START_MASK (0x20000U)
+#define FMC_FMSSTOP_SIG_START_SHIFT (17U)
+#define FMC_FMSSTOP_SIG_START(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSSTOP_SIG_START_SHIFT)) & FMC_FMSSTOP_SIG_START_MASK)
+
+/*! @name FMSW - Words of 128-bit signature word */
+#define FMC_FMSW_SW_MASK (0xFFFFFFFFU)
+#define FMC_FMSW_SW_SHIFT (0U)
+#define FMC_FMSW_SW(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSW_SW_SHIFT)) & FMC_FMSW_SW_MASK)
+
+/* The count of FMC_FMSW */
+#define FMC_FMSW_COUNT (4U)
+
+/*! @name FMSTAT - Signature generation status register */
+#define FMC_FMSTAT_SIG_DONE_MASK (0x4U)
+#define FMC_FMSTAT_SIG_DONE_SHIFT (2U)
+#define FMC_FMSTAT_SIG_DONE(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSTAT_SIG_DONE_SHIFT)) & FMC_FMSTAT_SIG_DONE_MASK)
+
+/*! @name FMSTATCLR - Signature generation status clear register */
+#define FMC_FMSTATCLR_SIG_DONE_CLR_MASK (0x4U)
+#define FMC_FMSTATCLR_SIG_DONE_CLR_SHIFT (2U)
+#define FMC_FMSTATCLR_SIG_DONE_CLR(x) (((uint32_t)(((uint32_t)(x)) << FMC_FMSTATCLR_SIG_DONE_CLR_SHIFT)) & FMC_FMSTATCLR_SIG_DONE_CLR_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group FMC_Register_Masks */
+
+
+/* FMC - Peripheral instance base addresses */
+/** Peripheral FMC base address */
+#define FMC_BASE (0x40034000u)
+/** Peripheral FMC base pointer */
+#define FMC ((FMC_Type *)FMC_BASE)
+/** Array initializer of FMC peripheral base addresses */
+#define FMC_BASE_ADDRS { FMC_BASE }
+/** Array initializer of FMC peripheral base pointers */
+#define FMC_BASE_PTRS { FMC }
+
+/*!
+ * @}
+ */ /* end of group FMC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- GINT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GINT_Peripheral_Access_Layer GINT Peripheral Access Layer
+ * @{
+ */
+
+/** GINT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CTRL; /**< GPIO grouped interrupt control register, offset: 0x0 */
+ uint8_t RESERVED_0[28];
+ __IO uint32_t PORT_POL[2]; /**< GPIO grouped interrupt port 0 polarity register, array offset: 0x20, array step: 0x4 */
+ uint8_t RESERVED_1[24];
+ __IO uint32_t PORT_ENA[2]; /**< GPIO grouped interrupt port 0 enable register, array offset: 0x40, array step: 0x4 */
+} GINT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- GINT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GINT_Register_Masks GINT Register Masks
+ * @{
+ */
+
+/*! @name CTRL - GPIO grouped interrupt control register */
+#define GINT_CTRL_INT_MASK (0x1U)
+#define GINT_CTRL_INT_SHIFT (0U)
+#define GINT_CTRL_INT(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_INT_SHIFT)) & GINT_CTRL_INT_MASK)
+#define GINT_CTRL_COMB_MASK (0x2U)
+#define GINT_CTRL_COMB_SHIFT (1U)
+#define GINT_CTRL_COMB(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_COMB_SHIFT)) & GINT_CTRL_COMB_MASK)
+#define GINT_CTRL_TRIG_MASK (0x4U)
+#define GINT_CTRL_TRIG_SHIFT (2U)
+#define GINT_CTRL_TRIG(x) (((uint32_t)(((uint32_t)(x)) << GINT_CTRL_TRIG_SHIFT)) & GINT_CTRL_TRIG_MASK)
+
+/*! @name PORT_POL - GPIO grouped interrupt port 0 polarity register */
+#define GINT_PORT_POL_POL_MASK (0xFFFFFFFFU)
+#define GINT_PORT_POL_POL_SHIFT (0U)
+#define GINT_PORT_POL_POL(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_POL_POL_SHIFT)) & GINT_PORT_POL_POL_MASK)
+
+/* The count of GINT_PORT_POL */
+#define GINT_PORT_POL_COUNT (2U)
+
+/*! @name PORT_ENA - GPIO grouped interrupt port 0 enable register */
+#define GINT_PORT_ENA_ENA_MASK (0xFFFFFFFFU)
+#define GINT_PORT_ENA_ENA_SHIFT (0U)
+#define GINT_PORT_ENA_ENA(x) (((uint32_t)(((uint32_t)(x)) << GINT_PORT_ENA_ENA_SHIFT)) & GINT_PORT_ENA_ENA_MASK)
+
+/* The count of GINT_PORT_ENA */
+#define GINT_PORT_ENA_COUNT (2U)
+
+
+/*!
+ * @}
+ */ /* end of group GINT_Register_Masks */
+
+
+/* GINT - Peripheral instance base addresses */
+/** Peripheral GINT0 base address */
+#define GINT0_BASE (0x40002000u)
+/** Peripheral GINT0 base pointer */
+#define GINT0 ((GINT_Type *)GINT0_BASE)
+/** Peripheral GINT1 base address */
+#define GINT1_BASE (0x40003000u)
+/** Peripheral GINT1 base pointer */
+#define GINT1 ((GINT_Type *)GINT1_BASE)
+/** Array initializer of GINT peripheral base addresses */
+#define GINT_BASE_ADDRS { GINT0_BASE, GINT1_BASE }
+/** Array initializer of GINT peripheral base pointers */
+#define GINT_BASE_PTRS { GINT0, GINT1 }
+/** Interrupt vectors for the GINT peripheral type */
+#define GINT_IRQS { GINT0_IRQn, GINT1_IRQn }
+
+/*!
+ * @}
+ */ /* end of group GINT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- GPIO Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Peripheral_Access_Layer GPIO Peripheral Access Layer
+ * @{
+ */
+
+/** GPIO - Register Layout Typedef */
+typedef struct {
+ __IO uint8_t B[6][32]; /**< Byte pin registers for all port 0 and 1 GPIO pins, array offset: 0x0, array step: index*0x20, index2*0x1 */
+ uint8_t RESERVED_0[3904];
+ __IO uint32_t W[6][32]; /**< Word pin registers for all port 0 and 1 GPIO pins, array offset: 0x1000, array step: index*0x80, index2*0x4 */
+ uint8_t RESERVED_1[3328];
+ __IO uint32_t DIR[6]; /**< Direction registers, array offset: 0x2000, array step: 0x4 */
+ uint8_t RESERVED_2[104];
+ __IO uint32_t MASK[6]; /**< Mask register, array offset: 0x2080, array step: 0x4 */
+ uint8_t RESERVED_3[104];
+ __IO uint32_t PIN[6]; /**< Port pin register, array offset: 0x2100, array step: 0x4 */
+ uint8_t RESERVED_4[104];
+ __IO uint32_t MPIN[6]; /**< Masked port register, array offset: 0x2180, array step: 0x4 */
+ uint8_t RESERVED_5[104];
+ __IO uint32_t SET[6]; /**< Write: Set register for port Read: output bits for port, array offset: 0x2200, array step: 0x4 */
+ uint8_t RESERVED_6[104];
+ __O uint32_t CLR[6]; /**< Clear port, array offset: 0x2280, array step: 0x4 */
+ uint8_t RESERVED_7[104];
+ __O uint32_t NOT[6]; /**< Toggle port, array offset: 0x2300, array step: 0x4 */
+ uint8_t RESERVED_8[104];
+ __O uint32_t DIRSET[6]; /**< Set pin direction bits for port, array offset: 0x2380, array step: 0x4 */
+ uint8_t RESERVED_9[104];
+ __O uint32_t DIRCLR[6]; /**< Clear pin direction bits for port, array offset: 0x2400, array step: 0x4 */
+ uint8_t RESERVED_10[104];
+ __O uint32_t DIRNOT[6]; /**< Toggle pin direction bits for port, array offset: 0x2480, array step: 0x4 */
+} GPIO_Type;
+
+/* ----------------------------------------------------------------------------
+ -- GPIO Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup GPIO_Register_Masks GPIO Register Masks
+ * @{
+ */
+
+/*! @name B - Byte pin registers for all port 0 and 1 GPIO pins */
+#define GPIO_B_PBYTE_MASK (0x1U)
+#define GPIO_B_PBYTE_SHIFT (0U)
+#define GPIO_B_PBYTE(x) (((uint8_t)(((uint8_t)(x)) << GPIO_B_PBYTE_SHIFT)) & GPIO_B_PBYTE_MASK)
+
+/* The count of GPIO_B */
+#define GPIO_B_COUNT (6U)
+
+/* The count of GPIO_B */
+#define GPIO_B_COUNT2 (32U)
+
+/*! @name W - Word pin registers for all port 0 and 1 GPIO pins */
+#define GPIO_W_PWORD_MASK (0xFFFFFFFFU)
+#define GPIO_W_PWORD_SHIFT (0U)
+#define GPIO_W_PWORD(x) (((uint32_t)(((uint32_t)(x)) << GPIO_W_PWORD_SHIFT)) & GPIO_W_PWORD_MASK)
+
+/* The count of GPIO_W */
+#define GPIO_W_COUNT (6U)
+
+/* The count of GPIO_W */
+#define GPIO_W_COUNT2 (32U)
+
+/*! @name DIR - Direction registers */
+#define GPIO_DIR_DIRP_MASK (0xFFFFFFFFU)
+#define GPIO_DIR_DIRP_SHIFT (0U)
+#define GPIO_DIR_DIRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIR_DIRP_SHIFT)) & GPIO_DIR_DIRP_MASK)
+
+/* The count of GPIO_DIR */
+#define GPIO_DIR_COUNT (6U)
+
+/*! @name MASK - Mask register */
+#define GPIO_MASK_MASKP_MASK (0xFFFFFFFFU)
+#define GPIO_MASK_MASKP_SHIFT (0U)
+#define GPIO_MASK_MASKP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MASK_MASKP_SHIFT)) & GPIO_MASK_MASKP_MASK)
+
+/* The count of GPIO_MASK */
+#define GPIO_MASK_COUNT (6U)
+
+/*! @name PIN - Port pin register */
+#define GPIO_PIN_PORT_MASK (0xFFFFFFFFU)
+#define GPIO_PIN_PORT_SHIFT (0U)
+#define GPIO_PIN_PORT(x) (((uint32_t)(((uint32_t)(x)) << GPIO_PIN_PORT_SHIFT)) & GPIO_PIN_PORT_MASK)
+
+/* The count of GPIO_PIN */
+#define GPIO_PIN_COUNT (6U)
+
+/*! @name MPIN - Masked port register */
+#define GPIO_MPIN_MPORTP_MASK (0xFFFFFFFFU)
+#define GPIO_MPIN_MPORTP_SHIFT (0U)
+#define GPIO_MPIN_MPORTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_MPIN_MPORTP_SHIFT)) & GPIO_MPIN_MPORTP_MASK)
+
+/* The count of GPIO_MPIN */
+#define GPIO_MPIN_COUNT (6U)
+
+/*! @name SET - Write: Set register for port Read: output bits for port */
+#define GPIO_SET_SETP_MASK (0xFFFFFFFFU)
+#define GPIO_SET_SETP_SHIFT (0U)
+#define GPIO_SET_SETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_SET_SETP_SHIFT)) & GPIO_SET_SETP_MASK)
+
+/* The count of GPIO_SET */
+#define GPIO_SET_COUNT (6U)
+
+/*! @name CLR - Clear port */
+#define GPIO_CLR_CLRP_MASK (0xFFFFFFFFU)
+#define GPIO_CLR_CLRP_SHIFT (0U)
+#define GPIO_CLR_CLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_CLR_CLRP_SHIFT)) & GPIO_CLR_CLRP_MASK)
+
+/* The count of GPIO_CLR */
+#define GPIO_CLR_COUNT (6U)
+
+/*! @name NOT - Toggle port */
+#define GPIO_NOT_NOTP_MASK (0xFFFFFFFFU)
+#define GPIO_NOT_NOTP_SHIFT (0U)
+#define GPIO_NOT_NOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_NOT_NOTP_SHIFT)) & GPIO_NOT_NOTP_MASK)
+
+/* The count of GPIO_NOT */
+#define GPIO_NOT_COUNT (6U)
+
+/*! @name DIRSET - Set pin direction bits for port */
+#define GPIO_DIRSET_DIRSETP_MASK (0x1FFFFFFFU)
+#define GPIO_DIRSET_DIRSETP_SHIFT (0U)
+#define GPIO_DIRSET_DIRSETP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRSET_DIRSETP_SHIFT)) & GPIO_DIRSET_DIRSETP_MASK)
+
+/* The count of GPIO_DIRSET */
+#define GPIO_DIRSET_COUNT (6U)
+
+/*! @name DIRCLR - Clear pin direction bits for port */
+#define GPIO_DIRCLR_DIRCLRP_MASK (0x1FFFFFFFU)
+#define GPIO_DIRCLR_DIRCLRP_SHIFT (0U)
+#define GPIO_DIRCLR_DIRCLRP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRCLR_DIRCLRP_SHIFT)) & GPIO_DIRCLR_DIRCLRP_MASK)
+
+/* The count of GPIO_DIRCLR */
+#define GPIO_DIRCLR_COUNT (6U)
+
+/*! @name DIRNOT - Toggle pin direction bits for port */
+#define GPIO_DIRNOT_DIRNOTP_MASK (0x1FFFFFFFU)
+#define GPIO_DIRNOT_DIRNOTP_SHIFT (0U)
+#define GPIO_DIRNOT_DIRNOTP(x) (((uint32_t)(((uint32_t)(x)) << GPIO_DIRNOT_DIRNOTP_SHIFT)) & GPIO_DIRNOT_DIRNOTP_MASK)
+
+/* The count of GPIO_DIRNOT */
+#define GPIO_DIRNOT_COUNT (6U)
+
+
+/*!
+ * @}
+ */ /* end of group GPIO_Register_Masks */
+
+
+/* GPIO - Peripheral instance base addresses */
+/** Peripheral GPIO base address */
+#define GPIO_BASE (0x4008C000u)
+/** Peripheral GPIO base pointer */
+#define GPIO ((GPIO_Type *)GPIO_BASE)
+/** Array initializer of GPIO peripheral base addresses */
+#define GPIO_BASE_ADDRS { GPIO_BASE }
+/** Array initializer of GPIO peripheral base pointers */
+#define GPIO_BASE_PTRS { GPIO }
+
+/*!
+ * @}
+ */ /* end of group GPIO_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2C Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Peripheral_Access_Layer I2C Peripheral Access Layer
+ * @{
+ */
+
+/** I2C - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[2048];
+ __IO uint32_t CFG; /**< Configuration for shared functions., offset: 0x800 */
+ __IO uint32_t STAT; /**< Status register for Master, Slave, and Monitor functions., offset: 0x804 */
+ __IO uint32_t INTENSET; /**< Interrupt Enable Set and read register., offset: 0x808 */
+ __O uint32_t INTENCLR; /**< Interrupt Enable Clear register., offset: 0x80C */
+ __IO uint32_t TIMEOUT; /**< Time-out value register., offset: 0x810 */
+ __IO uint32_t CLKDIV; /**< Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function., offset: 0x814 */
+ __I uint32_t INTSTAT; /**< Interrupt Status register for Master, Slave, and Monitor functions., offset: 0x818 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t MSTCTL; /**< Master control register., offset: 0x820 */
+ __IO uint32_t MSTTIME; /**< Master timing configuration., offset: 0x824 */
+ __IO uint32_t MSTDAT; /**< Combined Master receiver and transmitter data register., offset: 0x828 */
+ uint8_t RESERVED_2[20];
+ __IO uint32_t SLVCTL; /**< Slave control register., offset: 0x840 */
+ __IO uint32_t SLVDAT; /**< Combined Slave receiver and transmitter data register., offset: 0x844 */
+ __IO uint32_t SLVADR[4]; /**< Slave address register., array offset: 0x848, array step: 0x4 */
+ __IO uint32_t SLVQUAL0; /**< Slave Qualification for address 0., offset: 0x858 */
+ uint8_t RESERVED_3[36];
+ __I uint32_t MONRXDAT; /**< Monitor receiver data register., offset: 0x880 */
+ uint8_t RESERVED_4[1912];
+ __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */
+} I2C_Type;
+
+/* ----------------------------------------------------------------------------
+ -- I2C Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2C_Register_Masks I2C Register Masks
+ * @{
+ */
+
+/*! @name CFG - Configuration for shared functions. */
+#define I2C_CFG_MSTEN_MASK (0x1U)
+#define I2C_CFG_MSTEN_SHIFT (0U)
+#define I2C_CFG_MSTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MSTEN_SHIFT)) & I2C_CFG_MSTEN_MASK)
+#define I2C_CFG_SLVEN_MASK (0x2U)
+#define I2C_CFG_SLVEN_SHIFT (1U)
+#define I2C_CFG_SLVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_SLVEN_SHIFT)) & I2C_CFG_SLVEN_MASK)
+#define I2C_CFG_MONEN_MASK (0x4U)
+#define I2C_CFG_MONEN_SHIFT (2U)
+#define I2C_CFG_MONEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONEN_SHIFT)) & I2C_CFG_MONEN_MASK)
+#define I2C_CFG_TIMEOUTEN_MASK (0x8U)
+#define I2C_CFG_TIMEOUTEN_SHIFT (3U)
+#define I2C_CFG_TIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_TIMEOUTEN_SHIFT)) & I2C_CFG_TIMEOUTEN_MASK)
+#define I2C_CFG_MONCLKSTR_MASK (0x10U)
+#define I2C_CFG_MONCLKSTR_SHIFT (4U)
+#define I2C_CFG_MONCLKSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_MONCLKSTR_SHIFT)) & I2C_CFG_MONCLKSTR_MASK)
+#define I2C_CFG_HSCAPABLE_MASK (0x20U)
+#define I2C_CFG_HSCAPABLE_SHIFT (5U)
+#define I2C_CFG_HSCAPABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_CFG_HSCAPABLE_SHIFT)) & I2C_CFG_HSCAPABLE_MASK)
+
+/*! @name STAT - Status register for Master, Slave, and Monitor functions. */
+#define I2C_STAT_MSTPENDING_MASK (0x1U)
+#define I2C_STAT_MSTPENDING_SHIFT (0U)
+#define I2C_STAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTPENDING_SHIFT)) & I2C_STAT_MSTPENDING_MASK)
+#define I2C_STAT_MSTSTATE_MASK (0xEU)
+#define I2C_STAT_MSTSTATE_SHIFT (1U)
+#define I2C_STAT_MSTSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTATE_SHIFT)) & I2C_STAT_MSTSTATE_MASK)
+#define I2C_STAT_MSTARBLOSS_MASK (0x10U)
+#define I2C_STAT_MSTARBLOSS_SHIFT (4U)
+#define I2C_STAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTARBLOSS_SHIFT)) & I2C_STAT_MSTARBLOSS_MASK)
+#define I2C_STAT_MSTSTSTPERR_MASK (0x40U)
+#define I2C_STAT_MSTSTSTPERR_SHIFT (6U)
+#define I2C_STAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MSTSTSTPERR_SHIFT)) & I2C_STAT_MSTSTSTPERR_MASK)
+#define I2C_STAT_SLVPENDING_MASK (0x100U)
+#define I2C_STAT_SLVPENDING_SHIFT (8U)
+#define I2C_STAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVPENDING_SHIFT)) & I2C_STAT_SLVPENDING_MASK)
+#define I2C_STAT_SLVSTATE_MASK (0x600U)
+#define I2C_STAT_SLVSTATE_SHIFT (9U)
+#define I2C_STAT_SLVSTATE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSTATE_SHIFT)) & I2C_STAT_SLVSTATE_MASK)
+#define I2C_STAT_SLVNOTSTR_MASK (0x800U)
+#define I2C_STAT_SLVNOTSTR_SHIFT (11U)
+#define I2C_STAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVNOTSTR_SHIFT)) & I2C_STAT_SLVNOTSTR_MASK)
+#define I2C_STAT_SLVIDX_MASK (0x3000U)
+#define I2C_STAT_SLVIDX_SHIFT (12U)
+#define I2C_STAT_SLVIDX(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVIDX_SHIFT)) & I2C_STAT_SLVIDX_MASK)
+#define I2C_STAT_SLVSEL_MASK (0x4000U)
+#define I2C_STAT_SLVSEL_SHIFT (14U)
+#define I2C_STAT_SLVSEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVSEL_SHIFT)) & I2C_STAT_SLVSEL_MASK)
+#define I2C_STAT_SLVDESEL_MASK (0x8000U)
+#define I2C_STAT_SLVDESEL_SHIFT (15U)
+#define I2C_STAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SLVDESEL_SHIFT)) & I2C_STAT_SLVDESEL_MASK)
+#define I2C_STAT_MONRDY_MASK (0x10000U)
+#define I2C_STAT_MONRDY_SHIFT (16U)
+#define I2C_STAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONRDY_SHIFT)) & I2C_STAT_MONRDY_MASK)
+#define I2C_STAT_MONOV_MASK (0x20000U)
+#define I2C_STAT_MONOV_SHIFT (17U)
+#define I2C_STAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONOV_SHIFT)) & I2C_STAT_MONOV_MASK)
+#define I2C_STAT_MONACTIVE_MASK (0x40000U)
+#define I2C_STAT_MONACTIVE_SHIFT (18U)
+#define I2C_STAT_MONACTIVE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONACTIVE_SHIFT)) & I2C_STAT_MONACTIVE_MASK)
+#define I2C_STAT_MONIDLE_MASK (0x80000U)
+#define I2C_STAT_MONIDLE_SHIFT (19U)
+#define I2C_STAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_MONIDLE_SHIFT)) & I2C_STAT_MONIDLE_MASK)
+#define I2C_STAT_EVENTTIMEOUT_MASK (0x1000000U)
+#define I2C_STAT_EVENTTIMEOUT_SHIFT (24U)
+#define I2C_STAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_EVENTTIMEOUT_SHIFT)) & I2C_STAT_EVENTTIMEOUT_MASK)
+#define I2C_STAT_SCLTIMEOUT_MASK (0x2000000U)
+#define I2C_STAT_SCLTIMEOUT_SHIFT (25U)
+#define I2C_STAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_STAT_SCLTIMEOUT_SHIFT)) & I2C_STAT_SCLTIMEOUT_MASK)
+
+/*! @name INTENSET - Interrupt Enable Set and read register. */
+#define I2C_INTENSET_MSTPENDINGEN_MASK (0x1U)
+#define I2C_INTENSET_MSTPENDINGEN_SHIFT (0U)
+#define I2C_INTENSET_MSTPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTPENDINGEN_SHIFT)) & I2C_INTENSET_MSTPENDINGEN_MASK)
+#define I2C_INTENSET_MSTARBLOSSEN_MASK (0x10U)
+#define I2C_INTENSET_MSTARBLOSSEN_SHIFT (4U)
+#define I2C_INTENSET_MSTARBLOSSEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTARBLOSSEN_SHIFT)) & I2C_INTENSET_MSTARBLOSSEN_MASK)
+#define I2C_INTENSET_MSTSTSTPERREN_MASK (0x40U)
+#define I2C_INTENSET_MSTSTSTPERREN_SHIFT (6U)
+#define I2C_INTENSET_MSTSTSTPERREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MSTSTSTPERREN_SHIFT)) & I2C_INTENSET_MSTSTSTPERREN_MASK)
+#define I2C_INTENSET_SLVPENDINGEN_MASK (0x100U)
+#define I2C_INTENSET_SLVPENDINGEN_SHIFT (8U)
+#define I2C_INTENSET_SLVPENDINGEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVPENDINGEN_SHIFT)) & I2C_INTENSET_SLVPENDINGEN_MASK)
+#define I2C_INTENSET_SLVNOTSTREN_MASK (0x800U)
+#define I2C_INTENSET_SLVNOTSTREN_SHIFT (11U)
+#define I2C_INTENSET_SLVNOTSTREN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVNOTSTREN_SHIFT)) & I2C_INTENSET_SLVNOTSTREN_MASK)
+#define I2C_INTENSET_SLVDESELEN_MASK (0x8000U)
+#define I2C_INTENSET_SLVDESELEN_SHIFT (15U)
+#define I2C_INTENSET_SLVDESELEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SLVDESELEN_SHIFT)) & I2C_INTENSET_SLVDESELEN_MASK)
+#define I2C_INTENSET_MONRDYEN_MASK (0x10000U)
+#define I2C_INTENSET_MONRDYEN_SHIFT (16U)
+#define I2C_INTENSET_MONRDYEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONRDYEN_SHIFT)) & I2C_INTENSET_MONRDYEN_MASK)
+#define I2C_INTENSET_MONOVEN_MASK (0x20000U)
+#define I2C_INTENSET_MONOVEN_SHIFT (17U)
+#define I2C_INTENSET_MONOVEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONOVEN_SHIFT)) & I2C_INTENSET_MONOVEN_MASK)
+#define I2C_INTENSET_MONIDLEEN_MASK (0x80000U)
+#define I2C_INTENSET_MONIDLEEN_SHIFT (19U)
+#define I2C_INTENSET_MONIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_MONIDLEEN_SHIFT)) & I2C_INTENSET_MONIDLEEN_MASK)
+#define I2C_INTENSET_EVENTTIMEOUTEN_MASK (0x1000000U)
+#define I2C_INTENSET_EVENTTIMEOUTEN_SHIFT (24U)
+#define I2C_INTENSET_EVENTTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_EVENTTIMEOUTEN_SHIFT)) & I2C_INTENSET_EVENTTIMEOUTEN_MASK)
+#define I2C_INTENSET_SCLTIMEOUTEN_MASK (0x2000000U)
+#define I2C_INTENSET_SCLTIMEOUTEN_SHIFT (25U)
+#define I2C_INTENSET_SCLTIMEOUTEN(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENSET_SCLTIMEOUTEN_SHIFT)) & I2C_INTENSET_SCLTIMEOUTEN_MASK)
+
+/*! @name INTENCLR - Interrupt Enable Clear register. */
+#define I2C_INTENCLR_MSTPENDINGCLR_MASK (0x1U)
+#define I2C_INTENCLR_MSTPENDINGCLR_SHIFT (0U)
+#define I2C_INTENCLR_MSTPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTPENDINGCLR_SHIFT)) & I2C_INTENCLR_MSTPENDINGCLR_MASK)
+#define I2C_INTENCLR_MSTARBLOSSCLR_MASK (0x10U)
+#define I2C_INTENCLR_MSTARBLOSSCLR_SHIFT (4U)
+#define I2C_INTENCLR_MSTARBLOSSCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTARBLOSSCLR_SHIFT)) & I2C_INTENCLR_MSTARBLOSSCLR_MASK)
+#define I2C_INTENCLR_MSTSTSTPERRCLR_MASK (0x40U)
+#define I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT (6U)
+#define I2C_INTENCLR_MSTSTSTPERRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MSTSTSTPERRCLR_SHIFT)) & I2C_INTENCLR_MSTSTSTPERRCLR_MASK)
+#define I2C_INTENCLR_SLVPENDINGCLR_MASK (0x100U)
+#define I2C_INTENCLR_SLVPENDINGCLR_SHIFT (8U)
+#define I2C_INTENCLR_SLVPENDINGCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVPENDINGCLR_SHIFT)) & I2C_INTENCLR_SLVPENDINGCLR_MASK)
+#define I2C_INTENCLR_SLVNOTSTRCLR_MASK (0x800U)
+#define I2C_INTENCLR_SLVNOTSTRCLR_SHIFT (11U)
+#define I2C_INTENCLR_SLVNOTSTRCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVNOTSTRCLR_SHIFT)) & I2C_INTENCLR_SLVNOTSTRCLR_MASK)
+#define I2C_INTENCLR_SLVDESELCLR_MASK (0x8000U)
+#define I2C_INTENCLR_SLVDESELCLR_SHIFT (15U)
+#define I2C_INTENCLR_SLVDESELCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SLVDESELCLR_SHIFT)) & I2C_INTENCLR_SLVDESELCLR_MASK)
+#define I2C_INTENCLR_MONRDYCLR_MASK (0x10000U)
+#define I2C_INTENCLR_MONRDYCLR_SHIFT (16U)
+#define I2C_INTENCLR_MONRDYCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONRDYCLR_SHIFT)) & I2C_INTENCLR_MONRDYCLR_MASK)
+#define I2C_INTENCLR_MONOVCLR_MASK (0x20000U)
+#define I2C_INTENCLR_MONOVCLR_SHIFT (17U)
+#define I2C_INTENCLR_MONOVCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONOVCLR_SHIFT)) & I2C_INTENCLR_MONOVCLR_MASK)
+#define I2C_INTENCLR_MONIDLECLR_MASK (0x80000U)
+#define I2C_INTENCLR_MONIDLECLR_SHIFT (19U)
+#define I2C_INTENCLR_MONIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_MONIDLECLR_SHIFT)) & I2C_INTENCLR_MONIDLECLR_MASK)
+#define I2C_INTENCLR_EVENTTIMEOUTCLR_MASK (0x1000000U)
+#define I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT (24U)
+#define I2C_INTENCLR_EVENTTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_EVENTTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_EVENTTIMEOUTCLR_MASK)
+#define I2C_INTENCLR_SCLTIMEOUTCLR_MASK (0x2000000U)
+#define I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT (25U)
+#define I2C_INTENCLR_SCLTIMEOUTCLR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTENCLR_SCLTIMEOUTCLR_SHIFT)) & I2C_INTENCLR_SCLTIMEOUTCLR_MASK)
+
+/*! @name TIMEOUT - Time-out value register. */
+#define I2C_TIMEOUT_TOMIN_MASK (0xFU)
+#define I2C_TIMEOUT_TOMIN_SHIFT (0U)
+#define I2C_TIMEOUT_TOMIN(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TOMIN_SHIFT)) & I2C_TIMEOUT_TOMIN_MASK)
+#define I2C_TIMEOUT_TO_MASK (0xFFF0U)
+#define I2C_TIMEOUT_TO_SHIFT (4U)
+#define I2C_TIMEOUT_TO(x) (((uint32_t)(((uint32_t)(x)) << I2C_TIMEOUT_TO_SHIFT)) & I2C_TIMEOUT_TO_MASK)
+
+/*! @name CLKDIV - Clock pre-divider for the entire I2C interface. This determines what time increments are used for the MSTTIME register, and controls some timing of the Slave function. */
+#define I2C_CLKDIV_DIVVAL_MASK (0xFFFFU)
+#define I2C_CLKDIV_DIVVAL_SHIFT (0U)
+#define I2C_CLKDIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << I2C_CLKDIV_DIVVAL_SHIFT)) & I2C_CLKDIV_DIVVAL_MASK)
+
+/*! @name INTSTAT - Interrupt Status register for Master, Slave, and Monitor functions. */
+#define I2C_INTSTAT_MSTPENDING_MASK (0x1U)
+#define I2C_INTSTAT_MSTPENDING_SHIFT (0U)
+#define I2C_INTSTAT_MSTPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTPENDING_SHIFT)) & I2C_INTSTAT_MSTPENDING_MASK)
+#define I2C_INTSTAT_MSTARBLOSS_MASK (0x10U)
+#define I2C_INTSTAT_MSTARBLOSS_SHIFT (4U)
+#define I2C_INTSTAT_MSTARBLOSS(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTARBLOSS_SHIFT)) & I2C_INTSTAT_MSTARBLOSS_MASK)
+#define I2C_INTSTAT_MSTSTSTPERR_MASK (0x40U)
+#define I2C_INTSTAT_MSTSTSTPERR_SHIFT (6U)
+#define I2C_INTSTAT_MSTSTSTPERR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MSTSTSTPERR_SHIFT)) & I2C_INTSTAT_MSTSTSTPERR_MASK)
+#define I2C_INTSTAT_SLVPENDING_MASK (0x100U)
+#define I2C_INTSTAT_SLVPENDING_SHIFT (8U)
+#define I2C_INTSTAT_SLVPENDING(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVPENDING_SHIFT)) & I2C_INTSTAT_SLVPENDING_MASK)
+#define I2C_INTSTAT_SLVNOTSTR_MASK (0x800U)
+#define I2C_INTSTAT_SLVNOTSTR_SHIFT (11U)
+#define I2C_INTSTAT_SLVNOTSTR(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVNOTSTR_SHIFT)) & I2C_INTSTAT_SLVNOTSTR_MASK)
+#define I2C_INTSTAT_SLVDESEL_MASK (0x8000U)
+#define I2C_INTSTAT_SLVDESEL_SHIFT (15U)
+#define I2C_INTSTAT_SLVDESEL(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SLVDESEL_SHIFT)) & I2C_INTSTAT_SLVDESEL_MASK)
+#define I2C_INTSTAT_MONRDY_MASK (0x10000U)
+#define I2C_INTSTAT_MONRDY_SHIFT (16U)
+#define I2C_INTSTAT_MONRDY(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONRDY_SHIFT)) & I2C_INTSTAT_MONRDY_MASK)
+#define I2C_INTSTAT_MONOV_MASK (0x20000U)
+#define I2C_INTSTAT_MONOV_SHIFT (17U)
+#define I2C_INTSTAT_MONOV(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONOV_SHIFT)) & I2C_INTSTAT_MONOV_MASK)
+#define I2C_INTSTAT_MONIDLE_MASK (0x80000U)
+#define I2C_INTSTAT_MONIDLE_SHIFT (19U)
+#define I2C_INTSTAT_MONIDLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_MONIDLE_SHIFT)) & I2C_INTSTAT_MONIDLE_MASK)
+#define I2C_INTSTAT_EVENTTIMEOUT_MASK (0x1000000U)
+#define I2C_INTSTAT_EVENTTIMEOUT_SHIFT (24U)
+#define I2C_INTSTAT_EVENTTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_EVENTTIMEOUT_SHIFT)) & I2C_INTSTAT_EVENTTIMEOUT_MASK)
+#define I2C_INTSTAT_SCLTIMEOUT_MASK (0x2000000U)
+#define I2C_INTSTAT_SCLTIMEOUT_SHIFT (25U)
+#define I2C_INTSTAT_SCLTIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << I2C_INTSTAT_SCLTIMEOUT_SHIFT)) & I2C_INTSTAT_SCLTIMEOUT_MASK)
+
+/*! @name MSTCTL - Master control register. */
+#define I2C_MSTCTL_MSTCONTINUE_MASK (0x1U)
+#define I2C_MSTCTL_MSTCONTINUE_SHIFT (0U)
+#define I2C_MSTCTL_MSTCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTCONTINUE_SHIFT)) & I2C_MSTCTL_MSTCONTINUE_MASK)
+#define I2C_MSTCTL_MSTSTART_MASK (0x2U)
+#define I2C_MSTCTL_MSTSTART_SHIFT (1U)
+#define I2C_MSTCTL_MSTSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTART_SHIFT)) & I2C_MSTCTL_MSTSTART_MASK)
+#define I2C_MSTCTL_MSTSTOP_MASK (0x4U)
+#define I2C_MSTCTL_MSTSTOP_SHIFT (2U)
+#define I2C_MSTCTL_MSTSTOP(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTSTOP_SHIFT)) & I2C_MSTCTL_MSTSTOP_MASK)
+#define I2C_MSTCTL_MSTDMA_MASK (0x8U)
+#define I2C_MSTCTL_MSTDMA_SHIFT (3U)
+#define I2C_MSTCTL_MSTDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTCTL_MSTDMA_SHIFT)) & I2C_MSTCTL_MSTDMA_MASK)
+
+/*! @name MSTTIME - Master timing configuration. */
+#define I2C_MSTTIME_MSTSCLLOW_MASK (0x7U)
+#define I2C_MSTTIME_MSTSCLLOW_SHIFT (0U)
+#define I2C_MSTTIME_MSTSCLLOW(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLLOW_SHIFT)) & I2C_MSTTIME_MSTSCLLOW_MASK)
+#define I2C_MSTTIME_MSTSCLHIGH_MASK (0x70U)
+#define I2C_MSTTIME_MSTSCLHIGH_SHIFT (4U)
+#define I2C_MSTTIME_MSTSCLHIGH(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTTIME_MSTSCLHIGH_SHIFT)) & I2C_MSTTIME_MSTSCLHIGH_MASK)
+
+/*! @name MSTDAT - Combined Master receiver and transmitter data register. */
+#define I2C_MSTDAT_DATA_MASK (0xFFU)
+#define I2C_MSTDAT_DATA_SHIFT (0U)
+#define I2C_MSTDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_MSTDAT_DATA_SHIFT)) & I2C_MSTDAT_DATA_MASK)
+
+/*! @name SLVCTL - Slave control register. */
+#define I2C_SLVCTL_SLVCONTINUE_MASK (0x1U)
+#define I2C_SLVCTL_SLVCONTINUE_SHIFT (0U)
+#define I2C_SLVCTL_SLVCONTINUE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVCONTINUE_SHIFT)) & I2C_SLVCTL_SLVCONTINUE_MASK)
+#define I2C_SLVCTL_SLVNACK_MASK (0x2U)
+#define I2C_SLVCTL_SLVNACK_SHIFT (1U)
+#define I2C_SLVCTL_SLVNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVNACK_SHIFT)) & I2C_SLVCTL_SLVNACK_MASK)
+#define I2C_SLVCTL_SLVDMA_MASK (0x8U)
+#define I2C_SLVCTL_SLVDMA_SHIFT (3U)
+#define I2C_SLVCTL_SLVDMA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_SLVDMA_SHIFT)) & I2C_SLVCTL_SLVDMA_MASK)
+#define I2C_SLVCTL_AUTOACK_MASK (0x100U)
+#define I2C_SLVCTL_AUTOACK_SHIFT (8U)
+#define I2C_SLVCTL_AUTOACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOACK_SHIFT)) & I2C_SLVCTL_AUTOACK_MASK)
+#define I2C_SLVCTL_AUTOMATCHREAD_MASK (0x200U)
+#define I2C_SLVCTL_AUTOMATCHREAD_SHIFT (9U)
+#define I2C_SLVCTL_AUTOMATCHREAD(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVCTL_AUTOMATCHREAD_SHIFT)) & I2C_SLVCTL_AUTOMATCHREAD_MASK)
+
+/*! @name SLVDAT - Combined Slave receiver and transmitter data register. */
+#define I2C_SLVDAT_DATA_MASK (0xFFU)
+#define I2C_SLVDAT_DATA_SHIFT (0U)
+#define I2C_SLVDAT_DATA(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVDAT_DATA_SHIFT)) & I2C_SLVDAT_DATA_MASK)
+
+/*! @name SLVADR - Slave address register. */
+#define I2C_SLVADR_SADISABLE_MASK (0x1U)
+#define I2C_SLVADR_SADISABLE_SHIFT (0U)
+#define I2C_SLVADR_SADISABLE(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SADISABLE_SHIFT)) & I2C_SLVADR_SADISABLE_MASK)
+#define I2C_SLVADR_SLVADR_MASK (0xFEU)
+#define I2C_SLVADR_SLVADR_SHIFT (1U)
+#define I2C_SLVADR_SLVADR(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_SLVADR_SHIFT)) & I2C_SLVADR_SLVADR_MASK)
+#define I2C_SLVADR_AUTONACK_MASK (0x8000U)
+#define I2C_SLVADR_AUTONACK_SHIFT (15U)
+#define I2C_SLVADR_AUTONACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVADR_AUTONACK_SHIFT)) & I2C_SLVADR_AUTONACK_MASK)
+
+/* The count of I2C_SLVADR */
+#define I2C_SLVADR_COUNT (4U)
+
+/*! @name SLVQUAL0 - Slave Qualification for address 0. */
+#define I2C_SLVQUAL0_QUALMODE0_MASK (0x1U)
+#define I2C_SLVQUAL0_QUALMODE0_SHIFT (0U)
+#define I2C_SLVQUAL0_QUALMODE0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_QUALMODE0_SHIFT)) & I2C_SLVQUAL0_QUALMODE0_MASK)
+#define I2C_SLVQUAL0_SLVQUAL0_MASK (0xFEU)
+#define I2C_SLVQUAL0_SLVQUAL0_SHIFT (1U)
+#define I2C_SLVQUAL0_SLVQUAL0(x) (((uint32_t)(((uint32_t)(x)) << I2C_SLVQUAL0_SLVQUAL0_SHIFT)) & I2C_SLVQUAL0_SLVQUAL0_MASK)
+
+/*! @name MONRXDAT - Monitor receiver data register. */
+#define I2C_MONRXDAT_MONRXDAT_MASK (0xFFU)
+#define I2C_MONRXDAT_MONRXDAT_SHIFT (0U)
+#define I2C_MONRXDAT_MONRXDAT(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRXDAT_SHIFT)) & I2C_MONRXDAT_MONRXDAT_MASK)
+#define I2C_MONRXDAT_MONSTART_MASK (0x100U)
+#define I2C_MONRXDAT_MONSTART_SHIFT (8U)
+#define I2C_MONRXDAT_MONSTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONSTART_SHIFT)) & I2C_MONRXDAT_MONSTART_MASK)
+#define I2C_MONRXDAT_MONRESTART_MASK (0x200U)
+#define I2C_MONRXDAT_MONRESTART_SHIFT (9U)
+#define I2C_MONRXDAT_MONRESTART(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONRESTART_SHIFT)) & I2C_MONRXDAT_MONRESTART_MASK)
+#define I2C_MONRXDAT_MONNACK_MASK (0x400U)
+#define I2C_MONRXDAT_MONNACK_SHIFT (10U)
+#define I2C_MONRXDAT_MONNACK(x) (((uint32_t)(((uint32_t)(x)) << I2C_MONRXDAT_MONNACK_SHIFT)) & I2C_MONRXDAT_MONNACK_MASK)
+
+/*! @name ID - Peripheral identification register. */
+#define I2C_ID_APERTURE_MASK (0xFFU)
+#define I2C_ID_APERTURE_SHIFT (0U)
+#define I2C_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_APERTURE_SHIFT)) & I2C_ID_APERTURE_MASK)
+#define I2C_ID_MINOR_REV_MASK (0xF00U)
+#define I2C_ID_MINOR_REV_SHIFT (8U)
+#define I2C_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MINOR_REV_SHIFT)) & I2C_ID_MINOR_REV_MASK)
+#define I2C_ID_MAJOR_REV_MASK (0xF000U)
+#define I2C_ID_MAJOR_REV_SHIFT (12U)
+#define I2C_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_MAJOR_REV_SHIFT)) & I2C_ID_MAJOR_REV_MASK)
+#define I2C_ID_ID_MASK (0xFFFF0000U)
+#define I2C_ID_ID_SHIFT (16U)
+#define I2C_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2C_ID_ID_SHIFT)) & I2C_ID_ID_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group I2C_Register_Masks */
+
+
+/* I2C - Peripheral instance base addresses */
+/** Peripheral I2C0 base address */
+#define I2C0_BASE (0x40086000u)
+/** Peripheral I2C0 base pointer */
+#define I2C0 ((I2C_Type *)I2C0_BASE)
+/** Peripheral I2C1 base address */
+#define I2C1_BASE (0x40087000u)
+/** Peripheral I2C1 base pointer */
+#define I2C1 ((I2C_Type *)I2C1_BASE)
+/** Peripheral I2C2 base address */
+#define I2C2_BASE (0x40088000u)
+/** Peripheral I2C2 base pointer */
+#define I2C2 ((I2C_Type *)I2C2_BASE)
+/** Peripheral I2C3 base address */
+#define I2C3_BASE (0x40089000u)
+/** Peripheral I2C3 base pointer */
+#define I2C3 ((I2C_Type *)I2C3_BASE)
+/** Peripheral I2C4 base address */
+#define I2C4_BASE (0x4008A000u)
+/** Peripheral I2C4 base pointer */
+#define I2C4 ((I2C_Type *)I2C4_BASE)
+/** Peripheral I2C5 base address */
+#define I2C5_BASE (0x40096000u)
+/** Peripheral I2C5 base pointer */
+#define I2C5 ((I2C_Type *)I2C5_BASE)
+/** Peripheral I2C6 base address */
+#define I2C6_BASE (0x40097000u)
+/** Peripheral I2C6 base pointer */
+#define I2C6 ((I2C_Type *)I2C6_BASE)
+/** Peripheral I2C7 base address */
+#define I2C7_BASE (0x40098000u)
+/** Peripheral I2C7 base pointer */
+#define I2C7 ((I2C_Type *)I2C7_BASE)
+/** Peripheral I2C8 base address */
+#define I2C8_BASE (0x40099000u)
+/** Peripheral I2C8 base pointer */
+#define I2C8 ((I2C_Type *)I2C8_BASE)
+/** Peripheral I2C9 base address */
+#define I2C9_BASE (0x4009A000u)
+/** Peripheral I2C9 base pointer */
+#define I2C9 ((I2C_Type *)I2C9_BASE)
+/** Array initializer of I2C peripheral base addresses */
+#define I2C_BASE_ADDRS { I2C0_BASE, I2C1_BASE, I2C2_BASE, I2C3_BASE, I2C4_BASE, I2C5_BASE, I2C6_BASE, I2C7_BASE, I2C8_BASE, I2C9_BASE }
+/** Array initializer of I2C peripheral base pointers */
+#define I2C_BASE_PTRS { I2C0, I2C1, I2C2, I2C3, I2C4, I2C5, I2C6, I2C7, I2C8, I2C9 }
+/** Interrupt vectors for the I2C peripheral type */
+#define I2C_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn }
+
+/*!
+ * @}
+ */ /* end of group I2C_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- I2S Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Peripheral_Access_Layer I2S Peripheral Access Layer
+ * @{
+ */
+
+/** I2S - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[32];
+ struct { /* offset: 0x20, array step: 0x20 */
+ __IO uint32_t PCFG1; /**< Configuration register 1 for channel pair, array offset: 0x20, array step: 0x20 */
+ __IO uint32_t PCFG2; /**< Configuration register 2 for channel pair, array offset: 0x24, array step: 0x20 */
+ __IO uint32_t PSTAT; /**< Status register for channel pair, array offset: 0x28, array step: 0x20 */
+ uint8_t RESERVED_0[20];
+ } SECCHANNEL[3];
+ uint8_t RESERVED_1[2944];
+ __IO uint32_t CFG1; /**< Configuration register 1 for the primary channel pair., offset: 0xC00 */
+ __IO uint32_t CFG2; /**< Configuration register 2 for the primary channel pair., offset: 0xC04 */
+ __IO uint32_t STAT; /**< Status register for the primary channel pair., offset: 0xC08 */
+ uint8_t RESERVED_2[16];
+ __IO uint32_t DIV; /**< Clock divider, used by all channel pairs., offset: 0xC1C */
+ uint8_t RESERVED_3[480];
+ __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */
+ __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */
+ __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */
+ uint8_t RESERVED_4[4];
+ __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */
+ __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */
+ __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */
+ uint8_t RESERVED_5[4];
+ __O uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */
+ __O uint32_t FIFOWR48H; /**< FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE24 */
+ uint8_t RESERVED_6[8];
+ __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */
+ __I uint32_t FIFORD48H; /**< FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE34 */
+ uint8_t RESERVED_7[8];
+ __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */
+ __I uint32_t FIFORD48HNOPOP; /**< FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA., offset: 0xE44 */
+ uint8_t RESERVED_8[4020];
+ __I uint32_t ID; /**< I2S Module identification, offset: 0x1DFC */
+} I2S_Type;
+
+/* ----------------------------------------------------------------------------
+ -- I2S Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup I2S_Register_Masks I2S Register Masks
+ * @{
+ */
+
+/*! @name SECCHANNEL_PCFG1 - Configuration register 1 for channel pair */
+#define I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK (0x1U)
+#define I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT (0U)
+#define I2S_SECCHANNEL_PCFG1_PAIRENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_PAIRENABLE_SHIFT)) & I2S_SECCHANNEL_PCFG1_PAIRENABLE_MASK)
+#define I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK (0x400U)
+#define I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT (10U)
+#define I2S_SECCHANNEL_PCFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG1_ONECHANNEL_SHIFT)) & I2S_SECCHANNEL_PCFG1_ONECHANNEL_MASK)
+
+/* The count of I2S_SECCHANNEL_PCFG1 */
+#define I2S_SECCHANNEL_PCFG1_COUNT (3U)
+
+/*! @name SECCHANNEL_PCFG2 - Configuration register 2 for channel pair */
+#define I2S_SECCHANNEL_PCFG2_POSITION_MASK (0x1FF0000U)
+#define I2S_SECCHANNEL_PCFG2_POSITION_SHIFT (16U)
+#define I2S_SECCHANNEL_PCFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PCFG2_POSITION_SHIFT)) & I2S_SECCHANNEL_PCFG2_POSITION_MASK)
+
+/* The count of I2S_SECCHANNEL_PCFG2 */
+#define I2S_SECCHANNEL_PCFG2_COUNT (3U)
+
+/*! @name SECCHANNEL_PSTAT - Status register for channel pair */
+#define I2S_SECCHANNEL_PSTAT_BUSY_MASK (0x1U)
+#define I2S_SECCHANNEL_PSTAT_BUSY_SHIFT (0U)
+#define I2S_SECCHANNEL_PSTAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_BUSY_SHIFT)) & I2S_SECCHANNEL_PSTAT_BUSY_MASK)
+#define I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK (0x2U)
+#define I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT (1U)
+#define I2S_SECCHANNEL_PSTAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_SLVFRMERR_SHIFT)) & I2S_SECCHANNEL_PSTAT_SLVFRMERR_MASK)
+#define I2S_SECCHANNEL_PSTAT_LR_MASK (0x4U)
+#define I2S_SECCHANNEL_PSTAT_LR_SHIFT (2U)
+#define I2S_SECCHANNEL_PSTAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_LR_SHIFT)) & I2S_SECCHANNEL_PSTAT_LR_MASK)
+#define I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK (0x8U)
+#define I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT (3U)
+#define I2S_SECCHANNEL_PSTAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_SECCHANNEL_PSTAT_DATAPAUSED_SHIFT)) & I2S_SECCHANNEL_PSTAT_DATAPAUSED_MASK)
+
+/* The count of I2S_SECCHANNEL_PSTAT */
+#define I2S_SECCHANNEL_PSTAT_COUNT (3U)
+
+/*! @name CFG1 - Configuration register 1 for the primary channel pair. */
+#define I2S_CFG1_MAINENABLE_MASK (0x1U)
+#define I2S_CFG1_MAINENABLE_SHIFT (0U)
+#define I2S_CFG1_MAINENABLE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MAINENABLE_SHIFT)) & I2S_CFG1_MAINENABLE_MASK)
+#define I2S_CFG1_DATAPAUSE_MASK (0x2U)
+#define I2S_CFG1_DATAPAUSE_SHIFT (1U)
+#define I2S_CFG1_DATAPAUSE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATAPAUSE_SHIFT)) & I2S_CFG1_DATAPAUSE_MASK)
+#define I2S_CFG1_PAIRCOUNT_MASK (0xCU)
+#define I2S_CFG1_PAIRCOUNT_SHIFT (2U)
+#define I2S_CFG1_PAIRCOUNT(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PAIRCOUNT_SHIFT)) & I2S_CFG1_PAIRCOUNT_MASK)
+#define I2S_CFG1_MSTSLVCFG_MASK (0x30U)
+#define I2S_CFG1_MSTSLVCFG_SHIFT (4U)
+#define I2S_CFG1_MSTSLVCFG(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MSTSLVCFG_SHIFT)) & I2S_CFG1_MSTSLVCFG_MASK)
+#define I2S_CFG1_MODE_MASK (0xC0U)
+#define I2S_CFG1_MODE_SHIFT (6U)
+#define I2S_CFG1_MODE(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_MODE_SHIFT)) & I2S_CFG1_MODE_MASK)
+#define I2S_CFG1_RIGHTLOW_MASK (0x100U)
+#define I2S_CFG1_RIGHTLOW_SHIFT (8U)
+#define I2S_CFG1_RIGHTLOW(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_RIGHTLOW_SHIFT)) & I2S_CFG1_RIGHTLOW_MASK)
+#define I2S_CFG1_LEFTJUST_MASK (0x200U)
+#define I2S_CFG1_LEFTJUST_SHIFT (9U)
+#define I2S_CFG1_LEFTJUST(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_LEFTJUST_SHIFT)) & I2S_CFG1_LEFTJUST_MASK)
+#define I2S_CFG1_ONECHANNEL_MASK (0x400U)
+#define I2S_CFG1_ONECHANNEL_SHIFT (10U)
+#define I2S_CFG1_ONECHANNEL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_ONECHANNEL_SHIFT)) & I2S_CFG1_ONECHANNEL_MASK)
+#define I2S_CFG1_PDMDATA_MASK (0x800U)
+#define I2S_CFG1_PDMDATA_SHIFT (11U)
+#define I2S_CFG1_PDMDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_PDMDATA_SHIFT)) & I2S_CFG1_PDMDATA_MASK)
+#define I2S_CFG1_SCK_POL_MASK (0x1000U)
+#define I2S_CFG1_SCK_POL_SHIFT (12U)
+#define I2S_CFG1_SCK_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_SCK_POL_SHIFT)) & I2S_CFG1_SCK_POL_MASK)
+#define I2S_CFG1_WS_POL_MASK (0x2000U)
+#define I2S_CFG1_WS_POL_SHIFT (13U)
+#define I2S_CFG1_WS_POL(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_WS_POL_SHIFT)) & I2S_CFG1_WS_POL_MASK)
+#define I2S_CFG1_DATALEN_MASK (0x1F0000U)
+#define I2S_CFG1_DATALEN_SHIFT (16U)
+#define I2S_CFG1_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG1_DATALEN_SHIFT)) & I2S_CFG1_DATALEN_MASK)
+
+/*! @name CFG2 - Configuration register 2 for the primary channel pair. */
+#define I2S_CFG2_FRAMELEN_MASK (0x1FFU)
+#define I2S_CFG2_FRAMELEN_SHIFT (0U)
+#define I2S_CFG2_FRAMELEN(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_FRAMELEN_SHIFT)) & I2S_CFG2_FRAMELEN_MASK)
+#define I2S_CFG2_POSITION_MASK (0x1FF0000U)
+#define I2S_CFG2_POSITION_SHIFT (16U)
+#define I2S_CFG2_POSITION(x) (((uint32_t)(((uint32_t)(x)) << I2S_CFG2_POSITION_SHIFT)) & I2S_CFG2_POSITION_MASK)
+
+/*! @name STAT - Status register for the primary channel pair. */
+#define I2S_STAT_BUSY_MASK (0x1U)
+#define I2S_STAT_BUSY_SHIFT (0U)
+#define I2S_STAT_BUSY(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_BUSY_SHIFT)) & I2S_STAT_BUSY_MASK)
+#define I2S_STAT_SLVFRMERR_MASK (0x2U)
+#define I2S_STAT_SLVFRMERR_SHIFT (1U)
+#define I2S_STAT_SLVFRMERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_SLVFRMERR_SHIFT)) & I2S_STAT_SLVFRMERR_MASK)
+#define I2S_STAT_LR_MASK (0x4U)
+#define I2S_STAT_LR_SHIFT (2U)
+#define I2S_STAT_LR(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_LR_SHIFT)) & I2S_STAT_LR_MASK)
+#define I2S_STAT_DATAPAUSED_MASK (0x8U)
+#define I2S_STAT_DATAPAUSED_SHIFT (3U)
+#define I2S_STAT_DATAPAUSED(x) (((uint32_t)(((uint32_t)(x)) << I2S_STAT_DATAPAUSED_SHIFT)) & I2S_STAT_DATAPAUSED_MASK)
+
+/*! @name DIV - Clock divider, used by all channel pairs. */
+#define I2S_DIV_DIV_MASK (0xFFFU)
+#define I2S_DIV_DIV_SHIFT (0U)
+#define I2S_DIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << I2S_DIV_DIV_SHIFT)) & I2S_DIV_DIV_MASK)
+
+/*! @name FIFOCFG - FIFO configuration and enable register. */
+#define I2S_FIFOCFG_ENABLETX_MASK (0x1U)
+#define I2S_FIFOCFG_ENABLETX_SHIFT (0U)
+#define I2S_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLETX_SHIFT)) & I2S_FIFOCFG_ENABLETX_MASK)
+#define I2S_FIFOCFG_ENABLERX_MASK (0x2U)
+#define I2S_FIFOCFG_ENABLERX_SHIFT (1U)
+#define I2S_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_ENABLERX_SHIFT)) & I2S_FIFOCFG_ENABLERX_MASK)
+#define I2S_FIFOCFG_TXI2SE0_MASK (0x4U)
+#define I2S_FIFOCFG_TXI2SE0_SHIFT (2U)
+#define I2S_FIFOCFG_TXI2SE0(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_TXI2SE0_SHIFT)) & I2S_FIFOCFG_TXI2SE0_MASK)
+#define I2S_FIFOCFG_PACK48_MASK (0x8U)
+#define I2S_FIFOCFG_PACK48_SHIFT (3U)
+#define I2S_FIFOCFG_PACK48(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_PACK48_SHIFT)) & I2S_FIFOCFG_PACK48_MASK)
+#define I2S_FIFOCFG_SIZE_MASK (0x30U)
+#define I2S_FIFOCFG_SIZE_SHIFT (4U)
+#define I2S_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_SIZE_SHIFT)) & I2S_FIFOCFG_SIZE_MASK)
+#define I2S_FIFOCFG_DMATX_MASK (0x1000U)
+#define I2S_FIFOCFG_DMATX_SHIFT (12U)
+#define I2S_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMATX_SHIFT)) & I2S_FIFOCFG_DMATX_MASK)
+#define I2S_FIFOCFG_DMARX_MASK (0x2000U)
+#define I2S_FIFOCFG_DMARX_SHIFT (13U)
+#define I2S_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_DMARX_SHIFT)) & I2S_FIFOCFG_DMARX_MASK)
+#define I2S_FIFOCFG_WAKETX_MASK (0x4000U)
+#define I2S_FIFOCFG_WAKETX_SHIFT (14U)
+#define I2S_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKETX_SHIFT)) & I2S_FIFOCFG_WAKETX_MASK)
+#define I2S_FIFOCFG_WAKERX_MASK (0x8000U)
+#define I2S_FIFOCFG_WAKERX_SHIFT (15U)
+#define I2S_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_WAKERX_SHIFT)) & I2S_FIFOCFG_WAKERX_MASK)
+#define I2S_FIFOCFG_EMPTYTX_MASK (0x10000U)
+#define I2S_FIFOCFG_EMPTYTX_SHIFT (16U)
+#define I2S_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYTX_SHIFT)) & I2S_FIFOCFG_EMPTYTX_MASK)
+#define I2S_FIFOCFG_EMPTYRX_MASK (0x20000U)
+#define I2S_FIFOCFG_EMPTYRX_SHIFT (17U)
+#define I2S_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_EMPTYRX_SHIFT)) & I2S_FIFOCFG_EMPTYRX_MASK)
+#define I2S_FIFOCFG_POPDBG_MASK (0x40000U)
+#define I2S_FIFOCFG_POPDBG_SHIFT (18U)
+#define I2S_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOCFG_POPDBG_SHIFT)) & I2S_FIFOCFG_POPDBG_MASK)
+
+/*! @name FIFOSTAT - FIFO status register. */
+#define I2S_FIFOSTAT_TXERR_MASK (0x1U)
+#define I2S_FIFOSTAT_TXERR_SHIFT (0U)
+#define I2S_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXERR_SHIFT)) & I2S_FIFOSTAT_TXERR_MASK)
+#define I2S_FIFOSTAT_RXERR_MASK (0x2U)
+#define I2S_FIFOSTAT_RXERR_SHIFT (1U)
+#define I2S_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXERR_SHIFT)) & I2S_FIFOSTAT_RXERR_MASK)
+#define I2S_FIFOSTAT_PERINT_MASK (0x8U)
+#define I2S_FIFOSTAT_PERINT_SHIFT (3U)
+#define I2S_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_PERINT_SHIFT)) & I2S_FIFOSTAT_PERINT_MASK)
+#define I2S_FIFOSTAT_TXEMPTY_MASK (0x10U)
+#define I2S_FIFOSTAT_TXEMPTY_SHIFT (4U)
+#define I2S_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXEMPTY_SHIFT)) & I2S_FIFOSTAT_TXEMPTY_MASK)
+#define I2S_FIFOSTAT_TXNOTFULL_MASK (0x20U)
+#define I2S_FIFOSTAT_TXNOTFULL_SHIFT (5U)
+#define I2S_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXNOTFULL_SHIFT)) & I2S_FIFOSTAT_TXNOTFULL_MASK)
+#define I2S_FIFOSTAT_RXNOTEMPTY_MASK (0x40U)
+#define I2S_FIFOSTAT_RXNOTEMPTY_SHIFT (6U)
+#define I2S_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXNOTEMPTY_SHIFT)) & I2S_FIFOSTAT_RXNOTEMPTY_MASK)
+#define I2S_FIFOSTAT_RXFULL_MASK (0x80U)
+#define I2S_FIFOSTAT_RXFULL_SHIFT (7U)
+#define I2S_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXFULL_SHIFT)) & I2S_FIFOSTAT_RXFULL_MASK)
+#define I2S_FIFOSTAT_TXLVL_MASK (0x1F00U)
+#define I2S_FIFOSTAT_TXLVL_SHIFT (8U)
+#define I2S_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_TXLVL_SHIFT)) & I2S_FIFOSTAT_TXLVL_MASK)
+#define I2S_FIFOSTAT_RXLVL_MASK (0x1F0000U)
+#define I2S_FIFOSTAT_RXLVL_SHIFT (16U)
+#define I2S_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOSTAT_RXLVL_SHIFT)) & I2S_FIFOSTAT_RXLVL_MASK)
+
+/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */
+#define I2S_FIFOTRIG_TXLVLENA_MASK (0x1U)
+#define I2S_FIFOTRIG_TXLVLENA_SHIFT (0U)
+#define I2S_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVLENA_SHIFT)) & I2S_FIFOTRIG_TXLVLENA_MASK)
+#define I2S_FIFOTRIG_RXLVLENA_MASK (0x2U)
+#define I2S_FIFOTRIG_RXLVLENA_SHIFT (1U)
+#define I2S_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVLENA_SHIFT)) & I2S_FIFOTRIG_RXLVLENA_MASK)
+#define I2S_FIFOTRIG_TXLVL_MASK (0xF00U)
+#define I2S_FIFOTRIG_TXLVL_SHIFT (8U)
+#define I2S_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_TXLVL_SHIFT)) & I2S_FIFOTRIG_TXLVL_MASK)
+#define I2S_FIFOTRIG_RXLVL_MASK (0xF0000U)
+#define I2S_FIFOTRIG_RXLVL_SHIFT (16U)
+#define I2S_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOTRIG_RXLVL_SHIFT)) & I2S_FIFOTRIG_RXLVL_MASK)
+
+/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */
+#define I2S_FIFOINTENSET_TXERR_MASK (0x1U)
+#define I2S_FIFOINTENSET_TXERR_SHIFT (0U)
+#define I2S_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXERR_SHIFT)) & I2S_FIFOINTENSET_TXERR_MASK)
+#define I2S_FIFOINTENSET_RXERR_MASK (0x2U)
+#define I2S_FIFOINTENSET_RXERR_SHIFT (1U)
+#define I2S_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXERR_SHIFT)) & I2S_FIFOINTENSET_RXERR_MASK)
+#define I2S_FIFOINTENSET_TXLVL_MASK (0x4U)
+#define I2S_FIFOINTENSET_TXLVL_SHIFT (2U)
+#define I2S_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_TXLVL_SHIFT)) & I2S_FIFOINTENSET_TXLVL_MASK)
+#define I2S_FIFOINTENSET_RXLVL_MASK (0x8U)
+#define I2S_FIFOINTENSET_RXLVL_SHIFT (3U)
+#define I2S_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENSET_RXLVL_SHIFT)) & I2S_FIFOINTENSET_RXLVL_MASK)
+
+/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */
+#define I2S_FIFOINTENCLR_TXERR_MASK (0x1U)
+#define I2S_FIFOINTENCLR_TXERR_SHIFT (0U)
+#define I2S_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXERR_SHIFT)) & I2S_FIFOINTENCLR_TXERR_MASK)
+#define I2S_FIFOINTENCLR_RXERR_MASK (0x2U)
+#define I2S_FIFOINTENCLR_RXERR_SHIFT (1U)
+#define I2S_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXERR_SHIFT)) & I2S_FIFOINTENCLR_RXERR_MASK)
+#define I2S_FIFOINTENCLR_TXLVL_MASK (0x4U)
+#define I2S_FIFOINTENCLR_TXLVL_SHIFT (2U)
+#define I2S_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_TXLVL_SHIFT)) & I2S_FIFOINTENCLR_TXLVL_MASK)
+#define I2S_FIFOINTENCLR_RXLVL_MASK (0x8U)
+#define I2S_FIFOINTENCLR_RXLVL_SHIFT (3U)
+#define I2S_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTENCLR_RXLVL_SHIFT)) & I2S_FIFOINTENCLR_RXLVL_MASK)
+
+/*! @name FIFOINTSTAT - FIFO interrupt status register. */
+#define I2S_FIFOINTSTAT_TXERR_MASK (0x1U)
+#define I2S_FIFOINTSTAT_TXERR_SHIFT (0U)
+#define I2S_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXERR_SHIFT)) & I2S_FIFOINTSTAT_TXERR_MASK)
+#define I2S_FIFOINTSTAT_RXERR_MASK (0x2U)
+#define I2S_FIFOINTSTAT_RXERR_SHIFT (1U)
+#define I2S_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXERR_SHIFT)) & I2S_FIFOINTSTAT_RXERR_MASK)
+#define I2S_FIFOINTSTAT_TXLVL_MASK (0x4U)
+#define I2S_FIFOINTSTAT_TXLVL_SHIFT (2U)
+#define I2S_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_TXLVL_SHIFT)) & I2S_FIFOINTSTAT_TXLVL_MASK)
+#define I2S_FIFOINTSTAT_RXLVL_MASK (0x8U)
+#define I2S_FIFOINTSTAT_RXLVL_SHIFT (3U)
+#define I2S_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_RXLVL_SHIFT)) & I2S_FIFOINTSTAT_RXLVL_MASK)
+#define I2S_FIFOINTSTAT_PERINT_MASK (0x10U)
+#define I2S_FIFOINTSTAT_PERINT_SHIFT (4U)
+#define I2S_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOINTSTAT_PERINT_SHIFT)) & I2S_FIFOINTSTAT_PERINT_MASK)
+
+/*! @name FIFOWR - FIFO write data. */
+#define I2S_FIFOWR_TXDATA_MASK (0xFFFFFFFFU)
+#define I2S_FIFOWR_TXDATA_SHIFT (0U)
+#define I2S_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR_TXDATA_SHIFT)) & I2S_FIFOWR_TXDATA_MASK)
+
+/*! @name FIFOWR48H - FIFO write data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */
+#define I2S_FIFOWR48H_TXDATA_MASK (0xFFFFFFU)
+#define I2S_FIFOWR48H_TXDATA_SHIFT (0U)
+#define I2S_FIFOWR48H_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFOWR48H_TXDATA_SHIFT)) & I2S_FIFOWR48H_TXDATA_MASK)
+
+/*! @name FIFORD - FIFO read data. */
+#define I2S_FIFORD_RXDATA_MASK (0xFFFFFFFFU)
+#define I2S_FIFORD_RXDATA_SHIFT (0U)
+#define I2S_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD_RXDATA_SHIFT)) & I2S_FIFORD_RXDATA_MASK)
+
+/*! @name FIFORD48H - FIFO read data for upper data bits. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */
+#define I2S_FIFORD48H_RXDATA_MASK (0xFFFFFFU)
+#define I2S_FIFORD48H_RXDATA_SHIFT (0U)
+#define I2S_FIFORD48H_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48H_RXDATA_SHIFT)) & I2S_FIFORD48H_RXDATA_MASK)
+
+/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */
+#define I2S_FIFORDNOPOP_RXDATA_MASK (0xFFFFFFFFU)
+#define I2S_FIFORDNOPOP_RXDATA_SHIFT (0U)
+#define I2S_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORDNOPOP_RXDATA_SHIFT)) & I2S_FIFORDNOPOP_RXDATA_MASK)
+
+/*! @name FIFORD48HNOPOP - FIFO data read for upper data bits with no FIFO pop. May only be used if the I2S is configured for 2x 24-bit data and not using DMA. */
+#define I2S_FIFORD48HNOPOP_RXDATA_MASK (0xFFFFFFU)
+#define I2S_FIFORD48HNOPOP_RXDATA_SHIFT (0U)
+#define I2S_FIFORD48HNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << I2S_FIFORD48HNOPOP_RXDATA_SHIFT)) & I2S_FIFORD48HNOPOP_RXDATA_MASK)
+
+/*! @name ID - I2S Module identification */
+#define I2S_ID_Aperture_MASK (0xFFU)
+#define I2S_ID_Aperture_SHIFT (0U)
+#define I2S_ID_Aperture(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Aperture_SHIFT)) & I2S_ID_Aperture_MASK)
+#define I2S_ID_Minor_Rev_MASK (0xF00U)
+#define I2S_ID_Minor_Rev_SHIFT (8U)
+#define I2S_ID_Minor_Rev(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Minor_Rev_SHIFT)) & I2S_ID_Minor_Rev_MASK)
+#define I2S_ID_Major_Rev_MASK (0xF000U)
+#define I2S_ID_Major_Rev_SHIFT (12U)
+#define I2S_ID_Major_Rev(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_Major_Rev_SHIFT)) & I2S_ID_Major_Rev_MASK)
+#define I2S_ID_ID_MASK (0xFFFF0000U)
+#define I2S_ID_ID_SHIFT (16U)
+#define I2S_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << I2S_ID_ID_SHIFT)) & I2S_ID_ID_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group I2S_Register_Masks */
+
+
+/* I2S - Peripheral instance base addresses */
+/** Peripheral I2S0 base address */
+#define I2S0_BASE (0x40097000u)
+/** Peripheral I2S0 base pointer */
+#define I2S0 ((I2S_Type *)I2S0_BASE)
+/** Peripheral I2S1 base address */
+#define I2S1_BASE (0x40098000u)
+/** Peripheral I2S1 base pointer */
+#define I2S1 ((I2S_Type *)I2S1_BASE)
+/** Array initializer of I2S peripheral base addresses */
+#define I2S_BASE_ADDRS { I2S0_BASE, I2S1_BASE }
+/** Array initializer of I2S peripheral base pointers */
+#define I2S_BASE_PTRS { I2S0, I2S1 }
+/** Interrupt vectors for the I2S peripheral type */
+#define I2S_IRQS { FLEXCOMM6_IRQn, FLEXCOMM7_IRQn }
+
+/*!
+ * @}
+ */ /* end of group I2S_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- INPUTMUX Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup INPUTMUX_Peripheral_Access_Layer INPUTMUX Peripheral Access Layer
+ * @{
+ */
+
+/** INPUTMUX - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t SCT0_INMUX[7]; /**< Trigger select register for DMA channel, array offset: 0x0, array step: 0x4 */
+ uint8_t RESERVED_0[164];
+ __IO uint32_t PINTSEL[8]; /**< Pin interrupt select register, array offset: 0xC0, array step: 0x4 */
+ __IO uint32_t DMA_ITRIG_INMUX[30]; /**< Trigger select register for DMA channel, array offset: 0xE0, array step: 0x4 */
+ uint8_t RESERVED_1[8];
+ __IO uint32_t DMA_OTRIG_INMUX[4]; /**< DMA output trigger selection to become DMA trigger, array offset: 0x160, array step: 0x4 */
+ uint8_t RESERVED_2[16];
+ __IO uint32_t FREQMEAS_REF; /**< Selection for frequency measurement reference clock, offset: 0x180 */
+ __IO uint32_t FREQMEAS_TARGET; /**< Selection for frequency measurement target clock, offset: 0x184 */
+} INPUTMUX_Type;
+
+/* ----------------------------------------------------------------------------
+ -- INPUTMUX Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup INPUTMUX_Register_Masks INPUTMUX Register Masks
+ * @{
+ */
+
+/*! @name SCT0_INMUX - Trigger select register for DMA channel */
+#define INPUTMUX_SCT0_INMUX_INP_N_MASK (0x1FU)
+#define INPUTMUX_SCT0_INMUX_INP_N_SHIFT (0U)
+#define INPUTMUX_SCT0_INMUX_INP_N(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_SCT0_INMUX_INP_N_SHIFT)) & INPUTMUX_SCT0_INMUX_INP_N_MASK)
+
+/* The count of INPUTMUX_SCT0_INMUX */
+#define INPUTMUX_SCT0_INMUX_COUNT (7U)
+
+/*! @name PINTSEL - Pin interrupt select register */
+#define INPUTMUX_PINTSEL_INTPIN_MASK (0xFFU)
+#define INPUTMUX_PINTSEL_INTPIN_SHIFT (0U)
+#define INPUTMUX_PINTSEL_INTPIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_PINTSEL_INTPIN_SHIFT)) & INPUTMUX_PINTSEL_INTPIN_MASK)
+
+/* The count of INPUTMUX_PINTSEL */
+#define INPUTMUX_PINTSEL_COUNT (8U)
+
+/*! @name DMA_ITRIG_INMUX - Trigger select register for DMA channel */
+#define INPUTMUX_DMA_ITRIG_INMUX_INP_MASK (0x1FU)
+#define INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT (0U)
+#define INPUTMUX_DMA_ITRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_ITRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_ITRIG_INMUX_INP_MASK)
+
+/* The count of INPUTMUX_DMA_ITRIG_INMUX */
+#define INPUTMUX_DMA_ITRIG_INMUX_COUNT (30U)
+
+/*! @name DMA_OTRIG_INMUX - DMA output trigger selection to become DMA trigger */
+#define INPUTMUX_DMA_OTRIG_INMUX_INP_MASK (0x1FU)
+#define INPUTMUX_DMA_OTRIG_INMUX_INP_SHIFT (0U)
+#define INPUTMUX_DMA_OTRIG_INMUX_INP(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_DMA_OTRIG_INMUX_INP_SHIFT)) & INPUTMUX_DMA_OTRIG_INMUX_INP_MASK)
+
+/* The count of INPUTMUX_DMA_OTRIG_INMUX */
+#define INPUTMUX_DMA_OTRIG_INMUX_COUNT (4U)
+
+/*! @name FREQMEAS_REF - Selection for frequency measurement reference clock */
+#define INPUTMUX_FREQMEAS_REF_CLKIN_MASK (0x1FU)
+#define INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT (0U)
+#define INPUTMUX_FREQMEAS_REF_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_REF_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_REF_CLKIN_MASK)
+
+/*! @name FREQMEAS_TARGET - Selection for frequency measurement target clock */
+#define INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK (0x1FU)
+#define INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT (0U)
+#define INPUTMUX_FREQMEAS_TARGET_CLKIN(x) (((uint32_t)(((uint32_t)(x)) << INPUTMUX_FREQMEAS_TARGET_CLKIN_SHIFT)) & INPUTMUX_FREQMEAS_TARGET_CLKIN_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group INPUTMUX_Register_Masks */
+
+
+/* INPUTMUX - Peripheral instance base addresses */
+/** Peripheral INPUTMUX base address */
+#define INPUTMUX_BASE (0x40005000u)
+/** Peripheral INPUTMUX base pointer */
+#define INPUTMUX ((INPUTMUX_Type *)INPUTMUX_BASE)
+/** Array initializer of INPUTMUX peripheral base addresses */
+#define INPUTMUX_BASE_ADDRS { INPUTMUX_BASE }
+/** Array initializer of INPUTMUX peripheral base pointers */
+#define INPUTMUX_BASE_PTRS { INPUTMUX }
+
+/*!
+ * @}
+ */ /* end of group INPUTMUX_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- IOCON Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup IOCON_Peripheral_Access_Layer IOCON Peripheral Access Layer
+ * @{
+ */
+
+/** IOCON - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t PIO[6][32]; /**< Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 5 pins PIO5_31, array offset: 0x0, array step: index*0x80, index2*0x4 */
+} IOCON_Type;
+
+/* ----------------------------------------------------------------------------
+ -- IOCON Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup IOCON_Register_Masks IOCON Register Masks
+ * @{
+ */
+
+/*! @name PIO - Digital I/O control for port 0 pins PIO0_0..Digital I/O control for port 5 pins PIO5_31 */
+#define IOCON_PIO_FUNC_MASK (0xFU)
+#define IOCON_PIO_FUNC_SHIFT (0U)
+#define IOCON_PIO_FUNC(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FUNC_SHIFT)) & IOCON_PIO_FUNC_MASK)
+#define IOCON_PIO_MODE_MASK (0x30U)
+#define IOCON_PIO_MODE_SHIFT (4U)
+#define IOCON_PIO_MODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_MODE_SHIFT)) & IOCON_PIO_MODE_MASK)
+#define IOCON_PIO_I2CSLEW_MASK (0x40U)
+#define IOCON_PIO_I2CSLEW_SHIFT (6U)
+#define IOCON_PIO_I2CSLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CSLEW_SHIFT)) & IOCON_PIO_I2CSLEW_MASK)
+#define IOCON_PIO_INVERT_MASK (0x80U)
+#define IOCON_PIO_INVERT_SHIFT (7U)
+#define IOCON_PIO_INVERT(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_INVERT_SHIFT)) & IOCON_PIO_INVERT_MASK)
+#define IOCON_PIO_DIGIMODE_MASK (0x100U)
+#define IOCON_PIO_DIGIMODE_SHIFT (8U)
+#define IOCON_PIO_DIGIMODE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_DIGIMODE_SHIFT)) & IOCON_PIO_DIGIMODE_MASK)
+#define IOCON_PIO_FILTEROFF_MASK (0x200U)
+#define IOCON_PIO_FILTEROFF_SHIFT (9U)
+#define IOCON_PIO_FILTEROFF(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_FILTEROFF_SHIFT)) & IOCON_PIO_FILTEROFF_MASK)
+#define IOCON_PIO_I2CDRIVE_MASK (0x400U)
+#define IOCON_PIO_I2CDRIVE_SHIFT (10U)
+#define IOCON_PIO_I2CDRIVE(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CDRIVE_SHIFT)) & IOCON_PIO_I2CDRIVE_MASK)
+#define IOCON_PIO_SLEW_MASK (0x400U)
+#define IOCON_PIO_SLEW_SHIFT (10U)
+#define IOCON_PIO_SLEW(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_SLEW_SHIFT)) & IOCON_PIO_SLEW_MASK)
+#define IOCON_PIO_OD_MASK (0x800U)
+#define IOCON_PIO_OD_SHIFT (11U)
+#define IOCON_PIO_OD(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_OD_SHIFT)) & IOCON_PIO_OD_MASK)
+#define IOCON_PIO_I2CFILTER_MASK (0x800U)
+#define IOCON_PIO_I2CFILTER_SHIFT (11U)
+#define IOCON_PIO_I2CFILTER(x) (((uint32_t)(((uint32_t)(x)) << IOCON_PIO_I2CFILTER_SHIFT)) & IOCON_PIO_I2CFILTER_MASK)
+
+/* The count of IOCON_PIO */
+#define IOCON_PIO_COUNT (6U)
+
+/* The count of IOCON_PIO */
+#define IOCON_PIO_COUNT2 (32U)
+
+
+/*!
+ * @}
+ */ /* end of group IOCON_Register_Masks */
+
+
+/* IOCON - Peripheral instance base addresses */
+/** Peripheral IOCON base address */
+#define IOCON_BASE (0x40001000u)
+/** Peripheral IOCON base pointer */
+#define IOCON ((IOCON_Type *)IOCON_BASE)
+/** Array initializer of IOCON peripheral base addresses */
+#define IOCON_BASE_ADDRS { IOCON_BASE }
+/** Array initializer of IOCON peripheral base pointers */
+#define IOCON_BASE_PTRS { IOCON }
+
+/*!
+ * @}
+ */ /* end of group IOCON_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- LCD Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LCD_Peripheral_Access_Layer LCD Peripheral Access Layer
+ * @{
+ */
+
+/** LCD - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t TIMH; /**< Horizontal Timing Control register, offset: 0x0 */
+ __IO uint32_t TIMV; /**< Vertical Timing Control register, offset: 0x4 */
+ __IO uint32_t POL; /**< Clock and Signal Polarity Control register, offset: 0x8 */
+ __IO uint32_t LE; /**< Line End Control register, offset: 0xC */
+ __IO uint32_t UPBASE; /**< Upper Panel Frame Base Address register, offset: 0x10 */
+ __IO uint32_t LPBASE; /**< Lower Panel Frame Base Address register, offset: 0x14 */
+ __IO uint32_t CTRL; /**< LCD Control register, offset: 0x18 */
+ __IO uint32_t INTMSK; /**< Interrupt Mask register, offset: 0x1C */
+ __I uint32_t INTRAW; /**< Raw Interrupt Status register, offset: 0x20 */
+ __I uint32_t INTSTAT; /**< Masked Interrupt Status register, offset: 0x24 */
+ __IO uint32_t INTCLR; /**< Interrupt Clear register, offset: 0x28 */
+ __I uint32_t UPCURR; /**< Upper Panel Current Address Value register, offset: 0x2C */
+ __I uint32_t LPCURR; /**< Lower Panel Current Address Value register, offset: 0x30 */
+ uint8_t RESERVED_0[460];
+ __IO uint32_t PAL[128]; /**< 256x16-bit Color Palette registers, array offset: 0x200, array step: 0x4 */
+ uint8_t RESERVED_1[1024];
+ __IO uint32_t CRSR_IMG[256]; /**< Cursor Image registers, array offset: 0x800, array step: 0x4 */
+ __IO uint32_t CRSR_CTRL; /**< Cursor Control register, offset: 0xC00 */
+ __IO uint32_t CRSR_CFG; /**< Cursor Configuration register, offset: 0xC04 */
+ __IO uint32_t CRSR_PAL0; /**< Cursor Palette register 0, offset: 0xC08 */
+ __IO uint32_t CRSR_PAL1; /**< Cursor Palette register 1, offset: 0xC0C */
+ __IO uint32_t CRSR_XY; /**< Cursor XY Position register, offset: 0xC10 */
+ __IO uint32_t CRSR_CLIP; /**< Cursor Clip Position register, offset: 0xC14 */
+ uint8_t RESERVED_2[8];
+ __IO uint32_t CRSR_INTMSK; /**< Cursor Interrupt Mask register, offset: 0xC20 */
+ __O uint32_t CRSR_INTCLR; /**< Cursor Interrupt Clear register, offset: 0xC24 */
+ __I uint32_t CRSR_INTRAW; /**< Cursor Raw Interrupt Status register, offset: 0xC28 */
+ __I uint32_t CRSR_INTSTAT; /**< Cursor Masked Interrupt Status register, offset: 0xC2C */
+} LCD_Type;
+
+/* ----------------------------------------------------------------------------
+ -- LCD Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup LCD_Register_Masks LCD Register Masks
+ * @{
+ */
+
+/*! @name TIMH - Horizontal Timing Control register */
+#define LCD_TIMH_PPL_MASK (0xFCU)
+#define LCD_TIMH_PPL_SHIFT (2U)
+#define LCD_TIMH_PPL(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMH_PPL_SHIFT)) & LCD_TIMH_PPL_MASK)
+#define LCD_TIMH_HSW_MASK (0xFF00U)
+#define LCD_TIMH_HSW_SHIFT (8U)
+#define LCD_TIMH_HSW(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMH_HSW_SHIFT)) & LCD_TIMH_HSW_MASK)
+#define LCD_TIMH_HFP_MASK (0xFF0000U)
+#define LCD_TIMH_HFP_SHIFT (16U)
+#define LCD_TIMH_HFP(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMH_HFP_SHIFT)) & LCD_TIMH_HFP_MASK)
+#define LCD_TIMH_HBP_MASK (0xFF000000U)
+#define LCD_TIMH_HBP_SHIFT (24U)
+#define LCD_TIMH_HBP(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMH_HBP_SHIFT)) & LCD_TIMH_HBP_MASK)
+
+/*! @name TIMV - Vertical Timing Control register */
+#define LCD_TIMV_LPP_MASK (0x3FFU)
+#define LCD_TIMV_LPP_SHIFT (0U)
+#define LCD_TIMV_LPP(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMV_LPP_SHIFT)) & LCD_TIMV_LPP_MASK)
+#define LCD_TIMV_VSW_MASK (0xFC00U)
+#define LCD_TIMV_VSW_SHIFT (10U)
+#define LCD_TIMV_VSW(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMV_VSW_SHIFT)) & LCD_TIMV_VSW_MASK)
+#define LCD_TIMV_VFP_MASK (0xFF0000U)
+#define LCD_TIMV_VFP_SHIFT (16U)
+#define LCD_TIMV_VFP(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMV_VFP_SHIFT)) & LCD_TIMV_VFP_MASK)
+#define LCD_TIMV_VBP_MASK (0xFF000000U)
+#define LCD_TIMV_VBP_SHIFT (24U)
+#define LCD_TIMV_VBP(x) (((uint32_t)(((uint32_t)(x)) << LCD_TIMV_VBP_SHIFT)) & LCD_TIMV_VBP_MASK)
+
+/*! @name POL - Clock and Signal Polarity Control register */
+#define LCD_POL_PCD_LO_MASK (0x1FU)
+#define LCD_POL_PCD_LO_SHIFT (0U)
+#define LCD_POL_PCD_LO(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_PCD_LO_SHIFT)) & LCD_POL_PCD_LO_MASK)
+#define LCD_POL_ACB_MASK (0x7C0U)
+#define LCD_POL_ACB_SHIFT (6U)
+#define LCD_POL_ACB(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_ACB_SHIFT)) & LCD_POL_ACB_MASK)
+#define LCD_POL_IVS_MASK (0x800U)
+#define LCD_POL_IVS_SHIFT (11U)
+#define LCD_POL_IVS(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_IVS_SHIFT)) & LCD_POL_IVS_MASK)
+#define LCD_POL_IHS_MASK (0x1000U)
+#define LCD_POL_IHS_SHIFT (12U)
+#define LCD_POL_IHS(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_IHS_SHIFT)) & LCD_POL_IHS_MASK)
+#define LCD_POL_IPC_MASK (0x2000U)
+#define LCD_POL_IPC_SHIFT (13U)
+#define LCD_POL_IPC(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_IPC_SHIFT)) & LCD_POL_IPC_MASK)
+#define LCD_POL_IOE_MASK (0x4000U)
+#define LCD_POL_IOE_SHIFT (14U)
+#define LCD_POL_IOE(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_IOE_SHIFT)) & LCD_POL_IOE_MASK)
+#define LCD_POL_CPL_MASK (0x3FF0000U)
+#define LCD_POL_CPL_SHIFT (16U)
+#define LCD_POL_CPL(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_CPL_SHIFT)) & LCD_POL_CPL_MASK)
+#define LCD_POL_BCD_MASK (0x4000000U)
+#define LCD_POL_BCD_SHIFT (26U)
+#define LCD_POL_BCD(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_BCD_SHIFT)) & LCD_POL_BCD_MASK)
+#define LCD_POL_PCD_HI_MASK (0xF8000000U)
+#define LCD_POL_PCD_HI_SHIFT (27U)
+#define LCD_POL_PCD_HI(x) (((uint32_t)(((uint32_t)(x)) << LCD_POL_PCD_HI_SHIFT)) & LCD_POL_PCD_HI_MASK)
+
+/*! @name LE - Line End Control register */
+#define LCD_LE_LED_MASK (0x7FU)
+#define LCD_LE_LED_SHIFT (0U)
+#define LCD_LE_LED(x) (((uint32_t)(((uint32_t)(x)) << LCD_LE_LED_SHIFT)) & LCD_LE_LED_MASK)
+#define LCD_LE_LEE_MASK (0x10000U)
+#define LCD_LE_LEE_SHIFT (16U)
+#define LCD_LE_LEE(x) (((uint32_t)(((uint32_t)(x)) << LCD_LE_LEE_SHIFT)) & LCD_LE_LEE_MASK)
+
+/*! @name UPBASE - Upper Panel Frame Base Address register */
+#define LCD_UPBASE_LCDUPBASE_MASK (0xFFFFFFF8U)
+#define LCD_UPBASE_LCDUPBASE_SHIFT (3U)
+#define LCD_UPBASE_LCDUPBASE(x) (((uint32_t)(((uint32_t)(x)) << LCD_UPBASE_LCDUPBASE_SHIFT)) & LCD_UPBASE_LCDUPBASE_MASK)
+
+/*! @name LPBASE - Lower Panel Frame Base Address register */
+#define LCD_LPBASE_LCDLPBASE_MASK (0xFFFFFFF8U)
+#define LCD_LPBASE_LCDLPBASE_SHIFT (3U)
+#define LCD_LPBASE_LCDLPBASE(x) (((uint32_t)(((uint32_t)(x)) << LCD_LPBASE_LCDLPBASE_SHIFT)) & LCD_LPBASE_LCDLPBASE_MASK)
+
+/*! @name CTRL - LCD Control register */
+#define LCD_CTRL_LCDEN_MASK (0x1U)
+#define LCD_CTRL_LCDEN_SHIFT (0U)
+#define LCD_CTRL_LCDEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDEN_SHIFT)) & LCD_CTRL_LCDEN_MASK)
+#define LCD_CTRL_LCDBPP_MASK (0xEU)
+#define LCD_CTRL_LCDBPP_SHIFT (1U)
+#define LCD_CTRL_LCDBPP(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDBPP_SHIFT)) & LCD_CTRL_LCDBPP_MASK)
+#define LCD_CTRL_LCDBW_MASK (0x10U)
+#define LCD_CTRL_LCDBW_SHIFT (4U)
+#define LCD_CTRL_LCDBW(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDBW_SHIFT)) & LCD_CTRL_LCDBW_MASK)
+#define LCD_CTRL_LCDTFT_MASK (0x20U)
+#define LCD_CTRL_LCDTFT_SHIFT (5U)
+#define LCD_CTRL_LCDTFT(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDTFT_SHIFT)) & LCD_CTRL_LCDTFT_MASK)
+#define LCD_CTRL_LCDMONO8_MASK (0x40U)
+#define LCD_CTRL_LCDMONO8_SHIFT (6U)
+#define LCD_CTRL_LCDMONO8(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDMONO8_SHIFT)) & LCD_CTRL_LCDMONO8_MASK)
+#define LCD_CTRL_LCDDUAL_MASK (0x80U)
+#define LCD_CTRL_LCDDUAL_SHIFT (7U)
+#define LCD_CTRL_LCDDUAL(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDDUAL_SHIFT)) & LCD_CTRL_LCDDUAL_MASK)
+#define LCD_CTRL_BGR_MASK (0x100U)
+#define LCD_CTRL_BGR_SHIFT (8U)
+#define LCD_CTRL_BGR(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_BGR_SHIFT)) & LCD_CTRL_BGR_MASK)
+#define LCD_CTRL_BEBO_MASK (0x200U)
+#define LCD_CTRL_BEBO_SHIFT (9U)
+#define LCD_CTRL_BEBO(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_BEBO_SHIFT)) & LCD_CTRL_BEBO_MASK)
+#define LCD_CTRL_BEPO_MASK (0x400U)
+#define LCD_CTRL_BEPO_SHIFT (10U)
+#define LCD_CTRL_BEPO(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_BEPO_SHIFT)) & LCD_CTRL_BEPO_MASK)
+#define LCD_CTRL_LCDPWR_MASK (0x800U)
+#define LCD_CTRL_LCDPWR_SHIFT (11U)
+#define LCD_CTRL_LCDPWR(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDPWR_SHIFT)) & LCD_CTRL_LCDPWR_MASK)
+#define LCD_CTRL_LCDVCOMP_MASK (0x3000U)
+#define LCD_CTRL_LCDVCOMP_SHIFT (12U)
+#define LCD_CTRL_LCDVCOMP(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_LCDVCOMP_SHIFT)) & LCD_CTRL_LCDVCOMP_MASK)
+#define LCD_CTRL_WATERMARK_MASK (0x10000U)
+#define LCD_CTRL_WATERMARK_SHIFT (16U)
+#define LCD_CTRL_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << LCD_CTRL_WATERMARK_SHIFT)) & LCD_CTRL_WATERMARK_MASK)
+
+/*! @name INTMSK - Interrupt Mask register */
+#define LCD_INTMSK_FUFIM_MASK (0x2U)
+#define LCD_INTMSK_FUFIM_SHIFT (1U)
+#define LCD_INTMSK_FUFIM(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTMSK_FUFIM_SHIFT)) & LCD_INTMSK_FUFIM_MASK)
+#define LCD_INTMSK_LNBUIM_MASK (0x4U)
+#define LCD_INTMSK_LNBUIM_SHIFT (2U)
+#define LCD_INTMSK_LNBUIM(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTMSK_LNBUIM_SHIFT)) & LCD_INTMSK_LNBUIM_MASK)
+#define LCD_INTMSK_VCOMPIM_MASK (0x8U)
+#define LCD_INTMSK_VCOMPIM_SHIFT (3U)
+#define LCD_INTMSK_VCOMPIM(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTMSK_VCOMPIM_SHIFT)) & LCD_INTMSK_VCOMPIM_MASK)
+#define LCD_INTMSK_BERIM_MASK (0x10U)
+#define LCD_INTMSK_BERIM_SHIFT (4U)
+#define LCD_INTMSK_BERIM(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTMSK_BERIM_SHIFT)) & LCD_INTMSK_BERIM_MASK)
+
+/*! @name INTRAW - Raw Interrupt Status register */
+#define LCD_INTRAW_FUFRIS_MASK (0x2U)
+#define LCD_INTRAW_FUFRIS_SHIFT (1U)
+#define LCD_INTRAW_FUFRIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTRAW_FUFRIS_SHIFT)) & LCD_INTRAW_FUFRIS_MASK)
+#define LCD_INTRAW_LNBURIS_MASK (0x4U)
+#define LCD_INTRAW_LNBURIS_SHIFT (2U)
+#define LCD_INTRAW_LNBURIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTRAW_LNBURIS_SHIFT)) & LCD_INTRAW_LNBURIS_MASK)
+#define LCD_INTRAW_VCOMPRIS_MASK (0x8U)
+#define LCD_INTRAW_VCOMPRIS_SHIFT (3U)
+#define LCD_INTRAW_VCOMPRIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTRAW_VCOMPRIS_SHIFT)) & LCD_INTRAW_VCOMPRIS_MASK)
+#define LCD_INTRAW_BERRAW_MASK (0x10U)
+#define LCD_INTRAW_BERRAW_SHIFT (4U)
+#define LCD_INTRAW_BERRAW(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTRAW_BERRAW_SHIFT)) & LCD_INTRAW_BERRAW_MASK)
+
+/*! @name INTSTAT - Masked Interrupt Status register */
+#define LCD_INTSTAT_FUFMIS_MASK (0x2U)
+#define LCD_INTSTAT_FUFMIS_SHIFT (1U)
+#define LCD_INTSTAT_FUFMIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTSTAT_FUFMIS_SHIFT)) & LCD_INTSTAT_FUFMIS_MASK)
+#define LCD_INTSTAT_LNBUMIS_MASK (0x4U)
+#define LCD_INTSTAT_LNBUMIS_SHIFT (2U)
+#define LCD_INTSTAT_LNBUMIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTSTAT_LNBUMIS_SHIFT)) & LCD_INTSTAT_LNBUMIS_MASK)
+#define LCD_INTSTAT_VCOMPMIS_MASK (0x8U)
+#define LCD_INTSTAT_VCOMPMIS_SHIFT (3U)
+#define LCD_INTSTAT_VCOMPMIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTSTAT_VCOMPMIS_SHIFT)) & LCD_INTSTAT_VCOMPMIS_MASK)
+#define LCD_INTSTAT_BERMIS_MASK (0x10U)
+#define LCD_INTSTAT_BERMIS_SHIFT (4U)
+#define LCD_INTSTAT_BERMIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTSTAT_BERMIS_SHIFT)) & LCD_INTSTAT_BERMIS_MASK)
+
+/*! @name INTCLR - Interrupt Clear register */
+#define LCD_INTCLR_FUFIC_MASK (0x2U)
+#define LCD_INTCLR_FUFIC_SHIFT (1U)
+#define LCD_INTCLR_FUFIC(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTCLR_FUFIC_SHIFT)) & LCD_INTCLR_FUFIC_MASK)
+#define LCD_INTCLR_LNBUIC_MASK (0x4U)
+#define LCD_INTCLR_LNBUIC_SHIFT (2U)
+#define LCD_INTCLR_LNBUIC(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTCLR_LNBUIC_SHIFT)) & LCD_INTCLR_LNBUIC_MASK)
+#define LCD_INTCLR_VCOMPIC_MASK (0x8U)
+#define LCD_INTCLR_VCOMPIC_SHIFT (3U)
+#define LCD_INTCLR_VCOMPIC(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTCLR_VCOMPIC_SHIFT)) & LCD_INTCLR_VCOMPIC_MASK)
+#define LCD_INTCLR_BERIC_MASK (0x10U)
+#define LCD_INTCLR_BERIC_SHIFT (4U)
+#define LCD_INTCLR_BERIC(x) (((uint32_t)(((uint32_t)(x)) << LCD_INTCLR_BERIC_SHIFT)) & LCD_INTCLR_BERIC_MASK)
+
+/*! @name UPCURR - Upper Panel Current Address Value register */
+#define LCD_UPCURR_LCDUPCURR_MASK (0xFFFFFFFFU)
+#define LCD_UPCURR_LCDUPCURR_SHIFT (0U)
+#define LCD_UPCURR_LCDUPCURR(x) (((uint32_t)(((uint32_t)(x)) << LCD_UPCURR_LCDUPCURR_SHIFT)) & LCD_UPCURR_LCDUPCURR_MASK)
+
+/*! @name LPCURR - Lower Panel Current Address Value register */
+#define LCD_LPCURR_LCDLPCURR_MASK (0xFFFFFFFFU)
+#define LCD_LPCURR_LCDLPCURR_SHIFT (0U)
+#define LCD_LPCURR_LCDLPCURR(x) (((uint32_t)(((uint32_t)(x)) << LCD_LPCURR_LCDLPCURR_SHIFT)) & LCD_LPCURR_LCDLPCURR_MASK)
+
+/*! @name PAL - 256x16-bit Color Palette registers */
+#define LCD_PAL_R04_0_MASK (0x1FU)
+#define LCD_PAL_R04_0_SHIFT (0U)
+#define LCD_PAL_R04_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_R04_0_SHIFT)) & LCD_PAL_R04_0_MASK)
+#define LCD_PAL_G04_0_MASK (0x3E0U)
+#define LCD_PAL_G04_0_SHIFT (5U)
+#define LCD_PAL_G04_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_G04_0_SHIFT)) & LCD_PAL_G04_0_MASK)
+#define LCD_PAL_B04_0_MASK (0x7C00U)
+#define LCD_PAL_B04_0_SHIFT (10U)
+#define LCD_PAL_B04_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_B04_0_SHIFT)) & LCD_PAL_B04_0_MASK)
+#define LCD_PAL_I0_MASK (0x8000U)
+#define LCD_PAL_I0_SHIFT (15U)
+#define LCD_PAL_I0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_I0_SHIFT)) & LCD_PAL_I0_MASK)
+#define LCD_PAL_R14_0_MASK (0x1F0000U)
+#define LCD_PAL_R14_0_SHIFT (16U)
+#define LCD_PAL_R14_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_R14_0_SHIFT)) & LCD_PAL_R14_0_MASK)
+#define LCD_PAL_G14_0_MASK (0x3E00000U)
+#define LCD_PAL_G14_0_SHIFT (21U)
+#define LCD_PAL_G14_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_G14_0_SHIFT)) & LCD_PAL_G14_0_MASK)
+#define LCD_PAL_B14_0_MASK (0x7C000000U)
+#define LCD_PAL_B14_0_SHIFT (26U)
+#define LCD_PAL_B14_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_B14_0_SHIFT)) & LCD_PAL_B14_0_MASK)
+#define LCD_PAL_I1_MASK (0x80000000U)
+#define LCD_PAL_I1_SHIFT (31U)
+#define LCD_PAL_I1(x) (((uint32_t)(((uint32_t)(x)) << LCD_PAL_I1_SHIFT)) & LCD_PAL_I1_MASK)
+
+/* The count of LCD_PAL */
+#define LCD_PAL_COUNT (128U)
+
+/*! @name CRSR_IMG - Cursor Image registers */
+#define LCD_CRSR_IMG_CRSR_IMG_MASK (0xFFFFFFFFU)
+#define LCD_CRSR_IMG_CRSR_IMG_SHIFT (0U)
+#define LCD_CRSR_IMG_CRSR_IMG(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_IMG_CRSR_IMG_SHIFT)) & LCD_CRSR_IMG_CRSR_IMG_MASK)
+
+/* The count of LCD_CRSR_IMG */
+#define LCD_CRSR_IMG_COUNT (256U)
+
+/*! @name CRSR_CTRL - Cursor Control register */
+#define LCD_CRSR_CTRL_CRSRON_MASK (0x1U)
+#define LCD_CRSR_CTRL_CRSRON_SHIFT (0U)
+#define LCD_CRSR_CTRL_CRSRON(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CTRL_CRSRON_SHIFT)) & LCD_CRSR_CTRL_CRSRON_MASK)
+#define LCD_CRSR_CTRL_CRSRNUM1_0_MASK (0x30U)
+#define LCD_CRSR_CTRL_CRSRNUM1_0_SHIFT (4U)
+#define LCD_CRSR_CTRL_CRSRNUM1_0(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CTRL_CRSRNUM1_0_SHIFT)) & LCD_CRSR_CTRL_CRSRNUM1_0_MASK)
+
+/*! @name CRSR_CFG - Cursor Configuration register */
+#define LCD_CRSR_CFG_CRSRSIZE_MASK (0x1U)
+#define LCD_CRSR_CFG_CRSRSIZE_SHIFT (0U)
+#define LCD_CRSR_CFG_CRSRSIZE(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CFG_CRSRSIZE_SHIFT)) & LCD_CRSR_CFG_CRSRSIZE_MASK)
+#define LCD_CRSR_CFG_FRAMESYNC_MASK (0x2U)
+#define LCD_CRSR_CFG_FRAMESYNC_SHIFT (1U)
+#define LCD_CRSR_CFG_FRAMESYNC(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CFG_FRAMESYNC_SHIFT)) & LCD_CRSR_CFG_FRAMESYNC_MASK)
+
+/*! @name CRSR_PAL0 - Cursor Palette register 0 */
+#define LCD_CRSR_PAL0_RED_MASK (0xFFU)
+#define LCD_CRSR_PAL0_RED_SHIFT (0U)
+#define LCD_CRSR_PAL0_RED(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL0_RED_SHIFT)) & LCD_CRSR_PAL0_RED_MASK)
+#define LCD_CRSR_PAL0_GREEN_MASK (0xFF00U)
+#define LCD_CRSR_PAL0_GREEN_SHIFT (8U)
+#define LCD_CRSR_PAL0_GREEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL0_GREEN_SHIFT)) & LCD_CRSR_PAL0_GREEN_MASK)
+#define LCD_CRSR_PAL0_BLUE_MASK (0xFF0000U)
+#define LCD_CRSR_PAL0_BLUE_SHIFT (16U)
+#define LCD_CRSR_PAL0_BLUE(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL0_BLUE_SHIFT)) & LCD_CRSR_PAL0_BLUE_MASK)
+
+/*! @name CRSR_PAL1 - Cursor Palette register 1 */
+#define LCD_CRSR_PAL1_RED_MASK (0xFFU)
+#define LCD_CRSR_PAL1_RED_SHIFT (0U)
+#define LCD_CRSR_PAL1_RED(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL1_RED_SHIFT)) & LCD_CRSR_PAL1_RED_MASK)
+#define LCD_CRSR_PAL1_GREEN_MASK (0xFF00U)
+#define LCD_CRSR_PAL1_GREEN_SHIFT (8U)
+#define LCD_CRSR_PAL1_GREEN(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL1_GREEN_SHIFT)) & LCD_CRSR_PAL1_GREEN_MASK)
+#define LCD_CRSR_PAL1_BLUE_MASK (0xFF0000U)
+#define LCD_CRSR_PAL1_BLUE_SHIFT (16U)
+#define LCD_CRSR_PAL1_BLUE(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_PAL1_BLUE_SHIFT)) & LCD_CRSR_PAL1_BLUE_MASK)
+
+/*! @name CRSR_XY - Cursor XY Position register */
+#define LCD_CRSR_XY_CRSRX_MASK (0x3FFU)
+#define LCD_CRSR_XY_CRSRX_SHIFT (0U)
+#define LCD_CRSR_XY_CRSRX(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_XY_CRSRX_SHIFT)) & LCD_CRSR_XY_CRSRX_MASK)
+#define LCD_CRSR_XY_CRSRY_MASK (0x3FF0000U)
+#define LCD_CRSR_XY_CRSRY_SHIFT (16U)
+#define LCD_CRSR_XY_CRSRY(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_XY_CRSRY_SHIFT)) & LCD_CRSR_XY_CRSRY_MASK)
+
+/*! @name CRSR_CLIP - Cursor Clip Position register */
+#define LCD_CRSR_CLIP_CRSRCLIPX_MASK (0x3FU)
+#define LCD_CRSR_CLIP_CRSRCLIPX_SHIFT (0U)
+#define LCD_CRSR_CLIP_CRSRCLIPX(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CLIP_CRSRCLIPX_SHIFT)) & LCD_CRSR_CLIP_CRSRCLIPX_MASK)
+#define LCD_CRSR_CLIP_CRSRCLIPY_MASK (0x3F00U)
+#define LCD_CRSR_CLIP_CRSRCLIPY_SHIFT (8U)
+#define LCD_CRSR_CLIP_CRSRCLIPY(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_CLIP_CRSRCLIPY_SHIFT)) & LCD_CRSR_CLIP_CRSRCLIPY_MASK)
+
+/*! @name CRSR_INTMSK - Cursor Interrupt Mask register */
+#define LCD_CRSR_INTMSK_CRSRIM_MASK (0x1U)
+#define LCD_CRSR_INTMSK_CRSRIM_SHIFT (0U)
+#define LCD_CRSR_INTMSK_CRSRIM(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_INTMSK_CRSRIM_SHIFT)) & LCD_CRSR_INTMSK_CRSRIM_MASK)
+
+/*! @name CRSR_INTCLR - Cursor Interrupt Clear register */
+#define LCD_CRSR_INTCLR_CRSRIC_MASK (0x1U)
+#define LCD_CRSR_INTCLR_CRSRIC_SHIFT (0U)
+#define LCD_CRSR_INTCLR_CRSRIC(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_INTCLR_CRSRIC_SHIFT)) & LCD_CRSR_INTCLR_CRSRIC_MASK)
+
+/*! @name CRSR_INTRAW - Cursor Raw Interrupt Status register */
+#define LCD_CRSR_INTRAW_CRSRRIS_MASK (0x1U)
+#define LCD_CRSR_INTRAW_CRSRRIS_SHIFT (0U)
+#define LCD_CRSR_INTRAW_CRSRRIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_INTRAW_CRSRRIS_SHIFT)) & LCD_CRSR_INTRAW_CRSRRIS_MASK)
+
+/*! @name CRSR_INTSTAT - Cursor Masked Interrupt Status register */
+#define LCD_CRSR_INTSTAT_CRSRMIS_MASK (0x1U)
+#define LCD_CRSR_INTSTAT_CRSRMIS_SHIFT (0U)
+#define LCD_CRSR_INTSTAT_CRSRMIS(x) (((uint32_t)(((uint32_t)(x)) << LCD_CRSR_INTSTAT_CRSRMIS_SHIFT)) & LCD_CRSR_INTSTAT_CRSRMIS_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group LCD_Register_Masks */
+
+
+/* LCD - Peripheral instance base addresses */
+/** Peripheral LCD base address */
+#define LCD_BASE (0x40083000u)
+/** Peripheral LCD base pointer */
+#define LCD ((LCD_Type *)LCD_BASE)
+/** Array initializer of LCD peripheral base addresses */
+#define LCD_BASE_ADDRS { LCD_BASE }
+/** Array initializer of LCD peripheral base pointers */
+#define LCD_BASE_PTRS { LCD }
+/** Interrupt vectors for the LCD peripheral type */
+#define LCD_IRQS { LCD_IRQn }
+
+/*!
+ * @}
+ */ /* end of group LCD_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- MRT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MRT_Peripheral_Access_Layer MRT Peripheral Access Layer
+ * @{
+ */
+
+/** MRT - Register Layout Typedef */
+typedef struct {
+ struct { /* offset: 0x0, array step: 0x10 */
+ __IO uint32_t INTVAL; /**< MRT Time interval value register. This value is loaded into the TIMER register., array offset: 0x0, array step: 0x10 */
+ __I uint32_t TIMER; /**< MRT Timer register. This register reads the value of the down-counter., array offset: 0x4, array step: 0x10 */
+ __IO uint32_t CTRL; /**< MRT Control register. This register controls the MRT modes., array offset: 0x8, array step: 0x10 */
+ __IO uint32_t STAT; /**< MRT Status register., array offset: 0xC, array step: 0x10 */
+ } CHANNEL[4];
+ uint8_t RESERVED_0[176];
+ __IO uint32_t MODCFG; /**< Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature., offset: 0xF0 */
+ __I uint32_t IDLE_CH; /**< Idle channel register. This register returns the number of the first idle channel., offset: 0xF4 */
+ __IO uint32_t IRQ_FLAG; /**< Global interrupt flag register, offset: 0xF8 */
+} MRT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- MRT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup MRT_Register_Masks MRT Register Masks
+ * @{
+ */
+
+/*! @name CHANNEL_INTVAL - MRT Time interval value register. This value is loaded into the TIMER register. */
+#define MRT_CHANNEL_INTVAL_IVALUE_MASK (0xFFFFFFU)
+#define MRT_CHANNEL_INTVAL_IVALUE_SHIFT (0U)
+#define MRT_CHANNEL_INTVAL_IVALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_IVALUE_SHIFT)) & MRT_CHANNEL_INTVAL_IVALUE_MASK)
+#define MRT_CHANNEL_INTVAL_LOAD_MASK (0x80000000U)
+#define MRT_CHANNEL_INTVAL_LOAD_SHIFT (31U)
+#define MRT_CHANNEL_INTVAL_LOAD(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_INTVAL_LOAD_SHIFT)) & MRT_CHANNEL_INTVAL_LOAD_MASK)
+
+/* The count of MRT_CHANNEL_INTVAL */
+#define MRT_CHANNEL_INTVAL_COUNT (4U)
+
+/*! @name CHANNEL_TIMER - MRT Timer register. This register reads the value of the down-counter. */
+#define MRT_CHANNEL_TIMER_VALUE_MASK (0xFFFFFFU)
+#define MRT_CHANNEL_TIMER_VALUE_SHIFT (0U)
+#define MRT_CHANNEL_TIMER_VALUE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_TIMER_VALUE_SHIFT)) & MRT_CHANNEL_TIMER_VALUE_MASK)
+
+/* The count of MRT_CHANNEL_TIMER */
+#define MRT_CHANNEL_TIMER_COUNT (4U)
+
+/*! @name CHANNEL_CTRL - MRT Control register. This register controls the MRT modes. */
+#define MRT_CHANNEL_CTRL_INTEN_MASK (0x1U)
+#define MRT_CHANNEL_CTRL_INTEN_SHIFT (0U)
+#define MRT_CHANNEL_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_INTEN_SHIFT)) & MRT_CHANNEL_CTRL_INTEN_MASK)
+#define MRT_CHANNEL_CTRL_MODE_MASK (0x6U)
+#define MRT_CHANNEL_CTRL_MODE_SHIFT (1U)
+#define MRT_CHANNEL_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_CTRL_MODE_SHIFT)) & MRT_CHANNEL_CTRL_MODE_MASK)
+
+/* The count of MRT_CHANNEL_CTRL */
+#define MRT_CHANNEL_CTRL_COUNT (4U)
+
+/*! @name CHANNEL_STAT - MRT Status register. */
+#define MRT_CHANNEL_STAT_INTFLAG_MASK (0x1U)
+#define MRT_CHANNEL_STAT_INTFLAG_SHIFT (0U)
+#define MRT_CHANNEL_STAT_INTFLAG(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INTFLAG_SHIFT)) & MRT_CHANNEL_STAT_INTFLAG_MASK)
+#define MRT_CHANNEL_STAT_RUN_MASK (0x2U)
+#define MRT_CHANNEL_STAT_RUN_SHIFT (1U)
+#define MRT_CHANNEL_STAT_RUN(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_RUN_SHIFT)) & MRT_CHANNEL_STAT_RUN_MASK)
+#define MRT_CHANNEL_STAT_INUSE_MASK (0x4U)
+#define MRT_CHANNEL_STAT_INUSE_SHIFT (2U)
+#define MRT_CHANNEL_STAT_INUSE(x) (((uint32_t)(((uint32_t)(x)) << MRT_CHANNEL_STAT_INUSE_SHIFT)) & MRT_CHANNEL_STAT_INUSE_MASK)
+
+/* The count of MRT_CHANNEL_STAT */
+#define MRT_CHANNEL_STAT_COUNT (4U)
+
+/*! @name MODCFG - Module Configuration register. This register provides information about this particular MRT instance, and allows choosing an overall mode for the idle channel feature. */
+#define MRT_MODCFG_NOC_MASK (0xFU)
+#define MRT_MODCFG_NOC_SHIFT (0U)
+#define MRT_MODCFG_NOC(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOC_SHIFT)) & MRT_MODCFG_NOC_MASK)
+#define MRT_MODCFG_NOB_MASK (0x1F0U)
+#define MRT_MODCFG_NOB_SHIFT (4U)
+#define MRT_MODCFG_NOB(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_NOB_SHIFT)) & MRT_MODCFG_NOB_MASK)
+#define MRT_MODCFG_MULTITASK_MASK (0x80000000U)
+#define MRT_MODCFG_MULTITASK_SHIFT (31U)
+#define MRT_MODCFG_MULTITASK(x) (((uint32_t)(((uint32_t)(x)) << MRT_MODCFG_MULTITASK_SHIFT)) & MRT_MODCFG_MULTITASK_MASK)
+
+/*! @name IDLE_CH - Idle channel register. This register returns the number of the first idle channel. */
+#define MRT_IDLE_CH_CHAN_MASK (0xF0U)
+#define MRT_IDLE_CH_CHAN_SHIFT (4U)
+#define MRT_IDLE_CH_CHAN(x) (((uint32_t)(((uint32_t)(x)) << MRT_IDLE_CH_CHAN_SHIFT)) & MRT_IDLE_CH_CHAN_MASK)
+
+/*! @name IRQ_FLAG - Global interrupt flag register */
+#define MRT_IRQ_FLAG_GFLAG0_MASK (0x1U)
+#define MRT_IRQ_FLAG_GFLAG0_SHIFT (0U)
+#define MRT_IRQ_FLAG_GFLAG0(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG0_SHIFT)) & MRT_IRQ_FLAG_GFLAG0_MASK)
+#define MRT_IRQ_FLAG_GFLAG1_MASK (0x2U)
+#define MRT_IRQ_FLAG_GFLAG1_SHIFT (1U)
+#define MRT_IRQ_FLAG_GFLAG1(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG1_SHIFT)) & MRT_IRQ_FLAG_GFLAG1_MASK)
+#define MRT_IRQ_FLAG_GFLAG2_MASK (0x4U)
+#define MRT_IRQ_FLAG_GFLAG2_SHIFT (2U)
+#define MRT_IRQ_FLAG_GFLAG2(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG2_SHIFT)) & MRT_IRQ_FLAG_GFLAG2_MASK)
+#define MRT_IRQ_FLAG_GFLAG3_MASK (0x8U)
+#define MRT_IRQ_FLAG_GFLAG3_SHIFT (3U)
+#define MRT_IRQ_FLAG_GFLAG3(x) (((uint32_t)(((uint32_t)(x)) << MRT_IRQ_FLAG_GFLAG3_SHIFT)) & MRT_IRQ_FLAG_GFLAG3_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group MRT_Register_Masks */
+
+
+/* MRT - Peripheral instance base addresses */
+/** Peripheral MRT0 base address */
+#define MRT0_BASE (0x4000D000u)
+/** Peripheral MRT0 base pointer */
+#define MRT0 ((MRT_Type *)MRT0_BASE)
+/** Array initializer of MRT peripheral base addresses */
+#define MRT_BASE_ADDRS { MRT0_BASE }
+/** Array initializer of MRT peripheral base pointers */
+#define MRT_BASE_PTRS { MRT0 }
+/** Interrupt vectors for the MRT peripheral type */
+#define MRT_IRQS { MRT0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group MRT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- OTPC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OTPC_Peripheral_Access_Layer OTPC Peripheral Access Layer
+ * @{
+ */
+
+/** OTPC - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[16];
+ __I uint32_t AESKEY[8]; /**< Register for reading the AES key., array offset: 0x10, array step: 0x4 */
+ __I uint32_t ECRP; /**< ECRP options., offset: 0x30 */
+ uint8_t RESERVED_1[4];
+ __I uint32_t USER0; /**< User application specific options., offset: 0x38 */
+ __I uint32_t USER1; /**< User application specific options., offset: 0x3C */
+} OTPC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- OTPC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup OTPC_Register_Masks OTPC Register Masks
+ * @{
+ */
+
+/*! @name AESKEY - Register for reading the AES key. */
+#define OTPC_AESKEY_KEY_MASK (0xFFFFFFFFU)
+#define OTPC_AESKEY_KEY_SHIFT (0U)
+#define OTPC_AESKEY_KEY(x) (((uint32_t)(((uint32_t)(x)) << OTPC_AESKEY_KEY_SHIFT)) & OTPC_AESKEY_KEY_MASK)
+
+/* The count of OTPC_AESKEY */
+#define OTPC_AESKEY_COUNT (8U)
+
+/*! @name ECRP - ECRP options. */
+#define OTPC_ECRP_CRP_MASS_ERASE_DISABLE_MASK (0x10U)
+#define OTPC_ECRP_CRP_MASS_ERASE_DISABLE_SHIFT (4U)
+#define OTPC_ECRP_CRP_MASS_ERASE_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_CRP_MASS_ERASE_DISABLE_SHIFT)) & OTPC_ECRP_CRP_MASS_ERASE_DISABLE_MASK)
+#define OTPC_ECRP_IAP_PROTECTION_ENABLE_MASK (0x20U)
+#define OTPC_ECRP_IAP_PROTECTION_ENABLE_SHIFT (5U)
+#define OTPC_ECRP_IAP_PROTECTION_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_IAP_PROTECTION_ENABLE_SHIFT)) & OTPC_ECRP_IAP_PROTECTION_ENABLE_MASK)
+#define OTPC_ECRP_CRP_ISP_DISABLE_PIN_MASK (0x40U)
+#define OTPC_ECRP_CRP_ISP_DISABLE_PIN_SHIFT (6U)
+#define OTPC_ECRP_CRP_ISP_DISABLE_PIN(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_CRP_ISP_DISABLE_PIN_SHIFT)) & OTPC_ECRP_CRP_ISP_DISABLE_PIN_MASK)
+#define OTPC_ECRP_CRP_ISP_DISABLE_IAP_MASK (0x80U)
+#define OTPC_ECRP_CRP_ISP_DISABLE_IAP_SHIFT (7U)
+#define OTPC_ECRP_CRP_ISP_DISABLE_IAP(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_CRP_ISP_DISABLE_IAP_SHIFT)) & OTPC_ECRP_CRP_ISP_DISABLE_IAP_MASK)
+#define OTPC_ECRP_CRP_ALLOW_ZERO_MASK (0x200U)
+#define OTPC_ECRP_CRP_ALLOW_ZERO_SHIFT (9U)
+#define OTPC_ECRP_CRP_ALLOW_ZERO(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_CRP_ALLOW_ZERO_SHIFT)) & OTPC_ECRP_CRP_ALLOW_ZERO_MASK)
+#define OTPC_ECRP_JTAG_DISABLE_MASK (0x80000000U)
+#define OTPC_ECRP_JTAG_DISABLE_SHIFT (31U)
+#define OTPC_ECRP_JTAG_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << OTPC_ECRP_JTAG_DISABLE_SHIFT)) & OTPC_ECRP_JTAG_DISABLE_MASK)
+
+/*! @name USER0 - User application specific options. */
+#define OTPC_USER0_USER0_MASK (0xFFFFFFFFU)
+#define OTPC_USER0_USER0_SHIFT (0U)
+#define OTPC_USER0_USER0(x) (((uint32_t)(((uint32_t)(x)) << OTPC_USER0_USER0_SHIFT)) & OTPC_USER0_USER0_MASK)
+
+/*! @name USER1 - User application specific options. */
+#define OTPC_USER1_USER1_MASK (0xFFFFFFFFU)
+#define OTPC_USER1_USER1_SHIFT (0U)
+#define OTPC_USER1_USER1(x) (((uint32_t)(((uint32_t)(x)) << OTPC_USER1_USER1_SHIFT)) & OTPC_USER1_USER1_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group OTPC_Register_Masks */
+
+
+/* OTPC - Peripheral instance base addresses */
+/** Peripheral OTPC base address */
+#define OTPC_BASE (0x40015000u)
+/** Peripheral OTPC base pointer */
+#define OTPC ((OTPC_Type *)OTPC_BASE)
+/** Array initializer of OTPC peripheral base addresses */
+#define OTPC_BASE_ADDRS { OTPC_BASE }
+/** Array initializer of OTPC peripheral base pointers */
+#define OTPC_BASE_PTRS { OTPC }
+
+/*!
+ * @}
+ */ /* end of group OTPC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- PINT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PINT_Peripheral_Access_Layer PINT Peripheral Access Layer
+ * @{
+ */
+
+/** PINT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t ISEL; /**< Pin Interrupt Mode register, offset: 0x0 */
+ __IO uint32_t IENR; /**< Pin interrupt level or rising edge interrupt enable register, offset: 0x4 */
+ __O uint32_t SIENR; /**< Pin interrupt level or rising edge interrupt set register, offset: 0x8 */
+ __O uint32_t CIENR; /**< Pin interrupt level (rising edge interrupt) clear register, offset: 0xC */
+ __IO uint32_t IENF; /**< Pin interrupt active level or falling edge interrupt enable register, offset: 0x10 */
+ __O uint32_t SIENF; /**< Pin interrupt active level or falling edge interrupt set register, offset: 0x14 */
+ __O uint32_t CIENF; /**< Pin interrupt active level or falling edge interrupt clear register, offset: 0x18 */
+ __IO uint32_t RISE; /**< Pin interrupt rising edge register, offset: 0x1C */
+ __IO uint32_t FALL; /**< Pin interrupt falling edge register, offset: 0x20 */
+ __IO uint32_t IST; /**< Pin interrupt status register, offset: 0x24 */
+ __IO uint32_t PMCTRL; /**< Pattern match interrupt control register, offset: 0x28 */
+ __IO uint32_t PMSRC; /**< Pattern match interrupt bit-slice source register, offset: 0x2C */
+ __IO uint32_t PMCFG; /**< Pattern match interrupt bit slice configuration register, offset: 0x30 */
+} PINT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- PINT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup PINT_Register_Masks PINT Register Masks
+ * @{
+ */
+
+/*! @name ISEL - Pin Interrupt Mode register */
+#define PINT_ISEL_PMODE_MASK (0xFFU)
+#define PINT_ISEL_PMODE_SHIFT (0U)
+#define PINT_ISEL_PMODE(x) (((uint32_t)(((uint32_t)(x)) << PINT_ISEL_PMODE_SHIFT)) & PINT_ISEL_PMODE_MASK)
+
+/*! @name IENR - Pin interrupt level or rising edge interrupt enable register */
+#define PINT_IENR_ENRL_MASK (0xFFU)
+#define PINT_IENR_ENRL_SHIFT (0U)
+#define PINT_IENR_ENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENR_ENRL_SHIFT)) & PINT_IENR_ENRL_MASK)
+
+/*! @name SIENR - Pin interrupt level or rising edge interrupt set register */
+#define PINT_SIENR_SETENRL_MASK (0xFFU)
+#define PINT_SIENR_SETENRL_SHIFT (0U)
+#define PINT_SIENR_SETENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENR_SETENRL_SHIFT)) & PINT_SIENR_SETENRL_MASK)
+
+/*! @name CIENR - Pin interrupt level (rising edge interrupt) clear register */
+#define PINT_CIENR_CENRL_MASK (0xFFU)
+#define PINT_CIENR_CENRL_SHIFT (0U)
+#define PINT_CIENR_CENRL(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENR_CENRL_SHIFT)) & PINT_CIENR_CENRL_MASK)
+
+/*! @name IENF - Pin interrupt active level or falling edge interrupt enable register */
+#define PINT_IENF_ENAF_MASK (0xFFU)
+#define PINT_IENF_ENAF_SHIFT (0U)
+#define PINT_IENF_ENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_IENF_ENAF_SHIFT)) & PINT_IENF_ENAF_MASK)
+
+/*! @name SIENF - Pin interrupt active level or falling edge interrupt set register */
+#define PINT_SIENF_SETENAF_MASK (0xFFU)
+#define PINT_SIENF_SETENAF_SHIFT (0U)
+#define PINT_SIENF_SETENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_SIENF_SETENAF_SHIFT)) & PINT_SIENF_SETENAF_MASK)
+
+/*! @name CIENF - Pin interrupt active level or falling edge interrupt clear register */
+#define PINT_CIENF_CENAF_MASK (0xFFU)
+#define PINT_CIENF_CENAF_SHIFT (0U)
+#define PINT_CIENF_CENAF(x) (((uint32_t)(((uint32_t)(x)) << PINT_CIENF_CENAF_SHIFT)) & PINT_CIENF_CENAF_MASK)
+
+/*! @name RISE - Pin interrupt rising edge register */
+#define PINT_RISE_RDET_MASK (0xFFU)
+#define PINT_RISE_RDET_SHIFT (0U)
+#define PINT_RISE_RDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_RISE_RDET_SHIFT)) & PINT_RISE_RDET_MASK)
+
+/*! @name FALL - Pin interrupt falling edge register */
+#define PINT_FALL_FDET_MASK (0xFFU)
+#define PINT_FALL_FDET_SHIFT (0U)
+#define PINT_FALL_FDET(x) (((uint32_t)(((uint32_t)(x)) << PINT_FALL_FDET_SHIFT)) & PINT_FALL_FDET_MASK)
+
+/*! @name IST - Pin interrupt status register */
+#define PINT_IST_PSTAT_MASK (0xFFU)
+#define PINT_IST_PSTAT_SHIFT (0U)
+#define PINT_IST_PSTAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_IST_PSTAT_SHIFT)) & PINT_IST_PSTAT_MASK)
+
+/*! @name PMCTRL - Pattern match interrupt control register */
+#define PINT_PMCTRL_SEL_PMATCH_MASK (0x1U)
+#define PINT_PMCTRL_SEL_PMATCH_SHIFT (0U)
+#define PINT_PMCTRL_SEL_PMATCH(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_SEL_PMATCH_SHIFT)) & PINT_PMCTRL_SEL_PMATCH_MASK)
+#define PINT_PMCTRL_ENA_RXEV_MASK (0x2U)
+#define PINT_PMCTRL_ENA_RXEV_SHIFT (1U)
+#define PINT_PMCTRL_ENA_RXEV(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_ENA_RXEV_SHIFT)) & PINT_PMCTRL_ENA_RXEV_MASK)
+#define PINT_PMCTRL_PMAT_MASK (0xFF000000U)
+#define PINT_PMCTRL_PMAT_SHIFT (24U)
+#define PINT_PMCTRL_PMAT(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCTRL_PMAT_SHIFT)) & PINT_PMCTRL_PMAT_MASK)
+
+/*! @name PMSRC - Pattern match interrupt bit-slice source register */
+#define PINT_PMSRC_SRC0_MASK (0x700U)
+#define PINT_PMSRC_SRC0_SHIFT (8U)
+#define PINT_PMSRC_SRC0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC0_SHIFT)) & PINT_PMSRC_SRC0_MASK)
+#define PINT_PMSRC_SRC1_MASK (0x3800U)
+#define PINT_PMSRC_SRC1_SHIFT (11U)
+#define PINT_PMSRC_SRC1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC1_SHIFT)) & PINT_PMSRC_SRC1_MASK)
+#define PINT_PMSRC_SRC2_MASK (0x1C000U)
+#define PINT_PMSRC_SRC2_SHIFT (14U)
+#define PINT_PMSRC_SRC2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC2_SHIFT)) & PINT_PMSRC_SRC2_MASK)
+#define PINT_PMSRC_SRC3_MASK (0xE0000U)
+#define PINT_PMSRC_SRC3_SHIFT (17U)
+#define PINT_PMSRC_SRC3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC3_SHIFT)) & PINT_PMSRC_SRC3_MASK)
+#define PINT_PMSRC_SRC4_MASK (0x700000U)
+#define PINT_PMSRC_SRC4_SHIFT (20U)
+#define PINT_PMSRC_SRC4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC4_SHIFT)) & PINT_PMSRC_SRC4_MASK)
+#define PINT_PMSRC_SRC5_MASK (0x3800000U)
+#define PINT_PMSRC_SRC5_SHIFT (23U)
+#define PINT_PMSRC_SRC5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC5_SHIFT)) & PINT_PMSRC_SRC5_MASK)
+#define PINT_PMSRC_SRC6_MASK (0x1C000000U)
+#define PINT_PMSRC_SRC6_SHIFT (26U)
+#define PINT_PMSRC_SRC6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC6_SHIFT)) & PINT_PMSRC_SRC6_MASK)
+#define PINT_PMSRC_SRC7_MASK (0xE0000000U)
+#define PINT_PMSRC_SRC7_SHIFT (29U)
+#define PINT_PMSRC_SRC7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMSRC_SRC7_SHIFT)) & PINT_PMSRC_SRC7_MASK)
+
+/*! @name PMCFG - Pattern match interrupt bit slice configuration register */
+#define PINT_PMCFG_PROD_ENDPTS0_MASK (0x1U)
+#define PINT_PMCFG_PROD_ENDPTS0_SHIFT (0U)
+#define PINT_PMCFG_PROD_ENDPTS0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS0_SHIFT)) & PINT_PMCFG_PROD_ENDPTS0_MASK)
+#define PINT_PMCFG_PROD_ENDPTS1_MASK (0x2U)
+#define PINT_PMCFG_PROD_ENDPTS1_SHIFT (1U)
+#define PINT_PMCFG_PROD_ENDPTS1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS1_SHIFT)) & PINT_PMCFG_PROD_ENDPTS1_MASK)
+#define PINT_PMCFG_PROD_ENDPTS2_MASK (0x4U)
+#define PINT_PMCFG_PROD_ENDPTS2_SHIFT (2U)
+#define PINT_PMCFG_PROD_ENDPTS2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS2_SHIFT)) & PINT_PMCFG_PROD_ENDPTS2_MASK)
+#define PINT_PMCFG_PROD_ENDPTS3_MASK (0x8U)
+#define PINT_PMCFG_PROD_ENDPTS3_SHIFT (3U)
+#define PINT_PMCFG_PROD_ENDPTS3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS3_SHIFT)) & PINT_PMCFG_PROD_ENDPTS3_MASK)
+#define PINT_PMCFG_PROD_ENDPTS4_MASK (0x10U)
+#define PINT_PMCFG_PROD_ENDPTS4_SHIFT (4U)
+#define PINT_PMCFG_PROD_ENDPTS4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS4_SHIFT)) & PINT_PMCFG_PROD_ENDPTS4_MASK)
+#define PINT_PMCFG_PROD_ENDPTS5_MASK (0x20U)
+#define PINT_PMCFG_PROD_ENDPTS5_SHIFT (5U)
+#define PINT_PMCFG_PROD_ENDPTS5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS5_SHIFT)) & PINT_PMCFG_PROD_ENDPTS5_MASK)
+#define PINT_PMCFG_PROD_ENDPTS6_MASK (0x40U)
+#define PINT_PMCFG_PROD_ENDPTS6_SHIFT (6U)
+#define PINT_PMCFG_PROD_ENDPTS6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_PROD_ENDPTS6_SHIFT)) & PINT_PMCFG_PROD_ENDPTS6_MASK)
+#define PINT_PMCFG_CFG0_MASK (0x700U)
+#define PINT_PMCFG_CFG0_SHIFT (8U)
+#define PINT_PMCFG_CFG0(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG0_SHIFT)) & PINT_PMCFG_CFG0_MASK)
+#define PINT_PMCFG_CFG1_MASK (0x3800U)
+#define PINT_PMCFG_CFG1_SHIFT (11U)
+#define PINT_PMCFG_CFG1(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG1_SHIFT)) & PINT_PMCFG_CFG1_MASK)
+#define PINT_PMCFG_CFG2_MASK (0x1C000U)
+#define PINT_PMCFG_CFG2_SHIFT (14U)
+#define PINT_PMCFG_CFG2(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG2_SHIFT)) & PINT_PMCFG_CFG2_MASK)
+#define PINT_PMCFG_CFG3_MASK (0xE0000U)
+#define PINT_PMCFG_CFG3_SHIFT (17U)
+#define PINT_PMCFG_CFG3(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG3_SHIFT)) & PINT_PMCFG_CFG3_MASK)
+#define PINT_PMCFG_CFG4_MASK (0x700000U)
+#define PINT_PMCFG_CFG4_SHIFT (20U)
+#define PINT_PMCFG_CFG4(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG4_SHIFT)) & PINT_PMCFG_CFG4_MASK)
+#define PINT_PMCFG_CFG5_MASK (0x3800000U)
+#define PINT_PMCFG_CFG5_SHIFT (23U)
+#define PINT_PMCFG_CFG5(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG5_SHIFT)) & PINT_PMCFG_CFG5_MASK)
+#define PINT_PMCFG_CFG6_MASK (0x1C000000U)
+#define PINT_PMCFG_CFG6_SHIFT (26U)
+#define PINT_PMCFG_CFG6(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG6_SHIFT)) & PINT_PMCFG_CFG6_MASK)
+#define PINT_PMCFG_CFG7_MASK (0xE0000000U)
+#define PINT_PMCFG_CFG7_SHIFT (29U)
+#define PINT_PMCFG_CFG7(x) (((uint32_t)(((uint32_t)(x)) << PINT_PMCFG_CFG7_SHIFT)) & PINT_PMCFG_CFG7_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group PINT_Register_Masks */
+
+
+/* PINT - Peripheral instance base addresses */
+/** Peripheral PINT base address */
+#define PINT_BASE (0x40004000u)
+/** Peripheral PINT base pointer */
+#define PINT ((PINT_Type *)PINT_BASE)
+/** Array initializer of PINT peripheral base addresses */
+#define PINT_BASE_ADDRS { PINT_BASE }
+/** Array initializer of PINT peripheral base pointers */
+#define PINT_BASE_PTRS { PINT }
+/** Interrupt vectors for the PINT peripheral type */
+#define PINT_IRQS { PIN_INT0_IRQn, PIN_INT1_IRQn, PIN_INT2_IRQn, PIN_INT3_IRQn, PIN_INT4_IRQn, PIN_INT5_IRQn, PIN_INT6_IRQn, PIN_INT7_IRQn }
+
+/*!
+ * @}
+ */ /* end of group PINT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RIT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RIT_Peripheral_Access_Layer RIT Peripheral Access Layer
+ * @{
+ */
+
+/** RIT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t COMPVAL; /**< Compare value LSB register, offset: 0x0 */
+ __IO uint32_t MASK; /**< Mask LSB register, offset: 0x4 */
+ __IO uint32_t CTRL; /**< Control register, offset: 0x8 */
+ __IO uint32_t COUNTER; /**< Counter LSB register, offset: 0xC */
+ __IO uint32_t COMPVAL_H; /**< Compare value MSB register, offset: 0x10 */
+ __IO uint32_t MASK_H; /**< Mask MSB register, offset: 0x14 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t COUNTER_H; /**< Counter MSB register, offset: 0x1C */
+} RIT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- RIT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RIT_Register_Masks RIT Register Masks
+ * @{
+ */
+
+/*! @name COMPVAL - Compare value LSB register */
+#define RIT_COMPVAL_RICOMP_MASK (0xFFFFFFFFU)
+#define RIT_COMPVAL_RICOMP_SHIFT (0U)
+#define RIT_COMPVAL_RICOMP(x) (((uint32_t)(((uint32_t)(x)) << RIT_COMPVAL_RICOMP_SHIFT)) & RIT_COMPVAL_RICOMP_MASK)
+
+/*! @name MASK - Mask LSB register */
+#define RIT_MASK_RIMASK_MASK (0xFFFFFFFFU)
+#define RIT_MASK_RIMASK_SHIFT (0U)
+#define RIT_MASK_RIMASK(x) (((uint32_t)(((uint32_t)(x)) << RIT_MASK_RIMASK_SHIFT)) & RIT_MASK_RIMASK_MASK)
+
+/*! @name CTRL - Control register */
+#define RIT_CTRL_RITINT_MASK (0x1U)
+#define RIT_CTRL_RITINT_SHIFT (0U)
+#define RIT_CTRL_RITINT(x) (((uint32_t)(((uint32_t)(x)) << RIT_CTRL_RITINT_SHIFT)) & RIT_CTRL_RITINT_MASK)
+#define RIT_CTRL_RITENCLR_MASK (0x2U)
+#define RIT_CTRL_RITENCLR_SHIFT (1U)
+#define RIT_CTRL_RITENCLR(x) (((uint32_t)(((uint32_t)(x)) << RIT_CTRL_RITENCLR_SHIFT)) & RIT_CTRL_RITENCLR_MASK)
+#define RIT_CTRL_RITENBR_MASK (0x4U)
+#define RIT_CTRL_RITENBR_SHIFT (2U)
+#define RIT_CTRL_RITENBR(x) (((uint32_t)(((uint32_t)(x)) << RIT_CTRL_RITENBR_SHIFT)) & RIT_CTRL_RITENBR_MASK)
+#define RIT_CTRL_RITEN_MASK (0x8U)
+#define RIT_CTRL_RITEN_SHIFT (3U)
+#define RIT_CTRL_RITEN(x) (((uint32_t)(((uint32_t)(x)) << RIT_CTRL_RITEN_SHIFT)) & RIT_CTRL_RITEN_MASK)
+
+/*! @name COUNTER - Counter LSB register */
+#define RIT_COUNTER_RICOUNTER_MASK (0xFFFFFFFFU)
+#define RIT_COUNTER_RICOUNTER_SHIFT (0U)
+#define RIT_COUNTER_RICOUNTER(x) (((uint32_t)(((uint32_t)(x)) << RIT_COUNTER_RICOUNTER_SHIFT)) & RIT_COUNTER_RICOUNTER_MASK)
+
+/*! @name COMPVAL_H - Compare value MSB register */
+#define RIT_COMPVAL_H_RICOMP_MASK (0xFFFFU)
+#define RIT_COMPVAL_H_RICOMP_SHIFT (0U)
+#define RIT_COMPVAL_H_RICOMP(x) (((uint32_t)(((uint32_t)(x)) << RIT_COMPVAL_H_RICOMP_SHIFT)) & RIT_COMPVAL_H_RICOMP_MASK)
+
+/*! @name MASK_H - Mask MSB register */
+#define RIT_MASK_H_RIMASK_MASK (0xFFFFU)
+#define RIT_MASK_H_RIMASK_SHIFT (0U)
+#define RIT_MASK_H_RIMASK(x) (((uint32_t)(((uint32_t)(x)) << RIT_MASK_H_RIMASK_SHIFT)) & RIT_MASK_H_RIMASK_MASK)
+
+/*! @name COUNTER_H - Counter MSB register */
+#define RIT_COUNTER_H_RICOUNTER_MASK (0xFFFFU)
+#define RIT_COUNTER_H_RICOUNTER_SHIFT (0U)
+#define RIT_COUNTER_H_RICOUNTER(x) (((uint32_t)(((uint32_t)(x)) << RIT_COUNTER_H_RICOUNTER_SHIFT)) & RIT_COUNTER_H_RICOUNTER_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group RIT_Register_Masks */
+
+
+/* RIT - Peripheral instance base addresses */
+/** Peripheral RIT base address */
+#define RIT_BASE (0x4002D000u)
+/** Peripheral RIT base pointer */
+#define RIT ((RIT_Type *)RIT_BASE)
+/** Array initializer of RIT peripheral base addresses */
+#define RIT_BASE_ADDRS { RIT_BASE }
+/** Array initializer of RIT peripheral base pointers */
+#define RIT_BASE_PTRS { RIT }
+/** Interrupt vectors for the RIT peripheral type */
+#define RIT_IRQS { RIT_IRQn }
+
+/*!
+ * @}
+ */ /* end of group RIT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- RTC Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Peripheral_Access_Layer RTC Peripheral Access Layer
+ * @{
+ */
+
+/** RTC - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CTRL; /**< RTC control register, offset: 0x0 */
+ __IO uint32_t MATCH; /**< RTC match register, offset: 0x4 */
+ __IO uint32_t COUNT; /**< RTC counter register, offset: 0x8 */
+ __IO uint32_t WAKE; /**< High-resolution/wake-up timer control register, offset: 0xC */
+ uint8_t RESERVED_0[48];
+ __IO uint32_t GPREG[8]; /**< General Purpose register, array offset: 0x40, array step: 0x4 */
+} RTC_Type;
+
+/* ----------------------------------------------------------------------------
+ -- RTC Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup RTC_Register_Masks RTC Register Masks
+ * @{
+ */
+
+/*! @name CTRL - RTC control register */
+#define RTC_CTRL_SWRESET_MASK (0x1U)
+#define RTC_CTRL_SWRESET_SHIFT (0U)
+#define RTC_CTRL_SWRESET(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_SWRESET_SHIFT)) & RTC_CTRL_SWRESET_MASK)
+#define RTC_CTRL_ALARM1HZ_MASK (0x4U)
+#define RTC_CTRL_ALARM1HZ_SHIFT (2U)
+#define RTC_CTRL_ALARM1HZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARM1HZ_SHIFT)) & RTC_CTRL_ALARM1HZ_MASK)
+#define RTC_CTRL_WAKE1KHZ_MASK (0x8U)
+#define RTC_CTRL_WAKE1KHZ_SHIFT (3U)
+#define RTC_CTRL_WAKE1KHZ(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKE1KHZ_SHIFT)) & RTC_CTRL_WAKE1KHZ_MASK)
+#define RTC_CTRL_ALARMDPD_EN_MASK (0x10U)
+#define RTC_CTRL_ALARMDPD_EN_SHIFT (4U)
+#define RTC_CTRL_ALARMDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_ALARMDPD_EN_SHIFT)) & RTC_CTRL_ALARMDPD_EN_MASK)
+#define RTC_CTRL_WAKEDPD_EN_MASK (0x20U)
+#define RTC_CTRL_WAKEDPD_EN_SHIFT (5U)
+#define RTC_CTRL_WAKEDPD_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_WAKEDPD_EN_SHIFT)) & RTC_CTRL_WAKEDPD_EN_MASK)
+#define RTC_CTRL_RTC1KHZ_EN_MASK (0x40U)
+#define RTC_CTRL_RTC1KHZ_EN_SHIFT (6U)
+#define RTC_CTRL_RTC1KHZ_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC1KHZ_EN_SHIFT)) & RTC_CTRL_RTC1KHZ_EN_MASK)
+#define RTC_CTRL_RTC_EN_MASK (0x80U)
+#define RTC_CTRL_RTC_EN_SHIFT (7U)
+#define RTC_CTRL_RTC_EN(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_EN_SHIFT)) & RTC_CTRL_RTC_EN_MASK)
+#define RTC_CTRL_RTC_OSC_PD_MASK (0x100U)
+#define RTC_CTRL_RTC_OSC_PD_SHIFT (8U)
+#define RTC_CTRL_RTC_OSC_PD(x) (((uint32_t)(((uint32_t)(x)) << RTC_CTRL_RTC_OSC_PD_SHIFT)) & RTC_CTRL_RTC_OSC_PD_MASK)
+
+/*! @name MATCH - RTC match register */
+#define RTC_MATCH_MATVAL_MASK (0xFFFFFFFFU)
+#define RTC_MATCH_MATVAL_SHIFT (0U)
+#define RTC_MATCH_MATVAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_MATCH_MATVAL_SHIFT)) & RTC_MATCH_MATVAL_MASK)
+
+/*! @name COUNT - RTC counter register */
+#define RTC_COUNT_VAL_MASK (0xFFFFFFFFU)
+#define RTC_COUNT_VAL_SHIFT (0U)
+#define RTC_COUNT_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_COUNT_VAL_SHIFT)) & RTC_COUNT_VAL_MASK)
+
+/*! @name WAKE - High-resolution/wake-up timer control register */
+#define RTC_WAKE_VAL_MASK (0xFFFFU)
+#define RTC_WAKE_VAL_SHIFT (0U)
+#define RTC_WAKE_VAL(x) (((uint32_t)(((uint32_t)(x)) << RTC_WAKE_VAL_SHIFT)) & RTC_WAKE_VAL_MASK)
+
+/*! @name GPREG - General Purpose register */
+#define RTC_GPREG_GPDATA_MASK (0xFFFFFFFFU)
+#define RTC_GPREG_GPDATA_SHIFT (0U)
+#define RTC_GPREG_GPDATA(x) (((uint32_t)(((uint32_t)(x)) << RTC_GPREG_GPDATA_SHIFT)) & RTC_GPREG_GPDATA_MASK)
+
+/* The count of RTC_GPREG */
+#define RTC_GPREG_COUNT (8U)
+
+
+/*!
+ * @}
+ */ /* end of group RTC_Register_Masks */
+
+
+/* RTC - Peripheral instance base addresses */
+/** Peripheral RTC base address */
+#define RTC_BASE (0x4002C000u)
+/** Peripheral RTC base pointer */
+#define RTC ((RTC_Type *)RTC_BASE)
+/** Array initializer of RTC peripheral base addresses */
+#define RTC_BASE_ADDRS { RTC_BASE }
+/** Array initializer of RTC peripheral base pointers */
+#define RTC_BASE_PTRS { RTC }
+/** Interrupt vectors for the RTC peripheral type */
+#define RTC_IRQS { RTC_IRQn }
+
+/*!
+ * @}
+ */ /* end of group RTC_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SCT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SCT_Peripheral_Access_Layer SCT Peripheral Access Layer
+ * @{
+ */
+
+/** SCT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CONFIG; /**< SCT configuration register, offset: 0x0 */
+ __IO uint32_t CTRL; /**< SCT control register, offset: 0x4 */
+ __IO uint32_t LIMIT; /**< SCT limit event select register, offset: 0x8 */
+ __IO uint32_t HALT; /**< SCT halt event select register, offset: 0xC */
+ __IO uint32_t STOP; /**< SCT stop event select register, offset: 0x10 */
+ __IO uint32_t START; /**< SCT start event select register, offset: 0x14 */
+ uint8_t RESERVED_0[40];
+ __IO uint32_t COUNT; /**< SCT counter register, offset: 0x40 */
+ __IO uint32_t STATE; /**< SCT state register, offset: 0x44 */
+ __I uint32_t INPUT; /**< SCT input register, offset: 0x48 */
+ __IO uint32_t REGMODE; /**< SCT match/capture mode register, offset: 0x4C */
+ __IO uint32_t OUTPUT; /**< SCT output register, offset: 0x50 */
+ __IO uint32_t OUTPUTDIRCTRL; /**< SCT output counter direction control register, offset: 0x54 */
+ __IO uint32_t RES; /**< SCT conflict resolution register, offset: 0x58 */
+ __IO uint32_t DMA0REQUEST; /**< SCT DMA request 0 register, offset: 0x5C */
+ __IO uint32_t DMA1REQUEST; /**< SCT DMA request 1 register, offset: 0x60 */
+ uint8_t RESERVED_1[140];
+ __IO uint32_t EVEN; /**< SCT event interrupt enable register, offset: 0xF0 */
+ __IO uint32_t EVFLAG; /**< SCT event flag register, offset: 0xF4 */
+ __IO uint32_t CONEN; /**< SCT conflict interrupt enable register, offset: 0xF8 */
+ __IO uint32_t CONFLAG; /**< SCT conflict flag register, offset: 0xFC */
+ union { /* offset: 0x100 */
+ __IO uint32_t SCTCAP[10]; /**< SCT capture register of capture channel, array offset: 0x100, array step: 0x4 */
+ __IO uint32_t SCTMATCH[10]; /**< SCT match value register of match channels, array offset: 0x100, array step: 0x4 */
+ };
+ uint8_t RESERVED_2[216];
+ union { /* offset: 0x200 */
+ __IO uint32_t SCTCAPCTRL[10]; /**< SCT capture control register, array offset: 0x200, array step: 0x4 */
+ __IO uint32_t SCTMATCHREL[10]; /**< SCT match reload value register, array offset: 0x200, array step: 0x4 */
+ };
+ uint8_t RESERVED_3[216];
+ struct { /* offset: 0x300, array step: 0x8 */
+ __IO uint32_t STATE; /**< SCT event state register 0, array offset: 0x300, array step: 0x8 */
+ __IO uint32_t CTRL; /**< SCT event control register 0, array offset: 0x304, array step: 0x8 */
+ } EVENT[10];
+ uint8_t RESERVED_4[432];
+ struct { /* offset: 0x500, array step: 0x8 */
+ __IO uint32_t SET; /**< SCT output 0 set register, array offset: 0x500, array step: 0x8 */
+ __IO uint32_t CLR; /**< SCT output 0 clear register, array offset: 0x504, array step: 0x8 */
+ } OUT[10];
+} SCT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SCT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SCT_Register_Masks SCT Register Masks
+ * @{
+ */
+
+/*! @name CONFIG - SCT configuration register */
+#define SCT_CONFIG_UNIFY_MASK (0x1U)
+#define SCT_CONFIG_UNIFY_SHIFT (0U)
+#define SCT_CONFIG_UNIFY(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_UNIFY_SHIFT)) & SCT_CONFIG_UNIFY_MASK)
+#define SCT_CONFIG_CLKMODE_MASK (0x6U)
+#define SCT_CONFIG_CLKMODE_SHIFT (1U)
+#define SCT_CONFIG_CLKMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CLKMODE_SHIFT)) & SCT_CONFIG_CLKMODE_MASK)
+#define SCT_CONFIG_CKSEL_MASK (0x78U)
+#define SCT_CONFIG_CKSEL_SHIFT (3U)
+#define SCT_CONFIG_CKSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_CKSEL_SHIFT)) & SCT_CONFIG_CKSEL_MASK)
+#define SCT_CONFIG_NORELAOD_L_MASK (0x80U)
+#define SCT_CONFIG_NORELAOD_L_SHIFT (7U)
+#define SCT_CONFIG_NORELAOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELAOD_L_SHIFT)) & SCT_CONFIG_NORELAOD_L_MASK)
+#define SCT_CONFIG_NORELOAD_H_MASK (0x100U)
+#define SCT_CONFIG_NORELOAD_H_SHIFT (8U)
+#define SCT_CONFIG_NORELOAD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_NORELOAD_H_SHIFT)) & SCT_CONFIG_NORELOAD_H_MASK)
+#define SCT_CONFIG_INSYNC_MASK (0x1E00U)
+#define SCT_CONFIG_INSYNC_SHIFT (9U)
+#define SCT_CONFIG_INSYNC(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_INSYNC_SHIFT)) & SCT_CONFIG_INSYNC_MASK)
+#define SCT_CONFIG_AUTOLIMIT_L_MASK (0x20000U)
+#define SCT_CONFIG_AUTOLIMIT_L_SHIFT (17U)
+#define SCT_CONFIG_AUTOLIMIT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_L_SHIFT)) & SCT_CONFIG_AUTOLIMIT_L_MASK)
+#define SCT_CONFIG_AUTOLIMIT_H_MASK (0x40000U)
+#define SCT_CONFIG_AUTOLIMIT_H_SHIFT (18U)
+#define SCT_CONFIG_AUTOLIMIT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFIG_AUTOLIMIT_H_SHIFT)) & SCT_CONFIG_AUTOLIMIT_H_MASK)
+
+/*! @name CTRL - SCT control register */
+#define SCT_CTRL_DOWN_L_MASK (0x1U)
+#define SCT_CTRL_DOWN_L_SHIFT (0U)
+#define SCT_CTRL_DOWN_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_L_SHIFT)) & SCT_CTRL_DOWN_L_MASK)
+#define SCT_CTRL_STOP_L_MASK (0x2U)
+#define SCT_CTRL_STOP_L_SHIFT (1U)
+#define SCT_CTRL_STOP_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_L_SHIFT)) & SCT_CTRL_STOP_L_MASK)
+#define SCT_CTRL_HALT_L_MASK (0x4U)
+#define SCT_CTRL_HALT_L_SHIFT (2U)
+#define SCT_CTRL_HALT_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_L_SHIFT)) & SCT_CTRL_HALT_L_MASK)
+#define SCT_CTRL_CLRCTR_L_MASK (0x8U)
+#define SCT_CTRL_CLRCTR_L_SHIFT (3U)
+#define SCT_CTRL_CLRCTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_L_SHIFT)) & SCT_CTRL_CLRCTR_L_MASK)
+#define SCT_CTRL_BIDIR_L_MASK (0x10U)
+#define SCT_CTRL_BIDIR_L_SHIFT (4U)
+#define SCT_CTRL_BIDIR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_L_SHIFT)) & SCT_CTRL_BIDIR_L_MASK)
+#define SCT_CTRL_PRE_L_MASK (0x1FE0U)
+#define SCT_CTRL_PRE_L_SHIFT (5U)
+#define SCT_CTRL_PRE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_L_SHIFT)) & SCT_CTRL_PRE_L_MASK)
+#define SCT_CTRL_DOWN_H_MASK (0x10000U)
+#define SCT_CTRL_DOWN_H_SHIFT (16U)
+#define SCT_CTRL_DOWN_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_DOWN_H_SHIFT)) & SCT_CTRL_DOWN_H_MASK)
+#define SCT_CTRL_STOP_H_MASK (0x20000U)
+#define SCT_CTRL_STOP_H_SHIFT (17U)
+#define SCT_CTRL_STOP_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_STOP_H_SHIFT)) & SCT_CTRL_STOP_H_MASK)
+#define SCT_CTRL_HALT_H_MASK (0x40000U)
+#define SCT_CTRL_HALT_H_SHIFT (18U)
+#define SCT_CTRL_HALT_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_HALT_H_SHIFT)) & SCT_CTRL_HALT_H_MASK)
+#define SCT_CTRL_CLRCTR_H_MASK (0x80000U)
+#define SCT_CTRL_CLRCTR_H_SHIFT (19U)
+#define SCT_CTRL_CLRCTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_CLRCTR_H_SHIFT)) & SCT_CTRL_CLRCTR_H_MASK)
+#define SCT_CTRL_BIDIR_H_MASK (0x100000U)
+#define SCT_CTRL_BIDIR_H_SHIFT (20U)
+#define SCT_CTRL_BIDIR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_BIDIR_H_SHIFT)) & SCT_CTRL_BIDIR_H_MASK)
+#define SCT_CTRL_PRE_H_MASK (0x1FE00000U)
+#define SCT_CTRL_PRE_H_SHIFT (21U)
+#define SCT_CTRL_PRE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_CTRL_PRE_H_SHIFT)) & SCT_CTRL_PRE_H_MASK)
+
+/*! @name LIMIT - SCT limit event select register */
+#define SCT_LIMIT_LIMMSK_L_MASK (0xFFFFU)
+#define SCT_LIMIT_LIMMSK_L_SHIFT (0U)
+#define SCT_LIMIT_LIMMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_L_SHIFT)) & SCT_LIMIT_LIMMSK_L_MASK)
+#define SCT_LIMIT_LIMMSK_H_MASK (0xFFFF0000U)
+#define SCT_LIMIT_LIMMSK_H_SHIFT (16U)
+#define SCT_LIMIT_LIMMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_LIMIT_LIMMSK_H_SHIFT)) & SCT_LIMIT_LIMMSK_H_MASK)
+
+/*! @name HALT - SCT halt event select register */
+#define SCT_HALT_HALTMSK_L_MASK (0xFFFFU)
+#define SCT_HALT_HALTMSK_L_SHIFT (0U)
+#define SCT_HALT_HALTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_L_SHIFT)) & SCT_HALT_HALTMSK_L_MASK)
+#define SCT_HALT_HALTMSK_H_MASK (0xFFFF0000U)
+#define SCT_HALT_HALTMSK_H_SHIFT (16U)
+#define SCT_HALT_HALTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_HALT_HALTMSK_H_SHIFT)) & SCT_HALT_HALTMSK_H_MASK)
+
+/*! @name STOP - SCT stop event select register */
+#define SCT_STOP_STOPMSK_L_MASK (0xFFFFU)
+#define SCT_STOP_STOPMSK_L_SHIFT (0U)
+#define SCT_STOP_STOPMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_L_SHIFT)) & SCT_STOP_STOPMSK_L_MASK)
+#define SCT_STOP_STOPMSK_H_MASK (0xFFFF0000U)
+#define SCT_STOP_STOPMSK_H_SHIFT (16U)
+#define SCT_STOP_STOPMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STOP_STOPMSK_H_SHIFT)) & SCT_STOP_STOPMSK_H_MASK)
+
+/*! @name START - SCT start event select register */
+#define SCT_START_STARTMSK_L_MASK (0xFFFFU)
+#define SCT_START_STARTMSK_L_SHIFT (0U)
+#define SCT_START_STARTMSK_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_L_SHIFT)) & SCT_START_STARTMSK_L_MASK)
+#define SCT_START_STARTMSK_H_MASK (0xFFFF0000U)
+#define SCT_START_STARTMSK_H_SHIFT (16U)
+#define SCT_START_STARTMSK_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_START_STARTMSK_H_SHIFT)) & SCT_START_STARTMSK_H_MASK)
+
+/*! @name COUNT - SCT counter register */
+#define SCT_COUNT_CTR_L_MASK (0xFFFFU)
+#define SCT_COUNT_CTR_L_SHIFT (0U)
+#define SCT_COUNT_CTR_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_L_SHIFT)) & SCT_COUNT_CTR_L_MASK)
+#define SCT_COUNT_CTR_H_MASK (0xFFFF0000U)
+#define SCT_COUNT_CTR_H_SHIFT (16U)
+#define SCT_COUNT_CTR_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_COUNT_CTR_H_SHIFT)) & SCT_COUNT_CTR_H_MASK)
+
+/*! @name STATE - SCT state register */
+#define SCT_STATE_STATE_L_MASK (0x1FU)
+#define SCT_STATE_STATE_L_SHIFT (0U)
+#define SCT_STATE_STATE_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_L_SHIFT)) & SCT_STATE_STATE_L_MASK)
+#define SCT_STATE_STATE_H_MASK (0x1F0000U)
+#define SCT_STATE_STATE_H_SHIFT (16U)
+#define SCT_STATE_STATE_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_STATE_STATE_H_SHIFT)) & SCT_STATE_STATE_H_MASK)
+
+/*! @name INPUT - SCT input register */
+#define SCT_INPUT_AIN0_MASK (0x1U)
+#define SCT_INPUT_AIN0_SHIFT (0U)
+#define SCT_INPUT_AIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN0_SHIFT)) & SCT_INPUT_AIN0_MASK)
+#define SCT_INPUT_AIN1_MASK (0x2U)
+#define SCT_INPUT_AIN1_SHIFT (1U)
+#define SCT_INPUT_AIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN1_SHIFT)) & SCT_INPUT_AIN1_MASK)
+#define SCT_INPUT_AIN2_MASK (0x4U)
+#define SCT_INPUT_AIN2_SHIFT (2U)
+#define SCT_INPUT_AIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN2_SHIFT)) & SCT_INPUT_AIN2_MASK)
+#define SCT_INPUT_AIN3_MASK (0x8U)
+#define SCT_INPUT_AIN3_SHIFT (3U)
+#define SCT_INPUT_AIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN3_SHIFT)) & SCT_INPUT_AIN3_MASK)
+#define SCT_INPUT_AIN4_MASK (0x10U)
+#define SCT_INPUT_AIN4_SHIFT (4U)
+#define SCT_INPUT_AIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN4_SHIFT)) & SCT_INPUT_AIN4_MASK)
+#define SCT_INPUT_AIN5_MASK (0x20U)
+#define SCT_INPUT_AIN5_SHIFT (5U)
+#define SCT_INPUT_AIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN5_SHIFT)) & SCT_INPUT_AIN5_MASK)
+#define SCT_INPUT_AIN6_MASK (0x40U)
+#define SCT_INPUT_AIN6_SHIFT (6U)
+#define SCT_INPUT_AIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN6_SHIFT)) & SCT_INPUT_AIN6_MASK)
+#define SCT_INPUT_AIN7_MASK (0x80U)
+#define SCT_INPUT_AIN7_SHIFT (7U)
+#define SCT_INPUT_AIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN7_SHIFT)) & SCT_INPUT_AIN7_MASK)
+#define SCT_INPUT_AIN8_MASK (0x100U)
+#define SCT_INPUT_AIN8_SHIFT (8U)
+#define SCT_INPUT_AIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN8_SHIFT)) & SCT_INPUT_AIN8_MASK)
+#define SCT_INPUT_AIN9_MASK (0x200U)
+#define SCT_INPUT_AIN9_SHIFT (9U)
+#define SCT_INPUT_AIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN9_SHIFT)) & SCT_INPUT_AIN9_MASK)
+#define SCT_INPUT_AIN10_MASK (0x400U)
+#define SCT_INPUT_AIN10_SHIFT (10U)
+#define SCT_INPUT_AIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN10_SHIFT)) & SCT_INPUT_AIN10_MASK)
+#define SCT_INPUT_AIN11_MASK (0x800U)
+#define SCT_INPUT_AIN11_SHIFT (11U)
+#define SCT_INPUT_AIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN11_SHIFT)) & SCT_INPUT_AIN11_MASK)
+#define SCT_INPUT_AIN12_MASK (0x1000U)
+#define SCT_INPUT_AIN12_SHIFT (12U)
+#define SCT_INPUT_AIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN12_SHIFT)) & SCT_INPUT_AIN12_MASK)
+#define SCT_INPUT_AIN13_MASK (0x2000U)
+#define SCT_INPUT_AIN13_SHIFT (13U)
+#define SCT_INPUT_AIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN13_SHIFT)) & SCT_INPUT_AIN13_MASK)
+#define SCT_INPUT_AIN14_MASK (0x4000U)
+#define SCT_INPUT_AIN14_SHIFT (14U)
+#define SCT_INPUT_AIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN14_SHIFT)) & SCT_INPUT_AIN14_MASK)
+#define SCT_INPUT_AIN15_MASK (0x8000U)
+#define SCT_INPUT_AIN15_SHIFT (15U)
+#define SCT_INPUT_AIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_AIN15_SHIFT)) & SCT_INPUT_AIN15_MASK)
+#define SCT_INPUT_SIN0_MASK (0x10000U)
+#define SCT_INPUT_SIN0_SHIFT (16U)
+#define SCT_INPUT_SIN0(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN0_SHIFT)) & SCT_INPUT_SIN0_MASK)
+#define SCT_INPUT_SIN1_MASK (0x20000U)
+#define SCT_INPUT_SIN1_SHIFT (17U)
+#define SCT_INPUT_SIN1(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN1_SHIFT)) & SCT_INPUT_SIN1_MASK)
+#define SCT_INPUT_SIN2_MASK (0x40000U)
+#define SCT_INPUT_SIN2_SHIFT (18U)
+#define SCT_INPUT_SIN2(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN2_SHIFT)) & SCT_INPUT_SIN2_MASK)
+#define SCT_INPUT_SIN3_MASK (0x80000U)
+#define SCT_INPUT_SIN3_SHIFT (19U)
+#define SCT_INPUT_SIN3(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN3_SHIFT)) & SCT_INPUT_SIN3_MASK)
+#define SCT_INPUT_SIN4_MASK (0x100000U)
+#define SCT_INPUT_SIN4_SHIFT (20U)
+#define SCT_INPUT_SIN4(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN4_SHIFT)) & SCT_INPUT_SIN4_MASK)
+#define SCT_INPUT_SIN5_MASK (0x200000U)
+#define SCT_INPUT_SIN5_SHIFT (21U)
+#define SCT_INPUT_SIN5(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN5_SHIFT)) & SCT_INPUT_SIN5_MASK)
+#define SCT_INPUT_SIN6_MASK (0x400000U)
+#define SCT_INPUT_SIN6_SHIFT (22U)
+#define SCT_INPUT_SIN6(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN6_SHIFT)) & SCT_INPUT_SIN6_MASK)
+#define SCT_INPUT_SIN7_MASK (0x800000U)
+#define SCT_INPUT_SIN7_SHIFT (23U)
+#define SCT_INPUT_SIN7(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN7_SHIFT)) & SCT_INPUT_SIN7_MASK)
+#define SCT_INPUT_SIN8_MASK (0x1000000U)
+#define SCT_INPUT_SIN8_SHIFT (24U)
+#define SCT_INPUT_SIN8(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN8_SHIFT)) & SCT_INPUT_SIN8_MASK)
+#define SCT_INPUT_SIN9_MASK (0x2000000U)
+#define SCT_INPUT_SIN9_SHIFT (25U)
+#define SCT_INPUT_SIN9(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN9_SHIFT)) & SCT_INPUT_SIN9_MASK)
+#define SCT_INPUT_SIN10_MASK (0x4000000U)
+#define SCT_INPUT_SIN10_SHIFT (26U)
+#define SCT_INPUT_SIN10(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN10_SHIFT)) & SCT_INPUT_SIN10_MASK)
+#define SCT_INPUT_SIN11_MASK (0x8000000U)
+#define SCT_INPUT_SIN11_SHIFT (27U)
+#define SCT_INPUT_SIN11(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN11_SHIFT)) & SCT_INPUT_SIN11_MASK)
+#define SCT_INPUT_SIN12_MASK (0x10000000U)
+#define SCT_INPUT_SIN12_SHIFT (28U)
+#define SCT_INPUT_SIN12(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN12_SHIFT)) & SCT_INPUT_SIN12_MASK)
+#define SCT_INPUT_SIN13_MASK (0x20000000U)
+#define SCT_INPUT_SIN13_SHIFT (29U)
+#define SCT_INPUT_SIN13(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN13_SHIFT)) & SCT_INPUT_SIN13_MASK)
+#define SCT_INPUT_SIN14_MASK (0x40000000U)
+#define SCT_INPUT_SIN14_SHIFT (30U)
+#define SCT_INPUT_SIN14(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN14_SHIFT)) & SCT_INPUT_SIN14_MASK)
+#define SCT_INPUT_SIN15_MASK (0x80000000U)
+#define SCT_INPUT_SIN15_SHIFT (31U)
+#define SCT_INPUT_SIN15(x) (((uint32_t)(((uint32_t)(x)) << SCT_INPUT_SIN15_SHIFT)) & SCT_INPUT_SIN15_MASK)
+
+/*! @name REGMODE - SCT match/capture mode register */
+#define SCT_REGMODE_REGMOD_L_MASK (0xFFFFU)
+#define SCT_REGMODE_REGMOD_L_SHIFT (0U)
+#define SCT_REGMODE_REGMOD_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_L_SHIFT)) & SCT_REGMODE_REGMOD_L_MASK)
+#define SCT_REGMODE_REGMOD_H_MASK (0xFFFF0000U)
+#define SCT_REGMODE_REGMOD_H_SHIFT (16U)
+#define SCT_REGMODE_REGMOD_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_REGMODE_REGMOD_H_SHIFT)) & SCT_REGMODE_REGMOD_H_MASK)
+
+/*! @name OUTPUT - SCT output register */
+#define SCT_OUTPUT_OUT_MASK (0xFFFFU)
+#define SCT_OUTPUT_OUT_SHIFT (0U)
+#define SCT_OUTPUT_OUT(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUT_OUT_SHIFT)) & SCT_OUTPUT_OUT_MASK)
+
+/*! @name OUTPUTDIRCTRL - SCT output counter direction control register */
+#define SCT_OUTPUTDIRCTRL_SETCLR0_MASK (0x3U)
+#define SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT (0U)
+#define SCT_OUTPUTDIRCTRL_SETCLR0(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR0_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR0_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR1_MASK (0xCU)
+#define SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT (2U)
+#define SCT_OUTPUTDIRCTRL_SETCLR1(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR1_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR1_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR2_MASK (0x30U)
+#define SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT (4U)
+#define SCT_OUTPUTDIRCTRL_SETCLR2(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR2_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR2_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR3_MASK (0xC0U)
+#define SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT (6U)
+#define SCT_OUTPUTDIRCTRL_SETCLR3(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR3_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR3_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR4_MASK (0x300U)
+#define SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT (8U)
+#define SCT_OUTPUTDIRCTRL_SETCLR4(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR4_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR4_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR5_MASK (0xC00U)
+#define SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT (10U)
+#define SCT_OUTPUTDIRCTRL_SETCLR5(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR5_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR5_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR6_MASK (0x3000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT (12U)
+#define SCT_OUTPUTDIRCTRL_SETCLR6(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR6_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR6_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR7_MASK (0xC000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT (14U)
+#define SCT_OUTPUTDIRCTRL_SETCLR7(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR7_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR7_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR8_MASK (0x30000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT (16U)
+#define SCT_OUTPUTDIRCTRL_SETCLR8(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR8_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR8_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR9_MASK (0xC0000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT (18U)
+#define SCT_OUTPUTDIRCTRL_SETCLR9(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR9_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR9_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR10_MASK (0x300000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT (20U)
+#define SCT_OUTPUTDIRCTRL_SETCLR10(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR10_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR10_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR11_MASK (0xC00000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT (22U)
+#define SCT_OUTPUTDIRCTRL_SETCLR11(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR11_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR11_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR12_MASK (0x3000000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT (24U)
+#define SCT_OUTPUTDIRCTRL_SETCLR12(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR12_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR12_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR13_MASK (0xC000000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT (26U)
+#define SCT_OUTPUTDIRCTRL_SETCLR13(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR13_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR13_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR14_MASK (0x30000000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT (28U)
+#define SCT_OUTPUTDIRCTRL_SETCLR14(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR14_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR14_MASK)
+#define SCT_OUTPUTDIRCTRL_SETCLR15_MASK (0xC0000000U)
+#define SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT (30U)
+#define SCT_OUTPUTDIRCTRL_SETCLR15(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUTPUTDIRCTRL_SETCLR15_SHIFT)) & SCT_OUTPUTDIRCTRL_SETCLR15_MASK)
+
+/*! @name RES - SCT conflict resolution register */
+#define SCT_RES_O0RES_MASK (0x3U)
+#define SCT_RES_O0RES_SHIFT (0U)
+#define SCT_RES_O0RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O0RES_SHIFT)) & SCT_RES_O0RES_MASK)
+#define SCT_RES_O1RES_MASK (0xCU)
+#define SCT_RES_O1RES_SHIFT (2U)
+#define SCT_RES_O1RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O1RES_SHIFT)) & SCT_RES_O1RES_MASK)
+#define SCT_RES_O2RES_MASK (0x30U)
+#define SCT_RES_O2RES_SHIFT (4U)
+#define SCT_RES_O2RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O2RES_SHIFT)) & SCT_RES_O2RES_MASK)
+#define SCT_RES_O3RES_MASK (0xC0U)
+#define SCT_RES_O3RES_SHIFT (6U)
+#define SCT_RES_O3RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O3RES_SHIFT)) & SCT_RES_O3RES_MASK)
+#define SCT_RES_O4RES_MASK (0x300U)
+#define SCT_RES_O4RES_SHIFT (8U)
+#define SCT_RES_O4RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O4RES_SHIFT)) & SCT_RES_O4RES_MASK)
+#define SCT_RES_O5RES_MASK (0xC00U)
+#define SCT_RES_O5RES_SHIFT (10U)
+#define SCT_RES_O5RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O5RES_SHIFT)) & SCT_RES_O5RES_MASK)
+#define SCT_RES_O6RES_MASK (0x3000U)
+#define SCT_RES_O6RES_SHIFT (12U)
+#define SCT_RES_O6RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O6RES_SHIFT)) & SCT_RES_O6RES_MASK)
+#define SCT_RES_O7RES_MASK (0xC000U)
+#define SCT_RES_O7RES_SHIFT (14U)
+#define SCT_RES_O7RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O7RES_SHIFT)) & SCT_RES_O7RES_MASK)
+#define SCT_RES_O8RES_MASK (0x30000U)
+#define SCT_RES_O8RES_SHIFT (16U)
+#define SCT_RES_O8RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O8RES_SHIFT)) & SCT_RES_O8RES_MASK)
+#define SCT_RES_O9RES_MASK (0xC0000U)
+#define SCT_RES_O9RES_SHIFT (18U)
+#define SCT_RES_O9RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O9RES_SHIFT)) & SCT_RES_O9RES_MASK)
+#define SCT_RES_O10RES_MASK (0x300000U)
+#define SCT_RES_O10RES_SHIFT (20U)
+#define SCT_RES_O10RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O10RES_SHIFT)) & SCT_RES_O10RES_MASK)
+#define SCT_RES_O11RES_MASK (0xC00000U)
+#define SCT_RES_O11RES_SHIFT (22U)
+#define SCT_RES_O11RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O11RES_SHIFT)) & SCT_RES_O11RES_MASK)
+#define SCT_RES_O12RES_MASK (0x3000000U)
+#define SCT_RES_O12RES_SHIFT (24U)
+#define SCT_RES_O12RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O12RES_SHIFT)) & SCT_RES_O12RES_MASK)
+#define SCT_RES_O13RES_MASK (0xC000000U)
+#define SCT_RES_O13RES_SHIFT (26U)
+#define SCT_RES_O13RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O13RES_SHIFT)) & SCT_RES_O13RES_MASK)
+#define SCT_RES_O14RES_MASK (0x30000000U)
+#define SCT_RES_O14RES_SHIFT (28U)
+#define SCT_RES_O14RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O14RES_SHIFT)) & SCT_RES_O14RES_MASK)
+#define SCT_RES_O15RES_MASK (0xC0000000U)
+#define SCT_RES_O15RES_SHIFT (30U)
+#define SCT_RES_O15RES(x) (((uint32_t)(((uint32_t)(x)) << SCT_RES_O15RES_SHIFT)) & SCT_RES_O15RES_MASK)
+
+/*! @name DMA0REQUEST - SCT DMA request 0 register */
+#define SCT_DMA0REQUEST_DEV_0_MASK (0xFFFFU)
+#define SCT_DMA0REQUEST_DEV_0_SHIFT (0U)
+#define SCT_DMA0REQUEST_DEV_0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DEV_0_SHIFT)) & SCT_DMA0REQUEST_DEV_0_MASK)
+#define SCT_DMA0REQUEST_DRL0_MASK (0x40000000U)
+#define SCT_DMA0REQUEST_DRL0_SHIFT (30U)
+#define SCT_DMA0REQUEST_DRL0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DRL0_SHIFT)) & SCT_DMA0REQUEST_DRL0_MASK)
+#define SCT_DMA0REQUEST_DRQ0_MASK (0x80000000U)
+#define SCT_DMA0REQUEST_DRQ0_SHIFT (31U)
+#define SCT_DMA0REQUEST_DRQ0(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA0REQUEST_DRQ0_SHIFT)) & SCT_DMA0REQUEST_DRQ0_MASK)
+
+/*! @name DMA1REQUEST - SCT DMA request 1 register */
+#define SCT_DMA1REQUEST_DEV_1_MASK (0xFFFFU)
+#define SCT_DMA1REQUEST_DEV_1_SHIFT (0U)
+#define SCT_DMA1REQUEST_DEV_1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DEV_1_SHIFT)) & SCT_DMA1REQUEST_DEV_1_MASK)
+#define SCT_DMA1REQUEST_DRL1_MASK (0x40000000U)
+#define SCT_DMA1REQUEST_DRL1_SHIFT (30U)
+#define SCT_DMA1REQUEST_DRL1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DRL1_SHIFT)) & SCT_DMA1REQUEST_DRL1_MASK)
+#define SCT_DMA1REQUEST_DRQ1_MASK (0x80000000U)
+#define SCT_DMA1REQUEST_DRQ1_SHIFT (31U)
+#define SCT_DMA1REQUEST_DRQ1(x) (((uint32_t)(((uint32_t)(x)) << SCT_DMA1REQUEST_DRQ1_SHIFT)) & SCT_DMA1REQUEST_DRQ1_MASK)
+
+/*! @name EVEN - SCT event interrupt enable register */
+#define SCT_EVEN_IEN_MASK (0xFFFFU)
+#define SCT_EVEN_IEN_SHIFT (0U)
+#define SCT_EVEN_IEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVEN_IEN_SHIFT)) & SCT_EVEN_IEN_MASK)
+
+/*! @name EVFLAG - SCT event flag register */
+#define SCT_EVFLAG_FLAG_MASK (0xFFFFU)
+#define SCT_EVFLAG_FLAG_SHIFT (0U)
+#define SCT_EVFLAG_FLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVFLAG_FLAG_SHIFT)) & SCT_EVFLAG_FLAG_MASK)
+
+/*! @name CONEN - SCT conflict interrupt enable register */
+#define SCT_CONEN_NCEN_MASK (0xFFFFU)
+#define SCT_CONEN_NCEN_SHIFT (0U)
+#define SCT_CONEN_NCEN(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONEN_NCEN_SHIFT)) & SCT_CONEN_NCEN_MASK)
+
+/*! @name CONFLAG - SCT conflict flag register */
+#define SCT_CONFLAG_NCFLAG_MASK (0xFFFFU)
+#define SCT_CONFLAG_NCFLAG_SHIFT (0U)
+#define SCT_CONFLAG_NCFLAG(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_NCFLAG_SHIFT)) & SCT_CONFLAG_NCFLAG_MASK)
+#define SCT_CONFLAG_BUSERRL_MASK (0x40000000U)
+#define SCT_CONFLAG_BUSERRL_SHIFT (30U)
+#define SCT_CONFLAG_BUSERRL(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRL_SHIFT)) & SCT_CONFLAG_BUSERRL_MASK)
+#define SCT_CONFLAG_BUSERRH_MASK (0x80000000U)
+#define SCT_CONFLAG_BUSERRH_SHIFT (31U)
+#define SCT_CONFLAG_BUSERRH(x) (((uint32_t)(((uint32_t)(x)) << SCT_CONFLAG_BUSERRH_SHIFT)) & SCT_CONFLAG_BUSERRH_MASK)
+
+/*! @name SCTCAP - SCT capture register of capture channel */
+#define SCT_SCTCAP_CAPn_L_MASK (0xFFFFU)
+#define SCT_SCTCAP_CAPn_L_SHIFT (0U)
+#define SCT_SCTCAP_CAPn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_L_SHIFT)) & SCT_SCTCAP_CAPn_L_MASK)
+#define SCT_SCTCAP_CAPn_H_MASK (0xFFFF0000U)
+#define SCT_SCTCAP_CAPn_H_SHIFT (16U)
+#define SCT_SCTCAP_CAPn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAP_CAPn_H_SHIFT)) & SCT_SCTCAP_CAPn_H_MASK)
+
+/* The count of SCT_SCTCAP */
+#define SCT_SCTCAP_COUNT (10U)
+
+/*! @name SCTMATCH - SCT match value register of match channels */
+#define SCT_SCTMATCH_MATCHn_L_MASK (0xFFFFU)
+#define SCT_SCTMATCH_MATCHn_L_SHIFT (0U)
+#define SCT_SCTMATCH_MATCHn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_L_SHIFT)) & SCT_SCTMATCH_MATCHn_L_MASK)
+#define SCT_SCTMATCH_MATCHn_H_MASK (0xFFFF0000U)
+#define SCT_SCTMATCH_MATCHn_H_SHIFT (16U)
+#define SCT_SCTMATCH_MATCHn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCH_MATCHn_H_SHIFT)) & SCT_SCTMATCH_MATCHn_H_MASK)
+
+/* The count of SCT_SCTMATCH */
+#define SCT_SCTMATCH_COUNT (10U)
+
+/*! @name SCTCAPCTRL - SCT capture control register */
+#define SCT_SCTCAPCTRL_CAPCONn_L_MASK (0xFFFFU)
+#define SCT_SCTCAPCTRL_CAPCONn_L_SHIFT (0U)
+#define SCT_SCTCAPCTRL_CAPCONn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_L_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_L_MASK)
+#define SCT_SCTCAPCTRL_CAPCONn_H_MASK (0xFFFF0000U)
+#define SCT_SCTCAPCTRL_CAPCONn_H_SHIFT (16U)
+#define SCT_SCTCAPCTRL_CAPCONn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTCAPCTRL_CAPCONn_H_SHIFT)) & SCT_SCTCAPCTRL_CAPCONn_H_MASK)
+
+/* The count of SCT_SCTCAPCTRL */
+#define SCT_SCTCAPCTRL_COUNT (10U)
+
+/*! @name SCTMATCHREL - SCT match reload value register */
+#define SCT_SCTMATCHREL_RELOADn_L_MASK (0xFFFFU)
+#define SCT_SCTMATCHREL_RELOADn_L_SHIFT (0U)
+#define SCT_SCTMATCHREL_RELOADn_L(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_L_SHIFT)) & SCT_SCTMATCHREL_RELOADn_L_MASK)
+#define SCT_SCTMATCHREL_RELOADn_H_MASK (0xFFFF0000U)
+#define SCT_SCTMATCHREL_RELOADn_H_SHIFT (16U)
+#define SCT_SCTMATCHREL_RELOADn_H(x) (((uint32_t)(((uint32_t)(x)) << SCT_SCTMATCHREL_RELOADn_H_SHIFT)) & SCT_SCTMATCHREL_RELOADn_H_MASK)
+
+/* The count of SCT_SCTMATCHREL */
+#define SCT_SCTMATCHREL_COUNT (10U)
+
+/*! @name EVENT_STATE - SCT event state register 0 */
+#define SCT_EVENT_STATE_STATEMSKn_MASK (0xFFFFU)
+#define SCT_EVENT_STATE_STATEMSKn_SHIFT (0U)
+#define SCT_EVENT_STATE_STATEMSKn(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_STATE_STATEMSKn_SHIFT)) & SCT_EVENT_STATE_STATEMSKn_MASK)
+
+/* The count of SCT_EVENT_STATE */
+#define SCT_EVENT_STATE_COUNT (10U)
+
+/*! @name EVENT_CTRL - SCT event control register 0 */
+#define SCT_EVENT_CTRL_MATCHSEL_MASK (0xFU)
+#define SCT_EVENT_CTRL_MATCHSEL_SHIFT (0U)
+#define SCT_EVENT_CTRL_MATCHSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_MATCHSEL_SHIFT)) & SCT_EVENT_CTRL_MATCHSEL_MASK)
+#define SCT_EVENT_CTRL_HEVENT_MASK (0x10U)
+#define SCT_EVENT_CTRL_HEVENT_SHIFT (4U)
+#define SCT_EVENT_CTRL_HEVENT(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_HEVENT_SHIFT)) & SCT_EVENT_CTRL_HEVENT_MASK)
+#define SCT_EVENT_CTRL_OUTSEL_MASK (0x20U)
+#define SCT_EVENT_CTRL_OUTSEL_SHIFT (5U)
+#define SCT_EVENT_CTRL_OUTSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_OUTSEL_SHIFT)) & SCT_EVENT_CTRL_OUTSEL_MASK)
+#define SCT_EVENT_CTRL_IOSEL_MASK (0x3C0U)
+#define SCT_EVENT_CTRL_IOSEL_SHIFT (6U)
+#define SCT_EVENT_CTRL_IOSEL(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_IOSEL_SHIFT)) & SCT_EVENT_CTRL_IOSEL_MASK)
+#define SCT_EVENT_CTRL_IOCOND_MASK (0xC00U)
+#define SCT_EVENT_CTRL_IOCOND_SHIFT (10U)
+#define SCT_EVENT_CTRL_IOCOND(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_IOCOND_SHIFT)) & SCT_EVENT_CTRL_IOCOND_MASK)
+#define SCT_EVENT_CTRL_COMBMODE_MASK (0x3000U)
+#define SCT_EVENT_CTRL_COMBMODE_SHIFT (12U)
+#define SCT_EVENT_CTRL_COMBMODE(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_COMBMODE_SHIFT)) & SCT_EVENT_CTRL_COMBMODE_MASK)
+#define SCT_EVENT_CTRL_STATELD_MASK (0x4000U)
+#define SCT_EVENT_CTRL_STATELD_SHIFT (14U)
+#define SCT_EVENT_CTRL_STATELD(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_STATELD_SHIFT)) & SCT_EVENT_CTRL_STATELD_MASK)
+#define SCT_EVENT_CTRL_STATEV_MASK (0xF8000U)
+#define SCT_EVENT_CTRL_STATEV_SHIFT (15U)
+#define SCT_EVENT_CTRL_STATEV(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_STATEV_SHIFT)) & SCT_EVENT_CTRL_STATEV_MASK)
+#define SCT_EVENT_CTRL_MATCHMEM_MASK (0x100000U)
+#define SCT_EVENT_CTRL_MATCHMEM_SHIFT (20U)
+#define SCT_EVENT_CTRL_MATCHMEM(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_MATCHMEM_SHIFT)) & SCT_EVENT_CTRL_MATCHMEM_MASK)
+#define SCT_EVENT_CTRL_DIRECTION_MASK (0x600000U)
+#define SCT_EVENT_CTRL_DIRECTION_SHIFT (21U)
+#define SCT_EVENT_CTRL_DIRECTION(x) (((uint32_t)(((uint32_t)(x)) << SCT_EVENT_CTRL_DIRECTION_SHIFT)) & SCT_EVENT_CTRL_DIRECTION_MASK)
+
+/* The count of SCT_EVENT_CTRL */
+#define SCT_EVENT_CTRL_COUNT (10U)
+
+/*! @name OUT_SET - SCT output 0 set register */
+#define SCT_OUT_SET_SET_MASK (0xFFFFU)
+#define SCT_OUT_SET_SET_SHIFT (0U)
+#define SCT_OUT_SET_SET(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_SET_SET_SHIFT)) & SCT_OUT_SET_SET_MASK)
+
+/* The count of SCT_OUT_SET */
+#define SCT_OUT_SET_COUNT (10U)
+
+/*! @name OUT_CLR - SCT output 0 clear register */
+#define SCT_OUT_CLR_CLR_MASK (0xFFFFU)
+#define SCT_OUT_CLR_CLR_SHIFT (0U)
+#define SCT_OUT_CLR_CLR(x) (((uint32_t)(((uint32_t)(x)) << SCT_OUT_CLR_CLR_SHIFT)) & SCT_OUT_CLR_CLR_MASK)
+
+/* The count of SCT_OUT_CLR */
+#define SCT_OUT_CLR_COUNT (10U)
+
+
+/*!
+ * @}
+ */ /* end of group SCT_Register_Masks */
+
+
+/* SCT - Peripheral instance base addresses */
+/** Peripheral SCT0 base address */
+#define SCT0_BASE (0x40085000u)
+/** Peripheral SCT0 base pointer */
+#define SCT0 ((SCT_Type *)SCT0_BASE)
+/** Array initializer of SCT peripheral base addresses */
+#define SCT_BASE_ADDRS { SCT0_BASE }
+/** Array initializer of SCT peripheral base pointers */
+#define SCT_BASE_PTRS { SCT0 }
+/** Interrupt vectors for the SCT peripheral type */
+#define SCT_IRQS { SCT0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group SCT_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SDIF Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDIF_Peripheral_Access_Layer SDIF Peripheral Access Layer
+ * @{
+ */
+
+/** SDIF - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CTRL; /**< Control register, offset: 0x0 */
+ __IO uint32_t PWREN; /**< Power Enable register, offset: 0x4 */
+ __IO uint32_t CLKDIV; /**< Clock Divider register, offset: 0x8 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t CLKENA; /**< Clock Enable register, offset: 0x10 */
+ __IO uint32_t TMOUT; /**< Time-out register, offset: 0x14 */
+ __IO uint32_t CTYPE; /**< Card Type register, offset: 0x18 */
+ __IO uint32_t BLKSIZ; /**< Block Size register, offset: 0x1C */
+ __IO uint32_t BYTCNT; /**< Byte Count register, offset: 0x20 */
+ __IO uint32_t INTMASK; /**< Interrupt Mask register, offset: 0x24 */
+ __IO uint32_t CMDARG; /**< Command Argument register, offset: 0x28 */
+ __IO uint32_t CMD; /**< Command register, offset: 0x2C */
+ __IO uint32_t RESP[4]; /**< Response register, array offset: 0x30, array step: 0x4 */
+ __IO uint32_t MINTSTS; /**< Masked Interrupt Status register, offset: 0x40 */
+ __IO uint32_t RINTSTS; /**< Raw Interrupt Status register, offset: 0x44 */
+ __IO uint32_t STATUS; /**< Status register, offset: 0x48 */
+ __IO uint32_t FIFOTH; /**< FIFO Threshold Watermark register, offset: 0x4C */
+ __IO uint32_t CDETECT; /**< Card Detect register, offset: 0x50 */
+ __IO uint32_t WRTPRT; /**< Write Protect register, offset: 0x54 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t TCBCNT; /**< Transferred CIU Card Byte Count register, offset: 0x5C */
+ __IO uint32_t TBBCNT; /**< Transferred Host to BIU-FIFO Byte Count register, offset: 0x60 */
+ __IO uint32_t DEBNCE; /**< Debounce Count register, offset: 0x64 */
+ uint8_t RESERVED_2[16];
+ __IO uint32_t RST_N; /**< Hardware Reset, offset: 0x78 */
+ uint8_t RESERVED_3[4];
+ __IO uint32_t BMOD; /**< Bus Mode register, offset: 0x80 */
+ __IO uint32_t PLDMND; /**< Poll Demand register, offset: 0x84 */
+ __IO uint32_t DBADDR; /**< Descriptor List Base Address register, offset: 0x88 */
+ __IO uint32_t IDSTS; /**< Internal DMAC Status register, offset: 0x8C */
+ __IO uint32_t IDINTEN; /**< Internal DMAC Interrupt Enable register, offset: 0x90 */
+ __IO uint32_t DSCADDR; /**< Current Host Descriptor Address register, offset: 0x94 */
+ __IO uint32_t BUFADDR; /**< Current Buffer Descriptor Address register, offset: 0x98 */
+ uint8_t RESERVED_4[100];
+ __IO uint32_t CARDTHRCTL; /**< Card Threshold Control, offset: 0x100 */
+ __IO uint32_t BACKENDPWR; /**< Power control, offset: 0x104 */
+ uint8_t RESERVED_5[248];
+ __IO uint32_t FIFO[64]; /**< SDIF FIFO, array offset: 0x200, array step: 0x4 */
+} SDIF_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SDIF Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDIF_Register_Masks SDIF Register Masks
+ * @{
+ */
+
+/*! @name CTRL - Control register */
+#define SDIF_CTRL_CONTROLLER_RESET_MASK (0x1U)
+#define SDIF_CTRL_CONTROLLER_RESET_SHIFT (0U)
+#define SDIF_CTRL_CONTROLLER_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CONTROLLER_RESET_SHIFT)) & SDIF_CTRL_CONTROLLER_RESET_MASK)
+#define SDIF_CTRL_FIFO_RESET_MASK (0x2U)
+#define SDIF_CTRL_FIFO_RESET_SHIFT (1U)
+#define SDIF_CTRL_FIFO_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_FIFO_RESET_SHIFT)) & SDIF_CTRL_FIFO_RESET_MASK)
+#define SDIF_CTRL_DMA_RESET_MASK (0x4U)
+#define SDIF_CTRL_DMA_RESET_SHIFT (2U)
+#define SDIF_CTRL_DMA_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_DMA_RESET_SHIFT)) & SDIF_CTRL_DMA_RESET_MASK)
+#define SDIF_CTRL_INT_ENABLE_MASK (0x10U)
+#define SDIF_CTRL_INT_ENABLE_SHIFT (4U)
+#define SDIF_CTRL_INT_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_INT_ENABLE_SHIFT)) & SDIF_CTRL_INT_ENABLE_MASK)
+#define SDIF_CTRL_READ_WAIT_MASK (0x40U)
+#define SDIF_CTRL_READ_WAIT_SHIFT (6U)
+#define SDIF_CTRL_READ_WAIT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_READ_WAIT_SHIFT)) & SDIF_CTRL_READ_WAIT_MASK)
+#define SDIF_CTRL_SEND_IRQ_RESPONSE_MASK (0x80U)
+#define SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT (7U)
+#define SDIF_CTRL_SEND_IRQ_RESPONSE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_IRQ_RESPONSE_SHIFT)) & SDIF_CTRL_SEND_IRQ_RESPONSE_MASK)
+#define SDIF_CTRL_ABORT_READ_DATA_MASK (0x100U)
+#define SDIF_CTRL_ABORT_READ_DATA_SHIFT (8U)
+#define SDIF_CTRL_ABORT_READ_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_ABORT_READ_DATA_SHIFT)) & SDIF_CTRL_ABORT_READ_DATA_MASK)
+#define SDIF_CTRL_SEND_CCSD_MASK (0x200U)
+#define SDIF_CTRL_SEND_CCSD_SHIFT (9U)
+#define SDIF_CTRL_SEND_CCSD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_CCSD_SHIFT)) & SDIF_CTRL_SEND_CCSD_MASK)
+#define SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK (0x400U)
+#define SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT (10U)
+#define SDIF_CTRL_SEND_AUTO_STOP_CCSD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_SEND_AUTO_STOP_CCSD_SHIFT)) & SDIF_CTRL_SEND_AUTO_STOP_CCSD_MASK)
+#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK (0x800U)
+#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT (11U)
+#define SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_SHIFT)) & SDIF_CTRL_CEATA_DEVICE_INTERRUPT_STATUS_MASK)
+#define SDIF_CTRL_CARD_VOLTAGE_A0_MASK (0x10000U)
+#define SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT (16U)
+#define SDIF_CTRL_CARD_VOLTAGE_A0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A0_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A0_MASK)
+#define SDIF_CTRL_CARD_VOLTAGE_A1_MASK (0x20000U)
+#define SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT (17U)
+#define SDIF_CTRL_CARD_VOLTAGE_A1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A1_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A1_MASK)
+#define SDIF_CTRL_CARD_VOLTAGE_A2_MASK (0x40000U)
+#define SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT (18U)
+#define SDIF_CTRL_CARD_VOLTAGE_A2(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_CARD_VOLTAGE_A2_SHIFT)) & SDIF_CTRL_CARD_VOLTAGE_A2_MASK)
+#define SDIF_CTRL_USE_INTERNAL_DMAC_MASK (0x2000000U)
+#define SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT (25U)
+#define SDIF_CTRL_USE_INTERNAL_DMAC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTRL_USE_INTERNAL_DMAC_SHIFT)) & SDIF_CTRL_USE_INTERNAL_DMAC_MASK)
+
+/*! @name PWREN - Power Enable register */
+#define SDIF_PWREN_POWER_ENABLE_MASK (0x1U)
+#define SDIF_PWREN_POWER_ENABLE_SHIFT (0U)
+#define SDIF_PWREN_POWER_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PWREN_POWER_ENABLE_SHIFT)) & SDIF_PWREN_POWER_ENABLE_MASK)
+
+/*! @name CLKDIV - Clock Divider register */
+#define SDIF_CLKDIV_CLK_DIVIDER0_MASK (0xFFU)
+#define SDIF_CLKDIV_CLK_DIVIDER0_SHIFT (0U)
+#define SDIF_CLKDIV_CLK_DIVIDER0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKDIV_CLK_DIVIDER0_SHIFT)) & SDIF_CLKDIV_CLK_DIVIDER0_MASK)
+
+/*! @name CLKENA - Clock Enable register */
+#define SDIF_CLKENA_CCLK_ENABLE_MASK (0x1U)
+#define SDIF_CLKENA_CCLK_ENABLE_SHIFT (0U)
+#define SDIF_CLKENA_CCLK_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK_ENABLE_SHIFT)) & SDIF_CLKENA_CCLK_ENABLE_MASK)
+#define SDIF_CLKENA_CCLK_LOW_POWER_MASK (0x10000U)
+#define SDIF_CLKENA_CCLK_LOW_POWER_SHIFT (16U)
+#define SDIF_CLKENA_CCLK_LOW_POWER(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CLKENA_CCLK_LOW_POWER_SHIFT)) & SDIF_CLKENA_CCLK_LOW_POWER_MASK)
+
+/*! @name TMOUT - Time-out register */
+#define SDIF_TMOUT_RESPONSE_TIMEOUT_MASK (0xFFU)
+#define SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT (0U)
+#define SDIF_TMOUT_RESPONSE_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_RESPONSE_TIMEOUT_SHIFT)) & SDIF_TMOUT_RESPONSE_TIMEOUT_MASK)
+#define SDIF_TMOUT_DATA_TIMEOUT_MASK (0xFFFFFF00U)
+#define SDIF_TMOUT_DATA_TIMEOUT_SHIFT (8U)
+#define SDIF_TMOUT_DATA_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TMOUT_DATA_TIMEOUT_SHIFT)) & SDIF_TMOUT_DATA_TIMEOUT_MASK)
+
+/*! @name CTYPE - Card Type register */
+#define SDIF_CTYPE_CARD_WIDTH0_MASK (0x1U)
+#define SDIF_CTYPE_CARD_WIDTH0_SHIFT (0U)
+#define SDIF_CTYPE_CARD_WIDTH0(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD_WIDTH0_SHIFT)) & SDIF_CTYPE_CARD_WIDTH0_MASK)
+#define SDIF_CTYPE_CARD_WIDTH1_MASK (0x10000U)
+#define SDIF_CTYPE_CARD_WIDTH1_SHIFT (16U)
+#define SDIF_CTYPE_CARD_WIDTH1(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CTYPE_CARD_WIDTH1_SHIFT)) & SDIF_CTYPE_CARD_WIDTH1_MASK)
+
+/*! @name BLKSIZ - Block Size register */
+#define SDIF_BLKSIZ_BLOCK_SIZE_MASK (0xFFFFU)
+#define SDIF_BLKSIZ_BLOCK_SIZE_SHIFT (0U)
+#define SDIF_BLKSIZ_BLOCK_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BLKSIZ_BLOCK_SIZE_SHIFT)) & SDIF_BLKSIZ_BLOCK_SIZE_MASK)
+
+/*! @name BYTCNT - Byte Count register */
+#define SDIF_BYTCNT_BYTE_COUNT_MASK (0xFFFFFFFFU)
+#define SDIF_BYTCNT_BYTE_COUNT_SHIFT (0U)
+#define SDIF_BYTCNT_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BYTCNT_BYTE_COUNT_SHIFT)) & SDIF_BYTCNT_BYTE_COUNT_MASK)
+
+/*! @name INTMASK - Interrupt Mask register */
+#define SDIF_INTMASK_CDET_MASK (0x1U)
+#define SDIF_INTMASK_CDET_SHIFT (0U)
+#define SDIF_INTMASK_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDET_SHIFT)) & SDIF_INTMASK_CDET_MASK)
+#define SDIF_INTMASK_RE_MASK (0x2U)
+#define SDIF_INTMASK_RE_SHIFT (1U)
+#define SDIF_INTMASK_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RE_SHIFT)) & SDIF_INTMASK_RE_MASK)
+#define SDIF_INTMASK_CDONE_MASK (0x4U)
+#define SDIF_INTMASK_CDONE_SHIFT (2U)
+#define SDIF_INTMASK_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_CDONE_SHIFT)) & SDIF_INTMASK_CDONE_MASK)
+#define SDIF_INTMASK_DTO_MASK (0x8U)
+#define SDIF_INTMASK_DTO_SHIFT (3U)
+#define SDIF_INTMASK_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DTO_SHIFT)) & SDIF_INTMASK_DTO_MASK)
+#define SDIF_INTMASK_TXDR_MASK (0x10U)
+#define SDIF_INTMASK_TXDR_SHIFT (4U)
+#define SDIF_INTMASK_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_TXDR_SHIFT)) & SDIF_INTMASK_TXDR_MASK)
+#define SDIF_INTMASK_RXDR_MASK (0x20U)
+#define SDIF_INTMASK_RXDR_SHIFT (5U)
+#define SDIF_INTMASK_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RXDR_SHIFT)) & SDIF_INTMASK_RXDR_MASK)
+#define SDIF_INTMASK_RCRC_MASK (0x40U)
+#define SDIF_INTMASK_RCRC_SHIFT (6U)
+#define SDIF_INTMASK_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RCRC_SHIFT)) & SDIF_INTMASK_RCRC_MASK)
+#define SDIF_INTMASK_DCRC_MASK (0x80U)
+#define SDIF_INTMASK_DCRC_SHIFT (7U)
+#define SDIF_INTMASK_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DCRC_SHIFT)) & SDIF_INTMASK_DCRC_MASK)
+#define SDIF_INTMASK_RTO_MASK (0x100U)
+#define SDIF_INTMASK_RTO_SHIFT (8U)
+#define SDIF_INTMASK_RTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_RTO_SHIFT)) & SDIF_INTMASK_RTO_MASK)
+#define SDIF_INTMASK_DRTO_MASK (0x200U)
+#define SDIF_INTMASK_DRTO_SHIFT (9U)
+#define SDIF_INTMASK_DRTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_DRTO_SHIFT)) & SDIF_INTMASK_DRTO_MASK)
+#define SDIF_INTMASK_HTO_MASK (0x400U)
+#define SDIF_INTMASK_HTO_SHIFT (10U)
+#define SDIF_INTMASK_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HTO_SHIFT)) & SDIF_INTMASK_HTO_MASK)
+#define SDIF_INTMASK_FRUN_MASK (0x800U)
+#define SDIF_INTMASK_FRUN_SHIFT (11U)
+#define SDIF_INTMASK_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_FRUN_SHIFT)) & SDIF_INTMASK_FRUN_MASK)
+#define SDIF_INTMASK_HLE_MASK (0x1000U)
+#define SDIF_INTMASK_HLE_SHIFT (12U)
+#define SDIF_INTMASK_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_HLE_SHIFT)) & SDIF_INTMASK_HLE_MASK)
+#define SDIF_INTMASK_SBE_MASK (0x2000U)
+#define SDIF_INTMASK_SBE_SHIFT (13U)
+#define SDIF_INTMASK_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SBE_SHIFT)) & SDIF_INTMASK_SBE_MASK)
+#define SDIF_INTMASK_ACD_MASK (0x4000U)
+#define SDIF_INTMASK_ACD_SHIFT (14U)
+#define SDIF_INTMASK_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_ACD_SHIFT)) & SDIF_INTMASK_ACD_MASK)
+#define SDIF_INTMASK_EBE_MASK (0x8000U)
+#define SDIF_INTMASK_EBE_SHIFT (15U)
+#define SDIF_INTMASK_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_EBE_SHIFT)) & SDIF_INTMASK_EBE_MASK)
+#define SDIF_INTMASK_SDIO_INT_MASK_MASK (0x10000U)
+#define SDIF_INTMASK_SDIO_INT_MASK_SHIFT (16U)
+#define SDIF_INTMASK_SDIO_INT_MASK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_INTMASK_SDIO_INT_MASK_SHIFT)) & SDIF_INTMASK_SDIO_INT_MASK_MASK)
+
+/*! @name CMDARG - Command Argument register */
+#define SDIF_CMDARG_CMD_ARG_MASK (0xFFFFFFFFU)
+#define SDIF_CMDARG_CMD_ARG_SHIFT (0U)
+#define SDIF_CMDARG_CMD_ARG(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMDARG_CMD_ARG_SHIFT)) & SDIF_CMDARG_CMD_ARG_MASK)
+
+/*! @name CMD - Command register */
+#define SDIF_CMD_CMD_INDEX_MASK (0x3FU)
+#define SDIF_CMD_CMD_INDEX_SHIFT (0U)
+#define SDIF_CMD_CMD_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CMD_INDEX_SHIFT)) & SDIF_CMD_CMD_INDEX_MASK)
+#define SDIF_CMD_RESPONSE_EXPECT_MASK (0x40U)
+#define SDIF_CMD_RESPONSE_EXPECT_SHIFT (6U)
+#define SDIF_CMD_RESPONSE_EXPECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_EXPECT_SHIFT)) & SDIF_CMD_RESPONSE_EXPECT_MASK)
+#define SDIF_CMD_RESPONSE_LENGTH_MASK (0x80U)
+#define SDIF_CMD_RESPONSE_LENGTH_SHIFT (7U)
+#define SDIF_CMD_RESPONSE_LENGTH(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_RESPONSE_LENGTH_SHIFT)) & SDIF_CMD_RESPONSE_LENGTH_MASK)
+#define SDIF_CMD_CHECK_RESPONSE_CRC_MASK (0x100U)
+#define SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT (8U)
+#define SDIF_CMD_CHECK_RESPONSE_CRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CHECK_RESPONSE_CRC_SHIFT)) & SDIF_CMD_CHECK_RESPONSE_CRC_MASK)
+#define SDIF_CMD_DATA_EXPECTED_MASK (0x200U)
+#define SDIF_CMD_DATA_EXPECTED_SHIFT (9U)
+#define SDIF_CMD_DATA_EXPECTED(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DATA_EXPECTED_SHIFT)) & SDIF_CMD_DATA_EXPECTED_MASK)
+#define SDIF_CMD_READ_WRITE_MASK (0x400U)
+#define SDIF_CMD_READ_WRITE_SHIFT (10U)
+#define SDIF_CMD_READ_WRITE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_WRITE_SHIFT)) & SDIF_CMD_READ_WRITE_MASK)
+#define SDIF_CMD_TRANSFER_MODE_MASK (0x800U)
+#define SDIF_CMD_TRANSFER_MODE_SHIFT (11U)
+#define SDIF_CMD_TRANSFER_MODE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_TRANSFER_MODE_SHIFT)) & SDIF_CMD_TRANSFER_MODE_MASK)
+#define SDIF_CMD_SEND_AUTO_STOP_MASK (0x1000U)
+#define SDIF_CMD_SEND_AUTO_STOP_SHIFT (12U)
+#define SDIF_CMD_SEND_AUTO_STOP(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_AUTO_STOP_SHIFT)) & SDIF_CMD_SEND_AUTO_STOP_MASK)
+#define SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK (0x2000U)
+#define SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT (13U)
+#define SDIF_CMD_WAIT_PRVDATA_COMPLETE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_WAIT_PRVDATA_COMPLETE_SHIFT)) & SDIF_CMD_WAIT_PRVDATA_COMPLETE_MASK)
+#define SDIF_CMD_STOP_ABORT_CMD_MASK (0x4000U)
+#define SDIF_CMD_STOP_ABORT_CMD_SHIFT (14U)
+#define SDIF_CMD_STOP_ABORT_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_STOP_ABORT_CMD_SHIFT)) & SDIF_CMD_STOP_ABORT_CMD_MASK)
+#define SDIF_CMD_SEND_INITIALIZATION_MASK (0x8000U)
+#define SDIF_CMD_SEND_INITIALIZATION_SHIFT (15U)
+#define SDIF_CMD_SEND_INITIALIZATION(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_SEND_INITIALIZATION_SHIFT)) & SDIF_CMD_SEND_INITIALIZATION_MASK)
+#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK (0x200000U)
+#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT (21U)
+#define SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_SHIFT)) & SDIF_CMD_UPDATE_CLOCK_REGISTERS_ONLY_MASK)
+#define SDIF_CMD_READ_CEATA_DEVICE_MASK (0x400000U)
+#define SDIF_CMD_READ_CEATA_DEVICE_SHIFT (22U)
+#define SDIF_CMD_READ_CEATA_DEVICE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_READ_CEATA_DEVICE_SHIFT)) & SDIF_CMD_READ_CEATA_DEVICE_MASK)
+#define SDIF_CMD_CCS_EXPECTED_MASK (0x800000U)
+#define SDIF_CMD_CCS_EXPECTED_SHIFT (23U)
+#define SDIF_CMD_CCS_EXPECTED(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_CCS_EXPECTED_SHIFT)) & SDIF_CMD_CCS_EXPECTED_MASK)
+#define SDIF_CMD_ENABLE_BOOT_MASK (0x1000000U)
+#define SDIF_CMD_ENABLE_BOOT_SHIFT (24U)
+#define SDIF_CMD_ENABLE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_ENABLE_BOOT_SHIFT)) & SDIF_CMD_ENABLE_BOOT_MASK)
+#define SDIF_CMD_EXPECT_BOOT_ACK_MASK (0x2000000U)
+#define SDIF_CMD_EXPECT_BOOT_ACK_SHIFT (25U)
+#define SDIF_CMD_EXPECT_BOOT_ACK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_EXPECT_BOOT_ACK_SHIFT)) & SDIF_CMD_EXPECT_BOOT_ACK_MASK)
+#define SDIF_CMD_DISABLE_BOOT_MASK (0x4000000U)
+#define SDIF_CMD_DISABLE_BOOT_SHIFT (26U)
+#define SDIF_CMD_DISABLE_BOOT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_DISABLE_BOOT_SHIFT)) & SDIF_CMD_DISABLE_BOOT_MASK)
+#define SDIF_CMD_BOOT_MODE_MASK (0x8000000U)
+#define SDIF_CMD_BOOT_MODE_SHIFT (27U)
+#define SDIF_CMD_BOOT_MODE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_BOOT_MODE_SHIFT)) & SDIF_CMD_BOOT_MODE_MASK)
+#define SDIF_CMD_VOLT_SWITCH_MASK (0x10000000U)
+#define SDIF_CMD_VOLT_SWITCH_SHIFT (28U)
+#define SDIF_CMD_VOLT_SWITCH(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_VOLT_SWITCH_SHIFT)) & SDIF_CMD_VOLT_SWITCH_MASK)
+#define SDIF_CMD_USE_HOLD_REG_MASK (0x20000000U)
+#define SDIF_CMD_USE_HOLD_REG_SHIFT (29U)
+#define SDIF_CMD_USE_HOLD_REG(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_USE_HOLD_REG_SHIFT)) & SDIF_CMD_USE_HOLD_REG_MASK)
+#define SDIF_CMD_START_CMD_MASK (0x80000000U)
+#define SDIF_CMD_START_CMD_SHIFT (31U)
+#define SDIF_CMD_START_CMD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CMD_START_CMD_SHIFT)) & SDIF_CMD_START_CMD_MASK)
+
+/*! @name RESP - Response register */
+#define SDIF_RESP_RESPONSE_MASK (0xFFFFFFFFU)
+#define SDIF_RESP_RESPONSE_SHIFT (0U)
+#define SDIF_RESP_RESPONSE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RESP_RESPONSE_SHIFT)) & SDIF_RESP_RESPONSE_MASK)
+
+/* The count of SDIF_RESP */
+#define SDIF_RESP_COUNT (4U)
+
+/*! @name MINTSTS - Masked Interrupt Status register */
+#define SDIF_MINTSTS_CDET_MASK (0x1U)
+#define SDIF_MINTSTS_CDET_SHIFT (0U)
+#define SDIF_MINTSTS_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDET_SHIFT)) & SDIF_MINTSTS_CDET_MASK)
+#define SDIF_MINTSTS_RE_MASK (0x2U)
+#define SDIF_MINTSTS_RE_SHIFT (1U)
+#define SDIF_MINTSTS_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RE_SHIFT)) & SDIF_MINTSTS_RE_MASK)
+#define SDIF_MINTSTS_CDONE_MASK (0x4U)
+#define SDIF_MINTSTS_CDONE_SHIFT (2U)
+#define SDIF_MINTSTS_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_CDONE_SHIFT)) & SDIF_MINTSTS_CDONE_MASK)
+#define SDIF_MINTSTS_DTO_MASK (0x8U)
+#define SDIF_MINTSTS_DTO_SHIFT (3U)
+#define SDIF_MINTSTS_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DTO_SHIFT)) & SDIF_MINTSTS_DTO_MASK)
+#define SDIF_MINTSTS_TXDR_MASK (0x10U)
+#define SDIF_MINTSTS_TXDR_SHIFT (4U)
+#define SDIF_MINTSTS_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_TXDR_SHIFT)) & SDIF_MINTSTS_TXDR_MASK)
+#define SDIF_MINTSTS_RXDR_MASK (0x20U)
+#define SDIF_MINTSTS_RXDR_SHIFT (5U)
+#define SDIF_MINTSTS_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RXDR_SHIFT)) & SDIF_MINTSTS_RXDR_MASK)
+#define SDIF_MINTSTS_RCRC_MASK (0x40U)
+#define SDIF_MINTSTS_RCRC_SHIFT (6U)
+#define SDIF_MINTSTS_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RCRC_SHIFT)) & SDIF_MINTSTS_RCRC_MASK)
+#define SDIF_MINTSTS_DCRC_MASK (0x80U)
+#define SDIF_MINTSTS_DCRC_SHIFT (7U)
+#define SDIF_MINTSTS_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DCRC_SHIFT)) & SDIF_MINTSTS_DCRC_MASK)
+#define SDIF_MINTSTS_RTO_MASK (0x100U)
+#define SDIF_MINTSTS_RTO_SHIFT (8U)
+#define SDIF_MINTSTS_RTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_RTO_SHIFT)) & SDIF_MINTSTS_RTO_MASK)
+#define SDIF_MINTSTS_DRTO_MASK (0x200U)
+#define SDIF_MINTSTS_DRTO_SHIFT (9U)
+#define SDIF_MINTSTS_DRTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_DRTO_SHIFT)) & SDIF_MINTSTS_DRTO_MASK)
+#define SDIF_MINTSTS_HTO_MASK (0x400U)
+#define SDIF_MINTSTS_HTO_SHIFT (10U)
+#define SDIF_MINTSTS_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HTO_SHIFT)) & SDIF_MINTSTS_HTO_MASK)
+#define SDIF_MINTSTS_FRUN_MASK (0x800U)
+#define SDIF_MINTSTS_FRUN_SHIFT (11U)
+#define SDIF_MINTSTS_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_FRUN_SHIFT)) & SDIF_MINTSTS_FRUN_MASK)
+#define SDIF_MINTSTS_HLE_MASK (0x1000U)
+#define SDIF_MINTSTS_HLE_SHIFT (12U)
+#define SDIF_MINTSTS_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_HLE_SHIFT)) & SDIF_MINTSTS_HLE_MASK)
+#define SDIF_MINTSTS_SBE_MASK (0x2000U)
+#define SDIF_MINTSTS_SBE_SHIFT (13U)
+#define SDIF_MINTSTS_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SBE_SHIFT)) & SDIF_MINTSTS_SBE_MASK)
+#define SDIF_MINTSTS_ACD_MASK (0x4000U)
+#define SDIF_MINTSTS_ACD_SHIFT (14U)
+#define SDIF_MINTSTS_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_ACD_SHIFT)) & SDIF_MINTSTS_ACD_MASK)
+#define SDIF_MINTSTS_EBE_MASK (0x8000U)
+#define SDIF_MINTSTS_EBE_SHIFT (15U)
+#define SDIF_MINTSTS_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_EBE_SHIFT)) & SDIF_MINTSTS_EBE_MASK)
+#define SDIF_MINTSTS_SDIO_INTERRUPT_MASK (0x10000U)
+#define SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT (16U)
+#define SDIF_MINTSTS_SDIO_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_MINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_MINTSTS_SDIO_INTERRUPT_MASK)
+
+/*! @name RINTSTS - Raw Interrupt Status register */
+#define SDIF_RINTSTS_CDET_MASK (0x1U)
+#define SDIF_RINTSTS_CDET_SHIFT (0U)
+#define SDIF_RINTSTS_CDET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDET_SHIFT)) & SDIF_RINTSTS_CDET_MASK)
+#define SDIF_RINTSTS_RE_MASK (0x2U)
+#define SDIF_RINTSTS_RE_SHIFT (1U)
+#define SDIF_RINTSTS_RE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RE_SHIFT)) & SDIF_RINTSTS_RE_MASK)
+#define SDIF_RINTSTS_CDONE_MASK (0x4U)
+#define SDIF_RINTSTS_CDONE_SHIFT (2U)
+#define SDIF_RINTSTS_CDONE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_CDONE_SHIFT)) & SDIF_RINTSTS_CDONE_MASK)
+#define SDIF_RINTSTS_DTO_MASK (0x8U)
+#define SDIF_RINTSTS_DTO_SHIFT (3U)
+#define SDIF_RINTSTS_DTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DTO_SHIFT)) & SDIF_RINTSTS_DTO_MASK)
+#define SDIF_RINTSTS_TXDR_MASK (0x10U)
+#define SDIF_RINTSTS_TXDR_SHIFT (4U)
+#define SDIF_RINTSTS_TXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_TXDR_SHIFT)) & SDIF_RINTSTS_TXDR_MASK)
+#define SDIF_RINTSTS_RXDR_MASK (0x20U)
+#define SDIF_RINTSTS_RXDR_SHIFT (5U)
+#define SDIF_RINTSTS_RXDR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RXDR_SHIFT)) & SDIF_RINTSTS_RXDR_MASK)
+#define SDIF_RINTSTS_RCRC_MASK (0x40U)
+#define SDIF_RINTSTS_RCRC_SHIFT (6U)
+#define SDIF_RINTSTS_RCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RCRC_SHIFT)) & SDIF_RINTSTS_RCRC_MASK)
+#define SDIF_RINTSTS_DCRC_MASK (0x80U)
+#define SDIF_RINTSTS_DCRC_SHIFT (7U)
+#define SDIF_RINTSTS_DCRC(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DCRC_SHIFT)) & SDIF_RINTSTS_DCRC_MASK)
+#define SDIF_RINTSTS_RTO_BAR_MASK (0x100U)
+#define SDIF_RINTSTS_RTO_BAR_SHIFT (8U)
+#define SDIF_RINTSTS_RTO_BAR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_RTO_BAR_SHIFT)) & SDIF_RINTSTS_RTO_BAR_MASK)
+#define SDIF_RINTSTS_DRTO_BDS_MASK (0x200U)
+#define SDIF_RINTSTS_DRTO_BDS_SHIFT (9U)
+#define SDIF_RINTSTS_DRTO_BDS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_DRTO_BDS_SHIFT)) & SDIF_RINTSTS_DRTO_BDS_MASK)
+#define SDIF_RINTSTS_HTO_MASK (0x400U)
+#define SDIF_RINTSTS_HTO_SHIFT (10U)
+#define SDIF_RINTSTS_HTO(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HTO_SHIFT)) & SDIF_RINTSTS_HTO_MASK)
+#define SDIF_RINTSTS_FRUN_MASK (0x800U)
+#define SDIF_RINTSTS_FRUN_SHIFT (11U)
+#define SDIF_RINTSTS_FRUN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_FRUN_SHIFT)) & SDIF_RINTSTS_FRUN_MASK)
+#define SDIF_RINTSTS_HLE_MASK (0x1000U)
+#define SDIF_RINTSTS_HLE_SHIFT (12U)
+#define SDIF_RINTSTS_HLE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_HLE_SHIFT)) & SDIF_RINTSTS_HLE_MASK)
+#define SDIF_RINTSTS_SBE_MASK (0x2000U)
+#define SDIF_RINTSTS_SBE_SHIFT (13U)
+#define SDIF_RINTSTS_SBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SBE_SHIFT)) & SDIF_RINTSTS_SBE_MASK)
+#define SDIF_RINTSTS_ACD_MASK (0x4000U)
+#define SDIF_RINTSTS_ACD_SHIFT (14U)
+#define SDIF_RINTSTS_ACD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_ACD_SHIFT)) & SDIF_RINTSTS_ACD_MASK)
+#define SDIF_RINTSTS_EBE_MASK (0x8000U)
+#define SDIF_RINTSTS_EBE_SHIFT (15U)
+#define SDIF_RINTSTS_EBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_EBE_SHIFT)) & SDIF_RINTSTS_EBE_MASK)
+#define SDIF_RINTSTS_SDIO_INTERRUPT_MASK (0x10000U)
+#define SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT (16U)
+#define SDIF_RINTSTS_SDIO_INTERRUPT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RINTSTS_SDIO_INTERRUPT_SHIFT)) & SDIF_RINTSTS_SDIO_INTERRUPT_MASK)
+
+/*! @name STATUS - Status register */
+#define SDIF_STATUS_FIFO_RX_WATERMARK_MASK (0x1U)
+#define SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT (0U)
+#define SDIF_STATUS_FIFO_RX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_RX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_RX_WATERMARK_MASK)
+#define SDIF_STATUS_FIFO_TX_WATERMARK_MASK (0x2U)
+#define SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT (1U)
+#define SDIF_STATUS_FIFO_TX_WATERMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_TX_WATERMARK_SHIFT)) & SDIF_STATUS_FIFO_TX_WATERMARK_MASK)
+#define SDIF_STATUS_FIFO_EMPTY_MASK (0x4U)
+#define SDIF_STATUS_FIFO_EMPTY_SHIFT (2U)
+#define SDIF_STATUS_FIFO_EMPTY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_EMPTY_SHIFT)) & SDIF_STATUS_FIFO_EMPTY_MASK)
+#define SDIF_STATUS_FIFO_FULL_MASK (0x8U)
+#define SDIF_STATUS_FIFO_FULL_SHIFT (3U)
+#define SDIF_STATUS_FIFO_FULL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_FULL_SHIFT)) & SDIF_STATUS_FIFO_FULL_MASK)
+#define SDIF_STATUS_CMDFSMSTATES_MASK (0xF0U)
+#define SDIF_STATUS_CMDFSMSTATES_SHIFT (4U)
+#define SDIF_STATUS_CMDFSMSTATES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_CMDFSMSTATES_SHIFT)) & SDIF_STATUS_CMDFSMSTATES_MASK)
+#define SDIF_STATUS_DATA_3_STATUS_MASK (0x100U)
+#define SDIF_STATUS_DATA_3_STATUS_SHIFT (8U)
+#define SDIF_STATUS_DATA_3_STATUS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_3_STATUS_SHIFT)) & SDIF_STATUS_DATA_3_STATUS_MASK)
+#define SDIF_STATUS_DATA_BUSY_MASK (0x200U)
+#define SDIF_STATUS_DATA_BUSY_SHIFT (9U)
+#define SDIF_STATUS_DATA_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_BUSY_SHIFT)) & SDIF_STATUS_DATA_BUSY_MASK)
+#define SDIF_STATUS_DATA_STATE_MC_BUSY_MASK (0x400U)
+#define SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT (10U)
+#define SDIF_STATUS_DATA_STATE_MC_BUSY(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DATA_STATE_MC_BUSY_SHIFT)) & SDIF_STATUS_DATA_STATE_MC_BUSY_MASK)
+#define SDIF_STATUS_RESPONSE_INDEX_MASK (0x1F800U)
+#define SDIF_STATUS_RESPONSE_INDEX_SHIFT (11U)
+#define SDIF_STATUS_RESPONSE_INDEX(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_RESPONSE_INDEX_SHIFT)) & SDIF_STATUS_RESPONSE_INDEX_MASK)
+#define SDIF_STATUS_FIFO_COUNT_MASK (0x3FFE0000U)
+#define SDIF_STATUS_FIFO_COUNT_SHIFT (17U)
+#define SDIF_STATUS_FIFO_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_FIFO_COUNT_SHIFT)) & SDIF_STATUS_FIFO_COUNT_MASK)
+#define SDIF_STATUS_DMA_ACK_MASK (0x40000000U)
+#define SDIF_STATUS_DMA_ACK_SHIFT (30U)
+#define SDIF_STATUS_DMA_ACK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_ACK_SHIFT)) & SDIF_STATUS_DMA_ACK_MASK)
+#define SDIF_STATUS_DMA_REQ_MASK (0x80000000U)
+#define SDIF_STATUS_DMA_REQ_SHIFT (31U)
+#define SDIF_STATUS_DMA_REQ(x) (((uint32_t)(((uint32_t)(x)) << SDIF_STATUS_DMA_REQ_SHIFT)) & SDIF_STATUS_DMA_REQ_MASK)
+
+/*! @name FIFOTH - FIFO Threshold Watermark register */
+#define SDIF_FIFOTH_TX_WMARK_MASK (0xFFFU)
+#define SDIF_FIFOTH_TX_WMARK_SHIFT (0U)
+#define SDIF_FIFOTH_TX_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_TX_WMARK_SHIFT)) & SDIF_FIFOTH_TX_WMARK_MASK)
+#define SDIF_FIFOTH_RX_WMARK_MASK (0xFFF0000U)
+#define SDIF_FIFOTH_RX_WMARK_SHIFT (16U)
+#define SDIF_FIFOTH_RX_WMARK(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_RX_WMARK_SHIFT)) & SDIF_FIFOTH_RX_WMARK_MASK)
+#define SDIF_FIFOTH_DMA_MTS_MASK (0x70000000U)
+#define SDIF_FIFOTH_DMA_MTS_SHIFT (28U)
+#define SDIF_FIFOTH_DMA_MTS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFOTH_DMA_MTS_SHIFT)) & SDIF_FIFOTH_DMA_MTS_MASK)
+
+/*! @name CDETECT - Card Detect register */
+#define SDIF_CDETECT_CARD_DETECT_MASK (0x1U)
+#define SDIF_CDETECT_CARD_DETECT_SHIFT (0U)
+#define SDIF_CDETECT_CARD_DETECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CDETECT_CARD_DETECT_SHIFT)) & SDIF_CDETECT_CARD_DETECT_MASK)
+
+/*! @name WRTPRT - Write Protect register */
+#define SDIF_WRTPRT_WRITE_PROTECT_MASK (0x1U)
+#define SDIF_WRTPRT_WRITE_PROTECT_SHIFT (0U)
+#define SDIF_WRTPRT_WRITE_PROTECT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_WRTPRT_WRITE_PROTECT_SHIFT)) & SDIF_WRTPRT_WRITE_PROTECT_MASK)
+
+/*! @name TCBCNT - Transferred CIU Card Byte Count register */
+#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK (0xFFFFFFFFU)
+#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT (0U)
+#define SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_SHIFT)) & SDIF_TCBCNT_TRANS_CARD_BYTE_COUNT_MASK)
+
+/*! @name TBBCNT - Transferred Host to BIU-FIFO Byte Count register */
+#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK (0xFFFFFFFFU)
+#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT (0U)
+#define SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_SHIFT)) & SDIF_TBBCNT_TRANS_FIFO_BYTE_COUNT_MASK)
+
+/*! @name DEBNCE - Debounce Count register */
+#define SDIF_DEBNCE_DEBOUNCE_COUNT_MASK (0xFFFFFFU)
+#define SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT (0U)
+#define SDIF_DEBNCE_DEBOUNCE_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DEBNCE_DEBOUNCE_COUNT_SHIFT)) & SDIF_DEBNCE_DEBOUNCE_COUNT_MASK)
+
+/*! @name RST_N - Hardware Reset */
+#define SDIF_RST_N_CARD_RESET_MASK (0x1U)
+#define SDIF_RST_N_CARD_RESET_SHIFT (0U)
+#define SDIF_RST_N_CARD_RESET(x) (((uint32_t)(((uint32_t)(x)) << SDIF_RST_N_CARD_RESET_SHIFT)) & SDIF_RST_N_CARD_RESET_MASK)
+
+/*! @name BMOD - Bus Mode register */
+#define SDIF_BMOD_SWR_MASK (0x1U)
+#define SDIF_BMOD_SWR_SHIFT (0U)
+#define SDIF_BMOD_SWR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_SWR_SHIFT)) & SDIF_BMOD_SWR_MASK)
+#define SDIF_BMOD_FB_MASK (0x2U)
+#define SDIF_BMOD_FB_SHIFT (1U)
+#define SDIF_BMOD_FB(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_FB_SHIFT)) & SDIF_BMOD_FB_MASK)
+#define SDIF_BMOD_DSL_MASK (0x7CU)
+#define SDIF_BMOD_DSL_SHIFT (2U)
+#define SDIF_BMOD_DSL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DSL_SHIFT)) & SDIF_BMOD_DSL_MASK)
+#define SDIF_BMOD_DE_MASK (0x80U)
+#define SDIF_BMOD_DE_SHIFT (7U)
+#define SDIF_BMOD_DE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_DE_SHIFT)) & SDIF_BMOD_DE_MASK)
+#define SDIF_BMOD_PBL_MASK (0x700U)
+#define SDIF_BMOD_PBL_SHIFT (8U)
+#define SDIF_BMOD_PBL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BMOD_PBL_SHIFT)) & SDIF_BMOD_PBL_MASK)
+
+/*! @name PLDMND - Poll Demand register */
+#define SDIF_PLDMND_PD_MASK (0xFFFFFFFFU)
+#define SDIF_PLDMND_PD_SHIFT (0U)
+#define SDIF_PLDMND_PD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_PLDMND_PD_SHIFT)) & SDIF_PLDMND_PD_MASK)
+
+/*! @name DBADDR - Descriptor List Base Address register */
+#define SDIF_DBADDR_SDL_MASK (0xFFFFFFFFU)
+#define SDIF_DBADDR_SDL_SHIFT (0U)
+#define SDIF_DBADDR_SDL(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DBADDR_SDL_SHIFT)) & SDIF_DBADDR_SDL_MASK)
+
+/*! @name IDSTS - Internal DMAC Status register */
+#define SDIF_IDSTS_TI_MASK (0x1U)
+#define SDIF_IDSTS_TI_SHIFT (0U)
+#define SDIF_IDSTS_TI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_TI_SHIFT)) & SDIF_IDSTS_TI_MASK)
+#define SDIF_IDSTS_RI_MASK (0x2U)
+#define SDIF_IDSTS_RI_SHIFT (1U)
+#define SDIF_IDSTS_RI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_RI_SHIFT)) & SDIF_IDSTS_RI_MASK)
+#define SDIF_IDSTS_FBE_MASK (0x4U)
+#define SDIF_IDSTS_FBE_SHIFT (2U)
+#define SDIF_IDSTS_FBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FBE_SHIFT)) & SDIF_IDSTS_FBE_MASK)
+#define SDIF_IDSTS_DU_MASK (0x10U)
+#define SDIF_IDSTS_DU_SHIFT (4U)
+#define SDIF_IDSTS_DU(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_DU_SHIFT)) & SDIF_IDSTS_DU_MASK)
+#define SDIF_IDSTS_CES_MASK (0x20U)
+#define SDIF_IDSTS_CES_SHIFT (5U)
+#define SDIF_IDSTS_CES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_CES_SHIFT)) & SDIF_IDSTS_CES_MASK)
+#define SDIF_IDSTS_NIS_MASK (0x100U)
+#define SDIF_IDSTS_NIS_SHIFT (8U)
+#define SDIF_IDSTS_NIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_NIS_SHIFT)) & SDIF_IDSTS_NIS_MASK)
+#define SDIF_IDSTS_AIS_MASK (0x200U)
+#define SDIF_IDSTS_AIS_SHIFT (9U)
+#define SDIF_IDSTS_AIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_AIS_SHIFT)) & SDIF_IDSTS_AIS_MASK)
+#define SDIF_IDSTS_EB_MASK (0x1C00U)
+#define SDIF_IDSTS_EB_SHIFT (10U)
+#define SDIF_IDSTS_EB(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_EB_SHIFT)) & SDIF_IDSTS_EB_MASK)
+#define SDIF_IDSTS_FSM_MASK (0x1E000U)
+#define SDIF_IDSTS_FSM_SHIFT (13U)
+#define SDIF_IDSTS_FSM(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDSTS_FSM_SHIFT)) & SDIF_IDSTS_FSM_MASK)
+
+/*! @name IDINTEN - Internal DMAC Interrupt Enable register */
+#define SDIF_IDINTEN_TI_MASK (0x1U)
+#define SDIF_IDINTEN_TI_SHIFT (0U)
+#define SDIF_IDINTEN_TI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_TI_SHIFT)) & SDIF_IDINTEN_TI_MASK)
+#define SDIF_IDINTEN_RI_MASK (0x2U)
+#define SDIF_IDINTEN_RI_SHIFT (1U)
+#define SDIF_IDINTEN_RI(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_RI_SHIFT)) & SDIF_IDINTEN_RI_MASK)
+#define SDIF_IDINTEN_FBE_MASK (0x4U)
+#define SDIF_IDINTEN_FBE_SHIFT (2U)
+#define SDIF_IDINTEN_FBE(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_FBE_SHIFT)) & SDIF_IDINTEN_FBE_MASK)
+#define SDIF_IDINTEN_DU_MASK (0x10U)
+#define SDIF_IDINTEN_DU_SHIFT (4U)
+#define SDIF_IDINTEN_DU(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_DU_SHIFT)) & SDIF_IDINTEN_DU_MASK)
+#define SDIF_IDINTEN_CES_MASK (0x20U)
+#define SDIF_IDINTEN_CES_SHIFT (5U)
+#define SDIF_IDINTEN_CES(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_CES_SHIFT)) & SDIF_IDINTEN_CES_MASK)
+#define SDIF_IDINTEN_NIS_MASK (0x100U)
+#define SDIF_IDINTEN_NIS_SHIFT (8U)
+#define SDIF_IDINTEN_NIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_NIS_SHIFT)) & SDIF_IDINTEN_NIS_MASK)
+#define SDIF_IDINTEN_AIS_MASK (0x200U)
+#define SDIF_IDINTEN_AIS_SHIFT (9U)
+#define SDIF_IDINTEN_AIS(x) (((uint32_t)(((uint32_t)(x)) << SDIF_IDINTEN_AIS_SHIFT)) & SDIF_IDINTEN_AIS_MASK)
+
+/*! @name DSCADDR - Current Host Descriptor Address register */
+#define SDIF_DSCADDR_HDA_MASK (0xFFFFFFFFU)
+#define SDIF_DSCADDR_HDA_SHIFT (0U)
+#define SDIF_DSCADDR_HDA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_DSCADDR_HDA_SHIFT)) & SDIF_DSCADDR_HDA_MASK)
+
+/*! @name BUFADDR - Current Buffer Descriptor Address register */
+#define SDIF_BUFADDR_HBA_MASK (0xFFFFFFFFU)
+#define SDIF_BUFADDR_HBA_SHIFT (0U)
+#define SDIF_BUFADDR_HBA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BUFADDR_HBA_SHIFT)) & SDIF_BUFADDR_HBA_MASK)
+
+/*! @name CARDTHRCTL - Card Threshold Control */
+#define SDIF_CARDTHRCTL_CARDRDTHREN_MASK (0x1U)
+#define SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT (0U)
+#define SDIF_CARDTHRCTL_CARDRDTHREN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDRDTHREN_SHIFT)) & SDIF_CARDTHRCTL_CARDRDTHREN_MASK)
+#define SDIF_CARDTHRCTL_BSYCLRINTEN_MASK (0x2U)
+#define SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT (1U)
+#define SDIF_CARDTHRCTL_BSYCLRINTEN(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_BSYCLRINTEN_SHIFT)) & SDIF_CARDTHRCTL_BSYCLRINTEN_MASK)
+#define SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK (0xFF0000U)
+#define SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT (16U)
+#define SDIF_CARDTHRCTL_CARDTHRESHOLD(x) (((uint32_t)(((uint32_t)(x)) << SDIF_CARDTHRCTL_CARDTHRESHOLD_SHIFT)) & SDIF_CARDTHRCTL_CARDTHRESHOLD_MASK)
+
+/*! @name BACKENDPWR - Power control */
+#define SDIF_BACKENDPWR_BACKENDPWR_MASK (0x1U)
+#define SDIF_BACKENDPWR_BACKENDPWR_SHIFT (0U)
+#define SDIF_BACKENDPWR_BACKENDPWR(x) (((uint32_t)(((uint32_t)(x)) << SDIF_BACKENDPWR_BACKENDPWR_SHIFT)) & SDIF_BACKENDPWR_BACKENDPWR_MASK)
+
+/*! @name FIFO - SDIF FIFO */
+#define SDIF_FIFO_DATA_MASK (0xFFFFFFFFU)
+#define SDIF_FIFO_DATA_SHIFT (0U)
+#define SDIF_FIFO_DATA(x) (((uint32_t)(((uint32_t)(x)) << SDIF_FIFO_DATA_SHIFT)) & SDIF_FIFO_DATA_MASK)
+
+/* The count of SDIF_FIFO */
+#define SDIF_FIFO_COUNT (64U)
+
+
+/*!
+ * @}
+ */ /* end of group SDIF_Register_Masks */
+
+
+/* SDIF - Peripheral instance base addresses */
+/** Peripheral SDIF base address */
+#define SDIF_BASE (0x4009B000u)
+/** Peripheral SDIF base pointer */
+#define SDIF ((SDIF_Type *)SDIF_BASE)
+/** Array initializer of SDIF peripheral base addresses */
+#define SDIF_BASE_ADDRS { SDIF_BASE }
+/** Array initializer of SDIF peripheral base pointers */
+#define SDIF_BASE_PTRS { SDIF }
+/** Interrupt vectors for the SDIF peripheral type */
+#define SDIF_IRQS { SDIO_IRQn }
+
+/*!
+ * @}
+ */ /* end of group SDIF_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SHA Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SHA_Peripheral_Access_Layer SHA Peripheral Access Layer
+ * @{
+ */
+
+/** SHA - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CTRL; /**< Control register, offset: 0x0 */
+ __IO uint32_t STATUS; /**< Status register, offset: 0x4 */
+ __IO uint32_t INTENSET; /**< Interrupt Enable register, offset: 0x8 */
+ __IO uint32_t INTENCLR; /**< Interrupt Clear register, offset: 0xC */
+ __IO uint32_t MEMCTRL; /**< Memory Control register, offset: 0x10 */
+ __IO uint32_t MEMADDR; /**< Memory Address register, offset: 0x14 */
+ uint8_t RESERVED_0[8];
+ __IO uint32_t INDATA; /**< Input Data register, offset: 0x20 */
+ __IO uint32_t ALIAS[7]; /**< Alias register, array offset: 0x24, array step: 0x4 */
+ __I uint32_t DIGEST[8]; /**< Digest register, array offset: 0x40, array step: 0x4 */
+} SHA_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SHA Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SHA_Register_Masks SHA Register Masks
+ * @{
+ */
+
+/*! @name CTRL - Control register */
+#define SHA_CTRL_MODE_MASK (0x3U)
+#define SHA_CTRL_MODE_SHIFT (0U)
+#define SHA_CTRL_MODE(x) (((uint32_t)(((uint32_t)(x)) << SHA_CTRL_MODE_SHIFT)) & SHA_CTRL_MODE_MASK)
+#define SHA_CTRL_NEW_MASK (0x10U)
+#define SHA_CTRL_NEW_SHIFT (4U)
+#define SHA_CTRL_NEW(x) (((uint32_t)(((uint32_t)(x)) << SHA_CTRL_NEW_SHIFT)) & SHA_CTRL_NEW_MASK)
+#define SHA_CTRL_DMA_MASK (0x100U)
+#define SHA_CTRL_DMA_SHIFT (8U)
+#define SHA_CTRL_DMA(x) (((uint32_t)(((uint32_t)(x)) << SHA_CTRL_DMA_SHIFT)) & SHA_CTRL_DMA_MASK)
+
+/*! @name STATUS - Status register */
+#define SHA_STATUS_WAITING_MASK (0x1U)
+#define SHA_STATUS_WAITING_SHIFT (0U)
+#define SHA_STATUS_WAITING(x) (((uint32_t)(((uint32_t)(x)) << SHA_STATUS_WAITING_SHIFT)) & SHA_STATUS_WAITING_MASK)
+#define SHA_STATUS_DIGEST_MASK (0x2U)
+#define SHA_STATUS_DIGEST_SHIFT (1U)
+#define SHA_STATUS_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << SHA_STATUS_DIGEST_SHIFT)) & SHA_STATUS_DIGEST_MASK)
+#define SHA_STATUS_ERROR_MASK (0x4U)
+#define SHA_STATUS_ERROR_SHIFT (2U)
+#define SHA_STATUS_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SHA_STATUS_ERROR_SHIFT)) & SHA_STATUS_ERROR_MASK)
+
+/*! @name INTENSET - Interrupt Enable register */
+#define SHA_INTENSET_WAITING_MASK (0x1U)
+#define SHA_INTENSET_WAITING_SHIFT (0U)
+#define SHA_INTENSET_WAITING(x) (((uint32_t)(((uint32_t)(x)) << SHA_INTENSET_WAITING_SHIFT)) & SHA_INTENSET_WAITING_MASK)
+#define SHA_INTENSET_DIGEST_MASK (0x2U)
+#define SHA_INTENSET_DIGEST_SHIFT (1U)
+#define SHA_INTENSET_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << SHA_INTENSET_DIGEST_SHIFT)) & SHA_INTENSET_DIGEST_MASK)
+#define SHA_INTENSET_ERROR_MASK (0x4U)
+#define SHA_INTENSET_ERROR_SHIFT (2U)
+#define SHA_INTENSET_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SHA_INTENSET_ERROR_SHIFT)) & SHA_INTENSET_ERROR_MASK)
+
+/*! @name INTENCLR - Interrupt Clear register */
+#define SHA_INTENCLR_WAITING_MASK (0x1U)
+#define SHA_INTENCLR_WAITING_SHIFT (0U)
+#define SHA_INTENCLR_WAITING(x) (((uint32_t)(((uint32_t)(x)) << SHA_INTENCLR_WAITING_SHIFT)) & SHA_INTENCLR_WAITING_MASK)
+#define SHA_INTENCLR_DIGEST_MASK (0x2U)
+#define SHA_INTENCLR_DIGEST_SHIFT (1U)
+#define SHA_INTENCLR_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << SHA_INTENCLR_DIGEST_SHIFT)) & SHA_INTENCLR_DIGEST_MASK)
+#define SHA_INTENCLR_ERROR_MASK (0x4U)
+#define SHA_INTENCLR_ERROR_SHIFT (2U)
+#define SHA_INTENCLR_ERROR(x) (((uint32_t)(((uint32_t)(x)) << SHA_INTENCLR_ERROR_SHIFT)) & SHA_INTENCLR_ERROR_MASK)
+
+/*! @name MEMCTRL - Memory Control register */
+#define SHA_MEMCTRL_MASTER_MASK (0x1U)
+#define SHA_MEMCTRL_MASTER_SHIFT (0U)
+#define SHA_MEMCTRL_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SHA_MEMCTRL_MASTER_SHIFT)) & SHA_MEMCTRL_MASTER_MASK)
+#define SHA_MEMCTRL_COUNT_MASK (0x7FF0000U)
+#define SHA_MEMCTRL_COUNT_SHIFT (16U)
+#define SHA_MEMCTRL_COUNT(x) (((uint32_t)(((uint32_t)(x)) << SHA_MEMCTRL_COUNT_SHIFT)) & SHA_MEMCTRL_COUNT_MASK)
+
+/*! @name MEMADDR - Memory Address register */
+#define SHA_MEMADDR_BASEADDR_MASK (0xFFFFFFFFU)
+#define SHA_MEMADDR_BASEADDR_SHIFT (0U)
+#define SHA_MEMADDR_BASEADDR(x) (((uint32_t)(((uint32_t)(x)) << SHA_MEMADDR_BASEADDR_SHIFT)) & SHA_MEMADDR_BASEADDR_MASK)
+
+/*! @name INDATA - Input Data register */
+#define SHA_INDATA_DATA_MASK (0xFFFFFFFFU)
+#define SHA_INDATA_DATA_SHIFT (0U)
+#define SHA_INDATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << SHA_INDATA_DATA_SHIFT)) & SHA_INDATA_DATA_MASK)
+
+/*! @name ALIAS - Alias register */
+#define SHA_ALIAS_DATA_MASK (0xFFFFFFFFU)
+#define SHA_ALIAS_DATA_SHIFT (0U)
+#define SHA_ALIAS_DATA(x) (((uint32_t)(((uint32_t)(x)) << SHA_ALIAS_DATA_SHIFT)) & SHA_ALIAS_DATA_MASK)
+
+/* The count of SHA_ALIAS */
+#define SHA_ALIAS_COUNT (7U)
+
+/*! @name DIGEST - Digest register */
+#define SHA_DIGEST_DIGEST_MASK (0xFFFFFFFFU)
+#define SHA_DIGEST_DIGEST_SHIFT (0U)
+#define SHA_DIGEST_DIGEST(x) (((uint32_t)(((uint32_t)(x)) << SHA_DIGEST_DIGEST_SHIFT)) & SHA_DIGEST_DIGEST_MASK)
+
+/* The count of SHA_DIGEST */
+#define SHA_DIGEST_COUNT (8U)
+
+
+/*!
+ * @}
+ */ /* end of group SHA_Register_Masks */
+
+
+/* SHA - Peripheral instance base addresses */
+/** Peripheral SHA0 base address */
+#define SHA0_BASE (0x400A4000u)
+/** Peripheral SHA0 base pointer */
+#define SHA0 ((SHA_Type *)SHA0_BASE)
+/** Array initializer of SHA peripheral base addresses */
+#define SHA_BASE_ADDRS { SHA0_BASE }
+/** Array initializer of SHA peripheral base pointers */
+#define SHA_BASE_PTRS { SHA0 }
+
+/*!
+ * @}
+ */ /* end of group SHA_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SMARTCARD Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMARTCARD_Peripheral_Access_Layer SMARTCARD Peripheral Access Layer
+ * @{
+ */
+
+/** SMARTCARD - Register Layout Typedef */
+typedef struct {
+ union { /* offset: 0x0 */
+ __IO uint32_t DLL; /**< Divisor Latch LSB, offset: 0x0 */
+ __I uint32_t RBR; /**< Receiver Buffer Register, offset: 0x0 */
+ __O uint32_t THR; /**< Transmit Holding Register, offset: 0x0 */
+ };
+ union { /* offset: 0x4 */
+ __IO uint32_t DLM; /**< Divisor Latch MSB, offset: 0x4 */
+ __IO uint32_t IER; /**< Interrupt Enable Register, offset: 0x4 */
+ };
+ union { /* offset: 0x8 */
+ __O uint32_t FCR; /**< FIFO Control Register, offset: 0x8 */
+ __I uint32_t IIR; /**< Interrupt ID Register, offset: 0x8 */
+ };
+ __IO uint32_t LCR; /**< Line Control Register, offset: 0xC */
+ uint8_t RESERVED_0[4];
+ __I uint32_t LSR; /**< Line Status Register, offset: 0x14 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t SCR; /**< Scratch Pad Register, offset: 0x1C */
+ uint8_t RESERVED_2[12];
+ __IO uint32_t OSR; /**< Oversampling register, offset: 0x2C */
+ uint8_t RESERVED_3[24];
+ __IO uint32_t SCICTRL; /**< Smart Card Interface control register, offset: 0x48 */
+} SMARTCARD_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SMARTCARD Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SMARTCARD_Register_Masks SMARTCARD Register Masks
+ * @{
+ */
+
+/*! @name DLL - Divisor Latch LSB */
+#define SMARTCARD_DLL_DLLSB_MASK (0xFFU)
+#define SMARTCARD_DLL_DLLSB_SHIFT (0U)
+#define SMARTCARD_DLL_DLLSB(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_DLL_DLLSB_SHIFT)) & SMARTCARD_DLL_DLLSB_MASK)
+
+/*! @name RBR - Receiver Buffer Register */
+#define SMARTCARD_RBR_RBR_MASK (0xFFU)
+#define SMARTCARD_RBR_RBR_SHIFT (0U)
+#define SMARTCARD_RBR_RBR(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_RBR_RBR_SHIFT)) & SMARTCARD_RBR_RBR_MASK)
+
+/*! @name THR - Transmit Holding Register */
+#define SMARTCARD_THR_THR_MASK (0xFFU)
+#define SMARTCARD_THR_THR_SHIFT (0U)
+#define SMARTCARD_THR_THR(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_THR_THR_SHIFT)) & SMARTCARD_THR_THR_MASK)
+
+/*! @name DLM - Divisor Latch MSB */
+#define SMARTCARD_DLM_DLMSB_MASK (0xFFU)
+#define SMARTCARD_DLM_DLMSB_SHIFT (0U)
+#define SMARTCARD_DLM_DLMSB(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_DLM_DLMSB_SHIFT)) & SMARTCARD_DLM_DLMSB_MASK)
+
+/*! @name IER - Interrupt Enable Register */
+#define SMARTCARD_IER_RBRIE_MASK (0x1U)
+#define SMARTCARD_IER_RBRIE_SHIFT (0U)
+#define SMARTCARD_IER_RBRIE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IER_RBRIE_SHIFT)) & SMARTCARD_IER_RBRIE_MASK)
+#define SMARTCARD_IER_THREIE_MASK (0x2U)
+#define SMARTCARD_IER_THREIE_SHIFT (1U)
+#define SMARTCARD_IER_THREIE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IER_THREIE_SHIFT)) & SMARTCARD_IER_THREIE_MASK)
+#define SMARTCARD_IER_RXIE_MASK (0x4U)
+#define SMARTCARD_IER_RXIE_SHIFT (2U)
+#define SMARTCARD_IER_RXIE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IER_RXIE_SHIFT)) & SMARTCARD_IER_RXIE_MASK)
+
+/*! @name FCR - FIFO Control Register */
+#define SMARTCARD_FCR_FIFOEN_MASK (0x1U)
+#define SMARTCARD_FCR_FIFOEN_SHIFT (0U)
+#define SMARTCARD_FCR_FIFOEN(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_FIFOEN_SHIFT)) & SMARTCARD_FCR_FIFOEN_MASK)
+#define SMARTCARD_FCR_RXFIFORES_MASK (0x2U)
+#define SMARTCARD_FCR_RXFIFORES_SHIFT (1U)
+#define SMARTCARD_FCR_RXFIFORES(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_RXFIFORES_SHIFT)) & SMARTCARD_FCR_RXFIFORES_MASK)
+#define SMARTCARD_FCR_TXFIFORES_MASK (0x4U)
+#define SMARTCARD_FCR_TXFIFORES_SHIFT (2U)
+#define SMARTCARD_FCR_TXFIFORES(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_TXFIFORES_SHIFT)) & SMARTCARD_FCR_TXFIFORES_MASK)
+#define SMARTCARD_FCR_DMAMODE_MASK (0x8U)
+#define SMARTCARD_FCR_DMAMODE_SHIFT (3U)
+#define SMARTCARD_FCR_DMAMODE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_DMAMODE_SHIFT)) & SMARTCARD_FCR_DMAMODE_MASK)
+#define SMARTCARD_FCR_RXTRIGLVL_MASK (0xC0U)
+#define SMARTCARD_FCR_RXTRIGLVL_SHIFT (6U)
+#define SMARTCARD_FCR_RXTRIGLVL(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_FCR_RXTRIGLVL_SHIFT)) & SMARTCARD_FCR_RXTRIGLVL_MASK)
+
+/*! @name IIR - Interrupt ID Register */
+#define SMARTCARD_IIR_INTSTATUS_MASK (0x1U)
+#define SMARTCARD_IIR_INTSTATUS_SHIFT (0U)
+#define SMARTCARD_IIR_INTSTATUS(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IIR_INTSTATUS_SHIFT)) & SMARTCARD_IIR_INTSTATUS_MASK)
+#define SMARTCARD_IIR_INTID_MASK (0xEU)
+#define SMARTCARD_IIR_INTID_SHIFT (1U)
+#define SMARTCARD_IIR_INTID(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IIR_INTID_SHIFT)) & SMARTCARD_IIR_INTID_MASK)
+#define SMARTCARD_IIR_FIFOENABLE_MASK (0xC0U)
+#define SMARTCARD_IIR_FIFOENABLE_SHIFT (6U)
+#define SMARTCARD_IIR_FIFOENABLE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_IIR_FIFOENABLE_SHIFT)) & SMARTCARD_IIR_FIFOENABLE_MASK)
+
+/*! @name LCR - Line Control Register */
+#define SMARTCARD_LCR_WLS_MASK (0x3U)
+#define SMARTCARD_LCR_WLS_SHIFT (0U)
+#define SMARTCARD_LCR_WLS(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_WLS_SHIFT)) & SMARTCARD_LCR_WLS_MASK)
+#define SMARTCARD_LCR_SBS_MASK (0x4U)
+#define SMARTCARD_LCR_SBS_SHIFT (2U)
+#define SMARTCARD_LCR_SBS(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_SBS_SHIFT)) & SMARTCARD_LCR_SBS_MASK)
+#define SMARTCARD_LCR_PE_MASK (0x8U)
+#define SMARTCARD_LCR_PE_SHIFT (3U)
+#define SMARTCARD_LCR_PE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_PE_SHIFT)) & SMARTCARD_LCR_PE_MASK)
+#define SMARTCARD_LCR_PS_MASK (0x30U)
+#define SMARTCARD_LCR_PS_SHIFT (4U)
+#define SMARTCARD_LCR_PS(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_PS_SHIFT)) & SMARTCARD_LCR_PS_MASK)
+#define SMARTCARD_LCR_DLAB_MASK (0x80U)
+#define SMARTCARD_LCR_DLAB_SHIFT (7U)
+#define SMARTCARD_LCR_DLAB(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LCR_DLAB_SHIFT)) & SMARTCARD_LCR_DLAB_MASK)
+
+/*! @name LSR - Line Status Register */
+#define SMARTCARD_LSR_RDR_MASK (0x1U)
+#define SMARTCARD_LSR_RDR_SHIFT (0U)
+#define SMARTCARD_LSR_RDR(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_RDR_SHIFT)) & SMARTCARD_LSR_RDR_MASK)
+#define SMARTCARD_LSR_OE_MASK (0x2U)
+#define SMARTCARD_LSR_OE_SHIFT (1U)
+#define SMARTCARD_LSR_OE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_OE_SHIFT)) & SMARTCARD_LSR_OE_MASK)
+#define SMARTCARD_LSR_PE_MASK (0x4U)
+#define SMARTCARD_LSR_PE_SHIFT (2U)
+#define SMARTCARD_LSR_PE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_PE_SHIFT)) & SMARTCARD_LSR_PE_MASK)
+#define SMARTCARD_LSR_FE_MASK (0x8U)
+#define SMARTCARD_LSR_FE_SHIFT (3U)
+#define SMARTCARD_LSR_FE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_FE_SHIFT)) & SMARTCARD_LSR_FE_MASK)
+#define SMARTCARD_LSR_THRE_MASK (0x20U)
+#define SMARTCARD_LSR_THRE_SHIFT (5U)
+#define SMARTCARD_LSR_THRE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_THRE_SHIFT)) & SMARTCARD_LSR_THRE_MASK)
+#define SMARTCARD_LSR_TEMT_MASK (0x40U)
+#define SMARTCARD_LSR_TEMT_SHIFT (6U)
+#define SMARTCARD_LSR_TEMT(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_TEMT_SHIFT)) & SMARTCARD_LSR_TEMT_MASK)
+#define SMARTCARD_LSR_RXFE_MASK (0x80U)
+#define SMARTCARD_LSR_RXFE_SHIFT (7U)
+#define SMARTCARD_LSR_RXFE(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_LSR_RXFE_SHIFT)) & SMARTCARD_LSR_RXFE_MASK)
+
+/*! @name SCR - Scratch Pad Register */
+#define SMARTCARD_SCR_PAD_MASK (0xFFU)
+#define SMARTCARD_SCR_PAD_SHIFT (0U)
+#define SMARTCARD_SCR_PAD(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCR_PAD_SHIFT)) & SMARTCARD_SCR_PAD_MASK)
+
+/*! @name OSR - Oversampling register */
+#define SMARTCARD_OSR_OSFRAC_MASK (0xEU)
+#define SMARTCARD_OSR_OSFRAC_SHIFT (1U)
+#define SMARTCARD_OSR_OSFRAC(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_OSR_OSFRAC_SHIFT)) & SMARTCARD_OSR_OSFRAC_MASK)
+#define SMARTCARD_OSR_OSINT_MASK (0xF0U)
+#define SMARTCARD_OSR_OSINT_SHIFT (4U)
+#define SMARTCARD_OSR_OSINT(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_OSR_OSINT_SHIFT)) & SMARTCARD_OSR_OSINT_MASK)
+#define SMARTCARD_OSR_FDINT_MASK (0x7F00U)
+#define SMARTCARD_OSR_FDINT_SHIFT (8U)
+#define SMARTCARD_OSR_FDINT(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_OSR_FDINT_SHIFT)) & SMARTCARD_OSR_FDINT_MASK)
+
+/*! @name SCICTRL - Smart Card Interface control register */
+#define SMARTCARD_SCICTRL_SCIEN_MASK (0x1U)
+#define SMARTCARD_SCICTRL_SCIEN_SHIFT (0U)
+#define SMARTCARD_SCICTRL_SCIEN(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_SCIEN_SHIFT)) & SMARTCARD_SCICTRL_SCIEN_MASK)
+#define SMARTCARD_SCICTRL_NACKDIS_MASK (0x2U)
+#define SMARTCARD_SCICTRL_NACKDIS_SHIFT (1U)
+#define SMARTCARD_SCICTRL_NACKDIS(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_NACKDIS_SHIFT)) & SMARTCARD_SCICTRL_NACKDIS_MASK)
+#define SMARTCARD_SCICTRL_PROTSEL_MASK (0x4U)
+#define SMARTCARD_SCICTRL_PROTSEL_SHIFT (2U)
+#define SMARTCARD_SCICTRL_PROTSEL(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_PROTSEL_SHIFT)) & SMARTCARD_SCICTRL_PROTSEL_MASK)
+#define SMARTCARD_SCICTRL_TXRETRY_MASK (0xE0U)
+#define SMARTCARD_SCICTRL_TXRETRY_SHIFT (5U)
+#define SMARTCARD_SCICTRL_TXRETRY(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_TXRETRY_SHIFT)) & SMARTCARD_SCICTRL_TXRETRY_MASK)
+#define SMARTCARD_SCICTRL_GUARDTIME_MASK (0xFF00U)
+#define SMARTCARD_SCICTRL_GUARDTIME_SHIFT (8U)
+#define SMARTCARD_SCICTRL_GUARDTIME(x) (((uint32_t)(((uint32_t)(x)) << SMARTCARD_SCICTRL_GUARDTIME_SHIFT)) & SMARTCARD_SCICTRL_GUARDTIME_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group SMARTCARD_Register_Masks */
+
+
+/* SMARTCARD - Peripheral instance base addresses */
+/** Peripheral SMARTCARD0 base address */
+#define SMARTCARD0_BASE (0x40036000u)
+/** Peripheral SMARTCARD0 base pointer */
+#define SMARTCARD0 ((SMARTCARD_Type *)SMARTCARD0_BASE)
+/** Peripheral SMARTCARD1 base address */
+#define SMARTCARD1_BASE (0x40037000u)
+/** Peripheral SMARTCARD1 base pointer */
+#define SMARTCARD1 ((SMARTCARD_Type *)SMARTCARD1_BASE)
+/** Array initializer of SMARTCARD peripheral base addresses */
+#define SMARTCARD_BASE_ADDRS { SMARTCARD0_BASE, SMARTCARD1_BASE }
+/** Array initializer of SMARTCARD peripheral base pointers */
+#define SMARTCARD_BASE_PTRS { SMARTCARD0, SMARTCARD1 }
+/** Interrupt vectors for the SMARTCARD peripheral type */
+#define SMARTCARD_IRQS { SMARTCARD0_IRQn, SMARTCARD1_IRQn }
+
+/*!
+ * @}
+ */ /* end of group SMARTCARD_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SPI Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Peripheral_Access_Layer SPI Peripheral Access Layer
+ * @{
+ */
+
+/** SPI - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[1024];
+ __IO uint32_t CFG; /**< SPI Configuration register, offset: 0x400 */
+ __IO uint32_t DLY; /**< SPI Delay register, offset: 0x404 */
+ __IO uint32_t STAT; /**< SPI Status. Some status flags can be cleared by writing a 1 to that bit position., offset: 0x408 */
+ __IO uint32_t INTENSET; /**< SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0x40C */
+ __O uint32_t INTENCLR; /**< SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared., offset: 0x410 */
+ uint8_t RESERVED_1[16];
+ __IO uint32_t DIV; /**< SPI clock Divider, offset: 0x424 */
+ __I uint32_t INTSTAT; /**< SPI Interrupt Status, offset: 0x428 */
+ uint8_t RESERVED_2[2516];
+ __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */
+ __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */
+ __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */
+ uint8_t RESERVED_3[4];
+ __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */
+ __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */
+ __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */
+ uint8_t RESERVED_4[4];
+ __IO uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */
+ uint8_t RESERVED_5[12];
+ __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */
+ uint8_t RESERVED_6[12];
+ __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */
+ uint8_t RESERVED_7[440];
+ __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */
+} SPI_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SPI Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPI_Register_Masks SPI Register Masks
+ * @{
+ */
+
+/*! @name CFG - SPI Configuration register */
+#define SPI_CFG_ENABLE_MASK (0x1U)
+#define SPI_CFG_ENABLE_SHIFT (0U)
+#define SPI_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_ENABLE_SHIFT)) & SPI_CFG_ENABLE_MASK)
+#define SPI_CFG_MASTER_MASK (0x4U)
+#define SPI_CFG_MASTER_SHIFT (2U)
+#define SPI_CFG_MASTER(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_MASTER_SHIFT)) & SPI_CFG_MASTER_MASK)
+#define SPI_CFG_LSBF_MASK (0x8U)
+#define SPI_CFG_LSBF_SHIFT (3U)
+#define SPI_CFG_LSBF(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LSBF_SHIFT)) & SPI_CFG_LSBF_MASK)
+#define SPI_CFG_CPHA_MASK (0x10U)
+#define SPI_CFG_CPHA_SHIFT (4U)
+#define SPI_CFG_CPHA(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPHA_SHIFT)) & SPI_CFG_CPHA_MASK)
+#define SPI_CFG_CPOL_MASK (0x20U)
+#define SPI_CFG_CPOL_SHIFT (5U)
+#define SPI_CFG_CPOL(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_CPOL_SHIFT)) & SPI_CFG_CPOL_MASK)
+#define SPI_CFG_LOOP_MASK (0x80U)
+#define SPI_CFG_LOOP_SHIFT (7U)
+#define SPI_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_LOOP_SHIFT)) & SPI_CFG_LOOP_MASK)
+#define SPI_CFG_SPOL0_MASK (0x100U)
+#define SPI_CFG_SPOL0_SHIFT (8U)
+#define SPI_CFG_SPOL0(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL0_SHIFT)) & SPI_CFG_SPOL0_MASK)
+#define SPI_CFG_SPOL1_MASK (0x200U)
+#define SPI_CFG_SPOL1_SHIFT (9U)
+#define SPI_CFG_SPOL1(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL1_SHIFT)) & SPI_CFG_SPOL1_MASK)
+#define SPI_CFG_SPOL2_MASK (0x400U)
+#define SPI_CFG_SPOL2_SHIFT (10U)
+#define SPI_CFG_SPOL2(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL2_SHIFT)) & SPI_CFG_SPOL2_MASK)
+#define SPI_CFG_SPOL3_MASK (0x800U)
+#define SPI_CFG_SPOL3_SHIFT (11U)
+#define SPI_CFG_SPOL3(x) (((uint32_t)(((uint32_t)(x)) << SPI_CFG_SPOL3_SHIFT)) & SPI_CFG_SPOL3_MASK)
+
+/*! @name DLY - SPI Delay register */
+#define SPI_DLY_PRE_DELAY_MASK (0xFU)
+#define SPI_DLY_PRE_DELAY_SHIFT (0U)
+#define SPI_DLY_PRE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_PRE_DELAY_SHIFT)) & SPI_DLY_PRE_DELAY_MASK)
+#define SPI_DLY_POST_DELAY_MASK (0xF0U)
+#define SPI_DLY_POST_DELAY_SHIFT (4U)
+#define SPI_DLY_POST_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_POST_DELAY_SHIFT)) & SPI_DLY_POST_DELAY_MASK)
+#define SPI_DLY_FRAME_DELAY_MASK (0xF00U)
+#define SPI_DLY_FRAME_DELAY_SHIFT (8U)
+#define SPI_DLY_FRAME_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_FRAME_DELAY_SHIFT)) & SPI_DLY_FRAME_DELAY_MASK)
+#define SPI_DLY_TRANSFER_DELAY_MASK (0xF000U)
+#define SPI_DLY_TRANSFER_DELAY_SHIFT (12U)
+#define SPI_DLY_TRANSFER_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SPI_DLY_TRANSFER_DELAY_SHIFT)) & SPI_DLY_TRANSFER_DELAY_MASK)
+
+/*! @name STAT - SPI Status. Some status flags can be cleared by writing a 1 to that bit position. */
+#define SPI_STAT_SSA_MASK (0x10U)
+#define SPI_STAT_SSA_SHIFT (4U)
+#define SPI_STAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSA_SHIFT)) & SPI_STAT_SSA_MASK)
+#define SPI_STAT_SSD_MASK (0x20U)
+#define SPI_STAT_SSD_SHIFT (5U)
+#define SPI_STAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_SSD_SHIFT)) & SPI_STAT_SSD_MASK)
+#define SPI_STAT_STALLED_MASK (0x40U)
+#define SPI_STAT_STALLED_SHIFT (6U)
+#define SPI_STAT_STALLED(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_STALLED_SHIFT)) & SPI_STAT_STALLED_MASK)
+#define SPI_STAT_ENDTRANSFER_MASK (0x80U)
+#define SPI_STAT_ENDTRANSFER_SHIFT (7U)
+#define SPI_STAT_ENDTRANSFER(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_ENDTRANSFER_SHIFT)) & SPI_STAT_ENDTRANSFER_MASK)
+#define SPI_STAT_MSTIDLE_MASK (0x100U)
+#define SPI_STAT_MSTIDLE_SHIFT (8U)
+#define SPI_STAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_STAT_MSTIDLE_SHIFT)) & SPI_STAT_MSTIDLE_MASK)
+
+/*! @name INTENSET - SPI Interrupt Enable read and Set. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */
+#define SPI_INTENSET_SSAEN_MASK (0x10U)
+#define SPI_INTENSET_SSAEN_SHIFT (4U)
+#define SPI_INTENSET_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSAEN_SHIFT)) & SPI_INTENSET_SSAEN_MASK)
+#define SPI_INTENSET_SSDEN_MASK (0x20U)
+#define SPI_INTENSET_SSDEN_SHIFT (5U)
+#define SPI_INTENSET_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_SSDEN_SHIFT)) & SPI_INTENSET_SSDEN_MASK)
+#define SPI_INTENSET_MSTIDLEEN_MASK (0x100U)
+#define SPI_INTENSET_MSTIDLEEN_SHIFT (8U)
+#define SPI_INTENSET_MSTIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENSET_MSTIDLEEN_SHIFT)) & SPI_INTENSET_MSTIDLEEN_MASK)
+
+/*! @name INTENCLR - SPI Interrupt Enable Clear. Writing a 1 to any implemented bit position causes the corresponding bit in INTENSET to be cleared. */
+#define SPI_INTENCLR_SSAEN_MASK (0x10U)
+#define SPI_INTENCLR_SSAEN_SHIFT (4U)
+#define SPI_INTENCLR_SSAEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSAEN_SHIFT)) & SPI_INTENCLR_SSAEN_MASK)
+#define SPI_INTENCLR_SSDEN_MASK (0x20U)
+#define SPI_INTENCLR_SSDEN_SHIFT (5U)
+#define SPI_INTENCLR_SSDEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_SSDEN_SHIFT)) & SPI_INTENCLR_SSDEN_MASK)
+#define SPI_INTENCLR_MSTIDLE_MASK (0x100U)
+#define SPI_INTENCLR_MSTIDLE_SHIFT (8U)
+#define SPI_INTENCLR_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTENCLR_MSTIDLE_SHIFT)) & SPI_INTENCLR_MSTIDLE_MASK)
+
+/*! @name DIV - SPI clock Divider */
+#define SPI_DIV_DIVVAL_MASK (0xFFFFU)
+#define SPI_DIV_DIVVAL_SHIFT (0U)
+#define SPI_DIV_DIVVAL(x) (((uint32_t)(((uint32_t)(x)) << SPI_DIV_DIVVAL_SHIFT)) & SPI_DIV_DIVVAL_MASK)
+
+/*! @name INTSTAT - SPI Interrupt Status */
+#define SPI_INTSTAT_SSA_MASK (0x10U)
+#define SPI_INTSTAT_SSA_SHIFT (4U)
+#define SPI_INTSTAT_SSA(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSA_SHIFT)) & SPI_INTSTAT_SSA_MASK)
+#define SPI_INTSTAT_SSD_MASK (0x20U)
+#define SPI_INTSTAT_SSD_SHIFT (5U)
+#define SPI_INTSTAT_SSD(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_SSD_SHIFT)) & SPI_INTSTAT_SSD_MASK)
+#define SPI_INTSTAT_MSTIDLE_MASK (0x100U)
+#define SPI_INTSTAT_MSTIDLE_SHIFT (8U)
+#define SPI_INTSTAT_MSTIDLE(x) (((uint32_t)(((uint32_t)(x)) << SPI_INTSTAT_MSTIDLE_SHIFT)) & SPI_INTSTAT_MSTIDLE_MASK)
+
+/*! @name FIFOCFG - FIFO configuration and enable register. */
+#define SPI_FIFOCFG_ENABLETX_MASK (0x1U)
+#define SPI_FIFOCFG_ENABLETX_SHIFT (0U)
+#define SPI_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLETX_SHIFT)) & SPI_FIFOCFG_ENABLETX_MASK)
+#define SPI_FIFOCFG_ENABLERX_MASK (0x2U)
+#define SPI_FIFOCFG_ENABLERX_SHIFT (1U)
+#define SPI_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_ENABLERX_SHIFT)) & SPI_FIFOCFG_ENABLERX_MASK)
+#define SPI_FIFOCFG_SIZE_MASK (0x30U)
+#define SPI_FIFOCFG_SIZE_SHIFT (4U)
+#define SPI_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_SIZE_SHIFT)) & SPI_FIFOCFG_SIZE_MASK)
+#define SPI_FIFOCFG_DMATX_MASK (0x1000U)
+#define SPI_FIFOCFG_DMATX_SHIFT (12U)
+#define SPI_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMATX_SHIFT)) & SPI_FIFOCFG_DMATX_MASK)
+#define SPI_FIFOCFG_DMARX_MASK (0x2000U)
+#define SPI_FIFOCFG_DMARX_SHIFT (13U)
+#define SPI_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_DMARX_SHIFT)) & SPI_FIFOCFG_DMARX_MASK)
+#define SPI_FIFOCFG_WAKETX_MASK (0x4000U)
+#define SPI_FIFOCFG_WAKETX_SHIFT (14U)
+#define SPI_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKETX_SHIFT)) & SPI_FIFOCFG_WAKETX_MASK)
+#define SPI_FIFOCFG_WAKERX_MASK (0x8000U)
+#define SPI_FIFOCFG_WAKERX_SHIFT (15U)
+#define SPI_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_WAKERX_SHIFT)) & SPI_FIFOCFG_WAKERX_MASK)
+#define SPI_FIFOCFG_EMPTYTX_MASK (0x10000U)
+#define SPI_FIFOCFG_EMPTYTX_SHIFT (16U)
+#define SPI_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYTX_SHIFT)) & SPI_FIFOCFG_EMPTYTX_MASK)
+#define SPI_FIFOCFG_EMPTYRX_MASK (0x20000U)
+#define SPI_FIFOCFG_EMPTYRX_SHIFT (17U)
+#define SPI_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_EMPTYRX_SHIFT)) & SPI_FIFOCFG_EMPTYRX_MASK)
+#define SPI_FIFOCFG_POPDBG_MASK (0x40000U)
+#define SPI_FIFOCFG_POPDBG_SHIFT (18U)
+#define SPI_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOCFG_POPDBG_SHIFT)) & SPI_FIFOCFG_POPDBG_MASK)
+
+/*! @name FIFOSTAT - FIFO status register. */
+#define SPI_FIFOSTAT_TXERR_MASK (0x1U)
+#define SPI_FIFOSTAT_TXERR_SHIFT (0U)
+#define SPI_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXERR_SHIFT)) & SPI_FIFOSTAT_TXERR_MASK)
+#define SPI_FIFOSTAT_RXERR_MASK (0x2U)
+#define SPI_FIFOSTAT_RXERR_SHIFT (1U)
+#define SPI_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXERR_SHIFT)) & SPI_FIFOSTAT_RXERR_MASK)
+#define SPI_FIFOSTAT_PERINT_MASK (0x8U)
+#define SPI_FIFOSTAT_PERINT_SHIFT (3U)
+#define SPI_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_PERINT_SHIFT)) & SPI_FIFOSTAT_PERINT_MASK)
+#define SPI_FIFOSTAT_TXEMPTY_MASK (0x10U)
+#define SPI_FIFOSTAT_TXEMPTY_SHIFT (4U)
+#define SPI_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXEMPTY_SHIFT)) & SPI_FIFOSTAT_TXEMPTY_MASK)
+#define SPI_FIFOSTAT_TXNOTFULL_MASK (0x20U)
+#define SPI_FIFOSTAT_TXNOTFULL_SHIFT (5U)
+#define SPI_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXNOTFULL_SHIFT)) & SPI_FIFOSTAT_TXNOTFULL_MASK)
+#define SPI_FIFOSTAT_RXNOTEMPTY_MASK (0x40U)
+#define SPI_FIFOSTAT_RXNOTEMPTY_SHIFT (6U)
+#define SPI_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXNOTEMPTY_SHIFT)) & SPI_FIFOSTAT_RXNOTEMPTY_MASK)
+#define SPI_FIFOSTAT_RXFULL_MASK (0x80U)
+#define SPI_FIFOSTAT_RXFULL_SHIFT (7U)
+#define SPI_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXFULL_SHIFT)) & SPI_FIFOSTAT_RXFULL_MASK)
+#define SPI_FIFOSTAT_TXLVL_MASK (0x1F00U)
+#define SPI_FIFOSTAT_TXLVL_SHIFT (8U)
+#define SPI_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_TXLVL_SHIFT)) & SPI_FIFOSTAT_TXLVL_MASK)
+#define SPI_FIFOSTAT_RXLVL_MASK (0x1F0000U)
+#define SPI_FIFOSTAT_RXLVL_SHIFT (16U)
+#define SPI_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOSTAT_RXLVL_SHIFT)) & SPI_FIFOSTAT_RXLVL_MASK)
+
+/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */
+#define SPI_FIFOTRIG_TXLVLENA_MASK (0x1U)
+#define SPI_FIFOTRIG_TXLVLENA_SHIFT (0U)
+#define SPI_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVLENA_SHIFT)) & SPI_FIFOTRIG_TXLVLENA_MASK)
+#define SPI_FIFOTRIG_RXLVLENA_MASK (0x2U)
+#define SPI_FIFOTRIG_RXLVLENA_SHIFT (1U)
+#define SPI_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVLENA_SHIFT)) & SPI_FIFOTRIG_RXLVLENA_MASK)
+#define SPI_FIFOTRIG_TXLVL_MASK (0xF00U)
+#define SPI_FIFOTRIG_TXLVL_SHIFT (8U)
+#define SPI_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_TXLVL_SHIFT)) & SPI_FIFOTRIG_TXLVL_MASK)
+#define SPI_FIFOTRIG_RXLVL_MASK (0xF0000U)
+#define SPI_FIFOTRIG_RXLVL_SHIFT (16U)
+#define SPI_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOTRIG_RXLVL_SHIFT)) & SPI_FIFOTRIG_RXLVL_MASK)
+
+/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */
+#define SPI_FIFOINTENSET_TXERR_MASK (0x1U)
+#define SPI_FIFOINTENSET_TXERR_SHIFT (0U)
+#define SPI_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXERR_SHIFT)) & SPI_FIFOINTENSET_TXERR_MASK)
+#define SPI_FIFOINTENSET_RXERR_MASK (0x2U)
+#define SPI_FIFOINTENSET_RXERR_SHIFT (1U)
+#define SPI_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXERR_SHIFT)) & SPI_FIFOINTENSET_RXERR_MASK)
+#define SPI_FIFOINTENSET_TXLVL_MASK (0x4U)
+#define SPI_FIFOINTENSET_TXLVL_SHIFT (2U)
+#define SPI_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_TXLVL_SHIFT)) & SPI_FIFOINTENSET_TXLVL_MASK)
+#define SPI_FIFOINTENSET_RXLVL_MASK (0x8U)
+#define SPI_FIFOINTENSET_RXLVL_SHIFT (3U)
+#define SPI_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENSET_RXLVL_SHIFT)) & SPI_FIFOINTENSET_RXLVL_MASK)
+
+/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */
+#define SPI_FIFOINTENCLR_TXERR_MASK (0x1U)
+#define SPI_FIFOINTENCLR_TXERR_SHIFT (0U)
+#define SPI_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXERR_SHIFT)) & SPI_FIFOINTENCLR_TXERR_MASK)
+#define SPI_FIFOINTENCLR_RXERR_MASK (0x2U)
+#define SPI_FIFOINTENCLR_RXERR_SHIFT (1U)
+#define SPI_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXERR_SHIFT)) & SPI_FIFOINTENCLR_RXERR_MASK)
+#define SPI_FIFOINTENCLR_TXLVL_MASK (0x4U)
+#define SPI_FIFOINTENCLR_TXLVL_SHIFT (2U)
+#define SPI_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_TXLVL_SHIFT)) & SPI_FIFOINTENCLR_TXLVL_MASK)
+#define SPI_FIFOINTENCLR_RXLVL_MASK (0x8U)
+#define SPI_FIFOINTENCLR_RXLVL_SHIFT (3U)
+#define SPI_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTENCLR_RXLVL_SHIFT)) & SPI_FIFOINTENCLR_RXLVL_MASK)
+
+/*! @name FIFOINTSTAT - FIFO interrupt status register. */
+#define SPI_FIFOINTSTAT_TXERR_MASK (0x1U)
+#define SPI_FIFOINTSTAT_TXERR_SHIFT (0U)
+#define SPI_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXERR_SHIFT)) & SPI_FIFOINTSTAT_TXERR_MASK)
+#define SPI_FIFOINTSTAT_RXERR_MASK (0x2U)
+#define SPI_FIFOINTSTAT_RXERR_SHIFT (1U)
+#define SPI_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXERR_SHIFT)) & SPI_FIFOINTSTAT_RXERR_MASK)
+#define SPI_FIFOINTSTAT_TXLVL_MASK (0x4U)
+#define SPI_FIFOINTSTAT_TXLVL_SHIFT (2U)
+#define SPI_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_TXLVL_SHIFT)) & SPI_FIFOINTSTAT_TXLVL_MASK)
+#define SPI_FIFOINTSTAT_RXLVL_MASK (0x8U)
+#define SPI_FIFOINTSTAT_RXLVL_SHIFT (3U)
+#define SPI_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_RXLVL_SHIFT)) & SPI_FIFOINTSTAT_RXLVL_MASK)
+#define SPI_FIFOINTSTAT_PERINT_MASK (0x10U)
+#define SPI_FIFOINTSTAT_PERINT_SHIFT (4U)
+#define SPI_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOINTSTAT_PERINT_SHIFT)) & SPI_FIFOINTSTAT_PERINT_MASK)
+
+/*! @name FIFOWR - FIFO write data. */
+#define SPI_FIFOWR_TXDATA_MASK (0xFFFFU)
+#define SPI_FIFOWR_TXDATA_SHIFT (0U)
+#define SPI_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXDATA_SHIFT)) & SPI_FIFOWR_TXDATA_MASK)
+#define SPI_FIFOWR_TXSSEL0_N_MASK (0x10000U)
+#define SPI_FIFOWR_TXSSEL0_N_SHIFT (16U)
+#define SPI_FIFOWR_TXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL0_N_SHIFT)) & SPI_FIFOWR_TXSSEL0_N_MASK)
+#define SPI_FIFOWR_TXSSEL1_N_MASK (0x20000U)
+#define SPI_FIFOWR_TXSSEL1_N_SHIFT (17U)
+#define SPI_FIFOWR_TXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL1_N_SHIFT)) & SPI_FIFOWR_TXSSEL1_N_MASK)
+#define SPI_FIFOWR_TXSSEL2_N_MASK (0x40000U)
+#define SPI_FIFOWR_TXSSEL2_N_SHIFT (18U)
+#define SPI_FIFOWR_TXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL2_N_SHIFT)) & SPI_FIFOWR_TXSSEL2_N_MASK)
+#define SPI_FIFOWR_TXSSEL3_N_MASK (0x80000U)
+#define SPI_FIFOWR_TXSSEL3_N_SHIFT (19U)
+#define SPI_FIFOWR_TXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_TXSSEL3_N_SHIFT)) & SPI_FIFOWR_TXSSEL3_N_MASK)
+#define SPI_FIFOWR_EOT_MASK (0x100000U)
+#define SPI_FIFOWR_EOT_SHIFT (20U)
+#define SPI_FIFOWR_EOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOT_SHIFT)) & SPI_FIFOWR_EOT_MASK)
+#define SPI_FIFOWR_EOF_MASK (0x200000U)
+#define SPI_FIFOWR_EOF_SHIFT (21U)
+#define SPI_FIFOWR_EOF(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_EOF_SHIFT)) & SPI_FIFOWR_EOF_MASK)
+#define SPI_FIFOWR_RXIGNORE_MASK (0x400000U)
+#define SPI_FIFOWR_RXIGNORE_SHIFT (22U)
+#define SPI_FIFOWR_RXIGNORE(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_RXIGNORE_SHIFT)) & SPI_FIFOWR_RXIGNORE_MASK)
+#define SPI_FIFOWR_LEN_MASK (0xF000000U)
+#define SPI_FIFOWR_LEN_SHIFT (24U)
+#define SPI_FIFOWR_LEN(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFOWR_LEN_SHIFT)) & SPI_FIFOWR_LEN_MASK)
+
+/*! @name FIFORD - FIFO read data. */
+#define SPI_FIFORD_RXDATA_MASK (0xFFFFU)
+#define SPI_FIFORD_RXDATA_SHIFT (0U)
+#define SPI_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXDATA_SHIFT)) & SPI_FIFORD_RXDATA_MASK)
+#define SPI_FIFORD_RXSSEL0_N_MASK (0x10000U)
+#define SPI_FIFORD_RXSSEL0_N_SHIFT (16U)
+#define SPI_FIFORD_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL0_N_SHIFT)) & SPI_FIFORD_RXSSEL0_N_MASK)
+#define SPI_FIFORD_RXSSEL1_N_MASK (0x20000U)
+#define SPI_FIFORD_RXSSEL1_N_SHIFT (17U)
+#define SPI_FIFORD_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL1_N_SHIFT)) & SPI_FIFORD_RXSSEL1_N_MASK)
+#define SPI_FIFORD_RXSSEL2_N_MASK (0x40000U)
+#define SPI_FIFORD_RXSSEL2_N_SHIFT (18U)
+#define SPI_FIFORD_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL2_N_SHIFT)) & SPI_FIFORD_RXSSEL2_N_MASK)
+#define SPI_FIFORD_RXSSEL3_N_MASK (0x80000U)
+#define SPI_FIFORD_RXSSEL3_N_SHIFT (19U)
+#define SPI_FIFORD_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_RXSSEL3_N_SHIFT)) & SPI_FIFORD_RXSSEL3_N_MASK)
+#define SPI_FIFORD_SOT_MASK (0x100000U)
+#define SPI_FIFORD_SOT_SHIFT (20U)
+#define SPI_FIFORD_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORD_SOT_SHIFT)) & SPI_FIFORD_SOT_MASK)
+
+/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */
+#define SPI_FIFORDNOPOP_RXDATA_MASK (0xFFFFU)
+#define SPI_FIFORDNOPOP_RXDATA_SHIFT (0U)
+#define SPI_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXDATA_SHIFT)) & SPI_FIFORDNOPOP_RXDATA_MASK)
+#define SPI_FIFORDNOPOP_RXSSEL0_N_MASK (0x10000U)
+#define SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT (16U)
+#define SPI_FIFORDNOPOP_RXSSEL0_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL0_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL0_N_MASK)
+#define SPI_FIFORDNOPOP_RXSSEL1_N_MASK (0x20000U)
+#define SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT (17U)
+#define SPI_FIFORDNOPOP_RXSSEL1_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL1_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL1_N_MASK)
+#define SPI_FIFORDNOPOP_RXSSEL2_N_MASK (0x40000U)
+#define SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT (18U)
+#define SPI_FIFORDNOPOP_RXSSEL2_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL2_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL2_N_MASK)
+#define SPI_FIFORDNOPOP_RXSSEL3_N_MASK (0x80000U)
+#define SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT (19U)
+#define SPI_FIFORDNOPOP_RXSSEL3_N(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_RXSSEL3_N_SHIFT)) & SPI_FIFORDNOPOP_RXSSEL3_N_MASK)
+#define SPI_FIFORDNOPOP_SOT_MASK (0x100000U)
+#define SPI_FIFORDNOPOP_SOT_SHIFT (20U)
+#define SPI_FIFORDNOPOP_SOT(x) (((uint32_t)(((uint32_t)(x)) << SPI_FIFORDNOPOP_SOT_SHIFT)) & SPI_FIFORDNOPOP_SOT_MASK)
+
+/*! @name ID - Peripheral identification register. */
+#define SPI_ID_APERTURE_MASK (0xFFU)
+#define SPI_ID_APERTURE_SHIFT (0U)
+#define SPI_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_APERTURE_SHIFT)) & SPI_ID_APERTURE_MASK)
+#define SPI_ID_MINOR_REV_MASK (0xF00U)
+#define SPI_ID_MINOR_REV_SHIFT (8U)
+#define SPI_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MINOR_REV_SHIFT)) & SPI_ID_MINOR_REV_MASK)
+#define SPI_ID_MAJOR_REV_MASK (0xF000U)
+#define SPI_ID_MAJOR_REV_SHIFT (12U)
+#define SPI_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_MAJOR_REV_SHIFT)) & SPI_ID_MAJOR_REV_MASK)
+#define SPI_ID_ID_MASK (0xFFFF0000U)
+#define SPI_ID_ID_SHIFT (16U)
+#define SPI_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << SPI_ID_ID_SHIFT)) & SPI_ID_ID_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group SPI_Register_Masks */
+
+
+/* SPI - Peripheral instance base addresses */
+/** Peripheral SPI0 base address */
+#define SPI0_BASE (0x40086000u)
+/** Peripheral SPI0 base pointer */
+#define SPI0 ((SPI_Type *)SPI0_BASE)
+/** Peripheral SPI1 base address */
+#define SPI1_BASE (0x40087000u)
+/** Peripheral SPI1 base pointer */
+#define SPI1 ((SPI_Type *)SPI1_BASE)
+/** Peripheral SPI2 base address */
+#define SPI2_BASE (0x40088000u)
+/** Peripheral SPI2 base pointer */
+#define SPI2 ((SPI_Type *)SPI2_BASE)
+/** Peripheral SPI3 base address */
+#define SPI3_BASE (0x40089000u)
+/** Peripheral SPI3 base pointer */
+#define SPI3 ((SPI_Type *)SPI3_BASE)
+/** Peripheral SPI4 base address */
+#define SPI4_BASE (0x4008A000u)
+/** Peripheral SPI4 base pointer */
+#define SPI4 ((SPI_Type *)SPI4_BASE)
+/** Peripheral SPI5 base address */
+#define SPI5_BASE (0x40096000u)
+/** Peripheral SPI5 base pointer */
+#define SPI5 ((SPI_Type *)SPI5_BASE)
+/** Peripheral SPI6 base address */
+#define SPI6_BASE (0x40097000u)
+/** Peripheral SPI6 base pointer */
+#define SPI6 ((SPI_Type *)SPI6_BASE)
+/** Peripheral SPI7 base address */
+#define SPI7_BASE (0x40098000u)
+/** Peripheral SPI7 base pointer */
+#define SPI7 ((SPI_Type *)SPI7_BASE)
+/** Peripheral SPI8 base address */
+#define SPI8_BASE (0x40099000u)
+/** Peripheral SPI8 base pointer */
+#define SPI8 ((SPI_Type *)SPI8_BASE)
+/** Peripheral SPI9 base address */
+#define SPI9_BASE (0x4009A000u)
+/** Peripheral SPI9 base pointer */
+#define SPI9 ((SPI_Type *)SPI9_BASE)
+/** Array initializer of SPI peripheral base addresses */
+#define SPI_BASE_ADDRS { SPI0_BASE, SPI1_BASE, SPI2_BASE, SPI3_BASE, SPI4_BASE, SPI5_BASE, SPI6_BASE, SPI7_BASE, SPI8_BASE, SPI9_BASE }
+/** Array initializer of SPI peripheral base pointers */
+#define SPI_BASE_PTRS { SPI0, SPI1, SPI2, SPI3, SPI4, SPI5, SPI6, SPI7, SPI8, SPI9 }
+/** Interrupt vectors for the SPI peripheral type */
+#define SPI_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn }
+
+/*!
+ * @}
+ */ /* end of group SPI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SPIFI Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPIFI_Peripheral_Access_Layer SPIFI Peripheral Access Layer
+ * @{
+ */
+
+/** SPIFI - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CTRL; /**< SPIFI control register, offset: 0x0 */
+ __IO uint32_t CMD; /**< SPIFI command register, offset: 0x4 */
+ __IO uint32_t ADDR; /**< SPIFI address register, offset: 0x8 */
+ __IO uint32_t IDATA; /**< SPIFI intermediate data register, offset: 0xC */
+ __IO uint32_t CLIMIT; /**< SPIFI limit register, offset: 0x10 */
+ __IO uint32_t DATA; /**< SPIFI data register, offset: 0x14 */
+ __IO uint32_t MCMD; /**< SPIFI memory command register, offset: 0x18 */
+ __IO uint32_t STAT; /**< SPIFI status register, offset: 0x1C */
+} SPIFI_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SPIFI Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SPIFI_Register_Masks SPIFI Register Masks
+ * @{
+ */
+
+/*! @name CTRL - SPIFI control register */
+#define SPIFI_CTRL_TIMEOUT_MASK (0xFFFFU)
+#define SPIFI_CTRL_TIMEOUT_SHIFT (0U)
+#define SPIFI_CTRL_TIMEOUT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_TIMEOUT_SHIFT)) & SPIFI_CTRL_TIMEOUT_MASK)
+#define SPIFI_CTRL_CSHIGH_MASK (0xF0000U)
+#define SPIFI_CTRL_CSHIGH_SHIFT (16U)
+#define SPIFI_CTRL_CSHIGH(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_CSHIGH_SHIFT)) & SPIFI_CTRL_CSHIGH_MASK)
+#define SPIFI_CTRL_D_PRFTCH_DIS_MASK (0x200000U)
+#define SPIFI_CTRL_D_PRFTCH_DIS_SHIFT (21U)
+#define SPIFI_CTRL_D_PRFTCH_DIS(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_D_PRFTCH_DIS_SHIFT)) & SPIFI_CTRL_D_PRFTCH_DIS_MASK)
+#define SPIFI_CTRL_INTEN_MASK (0x400000U)
+#define SPIFI_CTRL_INTEN_SHIFT (22U)
+#define SPIFI_CTRL_INTEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_INTEN_SHIFT)) & SPIFI_CTRL_INTEN_MASK)
+#define SPIFI_CTRL_MODE3_MASK (0x800000U)
+#define SPIFI_CTRL_MODE3_SHIFT (23U)
+#define SPIFI_CTRL_MODE3(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_MODE3_SHIFT)) & SPIFI_CTRL_MODE3_MASK)
+#define SPIFI_CTRL_PRFTCH_DIS_MASK (0x8000000U)
+#define SPIFI_CTRL_PRFTCH_DIS_SHIFT (27U)
+#define SPIFI_CTRL_PRFTCH_DIS(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_PRFTCH_DIS_SHIFT)) & SPIFI_CTRL_PRFTCH_DIS_MASK)
+#define SPIFI_CTRL_DUAL_MASK (0x10000000U)
+#define SPIFI_CTRL_DUAL_SHIFT (28U)
+#define SPIFI_CTRL_DUAL(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_DUAL_SHIFT)) & SPIFI_CTRL_DUAL_MASK)
+#define SPIFI_CTRL_RFCLK_MASK (0x20000000U)
+#define SPIFI_CTRL_RFCLK_SHIFT (29U)
+#define SPIFI_CTRL_RFCLK(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_RFCLK_SHIFT)) & SPIFI_CTRL_RFCLK_MASK)
+#define SPIFI_CTRL_FBCLK_MASK (0x40000000U)
+#define SPIFI_CTRL_FBCLK_SHIFT (30U)
+#define SPIFI_CTRL_FBCLK(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_FBCLK_SHIFT)) & SPIFI_CTRL_FBCLK_MASK)
+#define SPIFI_CTRL_DMAEN_MASK (0x80000000U)
+#define SPIFI_CTRL_DMAEN_SHIFT (31U)
+#define SPIFI_CTRL_DMAEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CTRL_DMAEN_SHIFT)) & SPIFI_CTRL_DMAEN_MASK)
+
+/*! @name CMD - SPIFI command register */
+#define SPIFI_CMD_DATALEN_MASK (0x3FFFU)
+#define SPIFI_CMD_DATALEN_SHIFT (0U)
+#define SPIFI_CMD_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_DATALEN_SHIFT)) & SPIFI_CMD_DATALEN_MASK)
+#define SPIFI_CMD_POLL_MASK (0x4000U)
+#define SPIFI_CMD_POLL_SHIFT (14U)
+#define SPIFI_CMD_POLL(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_POLL_SHIFT)) & SPIFI_CMD_POLL_MASK)
+#define SPIFI_CMD_DOUT_MASK (0x8000U)
+#define SPIFI_CMD_DOUT_SHIFT (15U)
+#define SPIFI_CMD_DOUT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_DOUT_SHIFT)) & SPIFI_CMD_DOUT_MASK)
+#define SPIFI_CMD_INTLEN_MASK (0x70000U)
+#define SPIFI_CMD_INTLEN_SHIFT (16U)
+#define SPIFI_CMD_INTLEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_INTLEN_SHIFT)) & SPIFI_CMD_INTLEN_MASK)
+#define SPIFI_CMD_FIELDFORM_MASK (0x180000U)
+#define SPIFI_CMD_FIELDFORM_SHIFT (19U)
+#define SPIFI_CMD_FIELDFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_FIELDFORM_SHIFT)) & SPIFI_CMD_FIELDFORM_MASK)
+#define SPIFI_CMD_FRAMEFORM_MASK (0xE00000U)
+#define SPIFI_CMD_FRAMEFORM_SHIFT (21U)
+#define SPIFI_CMD_FRAMEFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_FRAMEFORM_SHIFT)) & SPIFI_CMD_FRAMEFORM_MASK)
+#define SPIFI_CMD_OPCODE_MASK (0xFF000000U)
+#define SPIFI_CMD_OPCODE_SHIFT (24U)
+#define SPIFI_CMD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CMD_OPCODE_SHIFT)) & SPIFI_CMD_OPCODE_MASK)
+
+/*! @name ADDR - SPIFI address register */
+#define SPIFI_ADDR_ADDRESS_MASK (0xFFFFFFFFU)
+#define SPIFI_ADDR_ADDRESS_SHIFT (0U)
+#define SPIFI_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_ADDR_ADDRESS_SHIFT)) & SPIFI_ADDR_ADDRESS_MASK)
+
+/*! @name IDATA - SPIFI intermediate data register */
+#define SPIFI_IDATA_IDATA_MASK (0xFFFFFFFFU)
+#define SPIFI_IDATA_IDATA_SHIFT (0U)
+#define SPIFI_IDATA_IDATA(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_IDATA_IDATA_SHIFT)) & SPIFI_IDATA_IDATA_MASK)
+
+/*! @name CLIMIT - SPIFI limit register */
+#define SPIFI_CLIMIT_CLIMIT_MASK (0xFFFFFFFFU)
+#define SPIFI_CLIMIT_CLIMIT_SHIFT (0U)
+#define SPIFI_CLIMIT_CLIMIT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_CLIMIT_CLIMIT_SHIFT)) & SPIFI_CLIMIT_CLIMIT_MASK)
+
+/*! @name DATA - SPIFI data register */
+#define SPIFI_DATA_DATA_MASK (0xFFFFFFFFU)
+#define SPIFI_DATA_DATA_SHIFT (0U)
+#define SPIFI_DATA_DATA(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_DATA_DATA_SHIFT)) & SPIFI_DATA_DATA_MASK)
+
+/*! @name MCMD - SPIFI memory command register */
+#define SPIFI_MCMD_POLL_MASK (0x4000U)
+#define SPIFI_MCMD_POLL_SHIFT (14U)
+#define SPIFI_MCMD_POLL(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_POLL_SHIFT)) & SPIFI_MCMD_POLL_MASK)
+#define SPIFI_MCMD_DOUT_MASK (0x8000U)
+#define SPIFI_MCMD_DOUT_SHIFT (15U)
+#define SPIFI_MCMD_DOUT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_DOUT_SHIFT)) & SPIFI_MCMD_DOUT_MASK)
+#define SPIFI_MCMD_INTLEN_MASK (0x70000U)
+#define SPIFI_MCMD_INTLEN_SHIFT (16U)
+#define SPIFI_MCMD_INTLEN(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_INTLEN_SHIFT)) & SPIFI_MCMD_INTLEN_MASK)
+#define SPIFI_MCMD_FIELDFORM_MASK (0x180000U)
+#define SPIFI_MCMD_FIELDFORM_SHIFT (19U)
+#define SPIFI_MCMD_FIELDFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_FIELDFORM_SHIFT)) & SPIFI_MCMD_FIELDFORM_MASK)
+#define SPIFI_MCMD_FRAMEFORM_MASK (0xE00000U)
+#define SPIFI_MCMD_FRAMEFORM_SHIFT (21U)
+#define SPIFI_MCMD_FRAMEFORM(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_FRAMEFORM_SHIFT)) & SPIFI_MCMD_FRAMEFORM_MASK)
+#define SPIFI_MCMD_OPCODE_MASK (0xFF000000U)
+#define SPIFI_MCMD_OPCODE_SHIFT (24U)
+#define SPIFI_MCMD_OPCODE(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_MCMD_OPCODE_SHIFT)) & SPIFI_MCMD_OPCODE_MASK)
+
+/*! @name STAT - SPIFI status register */
+#define SPIFI_STAT_MCINIT_MASK (0x1U)
+#define SPIFI_STAT_MCINIT_SHIFT (0U)
+#define SPIFI_STAT_MCINIT(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_MCINIT_SHIFT)) & SPIFI_STAT_MCINIT_MASK)
+#define SPIFI_STAT_CMD_MASK (0x2U)
+#define SPIFI_STAT_CMD_SHIFT (1U)
+#define SPIFI_STAT_CMD(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_CMD_SHIFT)) & SPIFI_STAT_CMD_MASK)
+#define SPIFI_STAT_RESET_MASK (0x10U)
+#define SPIFI_STAT_RESET_SHIFT (4U)
+#define SPIFI_STAT_RESET(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_RESET_SHIFT)) & SPIFI_STAT_RESET_MASK)
+#define SPIFI_STAT_INTRQ_MASK (0x20U)
+#define SPIFI_STAT_INTRQ_SHIFT (5U)
+#define SPIFI_STAT_INTRQ(x) (((uint32_t)(((uint32_t)(x)) << SPIFI_STAT_INTRQ_SHIFT)) & SPIFI_STAT_INTRQ_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group SPIFI_Register_Masks */
+
+
+/* SPIFI - Peripheral instance base addresses */
+/** Peripheral SPIFI0 base address */
+#define SPIFI0_BASE (0x40080000u)
+/** Peripheral SPIFI0 base pointer */
+#define SPIFI0 ((SPIFI_Type *)SPIFI0_BASE)
+/** Array initializer of SPIFI peripheral base addresses */
+#define SPIFI_BASE_ADDRS { SPIFI0_BASE }
+/** Array initializer of SPIFI peripheral base pointers */
+#define SPIFI_BASE_PTRS { SPIFI0 }
+/** Interrupt vectors for the SPIFI peripheral type */
+#define SPIFI_IRQS { SPIFI0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group SPIFI_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- SYSCON Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SYSCON_Peripheral_Access_Layer SYSCON Peripheral Access Layer
+ * @{
+ */
+
+/** SYSCON - Register Layout Typedef */
+typedef struct {
+ uint8_t RESERVED_0[16];
+ __IO uint32_t AHBMATPRIO; /**< AHB multilayer matrix priority control, offset: 0x10 */
+ uint8_t RESERVED_1[44];
+ __IO uint32_t SYSTCKCAL; /**< System tick counter calibration, offset: 0x40 */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t NMISRC; /**< NMI Source Select, offset: 0x48 */
+ __IO uint32_t ASYNCAPBCTRL; /**< Asynchronous APB Control, offset: 0x4C */
+ uint8_t RESERVED_3[112];
+ __I uint32_t PIOPORCAP[2]; /**< POR captured value of port n, array offset: 0xC0, array step: 0x4 */
+ uint8_t RESERVED_4[8];
+ __I uint32_t PIORESCAP[2]; /**< Reset captured value of port n, array offset: 0xD0, array step: 0x4 */
+ uint8_t RESERVED_5[40];
+ __IO uint32_t PRESETCTRL[3]; /**< Peripheral reset control n, array offset: 0x100, array step: 0x4 */
+ uint8_t RESERVED_6[20];
+ __O uint32_t PRESETCTRLSET[3]; /**< Set bits in PRESETCTRLn, array offset: 0x120, array step: 0x4 */
+ uint8_t RESERVED_7[20];
+ __O uint32_t PRESETCTRLCLR[3]; /**< Clear bits in PRESETCTRLn, array offset: 0x140, array step: 0x4 */
+ uint8_t RESERVED_8[164];
+ __IO uint32_t SYSRSTSTAT; /**< System reset status register, offset: 0x1F0 */
+ uint8_t RESERVED_9[12];
+ __IO uint32_t AHBCLKCTRL[3]; /**< AHB Clock control n, array offset: 0x200, array step: 0x4 */
+ uint8_t RESERVED_10[20];
+ __O uint32_t AHBCLKCTRLSET[3]; /**< Set bits in AHBCLKCTRLn, array offset: 0x220, array step: 0x4 */
+ uint8_t RESERVED_11[20];
+ __O uint32_t AHBCLKCTRLCLR[3]; /**< Clear bits in AHBCLKCTRLn, array offset: 0x240, array step: 0x4 */
+ uint8_t RESERVED_12[52];
+ __IO uint32_t MAINCLKSELA; /**< Main clock source select A, offset: 0x280 */
+ __IO uint32_t MAINCLKSELB; /**< Main clock source select B, offset: 0x284 */
+ __IO uint32_t CLKOUTSELA; /**< CLKOUT clock source select A, offset: 0x288 */
+ uint8_t RESERVED_13[4];
+ __IO uint32_t SYSPLLCLKSEL; /**< PLL clock source select, offset: 0x290 */
+ uint8_t RESERVED_14[4];
+ __IO uint32_t AUDPLLCLKSEL; /**< Audio PLL clock source select, offset: 0x298 */
+ uint8_t RESERVED_15[4];
+ __IO uint32_t SPIFICLKSEL; /**< SPIFI clock source select, offset: 0x2A0 */
+ __IO uint32_t ADCCLKSEL; /**< ADC clock source select, offset: 0x2A4 */
+ __IO uint32_t USB0CLKSEL; /**< USB0 clock source select, offset: 0x2A8 */
+ __IO uint32_t USB1CLKSEL; /**< USB1 clock source select, offset: 0x2AC */
+ __IO uint32_t FCLKSEL[10]; /**< Flexcomm 0 clock source select, array offset: 0x2B0, array step: 0x4 */
+ uint8_t RESERVED_16[8];
+ __IO uint32_t MCLKCLKSEL; /**< MCLK clock source select, offset: 0x2E0 */
+ uint8_t RESERVED_17[4];
+ __IO uint32_t FRGCLKSEL; /**< Fractional Rate Generator clock source select, offset: 0x2E8 */
+ __IO uint32_t DMICCLKSEL; /**< Digital microphone (DMIC) subsystem clock select, offset: 0x2EC */
+ __IO uint32_t SCTCLKSEL; /**< SCTimer/PWM clock source select, offset: 0x2F0 */
+ __IO uint32_t LCDCLKSEL; /**< LCD clock source select, offset: 0x2F4 */
+ __IO uint32_t SDIOCLKSEL; /**< SDIO clock source select, offset: 0x2F8 */
+ uint8_t RESERVED_18[4];
+ __IO uint32_t SYSTICKCLKDIV; /**< SYSTICK clock divider, offset: 0x300 */
+ __IO uint32_t ARMTRACECLKDIV; /**< ARM Trace clock divider, offset: 0x304 */
+ __IO uint32_t CAN0CLKDIV; /**< MCAN0 clock divider, offset: 0x308 */
+ __IO uint32_t CAN1CLKDIV; /**< MCAN1 clock divider, offset: 0x30C */
+ __IO uint32_t SC0CLKDIV; /**< Smartcard0 clock divider, offset: 0x310 */
+ __IO uint32_t SC1CLKDIV; /**< Smartcard1 clock divider, offset: 0x314 */
+ uint8_t RESERVED_19[104];
+ __IO uint32_t AHBCLKDIV; /**< AHB clock divider, offset: 0x380 */
+ __IO uint32_t CLKOUTDIV; /**< CLKOUT clock divider, offset: 0x384 */
+ __IO uint32_t FROHFCLKDIV; /**< FROHF clock divider, offset: 0x388 */
+ uint8_t RESERVED_20[4];
+ __IO uint32_t SPIFICLKDIV; /**< SPIFI clock divider, offset: 0x390 */
+ __IO uint32_t ADCCLKDIV; /**< ADC clock divider, offset: 0x394 */
+ __IO uint32_t USB0CLKDIV; /**< USB0 clock divider, offset: 0x398 */
+ __IO uint32_t USB1CLKDIV; /**< USB1 clock divider, offset: 0x39C */
+ __IO uint32_t FRGCTRL; /**< Fractional rate divider, offset: 0x3A0 */
+ uint8_t RESERVED_21[4];
+ __IO uint32_t DMICCLKDIV; /**< DMIC clock divider, offset: 0x3A8 */
+ __IO uint32_t MCLKDIV; /**< I2S MCLK clock divider, offset: 0x3AC */
+ __IO uint32_t LCDCLKDIV; /**< LCD clock divider, offset: 0x3B0 */
+ __IO uint32_t SCTCLKDIV; /**< SCT/PWM clock divider, offset: 0x3B4 */
+ __IO uint32_t EMCCLKDIV; /**< EMC clock divider, offset: 0x3B8 */
+ __IO uint32_t SDIOCLKDIV; /**< SDIO clock divider, offset: 0x3BC */
+ uint8_t RESERVED_22[64];
+ __IO uint32_t FLASHCFG; /**< Flash wait states configuration, offset: 0x400 */
+ uint8_t RESERVED_23[8];
+ __IO uint32_t USB0CLKCTRL; /**< USB0 clock control, offset: 0x40C */
+ __IO uint32_t USB0CLKSTAT; /**< USB0 clock status, offset: 0x410 */
+ uint8_t RESERVED_24[4];
+ __IO uint32_t FREQMECTRL; /**< Frequency measure register, offset: 0x418 */
+ uint8_t RESERVED_25[4];
+ __IO uint32_t MCLKIO; /**< MCLK input/output control, offset: 0x420 */
+ __IO uint32_t USB1CLKCTRL; /**< USB1 clock control, offset: 0x424 */
+ __IO uint32_t USB1CLKSTAT; /**< USB1 clock status, offset: 0x428 */
+ uint8_t RESERVED_26[24];
+ __IO uint32_t EMCSYSCTRL; /**< EMC system control, offset: 0x444 */
+ __IO uint32_t EMCDLYCTRL; /**< EMC clock delay control, offset: 0x448 */
+ __IO uint32_t EMCDLYCAL; /**< EMC delay chain calibration control, offset: 0x44C */
+ __IO uint32_t ETHPHYSEL; /**< Ethernet PHY Selection, offset: 0x450 */
+ __IO uint32_t ETHSBDCTRL; /**< Ethernet SBD flow control, offset: 0x454 */
+ uint8_t RESERVED_27[8];
+ __IO uint32_t SDIOCLKCTRL; /**< SDIO CCLKIN phase and delay control, offset: 0x460 */
+ uint8_t RESERVED_28[156];
+ __IO uint32_t FROCTRL; /**< FRO oscillator control, offset: 0x500 */
+ __IO uint32_t SYSOSCCTRL; /**< System oscillator control, offset: 0x504 */
+ __IO uint32_t WDTOSCCTRL; /**< Watchdog oscillator control, offset: 0x508 */
+ __IO uint32_t RTCOSCCTRL; /**< RTC oscillator 32 kHz output control, offset: 0x50C */
+ uint8_t RESERVED_29[12];
+ __IO uint32_t USBPLLCTRL; /**< USB PLL control, offset: 0x51C */
+ __IO uint32_t USBPLLSTAT; /**< USB PLL status, offset: 0x520 */
+ uint8_t RESERVED_30[92];
+ __IO uint32_t SYSPLLCTRL; /**< System PLL control, offset: 0x580 */
+ __IO uint32_t SYSPLLSTAT; /**< PLL status, offset: 0x584 */
+ __IO uint32_t SYSPLLNDEC; /**< PLL N divider, offset: 0x588 */
+ __IO uint32_t SYSPLLPDEC; /**< PLL P divider, offset: 0x58C */
+ __IO uint32_t SYSPLLMDEC; /**< System PLL M divider, offset: 0x590 */
+ uint8_t RESERVED_31[12];
+ __IO uint32_t AUDPLLCTRL; /**< Audio PLL control, offset: 0x5A0 */
+ __IO uint32_t AUDPLLSTAT; /**< Audio PLL status, offset: 0x5A4 */
+ __IO uint32_t AUDPLLNDEC; /**< Audio PLL N divider, offset: 0x5A8 */
+ __IO uint32_t AUDPLLPDEC; /**< Audio PLL P divider, offset: 0x5AC */
+ __IO uint32_t AUDPLLMDEC; /**< Audio PLL M divider, offset: 0x5B0 */
+ __IO uint32_t AUDPLLFRAC; /**< Audio PLL fractional divider control, offset: 0x5B4 */
+ uint8_t RESERVED_32[72];
+ __IO uint32_t PDSLEEPCFG[2]; /**< Power configuration register 0, array offset: 0x600, array step: 0x4 */
+ uint8_t RESERVED_33[8];
+ __IO uint32_t PDRUNCFG[2]; /**< Power configuration register 0, array offset: 0x610, array step: 0x4 */
+ uint8_t RESERVED_34[8];
+ __IO uint32_t PDRUNCFGSET[2]; /**< Set bits in PDRUNCFG0, array offset: 0x620, array step: 0x4 */
+ uint8_t RESERVED_35[8];
+ __IO uint32_t PDRUNCFGCLR[2]; /**< Clear bits in PDRUNCFG0, array offset: 0x630, array step: 0x4 */
+ uint8_t RESERVED_36[72];
+ __IO uint32_t STARTER[2]; /**< Start logic 0 wake-up enable register, array offset: 0x680, array step: 0x4 */
+ uint8_t RESERVED_37[24];
+ __O uint32_t STARTERSET[2]; /**< Set bits in STARTER, array offset: 0x6A0, array step: 0x4 */
+ uint8_t RESERVED_38[24];
+ __O uint32_t STARTERCLR[2]; /**< Clear bits in STARTER0, array offset: 0x6C0, array step: 0x4 */
+ uint8_t RESERVED_39[184];
+ __IO uint32_t HWWAKE; /**< Configures special cases of hardware wake-up, offset: 0x780 */
+ uint8_t RESERVED_40[1664];
+ __IO uint32_t AUTOCGOR; /**< Auto Clock-Gate Override Register, offset: 0xE04 */
+ uint8_t RESERVED_41[492];
+ __I uint32_t JTAGIDCODE; /**< JTAG ID code register, offset: 0xFF4 */
+ __I uint32_t DEVICE_ID0; /**< Part ID register, offset: 0xFF8 */
+ __I uint32_t DEVICE_ID1; /**< Boot ROM and die revision register, offset: 0xFFC */
+ uint8_t RESERVED_42[127044];
+ __IO uint32_t BODCTRL; /**< Brown-Out Detect control, offset: 0x20044 */
+} SYSCON_Type;
+
+/* ----------------------------------------------------------------------------
+ -- SYSCON Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SYSCON_Register_Masks SYSCON Register Masks
+ * @{
+ */
+
+/*! @name AHBMATPRIO - AHB multilayer matrix priority control */
+#define SYSCON_AHBMATPRIO_PRI_ICODE_MASK (0x3U)
+#define SYSCON_AHBMATPRIO_PRI_ICODE_SHIFT (0U)
+#define SYSCON_AHBMATPRIO_PRI_ICODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_ICODE_SHIFT)) & SYSCON_AHBMATPRIO_PRI_ICODE_MASK)
+#define SYSCON_AHBMATPRIO_PRI_DCODE_MASK (0xCU)
+#define SYSCON_AHBMATPRIO_PRI_DCODE_SHIFT (2U)
+#define SYSCON_AHBMATPRIO_PRI_DCODE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_DCODE_SHIFT)) & SYSCON_AHBMATPRIO_PRI_DCODE_MASK)
+#define SYSCON_AHBMATPRIO_PRI_SYS_MASK (0x30U)
+#define SYSCON_AHBMATPRIO_PRI_SYS_SHIFT (4U)
+#define SYSCON_AHBMATPRIO_PRI_SYS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SYS_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SYS_MASK)
+#define SYSCON_AHBMATPRIO_PRI_DMA_MASK (0x3C0U)
+#define SYSCON_AHBMATPRIO_PRI_DMA_SHIFT (6U)
+#define SYSCON_AHBMATPRIO_PRI_DMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_DMA_SHIFT)) & SYSCON_AHBMATPRIO_PRI_DMA_MASK)
+#define SYSCON_AHBMATPRIO_PRI_ETH_MASK (0xC00U)
+#define SYSCON_AHBMATPRIO_PRI_ETH_SHIFT (10U)
+#define SYSCON_AHBMATPRIO_PRI_ETH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_ETH_SHIFT)) & SYSCON_AHBMATPRIO_PRI_ETH_MASK)
+#define SYSCON_AHBMATPRIO_PRI_LCD_MASK (0x3000U)
+#define SYSCON_AHBMATPRIO_PRI_LCD_SHIFT (12U)
+#define SYSCON_AHBMATPRIO_PRI_LCD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_LCD_SHIFT)) & SYSCON_AHBMATPRIO_PRI_LCD_MASK)
+#define SYSCON_AHBMATPRIO_PRI_USB0_MASK (0xC000U)
+#define SYSCON_AHBMATPRIO_PRI_USB0_SHIFT (14U)
+#define SYSCON_AHBMATPRIO_PRI_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB0_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB0_MASK)
+#define SYSCON_AHBMATPRIO_PRI_USB1_MASK (0x30000U)
+#define SYSCON_AHBMATPRIO_PRI_USB1_SHIFT (16U)
+#define SYSCON_AHBMATPRIO_PRI_USB1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_USB1_SHIFT)) & SYSCON_AHBMATPRIO_PRI_USB1_MASK)
+#define SYSCON_AHBMATPRIO_PRI_SDIO_MASK (0xC0000U)
+#define SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT (18U)
+#define SYSCON_AHBMATPRIO_PRI_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SDIO_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SDIO_MASK)
+#define SYSCON_AHBMATPRIO_PRI_MCAN1_MASK (0x300000U)
+#define SYSCON_AHBMATPRIO_PRI_MCAN1_SHIFT (20U)
+#define SYSCON_AHBMATPRIO_PRI_MCAN1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_MCAN1_SHIFT)) & SYSCON_AHBMATPRIO_PRI_MCAN1_MASK)
+#define SYSCON_AHBMATPRIO_PRI_MCAN2_MASK (0xC00000U)
+#define SYSCON_AHBMATPRIO_PRI_MCAN2_SHIFT (22U)
+#define SYSCON_AHBMATPRIO_PRI_MCAN2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_MCAN2_SHIFT)) & SYSCON_AHBMATPRIO_PRI_MCAN2_MASK)
+#define SYSCON_AHBMATPRIO_PRI_SHA_MASK (0x3000000U)
+#define SYSCON_AHBMATPRIO_PRI_SHA_SHIFT (24U)
+#define SYSCON_AHBMATPRIO_PRI_SHA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBMATPRIO_PRI_SHA_SHIFT)) & SYSCON_AHBMATPRIO_PRI_SHA_MASK)
+
+/*! @name SYSTCKCAL - System tick counter calibration */
+#define SYSCON_SYSTCKCAL_CAL_MASK (0xFFFFFFU)
+#define SYSCON_SYSTCKCAL_CAL_SHIFT (0U)
+#define SYSCON_SYSTCKCAL_CAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_CAL_SHIFT)) & SYSCON_SYSTCKCAL_CAL_MASK)
+#define SYSCON_SYSTCKCAL_SKEW_MASK (0x1000000U)
+#define SYSCON_SYSTCKCAL_SKEW_SHIFT (24U)
+#define SYSCON_SYSTCKCAL_SKEW(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_SKEW_SHIFT)) & SYSCON_SYSTCKCAL_SKEW_MASK)
+#define SYSCON_SYSTCKCAL_NOREF_MASK (0x2000000U)
+#define SYSCON_SYSTCKCAL_NOREF_SHIFT (25U)
+#define SYSCON_SYSTCKCAL_NOREF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTCKCAL_NOREF_SHIFT)) & SYSCON_SYSTCKCAL_NOREF_MASK)
+
+/*! @name NMISRC - NMI Source Select */
+#define SYSCON_NMISRC_IRQM4_MASK (0x3FU)
+#define SYSCON_NMISRC_IRQM4_SHIFT (0U)
+#define SYSCON_NMISRC_IRQM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_IRQM4_SHIFT)) & SYSCON_NMISRC_IRQM4_MASK)
+#define SYSCON_NMISRC_NMIENM4_MASK (0x80000000U)
+#define SYSCON_NMISRC_NMIENM4_SHIFT (31U)
+#define SYSCON_NMISRC_NMIENM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_NMISRC_NMIENM4_SHIFT)) & SYSCON_NMISRC_NMIENM4_MASK)
+
+/*! @name ASYNCAPBCTRL - Asynchronous APB Control */
+#define SYSCON_ASYNCAPBCTRL_ENABLE_MASK (0x1U)
+#define SYSCON_ASYNCAPBCTRL_ENABLE_SHIFT (0U)
+#define SYSCON_ASYNCAPBCTRL_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ASYNCAPBCTRL_ENABLE_SHIFT)) & SYSCON_ASYNCAPBCTRL_ENABLE_MASK)
+
+/*! @name PIOPORCAP - POR captured value of port n */
+#define SYSCON_PIOPORCAP_PIOPORCAP_MASK (0xFFFFFFFFU)
+#define SYSCON_PIOPORCAP_PIOPORCAP_SHIFT (0U)
+#define SYSCON_PIOPORCAP_PIOPORCAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PIOPORCAP_PIOPORCAP_SHIFT)) & SYSCON_PIOPORCAP_PIOPORCAP_MASK)
+
+/* The count of SYSCON_PIOPORCAP */
+#define SYSCON_PIOPORCAP_COUNT (2U)
+
+/*! @name PIORESCAP - Reset captured value of port n */
+#define SYSCON_PIORESCAP_PIORESCAP_MASK (0xFFFFFFFFU)
+#define SYSCON_PIORESCAP_PIORESCAP_SHIFT (0U)
+#define SYSCON_PIORESCAP_PIORESCAP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PIORESCAP_PIORESCAP_SHIFT)) & SYSCON_PIORESCAP_PIORESCAP_MASK)
+
+/* The count of SYSCON_PIORESCAP */
+#define SYSCON_PIORESCAP_COUNT (2U)
+
+/*! @name PRESETCTRL - Peripheral reset control n */
+#define SYSCON_PRESETCTRL_MRT_RST_MASK (0x1U)
+#define SYSCON_PRESETCTRL_MRT_RST_SHIFT (0U)
+#define SYSCON_PRESETCTRL_MRT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MRT_RST_SHIFT)) & SYSCON_PRESETCTRL_MRT_RST_MASK)
+#define SYSCON_PRESETCTRL_SCT0_RST_MASK (0x4U)
+#define SYSCON_PRESETCTRL_SCT0_RST_SHIFT (2U)
+#define SYSCON_PRESETCTRL_SCT0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SCT0_RST_SHIFT)) & SYSCON_PRESETCTRL_SCT0_RST_MASK)
+#define SYSCON_PRESETCTRL_LCD_RST_MASK (0x4U)
+#define SYSCON_PRESETCTRL_LCD_RST_SHIFT (2U)
+#define SYSCON_PRESETCTRL_LCD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_LCD_RST_SHIFT)) & SYSCON_PRESETCTRL_LCD_RST_MASK)
+#define SYSCON_PRESETCTRL_SDIO_RST_MASK (0x8U)
+#define SYSCON_PRESETCTRL_SDIO_RST_SHIFT (3U)
+#define SYSCON_PRESETCTRL_SDIO_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SDIO_RST_SHIFT)) & SYSCON_PRESETCTRL_SDIO_RST_MASK)
+#define SYSCON_PRESETCTRL_USB1H_RST_MASK (0x10U)
+#define SYSCON_PRESETCTRL_USB1H_RST_SHIFT (4U)
+#define SYSCON_PRESETCTRL_USB1H_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB1H_RST_SHIFT)) & SYSCON_PRESETCTRL_USB1H_RST_MASK)
+#define SYSCON_PRESETCTRL_USB1D_RST_MASK (0x20U)
+#define SYSCON_PRESETCTRL_USB1D_RST_SHIFT (5U)
+#define SYSCON_PRESETCTRL_USB1D_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB1D_RST_SHIFT)) & SYSCON_PRESETCTRL_USB1D_RST_MASK)
+#define SYSCON_PRESETCTRL_USB1RAM_RST_MASK (0x40U)
+#define SYSCON_PRESETCTRL_USB1RAM_RST_SHIFT (6U)
+#define SYSCON_PRESETCTRL_USB1RAM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB1RAM_RST_SHIFT)) & SYSCON_PRESETCTRL_USB1RAM_RST_MASK)
+#define SYSCON_PRESETCTRL_EMC_RESET_MASK (0x80U)
+#define SYSCON_PRESETCTRL_EMC_RESET_SHIFT (7U)
+#define SYSCON_PRESETCTRL_EMC_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_EMC_RESET_SHIFT)) & SYSCON_PRESETCTRL_EMC_RESET_MASK)
+#define SYSCON_PRESETCTRL_FLASH_RST_MASK (0x80U)
+#define SYSCON_PRESETCTRL_FLASH_RST_SHIFT (7U)
+#define SYSCON_PRESETCTRL_FLASH_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FLASH_RST_SHIFT)) & SYSCON_PRESETCTRL_FLASH_RST_MASK)
+#define SYSCON_PRESETCTRL_MCAN0_RST_MASK (0x80U)
+#define SYSCON_PRESETCTRL_MCAN0_RST_SHIFT (7U)
+#define SYSCON_PRESETCTRL_MCAN0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MCAN0_RST_SHIFT)) & SYSCON_PRESETCTRL_MCAN0_RST_MASK)
+#define SYSCON_PRESETCTRL_FMC_RST_MASK (0x100U)
+#define SYSCON_PRESETCTRL_FMC_RST_SHIFT (8U)
+#define SYSCON_PRESETCTRL_FMC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FMC_RST_SHIFT)) & SYSCON_PRESETCTRL_FMC_RST_MASK)
+#define SYSCON_PRESETCTRL_ETH_RST_MASK (0x100U)
+#define SYSCON_PRESETCTRL_ETH_RST_SHIFT (8U)
+#define SYSCON_PRESETCTRL_ETH_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_ETH_RST_SHIFT)) & SYSCON_PRESETCTRL_ETH_RST_MASK)
+#define SYSCON_PRESETCTRL_MCAN1_RST_MASK (0x100U)
+#define SYSCON_PRESETCTRL_MCAN1_RST_SHIFT (8U)
+#define SYSCON_PRESETCTRL_MCAN1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MCAN1_RST_SHIFT)) & SYSCON_PRESETCTRL_MCAN1_RST_MASK)
+#define SYSCON_PRESETCTRL_GPIO4_RST_MASK (0x200U)
+#define SYSCON_PRESETCTRL_GPIO4_RST_SHIFT (9U)
+#define SYSCON_PRESETCTRL_GPIO4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO4_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO4_RST_MASK)
+#define SYSCON_PRESETCTRL_EEPROM_RST_MASK (0x200U)
+#define SYSCON_PRESETCTRL_EEPROM_RST_SHIFT (9U)
+#define SYSCON_PRESETCTRL_EEPROM_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_EEPROM_RST_SHIFT)) & SYSCON_PRESETCTRL_EEPROM_RST_MASK)
+#define SYSCON_PRESETCTRL_GPIO5_RST_MASK (0x400U)
+#define SYSCON_PRESETCTRL_GPIO5_RST_SHIFT (10U)
+#define SYSCON_PRESETCTRL_GPIO5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO5_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO5_RST_MASK)
+#define SYSCON_PRESETCTRL_UTICK_RST_MASK (0x400U)
+#define SYSCON_PRESETCTRL_UTICK_RST_SHIFT (10U)
+#define SYSCON_PRESETCTRL_UTICK_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_UTICK_RST_SHIFT)) & SYSCON_PRESETCTRL_UTICK_RST_MASK)
+#define SYSCON_PRESETCTRL_SPIFI_RST_MASK (0x400U)
+#define SYSCON_PRESETCTRL_SPIFI_RST_SHIFT (10U)
+#define SYSCON_PRESETCTRL_SPIFI_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SPIFI_RST_SHIFT)) & SYSCON_PRESETCTRL_SPIFI_RST_MASK)
+#define SYSCON_PRESETCTRL_AES_RST_MASK (0x800U)
+#define SYSCON_PRESETCTRL_AES_RST_SHIFT (11U)
+#define SYSCON_PRESETCTRL_AES_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_AES_RST_SHIFT)) & SYSCON_PRESETCTRL_AES_RST_MASK)
+#define SYSCON_PRESETCTRL_MUX_RST_MASK (0x800U)
+#define SYSCON_PRESETCTRL_MUX_RST_SHIFT (11U)
+#define SYSCON_PRESETCTRL_MUX_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_MUX_RST_SHIFT)) & SYSCON_PRESETCTRL_MUX_RST_MASK)
+#define SYSCON_PRESETCTRL_FC0_RST_MASK (0x800U)
+#define SYSCON_PRESETCTRL_FC0_RST_SHIFT (11U)
+#define SYSCON_PRESETCTRL_FC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC0_RST_SHIFT)) & SYSCON_PRESETCTRL_FC0_RST_MASK)
+#define SYSCON_PRESETCTRL_OTP_RST_MASK (0x1000U)
+#define SYSCON_PRESETCTRL_OTP_RST_SHIFT (12U)
+#define SYSCON_PRESETCTRL_OTP_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_OTP_RST_SHIFT)) & SYSCON_PRESETCTRL_OTP_RST_MASK)
+#define SYSCON_PRESETCTRL_FC1_RST_MASK (0x1000U)
+#define SYSCON_PRESETCTRL_FC1_RST_SHIFT (12U)
+#define SYSCON_PRESETCTRL_FC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC1_RST_SHIFT)) & SYSCON_PRESETCTRL_FC1_RST_MASK)
+#define SYSCON_PRESETCTRL_IOCON_RST_MASK (0x2000U)
+#define SYSCON_PRESETCTRL_IOCON_RST_SHIFT (13U)
+#define SYSCON_PRESETCTRL_IOCON_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_IOCON_RST_SHIFT)) & SYSCON_PRESETCTRL_IOCON_RST_MASK)
+#define SYSCON_PRESETCTRL_RNG_RST_MASK (0x2000U)
+#define SYSCON_PRESETCTRL_RNG_RST_SHIFT (13U)
+#define SYSCON_PRESETCTRL_RNG_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_RNG_RST_SHIFT)) & SYSCON_PRESETCTRL_RNG_RST_MASK)
+#define SYSCON_PRESETCTRL_FC2_RST_MASK (0x2000U)
+#define SYSCON_PRESETCTRL_FC2_RST_SHIFT (13U)
+#define SYSCON_PRESETCTRL_FC2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC2_RST_SHIFT)) & SYSCON_PRESETCTRL_FC2_RST_MASK)
+#define SYSCON_PRESETCTRL_FC8_RST_MASK (0x4000U)
+#define SYSCON_PRESETCTRL_FC8_RST_SHIFT (14U)
+#define SYSCON_PRESETCTRL_FC8_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC8_RST_SHIFT)) & SYSCON_PRESETCTRL_FC8_RST_MASK)
+#define SYSCON_PRESETCTRL_FC3_RST_MASK (0x4000U)
+#define SYSCON_PRESETCTRL_FC3_RST_SHIFT (14U)
+#define SYSCON_PRESETCTRL_FC3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC3_RST_SHIFT)) & SYSCON_PRESETCTRL_FC3_RST_MASK)
+#define SYSCON_PRESETCTRL_GPIO0_RST_MASK (0x4000U)
+#define SYSCON_PRESETCTRL_GPIO0_RST_SHIFT (14U)
+#define SYSCON_PRESETCTRL_GPIO0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO0_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO0_RST_MASK)
+#define SYSCON_PRESETCTRL_GPIO1_RST_MASK (0x8000U)
+#define SYSCON_PRESETCTRL_GPIO1_RST_SHIFT (15U)
+#define SYSCON_PRESETCTRL_GPIO1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO1_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO1_RST_MASK)
+#define SYSCON_PRESETCTRL_FC9_RST_MASK (0x8000U)
+#define SYSCON_PRESETCTRL_FC9_RST_SHIFT (15U)
+#define SYSCON_PRESETCTRL_FC9_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC9_RST_SHIFT)) & SYSCON_PRESETCTRL_FC9_RST_MASK)
+#define SYSCON_PRESETCTRL_FC4_RST_MASK (0x8000U)
+#define SYSCON_PRESETCTRL_FC4_RST_SHIFT (15U)
+#define SYSCON_PRESETCTRL_FC4_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC4_RST_SHIFT)) & SYSCON_PRESETCTRL_FC4_RST_MASK)
+#define SYSCON_PRESETCTRL_USB0HMR_RST_MASK (0x10000U)
+#define SYSCON_PRESETCTRL_USB0HMR_RST_SHIFT (16U)
+#define SYSCON_PRESETCTRL_USB0HMR_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB0HMR_RST_SHIFT)) & SYSCON_PRESETCTRL_USB0HMR_RST_MASK)
+#define SYSCON_PRESETCTRL_GPIO2_RST_MASK (0x10000U)
+#define SYSCON_PRESETCTRL_GPIO2_RST_SHIFT (16U)
+#define SYSCON_PRESETCTRL_GPIO2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO2_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO2_RST_MASK)
+#define SYSCON_PRESETCTRL_FC5_RST_MASK (0x10000U)
+#define SYSCON_PRESETCTRL_FC5_RST_SHIFT (16U)
+#define SYSCON_PRESETCTRL_FC5_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC5_RST_SHIFT)) & SYSCON_PRESETCTRL_FC5_RST_MASK)
+#define SYSCON_PRESETCTRL_GPIO3_RST_MASK (0x20000U)
+#define SYSCON_PRESETCTRL_GPIO3_RST_SHIFT (17U)
+#define SYSCON_PRESETCTRL_GPIO3_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GPIO3_RST_SHIFT)) & SYSCON_PRESETCTRL_GPIO3_RST_MASK)
+#define SYSCON_PRESETCTRL_FC6_RST_MASK (0x20000U)
+#define SYSCON_PRESETCTRL_FC6_RST_SHIFT (17U)
+#define SYSCON_PRESETCTRL_FC6_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC6_RST_SHIFT)) & SYSCON_PRESETCTRL_FC6_RST_MASK)
+#define SYSCON_PRESETCTRL_USB0HSL_RST_MASK (0x20000U)
+#define SYSCON_PRESETCTRL_USB0HSL_RST_SHIFT (17U)
+#define SYSCON_PRESETCTRL_USB0HSL_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB0HSL_RST_SHIFT)) & SYSCON_PRESETCTRL_USB0HSL_RST_MASK)
+#define SYSCON_PRESETCTRL_FC7_RST_MASK (0x40000U)
+#define SYSCON_PRESETCTRL_FC7_RST_SHIFT (18U)
+#define SYSCON_PRESETCTRL_FC7_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_FC7_RST_SHIFT)) & SYSCON_PRESETCTRL_FC7_RST_MASK)
+#define SYSCON_PRESETCTRL_SHA_RST_MASK (0x40000U)
+#define SYSCON_PRESETCTRL_SHA_RST_SHIFT (18U)
+#define SYSCON_PRESETCTRL_SHA_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SHA_RST_SHIFT)) & SYSCON_PRESETCTRL_SHA_RST_MASK)
+#define SYSCON_PRESETCTRL_PINT_RST_MASK (0x40000U)
+#define SYSCON_PRESETCTRL_PINT_RST_SHIFT (18U)
+#define SYSCON_PRESETCTRL_PINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_PINT_RST_SHIFT)) & SYSCON_PRESETCTRL_PINT_RST_MASK)
+#define SYSCON_PRESETCTRL_DMIC_RST_MASK (0x80000U)
+#define SYSCON_PRESETCTRL_DMIC_RST_SHIFT (19U)
+#define SYSCON_PRESETCTRL_DMIC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_DMIC_RST_SHIFT)) & SYSCON_PRESETCTRL_DMIC_RST_MASK)
+#define SYSCON_PRESETCTRL_SC0_RST_MASK (0x80000U)
+#define SYSCON_PRESETCTRL_SC0_RST_SHIFT (19U)
+#define SYSCON_PRESETCTRL_SC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SC0_RST_SHIFT)) & SYSCON_PRESETCTRL_SC0_RST_MASK)
+#define SYSCON_PRESETCTRL_GINT_RST_MASK (0x80000U)
+#define SYSCON_PRESETCTRL_GINT_RST_SHIFT (19U)
+#define SYSCON_PRESETCTRL_GINT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_GINT_RST_SHIFT)) & SYSCON_PRESETCTRL_GINT_RST_MASK)
+#define SYSCON_PRESETCTRL_SC1_RST_MASK (0x100000U)
+#define SYSCON_PRESETCTRL_SC1_RST_SHIFT (20U)
+#define SYSCON_PRESETCTRL_SC1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_SC1_RST_SHIFT)) & SYSCON_PRESETCTRL_SC1_RST_MASK)
+#define SYSCON_PRESETCTRL_DMA0_RST_MASK (0x100000U)
+#define SYSCON_PRESETCTRL_DMA0_RST_SHIFT (20U)
+#define SYSCON_PRESETCTRL_DMA0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_DMA0_RST_SHIFT)) & SYSCON_PRESETCTRL_DMA0_RST_MASK)
+#define SYSCON_PRESETCTRL_CRC_RST_MASK (0x200000U)
+#define SYSCON_PRESETCTRL_CRC_RST_SHIFT (21U)
+#define SYSCON_PRESETCTRL_CRC_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CRC_RST_SHIFT)) & SYSCON_PRESETCTRL_CRC_RST_MASK)
+#define SYSCON_PRESETCTRL_CTIMER2_RST_MASK (0x400000U)
+#define SYSCON_PRESETCTRL_CTIMER2_RST_SHIFT (22U)
+#define SYSCON_PRESETCTRL_CTIMER2_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER2_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER2_RST_MASK)
+#define SYSCON_PRESETCTRL_WWDT_RST_MASK (0x400000U)
+#define SYSCON_PRESETCTRL_WWDT_RST_SHIFT (22U)
+#define SYSCON_PRESETCTRL_WWDT_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_WWDT_RST_SHIFT)) & SYSCON_PRESETCTRL_WWDT_RST_MASK)
+#define SYSCON_PRESETCTRL_USB0D_RST_MASK (0x2000000U)
+#define SYSCON_PRESETCTRL_USB0D_RST_SHIFT (25U)
+#define SYSCON_PRESETCTRL_USB0D_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_USB0D_RST_SHIFT)) & SYSCON_PRESETCTRL_USB0D_RST_MASK)
+#define SYSCON_PRESETCTRL_CTIMER0_RST_MASK (0x4000000U)
+#define SYSCON_PRESETCTRL_CTIMER0_RST_SHIFT (26U)
+#define SYSCON_PRESETCTRL_CTIMER0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER0_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER0_RST_MASK)
+#define SYSCON_PRESETCTRL_ADC0_RST_MASK (0x8000000U)
+#define SYSCON_PRESETCTRL_ADC0_RST_SHIFT (27U)
+#define SYSCON_PRESETCTRL_ADC0_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_ADC0_RST_SHIFT)) & SYSCON_PRESETCTRL_ADC0_RST_MASK)
+#define SYSCON_PRESETCTRL_CTIMER1_RST_MASK (0x8000000U)
+#define SYSCON_PRESETCTRL_CTIMER1_RST_SHIFT (27U)
+#define SYSCON_PRESETCTRL_CTIMER1_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRL_CTIMER1_RST_SHIFT)) & SYSCON_PRESETCTRL_CTIMER1_RST_MASK)
+
+/* The count of SYSCON_PRESETCTRL */
+#define SYSCON_PRESETCTRL_COUNT (3U)
+
+/*! @name PRESETCTRLSET - Set bits in PRESETCTRLn */
+#define SYSCON_PRESETCTRLSET_RST_SET_MASK (0xFFFFFFFFU)
+#define SYSCON_PRESETCTRLSET_RST_SET_SHIFT (0U)
+#define SYSCON_PRESETCTRLSET_RST_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLSET_RST_SET_SHIFT)) & SYSCON_PRESETCTRLSET_RST_SET_MASK)
+
+/* The count of SYSCON_PRESETCTRLSET */
+#define SYSCON_PRESETCTRLSET_COUNT (3U)
+
+/*! @name PRESETCTRLCLR - Clear bits in PRESETCTRLn */
+#define SYSCON_PRESETCTRLCLR_RST_CLR_MASK (0xFFFFFFFFU)
+#define SYSCON_PRESETCTRLCLR_RST_CLR_SHIFT (0U)
+#define SYSCON_PRESETCTRLCLR_RST_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PRESETCTRLCLR_RST_CLR_SHIFT)) & SYSCON_PRESETCTRLCLR_RST_CLR_MASK)
+
+/* The count of SYSCON_PRESETCTRLCLR */
+#define SYSCON_PRESETCTRLCLR_COUNT (3U)
+
+/*! @name SYSRSTSTAT - System reset status register */
+#define SYSCON_SYSRSTSTAT_POR_MASK (0x1U)
+#define SYSCON_SYSRSTSTAT_POR_SHIFT (0U)
+#define SYSCON_SYSRSTSTAT_POR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_POR_SHIFT)) & SYSCON_SYSRSTSTAT_POR_MASK)
+#define SYSCON_SYSRSTSTAT_EXTRST_MASK (0x2U)
+#define SYSCON_SYSRSTSTAT_EXTRST_SHIFT (1U)
+#define SYSCON_SYSRSTSTAT_EXTRST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_EXTRST_SHIFT)) & SYSCON_SYSRSTSTAT_EXTRST_MASK)
+#define SYSCON_SYSRSTSTAT_WDT_MASK (0x4U)
+#define SYSCON_SYSRSTSTAT_WDT_SHIFT (2U)
+#define SYSCON_SYSRSTSTAT_WDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_WDT_SHIFT)) & SYSCON_SYSRSTSTAT_WDT_MASK)
+#define SYSCON_SYSRSTSTAT_BOD_MASK (0x8U)
+#define SYSCON_SYSRSTSTAT_BOD_SHIFT (3U)
+#define SYSCON_SYSRSTSTAT_BOD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_BOD_SHIFT)) & SYSCON_SYSRSTSTAT_BOD_MASK)
+#define SYSCON_SYSRSTSTAT_SYSRST_MASK (0x10U)
+#define SYSCON_SYSRSTSTAT_SYSRST_SHIFT (4U)
+#define SYSCON_SYSRSTSTAT_SYSRST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSRSTSTAT_SYSRST_SHIFT)) & SYSCON_SYSRSTSTAT_SYSRST_MASK)
+
+/*! @name AHBCLKCTRL - AHB Clock control n */
+#define SYSCON_AHBCLKCTRL_MRT_MASK (0x1U)
+#define SYSCON_AHBCLKCTRL_MRT_SHIFT (0U)
+#define SYSCON_AHBCLKCTRL_MRT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MRT_SHIFT)) & SYSCON_AHBCLKCTRL_MRT_MASK)
+#define SYSCON_AHBCLKCTRL_RIT_MASK (0x2U)
+#define SYSCON_AHBCLKCTRL_RIT_SHIFT (1U)
+#define SYSCON_AHBCLKCTRL_RIT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_RIT_SHIFT)) & SYSCON_AHBCLKCTRL_RIT_MASK)
+#define SYSCON_AHBCLKCTRL_ROM_MASK (0x2U)
+#define SYSCON_AHBCLKCTRL_ROM_SHIFT (1U)
+#define SYSCON_AHBCLKCTRL_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ROM_SHIFT)) & SYSCON_AHBCLKCTRL_ROM_MASK)
+#define SYSCON_AHBCLKCTRL_SCT0_MASK (0x4U)
+#define SYSCON_AHBCLKCTRL_SCT0_SHIFT (2U)
+#define SYSCON_AHBCLKCTRL_SCT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SCT0_SHIFT)) & SYSCON_AHBCLKCTRL_SCT0_MASK)
+#define SYSCON_AHBCLKCTRL_LCD_MASK (0x4U)
+#define SYSCON_AHBCLKCTRL_LCD_SHIFT (2U)
+#define SYSCON_AHBCLKCTRL_LCD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_LCD_SHIFT)) & SYSCON_AHBCLKCTRL_LCD_MASK)
+#define SYSCON_AHBCLKCTRL_SRAM1_MASK (0x8U)
+#define SYSCON_AHBCLKCTRL_SRAM1_SHIFT (3U)
+#define SYSCON_AHBCLKCTRL_SRAM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM1_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM1_MASK)
+#define SYSCON_AHBCLKCTRL_SDIO_MASK (0x8U)
+#define SYSCON_AHBCLKCTRL_SDIO_SHIFT (3U)
+#define SYSCON_AHBCLKCTRL_SDIO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SDIO_SHIFT)) & SYSCON_AHBCLKCTRL_SDIO_MASK)
+#define SYSCON_AHBCLKCTRL_SRAM2_MASK (0x10U)
+#define SYSCON_AHBCLKCTRL_SRAM2_SHIFT (4U)
+#define SYSCON_AHBCLKCTRL_SRAM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM2_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM2_MASK)
+#define SYSCON_AHBCLKCTRL_USB1H_MASK (0x10U)
+#define SYSCON_AHBCLKCTRL_USB1H_SHIFT (4U)
+#define SYSCON_AHBCLKCTRL_USB1H(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB1H_SHIFT)) & SYSCON_AHBCLKCTRL_USB1H_MASK)
+#define SYSCON_AHBCLKCTRL_SRAM3_MASK (0x20U)
+#define SYSCON_AHBCLKCTRL_SRAM3_SHIFT (5U)
+#define SYSCON_AHBCLKCTRL_SRAM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SRAM3_SHIFT)) & SYSCON_AHBCLKCTRL_SRAM3_MASK)
+#define SYSCON_AHBCLKCTRL_USB1D_MASK (0x20U)
+#define SYSCON_AHBCLKCTRL_USB1D_SHIFT (5U)
+#define SYSCON_AHBCLKCTRL_USB1D(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB1D_SHIFT)) & SYSCON_AHBCLKCTRL_USB1D_MASK)
+#define SYSCON_AHBCLKCTRL_USB1RAM_MASK (0x40U)
+#define SYSCON_AHBCLKCTRL_USB1RAM_SHIFT (6U)
+#define SYSCON_AHBCLKCTRL_USB1RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB1RAM_SHIFT)) & SYSCON_AHBCLKCTRL_USB1RAM_MASK)
+#define SYSCON_AHBCLKCTRL_FLASH_MASK (0x80U)
+#define SYSCON_AHBCLKCTRL_FLASH_SHIFT (7U)
+#define SYSCON_AHBCLKCTRL_FLASH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLASH_SHIFT)) & SYSCON_AHBCLKCTRL_FLASH_MASK)
+#define SYSCON_AHBCLKCTRL_EMC_MASK (0x80U)
+#define SYSCON_AHBCLKCTRL_EMC_SHIFT (7U)
+#define SYSCON_AHBCLKCTRL_EMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_EMC_SHIFT)) & SYSCON_AHBCLKCTRL_EMC_MASK)
+#define SYSCON_AHBCLKCTRL_MCAN0_MASK (0x80U)
+#define SYSCON_AHBCLKCTRL_MCAN0_SHIFT (7U)
+#define SYSCON_AHBCLKCTRL_MCAN0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MCAN0_SHIFT)) & SYSCON_AHBCLKCTRL_MCAN0_MASK)
+#define SYSCON_AHBCLKCTRL_FMC_MASK (0x100U)
+#define SYSCON_AHBCLKCTRL_FMC_SHIFT (8U)
+#define SYSCON_AHBCLKCTRL_FMC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FMC_SHIFT)) & SYSCON_AHBCLKCTRL_FMC_MASK)
+#define SYSCON_AHBCLKCTRL_ETH_MASK (0x100U)
+#define SYSCON_AHBCLKCTRL_ETH_SHIFT (8U)
+#define SYSCON_AHBCLKCTRL_ETH(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ETH_SHIFT)) & SYSCON_AHBCLKCTRL_ETH_MASK)
+#define SYSCON_AHBCLKCTRL_MCAN1_MASK (0x100U)
+#define SYSCON_AHBCLKCTRL_MCAN1_SHIFT (8U)
+#define SYSCON_AHBCLKCTRL_MCAN1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_MCAN1_SHIFT)) & SYSCON_AHBCLKCTRL_MCAN1_MASK)
+#define SYSCON_AHBCLKCTRL_EEPROM_MASK (0x200U)
+#define SYSCON_AHBCLKCTRL_EEPROM_SHIFT (9U)
+#define SYSCON_AHBCLKCTRL_EEPROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_EEPROM_SHIFT)) & SYSCON_AHBCLKCTRL_EEPROM_MASK)
+#define SYSCON_AHBCLKCTRL_GPIO4_MASK (0x200U)
+#define SYSCON_AHBCLKCTRL_GPIO4_SHIFT (9U)
+#define SYSCON_AHBCLKCTRL_GPIO4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO4_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO4_MASK)
+#define SYSCON_AHBCLKCTRL_GPIO5_MASK (0x400U)
+#define SYSCON_AHBCLKCTRL_GPIO5_SHIFT (10U)
+#define SYSCON_AHBCLKCTRL_GPIO5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO5_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO5_MASK)
+#define SYSCON_AHBCLKCTRL_UTICK_MASK (0x400U)
+#define SYSCON_AHBCLKCTRL_UTICK_SHIFT (10U)
+#define SYSCON_AHBCLKCTRL_UTICK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_UTICK_SHIFT)) & SYSCON_AHBCLKCTRL_UTICK_MASK)
+#define SYSCON_AHBCLKCTRL_SPIFI_MASK (0x400U)
+#define SYSCON_AHBCLKCTRL_SPIFI_SHIFT (10U)
+#define SYSCON_AHBCLKCTRL_SPIFI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SPIFI_SHIFT)) & SYSCON_AHBCLKCTRL_SPIFI_MASK)
+#define SYSCON_AHBCLKCTRL_INPUTMUX_MASK (0x800U)
+#define SYSCON_AHBCLKCTRL_INPUTMUX_SHIFT (11U)
+#define SYSCON_AHBCLKCTRL_INPUTMUX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_INPUTMUX_SHIFT)) & SYSCON_AHBCLKCTRL_INPUTMUX_MASK)
+#define SYSCON_AHBCLKCTRL_AES_MASK (0x800U)
+#define SYSCON_AHBCLKCTRL_AES_SHIFT (11U)
+#define SYSCON_AHBCLKCTRL_AES(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_AES_SHIFT)) & SYSCON_AHBCLKCTRL_AES_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM0_MASK (0x800U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM0_SHIFT (11U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM0_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM0_MASK)
+#define SYSCON_AHBCLKCTRL_OTP_MASK (0x1000U)
+#define SYSCON_AHBCLKCTRL_OTP_SHIFT (12U)
+#define SYSCON_AHBCLKCTRL_OTP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_OTP_SHIFT)) & SYSCON_AHBCLKCTRL_OTP_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM1_MASK (0x1000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM1_SHIFT (12U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM1_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM1_MASK)
+#define SYSCON_AHBCLKCTRL_RNG_MASK (0x2000U)
+#define SYSCON_AHBCLKCTRL_RNG_SHIFT (13U)
+#define SYSCON_AHBCLKCTRL_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_RNG_SHIFT)) & SYSCON_AHBCLKCTRL_RNG_MASK)
+#define SYSCON_AHBCLKCTRL_IOCON_MASK (0x2000U)
+#define SYSCON_AHBCLKCTRL_IOCON_SHIFT (13U)
+#define SYSCON_AHBCLKCTRL_IOCON(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_IOCON_SHIFT)) & SYSCON_AHBCLKCTRL_IOCON_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM2_MASK (0x2000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM2_SHIFT (13U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM2_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM2_MASK)
+#define SYSCON_AHBCLKCTRL_GPIO0_MASK (0x4000U)
+#define SYSCON_AHBCLKCTRL_GPIO0_SHIFT (14U)
+#define SYSCON_AHBCLKCTRL_GPIO0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO0_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO0_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM3_MASK (0x4000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM3_SHIFT (14U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM3_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM3_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM8_MASK (0x4000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM8_SHIFT (14U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM8(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM8_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM8_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM9_MASK (0x8000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM9_SHIFT (15U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM9(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM9_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM9_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM4_MASK (0x8000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM4_SHIFT (15U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM4_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM4_MASK)
+#define SYSCON_AHBCLKCTRL_GPIO1_MASK (0x8000U)
+#define SYSCON_AHBCLKCTRL_GPIO1_SHIFT (15U)
+#define SYSCON_AHBCLKCTRL_GPIO1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO1_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO1_MASK)
+#define SYSCON_AHBCLKCTRL_GPIO2_MASK (0x10000U)
+#define SYSCON_AHBCLKCTRL_GPIO2_SHIFT (16U)
+#define SYSCON_AHBCLKCTRL_GPIO2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO2_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO2_MASK)
+#define SYSCON_AHBCLKCTRL_USB0HMR_MASK (0x10000U)
+#define SYSCON_AHBCLKCTRL_USB0HMR_SHIFT (16U)
+#define SYSCON_AHBCLKCTRL_USB0HMR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB0HMR_SHIFT)) & SYSCON_AHBCLKCTRL_USB0HMR_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM5_MASK (0x10000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM5_SHIFT (16U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM5_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM5_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM6_MASK (0x20000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM6_SHIFT (17U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM6_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM6_MASK)
+#define SYSCON_AHBCLKCTRL_GPIO3_MASK (0x20000U)
+#define SYSCON_AHBCLKCTRL_GPIO3_SHIFT (17U)
+#define SYSCON_AHBCLKCTRL_GPIO3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GPIO3_SHIFT)) & SYSCON_AHBCLKCTRL_GPIO3_MASK)
+#define SYSCON_AHBCLKCTRL_USB0HSL_MASK (0x20000U)
+#define SYSCON_AHBCLKCTRL_USB0HSL_SHIFT (17U)
+#define SYSCON_AHBCLKCTRL_USB0HSL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB0HSL_SHIFT)) & SYSCON_AHBCLKCTRL_USB0HSL_MASK)
+#define SYSCON_AHBCLKCTRL_PINT_MASK (0x40000U)
+#define SYSCON_AHBCLKCTRL_PINT_SHIFT (18U)
+#define SYSCON_AHBCLKCTRL_PINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_PINT_SHIFT)) & SYSCON_AHBCLKCTRL_PINT_MASK)
+#define SYSCON_AHBCLKCTRL_SHA0_MASK (0x40000U)
+#define SYSCON_AHBCLKCTRL_SHA0_SHIFT (18U)
+#define SYSCON_AHBCLKCTRL_SHA0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SHA0_SHIFT)) & SYSCON_AHBCLKCTRL_SHA0_MASK)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM7_MASK (0x40000U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM7_SHIFT (18U)
+#define SYSCON_AHBCLKCTRL_FLEXCOMM7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_FLEXCOMM7_SHIFT)) & SYSCON_AHBCLKCTRL_FLEXCOMM7_MASK)
+#define SYSCON_AHBCLKCTRL_DMIC_MASK (0x80000U)
+#define SYSCON_AHBCLKCTRL_DMIC_SHIFT (19U)
+#define SYSCON_AHBCLKCTRL_DMIC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_DMIC_SHIFT)) & SYSCON_AHBCLKCTRL_DMIC_MASK)
+#define SYSCON_AHBCLKCTRL_GINT_MASK (0x80000U)
+#define SYSCON_AHBCLKCTRL_GINT_SHIFT (19U)
+#define SYSCON_AHBCLKCTRL_GINT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_GINT_SHIFT)) & SYSCON_AHBCLKCTRL_GINT_MASK)
+#define SYSCON_AHBCLKCTRL_SC0_MASK (0x80000U)
+#define SYSCON_AHBCLKCTRL_SC0_SHIFT (19U)
+#define SYSCON_AHBCLKCTRL_SC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SC0_SHIFT)) & SYSCON_AHBCLKCTRL_SC0_MASK)
+#define SYSCON_AHBCLKCTRL_SC1_MASK (0x100000U)
+#define SYSCON_AHBCLKCTRL_SC1_SHIFT (20U)
+#define SYSCON_AHBCLKCTRL_SC1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_SC1_SHIFT)) & SYSCON_AHBCLKCTRL_SC1_MASK)
+#define SYSCON_AHBCLKCTRL_DMA_MASK (0x100000U)
+#define SYSCON_AHBCLKCTRL_DMA_SHIFT (20U)
+#define SYSCON_AHBCLKCTRL_DMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_DMA_SHIFT)) & SYSCON_AHBCLKCTRL_DMA_MASK)
+#define SYSCON_AHBCLKCTRL_CRC_MASK (0x200000U)
+#define SYSCON_AHBCLKCTRL_CRC_SHIFT (21U)
+#define SYSCON_AHBCLKCTRL_CRC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CRC_SHIFT)) & SYSCON_AHBCLKCTRL_CRC_MASK)
+#define SYSCON_AHBCLKCTRL_WWDT_MASK (0x400000U)
+#define SYSCON_AHBCLKCTRL_WWDT_SHIFT (22U)
+#define SYSCON_AHBCLKCTRL_WWDT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_WWDT_SHIFT)) & SYSCON_AHBCLKCTRL_WWDT_MASK)
+#define SYSCON_AHBCLKCTRL_CTIMER2_MASK (0x400000U)
+#define SYSCON_AHBCLKCTRL_CTIMER2_SHIFT (22U)
+#define SYSCON_AHBCLKCTRL_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER2_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER2_MASK)
+#define SYSCON_AHBCLKCTRL_RTC_MASK (0x800000U)
+#define SYSCON_AHBCLKCTRL_RTC_SHIFT (23U)
+#define SYSCON_AHBCLKCTRL_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_RTC_SHIFT)) & SYSCON_AHBCLKCTRL_RTC_MASK)
+#define SYSCON_AHBCLKCTRL_USB0D_MASK (0x2000000U)
+#define SYSCON_AHBCLKCTRL_USB0D_SHIFT (25U)
+#define SYSCON_AHBCLKCTRL_USB0D(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_USB0D_SHIFT)) & SYSCON_AHBCLKCTRL_USB0D_MASK)
+#define SYSCON_AHBCLKCTRL_CTIMER0_MASK (0x4000000U)
+#define SYSCON_AHBCLKCTRL_CTIMER0_SHIFT (26U)
+#define SYSCON_AHBCLKCTRL_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER0_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER0_MASK)
+#define SYSCON_AHBCLKCTRL_CTIMER1_MASK (0x8000000U)
+#define SYSCON_AHBCLKCTRL_CTIMER1_SHIFT (27U)
+#define SYSCON_AHBCLKCTRL_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_CTIMER1_SHIFT)) & SYSCON_AHBCLKCTRL_CTIMER1_MASK)
+#define SYSCON_AHBCLKCTRL_ADC0_MASK (0x8000000U)
+#define SYSCON_AHBCLKCTRL_ADC0_SHIFT (27U)
+#define SYSCON_AHBCLKCTRL_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRL_ADC0_SHIFT)) & SYSCON_AHBCLKCTRL_ADC0_MASK)
+
+/* The count of SYSCON_AHBCLKCTRL */
+#define SYSCON_AHBCLKCTRL_COUNT (3U)
+
+/*! @name AHBCLKCTRLSET - Set bits in AHBCLKCTRLn */
+#define SYSCON_AHBCLKCTRLSET_CLK_SET_MASK (0xFFFFFFFFU)
+#define SYSCON_AHBCLKCTRLSET_CLK_SET_SHIFT (0U)
+#define SYSCON_AHBCLKCTRLSET_CLK_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLSET_CLK_SET_SHIFT)) & SYSCON_AHBCLKCTRLSET_CLK_SET_MASK)
+
+/* The count of SYSCON_AHBCLKCTRLSET */
+#define SYSCON_AHBCLKCTRLSET_COUNT (3U)
+
+/*! @name AHBCLKCTRLCLR - Clear bits in AHBCLKCTRLn */
+#define SYSCON_AHBCLKCTRLCLR_CLK_CLR_MASK (0xFFFFFFFFU)
+#define SYSCON_AHBCLKCTRLCLR_CLK_CLR_SHIFT (0U)
+#define SYSCON_AHBCLKCTRLCLR_CLK_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKCTRLCLR_CLK_CLR_SHIFT)) & SYSCON_AHBCLKCTRLCLR_CLK_CLR_MASK)
+
+/* The count of SYSCON_AHBCLKCTRLCLR */
+#define SYSCON_AHBCLKCTRLCLR_COUNT (3U)
+
+/*! @name MAINCLKSELA - Main clock source select A */
+#define SYSCON_MAINCLKSELA_SEL_MASK (0x3U)
+#define SYSCON_MAINCLKSELA_SEL_SHIFT (0U)
+#define SYSCON_MAINCLKSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELA_SEL_SHIFT)) & SYSCON_MAINCLKSELA_SEL_MASK)
+
+/*! @name MAINCLKSELB - Main clock source select B */
+#define SYSCON_MAINCLKSELB_SEL_MASK (0x3U)
+#define SYSCON_MAINCLKSELB_SEL_SHIFT (0U)
+#define SYSCON_MAINCLKSELB_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MAINCLKSELB_SEL_SHIFT)) & SYSCON_MAINCLKSELB_SEL_MASK)
+
+/*! @name CLKOUTSELA - CLKOUT clock source select A */
+#define SYSCON_CLKOUTSELA_SEL_MASK (0x7U)
+#define SYSCON_CLKOUTSELA_SEL_SHIFT (0U)
+#define SYSCON_CLKOUTSELA_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTSELA_SEL_SHIFT)) & SYSCON_CLKOUTSELA_SEL_MASK)
+
+/*! @name SYSPLLCLKSEL - PLL clock source select */
+#define SYSCON_SYSPLLCLKSEL_SEL_MASK (0x7U)
+#define SYSCON_SYSPLLCLKSEL_SEL_SHIFT (0U)
+#define SYSCON_SYSPLLCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCLKSEL_SEL_SHIFT)) & SYSCON_SYSPLLCLKSEL_SEL_MASK)
+
+/*! @name AUDPLLCLKSEL - Audio PLL clock source select */
+#define SYSCON_AUDPLLCLKSEL_SEL_MASK (0x7U)
+#define SYSCON_AUDPLLCLKSEL_SEL_SHIFT (0U)
+#define SYSCON_AUDPLLCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCLKSEL_SEL_SHIFT)) & SYSCON_AUDPLLCLKSEL_SEL_MASK)
+
+/*! @name SPIFICLKSEL - SPIFI clock source select */
+#define SYSCON_SPIFICLKSEL_SEL_MASK (0x7U)
+#define SYSCON_SPIFICLKSEL_SEL_SHIFT (0U)
+#define SYSCON_SPIFICLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKSEL_SEL_SHIFT)) & SYSCON_SPIFICLKSEL_SEL_MASK)
+
+/*! @name ADCCLKSEL - ADC clock source select */
+#define SYSCON_ADCCLKSEL_SEL_MASK (0x7U)
+#define SYSCON_ADCCLKSEL_SEL_SHIFT (0U)
+#define SYSCON_ADCCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKSEL_SEL_SHIFT)) & SYSCON_ADCCLKSEL_SEL_MASK)
+
+/*! @name USB0CLKSEL - USB0 clock source select */
+#define SYSCON_USB0CLKSEL_SEL_MASK (0x7U)
+#define SYSCON_USB0CLKSEL_SEL_SHIFT (0U)
+#define SYSCON_USB0CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSEL_SEL_SHIFT)) & SYSCON_USB0CLKSEL_SEL_MASK)
+
+/*! @name USB1CLKSEL - USB1 clock source select */
+#define SYSCON_USB1CLKSEL_SEL_MASK (0x7U)
+#define SYSCON_USB1CLKSEL_SEL_SHIFT (0U)
+#define SYSCON_USB1CLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSEL_SEL_SHIFT)) & SYSCON_USB1CLKSEL_SEL_MASK)
+
+/*! @name FCLKSEL - Flexcomm 0 clock source select */
+#define SYSCON_FCLKSEL_SEL_MASK (0x7U)
+#define SYSCON_FCLKSEL_SEL_SHIFT (0U)
+#define SYSCON_FCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FCLKSEL_SEL_SHIFT)) & SYSCON_FCLKSEL_SEL_MASK)
+
+/* The count of SYSCON_FCLKSEL */
+#define SYSCON_FCLKSEL_COUNT (10U)
+
+/*! @name MCLKCLKSEL - MCLK clock source select */
+#define SYSCON_MCLKCLKSEL_SEL_MASK (0x7U)
+#define SYSCON_MCLKCLKSEL_SEL_SHIFT (0U)
+#define SYSCON_MCLKCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKCLKSEL_SEL_SHIFT)) & SYSCON_MCLKCLKSEL_SEL_MASK)
+
+/*! @name FRGCLKSEL - Fractional Rate Generator clock source select */
+#define SYSCON_FRGCLKSEL_SEL_MASK (0x7U)
+#define SYSCON_FRGCLKSEL_SEL_SHIFT (0U)
+#define SYSCON_FRGCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCLKSEL_SEL_SHIFT)) & SYSCON_FRGCLKSEL_SEL_MASK)
+
+/*! @name DMICCLKSEL - Digital microphone (DMIC) subsystem clock select */
+#define SYSCON_DMICCLKSEL_SEL_MASK (0x7U)
+#define SYSCON_DMICCLKSEL_SEL_SHIFT (0U)
+#define SYSCON_DMICCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKSEL_SEL_SHIFT)) & SYSCON_DMICCLKSEL_SEL_MASK)
+
+/*! @name SCTCLKSEL - SCTimer/PWM clock source select */
+#define SYSCON_SCTCLKSEL_SEL_MASK (0x7U)
+#define SYSCON_SCTCLKSEL_SEL_SHIFT (0U)
+#define SYSCON_SCTCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKSEL_SEL_SHIFT)) & SYSCON_SCTCLKSEL_SEL_MASK)
+
+/*! @name LCDCLKSEL - LCD clock source select */
+#define SYSCON_LCDCLKSEL_SEL_MASK (0x3U)
+#define SYSCON_LCDCLKSEL_SEL_SHIFT (0U)
+#define SYSCON_LCDCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKSEL_SEL_SHIFT)) & SYSCON_LCDCLKSEL_SEL_MASK)
+
+/*! @name SDIOCLKSEL - SDIO clock source select */
+#define SYSCON_SDIOCLKSEL_SEL_MASK (0x7U)
+#define SYSCON_SDIOCLKSEL_SEL_SHIFT (0U)
+#define SYSCON_SDIOCLKSEL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKSEL_SEL_SHIFT)) & SYSCON_SDIOCLKSEL_SEL_MASK)
+
+/*! @name SYSTICKCLKDIV - SYSTICK clock divider */
+#define SYSCON_SYSTICKCLKDIV_DIV_MASK (0xFFU)
+#define SYSCON_SYSTICKCLKDIV_DIV_SHIFT (0U)
+#define SYSCON_SYSTICKCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_DIV_SHIFT)) & SYSCON_SYSTICKCLKDIV_DIV_MASK)
+#define SYSCON_SYSTICKCLKDIV_RESET_MASK (0x20000000U)
+#define SYSCON_SYSTICKCLKDIV_RESET_SHIFT (29U)
+#define SYSCON_SYSTICKCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_RESET_SHIFT)) & SYSCON_SYSTICKCLKDIV_RESET_MASK)
+#define SYSCON_SYSTICKCLKDIV_HALT_MASK (0x40000000U)
+#define SYSCON_SYSTICKCLKDIV_HALT_SHIFT (30U)
+#define SYSCON_SYSTICKCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_HALT_SHIFT)) & SYSCON_SYSTICKCLKDIV_HALT_MASK)
+#define SYSCON_SYSTICKCLKDIV_REQFLAG_MASK (0x80000000U)
+#define SYSCON_SYSTICKCLKDIV_REQFLAG_SHIFT (31U)
+#define SYSCON_SYSTICKCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSTICKCLKDIV_REQFLAG_SHIFT)) & SYSCON_SYSTICKCLKDIV_REQFLAG_MASK)
+
+/*! @name ARMTRACECLKDIV - ARM Trace clock divider */
+#define SYSCON_ARMTRACECLKDIV_DIV_MASK (0xFFU)
+#define SYSCON_ARMTRACECLKDIV_DIV_SHIFT (0U)
+#define SYSCON_ARMTRACECLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ARMTRACECLKDIV_DIV_SHIFT)) & SYSCON_ARMTRACECLKDIV_DIV_MASK)
+#define SYSCON_ARMTRACECLKDIV_RESET_MASK (0x20000000U)
+#define SYSCON_ARMTRACECLKDIV_RESET_SHIFT (29U)
+#define SYSCON_ARMTRACECLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ARMTRACECLKDIV_RESET_SHIFT)) & SYSCON_ARMTRACECLKDIV_RESET_MASK)
+#define SYSCON_ARMTRACECLKDIV_HALT_MASK (0x40000000U)
+#define SYSCON_ARMTRACECLKDIV_HALT_SHIFT (30U)
+#define SYSCON_ARMTRACECLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ARMTRACECLKDIV_HALT_SHIFT)) & SYSCON_ARMTRACECLKDIV_HALT_MASK)
+#define SYSCON_ARMTRACECLKDIV_REQFLAG_MASK (0x80000000U)
+#define SYSCON_ARMTRACECLKDIV_REQFLAG_SHIFT (31U)
+#define SYSCON_ARMTRACECLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ARMTRACECLKDIV_REQFLAG_SHIFT)) & SYSCON_ARMTRACECLKDIV_REQFLAG_MASK)
+
+/*! @name CAN0CLKDIV - MCAN0 clock divider */
+#define SYSCON_CAN0CLKDIV_DIV_MASK (0xFFU)
+#define SYSCON_CAN0CLKDIV_DIV_SHIFT (0U)
+#define SYSCON_CAN0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN0CLKDIV_DIV_SHIFT)) & SYSCON_CAN0CLKDIV_DIV_MASK)
+#define SYSCON_CAN0CLKDIV_RESET_MASK (0x20000000U)
+#define SYSCON_CAN0CLKDIV_RESET_SHIFT (29U)
+#define SYSCON_CAN0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN0CLKDIV_RESET_SHIFT)) & SYSCON_CAN0CLKDIV_RESET_MASK)
+#define SYSCON_CAN0CLKDIV_HALT_MASK (0x40000000U)
+#define SYSCON_CAN0CLKDIV_HALT_SHIFT (30U)
+#define SYSCON_CAN0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN0CLKDIV_HALT_SHIFT)) & SYSCON_CAN0CLKDIV_HALT_MASK)
+#define SYSCON_CAN0CLKDIV_REQFLAG_MASK (0x80000000U)
+#define SYSCON_CAN0CLKDIV_REQFLAG_SHIFT (31U)
+#define SYSCON_CAN0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN0CLKDIV_REQFLAG_SHIFT)) & SYSCON_CAN0CLKDIV_REQFLAG_MASK)
+
+/*! @name CAN1CLKDIV - MCAN1 clock divider */
+#define SYSCON_CAN1CLKDIV_DIV_MASK (0xFFU)
+#define SYSCON_CAN1CLKDIV_DIV_SHIFT (0U)
+#define SYSCON_CAN1CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN1CLKDIV_DIV_SHIFT)) & SYSCON_CAN1CLKDIV_DIV_MASK)
+#define SYSCON_CAN1CLKDIV_RESET_MASK (0x20000000U)
+#define SYSCON_CAN1CLKDIV_RESET_SHIFT (29U)
+#define SYSCON_CAN1CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN1CLKDIV_RESET_SHIFT)) & SYSCON_CAN1CLKDIV_RESET_MASK)
+#define SYSCON_CAN1CLKDIV_HALT_MASK (0x40000000U)
+#define SYSCON_CAN1CLKDIV_HALT_SHIFT (30U)
+#define SYSCON_CAN1CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN1CLKDIV_HALT_SHIFT)) & SYSCON_CAN1CLKDIV_HALT_MASK)
+#define SYSCON_CAN1CLKDIV_REQFLAG_MASK (0x80000000U)
+#define SYSCON_CAN1CLKDIV_REQFLAG_SHIFT (31U)
+#define SYSCON_CAN1CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CAN1CLKDIV_REQFLAG_SHIFT)) & SYSCON_CAN1CLKDIV_REQFLAG_MASK)
+
+/*! @name SC0CLKDIV - Smartcard0 clock divider */
+#define SYSCON_SC0CLKDIV_DIV_MASK (0xFFU)
+#define SYSCON_SC0CLKDIV_DIV_SHIFT (0U)
+#define SYSCON_SC0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC0CLKDIV_DIV_SHIFT)) & SYSCON_SC0CLKDIV_DIV_MASK)
+#define SYSCON_SC0CLKDIV_RESET_MASK (0x20000000U)
+#define SYSCON_SC0CLKDIV_RESET_SHIFT (29U)
+#define SYSCON_SC0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC0CLKDIV_RESET_SHIFT)) & SYSCON_SC0CLKDIV_RESET_MASK)
+#define SYSCON_SC0CLKDIV_HALT_MASK (0x40000000U)
+#define SYSCON_SC0CLKDIV_HALT_SHIFT (30U)
+#define SYSCON_SC0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC0CLKDIV_HALT_SHIFT)) & SYSCON_SC0CLKDIV_HALT_MASK)
+#define SYSCON_SC0CLKDIV_REQFLAG_MASK (0x80000000U)
+#define SYSCON_SC0CLKDIV_REQFLAG_SHIFT (31U)
+#define SYSCON_SC0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC0CLKDIV_REQFLAG_SHIFT)) & SYSCON_SC0CLKDIV_REQFLAG_MASK)
+
+/*! @name SC1CLKDIV - Smartcard1 clock divider */
+#define SYSCON_SC1CLKDIV_DIV_MASK (0xFFU)
+#define SYSCON_SC1CLKDIV_DIV_SHIFT (0U)
+#define SYSCON_SC1CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC1CLKDIV_DIV_SHIFT)) & SYSCON_SC1CLKDIV_DIV_MASK)
+#define SYSCON_SC1CLKDIV_RESET_MASK (0x20000000U)
+#define SYSCON_SC1CLKDIV_RESET_SHIFT (29U)
+#define SYSCON_SC1CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC1CLKDIV_RESET_SHIFT)) & SYSCON_SC1CLKDIV_RESET_MASK)
+#define SYSCON_SC1CLKDIV_HALT_MASK (0x40000000U)
+#define SYSCON_SC1CLKDIV_HALT_SHIFT (30U)
+#define SYSCON_SC1CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC1CLKDIV_HALT_SHIFT)) & SYSCON_SC1CLKDIV_HALT_MASK)
+#define SYSCON_SC1CLKDIV_REQFLAG_MASK (0x80000000U)
+#define SYSCON_SC1CLKDIV_REQFLAG_SHIFT (31U)
+#define SYSCON_SC1CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SC1CLKDIV_REQFLAG_SHIFT)) & SYSCON_SC1CLKDIV_REQFLAG_MASK)
+
+/*! @name AHBCLKDIV - AHB clock divider */
+#define SYSCON_AHBCLKDIV_DIV_MASK (0xFFU)
+#define SYSCON_AHBCLKDIV_DIV_SHIFT (0U)
+#define SYSCON_AHBCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_DIV_SHIFT)) & SYSCON_AHBCLKDIV_DIV_MASK)
+#define SYSCON_AHBCLKDIV_REQFLAG_MASK (0x80000000U)
+#define SYSCON_AHBCLKDIV_REQFLAG_SHIFT (31U)
+#define SYSCON_AHBCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AHBCLKDIV_REQFLAG_SHIFT)) & SYSCON_AHBCLKDIV_REQFLAG_MASK)
+
+/*! @name CLKOUTDIV - CLKOUT clock divider */
+#define SYSCON_CLKOUTDIV_DIV_MASK (0xFFU)
+#define SYSCON_CLKOUTDIV_DIV_SHIFT (0U)
+#define SYSCON_CLKOUTDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_DIV_SHIFT)) & SYSCON_CLKOUTDIV_DIV_MASK)
+#define SYSCON_CLKOUTDIV_RESET_MASK (0x20000000U)
+#define SYSCON_CLKOUTDIV_RESET_SHIFT (29U)
+#define SYSCON_CLKOUTDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_RESET_SHIFT)) & SYSCON_CLKOUTDIV_RESET_MASK)
+#define SYSCON_CLKOUTDIV_HALT_MASK (0x40000000U)
+#define SYSCON_CLKOUTDIV_HALT_SHIFT (30U)
+#define SYSCON_CLKOUTDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_HALT_SHIFT)) & SYSCON_CLKOUTDIV_HALT_MASK)
+#define SYSCON_CLKOUTDIV_REQFLAG_MASK (0x80000000U)
+#define SYSCON_CLKOUTDIV_REQFLAG_SHIFT (31U)
+#define SYSCON_CLKOUTDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_CLKOUTDIV_REQFLAG_SHIFT)) & SYSCON_CLKOUTDIV_REQFLAG_MASK)
+
+/*! @name FROHFCLKDIV - FROHF clock divider */
+#define SYSCON_FROHFCLKDIV_DIV_MASK (0xFFU)
+#define SYSCON_FROHFCLKDIV_DIV_SHIFT (0U)
+#define SYSCON_FROHFCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFCLKDIV_DIV_SHIFT)) & SYSCON_FROHFCLKDIV_DIV_MASK)
+#define SYSCON_FROHFCLKDIV_RESET_MASK (0x20000000U)
+#define SYSCON_FROHFCLKDIV_RESET_SHIFT (29U)
+#define SYSCON_FROHFCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFCLKDIV_RESET_SHIFT)) & SYSCON_FROHFCLKDIV_RESET_MASK)
+#define SYSCON_FROHFCLKDIV_HALT_MASK (0x40000000U)
+#define SYSCON_FROHFCLKDIV_HALT_SHIFT (30U)
+#define SYSCON_FROHFCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFCLKDIV_HALT_SHIFT)) & SYSCON_FROHFCLKDIV_HALT_MASK)
+#define SYSCON_FROHFCLKDIV_REQFLAG_MASK (0x80000000U)
+#define SYSCON_FROHFCLKDIV_REQFLAG_SHIFT (31U)
+#define SYSCON_FROHFCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROHFCLKDIV_REQFLAG_SHIFT)) & SYSCON_FROHFCLKDIV_REQFLAG_MASK)
+
+/*! @name SPIFICLKDIV - SPIFI clock divider */
+#define SYSCON_SPIFICLKDIV_DIV_MASK (0xFFU)
+#define SYSCON_SPIFICLKDIV_DIV_SHIFT (0U)
+#define SYSCON_SPIFICLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_DIV_SHIFT)) & SYSCON_SPIFICLKDIV_DIV_MASK)
+#define SYSCON_SPIFICLKDIV_RESET_MASK (0x20000000U)
+#define SYSCON_SPIFICLKDIV_RESET_SHIFT (29U)
+#define SYSCON_SPIFICLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_RESET_SHIFT)) & SYSCON_SPIFICLKDIV_RESET_MASK)
+#define SYSCON_SPIFICLKDIV_HALT_MASK (0x40000000U)
+#define SYSCON_SPIFICLKDIV_HALT_SHIFT (30U)
+#define SYSCON_SPIFICLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_HALT_SHIFT)) & SYSCON_SPIFICLKDIV_HALT_MASK)
+#define SYSCON_SPIFICLKDIV_REQFLAG_MASK (0x80000000U)
+#define SYSCON_SPIFICLKDIV_REQFLAG_SHIFT (31U)
+#define SYSCON_SPIFICLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SPIFICLKDIV_REQFLAG_SHIFT)) & SYSCON_SPIFICLKDIV_REQFLAG_MASK)
+
+/*! @name ADCCLKDIV - ADC clock divider */
+#define SYSCON_ADCCLKDIV_DIV_MASK (0xFFU)
+#define SYSCON_ADCCLKDIV_DIV_SHIFT (0U)
+#define SYSCON_ADCCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_DIV_SHIFT)) & SYSCON_ADCCLKDIV_DIV_MASK)
+#define SYSCON_ADCCLKDIV_RESET_MASK (0x20000000U)
+#define SYSCON_ADCCLKDIV_RESET_SHIFT (29U)
+#define SYSCON_ADCCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_RESET_SHIFT)) & SYSCON_ADCCLKDIV_RESET_MASK)
+#define SYSCON_ADCCLKDIV_HALT_MASK (0x40000000U)
+#define SYSCON_ADCCLKDIV_HALT_SHIFT (30U)
+#define SYSCON_ADCCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_HALT_SHIFT)) & SYSCON_ADCCLKDIV_HALT_MASK)
+#define SYSCON_ADCCLKDIV_REQFLAG_MASK (0x80000000U)
+#define SYSCON_ADCCLKDIV_REQFLAG_SHIFT (31U)
+#define SYSCON_ADCCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ADCCLKDIV_REQFLAG_SHIFT)) & SYSCON_ADCCLKDIV_REQFLAG_MASK)
+
+/*! @name USB0CLKDIV - USB0 clock divider */
+#define SYSCON_USB0CLKDIV_DIV_MASK (0xFFU)
+#define SYSCON_USB0CLKDIV_DIV_SHIFT (0U)
+#define SYSCON_USB0CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_DIV_SHIFT)) & SYSCON_USB0CLKDIV_DIV_MASK)
+#define SYSCON_USB0CLKDIV_RESET_MASK (0x20000000U)
+#define SYSCON_USB0CLKDIV_RESET_SHIFT (29U)
+#define SYSCON_USB0CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_RESET_SHIFT)) & SYSCON_USB0CLKDIV_RESET_MASK)
+#define SYSCON_USB0CLKDIV_HALT_MASK (0x40000000U)
+#define SYSCON_USB0CLKDIV_HALT_SHIFT (30U)
+#define SYSCON_USB0CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_HALT_SHIFT)) & SYSCON_USB0CLKDIV_HALT_MASK)
+#define SYSCON_USB0CLKDIV_REQFLAG_MASK (0x80000000U)
+#define SYSCON_USB0CLKDIV_REQFLAG_SHIFT (31U)
+#define SYSCON_USB0CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKDIV_REQFLAG_SHIFT)) & SYSCON_USB0CLKDIV_REQFLAG_MASK)
+
+/*! @name USB1CLKDIV - USB1 clock divider */
+#define SYSCON_USB1CLKDIV_DIV_MASK (0xFFU)
+#define SYSCON_USB1CLKDIV_DIV_SHIFT (0U)
+#define SYSCON_USB1CLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKDIV_DIV_SHIFT)) & SYSCON_USB1CLKDIV_DIV_MASK)
+#define SYSCON_USB1CLKDIV_RESET_MASK (0x20000000U)
+#define SYSCON_USB1CLKDIV_RESET_SHIFT (29U)
+#define SYSCON_USB1CLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKDIV_RESET_SHIFT)) & SYSCON_USB1CLKDIV_RESET_MASK)
+#define SYSCON_USB1CLKDIV_HALT_MASK (0x40000000U)
+#define SYSCON_USB1CLKDIV_HALT_SHIFT (30U)
+#define SYSCON_USB1CLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKDIV_HALT_SHIFT)) & SYSCON_USB1CLKDIV_HALT_MASK)
+#define SYSCON_USB1CLKDIV_REQFLAG_MASK (0x80000000U)
+#define SYSCON_USB1CLKDIV_REQFLAG_SHIFT (31U)
+#define SYSCON_USB1CLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKDIV_REQFLAG_SHIFT)) & SYSCON_USB1CLKDIV_REQFLAG_MASK)
+
+/*! @name FRGCTRL - Fractional rate divider */
+#define SYSCON_FRGCTRL_DIV_MASK (0xFFU)
+#define SYSCON_FRGCTRL_DIV_SHIFT (0U)
+#define SYSCON_FRGCTRL_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_DIV_SHIFT)) & SYSCON_FRGCTRL_DIV_MASK)
+#define SYSCON_FRGCTRL_MULT_MASK (0xFF00U)
+#define SYSCON_FRGCTRL_MULT_SHIFT (8U)
+#define SYSCON_FRGCTRL_MULT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FRGCTRL_MULT_SHIFT)) & SYSCON_FRGCTRL_MULT_MASK)
+
+/*! @name DMICCLKDIV - DMIC clock divider */
+#define SYSCON_DMICCLKDIV_DIV_MASK (0xFFU)
+#define SYSCON_DMICCLKDIV_DIV_SHIFT (0U)
+#define SYSCON_DMICCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_DIV_SHIFT)) & SYSCON_DMICCLKDIV_DIV_MASK)
+#define SYSCON_DMICCLKDIV_RESET_MASK (0x20000000U)
+#define SYSCON_DMICCLKDIV_RESET_SHIFT (29U)
+#define SYSCON_DMICCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_RESET_SHIFT)) & SYSCON_DMICCLKDIV_RESET_MASK)
+#define SYSCON_DMICCLKDIV_HALT_MASK (0x40000000U)
+#define SYSCON_DMICCLKDIV_HALT_SHIFT (30U)
+#define SYSCON_DMICCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_HALT_SHIFT)) & SYSCON_DMICCLKDIV_HALT_MASK)
+#define SYSCON_DMICCLKDIV_REQFLAG_MASK (0x80000000U)
+#define SYSCON_DMICCLKDIV_REQFLAG_SHIFT (31U)
+#define SYSCON_DMICCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DMICCLKDIV_REQFLAG_SHIFT)) & SYSCON_DMICCLKDIV_REQFLAG_MASK)
+
+/*! @name MCLKDIV - I2S MCLK clock divider */
+#define SYSCON_MCLKDIV_DIV_MASK (0xFFU)
+#define SYSCON_MCLKDIV_DIV_SHIFT (0U)
+#define SYSCON_MCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_DIV_SHIFT)) & SYSCON_MCLKDIV_DIV_MASK)
+#define SYSCON_MCLKDIV_RESET_MASK (0x20000000U)
+#define SYSCON_MCLKDIV_RESET_SHIFT (29U)
+#define SYSCON_MCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_RESET_SHIFT)) & SYSCON_MCLKDIV_RESET_MASK)
+#define SYSCON_MCLKDIV_HALT_MASK (0x40000000U)
+#define SYSCON_MCLKDIV_HALT_SHIFT (30U)
+#define SYSCON_MCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_HALT_SHIFT)) & SYSCON_MCLKDIV_HALT_MASK)
+#define SYSCON_MCLKDIV_REQFLAG_MASK (0x80000000U)
+#define SYSCON_MCLKDIV_REQFLAG_SHIFT (31U)
+#define SYSCON_MCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKDIV_REQFLAG_SHIFT)) & SYSCON_MCLKDIV_REQFLAG_MASK)
+
+/*! @name LCDCLKDIV - LCD clock divider */
+#define SYSCON_LCDCLKDIV_DIV_MASK (0xFFU)
+#define SYSCON_LCDCLKDIV_DIV_SHIFT (0U)
+#define SYSCON_LCDCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKDIV_DIV_SHIFT)) & SYSCON_LCDCLKDIV_DIV_MASK)
+#define SYSCON_LCDCLKDIV_RESET_MASK (0x20000000U)
+#define SYSCON_LCDCLKDIV_RESET_SHIFT (29U)
+#define SYSCON_LCDCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKDIV_RESET_SHIFT)) & SYSCON_LCDCLKDIV_RESET_MASK)
+#define SYSCON_LCDCLKDIV_HALT_MASK (0x40000000U)
+#define SYSCON_LCDCLKDIV_HALT_SHIFT (30U)
+#define SYSCON_LCDCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKDIV_HALT_SHIFT)) & SYSCON_LCDCLKDIV_HALT_MASK)
+#define SYSCON_LCDCLKDIV_REQFLAG_MASK (0x80000000U)
+#define SYSCON_LCDCLKDIV_REQFLAG_SHIFT (31U)
+#define SYSCON_LCDCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_LCDCLKDIV_REQFLAG_SHIFT)) & SYSCON_LCDCLKDIV_REQFLAG_MASK)
+
+/*! @name SCTCLKDIV - SCT/PWM clock divider */
+#define SYSCON_SCTCLKDIV_DIV_MASK (0xFFU)
+#define SYSCON_SCTCLKDIV_DIV_SHIFT (0U)
+#define SYSCON_SCTCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_DIV_SHIFT)) & SYSCON_SCTCLKDIV_DIV_MASK)
+#define SYSCON_SCTCLKDIV_RESET_MASK (0x20000000U)
+#define SYSCON_SCTCLKDIV_RESET_SHIFT (29U)
+#define SYSCON_SCTCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_RESET_SHIFT)) & SYSCON_SCTCLKDIV_RESET_MASK)
+#define SYSCON_SCTCLKDIV_HALT_MASK (0x40000000U)
+#define SYSCON_SCTCLKDIV_HALT_SHIFT (30U)
+#define SYSCON_SCTCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_HALT_SHIFT)) & SYSCON_SCTCLKDIV_HALT_MASK)
+#define SYSCON_SCTCLKDIV_REQFLAG_MASK (0x80000000U)
+#define SYSCON_SCTCLKDIV_REQFLAG_SHIFT (31U)
+#define SYSCON_SCTCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SCTCLKDIV_REQFLAG_SHIFT)) & SYSCON_SCTCLKDIV_REQFLAG_MASK)
+
+/*! @name EMCCLKDIV - EMC clock divider */
+#define SYSCON_EMCCLKDIV_DIV_MASK (0xFFU)
+#define SYSCON_EMCCLKDIV_DIV_SHIFT (0U)
+#define SYSCON_EMCCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCLKDIV_DIV_SHIFT)) & SYSCON_EMCCLKDIV_DIV_MASK)
+#define SYSCON_EMCCLKDIV_RESET_MASK (0x20000000U)
+#define SYSCON_EMCCLKDIV_RESET_SHIFT (29U)
+#define SYSCON_EMCCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCLKDIV_RESET_SHIFT)) & SYSCON_EMCCLKDIV_RESET_MASK)
+#define SYSCON_EMCCLKDIV_HALT_MASK (0x40000000U)
+#define SYSCON_EMCCLKDIV_HALT_SHIFT (30U)
+#define SYSCON_EMCCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCLKDIV_HALT_SHIFT)) & SYSCON_EMCCLKDIV_HALT_MASK)
+#define SYSCON_EMCCLKDIV_REQFLAG_MASK (0x80000000U)
+#define SYSCON_EMCCLKDIV_REQFLAG_SHIFT (31U)
+#define SYSCON_EMCCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCCLKDIV_REQFLAG_SHIFT)) & SYSCON_EMCCLKDIV_REQFLAG_MASK)
+
+/*! @name SDIOCLKDIV - SDIO clock divider */
+#define SYSCON_SDIOCLKDIV_DIV_MASK (0xFFU)
+#define SYSCON_SDIOCLKDIV_DIV_SHIFT (0U)
+#define SYSCON_SDIOCLKDIV_DIV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_DIV_SHIFT)) & SYSCON_SDIOCLKDIV_DIV_MASK)
+#define SYSCON_SDIOCLKDIV_RESET_MASK (0x20000000U)
+#define SYSCON_SDIOCLKDIV_RESET_SHIFT (29U)
+#define SYSCON_SDIOCLKDIV_RESET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_RESET_SHIFT)) & SYSCON_SDIOCLKDIV_RESET_MASK)
+#define SYSCON_SDIOCLKDIV_HALT_MASK (0x40000000U)
+#define SYSCON_SDIOCLKDIV_HALT_SHIFT (30U)
+#define SYSCON_SDIOCLKDIV_HALT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_HALT_SHIFT)) & SYSCON_SDIOCLKDIV_HALT_MASK)
+#define SYSCON_SDIOCLKDIV_REQFLAG_MASK (0x80000000U)
+#define SYSCON_SDIOCLKDIV_REQFLAG_SHIFT (31U)
+#define SYSCON_SDIOCLKDIV_REQFLAG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKDIV_REQFLAG_SHIFT)) & SYSCON_SDIOCLKDIV_REQFLAG_MASK)
+
+/*! @name FLASHCFG - Flash wait states configuration */
+#define SYSCON_FLASHCFG_FETCHCFG_MASK (0x3U)
+#define SYSCON_FLASHCFG_FETCHCFG_SHIFT (0U)
+#define SYSCON_FLASHCFG_FETCHCFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_FETCHCFG_SHIFT)) & SYSCON_FLASHCFG_FETCHCFG_MASK)
+#define SYSCON_FLASHCFG_DATACFG_MASK (0xCU)
+#define SYSCON_FLASHCFG_DATACFG_SHIFT (2U)
+#define SYSCON_FLASHCFG_DATACFG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_DATACFG_SHIFT)) & SYSCON_FLASHCFG_DATACFG_MASK)
+#define SYSCON_FLASHCFG_ACCEL_MASK (0x10U)
+#define SYSCON_FLASHCFG_ACCEL_SHIFT (4U)
+#define SYSCON_FLASHCFG_ACCEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_ACCEL_SHIFT)) & SYSCON_FLASHCFG_ACCEL_MASK)
+#define SYSCON_FLASHCFG_PREFEN_MASK (0x20U)
+#define SYSCON_FLASHCFG_PREFEN_SHIFT (5U)
+#define SYSCON_FLASHCFG_PREFEN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_PREFEN_SHIFT)) & SYSCON_FLASHCFG_PREFEN_MASK)
+#define SYSCON_FLASHCFG_PREFOVR_MASK (0x40U)
+#define SYSCON_FLASHCFG_PREFOVR_SHIFT (6U)
+#define SYSCON_FLASHCFG_PREFOVR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_PREFOVR_SHIFT)) & SYSCON_FLASHCFG_PREFOVR_MASK)
+#define SYSCON_FLASHCFG_FLASHTIM_MASK (0xF000U)
+#define SYSCON_FLASHCFG_FLASHTIM_SHIFT (12U)
+#define SYSCON_FLASHCFG_FLASHTIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FLASHCFG_FLASHTIM_SHIFT)) & SYSCON_FLASHCFG_FLASHTIM_MASK)
+
+/*! @name USB0CLKCTRL - USB0 clock control */
+#define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_MASK (0x1U)
+#define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_SHIFT (0U)
+#define SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_AP_FS_DEV_CLK_MASK)
+#define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_MASK (0x2U)
+#define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_SHIFT (1U)
+#define SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_POL_FS_DEV_CLK_MASK)
+#define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_MASK (0x4U)
+#define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_SHIFT (2U)
+#define SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_AP_FS_HOST_CLK_MASK)
+#define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_MASK (0x8U)
+#define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_SHIFT (3U)
+#define SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_SHIFT)) & SYSCON_USB0CLKCTRL_POL_FS_HOST_CLK_MASK)
+#define SYSCON_USB0CLKCTRL_PU_DISABLE_MASK (0x10U)
+#define SYSCON_USB0CLKCTRL_PU_DISABLE_SHIFT (4U)
+#define SYSCON_USB0CLKCTRL_PU_DISABLE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKCTRL_PU_DISABLE_SHIFT)) & SYSCON_USB0CLKCTRL_PU_DISABLE_MASK)
+
+/*! @name USB0CLKSTAT - USB0 clock status */
+#define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_MASK (0x1U)
+#define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_SHIFT (0U)
+#define SYSCON_USB0CLKSTAT_DEV_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_SHIFT)) & SYSCON_USB0CLKSTAT_DEV_NEED_CLKST_MASK)
+#define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_MASK (0x2U)
+#define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_SHIFT (1U)
+#define SYSCON_USB0CLKSTAT_HOST_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_SHIFT)) & SYSCON_USB0CLKSTAT_HOST_NEED_CLKST_MASK)
+
+/*! @name FREQMECTRL - Frequency measure register */
+#define SYSCON_FREQMECTRL_CAPVAL_MASK (0x3FFFU)
+#define SYSCON_FREQMECTRL_CAPVAL_SHIFT (0U)
+#define SYSCON_FREQMECTRL_CAPVAL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FREQMECTRL_CAPVAL_SHIFT)) & SYSCON_FREQMECTRL_CAPVAL_MASK)
+#define SYSCON_FREQMECTRL_PROG_MASK (0x80000000U)
+#define SYSCON_FREQMECTRL_PROG_SHIFT (31U)
+#define SYSCON_FREQMECTRL_PROG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FREQMECTRL_PROG_SHIFT)) & SYSCON_FREQMECTRL_PROG_MASK)
+
+/*! @name MCLKIO - MCLK input/output control */
+#define SYSCON_MCLKIO_DIR_MASK (0x1U)
+#define SYSCON_MCLKIO_DIR_SHIFT (0U)
+#define SYSCON_MCLKIO_DIR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_MCLKIO_DIR_SHIFT)) & SYSCON_MCLKIO_DIR_MASK)
+
+/*! @name USB1CLKCTRL - USB1 clock control */
+#define SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK_MASK (0x1U)
+#define SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK_SHIFT (0U)
+#define SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_AP_FS_DEV_CLK_MASK)
+#define SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK_MASK (0x2U)
+#define SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK_SHIFT (1U)
+#define SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_POL_FS_DEV_CLK_MASK)
+#define SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK_MASK (0x4U)
+#define SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK_SHIFT (2U)
+#define SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_AP_FS_HOST_CLK_MASK)
+#define SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK_MASK (0x8U)
+#define SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK_SHIFT (3U)
+#define SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK_SHIFT)) & SYSCON_USB1CLKCTRL_POL_FS_HOST_CLK_MASK)
+#define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_MASK (0x10U)
+#define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_SHIFT (4U)
+#define SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_SHIFT)) & SYSCON_USB1CLKCTRL_HS_DEV_WAKEUP_N_MASK)
+
+/*! @name USB1CLKSTAT - USB1 clock status */
+#define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_MASK (0x1U)
+#define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_SHIFT (0U)
+#define SYSCON_USB1CLKSTAT_DEV_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_SHIFT)) & SYSCON_USB1CLKSTAT_DEV_NEED_CLKST_MASK)
+#define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_MASK (0x2U)
+#define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_SHIFT (1U)
+#define SYSCON_USB1CLKSTAT_HOST_NEED_CLKST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_SHIFT)) & SYSCON_USB1CLKSTAT_HOST_NEED_CLKST_MASK)
+
+/*! @name EMCSYSCTRL - EMC system control */
+#define SYSCON_EMCSYSCTRL_EMCSC_MASK (0x1U)
+#define SYSCON_EMCSYSCTRL_EMCSC_SHIFT (0U)
+#define SYSCON_EMCSYSCTRL_EMCSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCSYSCTRL_EMCSC_SHIFT)) & SYSCON_EMCSYSCTRL_EMCSC_MASK)
+#define SYSCON_EMCSYSCTRL_EMCRD_MASK (0x2U)
+#define SYSCON_EMCSYSCTRL_EMCRD_SHIFT (1U)
+#define SYSCON_EMCSYSCTRL_EMCRD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCSYSCTRL_EMCRD_SHIFT)) & SYSCON_EMCSYSCTRL_EMCRD_MASK)
+#define SYSCON_EMCSYSCTRL_EMCBC_MASK (0x4U)
+#define SYSCON_EMCSYSCTRL_EMCBC_SHIFT (2U)
+#define SYSCON_EMCSYSCTRL_EMCBC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCSYSCTRL_EMCBC_SHIFT)) & SYSCON_EMCSYSCTRL_EMCBC_MASK)
+#define SYSCON_EMCSYSCTRL_EMCFBCLKINSEL_MASK (0x8U)
+#define SYSCON_EMCSYSCTRL_EMCFBCLKINSEL_SHIFT (3U)
+#define SYSCON_EMCSYSCTRL_EMCFBCLKINSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCSYSCTRL_EMCFBCLKINSEL_SHIFT)) & SYSCON_EMCSYSCTRL_EMCFBCLKINSEL_MASK)
+
+/*! @name EMCDLYCTRL - EMC clock delay control */
+#define SYSCON_EMCDLYCTRL_CMD_DELAY_MASK (0x1FU)
+#define SYSCON_EMCDLYCTRL_CMD_DELAY_SHIFT (0U)
+#define SYSCON_EMCDLYCTRL_CMD_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCDLYCTRL_CMD_DELAY_SHIFT)) & SYSCON_EMCDLYCTRL_CMD_DELAY_MASK)
+#define SYSCON_EMCDLYCTRL_FBCLK_DELAY_MASK (0x1F00U)
+#define SYSCON_EMCDLYCTRL_FBCLK_DELAY_SHIFT (8U)
+#define SYSCON_EMCDLYCTRL_FBCLK_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCDLYCTRL_FBCLK_DELAY_SHIFT)) & SYSCON_EMCDLYCTRL_FBCLK_DELAY_MASK)
+
+/*! @name EMCDLYCAL - EMC delay chain calibration control */
+#define SYSCON_EMCDLYCAL_CALVALUE_MASK (0xFFU)
+#define SYSCON_EMCDLYCAL_CALVALUE_SHIFT (0U)
+#define SYSCON_EMCDLYCAL_CALVALUE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCDLYCAL_CALVALUE_SHIFT)) & SYSCON_EMCDLYCAL_CALVALUE_MASK)
+#define SYSCON_EMCDLYCAL_START_MASK (0x4000U)
+#define SYSCON_EMCDLYCAL_START_SHIFT (14U)
+#define SYSCON_EMCDLYCAL_START(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCDLYCAL_START_SHIFT)) & SYSCON_EMCDLYCAL_START_MASK)
+#define SYSCON_EMCDLYCAL_DONE_MASK (0x8000U)
+#define SYSCON_EMCDLYCAL_DONE_SHIFT (15U)
+#define SYSCON_EMCDLYCAL_DONE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_EMCDLYCAL_DONE_SHIFT)) & SYSCON_EMCDLYCAL_DONE_MASK)
+
+/*! @name ETHPHYSEL - Ethernet PHY Selection */
+#define SYSCON_ETHPHYSEL_PHY_SEL_MASK (0x4U)
+#define SYSCON_ETHPHYSEL_PHY_SEL_SHIFT (2U)
+#define SYSCON_ETHPHYSEL_PHY_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ETHPHYSEL_PHY_SEL_SHIFT)) & SYSCON_ETHPHYSEL_PHY_SEL_MASK)
+
+/*! @name ETHSBDCTRL - Ethernet SBD flow control */
+#define SYSCON_ETHSBDCTRL_SBD_CTRL_MASK (0x3U)
+#define SYSCON_ETHSBDCTRL_SBD_CTRL_SHIFT (0U)
+#define SYSCON_ETHSBDCTRL_SBD_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_ETHSBDCTRL_SBD_CTRL_SHIFT)) & SYSCON_ETHSBDCTRL_SBD_CTRL_MASK)
+
+/*! @name SDIOCLKCTRL - SDIO CCLKIN phase and delay control */
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK (0x3U)
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT (0U)
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE_MASK)
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK (0xCU)
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT (2U)
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE_MASK)
+#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK (0x80U)
+#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT (7U)
+#define SYSCON_SDIOCLKCTRL_PHASE_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK)
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK (0x1F0000U)
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT (16U)
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_MASK)
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK (0x800000U)
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT (23U)
+#define SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK)
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK (0x1F000000U)
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT (24U)
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_MASK)
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK (0x80000000U)
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT (31U)
+#define SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_SHIFT)) & SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK)
+
+/*! @name FROCTRL - FRO oscillator control */
+#define SYSCON_FROCTRL_TRIM_MASK (0x3FFFU)
+#define SYSCON_FROCTRL_TRIM_SHIFT (0U)
+#define SYSCON_FROCTRL_TRIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_TRIM_SHIFT)) & SYSCON_FROCTRL_TRIM_MASK)
+#define SYSCON_FROCTRL_SEL_MASK (0x4000U)
+#define SYSCON_FROCTRL_SEL_SHIFT (14U)
+#define SYSCON_FROCTRL_SEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_SEL_SHIFT)) & SYSCON_FROCTRL_SEL_MASK)
+#define SYSCON_FROCTRL_FREQTRIM_MASK (0xFF0000U)
+#define SYSCON_FROCTRL_FREQTRIM_SHIFT (16U)
+#define SYSCON_FROCTRL_FREQTRIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_FREQTRIM_SHIFT)) & SYSCON_FROCTRL_FREQTRIM_MASK)
+#define SYSCON_FROCTRL_USBCLKADJ_MASK (0x1000000U)
+#define SYSCON_FROCTRL_USBCLKADJ_SHIFT (24U)
+#define SYSCON_FROCTRL_USBCLKADJ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_USBCLKADJ_SHIFT)) & SYSCON_FROCTRL_USBCLKADJ_MASK)
+#define SYSCON_FROCTRL_USBMODCHG_MASK (0x2000000U)
+#define SYSCON_FROCTRL_USBMODCHG_SHIFT (25U)
+#define SYSCON_FROCTRL_USBMODCHG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_USBMODCHG_SHIFT)) & SYSCON_FROCTRL_USBMODCHG_MASK)
+#define SYSCON_FROCTRL_HSPDCLK_MASK (0x40000000U)
+#define SYSCON_FROCTRL_HSPDCLK_SHIFT (30U)
+#define SYSCON_FROCTRL_HSPDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_HSPDCLK_SHIFT)) & SYSCON_FROCTRL_HSPDCLK_MASK)
+#define SYSCON_FROCTRL_WRTRIM_MASK (0x80000000U)
+#define SYSCON_FROCTRL_WRTRIM_SHIFT (31U)
+#define SYSCON_FROCTRL_WRTRIM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_FROCTRL_WRTRIM_SHIFT)) & SYSCON_FROCTRL_WRTRIM_MASK)
+
+/*! @name SYSOSCCTRL - System oscillator control */
+#define SYSCON_SYSOSCCTRL_BYPASS_MASK (0x1U)
+#define SYSCON_SYSOSCCTRL_BYPASS_SHIFT (0U)
+#define SYSCON_SYSOSCCTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSOSCCTRL_BYPASS_SHIFT)) & SYSCON_SYSOSCCTRL_BYPASS_MASK)
+#define SYSCON_SYSOSCCTRL_FREQRANGE_MASK (0x2U)
+#define SYSCON_SYSOSCCTRL_FREQRANGE_SHIFT (1U)
+#define SYSCON_SYSOSCCTRL_FREQRANGE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSOSCCTRL_FREQRANGE_SHIFT)) & SYSCON_SYSOSCCTRL_FREQRANGE_MASK)
+
+/*! @name WDTOSCCTRL - Watchdog oscillator control */
+#define SYSCON_WDTOSCCTRL_DIVSEL_MASK (0x1FU)
+#define SYSCON_WDTOSCCTRL_DIVSEL_SHIFT (0U)
+#define SYSCON_WDTOSCCTRL_DIVSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_DIVSEL_SHIFT)) & SYSCON_WDTOSCCTRL_DIVSEL_MASK)
+#define SYSCON_WDTOSCCTRL_FREQSEL_MASK (0x3E0U)
+#define SYSCON_WDTOSCCTRL_FREQSEL_SHIFT (5U)
+#define SYSCON_WDTOSCCTRL_FREQSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)) & SYSCON_WDTOSCCTRL_FREQSEL_MASK)
+
+/*! @name RTCOSCCTRL - RTC oscillator 32 kHz output control */
+#define SYSCON_RTCOSCCTRL_EN_MASK (0x1U)
+#define SYSCON_RTCOSCCTRL_EN_SHIFT (0U)
+#define SYSCON_RTCOSCCTRL_EN(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_RTCOSCCTRL_EN_SHIFT)) & SYSCON_RTCOSCCTRL_EN_MASK)
+
+/*! @name USBPLLCTRL - USB PLL control */
+#define SYSCON_USBPLLCTRL_MSEL_MASK (0xFFU)
+#define SYSCON_USBPLLCTRL_MSEL_SHIFT (0U)
+#define SYSCON_USBPLLCTRL_MSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_MSEL_SHIFT)) & SYSCON_USBPLLCTRL_MSEL_MASK)
+#define SYSCON_USBPLLCTRL_PSEL_MASK (0x300U)
+#define SYSCON_USBPLLCTRL_PSEL_SHIFT (8U)
+#define SYSCON_USBPLLCTRL_PSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_PSEL_SHIFT)) & SYSCON_USBPLLCTRL_PSEL_MASK)
+#define SYSCON_USBPLLCTRL_NSEL_MASK (0xC00U)
+#define SYSCON_USBPLLCTRL_NSEL_SHIFT (10U)
+#define SYSCON_USBPLLCTRL_NSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_NSEL_SHIFT)) & SYSCON_USBPLLCTRL_NSEL_MASK)
+#define SYSCON_USBPLLCTRL_DIRECT_MASK (0x1000U)
+#define SYSCON_USBPLLCTRL_DIRECT_SHIFT (12U)
+#define SYSCON_USBPLLCTRL_DIRECT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_DIRECT_SHIFT)) & SYSCON_USBPLLCTRL_DIRECT_MASK)
+#define SYSCON_USBPLLCTRL_BYPASS_MASK (0x2000U)
+#define SYSCON_USBPLLCTRL_BYPASS_SHIFT (13U)
+#define SYSCON_USBPLLCTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_BYPASS_SHIFT)) & SYSCON_USBPLLCTRL_BYPASS_MASK)
+#define SYSCON_USBPLLCTRL_FBSEL_MASK (0x4000U)
+#define SYSCON_USBPLLCTRL_FBSEL_SHIFT (14U)
+#define SYSCON_USBPLLCTRL_FBSEL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLCTRL_FBSEL_SHIFT)) & SYSCON_USBPLLCTRL_FBSEL_MASK)
+
+/*! @name USBPLLSTAT - USB PLL status */
+#define SYSCON_USBPLLSTAT_LOCK_MASK (0x1U)
+#define SYSCON_USBPLLSTAT_LOCK_SHIFT (0U)
+#define SYSCON_USBPLLSTAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_USBPLLSTAT_LOCK_SHIFT)) & SYSCON_USBPLLSTAT_LOCK_MASK)
+
+/*! @name SYSPLLCTRL - System PLL control */
+#define SYSCON_SYSPLLCTRL_SELR_MASK (0xFU)
+#define SYSCON_SYSPLLCTRL_SELR_SHIFT (0U)
+#define SYSCON_SYSPLLCTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELR_SHIFT)) & SYSCON_SYSPLLCTRL_SELR_MASK)
+#define SYSCON_SYSPLLCTRL_SELI_MASK (0x3F0U)
+#define SYSCON_SYSPLLCTRL_SELI_SHIFT (4U)
+#define SYSCON_SYSPLLCTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELI_SHIFT)) & SYSCON_SYSPLLCTRL_SELI_MASK)
+#define SYSCON_SYSPLLCTRL_SELP_MASK (0x7C00U)
+#define SYSCON_SYSPLLCTRL_SELP_SHIFT (10U)
+#define SYSCON_SYSPLLCTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_SELP_SHIFT)) & SYSCON_SYSPLLCTRL_SELP_MASK)
+#define SYSCON_SYSPLLCTRL_BYPASS_MASK (0x8000U)
+#define SYSCON_SYSPLLCTRL_BYPASS_SHIFT (15U)
+#define SYSCON_SYSPLLCTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_BYPASS_SHIFT)) & SYSCON_SYSPLLCTRL_BYPASS_MASK)
+#define SYSCON_SYSPLLCTRL_UPLIMOFF_MASK (0x20000U)
+#define SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT (17U)
+#define SYSCON_SYSPLLCTRL_UPLIMOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_UPLIMOFF_SHIFT)) & SYSCON_SYSPLLCTRL_UPLIMOFF_MASK)
+#define SYSCON_SYSPLLCTRL_DIRECTI_MASK (0x80000U)
+#define SYSCON_SYSPLLCTRL_DIRECTI_SHIFT (19U)
+#define SYSCON_SYSPLLCTRL_DIRECTI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_DIRECTI_SHIFT)) & SYSCON_SYSPLLCTRL_DIRECTI_MASK)
+#define SYSCON_SYSPLLCTRL_DIRECTO_MASK (0x100000U)
+#define SYSCON_SYSPLLCTRL_DIRECTO_SHIFT (20U)
+#define SYSCON_SYSPLLCTRL_DIRECTO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLCTRL_DIRECTO_SHIFT)) & SYSCON_SYSPLLCTRL_DIRECTO_MASK)
+
+/*! @name SYSPLLSTAT - PLL status */
+#define SYSCON_SYSPLLSTAT_LOCK_MASK (0x1U)
+#define SYSCON_SYSPLLSTAT_LOCK_SHIFT (0U)
+#define SYSCON_SYSPLLSTAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLSTAT_LOCK_SHIFT)) & SYSCON_SYSPLLSTAT_LOCK_MASK)
+
+/*! @name SYSPLLNDEC - PLL N divider */
+#define SYSCON_SYSPLLNDEC_NDEC_MASK (0x3FFU)
+#define SYSCON_SYSPLLNDEC_NDEC_SHIFT (0U)
+#define SYSCON_SYSPLLNDEC_NDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLNDEC_NDEC_SHIFT)) & SYSCON_SYSPLLNDEC_NDEC_MASK)
+#define SYSCON_SYSPLLNDEC_NREQ_MASK (0x400U)
+#define SYSCON_SYSPLLNDEC_NREQ_SHIFT (10U)
+#define SYSCON_SYSPLLNDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLNDEC_NREQ_SHIFT)) & SYSCON_SYSPLLNDEC_NREQ_MASK)
+
+/*! @name SYSPLLPDEC - PLL P divider */
+#define SYSCON_SYSPLLPDEC_PDEC_MASK (0x7FU)
+#define SYSCON_SYSPLLPDEC_PDEC_SHIFT (0U)
+#define SYSCON_SYSPLLPDEC_PDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLPDEC_PDEC_SHIFT)) & SYSCON_SYSPLLPDEC_PDEC_MASK)
+#define SYSCON_SYSPLLPDEC_PREQ_MASK (0x80U)
+#define SYSCON_SYSPLLPDEC_PREQ_SHIFT (7U)
+#define SYSCON_SYSPLLPDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLPDEC_PREQ_SHIFT)) & SYSCON_SYSPLLPDEC_PREQ_MASK)
+
+/*! @name SYSPLLMDEC - System PLL M divider */
+#define SYSCON_SYSPLLMDEC_MDEC_MASK (0x1FFFFU)
+#define SYSCON_SYSPLLMDEC_MDEC_SHIFT (0U)
+#define SYSCON_SYSPLLMDEC_MDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLMDEC_MDEC_SHIFT)) & SYSCON_SYSPLLMDEC_MDEC_MASK)
+#define SYSCON_SYSPLLMDEC_MREQ_MASK (0x20000U)
+#define SYSCON_SYSPLLMDEC_MREQ_SHIFT (17U)
+#define SYSCON_SYSPLLMDEC_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_SYSPLLMDEC_MREQ_SHIFT)) & SYSCON_SYSPLLMDEC_MREQ_MASK)
+
+/*! @name AUDPLLCTRL - Audio PLL control */
+#define SYSCON_AUDPLLCTRL_SELR_MASK (0xFU)
+#define SYSCON_AUDPLLCTRL_SELR_SHIFT (0U)
+#define SYSCON_AUDPLLCTRL_SELR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_SELR_SHIFT)) & SYSCON_AUDPLLCTRL_SELR_MASK)
+#define SYSCON_AUDPLLCTRL_SELI_MASK (0x3F0U)
+#define SYSCON_AUDPLLCTRL_SELI_SHIFT (4U)
+#define SYSCON_AUDPLLCTRL_SELI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_SELI_SHIFT)) & SYSCON_AUDPLLCTRL_SELI_MASK)
+#define SYSCON_AUDPLLCTRL_SELP_MASK (0x7C00U)
+#define SYSCON_AUDPLLCTRL_SELP_SHIFT (10U)
+#define SYSCON_AUDPLLCTRL_SELP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_SELP_SHIFT)) & SYSCON_AUDPLLCTRL_SELP_MASK)
+#define SYSCON_AUDPLLCTRL_BYPASS_MASK (0x8000U)
+#define SYSCON_AUDPLLCTRL_BYPASS_SHIFT (15U)
+#define SYSCON_AUDPLLCTRL_BYPASS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_BYPASS_SHIFT)) & SYSCON_AUDPLLCTRL_BYPASS_MASK)
+#define SYSCON_AUDPLLCTRL_UPLIMOFF_MASK (0x20000U)
+#define SYSCON_AUDPLLCTRL_UPLIMOFF_SHIFT (17U)
+#define SYSCON_AUDPLLCTRL_UPLIMOFF(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_UPLIMOFF_SHIFT)) & SYSCON_AUDPLLCTRL_UPLIMOFF_MASK)
+#define SYSCON_AUDPLLCTRL_DIRECTI_MASK (0x80000U)
+#define SYSCON_AUDPLLCTRL_DIRECTI_SHIFT (19U)
+#define SYSCON_AUDPLLCTRL_DIRECTI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_DIRECTI_SHIFT)) & SYSCON_AUDPLLCTRL_DIRECTI_MASK)
+#define SYSCON_AUDPLLCTRL_DIRECTO_MASK (0x100000U)
+#define SYSCON_AUDPLLCTRL_DIRECTO_SHIFT (20U)
+#define SYSCON_AUDPLLCTRL_DIRECTO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLCTRL_DIRECTO_SHIFT)) & SYSCON_AUDPLLCTRL_DIRECTO_MASK)
+
+/*! @name AUDPLLSTAT - Audio PLL status */
+#define SYSCON_AUDPLLSTAT_LOCK_MASK (0x1U)
+#define SYSCON_AUDPLLSTAT_LOCK_SHIFT (0U)
+#define SYSCON_AUDPLLSTAT_LOCK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLSTAT_LOCK_SHIFT)) & SYSCON_AUDPLLSTAT_LOCK_MASK)
+
+/*! @name AUDPLLNDEC - Audio PLL N divider */
+#define SYSCON_AUDPLLNDEC_NDEC_MASK (0x3FFU)
+#define SYSCON_AUDPLLNDEC_NDEC_SHIFT (0U)
+#define SYSCON_AUDPLLNDEC_NDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLNDEC_NDEC_SHIFT)) & SYSCON_AUDPLLNDEC_NDEC_MASK)
+#define SYSCON_AUDPLLNDEC_NREQ_MASK (0x400U)
+#define SYSCON_AUDPLLNDEC_NREQ_SHIFT (10U)
+#define SYSCON_AUDPLLNDEC_NREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLNDEC_NREQ_SHIFT)) & SYSCON_AUDPLLNDEC_NREQ_MASK)
+
+/*! @name AUDPLLPDEC - Audio PLL P divider */
+#define SYSCON_AUDPLLPDEC_PDEC_MASK (0x7FU)
+#define SYSCON_AUDPLLPDEC_PDEC_SHIFT (0U)
+#define SYSCON_AUDPLLPDEC_PDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLPDEC_PDEC_SHIFT)) & SYSCON_AUDPLLPDEC_PDEC_MASK)
+#define SYSCON_AUDPLLPDEC_PREQ_MASK (0x80U)
+#define SYSCON_AUDPLLPDEC_PREQ_SHIFT (7U)
+#define SYSCON_AUDPLLPDEC_PREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLPDEC_PREQ_SHIFT)) & SYSCON_AUDPLLPDEC_PREQ_MASK)
+
+/*! @name AUDPLLMDEC - Audio PLL M divider */
+#define SYSCON_AUDPLLMDEC_MDEC_MASK (0x1FFFFU)
+#define SYSCON_AUDPLLMDEC_MDEC_SHIFT (0U)
+#define SYSCON_AUDPLLMDEC_MDEC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLMDEC_MDEC_SHIFT)) & SYSCON_AUDPLLMDEC_MDEC_MASK)
+#define SYSCON_AUDPLLMDEC_MREQ_MASK (0x20000U)
+#define SYSCON_AUDPLLMDEC_MREQ_SHIFT (17U)
+#define SYSCON_AUDPLLMDEC_MREQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLMDEC_MREQ_SHIFT)) & SYSCON_AUDPLLMDEC_MREQ_MASK)
+
+/*! @name AUDPLLFRAC - Audio PLL fractional divider control */
+#define SYSCON_AUDPLLFRAC_CTRL_MASK (0x3FFFFFU)
+#define SYSCON_AUDPLLFRAC_CTRL_SHIFT (0U)
+#define SYSCON_AUDPLLFRAC_CTRL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLFRAC_CTRL_SHIFT)) & SYSCON_AUDPLLFRAC_CTRL_MASK)
+#define SYSCON_AUDPLLFRAC_REQ_MASK (0x400000U)
+#define SYSCON_AUDPLLFRAC_REQ_SHIFT (22U)
+#define SYSCON_AUDPLLFRAC_REQ(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLFRAC_REQ_SHIFT)) & SYSCON_AUDPLLFRAC_REQ_MASK)
+#define SYSCON_AUDPLLFRAC_SEL_EXT_MASK (0x800000U)
+#define SYSCON_AUDPLLFRAC_SEL_EXT_SHIFT (23U)
+#define SYSCON_AUDPLLFRAC_SEL_EXT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUDPLLFRAC_SEL_EXT_SHIFT)) & SYSCON_AUDPLLFRAC_SEL_EXT_MASK)
+
+/*! @name PDSLEEPCFG - Power configuration register 0 */
+#define SYSCON_PDSLEEPCFG_PDEN_USB1_PHY_MASK (0x1U)
+#define SYSCON_PDSLEEPCFG_PDEN_USB1_PHY_SHIFT (0U)
+#define SYSCON_PDSLEEPCFG_PDEN_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_USB1_PHY_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_USB1_PHY_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_USB1_PLL_MASK (0x2U)
+#define SYSCON_PDSLEEPCFG_PDEN_USB1_PLL_SHIFT (1U)
+#define SYSCON_PDSLEEPCFG_PDEN_USB1_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_USB1_PLL_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_USB1_PLL_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_AUD_PLL_MASK (0x4U)
+#define SYSCON_PDSLEEPCFG_PDEN_AUD_PLL_SHIFT (2U)
+#define SYSCON_PDSLEEPCFG_PDEN_AUD_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_AUD_PLL_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_AUD_PLL_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_SYSOSC_MASK (0x8U)
+#define SYSCON_PDSLEEPCFG_PDEN_SYSOSC_SHIFT (3U)
+#define SYSCON_PDSLEEPCFG_PDEN_SYSOSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SYSOSC_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SYSOSC_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_FRO_MASK (0x10U)
+#define SYSCON_PDSLEEPCFG_PDEN_FRO_SHIFT (4U)
+#define SYSCON_PDSLEEPCFG_PDEN_FRO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_FRO_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_FRO_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_EEPROM_MASK (0x20U)
+#define SYSCON_PDSLEEPCFG_PDEN_EEPROM_SHIFT (5U)
+#define SYSCON_PDSLEEPCFG_PDEN_EEPROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_EEPROM_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_EEPROM_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_TS_MASK (0x40U)
+#define SYSCON_PDSLEEPCFG_PDEN_TS_SHIFT (6U)
+#define SYSCON_PDSLEEPCFG_PDEN_TS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_TS_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_TS_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_BOD_RST_MASK (0x80U)
+#define SYSCON_PDSLEEPCFG_PDEN_BOD_RST_SHIFT (7U)
+#define SYSCON_PDSLEEPCFG_PDEN_BOD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_BOD_RST_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_BOD_RST_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_RNG_MASK (0x80U)
+#define SYSCON_PDSLEEPCFG_PDEN_RNG_SHIFT (7U)
+#define SYSCON_PDSLEEPCFG_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_RNG_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_RNG_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_BOD_INTR_MASK (0x100U)
+#define SYSCON_PDSLEEPCFG_PDEN_BOD_INTR_SHIFT (8U)
+#define SYSCON_PDSLEEPCFG_PDEN_BOD_INTR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_BOD_INTR_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_VD2_ANA_MASK (0x200U)
+#define SYSCON_PDSLEEPCFG_PDEN_VD2_ANA_SHIFT (9U)
+#define SYSCON_PDSLEEPCFG_PDEN_VD2_ANA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD2_ANA_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD2_ANA_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_ADC0_MASK (0x400U)
+#define SYSCON_PDSLEEPCFG_PDEN_ADC0_SHIFT (10U)
+#define SYSCON_PDSLEEPCFG_PDEN_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_ADC0_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_ADC0_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_SRAMX_MASK (0x2000U)
+#define SYSCON_PDSLEEPCFG_PDEN_SRAMX_SHIFT (13U)
+#define SYSCON_PDSLEEPCFG_PDEN_SRAMX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SRAMX_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SRAMX_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_SRAM0_MASK (0x4000U)
+#define SYSCON_PDSLEEPCFG_PDEN_SRAM0_SHIFT (14U)
+#define SYSCON_PDSLEEPCFG_PDEN_SRAM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SRAM0_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SRAM0_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3_MASK (0x8000U)
+#define SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3_SHIFT (15U)
+#define SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SRAM1_2_3_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_USB_RAM_MASK (0x10000U)
+#define SYSCON_PDSLEEPCFG_PDEN_USB_RAM_SHIFT (16U)
+#define SYSCON_PDSLEEPCFG_PDEN_USB_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_USB_RAM_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_USB_RAM_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_ROM_MASK (0x20000U)
+#define SYSCON_PDSLEEPCFG_PDEN_ROM_SHIFT (17U)
+#define SYSCON_PDSLEEPCFG_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_ROM_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_ROM_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_VDDA_MASK (0x80000U)
+#define SYSCON_PDSLEEPCFG_PDEN_VDDA_SHIFT (19U)
+#define SYSCON_PDSLEEPCFG_PDEN_VDDA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VDDA_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VDDA_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_WDT_OSC_MASK (0x100000U)
+#define SYSCON_PDSLEEPCFG_PDEN_WDT_OSC_SHIFT (20U)
+#define SYSCON_PDSLEEPCFG_PDEN_WDT_OSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_WDT_OSC_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_USB0_PHY_MASK (0x200000U)
+#define SYSCON_PDSLEEPCFG_PDEN_USB0_PHY_SHIFT (21U)
+#define SYSCON_PDSLEEPCFG_PDEN_USB0_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_USB0_PHY_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_USB0_PHY_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_SYS_PLL_MASK (0x400000U)
+#define SYSCON_PDSLEEPCFG_PDEN_SYS_PLL_SHIFT (22U)
+#define SYSCON_PDSLEEPCFG_PDEN_SYS_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_SYS_PLL_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_VREFP_MASK (0x800000U)
+#define SYSCON_PDSLEEPCFG_PDEN_VREFP_SHIFT (23U)
+#define SYSCON_PDSLEEPCFG_PDEN_VREFP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VREFP_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VREFP_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_VD3_MASK (0x4000000U)
+#define SYSCON_PDSLEEPCFG_PDEN_VD3_SHIFT (26U)
+#define SYSCON_PDSLEEPCFG_PDEN_VD3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD3_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD3_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_VD4_MASK (0x8000000U)
+#define SYSCON_PDSLEEPCFG_PDEN_VD4_SHIFT (27U)
+#define SYSCON_PDSLEEPCFG_PDEN_VD4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD4_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD4_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_VD5_MASK (0x10000000U)
+#define SYSCON_PDSLEEPCFG_PDEN_VD5_SHIFT (28U)
+#define SYSCON_PDSLEEPCFG_PDEN_VD5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD5_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD5_MASK)
+#define SYSCON_PDSLEEPCFG_PDEN_VD6_MASK (0x20000000U)
+#define SYSCON_PDSLEEPCFG_PDEN_VD6_SHIFT (29U)
+#define SYSCON_PDSLEEPCFG_PDEN_VD6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDSLEEPCFG_PDEN_VD6_SHIFT)) & SYSCON_PDSLEEPCFG_PDEN_VD6_MASK)
+
+/* The count of SYSCON_PDSLEEPCFG */
+#define SYSCON_PDSLEEPCFG_COUNT (2U)
+
+/*! @name PDRUNCFG - Power configuration register 0 */
+#define SYSCON_PDRUNCFG_PDEN_USB1_PHY_MASK (0x1U)
+#define SYSCON_PDRUNCFG_PDEN_USB1_PHY_SHIFT (0U)
+#define SYSCON_PDRUNCFG_PDEN_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB1_PHY_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB1_PHY_MASK)
+#define SYSCON_PDRUNCFG_PDEN_USB1_PLL_MASK (0x2U)
+#define SYSCON_PDRUNCFG_PDEN_USB1_PLL_SHIFT (1U)
+#define SYSCON_PDRUNCFG_PDEN_USB1_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB1_PLL_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB1_PLL_MASK)
+#define SYSCON_PDRUNCFG_PDEN_AUD_PLL_MASK (0x4U)
+#define SYSCON_PDRUNCFG_PDEN_AUD_PLL_SHIFT (2U)
+#define SYSCON_PDRUNCFG_PDEN_AUD_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_AUD_PLL_SHIFT)) & SYSCON_PDRUNCFG_PDEN_AUD_PLL_MASK)
+#define SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK (0x8U)
+#define SYSCON_PDRUNCFG_PDEN_SYSOSC_SHIFT (3U)
+#define SYSCON_PDRUNCFG_PDEN_SYSOSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SYSOSC_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK)
+#define SYSCON_PDRUNCFG_PDEN_FRO_MASK (0x10U)
+#define SYSCON_PDRUNCFG_PDEN_FRO_SHIFT (4U)
+#define SYSCON_PDRUNCFG_PDEN_FRO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_FRO_SHIFT)) & SYSCON_PDRUNCFG_PDEN_FRO_MASK)
+#define SYSCON_PDRUNCFG_PDEN_EEPROM_MASK (0x20U)
+#define SYSCON_PDRUNCFG_PDEN_EEPROM_SHIFT (5U)
+#define SYSCON_PDRUNCFG_PDEN_EEPROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_EEPROM_SHIFT)) & SYSCON_PDRUNCFG_PDEN_EEPROM_MASK)
+#define SYSCON_PDRUNCFG_PDEN_TS_MASK (0x40U)
+#define SYSCON_PDRUNCFG_PDEN_TS_SHIFT (6U)
+#define SYSCON_PDRUNCFG_PDEN_TS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_TS_SHIFT)) & SYSCON_PDRUNCFG_PDEN_TS_MASK)
+#define SYSCON_PDRUNCFG_PDEN_BOD_RST_MASK (0x80U)
+#define SYSCON_PDRUNCFG_PDEN_BOD_RST_SHIFT (7U)
+#define SYSCON_PDRUNCFG_PDEN_BOD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_BOD_RST_SHIFT)) & SYSCON_PDRUNCFG_PDEN_BOD_RST_MASK)
+#define SYSCON_PDRUNCFG_PDEN_RNG_MASK (0x80U)
+#define SYSCON_PDRUNCFG_PDEN_RNG_SHIFT (7U)
+#define SYSCON_PDRUNCFG_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_RNG_SHIFT)) & SYSCON_PDRUNCFG_PDEN_RNG_MASK)
+#define SYSCON_PDRUNCFG_PDEN_BOD_INTR_MASK (0x100U)
+#define SYSCON_PDRUNCFG_PDEN_BOD_INTR_SHIFT (8U)
+#define SYSCON_PDRUNCFG_PDEN_BOD_INTR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDRUNCFG_PDEN_BOD_INTR_MASK)
+#define SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK (0x200U)
+#define SYSCON_PDRUNCFG_PDEN_VD2_ANA_SHIFT (9U)
+#define SYSCON_PDRUNCFG_PDEN_VD2_ANA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD2_ANA_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK)
+#define SYSCON_PDRUNCFG_PDEN_ADC0_MASK (0x400U)
+#define SYSCON_PDRUNCFG_PDEN_ADC0_SHIFT (10U)
+#define SYSCON_PDRUNCFG_PDEN_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_ADC0_SHIFT)) & SYSCON_PDRUNCFG_PDEN_ADC0_MASK)
+#define SYSCON_PDRUNCFG_PDEN_SRAMX_MASK (0x2000U)
+#define SYSCON_PDRUNCFG_PDEN_SRAMX_SHIFT (13U)
+#define SYSCON_PDRUNCFG_PDEN_SRAMX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAMX_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAMX_MASK)
+#define SYSCON_PDRUNCFG_PDEN_SRAM0_MASK (0x4000U)
+#define SYSCON_PDRUNCFG_PDEN_SRAM0_SHIFT (14U)
+#define SYSCON_PDRUNCFG_PDEN_SRAM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAM0_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAM0_MASK)
+#define SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_MASK (0x8000U)
+#define SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_SHIFT (15U)
+#define SYSCON_PDRUNCFG_PDEN_SRAM1_2_3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SRAM1_2_3_MASK)
+#define SYSCON_PDRUNCFG_PDEN_USB_RAM_MASK (0x10000U)
+#define SYSCON_PDRUNCFG_PDEN_USB_RAM_SHIFT (16U)
+#define SYSCON_PDRUNCFG_PDEN_USB_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB_RAM_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB_RAM_MASK)
+#define SYSCON_PDRUNCFG_PDEN_ROM_MASK (0x20000U)
+#define SYSCON_PDRUNCFG_PDEN_ROM_SHIFT (17U)
+#define SYSCON_PDRUNCFG_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_ROM_SHIFT)) & SYSCON_PDRUNCFG_PDEN_ROM_MASK)
+#define SYSCON_PDRUNCFG_PDEN_VDDA_MASK (0x80000U)
+#define SYSCON_PDRUNCFG_PDEN_VDDA_SHIFT (19U)
+#define SYSCON_PDRUNCFG_PDEN_VDDA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VDDA_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VDDA_MASK)
+#define SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK (0x100000U)
+#define SYSCON_PDRUNCFG_PDEN_WDT_OSC_SHIFT (20U)
+#define SYSCON_PDRUNCFG_PDEN_WDT_OSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK)
+#define SYSCON_PDRUNCFG_PDEN_USB0_PHY_MASK (0x200000U)
+#define SYSCON_PDRUNCFG_PDEN_USB0_PHY_SHIFT (21U)
+#define SYSCON_PDRUNCFG_PDEN_USB0_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_USB0_PHY_SHIFT)) & SYSCON_PDRUNCFG_PDEN_USB0_PHY_MASK)
+#define SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK (0x400000U)
+#define SYSCON_PDRUNCFG_PDEN_SYS_PLL_SHIFT (22U)
+#define SYSCON_PDRUNCFG_PDEN_SYS_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDRUNCFG_PDEN_SYS_PLL_MASK)
+#define SYSCON_PDRUNCFG_PDEN_VREFP_MASK (0x800000U)
+#define SYSCON_PDRUNCFG_PDEN_VREFP_SHIFT (23U)
+#define SYSCON_PDRUNCFG_PDEN_VREFP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VREFP_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VREFP_MASK)
+#define SYSCON_PDRUNCFG_PDEN_VD3_MASK (0x4000000U)
+#define SYSCON_PDRUNCFG_PDEN_VD3_SHIFT (26U)
+#define SYSCON_PDRUNCFG_PDEN_VD3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD3_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD3_MASK)
+#define SYSCON_PDRUNCFG_PDEN_VD4_MASK (0x8000000U)
+#define SYSCON_PDRUNCFG_PDEN_VD4_SHIFT (27U)
+#define SYSCON_PDRUNCFG_PDEN_VD4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD4_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD4_MASK)
+#define SYSCON_PDRUNCFG_PDEN_VD5_MASK (0x10000000U)
+#define SYSCON_PDRUNCFG_PDEN_VD5_SHIFT (28U)
+#define SYSCON_PDRUNCFG_PDEN_VD5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD5_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD5_MASK)
+#define SYSCON_PDRUNCFG_PDEN_VD6_MASK (0x20000000U)
+#define SYSCON_PDRUNCFG_PDEN_VD6_SHIFT (29U)
+#define SYSCON_PDRUNCFG_PDEN_VD6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFG_PDEN_VD6_SHIFT)) & SYSCON_PDRUNCFG_PDEN_VD6_MASK)
+
+/* The count of SYSCON_PDRUNCFG */
+#define SYSCON_PDRUNCFG_COUNT (2U)
+
+/*! @name PDRUNCFGSET - Set bits in PDRUNCFG0 */
+#define SYSCON_PDRUNCFGSET_PDEN_USB1_PHY_MASK (0x1U)
+#define SYSCON_PDRUNCFGSET_PDEN_USB1_PHY_SHIFT (0U)
+#define SYSCON_PDRUNCFGSET_PDEN_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_USB1_PHY_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_USB1_PHY_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_USB1_PLL_MASK (0x2U)
+#define SYSCON_PDRUNCFGSET_PDEN_USB1_PLL_SHIFT (1U)
+#define SYSCON_PDRUNCFGSET_PDEN_USB1_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_USB1_PLL_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_USB1_PLL_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_AUD_PLL_MASK (0x4U)
+#define SYSCON_PDRUNCFGSET_PDEN_AUD_PLL_SHIFT (2U)
+#define SYSCON_PDRUNCFGSET_PDEN_AUD_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_AUD_PLL_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_AUD_PLL_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_SYSOSC_MASK (0x8U)
+#define SYSCON_PDRUNCFGSET_PDEN_SYSOSC_SHIFT (3U)
+#define SYSCON_PDRUNCFGSET_PDEN_SYSOSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SYSOSC_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SYSOSC_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_FRO_MASK (0x10U)
+#define SYSCON_PDRUNCFGSET_PDEN_FRO_SHIFT (4U)
+#define SYSCON_PDRUNCFGSET_PDEN_FRO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_FRO_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_FRO_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_EEPROM_MASK (0x20U)
+#define SYSCON_PDRUNCFGSET_PDEN_EEPROM_SHIFT (5U)
+#define SYSCON_PDRUNCFGSET_PDEN_EEPROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_EEPROM_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_EEPROM_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_TS_MASK (0x40U)
+#define SYSCON_PDRUNCFGSET_PDEN_TS_SHIFT (6U)
+#define SYSCON_PDRUNCFGSET_PDEN_TS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_TS_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_TS_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_BOD_RST_MASK (0x80U)
+#define SYSCON_PDRUNCFGSET_PDEN_BOD_RST_SHIFT (7U)
+#define SYSCON_PDRUNCFGSET_PDEN_BOD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_BOD_RST_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_BOD_RST_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_RNG_MASK (0x80U)
+#define SYSCON_PDRUNCFGSET_PDEN_RNG_SHIFT (7U)
+#define SYSCON_PDRUNCFGSET_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_RNG_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_RNG_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_BOD_INTR_MASK (0x100U)
+#define SYSCON_PDRUNCFGSET_PDEN_BOD_INTR_SHIFT (8U)
+#define SYSCON_PDRUNCFGSET_PDEN_BOD_INTR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_BOD_INTR_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_VD2_ANA_MASK (0x200U)
+#define SYSCON_PDRUNCFGSET_PDEN_VD2_ANA_SHIFT (9U)
+#define SYSCON_PDRUNCFGSET_PDEN_VD2_ANA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD2_ANA_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD2_ANA_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_ADC0_MASK (0x400U)
+#define SYSCON_PDRUNCFGSET_PDEN_ADC0_SHIFT (10U)
+#define SYSCON_PDRUNCFGSET_PDEN_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_ADC0_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_ADC0_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_SRAMX_MASK (0x2000U)
+#define SYSCON_PDRUNCFGSET_PDEN_SRAMX_SHIFT (13U)
+#define SYSCON_PDRUNCFGSET_PDEN_SRAMX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SRAMX_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SRAMX_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_SRAM0_MASK (0x4000U)
+#define SYSCON_PDRUNCFGSET_PDEN_SRAM0_SHIFT (14U)
+#define SYSCON_PDRUNCFGSET_PDEN_SRAM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SRAM0_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SRAM0_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3_MASK (0x8000U)
+#define SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3_SHIFT (15U)
+#define SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SRAM1_2_3_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_USB_RAM_MASK (0x10000U)
+#define SYSCON_PDRUNCFGSET_PDEN_USB_RAM_SHIFT (16U)
+#define SYSCON_PDRUNCFGSET_PDEN_USB_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_USB_RAM_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_USB_RAM_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_ROM_MASK (0x20000U)
+#define SYSCON_PDRUNCFGSET_PDEN_ROM_SHIFT (17U)
+#define SYSCON_PDRUNCFGSET_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_ROM_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_ROM_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_VDDA_MASK (0x80000U)
+#define SYSCON_PDRUNCFGSET_PDEN_VDDA_SHIFT (19U)
+#define SYSCON_PDRUNCFGSET_PDEN_VDDA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VDDA_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VDDA_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_WDT_OSC_MASK (0x100000U)
+#define SYSCON_PDRUNCFGSET_PDEN_WDT_OSC_SHIFT (20U)
+#define SYSCON_PDRUNCFGSET_PDEN_WDT_OSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_WDT_OSC_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_USB0_PHY_MASK (0x200000U)
+#define SYSCON_PDRUNCFGSET_PDEN_USB0_PHY_SHIFT (21U)
+#define SYSCON_PDRUNCFGSET_PDEN_USB0_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_USB0_PHY_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_USB0_PHY_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_SYS_PLL_MASK (0x400000U)
+#define SYSCON_PDRUNCFGSET_PDEN_SYS_PLL_SHIFT (22U)
+#define SYSCON_PDRUNCFGSET_PDEN_SYS_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_SYS_PLL_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_VREFP_MASK (0x800000U)
+#define SYSCON_PDRUNCFGSET_PDEN_VREFP_SHIFT (23U)
+#define SYSCON_PDRUNCFGSET_PDEN_VREFP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VREFP_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VREFP_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_VD3_MASK (0x4000000U)
+#define SYSCON_PDRUNCFGSET_PDEN_VD3_SHIFT (26U)
+#define SYSCON_PDRUNCFGSET_PDEN_VD3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD3_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD3_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_VD4_MASK (0x8000000U)
+#define SYSCON_PDRUNCFGSET_PDEN_VD4_SHIFT (27U)
+#define SYSCON_PDRUNCFGSET_PDEN_VD4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD4_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD4_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_VD5_MASK (0x10000000U)
+#define SYSCON_PDRUNCFGSET_PDEN_VD5_SHIFT (28U)
+#define SYSCON_PDRUNCFGSET_PDEN_VD5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD5_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD5_MASK)
+#define SYSCON_PDRUNCFGSET_PDEN_VD6_MASK (0x20000000U)
+#define SYSCON_PDRUNCFGSET_PDEN_VD6_SHIFT (29U)
+#define SYSCON_PDRUNCFGSET_PDEN_VD6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGSET_PDEN_VD6_SHIFT)) & SYSCON_PDRUNCFGSET_PDEN_VD6_MASK)
+
+/* The count of SYSCON_PDRUNCFGSET */
+#define SYSCON_PDRUNCFGSET_COUNT (2U)
+
+/*! @name PDRUNCFGCLR - Clear bits in PDRUNCFG0 */
+#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY_MASK (0x1U)
+#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY_SHIFT (0U)
+#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_USB1_PHY_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL_MASK (0x2U)
+#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL_SHIFT (1U)
+#define SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_USB1_PLL_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL_MASK (0x4U)
+#define SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL_SHIFT (2U)
+#define SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_AUD_PLL_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_SYSOSC_MASK (0x8U)
+#define SYSCON_PDRUNCFGCLR_PDEN_SYSOSC_SHIFT (3U)
+#define SYSCON_PDRUNCFGCLR_PDEN_SYSOSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SYSOSC_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SYSOSC_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_FRO_MASK (0x10U)
+#define SYSCON_PDRUNCFGCLR_PDEN_FRO_SHIFT (4U)
+#define SYSCON_PDRUNCFGCLR_PDEN_FRO(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_FRO_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_FRO_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_EEPROM_MASK (0x20U)
+#define SYSCON_PDRUNCFGCLR_PDEN_EEPROM_SHIFT (5U)
+#define SYSCON_PDRUNCFGCLR_PDEN_EEPROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_EEPROM_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_EEPROM_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_TS_MASK (0x40U)
+#define SYSCON_PDRUNCFGCLR_PDEN_TS_SHIFT (6U)
+#define SYSCON_PDRUNCFGCLR_PDEN_TS(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_TS_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_TS_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_BOD_RST_MASK (0x80U)
+#define SYSCON_PDRUNCFGCLR_PDEN_BOD_RST_SHIFT (7U)
+#define SYSCON_PDRUNCFGCLR_PDEN_BOD_RST(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_BOD_RST_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_BOD_RST_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_RNG_MASK (0x80U)
+#define SYSCON_PDRUNCFGCLR_PDEN_RNG_SHIFT (7U)
+#define SYSCON_PDRUNCFGCLR_PDEN_RNG(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_RNG_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_RNG_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR_MASK (0x100U)
+#define SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR_SHIFT (8U)
+#define SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_BOD_INTR_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA_MASK (0x200U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA_SHIFT (9U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD2_ANA_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_ADC0_MASK (0x400U)
+#define SYSCON_PDRUNCFGCLR_PDEN_ADC0_SHIFT (10U)
+#define SYSCON_PDRUNCFGCLR_PDEN_ADC0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_ADC0_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_ADC0_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAMX_MASK (0x2000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAMX_SHIFT (13U)
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAMX(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SRAMX_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SRAMX_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAM0_MASK (0x4000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAM0_SHIFT (14U)
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SRAM0_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SRAM0_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3_MASK (0x8000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3_SHIFT (15U)
+#define SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SRAM1_2_3_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_USB_RAM_MASK (0x10000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_USB_RAM_SHIFT (16U)
+#define SYSCON_PDRUNCFGCLR_PDEN_USB_RAM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_USB_RAM_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_USB_RAM_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_ROM_MASK (0x20000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_ROM_SHIFT (17U)
+#define SYSCON_PDRUNCFGCLR_PDEN_ROM(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_ROM_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_ROM_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_VDDA_MASK (0x80000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VDDA_SHIFT (19U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VDDA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VDDA_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VDDA_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC_MASK (0x100000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC_SHIFT (20U)
+#define SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_WDT_OSC_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY_MASK (0x200000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY_SHIFT (21U)
+#define SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_USB0_PHY_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL_MASK (0x400000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL_SHIFT (22U)
+#define SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_SYS_PLL_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_VREFP_MASK (0x800000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VREFP_SHIFT (23U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VREFP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VREFP_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VREFP_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD3_MASK (0x4000000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD3_SHIFT (26U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD3_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD3_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD4_MASK (0x8000000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD4_SHIFT (27U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD4_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD4_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD5_MASK (0x10000000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD5_SHIFT (28U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD5_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD5_MASK)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD6_MASK (0x20000000U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD6_SHIFT (29U)
+#define SYSCON_PDRUNCFGCLR_PDEN_VD6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_PDRUNCFGCLR_PDEN_VD6_SHIFT)) & SYSCON_PDRUNCFGCLR_PDEN_VD6_MASK)
+
+/* The count of SYSCON_PDRUNCFGCLR */
+#define SYSCON_PDRUNCFGCLR_COUNT (2U)
+
+/*! @name STARTER - Start logic 0 wake-up enable register */
+#define SYSCON_STARTER_WDT_BOD_MASK (0x1U)
+#define SYSCON_STARTER_WDT_BOD_SHIFT (0U)
+#define SYSCON_STARTER_WDT_BOD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_WDT_BOD_SHIFT)) & SYSCON_STARTER_WDT_BOD_MASK)
+#define SYSCON_STARTER_PINT4_MASK (0x1U)
+#define SYSCON_STARTER_PINT4_SHIFT (0U)
+#define SYSCON_STARTER_PINT4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PINT4_SHIFT)) & SYSCON_STARTER_PINT4_MASK)
+#define SYSCON_STARTER_PINT5_MASK (0x2U)
+#define SYSCON_STARTER_PINT5_SHIFT (1U)
+#define SYSCON_STARTER_PINT5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PINT5_SHIFT)) & SYSCON_STARTER_PINT5_MASK)
+#define SYSCON_STARTER_DMA_MASK (0x2U)
+#define SYSCON_STARTER_DMA_SHIFT (1U)
+#define SYSCON_STARTER_DMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_DMA_SHIFT)) & SYSCON_STARTER_DMA_MASK)
+#define SYSCON_STARTER_GINT0_MASK (0x4U)
+#define SYSCON_STARTER_GINT0_SHIFT (2U)
+#define SYSCON_STARTER_GINT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GINT0_SHIFT)) & SYSCON_STARTER_GINT0_MASK)
+#define SYSCON_STARTER_PINT6_MASK (0x4U)
+#define SYSCON_STARTER_PINT6_SHIFT (2U)
+#define SYSCON_STARTER_PINT6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PINT6_SHIFT)) & SYSCON_STARTER_PINT6_MASK)
+#define SYSCON_STARTER_GINT1_MASK (0x8U)
+#define SYSCON_STARTER_GINT1_SHIFT (3U)
+#define SYSCON_STARTER_GINT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_GINT1_SHIFT)) & SYSCON_STARTER_GINT1_MASK)
+#define SYSCON_STARTER_PINT7_MASK (0x8U)
+#define SYSCON_STARTER_PINT7_SHIFT (3U)
+#define SYSCON_STARTER_PINT7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PINT7_SHIFT)) & SYSCON_STARTER_PINT7_MASK)
+#define SYSCON_STARTER_CTIMER2_MASK (0x10U)
+#define SYSCON_STARTER_CTIMER2_SHIFT (4U)
+#define SYSCON_STARTER_CTIMER2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER2_SHIFT)) & SYSCON_STARTER_CTIMER2_MASK)
+#define SYSCON_STARTER_PIN_INT0_MASK (0x10U)
+#define SYSCON_STARTER_PIN_INT0_SHIFT (4U)
+#define SYSCON_STARTER_PIN_INT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT0_SHIFT)) & SYSCON_STARTER_PIN_INT0_MASK)
+#define SYSCON_STARTER_CTIMER4_MASK (0x20U)
+#define SYSCON_STARTER_CTIMER4_SHIFT (5U)
+#define SYSCON_STARTER_CTIMER4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER4_SHIFT)) & SYSCON_STARTER_CTIMER4_MASK)
+#define SYSCON_STARTER_PIN_INT1_MASK (0x20U)
+#define SYSCON_STARTER_PIN_INT1_SHIFT (5U)
+#define SYSCON_STARTER_PIN_INT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT1_SHIFT)) & SYSCON_STARTER_PIN_INT1_MASK)
+#define SYSCON_STARTER_PIN_INT2_MASK (0x40U)
+#define SYSCON_STARTER_PIN_INT2_SHIFT (6U)
+#define SYSCON_STARTER_PIN_INT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT2_SHIFT)) & SYSCON_STARTER_PIN_INT2_MASK)
+#define SYSCON_STARTER_PIN_INT3_MASK (0x80U)
+#define SYSCON_STARTER_PIN_INT3_SHIFT (7U)
+#define SYSCON_STARTER_PIN_INT3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_PIN_INT3_SHIFT)) & SYSCON_STARTER_PIN_INT3_MASK)
+#define SYSCON_STARTER_SPIFI_MASK (0x80U)
+#define SYSCON_STARTER_SPIFI_SHIFT (7U)
+#define SYSCON_STARTER_SPIFI(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SPIFI_SHIFT)) & SYSCON_STARTER_SPIFI_MASK)
+#define SYSCON_STARTER_FLEXCOMM8_MASK (0x100U)
+#define SYSCON_STARTER_FLEXCOMM8_SHIFT (8U)
+#define SYSCON_STARTER_FLEXCOMM8(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM8_SHIFT)) & SYSCON_STARTER_FLEXCOMM8_MASK)
+#define SYSCON_STARTER_UTICK_MASK (0x100U)
+#define SYSCON_STARTER_UTICK_SHIFT (8U)
+#define SYSCON_STARTER_UTICK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_UTICK_SHIFT)) & SYSCON_STARTER_UTICK_MASK)
+#define SYSCON_STARTER_MRT_MASK (0x200U)
+#define SYSCON_STARTER_MRT_SHIFT (9U)
+#define SYSCON_STARTER_MRT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_MRT_SHIFT)) & SYSCON_STARTER_MRT_MASK)
+#define SYSCON_STARTER_FLEXCOMM9_MASK (0x200U)
+#define SYSCON_STARTER_FLEXCOMM9_SHIFT (9U)
+#define SYSCON_STARTER_FLEXCOMM9(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM9_SHIFT)) & SYSCON_STARTER_FLEXCOMM9_MASK)
+#define SYSCON_STARTER_CTIMER0_MASK (0x400U)
+#define SYSCON_STARTER_CTIMER0_SHIFT (10U)
+#define SYSCON_STARTER_CTIMER0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER0_SHIFT)) & SYSCON_STARTER_CTIMER0_MASK)
+#define SYSCON_STARTER_CTIMER1_MASK (0x800U)
+#define SYSCON_STARTER_CTIMER1_SHIFT (11U)
+#define SYSCON_STARTER_CTIMER1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER1_SHIFT)) & SYSCON_STARTER_CTIMER1_MASK)
+#define SYSCON_STARTER_SCT0_MASK (0x1000U)
+#define SYSCON_STARTER_SCT0_SHIFT (12U)
+#define SYSCON_STARTER_SCT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SCT0_SHIFT)) & SYSCON_STARTER_SCT0_MASK)
+#define SYSCON_STARTER_CTIMER3_MASK (0x2000U)
+#define SYSCON_STARTER_CTIMER3_SHIFT (13U)
+#define SYSCON_STARTER_CTIMER3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_CTIMER3_SHIFT)) & SYSCON_STARTER_CTIMER3_MASK)
+#define SYSCON_STARTER_FLEXCOMM0_MASK (0x4000U)
+#define SYSCON_STARTER_FLEXCOMM0_SHIFT (14U)
+#define SYSCON_STARTER_FLEXCOMM0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM0_SHIFT)) & SYSCON_STARTER_FLEXCOMM0_MASK)
+#define SYSCON_STARTER_FLEXCOMM1_MASK (0x8000U)
+#define SYSCON_STARTER_FLEXCOMM1_SHIFT (15U)
+#define SYSCON_STARTER_FLEXCOMM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM1_SHIFT)) & SYSCON_STARTER_FLEXCOMM1_MASK)
+#define SYSCON_STARTER_USB1_MASK (0x8000U)
+#define SYSCON_STARTER_USB1_SHIFT (15U)
+#define SYSCON_STARTER_USB1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB1_SHIFT)) & SYSCON_STARTER_USB1_MASK)
+#define SYSCON_STARTER_FLEXCOMM2_MASK (0x10000U)
+#define SYSCON_STARTER_FLEXCOMM2_SHIFT (16U)
+#define SYSCON_STARTER_FLEXCOMM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM2_SHIFT)) & SYSCON_STARTER_FLEXCOMM2_MASK)
+#define SYSCON_STARTER_USB1_ACT_MASK (0x10000U)
+#define SYSCON_STARTER_USB1_ACT_SHIFT (16U)
+#define SYSCON_STARTER_USB1_ACT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB1_ACT_SHIFT)) & SYSCON_STARTER_USB1_ACT_MASK)
+#define SYSCON_STARTER_ENET_INT1_MASK (0x20000U)
+#define SYSCON_STARTER_ENET_INT1_SHIFT (17U)
+#define SYSCON_STARTER_ENET_INT1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ENET_INT1_SHIFT)) & SYSCON_STARTER_ENET_INT1_MASK)
+#define SYSCON_STARTER_FLEXCOMM3_MASK (0x20000U)
+#define SYSCON_STARTER_FLEXCOMM3_SHIFT (17U)
+#define SYSCON_STARTER_FLEXCOMM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM3_SHIFT)) & SYSCON_STARTER_FLEXCOMM3_MASK)
+#define SYSCON_STARTER_ENET_INT2_MASK (0x40000U)
+#define SYSCON_STARTER_ENET_INT2_SHIFT (18U)
+#define SYSCON_STARTER_ENET_INT2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ENET_INT2_SHIFT)) & SYSCON_STARTER_ENET_INT2_MASK)
+#define SYSCON_STARTER_FLEXCOMM4_MASK (0x40000U)
+#define SYSCON_STARTER_FLEXCOMM4_SHIFT (18U)
+#define SYSCON_STARTER_FLEXCOMM4(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM4_SHIFT)) & SYSCON_STARTER_FLEXCOMM4_MASK)
+#define SYSCON_STARTER_ENET_INT0_MASK (0x80000U)
+#define SYSCON_STARTER_ENET_INT0_SHIFT (19U)
+#define SYSCON_STARTER_ENET_INT0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ENET_INT0_SHIFT)) & SYSCON_STARTER_ENET_INT0_MASK)
+#define SYSCON_STARTER_FLEXCOMM5_MASK (0x80000U)
+#define SYSCON_STARTER_FLEXCOMM5_SHIFT (19U)
+#define SYSCON_STARTER_FLEXCOMM5(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM5_SHIFT)) & SYSCON_STARTER_FLEXCOMM5_MASK)
+#define SYSCON_STARTER_FLEXCOMM6_MASK (0x100000U)
+#define SYSCON_STARTER_FLEXCOMM6_SHIFT (20U)
+#define SYSCON_STARTER_FLEXCOMM6(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM6_SHIFT)) & SYSCON_STARTER_FLEXCOMM6_MASK)
+#define SYSCON_STARTER_FLEXCOMM7_MASK (0x200000U)
+#define SYSCON_STARTER_FLEXCOMM7_SHIFT (21U)
+#define SYSCON_STARTER_FLEXCOMM7(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_FLEXCOMM7_SHIFT)) & SYSCON_STARTER_FLEXCOMM7_MASK)
+#define SYSCON_STARTER_ADC0_SEQA_MASK (0x400000U)
+#define SYSCON_STARTER_ADC0_SEQA_SHIFT (22U)
+#define SYSCON_STARTER_ADC0_SEQA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ADC0_SEQA_SHIFT)) & SYSCON_STARTER_ADC0_SEQA_MASK)
+#define SYSCON_STARTER_SMARTCARD0_MASK (0x800000U)
+#define SYSCON_STARTER_SMARTCARD0_SHIFT (23U)
+#define SYSCON_STARTER_SMARTCARD0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SMARTCARD0_SHIFT)) & SYSCON_STARTER_SMARTCARD0_MASK)
+#define SYSCON_STARTER_ADC0_SEQB_MASK (0x800000U)
+#define SYSCON_STARTER_ADC0_SEQB_SHIFT (23U)
+#define SYSCON_STARTER_ADC0_SEQB(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ADC0_SEQB_SHIFT)) & SYSCON_STARTER_ADC0_SEQB_MASK)
+#define SYSCON_STARTER_ADC0_THCMP_MASK (0x1000000U)
+#define SYSCON_STARTER_ADC0_THCMP_SHIFT (24U)
+#define SYSCON_STARTER_ADC0_THCMP(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_ADC0_THCMP_SHIFT)) & SYSCON_STARTER_ADC0_THCMP_MASK)
+#define SYSCON_STARTER_SMARTCARD1_MASK (0x1000000U)
+#define SYSCON_STARTER_SMARTCARD1_SHIFT (24U)
+#define SYSCON_STARTER_SMARTCARD1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_SMARTCARD1_SHIFT)) & SYSCON_STARTER_SMARTCARD1_MASK)
+#define SYSCON_STARTER_DMIC_MASK (0x2000000U)
+#define SYSCON_STARTER_DMIC_SHIFT (25U)
+#define SYSCON_STARTER_DMIC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_DMIC_SHIFT)) & SYSCON_STARTER_DMIC_MASK)
+#define SYSCON_STARTER_HWVAD_MASK (0x4000000U)
+#define SYSCON_STARTER_HWVAD_SHIFT (26U)
+#define SYSCON_STARTER_HWVAD(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_HWVAD_SHIFT)) & SYSCON_STARTER_HWVAD_MASK)
+#define SYSCON_STARTER_USB0_NEEDCLK_MASK (0x8000000U)
+#define SYSCON_STARTER_USB0_NEEDCLK_SHIFT (27U)
+#define SYSCON_STARTER_USB0_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB0_NEEDCLK_SHIFT)) & SYSCON_STARTER_USB0_NEEDCLK_MASK)
+#define SYSCON_STARTER_USB0_MASK (0x10000000U)
+#define SYSCON_STARTER_USB0_SHIFT (28U)
+#define SYSCON_STARTER_USB0(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_USB0_SHIFT)) & SYSCON_STARTER_USB0_MASK)
+#define SYSCON_STARTER_RTC_MASK (0x20000000U)
+#define SYSCON_STARTER_RTC_SHIFT (29U)
+#define SYSCON_STARTER_RTC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTER_RTC_SHIFT)) & SYSCON_STARTER_RTC_MASK)
+
+/* The count of SYSCON_STARTER */
+#define SYSCON_STARTER_COUNT (2U)
+
+/*! @name STARTERSET - Set bits in STARTER */
+#define SYSCON_STARTERSET_START_SET_MASK (0xFFFFFFFFU)
+#define SYSCON_STARTERSET_START_SET_SHIFT (0U)
+#define SYSCON_STARTERSET_START_SET(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERSET_START_SET_SHIFT)) & SYSCON_STARTERSET_START_SET_MASK)
+
+/* The count of SYSCON_STARTERSET */
+#define SYSCON_STARTERSET_COUNT (2U)
+
+/*! @name STARTERCLR - Clear bits in STARTER0 */
+#define SYSCON_STARTERCLR_START_CLR_MASK (0xFFFFFFFFU)
+#define SYSCON_STARTERCLR_START_CLR_SHIFT (0U)
+#define SYSCON_STARTERCLR_START_CLR(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_STARTERCLR_START_CLR_SHIFT)) & SYSCON_STARTERCLR_START_CLR_MASK)
+
+/* The count of SYSCON_STARTERCLR */
+#define SYSCON_STARTERCLR_COUNT (2U)
+
+/*! @name HWWAKE - Configures special cases of hardware wake-up */
+#define SYSCON_HWWAKE_FORCEWAKE_MASK (0x1U)
+#define SYSCON_HWWAKE_FORCEWAKE_SHIFT (0U)
+#define SYSCON_HWWAKE_FORCEWAKE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_FORCEWAKE_SHIFT)) & SYSCON_HWWAKE_FORCEWAKE_MASK)
+#define SYSCON_HWWAKE_FCWAKE_MASK (0x2U)
+#define SYSCON_HWWAKE_FCWAKE_SHIFT (1U)
+#define SYSCON_HWWAKE_FCWAKE(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_FCWAKE_SHIFT)) & SYSCON_HWWAKE_FCWAKE_MASK)
+#define SYSCON_HWWAKE_WAKEDMIC_MASK (0x4U)
+#define SYSCON_HWWAKE_WAKEDMIC_SHIFT (2U)
+#define SYSCON_HWWAKE_WAKEDMIC(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_WAKEDMIC_SHIFT)) & SYSCON_HWWAKE_WAKEDMIC_MASK)
+#define SYSCON_HWWAKE_WAKEDMA_MASK (0x8U)
+#define SYSCON_HWWAKE_WAKEDMA_SHIFT (3U)
+#define SYSCON_HWWAKE_WAKEDMA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_HWWAKE_WAKEDMA_SHIFT)) & SYSCON_HWWAKE_WAKEDMA_MASK)
+
+/*! @name AUTOCGOR - Auto Clock-Gate Override Register */
+#define SYSCON_AUTOCGOR_RAM0X_MASK (0x2U)
+#define SYSCON_AUTOCGOR_RAM0X_SHIFT (1U)
+#define SYSCON_AUTOCGOR_RAM0X(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM0X_SHIFT)) & SYSCON_AUTOCGOR_RAM0X_MASK)
+#define SYSCON_AUTOCGOR_RAM1_MASK (0x4U)
+#define SYSCON_AUTOCGOR_RAM1_SHIFT (2U)
+#define SYSCON_AUTOCGOR_RAM1(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM1_SHIFT)) & SYSCON_AUTOCGOR_RAM1_MASK)
+#define SYSCON_AUTOCGOR_RAM2_MASK (0x8U)
+#define SYSCON_AUTOCGOR_RAM2_SHIFT (3U)
+#define SYSCON_AUTOCGOR_RAM2(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM2_SHIFT)) & SYSCON_AUTOCGOR_RAM2_MASK)
+#define SYSCON_AUTOCGOR_RAM3_MASK (0x10U)
+#define SYSCON_AUTOCGOR_RAM3_SHIFT (4U)
+#define SYSCON_AUTOCGOR_RAM3(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_AUTOCGOR_RAM3_SHIFT)) & SYSCON_AUTOCGOR_RAM3_MASK)
+
+/*! @name JTAGIDCODE - JTAG ID code register */
+#define SYSCON_JTAGIDCODE_JTAGID_MASK (0xFFFFFFFFU)
+#define SYSCON_JTAGIDCODE_JTAGID_SHIFT (0U)
+#define SYSCON_JTAGIDCODE_JTAGID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_JTAGIDCODE_JTAGID_SHIFT)) & SYSCON_JTAGIDCODE_JTAGID_MASK)
+
+/*! @name DEVICE_ID0 - Part ID register */
+#define SYSCON_DEVICE_ID0_PARTID_MASK (0xFFFFFFFFU)
+#define SYSCON_DEVICE_ID0_PARTID_SHIFT (0U)
+#define SYSCON_DEVICE_ID0_PARTID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID0_PARTID_SHIFT)) & SYSCON_DEVICE_ID0_PARTID_MASK)
+
+/*! @name DEVICE_ID1 - Boot ROM and die revision register */
+#define SYSCON_DEVICE_ID1_REVID_MASK (0xFFFFFFFFU)
+#define SYSCON_DEVICE_ID1_REVID_SHIFT (0U)
+#define SYSCON_DEVICE_ID1_REVID(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_DEVICE_ID1_REVID_SHIFT)) & SYSCON_DEVICE_ID1_REVID_MASK)
+
+/*! @name BODCTRL - Brown-Out Detect control */
+#define SYSCON_BODCTRL_BODRSTLEV_MASK (0x3U)
+#define SYSCON_BODCTRL_BODRSTLEV_SHIFT (0U)
+#define SYSCON_BODCTRL_BODRSTLEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTLEV_SHIFT)) & SYSCON_BODCTRL_BODRSTLEV_MASK)
+#define SYSCON_BODCTRL_BODRSTENA_MASK (0x4U)
+#define SYSCON_BODCTRL_BODRSTENA_SHIFT (2U)
+#define SYSCON_BODCTRL_BODRSTENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTENA_SHIFT)) & SYSCON_BODCTRL_BODRSTENA_MASK)
+#define SYSCON_BODCTRL_BODINTLEV_MASK (0x18U)
+#define SYSCON_BODCTRL_BODINTLEV_SHIFT (3U)
+#define SYSCON_BODCTRL_BODINTLEV(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTLEV_SHIFT)) & SYSCON_BODCTRL_BODINTLEV_MASK)
+#define SYSCON_BODCTRL_BODINTENA_MASK (0x20U)
+#define SYSCON_BODCTRL_BODINTENA_SHIFT (5U)
+#define SYSCON_BODCTRL_BODINTENA(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTENA_SHIFT)) & SYSCON_BODCTRL_BODINTENA_MASK)
+#define SYSCON_BODCTRL_BODRSTSTAT_MASK (0x40U)
+#define SYSCON_BODCTRL_BODRSTSTAT_SHIFT (6U)
+#define SYSCON_BODCTRL_BODRSTSTAT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODRSTSTAT_SHIFT)) & SYSCON_BODCTRL_BODRSTSTAT_MASK)
+#define SYSCON_BODCTRL_BODINTSTAT_MASK (0x80U)
+#define SYSCON_BODCTRL_BODINTSTAT_SHIFT (7U)
+#define SYSCON_BODCTRL_BODINTSTAT(x) (((uint32_t)(((uint32_t)(x)) << SYSCON_BODCTRL_BODINTSTAT_SHIFT)) & SYSCON_BODCTRL_BODINTSTAT_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group SYSCON_Register_Masks */
+
+
+/* SYSCON - Peripheral instance base addresses */
+/** Peripheral SYSCON base address */
+#define SYSCON_BASE (0x40000000u)
+/** Peripheral SYSCON base pointer */
+#define SYSCON ((SYSCON_Type *)SYSCON_BASE)
+/** Array initializer of SYSCON peripheral base addresses */
+#define SYSCON_BASE_ADDRS { SYSCON_BASE }
+/** Array initializer of SYSCON peripheral base pointers */
+#define SYSCON_BASE_PTRS { SYSCON }
+
+/*!
+ * @}
+ */ /* end of group SYSCON_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- USART Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USART_Peripheral_Access_Layer USART Peripheral Access Layer
+ * @{
+ */
+
+/** USART - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CFG; /**< USART Configuration register. Basic USART configuration settings that typically are not changed during operation., offset: 0x0 */
+ __IO uint32_t CTL; /**< USART Control register. USART control settings that are more likely to change during operation., offset: 0x4 */
+ __IO uint32_t STAT; /**< USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them., offset: 0x8 */
+ __IO uint32_t INTENSET; /**< Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set., offset: 0xC */
+ __O uint32_t INTENCLR; /**< Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared., offset: 0x10 */
+ uint8_t RESERVED_0[12];
+ __IO uint32_t BRG; /**< Baud Rate Generator register. 16-bit integer baud rate divisor value., offset: 0x20 */
+ __I uint32_t INTSTAT; /**< Interrupt status register. Reflects interrupts that are currently enabled., offset: 0x24 */
+ __IO uint32_t OSR; /**< Oversample selection register for asynchronous communication., offset: 0x28 */
+ __IO uint32_t ADDR; /**< Address register for automatic address matching., offset: 0x2C */
+ uint8_t RESERVED_1[3536];
+ __IO uint32_t FIFOCFG; /**< FIFO configuration and enable register., offset: 0xE00 */
+ __IO uint32_t FIFOSTAT; /**< FIFO status register., offset: 0xE04 */
+ __IO uint32_t FIFOTRIG; /**< FIFO trigger settings for interrupt and DMA request., offset: 0xE08 */
+ uint8_t RESERVED_2[4];
+ __IO uint32_t FIFOINTENSET; /**< FIFO interrupt enable set (enable) and read register., offset: 0xE10 */
+ __IO uint32_t FIFOINTENCLR; /**< FIFO interrupt enable clear (disable) and read register., offset: 0xE14 */
+ __I uint32_t FIFOINTSTAT; /**< FIFO interrupt status register., offset: 0xE18 */
+ uint8_t RESERVED_3[4];
+ __IO uint32_t FIFOWR; /**< FIFO write data., offset: 0xE20 */
+ uint8_t RESERVED_4[12];
+ __I uint32_t FIFORD; /**< FIFO read data., offset: 0xE30 */
+ uint8_t RESERVED_5[12];
+ __I uint32_t FIFORDNOPOP; /**< FIFO data read with no FIFO pop., offset: 0xE40 */
+ uint8_t RESERVED_6[440];
+ __I uint32_t ID; /**< Peripheral identification register., offset: 0xFFC */
+} USART_Type;
+
+/* ----------------------------------------------------------------------------
+ -- USART Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USART_Register_Masks USART Register Masks
+ * @{
+ */
+
+/*! @name CFG - USART Configuration register. Basic USART configuration settings that typically are not changed during operation. */
+#define USART_CFG_ENABLE_MASK (0x1U)
+#define USART_CFG_ENABLE_SHIFT (0U)
+#define USART_CFG_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_ENABLE_SHIFT)) & USART_CFG_ENABLE_MASK)
+#define USART_CFG_DATALEN_MASK (0xCU)
+#define USART_CFG_DATALEN_SHIFT (2U)
+#define USART_CFG_DATALEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_DATALEN_SHIFT)) & USART_CFG_DATALEN_MASK)
+#define USART_CFG_PARITYSEL_MASK (0x30U)
+#define USART_CFG_PARITYSEL_SHIFT (4U)
+#define USART_CFG_PARITYSEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_PARITYSEL_SHIFT)) & USART_CFG_PARITYSEL_MASK)
+#define USART_CFG_STOPLEN_MASK (0x40U)
+#define USART_CFG_STOPLEN_SHIFT (6U)
+#define USART_CFG_STOPLEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_STOPLEN_SHIFT)) & USART_CFG_STOPLEN_MASK)
+#define USART_CFG_MODE32K_MASK (0x80U)
+#define USART_CFG_MODE32K_SHIFT (7U)
+#define USART_CFG_MODE32K(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_MODE32K_SHIFT)) & USART_CFG_MODE32K_MASK)
+#define USART_CFG_LINMODE_MASK (0x100U)
+#define USART_CFG_LINMODE_SHIFT (8U)
+#define USART_CFG_LINMODE(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LINMODE_SHIFT)) & USART_CFG_LINMODE_MASK)
+#define USART_CFG_CTSEN_MASK (0x200U)
+#define USART_CFG_CTSEN_SHIFT (9U)
+#define USART_CFG_CTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CTSEN_SHIFT)) & USART_CFG_CTSEN_MASK)
+#define USART_CFG_SYNCEN_MASK (0x800U)
+#define USART_CFG_SYNCEN_SHIFT (11U)
+#define USART_CFG_SYNCEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCEN_SHIFT)) & USART_CFG_SYNCEN_MASK)
+#define USART_CFG_CLKPOL_MASK (0x1000U)
+#define USART_CFG_CLKPOL_SHIFT (12U)
+#define USART_CFG_CLKPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_CLKPOL_SHIFT)) & USART_CFG_CLKPOL_MASK)
+#define USART_CFG_SYNCMST_MASK (0x4000U)
+#define USART_CFG_SYNCMST_SHIFT (14U)
+#define USART_CFG_SYNCMST(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_SYNCMST_SHIFT)) & USART_CFG_SYNCMST_MASK)
+#define USART_CFG_LOOP_MASK (0x8000U)
+#define USART_CFG_LOOP_SHIFT (15U)
+#define USART_CFG_LOOP(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_LOOP_SHIFT)) & USART_CFG_LOOP_MASK)
+#define USART_CFG_OETA_MASK (0x40000U)
+#define USART_CFG_OETA_SHIFT (18U)
+#define USART_CFG_OETA(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OETA_SHIFT)) & USART_CFG_OETA_MASK)
+#define USART_CFG_AUTOADDR_MASK (0x80000U)
+#define USART_CFG_AUTOADDR_SHIFT (19U)
+#define USART_CFG_AUTOADDR(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_AUTOADDR_SHIFT)) & USART_CFG_AUTOADDR_MASK)
+#define USART_CFG_OESEL_MASK (0x100000U)
+#define USART_CFG_OESEL_SHIFT (20U)
+#define USART_CFG_OESEL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OESEL_SHIFT)) & USART_CFG_OESEL_MASK)
+#define USART_CFG_OEPOL_MASK (0x200000U)
+#define USART_CFG_OEPOL_SHIFT (21U)
+#define USART_CFG_OEPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_OEPOL_SHIFT)) & USART_CFG_OEPOL_MASK)
+#define USART_CFG_RXPOL_MASK (0x400000U)
+#define USART_CFG_RXPOL_SHIFT (22U)
+#define USART_CFG_RXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_RXPOL_SHIFT)) & USART_CFG_RXPOL_MASK)
+#define USART_CFG_TXPOL_MASK (0x800000U)
+#define USART_CFG_TXPOL_SHIFT (23U)
+#define USART_CFG_TXPOL(x) (((uint32_t)(((uint32_t)(x)) << USART_CFG_TXPOL_SHIFT)) & USART_CFG_TXPOL_MASK)
+
+/*! @name CTL - USART Control register. USART control settings that are more likely to change during operation. */
+#define USART_CTL_TXBRKEN_MASK (0x2U)
+#define USART_CTL_TXBRKEN_SHIFT (1U)
+#define USART_CTL_TXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXBRKEN_SHIFT)) & USART_CTL_TXBRKEN_MASK)
+#define USART_CTL_ADDRDET_MASK (0x4U)
+#define USART_CTL_ADDRDET_SHIFT (2U)
+#define USART_CTL_ADDRDET(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_ADDRDET_SHIFT)) & USART_CTL_ADDRDET_MASK)
+#define USART_CTL_TXDIS_MASK (0x40U)
+#define USART_CTL_TXDIS_SHIFT (6U)
+#define USART_CTL_TXDIS(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_TXDIS_SHIFT)) & USART_CTL_TXDIS_MASK)
+#define USART_CTL_CC_MASK (0x100U)
+#define USART_CTL_CC_SHIFT (8U)
+#define USART_CTL_CC(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CC_SHIFT)) & USART_CTL_CC_MASK)
+#define USART_CTL_CLRCCONRX_MASK (0x200U)
+#define USART_CTL_CLRCCONRX_SHIFT (9U)
+#define USART_CTL_CLRCCONRX(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_CLRCCONRX_SHIFT)) & USART_CTL_CLRCCONRX_MASK)
+#define USART_CTL_AUTOBAUD_MASK (0x10000U)
+#define USART_CTL_AUTOBAUD_SHIFT (16U)
+#define USART_CTL_AUTOBAUD(x) (((uint32_t)(((uint32_t)(x)) << USART_CTL_AUTOBAUD_SHIFT)) & USART_CTL_AUTOBAUD_MASK)
+
+/*! @name STAT - USART Status register. The complete status value can be read here. Writing ones clears some bits in the register. Some bits can be cleared by writing a 1 to them. */
+#define USART_STAT_RXIDLE_MASK (0x2U)
+#define USART_STAT_RXIDLE_SHIFT (1U)
+#define USART_STAT_RXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXIDLE_SHIFT)) & USART_STAT_RXIDLE_MASK)
+#define USART_STAT_TXIDLE_MASK (0x8U)
+#define USART_STAT_TXIDLE_SHIFT (3U)
+#define USART_STAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXIDLE_SHIFT)) & USART_STAT_TXIDLE_MASK)
+#define USART_STAT_CTS_MASK (0x10U)
+#define USART_STAT_CTS_SHIFT (4U)
+#define USART_STAT_CTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_CTS_SHIFT)) & USART_STAT_CTS_MASK)
+#define USART_STAT_DELTACTS_MASK (0x20U)
+#define USART_STAT_DELTACTS_SHIFT (5U)
+#define USART_STAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTACTS_SHIFT)) & USART_STAT_DELTACTS_MASK)
+#define USART_STAT_TXDISSTAT_MASK (0x40U)
+#define USART_STAT_TXDISSTAT_SHIFT (6U)
+#define USART_STAT_TXDISSTAT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_TXDISSTAT_SHIFT)) & USART_STAT_TXDISSTAT_MASK)
+#define USART_STAT_RXBRK_MASK (0x400U)
+#define USART_STAT_RXBRK_SHIFT (10U)
+#define USART_STAT_RXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXBRK_SHIFT)) & USART_STAT_RXBRK_MASK)
+#define USART_STAT_DELTARXBRK_MASK (0x800U)
+#define USART_STAT_DELTARXBRK_SHIFT (11U)
+#define USART_STAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_DELTARXBRK_SHIFT)) & USART_STAT_DELTARXBRK_MASK)
+#define USART_STAT_START_MASK (0x1000U)
+#define USART_STAT_START_SHIFT (12U)
+#define USART_STAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_START_SHIFT)) & USART_STAT_START_MASK)
+#define USART_STAT_FRAMERRINT_MASK (0x2000U)
+#define USART_STAT_FRAMERRINT_SHIFT (13U)
+#define USART_STAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_FRAMERRINT_SHIFT)) & USART_STAT_FRAMERRINT_MASK)
+#define USART_STAT_PARITYERRINT_MASK (0x4000U)
+#define USART_STAT_PARITYERRINT_SHIFT (14U)
+#define USART_STAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_PARITYERRINT_SHIFT)) & USART_STAT_PARITYERRINT_MASK)
+#define USART_STAT_RXNOISEINT_MASK (0x8000U)
+#define USART_STAT_RXNOISEINT_SHIFT (15U)
+#define USART_STAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_RXNOISEINT_SHIFT)) & USART_STAT_RXNOISEINT_MASK)
+#define USART_STAT_ABERR_MASK (0x10000U)
+#define USART_STAT_ABERR_SHIFT (16U)
+#define USART_STAT_ABERR(x) (((uint32_t)(((uint32_t)(x)) << USART_STAT_ABERR_SHIFT)) & USART_STAT_ABERR_MASK)
+
+/*! @name INTENSET - Interrupt Enable read and Set register for USART (not FIFO) status. Contains individual interrupt enable bits for each potential USART interrupt. A complete value may be read from this register. Writing a 1 to any implemented bit position causes that bit to be set. */
+#define USART_INTENSET_TXIDLEEN_MASK (0x8U)
+#define USART_INTENSET_TXIDLEEN_SHIFT (3U)
+#define USART_INTENSET_TXIDLEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXIDLEEN_SHIFT)) & USART_INTENSET_TXIDLEEN_MASK)
+#define USART_INTENSET_DELTACTSEN_MASK (0x20U)
+#define USART_INTENSET_DELTACTSEN_SHIFT (5U)
+#define USART_INTENSET_DELTACTSEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTACTSEN_SHIFT)) & USART_INTENSET_DELTACTSEN_MASK)
+#define USART_INTENSET_TXDISEN_MASK (0x40U)
+#define USART_INTENSET_TXDISEN_SHIFT (6U)
+#define USART_INTENSET_TXDISEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_TXDISEN_SHIFT)) & USART_INTENSET_TXDISEN_MASK)
+#define USART_INTENSET_DELTARXBRKEN_MASK (0x800U)
+#define USART_INTENSET_DELTARXBRKEN_SHIFT (11U)
+#define USART_INTENSET_DELTARXBRKEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_DELTARXBRKEN_SHIFT)) & USART_INTENSET_DELTARXBRKEN_MASK)
+#define USART_INTENSET_STARTEN_MASK (0x1000U)
+#define USART_INTENSET_STARTEN_SHIFT (12U)
+#define USART_INTENSET_STARTEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_STARTEN_SHIFT)) & USART_INTENSET_STARTEN_MASK)
+#define USART_INTENSET_FRAMERREN_MASK (0x2000U)
+#define USART_INTENSET_FRAMERREN_SHIFT (13U)
+#define USART_INTENSET_FRAMERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_FRAMERREN_SHIFT)) & USART_INTENSET_FRAMERREN_MASK)
+#define USART_INTENSET_PARITYERREN_MASK (0x4000U)
+#define USART_INTENSET_PARITYERREN_SHIFT (14U)
+#define USART_INTENSET_PARITYERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_PARITYERREN_SHIFT)) & USART_INTENSET_PARITYERREN_MASK)
+#define USART_INTENSET_RXNOISEEN_MASK (0x8000U)
+#define USART_INTENSET_RXNOISEEN_SHIFT (15U)
+#define USART_INTENSET_RXNOISEEN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_RXNOISEEN_SHIFT)) & USART_INTENSET_RXNOISEEN_MASK)
+#define USART_INTENSET_ABERREN_MASK (0x10000U)
+#define USART_INTENSET_ABERREN_SHIFT (16U)
+#define USART_INTENSET_ABERREN(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENSET_ABERREN_SHIFT)) & USART_INTENSET_ABERREN_MASK)
+
+/*! @name INTENCLR - Interrupt Enable Clear register. Allows clearing any combination of bits in the INTENSET register. Writing a 1 to any implemented bit position causes the corresponding bit to be cleared. */
+#define USART_INTENCLR_TXIDLECLR_MASK (0x8U)
+#define USART_INTENCLR_TXIDLECLR_SHIFT (3U)
+#define USART_INTENCLR_TXIDLECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXIDLECLR_SHIFT)) & USART_INTENCLR_TXIDLECLR_MASK)
+#define USART_INTENCLR_DELTACTSCLR_MASK (0x20U)
+#define USART_INTENCLR_DELTACTSCLR_SHIFT (5U)
+#define USART_INTENCLR_DELTACTSCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTACTSCLR_SHIFT)) & USART_INTENCLR_DELTACTSCLR_MASK)
+#define USART_INTENCLR_TXDISCLR_MASK (0x40U)
+#define USART_INTENCLR_TXDISCLR_SHIFT (6U)
+#define USART_INTENCLR_TXDISCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_TXDISCLR_SHIFT)) & USART_INTENCLR_TXDISCLR_MASK)
+#define USART_INTENCLR_DELTARXBRKCLR_MASK (0x800U)
+#define USART_INTENCLR_DELTARXBRKCLR_SHIFT (11U)
+#define USART_INTENCLR_DELTARXBRKCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_DELTARXBRKCLR_SHIFT)) & USART_INTENCLR_DELTARXBRKCLR_MASK)
+#define USART_INTENCLR_STARTCLR_MASK (0x1000U)
+#define USART_INTENCLR_STARTCLR_SHIFT (12U)
+#define USART_INTENCLR_STARTCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_STARTCLR_SHIFT)) & USART_INTENCLR_STARTCLR_MASK)
+#define USART_INTENCLR_FRAMERRCLR_MASK (0x2000U)
+#define USART_INTENCLR_FRAMERRCLR_SHIFT (13U)
+#define USART_INTENCLR_FRAMERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_FRAMERRCLR_SHIFT)) & USART_INTENCLR_FRAMERRCLR_MASK)
+#define USART_INTENCLR_PARITYERRCLR_MASK (0x4000U)
+#define USART_INTENCLR_PARITYERRCLR_SHIFT (14U)
+#define USART_INTENCLR_PARITYERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_PARITYERRCLR_SHIFT)) & USART_INTENCLR_PARITYERRCLR_MASK)
+#define USART_INTENCLR_RXNOISECLR_MASK (0x8000U)
+#define USART_INTENCLR_RXNOISECLR_SHIFT (15U)
+#define USART_INTENCLR_RXNOISECLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_RXNOISECLR_SHIFT)) & USART_INTENCLR_RXNOISECLR_MASK)
+#define USART_INTENCLR_ABERRCLR_MASK (0x10000U)
+#define USART_INTENCLR_ABERRCLR_SHIFT (16U)
+#define USART_INTENCLR_ABERRCLR(x) (((uint32_t)(((uint32_t)(x)) << USART_INTENCLR_ABERRCLR_SHIFT)) & USART_INTENCLR_ABERRCLR_MASK)
+
+/*! @name BRG - Baud Rate Generator register. 16-bit integer baud rate divisor value. */
+#define USART_BRG_BRGVAL_MASK (0xFFFFU)
+#define USART_BRG_BRGVAL_SHIFT (0U)
+#define USART_BRG_BRGVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_BRG_BRGVAL_SHIFT)) & USART_BRG_BRGVAL_MASK)
+
+/*! @name INTSTAT - Interrupt status register. Reflects interrupts that are currently enabled. */
+#define USART_INTSTAT_TXIDLE_MASK (0x8U)
+#define USART_INTSTAT_TXIDLE_SHIFT (3U)
+#define USART_INTSTAT_TXIDLE(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXIDLE_SHIFT)) & USART_INTSTAT_TXIDLE_MASK)
+#define USART_INTSTAT_DELTACTS_MASK (0x20U)
+#define USART_INTSTAT_DELTACTS_SHIFT (5U)
+#define USART_INTSTAT_DELTACTS(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTACTS_SHIFT)) & USART_INTSTAT_DELTACTS_MASK)
+#define USART_INTSTAT_TXDISINT_MASK (0x40U)
+#define USART_INTSTAT_TXDISINT_SHIFT (6U)
+#define USART_INTSTAT_TXDISINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_TXDISINT_SHIFT)) & USART_INTSTAT_TXDISINT_MASK)
+#define USART_INTSTAT_DELTARXBRK_MASK (0x800U)
+#define USART_INTSTAT_DELTARXBRK_SHIFT (11U)
+#define USART_INTSTAT_DELTARXBRK(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_DELTARXBRK_SHIFT)) & USART_INTSTAT_DELTARXBRK_MASK)
+#define USART_INTSTAT_START_MASK (0x1000U)
+#define USART_INTSTAT_START_SHIFT (12U)
+#define USART_INTSTAT_START(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_START_SHIFT)) & USART_INTSTAT_START_MASK)
+#define USART_INTSTAT_FRAMERRINT_MASK (0x2000U)
+#define USART_INTSTAT_FRAMERRINT_SHIFT (13U)
+#define USART_INTSTAT_FRAMERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_FRAMERRINT_SHIFT)) & USART_INTSTAT_FRAMERRINT_MASK)
+#define USART_INTSTAT_PARITYERRINT_MASK (0x4000U)
+#define USART_INTSTAT_PARITYERRINT_SHIFT (14U)
+#define USART_INTSTAT_PARITYERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_PARITYERRINT_SHIFT)) & USART_INTSTAT_PARITYERRINT_MASK)
+#define USART_INTSTAT_RXNOISEINT_MASK (0x8000U)
+#define USART_INTSTAT_RXNOISEINT_SHIFT (15U)
+#define USART_INTSTAT_RXNOISEINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_RXNOISEINT_SHIFT)) & USART_INTSTAT_RXNOISEINT_MASK)
+#define USART_INTSTAT_ABERRINT_MASK (0x10000U)
+#define USART_INTSTAT_ABERRINT_SHIFT (16U)
+#define USART_INTSTAT_ABERRINT(x) (((uint32_t)(((uint32_t)(x)) << USART_INTSTAT_ABERRINT_SHIFT)) & USART_INTSTAT_ABERRINT_MASK)
+
+/*! @name OSR - Oversample selection register for asynchronous communication. */
+#define USART_OSR_OSRVAL_MASK (0xFU)
+#define USART_OSR_OSRVAL_SHIFT (0U)
+#define USART_OSR_OSRVAL(x) (((uint32_t)(((uint32_t)(x)) << USART_OSR_OSRVAL_SHIFT)) & USART_OSR_OSRVAL_MASK)
+
+/*! @name ADDR - Address register for automatic address matching. */
+#define USART_ADDR_ADDRESS_MASK (0xFFU)
+#define USART_ADDR_ADDRESS_SHIFT (0U)
+#define USART_ADDR_ADDRESS(x) (((uint32_t)(((uint32_t)(x)) << USART_ADDR_ADDRESS_SHIFT)) & USART_ADDR_ADDRESS_MASK)
+
+/*! @name FIFOCFG - FIFO configuration and enable register. */
+#define USART_FIFOCFG_ENABLETX_MASK (0x1U)
+#define USART_FIFOCFG_ENABLETX_SHIFT (0U)
+#define USART_FIFOCFG_ENABLETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLETX_SHIFT)) & USART_FIFOCFG_ENABLETX_MASK)
+#define USART_FIFOCFG_ENABLERX_MASK (0x2U)
+#define USART_FIFOCFG_ENABLERX_SHIFT (1U)
+#define USART_FIFOCFG_ENABLERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_ENABLERX_SHIFT)) & USART_FIFOCFG_ENABLERX_MASK)
+#define USART_FIFOCFG_SIZE_MASK (0x30U)
+#define USART_FIFOCFG_SIZE_SHIFT (4U)
+#define USART_FIFOCFG_SIZE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_SIZE_SHIFT)) & USART_FIFOCFG_SIZE_MASK)
+#define USART_FIFOCFG_DMATX_MASK (0x1000U)
+#define USART_FIFOCFG_DMATX_SHIFT (12U)
+#define USART_FIFOCFG_DMATX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMATX_SHIFT)) & USART_FIFOCFG_DMATX_MASK)
+#define USART_FIFOCFG_DMARX_MASK (0x2000U)
+#define USART_FIFOCFG_DMARX_SHIFT (13U)
+#define USART_FIFOCFG_DMARX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_DMARX_SHIFT)) & USART_FIFOCFG_DMARX_MASK)
+#define USART_FIFOCFG_WAKETX_MASK (0x4000U)
+#define USART_FIFOCFG_WAKETX_SHIFT (14U)
+#define USART_FIFOCFG_WAKETX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKETX_SHIFT)) & USART_FIFOCFG_WAKETX_MASK)
+#define USART_FIFOCFG_WAKERX_MASK (0x8000U)
+#define USART_FIFOCFG_WAKERX_SHIFT (15U)
+#define USART_FIFOCFG_WAKERX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_WAKERX_SHIFT)) & USART_FIFOCFG_WAKERX_MASK)
+#define USART_FIFOCFG_EMPTYTX_MASK (0x10000U)
+#define USART_FIFOCFG_EMPTYTX_SHIFT (16U)
+#define USART_FIFOCFG_EMPTYTX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYTX_SHIFT)) & USART_FIFOCFG_EMPTYTX_MASK)
+#define USART_FIFOCFG_EMPTYRX_MASK (0x20000U)
+#define USART_FIFOCFG_EMPTYRX_SHIFT (17U)
+#define USART_FIFOCFG_EMPTYRX(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_EMPTYRX_SHIFT)) & USART_FIFOCFG_EMPTYRX_MASK)
+#define USART_FIFOCFG_POPDBG_MASK (0x40000U)
+#define USART_FIFOCFG_POPDBG_SHIFT (18U)
+#define USART_FIFOCFG_POPDBG(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOCFG_POPDBG_SHIFT)) & USART_FIFOCFG_POPDBG_MASK)
+
+/*! @name FIFOSTAT - FIFO status register. */
+#define USART_FIFOSTAT_TXERR_MASK (0x1U)
+#define USART_FIFOSTAT_TXERR_SHIFT (0U)
+#define USART_FIFOSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXERR_SHIFT)) & USART_FIFOSTAT_TXERR_MASK)
+#define USART_FIFOSTAT_RXERR_MASK (0x2U)
+#define USART_FIFOSTAT_RXERR_SHIFT (1U)
+#define USART_FIFOSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXERR_SHIFT)) & USART_FIFOSTAT_RXERR_MASK)
+#define USART_FIFOSTAT_PERINT_MASK (0x8U)
+#define USART_FIFOSTAT_PERINT_SHIFT (3U)
+#define USART_FIFOSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_PERINT_SHIFT)) & USART_FIFOSTAT_PERINT_MASK)
+#define USART_FIFOSTAT_TXEMPTY_MASK (0x10U)
+#define USART_FIFOSTAT_TXEMPTY_SHIFT (4U)
+#define USART_FIFOSTAT_TXEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXEMPTY_SHIFT)) & USART_FIFOSTAT_TXEMPTY_MASK)
+#define USART_FIFOSTAT_TXNOTFULL_MASK (0x20U)
+#define USART_FIFOSTAT_TXNOTFULL_SHIFT (5U)
+#define USART_FIFOSTAT_TXNOTFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXNOTFULL_SHIFT)) & USART_FIFOSTAT_TXNOTFULL_MASK)
+#define USART_FIFOSTAT_RXNOTEMPTY_MASK (0x40U)
+#define USART_FIFOSTAT_RXNOTEMPTY_SHIFT (6U)
+#define USART_FIFOSTAT_RXNOTEMPTY(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXNOTEMPTY_SHIFT)) & USART_FIFOSTAT_RXNOTEMPTY_MASK)
+#define USART_FIFOSTAT_RXFULL_MASK (0x80U)
+#define USART_FIFOSTAT_RXFULL_SHIFT (7U)
+#define USART_FIFOSTAT_RXFULL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXFULL_SHIFT)) & USART_FIFOSTAT_RXFULL_MASK)
+#define USART_FIFOSTAT_TXLVL_MASK (0x1F00U)
+#define USART_FIFOSTAT_TXLVL_SHIFT (8U)
+#define USART_FIFOSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_TXLVL_SHIFT)) & USART_FIFOSTAT_TXLVL_MASK)
+#define USART_FIFOSTAT_RXLVL_MASK (0x1F0000U)
+#define USART_FIFOSTAT_RXLVL_SHIFT (16U)
+#define USART_FIFOSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOSTAT_RXLVL_SHIFT)) & USART_FIFOSTAT_RXLVL_MASK)
+
+/*! @name FIFOTRIG - FIFO trigger settings for interrupt and DMA request. */
+#define USART_FIFOTRIG_TXLVLENA_MASK (0x1U)
+#define USART_FIFOTRIG_TXLVLENA_SHIFT (0U)
+#define USART_FIFOTRIG_TXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVLENA_SHIFT)) & USART_FIFOTRIG_TXLVLENA_MASK)
+#define USART_FIFOTRIG_RXLVLENA_MASK (0x2U)
+#define USART_FIFOTRIG_RXLVLENA_SHIFT (1U)
+#define USART_FIFOTRIG_RXLVLENA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVLENA_SHIFT)) & USART_FIFOTRIG_RXLVLENA_MASK)
+#define USART_FIFOTRIG_TXLVL_MASK (0xF00U)
+#define USART_FIFOTRIG_TXLVL_SHIFT (8U)
+#define USART_FIFOTRIG_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_TXLVL_SHIFT)) & USART_FIFOTRIG_TXLVL_MASK)
+#define USART_FIFOTRIG_RXLVL_MASK (0xF0000U)
+#define USART_FIFOTRIG_RXLVL_SHIFT (16U)
+#define USART_FIFOTRIG_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOTRIG_RXLVL_SHIFT)) & USART_FIFOTRIG_RXLVL_MASK)
+
+/*! @name FIFOINTENSET - FIFO interrupt enable set (enable) and read register. */
+#define USART_FIFOINTENSET_TXERR_MASK (0x1U)
+#define USART_FIFOINTENSET_TXERR_SHIFT (0U)
+#define USART_FIFOINTENSET_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXERR_SHIFT)) & USART_FIFOINTENSET_TXERR_MASK)
+#define USART_FIFOINTENSET_RXERR_MASK (0x2U)
+#define USART_FIFOINTENSET_RXERR_SHIFT (1U)
+#define USART_FIFOINTENSET_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXERR_SHIFT)) & USART_FIFOINTENSET_RXERR_MASK)
+#define USART_FIFOINTENSET_TXLVL_MASK (0x4U)
+#define USART_FIFOINTENSET_TXLVL_SHIFT (2U)
+#define USART_FIFOINTENSET_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_TXLVL_SHIFT)) & USART_FIFOINTENSET_TXLVL_MASK)
+#define USART_FIFOINTENSET_RXLVL_MASK (0x8U)
+#define USART_FIFOINTENSET_RXLVL_SHIFT (3U)
+#define USART_FIFOINTENSET_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENSET_RXLVL_SHIFT)) & USART_FIFOINTENSET_RXLVL_MASK)
+
+/*! @name FIFOINTENCLR - FIFO interrupt enable clear (disable) and read register. */
+#define USART_FIFOINTENCLR_TXERR_MASK (0x1U)
+#define USART_FIFOINTENCLR_TXERR_SHIFT (0U)
+#define USART_FIFOINTENCLR_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXERR_SHIFT)) & USART_FIFOINTENCLR_TXERR_MASK)
+#define USART_FIFOINTENCLR_RXERR_MASK (0x2U)
+#define USART_FIFOINTENCLR_RXERR_SHIFT (1U)
+#define USART_FIFOINTENCLR_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXERR_SHIFT)) & USART_FIFOINTENCLR_RXERR_MASK)
+#define USART_FIFOINTENCLR_TXLVL_MASK (0x4U)
+#define USART_FIFOINTENCLR_TXLVL_SHIFT (2U)
+#define USART_FIFOINTENCLR_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_TXLVL_SHIFT)) & USART_FIFOINTENCLR_TXLVL_MASK)
+#define USART_FIFOINTENCLR_RXLVL_MASK (0x8U)
+#define USART_FIFOINTENCLR_RXLVL_SHIFT (3U)
+#define USART_FIFOINTENCLR_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTENCLR_RXLVL_SHIFT)) & USART_FIFOINTENCLR_RXLVL_MASK)
+
+/*! @name FIFOINTSTAT - FIFO interrupt status register. */
+#define USART_FIFOINTSTAT_TXERR_MASK (0x1U)
+#define USART_FIFOINTSTAT_TXERR_SHIFT (0U)
+#define USART_FIFOINTSTAT_TXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXERR_SHIFT)) & USART_FIFOINTSTAT_TXERR_MASK)
+#define USART_FIFOINTSTAT_RXERR_MASK (0x2U)
+#define USART_FIFOINTSTAT_RXERR_SHIFT (1U)
+#define USART_FIFOINTSTAT_RXERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXERR_SHIFT)) & USART_FIFOINTSTAT_RXERR_MASK)
+#define USART_FIFOINTSTAT_TXLVL_MASK (0x4U)
+#define USART_FIFOINTSTAT_TXLVL_SHIFT (2U)
+#define USART_FIFOINTSTAT_TXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_TXLVL_SHIFT)) & USART_FIFOINTSTAT_TXLVL_MASK)
+#define USART_FIFOINTSTAT_RXLVL_MASK (0x8U)
+#define USART_FIFOINTSTAT_RXLVL_SHIFT (3U)
+#define USART_FIFOINTSTAT_RXLVL(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_RXLVL_SHIFT)) & USART_FIFOINTSTAT_RXLVL_MASK)
+#define USART_FIFOINTSTAT_PERINT_MASK (0x10U)
+#define USART_FIFOINTSTAT_PERINT_SHIFT (4U)
+#define USART_FIFOINTSTAT_PERINT(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOINTSTAT_PERINT_SHIFT)) & USART_FIFOINTSTAT_PERINT_MASK)
+
+/*! @name FIFOWR - FIFO write data. */
+#define USART_FIFOWR_TXDATA_MASK (0x1FFU)
+#define USART_FIFOWR_TXDATA_SHIFT (0U)
+#define USART_FIFOWR_TXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFOWR_TXDATA_SHIFT)) & USART_FIFOWR_TXDATA_MASK)
+
+/*! @name FIFORD - FIFO read data. */
+#define USART_FIFORD_RXDATA_MASK (0x1FFU)
+#define USART_FIFORD_RXDATA_SHIFT (0U)
+#define USART_FIFORD_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXDATA_SHIFT)) & USART_FIFORD_RXDATA_MASK)
+#define USART_FIFORD_FRAMERR_MASK (0x2000U)
+#define USART_FIFORD_FRAMERR_SHIFT (13U)
+#define USART_FIFORD_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_FRAMERR_SHIFT)) & USART_FIFORD_FRAMERR_MASK)
+#define USART_FIFORD_PARITYERR_MASK (0x4000U)
+#define USART_FIFORD_PARITYERR_SHIFT (14U)
+#define USART_FIFORD_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_PARITYERR_SHIFT)) & USART_FIFORD_PARITYERR_MASK)
+#define USART_FIFORD_RXNOISE_MASK (0x8000U)
+#define USART_FIFORD_RXNOISE_SHIFT (15U)
+#define USART_FIFORD_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORD_RXNOISE_SHIFT)) & USART_FIFORD_RXNOISE_MASK)
+
+/*! @name FIFORDNOPOP - FIFO data read with no FIFO pop. */
+#define USART_FIFORDNOPOP_RXDATA_MASK (0x1FFU)
+#define USART_FIFORDNOPOP_RXDATA_SHIFT (0U)
+#define USART_FIFORDNOPOP_RXDATA(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXDATA_SHIFT)) & USART_FIFORDNOPOP_RXDATA_MASK)
+#define USART_FIFORDNOPOP_FRAMERR_MASK (0x2000U)
+#define USART_FIFORDNOPOP_FRAMERR_SHIFT (13U)
+#define USART_FIFORDNOPOP_FRAMERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_FRAMERR_SHIFT)) & USART_FIFORDNOPOP_FRAMERR_MASK)
+#define USART_FIFORDNOPOP_PARITYERR_MASK (0x4000U)
+#define USART_FIFORDNOPOP_PARITYERR_SHIFT (14U)
+#define USART_FIFORDNOPOP_PARITYERR(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_PARITYERR_SHIFT)) & USART_FIFORDNOPOP_PARITYERR_MASK)
+#define USART_FIFORDNOPOP_RXNOISE_MASK (0x8000U)
+#define USART_FIFORDNOPOP_RXNOISE_SHIFT (15U)
+#define USART_FIFORDNOPOP_RXNOISE(x) (((uint32_t)(((uint32_t)(x)) << USART_FIFORDNOPOP_RXNOISE_SHIFT)) & USART_FIFORDNOPOP_RXNOISE_MASK)
+
+/*! @name ID - Peripheral identification register. */
+#define USART_ID_APERTURE_MASK (0xFFU)
+#define USART_ID_APERTURE_SHIFT (0U)
+#define USART_ID_APERTURE(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_APERTURE_SHIFT)) & USART_ID_APERTURE_MASK)
+#define USART_ID_MINOR_REV_MASK (0xF00U)
+#define USART_ID_MINOR_REV_SHIFT (8U)
+#define USART_ID_MINOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MINOR_REV_SHIFT)) & USART_ID_MINOR_REV_MASK)
+#define USART_ID_MAJOR_REV_MASK (0xF000U)
+#define USART_ID_MAJOR_REV_SHIFT (12U)
+#define USART_ID_MAJOR_REV(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_MAJOR_REV_SHIFT)) & USART_ID_MAJOR_REV_MASK)
+#define USART_ID_ID_MASK (0xFFFF0000U)
+#define USART_ID_ID_SHIFT (16U)
+#define USART_ID_ID(x) (((uint32_t)(((uint32_t)(x)) << USART_ID_ID_SHIFT)) & USART_ID_ID_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group USART_Register_Masks */
+
+
+/* USART - Peripheral instance base addresses */
+/** Peripheral USART0 base address */
+#define USART0_BASE (0x40086000u)
+/** Peripheral USART0 base pointer */
+#define USART0 ((USART_Type *)USART0_BASE)
+/** Peripheral USART1 base address */
+#define USART1_BASE (0x40087000u)
+/** Peripheral USART1 base pointer */
+#define USART1 ((USART_Type *)USART1_BASE)
+/** Peripheral USART2 base address */
+#define USART2_BASE (0x40088000u)
+/** Peripheral USART2 base pointer */
+#define USART2 ((USART_Type *)USART2_BASE)
+/** Peripheral USART3 base address */
+#define USART3_BASE (0x40089000u)
+/** Peripheral USART3 base pointer */
+#define USART3 ((USART_Type *)USART3_BASE)
+/** Peripheral USART4 base address */
+#define USART4_BASE (0x4008A000u)
+/** Peripheral USART4 base pointer */
+#define USART4 ((USART_Type *)USART4_BASE)
+/** Peripheral USART5 base address */
+#define USART5_BASE (0x40096000u)
+/** Peripheral USART5 base pointer */
+#define USART5 ((USART_Type *)USART5_BASE)
+/** Peripheral USART6 base address */
+#define USART6_BASE (0x40097000u)
+/** Peripheral USART6 base pointer */
+#define USART6 ((USART_Type *)USART6_BASE)
+/** Peripheral USART7 base address */
+#define USART7_BASE (0x40098000u)
+/** Peripheral USART7 base pointer */
+#define USART7 ((USART_Type *)USART7_BASE)
+/** Peripheral USART8 base address */
+#define USART8_BASE (0x40099000u)
+/** Peripheral USART8 base pointer */
+#define USART8 ((USART_Type *)USART8_BASE)
+/** Peripheral USART9 base address */
+#define USART9_BASE (0x4009A000u)
+/** Peripheral USART9 base pointer */
+#define USART9 ((USART_Type *)USART9_BASE)
+/** Array initializer of USART peripheral base addresses */
+#define USART_BASE_ADDRS { USART0_BASE, USART1_BASE, USART2_BASE, USART3_BASE, USART4_BASE, USART5_BASE, USART6_BASE, USART7_BASE, USART8_BASE, USART9_BASE }
+/** Array initializer of USART peripheral base pointers */
+#define USART_BASE_PTRS { USART0, USART1, USART2, USART3, USART4, USART5, USART6, USART7, USART8, USART9 }
+/** Interrupt vectors for the USART peripheral type */
+#define USART_IRQS { FLEXCOMM0_IRQn, FLEXCOMM1_IRQn, FLEXCOMM2_IRQn, FLEXCOMM3_IRQn, FLEXCOMM4_IRQn, FLEXCOMM5_IRQn, FLEXCOMM6_IRQn, FLEXCOMM7_IRQn, FLEXCOMM8_IRQn, FLEXCOMM9_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USART_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- USB Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Peripheral_Access_Layer USB Peripheral Access Layer
+ * @{
+ */
+
+/** USB - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */
+ __IO uint32_t INFO; /**< USB Info register, offset: 0x4 */
+ __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */
+ __IO uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */
+ __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */
+ __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */
+ __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */
+ __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */
+ __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */
+ __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */
+ __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */
+ uint8_t RESERVED_0[8];
+ __IO uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */
+} USB_Type;
+
+/* ----------------------------------------------------------------------------
+ -- USB Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USB_Register_Masks USB Register Masks
+ * @{
+ */
+
+/*! @name DEVCMDSTAT - USB Device Command/Status register */
+#define USB_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU)
+#define USB_DEVCMDSTAT_DEV_ADDR_SHIFT (0U)
+#define USB_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USB_DEVCMDSTAT_DEV_ADDR_MASK)
+#define USB_DEVCMDSTAT_DEV_EN_MASK (0x80U)
+#define USB_DEVCMDSTAT_DEV_EN_SHIFT (7U)
+#define USB_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DEV_EN_SHIFT)) & USB_DEVCMDSTAT_DEV_EN_MASK)
+#define USB_DEVCMDSTAT_SETUP_MASK (0x100U)
+#define USB_DEVCMDSTAT_SETUP_SHIFT (8U)
+#define USB_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_SETUP_SHIFT)) & USB_DEVCMDSTAT_SETUP_MASK)
+#define USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U)
+#define USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U)
+#define USB_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USB_DEVCMDSTAT_FORCE_NEEDCLK_MASK)
+#define USB_DEVCMDSTAT_LPM_SUP_MASK (0x800U)
+#define USB_DEVCMDSTAT_LPM_SUP_SHIFT (11U)
+#define USB_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUP_SHIFT)) & USB_DEVCMDSTAT_LPM_SUP_MASK)
+#define USB_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U)
+#define USB_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U)
+#define USB_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AO_MASK)
+#define USB_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U)
+#define USB_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U)
+#define USB_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_AI_MASK)
+#define USB_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U)
+#define USB_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U)
+#define USB_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CO_MASK)
+#define USB_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U)
+#define USB_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U)
+#define USB_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USB_DEVCMDSTAT_INTONNAK_CI_MASK)
+#define USB_DEVCMDSTAT_DCON_MASK (0x10000U)
+#define USB_DEVCMDSTAT_DCON_SHIFT (16U)
+#define USB_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_SHIFT)) & USB_DEVCMDSTAT_DCON_MASK)
+#define USB_DEVCMDSTAT_DSUS_MASK (0x20000U)
+#define USB_DEVCMDSTAT_DSUS_SHIFT (17U)
+#define USB_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_SHIFT)) & USB_DEVCMDSTAT_DSUS_MASK)
+#define USB_DEVCMDSTAT_LPM_SUS_MASK (0x80000U)
+#define USB_DEVCMDSTAT_LPM_SUS_SHIFT (19U)
+#define USB_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_SUS_SHIFT)) & USB_DEVCMDSTAT_LPM_SUS_MASK)
+#define USB_DEVCMDSTAT_LPM_REWP_MASK (0x100000U)
+#define USB_DEVCMDSTAT_LPM_REWP_SHIFT (20U)
+#define USB_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_LPM_REWP_SHIFT)) & USB_DEVCMDSTAT_LPM_REWP_MASK)
+#define USB_DEVCMDSTAT_DCON_C_MASK (0x1000000U)
+#define USB_DEVCMDSTAT_DCON_C_SHIFT (24U)
+#define USB_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DCON_C_SHIFT)) & USB_DEVCMDSTAT_DCON_C_MASK)
+#define USB_DEVCMDSTAT_DSUS_C_MASK (0x2000000U)
+#define USB_DEVCMDSTAT_DSUS_C_SHIFT (25U)
+#define USB_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DSUS_C_SHIFT)) & USB_DEVCMDSTAT_DSUS_C_MASK)
+#define USB_DEVCMDSTAT_DRES_C_MASK (0x4000000U)
+#define USB_DEVCMDSTAT_DRES_C_SHIFT (26U)
+#define USB_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_DRES_C_SHIFT)) & USB_DEVCMDSTAT_DRES_C_MASK)
+#define USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK (0x10000000U)
+#define USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT (28U)
+#define USB_DEVCMDSTAT_VBUSDEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USB_DEVCMDSTAT_VBUSDEBOUNCED_SHIFT)) & USB_DEVCMDSTAT_VBUSDEBOUNCED_MASK)
+
+/*! @name INFO - USB Info register */
+#define USB_INFO_FRAME_NR_MASK (0x7FFU)
+#define USB_INFO_FRAME_NR_SHIFT (0U)
+#define USB_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_FRAME_NR_SHIFT)) & USB_INFO_FRAME_NR_MASK)
+#define USB_INFO_ERR_CODE_MASK (0x7800U)
+#define USB_INFO_ERR_CODE_SHIFT (11U)
+#define USB_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_ERR_CODE_SHIFT)) & USB_INFO_ERR_CODE_MASK)
+#define USB_INFO_MINREV_MASK (0xFF0000U)
+#define USB_INFO_MINREV_SHIFT (16U)
+#define USB_INFO_MINREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MINREV_SHIFT)) & USB_INFO_MINREV_MASK)
+#define USB_INFO_MAJREV_MASK (0xFF000000U)
+#define USB_INFO_MAJREV_SHIFT (24U)
+#define USB_INFO_MAJREV(x) (((uint32_t)(((uint32_t)(x)) << USB_INFO_MAJREV_SHIFT)) & USB_INFO_MAJREV_MASK)
+
+/*! @name EPLISTSTART - USB EP Command/Status List start address */
+#define USB_EPLISTSTART_EP_LIST_MASK (0xFFFFFF00U)
+#define USB_EPLISTSTART_EP_LIST_SHIFT (8U)
+#define USB_EPLISTSTART_EP_LIST(x) (((uint32_t)(((uint32_t)(x)) << USB_EPLISTSTART_EP_LIST_SHIFT)) & USB_EPLISTSTART_EP_LIST_MASK)
+
+/*! @name DATABUFSTART - USB Data buffer start address */
+#define USB_DATABUFSTART_DA_BUF_MASK (0xFFC00000U)
+#define USB_DATABUFSTART_DA_BUF_SHIFT (22U)
+#define USB_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_DATABUFSTART_DA_BUF_SHIFT)) & USB_DATABUFSTART_DA_BUF_MASK)
+
+/*! @name LPM - USB Link Power Management register */
+#define USB_LPM_HIRD_HW_MASK (0xFU)
+#define USB_LPM_HIRD_HW_SHIFT (0U)
+#define USB_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_HW_SHIFT)) & USB_LPM_HIRD_HW_MASK)
+#define USB_LPM_HIRD_SW_MASK (0xF0U)
+#define USB_LPM_HIRD_SW_SHIFT (4U)
+#define USB_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_HIRD_SW_SHIFT)) & USB_LPM_HIRD_SW_MASK)
+#define USB_LPM_DATA_PENDING_MASK (0x100U)
+#define USB_LPM_DATA_PENDING_SHIFT (8U)
+#define USB_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USB_LPM_DATA_PENDING_SHIFT)) & USB_LPM_DATA_PENDING_MASK)
+
+/*! @name EPSKIP - USB Endpoint skip */
+#define USB_EPSKIP_SKIP_MASK (0x3FFU)
+#define USB_EPSKIP_SKIP_SHIFT (0U)
+#define USB_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USB_EPSKIP_SKIP_SHIFT)) & USB_EPSKIP_SKIP_MASK)
+
+/*! @name EPINUSE - USB Endpoint Buffer in use */
+#define USB_EPINUSE_BUF_MASK (0x3FCU)
+#define USB_EPINUSE_BUF_SHIFT (2U)
+#define USB_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USB_EPINUSE_BUF_SHIFT)) & USB_EPINUSE_BUF_MASK)
+
+/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */
+#define USB_EPBUFCFG_BUF_SB_MASK (0x3FCU)
+#define USB_EPBUFCFG_BUF_SB_SHIFT (2U)
+#define USB_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USB_EPBUFCFG_BUF_SB_SHIFT)) & USB_EPBUFCFG_BUF_SB_MASK)
+
+/*! @name INTSTAT - USB interrupt status register */
+#define USB_INTSTAT_EP0OUT_MASK (0x1U)
+#define USB_INTSTAT_EP0OUT_SHIFT (0U)
+#define USB_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0OUT_SHIFT)) & USB_INTSTAT_EP0OUT_MASK)
+#define USB_INTSTAT_EP0IN_MASK (0x2U)
+#define USB_INTSTAT_EP0IN_SHIFT (1U)
+#define USB_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP0IN_SHIFT)) & USB_INTSTAT_EP0IN_MASK)
+#define USB_INTSTAT_EP1OUT_MASK (0x4U)
+#define USB_INTSTAT_EP1OUT_SHIFT (2U)
+#define USB_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1OUT_SHIFT)) & USB_INTSTAT_EP1OUT_MASK)
+#define USB_INTSTAT_EP1IN_MASK (0x8U)
+#define USB_INTSTAT_EP1IN_SHIFT (3U)
+#define USB_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP1IN_SHIFT)) & USB_INTSTAT_EP1IN_MASK)
+#define USB_INTSTAT_EP2OUT_MASK (0x10U)
+#define USB_INTSTAT_EP2OUT_SHIFT (4U)
+#define USB_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2OUT_SHIFT)) & USB_INTSTAT_EP2OUT_MASK)
+#define USB_INTSTAT_EP2IN_MASK (0x20U)
+#define USB_INTSTAT_EP2IN_SHIFT (5U)
+#define USB_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP2IN_SHIFT)) & USB_INTSTAT_EP2IN_MASK)
+#define USB_INTSTAT_EP3OUT_MASK (0x40U)
+#define USB_INTSTAT_EP3OUT_SHIFT (6U)
+#define USB_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3OUT_SHIFT)) & USB_INTSTAT_EP3OUT_MASK)
+#define USB_INTSTAT_EP3IN_MASK (0x80U)
+#define USB_INTSTAT_EP3IN_SHIFT (7U)
+#define USB_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP3IN_SHIFT)) & USB_INTSTAT_EP3IN_MASK)
+#define USB_INTSTAT_EP4OUT_MASK (0x100U)
+#define USB_INTSTAT_EP4OUT_SHIFT (8U)
+#define USB_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4OUT_SHIFT)) & USB_INTSTAT_EP4OUT_MASK)
+#define USB_INTSTAT_EP4IN_MASK (0x200U)
+#define USB_INTSTAT_EP4IN_SHIFT (9U)
+#define USB_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_EP4IN_SHIFT)) & USB_INTSTAT_EP4IN_MASK)
+#define USB_INTSTAT_FRAME_INT_MASK (0x40000000U)
+#define USB_INTSTAT_FRAME_INT_SHIFT (30U)
+#define USB_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_FRAME_INT_SHIFT)) & USB_INTSTAT_FRAME_INT_MASK)
+#define USB_INTSTAT_DEV_INT_MASK (0x80000000U)
+#define USB_INTSTAT_DEV_INT_SHIFT (31U)
+#define USB_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSTAT_DEV_INT_SHIFT)) & USB_INTSTAT_DEV_INT_MASK)
+
+/*! @name INTEN - USB interrupt enable register */
+#define USB_INTEN_EP_INT_EN_MASK (0x3FFU)
+#define USB_INTEN_EP_INT_EN_SHIFT (0U)
+#define USB_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_EP_INT_EN_SHIFT)) & USB_INTEN_EP_INT_EN_MASK)
+#define USB_INTEN_FRAME_INT_EN_MASK (0x40000000U)
+#define USB_INTEN_FRAME_INT_EN_SHIFT (30U)
+#define USB_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_FRAME_INT_EN_SHIFT)) & USB_INTEN_FRAME_INT_EN_MASK)
+#define USB_INTEN_DEV_INT_EN_MASK (0x80000000U)
+#define USB_INTEN_DEV_INT_EN_SHIFT (31U)
+#define USB_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USB_INTEN_DEV_INT_EN_SHIFT)) & USB_INTEN_DEV_INT_EN_MASK)
+
+/*! @name INTSETSTAT - USB set interrupt status register */
+#define USB_INTSETSTAT_EP_SET_INT_MASK (0x3FFU)
+#define USB_INTSETSTAT_EP_SET_INT_SHIFT (0U)
+#define USB_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_EP_SET_INT_SHIFT)) & USB_INTSETSTAT_EP_SET_INT_MASK)
+#define USB_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U)
+#define USB_INTSETSTAT_FRAME_SET_INT_SHIFT (30U)
+#define USB_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USB_INTSETSTAT_FRAME_SET_INT_MASK)
+#define USB_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U)
+#define USB_INTSETSTAT_DEV_SET_INT_SHIFT (31U)
+#define USB_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USB_INTSETSTAT_DEV_SET_INT_SHIFT)) & USB_INTSETSTAT_DEV_SET_INT_MASK)
+
+/*! @name EPTOGGLE - USB Endpoint toggle register */
+#define USB_EPTOGGLE_TOGGLE_MASK (0x3FFU)
+#define USB_EPTOGGLE_TOGGLE_SHIFT (0U)
+#define USB_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USB_EPTOGGLE_TOGGLE_SHIFT)) & USB_EPTOGGLE_TOGGLE_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group USB_Register_Masks */
+
+
+/* USB - Peripheral instance base addresses */
+/** Peripheral USB0 base address */
+#define USB0_BASE (0x40084000u)
+/** Peripheral USB0 base pointer */
+#define USB0 ((USB_Type *)USB0_BASE)
+/** Array initializer of USB peripheral base addresses */
+#define USB_BASE_ADDRS { USB0_BASE }
+/** Array initializer of USB peripheral base pointers */
+#define USB_BASE_PTRS { USB0 }
+/** Interrupt vectors for the USB peripheral type */
+#define USB_IRQS { USB0_IRQn }
+#define USB_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USB_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- USBFSH Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBFSH_Peripheral_Access_Layer USBFSH Peripheral Access Layer
+ * @{
+ */
+
+/** USBFSH - Register Layout Typedef */
+typedef struct {
+ __I uint32_t HCREVISION; /**< BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC), offset: 0x0 */
+ __IO uint32_t HCCONTROL; /**< Defines the operating modes of the HC, offset: 0x4 */
+ __IO uint32_t HCCOMMANDSTATUS; /**< This register is used to receive the commands from the Host Controller Driver (HCD), offset: 0x8 */
+ __IO uint32_t HCINTERRUPTSTATUS; /**< Indicates the status on various events that cause hardware interrupts by setting the appropriate bits, offset: 0xC */
+ __IO uint32_t HCINTERRUPTENABLE; /**< Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt, offset: 0x10 */
+ __IO uint32_t HCINTERRUPTDISABLE; /**< The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt, offset: 0x14 */
+ __IO uint32_t HCHCCA; /**< Contains the physical address of the host controller communication area, offset: 0x18 */
+ __IO uint32_t HCPERIODCURRENTED; /**< Contains the physical address of the current isochronous or interrupt endpoint descriptor, offset: 0x1C */
+ __IO uint32_t HCCONTROLHEADED; /**< Contains the physical address of the first endpoint descriptor of the control list, offset: 0x20 */
+ __IO uint32_t HCCONTROLCURRENTED; /**< Contains the physical address of the current endpoint descriptor of the control list, offset: 0x24 */
+ __IO uint32_t HCBULKHEADED; /**< Contains the physical address of the first endpoint descriptor of the bulk list, offset: 0x28 */
+ __IO uint32_t HCBULKCURRENTED; /**< Contains the physical address of the current endpoint descriptor of the bulk list, offset: 0x2C */
+ __IO uint32_t HCDONEHEAD; /**< Contains the physical address of the last transfer descriptor added to the 'Done' queue, offset: 0x30 */
+ __IO uint32_t HCFMINTERVAL; /**< Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun, offset: 0x34 */
+ __IO uint32_t HCFMREMAINING; /**< A 14-bit counter showing the bit time remaining in the current frame, offset: 0x38 */
+ __IO uint32_t HCFMNUMBER; /**< Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD, offset: 0x3C */
+ __IO uint32_t HCPERIODICSTART; /**< Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list, offset: 0x40 */
+ __IO uint32_t HCLSTHRESHOLD; /**< Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF, offset: 0x44 */
+ __IO uint32_t HCRHDESCRIPTORA; /**< First of the two registers which describes the characteristics of the root hub, offset: 0x48 */
+ __IO uint32_t HCRHDESCRIPTORB; /**< Second of the two registers which describes the characteristics of the Root Hub, offset: 0x4C */
+ __IO uint32_t HCRHSTATUS; /**< This register is divided into two parts, offset: 0x50 */
+ __IO uint32_t HCRHPORTSTATUS; /**< Controls and reports the port events on a per-port basis, offset: 0x54 */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t PORTMODE; /**< Controls the port if it is attached to the host block or the device block, offset: 0x5C */
+} USBFSH_Type;
+
+/* ----------------------------------------------------------------------------
+ -- USBFSH Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBFSH_Register_Masks USBFSH Register Masks
+ * @{
+ */
+
+/*! @name HCREVISION - BCD representation of the version of the HCI specification that is implemented by the Host Controller (HC) */
+#define USBFSH_HCREVISION_REV_MASK (0xFFU)
+#define USBFSH_HCREVISION_REV_SHIFT (0U)
+#define USBFSH_HCREVISION_REV(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCREVISION_REV_SHIFT)) & USBFSH_HCREVISION_REV_MASK)
+
+/*! @name HCCONTROL - Defines the operating modes of the HC */
+#define USBFSH_HCCONTROL_CBSR_MASK (0x3U)
+#define USBFSH_HCCONTROL_CBSR_SHIFT (0U)
+#define USBFSH_HCCONTROL_CBSR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CBSR_SHIFT)) & USBFSH_HCCONTROL_CBSR_MASK)
+#define USBFSH_HCCONTROL_PLE_MASK (0x4U)
+#define USBFSH_HCCONTROL_PLE_SHIFT (2U)
+#define USBFSH_HCCONTROL_PLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_PLE_SHIFT)) & USBFSH_HCCONTROL_PLE_MASK)
+#define USBFSH_HCCONTROL_IE_MASK (0x8U)
+#define USBFSH_HCCONTROL_IE_SHIFT (3U)
+#define USBFSH_HCCONTROL_IE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IE_SHIFT)) & USBFSH_HCCONTROL_IE_MASK)
+#define USBFSH_HCCONTROL_CLE_MASK (0x10U)
+#define USBFSH_HCCONTROL_CLE_SHIFT (4U)
+#define USBFSH_HCCONTROL_CLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_CLE_SHIFT)) & USBFSH_HCCONTROL_CLE_MASK)
+#define USBFSH_HCCONTROL_BLE_MASK (0x20U)
+#define USBFSH_HCCONTROL_BLE_SHIFT (5U)
+#define USBFSH_HCCONTROL_BLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_BLE_SHIFT)) & USBFSH_HCCONTROL_BLE_MASK)
+#define USBFSH_HCCONTROL_HCFS_MASK (0xC0U)
+#define USBFSH_HCCONTROL_HCFS_SHIFT (6U)
+#define USBFSH_HCCONTROL_HCFS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_HCFS_SHIFT)) & USBFSH_HCCONTROL_HCFS_MASK)
+#define USBFSH_HCCONTROL_IR_MASK (0x100U)
+#define USBFSH_HCCONTROL_IR_SHIFT (8U)
+#define USBFSH_HCCONTROL_IR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_IR_SHIFT)) & USBFSH_HCCONTROL_IR_MASK)
+#define USBFSH_HCCONTROL_RWC_MASK (0x200U)
+#define USBFSH_HCCONTROL_RWC_SHIFT (9U)
+#define USBFSH_HCCONTROL_RWC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWC_SHIFT)) & USBFSH_HCCONTROL_RWC_MASK)
+#define USBFSH_HCCONTROL_RWE_MASK (0x400U)
+#define USBFSH_HCCONTROL_RWE_SHIFT (10U)
+#define USBFSH_HCCONTROL_RWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROL_RWE_SHIFT)) & USBFSH_HCCONTROL_RWE_MASK)
+
+/*! @name HCCOMMANDSTATUS - This register is used to receive the commands from the Host Controller Driver (HCD) */
+#define USBFSH_HCCOMMANDSTATUS_HCR_MASK (0x1U)
+#define USBFSH_HCCOMMANDSTATUS_HCR_SHIFT (0U)
+#define USBFSH_HCCOMMANDSTATUS_HCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_HCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_HCR_MASK)
+#define USBFSH_HCCOMMANDSTATUS_CLF_MASK (0x2U)
+#define USBFSH_HCCOMMANDSTATUS_CLF_SHIFT (1U)
+#define USBFSH_HCCOMMANDSTATUS_CLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_CLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_CLF_MASK)
+#define USBFSH_HCCOMMANDSTATUS_BLF_MASK (0x4U)
+#define USBFSH_HCCOMMANDSTATUS_BLF_SHIFT (2U)
+#define USBFSH_HCCOMMANDSTATUS_BLF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_BLF_SHIFT)) & USBFSH_HCCOMMANDSTATUS_BLF_MASK)
+#define USBFSH_HCCOMMANDSTATUS_OCR_MASK (0x8U)
+#define USBFSH_HCCOMMANDSTATUS_OCR_SHIFT (3U)
+#define USBFSH_HCCOMMANDSTATUS_OCR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_OCR_SHIFT)) & USBFSH_HCCOMMANDSTATUS_OCR_MASK)
+#define USBFSH_HCCOMMANDSTATUS_SOC_MASK (0xC0U)
+#define USBFSH_HCCOMMANDSTATUS_SOC_SHIFT (6U)
+#define USBFSH_HCCOMMANDSTATUS_SOC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCOMMANDSTATUS_SOC_SHIFT)) & USBFSH_HCCOMMANDSTATUS_SOC_MASK)
+
+/*! @name HCINTERRUPTSTATUS - Indicates the status on various events that cause hardware interrupts by setting the appropriate bits */
+#define USBFSH_HCINTERRUPTSTATUS_SO_MASK (0x1U)
+#define USBFSH_HCINTERRUPTSTATUS_SO_SHIFT (0U)
+#define USBFSH_HCINTERRUPTSTATUS_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SO_MASK)
+#define USBFSH_HCINTERRUPTSTATUS_WDH_MASK (0x2U)
+#define USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT (1U)
+#define USBFSH_HCINTERRUPTSTATUS_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_WDH_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_WDH_MASK)
+#define USBFSH_HCINTERRUPTSTATUS_SF_MASK (0x4U)
+#define USBFSH_HCINTERRUPTSTATUS_SF_SHIFT (2U)
+#define USBFSH_HCINTERRUPTSTATUS_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_SF_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_SF_MASK)
+#define USBFSH_HCINTERRUPTSTATUS_RD_MASK (0x8U)
+#define USBFSH_HCINTERRUPTSTATUS_RD_SHIFT (3U)
+#define USBFSH_HCINTERRUPTSTATUS_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RD_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RD_MASK)
+#define USBFSH_HCINTERRUPTSTATUS_UE_MASK (0x10U)
+#define USBFSH_HCINTERRUPTSTATUS_UE_SHIFT (4U)
+#define USBFSH_HCINTERRUPTSTATUS_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_UE_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_UE_MASK)
+#define USBFSH_HCINTERRUPTSTATUS_FNO_MASK (0x20U)
+#define USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT (5U)
+#define USBFSH_HCINTERRUPTSTATUS_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_FNO_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_FNO_MASK)
+#define USBFSH_HCINTERRUPTSTATUS_RHSC_MASK (0x40U)
+#define USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT (6U)
+#define USBFSH_HCINTERRUPTSTATUS_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_RHSC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_RHSC_MASK)
+#define USBFSH_HCINTERRUPTSTATUS_OC_MASK (0xFFFFFC00U)
+#define USBFSH_HCINTERRUPTSTATUS_OC_SHIFT (10U)
+#define USBFSH_HCINTERRUPTSTATUS_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTSTATUS_OC_SHIFT)) & USBFSH_HCINTERRUPTSTATUS_OC_MASK)
+
+/*! @name HCINTERRUPTENABLE - Controls the bits in the HcInterruptStatus register and indicates which events will generate a hardware interrupt */
+#define USBFSH_HCINTERRUPTENABLE_SO_MASK (0x1U)
+#define USBFSH_HCINTERRUPTENABLE_SO_SHIFT (0U)
+#define USBFSH_HCINTERRUPTENABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SO_MASK)
+#define USBFSH_HCINTERRUPTENABLE_WDH_MASK (0x2U)
+#define USBFSH_HCINTERRUPTENABLE_WDH_SHIFT (1U)
+#define USBFSH_HCINTERRUPTENABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTENABLE_WDH_MASK)
+#define USBFSH_HCINTERRUPTENABLE_SF_MASK (0x4U)
+#define USBFSH_HCINTERRUPTENABLE_SF_SHIFT (2U)
+#define USBFSH_HCINTERRUPTENABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTENABLE_SF_MASK)
+#define USBFSH_HCINTERRUPTENABLE_RD_MASK (0x8U)
+#define USBFSH_HCINTERRUPTENABLE_RD_SHIFT (3U)
+#define USBFSH_HCINTERRUPTENABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RD_MASK)
+#define USBFSH_HCINTERRUPTENABLE_UE_MASK (0x10U)
+#define USBFSH_HCINTERRUPTENABLE_UE_SHIFT (4U)
+#define USBFSH_HCINTERRUPTENABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_UE_MASK)
+#define USBFSH_HCINTERRUPTENABLE_FNO_MASK (0x20U)
+#define USBFSH_HCINTERRUPTENABLE_FNO_SHIFT (5U)
+#define USBFSH_HCINTERRUPTENABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTENABLE_FNO_MASK)
+#define USBFSH_HCINTERRUPTENABLE_RHSC_MASK (0x40U)
+#define USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT (6U)
+#define USBFSH_HCINTERRUPTENABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_RHSC_MASK)
+#define USBFSH_HCINTERRUPTENABLE_OC_MASK (0x40000000U)
+#define USBFSH_HCINTERRUPTENABLE_OC_SHIFT (30U)
+#define USBFSH_HCINTERRUPTENABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTENABLE_OC_MASK)
+#define USBFSH_HCINTERRUPTENABLE_MIE_MASK (0x80000000U)
+#define USBFSH_HCINTERRUPTENABLE_MIE_SHIFT (31U)
+#define USBFSH_HCINTERRUPTENABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTENABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTENABLE_MIE_MASK)
+
+/*! @name HCINTERRUPTDISABLE - The bits in this register are used to disable corresponding bits in the HCInterruptStatus register and in turn disable that event leading to hardware interrupt */
+#define USBFSH_HCINTERRUPTDISABLE_SO_MASK (0x1U)
+#define USBFSH_HCINTERRUPTDISABLE_SO_SHIFT (0U)
+#define USBFSH_HCINTERRUPTDISABLE_SO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SO_MASK)
+#define USBFSH_HCINTERRUPTDISABLE_WDH_MASK (0x2U)
+#define USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT (1U)
+#define USBFSH_HCINTERRUPTDISABLE_WDH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_WDH_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_WDH_MASK)
+#define USBFSH_HCINTERRUPTDISABLE_SF_MASK (0x4U)
+#define USBFSH_HCINTERRUPTDISABLE_SF_SHIFT (2U)
+#define USBFSH_HCINTERRUPTDISABLE_SF(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_SF_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_SF_MASK)
+#define USBFSH_HCINTERRUPTDISABLE_RD_MASK (0x8U)
+#define USBFSH_HCINTERRUPTDISABLE_RD_SHIFT (3U)
+#define USBFSH_HCINTERRUPTDISABLE_RD(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RD_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RD_MASK)
+#define USBFSH_HCINTERRUPTDISABLE_UE_MASK (0x10U)
+#define USBFSH_HCINTERRUPTDISABLE_UE_SHIFT (4U)
+#define USBFSH_HCINTERRUPTDISABLE_UE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_UE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_UE_MASK)
+#define USBFSH_HCINTERRUPTDISABLE_FNO_MASK (0x20U)
+#define USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT (5U)
+#define USBFSH_HCINTERRUPTDISABLE_FNO(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_FNO_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_FNO_MASK)
+#define USBFSH_HCINTERRUPTDISABLE_RHSC_MASK (0x40U)
+#define USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT (6U)
+#define USBFSH_HCINTERRUPTDISABLE_RHSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_RHSC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_RHSC_MASK)
+#define USBFSH_HCINTERRUPTDISABLE_OC_MASK (0x40000000U)
+#define USBFSH_HCINTERRUPTDISABLE_OC_SHIFT (30U)
+#define USBFSH_HCINTERRUPTDISABLE_OC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_OC_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_OC_MASK)
+#define USBFSH_HCINTERRUPTDISABLE_MIE_MASK (0x80000000U)
+#define USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT (31U)
+#define USBFSH_HCINTERRUPTDISABLE_MIE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCINTERRUPTDISABLE_MIE_SHIFT)) & USBFSH_HCINTERRUPTDISABLE_MIE_MASK)
+
+/*! @name HCHCCA - Contains the physical address of the host controller communication area */
+#define USBFSH_HCHCCA_HCCA_MASK (0xFFFFFF00U)
+#define USBFSH_HCHCCA_HCCA_SHIFT (8U)
+#define USBFSH_HCHCCA_HCCA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCHCCA_HCCA_SHIFT)) & USBFSH_HCHCCA_HCCA_MASK)
+
+/*! @name HCPERIODCURRENTED - Contains the physical address of the current isochronous or interrupt endpoint descriptor */
+#define USBFSH_HCPERIODCURRENTED_PCED_MASK (0xFFFFFFF0U)
+#define USBFSH_HCPERIODCURRENTED_PCED_SHIFT (4U)
+#define USBFSH_HCPERIODCURRENTED_PCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODCURRENTED_PCED_SHIFT)) & USBFSH_HCPERIODCURRENTED_PCED_MASK)
+
+/*! @name HCCONTROLHEADED - Contains the physical address of the first endpoint descriptor of the control list */
+#define USBFSH_HCCONTROLHEADED_CHED_MASK (0xFFFFFFF0U)
+#define USBFSH_HCCONTROLHEADED_CHED_SHIFT (4U)
+#define USBFSH_HCCONTROLHEADED_CHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLHEADED_CHED_SHIFT)) & USBFSH_HCCONTROLHEADED_CHED_MASK)
+
+/*! @name HCCONTROLCURRENTED - Contains the physical address of the current endpoint descriptor of the control list */
+#define USBFSH_HCCONTROLCURRENTED_CCED_MASK (0xFFFFFFF0U)
+#define USBFSH_HCCONTROLCURRENTED_CCED_SHIFT (4U)
+#define USBFSH_HCCONTROLCURRENTED_CCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCCONTROLCURRENTED_CCED_SHIFT)) & USBFSH_HCCONTROLCURRENTED_CCED_MASK)
+
+/*! @name HCBULKHEADED - Contains the physical address of the first endpoint descriptor of the bulk list */
+#define USBFSH_HCBULKHEADED_BHED_MASK (0xFFFFFFF0U)
+#define USBFSH_HCBULKHEADED_BHED_SHIFT (4U)
+#define USBFSH_HCBULKHEADED_BHED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKHEADED_BHED_SHIFT)) & USBFSH_HCBULKHEADED_BHED_MASK)
+
+/*! @name HCBULKCURRENTED - Contains the physical address of the current endpoint descriptor of the bulk list */
+#define USBFSH_HCBULKCURRENTED_BCED_MASK (0xFFFFFFF0U)
+#define USBFSH_HCBULKCURRENTED_BCED_SHIFT (4U)
+#define USBFSH_HCBULKCURRENTED_BCED(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCBULKCURRENTED_BCED_SHIFT)) & USBFSH_HCBULKCURRENTED_BCED_MASK)
+
+/*! @name HCDONEHEAD - Contains the physical address of the last transfer descriptor added to the 'Done' queue */
+#define USBFSH_HCDONEHEAD_DH_MASK (0xFFFFFFF0U)
+#define USBFSH_HCDONEHEAD_DH_SHIFT (4U)
+#define USBFSH_HCDONEHEAD_DH(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCDONEHEAD_DH_SHIFT)) & USBFSH_HCDONEHEAD_DH_MASK)
+
+/*! @name HCFMINTERVAL - Defines the bit time interval in a frame and the full speed maximum packet size which would not cause an overrun */
+#define USBFSH_HCFMINTERVAL_FI_MASK (0x3FFFU)
+#define USBFSH_HCFMINTERVAL_FI_SHIFT (0U)
+#define USBFSH_HCFMINTERVAL_FI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FI_SHIFT)) & USBFSH_HCFMINTERVAL_FI_MASK)
+#define USBFSH_HCFMINTERVAL_FSMPS_MASK (0x7FFF0000U)
+#define USBFSH_HCFMINTERVAL_FSMPS_SHIFT (16U)
+#define USBFSH_HCFMINTERVAL_FSMPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FSMPS_SHIFT)) & USBFSH_HCFMINTERVAL_FSMPS_MASK)
+#define USBFSH_HCFMINTERVAL_FIT_MASK (0x80000000U)
+#define USBFSH_HCFMINTERVAL_FIT_SHIFT (31U)
+#define USBFSH_HCFMINTERVAL_FIT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMINTERVAL_FIT_SHIFT)) & USBFSH_HCFMINTERVAL_FIT_MASK)
+
+/*! @name HCFMREMAINING - A 14-bit counter showing the bit time remaining in the current frame */
+#define USBFSH_HCFMREMAINING_FR_MASK (0x3FFFU)
+#define USBFSH_HCFMREMAINING_FR_SHIFT (0U)
+#define USBFSH_HCFMREMAINING_FR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FR_SHIFT)) & USBFSH_HCFMREMAINING_FR_MASK)
+#define USBFSH_HCFMREMAINING_FRT_MASK (0x80000000U)
+#define USBFSH_HCFMREMAINING_FRT_SHIFT (31U)
+#define USBFSH_HCFMREMAINING_FRT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMREMAINING_FRT_SHIFT)) & USBFSH_HCFMREMAINING_FRT_MASK)
+
+/*! @name HCFMNUMBER - Contains a 16-bit counter and provides the timing reference among events happening in the HC and the HCD */
+#define USBFSH_HCFMNUMBER_FN_MASK (0xFFFFU)
+#define USBFSH_HCFMNUMBER_FN_SHIFT (0U)
+#define USBFSH_HCFMNUMBER_FN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCFMNUMBER_FN_SHIFT)) & USBFSH_HCFMNUMBER_FN_MASK)
+
+/*! @name HCPERIODICSTART - Contains a programmable 14-bit value which determines the earliest time HC should start processing a periodic list */
+#define USBFSH_HCPERIODICSTART_PS_MASK (0x3FFFU)
+#define USBFSH_HCPERIODICSTART_PS_SHIFT (0U)
+#define USBFSH_HCPERIODICSTART_PS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCPERIODICSTART_PS_SHIFT)) & USBFSH_HCPERIODICSTART_PS_MASK)
+
+/*! @name HCLSTHRESHOLD - Contains 11-bit value which is used by the HC to determine whether to commit to transfer a maximum of 8-byte LS packet before EOF */
+#define USBFSH_HCLSTHRESHOLD_LST_MASK (0xFFFU)
+#define USBFSH_HCLSTHRESHOLD_LST_SHIFT (0U)
+#define USBFSH_HCLSTHRESHOLD_LST(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCLSTHRESHOLD_LST_SHIFT)) & USBFSH_HCLSTHRESHOLD_LST_MASK)
+
+/*! @name HCRHDESCRIPTORA - First of the two registers which describes the characteristics of the root hub */
+#define USBFSH_HCRHDESCRIPTORA_NDP_MASK (0xFFU)
+#define USBFSH_HCRHDESCRIPTORA_NDP_SHIFT (0U)
+#define USBFSH_HCRHDESCRIPTORA_NDP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NDP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NDP_MASK)
+#define USBFSH_HCRHDESCRIPTORA_PSM_MASK (0x100U)
+#define USBFSH_HCRHDESCRIPTORA_PSM_SHIFT (8U)
+#define USBFSH_HCRHDESCRIPTORA_PSM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_PSM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_PSM_MASK)
+#define USBFSH_HCRHDESCRIPTORA_NPS_MASK (0x200U)
+#define USBFSH_HCRHDESCRIPTORA_NPS_SHIFT (9U)
+#define USBFSH_HCRHDESCRIPTORA_NPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NPS_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NPS_MASK)
+#define USBFSH_HCRHDESCRIPTORA_DT_MASK (0x400U)
+#define USBFSH_HCRHDESCRIPTORA_DT_SHIFT (10U)
+#define USBFSH_HCRHDESCRIPTORA_DT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_DT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_DT_MASK)
+#define USBFSH_HCRHDESCRIPTORA_OCPM_MASK (0x800U)
+#define USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT (11U)
+#define USBFSH_HCRHDESCRIPTORA_OCPM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_OCPM_SHIFT)) & USBFSH_HCRHDESCRIPTORA_OCPM_MASK)
+#define USBFSH_HCRHDESCRIPTORA_NOCP_MASK (0x1000U)
+#define USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT (12U)
+#define USBFSH_HCRHDESCRIPTORA_NOCP(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_NOCP_SHIFT)) & USBFSH_HCRHDESCRIPTORA_NOCP_MASK)
+#define USBFSH_HCRHDESCRIPTORA_POTPGT_MASK (0xFF000000U)
+#define USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT (24U)
+#define USBFSH_HCRHDESCRIPTORA_POTPGT(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORA_POTPGT_SHIFT)) & USBFSH_HCRHDESCRIPTORA_POTPGT_MASK)
+
+/*! @name HCRHDESCRIPTORB - Second of the two registers which describes the characteristics of the Root Hub */
+#define USBFSH_HCRHDESCRIPTORB_DR_MASK (0xFFFFU)
+#define USBFSH_HCRHDESCRIPTORB_DR_SHIFT (0U)
+#define USBFSH_HCRHDESCRIPTORB_DR(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_DR_SHIFT)) & USBFSH_HCRHDESCRIPTORB_DR_MASK)
+#define USBFSH_HCRHDESCRIPTORB_PPCM_MASK (0xFFFF0000U)
+#define USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT (16U)
+#define USBFSH_HCRHDESCRIPTORB_PPCM(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHDESCRIPTORB_PPCM_SHIFT)) & USBFSH_HCRHDESCRIPTORB_PPCM_MASK)
+
+/*! @name HCRHSTATUS - This register is divided into two parts */
+#define USBFSH_HCRHSTATUS_LPS_MASK (0x1U)
+#define USBFSH_HCRHSTATUS_LPS_SHIFT (0U)
+#define USBFSH_HCRHSTATUS_LPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPS_SHIFT)) & USBFSH_HCRHSTATUS_LPS_MASK)
+#define USBFSH_HCRHSTATUS_OCI_MASK (0x2U)
+#define USBFSH_HCRHSTATUS_OCI_SHIFT (1U)
+#define USBFSH_HCRHSTATUS_OCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCI_SHIFT)) & USBFSH_HCRHSTATUS_OCI_MASK)
+#define USBFSH_HCRHSTATUS_DRWE_MASK (0x8000U)
+#define USBFSH_HCRHSTATUS_DRWE_SHIFT (15U)
+#define USBFSH_HCRHSTATUS_DRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_DRWE_SHIFT)) & USBFSH_HCRHSTATUS_DRWE_MASK)
+#define USBFSH_HCRHSTATUS_LPSC_MASK (0x10000U)
+#define USBFSH_HCRHSTATUS_LPSC_SHIFT (16U)
+#define USBFSH_HCRHSTATUS_LPSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_LPSC_SHIFT)) & USBFSH_HCRHSTATUS_LPSC_MASK)
+#define USBFSH_HCRHSTATUS_OCIC_MASK (0x20000U)
+#define USBFSH_HCRHSTATUS_OCIC_SHIFT (17U)
+#define USBFSH_HCRHSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_OCIC_SHIFT)) & USBFSH_HCRHSTATUS_OCIC_MASK)
+#define USBFSH_HCRHSTATUS_CRWE_MASK (0x80000000U)
+#define USBFSH_HCRHSTATUS_CRWE_SHIFT (31U)
+#define USBFSH_HCRHSTATUS_CRWE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHSTATUS_CRWE_SHIFT)) & USBFSH_HCRHSTATUS_CRWE_MASK)
+
+/*! @name HCRHPORTSTATUS - Controls and reports the port events on a per-port basis */
+#define USBFSH_HCRHPORTSTATUS_CCS_MASK (0x1U)
+#define USBFSH_HCRHPORTSTATUS_CCS_SHIFT (0U)
+#define USBFSH_HCRHPORTSTATUS_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CCS_SHIFT)) & USBFSH_HCRHPORTSTATUS_CCS_MASK)
+#define USBFSH_HCRHPORTSTATUS_PES_MASK (0x2U)
+#define USBFSH_HCRHPORTSTATUS_PES_SHIFT (1U)
+#define USBFSH_HCRHPORTSTATUS_PES(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PES_SHIFT)) & USBFSH_HCRHPORTSTATUS_PES_MASK)
+#define USBFSH_HCRHPORTSTATUS_PSS_MASK (0x4U)
+#define USBFSH_HCRHPORTSTATUS_PSS_SHIFT (2U)
+#define USBFSH_HCRHPORTSTATUS_PSS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSS_MASK)
+#define USBFSH_HCRHPORTSTATUS_POCI_MASK (0x8U)
+#define USBFSH_HCRHPORTSTATUS_POCI_SHIFT (3U)
+#define USBFSH_HCRHPORTSTATUS_POCI(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_POCI_SHIFT)) & USBFSH_HCRHPORTSTATUS_POCI_MASK)
+#define USBFSH_HCRHPORTSTATUS_PRS_MASK (0x10U)
+#define USBFSH_HCRHPORTSTATUS_PRS_SHIFT (4U)
+#define USBFSH_HCRHPORTSTATUS_PRS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRS_MASK)
+#define USBFSH_HCRHPORTSTATUS_PPS_MASK (0x100U)
+#define USBFSH_HCRHPORTSTATUS_PPS_SHIFT (8U)
+#define USBFSH_HCRHPORTSTATUS_PPS(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PPS_SHIFT)) & USBFSH_HCRHPORTSTATUS_PPS_MASK)
+#define USBFSH_HCRHPORTSTATUS_LSDA_MASK (0x200U)
+#define USBFSH_HCRHPORTSTATUS_LSDA_SHIFT (9U)
+#define USBFSH_HCRHPORTSTATUS_LSDA(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_LSDA_SHIFT)) & USBFSH_HCRHPORTSTATUS_LSDA_MASK)
+#define USBFSH_HCRHPORTSTATUS_CSC_MASK (0x10000U)
+#define USBFSH_HCRHPORTSTATUS_CSC_SHIFT (16U)
+#define USBFSH_HCRHPORTSTATUS_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_CSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_CSC_MASK)
+#define USBFSH_HCRHPORTSTATUS_PESC_MASK (0x20000U)
+#define USBFSH_HCRHPORTSTATUS_PESC_SHIFT (17U)
+#define USBFSH_HCRHPORTSTATUS_PESC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PESC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PESC_MASK)
+#define USBFSH_HCRHPORTSTATUS_PSSC_MASK (0x40000U)
+#define USBFSH_HCRHPORTSTATUS_PSSC_SHIFT (18U)
+#define USBFSH_HCRHPORTSTATUS_PSSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PSSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PSSC_MASK)
+#define USBFSH_HCRHPORTSTATUS_OCIC_MASK (0x80000U)
+#define USBFSH_HCRHPORTSTATUS_OCIC_SHIFT (19U)
+#define USBFSH_HCRHPORTSTATUS_OCIC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_OCIC_SHIFT)) & USBFSH_HCRHPORTSTATUS_OCIC_MASK)
+#define USBFSH_HCRHPORTSTATUS_PRSC_MASK (0x100000U)
+#define USBFSH_HCRHPORTSTATUS_PRSC_SHIFT (20U)
+#define USBFSH_HCRHPORTSTATUS_PRSC(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_HCRHPORTSTATUS_PRSC_SHIFT)) & USBFSH_HCRHPORTSTATUS_PRSC_MASK)
+
+/*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */
+#define USBFSH_PORTMODE_ID_MASK (0x1U)
+#define USBFSH_PORTMODE_ID_SHIFT (0U)
+#define USBFSH_PORTMODE_ID(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_SHIFT)) & USBFSH_PORTMODE_ID_MASK)
+#define USBFSH_PORTMODE_ID_EN_MASK (0x100U)
+#define USBFSH_PORTMODE_ID_EN_SHIFT (8U)
+#define USBFSH_PORTMODE_ID_EN(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_ID_EN_SHIFT)) & USBFSH_PORTMODE_ID_EN_MASK)
+#define USBFSH_PORTMODE_DEV_ENABLE_MASK (0x10000U)
+#define USBFSH_PORTMODE_DEV_ENABLE_SHIFT (16U)
+#define USBFSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBFSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBFSH_PORTMODE_DEV_ENABLE_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group USBFSH_Register_Masks */
+
+
+/* USBFSH - Peripheral instance base addresses */
+/** Peripheral USBFSH base address */
+#define USBFSH_BASE (0x400A2000u)
+/** Peripheral USBFSH base pointer */
+#define USBFSH ((USBFSH_Type *)USBFSH_BASE)
+/** Array initializer of USBFSH peripheral base addresses */
+#define USBFSH_BASE_ADDRS { USBFSH_BASE }
+/** Array initializer of USBFSH peripheral base pointers */
+#define USBFSH_BASE_PTRS { USBFSH }
+/** Interrupt vectors for the USBFSH peripheral type */
+#define USBFSH_IRQS { USB0_IRQn }
+#define USBFSH_NEEDCLK_IRQS { USB0_NEEDCLK_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USBFSH_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- USBHSD Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBHSD_Peripheral_Access_Layer USBHSD Peripheral Access Layer
+ * @{
+ */
+
+/** USBHSD - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t DEVCMDSTAT; /**< USB Device Command/Status register, offset: 0x0 */
+ __I uint32_t INFO; /**< USB Info register, offset: 0x4 */
+ __IO uint32_t EPLISTSTART; /**< USB EP Command/Status List start address, offset: 0x8 */
+ __I uint32_t DATABUFSTART; /**< USB Data buffer start address, offset: 0xC */
+ __IO uint32_t LPM; /**< USB Link Power Management register, offset: 0x10 */
+ __IO uint32_t EPSKIP; /**< USB Endpoint skip, offset: 0x14 */
+ __IO uint32_t EPINUSE; /**< USB Endpoint Buffer in use, offset: 0x18 */
+ __IO uint32_t EPBUFCFG; /**< USB Endpoint Buffer Configuration register, offset: 0x1C */
+ __IO uint32_t INTSTAT; /**< USB interrupt status register, offset: 0x20 */
+ __IO uint32_t INTEN; /**< USB interrupt enable register, offset: 0x24 */
+ __IO uint32_t INTSETSTAT; /**< USB set interrupt status register, offset: 0x28 */
+ uint8_t RESERVED_0[8];
+ __I uint32_t EPTOGGLE; /**< USB Endpoint toggle register, offset: 0x34 */
+ uint8_t RESERVED_1[4];
+ __IO uint32_t ULPIDEBUG; /**< UTMI/ULPI debug register, offset: 0x3C */
+} USBHSD_Type;
+
+/* ----------------------------------------------------------------------------
+ -- USBHSD Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBHSD_Register_Masks USBHSD Register Masks
+ * @{
+ */
+
+/*! @name DEVCMDSTAT - USB Device Command/Status register */
+#define USBHSD_DEVCMDSTAT_DEV_ADDR_MASK (0x7FU)
+#define USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT (0U)
+#define USBHSD_DEVCMDSTAT_DEV_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_ADDR_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_ADDR_MASK)
+#define USBHSD_DEVCMDSTAT_DEV_EN_MASK (0x80U)
+#define USBHSD_DEVCMDSTAT_DEV_EN_SHIFT (7U)
+#define USBHSD_DEVCMDSTAT_DEV_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DEV_EN_SHIFT)) & USBHSD_DEVCMDSTAT_DEV_EN_MASK)
+#define USBHSD_DEVCMDSTAT_SETUP_MASK (0x100U)
+#define USBHSD_DEVCMDSTAT_SETUP_SHIFT (8U)
+#define USBHSD_DEVCMDSTAT_SETUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_SETUP_SHIFT)) & USBHSD_DEVCMDSTAT_SETUP_MASK)
+#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK (0x200U)
+#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT (9U)
+#define USBHSD_DEVCMDSTAT_FORCE_NEEDCLK(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_NEEDCLK_MASK)
+#define USBHSD_DEVCMDSTAT_FORCE_VBUS_MASK (0x400U)
+#define USBHSD_DEVCMDSTAT_FORCE_VBUS_SHIFT (10U)
+#define USBHSD_DEVCMDSTAT_FORCE_VBUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_FORCE_VBUS_SHIFT)) & USBHSD_DEVCMDSTAT_FORCE_VBUS_MASK)
+#define USBHSD_DEVCMDSTAT_LPM_SUP_MASK (0x800U)
+#define USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT (11U)
+#define USBHSD_DEVCMDSTAT_LPM_SUP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUP_MASK)
+#define USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK (0x1000U)
+#define USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT (12U)
+#define USBHSD_DEVCMDSTAT_INTONNAK_AO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AO_MASK)
+#define USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK (0x2000U)
+#define USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT (13U)
+#define USBHSD_DEVCMDSTAT_INTONNAK_AI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_AI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_AI_MASK)
+#define USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK (0x4000U)
+#define USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT (14U)
+#define USBHSD_DEVCMDSTAT_INTONNAK_CO(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CO_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CO_MASK)
+#define USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK (0x8000U)
+#define USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT (15U)
+#define USBHSD_DEVCMDSTAT_INTONNAK_CI(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_INTONNAK_CI_SHIFT)) & USBHSD_DEVCMDSTAT_INTONNAK_CI_MASK)
+#define USBHSD_DEVCMDSTAT_DCON_MASK (0x10000U)
+#define USBHSD_DEVCMDSTAT_DCON_SHIFT (16U)
+#define USBHSD_DEVCMDSTAT_DCON(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_MASK)
+#define USBHSD_DEVCMDSTAT_DSUS_MASK (0x20000U)
+#define USBHSD_DEVCMDSTAT_DSUS_SHIFT (17U)
+#define USBHSD_DEVCMDSTAT_DSUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_MASK)
+#define USBHSD_DEVCMDSTAT_LPM_SUS_MASK (0x80000U)
+#define USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT (19U)
+#define USBHSD_DEVCMDSTAT_LPM_SUS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_SUS_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_SUS_MASK)
+#define USBHSD_DEVCMDSTAT_LPM_REWP_MASK (0x100000U)
+#define USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT (20U)
+#define USBHSD_DEVCMDSTAT_LPM_REWP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_LPM_REWP_SHIFT)) & USBHSD_DEVCMDSTAT_LPM_REWP_MASK)
+#define USBHSD_DEVCMDSTAT_Speed_MASK (0xC00000U)
+#define USBHSD_DEVCMDSTAT_Speed_SHIFT (22U)
+#define USBHSD_DEVCMDSTAT_Speed(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_Speed_SHIFT)) & USBHSD_DEVCMDSTAT_Speed_MASK)
+#define USBHSD_DEVCMDSTAT_DCON_C_MASK (0x1000000U)
+#define USBHSD_DEVCMDSTAT_DCON_C_SHIFT (24U)
+#define USBHSD_DEVCMDSTAT_DCON_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DCON_C_SHIFT)) & USBHSD_DEVCMDSTAT_DCON_C_MASK)
+#define USBHSD_DEVCMDSTAT_DSUS_C_MASK (0x2000000U)
+#define USBHSD_DEVCMDSTAT_DSUS_C_SHIFT (25U)
+#define USBHSD_DEVCMDSTAT_DSUS_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DSUS_C_SHIFT)) & USBHSD_DEVCMDSTAT_DSUS_C_MASK)
+#define USBHSD_DEVCMDSTAT_DRES_C_MASK (0x4000000U)
+#define USBHSD_DEVCMDSTAT_DRES_C_SHIFT (26U)
+#define USBHSD_DEVCMDSTAT_DRES_C(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_DRES_C_SHIFT)) & USBHSD_DEVCMDSTAT_DRES_C_MASK)
+#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK (0x10000000U)
+#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT (28U)
+#define USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_SHIFT)) & USBHSD_DEVCMDSTAT_VBUS_DEBOUNCED_MASK)
+#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK (0xE0000000U)
+#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT (29U)
+#define USBHSD_DEVCMDSTAT_PHY_TEST_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DEVCMDSTAT_PHY_TEST_MODE_SHIFT)) & USBHSD_DEVCMDSTAT_PHY_TEST_MODE_MASK)
+
+/*! @name INFO - USB Info register */
+#define USBHSD_INFO_FRAME_NR_MASK (0x7FFU)
+#define USBHSD_INFO_FRAME_NR_SHIFT (0U)
+#define USBHSD_INFO_FRAME_NR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_FRAME_NR_SHIFT)) & USBHSD_INFO_FRAME_NR_MASK)
+#define USBHSD_INFO_ERR_CODE_MASK (0x7800U)
+#define USBHSD_INFO_ERR_CODE_SHIFT (11U)
+#define USBHSD_INFO_ERR_CODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_ERR_CODE_SHIFT)) & USBHSD_INFO_ERR_CODE_MASK)
+#define USBHSD_INFO_Minrev_MASK (0xFF0000U)
+#define USBHSD_INFO_Minrev_SHIFT (16U)
+#define USBHSD_INFO_Minrev(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_Minrev_SHIFT)) & USBHSD_INFO_Minrev_MASK)
+#define USBHSD_INFO_Majrev_MASK (0xFF000000U)
+#define USBHSD_INFO_Majrev_SHIFT (24U)
+#define USBHSD_INFO_Majrev(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INFO_Majrev_SHIFT)) & USBHSD_INFO_Majrev_MASK)
+
+/*! @name EPLISTSTART - USB EP Command/Status List start address */
+#define USBHSD_EPLISTSTART_EP_LIST_PRG_MASK (0xFFF00U)
+#define USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT (8U)
+#define USBHSD_EPLISTSTART_EP_LIST_PRG(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_PRG_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_PRG_MASK)
+#define USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK (0xFFF00000U)
+#define USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT (20U)
+#define USBHSD_EPLISTSTART_EP_LIST_FIXED(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPLISTSTART_EP_LIST_FIXED_SHIFT)) & USBHSD_EPLISTSTART_EP_LIST_FIXED_MASK)
+
+/*! @name DATABUFSTART - USB Data buffer start address */
+#define USBHSD_DATABUFSTART_DA_BUF_MASK (0xFFFFFFFFU)
+#define USBHSD_DATABUFSTART_DA_BUF_SHIFT (0U)
+#define USBHSD_DATABUFSTART_DA_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_DATABUFSTART_DA_BUF_SHIFT)) & USBHSD_DATABUFSTART_DA_BUF_MASK)
+
+/*! @name LPM - USB Link Power Management register */
+#define USBHSD_LPM_HIRD_HW_MASK (0xFU)
+#define USBHSD_LPM_HIRD_HW_SHIFT (0U)
+#define USBHSD_LPM_HIRD_HW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_HW_SHIFT)) & USBHSD_LPM_HIRD_HW_MASK)
+#define USBHSD_LPM_HIRD_SW_MASK (0xF0U)
+#define USBHSD_LPM_HIRD_SW_SHIFT (4U)
+#define USBHSD_LPM_HIRD_SW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_HIRD_SW_SHIFT)) & USBHSD_LPM_HIRD_SW_MASK)
+#define USBHSD_LPM_DATA_PENDING_MASK (0x100U)
+#define USBHSD_LPM_DATA_PENDING_SHIFT (8U)
+#define USBHSD_LPM_DATA_PENDING(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_LPM_DATA_PENDING_SHIFT)) & USBHSD_LPM_DATA_PENDING_MASK)
+
+/*! @name EPSKIP - USB Endpoint skip */
+#define USBHSD_EPSKIP_SKIP_MASK (0xFFFU)
+#define USBHSD_EPSKIP_SKIP_SHIFT (0U)
+#define USBHSD_EPSKIP_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPSKIP_SKIP_SHIFT)) & USBHSD_EPSKIP_SKIP_MASK)
+
+/*! @name EPINUSE - USB Endpoint Buffer in use */
+#define USBHSD_EPINUSE_BUF_MASK (0xFFCU)
+#define USBHSD_EPINUSE_BUF_SHIFT (2U)
+#define USBHSD_EPINUSE_BUF(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPINUSE_BUF_SHIFT)) & USBHSD_EPINUSE_BUF_MASK)
+
+/*! @name EPBUFCFG - USB Endpoint Buffer Configuration register */
+#define USBHSD_EPBUFCFG_BUF_SB_MASK (0xFFCU)
+#define USBHSD_EPBUFCFG_BUF_SB_SHIFT (2U)
+#define USBHSD_EPBUFCFG_BUF_SB(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPBUFCFG_BUF_SB_SHIFT)) & USBHSD_EPBUFCFG_BUF_SB_MASK)
+
+/*! @name INTSTAT - USB interrupt status register */
+#define USBHSD_INTSTAT_EP0OUT_MASK (0x1U)
+#define USBHSD_INTSTAT_EP0OUT_SHIFT (0U)
+#define USBHSD_INTSTAT_EP0OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0OUT_SHIFT)) & USBHSD_INTSTAT_EP0OUT_MASK)
+#define USBHSD_INTSTAT_EP0IN_MASK (0x2U)
+#define USBHSD_INTSTAT_EP0IN_SHIFT (1U)
+#define USBHSD_INTSTAT_EP0IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP0IN_SHIFT)) & USBHSD_INTSTAT_EP0IN_MASK)
+#define USBHSD_INTSTAT_EP1OUT_MASK (0x4U)
+#define USBHSD_INTSTAT_EP1OUT_SHIFT (2U)
+#define USBHSD_INTSTAT_EP1OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1OUT_SHIFT)) & USBHSD_INTSTAT_EP1OUT_MASK)
+#define USBHSD_INTSTAT_EP1IN_MASK (0x8U)
+#define USBHSD_INTSTAT_EP1IN_SHIFT (3U)
+#define USBHSD_INTSTAT_EP1IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP1IN_SHIFT)) & USBHSD_INTSTAT_EP1IN_MASK)
+#define USBHSD_INTSTAT_EP2OUT_MASK (0x10U)
+#define USBHSD_INTSTAT_EP2OUT_SHIFT (4U)
+#define USBHSD_INTSTAT_EP2OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2OUT_SHIFT)) & USBHSD_INTSTAT_EP2OUT_MASK)
+#define USBHSD_INTSTAT_EP2IN_MASK (0x20U)
+#define USBHSD_INTSTAT_EP2IN_SHIFT (5U)
+#define USBHSD_INTSTAT_EP2IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP2IN_SHIFT)) & USBHSD_INTSTAT_EP2IN_MASK)
+#define USBHSD_INTSTAT_EP3OUT_MASK (0x40U)
+#define USBHSD_INTSTAT_EP3OUT_SHIFT (6U)
+#define USBHSD_INTSTAT_EP3OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3OUT_SHIFT)) & USBHSD_INTSTAT_EP3OUT_MASK)
+#define USBHSD_INTSTAT_EP3IN_MASK (0x80U)
+#define USBHSD_INTSTAT_EP3IN_SHIFT (7U)
+#define USBHSD_INTSTAT_EP3IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP3IN_SHIFT)) & USBHSD_INTSTAT_EP3IN_MASK)
+#define USBHSD_INTSTAT_EP4OUT_MASK (0x100U)
+#define USBHSD_INTSTAT_EP4OUT_SHIFT (8U)
+#define USBHSD_INTSTAT_EP4OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4OUT_SHIFT)) & USBHSD_INTSTAT_EP4OUT_MASK)
+#define USBHSD_INTSTAT_EP4IN_MASK (0x200U)
+#define USBHSD_INTSTAT_EP4IN_SHIFT (9U)
+#define USBHSD_INTSTAT_EP4IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP4IN_SHIFT)) & USBHSD_INTSTAT_EP4IN_MASK)
+#define USBHSD_INTSTAT_EP5OUT_MASK (0x400U)
+#define USBHSD_INTSTAT_EP5OUT_SHIFT (10U)
+#define USBHSD_INTSTAT_EP5OUT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5OUT_SHIFT)) & USBHSD_INTSTAT_EP5OUT_MASK)
+#define USBHSD_INTSTAT_EP5IN_MASK (0x800U)
+#define USBHSD_INTSTAT_EP5IN_SHIFT (11U)
+#define USBHSD_INTSTAT_EP5IN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_EP5IN_SHIFT)) & USBHSD_INTSTAT_EP5IN_MASK)
+#define USBHSD_INTSTAT_FRAME_INT_MASK (0x40000000U)
+#define USBHSD_INTSTAT_FRAME_INT_SHIFT (30U)
+#define USBHSD_INTSTAT_FRAME_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_FRAME_INT_SHIFT)) & USBHSD_INTSTAT_FRAME_INT_MASK)
+#define USBHSD_INTSTAT_DEV_INT_MASK (0x80000000U)
+#define USBHSD_INTSTAT_DEV_INT_SHIFT (31U)
+#define USBHSD_INTSTAT_DEV_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSTAT_DEV_INT_SHIFT)) & USBHSD_INTSTAT_DEV_INT_MASK)
+
+/*! @name INTEN - USB interrupt enable register */
+#define USBHSD_INTEN_EP_INT_EN_MASK (0xFFFU)
+#define USBHSD_INTEN_EP_INT_EN_SHIFT (0U)
+#define USBHSD_INTEN_EP_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_EP_INT_EN_SHIFT)) & USBHSD_INTEN_EP_INT_EN_MASK)
+#define USBHSD_INTEN_FRAME_INT_EN_MASK (0x40000000U)
+#define USBHSD_INTEN_FRAME_INT_EN_SHIFT (30U)
+#define USBHSD_INTEN_FRAME_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_FRAME_INT_EN_SHIFT)) & USBHSD_INTEN_FRAME_INT_EN_MASK)
+#define USBHSD_INTEN_DEV_INT_EN_MASK (0x80000000U)
+#define USBHSD_INTEN_DEV_INT_EN_SHIFT (31U)
+#define USBHSD_INTEN_DEV_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTEN_DEV_INT_EN_SHIFT)) & USBHSD_INTEN_DEV_INT_EN_MASK)
+
+/*! @name INTSETSTAT - USB set interrupt status register */
+#define USBHSD_INTSETSTAT_EP_SET_INT_MASK (0xFFFU)
+#define USBHSD_INTSETSTAT_EP_SET_INT_SHIFT (0U)
+#define USBHSD_INTSETSTAT_EP_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_EP_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_EP_SET_INT_MASK)
+#define USBHSD_INTSETSTAT_FRAME_SET_INT_MASK (0x40000000U)
+#define USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT (30U)
+#define USBHSD_INTSETSTAT_FRAME_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_FRAME_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_FRAME_SET_INT_MASK)
+#define USBHSD_INTSETSTAT_DEV_SET_INT_MASK (0x80000000U)
+#define USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT (31U)
+#define USBHSD_INTSETSTAT_DEV_SET_INT(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_INTSETSTAT_DEV_SET_INT_SHIFT)) & USBHSD_INTSETSTAT_DEV_SET_INT_MASK)
+
+/*! @name EPTOGGLE - USB Endpoint toggle register */
+#define USBHSD_EPTOGGLE_TOGGLE_MASK (0x3FFFFFFFU)
+#define USBHSD_EPTOGGLE_TOGGLE_SHIFT (0U)
+#define USBHSD_EPTOGGLE_TOGGLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_EPTOGGLE_TOGGLE_SHIFT)) & USBHSD_EPTOGGLE_TOGGLE_MASK)
+
+/*! @name ULPIDEBUG - UTMI/ULPI debug register */
+#define USBHSD_ULPIDEBUG_PHY_ADDR_MASK (0xFFU)
+#define USBHSD_ULPIDEBUG_PHY_ADDR_SHIFT (0U)
+#define USBHSD_ULPIDEBUG_PHY_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_ADDR_SHIFT)) & USBHSD_ULPIDEBUG_PHY_ADDR_MASK)
+#define USBHSD_ULPIDEBUG_PHY_WDATA_MASK (0xFF00U)
+#define USBHSD_ULPIDEBUG_PHY_WDATA_SHIFT (8U)
+#define USBHSD_ULPIDEBUG_PHY_WDATA(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_WDATA_SHIFT)) & USBHSD_ULPIDEBUG_PHY_WDATA_MASK)
+#define USBHSD_ULPIDEBUG_PHY_RDATA_MASK (0xFF0000U)
+#define USBHSD_ULPIDEBUG_PHY_RDATA_SHIFT (16U)
+#define USBHSD_ULPIDEBUG_PHY_RDATA(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_RDATA_SHIFT)) & USBHSD_ULPIDEBUG_PHY_RDATA_MASK)
+#define USBHSD_ULPIDEBUG_PHY_RW_MASK (0x1000000U)
+#define USBHSD_ULPIDEBUG_PHY_RW_SHIFT (24U)
+#define USBHSD_ULPIDEBUG_PHY_RW(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_RW_SHIFT)) & USBHSD_ULPIDEBUG_PHY_RW_MASK)
+#define USBHSD_ULPIDEBUG_PHY_ACCESS_MASK (0x2000000U)
+#define USBHSD_ULPIDEBUG_PHY_ACCESS_SHIFT (25U)
+#define USBHSD_ULPIDEBUG_PHY_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_ACCESS_SHIFT)) & USBHSD_ULPIDEBUG_PHY_ACCESS_MASK)
+#define USBHSD_ULPIDEBUG_PHY_MODE_MASK (0x80000000U)
+#define USBHSD_ULPIDEBUG_PHY_MODE_SHIFT (31U)
+#define USBHSD_ULPIDEBUG_PHY_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSD_ULPIDEBUG_PHY_MODE_SHIFT)) & USBHSD_ULPIDEBUG_PHY_MODE_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group USBHSD_Register_Masks */
+
+
+/* USBHSD - Peripheral instance base addresses */
+/** Peripheral USBHSD base address */
+#define USBHSD_BASE (0x40094000u)
+/** Peripheral USBHSD base pointer */
+#define USBHSD ((USBHSD_Type *)USBHSD_BASE)
+/** Array initializer of USBHSD peripheral base addresses */
+#define USBHSD_BASE_ADDRS { USBHSD_BASE }
+/** Array initializer of USBHSD peripheral base pointers */
+#define USBHSD_BASE_PTRS { USBHSD }
+/** Interrupt vectors for the USBHSD peripheral type */
+#define USBHSD_IRQS { USB1_IRQn }
+#define USBHSD_NEEDCLK_IRQS { USB1_NEEDCLK_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USBHSD_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- USBHSH Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBHSH_Peripheral_Access_Layer USBHSH Peripheral Access Layer
+ * @{
+ */
+
+/** USBHSH - Register Layout Typedef */
+typedef struct {
+ __I uint32_t CAPLENGTH_CHIPID; /**< This register contains the offset value towards the start of the operational register space and the version number of the IP block, offset: 0x0 */
+ __I uint32_t HCSPARAMS; /**< Host Controller Structural Parameters, offset: 0x4 */
+ __I uint32_t HCCPARAMS; /**< Host Controller Capability Parameters, offset: 0x8 */
+ __IO uint32_t FLADJ_FRINDEX; /**< Frame Length Adjustment, offset: 0xC */
+ __IO uint32_t ATL_PTD_BASE_ADDR; /**< Memory base address where ATL PTD0 is stored, offset: 0x10 */
+ __IO uint32_t ISO_PTD_BASE_ADDR; /**< Memory base address where ISO PTD0 is stored, offset: 0x14 */
+ __IO uint32_t INT_PTD_BASE_ADDR; /**< Memory base address where INT PTD0 is stored, offset: 0x18 */
+ __IO uint32_t DATA_PAYLOAD_BASE_ADDR; /**< Memory base address that indicates the start of the data payload buffers, offset: 0x1C */
+ __IO uint32_t USBCMD; /**< USB Command register, offset: 0x20 */
+ __IO uint32_t USBSTS; /**< USB Interrupt Status register, offset: 0x24 */
+ __IO uint32_t USBINTR; /**< USB Interrupt Enable register, offset: 0x28 */
+ __IO uint32_t PORTSC1; /**< Port Status and Control register, offset: 0x2C */
+ __IO uint32_t ATL_PTD_DONE_MAP; /**< Done map for each ATL PTD, offset: 0x30 */
+ __IO uint32_t ATL_PTD_SKIP_MAP; /**< Skip map for each ATL PTD, offset: 0x34 */
+ __IO uint32_t ISO_PTD_DONE_MAP; /**< Done map for each ISO PTD, offset: 0x38 */
+ __IO uint32_t ISO_PTD_SKIP_MAP; /**< Skip map for each ISO PTD, offset: 0x3C */
+ __IO uint32_t INT_PTD_DONE_MAP; /**< Done map for each INT PTD, offset: 0x40 */
+ __IO uint32_t INT_PTD_SKIP_MAP; /**< Skip map for each INT PTD, offset: 0x44 */
+ __IO uint32_t LAST_PTD_INUSE; /**< Marks the last PTD in the list for ISO, INT and ATL, offset: 0x48 */
+ __IO uint32_t UTMIPLUS_ULPI_DEBUG; /**< Register to read/write registers in the attached USB PHY, offset: 0x4C */
+ __IO uint32_t PORTMODE; /**< Controls the port if it is attached to the host block or the device block, offset: 0x50 */
+} USBHSH_Type;
+
+/* ----------------------------------------------------------------------------
+ -- USBHSH Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup USBHSH_Register_Masks USBHSH Register Masks
+ * @{
+ */
+
+/*! @name CAPLENGTH_CHIPID - This register contains the offset value towards the start of the operational register space and the version number of the IP block */
+#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK (0xFFU)
+#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT (0U)
+#define USBHSH_CAPLENGTH_CHIPID_CAPLENGTH(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CAPLENGTH_MASK)
+#define USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK (0xFFFF0000U)
+#define USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT (16U)
+#define USBHSH_CAPLENGTH_CHIPID_CHIPID(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_CAPLENGTH_CHIPID_CHIPID_SHIFT)) & USBHSH_CAPLENGTH_CHIPID_CHIPID_MASK)
+
+/*! @name HCSPARAMS - Host Controller Structural Parameters */
+#define USBHSH_HCSPARAMS_N_PORTS_MASK (0xFU)
+#define USBHSH_HCSPARAMS_N_PORTS_SHIFT (0U)
+#define USBHSH_HCSPARAMS_N_PORTS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_N_PORTS_SHIFT)) & USBHSH_HCSPARAMS_N_PORTS_MASK)
+#define USBHSH_HCSPARAMS_PPC_MASK (0x10U)
+#define USBHSH_HCSPARAMS_PPC_SHIFT (4U)
+#define USBHSH_HCSPARAMS_PPC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_PPC_SHIFT)) & USBHSH_HCSPARAMS_PPC_MASK)
+#define USBHSH_HCSPARAMS_P_INDICATOR_MASK (0x10000U)
+#define USBHSH_HCSPARAMS_P_INDICATOR_SHIFT (16U)
+#define USBHSH_HCSPARAMS_P_INDICATOR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCSPARAMS_P_INDICATOR_SHIFT)) & USBHSH_HCSPARAMS_P_INDICATOR_MASK)
+
+/*! @name HCCPARAMS - Host Controller Capability Parameters */
+#define USBHSH_HCCPARAMS_LPMC_MASK (0x20000U)
+#define USBHSH_HCCPARAMS_LPMC_SHIFT (17U)
+#define USBHSH_HCCPARAMS_LPMC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_HCCPARAMS_LPMC_SHIFT)) & USBHSH_HCCPARAMS_LPMC_MASK)
+
+/*! @name FLADJ_FRINDEX - Frame Length Adjustment */
+#define USBHSH_FLADJ_FRINDEX_FLADJ_MASK (0x3FU)
+#define USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT (0U)
+#define USBHSH_FLADJ_FRINDEX_FLADJ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FLADJ_SHIFT)) & USBHSH_FLADJ_FRINDEX_FLADJ_MASK)
+#define USBHSH_FLADJ_FRINDEX_FRINDEX_MASK (0x3FFF0000U)
+#define USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT (16U)
+#define USBHSH_FLADJ_FRINDEX_FRINDEX(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_FLADJ_FRINDEX_FRINDEX_SHIFT)) & USBHSH_FLADJ_FRINDEX_FRINDEX_MASK)
+
+/*! @name ATL_PTD_BASE_ADDR - Memory base address where ATL PTD0 is stored */
+#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_MASK (0x1F0U)
+#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_SHIFT (4U)
+#define USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_SHIFT)) & USBHSH_ATL_PTD_BASE_ADDR_ATL_CUR_MASK)
+#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_MASK (0xFFFFFE00U)
+#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_SHIFT (9U)
+#define USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_SHIFT)) & USBHSH_ATL_PTD_BASE_ADDR_ATL_BASE_MASK)
+
+/*! @name ISO_PTD_BASE_ADDR - Memory base address where ISO PTD0 is stored */
+#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_MASK (0x3E0U)
+#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_SHIFT (5U)
+#define USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_SHIFT)) & USBHSH_ISO_PTD_BASE_ADDR_ISO_FIRST_MASK)
+#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_MASK (0xFFFFFC00U)
+#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_SHIFT (10U)
+#define USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_SHIFT)) & USBHSH_ISO_PTD_BASE_ADDR_ISO_BASE_MASK)
+
+/*! @name INT_PTD_BASE_ADDR - Memory base address where INT PTD0 is stored */
+#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_MASK (0x3E0U)
+#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_SHIFT (5U)
+#define USBHSH_INT_PTD_BASE_ADDR_INT_FIRST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_SHIFT)) & USBHSH_INT_PTD_BASE_ADDR_INT_FIRST_MASK)
+#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE_MASK (0xFFFFFC00U)
+#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE_SHIFT (10U)
+#define USBHSH_INT_PTD_BASE_ADDR_INT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_BASE_ADDR_INT_BASE_SHIFT)) & USBHSH_INT_PTD_BASE_ADDR_INT_BASE_MASK)
+
+/*! @name DATA_PAYLOAD_BASE_ADDR - Memory base address that indicates the start of the data payload buffers */
+#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_MASK (0xFFFF0000U)
+#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_SHIFT (16U)
+#define USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_SHIFT)) & USBHSH_DATA_PAYLOAD_BASE_ADDR_DAT_BASE_MASK)
+
+/*! @name USBCMD - USB Command register */
+#define USBHSH_USBCMD_RS_MASK (0x1U)
+#define USBHSH_USBCMD_RS_SHIFT (0U)
+#define USBHSH_USBCMD_RS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_RS_SHIFT)) & USBHSH_USBCMD_RS_MASK)
+#define USBHSH_USBCMD_HCRESET_MASK (0x2U)
+#define USBHSH_USBCMD_HCRESET_SHIFT (1U)
+#define USBHSH_USBCMD_HCRESET(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HCRESET_SHIFT)) & USBHSH_USBCMD_HCRESET_MASK)
+#define USBHSH_USBCMD_FLS_MASK (0xCU)
+#define USBHSH_USBCMD_FLS_SHIFT (2U)
+#define USBHSH_USBCMD_FLS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_FLS_SHIFT)) & USBHSH_USBCMD_FLS_MASK)
+#define USBHSH_USBCMD_LHCR_MASK (0x80U)
+#define USBHSH_USBCMD_LHCR_SHIFT (7U)
+#define USBHSH_USBCMD_LHCR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_LHCR_SHIFT)) & USBHSH_USBCMD_LHCR_MASK)
+#define USBHSH_USBCMD_ATL_EN_MASK (0x100U)
+#define USBHSH_USBCMD_ATL_EN_SHIFT (8U)
+#define USBHSH_USBCMD_ATL_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ATL_EN_SHIFT)) & USBHSH_USBCMD_ATL_EN_MASK)
+#define USBHSH_USBCMD_ISO_EN_MASK (0x200U)
+#define USBHSH_USBCMD_ISO_EN_SHIFT (9U)
+#define USBHSH_USBCMD_ISO_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_ISO_EN_SHIFT)) & USBHSH_USBCMD_ISO_EN_MASK)
+#define USBHSH_USBCMD_INT_EN_MASK (0x400U)
+#define USBHSH_USBCMD_INT_EN_SHIFT (10U)
+#define USBHSH_USBCMD_INT_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_INT_EN_SHIFT)) & USBHSH_USBCMD_INT_EN_MASK)
+#define USBHSH_USBCMD_HIRD_MASK (0xF000000U)
+#define USBHSH_USBCMD_HIRD_SHIFT (24U)
+#define USBHSH_USBCMD_HIRD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_HIRD_SHIFT)) & USBHSH_USBCMD_HIRD_MASK)
+#define USBHSH_USBCMD_LPM_RWU_MASK (0x10000000U)
+#define USBHSH_USBCMD_LPM_RWU_SHIFT (28U)
+#define USBHSH_USBCMD_LPM_RWU(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBCMD_LPM_RWU_SHIFT)) & USBHSH_USBCMD_LPM_RWU_MASK)
+
+/*! @name USBSTS - USB Interrupt Status register */
+#define USBHSH_USBSTS_PCD_MASK (0x4U)
+#define USBHSH_USBSTS_PCD_SHIFT (2U)
+#define USBHSH_USBSTS_PCD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_PCD_SHIFT)) & USBHSH_USBSTS_PCD_MASK)
+#define USBHSH_USBSTS_FLR_MASK (0x8U)
+#define USBHSH_USBSTS_FLR_SHIFT (3U)
+#define USBHSH_USBSTS_FLR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_FLR_SHIFT)) & USBHSH_USBSTS_FLR_MASK)
+#define USBHSH_USBSTS_ATL_IRQ_MASK (0x10000U)
+#define USBHSH_USBSTS_ATL_IRQ_SHIFT (16U)
+#define USBHSH_USBSTS_ATL_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ATL_IRQ_SHIFT)) & USBHSH_USBSTS_ATL_IRQ_MASK)
+#define USBHSH_USBSTS_ISO_IRQ_MASK (0x20000U)
+#define USBHSH_USBSTS_ISO_IRQ_SHIFT (17U)
+#define USBHSH_USBSTS_ISO_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_ISO_IRQ_SHIFT)) & USBHSH_USBSTS_ISO_IRQ_MASK)
+#define USBHSH_USBSTS_INT_IRQ_MASK (0x40000U)
+#define USBHSH_USBSTS_INT_IRQ_SHIFT (18U)
+#define USBHSH_USBSTS_INT_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_INT_IRQ_SHIFT)) & USBHSH_USBSTS_INT_IRQ_MASK)
+#define USBHSH_USBSTS_SOF_IRQ_MASK (0x80000U)
+#define USBHSH_USBSTS_SOF_IRQ_SHIFT (19U)
+#define USBHSH_USBSTS_SOF_IRQ(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBSTS_SOF_IRQ_SHIFT)) & USBHSH_USBSTS_SOF_IRQ_MASK)
+
+/*! @name USBINTR - USB Interrupt Enable register */
+#define USBHSH_USBINTR_PCDE_MASK (0x4U)
+#define USBHSH_USBINTR_PCDE_SHIFT (2U)
+#define USBHSH_USBINTR_PCDE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_PCDE_SHIFT)) & USBHSH_USBINTR_PCDE_MASK)
+#define USBHSH_USBINTR_FLRE_MASK (0x8U)
+#define USBHSH_USBINTR_FLRE_SHIFT (3U)
+#define USBHSH_USBINTR_FLRE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_FLRE_SHIFT)) & USBHSH_USBINTR_FLRE_MASK)
+#define USBHSH_USBINTR_ATL_IRQ_E_MASK (0x10000U)
+#define USBHSH_USBINTR_ATL_IRQ_E_SHIFT (16U)
+#define USBHSH_USBINTR_ATL_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ATL_IRQ_E_SHIFT)) & USBHSH_USBINTR_ATL_IRQ_E_MASK)
+#define USBHSH_USBINTR_ISO_IRQ_E_MASK (0x20000U)
+#define USBHSH_USBINTR_ISO_IRQ_E_SHIFT (17U)
+#define USBHSH_USBINTR_ISO_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_ISO_IRQ_E_SHIFT)) & USBHSH_USBINTR_ISO_IRQ_E_MASK)
+#define USBHSH_USBINTR_INT_IRQ_E_MASK (0x40000U)
+#define USBHSH_USBINTR_INT_IRQ_E_SHIFT (18U)
+#define USBHSH_USBINTR_INT_IRQ_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_INT_IRQ_E_SHIFT)) & USBHSH_USBINTR_INT_IRQ_E_MASK)
+#define USBHSH_USBINTR_SOF_E_MASK (0x80000U)
+#define USBHSH_USBINTR_SOF_E_SHIFT (19U)
+#define USBHSH_USBINTR_SOF_E(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_USBINTR_SOF_E_SHIFT)) & USBHSH_USBINTR_SOF_E_MASK)
+
+/*! @name PORTSC1 - Port Status and Control register */
+#define USBHSH_PORTSC1_CCS_MASK (0x1U)
+#define USBHSH_PORTSC1_CCS_SHIFT (0U)
+#define USBHSH_PORTSC1_CCS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CCS_SHIFT)) & USBHSH_PORTSC1_CCS_MASK)
+#define USBHSH_PORTSC1_CSC_MASK (0x2U)
+#define USBHSH_PORTSC1_CSC_SHIFT (1U)
+#define USBHSH_PORTSC1_CSC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_CSC_SHIFT)) & USBHSH_PORTSC1_CSC_MASK)
+#define USBHSH_PORTSC1_PED_MASK (0x4U)
+#define USBHSH_PORTSC1_PED_SHIFT (2U)
+#define USBHSH_PORTSC1_PED(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PED_SHIFT)) & USBHSH_PORTSC1_PED_MASK)
+#define USBHSH_PORTSC1_PEDC_MASK (0x8U)
+#define USBHSH_PORTSC1_PEDC_SHIFT (3U)
+#define USBHSH_PORTSC1_PEDC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PEDC_SHIFT)) & USBHSH_PORTSC1_PEDC_MASK)
+#define USBHSH_PORTSC1_OCA_MASK (0x10U)
+#define USBHSH_PORTSC1_OCA_SHIFT (4U)
+#define USBHSH_PORTSC1_OCA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCA_SHIFT)) & USBHSH_PORTSC1_OCA_MASK)
+#define USBHSH_PORTSC1_OCC_MASK (0x20U)
+#define USBHSH_PORTSC1_OCC_SHIFT (5U)
+#define USBHSH_PORTSC1_OCC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_OCC_SHIFT)) & USBHSH_PORTSC1_OCC_MASK)
+#define USBHSH_PORTSC1_FPR_MASK (0x40U)
+#define USBHSH_PORTSC1_FPR_SHIFT (6U)
+#define USBHSH_PORTSC1_FPR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_FPR_SHIFT)) & USBHSH_PORTSC1_FPR_MASK)
+#define USBHSH_PORTSC1_SUSP_MASK (0x80U)
+#define USBHSH_PORTSC1_SUSP_SHIFT (7U)
+#define USBHSH_PORTSC1_SUSP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUSP_SHIFT)) & USBHSH_PORTSC1_SUSP_MASK)
+#define USBHSH_PORTSC1_PR_MASK (0x100U)
+#define USBHSH_PORTSC1_PR_SHIFT (8U)
+#define USBHSH_PORTSC1_PR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PR_SHIFT)) & USBHSH_PORTSC1_PR_MASK)
+#define USBHSH_PORTSC1_SUS_L1_MASK (0x200U)
+#define USBHSH_PORTSC1_SUS_L1_SHIFT (9U)
+#define USBHSH_PORTSC1_SUS_L1(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUS_L1_SHIFT)) & USBHSH_PORTSC1_SUS_L1_MASK)
+#define USBHSH_PORTSC1_LS_MASK (0xC00U)
+#define USBHSH_PORTSC1_LS_SHIFT (10U)
+#define USBHSH_PORTSC1_LS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_LS_SHIFT)) & USBHSH_PORTSC1_LS_MASK)
+#define USBHSH_PORTSC1_PP_MASK (0x1000U)
+#define USBHSH_PORTSC1_PP_SHIFT (12U)
+#define USBHSH_PORTSC1_PP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PP_SHIFT)) & USBHSH_PORTSC1_PP_MASK)
+#define USBHSH_PORTSC1_PIC_MASK (0xC000U)
+#define USBHSH_PORTSC1_PIC_SHIFT (14U)
+#define USBHSH_PORTSC1_PIC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PIC_SHIFT)) & USBHSH_PORTSC1_PIC_MASK)
+#define USBHSH_PORTSC1_PTC_MASK (0xF0000U)
+#define USBHSH_PORTSC1_PTC_SHIFT (16U)
+#define USBHSH_PORTSC1_PTC(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PTC_SHIFT)) & USBHSH_PORTSC1_PTC_MASK)
+#define USBHSH_PORTSC1_PSPD_MASK (0x300000U)
+#define USBHSH_PORTSC1_PSPD_SHIFT (20U)
+#define USBHSH_PORTSC1_PSPD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_PSPD_SHIFT)) & USBHSH_PORTSC1_PSPD_MASK)
+#define USBHSH_PORTSC1_WOO_MASK (0x400000U)
+#define USBHSH_PORTSC1_WOO_SHIFT (22U)
+#define USBHSH_PORTSC1_WOO(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_WOO_SHIFT)) & USBHSH_PORTSC1_WOO_MASK)
+#define USBHSH_PORTSC1_SUS_STAT_MASK (0x1800000U)
+#define USBHSH_PORTSC1_SUS_STAT_SHIFT (23U)
+#define USBHSH_PORTSC1_SUS_STAT(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_SUS_STAT_SHIFT)) & USBHSH_PORTSC1_SUS_STAT_MASK)
+#define USBHSH_PORTSC1_DEV_ADD_MASK (0xFE000000U)
+#define USBHSH_PORTSC1_DEV_ADD_SHIFT (25U)
+#define USBHSH_PORTSC1_DEV_ADD(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTSC1_DEV_ADD_SHIFT)) & USBHSH_PORTSC1_DEV_ADD_MASK)
+
+/*! @name ATL_PTD_DONE_MAP - Done map for each ATL PTD */
+#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_MASK (0xFFFFFFFFU)
+#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_SHIFT (0U)
+#define USBHSH_ATL_PTD_DONE_MAP_ATL_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_SHIFT)) & USBHSH_ATL_PTD_DONE_MAP_ATL_DONE_MASK)
+
+/*! @name ATL_PTD_SKIP_MAP - Skip map for each ATL PTD */
+#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_MASK (0xFFFFFFFFU)
+#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_SHIFT (0U)
+#define USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_SHIFT)) & USBHSH_ATL_PTD_SKIP_MAP_ATL_SKIP_MASK)
+
+/*! @name ISO_PTD_DONE_MAP - Done map for each ISO PTD */
+#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_MASK (0xFFFFFFFFU)
+#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_SHIFT (0U)
+#define USBHSH_ISO_PTD_DONE_MAP_ISO_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_SHIFT)) & USBHSH_ISO_PTD_DONE_MAP_ISO_DONE_MASK)
+
+/*! @name ISO_PTD_SKIP_MAP - Skip map for each ISO PTD */
+#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_MASK (0xFFFFFFFFU)
+#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_SHIFT (0U)
+#define USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_SHIFT)) & USBHSH_ISO_PTD_SKIP_MAP_ISO_SKIP_MASK)
+
+/*! @name INT_PTD_DONE_MAP - Done map for each INT PTD */
+#define USBHSH_INT_PTD_DONE_MAP_INT_DONE_MASK (0xFFFFFFFFU)
+#define USBHSH_INT_PTD_DONE_MAP_INT_DONE_SHIFT (0U)
+#define USBHSH_INT_PTD_DONE_MAP_INT_DONE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_DONE_MAP_INT_DONE_SHIFT)) & USBHSH_INT_PTD_DONE_MAP_INT_DONE_MASK)
+
+/*! @name INT_PTD_SKIP_MAP - Skip map for each INT PTD */
+#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_MASK (0xFFFFFFFFU)
+#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_SHIFT (0U)
+#define USBHSH_INT_PTD_SKIP_MAP_INT_SKIP(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_SHIFT)) & USBHSH_INT_PTD_SKIP_MAP_INT_SKIP_MASK)
+
+/*! @name LAST_PTD_INUSE - Marks the last PTD in the list for ISO, INT and ATL */
+#define USBHSH_LAST_PTD_INUSE_ATL_LAST_MASK (0x1FU)
+#define USBHSH_LAST_PTD_INUSE_ATL_LAST_SHIFT (0U)
+#define USBHSH_LAST_PTD_INUSE_ATL_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LAST_PTD_INUSE_ATL_LAST_SHIFT)) & USBHSH_LAST_PTD_INUSE_ATL_LAST_MASK)
+#define USBHSH_LAST_PTD_INUSE_ISO_LAST_MASK (0x1F00U)
+#define USBHSH_LAST_PTD_INUSE_ISO_LAST_SHIFT (8U)
+#define USBHSH_LAST_PTD_INUSE_ISO_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LAST_PTD_INUSE_ISO_LAST_SHIFT)) & USBHSH_LAST_PTD_INUSE_ISO_LAST_MASK)
+#define USBHSH_LAST_PTD_INUSE_INT_LAST_MASK (0x1F0000U)
+#define USBHSH_LAST_PTD_INUSE_INT_LAST_SHIFT (16U)
+#define USBHSH_LAST_PTD_INUSE_INT_LAST(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_LAST_PTD_INUSE_INT_LAST_SHIFT)) & USBHSH_LAST_PTD_INUSE_INT_LAST_MASK)
+
+/*! @name UTMIPLUS_ULPI_DEBUG - Register to read/write registers in the attached USB PHY */
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_MASK (0xFFU)
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_SHIFT (0U)
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ADDR_MASK)
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_MASK (0xFF00U)
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_SHIFT (8U)
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_WDATA_MASK)
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_MASK (0xFF0000U)
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_SHIFT (16U)
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RDATA_MASK)
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_MASK (0x1000000U)
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_SHIFT (24U)
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_RW_MASK)
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_MASK (0x2000000U)
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_SHIFT (25U)
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_ACCESS_MASK)
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_MASK (0x80000000U)
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_SHIFT (31U)
+#define USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_SHIFT)) & USBHSH_UTMIPLUS_ULPI_DEBUG_PHY_MODE_MASK)
+
+/*! @name PORTMODE - Controls the port if it is attached to the host block or the device block */
+#define USBHSH_PORTMODE_ID0_MASK (0x1U)
+#define USBHSH_PORTMODE_ID0_SHIFT (0U)
+#define USBHSH_PORTMODE_ID0(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_ID0_SHIFT)) & USBHSH_PORTMODE_ID0_MASK)
+#define USBHSH_PORTMODE_ID0_EN_MASK (0x100U)
+#define USBHSH_PORTMODE_ID0_EN_SHIFT (8U)
+#define USBHSH_PORTMODE_ID0_EN(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_ID0_EN_SHIFT)) & USBHSH_PORTMODE_ID0_EN_MASK)
+#define USBHSH_PORTMODE_DEV_ENABLE_MASK (0x10000U)
+#define USBHSH_PORTMODE_DEV_ENABLE_SHIFT (16U)
+#define USBHSH_PORTMODE_DEV_ENABLE(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_DEV_ENABLE_SHIFT)) & USBHSH_PORTMODE_DEV_ENABLE_MASK)
+#define USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK (0x40000U)
+#define USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT (18U)
+#define USBHSH_PORTMODE_SW_CTRL_PDCOM(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_CTRL_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_CTRL_PDCOM_MASK)
+#define USBHSH_PORTMODE_SW_PDCOM_MASK (0x80000U)
+#define USBHSH_PORTMODE_SW_PDCOM_SHIFT (19U)
+#define USBHSH_PORTMODE_SW_PDCOM(x) (((uint32_t)(((uint32_t)(x)) << USBHSH_PORTMODE_SW_PDCOM_SHIFT)) & USBHSH_PORTMODE_SW_PDCOM_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group USBHSH_Register_Masks */
+
+
+/* USBHSH - Peripheral instance base addresses */
+/** Peripheral USBHSH base address */
+#define USBHSH_BASE (0x400A3000u)
+/** Peripheral USBHSH base pointer */
+#define USBHSH ((USBHSH_Type *)USBHSH_BASE)
+/** Array initializer of USBHSH peripheral base addresses */
+#define USBHSH_BASE_ADDRS { USBHSH_BASE }
+/** Array initializer of USBHSH peripheral base pointers */
+#define USBHSH_BASE_PTRS { USBHSH }
+/** Interrupt vectors for the USBHSH peripheral type */
+#define USBHSH_IRQS { USB1_IRQn }
+#define USBHSH_NEEDCLK_IRQS { USB1_NEEDCLK_IRQn }
+
+/*!
+ * @}
+ */ /* end of group USBHSH_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- UTICK Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UTICK_Peripheral_Access_Layer UTICK Peripheral Access Layer
+ * @{
+ */
+
+/** UTICK - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t CTRL; /**< Control register., offset: 0x0 */
+ __IO uint32_t STAT; /**< Status register., offset: 0x4 */
+ __IO uint32_t CFG; /**< Capture configuration register., offset: 0x8 */
+ __O uint32_t CAPCLR; /**< Capture clear register., offset: 0xC */
+ __I uint32_t CAP[4]; /**< Capture register ., array offset: 0x10, array step: 0x4 */
+} UTICK_Type;
+
+/* ----------------------------------------------------------------------------
+ -- UTICK Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup UTICK_Register_Masks UTICK Register Masks
+ * @{
+ */
+
+/*! @name CTRL - Control register. */
+#define UTICK_CTRL_DELAYVAL_MASK (0x7FFFFFFFU)
+#define UTICK_CTRL_DELAYVAL_SHIFT (0U)
+#define UTICK_CTRL_DELAYVAL(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_DELAYVAL_SHIFT)) & UTICK_CTRL_DELAYVAL_MASK)
+#define UTICK_CTRL_REPEAT_MASK (0x80000000U)
+#define UTICK_CTRL_REPEAT_SHIFT (31U)
+#define UTICK_CTRL_REPEAT(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CTRL_REPEAT_SHIFT)) & UTICK_CTRL_REPEAT_MASK)
+
+/*! @name STAT - Status register. */
+#define UTICK_STAT_INTR_MASK (0x1U)
+#define UTICK_STAT_INTR_SHIFT (0U)
+#define UTICK_STAT_INTR(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_INTR_SHIFT)) & UTICK_STAT_INTR_MASK)
+#define UTICK_STAT_ACTIVE_MASK (0x2U)
+#define UTICK_STAT_ACTIVE_SHIFT (1U)
+#define UTICK_STAT_ACTIVE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_STAT_ACTIVE_SHIFT)) & UTICK_STAT_ACTIVE_MASK)
+
+/*! @name CFG - Capture configuration register. */
+#define UTICK_CFG_CAPEN0_MASK (0x1U)
+#define UTICK_CFG_CAPEN0_SHIFT (0U)
+#define UTICK_CFG_CAPEN0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN0_SHIFT)) & UTICK_CFG_CAPEN0_MASK)
+#define UTICK_CFG_CAPEN1_MASK (0x2U)
+#define UTICK_CFG_CAPEN1_SHIFT (1U)
+#define UTICK_CFG_CAPEN1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN1_SHIFT)) & UTICK_CFG_CAPEN1_MASK)
+#define UTICK_CFG_CAPEN2_MASK (0x4U)
+#define UTICK_CFG_CAPEN2_SHIFT (2U)
+#define UTICK_CFG_CAPEN2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN2_SHIFT)) & UTICK_CFG_CAPEN2_MASK)
+#define UTICK_CFG_CAPEN3_MASK (0x8U)
+#define UTICK_CFG_CAPEN3_SHIFT (3U)
+#define UTICK_CFG_CAPEN3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPEN3_SHIFT)) & UTICK_CFG_CAPEN3_MASK)
+#define UTICK_CFG_CAPPOL0_MASK (0x100U)
+#define UTICK_CFG_CAPPOL0_SHIFT (8U)
+#define UTICK_CFG_CAPPOL0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL0_SHIFT)) & UTICK_CFG_CAPPOL0_MASK)
+#define UTICK_CFG_CAPPOL1_MASK (0x200U)
+#define UTICK_CFG_CAPPOL1_SHIFT (9U)
+#define UTICK_CFG_CAPPOL1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL1_SHIFT)) & UTICK_CFG_CAPPOL1_MASK)
+#define UTICK_CFG_CAPPOL2_MASK (0x400U)
+#define UTICK_CFG_CAPPOL2_SHIFT (10U)
+#define UTICK_CFG_CAPPOL2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL2_SHIFT)) & UTICK_CFG_CAPPOL2_MASK)
+#define UTICK_CFG_CAPPOL3_MASK (0x800U)
+#define UTICK_CFG_CAPPOL3_SHIFT (11U)
+#define UTICK_CFG_CAPPOL3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CFG_CAPPOL3_SHIFT)) & UTICK_CFG_CAPPOL3_MASK)
+
+/*! @name CAPCLR - Capture clear register. */
+#define UTICK_CAPCLR_CAPCLR0_MASK (0x1U)
+#define UTICK_CAPCLR_CAPCLR0_SHIFT (0U)
+#define UTICK_CAPCLR_CAPCLR0(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR0_SHIFT)) & UTICK_CAPCLR_CAPCLR0_MASK)
+#define UTICK_CAPCLR_CAPCLR1_MASK (0x2U)
+#define UTICK_CAPCLR_CAPCLR1_SHIFT (1U)
+#define UTICK_CAPCLR_CAPCLR1(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR1_SHIFT)) & UTICK_CAPCLR_CAPCLR1_MASK)
+#define UTICK_CAPCLR_CAPCLR2_MASK (0x4U)
+#define UTICK_CAPCLR_CAPCLR2_SHIFT (2U)
+#define UTICK_CAPCLR_CAPCLR2(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR2_SHIFT)) & UTICK_CAPCLR_CAPCLR2_MASK)
+#define UTICK_CAPCLR_CAPCLR3_MASK (0x8U)
+#define UTICK_CAPCLR_CAPCLR3_SHIFT (3U)
+#define UTICK_CAPCLR_CAPCLR3(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAPCLR_CAPCLR3_SHIFT)) & UTICK_CAPCLR_CAPCLR3_MASK)
+
+/*! @name CAP - Capture register . */
+#define UTICK_CAP_CAP_VALUE_MASK (0x7FFFFFFFU)
+#define UTICK_CAP_CAP_VALUE_SHIFT (0U)
+#define UTICK_CAP_CAP_VALUE(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_CAP_VALUE_SHIFT)) & UTICK_CAP_CAP_VALUE_MASK)
+#define UTICK_CAP_VALID_MASK (0x80000000U)
+#define UTICK_CAP_VALID_SHIFT (31U)
+#define UTICK_CAP_VALID(x) (((uint32_t)(((uint32_t)(x)) << UTICK_CAP_VALID_SHIFT)) & UTICK_CAP_VALID_MASK)
+
+/* The count of UTICK_CAP */
+#define UTICK_CAP_COUNT (4U)
+
+
+/*!
+ * @}
+ */ /* end of group UTICK_Register_Masks */
+
+
+/* UTICK - Peripheral instance base addresses */
+/** Peripheral UTICK0 base address */
+#define UTICK0_BASE (0x4000E000u)
+/** Peripheral UTICK0 base pointer */
+#define UTICK0 ((UTICK_Type *)UTICK0_BASE)
+/** Array initializer of UTICK peripheral base addresses */
+#define UTICK_BASE_ADDRS { UTICK0_BASE }
+/** Array initializer of UTICK peripheral base pointers */
+#define UTICK_BASE_PTRS { UTICK0 }
+/** Interrupt vectors for the UTICK peripheral type */
+#define UTICK_IRQS { UTICK0_IRQn }
+
+/*!
+ * @}
+ */ /* end of group UTICK_Peripheral_Access_Layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- WWDT Peripheral Access Layer
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WWDT_Peripheral_Access_Layer WWDT Peripheral Access Layer
+ * @{
+ */
+
+/** WWDT - Register Layout Typedef */
+typedef struct {
+ __IO uint32_t MOD; /**< Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer., offset: 0x0 */
+ __IO uint32_t TC; /**< Watchdog timer constant register. This 24-bit register determines the time-out value., offset: 0x4 */
+ __O uint32_t FEED; /**< Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC., offset: 0x8 */
+ __I uint32_t TV; /**< Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer., offset: 0xC */
+ uint8_t RESERVED_0[4];
+ __IO uint32_t WARNINT; /**< Watchdog Warning Interrupt compare value., offset: 0x14 */
+ __IO uint32_t WINDOW; /**< Watchdog Window compare value., offset: 0x18 */
+} WWDT_Type;
+
+/* ----------------------------------------------------------------------------
+ -- WWDT Register Masks
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup WWDT_Register_Masks WWDT Register Masks
+ * @{
+ */
+
+/*! @name MOD - Watchdog mode register. This register contains the basic mode and status of the Watchdog Timer. */
+#define WWDT_MOD_WDEN_MASK (0x1U)
+#define WWDT_MOD_WDEN_SHIFT (0U)
+#define WWDT_MOD_WDEN(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDEN_SHIFT)) & WWDT_MOD_WDEN_MASK)
+#define WWDT_MOD_WDRESET_MASK (0x2U)
+#define WWDT_MOD_WDRESET_SHIFT (1U)
+#define WWDT_MOD_WDRESET(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDRESET_SHIFT)) & WWDT_MOD_WDRESET_MASK)
+#define WWDT_MOD_WDTOF_MASK (0x4U)
+#define WWDT_MOD_WDTOF_SHIFT (2U)
+#define WWDT_MOD_WDTOF(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDTOF_SHIFT)) & WWDT_MOD_WDTOF_MASK)
+#define WWDT_MOD_WDINT_MASK (0x8U)
+#define WWDT_MOD_WDINT_SHIFT (3U)
+#define WWDT_MOD_WDINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDINT_SHIFT)) & WWDT_MOD_WDINT_MASK)
+#define WWDT_MOD_WDPROTECT_MASK (0x10U)
+#define WWDT_MOD_WDPROTECT_SHIFT (4U)
+#define WWDT_MOD_WDPROTECT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_WDPROTECT_SHIFT)) & WWDT_MOD_WDPROTECT_MASK)
+#define WWDT_MOD_LOCK_MASK (0x20U)
+#define WWDT_MOD_LOCK_SHIFT (5U)
+#define WWDT_MOD_LOCK(x) (((uint32_t)(((uint32_t)(x)) << WWDT_MOD_LOCK_SHIFT)) & WWDT_MOD_LOCK_MASK)
+
+/*! @name TC - Watchdog timer constant register. This 24-bit register determines the time-out value. */
+#define WWDT_TC_COUNT_MASK (0xFFFFFFU)
+#define WWDT_TC_COUNT_SHIFT (0U)
+#define WWDT_TC_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TC_COUNT_SHIFT)) & WWDT_TC_COUNT_MASK)
+
+/*! @name FEED - Watchdog feed sequence register. Writing 0xAA followed by 0x55 to this register reloads the Watchdog timer with the value contained in TC. */
+#define WWDT_FEED_FEED_MASK (0xFFU)
+#define WWDT_FEED_FEED_SHIFT (0U)
+#define WWDT_FEED_FEED(x) (((uint32_t)(((uint32_t)(x)) << WWDT_FEED_FEED_SHIFT)) & WWDT_FEED_FEED_MASK)
+
+/*! @name TV - Watchdog timer value register. This 24-bit register reads out the current value of the Watchdog timer. */
+#define WWDT_TV_COUNT_MASK (0xFFFFFFU)
+#define WWDT_TV_COUNT_SHIFT (0U)
+#define WWDT_TV_COUNT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_TV_COUNT_SHIFT)) & WWDT_TV_COUNT_MASK)
+
+/*! @name WARNINT - Watchdog Warning Interrupt compare value. */
+#define WWDT_WARNINT_WARNINT_MASK (0x3FFU)
+#define WWDT_WARNINT_WARNINT_SHIFT (0U)
+#define WWDT_WARNINT_WARNINT(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WARNINT_WARNINT_SHIFT)) & WWDT_WARNINT_WARNINT_MASK)
+
+/*! @name WINDOW - Watchdog Window compare value. */
+#define WWDT_WINDOW_WINDOW_MASK (0xFFFFFFU)
+#define WWDT_WINDOW_WINDOW_SHIFT (0U)
+#define WWDT_WINDOW_WINDOW(x) (((uint32_t)(((uint32_t)(x)) << WWDT_WINDOW_WINDOW_SHIFT)) & WWDT_WINDOW_WINDOW_MASK)
+
+
+/*!
+ * @}
+ */ /* end of group WWDT_Register_Masks */
+
+
+/* WWDT - Peripheral instance base addresses */
+/** Peripheral WWDT base address */
+#define WWDT_BASE (0x4000C000u)
+/** Peripheral WWDT base pointer */
+#define WWDT ((WWDT_Type *)WWDT_BASE)
+/** Array initializer of WWDT peripheral base addresses */
+#define WWDT_BASE_ADDRS { WWDT_BASE }
+/** Array initializer of WWDT peripheral base pointers */
+#define WWDT_BASE_PTRS { WWDT }
+/** Interrupt vectors for the WWDT peripheral type */
+#define WWDT_IRQS { WDT_BOD_IRQn }
+
+/*!
+ * @}
+ */ /* end of group WWDT_Peripheral_Access_Layer */
+
+
+/*
+** End of section using anonymous unions
+*/
+
+#if defined(__ARMCC_VERSION)
+ #pragma pop
+#elif defined(__GNUC__)
+ /* leave anonymous unions enabled */
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma language=default
+#else
+ #error Not supported compiler type
+#endif
+
+/*!
+ * @}
+ */ /* end of group Peripheral_access_layer */
+
+
+/* ----------------------------------------------------------------------------
+ -- Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup Bit_Field_Generic_Macros Macros for use with bit field definitions (xxx_SHIFT, xxx_MASK).
+ * @{
+ */
+
+#if defined(__ARMCC_VERSION)
+ #if (__ARMCC_VERSION >= 6010050)
+ #pragma clang system_header
+ #endif
+#elif defined(__IAR_SYSTEMS_ICC__)
+ #pragma system_include
+#endif
+
+/**
+ * @brief Mask and left-shift a bit field value for use in a register bit range.
+ * @param field Name of the register bit field.
+ * @param value Value of the bit field.
+ * @return Masked and shifted value.
+ */
+#define NXP_VAL2FLD(field, value) (((value) << (field ## _SHIFT)) & (field ## _MASK))
+/**
+ * @brief Mask and right-shift a register value to extract a bit field value.
+ * @param field Name of the register bit field.
+ * @param value Value of the register.
+ * @return Masked and shifted bit field value.
+ */
+#define NXP_FLD2VAL(field, value) (((value) & (field ## _MASK)) >> (field ## _SHIFT))
+
+/*!
+ * @}
+ */ /* end of group Bit_Field_Generic_Macros */
+
+
+/* ----------------------------------------------------------------------------
+ -- SDK Compatibility
+ ---------------------------------------------------------------------------- */
+
+/*!
+ * @addtogroup SDK_Compatibility_Symbols SDK Compatibility
+ * @{
+ */
+
+/** EMC CS base address */
+#define EMC_CS0_BASE (0x80000000u)
+#define EMC_CS1_BASE (0x90000000u)
+#define EMC_CS2_BASE (0x98000000u)
+#define EMC_CS3_BASE (0x9C000000u)
+#define EMC_DYCS0_BASE (0xA0000000u)
+#define EMC_DYCS1_BASE (0xB0000000u)
+#define EMC_DYCS2_BASE (0xC0000000u)
+#define EMC_DYCS3_BASE (0xD0000000u)
+#define EMC_CS_ADDRESS {EMC_CS0_BASE, EMC_CS1_BASE, EMC_CS2_BASE, EMC_CS3_BASE}
+#define EMC_DYCS_ADDRESS {EMC_DYCS0_BASE, EMC_DYCS1_BASE, EMC_DYCS2_BASE, EMC_DYCS3_BASE}
+
+/** OTP API */
+typedef struct {
+ uint32_t (*otpInit)(void); /** Initializes OTP controller */
+ uint32_t (*otpEnableBankWriteMask)(uint32_t bankMask); /** Unlock one or more OTP banks for write access */
+ uint32_t (*otpDisableBankWriteMask)(uint32_t bankMask); /** Lock one or more OTP banks for write access */
+ uint32_t (*otpEnableBankWriteLock)(uint32_t bankIndex, uint32_t regEnableMask, uint32_t regDisableMask,
+ uint32_t lockWrite); /** Locks or unlocks write access to a register of an OTP bank and the write lock */
+ uint32_t (*otpEnableBankReadLock)(uint32_t bankIndex, uint32_t regEnableMask, uint32_t regDisableMask,
+ uint32_t lockWrite); /** Locks or unlocks read access to a register of an OTP bank and the write lock */
+ uint32_t (*otpProgramReg)(uint32_t bankIndex, uint32_t regIndex, uint32_t value); /** Program a single register in an OTP bank */
+ uint32_t RESERVED_0[5];
+ uint32_t (*rngRead)(void); /** Returns 32-bit number from hardware random number generator */
+ uint32_t (*otpGetDriverVersion)(void); /** Returns the version of the OTP driver in ROM */
+} OTP_API_Type;
+
+/** ROM API */
+typedef struct {
+ __I uint32_t usbdApiBase; /** USB API Base */
+ uint32_t RESERVED_0[13];
+ __I OTP_API_Type *otpApiBase; /** OTP API Base */
+ __I uint32_t aesApiBase; /** AES API Base */
+ __I uint32_t secureApiBase; /** Secure API Base */
+} ROM_API_Type;
+
+/** ROM API base address */
+#define ROM_API_BASE (0x03000200u)
+/** ROM API base pointer */
+#define ROM_API (*(ROM_API_Type**) ROM_API_BASE)
+/** OTP API base pointer */
+#define OTP_API (ROM_API->otpApiBase)
+
+/*!
+ * @}
+ */ /* end of group SDK_Compatibility_Symbols */
+
+
+#endif /* _LPC54628_H_ */
+
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/LPC54628_features.h Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,653 @@ +/* +** ################################################################### +** Version: rev. 1.2, 2017-06-08 +** Build: b170609 +** +** Abstract: +** Chip specific module features. +** +** Copyright 2016 Freescale Semiconductor, Inc. +** Copyright 2016-2017 NXP +** Redistribution and use in source and binary forms, with or without modification, +** are permitted provided that the following conditions are met: +** +** 1. Redistributions of source code must retain the above copyright notice, this list +** of conditions and the following disclaimer. +** +** 2. Redistributions in binary form must reproduce the above copyright notice, this +** list of conditions and the following disclaimer in the documentation and/or +** other materials provided with the distribution. +** +** 3. Neither the name of the copyright holder nor the names of its +** contributors may be used to endorse or promote products derived from this +** software without specific prior written permission. +** +** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +** +** http: www.nxp.com +** mail: support@nxp.com +** +** Revisions: +** - rev. 1.0 (2016-08-12) +** Initial version. +** - rev. 1.1 (2016-11-25) +** Update CANFD and Classic CAN register. +** Add MAC TIMERSTAMP registers. +** - rev. 1.2 (2017-06-08) +** Remove RTC_CTRL_RTC_OSC_BYPASS. +** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV. +** Remove RESET and HALT from SYSCON_AHBCLKDIV. +** +** ################################################################### +*/ + +#ifndef _LPC54628_FEATURES_H_ +#define _LPC54628_FEATURES_H_ + +/* SOC module features */ + +/* @brief ACMP availability on the SoC. */ +#define FSL_FEATURE_SOC_ACMP_COUNT (0) +/* @brief ADC availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC_COUNT (1) +/* @brief ADC12 availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC12_COUNT (0) +/* @brief ADC16 availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC16_COUNT (0) +/* @brief ADC_5HC availability on the SoC. */ +#define FSL_FEATURE_SOC_ADC_5HC_COUNT (0) +/* @brief AES availability on the SoC. */ +#define FSL_FEATURE_SOC_AES_COUNT (0) +/* @brief AFE availability on the SoC. */ +#define FSL_FEATURE_SOC_AFE_COUNT (0) +/* @brief AGC availability on the SoC. */ +#define FSL_FEATURE_SOC_AGC_COUNT (0) +/* @brief AIPS availability on the SoC. */ +#define FSL_FEATURE_SOC_AIPS_COUNT (0) +/* @brief AIPSTZ availability on the SoC. */ +#define FSL_FEATURE_SOC_AIPSTZ_COUNT (0) +/* @brief ANATOP availability on the SoC. */ +#define FSL_FEATURE_SOC_ANATOP_COUNT (0) +/* @brief AOI availability on the SoC. */ +#define FSL_FEATURE_SOC_AOI_COUNT (0) +/* @brief APBH availability on the SoC. */ +#define FSL_FEATURE_SOC_APBH_COUNT (0) +/* @brief ASMC availability on the SoC. */ +#define FSL_FEATURE_SOC_ASMC_COUNT (0) +/* @brief ASRC availability on the SoC. */ +#define FSL_FEATURE_SOC_ASRC_COUNT (0) +/* @brief ASYNC_SYSCON availability on the SoC. */ +#define FSL_FEATURE_SOC_ASYNC_SYSCON_COUNT (1) +/* @brief ATX availability on the SoC. */ +#define FSL_FEATURE_SOC_ATX_COUNT (0) +/* @brief AXBS availability on the SoC. */ +#define FSL_FEATURE_SOC_AXBS_COUNT (0) +/* @brief BCH availability on the SoC. */ +#define FSL_FEATURE_SOC_BCH_COUNT (0) +/* @brief BLEDP availability on the SoC. */ +#define FSL_FEATURE_SOC_BLEDP_COUNT (0) +/* @brief BOD availability on the SoC. */ +#define FSL_FEATURE_SOC_BOD_COUNT (0) +/* @brief CAAM availability on the SoC. */ +#define FSL_FEATURE_SOC_CAAM_COUNT (0) +/* @brief CADC availability on the SoC. */ +#define FSL_FEATURE_SOC_CADC_COUNT (0) +/* @brief CALIB availability on the SoC. */ +#define FSL_FEATURE_SOC_CALIB_COUNT (0) +/* @brief CAN availability on the SoC. */ +#define FSL_FEATURE_SOC_LPC_CAN_COUNT (2) +/* @brief CAU availability on the SoC. */ +#define FSL_FEATURE_SOC_CAU_COUNT (0) +/* @brief CAU3 availability on the SoC. */ +#define FSL_FEATURE_SOC_CAU3_COUNT (0) +/* @brief CCM availability on the SoC. */ +#define FSL_FEATURE_SOC_CCM_COUNT (0) +/* @brief CCM_ANALOG availability on the SoC. */ +#define FSL_FEATURE_SOC_CCM_ANALOG_COUNT (0) +/* @brief CHRG availability on the SoC. */ +#define FSL_FEATURE_SOC_CHRG_COUNT (0) +/* @brief CMP availability on the SoC. */ +#define FSL_FEATURE_SOC_CMP_COUNT (0) +/* @brief CMT availability on the SoC. */ +#define FSL_FEATURE_SOC_CMT_COUNT (0) +/* @brief CNC availability on the SoC. */ +#define FSL_FEATURE_SOC_CNC_COUNT (0) +/* @brief COP availability on the SoC. */ +#define FSL_FEATURE_SOC_COP_COUNT (0) +/* @brief CRC availability on the SoC. */ +#define FSL_FEATURE_SOC_CRC_COUNT (1) +/* @brief CS availability on the SoC. */ +#define FSL_FEATURE_SOC_CS_COUNT (0) +/* @brief CSI availability on the SoC. */ +#define FSL_FEATURE_SOC_CSI_COUNT (0) +/* @brief CT32B availability on the SoC. */ +#define FSL_FEATURE_SOC_CT32B_COUNT (0) +/* @brief CTI availability on the SoC. */ +#define FSL_FEATURE_SOC_CTI_COUNT (0) +/* @brief CTIMER availability on the SoC. */ +#define FSL_FEATURE_SOC_CTIMER_COUNT (5) +/* @brief DAC availability on the SoC. */ +#define FSL_FEATURE_SOC_DAC_COUNT (0) +/* @brief DAC32 availability on the SoC. */ +#define FSL_FEATURE_SOC_DAC32_COUNT (0) +/* @brief DCDC availability on the SoC. */ +#define FSL_FEATURE_SOC_DCDC_COUNT (0) +/* @brief DCP availability on the SoC. */ +#define FSL_FEATURE_SOC_DCP_COUNT (0) +/* @brief DDR availability on the SoC. */ +#define FSL_FEATURE_SOC_DDR_COUNT (0) +/* @brief DDRC availability on the SoC. */ +#define FSL_FEATURE_SOC_DDRC_COUNT (0) +/* @brief DDRC_MP availability on the SoC. */ +#define FSL_FEATURE_SOC_DDRC_MP_COUNT (0) +/* @brief DDR_PHY availability on the SoC. */ +#define FSL_FEATURE_SOC_DDR_PHY_COUNT (0) +/* @brief DMA availability on the SoC. */ +#define FSL_FEATURE_SOC_DMA_COUNT (1) +/* @brief DMAMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_DMAMUX_COUNT (0) +/* @brief DMIC availability on the SoC. */ +#define FSL_FEATURE_SOC_DMIC_COUNT (1) +/* @brief DRY availability on the SoC. */ +#define FSL_FEATURE_SOC_DRY_COUNT (0) +/* @brief DSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_DSPI_COUNT (0) +/* @brief ECSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_ECSPI_COUNT (0) +/* @brief EDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_EDMA_COUNT (0) +/* @brief EEPROM availability on the SoC. */ +#define FSL_FEATURE_SOC_EEPROM_COUNT (1) +/* @brief EIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EIM_COUNT (0) +/* @brief EMC availability on the SoC. */ +#define FSL_FEATURE_SOC_EMC_COUNT (1) +/* @brief EMVSIM availability on the SoC. */ +#define FSL_FEATURE_SOC_EMVSIM_COUNT (0) +/* @brief ENC availability on the SoC. */ +#define FSL_FEATURE_SOC_ENC_COUNT (0) +/* @brief ENET availability on the SoC. */ +#define FSL_FEATURE_SOC_LPC_ENET_COUNT (1) +/* @brief EPDC availability on the SoC. */ +#define FSL_FEATURE_SOC_EPDC_COUNT (0) +/* @brief EPIT availability on the SoC. */ +#define FSL_FEATURE_SOC_EPIT_COUNT (0) +/* @brief ESAI availability on the SoC. */ +#define FSL_FEATURE_SOC_ESAI_COUNT (0) +/* @brief EWM availability on the SoC. */ +#define FSL_FEATURE_SOC_EWM_COUNT (0) +/* @brief FB availability on the SoC. */ +#define FSL_FEATURE_SOC_FB_COUNT (0) +/* @brief FGPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FGPIO_COUNT (0) +/* @brief FLASH availability on the SoC. */ +#define FSL_FEATURE_SOC_FLASH_COUNT (0) +/* @brief FLEXCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCAN_COUNT (0) +/* @brief FLEXCOMM availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXCOMM_COUNT (10) +/* @brief FLEXIO availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXIO_COUNT (0) +/* @brief FLEXRAM availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXRAM_COUNT (0) +/* @brief FLEXSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_FLEXSPI_COUNT (0) +/* @brief FMC availability on the SoC. */ +#define FSL_FEATURE_SOC_FMC_COUNT (1) +/* @brief FSKDT availability on the SoC. */ +#define FSL_FEATURE_SOC_FSKDT_COUNT (0) +/* @brief FSP availability on the SoC. */ +#define FSL_FEATURE_SOC_FSP_COUNT (0) +/* @brief FTFA availability on the SoC. */ +#define FSL_FEATURE_SOC_FTFA_COUNT (0) +/* @brief FTFE availability on the SoC. */ +#define FSL_FEATURE_SOC_FTFE_COUNT (0) +/* @brief FTFL availability on the SoC. */ +#define FSL_FEATURE_SOC_FTFL_COUNT (0) +/* @brief FTM availability on the SoC. */ +#define FSL_FEATURE_SOC_FTM_COUNT (0) +/* @brief FTMRA availability on the SoC. */ +#define FSL_FEATURE_SOC_FTMRA_COUNT (0) +/* @brief FTMRE availability on the SoC. */ +#define FSL_FEATURE_SOC_FTMRE_COUNT (0) +/* @brief FTMRH availability on the SoC. */ +#define FSL_FEATURE_SOC_FTMRH_COUNT (0) +/* @brief GINT availability on the SoC. */ +#define FSL_FEATURE_SOC_GINT_COUNT (2) +/* @brief GPC availability on the SoC. */ +#define FSL_FEATURE_SOC_GPC_COUNT (0) +/* @brief GPC_PGC availability on the SoC. */ +#define FSL_FEATURE_SOC_GPC_PGC_COUNT (0) +/* @brief GPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_GPIO_COUNT (1) +/* @brief GPMI availability on the SoC. */ +#define FSL_FEATURE_SOC_GPMI_COUNT (0) +/* @brief GPT availability on the SoC. */ +#define FSL_FEATURE_SOC_GPT_COUNT (0) +/* @brief HSADC availability on the SoC. */ +#define FSL_FEATURE_SOC_HSADC_COUNT (0) +/* @brief I2C availability on the SoC. */ +#define FSL_FEATURE_SOC_I2C_COUNT (10) +/* @brief I2S availability on the SoC. */ +#define FSL_FEATURE_SOC_I2S_COUNT (2) +/* @brief ICS availability on the SoC. */ +#define FSL_FEATURE_SOC_ICS_COUNT (0) +/* @brief IEE availability on the SoC. */ +#define FSL_FEATURE_SOC_IEE_COUNT (0) +/* @brief IEER availability on the SoC. */ +#define FSL_FEATURE_SOC_IEER_COUNT (0) +/* @brief IGPIO availability on the SoC. */ +#define FSL_FEATURE_SOC_IGPIO_COUNT (0) +/* @brief II2C availability on the SoC. */ +#define FSL_FEATURE_SOC_II2C_COUNT (0) +/* @brief INPUTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INPUTMUX_COUNT (1) +/* @brief INTMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_INTMUX_COUNT (0) +/* @brief IOCON availability on the SoC. */ +#define FSL_FEATURE_SOC_IOCON_COUNT (1) +/* @brief IOMUXC availability on the SoC. */ +#define FSL_FEATURE_SOC_IOMUXC_COUNT (0) +/* @brief IOMUXC_GPR availability on the SoC. */ +#define FSL_FEATURE_SOC_IOMUXC_GPR_COUNT (0) +/* @brief IOMUXC_LPSR availability on the SoC. */ +#define FSL_FEATURE_SOC_IOMUXC_LPSR_COUNT (0) +/* @brief IOMUXC_LPSR_GPR availability on the SoC. */ +#define FSL_FEATURE_SOC_IOMUXC_LPSR_GPR_COUNT (0) +/* @brief IOMUXC_SNVS availability on the SoC. */ +#define FSL_FEATURE_SOC_IOMUXC_SNVS_COUNT (0) +/* @brief IPWM availability on the SoC. */ +#define FSL_FEATURE_SOC_IPWM_COUNT (0) +/* @brief IRQ availability on the SoC. */ +#define FSL_FEATURE_SOC_IRQ_COUNT (0) +/* @brief IUART availability on the SoC. */ +#define FSL_FEATURE_SOC_IUART_COUNT (0) +/* @brief KBI availability on the SoC. */ +#define FSL_FEATURE_SOC_KBI_COUNT (0) +/* @brief KPP availability on the SoC. */ +#define FSL_FEATURE_SOC_KPP_COUNT (0) +/* @brief L2CACHEC availability on the SoC. */ +#define FSL_FEATURE_SOC_L2CACHEC_COUNT (0) +/* @brief LCD availability on the SoC. */ +#define FSL_FEATURE_SOC_LCD_COUNT (1) +/* @brief LCDC availability on the SoC. */ +#define FSL_FEATURE_SOC_LCDC_COUNT (0) +/* @brief LCDIF availability on the SoC. */ +#define FSL_FEATURE_SOC_LCDIF_COUNT (0) +/* @brief LDO availability on the SoC. */ +#define FSL_FEATURE_SOC_LDO_COUNT (0) +/* @brief LLWU availability on the SoC. */ +#define FSL_FEATURE_SOC_LLWU_COUNT (0) +/* @brief LMEM availability on the SoC. */ +#define FSL_FEATURE_SOC_LMEM_COUNT (0) +/* @brief LPADC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPADC_COUNT (0) +/* @brief LPCMP availability on the SoC. */ +#define FSL_FEATURE_SOC_LPCMP_COUNT (0) +/* @brief LPDAC availability on the SoC. */ +#define FSL_FEATURE_SOC_LPDAC_COUNT (0) +/* @brief LPI2C availability on the SoC. */ +#define FSL_FEATURE_SOC_LPI2C_COUNT (0) +/* @brief LPIT availability on the SoC. */ +#define FSL_FEATURE_SOC_LPIT_COUNT (0) +/* @brief LPSCI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSCI_COUNT (0) +/* @brief LPSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_LPSPI_COUNT (0) +/* @brief LPTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTMR_COUNT (0) +/* @brief LPTPM availability on the SoC. */ +#define FSL_FEATURE_SOC_LPTPM_COUNT (0) +/* @brief LPUART availability on the SoC. */ +#define FSL_FEATURE_SOC_LPUART_COUNT (0) +/* @brief LTC availability on the SoC. */ +#define FSL_FEATURE_SOC_LTC_COUNT (0) +/* @brief MAILBOX availability on the SoC. */ +#define FSL_FEATURE_SOC_MAILBOX_COUNT (0) +/* @brief MC availability on the SoC. */ +#define FSL_FEATURE_SOC_MC_COUNT (0) +/* @brief MCG availability on the SoC. */ +#define FSL_FEATURE_SOC_MCG_COUNT (0) +/* @brief MCGLITE availability on the SoC. */ +#define FSL_FEATURE_SOC_MCGLITE_COUNT (0) +/* @brief MCM availability on the SoC. */ +#define FSL_FEATURE_SOC_MCM_COUNT (0) +/* @brief MIPI_CSI2 availability on the SoC. */ +#define FSL_FEATURE_SOC_MIPI_CSI2_COUNT (0) +/* @brief MIPI_DSI availability on the SoC. */ +#define FSL_FEATURE_SOC_MIPI_DSI_COUNT (0) +/* @brief MIPI_DSI_HOST availability on the SoC. */ +#define FSL_FEATURE_SOC_MIPI_DSI_HOST_COUNT (0) +/* @brief MMAU availability on the SoC. */ +#define FSL_FEATURE_SOC_MMAU_COUNT (0) +/* @brief MMCAU availability on the SoC. */ +#define FSL_FEATURE_SOC_MMCAU_COUNT (0) +/* @brief MMDC availability on the SoC. */ +#define FSL_FEATURE_SOC_MMDC_COUNT (0) +/* @brief MMDVSQ availability on the SoC. */ +#define FSL_FEATURE_SOC_MMDVSQ_COUNT (0) +/* @brief MPU availability on the SoC. */ +#define FSL_FEATURE_SOC_MPU_COUNT (0) +/* @brief MRT availability on the SoC. */ +#define FSL_FEATURE_SOC_MRT_COUNT (1) +/* @brief MSCAN availability on the SoC. */ +#define FSL_FEATURE_SOC_MSCAN_COUNT (0) +/* @brief MSCM availability on the SoC. */ +#define FSL_FEATURE_SOC_MSCM_COUNT (0) +/* @brief MTB availability on the SoC. */ +#define FSL_FEATURE_SOC_MTB_COUNT (0) +/* @brief MTBDWT availability on the SoC. */ +#define FSL_FEATURE_SOC_MTBDWT_COUNT (0) +/* @brief MU availability on the SoC. */ +#define FSL_FEATURE_SOC_MU_COUNT (0) +/* @brief NFC availability on the SoC. */ +#define FSL_FEATURE_SOC_NFC_COUNT (0) +/* @brief OCOTP availability on the SoC. */ +#define FSL_FEATURE_SOC_OCOTP_COUNT (0) +/* @brief OPAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_OPAMP_COUNT (0) +/* @brief OSC availability on the SoC. */ +#define FSL_FEATURE_SOC_OSC_COUNT (0) +/* @brief OSC32 availability on the SoC. */ +#define FSL_FEATURE_SOC_OSC32_COUNT (0) +/* @brief OTFAD availability on the SoC. */ +#define FSL_FEATURE_SOC_OTFAD_COUNT (0) +/* @brief PCC availability on the SoC. */ +#define FSL_FEATURE_SOC_PCC_COUNT (0) +/* @brief PCIE_PHY_CMN availability on the SoC. */ +#define FSL_FEATURE_SOC_PCIE_PHY_CMN_COUNT (0) +/* @brief PCIE_PHY_TRSV availability on the SoC. */ +#define FSL_FEATURE_SOC_PCIE_PHY_TRSV_COUNT (0) +/* @brief PDB availability on the SoC. */ +#define FSL_FEATURE_SOC_PDB_COUNT (0) +/* @brief PGA availability on the SoC. */ +#define FSL_FEATURE_SOC_PGA_COUNT (0) +/* @brief PINT availability on the SoC. */ +#define FSL_FEATURE_SOC_PINT_COUNT (1) +/* @brief PIT availability on the SoC. */ +#define FSL_FEATURE_SOC_PIT_COUNT (0) +/* @brief PMC availability on the SoC. */ +#define FSL_FEATURE_SOC_PMC_COUNT (0) +/* @brief PMU availability on the SoC. */ +#define FSL_FEATURE_SOC_PMU_COUNT (0) +/* @brief PORT availability on the SoC. */ +#define FSL_FEATURE_SOC_PORT_COUNT (0) +/* @brief PROP availability on the SoC. */ +#define FSL_FEATURE_SOC_PROP_COUNT (0) +/* @brief PWM availability on the SoC. */ +#define FSL_FEATURE_SOC_PWM_COUNT (0) +/* @brief PWT availability on the SoC. */ +#define FSL_FEATURE_SOC_PWT_COUNT (0) +/* @brief PXP availability on the SoC. */ +#define FSL_FEATURE_SOC_PXP_COUNT (0) +/* @brief QDEC availability on the SoC. */ +#define FSL_FEATURE_SOC_QDEC_COUNT (0) +/* @brief QuadSPI availability on the SoC. */ +#define FSL_FEATURE_SOC_QuadSPI_COUNT (0) +/* @brief RCM availability on the SoC. */ +#define FSL_FEATURE_SOC_RCM_COUNT (0) +/* @brief RDC availability on the SoC. */ +#define FSL_FEATURE_SOC_RDC_COUNT (0) +/* @brief RDC_SEMAPHORE availability on the SoC. */ +#define FSL_FEATURE_SOC_RDC_SEMAPHORE_COUNT (0) +/* @brief RFSYS availability on the SoC. */ +#define FSL_FEATURE_SOC_RFSYS_COUNT (0) +/* @brief RFVBAT availability on the SoC. */ +#define FSL_FEATURE_SOC_RFVBAT_COUNT (0) +/* @brief RIT availability on the SoC. */ +#define FSL_FEATURE_SOC_RIT_COUNT (1) +/* @brief RNG availability on the SoC. */ +#define FSL_FEATURE_SOC_LPC_RNG_COUNT (1) +/* @brief RNGB availability on the SoC. */ +#define FSL_FEATURE_SOC_RNGB_COUNT (0) +/* @brief ROM availability on the SoC. */ +#define FSL_FEATURE_SOC_ROM_COUNT (0) +/* @brief ROMC availability on the SoC. */ +#define FSL_FEATURE_SOC_ROMC_COUNT (0) +/* @brief RSIM availability on the SoC. */ +#define FSL_FEATURE_SOC_RSIM_COUNT (0) +/* @brief RTC availability on the SoC. */ +#define FSL_FEATURE_SOC_RTC_COUNT (1) +/* @brief SCG availability on the SoC. */ +#define FSL_FEATURE_SOC_SCG_COUNT (0) +/* @brief SCI availability on the SoC. */ +#define FSL_FEATURE_SOC_SCI_COUNT (0) +/* @brief SCT availability on the SoC. */ +#define FSL_FEATURE_SOC_SCT_COUNT (1) +/* @brief SDHC availability on the SoC. */ +#define FSL_FEATURE_SOC_SDHC_COUNT (0) +/* @brief SDIF availability on the SoC. */ +#define FSL_FEATURE_SOC_SDIF_COUNT (1) +/* @brief SDIO availability on the SoC. */ +#define FSL_FEATURE_SOC_SDIO_COUNT (0) +/* @brief SDMA availability on the SoC. */ +#define FSL_FEATURE_SOC_SDMA_COUNT (0) +/* @brief SDMAARM availability on the SoC. */ +#define FSL_FEATURE_SOC_SDMAARM_COUNT (0) +/* @brief SDMABP availability on the SoC. */ +#define FSL_FEATURE_SOC_SDMABP_COUNT (0) +/* @brief SDMACORE availability on the SoC. */ +#define FSL_FEATURE_SOC_SDMACORE_COUNT (0) +/* @brief SDMCORE availability on the SoC. */ +#define FSL_FEATURE_SOC_SDMCORE_COUNT (0) +/* @brief SDRAM availability on the SoC. */ +#define FSL_FEATURE_SOC_SDRAM_COUNT (0) +/* @brief SEMA4 availability on the SoC. */ +#define FSL_FEATURE_SOC_SEMA4_COUNT (0) +/* @brief SEMA42 availability on the SoC. */ +#define FSL_FEATURE_SOC_SEMA42_COUNT (0) +/* @brief SHA availability on the SoC. */ +#define FSL_FEATURE_SOC_SHA_COUNT (1) +/* @brief SIM availability on the SoC. */ +#define FSL_FEATURE_SOC_SIM_COUNT (0) +/* @brief SJC availability on the SoC. */ +#define FSL_FEATURE_SOC_SJC_COUNT (0) +/* @brief SLCD availability on the SoC. */ +#define FSL_FEATURE_SOC_SLCD_COUNT (0) +/* @brief SMARTCARD availability on the SoC. */ +#define FSL_FEATURE_SOC_SMARTCARD_COUNT (2) +/* @brief SMC availability on the SoC. */ +#define FSL_FEATURE_SOC_SMC_COUNT (0) +/* @brief SNVS availability on the SoC. */ +#define FSL_FEATURE_SOC_SNVS_COUNT (0) +/* @brief SPBA availability on the SoC. */ +#define FSL_FEATURE_SOC_SPBA_COUNT (0) +/* @brief SPDIF availability on the SoC. */ +#define FSL_FEATURE_SOC_SPDIF_COUNT (0) +/* @brief SPI availability on the SoC. */ +#define FSL_FEATURE_SOC_SPI_COUNT (10) +/* @brief SPIFI availability on the SoC. */ +#define FSL_FEATURE_SOC_SPIFI_COUNT (1) +/* @brief SPM availability on the SoC. */ +#define FSL_FEATURE_SOC_SPM_COUNT (0) +/* @brief SRC availability on the SoC. */ +#define FSL_FEATURE_SOC_SRC_COUNT (0) +/* @brief SYSCON availability on the SoC. */ +#define FSL_FEATURE_SOC_SYSCON_COUNT (1) +/* @brief TEMPMON availability on the SoC. */ +#define FSL_FEATURE_SOC_TEMPMON_COUNT (0) +/* @brief TMR availability on the SoC. */ +#define FSL_FEATURE_SOC_TMR_COUNT (0) +/* @brief TPM availability on the SoC. */ +#define FSL_FEATURE_SOC_TPM_COUNT (0) +/* @brief TRGMUX availability on the SoC. */ +#define FSL_FEATURE_SOC_TRGMUX_COUNT (0) +/* @brief TRIAMP availability on the SoC. */ +#define FSL_FEATURE_SOC_TRIAMP_COUNT (0) +/* @brief TRNG availability on the SoC. */ +#define FSL_FEATURE_SOC_TRNG_COUNT (0) +/* @brief TSC availability on the SoC. */ +#define FSL_FEATURE_SOC_TSC_COUNT (0) +/* @brief TSI availability on the SoC. */ +#define FSL_FEATURE_SOC_TSI_COUNT (0) +/* @brief TSTMR availability on the SoC. */ +#define FSL_FEATURE_SOC_TSTMR_COUNT (0) +/* @brief UART availability on the SoC. */ +#define FSL_FEATURE_SOC_UART_COUNT (0) +/* @brief USART availability on the SoC. */ +#define FSL_FEATURE_SOC_USART_COUNT (10) +/* @brief USB availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_COUNT (1) +/* @brief USBHS availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHS_COUNT (0) +/* @brief USBDCD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBDCD_COUNT (0) +/* @brief USBFSH availability on the SoC. */ +#define FSL_FEATURE_SOC_USBFSH_COUNT (1) +/* @brief USBHSD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSD_COUNT (1) +/* @brief USBHSDCD availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSDCD_COUNT (0) +/* @brief USBHSH availability on the SoC. */ +#define FSL_FEATURE_SOC_USBHSH_COUNT (1) +/* @brief USBNC availability on the SoC. */ +#define FSL_FEATURE_SOC_USBNC_COUNT (0) +/* @brief USBPHY availability on the SoC. */ +#define FSL_FEATURE_SOC_USBPHY_COUNT (0) +/* @brief USB_HSIC availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_HSIC_COUNT (0) +/* @brief USB_OTG availability on the SoC. */ +#define FSL_FEATURE_SOC_USB_OTG_COUNT (0) +/* @brief USBVREG availability on the SoC. */ +#define FSL_FEATURE_SOC_USBVREG_COUNT (0) +/* @brief USDHC availability on the SoC. */ +#define FSL_FEATURE_SOC_USDHC_COUNT (0) +/* @brief UTICK availability on the SoC. */ +#define FSL_FEATURE_SOC_UTICK_COUNT (1) +/* @brief VIU availability on the SoC. */ +#define FSL_FEATURE_SOC_VIU_COUNT (0) +/* @brief VREF availability on the SoC. */ +#define FSL_FEATURE_SOC_VREF_COUNT (0) +/* @brief VFIFO availability on the SoC. */ +#define FSL_FEATURE_SOC_VFIFO_COUNT (0) +/* @brief WDOG availability on the SoC. */ +#define FSL_FEATURE_SOC_WDOG_COUNT (0) +/* @brief WKPU availability on the SoC. */ +#define FSL_FEATURE_SOC_WKPU_COUNT (0) +/* @brief WWDT availability on the SoC. */ +#define FSL_FEATURE_SOC_WWDT_COUNT (1) +/* @brief XBAR availability on the SoC. */ +#define FSL_FEATURE_SOC_XBAR_COUNT (0) +/* @brief XBARA availability on the SoC. */ +#define FSL_FEATURE_SOC_XBARA_COUNT (0) +/* @brief XBARB availability on the SoC. */ +#define FSL_FEATURE_SOC_XBARB_COUNT (0) +/* @brief XCVR availability on the SoC. */ +#define FSL_FEATURE_SOC_XCVR_COUNT (0) +/* @brief XRDC availability on the SoC. */ +#define FSL_FEATURE_SOC_XRDC_COUNT (0) +/* @brief XTALOSC availability on the SoC. */ +#define FSL_FEATURE_SOC_XTALOSC_COUNT (0) +/* @brief XTALOSC24M availability on the SoC. */ +#define FSL_FEATURE_SOC_XTALOSC24M_COUNT (0) +/* @brief ZLL availability on the SoC. */ +#define FSL_FEATURE_SOC_ZLL_COUNT (0) + +/* CAN module features */ + +/* @brief Support CANFD or not */ +#define FSL_FEATURE_CAN_SUPPORT_CANFD (1) + +/* DMA module features */ + +/* @brief Number of channels */ +#define FSL_FEATURE_DMA_NUMBER_OF_CHANNELS (30) + +/* EEPROM module features */ + +/* @brief Size of the EEPROM */ +#define FSL_FEATURE_EEPROM_SIZE (0x00004000) +/* @brief Base address of the EEPROM */ +#define FSL_FEATURE_EEPROM_BASE_ADDRESS (0x40108000) +/* @brief Page count of the EEPROM */ +#define FSL_FEATURE_EEPROM_PAGE_COUNT (128) +/* @brief Command number for eeprom program */ +#define FSL_FEATURE_EEPROM_PROGRAM_CMD (6) +/* @brief EEPROM internal clock freqency */ +#define FSL_FEATURE_EEPROM_INTERNAL_FREQ (1500000) + +/* IOCON module features */ + +/* @brief Func bit field width */ +#define FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH (4) + +/* PINT module features */ + +/* @brief Number of connected outputs */ +#define FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS (8) + +/* SCT module features */ + +/* @brief Number of events */ +#define FSL_FEATURE_SCT_NUMBER_OF_EVENTS (10) +/* @brief Number of states */ +#define FSL_FEATURE_SCT_NUMBER_OF_STATES (10) +/* @brief Number of match capture */ +#define FSL_FEATURE_SCT_NUMBER_OF_MATCH_CAPTURE (10) + +/* SDIF module features */ + +/* @brief FIFO depth, every location is a WORD */ +#define FSL_FEATURE_SDIF_FIFO_DEPTH_64_32BITS (64) +/* @brief Max DMA buffer size */ +#define FSL_FEATURE_SDIF_INTERNAL_DMA_MAX_BUFFER_SIZE (4096) +/* @brief Max source clock in HZ */ +#define FSL_FEATURE_SDIF_MAX_SOURCE_CLOCK (52000000) + +/* SPIFI module features */ + +/* @brief SPIFI start address */ +#define FSL_FEATURE_SPIFI_START_ADDR (0x10000000) +/* @brief SPIFI end address */ +#define FSL_FEATURE_SPIFI_END_ADDR (0x17FFFFFF) + +/* SYSCON module features */ + +/* @brief Pointer to ROM IAP entry functions */ +#define FSL_FEATURE_SYSCON_IAP_ENTRY_LOCATION (0x03000205) +/* @brief Flash page size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_PAGE_SIZE_BYTES (256) +/* @brief Flash sector size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SECTOR_SIZE_BYTES (32768) +/* @brief Flash size in bytes */ +#define FSL_FEATURE_SYSCON_FLASH_SIZE_BYTES (524288) + +/* USB module features */ + +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USB_USB_RAM (0x00002000) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USB_USB_RAM_BASE_ADDRESS (0x40100000) + +/* USBFSH module features */ + +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USBFSH_USB_RAM (0x00002000) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USBFSH_USB_RAM_BASE_ADDRESS (0x40100000) + +/* USBHSD module features */ + +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USBHSD_USB_RAM (0x00002000) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USBHSD_USB_RAM_BASE_ADDRESS (0x40100000) + +/* USBHSH module features */ + +/* @brief Size of the USB dedicated RAM */ +#define FSL_FEATURE_USBHSH_USB_RAM (0x00002000) +/* @brief Base address of the USB dedicated RAM */ +#define FSL_FEATURE_USBHSH_USB_RAM_BASE_ADDRESS (0x40100000) + +#endif /* _LPC54628_FEATURES_H_ */ +
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_ARM_STD/LPC54618J512.sct Fri Feb 16 16:09:33 2018 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,121 +0,0 @@
-#! armcc -E
-/*
-** ###################################################################
-** Processors: LPC54618J512BD208
-** LPC54618J512ET180
-**
-** Compiler: Keil ARM C/C++ Compiler
-** Reference manual: LPC54S60x/LPC5460x User manual Rev.0.9 7 Nov 2016
-** Version: rev. 1.1, 2016-11-25
-** Build: b161227
-**
-** Abstract:
-** Linker file for the Keil ARM C/C++ Compiler
-**
-** Copyright (c) 2016 Freescale Semiconductor, Inc.
-** Copyright 2016 - 2017 NXP
-** Redistribution and use in source and binary forms, with or without modification,
-** are permitted provided that the following conditions are met:
-**
-** o Redistributions of source code must retain the above copyright notice, this list
-** of conditions and the following disclaimer.
-**
-** o Redistributions in binary form must reproduce the above copyright notice, this
-** list of conditions and the following disclaimer in the documentation and/or
-** other materials provided with the distribution.
-**
-** o Neither the name of the copyright holder nor the names of its
-** contributors may be used to endorse or promote products derived from this
-** software without specific prior written permission.
-**
-** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-**
-** http: www.nxp.com
-** mail: support@nxp.com
-**
-** ###################################################################
-*/
-#define __ram_vector_table__ 1
-
-#if (defined(__ram_vector_table__))
- #define __ram_vector_table_size__ 0x00000400
-#else
- #define __ram_vector_table_size__ 0x00000000
-#endif
-
-#define m_interrupts_start 0x00000000
-#define m_interrupts_size 0x00000400
-
-#define m_text_start 0x00000400
-#define m_text_size 0x0007FC00
-
-#define m_interrupts_ram_start 0x20000000
-#define m_interrupts_ram_size __ram_vector_table_size__
-
-#define m_data_start (m_interrupts_ram_start + m_interrupts_ram_size)
-#define m_data_size (0x00028000 - m_interrupts_ram_size)
-
-#define m_usb_sram_start 0x40100000
-#define m_usb_sram_size 0x00002000
-
-/* USB BDT size */
-#define usb_bdt_size 0x0
-/* Sizes */
-#if (defined(__stack_size__))
- #define Stack_Size __stack_size__
-#else
- #define Stack_Size 0x0400
-#endif
-
-#if (defined(__heap_size__))
- #define Heap_Size __heap_size__
-#else
- #define Heap_Size 0x0400
-#endif
-
-LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
- VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
- * (RESET,+FIRST)
- }
- ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
- * (InRoot$$Sections)
- .ANY (+RO)
- }
-
-#if (defined(__ram_vector_table__))
- VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size {
- }
-#else
- VECTOR_RAM m_interrupts_start EMPTY 0 {
- }
-#endif
- RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
- .ANY (+RW +ZI)
- }
- RW_IRAM1 +0 EMPTY Heap_Size { ; Heap region growing up
- }
- ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
- }
-}
-
-LR_m_usb_bdt m_usb_sram_start usb_bdt_size {
- ER_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
- * (m_usb_bdt)
- }
-}
-
-LR_m_usb_ram (m_usb_sram_start + usb_bdt_size) (m_usb_sram_size - usb_bdt_size) {
- ER_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
- * (m_usb_global)
- }
-}
-
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_ARM_STD/LPC54628J512.sct Tue Mar 20 16:56:18 2018 +0000
@@ -0,0 +1,119 @@
+#! armcc -E
+/*
+** ###################################################################
+** Processor: LPC54628J512ET180
+** Compiler: Keil ARM C/C++ Compiler
+** Reference manual: LPC546xx User manual Rev.1.9 5 June 2017
+** Version: rev. 1.2, 2017-06-08
+** Build: b170821
+**
+** Abstract:
+** Linker file for the Keil ARM C/C++ Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2017 NXP
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** 1. Redistributions of source code must retain the above copyright notice, this list
+** of conditions and the following disclaimer.
+**
+** 2. Redistributions in binary form must reproduce the above copyright notice, this
+** list of conditions and the following disclaimer in the documentation and/or
+** other materials provided with the distribution.
+**
+** 3. Neither the name of the copyright holder nor the names of its
+** contributors may be used to endorse or promote products derived from this
+** software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+#define __ram_vector_table__ 1
+
+#if (defined(__ram_vector_table__))
+ #define __ram_vector_table_size__ 0x00000400
+#else
+ #define __ram_vector_table_size__ 0x00000000
+#endif
+
+#define m_interrupts_start 0x00000000
+#define m_interrupts_size 0x00000400
+
+#define m_text_start 0x00000400
+#define m_text_size 0x0007FC00
+
+#define m_interrupts_ram_start 0x20000000
+#define m_interrupts_ram_size __ram_vector_table_size__
+
+#define m_data_start (m_interrupts_ram_start + m_interrupts_ram_size)
+#define m_data_size (0x00028000 - m_interrupts_ram_size)
+
+#define m_usb_sram_start 0x40100000
+#define m_usb_sram_size 0x00002000
+
+/* USB BDT size */
+#define usb_bdt_size 0x0
+/* Sizes */
+#if (defined(__stack_size__))
+ #define Stack_Size __stack_size__
+#else
+ #define Stack_Size 0x0400
+#endif
+
+#if (defined(__heap_size__))
+ #define Heap_Size __heap_size__
+#else
+ #define Heap_Size 0x0400
+#endif
+
+LR_m_text m_interrupts_start m_text_start+m_text_size-m_interrupts_start { ; load region size_region
+ VECTOR_ROM m_interrupts_start m_interrupts_size { ; load address = execution address
+ * (RESET,+FIRST)
+ }
+ ER_m_text m_text_start FIXED m_text_size { ; load address = execution address
+ * (InRoot$$Sections)
+ .ANY (+RO)
+ }
+
+#if (defined(__ram_vector_table__))
+ VECTOR_RAM m_interrupts_ram_start EMPTY m_interrupts_ram_size {
+ }
+#else
+ VECTOR_RAM m_interrupts_start EMPTY 0 {
+ }
+#endif
+ RW_m_data m_data_start m_data_size-Stack_Size-Heap_Size { ; RW data
+ .ANY (+RW +ZI)
+ }
+ RW_IRAM1 +0 EMPTY Heap_Size { ; Heap region growing up
+ }
+ ARM_LIB_STACK m_data_start+m_data_size EMPTY -Stack_Size { ; Stack region growing down
+ }
+}
+
+LR_m_usb_bdt m_usb_sram_start usb_bdt_size {
+ ER_m_usb_bdt m_usb_sram_start UNINIT usb_bdt_size {
+ * (m_usb_bdt)
+ }
+}
+
+LR_m_usb_ram (m_usb_sram_start + usb_bdt_size) (m_usb_sram_size - usb_bdt_size) {
+ ER_m_usb_ram (m_usb_sram_start + usb_bdt_size) UNINIT (m_usb_sram_size - usb_bdt_size) {
+ * (m_usb_global)
+ }
+}
+
Binary file targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_ARM_STD/lib_power.ar has changed
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_ARM_STD/startup_LPC54618.S Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,713 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC54618.s -; * @purpose: CMSIS Cortex-M4 Core Device Startup File for the -; * LPC54618 -; * @version: 1.1 -; * @date: 2016-11-25 -; * -; * Copyright 1997 - 2016 Freescale Semiconductor, Inc. -; * Copyright 2016 - 2017 NXP -; * -; * Redistribution and use in source and binary forms, with or without modification, -; * are permitted provided that the following conditions are met: -; * -; * o Redistributions of source code must retain the above copyright notice, this list -; * of conditions and the following disclaimer. -; * -; * o Redistributions in binary form must reproduce the above copyright notice, this -; * list of conditions and the following disclaimer in the documentation and/or -; * other materials provided with the distribution. -; * -; * o Neither the name of the copyright holder nor the names of its -; * contributors may be used to endorse or promote products derived from this -; * software without specific prior written permission. -; * -; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; * -; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -; * -; *****************************************************************************/ - - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack - DCD Reset_Handler ; Reset Handler - - DCD NMI_Handler - DCD HardFault_Handler - DCD MemManage_Handler - DCD BusFault_Handler - DCD UsageFault_Handler -__vector_table_0x1c - DCD 0 ; Checksum of the first 7 words - DCD 0xFFFFFFFF ; ECRP - DCD 0 ; Enhanced image marker, set to 0x0 for legacy boot - DCD 0 ; Pointer to enhanced boot block, set to 0x0 for legacy boot - DCD SVC_Handler - DCD DebugMon_Handler - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD WDT_BOD_IRQHandler ; Windowed watchdog timer, Brownout detect - DCD DMA0_IRQHandler ; DMA controller - DCD GINT0_IRQHandler ; GPIO group 0 - DCD GINT1_IRQHandler ; GPIO group 1 - DCD PIN_INT0_IRQHandler ; Pin interrupt 0 or pattern match engine slice 0 - DCD PIN_INT1_IRQHandler ; Pin interrupt 1or pattern match engine slice 1 - DCD PIN_INT2_IRQHandler ; Pin interrupt 2 or pattern match engine slice 2 - DCD PIN_INT3_IRQHandler ; Pin interrupt 3 or pattern match engine slice 3 - DCD UTICK0_IRQHandler ; Micro-tick Timer - DCD MRT0_IRQHandler ; Multi-rate timer - DCD CTIMER0_IRQHandler ; Standard counter/timer CTIMER0 - DCD CTIMER1_IRQHandler ; Standard counter/timer CTIMER1 - DCD SCT0_IRQHandler ; SCTimer/PWM - DCD CTIMER3_IRQHandler ; Standard counter/timer CTIMER3 - DCD FLEXCOMM0_IRQHandler ; Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) - DCD FLEXCOMM1_IRQHandler ; Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) - DCD FLEXCOMM2_IRQHandler ; Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) - DCD FLEXCOMM3_IRQHandler ; Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) - DCD FLEXCOMM4_IRQHandler ; Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) - DCD FLEXCOMM5_IRQHandler ; Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM) - DCD FLEXCOMM6_IRQHandler ; Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM) - DCD FLEXCOMM7_IRQHandler ; Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM) - DCD ADC0_SEQA_IRQHandler ; ADC0 sequence A completion. - DCD ADC0_SEQB_IRQHandler ; ADC0 sequence B completion. - DCD ADC0_THCMP_IRQHandler ; ADC0 threshold compare and error. - DCD DMIC0_IRQHandler ; Digital microphone and DMIC subsystem - DCD HWVAD0_IRQHandler ; Hardware Voice Activity Detector - DCD USB0_NEEDCLK_IRQHandler ; USB Activity Wake-up Interrupt - DCD USB0_IRQHandler ; USB device - DCD RTC_IRQHandler ; RTC alarm and wake-up interrupts - DCD Reserved46_IRQHandler ; Reserved interrupt - DCD Reserved47_IRQHandler ; Reserved interrupt - DCD PIN_INT4_IRQHandler ; Pin interrupt 4 or pattern match engine slice 4 int - DCD PIN_INT5_IRQHandler ; Pin interrupt 5 or pattern match engine slice 5 int - DCD PIN_INT6_IRQHandler ; Pin interrupt 6 or pattern match engine slice 6 int - DCD PIN_INT7_IRQHandler ; Pin interrupt 7 or pattern match engine slice 7 int - DCD CTIMER2_IRQHandler ; Standard counter/timer CTIMER2 - DCD CTIMER4_IRQHandler ; Standard counter/timer CTIMER4 - DCD RIT_IRQHandler ; Repetitive Interrupt Timer - DCD SPIFI0_IRQHandler ; SPI flash interface - DCD FLEXCOMM8_IRQHandler ; Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM) - DCD FLEXCOMM9_IRQHandler ; Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM) - DCD SDIO_IRQHandler ; SD/MMC - DCD CAN0_IRQ0_IRQHandler ; CAN0 interrupt0 - DCD CAN0_IRQ1_IRQHandler ; CAN0 interrupt1 - DCD CAN1_IRQ0_IRQHandler ; CAN1 interrupt0 - DCD CAN1_IRQ1_IRQHandler ; CAN1 interrupt1 - DCD USB1_IRQHandler ; USB1 interrupt - DCD USB1_NEEDCLK_IRQHandler ; USB1 activity - DCD ETHERNET_IRQHandler ; Ethernet - DCD ETHERNET_PMT_IRQHandler ; Ethernet power management interrupt - DCD ETHERNET_MACLP_IRQHandler ; Ethernet MAC interrupt - DCD EEPROM_IRQHandler ; EEPROM interrupt - DCD LCD_IRQHandler ; LCD interrupt - DCD SHA_IRQHandler ; SHA interrupt - DCD SMARTCARD0_IRQHandler ; Smart card 0 interrupt - DCD SMARTCARD1_IRQHandler ; Smart card 1 interrupt - - AREA |.text|, CODE, READONLY - -; Reset Handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - LDR r0, =SystemInit - BLX r0 - LDR r0, =__main - BX r0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP - -HardFault_Handler \ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP - -MemManage_Handler PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP - -BusFault_Handler PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP - -UsageFault_Handler PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP - -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP - -DebugMon_Handler PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP - -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP - -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -WDT_BOD_IRQHandler\ - PROC - EXPORT WDT_BOD_IRQHandler [WEAK] - LDR R0, =WDT_BOD_DriverIRQHandler - BX R0 - ENDP - -DMA0_IRQHandler\ - PROC - EXPORT DMA0_IRQHandler [WEAK] - LDR R0, =DMA0_DriverIRQHandler - BX R0 - ENDP - -GINT0_IRQHandler\ - PROC - EXPORT GINT0_IRQHandler [WEAK] - LDR R0, =GINT0_DriverIRQHandler - BX R0 - ENDP - -GINT1_IRQHandler\ - PROC - EXPORT GINT1_IRQHandler [WEAK] - LDR R0, =GINT1_DriverIRQHandler - BX R0 - ENDP - -PIN_INT0_IRQHandler\ - PROC - EXPORT PIN_INT0_IRQHandler [WEAK] - LDR R0, =PIN_INT0_DriverIRQHandler - BX R0 - ENDP - -PIN_INT1_IRQHandler\ - PROC - EXPORT PIN_INT1_IRQHandler [WEAK] - LDR R0, =PIN_INT1_DriverIRQHandler - BX R0 - ENDP - -PIN_INT2_IRQHandler\ - PROC - EXPORT PIN_INT2_IRQHandler [WEAK] - LDR R0, =PIN_INT2_DriverIRQHandler - BX R0 - ENDP - -PIN_INT3_IRQHandler\ - PROC - EXPORT PIN_INT3_IRQHandler [WEAK] - LDR R0, =PIN_INT3_DriverIRQHandler - BX R0 - ENDP - -UTICK0_IRQHandler\ - PROC - EXPORT UTICK0_IRQHandler [WEAK] - LDR R0, =UTICK0_DriverIRQHandler - BX R0 - ENDP - -MRT0_IRQHandler\ - PROC - EXPORT MRT0_IRQHandler [WEAK] - LDR R0, =MRT0_DriverIRQHandler - BX R0 - ENDP - -CTIMER0_IRQHandler\ - PROC - EXPORT CTIMER0_IRQHandler [WEAK] - LDR R0, =CTIMER0_DriverIRQHandler - BX R0 - ENDP - -CTIMER1_IRQHandler\ - PROC - EXPORT CTIMER1_IRQHandler [WEAK] - LDR R0, =CTIMER1_DriverIRQHandler - BX R0 - ENDP - -SCT0_IRQHandler\ - PROC - EXPORT SCT0_IRQHandler [WEAK] - LDR R0, =SCT0_DriverIRQHandler - BX R0 - ENDP - -CTIMER3_IRQHandler\ - PROC - EXPORT CTIMER3_IRQHandler [WEAK] - LDR R0, =CTIMER3_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM0_IRQHandler\ - PROC - EXPORT FLEXCOMM0_IRQHandler [WEAK] - LDR R0, =FLEXCOMM0_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM1_IRQHandler\ - PROC - EXPORT FLEXCOMM1_IRQHandler [WEAK] - LDR R0, =FLEXCOMM1_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM2_IRQHandler\ - PROC - EXPORT FLEXCOMM2_IRQHandler [WEAK] - LDR R0, =FLEXCOMM2_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM3_IRQHandler\ - PROC - EXPORT FLEXCOMM3_IRQHandler [WEAK] - LDR R0, =FLEXCOMM3_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM4_IRQHandler\ - PROC - EXPORT FLEXCOMM4_IRQHandler [WEAK] - LDR R0, =FLEXCOMM4_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM5_IRQHandler\ - PROC - EXPORT FLEXCOMM5_IRQHandler [WEAK] - LDR R0, =FLEXCOMM5_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM6_IRQHandler\ - PROC - EXPORT FLEXCOMM6_IRQHandler [WEAK] - LDR R0, =FLEXCOMM6_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM7_IRQHandler\ - PROC - EXPORT FLEXCOMM7_IRQHandler [WEAK] - LDR R0, =FLEXCOMM7_DriverIRQHandler - BX R0 - ENDP - -ADC0_SEQA_IRQHandler\ - PROC - EXPORT ADC0_SEQA_IRQHandler [WEAK] - LDR R0, =ADC0_SEQA_DriverIRQHandler - BX R0 - ENDP - -ADC0_SEQB_IRQHandler\ - PROC - EXPORT ADC0_SEQB_IRQHandler [WEAK] - LDR R0, =ADC0_SEQB_DriverIRQHandler - BX R0 - ENDP - -ADC0_THCMP_IRQHandler\ - PROC - EXPORT ADC0_THCMP_IRQHandler [WEAK] - LDR R0, =ADC0_THCMP_DriverIRQHandler - BX R0 - ENDP - -DMIC0_IRQHandler\ - PROC - EXPORT DMIC0_IRQHandler [WEAK] - LDR R0, =DMIC0_DriverIRQHandler - BX R0 - ENDP - -HWVAD0_IRQHandler\ - PROC - EXPORT HWVAD0_IRQHandler [WEAK] - LDR R0, =HWVAD0_DriverIRQHandler - BX R0 - ENDP - -USB0_NEEDCLK_IRQHandler\ - PROC - EXPORT USB0_NEEDCLK_IRQHandler [WEAK] - LDR R0, =USB0_NEEDCLK_DriverIRQHandler - BX R0 - ENDP - -USB0_IRQHandler\ - PROC - EXPORT USB0_IRQHandler [WEAK] - LDR R0, =USB0_DriverIRQHandler - BX R0 - ENDP - -RTC_IRQHandler\ - PROC - EXPORT RTC_IRQHandler [WEAK] - LDR R0, =RTC_DriverIRQHandler - BX R0 - ENDP - -Reserved46_IRQHandler\ - PROC - EXPORT Reserved46_IRQHandler [WEAK] - LDR R0, =Reserved46_DriverIRQHandler - BX R0 - ENDP - -Reserved47_IRQHandler\ - PROC - EXPORT Reserved47_IRQHandler [WEAK] - LDR R0, =Reserved47_DriverIRQHandler - BX R0 - ENDP - -PIN_INT4_IRQHandler\ - PROC - EXPORT PIN_INT4_IRQHandler [WEAK] - LDR R0, =PIN_INT4_DriverIRQHandler - BX R0 - ENDP - -PIN_INT5_IRQHandler\ - PROC - EXPORT PIN_INT5_IRQHandler [WEAK] - LDR R0, =PIN_INT5_DriverIRQHandler - BX R0 - ENDP - -PIN_INT6_IRQHandler\ - PROC - EXPORT PIN_INT6_IRQHandler [WEAK] - LDR R0, =PIN_INT6_DriverIRQHandler - BX R0 - ENDP - -PIN_INT7_IRQHandler\ - PROC - EXPORT PIN_INT7_IRQHandler [WEAK] - LDR R0, =PIN_INT7_DriverIRQHandler - BX R0 - ENDP - -CTIMER2_IRQHandler\ - PROC - EXPORT CTIMER2_IRQHandler [WEAK] - LDR R0, =CTIMER2_DriverIRQHandler - BX R0 - ENDP - -CTIMER4_IRQHandler\ - PROC - EXPORT CTIMER4_IRQHandler [WEAK] - LDR R0, =CTIMER4_DriverIRQHandler - BX R0 - ENDP - -RIT_IRQHandler\ - PROC - EXPORT RIT_IRQHandler [WEAK] - LDR R0, =RIT_DriverIRQHandler - BX R0 - ENDP - -SPIFI0_IRQHandler\ - PROC - EXPORT SPIFI0_IRQHandler [WEAK] - LDR R0, =SPIFI0_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM8_IRQHandler\ - PROC - EXPORT FLEXCOMM8_IRQHandler [WEAK] - LDR R0, =FLEXCOMM8_DriverIRQHandler - BX R0 - ENDP - -FLEXCOMM9_IRQHandler\ - PROC - EXPORT FLEXCOMM9_IRQHandler [WEAK] - LDR R0, =FLEXCOMM9_DriverIRQHandler - BX R0 - ENDP - -SDIO_IRQHandler\ - PROC - EXPORT SDIO_IRQHandler [WEAK] - LDR R0, =SDIO_DriverIRQHandler - BX R0 - ENDP - -CAN0_IRQ0_IRQHandler\ - PROC - EXPORT CAN0_IRQ0_IRQHandler [WEAK] - LDR R0, =CAN0_IRQ0_DriverIRQHandler - BX R0 - ENDP - -CAN0_IRQ1_IRQHandler\ - PROC - EXPORT CAN0_IRQ1_IRQHandler [WEAK] - LDR R0, =CAN0_IRQ1_DriverIRQHandler - BX R0 - ENDP - -CAN1_IRQ0_IRQHandler\ - PROC - EXPORT CAN1_IRQ0_IRQHandler [WEAK] - LDR R0, =CAN1_IRQ0_DriverIRQHandler - BX R0 - ENDP - -CAN1_IRQ1_IRQHandler\ - PROC - EXPORT CAN1_IRQ1_IRQHandler [WEAK] - LDR R0, =CAN1_IRQ1_DriverIRQHandler - BX R0 - ENDP - -USB1_IRQHandler\ - PROC - EXPORT USB1_IRQHandler [WEAK] - LDR R0, =USB1_DriverIRQHandler - BX R0 - ENDP - -USB1_NEEDCLK_IRQHandler\ - PROC - EXPORT USB1_NEEDCLK_IRQHandler [WEAK] - LDR R0, =USB1_NEEDCLK_DriverIRQHandler - BX R0 - ENDP - -ETHERNET_IRQHandler\ - PROC - EXPORT ETHERNET_IRQHandler [WEAK] - LDR R0, =ETHERNET_DriverIRQHandler - BX R0 - ENDP - -ETHERNET_PMT_IRQHandler\ - PROC - EXPORT ETHERNET_PMT_IRQHandler [WEAK] - LDR R0, =ETHERNET_PMT_DriverIRQHandler - BX R0 - ENDP - -ETHERNET_MACLP_IRQHandler\ - PROC - EXPORT ETHERNET_MACLP_IRQHandler [WEAK] - LDR R0, =ETHERNET_MACLP_DriverIRQHandler - BX R0 - ENDP - -EEPROM_IRQHandler\ - PROC - EXPORT EEPROM_IRQHandler [WEAK] - LDR R0, =EEPROM_DriverIRQHandler - BX R0 - ENDP - -LCD_IRQHandler\ - PROC - EXPORT LCD_IRQHandler [WEAK] - LDR R0, =LCD_DriverIRQHandler - BX R0 - ENDP - -SHA_IRQHandler\ - PROC - EXPORT SHA_IRQHandler [WEAK] - LDR R0, =SHA_DriverIRQHandler - BX R0 - ENDP - -SMARTCARD0_IRQHandler\ - PROC - EXPORT SMARTCARD0_IRQHandler [WEAK] - LDR R0, =SMARTCARD0_DriverIRQHandler - BX R0 - ENDP - -SMARTCARD1_IRQHandler\ - PROC - EXPORT SMARTCARD1_IRQHandler [WEAK] - LDR R0, =SMARTCARD1_DriverIRQHandler - BX R0 - ENDP - -Default_Handler PROC - EXPORT WDT_BOD_DriverIRQHandler [WEAK] - EXPORT DMA0_DriverIRQHandler [WEAK] - EXPORT GINT0_DriverIRQHandler [WEAK] - EXPORT GINT1_DriverIRQHandler [WEAK] - EXPORT PIN_INT0_DriverIRQHandler [WEAK] - EXPORT PIN_INT1_DriverIRQHandler [WEAK] - EXPORT PIN_INT2_DriverIRQHandler [WEAK] - EXPORT PIN_INT3_DriverIRQHandler [WEAK] - EXPORT UTICK0_DriverIRQHandler [WEAK] - EXPORT MRT0_DriverIRQHandler [WEAK] - EXPORT CTIMER0_DriverIRQHandler [WEAK] - EXPORT CTIMER1_DriverIRQHandler [WEAK] - EXPORT SCT0_DriverIRQHandler [WEAK] - EXPORT CTIMER3_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM0_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM1_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM2_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM3_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM4_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM5_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM6_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM7_DriverIRQHandler [WEAK] - EXPORT ADC0_SEQA_DriverIRQHandler [WEAK] - EXPORT ADC0_SEQB_DriverIRQHandler [WEAK] - EXPORT ADC0_THCMP_DriverIRQHandler [WEAK] - EXPORT DMIC0_DriverIRQHandler [WEAK] - EXPORT HWVAD0_DriverIRQHandler [WEAK] - EXPORT USB0_NEEDCLK_DriverIRQHandler [WEAK] - EXPORT USB0_DriverIRQHandler [WEAK] - EXPORT RTC_DriverIRQHandler [WEAK] - EXPORT Reserved46_DriverIRQHandler [WEAK] - EXPORT Reserved47_DriverIRQHandler [WEAK] - EXPORT PIN_INT4_DriverIRQHandler [WEAK] - EXPORT PIN_INT5_DriverIRQHandler [WEAK] - EXPORT PIN_INT6_DriverIRQHandler [WEAK] - EXPORT PIN_INT7_DriverIRQHandler [WEAK] - EXPORT CTIMER2_DriverIRQHandler [WEAK] - EXPORT CTIMER4_DriverIRQHandler [WEAK] - EXPORT RIT_DriverIRQHandler [WEAK] - EXPORT SPIFI0_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM8_DriverIRQHandler [WEAK] - EXPORT FLEXCOMM9_DriverIRQHandler [WEAK] - EXPORT SDIO_DriverIRQHandler [WEAK] - EXPORT CAN0_IRQ0_DriverIRQHandler [WEAK] - EXPORT CAN0_IRQ1_DriverIRQHandler [WEAK] - EXPORT CAN1_IRQ0_DriverIRQHandler [WEAK] - EXPORT CAN1_IRQ1_DriverIRQHandler [WEAK] - EXPORT USB1_DriverIRQHandler [WEAK] - EXPORT USB1_NEEDCLK_DriverIRQHandler [WEAK] - EXPORT ETHERNET_DriverIRQHandler [WEAK] - EXPORT ETHERNET_PMT_DriverIRQHandler [WEAK] - EXPORT ETHERNET_MACLP_DriverIRQHandler [WEAK] - EXPORT EEPROM_DriverIRQHandler [WEAK] - EXPORT LCD_DriverIRQHandler [WEAK] - EXPORT SHA_DriverIRQHandler [WEAK] - EXPORT SMARTCARD0_DriverIRQHandler [WEAK] - EXPORT SMARTCARD1_DriverIRQHandler [WEAK] - -WDT_BOD_DriverIRQHandler -DMA0_DriverIRQHandler -GINT0_DriverIRQHandler -GINT1_DriverIRQHandler -PIN_INT0_DriverIRQHandler -PIN_INT1_DriverIRQHandler -PIN_INT2_DriverIRQHandler -PIN_INT3_DriverIRQHandler -UTICK0_DriverIRQHandler -MRT0_DriverIRQHandler -CTIMER0_DriverIRQHandler -CTIMER1_DriverIRQHandler -SCT0_DriverIRQHandler -CTIMER3_DriverIRQHandler -FLEXCOMM0_DriverIRQHandler -FLEXCOMM1_DriverIRQHandler -FLEXCOMM2_DriverIRQHandler -FLEXCOMM3_DriverIRQHandler -FLEXCOMM4_DriverIRQHandler -FLEXCOMM5_DriverIRQHandler -FLEXCOMM6_DriverIRQHandler -FLEXCOMM7_DriverIRQHandler -ADC0_SEQA_DriverIRQHandler -ADC0_SEQB_DriverIRQHandler -ADC0_THCMP_DriverIRQHandler -DMIC0_DriverIRQHandler -HWVAD0_DriverIRQHandler -USB0_NEEDCLK_DriverIRQHandler -USB0_DriverIRQHandler -RTC_DriverIRQHandler -Reserved46_DriverIRQHandler -Reserved47_DriverIRQHandler -PIN_INT4_DriverIRQHandler -PIN_INT5_DriverIRQHandler -PIN_INT6_DriverIRQHandler -PIN_INT7_DriverIRQHandler -CTIMER2_DriverIRQHandler -CTIMER4_DriverIRQHandler -RIT_DriverIRQHandler -SPIFI0_DriverIRQHandler -FLEXCOMM8_DriverIRQHandler -FLEXCOMM9_DriverIRQHandler -SDIO_DriverIRQHandler -CAN0_IRQ0_DriverIRQHandler -CAN0_IRQ1_DriverIRQHandler -CAN1_IRQ0_DriverIRQHandler -CAN1_IRQ1_DriverIRQHandler -USB1_DriverIRQHandler -USB1_NEEDCLK_DriverIRQHandler -ETHERNET_DriverIRQHandler -ETHERNET_PMT_DriverIRQHandler -ETHERNET_MACLP_DriverIRQHandler -EEPROM_DriverIRQHandler -LCD_DriverIRQHandler -SHA_DriverIRQHandler -SMARTCARD0_DriverIRQHandler -SMARTCARD1_DriverIRQHandler - - B . - - ENDP - - - ALIGN - - - END -
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_ARM_STD/startup_LPC54628.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,713 @@ +;/***************************************************************************** +; * @file: startup_LPC54628.s +; * @purpose: CMSIS Cortex-M4 Core Device Startup File for the +; * LPC54628 +; * @version: 1.2 +; * @date: 2017-6-8 +; * +; * Copyright 1997-2016 Freescale Semiconductor, Inc. +; * Copyright 2016-2017 NXP +; * +; * Redistribution and use in source and binary forms, with or without modification, +; * are permitted provided that the following conditions are met: +; * +; * 1. Redistributions of source code must retain the above copyright notice, this list +; * of conditions and the following disclaimer. +; * +; * 2. Redistributions in binary form must reproduce the above copyright notice, this +; * list of conditions and the following disclaimer in the documentation and/or +; * other materials provided with the distribution. +; * +; * 3. Neither the name of the copyright holder nor the names of its +; * contributors may be used to endorse or promote products derived from this +; * software without specific prior written permission. +; * +; * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +; * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +; * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; * +; *------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +; * +; *****************************************************************************/ + + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + IMPORT |Image$$ARM_LIB_STACK$$ZI$$Limit| + +__Vectors DCD |Image$$ARM_LIB_STACK$$ZI$$Limit| ; Top of Stack + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 ; Checksum of the first 7 words + DCD 0xFFFFFFFF ; ECRP + DCD 0 ; Enhanced image marker, set to 0x0 for legacy boot + DCD 0 ; Pointer to enhanced boot block, set to 0x0 for legacy boot + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD WDT_BOD_IRQHandler ; Windowed watchdog timer, Brownout detect + DCD DMA0_IRQHandler ; DMA controller + DCD GINT0_IRQHandler ; GPIO group 0 + DCD GINT1_IRQHandler ; GPIO group 1 + DCD PIN_INT0_IRQHandler ; Pin interrupt 0 or pattern match engine slice 0 + DCD PIN_INT1_IRQHandler ; Pin interrupt 1or pattern match engine slice 1 + DCD PIN_INT2_IRQHandler ; Pin interrupt 2 or pattern match engine slice 2 + DCD PIN_INT3_IRQHandler ; Pin interrupt 3 or pattern match engine slice 3 + DCD UTICK0_IRQHandler ; Micro-tick Timer + DCD MRT0_IRQHandler ; Multi-rate timer + DCD CTIMER0_IRQHandler ; Standard counter/timer CTIMER0 + DCD CTIMER1_IRQHandler ; Standard counter/timer CTIMER1 + DCD SCT0_IRQHandler ; SCTimer/PWM + DCD CTIMER3_IRQHandler ; Standard counter/timer CTIMER3 + DCD FLEXCOMM0_IRQHandler ; Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) + DCD FLEXCOMM1_IRQHandler ; Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) + DCD FLEXCOMM2_IRQHandler ; Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) + DCD FLEXCOMM3_IRQHandler ; Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) + DCD FLEXCOMM4_IRQHandler ; Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) + DCD FLEXCOMM5_IRQHandler ; Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM) + DCD FLEXCOMM6_IRQHandler ; Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM) + DCD FLEXCOMM7_IRQHandler ; Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM) + DCD ADC0_SEQA_IRQHandler ; ADC0 sequence A completion. + DCD ADC0_SEQB_IRQHandler ; ADC0 sequence B completion. + DCD ADC0_THCMP_IRQHandler ; ADC0 threshold compare and error. + DCD DMIC0_IRQHandler ; Digital microphone and DMIC subsystem + DCD HWVAD0_IRQHandler ; Hardware Voice Activity Detector + DCD USB0_NEEDCLK_IRQHandler ; USB Activity Wake-up Interrupt + DCD USB0_IRQHandler ; USB device + DCD RTC_IRQHandler ; RTC alarm and wake-up interrupts + DCD Reserved46_IRQHandler ; Reserved interrupt + DCD Reserved47_IRQHandler ; Reserved interrupt + DCD PIN_INT4_IRQHandler ; Pin interrupt 4 or pattern match engine slice 4 int + DCD PIN_INT5_IRQHandler ; Pin interrupt 5 or pattern match engine slice 5 int + DCD PIN_INT6_IRQHandler ; Pin interrupt 6 or pattern match engine slice 6 int + DCD PIN_INT7_IRQHandler ; Pin interrupt 7 or pattern match engine slice 7 int + DCD CTIMER2_IRQHandler ; Standard counter/timer CTIMER2 + DCD CTIMER4_IRQHandler ; Standard counter/timer CTIMER4 + DCD RIT_IRQHandler ; Repetitive Interrupt Timer + DCD SPIFI0_IRQHandler ; SPI flash interface + DCD FLEXCOMM8_IRQHandler ; Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM) + DCD FLEXCOMM9_IRQHandler ; Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM) + DCD SDIO_IRQHandler ; SD/MMC + DCD CAN0_IRQ0_IRQHandler ; CAN0 interrupt0 + DCD CAN0_IRQ1_IRQHandler ; CAN0 interrupt1 + DCD CAN1_IRQ0_IRQHandler ; CAN1 interrupt0 + DCD CAN1_IRQ1_IRQHandler ; CAN1 interrupt1 + DCD USB1_IRQHandler ; USB1 interrupt + DCD USB1_NEEDCLK_IRQHandler ; USB1 activity + DCD ETHERNET_IRQHandler ; Ethernet + DCD ETHERNET_PMT_IRQHandler ; Ethernet power management interrupt + DCD ETHERNET_MACLP_IRQHandler ; Ethernet MAC interrupt + DCD EEPROM_IRQHandler ; EEPROM interrupt + DCD LCD_IRQHandler ; LCD interrupt + DCD SHA_IRQHandler ; SHA interrupt + DCD SMARTCARD0_IRQHandler ; Smart card 0 interrupt + DCD SMARTCARD1_IRQHandler ; Smart card 1 interrupt + + AREA |.text|, CODE, READONLY + +; Reset Handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR r0, =SystemInit + BLX r0 + LDR r0, =__main + BX r0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP + +HardFault_Handler \ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP + +MemManage_Handler PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP + +BusFault_Handler PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP + +UsageFault_Handler PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP + +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP + +DebugMon_Handler PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP + +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP + +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +WDT_BOD_IRQHandler\ + PROC + EXPORT WDT_BOD_IRQHandler [WEAK] + LDR R0, =WDT_BOD_DriverIRQHandler + BX R0 + ENDP + +DMA0_IRQHandler\ + PROC + EXPORT DMA0_IRQHandler [WEAK] + LDR R0, =DMA0_DriverIRQHandler + BX R0 + ENDP + +GINT0_IRQHandler\ + PROC + EXPORT GINT0_IRQHandler [WEAK] + LDR R0, =GINT0_DriverIRQHandler + BX R0 + ENDP + +GINT1_IRQHandler\ + PROC + EXPORT GINT1_IRQHandler [WEAK] + LDR R0, =GINT1_DriverIRQHandler + BX R0 + ENDP + +PIN_INT0_IRQHandler\ + PROC + EXPORT PIN_INT0_IRQHandler [WEAK] + LDR R0, =PIN_INT0_DriverIRQHandler + BX R0 + ENDP + +PIN_INT1_IRQHandler\ + PROC + EXPORT PIN_INT1_IRQHandler [WEAK] + LDR R0, =PIN_INT1_DriverIRQHandler + BX R0 + ENDP + +PIN_INT2_IRQHandler\ + PROC + EXPORT PIN_INT2_IRQHandler [WEAK] + LDR R0, =PIN_INT2_DriverIRQHandler + BX R0 + ENDP + +PIN_INT3_IRQHandler\ + PROC + EXPORT PIN_INT3_IRQHandler [WEAK] + LDR R0, =PIN_INT3_DriverIRQHandler + BX R0 + ENDP + +UTICK0_IRQHandler\ + PROC + EXPORT UTICK0_IRQHandler [WEAK] + LDR R0, =UTICK0_DriverIRQHandler + BX R0 + ENDP + +MRT0_IRQHandler\ + PROC + EXPORT MRT0_IRQHandler [WEAK] + LDR R0, =MRT0_DriverIRQHandler + BX R0 + ENDP + +CTIMER0_IRQHandler\ + PROC + EXPORT CTIMER0_IRQHandler [WEAK] + LDR R0, =CTIMER0_DriverIRQHandler + BX R0 + ENDP + +CTIMER1_IRQHandler\ + PROC + EXPORT CTIMER1_IRQHandler [WEAK] + LDR R0, =CTIMER1_DriverIRQHandler + BX R0 + ENDP + +SCT0_IRQHandler\ + PROC + EXPORT SCT0_IRQHandler [WEAK] + LDR R0, =SCT0_DriverIRQHandler + BX R0 + ENDP + +CTIMER3_IRQHandler\ + PROC + EXPORT CTIMER3_IRQHandler [WEAK] + LDR R0, =CTIMER3_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM0_IRQHandler\ + PROC + EXPORT FLEXCOMM0_IRQHandler [WEAK] + LDR R0, =FLEXCOMM0_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM1_IRQHandler\ + PROC + EXPORT FLEXCOMM1_IRQHandler [WEAK] + LDR R0, =FLEXCOMM1_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM2_IRQHandler\ + PROC + EXPORT FLEXCOMM2_IRQHandler [WEAK] + LDR R0, =FLEXCOMM2_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM3_IRQHandler\ + PROC + EXPORT FLEXCOMM3_IRQHandler [WEAK] + LDR R0, =FLEXCOMM3_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM4_IRQHandler\ + PROC + EXPORT FLEXCOMM4_IRQHandler [WEAK] + LDR R0, =FLEXCOMM4_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM5_IRQHandler\ + PROC + EXPORT FLEXCOMM5_IRQHandler [WEAK] + LDR R0, =FLEXCOMM5_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM6_IRQHandler\ + PROC + EXPORT FLEXCOMM6_IRQHandler [WEAK] + LDR R0, =FLEXCOMM6_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM7_IRQHandler\ + PROC + EXPORT FLEXCOMM7_IRQHandler [WEAK] + LDR R0, =FLEXCOMM7_DriverIRQHandler + BX R0 + ENDP + +ADC0_SEQA_IRQHandler\ + PROC + EXPORT ADC0_SEQA_IRQHandler [WEAK] + LDR R0, =ADC0_SEQA_DriverIRQHandler + BX R0 + ENDP + +ADC0_SEQB_IRQHandler\ + PROC + EXPORT ADC0_SEQB_IRQHandler [WEAK] + LDR R0, =ADC0_SEQB_DriverIRQHandler + BX R0 + ENDP + +ADC0_THCMP_IRQHandler\ + PROC + EXPORT ADC0_THCMP_IRQHandler [WEAK] + LDR R0, =ADC0_THCMP_DriverIRQHandler + BX R0 + ENDP + +DMIC0_IRQHandler\ + PROC + EXPORT DMIC0_IRQHandler [WEAK] + LDR R0, =DMIC0_DriverIRQHandler + BX R0 + ENDP + +HWVAD0_IRQHandler\ + PROC + EXPORT HWVAD0_IRQHandler [WEAK] + LDR R0, =HWVAD0_DriverIRQHandler + BX R0 + ENDP + +USB0_NEEDCLK_IRQHandler\ + PROC + EXPORT USB0_NEEDCLK_IRQHandler [WEAK] + LDR R0, =USB0_NEEDCLK_DriverIRQHandler + BX R0 + ENDP + +USB0_IRQHandler\ + PROC + EXPORT USB0_IRQHandler [WEAK] + LDR R0, =USB0_DriverIRQHandler + BX R0 + ENDP + +RTC_IRQHandler\ + PROC + EXPORT RTC_IRQHandler [WEAK] + LDR R0, =RTC_DriverIRQHandler + BX R0 + ENDP + +Reserved46_IRQHandler\ + PROC + EXPORT Reserved46_IRQHandler [WEAK] + LDR R0, =Reserved46_DriverIRQHandler + BX R0 + ENDP + +Reserved47_IRQHandler\ + PROC + EXPORT Reserved47_IRQHandler [WEAK] + LDR R0, =Reserved47_DriverIRQHandler + BX R0 + ENDP + +PIN_INT4_IRQHandler\ + PROC + EXPORT PIN_INT4_IRQHandler [WEAK] + LDR R0, =PIN_INT4_DriverIRQHandler + BX R0 + ENDP + +PIN_INT5_IRQHandler\ + PROC + EXPORT PIN_INT5_IRQHandler [WEAK] + LDR R0, =PIN_INT5_DriverIRQHandler + BX R0 + ENDP + +PIN_INT6_IRQHandler\ + PROC + EXPORT PIN_INT6_IRQHandler [WEAK] + LDR R0, =PIN_INT6_DriverIRQHandler + BX R0 + ENDP + +PIN_INT7_IRQHandler\ + PROC + EXPORT PIN_INT7_IRQHandler [WEAK] + LDR R0, =PIN_INT7_DriverIRQHandler + BX R0 + ENDP + +CTIMER2_IRQHandler\ + PROC + EXPORT CTIMER2_IRQHandler [WEAK] + LDR R0, =CTIMER2_DriverIRQHandler + BX R0 + ENDP + +CTIMER4_IRQHandler\ + PROC + EXPORT CTIMER4_IRQHandler [WEAK] + LDR R0, =CTIMER4_DriverIRQHandler + BX R0 + ENDP + +RIT_IRQHandler\ + PROC + EXPORT RIT_IRQHandler [WEAK] + LDR R0, =RIT_DriverIRQHandler + BX R0 + ENDP + +SPIFI0_IRQHandler\ + PROC + EXPORT SPIFI0_IRQHandler [WEAK] + LDR R0, =SPIFI0_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM8_IRQHandler\ + PROC + EXPORT FLEXCOMM8_IRQHandler [WEAK] + LDR R0, =FLEXCOMM8_DriverIRQHandler + BX R0 + ENDP + +FLEXCOMM9_IRQHandler\ + PROC + EXPORT FLEXCOMM9_IRQHandler [WEAK] + LDR R0, =FLEXCOMM9_DriverIRQHandler + BX R0 + ENDP + +SDIO_IRQHandler\ + PROC + EXPORT SDIO_IRQHandler [WEAK] + LDR R0, =SDIO_DriverIRQHandler + BX R0 + ENDP + +CAN0_IRQ0_IRQHandler\ + PROC + EXPORT CAN0_IRQ0_IRQHandler [WEAK] + LDR R0, =CAN0_IRQ0_DriverIRQHandler + BX R0 + ENDP + +CAN0_IRQ1_IRQHandler\ + PROC + EXPORT CAN0_IRQ1_IRQHandler [WEAK] + LDR R0, =CAN0_IRQ1_DriverIRQHandler + BX R0 + ENDP + +CAN1_IRQ0_IRQHandler\ + PROC + EXPORT CAN1_IRQ0_IRQHandler [WEAK] + LDR R0, =CAN1_IRQ0_DriverIRQHandler + BX R0 + ENDP + +CAN1_IRQ1_IRQHandler\ + PROC + EXPORT CAN1_IRQ1_IRQHandler [WEAK] + LDR R0, =CAN1_IRQ1_DriverIRQHandler + BX R0 + ENDP + +USB1_IRQHandler\ + PROC + EXPORT USB1_IRQHandler [WEAK] + LDR R0, =USB1_DriverIRQHandler + BX R0 + ENDP + +USB1_NEEDCLK_IRQHandler\ + PROC + EXPORT USB1_NEEDCLK_IRQHandler [WEAK] + LDR R0, =USB1_NEEDCLK_DriverIRQHandler + BX R0 + ENDP + +ETHERNET_IRQHandler\ + PROC + EXPORT ETHERNET_IRQHandler [WEAK] + LDR R0, =ETHERNET_DriverIRQHandler + BX R0 + ENDP + +ETHERNET_PMT_IRQHandler\ + PROC + EXPORT ETHERNET_PMT_IRQHandler [WEAK] + LDR R0, =ETHERNET_PMT_DriverIRQHandler + BX R0 + ENDP + +ETHERNET_MACLP_IRQHandler\ + PROC + EXPORT ETHERNET_MACLP_IRQHandler [WEAK] + LDR R0, =ETHERNET_MACLP_DriverIRQHandler + BX R0 + ENDP + +EEPROM_IRQHandler\ + PROC + EXPORT EEPROM_IRQHandler [WEAK] + LDR R0, =EEPROM_DriverIRQHandler + BX R0 + ENDP + +LCD_IRQHandler\ + PROC + EXPORT LCD_IRQHandler [WEAK] + LDR R0, =LCD_DriverIRQHandler + BX R0 + ENDP + +SHA_IRQHandler\ + PROC + EXPORT SHA_IRQHandler [WEAK] + LDR R0, =SHA_DriverIRQHandler + BX R0 + ENDP + +SMARTCARD0_IRQHandler\ + PROC + EXPORT SMARTCARD0_IRQHandler [WEAK] + LDR R0, =SMARTCARD0_DriverIRQHandler + BX R0 + ENDP + +SMARTCARD1_IRQHandler\ + PROC + EXPORT SMARTCARD1_IRQHandler [WEAK] + LDR R0, =SMARTCARD1_DriverIRQHandler + BX R0 + ENDP + +Default_Handler PROC + EXPORT WDT_BOD_DriverIRQHandler [WEAK] + EXPORT DMA0_DriverIRQHandler [WEAK] + EXPORT GINT0_DriverIRQHandler [WEAK] + EXPORT GINT1_DriverIRQHandler [WEAK] + EXPORT PIN_INT0_DriverIRQHandler [WEAK] + EXPORT PIN_INT1_DriverIRQHandler [WEAK] + EXPORT PIN_INT2_DriverIRQHandler [WEAK] + EXPORT PIN_INT3_DriverIRQHandler [WEAK] + EXPORT UTICK0_DriverIRQHandler [WEAK] + EXPORT MRT0_DriverIRQHandler [WEAK] + EXPORT CTIMER0_DriverIRQHandler [WEAK] + EXPORT CTIMER1_DriverIRQHandler [WEAK] + EXPORT SCT0_DriverIRQHandler [WEAK] + EXPORT CTIMER3_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM0_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM1_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM2_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM3_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM4_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM5_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM6_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM7_DriverIRQHandler [WEAK] + EXPORT ADC0_SEQA_DriverIRQHandler [WEAK] + EXPORT ADC0_SEQB_DriverIRQHandler [WEAK] + EXPORT ADC0_THCMP_DriverIRQHandler [WEAK] + EXPORT DMIC0_DriverIRQHandler [WEAK] + EXPORT HWVAD0_DriverIRQHandler [WEAK] + EXPORT USB0_NEEDCLK_DriverIRQHandler [WEAK] + EXPORT USB0_DriverIRQHandler [WEAK] + EXPORT RTC_DriverIRQHandler [WEAK] + EXPORT Reserved46_DriverIRQHandler [WEAK] + EXPORT Reserved47_DriverIRQHandler [WEAK] + EXPORT PIN_INT4_DriverIRQHandler [WEAK] + EXPORT PIN_INT5_DriverIRQHandler [WEAK] + EXPORT PIN_INT6_DriverIRQHandler [WEAK] + EXPORT PIN_INT7_DriverIRQHandler [WEAK] + EXPORT CTIMER2_DriverIRQHandler [WEAK] + EXPORT CTIMER4_DriverIRQHandler [WEAK] + EXPORT RIT_DriverIRQHandler [WEAK] + EXPORT SPIFI0_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM8_DriverIRQHandler [WEAK] + EXPORT FLEXCOMM9_DriverIRQHandler [WEAK] + EXPORT SDIO_DriverIRQHandler [WEAK] + EXPORT CAN0_IRQ0_DriverIRQHandler [WEAK] + EXPORT CAN0_IRQ1_DriverIRQHandler [WEAK] + EXPORT CAN1_IRQ0_DriverIRQHandler [WEAK] + EXPORT CAN1_IRQ1_DriverIRQHandler [WEAK] + EXPORT USB1_DriverIRQHandler [WEAK] + EXPORT USB1_NEEDCLK_DriverIRQHandler [WEAK] + EXPORT ETHERNET_DriverIRQHandler [WEAK] + EXPORT ETHERNET_PMT_DriverIRQHandler [WEAK] + EXPORT ETHERNET_MACLP_DriverIRQHandler [WEAK] + EXPORT EEPROM_DriverIRQHandler [WEAK] + EXPORT LCD_DriverIRQHandler [WEAK] + EXPORT SHA_DriverIRQHandler [WEAK] + EXPORT SMARTCARD0_DriverIRQHandler [WEAK] + EXPORT SMARTCARD1_DriverIRQHandler [WEAK] + +WDT_BOD_DriverIRQHandler +DMA0_DriverIRQHandler +GINT0_DriverIRQHandler +GINT1_DriverIRQHandler +PIN_INT0_DriverIRQHandler +PIN_INT1_DriverIRQHandler +PIN_INT2_DriverIRQHandler +PIN_INT3_DriverIRQHandler +UTICK0_DriverIRQHandler +MRT0_DriverIRQHandler +CTIMER0_DriverIRQHandler +CTIMER1_DriverIRQHandler +SCT0_DriverIRQHandler +CTIMER3_DriverIRQHandler +FLEXCOMM0_DriverIRQHandler +FLEXCOMM1_DriverIRQHandler +FLEXCOMM2_DriverIRQHandler +FLEXCOMM3_DriverIRQHandler +FLEXCOMM4_DriverIRQHandler +FLEXCOMM5_DriverIRQHandler +FLEXCOMM6_DriverIRQHandler +FLEXCOMM7_DriverIRQHandler +ADC0_SEQA_DriverIRQHandler +ADC0_SEQB_DriverIRQHandler +ADC0_THCMP_DriverIRQHandler +DMIC0_DriverIRQHandler +HWVAD0_DriverIRQHandler +USB0_NEEDCLK_DriverIRQHandler +USB0_DriverIRQHandler +RTC_DriverIRQHandler +Reserved46_DriverIRQHandler +Reserved47_DriverIRQHandler +PIN_INT4_DriverIRQHandler +PIN_INT5_DriverIRQHandler +PIN_INT6_DriverIRQHandler +PIN_INT7_DriverIRQHandler +CTIMER2_DriverIRQHandler +CTIMER4_DriverIRQHandler +RIT_DriverIRQHandler +SPIFI0_DriverIRQHandler +FLEXCOMM8_DriverIRQHandler +FLEXCOMM9_DriverIRQHandler +SDIO_DriverIRQHandler +CAN0_IRQ0_DriverIRQHandler +CAN0_IRQ1_DriverIRQHandler +CAN1_IRQ0_DriverIRQHandler +CAN1_IRQ1_DriverIRQHandler +USB1_DriverIRQHandler +USB1_NEEDCLK_DriverIRQHandler +ETHERNET_DriverIRQHandler +ETHERNET_PMT_DriverIRQHandler +ETHERNET_MACLP_DriverIRQHandler +EEPROM_DriverIRQHandler +LCD_DriverIRQHandler +SHA_DriverIRQHandler +SMARTCARD0_DriverIRQHandler +SMARTCARD1_DriverIRQHandler + + B . + + ENDP + + + ALIGN + + + END +
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_GCC_ARM/LPC54618J512.ld Fri Feb 16 16:09:33 2018 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,253 +0,0 @@
-/*
-** ###################################################################
-** Processors: LPC54618J512
-**
-** Compiler: GNU C Compiler
-** Reference manual: LPC54618 Series Reference Manual, Rev. 0 , 06/2017
-** Version: rev. 1.0, 2017-6-06
-** Build: b161214
-**
-** Abstract:
-** Linker file for the GNU C Compiler
-**
-** Copyright 2016 Freescale Semiconductor, Inc.
-** Copyright 2016-2017 NXP
-** Redistribution and use in source and binary forms, with or without modification,
-** are permitted provided that the following conditions are met:
-**
-** 1. Redistributions of source code must retain the above copyright notice, this list
-** of conditions and the following disclaimer.
-**
-** 2. Redistributions in binary form must reproduce the above copyright notice, this
-** list of conditions and the following disclaimer in the documentation and/or
-** other materials provided with the distribution.
-**
-** 3. Neither the name of the copyright holder nor the names of its
-** contributors may be used to endorse or promote products derived from this
-** software without specific prior written permission.
-**
-** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-**
-** http: www.nxp.com
-** mail: support@nxp.com
-**
-** ###################################################################
-*/
-
-/* Entry Point */
-ENTRY(Reset_Handler)
-
-__ram_vector_table__ = 1;
-
-__stack_size__ = 0x8000;
-__heap_size__ = 0xC000;
-
-HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
-STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800;
-M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x400 : 0x0;
-
-
-/* Specify the memory areas */
-MEMORY
-{
- m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000400
- m_text (RX) : ORIGIN = 0x00000400, LENGTH = 0x0007FC00
- m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00028000
- m_sramx (RW) : ORIGIN = 0x04000000, LENGTH = 0x00008000
- m_usb_sram (RW) : ORIGIN = 0x40100000, LENGTH = 0x00002000
-}
-
-/* Define output sections */
-SECTIONS
-{
- /* The startup code goes first into internal flash */
- .interrupts :
- {
- __VECTOR_TABLE = .;
- . = ALIGN(4);
- KEEP(*(.isr_vector)) /* Startup code */
- . = ALIGN(4);
- } > m_interrupts
-
- /* The program code and other data goes into internal flash */
- .text :
- {
- . = ALIGN(4);
- *(.text) /* .text sections (code) */
- *(.text*) /* .text* sections (code) */
- *(.rodata) /* .rodata sections (constants, strings, etc.) */
- *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
- *(.glue_7) /* glue arm to thumb code */
- *(.glue_7t) /* glue thumb to arm code */
- *(.eh_frame)
- KEEP (*(.init))
- KEEP (*(.fini))
- . = ALIGN(4);
- } > m_text
-
- .ARM.extab :
- {
- *(.ARM.extab* .gnu.linkonce.armextab.*)
- } > m_text
-
- .ARM :
- {
- __exidx_start = .;
- *(.ARM.exidx*)
- __exidx_end = .;
- } > m_text
-
- .ctors :
- {
- __CTOR_LIST__ = .;
- /* gcc uses crtbegin.o to find the start of
- the constructors, so we make sure it is
- first. Because this is a wildcard, it
- doesn't matter if the user does not
- actually link against crtbegin.o; the
- linker won't look for a file to match a
- wildcard. The wildcard also means that it
- doesn't matter which directory crtbegin.o
- is in. */
- KEEP (*crtbegin.o(.ctors))
- KEEP (*crtbegin?.o(.ctors))
- /* We don't want to include the .ctor section from
- from the crtend.o file until after the sorted ctors.
- The .ctor section from the crtend file contains the
- end of ctors marker and it must be last */
- KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
- KEEP (*(SORT(.ctors.*)))
- KEEP (*(.ctors))
- __CTOR_END__ = .;
- } > m_text
-
- .dtors :
- {
- __DTOR_LIST__ = .;
- KEEP (*crtbegin.o(.dtors))
- KEEP (*crtbegin?.o(.dtors))
- KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
- KEEP (*(SORT(.dtors.*)))
- KEEP (*(.dtors))
- __DTOR_END__ = .;
- } > m_text
-
- .preinit_array :
- {
- PROVIDE_HIDDEN (__preinit_array_start = .);
- KEEP (*(.preinit_array*))
- PROVIDE_HIDDEN (__preinit_array_end = .);
- } > m_text
-
- .init_array :
- {
- PROVIDE_HIDDEN (__init_array_start = .);
- KEEP (*(SORT(.init_array.*)))
- KEEP (*(.init_array*))
- PROVIDE_HIDDEN (__init_array_end = .);
- } > m_text
-
- .fini_array :
- {
- PROVIDE_HIDDEN (__fini_array_start = .);
- KEEP (*(SORT(.fini_array.*)))
- KEEP (*(.fini_array*))
- PROVIDE_HIDDEN (__fini_array_end = .);
- } > m_text
-
- __etext = .; /* define a global symbol at end of code */
- __DATA_ROM = .; /* Symbol is used by startup for data initialization */
-
- .interrupts_ram :
- {
- . = ALIGN(4);
- __VECTOR_RAM__ = .;
- __interrupts_ram_start__ = .; /* Create a global symbol at data start */
- *(.m_interrupts_ram) /* This is a user defined section */
- . += M_VECTOR_RAM_SIZE;
- . = ALIGN(4);
- __interrupts_ram_end__ = .; /* Define a global symbol at data end */
- } > m_data
-
- __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts);
- __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0;
-
- .data : AT(__DATA_ROM)
- {
- . = ALIGN(4);
- __DATA_RAM = .;
- __data_start__ = .; /* create a global symbol at data start */
- *(.ramfunc*) /* for functions in ram */
- *(.data) /* .data sections */
- *(.data*) /* .data* sections */
- KEEP(*(.jcr*))
- . = ALIGN(4);
- __data_end__ = .; /* define a global symbol at data end */
- } > m_data
-
- __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
- text_end = ORIGIN(m_text) + LENGTH(m_text);
- ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
-
- /* Uninitialized data section */
- .bss :
- {
- /* This is used by the startup in order to initialize the .bss section */
- . = ALIGN(4);
- __START_BSS = .;
- __bss_start__ = .;
- *(.bss)
- *(.bss*)
- *(COMMON)
- . = ALIGN(4);
- __bss_end__ = .;
- __END_BSS = .;
- } > m_data
-
- .heap :
- {
- . = ALIGN(8);
- __end__ = .;
- PROVIDE(end = .);
- __HeapBase = .;
- . += HEAP_SIZE;
- __HeapLimit = .;
- __heap_limit = .; /* Add for _sbrk */
- } > m_data
-
- .stack :
- {
- . = ALIGN(8);
- . += STACK_SIZE;
- } > m_data
-
- m_usb_bdt (NOLOAD) :
- {
- . = ALIGN(512);
- *(m_usb_bdt)
- } > m_usb_sram
-
- m_usb_global (NOLOAD) :
- {
- *(m_usb_global)
- } > m_usb_sram
-
- /* Initializes stack on the end of block */
- __StackTop = ORIGIN(m_data) + LENGTH(m_data);
- __StackLimit = __StackTop - STACK_SIZE;
- PROVIDE(__stack = __StackTop);
-
- .ARM.attributes 0 : { *(.ARM.attributes) }
-
- ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
-}
-
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_GCC_ARM/LPC54628J512.ld Tue Mar 20 16:56:18 2018 +0000
@@ -0,0 +1,253 @@
+/*
+** ###################################################################
+** Processors: LPC54628J512
+**
+** Compiler: GNU C Compiler
+** Reference manual: LPC54628 Series Reference Manual, Rev. 0 , 06/2017
+** Version: rev. 1.0, 2017-6-06
+** Build: b161214
+**
+** Abstract:
+** Linker file for the GNU C Compiler
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2017 NXP
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** 1. Redistributions of source code must retain the above copyright notice, this list
+** of conditions and the following disclaimer.
+**
+** 2. Redistributions in binary form must reproduce the above copyright notice, this
+** list of conditions and the following disclaimer in the documentation and/or
+** other materials provided with the distribution.
+**
+** 3. Neither the name of the copyright holder nor the names of its
+** contributors may be used to endorse or promote products derived from this
+** software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+
+/* Entry Point */
+ENTRY(Reset_Handler)
+
+__ram_vector_table__ = 1;
+
+__stack_size__ = 0x8000;
+__heap_size__ = 0xC000;
+
+HEAP_SIZE = DEFINED(__heap_size__) ? __heap_size__ : 0x0400;
+STACK_SIZE = DEFINED(__stack_size__) ? __stack_size__ : 0x0800;
+M_VECTOR_RAM_SIZE = DEFINED(__ram_vector_table__) ? 0x400 : 0x0;
+
+
+/* Specify the memory areas */
+MEMORY
+{
+ m_interrupts (RX) : ORIGIN = 0x00000000, LENGTH = 0x00000400
+ m_text (RX) : ORIGIN = 0x00000400, LENGTH = 0x0007FC00
+ m_data (RW) : ORIGIN = 0x20000000, LENGTH = 0x00028000
+ m_sramx (RW) : ORIGIN = 0x04000000, LENGTH = 0x00008000
+ m_usb_sram (RW) : ORIGIN = 0x40100000, LENGTH = 0x00002000
+}
+
+/* Define output sections */
+SECTIONS
+{
+ /* The startup code goes first into internal flash */
+ .interrupts :
+ {
+ __VECTOR_TABLE = .;
+ . = ALIGN(4);
+ KEEP(*(.isr_vector)) /* Startup code */
+ . = ALIGN(4);
+ } > m_interrupts
+
+ /* The program code and other data goes into internal flash */
+ .text :
+ {
+ . = ALIGN(4);
+ *(.text) /* .text sections (code) */
+ *(.text*) /* .text* sections (code) */
+ *(.rodata) /* .rodata sections (constants, strings, etc.) */
+ *(.rodata*) /* .rodata* sections (constants, strings, etc.) */
+ *(.glue_7) /* glue arm to thumb code */
+ *(.glue_7t) /* glue thumb to arm code */
+ *(.eh_frame)
+ KEEP (*(.init))
+ KEEP (*(.fini))
+ . = ALIGN(4);
+ } > m_text
+
+ .ARM.extab :
+ {
+ *(.ARM.extab* .gnu.linkonce.armextab.*)
+ } > m_text
+
+ .ARM :
+ {
+ __exidx_start = .;
+ *(.ARM.exidx*)
+ __exidx_end = .;
+ } > m_text
+
+ .ctors :
+ {
+ __CTOR_LIST__ = .;
+ /* gcc uses crtbegin.o to find the start of
+ the constructors, so we make sure it is
+ first. Because this is a wildcard, it
+ doesn't matter if the user does not
+ actually link against crtbegin.o; the
+ linker won't look for a file to match a
+ wildcard. The wildcard also means that it
+ doesn't matter which directory crtbegin.o
+ is in. */
+ KEEP (*crtbegin.o(.ctors))
+ KEEP (*crtbegin?.o(.ctors))
+ /* We don't want to include the .ctor section from
+ from the crtend.o file until after the sorted ctors.
+ The .ctor section from the crtend file contains the
+ end of ctors marker and it must be last */
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .ctors))
+ KEEP (*(SORT(.ctors.*)))
+ KEEP (*(.ctors))
+ __CTOR_END__ = .;
+ } > m_text
+
+ .dtors :
+ {
+ __DTOR_LIST__ = .;
+ KEEP (*crtbegin.o(.dtors))
+ KEEP (*crtbegin?.o(.dtors))
+ KEEP (*(EXCLUDE_FILE(*crtend?.o *crtend.o) .dtors))
+ KEEP (*(SORT(.dtors.*)))
+ KEEP (*(.dtors))
+ __DTOR_END__ = .;
+ } > m_text
+
+ .preinit_array :
+ {
+ PROVIDE_HIDDEN (__preinit_array_start = .);
+ KEEP (*(.preinit_array*))
+ PROVIDE_HIDDEN (__preinit_array_end = .);
+ } > m_text
+
+ .init_array :
+ {
+ PROVIDE_HIDDEN (__init_array_start = .);
+ KEEP (*(SORT(.init_array.*)))
+ KEEP (*(.init_array*))
+ PROVIDE_HIDDEN (__init_array_end = .);
+ } > m_text
+
+ .fini_array :
+ {
+ PROVIDE_HIDDEN (__fini_array_start = .);
+ KEEP (*(SORT(.fini_array.*)))
+ KEEP (*(.fini_array*))
+ PROVIDE_HIDDEN (__fini_array_end = .);
+ } > m_text
+
+ __etext = .; /* define a global symbol at end of code */
+ __DATA_ROM = .; /* Symbol is used by startup for data initialization */
+
+ .interrupts_ram :
+ {
+ . = ALIGN(4);
+ __VECTOR_RAM__ = .;
+ __interrupts_ram_start__ = .; /* Create a global symbol at data start */
+ *(.m_interrupts_ram) /* This is a user defined section */
+ . += M_VECTOR_RAM_SIZE;
+ . = ALIGN(4);
+ __interrupts_ram_end__ = .; /* Define a global symbol at data end */
+ } > m_data
+
+ __VECTOR_RAM = DEFINED(__ram_vector_table__) ? __VECTOR_RAM__ : ORIGIN(m_interrupts);
+ __RAM_VECTOR_TABLE_SIZE_BYTES = DEFINED(__ram_vector_table__) ? (__interrupts_ram_end__ - __interrupts_ram_start__) : 0x0;
+
+ .data : AT(__DATA_ROM)
+ {
+ . = ALIGN(4);
+ __DATA_RAM = .;
+ __data_start__ = .; /* create a global symbol at data start */
+ *(.ramfunc*) /* for functions in ram */
+ *(.data) /* .data sections */
+ *(.data*) /* .data* sections */
+ KEEP(*(.jcr*))
+ . = ALIGN(4);
+ __data_end__ = .; /* define a global symbol at data end */
+ } > m_data
+
+ __DATA_END = __DATA_ROM + (__data_end__ - __data_start__);
+ text_end = ORIGIN(m_text) + LENGTH(m_text);
+ ASSERT(__DATA_END <= text_end, "region m_text overflowed with text and data")
+
+ /* Uninitialized data section */
+ .bss :
+ {
+ /* This is used by the startup in order to initialize the .bss section */
+ . = ALIGN(4);
+ __START_BSS = .;
+ __bss_start__ = .;
+ *(.bss)
+ *(.bss*)
+ *(COMMON)
+ . = ALIGN(4);
+ __bss_end__ = .;
+ __END_BSS = .;
+ } > m_data
+
+ .heap :
+ {
+ . = ALIGN(8);
+ __end__ = .;
+ PROVIDE(end = .);
+ __HeapBase = .;
+ . += HEAP_SIZE;
+ __HeapLimit = .;
+ __heap_limit = .; /* Add for _sbrk */
+ } > m_data
+
+ .stack :
+ {
+ . = ALIGN(8);
+ . += STACK_SIZE;
+ } > m_data
+
+ m_usb_bdt (NOLOAD) :
+ {
+ . = ALIGN(512);
+ *(m_usb_bdt)
+ } > m_usb_sram
+
+ m_usb_global (NOLOAD) :
+ {
+ *(m_usb_global)
+ } > m_usb_sram
+
+ /* Initializes stack on the end of block */
+ __StackTop = ORIGIN(m_data) + LENGTH(m_data);
+ __StackLimit = __StackTop - STACK_SIZE;
+ PROVIDE(__stack = __StackTop);
+
+ .ARM.attributes 0 : { *(.ARM.attributes) }
+
+ ASSERT(__StackLimit >= __HeapLimit, "region m_data overflowed with stack and heap")
+}
+
Binary file targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_GCC_ARM/libpower.a has changed
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_GCC_ARM/startup_LPC54618.S Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,863 +0,0 @@ -/* ---------------------------------------------------------------------------------------*/ -/* @file: startup_LPC54618.S */ -/* @purpose: CMSIS Cortex-M4 Core Device Startup File */ -/* LPC54618 */ -/* @version: 1.0 */ -/* @date: 2017-6-6 */ -/* @build: b161214 */ -/* ---------------------------------------------------------------------------------------*/ -/* */ -/* Copyright 1997-2016 Freescale Semiconductor, Inc. */ -/* Copyright 2016-2017 NXP */ -/* Redistribution and use in source and binary forms, with or without modification, */ -/* are permitted provided that the following conditions are met: */ -/* */ -/* 1. Redistributions of source code must retain the above copyright notice, this list */ -/* of conditions and the following disclaimer. */ -/* */ -/* 2. Redistributions in binary form must reproduce the above copyright notice, this */ -/* list of conditions and the following disclaimer in the documentation and/or */ -/* other materials provided with the distribution. */ -/* */ -/* 3. Neither the name of the copyright holder nor the names of its */ -/* contributors may be used to endorse or promote products derived from this */ -/* software without specific prior written permission. */ -/* */ -/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND */ -/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED */ -/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */ -/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR */ -/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */ -/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; */ -/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON */ -/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ -/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS */ -/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -/*****************************************************************************/ -/* Version: GCC for ARM Embedded Processors */ -/*****************************************************************************/ - .syntax unified - .arch armv7-m - - .section .isr_vector, "a" - .align 2 - .globl __Vectors -__Vectors: - .long __StackTop /* Top of Stack */ - .long Reset_Handler /* Reset Handler */ - .long NMI_Handler /* NMI Handler */ - .long HardFault_Handler /* Hard Fault Handler */ - .long MemManage_Handler /* MPU Fault Handler */ - .long BusFault_Handler /* Bus Fault Handler */ - .long UsageFault_Handler /* Usage Fault Handler */ - .long 0 /* Reserved */ - .long 0xFFFFFFFF /* ECRP */ - .long 0 /* Reserved */ - .long 0 /* Reserved */ - .long SVC_Handler /* SVCall Handler */ - .long DebugMon_Handler /* Debug Monitor Handler */ - .long 0 - .long PendSV_Handler /* PendSV Handler */ - .long SysTick_Handler /* SysTick Handler */ - - /* External Interrupts */ - .long WDT_BOD_IRQHandler /* Windowed watchdog timer, Brownout detect */ - .long DMA0_IRQHandler /* DMA controller */ - .long GINT0_IRQHandler /* GPIO group 0 */ - .long GINT1_IRQHandler /* GPIO group 1 */ - .long PIN_INT0_IRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */ - .long PIN_INT1_IRQHandler /* Pin interrupt 1 or pattern match engine slice 1 */ - .long PIN_INT2_IRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */ - .long PIN_INT3_IRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */ - .long UTICK0_IRQHandler /* Micro-tick Timer */ - .long MRT0_IRQHandler /* Multi-rate timer */ - .long CTIMER0_IRQHandler /* Standard counter/timer CTIMER0 */ - .long CTIMER1_IRQHandler /* Standard counter/timer CTIMER1 */ - .long SCT0_IRQHandler /* SCTimer/PWM */ - .long CTIMER3_IRQHandler /* Standard counter/timer CTIMER3 */ - .long FLEXCOMM0_IRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) */ - .long FLEXCOMM1_IRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) */ - .long FLEXCOMM2_IRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) */ - .long FLEXCOMM3_IRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) */ - .long FLEXCOMM4_IRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) */ - .long FLEXCOMM5_IRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM) */ - .long FLEXCOMM6_IRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM) */ - .long FLEXCOMM7_IRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM) */ - .long ADC0_SEQA_IRQHandler /* ADC0 sequence A completion. */ - .long ADC0_SEQB_IRQHandler /* ADC0 sequence B completion. */ - .long ADC0_THCMP_IRQHandler /* ADC0 threshold compare and error. */ - .long DMIC0_IRQHandler /* Digital microphone and DMIC subsystem */ - .long HWVAD0_IRQHandler /* Hardware Voice Activity Detector */ - .long USB0_NEEDCLK_IRQHandler /* USB Activity Wake-up Interrupt */ - .long USB0_IRQHandler /* USB device */ - .long RTC_IRQHandler /* RTC alarm and wake-up interrupts */ - .long 0 /* Reserved interrupt */ - .long 0 /* Reserved interrupt */ - .long PIN_INT4_IRQHandler /* Pin interrupt 4 or pattern match engine slice 4 int */ - .long PIN_INT5_IRQHandler /* Pin interrupt 5 or pattern match engine slice 5 int */ - .long PIN_INT6_IRQHandler /* Pin interrupt 6 or pattern match engine slice 6 int */ - .long PIN_INT7_IRQHandler /* Pin interrupt 7 or pattern match engine slice 7 int */ - .long CTIMER2_IRQHandler /* Standard counter/timer CTIMER2 */ - .long CTIMER4_IRQHandler /* Standard counter/timer CTIMER4 */ - .long RIT_IRQHandler /* Repetitive Interrupt Timer */ - .long SPIFI0_IRQHandler /* SPI flash interface */ - .long FLEXCOMM8_IRQHandler /* Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM) */ - .long FLEXCOMM9_IRQHandler /* Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM) */ - .long SDIO_IRQHandler /* SD/MMC */ - .long CAN0_IRQ0_IRQHandler /* CAN0 interrupt0 */ - .long CAN0_IRQ1_IRQHandler /* CAN0 interrupt1 */ - .long CAN1_IRQ0_IRQHandler /* CAN1 interrupt0 */ - .long CAN1_IRQ1_IRQHandler /* CAN1 interrupt1 */ - .long USB1_IRQHandler /* USB1 interrupt */ - .long USB1_NEEDCLK_IRQHandler /* USB1 activity */ - .long ETHERNET_IRQHandler /* Ethernet */ - .long ETHERNET_PMT_IRQHandler /* Ethernet power management interrupt */ - .long ETHERNET_MACLP_IRQHandler /* Ethernet MAC interrupt */ - .long EEPROM_IRQHandler /* EEPROM interrupt */ - .long LCD_IRQHandler /* LCD interrupt */ - .long SHA_IRQHandler /* SHA interrupt */ - .long SMARTCARD0_IRQHandler /* Smart card 0 interrupt */ - .long SMARTCARD1_IRQHandler /* Smart card 1 interrupt */ - .size __Vectors, . - __Vectors - - - - .text - .thumb - -/* Reset Handler */ - - .thumb_func - .align 2 - .globl Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function - -Reset_Handler: -#ifndef __NO_SYSTEM_INIT - ldr r0,=SystemInit - blx r0 -#endif - - /* Loop to copy data from read only memory to RAM. The ranges - * of copy from/to are specified by following symbols evaluated in - * linker script. - * __etext: End of code section, i.e., begin of data sections to copy from. - * __data_start__/__data_end__: RAM address range that data should be - * copied to. Both must be aligned to 4 bytes boundary. */ - - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - -#if 1 -/* Here are two copies of loop implemenations. First one favors code size - * and the second one favors performance. Default uses the first one. - * Change to "#if 0" to use the second one */ -.LC0: - cmp r2, r3 - ittt lt - ldrlt r0, [r1], #4 - strlt r0, [r2], #4 - blt .LC0 -#else - subs r3, r2 - ble .LC1 -.LC0: - subs r3, #4 - ldr r0, [r1, r3] - str r0, [r2, r3] - bgt .LC0 -.LC1: -#endif - -#ifdef __STARTUP_CLEAR_BSS -/* This part of work usually is done in C library startup code. Otherwise, - * define this macro to enable it in this startup. - * - * Loop to zero out BSS section, which uses following symbols - * in linker script: - * __bss_start__: start of BSS section. Must align to 4 - * __bss_end__: end of BSS section. Must align to 4 - */ - ldr r1, =__bss_start__ - ldr r2, =__bss_end__ - - movs r0, 0 -.LC2: - cmp r1, r2 - itt lt - strlt r0, [r1], #4 - blt .LC2 -#endif /* __STARTUP_CLEAR_BSS */ - -#ifndef __START -#define __START _start -#endif -#ifndef __ATOLLIC__ - ldr r0,=__START - blx r0 -#else - ldr r0,=__libc_init_array - blx r0 - ldr r0,=main - bx r0 -#endif - - .pool - .size Reset_Handler, . - Reset_Handler - - .align 1 - .thumb_func - .weak DefaultISR - .type DefaultISR, %function -DefaultISR: - b DefaultISR - .size DefaultISR, . - DefaultISR - - .align 1 - .thumb_func - .weak NMI_Handler - .type NMI_Handler, %function -NMI_Handler: - ldr r0,=NMI_Handler - bx r0 - .size NMI_Handler, . - NMI_Handler - - .align 1 - .thumb_func - .weak HardFault_Handler - .type HardFault_Handler, %function -HardFault_Handler: - ldr r0,=HardFault_Handler - bx r0 - .size HardFault_Handler, . - HardFault_Handler - - .align 1 - .thumb_func - .weak MemManage_Handler - .type MemManage_Handler, %function -MemManage_Handler: - ldr r0,=MemManage_Handler - bx r0 - .size MemManage_Handler, . - MemManage_Handler - - .align 1 - .thumb_func - .weak BusFault_Handler - .type BusFault_Handler, %function -BusFault_Handler: - ldr r0,=BusFault_Handler - bx r0 - .size BusFault_Handler, . - BusFault_Handler - - .align 1 - .thumb_func - .weak UsageFault_Handler - .type UsageFault_Handler, %function -UsageFault_Handler: - ldr r0,=UsageFault_Handler - bx r0 - .size UsageFault_Handler, . - UsageFault_Handler - - .align 1 - .thumb_func - .weak SVC_Handler - .type SVC_Handler, %function -SVC_Handler: - ldr r0,=SVC_Handler - bx r0 - .size SVC_Handler, . - SVC_Handler - - .align 1 - .thumb_func - .weak DebugMon_Handler - .type DebugMon_Handler, %function -DebugMon_Handler: - ldr r0,=DebugMon_Handler - bx r0 - .size DebugMon_Handler, . - DebugMon_Handler - - .align 1 - .thumb_func - .weak PendSV_Handler - .type PendSV_Handler, %function -PendSV_Handler: - ldr r0,=PendSV_Handler - bx r0 - .size PendSV_Handler, . - PendSV_Handler - - .align 1 - .thumb_func - .weak SysTick_Handler - .type SysTick_Handler, %function -SysTick_Handler: - ldr r0,=SysTick_Handler - bx r0 - .size SysTick_Handler, . - SysTick_Handler - - .align 1 - .thumb_func - .weak WDT_BOD_IRQHandler - .type WDT_BOD_IRQHandler, %function -WDT_BOD_IRQHandler: - ldr r0,=WDT_BOD_DriverIRQHandler - bx r0 - .size WDT_BOD_IRQHandler, . - WDT_BOD_IRQHandler - - .align 1 - .thumb_func - .weak DMA0_IRQHandler - .type DMA0_IRQHandler, %function -DMA0_IRQHandler: - ldr r0,=DMA0_DriverIRQHandler - bx r0 - .size DMA0_IRQHandler, . - DMA0_IRQHandler - - .align 1 - .thumb_func - .weak GINT0_IRQHandler - .type GINT0_IRQHandler, %function -GINT0_IRQHandler: - ldr r0,=GINT0_DriverIRQHandler - bx r0 - .size GINT0_IRQHandler, . - GINT0_IRQHandler - - .align 1 - .thumb_func - .weak GINT1_IRQHandler - .type GINT1_IRQHandler, %function -GINT1_IRQHandler: - ldr r0,=GINT1_DriverIRQHandler - bx r0 - .size GINT1_IRQHandler, . - GINT1_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT0_IRQHandler - .type PIN_INT0_IRQHandler, %function -PIN_INT0_IRQHandler: - ldr r0,=PIN_INT0_DriverIRQHandler - bx r0 - .size PIN_INT0_IRQHandler, . - PIN_INT0_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT1_IRQHandler - .type PIN_INT1_IRQHandler, %function -PIN_INT1_IRQHandler: - ldr r0,=PIN_INT1_DriverIRQHandler - bx r0 - .size PIN_INT1_IRQHandler, . - PIN_INT1_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT2_IRQHandler - .type PIN_INT2_IRQHandler, %function -PIN_INT2_IRQHandler: - ldr r0,=PIN_INT2_DriverIRQHandler - bx r0 - .size PIN_INT2_IRQHandler, . - PIN_INT2_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT3_IRQHandler - .type PIN_INT3_IRQHandler, %function -PIN_INT3_IRQHandler: - ldr r0,=PIN_INT3_DriverIRQHandler - bx r0 - .size PIN_INT3_IRQHandler, . - PIN_INT3_IRQHandler - - .align 1 - .thumb_func - .weak UTICK0_IRQHandler - .type UTICK0_IRQHandler, %function -UTICK0_IRQHandler: - ldr r0,=UTICK0_DriverIRQHandler - bx r0 - .size UTICK0_IRQHandler, . - UTICK0_IRQHandler - - .align 1 - .thumb_func - .weak MRT0_IRQHandler - .type MRT0_IRQHandler, %function -MRT0_IRQHandler: - ldr r0,=MRT0_DriverIRQHandler - bx r0 - .size MRT0_IRQHandler, . - MRT0_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER0_IRQHandler - .type CTIMER0_IRQHandler, %function -CTIMER0_IRQHandler: - ldr r0,=CTIMER0_DriverIRQHandler - bx r0 - .size CTIMER0_IRQHandler, . - CTIMER0_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER1_IRQHandler - .type CTIMER1_IRQHandler, %function -CTIMER1_IRQHandler: - ldr r0,=CTIMER1_DriverIRQHandler - bx r0 - .size CTIMER1_IRQHandler, . - CTIMER1_IRQHandler - - .align 1 - .thumb_func - .weak SCT0_IRQHandler - .type SCT0_IRQHandler, %function -SCT0_IRQHandler: - ldr r0,=SCT0_DriverIRQHandler - bx r0 - .size SCT0_IRQHandler, . - SCT0_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER3_IRQHandler - .type CTIMER3_IRQHandler, %function -CTIMER3_IRQHandler: - ldr r0,=CTIMER3_DriverIRQHandler - bx r0 - .size CTIMER3_IRQHandler, . - CTIMER3_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM0_IRQHandler - .type FLEXCOMM0_IRQHandler, %function -FLEXCOMM0_IRQHandler: - ldr r0,=FLEXCOMM0_DriverIRQHandler - bx r0 - .size FLEXCOMM0_IRQHandler, . - FLEXCOMM0_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM1_IRQHandler - .type FLEXCOMM1_IRQHandler, %function -FLEXCOMM1_IRQHandler: - ldr r0,=FLEXCOMM1_DriverIRQHandler - bx r0 - .size FLEXCOMM1_IRQHandler, . - FLEXCOMM1_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM2_IRQHandler - .type FLEXCOMM2_IRQHandler, %function -FLEXCOMM2_IRQHandler: - ldr r0,=FLEXCOMM2_DriverIRQHandler - bx r0 - .size FLEXCOMM2_IRQHandler, . - FLEXCOMM2_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM3_IRQHandler - .type FLEXCOMM3_IRQHandler, %function -FLEXCOMM3_IRQHandler: - ldr r0,=FLEXCOMM3_DriverIRQHandler - bx r0 - .size FLEXCOMM3_IRQHandler, . - FLEXCOMM3_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM4_IRQHandler - .type FLEXCOMM4_IRQHandler, %function -FLEXCOMM4_IRQHandler: - ldr r0,=FLEXCOMM4_DriverIRQHandler - bx r0 - .size FLEXCOMM4_IRQHandler, . - FLEXCOMM4_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM5_IRQHandler - .type FLEXCOMM5_IRQHandler, %function -FLEXCOMM5_IRQHandler: - ldr r0,=FLEXCOMM5_DriverIRQHandler - bx r0 - .size FLEXCOMM5_IRQHandler, . - FLEXCOMM5_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM6_IRQHandler - .type FLEXCOMM6_IRQHandler, %function -FLEXCOMM6_IRQHandler: - ldr r0,=FLEXCOMM6_DriverIRQHandler - bx r0 - .size FLEXCOMM6_IRQHandler, . - FLEXCOMM6_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM7_IRQHandler - .type FLEXCOMM7_IRQHandler, %function -FLEXCOMM7_IRQHandler: - ldr r0,=FLEXCOMM7_DriverIRQHandler - bx r0 - .size FLEXCOMM7_IRQHandler, . - FLEXCOMM7_IRQHandler - - .align 1 - .thumb_func - .weak ADC0_SEQA_IRQHandler - .type ADC0_SEQA_IRQHandler, %function -ADC0_SEQA_IRQHandler: - ldr r0,=ADC0_SEQA_DriverIRQHandler - bx r0 - .size ADC0_SEQA_IRQHandler, . - ADC0_SEQA_IRQHandler - - .align 1 - .thumb_func - .weak ADC0_SEQB_IRQHandler - .type ADC0_SEQB_IRQHandler, %function -ADC0_SEQB_IRQHandler: - ldr r0,=ADC0_SEQB_DriverIRQHandler - bx r0 - .size ADC0_SEQB_IRQHandler, . - ADC0_SEQB_IRQHandler - - .align 1 - .thumb_func - .weak ADC0_THCMP_IRQHandler - .type ADC0_THCMP_IRQHandler, %function -ADC0_THCMP_IRQHandler: - ldr r0,=ADC0_THCMP_DriverIRQHandler - bx r0 - .size ADC0_THCMP_IRQHandler, . - ADC0_THCMP_IRQHandler - - .align 1 - .thumb_func - .weak DMIC0_IRQHandler - .type DMIC0_IRQHandler, %function -DMIC0_IRQHandler: - ldr r0,=DMIC0_DriverIRQHandler - bx r0 - .size DMIC0_IRQHandler, . - DMIC0_IRQHandler - - .align 1 - .thumb_func - .weak HWVAD0_IRQHandler - .type HWVAD0_IRQHandler, %function -HWVAD0_IRQHandler: - ldr r0,=HWVAD0_DriverIRQHandler - bx r0 - .size HWVAD0_IRQHandler, . - HWVAD0_IRQHandler - - .align 1 - .thumb_func - .weak USB0_NEEDCLK_IRQHandler - .type USB0_NEEDCLK_IRQHandler, %function -USB0_NEEDCLK_IRQHandler: - ldr r0,=USB0_NEEDCLK_DriverIRQHandler - bx r0 - .size USB0_NEEDCLK_IRQHandler, . - USB0_NEEDCLK_IRQHandler - - .align 1 - .thumb_func - .weak USB0_IRQHandler - .type USB0_IRQHandler, %function -USB0_IRQHandler: - ldr r0,=USB0_DriverIRQHandler - bx r0 - .size USB0_IRQHandler, . - USB0_IRQHandler - - .align 1 - .thumb_func - .weak RTC_IRQHandler - .type RTC_IRQHandler, %function -RTC_IRQHandler: - ldr r0,=RTC_DriverIRQHandler - bx r0 - .size RTC_IRQHandler, . - RTC_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT4_IRQHandler - .type PIN_INT4_IRQHandler, %function -PIN_INT4_IRQHandler: - ldr r0,=PIN_INT4_DriverIRQHandler - bx r0 - .size PIN_INT4_IRQHandler, . - PIN_INT4_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT5_IRQHandler - .type PIN_INT5_IRQHandler, %function -PIN_INT5_IRQHandler: - ldr r0,=PIN_INT5_DriverIRQHandler - bx r0 - .size PIN_INT5_IRQHandler, . - PIN_INT5_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT6_IRQHandler - .type PIN_INT6_IRQHandler, %function -PIN_INT6_IRQHandler: - ldr r0,=PIN_INT6_DriverIRQHandler - bx r0 - .size PIN_INT6_IRQHandler, . - PIN_INT6_IRQHandler - - .align 1 - .thumb_func - .weak PIN_INT7_IRQHandler - .type PIN_INT7_IRQHandler, %function -PIN_INT7_IRQHandler: - ldr r0,=PIN_INT7_DriverIRQHandler - bx r0 - .size PIN_INT7_IRQHandler, . - PIN_INT7_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER2_IRQHandler - .type CTIMER2_IRQHandler, %function -CTIMER2_IRQHandler: - ldr r0,=CTIMER2_DriverIRQHandler - bx r0 - .size CTIMER2_IRQHandler, . - CTIMER2_IRQHandler - - .align 1 - .thumb_func - .weak CTIMER4_IRQHandler - .type CTIMER4_IRQHandler, %function -CTIMER4_IRQHandler: - ldr r0,=CTIMER4_DriverIRQHandler - bx r0 - .size CTIMER4_IRQHandler, . - CTIMER4_IRQHandler - - .align 1 - .thumb_func - .weak RIT_IRQHandler - .type RIT_IRQHandler, %function -RIT_IRQHandler: - ldr r0,=RIT_DriverIRQHandler - bx r0 - .size RIT_IRQHandler, . - RIT_IRQHandler - - .align 1 - .thumb_func - .weak SPIFI0_IRQHandler - .type SPIFI0_IRQHandler, %function -SPIFI0_IRQHandler: - ldr r0,=SPIFI0_DriverIRQHandler - bx r0 - .size SPIFI0_IRQHandler, . - SPIFI0_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM8_IRQHandler - .type FLEXCOMM8_IRQHandler, %function -FLEXCOMM8_IRQHandler: - ldr r0,=FLEXCOMM8_DriverIRQHandler - bx r0 - .size FLEXCOMM8_IRQHandler, . - FLEXCOMM8_IRQHandler - - .align 1 - .thumb_func - .weak FLEXCOMM9_IRQHandler - .type FLEXCOMM9_IRQHandler, %function -FLEXCOMM9_IRQHandler: - ldr r0,=FLEXCOMM9_DriverIRQHandler - bx r0 - .size FLEXCOMM9_IRQHandler, . - FLEXCOMM9_IRQHandler - - .align 1 - .thumb_func - .weak SDIO_IRQHandler - .type SDIO_IRQHandler, %function -SDIO_IRQHandler: - ldr r0,=SDIO_DriverIRQHandler - bx r0 - .size SDIO_IRQHandler, . - SDIO_IRQHandler - - .align 1 - .thumb_func - .weak CAN0_IRQ0_IRQHandler - .type CAN0_IRQ0_IRQHandler, %function -CAN0_IRQ0_IRQHandler: - ldr r0,=CAN0_IRQ0_DriverIRQHandler - bx r0 - .size CAN0_IRQ0_IRQHandler, . - CAN0_IRQ0_IRQHandler - - .align 1 - .thumb_func - .weak CAN0_IRQ1_IRQHandler - .type CAN0_IRQ1_IRQHandler, %function -CAN0_IRQ1_IRQHandler: - ldr r0,=CAN0_IRQ1_DriverIRQHandler - bx r0 - .size CAN0_IRQ1_IRQHandler, . - CAN0_IRQ1_IRQHandler - - .align 1 - .thumb_func - .weak CAN1_IRQ0_IRQHandler - .type CAN1_IRQ0_IRQHandler, %function -CAN1_IRQ0_IRQHandler: - ldr r0,=CAN1_IRQ0_DriverIRQHandler - bx r0 - .size CAN1_IRQ0_IRQHandler, . - CAN1_IRQ0_IRQHandler - - .align 1 - .thumb_func - .weak CAN1_IRQ1_IRQHandler - .type CAN1_IRQ1_IRQHandler, %function -CAN1_IRQ1_IRQHandler: - ldr r0,=CAN1_IRQ1_DriverIRQHandler - bx r0 - .size CAN1_IRQ1_IRQHandler, . - CAN1_IRQ1_IRQHandler - - .align 1 - .thumb_func - .weak USB1_IRQHandler - .type USB1_IRQHandler, %function -USB1_IRQHandler: - ldr r0,=USB1_DriverIRQHandler - bx r0 - .size USB1_IRQHandler, . - USB1_IRQHandler - - .align 1 - .thumb_func - .weak USB1_NEEDCLK_IRQHandler - .type USB1_NEEDCLK_IRQHandler, %function -USB1_NEEDCLK_IRQHandler: - ldr r0,=USB1_NEEDCLK_DriverIRQHandler - bx r0 - .size USB1_NEEDCLK_IRQHandler, . - USB1_NEEDCLK_IRQHandler - - .align 1 - .thumb_func - .weak ETHERNET_IRQHandler - .type ETHERNET_IRQHandler, %function -ETHERNET_IRQHandler: - ldr r0,=ETHERNET_DriverIRQHandler - bx r0 - .size ETHERNET_IRQHandler, . - ETHERNET_IRQHandler - - .align 1 - .thumb_func - .weak ETHERNET_PMT_IRQHandler - .type ETHERNET_PMT_IRQHandler, %function -ETHERNET_PMT_IRQHandler: - ldr r0,=ETHERNET_PMT_DriverIRQHandler - bx r0 - .size ETHERNET_PMT_IRQHandler, . - ETHERNET_PMT_IRQHandler - - .align 1 - .thumb_func - .weak ETHERNET_MACLP_IRQHandler - .type ETHERNET_MACLP_IRQHandler, %function -ETHERNET_MACLP_IRQHandler: - ldr r0,=ETHERNET_MACLP_DriverIRQHandler - bx r0 - .size ETHERNET_MACLP_IRQHandler, . - ETHERNET_MACLP_IRQHandler - - .align 1 - .thumb_func - .weak EEPROM_IRQHandler - .type EEPROM_IRQHandler, %function -EEPROM_IRQHandler: - ldr r0,=EEPROM_DriverIRQHandler - bx r0 - .size EEPROM_IRQHandler, . - EEPROM_IRQHandler - - .align 1 - .thumb_func - .weak LCD_IRQHandler - .type LCD_IRQHandler, %function -LCD_IRQHandler: - ldr r0,=LCD_DriverIRQHandler - bx r0 - .size LCD_IRQHandler, . - LCD_IRQHandler - - .align 1 - .thumb_func - .weak SHA_IRQHandler - .type SHA_IRQHandler, %function -SHA_IRQHandler: - ldr r0,=SHA_DriverIRQHandler - bx r0 - .size SHA_IRQHandler, . - SHA_IRQHandler - - .align 1 - .thumb_func - .weak SMARTCARD0_IRQHandler - .type SMARTCARD0_IRQHandler, %function -SMARTCARD0_IRQHandler: - ldr r0,=SMARTCARD0_DriverIRQHandler - bx r0 - .size SMARTCARD0_IRQHandler, . - SMARTCARD0_IRQHandler - - .align 1 - .thumb_func - .weak SMARTCARD1_IRQHandler - .type SMARTCARD1_IRQHandler, %function -SMARTCARD1_IRQHandler: - ldr r0,=SMARTCARD1_DriverIRQHandler - bx r0 - .size SMARTCARD1_IRQHandler, . - SMARTCARD1_IRQHandler - - -/* Macro to define default handlers. Default handler - * will be weak symbol and just dead loops. They can be - * overwritten by other handlers */ - - .macro def_irq_handler handler_name - .weak \handler_name - .set \handler_name, DefaultISR - .endm - -/* Exception Handlers */ - def_irq_handler WDT_BOD_DriverIRQHandler /* Windowed watchdog timer, Brownout detect */ - def_irq_handler DMA0_DriverIRQHandler /* DMA controller */ - def_irq_handler GINT0_DriverIRQHandler /* GPIO group 0 */ - def_irq_handler GINT1_DriverIRQHandler /* GPIO group 1 */ - def_irq_handler PIN_INT0_DriverIRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */ - def_irq_handler PIN_INT1_DriverIRQHandler /* Pin interrupt 1or pattern match engine slice 1 */ - def_irq_handler PIN_INT2_DriverIRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */ - def_irq_handler PIN_INT3_DriverIRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */ - def_irq_handler UTICK0_DriverIRQHandler /* Micro-tick Timer */ - def_irq_handler MRT0_DriverIRQHandler /* Multi-rate timer */ - def_irq_handler CTIMER0_DriverIRQHandler /* Standard counter/timer CTIMER0 */ - def_irq_handler CTIMER1_DriverIRQHandler /* Standard counter/timer CTIMER1 */ - def_irq_handler SCT0_DriverIRQHandler /* SCTimer/PWM */ - def_irq_handler CTIMER3_DriverIRQHandler /* Standard counter/timer CTIMER3 */ - def_irq_handler FLEXCOMM0_DriverIRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) */ - def_irq_handler FLEXCOMM1_DriverIRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) */ - def_irq_handler FLEXCOMM2_DriverIRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) */ - def_irq_handler FLEXCOMM3_DriverIRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) */ - def_irq_handler FLEXCOMM4_DriverIRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) */ - def_irq_handler FLEXCOMM5_DriverIRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM) */ - def_irq_handler FLEXCOMM6_DriverIRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM) */ - def_irq_handler FLEXCOMM7_DriverIRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM) */ - def_irq_handler ADC0_SEQA_DriverIRQHandler /* ADC0 sequence A completion. */ - def_irq_handler ADC0_SEQB_DriverIRQHandler /* ADC0 sequence B completion. */ - def_irq_handler ADC0_THCMP_DriverIRQHandler /* ADC0 threshold compare and error. */ - def_irq_handler DMIC0_DriverIRQHandler /* Digital microphone and DMIC subsystem */ - def_irq_handler HWVAD0_DriverIRQHandler /* Hardware Voice Activity Detector */ - def_irq_handler USB0_NEEDCLK_DriverIRQHandler /* USB Activity Wake-up Interrupt */ - def_irq_handler USB0_DriverIRQHandler /* USB device */ - def_irq_handler RTC_DriverIRQHandler /* RTC alarm and wake-up interrupts */ - def_irq_handler Reserved46_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler Reserved47_DriverIRQHandler /* Reserved interrupt */ - def_irq_handler PIN_INT4_DriverIRQHandler /* Pin interrupt 4 or pattern match engine slice 4 int */ - def_irq_handler PIN_INT5_DriverIRQHandler /* Pin interrupt 5 or pattern match engine slice 5 int */ - def_irq_handler PIN_INT6_DriverIRQHandler /* Pin interrupt 6 or pattern match engine slice 6 int */ - def_irq_handler PIN_INT7_DriverIRQHandler /* Pin interrupt 7 or pattern match engine slice 7 int */ - def_irq_handler CTIMER2_DriverIRQHandler /* Standard counter/timer CTIMER2 */ - def_irq_handler CTIMER4_DriverIRQHandler /* Standard counter/timer CTIMER4 */ - def_irq_handler RIT_DriverIRQHandler /* Repetitive Interrupt Timer */ - def_irq_handler SPIFI0_DriverIRQHandler /* SPI flash interface */ - def_irq_handler FLEXCOMM8_DriverIRQHandler /* Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM) */ - def_irq_handler FLEXCOMM9_DriverIRQHandler /* Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM) */ - def_irq_handler SDIO_DriverIRQHandler /* SD/MMC */ - def_irq_handler CAN0_IRQ0_DriverIRQHandler /* CAN0 interrupt0 */ - def_irq_handler CAN0_IRQ1_DriverIRQHandler /* CAN0 interrupt1 */ - def_irq_handler CAN1_IRQ0_DriverIRQHandler /* CAN1 interrupt0 */ - def_irq_handler CAN1_IRQ1_DriverIRQHandler /* CAN1 interrupt1 */ - def_irq_handler USB1_DriverIRQHandler /* USB1 interrupt */ - def_irq_handler USB1_NEEDCLK_DriverIRQHandler /* USB1 activity */ - def_irq_handler ETHERNET_DriverIRQHandler /* Ethernet */ - def_irq_handler ETHERNET_PMT_DriverIRQHandler /* Ethernet power management interrupt */ - def_irq_handler ETHERNET_MACLP_DriverIRQHandler /* Ethernet MAC interrupt */ - def_irq_handler EEPROM_DriverIRQHandler /* EEPROM interrupt */ - def_irq_handler LCD_DriverIRQHandler /* LCD interrupt */ - def_irq_handler SHA_DriverIRQHandler /* SHA interrupt */ - def_irq_handler SMARTCARD0_DriverIRQHandler /* Smart card 0 interrupt */ - def_irq_handler SMARTCARD1_DriverIRQHandler /* Smart card 1 interrupt */ - - .end
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_GCC_ARM/startup_LPC54628.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,863 @@ +/* ---------------------------------------------------------------------------------------*/ +/* @file: startup_LPC54628.S */ +/* @purpose: CMSIS Cortex-M4 Core Device Startup File */ +/* LPC54628 */ +/* @version: 1.0 */ +/* @date: 2017-6-6 */ +/* @build: b161214 */ +/* ---------------------------------------------------------------------------------------*/ +/* */ +/* Copyright 1997-2016 Freescale Semiconductor, Inc. */ +/* Copyright 2016-2017 NXP */ +/* Redistribution and use in source and binary forms, with or without modification, */ +/* are permitted provided that the following conditions are met: */ +/* */ +/* 1. Redistributions of source code must retain the above copyright notice, this list */ +/* of conditions and the following disclaimer. */ +/* */ +/* 2. Redistributions in binary form must reproduce the above copyright notice, this */ +/* list of conditions and the following disclaimer in the documentation and/or */ +/* other materials provided with the distribution. */ +/* */ +/* 3. Neither the name of the copyright holder nor the names of its */ +/* contributors may be used to endorse or promote products derived from this */ +/* software without specific prior written permission. */ +/* */ +/* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND */ +/* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED */ +/* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */ +/* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR */ +/* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */ +/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; */ +/* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON */ +/* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */ +/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS */ +/* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ +/*****************************************************************************/ +/* Version: GCC for ARM Embedded Processors */ +/*****************************************************************************/ + .syntax unified + .arch armv7-m + + .section .isr_vector, "a" + .align 2 + .globl __Vectors +__Vectors: + .long __StackTop /* Top of Stack */ + .long Reset_Handler /* Reset Handler */ + .long NMI_Handler /* NMI Handler */ + .long HardFault_Handler /* Hard Fault Handler */ + .long MemManage_Handler /* MPU Fault Handler */ + .long BusFault_Handler /* Bus Fault Handler */ + .long UsageFault_Handler /* Usage Fault Handler */ + .long 0 /* Reserved */ + .long 0xFFFFFFFF /* ECRP */ + .long 0 /* Reserved */ + .long 0 /* Reserved */ + .long SVC_Handler /* SVCall Handler */ + .long DebugMon_Handler /* Debug Monitor Handler */ + .long 0 + .long PendSV_Handler /* PendSV Handler */ + .long SysTick_Handler /* SysTick Handler */ + + /* External Interrupts */ + .long WDT_BOD_IRQHandler /* Windowed watchdog timer, Brownout detect */ + .long DMA0_IRQHandler /* DMA controller */ + .long GINT0_IRQHandler /* GPIO group 0 */ + .long GINT1_IRQHandler /* GPIO group 1 */ + .long PIN_INT0_IRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */ + .long PIN_INT1_IRQHandler /* Pin interrupt 1 or pattern match engine slice 1 */ + .long PIN_INT2_IRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */ + .long PIN_INT3_IRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */ + .long UTICK0_IRQHandler /* Micro-tick Timer */ + .long MRT0_IRQHandler /* Multi-rate timer */ + .long CTIMER0_IRQHandler /* Standard counter/timer CTIMER0 */ + .long CTIMER1_IRQHandler /* Standard counter/timer CTIMER1 */ + .long SCT0_IRQHandler /* SCTimer/PWM */ + .long CTIMER3_IRQHandler /* Standard counter/timer CTIMER3 */ + .long FLEXCOMM0_IRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) */ + .long FLEXCOMM1_IRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) */ + .long FLEXCOMM2_IRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) */ + .long FLEXCOMM3_IRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) */ + .long FLEXCOMM4_IRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) */ + .long FLEXCOMM5_IRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM) */ + .long FLEXCOMM6_IRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM) */ + .long FLEXCOMM7_IRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM) */ + .long ADC0_SEQA_IRQHandler /* ADC0 sequence A completion. */ + .long ADC0_SEQB_IRQHandler /* ADC0 sequence B completion. */ + .long ADC0_THCMP_IRQHandler /* ADC0 threshold compare and error. */ + .long DMIC0_IRQHandler /* Digital microphone and DMIC subsystem */ + .long HWVAD0_IRQHandler /* Hardware Voice Activity Detector */ + .long USB0_NEEDCLK_IRQHandler /* USB Activity Wake-up Interrupt */ + .long USB0_IRQHandler /* USB device */ + .long RTC_IRQHandler /* RTC alarm and wake-up interrupts */ + .long 0 /* Reserved interrupt */ + .long 0 /* Reserved interrupt */ + .long PIN_INT4_IRQHandler /* Pin interrupt 4 or pattern match engine slice 4 int */ + .long PIN_INT5_IRQHandler /* Pin interrupt 5 or pattern match engine slice 5 int */ + .long PIN_INT6_IRQHandler /* Pin interrupt 6 or pattern match engine slice 6 int */ + .long PIN_INT7_IRQHandler /* Pin interrupt 7 or pattern match engine slice 7 int */ + .long CTIMER2_IRQHandler /* Standard counter/timer CTIMER2 */ + .long CTIMER4_IRQHandler /* Standard counter/timer CTIMER4 */ + .long RIT_IRQHandler /* Repetitive Interrupt Timer */ + .long SPIFI0_IRQHandler /* SPI flash interface */ + .long FLEXCOMM8_IRQHandler /* Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM) */ + .long FLEXCOMM9_IRQHandler /* Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM) */ + .long SDIO_IRQHandler /* SD/MMC */ + .long CAN0_IRQ0_IRQHandler /* CAN0 interrupt0 */ + .long CAN0_IRQ1_IRQHandler /* CAN0 interrupt1 */ + .long CAN1_IRQ0_IRQHandler /* CAN1 interrupt0 */ + .long CAN1_IRQ1_IRQHandler /* CAN1 interrupt1 */ + .long USB1_IRQHandler /* USB1 interrupt */ + .long USB1_NEEDCLK_IRQHandler /* USB1 activity */ + .long ETHERNET_IRQHandler /* Ethernet */ + .long ETHERNET_PMT_IRQHandler /* Ethernet power management interrupt */ + .long ETHERNET_MACLP_IRQHandler /* Ethernet MAC interrupt */ + .long EEPROM_IRQHandler /* EEPROM interrupt */ + .long LCD_IRQHandler /* LCD interrupt */ + .long SHA_IRQHandler /* SHA interrupt */ + .long SMARTCARD0_IRQHandler /* Smart card 0 interrupt */ + .long SMARTCARD1_IRQHandler /* Smart card 1 interrupt */ + .size __Vectors, . - __Vectors + + + + .text + .thumb + +/* Reset Handler */ + + .thumb_func + .align 2 + .globl Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function + +Reset_Handler: +#ifndef __NO_SYSTEM_INIT + ldr r0,=SystemInit + blx r0 +#endif + + /* Loop to copy data from read only memory to RAM. The ranges + * of copy from/to are specified by following symbols evaluated in + * linker script. + * __etext: End of code section, i.e., begin of data sections to copy from. + * __data_start__/__data_end__: RAM address range that data should be + * copied to. Both must be aligned to 4 bytes boundary. */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + +#if 1 +/* Here are two copies of loop implemenations. First one favors code size + * and the second one favors performance. Default uses the first one. + * Change to "#if 0" to use the second one */ +.LC0: + cmp r2, r3 + ittt lt + ldrlt r0, [r1], #4 + strlt r0, [r2], #4 + blt .LC0 +#else + subs r3, r2 + ble .LC1 +.LC0: + subs r3, #4 + ldr r0, [r1, r3] + str r0, [r2, r3] + bgt .LC0 +.LC1: +#endif + +#ifdef __STARTUP_CLEAR_BSS +/* This part of work usually is done in C library startup code. Otherwise, + * define this macro to enable it in this startup. + * + * Loop to zero out BSS section, which uses following symbols + * in linker script: + * __bss_start__: start of BSS section. Must align to 4 + * __bss_end__: end of BSS section. Must align to 4 + */ + ldr r1, =__bss_start__ + ldr r2, =__bss_end__ + + movs r0, 0 +.LC2: + cmp r1, r2 + itt lt + strlt r0, [r1], #4 + blt .LC2 +#endif /* __STARTUP_CLEAR_BSS */ + +#ifndef __START +#define __START _start +#endif +#ifndef __ATOLLIC__ + ldr r0,=__START + blx r0 +#else + ldr r0,=__libc_init_array + blx r0 + ldr r0,=main + bx r0 +#endif + + .pool + .size Reset_Handler, . - Reset_Handler + + .align 1 + .thumb_func + .weak DefaultISR + .type DefaultISR, %function +DefaultISR: + b DefaultISR + .size DefaultISR, . - DefaultISR + + .align 1 + .thumb_func + .weak NMI_Handler + .type NMI_Handler, %function +NMI_Handler: + ldr r0,=NMI_Handler + bx r0 + .size NMI_Handler, . - NMI_Handler + + .align 1 + .thumb_func + .weak HardFault_Handler + .type HardFault_Handler, %function +HardFault_Handler: + ldr r0,=HardFault_Handler + bx r0 + .size HardFault_Handler, . - HardFault_Handler + + .align 1 + .thumb_func + .weak MemManage_Handler + .type MemManage_Handler, %function +MemManage_Handler: + ldr r0,=MemManage_Handler + bx r0 + .size MemManage_Handler, . - MemManage_Handler + + .align 1 + .thumb_func + .weak BusFault_Handler + .type BusFault_Handler, %function +BusFault_Handler: + ldr r0,=BusFault_Handler + bx r0 + .size BusFault_Handler, . - BusFault_Handler + + .align 1 + .thumb_func + .weak UsageFault_Handler + .type UsageFault_Handler, %function +UsageFault_Handler: + ldr r0,=UsageFault_Handler + bx r0 + .size UsageFault_Handler, . - UsageFault_Handler + + .align 1 + .thumb_func + .weak SVC_Handler + .type SVC_Handler, %function +SVC_Handler: + ldr r0,=SVC_Handler + bx r0 + .size SVC_Handler, . - SVC_Handler + + .align 1 + .thumb_func + .weak DebugMon_Handler + .type DebugMon_Handler, %function +DebugMon_Handler: + ldr r0,=DebugMon_Handler + bx r0 + .size DebugMon_Handler, . - DebugMon_Handler + + .align 1 + .thumb_func + .weak PendSV_Handler + .type PendSV_Handler, %function +PendSV_Handler: + ldr r0,=PendSV_Handler + bx r0 + .size PendSV_Handler, . - PendSV_Handler + + .align 1 + .thumb_func + .weak SysTick_Handler + .type SysTick_Handler, %function +SysTick_Handler: + ldr r0,=SysTick_Handler + bx r0 + .size SysTick_Handler, . - SysTick_Handler + + .align 1 + .thumb_func + .weak WDT_BOD_IRQHandler + .type WDT_BOD_IRQHandler, %function +WDT_BOD_IRQHandler: + ldr r0,=WDT_BOD_DriverIRQHandler + bx r0 + .size WDT_BOD_IRQHandler, . - WDT_BOD_IRQHandler + + .align 1 + .thumb_func + .weak DMA0_IRQHandler + .type DMA0_IRQHandler, %function +DMA0_IRQHandler: + ldr r0,=DMA0_DriverIRQHandler + bx r0 + .size DMA0_IRQHandler, . - DMA0_IRQHandler + + .align 1 + .thumb_func + .weak GINT0_IRQHandler + .type GINT0_IRQHandler, %function +GINT0_IRQHandler: + ldr r0,=GINT0_DriverIRQHandler + bx r0 + .size GINT0_IRQHandler, . - GINT0_IRQHandler + + .align 1 + .thumb_func + .weak GINT1_IRQHandler + .type GINT1_IRQHandler, %function +GINT1_IRQHandler: + ldr r0,=GINT1_DriverIRQHandler + bx r0 + .size GINT1_IRQHandler, . - GINT1_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT0_IRQHandler + .type PIN_INT0_IRQHandler, %function +PIN_INT0_IRQHandler: + ldr r0,=PIN_INT0_DriverIRQHandler + bx r0 + .size PIN_INT0_IRQHandler, . - PIN_INT0_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT1_IRQHandler + .type PIN_INT1_IRQHandler, %function +PIN_INT1_IRQHandler: + ldr r0,=PIN_INT1_DriverIRQHandler + bx r0 + .size PIN_INT1_IRQHandler, . - PIN_INT1_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT2_IRQHandler + .type PIN_INT2_IRQHandler, %function +PIN_INT2_IRQHandler: + ldr r0,=PIN_INT2_DriverIRQHandler + bx r0 + .size PIN_INT2_IRQHandler, . - PIN_INT2_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT3_IRQHandler + .type PIN_INT3_IRQHandler, %function +PIN_INT3_IRQHandler: + ldr r0,=PIN_INT3_DriverIRQHandler + bx r0 + .size PIN_INT3_IRQHandler, . - PIN_INT3_IRQHandler + + .align 1 + .thumb_func + .weak UTICK0_IRQHandler + .type UTICK0_IRQHandler, %function +UTICK0_IRQHandler: + ldr r0,=UTICK0_DriverIRQHandler + bx r0 + .size UTICK0_IRQHandler, . - UTICK0_IRQHandler + + .align 1 + .thumb_func + .weak MRT0_IRQHandler + .type MRT0_IRQHandler, %function +MRT0_IRQHandler: + ldr r0,=MRT0_DriverIRQHandler + bx r0 + .size MRT0_IRQHandler, . - MRT0_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER0_IRQHandler + .type CTIMER0_IRQHandler, %function +CTIMER0_IRQHandler: + ldr r0,=CTIMER0_DriverIRQHandler + bx r0 + .size CTIMER0_IRQHandler, . - CTIMER0_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER1_IRQHandler + .type CTIMER1_IRQHandler, %function +CTIMER1_IRQHandler: + ldr r0,=CTIMER1_DriverIRQHandler + bx r0 + .size CTIMER1_IRQHandler, . - CTIMER1_IRQHandler + + .align 1 + .thumb_func + .weak SCT0_IRQHandler + .type SCT0_IRQHandler, %function +SCT0_IRQHandler: + ldr r0,=SCT0_DriverIRQHandler + bx r0 + .size SCT0_IRQHandler, . - SCT0_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER3_IRQHandler + .type CTIMER3_IRQHandler, %function +CTIMER3_IRQHandler: + ldr r0,=CTIMER3_DriverIRQHandler + bx r0 + .size CTIMER3_IRQHandler, . - CTIMER3_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM0_IRQHandler + .type FLEXCOMM0_IRQHandler, %function +FLEXCOMM0_IRQHandler: + ldr r0,=FLEXCOMM0_DriverIRQHandler + bx r0 + .size FLEXCOMM0_IRQHandler, . - FLEXCOMM0_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM1_IRQHandler + .type FLEXCOMM1_IRQHandler, %function +FLEXCOMM1_IRQHandler: + ldr r0,=FLEXCOMM1_DriverIRQHandler + bx r0 + .size FLEXCOMM1_IRQHandler, . - FLEXCOMM1_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM2_IRQHandler + .type FLEXCOMM2_IRQHandler, %function +FLEXCOMM2_IRQHandler: + ldr r0,=FLEXCOMM2_DriverIRQHandler + bx r0 + .size FLEXCOMM2_IRQHandler, . - FLEXCOMM2_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM3_IRQHandler + .type FLEXCOMM3_IRQHandler, %function +FLEXCOMM3_IRQHandler: + ldr r0,=FLEXCOMM3_DriverIRQHandler + bx r0 + .size FLEXCOMM3_IRQHandler, . - FLEXCOMM3_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM4_IRQHandler + .type FLEXCOMM4_IRQHandler, %function +FLEXCOMM4_IRQHandler: + ldr r0,=FLEXCOMM4_DriverIRQHandler + bx r0 + .size FLEXCOMM4_IRQHandler, . - FLEXCOMM4_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM5_IRQHandler + .type FLEXCOMM5_IRQHandler, %function +FLEXCOMM5_IRQHandler: + ldr r0,=FLEXCOMM5_DriverIRQHandler + bx r0 + .size FLEXCOMM5_IRQHandler, . - FLEXCOMM5_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM6_IRQHandler + .type FLEXCOMM6_IRQHandler, %function +FLEXCOMM6_IRQHandler: + ldr r0,=FLEXCOMM6_DriverIRQHandler + bx r0 + .size FLEXCOMM6_IRQHandler, . - FLEXCOMM6_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM7_IRQHandler + .type FLEXCOMM7_IRQHandler, %function +FLEXCOMM7_IRQHandler: + ldr r0,=FLEXCOMM7_DriverIRQHandler + bx r0 + .size FLEXCOMM7_IRQHandler, . - FLEXCOMM7_IRQHandler + + .align 1 + .thumb_func + .weak ADC0_SEQA_IRQHandler + .type ADC0_SEQA_IRQHandler, %function +ADC0_SEQA_IRQHandler: + ldr r0,=ADC0_SEQA_DriverIRQHandler + bx r0 + .size ADC0_SEQA_IRQHandler, . - ADC0_SEQA_IRQHandler + + .align 1 + .thumb_func + .weak ADC0_SEQB_IRQHandler + .type ADC0_SEQB_IRQHandler, %function +ADC0_SEQB_IRQHandler: + ldr r0,=ADC0_SEQB_DriverIRQHandler + bx r0 + .size ADC0_SEQB_IRQHandler, . - ADC0_SEQB_IRQHandler + + .align 1 + .thumb_func + .weak ADC0_THCMP_IRQHandler + .type ADC0_THCMP_IRQHandler, %function +ADC0_THCMP_IRQHandler: + ldr r0,=ADC0_THCMP_DriverIRQHandler + bx r0 + .size ADC0_THCMP_IRQHandler, . - ADC0_THCMP_IRQHandler + + .align 1 + .thumb_func + .weak DMIC0_IRQHandler + .type DMIC0_IRQHandler, %function +DMIC0_IRQHandler: + ldr r0,=DMIC0_DriverIRQHandler + bx r0 + .size DMIC0_IRQHandler, . - DMIC0_IRQHandler + + .align 1 + .thumb_func + .weak HWVAD0_IRQHandler + .type HWVAD0_IRQHandler, %function +HWVAD0_IRQHandler: + ldr r0,=HWVAD0_DriverIRQHandler + bx r0 + .size HWVAD0_IRQHandler, . - HWVAD0_IRQHandler + + .align 1 + .thumb_func + .weak USB0_NEEDCLK_IRQHandler + .type USB0_NEEDCLK_IRQHandler, %function +USB0_NEEDCLK_IRQHandler: + ldr r0,=USB0_NEEDCLK_DriverIRQHandler + bx r0 + .size USB0_NEEDCLK_IRQHandler, . - USB0_NEEDCLK_IRQHandler + + .align 1 + .thumb_func + .weak USB0_IRQHandler + .type USB0_IRQHandler, %function +USB0_IRQHandler: + ldr r0,=USB0_DriverIRQHandler + bx r0 + .size USB0_IRQHandler, . - USB0_IRQHandler + + .align 1 + .thumb_func + .weak RTC_IRQHandler + .type RTC_IRQHandler, %function +RTC_IRQHandler: + ldr r0,=RTC_DriverIRQHandler + bx r0 + .size RTC_IRQHandler, . - RTC_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT4_IRQHandler + .type PIN_INT4_IRQHandler, %function +PIN_INT4_IRQHandler: + ldr r0,=PIN_INT4_DriverIRQHandler + bx r0 + .size PIN_INT4_IRQHandler, . - PIN_INT4_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT5_IRQHandler + .type PIN_INT5_IRQHandler, %function +PIN_INT5_IRQHandler: + ldr r0,=PIN_INT5_DriverIRQHandler + bx r0 + .size PIN_INT5_IRQHandler, . - PIN_INT5_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT6_IRQHandler + .type PIN_INT6_IRQHandler, %function +PIN_INT6_IRQHandler: + ldr r0,=PIN_INT6_DriverIRQHandler + bx r0 + .size PIN_INT6_IRQHandler, . - PIN_INT6_IRQHandler + + .align 1 + .thumb_func + .weak PIN_INT7_IRQHandler + .type PIN_INT7_IRQHandler, %function +PIN_INT7_IRQHandler: + ldr r0,=PIN_INT7_DriverIRQHandler + bx r0 + .size PIN_INT7_IRQHandler, . - PIN_INT7_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER2_IRQHandler + .type CTIMER2_IRQHandler, %function +CTIMER2_IRQHandler: + ldr r0,=CTIMER2_DriverIRQHandler + bx r0 + .size CTIMER2_IRQHandler, . - CTIMER2_IRQHandler + + .align 1 + .thumb_func + .weak CTIMER4_IRQHandler + .type CTIMER4_IRQHandler, %function +CTIMER4_IRQHandler: + ldr r0,=CTIMER4_DriverIRQHandler + bx r0 + .size CTIMER4_IRQHandler, . - CTIMER4_IRQHandler + + .align 1 + .thumb_func + .weak RIT_IRQHandler + .type RIT_IRQHandler, %function +RIT_IRQHandler: + ldr r0,=RIT_DriverIRQHandler + bx r0 + .size RIT_IRQHandler, . - RIT_IRQHandler + + .align 1 + .thumb_func + .weak SPIFI0_IRQHandler + .type SPIFI0_IRQHandler, %function +SPIFI0_IRQHandler: + ldr r0,=SPIFI0_DriverIRQHandler + bx r0 + .size SPIFI0_IRQHandler, . - SPIFI0_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM8_IRQHandler + .type FLEXCOMM8_IRQHandler, %function +FLEXCOMM8_IRQHandler: + ldr r0,=FLEXCOMM8_DriverIRQHandler + bx r0 + .size FLEXCOMM8_IRQHandler, . - FLEXCOMM8_IRQHandler + + .align 1 + .thumb_func + .weak FLEXCOMM9_IRQHandler + .type FLEXCOMM9_IRQHandler, %function +FLEXCOMM9_IRQHandler: + ldr r0,=FLEXCOMM9_DriverIRQHandler + bx r0 + .size FLEXCOMM9_IRQHandler, . - FLEXCOMM9_IRQHandler + + .align 1 + .thumb_func + .weak SDIO_IRQHandler + .type SDIO_IRQHandler, %function +SDIO_IRQHandler: + ldr r0,=SDIO_DriverIRQHandler + bx r0 + .size SDIO_IRQHandler, . - SDIO_IRQHandler + + .align 1 + .thumb_func + .weak CAN0_IRQ0_IRQHandler + .type CAN0_IRQ0_IRQHandler, %function +CAN0_IRQ0_IRQHandler: + ldr r0,=CAN0_IRQ0_DriverIRQHandler + bx r0 + .size CAN0_IRQ0_IRQHandler, . - CAN0_IRQ0_IRQHandler + + .align 1 + .thumb_func + .weak CAN0_IRQ1_IRQHandler + .type CAN0_IRQ1_IRQHandler, %function +CAN0_IRQ1_IRQHandler: + ldr r0,=CAN0_IRQ1_DriverIRQHandler + bx r0 + .size CAN0_IRQ1_IRQHandler, . - CAN0_IRQ1_IRQHandler + + .align 1 + .thumb_func + .weak CAN1_IRQ0_IRQHandler + .type CAN1_IRQ0_IRQHandler, %function +CAN1_IRQ0_IRQHandler: + ldr r0,=CAN1_IRQ0_DriverIRQHandler + bx r0 + .size CAN1_IRQ0_IRQHandler, . - CAN1_IRQ0_IRQHandler + + .align 1 + .thumb_func + .weak CAN1_IRQ1_IRQHandler + .type CAN1_IRQ1_IRQHandler, %function +CAN1_IRQ1_IRQHandler: + ldr r0,=CAN1_IRQ1_DriverIRQHandler + bx r0 + .size CAN1_IRQ1_IRQHandler, . - CAN1_IRQ1_IRQHandler + + .align 1 + .thumb_func + .weak USB1_IRQHandler + .type USB1_IRQHandler, %function +USB1_IRQHandler: + ldr r0,=USB1_DriverIRQHandler + bx r0 + .size USB1_IRQHandler, . - USB1_IRQHandler + + .align 1 + .thumb_func + .weak USB1_NEEDCLK_IRQHandler + .type USB1_NEEDCLK_IRQHandler, %function +USB1_NEEDCLK_IRQHandler: + ldr r0,=USB1_NEEDCLK_DriverIRQHandler + bx r0 + .size USB1_NEEDCLK_IRQHandler, . - USB1_NEEDCLK_IRQHandler + + .align 1 + .thumb_func + .weak ETHERNET_IRQHandler + .type ETHERNET_IRQHandler, %function +ETHERNET_IRQHandler: + ldr r0,=ETHERNET_DriverIRQHandler + bx r0 + .size ETHERNET_IRQHandler, . - ETHERNET_IRQHandler + + .align 1 + .thumb_func + .weak ETHERNET_PMT_IRQHandler + .type ETHERNET_PMT_IRQHandler, %function +ETHERNET_PMT_IRQHandler: + ldr r0,=ETHERNET_PMT_DriverIRQHandler + bx r0 + .size ETHERNET_PMT_IRQHandler, . - ETHERNET_PMT_IRQHandler + + .align 1 + .thumb_func + .weak ETHERNET_MACLP_IRQHandler + .type ETHERNET_MACLP_IRQHandler, %function +ETHERNET_MACLP_IRQHandler: + ldr r0,=ETHERNET_MACLP_DriverIRQHandler + bx r0 + .size ETHERNET_MACLP_IRQHandler, . - ETHERNET_MACLP_IRQHandler + + .align 1 + .thumb_func + .weak EEPROM_IRQHandler + .type EEPROM_IRQHandler, %function +EEPROM_IRQHandler: + ldr r0,=EEPROM_DriverIRQHandler + bx r0 + .size EEPROM_IRQHandler, . - EEPROM_IRQHandler + + .align 1 + .thumb_func + .weak LCD_IRQHandler + .type LCD_IRQHandler, %function +LCD_IRQHandler: + ldr r0,=LCD_DriverIRQHandler + bx r0 + .size LCD_IRQHandler, . - LCD_IRQHandler + + .align 1 + .thumb_func + .weak SHA_IRQHandler + .type SHA_IRQHandler, %function +SHA_IRQHandler: + ldr r0,=SHA_DriverIRQHandler + bx r0 + .size SHA_IRQHandler, . - SHA_IRQHandler + + .align 1 + .thumb_func + .weak SMARTCARD0_IRQHandler + .type SMARTCARD0_IRQHandler, %function +SMARTCARD0_IRQHandler: + ldr r0,=SMARTCARD0_DriverIRQHandler + bx r0 + .size SMARTCARD0_IRQHandler, . - SMARTCARD0_IRQHandler + + .align 1 + .thumb_func + .weak SMARTCARD1_IRQHandler + .type SMARTCARD1_IRQHandler, %function +SMARTCARD1_IRQHandler: + ldr r0,=SMARTCARD1_DriverIRQHandler + bx r0 + .size SMARTCARD1_IRQHandler, . - SMARTCARD1_IRQHandler + + +/* Macro to define default handlers. Default handler + * will be weak symbol and just dead loops. They can be + * overwritten by other handlers */ + + .macro def_irq_handler handler_name + .weak \handler_name + .set \handler_name, DefaultISR + .endm + +/* Exception Handlers */ + def_irq_handler WDT_BOD_DriverIRQHandler /* Windowed watchdog timer, Brownout detect */ + def_irq_handler DMA0_DriverIRQHandler /* DMA controller */ + def_irq_handler GINT0_DriverIRQHandler /* GPIO group 0 */ + def_irq_handler GINT1_DriverIRQHandler /* GPIO group 1 */ + def_irq_handler PIN_INT0_DriverIRQHandler /* Pin interrupt 0 or pattern match engine slice 0 */ + def_irq_handler PIN_INT1_DriverIRQHandler /* Pin interrupt 1or pattern match engine slice 1 */ + def_irq_handler PIN_INT2_DriverIRQHandler /* Pin interrupt 2 or pattern match engine slice 2 */ + def_irq_handler PIN_INT3_DriverIRQHandler /* Pin interrupt 3 or pattern match engine slice 3 */ + def_irq_handler UTICK0_DriverIRQHandler /* Micro-tick Timer */ + def_irq_handler MRT0_DriverIRQHandler /* Multi-rate timer */ + def_irq_handler CTIMER0_DriverIRQHandler /* Standard counter/timer CTIMER0 */ + def_irq_handler CTIMER1_DriverIRQHandler /* Standard counter/timer CTIMER1 */ + def_irq_handler SCT0_DriverIRQHandler /* SCTimer/PWM */ + def_irq_handler CTIMER3_DriverIRQHandler /* Standard counter/timer CTIMER3 */ + def_irq_handler FLEXCOMM0_DriverIRQHandler /* Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) */ + def_irq_handler FLEXCOMM1_DriverIRQHandler /* Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) */ + def_irq_handler FLEXCOMM2_DriverIRQHandler /* Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) */ + def_irq_handler FLEXCOMM3_DriverIRQHandler /* Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) */ + def_irq_handler FLEXCOMM4_DriverIRQHandler /* Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) */ + def_irq_handler FLEXCOMM5_DriverIRQHandler /* Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM) */ + def_irq_handler FLEXCOMM6_DriverIRQHandler /* Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM) */ + def_irq_handler FLEXCOMM7_DriverIRQHandler /* Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM) */ + def_irq_handler ADC0_SEQA_DriverIRQHandler /* ADC0 sequence A completion. */ + def_irq_handler ADC0_SEQB_DriverIRQHandler /* ADC0 sequence B completion. */ + def_irq_handler ADC0_THCMP_DriverIRQHandler /* ADC0 threshold compare and error. */ + def_irq_handler DMIC0_DriverIRQHandler /* Digital microphone and DMIC subsystem */ + def_irq_handler HWVAD0_DriverIRQHandler /* Hardware Voice Activity Detector */ + def_irq_handler USB0_NEEDCLK_DriverIRQHandler /* USB Activity Wake-up Interrupt */ + def_irq_handler USB0_DriverIRQHandler /* USB device */ + def_irq_handler RTC_DriverIRQHandler /* RTC alarm and wake-up interrupts */ + def_irq_handler Reserved46_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler Reserved47_DriverIRQHandler /* Reserved interrupt */ + def_irq_handler PIN_INT4_DriverIRQHandler /* Pin interrupt 4 or pattern match engine slice 4 int */ + def_irq_handler PIN_INT5_DriverIRQHandler /* Pin interrupt 5 or pattern match engine slice 5 int */ + def_irq_handler PIN_INT6_DriverIRQHandler /* Pin interrupt 6 or pattern match engine slice 6 int */ + def_irq_handler PIN_INT7_DriverIRQHandler /* Pin interrupt 7 or pattern match engine slice 7 int */ + def_irq_handler CTIMER2_DriverIRQHandler /* Standard counter/timer CTIMER2 */ + def_irq_handler CTIMER4_DriverIRQHandler /* Standard counter/timer CTIMER4 */ + def_irq_handler RIT_DriverIRQHandler /* Repetitive Interrupt Timer */ + def_irq_handler SPIFI0_DriverIRQHandler /* SPI flash interface */ + def_irq_handler FLEXCOMM8_DriverIRQHandler /* Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM) */ + def_irq_handler FLEXCOMM9_DriverIRQHandler /* Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM) */ + def_irq_handler SDIO_DriverIRQHandler /* SD/MMC */ + def_irq_handler CAN0_IRQ0_DriverIRQHandler /* CAN0 interrupt0 */ + def_irq_handler CAN0_IRQ1_DriverIRQHandler /* CAN0 interrupt1 */ + def_irq_handler CAN1_IRQ0_DriverIRQHandler /* CAN1 interrupt0 */ + def_irq_handler CAN1_IRQ1_DriverIRQHandler /* CAN1 interrupt1 */ + def_irq_handler USB1_DriverIRQHandler /* USB1 interrupt */ + def_irq_handler USB1_NEEDCLK_DriverIRQHandler /* USB1 activity */ + def_irq_handler ETHERNET_DriverIRQHandler /* Ethernet */ + def_irq_handler ETHERNET_PMT_DriverIRQHandler /* Ethernet power management interrupt */ + def_irq_handler ETHERNET_MACLP_DriverIRQHandler /* Ethernet MAC interrupt */ + def_irq_handler EEPROM_DriverIRQHandler /* EEPROM interrupt */ + def_irq_handler LCD_DriverIRQHandler /* LCD interrupt */ + def_irq_handler SHA_DriverIRQHandler /* SHA interrupt */ + def_irq_handler SMARTCARD0_DriverIRQHandler /* Smart card 0 interrupt */ + def_irq_handler SMARTCARD1_DriverIRQHandler /* Smart card 1 interrupt */ + + .end
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_IAR/LPC54618J512.icf Fri Feb 16 16:09:33 2018 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,123 +0,0 @@
-/*
-** ###################################################################
-** Processors: LPC54618J512BD208
-** LPC54618J512ET180
-**
-** Compiler: IAR ANSI C/C++ Compiler for ARM
-** Reference manual: LPC54S60x/LPC5460x User manual Rev.0.9 7 Nov 2016
-** Version: rev. 1.1, 2016-11-25
-** Build: b161227
-**
-** Abstract:
-** Linker file for the IAR ANSI C/C++ Compiler for ARM
-**
-** Copyright (c) 2016 Freescale Semiconductor, Inc.
-** Copyright 2016 - 2017 NXP
-** Redistribution and use in source and binary forms, with or without modification,
-** are permitted provided that the following conditions are met:
-**
-** o Redistributions of source code must retain the above copyright notice, this list
-** of conditions and the following disclaimer.
-**
-** o Redistributions in binary form must reproduce the above copyright notice, this
-** list of conditions and the following disclaimer in the documentation and/or
-** other materials provided with the distribution.
-**
-** o Neither the name of the copyright holder nor the names of its
-** contributors may be used to endorse or promote products derived from this
-** software without specific prior written permission.
-**
-** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-**
-** http: www.nxp.com
-** mail: support@nxp.com
-**
-** ###################################################################
-*/
-define symbol __ram_vector_table__ = 1;
-
-define symbol __stack_size__=0x8000;
-define symbol __heap_size__=0xC000;
-
-define symbol __ram_vector_table_size__ = isdefinedsymbol(__ram_vector_table__) ? 0x00000400 : 0;
-define symbol __ram_vector_table_offset__ = isdefinedsymbol(__ram_vector_table__) ? 0x000003FF : 0;
-
-define symbol m_interrupts_start = 0x00000000;
-define symbol m_interrupts_end = 0x000003FF;
-
-define symbol m_text_start = 0x00000400;
-define symbol m_text_end = 0x0007FFFF;
-
-define symbol m_interrupts_ram_start = 0x20000000;
-define symbol m_interrupts_ram_end = 0x20000000 + __ram_vector_table_offset__;
-
-define symbol m_data_start = m_interrupts_ram_start + __ram_vector_table_size__;
-define symbol m_data_end = 0x20027FFF;
-
-define symbol m_usb_sram_start = 0x40100000;
-define symbol m_usb_sram_end = 0x40101FFF;
-
-/* USB BDT size */
-define symbol usb_bdt_size = 0x0;
-/* Sizes */
-if (isdefinedsymbol(__stack_size__)) {
- define symbol __size_cstack__ = __stack_size__;
-} else {
- define symbol __size_cstack__ = 0x0400;
-}
-
-if (isdefinedsymbol(__heap_size__)) {
- define symbol __size_heap__ = __heap_size__;
-} else {
- define symbol __size_heap__ = 0x0400;
-}
-
-define exported symbol __VECTOR_TABLE = m_interrupts_start;
-define exported symbol __VECTOR_RAM = isdefinedsymbol(__ram_vector_table__) ? m_interrupts_ram_start : m_interrupts_start;
-define exported symbol __RAM_VECTOR_TABLE_SIZE = __ram_vector_table_size__;
-
-define memory mem with size = 4G;
-define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
- | mem:[from m_text_start to m_text_end];
-define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];
-define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];
-define region m_interrupts_ram_region = mem:[from m_interrupts_ram_start to m_interrupts_ram_end];
-
-define block CSTACK with alignment = 8, size = __size_cstack__ { };
-define block HEAP with alignment = 8, size = __size_heap__ { };
-define block RW { readwrite };
-define block ZI { zi };
-
-/* regions for USB */
-define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1];
-define region USB_SRAM_region = mem:[from m_usb_sram_start + usb_bdt_size to m_usb_sram_end];
-place in USB_BDT_region { section m_usb_bdt };
-place in USB_SRAM_region { section m_usb_global };
-
-initialize by copy { readwrite, section .textrw };
-
-if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
-{
- /* Required in a multi-threaded application */
- initialize by copy with packing = none { section __DLIB_PERTHREAD };
-}
-
-do not initialize { section .noinit, section m_usb_bdt, section m_usb_global };
-
-place at address mem: m_interrupts_start { readonly section .intvec };
-place in TEXT_region { readonly };
-place in DATA_region { block RW };
-place in DATA_region { block ZI };
-place in DATA_region { last block HEAP };
-place in CSTACK_region { block CSTACK };
-place in m_interrupts_ram_region { section m_interrupts_ram };
-
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_IAR/LPC54628J512.icf Tue Mar 20 16:56:18 2018 +0000
@@ -0,0 +1,121 @@
+/*
+** ###################################################################
+** Processor: LPC54628J512ET180
+** Compiler: IAR ANSI C/C++ Compiler for ARM
+** Reference manual: LPC546xx User manual Rev.1.9 5 June 2017
+** Version: rev. 1.2, 2017-06-08
+** Build: b170821
+**
+** Abstract:
+** Linker file for the IAR ANSI C/C++ Compiler for ARM
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2017 NXP
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** 1. Redistributions of source code must retain the above copyright notice, this list
+** of conditions and the following disclaimer.
+**
+** 2. Redistributions in binary form must reproduce the above copyright notice, this
+** list of conditions and the following disclaimer in the documentation and/or
+** other materials provided with the distribution.
+**
+** 3. Neither the name of the copyright holder nor the names of its
+** contributors may be used to endorse or promote products derived from this
+** software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** ###################################################################
+*/
+define symbol __ram_vector_table__ = 1;
+
+define symbol __stack_size__=0x8000;
+define symbol __heap_size__=0xC000;
+
+define symbol __ram_vector_table_size__ = isdefinedsymbol(__ram_vector_table__) ? 0x00000400 : 0;
+define symbol __ram_vector_table_offset__ = isdefinedsymbol(__ram_vector_table__) ? 0x000003FF : 0;
+
+define symbol m_interrupts_start = 0x00000000;
+define symbol m_interrupts_end = 0x000003FF;
+
+define symbol m_text_start = 0x00000400;
+define symbol m_text_end = 0x0007FFFF;
+
+define symbol m_interrupts_ram_start = 0x20000000;
+define symbol m_interrupts_ram_end = 0x20000000 + __ram_vector_table_offset__;
+
+define symbol m_data_start = m_interrupts_ram_start + __ram_vector_table_size__;
+define symbol m_data_end = 0x20027FFF;
+
+define symbol m_usb_sram_start = 0x40100000;
+define symbol m_usb_sram_end = 0x40101FFF;
+
+/* USB BDT size */
+define symbol usb_bdt_size = 0x0;
+/* Sizes */
+if (isdefinedsymbol(__stack_size__)) {
+ define symbol __size_cstack__ = __stack_size__;
+} else {
+ define symbol __size_cstack__ = 0x0400;
+}
+
+if (isdefinedsymbol(__heap_size__)) {
+ define symbol __size_heap__ = __heap_size__;
+} else {
+ define symbol __size_heap__ = 0x0400;
+}
+
+define exported symbol __VECTOR_TABLE = m_interrupts_start;
+define exported symbol __VECTOR_RAM = isdefinedsymbol(__ram_vector_table__) ? m_interrupts_ram_start : m_interrupts_start;
+define exported symbol __RAM_VECTOR_TABLE_SIZE = __ram_vector_table_size__;
+
+define memory mem with size = 4G;
+define region TEXT_region = mem:[from m_interrupts_start to m_interrupts_end]
+ | mem:[from m_text_start to m_text_end];
+define region DATA_region = mem:[from m_data_start to m_data_end-__size_cstack__];
+define region CSTACK_region = mem:[from m_data_end-__size_cstack__+1 to m_data_end];
+define region m_interrupts_ram_region = mem:[from m_interrupts_ram_start to m_interrupts_ram_end];
+
+define block CSTACK with alignment = 8, size = __size_cstack__ { };
+define block HEAP with alignment = 8, size = __size_heap__ { };
+define block RW { readwrite };
+define block ZI { zi };
+
+/* regions for USB */
+define region USB_BDT_region = mem:[from m_usb_sram_start to m_usb_sram_start + usb_bdt_size - 1];
+define region USB_SRAM_region = mem:[from m_usb_sram_start + usb_bdt_size to m_usb_sram_end];
+place in USB_BDT_region { section m_usb_bdt };
+place in USB_SRAM_region { section m_usb_global };
+
+initialize by copy { readwrite, section .textrw };
+
+if (isdefinedsymbol(__USE_DLIB_PERTHREAD))
+{
+ /* Required in a multi-threaded application */
+ initialize by copy with packing = none { section __DLIB_PERTHREAD };
+}
+
+do not initialize { section .noinit, section m_usb_bdt, section m_usb_global };
+
+place at address mem: m_interrupts_start { readonly section .intvec };
+place in TEXT_region { readonly };
+place in DATA_region { block RW };
+place in DATA_region { block ZI };
+place in DATA_region { last block HEAP };
+place in CSTACK_region { block CSTACK };
+place in m_interrupts_ram_region { section m_interrupts_ram };
+
Binary file targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_IAR/lib_power.a has changed
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_IAR/startup_LPC54618.S Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,615 +0,0 @@ -;/***************************************************************************** -; * @file: startup_LPC54618.s -; * @purpose: CMSIS Cortex-M4 Core Device Startup File -; * LPC54618 -; * @version: 1.1 -; * @date: 2016-11-25 -; *---------------------------------------------------------------------------- -; * -; * Copyright 1997 - 2016 Freescale Semiconductor. -; * Copyright 2016 - 2017 NXP -; * -; Redistribution and use in source and binary forms, with or without modification, -; are permitted provided that the following conditions are met: -; -; o Redistributions of source code must retain the above copyright notice, this list -; of conditions and the following disclaimer. -; -; o Redistributions in binary form must reproduce the above copyright notice, this -; list of conditions and the following disclaimer in the documentation and/or -; other materials provided with the distribution. -; -; o Neither the name of the copyright holder nor the names of its -; contributors may be used to endorse or promote products derived from this -; software without specific prior written permission. -; -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND -; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED -; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR -; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES -; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; -; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON -; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT -; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS -; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler - DCD HardFault_Handler - DCD MemManage_Handler - DCD BusFault_Handler - DCD UsageFault_Handler -__vector_table_0x1c - DCD 0 - DCD 0xFFFFFFFF ;ECRP - DCD 0 - DCD 0 - DCD SVC_Handler - DCD DebugMon_Handler - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD WDT_BOD_IRQHandler ; Windowed watchdog timer, Brownout detect - DCD DMA0_IRQHandler ; DMA controller - DCD GINT0_IRQHandler ; GPIO group 0 - DCD GINT1_IRQHandler ; GPIO group 1 - DCD PIN_INT0_IRQHandler ; Pin interrupt 0 or pattern match engine slice 0 - DCD PIN_INT1_IRQHandler ; Pin interrupt 1or pattern match engine slice 1 - DCD PIN_INT2_IRQHandler ; Pin interrupt 2 or pattern match engine slice 2 - DCD PIN_INT3_IRQHandler ; Pin interrupt 3 or pattern match engine slice 3 - DCD UTICK0_IRQHandler ; Micro-tick Timer - DCD MRT0_IRQHandler ; Multi-rate timer - DCD CTIMER0_IRQHandler ; Standard counter/timer CTIMER0 - DCD CTIMER1_IRQHandler ; Standard counter/timer CTIMER1 - DCD SCT0_IRQHandler ; SCTimer/PWM - DCD CTIMER3_IRQHandler ; Standard counter/timer CTIMER3 - DCD FLEXCOMM0_IRQHandler ; Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) - DCD FLEXCOMM1_IRQHandler ; Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) - DCD FLEXCOMM2_IRQHandler ; Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) - DCD FLEXCOMM3_IRQHandler ; Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) - DCD FLEXCOMM4_IRQHandler ; Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) - DCD FLEXCOMM5_IRQHandler ; Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM) - DCD FLEXCOMM6_IRQHandler ; Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM) - DCD FLEXCOMM7_IRQHandler ; Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM) - DCD ADC0_SEQA_IRQHandler ; ADC0 sequence A completion. - DCD ADC0_SEQB_IRQHandler ; ADC0 sequence B completion. - DCD ADC0_THCMP_IRQHandler ; ADC0 threshold compare and error. - DCD DMIC0_IRQHandler ; Digital microphone and DMIC subsystem - DCD HWVAD0_IRQHandler ; Hardware Voice Activity Detector - DCD USB0_NEEDCLK_IRQHandler ; USB Activity Wake-up Interrupt - DCD USB0_IRQHandler ; USB device - DCD RTC_IRQHandler ; RTC alarm and wake-up interrupts - DCD Reserved46_IRQHandler ; Reserved interrupt - DCD Reserved47_IRQHandler ; Reserved interrupt - DCD PIN_INT4_IRQHandler ; Pin interrupt 4 or pattern match engine slice 4 int - DCD PIN_INT5_IRQHandler ; Pin interrupt 5 or pattern match engine slice 5 int - DCD PIN_INT6_IRQHandler ; Pin interrupt 6 or pattern match engine slice 6 int - DCD PIN_INT7_IRQHandler ; Pin interrupt 7 or pattern match engine slice 7 int - DCD CTIMER2_IRQHandler ; Standard counter/timer CTIMER2 - DCD CTIMER4_IRQHandler ; Standard counter/timer CTIMER4 - DCD RIT_IRQHandler ; Repetitive Interrupt Timer - DCD SPIFI0_IRQHandler ; SPI flash interface - DCD FLEXCOMM8_IRQHandler ; Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM) - DCD FLEXCOMM9_IRQHandler ; Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM) - DCD SDIO_IRQHandler ; SD/MMC - DCD CAN0_IRQ0_IRQHandler ; CAN0 interrupt0 - DCD CAN0_IRQ1_IRQHandler ; CAN0 interrupt1 - DCD CAN1_IRQ0_IRQHandler ; CAN1 interrupt0 - DCD CAN1_IRQ1_IRQHandler ; CAN1 interrupt1 - DCD USB1_IRQHandler ; USB1 interrupt - DCD USB1_NEEDCLK_IRQHandler ; USB1 activity - DCD ETHERNET_IRQHandler ; Ethernet - DCD ETHERNET_PMT_IRQHandler ; Ethernet power management interrupt - DCD ETHERNET_MACLP_IRQHandler ; Ethernet MAC interrupt - DCD EEPROM_IRQHandler ; EEPROM interrupt - DCD LCD_IRQHandler ; LCD interrupt - DCD SHA_IRQHandler ; SHA interrupt - DCD SMARTCARD0_IRQHandler ; Smart card 0 interrupt - DCD SMARTCARD1_IRQHandler ; Smart card 1 interrupt -__Vectors_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR r0, =SystemInit - BLX r0 - LDR r0, =__iar_program_start - BX r0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B . - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B . - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B . - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B . - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B . - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B . - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B . - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B . - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B . - - PUBWEAK WDT_BOD_IRQHandler - PUBWEAK WDT_BOD_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -WDT_BOD_IRQHandler - LDR R0, =WDT_BOD_DriverIRQHandler - BX R0 - PUBWEAK DMA0_IRQHandler - PUBWEAK DMA0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMA0_IRQHandler - LDR R0, =DMA0_DriverIRQHandler - BX R0 - PUBWEAK GINT0_IRQHandler - PUBWEAK GINT0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -GINT0_IRQHandler - LDR R0, =GINT0_DriverIRQHandler - BX R0 - PUBWEAK GINT1_IRQHandler - PUBWEAK GINT1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -GINT1_IRQHandler - LDR R0, =GINT1_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT0_IRQHandler - PUBWEAK PIN_INT0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT0_IRQHandler - LDR R0, =PIN_INT0_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT1_IRQHandler - PUBWEAK PIN_INT1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT1_IRQHandler - LDR R0, =PIN_INT1_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT2_IRQHandler - PUBWEAK PIN_INT2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT2_IRQHandler - LDR R0, =PIN_INT2_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT3_IRQHandler - PUBWEAK PIN_INT3_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT3_IRQHandler - LDR R0, =PIN_INT3_DriverIRQHandler - BX R0 - PUBWEAK UTICK0_IRQHandler - PUBWEAK UTICK0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -UTICK0_IRQHandler - LDR R0, =UTICK0_DriverIRQHandler - BX R0 - PUBWEAK MRT0_IRQHandler - PUBWEAK MRT0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -MRT0_IRQHandler - LDR R0, =MRT0_DriverIRQHandler - BX R0 - PUBWEAK CTIMER0_IRQHandler - PUBWEAK CTIMER0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER0_IRQHandler - LDR R0, =CTIMER0_DriverIRQHandler - BX R0 - PUBWEAK CTIMER1_IRQHandler - PUBWEAK CTIMER1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER1_IRQHandler - LDR R0, =CTIMER1_DriverIRQHandler - BX R0 - PUBWEAK SCT0_IRQHandler - PUBWEAK SCT0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SCT0_IRQHandler - LDR R0, =SCT0_DriverIRQHandler - BX R0 - PUBWEAK CTIMER3_IRQHandler - PUBWEAK CTIMER3_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER3_IRQHandler - LDR R0, =CTIMER3_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM0_IRQHandler - PUBWEAK FLEXCOMM0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM0_IRQHandler - LDR R0, =FLEXCOMM0_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM1_IRQHandler - PUBWEAK FLEXCOMM1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM1_IRQHandler - LDR R0, =FLEXCOMM1_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM2_IRQHandler - PUBWEAK FLEXCOMM2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM2_IRQHandler - LDR R0, =FLEXCOMM2_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM3_IRQHandler - PUBWEAK FLEXCOMM3_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM3_IRQHandler - LDR R0, =FLEXCOMM3_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM4_IRQHandler - PUBWEAK FLEXCOMM4_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM4_IRQHandler - LDR R0, =FLEXCOMM4_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM5_IRQHandler - PUBWEAK FLEXCOMM5_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM5_IRQHandler - LDR R0, =FLEXCOMM5_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM6_IRQHandler - PUBWEAK FLEXCOMM6_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM6_IRQHandler - LDR R0, =FLEXCOMM6_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM7_IRQHandler - PUBWEAK FLEXCOMM7_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM7_IRQHandler - LDR R0, =FLEXCOMM7_DriverIRQHandler - BX R0 - PUBWEAK ADC0_SEQA_IRQHandler - PUBWEAK ADC0_SEQA_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -ADC0_SEQA_IRQHandler - LDR R0, =ADC0_SEQA_DriverIRQHandler - BX R0 - PUBWEAK ADC0_SEQB_IRQHandler - PUBWEAK ADC0_SEQB_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -ADC0_SEQB_IRQHandler - LDR R0, =ADC0_SEQB_DriverIRQHandler - BX R0 - PUBWEAK ADC0_THCMP_IRQHandler - PUBWEAK ADC0_THCMP_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -ADC0_THCMP_IRQHandler - LDR R0, =ADC0_THCMP_DriverIRQHandler - BX R0 - PUBWEAK DMIC0_IRQHandler - PUBWEAK DMIC0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -DMIC0_IRQHandler - LDR R0, =DMIC0_DriverIRQHandler - BX R0 - PUBWEAK HWVAD0_IRQHandler - PUBWEAK HWVAD0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -HWVAD0_IRQHandler - LDR R0, =HWVAD0_DriverIRQHandler - BX R0 - PUBWEAK USB0_NEEDCLK_IRQHandler - PUBWEAK USB0_NEEDCLK_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -USB0_NEEDCLK_IRQHandler - LDR R0, =USB0_NEEDCLK_DriverIRQHandler - BX R0 - PUBWEAK USB0_IRQHandler - PUBWEAK USB0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -USB0_IRQHandler - LDR R0, =USB0_DriverIRQHandler - BX R0 - PUBWEAK RTC_IRQHandler - PUBWEAK RTC_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -RTC_IRQHandler - LDR R0, =RTC_DriverIRQHandler - BX R0 - PUBWEAK Reserved46_IRQHandler - PUBWEAK Reserved46_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved46_IRQHandler - LDR R0, =Reserved46_DriverIRQHandler - BX R0 - PUBWEAK Reserved47_IRQHandler - PUBWEAK Reserved47_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -Reserved47_IRQHandler - LDR R0, =Reserved47_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT4_IRQHandler - PUBWEAK PIN_INT4_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT4_IRQHandler - LDR R0, =PIN_INT4_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT5_IRQHandler - PUBWEAK PIN_INT5_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT5_IRQHandler - LDR R0, =PIN_INT5_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT6_IRQHandler - PUBWEAK PIN_INT6_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT6_IRQHandler - LDR R0, =PIN_INT6_DriverIRQHandler - BX R0 - PUBWEAK PIN_INT7_IRQHandler - PUBWEAK PIN_INT7_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -PIN_INT7_IRQHandler - LDR R0, =PIN_INT7_DriverIRQHandler - BX R0 - PUBWEAK CTIMER2_IRQHandler - PUBWEAK CTIMER2_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER2_IRQHandler - LDR R0, =CTIMER2_DriverIRQHandler - BX R0 - PUBWEAK CTIMER4_IRQHandler - PUBWEAK CTIMER4_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CTIMER4_IRQHandler - LDR R0, =CTIMER4_DriverIRQHandler - BX R0 - PUBWEAK RIT_IRQHandler - PUBWEAK RIT_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -RIT_IRQHandler - LDR R0, =RIT_DriverIRQHandler - BX R0 - PUBWEAK SPIFI0_IRQHandler - PUBWEAK SPIFI0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SPIFI0_IRQHandler - LDR R0, =SPIFI0_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM8_IRQHandler - PUBWEAK FLEXCOMM8_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM8_IRQHandler - LDR R0, =FLEXCOMM8_DriverIRQHandler - BX R0 - PUBWEAK FLEXCOMM9_IRQHandler - PUBWEAK FLEXCOMM9_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -FLEXCOMM9_IRQHandler - LDR R0, =FLEXCOMM9_DriverIRQHandler - BX R0 - PUBWEAK SDIO_IRQHandler - PUBWEAK SDIO_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SDIO_IRQHandler - LDR R0, =SDIO_DriverIRQHandler - BX R0 - PUBWEAK CAN0_IRQ0_IRQHandler - PUBWEAK CAN0_IRQ0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CAN0_IRQ0_IRQHandler - LDR R0, =CAN0_IRQ0_DriverIRQHandler - BX R0 - PUBWEAK CAN0_IRQ1_IRQHandler - PUBWEAK CAN0_IRQ1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CAN0_IRQ1_IRQHandler - LDR R0, =CAN0_IRQ1_DriverIRQHandler - BX R0 - PUBWEAK CAN1_IRQ0_IRQHandler - PUBWEAK CAN1_IRQ0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CAN1_IRQ0_IRQHandler - LDR R0, =CAN1_IRQ0_DriverIRQHandler - BX R0 - PUBWEAK CAN1_IRQ1_IRQHandler - PUBWEAK CAN1_IRQ1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -CAN1_IRQ1_IRQHandler - LDR R0, =CAN1_IRQ1_DriverIRQHandler - BX R0 - PUBWEAK USB1_IRQHandler - PUBWEAK USB1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -USB1_IRQHandler - LDR R0, =USB1_DriverIRQHandler - BX R0 - PUBWEAK USB1_NEEDCLK_IRQHandler - PUBWEAK USB1_NEEDCLK_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -USB1_NEEDCLK_IRQHandler - LDR R0, =USB1_NEEDCLK_DriverIRQHandler - BX R0 - PUBWEAK ETHERNET_IRQHandler - PUBWEAK ETHERNET_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -ETHERNET_IRQHandler - LDR R0, =ETHERNET_DriverIRQHandler - BX R0 - PUBWEAK ETHERNET_PMT_IRQHandler - PUBWEAK ETHERNET_PMT_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -ETHERNET_PMT_IRQHandler - LDR R0, =ETHERNET_PMT_DriverIRQHandler - BX R0 - PUBWEAK ETHERNET_MACLP_IRQHandler - PUBWEAK ETHERNET_MACLP_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -ETHERNET_MACLP_IRQHandler - LDR R0, =ETHERNET_MACLP_DriverIRQHandler - BX R0 - PUBWEAK EEPROM_IRQHandler - PUBWEAK EEPROM_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -EEPROM_IRQHandler - LDR R0, =EEPROM_DriverIRQHandler - BX R0 - PUBWEAK LCD_IRQHandler - PUBWEAK LCD_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -LCD_IRQHandler - LDR R0, =LCD_DriverIRQHandler - BX R0 - PUBWEAK SHA_IRQHandler - PUBWEAK SHA_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SHA_IRQHandler - LDR R0, =SHA_DriverIRQHandler - BX R0 - PUBWEAK SMARTCARD0_IRQHandler - PUBWEAK SMARTCARD0_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SMARTCARD0_IRQHandler - LDR R0, =SMARTCARD0_DriverIRQHandler - BX R0 - PUBWEAK SMARTCARD1_IRQHandler - PUBWEAK SMARTCARD1_DriverIRQHandler - SECTION .text:CODE:REORDER:NOROOT(2) -SMARTCARD1_IRQHandler - LDR R0, =SMARTCARD1_DriverIRQHandler - BX R0 -WDT_BOD_DriverIRQHandler -DMA0_DriverIRQHandler -GINT0_DriverIRQHandler -GINT1_DriverIRQHandler -PIN_INT0_DriverIRQHandler -PIN_INT1_DriverIRQHandler -PIN_INT2_DriverIRQHandler -PIN_INT3_DriverIRQHandler -UTICK0_DriverIRQHandler -MRT0_DriverIRQHandler -CTIMER0_DriverIRQHandler -CTIMER1_DriverIRQHandler -SCT0_DriverIRQHandler -CTIMER3_DriverIRQHandler -FLEXCOMM0_DriverIRQHandler -FLEXCOMM1_DriverIRQHandler -FLEXCOMM2_DriverIRQHandler -FLEXCOMM3_DriverIRQHandler -FLEXCOMM4_DriverIRQHandler -FLEXCOMM5_DriverIRQHandler -FLEXCOMM6_DriverIRQHandler -FLEXCOMM7_DriverIRQHandler -ADC0_SEQA_DriverIRQHandler -ADC0_SEQB_DriverIRQHandler -ADC0_THCMP_DriverIRQHandler -DMIC0_DriverIRQHandler -HWVAD0_DriverIRQHandler -USB0_NEEDCLK_DriverIRQHandler -USB0_DriverIRQHandler -RTC_DriverIRQHandler -Reserved46_DriverIRQHandler -Reserved47_DriverIRQHandler -PIN_INT4_DriverIRQHandler -PIN_INT5_DriverIRQHandler -PIN_INT6_DriverIRQHandler -PIN_INT7_DriverIRQHandler -CTIMER2_DriverIRQHandler -CTIMER4_DriverIRQHandler -RIT_DriverIRQHandler -SPIFI0_DriverIRQHandler -FLEXCOMM8_DriverIRQHandler -FLEXCOMM9_DriverIRQHandler -SDIO_DriverIRQHandler -CAN0_IRQ0_DriverIRQHandler -CAN0_IRQ1_DriverIRQHandler -CAN1_IRQ0_DriverIRQHandler -CAN1_IRQ1_DriverIRQHandler -USB1_DriverIRQHandler -USB1_NEEDCLK_DriverIRQHandler -ETHERNET_DriverIRQHandler -ETHERNET_PMT_DriverIRQHandler -ETHERNET_MACLP_DriverIRQHandler -EEPROM_DriverIRQHandler -LCD_DriverIRQHandler -SHA_DriverIRQHandler -SMARTCARD0_DriverIRQHandler -SMARTCARD1_DriverIRQHandler -DefaultISR - B . - - END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/TOOLCHAIN_IAR/startup_LPC54628.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,615 @@ +;/***************************************************************************** +; * @file: startup_LPC54628.s +; * @purpose: CMSIS Cortex-M4 Core Device Startup File +; * LPC54628 +; * @version: 1.2 +; * @date: 2017-6-8 +; *---------------------------------------------------------------------------- +; * +; * Copyright 1997-2016 Freescale Semiconductor, Inc. +; * Copyright 2016-2017 NXP +; * +; Redistribution and use in source and binary forms, with or without modification, +; are permitted provided that the following conditions are met: +; +; 1. Redistributions of source code must retain the above copyright notice, this list +; of conditions and the following disclaimer. +; +; 2. Redistributions in binary form must reproduce the above copyright notice, this +; list of conditions and the following disclaimer in the documentation and/or +; other materials provided with the distribution. +; +; 3. Neither the name of the copyright holder nor the names of its +; contributors may be used to endorse or promote products derived from this +; software without specific prior written permission. +; +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND +; ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED +; WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +; DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR +; ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES +; (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; +; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON +; ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT +; (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS +; SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0xFFFFFFFF ;ECRP + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD WDT_BOD_IRQHandler ; Windowed watchdog timer, Brownout detect + DCD DMA0_IRQHandler ; DMA controller + DCD GINT0_IRQHandler ; GPIO group 0 + DCD GINT1_IRQHandler ; GPIO group 1 + DCD PIN_INT0_IRQHandler ; Pin interrupt 0 or pattern match engine slice 0 + DCD PIN_INT1_IRQHandler ; Pin interrupt 1or pattern match engine slice 1 + DCD PIN_INT2_IRQHandler ; Pin interrupt 2 or pattern match engine slice 2 + DCD PIN_INT3_IRQHandler ; Pin interrupt 3 or pattern match engine slice 3 + DCD UTICK0_IRQHandler ; Micro-tick Timer + DCD MRT0_IRQHandler ; Multi-rate timer + DCD CTIMER0_IRQHandler ; Standard counter/timer CTIMER0 + DCD CTIMER1_IRQHandler ; Standard counter/timer CTIMER1 + DCD SCT0_IRQHandler ; SCTimer/PWM + DCD CTIMER3_IRQHandler ; Standard counter/timer CTIMER3 + DCD FLEXCOMM0_IRQHandler ; Flexcomm Interface 0 (USART, SPI, I2C, FLEXCOMM) + DCD FLEXCOMM1_IRQHandler ; Flexcomm Interface 1 (USART, SPI, I2C, FLEXCOMM) + DCD FLEXCOMM2_IRQHandler ; Flexcomm Interface 2 (USART, SPI, I2C, FLEXCOMM) + DCD FLEXCOMM3_IRQHandler ; Flexcomm Interface 3 (USART, SPI, I2C, FLEXCOMM) + DCD FLEXCOMM4_IRQHandler ; Flexcomm Interface 4 (USART, SPI, I2C, FLEXCOMM) + DCD FLEXCOMM5_IRQHandler ; Flexcomm Interface 5 (USART, SPI, I2C,, FLEXCOMM) + DCD FLEXCOMM6_IRQHandler ; Flexcomm Interface 6 (USART, SPI, I2C, I2S,, FLEXCOMM) + DCD FLEXCOMM7_IRQHandler ; Flexcomm Interface 7 (USART, SPI, I2C, I2S,, FLEXCOMM) + DCD ADC0_SEQA_IRQHandler ; ADC0 sequence A completion. + DCD ADC0_SEQB_IRQHandler ; ADC0 sequence B completion. + DCD ADC0_THCMP_IRQHandler ; ADC0 threshold compare and error. + DCD DMIC0_IRQHandler ; Digital microphone and DMIC subsystem + DCD HWVAD0_IRQHandler ; Hardware Voice Activity Detector + DCD USB0_NEEDCLK_IRQHandler ; USB Activity Wake-up Interrupt + DCD USB0_IRQHandler ; USB device + DCD RTC_IRQHandler ; RTC alarm and wake-up interrupts + DCD Reserved46_IRQHandler ; Reserved interrupt + DCD Reserved47_IRQHandler ; Reserved interrupt + DCD PIN_INT4_IRQHandler ; Pin interrupt 4 or pattern match engine slice 4 int + DCD PIN_INT5_IRQHandler ; Pin interrupt 5 or pattern match engine slice 5 int + DCD PIN_INT6_IRQHandler ; Pin interrupt 6 or pattern match engine slice 6 int + DCD PIN_INT7_IRQHandler ; Pin interrupt 7 or pattern match engine slice 7 int + DCD CTIMER2_IRQHandler ; Standard counter/timer CTIMER2 + DCD CTIMER4_IRQHandler ; Standard counter/timer CTIMER4 + DCD RIT_IRQHandler ; Repetitive Interrupt Timer + DCD SPIFI0_IRQHandler ; SPI flash interface + DCD FLEXCOMM8_IRQHandler ; Flexcomm Interface 8 (USART, SPI, I2C, FLEXCOMM) + DCD FLEXCOMM9_IRQHandler ; Flexcomm Interface 9 (USART, SPI, I2C, FLEXCOMM) + DCD SDIO_IRQHandler ; SD/MMC + DCD CAN0_IRQ0_IRQHandler ; CAN0 interrupt0 + DCD CAN0_IRQ1_IRQHandler ; CAN0 interrupt1 + DCD CAN1_IRQ0_IRQHandler ; CAN1 interrupt0 + DCD CAN1_IRQ1_IRQHandler ; CAN1 interrupt1 + DCD USB1_IRQHandler ; USB1 interrupt + DCD USB1_NEEDCLK_IRQHandler ; USB1 activity + DCD ETHERNET_IRQHandler ; Ethernet + DCD ETHERNET_PMT_IRQHandler ; Ethernet power management interrupt + DCD ETHERNET_MACLP_IRQHandler ; Ethernet MAC interrupt + DCD EEPROM_IRQHandler ; EEPROM interrupt + DCD LCD_IRQHandler ; LCD interrupt + DCD SHA_IRQHandler ; SHA interrupt + DCD SMARTCARD0_IRQHandler ; Smart card 0 interrupt + DCD SMARTCARD1_IRQHandler ; Smart card 1 interrupt +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR r0, =SystemInit + BLX r0 + LDR r0, =__iar_program_start + BX r0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B . + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B . + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + PUBWEAK WDT_BOD_IRQHandler + PUBWEAK WDT_BOD_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +WDT_BOD_IRQHandler + LDR R0, =WDT_BOD_DriverIRQHandler + BX R0 + PUBWEAK DMA0_IRQHandler + PUBWEAK DMA0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMA0_IRQHandler + LDR R0, =DMA0_DriverIRQHandler + BX R0 + PUBWEAK GINT0_IRQHandler + PUBWEAK GINT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +GINT0_IRQHandler + LDR R0, =GINT0_DriverIRQHandler + BX R0 + PUBWEAK GINT1_IRQHandler + PUBWEAK GINT1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +GINT1_IRQHandler + LDR R0, =GINT1_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT0_IRQHandler + PUBWEAK PIN_INT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT0_IRQHandler + LDR R0, =PIN_INT0_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT1_IRQHandler + PUBWEAK PIN_INT1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT1_IRQHandler + LDR R0, =PIN_INT1_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT2_IRQHandler + PUBWEAK PIN_INT2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT2_IRQHandler + LDR R0, =PIN_INT2_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT3_IRQHandler + PUBWEAK PIN_INT3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT3_IRQHandler + LDR R0, =PIN_INT3_DriverIRQHandler + BX R0 + PUBWEAK UTICK0_IRQHandler + PUBWEAK UTICK0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +UTICK0_IRQHandler + LDR R0, =UTICK0_DriverIRQHandler + BX R0 + PUBWEAK MRT0_IRQHandler + PUBWEAK MRT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +MRT0_IRQHandler + LDR R0, =MRT0_DriverIRQHandler + BX R0 + PUBWEAK CTIMER0_IRQHandler + PUBWEAK CTIMER0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER0_IRQHandler + LDR R0, =CTIMER0_DriverIRQHandler + BX R0 + PUBWEAK CTIMER1_IRQHandler + PUBWEAK CTIMER1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER1_IRQHandler + LDR R0, =CTIMER1_DriverIRQHandler + BX R0 + PUBWEAK SCT0_IRQHandler + PUBWEAK SCT0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SCT0_IRQHandler + LDR R0, =SCT0_DriverIRQHandler + BX R0 + PUBWEAK CTIMER3_IRQHandler + PUBWEAK CTIMER3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER3_IRQHandler + LDR R0, =CTIMER3_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM0_IRQHandler + PUBWEAK FLEXCOMM0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM0_IRQHandler + LDR R0, =FLEXCOMM0_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM1_IRQHandler + PUBWEAK FLEXCOMM1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM1_IRQHandler + LDR R0, =FLEXCOMM1_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM2_IRQHandler + PUBWEAK FLEXCOMM2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM2_IRQHandler + LDR R0, =FLEXCOMM2_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM3_IRQHandler + PUBWEAK FLEXCOMM3_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM3_IRQHandler + LDR R0, =FLEXCOMM3_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM4_IRQHandler + PUBWEAK FLEXCOMM4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM4_IRQHandler + LDR R0, =FLEXCOMM4_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM5_IRQHandler + PUBWEAK FLEXCOMM5_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM5_IRQHandler + LDR R0, =FLEXCOMM5_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM6_IRQHandler + PUBWEAK FLEXCOMM6_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM6_IRQHandler + LDR R0, =FLEXCOMM6_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM7_IRQHandler + PUBWEAK FLEXCOMM7_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM7_IRQHandler + LDR R0, =FLEXCOMM7_DriverIRQHandler + BX R0 + PUBWEAK ADC0_SEQA_IRQHandler + PUBWEAK ADC0_SEQA_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ADC0_SEQA_IRQHandler + LDR R0, =ADC0_SEQA_DriverIRQHandler + BX R0 + PUBWEAK ADC0_SEQB_IRQHandler + PUBWEAK ADC0_SEQB_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ADC0_SEQB_IRQHandler + LDR R0, =ADC0_SEQB_DriverIRQHandler + BX R0 + PUBWEAK ADC0_THCMP_IRQHandler + PUBWEAK ADC0_THCMP_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ADC0_THCMP_IRQHandler + LDR R0, =ADC0_THCMP_DriverIRQHandler + BX R0 + PUBWEAK DMIC0_IRQHandler + PUBWEAK DMIC0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +DMIC0_IRQHandler + LDR R0, =DMIC0_DriverIRQHandler + BX R0 + PUBWEAK HWVAD0_IRQHandler + PUBWEAK HWVAD0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +HWVAD0_IRQHandler + LDR R0, =HWVAD0_DriverIRQHandler + BX R0 + PUBWEAK USB0_NEEDCLK_IRQHandler + PUBWEAK USB0_NEEDCLK_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USB0_NEEDCLK_IRQHandler + LDR R0, =USB0_NEEDCLK_DriverIRQHandler + BX R0 + PUBWEAK USB0_IRQHandler + PUBWEAK USB0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USB0_IRQHandler + LDR R0, =USB0_DriverIRQHandler + BX R0 + PUBWEAK RTC_IRQHandler + PUBWEAK RTC_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +RTC_IRQHandler + LDR R0, =RTC_DriverIRQHandler + BX R0 + PUBWEAK Reserved46_IRQHandler + PUBWEAK Reserved46_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved46_IRQHandler + LDR R0, =Reserved46_DriverIRQHandler + BX R0 + PUBWEAK Reserved47_IRQHandler + PUBWEAK Reserved47_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +Reserved47_IRQHandler + LDR R0, =Reserved47_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT4_IRQHandler + PUBWEAK PIN_INT4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT4_IRQHandler + LDR R0, =PIN_INT4_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT5_IRQHandler + PUBWEAK PIN_INT5_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT5_IRQHandler + LDR R0, =PIN_INT5_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT6_IRQHandler + PUBWEAK PIN_INT6_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT6_IRQHandler + LDR R0, =PIN_INT6_DriverIRQHandler + BX R0 + PUBWEAK PIN_INT7_IRQHandler + PUBWEAK PIN_INT7_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +PIN_INT7_IRQHandler + LDR R0, =PIN_INT7_DriverIRQHandler + BX R0 + PUBWEAK CTIMER2_IRQHandler + PUBWEAK CTIMER2_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER2_IRQHandler + LDR R0, =CTIMER2_DriverIRQHandler + BX R0 + PUBWEAK CTIMER4_IRQHandler + PUBWEAK CTIMER4_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CTIMER4_IRQHandler + LDR R0, =CTIMER4_DriverIRQHandler + BX R0 + PUBWEAK RIT_IRQHandler + PUBWEAK RIT_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +RIT_IRQHandler + LDR R0, =RIT_DriverIRQHandler + BX R0 + PUBWEAK SPIFI0_IRQHandler + PUBWEAK SPIFI0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SPIFI0_IRQHandler + LDR R0, =SPIFI0_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM8_IRQHandler + PUBWEAK FLEXCOMM8_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM8_IRQHandler + LDR R0, =FLEXCOMM8_DriverIRQHandler + BX R0 + PUBWEAK FLEXCOMM9_IRQHandler + PUBWEAK FLEXCOMM9_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +FLEXCOMM9_IRQHandler + LDR R0, =FLEXCOMM9_DriverIRQHandler + BX R0 + PUBWEAK SDIO_IRQHandler + PUBWEAK SDIO_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SDIO_IRQHandler + LDR R0, =SDIO_DriverIRQHandler + BX R0 + PUBWEAK CAN0_IRQ0_IRQHandler + PUBWEAK CAN0_IRQ0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CAN0_IRQ0_IRQHandler + LDR R0, =CAN0_IRQ0_DriverIRQHandler + BX R0 + PUBWEAK CAN0_IRQ1_IRQHandler + PUBWEAK CAN0_IRQ1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CAN0_IRQ1_IRQHandler + LDR R0, =CAN0_IRQ1_DriverIRQHandler + BX R0 + PUBWEAK CAN1_IRQ0_IRQHandler + PUBWEAK CAN1_IRQ0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CAN1_IRQ0_IRQHandler + LDR R0, =CAN1_IRQ0_DriverIRQHandler + BX R0 + PUBWEAK CAN1_IRQ1_IRQHandler + PUBWEAK CAN1_IRQ1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +CAN1_IRQ1_IRQHandler + LDR R0, =CAN1_IRQ1_DriverIRQHandler + BX R0 + PUBWEAK USB1_IRQHandler + PUBWEAK USB1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USB1_IRQHandler + LDR R0, =USB1_DriverIRQHandler + BX R0 + PUBWEAK USB1_NEEDCLK_IRQHandler + PUBWEAK USB1_NEEDCLK_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +USB1_NEEDCLK_IRQHandler + LDR R0, =USB1_NEEDCLK_DriverIRQHandler + BX R0 + PUBWEAK ETHERNET_IRQHandler + PUBWEAK ETHERNET_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ETHERNET_IRQHandler + LDR R0, =ETHERNET_DriverIRQHandler + BX R0 + PUBWEAK ETHERNET_PMT_IRQHandler + PUBWEAK ETHERNET_PMT_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ETHERNET_PMT_IRQHandler + LDR R0, =ETHERNET_PMT_DriverIRQHandler + BX R0 + PUBWEAK ETHERNET_MACLP_IRQHandler + PUBWEAK ETHERNET_MACLP_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +ETHERNET_MACLP_IRQHandler + LDR R0, =ETHERNET_MACLP_DriverIRQHandler + BX R0 + PUBWEAK EEPROM_IRQHandler + PUBWEAK EEPROM_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +EEPROM_IRQHandler + LDR R0, =EEPROM_DriverIRQHandler + BX R0 + PUBWEAK LCD_IRQHandler + PUBWEAK LCD_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +LCD_IRQHandler + LDR R0, =LCD_DriverIRQHandler + BX R0 + PUBWEAK SHA_IRQHandler + PUBWEAK SHA_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SHA_IRQHandler + LDR R0, =SHA_DriverIRQHandler + BX R0 + PUBWEAK SMARTCARD0_IRQHandler + PUBWEAK SMARTCARD0_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SMARTCARD0_IRQHandler + LDR R0, =SMARTCARD0_DriverIRQHandler + BX R0 + PUBWEAK SMARTCARD1_IRQHandler + PUBWEAK SMARTCARD1_DriverIRQHandler + SECTION .text:CODE:REORDER:NOROOT(2) +SMARTCARD1_IRQHandler + LDR R0, =SMARTCARD1_DriverIRQHandler + BX R0 +WDT_BOD_DriverIRQHandler +DMA0_DriverIRQHandler +GINT0_DriverIRQHandler +GINT1_DriverIRQHandler +PIN_INT0_DriverIRQHandler +PIN_INT1_DriverIRQHandler +PIN_INT2_DriverIRQHandler +PIN_INT3_DriverIRQHandler +UTICK0_DriverIRQHandler +MRT0_DriverIRQHandler +CTIMER0_DriverIRQHandler +CTIMER1_DriverIRQHandler +SCT0_DriverIRQHandler +CTIMER3_DriverIRQHandler +FLEXCOMM0_DriverIRQHandler +FLEXCOMM1_DriverIRQHandler +FLEXCOMM2_DriverIRQHandler +FLEXCOMM3_DriverIRQHandler +FLEXCOMM4_DriverIRQHandler +FLEXCOMM5_DriverIRQHandler +FLEXCOMM6_DriverIRQHandler +FLEXCOMM7_DriverIRQHandler +ADC0_SEQA_DriverIRQHandler +ADC0_SEQB_DriverIRQHandler +ADC0_THCMP_DriverIRQHandler +DMIC0_DriverIRQHandler +HWVAD0_DriverIRQHandler +USB0_NEEDCLK_DriverIRQHandler +USB0_DriverIRQHandler +RTC_DriverIRQHandler +Reserved46_DriverIRQHandler +Reserved47_DriverIRQHandler +PIN_INT4_DriverIRQHandler +PIN_INT5_DriverIRQHandler +PIN_INT6_DriverIRQHandler +PIN_INT7_DriverIRQHandler +CTIMER2_DriverIRQHandler +CTIMER4_DriverIRQHandler +RIT_DriverIRQHandler +SPIFI0_DriverIRQHandler +FLEXCOMM8_DriverIRQHandler +FLEXCOMM9_DriverIRQHandler +SDIO_DriverIRQHandler +CAN0_IRQ0_DriverIRQHandler +CAN0_IRQ1_DriverIRQHandler +CAN1_IRQ0_DriverIRQHandler +CAN1_IRQ1_DriverIRQHandler +USB1_DriverIRQHandler +USB1_NEEDCLK_DriverIRQHandler +ETHERNET_DriverIRQHandler +ETHERNET_PMT_DriverIRQHandler +ETHERNET_MACLP_DriverIRQHandler +EEPROM_DriverIRQHandler +LCD_DriverIRQHandler +SHA_DriverIRQHandler +SMARTCARD0_DriverIRQHandler +SMARTCARD1_DriverIRQHandler +DefaultISR + B . + + END
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/fsl_device_registers.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/fsl_device_registers.h Tue Mar 20 16:56:18 2018 +0000
@@ -1,20 +1,25 @@
/*
- * Copyright (c) 2014 - 2016, Freescale Semiconductor, Inc.
- * Copyright 2016 - 2017 NXP
+ * The Clear BSD License
+ * Copyright 2014-2016 Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
* Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
*
- * o Redistributions of source code must retain the above copyright notice, this list
+ * 1. Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
*
- * o Redistributions in binary form must reproduce the above copyright notice, this
+ * 2. Redistributions in binary form must reproduce the above copyright notice, this
* list of conditions and the following disclaimer in the documentation and/or
* other materials provided with the distribution.
*
- * o Neither the name of the copyright holder nor the names of its
+ * 3. Neither the name of the copyright holder nor the names of its
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -36,14 +41,14 @@
*
* The CPU macro should be declared in the project or makefile.
*/
-#if (defined(CPU_LPC54618J512BD208) || defined(CPU_LPC54618J512ET180))
+#if (defined(CPU_LPC54628J512ET180))
-#define LPC54618_SERIES
+#define LPC54628_SERIES
/* CMSIS-style register definitions */
-#include "LPC54618.h"
+#include "LPC54628.h"
/* CPU specific feature definitions */
-#include "LPC54618_features.h"
+#include "LPC54628_features.h"
#else
#error "No valid CPU defined!"
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/system_LPC54618.c Fri Feb 16 16:09:33 2018 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,361 +0,0 @@
-/*
-** ###################################################################
-** Processors: LPC54618J512BD208
-** LPC54618J512ET180
-**
-** Compilers: Keil ARM C/C++ Compiler
-** GNU C Compiler
-** IAR ANSI C/C++ Compiler for ARM
-** MCUXpresso Compiler
-**
-** Reference manual: LPC54S60x/LPC5460x User manual Rev.0.9 7 Nov 2016
-** Version: rev. 1.1, 2016-11-25
-** Build: b170214
-**
-** Abstract:
-** Provides a system configuration function and a global variable that
-** contains the system frequency. It configures the device and initializes
-** the oscillator (PLL) that is part of the microcontroller device.
-**
-** Copyright 2016 Freescale Semiconductor, Inc.
-** Copyright 2016-2017 NXP
-** Redistribution and use in source and binary forms, with or without modification,
-** are permitted provided that the following conditions are met:
-**
-** o Redistributions of source code must retain the above copyright notice, this list
-** of conditions and the following disclaimer.
-**
-** o Redistributions in binary form must reproduce the above copyright notice, this
-** list of conditions and the following disclaimer in the documentation and/or
-** other materials provided with the distribution.
-**
-** o Neither the name of the copyright holder nor the names of its
-** contributors may be used to endorse or promote products derived from this
-** software without specific prior written permission.
-**
-** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-**
-** http: www.nxp.com
-** mail: support@nxp.com
-**
-** Revisions:
-** - rev. 1.0 (2016-08-12)
-** Initial version.
-** - rev. 1.1 (2016-11-25)
-** Update CANFD and Classic CAN register.
-** Add MAC TIMERSTAMP registers.
-**
-** ###################################################################
-*/
-
-/*!
- * @file LPC54618
- * @version 1.1
- * @date 2016-11-25
- * @brief Device specific configuration file for LPC54618 (implementation file)
- *
- * Provides a system configuration function and a global variable that contains
- * the system frequency. It configures the device and initializes the oscillator
- * (PLL) that is part of the microcontroller device.
- */
-
-#include <stdint.h>
-#include "fsl_device_registers.h"
-
-#define NVALMAX (0x100)
-#define PVALMAX (0x20)
-#define MVALMAX (0x8000)
-#define PLL_MDEC_VAL_P (0) /* MDEC is in bits 16:0 */
-#define PLL_MDEC_VAL_M (0x1FFFFUL << PLL_MDEC_VAL_P)
-#define PLL_NDEC_VAL_P (0) /* NDEC is in bits 9:0 */
-#define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P)
-#define PLL_PDEC_VAL_P (0) /* PDEC is in bits 6:0 */
-#define PLL_PDEC_VAL_M (0x7FUL << PLL_PDEC_VAL_P)
-
-extern void *__Vectors;
-
-static const uint8_t wdtFreqLookup[32] = {0, 8, 12, 15, 18, 20, 24, 26, 28, 30, 32, 34, 36, 38, 40, 41, 42, 44, 45, 46,
- 48, 49, 50, 52, 53, 54, 56, 57, 58, 59, 60, 61};
-/* Get WATCH DOG Clk */
-static uint32_t getWdtOscFreq(void)
-{
- uint8_t freq_sel, div_sel;
- if (SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK)
- {
- return 0U;
- }
- else
- {
- div_sel = ((SYSCON->WDTOSCCTRL & 0x1f) + 1) << 1;
- freq_sel = wdtFreqLookup[((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_FREQSEL_MASK) >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)];
- return ((uint32_t) freq_sel * 50000U)/((uint32_t)div_sel);
- }
-}
-/* Find decoded N value for raw NDEC value */
-static uint32_t pllDecodeN(uint32_t NDEC)
-{
- uint32_t n, x, i;
-
- /* Find NDec */
- switch (NDEC)
- {
- case 0x3FF:
- n = 0;
- break;
- case 0x302:
- n = 1;
- break;
- case 0x202:
- n = 2;
- break;
- default:
- x = 0x080;
- n = 0xFFFFFFFFU;
- for (i = NVALMAX; ((i >= 3) && (n == 0xFFFFFFFFU)); i--)
- {
- x = (((x ^ (x >> 2) ^ (x >> 3) ^ (x >> 4)) & 1) << 7) | ((x >> 1) & 0x7F);
- if ((x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P)) == NDEC)
- {
- /* Decoded value of NDEC */
- n = i;
- }
- }
- break;
- }
- return n;
-}
-
-/* Find decoded P value for raw PDEC value */
-static uint32_t pllDecodeP(uint32_t PDEC)
-{
- uint32_t p, x, i;
- /* Find PDec */
- switch (PDEC)
- {
- case 0x7F:
- p = 0;
- break;
- case 0x62:
- p = 1;
- break;
- case 0x42:
- p = 2;
- break;
- default:
- x = 0x10;
- p = 0xFFFFFFFFU;
- for (i = PVALMAX; ((i >= 3) && (p == 0xFFFFFFFFU)); i--)
- {
- x = (((x ^ (x >> 2)) & 1) << 4) | ((x >> 1) & 0xFU);
- if ((x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P)) == PDEC)
- {
- /* Decoded value of PDEC */
- p = i;
- }
- }
- break;
- }
- return p;
-}
-
-/* Find decoded M value for raw MDEC value */
-static uint32_t pllDecodeM(uint32_t MDEC)
-{
- uint32_t m, i, x;
-
- /* Find MDec */
- switch (MDEC)
- {
- case 0x1FFFF:
- m = 0;
- break;
- case 0x18003:
- m = 1;
- break;
- case 0x10003:
- m = 2;
- break;
- default:
- x = 0x04000;
- m = 0xFFFFFFFFU;
- for (i = MVALMAX; ((i >= 3) && (m == 0xFFFFFFFFU)); i--)
- {
- x = (((x ^ (x >> 1)) & 1) << 14) | ((x >> 1) & 0x3FFFU);
- if ((x & (PLL_MDEC_VAL_M >> PLL_MDEC_VAL_P)) == MDEC)
- {
- /* Decoded value of MDEC */
- m = i;
- }
- }
- break;
- }
- return m;
-}
-
-/* Get predivider (N) from PLL NDEC setting */
-static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg)
-{
- uint32_t preDiv = 1;
-
- /* Direct input is not used? */
- if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTI_MASK) == 0)
- {
- /* Decode NDEC value to get (N) pre divider */
- preDiv = pllDecodeN(nDecReg & 0x3FF);
- if (preDiv == 0)
- {
- preDiv = 1;
- }
- }
- /* Adjusted by 1, directi is used to bypass */
- return preDiv;
-}
-
-/* Get postdivider (P) from PLL PDEC setting */
-static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg)
-{
- uint32_t postDiv = 1;
-
- /* Direct input is not used? */
- if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTO_MASK) == 0)
- {
- /* Decode PDEC value to get (P) post divider */
- postDiv = 2 * pllDecodeP(pDecReg & 0x7F);
- if (postDiv == 0)
- {
- postDiv = 2;
- }
- }
- /* Adjusted by 1, directo is used to bypass */
- return postDiv;
-}
-
-/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */
-static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg)
-{
- uint32_t mMult = 1;
-
- /* Decode MDEC value to get (M) multiplier */
- mMult = pllDecodeM(mDecReg & 0x1FFFF);
- if (mMult == 0)
- {
- mMult = 1;
- }
- return mMult;
-}
-
-
-
-/* ----------------------------------------------------------------------------
- -- Core clock
- ---------------------------------------------------------------------------- */
-
-uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
-
-/* ----------------------------------------------------------------------------
- -- SystemInit()
- ---------------------------------------------------------------------------- */
-
-void SystemInit (void) {
-#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
- SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
-#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
-
-#if defined(__MCUXPRESSO)
- extern void(*const g_pfnVectors[]) (void);
- SCB->VTOR = (uint32_t) &g_pfnVectors;
-#else
- extern void *__Vectors;
- SCB->VTOR = (uint32_t) &__Vectors;
-#endif
- SYSCON->ARMTRACECLKDIV = 0;
-/* Optionally enable RAM banks that may be off by default at reset */
-#if !defined(DONT_ENABLE_DISABLED_RAMBANKS)
- SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL_SRAM1_MASK | SYSCON_AHBCLKCTRL_SRAM2_MASK | SYSCON_AHBCLKCTRL_SRAM3_MASK;
-#endif
-}
-
-/* ----------------------------------------------------------------------------
- -- SystemCoreClockUpdate()
- ---------------------------------------------------------------------------- */
-
-void SystemCoreClockUpdate (void) {
-uint32_t clkRate = 0;
- uint32_t prediv, postdiv;
- uint64_t workRate;
-
- switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK)
- {
- case 0x00: /* MAINCLKSELA clock (main_clk_a)*/
- switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK)
- {
- case 0x00: /* FRO 12 MHz (fro_12m) */
- clkRate = CLK_FRO_12MHZ;
- break;
- case 0x01: /* CLKIN (clk_in) */
- clkRate = CLK_CLK_IN;
- break;
- case 0x02: /* Watchdog oscillator (wdt_clk) */
- clkRate = getWdtOscFreq();
- break;
- default: /* = 0x03 = FRO 96 or 48 MHz (fro_hf) */
- if (SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK)
- {
- clkRate = CLK_FRO_96MHZ;
- }
- else
- {
- clkRate = CLK_FRO_48MHZ;
- }
- break;
- }
- break;
- case 0x02: /* System PLL clock (pll_clk)*/
- switch (SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK)
- {
- case 0x00: /* FRO 12 MHz (fro_12m) */
- clkRate = CLK_FRO_12MHZ;
- break;
- case 0x01: /* CLKIN (clk_in) */
- clkRate = CLK_CLK_IN;
- break;
- case 0x02: /* Watchdog oscillator (wdt_clk) */
- clkRate = getWdtOscFreq();
- break;
- case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */
- clkRate = CLK_RTC_32K_CLK;
- break;
- default:
- break;
- }
- if ((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_BYPASS_MASK) == 0)
- {
- /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */
- prediv = findPllPreDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLNDEC);
- postdiv = findPllPostDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLPDEC);
- /* Adjust input clock */
- clkRate = clkRate / prediv;
-
- /* MDEC used for rate */
- workRate = (uint64_t)clkRate * (uint64_t)findPllMMult(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLMDEC);
- clkRate = workRate / ((uint64_t)postdiv);
- clkRate = workRate * 2; /* PLL CCO output is divided by 2 before to M-Divider */
- }
- break;
- case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */
- clkRate = CLK_RTC_32K_CLK;
- break;
- default:
- break;
- }
- SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFF) + 1);
-}
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/system_LPC54618.h Fri Feb 16 16:09:33 2018 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,121 +0,0 @@
-/*
-** ###################################################################
-** Processors: LPC54618J512BD208
-** LPC54618J512ET180
-**
-** Compilers: Keil ARM C/C++ Compiler
-** GNU C Compiler
-** IAR ANSI C/C++ Compiler for ARM
-** MCUXpresso Compiler
-**
-** Reference manual: LPC54S60x/LPC5460x User manual Rev.0.9 7 Nov 2016
-** Version: rev. 1.1, 2016-11-25
-** Build: b161227
-**
-** Abstract:
-** Provides a system configuration function and a global variable that
-** contains the system frequency. It configures the device and initializes
-** the oscillator (PLL) that is part of the microcontroller device.
-**
-** Copyright (c) 2016 Freescale Semiconductor, Inc.
-** Copyright 2016 - 2017 NXP
-** Redistribution and use in source and binary forms, with or without modification,
-** are permitted provided that the following conditions are met:
-**
-** o Redistributions of source code must retain the above copyright notice, this list
-** of conditions and the following disclaimer.
-**
-** o Redistributions in binary form must reproduce the above copyright notice, this
-** list of conditions and the following disclaimer in the documentation and/or
-** other materials provided with the distribution.
-**
-** o Neither the name of the copyright holder nor the names of its
-** contributors may be used to endorse or promote products derived from this
-** software without specific prior written permission.
-**
-** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
-** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
-** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
-** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
-** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
-** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
-** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
-** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
-** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
-** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
-**
-** http: www.nxp.com
-** mail: support@nxp.com
-**
-** Revisions:
-** - rev. 1.0 (2016-08-12)
-** Initial version.
-** - rev. 1.1 (2016-11-25)
-** Update CANFD and Classic CAN register.
-** Add MAC TIMERSTAMP registers.
-**
-** ###################################################################
-*/
-
-/*!
- * @file LPC54618
- * @version 1.1
- * @date 2016-11-25
- * @brief Device specific configuration file for LPC54618 (header file)
- *
- * Provides a system configuration function and a global variable that contains
- * the system frequency. It configures the device and initializes the oscillator
- * (PLL) that is part of the microcontroller device.
- */
-
-#ifndef _SYSTEM_LPC54618_H_
-#define _SYSTEM_LPC54618_H_ /**< Symbol preventing repeated inclusion */
-
-#ifdef __cplusplus
-extern "C" {
-#endif
-
-#include <stdint.h>
-
-#define DEFAULT_SYSTEM_CLOCK 12000000u /* Default System clock value */
-#define CLK_RTC_32K_CLK 32768u /* RTC oscillator 32 kHz output (32k_clk */
-#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */
-#define CLK_FRO_48MHZ 48000000u /* FRO 48 MHz (fro_48m) */
-#define CLK_FRO_96MHZ 96000000u /* FRO 96 MHz (fro_96m) */
-#define CLK_CLK_IN 0u /* Default CLK_IN pin clock */
-
-
-/**
- * @brief System clock frequency (core clock)
- *
- * The system clock frequency supplied to the SysTick timer and the processor
- * core clock. This variable can be used by the user application to setup the
- * SysTick timer or configure other parameters. It may also be used by debugger to
- * query the frequency of the debug timer or configure the trace clock speed
- * SystemCoreClock is initialized with a correct predefined value.
- */
-extern uint32_t SystemCoreClock;
-
-/**
- * @brief Setup the microcontroller system.
- *
- * Typically this function configures the oscillator (PLL) that is part of the
- * microcontroller device. For systems with variable clock speed it also updates
- * the variable SystemCoreClock. SystemInit is called from startup_device file.
- */
-void SystemInit (void);
-
-/**
- * @brief Updates the SystemCoreClock variable.
- *
- * It must be called whenever the core clock is changed during program
- * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
- * the current core clock.
- */
-void SystemCoreClockUpdate (void);
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif /* _SYSTEM_LPC54618_H_ */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/system_LPC54628.c Tue Mar 20 16:56:18 2018 +0000
@@ -0,0 +1,363 @@
+/*
+** ###################################################################
+** Processor: LPC54628J512ET180
+** Compilers: Keil ARM C/C++ Compiler
+** GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+** MCUXpresso Compiler
+**
+** Reference manual: LPC546xx User manual Rev.1.9 5 June 2017
+** Version: rev. 1.2, 2017-06-08
+** Build: b170609
+**
+** Abstract:
+** Provides a system configuration function and a global variable that
+** contains the system frequency. It configures the device and initializes
+** the oscillator (PLL) that is part of the microcontroller device.
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2017 NXP
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** 1. Redistributions of source code must retain the above copyright notice, this list
+** of conditions and the following disclaimer.
+**
+** 2. Redistributions in binary form must reproduce the above copyright notice, this
+** list of conditions and the following disclaimer in the documentation and/or
+** other materials provided with the distribution.
+**
+** 3. Neither the name of the copyright holder nor the names of its
+** contributors may be used to endorse or promote products derived from this
+** software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** Revisions:
+** - rev. 1.0 (2016-08-12)
+** Initial version.
+** - rev. 1.1 (2016-11-25)
+** Update CANFD and Classic CAN register.
+** Add MAC TIMERSTAMP registers.
+** - rev. 1.2 (2017-06-08)
+** Remove RTC_CTRL_RTC_OSC_BYPASS.
+** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV.
+** Remove RESET and HALT from SYSCON_AHBCLKDIV.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file LPC54628
+ * @version 1.2
+ * @date 2017-06-08
+ * @brief Device specific configuration file for LPC54628 (implementation file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#include <stdint.h>
+#include "fsl_device_registers.h"
+
+#define NVALMAX (0x100)
+#define PVALMAX (0x20)
+#define MVALMAX (0x8000)
+#define PLL_MDEC_VAL_P (0) /* MDEC is in bits 16:0 */
+#define PLL_MDEC_VAL_M (0x1FFFFUL << PLL_MDEC_VAL_P)
+#define PLL_NDEC_VAL_P (0) /* NDEC is in bits 9:0 */
+#define PLL_NDEC_VAL_M (0x3FFUL << PLL_NDEC_VAL_P)
+#define PLL_PDEC_VAL_P (0) /* PDEC is in bits 6:0 */
+#define PLL_PDEC_VAL_M (0x7FUL << PLL_PDEC_VAL_P)
+
+extern void *__Vectors;
+
+static const uint8_t wdtFreqLookup[32] = {0, 8, 12, 15, 18, 20, 24, 26, 28, 30, 32, 34, 36, 38, 40, 41, 42, 44, 45, 46,
+ 48, 49, 50, 52, 53, 54, 56, 57, 58, 59, 60, 61};
+/* Get WATCH DOG Clk */
+static uint32_t getWdtOscFreq(void)
+{
+ uint8_t freq_sel, div_sel;
+ if (SYSCON->PDRUNCFG[0] & SYSCON_PDRUNCFG_PDEN_WDT_OSC_MASK)
+ {
+ return 0U;
+ }
+ else
+ {
+ div_sel = ((SYSCON->WDTOSCCTRL & 0x1f) + 1) << 1;
+ freq_sel = wdtFreqLookup[((SYSCON->WDTOSCCTRL & SYSCON_WDTOSCCTRL_FREQSEL_MASK) >> SYSCON_WDTOSCCTRL_FREQSEL_SHIFT)];
+ return ((uint32_t) freq_sel * 50000U)/((uint32_t)div_sel);
+ }
+}
+/* Find decoded N value for raw NDEC value */
+static uint32_t pllDecodeN(uint32_t NDEC)
+{
+ uint32_t n, x, i;
+
+ /* Find NDec */
+ switch (NDEC)
+ {
+ case 0x3FF:
+ n = 0;
+ break;
+ case 0x302:
+ n = 1;
+ break;
+ case 0x202:
+ n = 2;
+ break;
+ default:
+ x = 0x080;
+ n = 0xFFFFFFFFU;
+ for (i = NVALMAX; ((i >= 3) && (n == 0xFFFFFFFFU)); i--)
+ {
+ x = (((x ^ (x >> 2) ^ (x >> 3) ^ (x >> 4)) & 1) << 7) | ((x >> 1) & 0x7F);
+ if ((x & (PLL_NDEC_VAL_M >> PLL_NDEC_VAL_P)) == NDEC)
+ {
+ /* Decoded value of NDEC */
+ n = i;
+ }
+ }
+ break;
+ }
+ return n;
+}
+
+/* Find decoded P value for raw PDEC value */
+static uint32_t pllDecodeP(uint32_t PDEC)
+{
+ uint32_t p, x, i;
+ /* Find PDec */
+ switch (PDEC)
+ {
+ case 0x7F:
+ p = 0;
+ break;
+ case 0x62:
+ p = 1;
+ break;
+ case 0x42:
+ p = 2;
+ break;
+ default:
+ x = 0x10;
+ p = 0xFFFFFFFFU;
+ for (i = PVALMAX; ((i >= 3) && (p == 0xFFFFFFFFU)); i--)
+ {
+ x = (((x ^ (x >> 2)) & 1) << 4) | ((x >> 1) & 0xFU);
+ if ((x & (PLL_PDEC_VAL_M >> PLL_PDEC_VAL_P)) == PDEC)
+ {
+ /* Decoded value of PDEC */
+ p = i;
+ }
+ }
+ break;
+ }
+ return p;
+}
+
+/* Find decoded M value for raw MDEC value */
+static uint32_t pllDecodeM(uint32_t MDEC)
+{
+ uint32_t m, i, x;
+
+ /* Find MDec */
+ switch (MDEC)
+ {
+ case 0x1FFFF:
+ m = 0;
+ break;
+ case 0x18003:
+ m = 1;
+ break;
+ case 0x10003:
+ m = 2;
+ break;
+ default:
+ x = 0x04000;
+ m = 0xFFFFFFFFU;
+ for (i = MVALMAX; ((i >= 3) && (m == 0xFFFFFFFFU)); i--)
+ {
+ x = (((x ^ (x >> 1)) & 1) << 14) | ((x >> 1) & 0x3FFFU);
+ if ((x & (PLL_MDEC_VAL_M >> PLL_MDEC_VAL_P)) == MDEC)
+ {
+ /* Decoded value of MDEC */
+ m = i;
+ }
+ }
+ break;
+ }
+ return m;
+}
+
+/* Get predivider (N) from PLL NDEC setting */
+static uint32_t findPllPreDiv(uint32_t ctrlReg, uint32_t nDecReg)
+{
+ uint32_t preDiv = 1;
+
+ /* Direct input is not used? */
+ if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTI_MASK) == 0)
+ {
+ /* Decode NDEC value to get (N) pre divider */
+ preDiv = pllDecodeN(nDecReg & 0x3FF);
+ if (preDiv == 0)
+ {
+ preDiv = 1;
+ }
+ }
+ /* Adjusted by 1, directi is used to bypass */
+ return preDiv;
+}
+
+/* Get postdivider (P) from PLL PDEC setting */
+static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg)
+{
+ uint32_t postDiv = 1;
+
+ /* Direct input is not used? */
+ if ((ctrlReg & SYSCON_SYSPLLCTRL_DIRECTO_MASK) == 0)
+ {
+ /* Decode PDEC value to get (P) post divider */
+ postDiv = 2 * pllDecodeP(pDecReg & 0x7F);
+ if (postDiv == 0)
+ {
+ postDiv = 2;
+ }
+ }
+ /* Adjusted by 1, directo is used to bypass */
+ return postDiv;
+}
+
+/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */
+static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg)
+{
+ uint32_t mMult = 1;
+
+ /* Decode MDEC value to get (M) multiplier */
+ mMult = pllDecodeM(mDecReg & 0x1FFFF);
+ if (mMult == 0)
+ {
+ mMult = 1;
+ }
+ return mMult;
+}
+
+
+
+/* ----------------------------------------------------------------------------
+ -- Core clock
+ ---------------------------------------------------------------------------- */
+
+uint32_t SystemCoreClock = DEFAULT_SYSTEM_CLOCK;
+
+/* ----------------------------------------------------------------------------
+ -- SystemInit()
+ ---------------------------------------------------------------------------- */
+
+void SystemInit (void) {
+#if ((__FPU_PRESENT == 1) && (__FPU_USED == 1))
+ SCB->CPACR |= ((3UL << 10*2) | (3UL << 11*2)); /* set CP10, CP11 Full Access */
+#endif /* ((__FPU_PRESENT == 1) && (__FPU_USED == 1)) */
+
+#if defined(__MCUXPRESSO)
+ extern void(*const g_pfnVectors[]) (void);
+ SCB->VTOR = (uint32_t) &g_pfnVectors;
+#else
+ extern void *__Vectors;
+ SCB->VTOR = (uint32_t) &__Vectors;
+#endif
+ SYSCON->ARMTRACECLKDIV = 0;
+/* Optionally enable RAM banks that may be off by default at reset */
+#if !defined(DONT_ENABLE_DISABLED_RAMBANKS)
+ SYSCON->AHBCLKCTRLSET[0] = SYSCON_AHBCLKCTRL_SRAM1_MASK | SYSCON_AHBCLKCTRL_SRAM2_MASK | SYSCON_AHBCLKCTRL_SRAM3_MASK;
+#endif
+}
+
+/* ----------------------------------------------------------------------------
+ -- SystemCoreClockUpdate()
+ ---------------------------------------------------------------------------- */
+
+void SystemCoreClockUpdate (void) {
+uint32_t clkRate = 0;
+ uint32_t prediv, postdiv;
+ uint64_t workRate;
+
+ switch (SYSCON->MAINCLKSELB & SYSCON_MAINCLKSELB_SEL_MASK)
+ {
+ case 0x00: /* MAINCLKSELA clock (main_clk_a)*/
+ switch (SYSCON->MAINCLKSELA & SYSCON_MAINCLKSELA_SEL_MASK)
+ {
+ case 0x00: /* FRO 12 MHz (fro_12m) */
+ clkRate = CLK_FRO_12MHZ;
+ break;
+ case 0x01: /* CLKIN (clk_in) */
+ clkRate = CLK_CLK_IN;
+ break;
+ case 0x02: /* Watchdog oscillator (wdt_clk) */
+ clkRate = getWdtOscFreq();
+ break;
+ default: /* = 0x03 = FRO 96 or 48 MHz (fro_hf) */
+ if (SYSCON->FROCTRL & SYSCON_FROCTRL_SEL_MASK)
+ {
+ clkRate = CLK_FRO_96MHZ;
+ }
+ else
+ {
+ clkRate = CLK_FRO_48MHZ;
+ }
+ break;
+ }
+ break;
+ case 0x02: /* System PLL clock (pll_clk)*/
+ switch (SYSCON->SYSPLLCLKSEL & SYSCON_SYSPLLCLKSEL_SEL_MASK)
+ {
+ case 0x00: /* FRO 12 MHz (fro_12m) */
+ clkRate = CLK_FRO_12MHZ;
+ break;
+ case 0x01: /* CLKIN (clk_in) */
+ clkRate = CLK_CLK_IN;
+ break;
+ case 0x02: /* Watchdog oscillator (wdt_clk) */
+ clkRate = getWdtOscFreq();
+ break;
+ case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */
+ clkRate = CLK_RTC_32K_CLK;
+ break;
+ default:
+ break;
+ }
+ if ((SYSCON->SYSPLLCTRL & SYSCON_SYSPLLCTRL_BYPASS_MASK) == 0)
+ {
+ /* PLL is not in bypass mode, get pre-divider, post-divider, and M divider */
+ prediv = findPllPreDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLNDEC);
+ postdiv = findPllPostDiv(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLPDEC);
+ /* Adjust input clock */
+ clkRate = clkRate / prediv;
+
+ /* MDEC used for rate */
+ workRate = (uint64_t)clkRate * (uint64_t)findPllMMult(SYSCON->SYSPLLCTRL, SYSCON->SYSPLLMDEC);
+ clkRate = workRate / ((uint64_t)postdiv);
+ clkRate = workRate * 2; /* PLL CCO output is divided by 2 before to M-Divider */
+ }
+ break;
+ case 0x03: /* RTC oscillator 32 kHz output (32k_clk) */
+ clkRate = CLK_RTC_32K_CLK;
+ break;
+ default:
+ break;
+ }
+ SystemCoreClock = clkRate / ((SYSCON->AHBCLKDIV & 0xFF) + 1);
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/device/system_LPC54628.h Tue Mar 20 16:56:18 2018 +0000
@@ -0,0 +1,123 @@
+/*
+** ###################################################################
+** Processor: LPC54628J512ET180
+** Compilers: Keil ARM C/C++ Compiler
+** GNU C Compiler
+** IAR ANSI C/C++ Compiler for ARM
+** MCUXpresso Compiler
+**
+** Reference manual: LPC546xx User manual Rev.1.9 5 June 2017
+** Version: rev. 1.2, 2017-06-08
+** Build: b170609
+**
+** Abstract:
+** Provides a system configuration function and a global variable that
+** contains the system frequency. It configures the device and initializes
+** the oscillator (PLL) that is part of the microcontroller device.
+**
+** Copyright 2016 Freescale Semiconductor, Inc.
+** Copyright 2016-2017 NXP
+** Redistribution and use in source and binary forms, with or without modification,
+** are permitted provided that the following conditions are met:
+**
+** 1. Redistributions of source code must retain the above copyright notice, this list
+** of conditions and the following disclaimer.
+**
+** 2. Redistributions in binary form must reproduce the above copyright notice, this
+** list of conditions and the following disclaimer in the documentation and/or
+** other materials provided with the distribution.
+**
+** 3. Neither the name of the copyright holder nor the names of its
+** contributors may be used to endorse or promote products derived from this
+** software without specific prior written permission.
+**
+** THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+** ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+** WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+** DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+** ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+** (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+** LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+** ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+** (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+** SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+**
+** http: www.nxp.com
+** mail: support@nxp.com
+**
+** Revisions:
+** - rev. 1.0 (2016-08-12)
+** Initial version.
+** - rev. 1.1 (2016-11-25)
+** Update CANFD and Classic CAN register.
+** Add MAC TIMERSTAMP registers.
+** - rev. 1.2 (2017-06-08)
+** Remove RTC_CTRL_RTC_OSC_BYPASS.
+** SYSCON_ARMTRCLKDIV rename to SYSCON_ARMTRACECLKDIV.
+** Remove RESET and HALT from SYSCON_AHBCLKDIV.
+**
+** ###################################################################
+*/
+
+/*!
+ * @file LPC54628
+ * @version 1.2
+ * @date 2017-06-08
+ * @brief Device specific configuration file for LPC54628 (header file)
+ *
+ * Provides a system configuration function and a global variable that contains
+ * the system frequency. It configures the device and initializes the oscillator
+ * (PLL) that is part of the microcontroller device.
+ */
+
+#ifndef _SYSTEM_LPC54628_H_
+#define _SYSTEM_LPC54628_H_ /**< Symbol preventing repeated inclusion */
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+#include <stdint.h>
+
+#define DEFAULT_SYSTEM_CLOCK 12000000u /* Default System clock value */
+#define CLK_RTC_32K_CLK 32768u /* RTC oscillator 32 kHz output (32k_clk */
+#define CLK_FRO_12MHZ 12000000u /* FRO 12 MHz (fro_12m) */
+#define CLK_FRO_48MHZ 48000000u /* FRO 48 MHz (fro_48m) */
+#define CLK_FRO_96MHZ 96000000u /* FRO 96 MHz (fro_96m) */
+#define CLK_CLK_IN 0u /* Default CLK_IN pin clock */
+
+
+/**
+ * @brief System clock frequency (core clock)
+ *
+ * The system clock frequency supplied to the SysTick timer and the processor
+ * core clock. This variable can be used by the user application to setup the
+ * SysTick timer or configure other parameters. It may also be used by debugger to
+ * query the frequency of the debug timer or configure the trace clock speed
+ * SystemCoreClock is initialized with a correct predefined value.
+ */
+extern uint32_t SystemCoreClock;
+
+/**
+ * @brief Setup the microcontroller system.
+ *
+ * Typically this function configures the oscillator (PLL) that is part of the
+ * microcontroller device. For systems with variable clock speed it also updates
+ * the variable SystemCoreClock. SystemInit is called from startup_device file.
+ */
+void SystemInit (void);
+
+/**
+ * @brief Updates the SystemCoreClock variable.
+ *
+ * It must be called whenever the core clock is changed during program
+ * execution. SystemCoreClockUpdate() evaluates the clock register settings and calculates
+ * the current core clock.
+ */
+void SystemCoreClockUpdate (void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* _SYSTEM_LPC54628_H_ */
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_adc.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_adc.c Tue Mar 20 16:56:18 2018 +0000 @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_adc.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_adc.h Tue Mar 20 16:56:18 2018 +0000
@@ -1,9 +1,12 @@
/*
+ * The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
+ * All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -46,8 +50,8 @@
/*! @name Driver version */
/*@{*/
-/*! @brief ADC driver version 2.0.0. */
-#define LPC_ADC_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*! @brief ADC driver version 2.1.0. */
+#define LPC_ADC_DRIVER_VERSION (MAKE_VERSION(2, 1, 0))
/*@}*/
/*!
@@ -150,7 +154,7 @@
typedef enum _adc_priority
{
kADC_PriorityLow = 0U, /*!< This sequence would be preempted when another sequence is started. */
- kADC_PriorityHigh = 1U, /*!< This sequence would preempt other sequence even when is is started. */
+ kADC_PriorityHigh = 1U, /*!< This sequence would preempt other sequence even when it is started. */
} adc_priority_t;
/*!
@@ -247,7 +251,7 @@
*/
typedef struct _adc_result_info
{
- uint32_t result; /*!< Keey the conversion data value. */
+ uint32_t result; /*!< Keep the conversion data value. */
adc_threshold_compare_status_t thresholdCompareStatus; /*!< Keep the threshold compare status. */
adc_threshold_crossing_status_t thresholdCorssingStatus; /*!< Keep the threshold crossing status. */
uint32_t channelNumber; /*!< Keep the channel number for this conversion. */
@@ -307,6 +311,7 @@
*/
bool ADC_DoSelfCalibration(ADC_Type *base);
+#if !(defined(FSL_FEATURE_ADC_HAS_NO_INSEL) && FSL_FEATURE_ADC_HAS_NO_INSEL)
/*!
* @brief Enable the internal temperature sensor measurement.
*
@@ -327,7 +332,7 @@
base->INSEL = (base->INSEL & ~ADC_INSEL_SEL_MASK) | ADC_INSEL_SEL(0);
}
}
-
+#endif /* FSL_FEATURE_ADC_HAS_NO_INSEL. */
/* @} */
/*!
@@ -611,13 +616,24 @@
}
/*!
- * @brief Enable the interrupt of shreshold compare event for each channel.
+ * @brief Enable the interrupt of threshold compare event for each channel.
+ * @deprecated Do not use this function. It has been superceded by @ADC_EnableThresholdCompareInterrupt
+ */
+static inline void ADC_EnableShresholdCompareInterrupt(ADC_Type *base,
+ uint32_t channel,
+ adc_threshold_interrupt_mode_t mode)
+{
+ base->INTEN = (base->INTEN & ~(0x3U << ((channel << 1U) + 3U))) | ((uint32_t)(mode) << ((channel << 1U) + 3U));
+}
+
+/*!
+ * @brief Enable the interrupt of threshold compare event for each channel.
*
* @param base ADC peripheral base address.
* @param channel Channel number.
* @param mode Interrupt mode for threshold compare event, see to #adc_threshold_interrupt_mode_t.
*/
-static inline void ADC_EnableShresholdCompareInterrupt(ADC_Type *base,
+static inline void ADC_EnableThresholdCompareInterrupt(ADC_Type *base,
uint32_t channel,
adc_threshold_interrupt_mode_t mode)
{
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_clock.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_clock.c Tue Mar 20 16:56:18 2018 +0000
@@ -1,10 +1,13 @@
/*
+ * The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright (c) 2016 - 2017 , NXP
* All rights reserved.
*
+ *
* Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -17,6 +20,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -150,6 +154,10 @@
static uint32_t findPllPostDiv(uint32_t ctrlReg, uint32_t pDecReg);
/* Get multiplier (M) from PLL MDEC and BYPASS_FBDIV2 settings */
static uint32_t findPllMMult(uint32_t ctrlReg, uint32_t mDecReg);
+/* Convert the binary to fractional part */
+static double Binary2Fractional(uint32_t binaryPart);
+/* Calculate the powerTimes' power of 2 */
+static uint32_t power2Cal(uint32_t powerTimes);
/* Get the greatest common divisor */
static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n);
/* Set PLL output based on desired output rate */
@@ -969,6 +977,25 @@
return mMult;
}
+/* Calculate the powerTimes' power of 2 */
+static uint32_t power2Cal(uint32_t powerTimes)
+{
+ if (powerTimes == 0)
+ return 1;
+ return 2 * power2Cal(powerTimes - 1);
+}
+
+/* Convert the binary to fractional part */
+static double Binary2Fractional(uint32_t binaryPart)
+{
+ double fractional = 0;
+ for (uint32_t i = 0; i <= 14; i++)
+ {
+ fractional += (double)((binaryPart >> i) & 0x1U) / (double)power2Cal(15 - i);
+ }
+ return fractional;
+}
+
/* Find greatest common divisor between m and n */
static uint32_t FindGreatestCommonDivisor(uint32_t m, uint32_t n)
{
@@ -1174,6 +1201,12 @@
s_Audio_Pll_Freq = CLOCK_GetAudioPLLOutFromSetup(pSetup);
}
+/* Update AUDIO Fractional PLL rate variable */
+static void CLOCK_GetAudioPLLOutFromAudioFracSetupUpdate(pll_setup_t *pSetup)
+{
+ s_Audio_Pll_Freq = CLOCK_GetAudioPLLOutFromFractSetup(pSetup);
+}
+
/* Update USB PLL rate variable */
static void CLOCK_GetUsbPLLOutFromSetupUpdate(const usb_pll_setup_t *pSetup)
{
@@ -1366,6 +1399,58 @@
return (uint32_t)workRate;
}
+/* Return Audio PLL output clock rate from audio fractioanl setup structure */
+uint32_t CLOCK_GetAudioPLLOutFromFractSetup(pll_setup_t *pSetup)
+{
+ uint32_t prediv, postdiv, inPllRate;
+ double workRate, mMultFactional;
+
+ inPllRate = CLOCK_GetAudioPLLInClockRate();
+ if ((pSetup->pllctrl & (1UL << SYSCON_SYSPLLCTRL_BYPASS_SHIFT)) == 0U)
+ {
+ /* PLL is not in bypass mode, get pre-divider, and M divider, post-divider. */
+ /*
+ * 1. Pre-divider
+ * Pre-divider is only available when the DIRECTI is disabled.
+ */
+ if (0U == (pSetup->pllctrl & SYSCON_AUDPLLCTRL_DIRECTI_MASK))
+ {
+ prediv = findPllPreDiv(pSetup->pllctrl, pSetup->pllndec);
+ }
+ else
+ {
+ prediv = 1U; /* The pre-divider is bypassed. */
+ }
+ /*
+ * 2. Post-divider
+ * Post-divider is only available when the DIRECTO is disabled.
+ */
+ if (0U == (pSetup->pllctrl & SYSCON_AUDPLLCTRL_DIRECTO_MASK))
+ {
+ postdiv = findPllPostDiv(pSetup->pllctrl, pSetup->pllpdec);
+ }
+ else
+ {
+ postdiv = 1U; /* The post-divider is bypassed. */
+ }
+ /* Adjust input clock */
+ inPllRate = inPllRate / prediv;
+
+ mMultFactional = (double)(pSetup->audpllfrac >> 15) + (double)Binary2Fractional(pSetup->audpllfrac & 0x7FFFU);
+ workRate = (double)inPllRate * (double)mMultFactional;
+
+ workRate = workRate / ((double)postdiv);
+ workRate = workRate * 2U; /* SYS PLL hardware cco is divide by 2 before to M-DIVIDER*/
+ }
+ else
+ {
+ /* In bypass mode */
+ workRate = (uint64_t)inPllRate;
+ }
+
+ return (uint32_t)workRate;
+}
+
/* Set the current PLL Rate */
void CLOCK_SetStoredPLLClockRate(uint32_t rate)
{
@@ -1609,6 +1694,48 @@
return kStatus_PLL_Success;
}
+/* Set AUDIO PLL output from AUDIO PLL fractional setup structure */
+pll_error_t CLOCK_SetupAudioPLLPrecFract(pll_setup_t *pSetup, uint32_t flagcfg)
+{
+ if ((SYSCON->AUDPLLCLKSEL & SYSCON_AUDPLLCLKSEL_SEL_MASK) == 0x01U)
+ {
+ /* Turn on the ext clock if system pll input select clk_in */
+ CLOCK_Enable_SysOsc(true);
+ }
+ /* Enable power VD3 for PLLs */
+ POWER_SetPLL();
+ /* Power off PLL during setup changes */
+ POWER_EnablePD(kPDRUNCFG_PD_AUDIO_PLL);
+
+ pSetup->flags = flagcfg;
+
+ /* Write PLL setup data */
+ SYSCON->AUDPLLCTRL = pSetup->pllctrl;
+ SYSCON->AUDPLLNDEC = pSetup->pllndec;
+ SYSCON->AUDPLLNDEC = pSetup->pllndec | (1U << SYSCON_SYSPLLNDEC_NREQ_SHIFT); /* latch */
+ SYSCON->AUDPLLPDEC = pSetup->pllpdec;
+ SYSCON->AUDPLLPDEC = pSetup->pllpdec | (1U << SYSCON_SYSPLLPDEC_PREQ_SHIFT); /* latch */
+ SYSCON->AUDPLLMDEC = pSetup->pllmdec;
+ SYSCON->AUDPLLFRAC = SYSCON_AUDPLLFRAC_SEL_EXT(0); /* enable fractional function */
+ SYSCON->AUDPLLFRAC = pSetup->audpllfrac;
+ SYSCON->AUDPLLFRAC = pSetup->audpllfrac | (1U << SYSCON_AUDPLLFRAC_REQ_SHIFT);
+
+ /* Enable peripheral states by setting low */
+ POWER_DisablePD(kPDRUNCFG_PD_AUDIO_PLL);
+
+ if ((pSetup->flags & PLL_SETUPFLAG_WAITLOCK) != 0U)
+ {
+ while (CLOCK_IsAudioPLLLocked() == false)
+ {
+ }
+ }
+
+ /* Update current programmed PLL rate var */
+ CLOCK_GetAudioPLLOutFromAudioFracSetupUpdate(pSetup);
+
+ return kStatus_PLL_Success;
+}
+
/* Set Audio PLL output based on the passed Audio PLL setup data */
pll_error_t CLOCK_SetupAudioPLLData(pll_config_t *pControl, pll_setup_t *pSetup)
{
@@ -1819,7 +1946,7 @@
}
/* If configure the USB HOST clock, VD5 power for USB PHY should be enable
- before the the PLL is working */
+ before the PLL is working */
/* Turn on the ext clock for usb pll input */
CLOCK_Enable_SysOsc(true);
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_clock.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_clock.h Tue Mar 20 16:56:18 2018 +0000
@@ -1,10 +1,13 @@
/*
+ * The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright (c) 2016 - 2017 , NXP
* All rights reserved.
*
+ *
* Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -17,6 +20,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -46,6 +50,12 @@
* Definitions
*****************************************************************************/
+/*! @name Driver version */
+/*@{*/
+/*! @brief CLOCK driver version 2.0.0. */
+#define FSL_CLOCK_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
/*! @brief Configure whether driver controls clock
*
* When set to 0, peripheral drivers will enable clock in initialize function
@@ -119,7 +129,7 @@
/*! @brief Clock ip name array for GPIO. */
#define GPIO_CLOCKS \
{ \
- kCLOCK_Gpio0, kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5 \
+ kCLOCK_Gpio0,kCLOCK_Gpio1, kCLOCK_Gpio2, kCLOCK_Gpio3, kCLOCK_Gpio4, kCLOCK_Gpio5 \
}
/*! @brief Clock ip name array for PINT. */
#define PINT_CLOCKS \
@@ -670,12 +680,12 @@
kFRO_HF_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 3),
kAUDIO_PLL_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 4),
kNONE_to_SDIO_CLK = MUX_A(CM_SDIOCLKSEL, 7),
-
+
kMCLK_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 0),
kLCDCLKIN_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 1),
kFRO_HF_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 2),
kNONE_to_LCD_CLK = MUX_A(CM_LCDCLKSEL, 3),
-
+
kMAIN_CLK_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 0),
kFRO12M_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 1),
kAUDIO_PLL_to_ASYNC_APB = MUX_A(CM_ASYNCAPB, 2),
@@ -988,10 +998,10 @@
SYSCON->PDRUNCFGCLR[0] |= SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK;
SYSCON->PDRUNCFGCLR[1] |= SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK;
}
-
+
else
{
- SYSCON->PDRUNCFGSET[0] = SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK;
+ SYSCON->PDRUNCFGSET[0] = SYSCON_PDRUNCFG_PDEN_VD2_ANA_MASK;
SYSCON->PDRUNCFGSET[1] = SYSCON_PDRUNCFG_PDEN_SYSOSC_MASK;
}
@@ -1134,6 +1144,12 @@
*/
uint32_t CLOCK_GetAudioPLLOutFromSetup(pll_setup_t *pSetup);
+/*! @brief Return System AUDIO PLL output clock rate from audio fractioanl setup structure
+ * @param pSetup : Pointer to a PLL setup structure
+ * @return System PLL output clock rate the setup structure will generate
+ */
+uint32_t CLOCK_GetAudioPLLOutFromFractSetup(pll_setup_t *pSetup);
+
/*! @brief Return System USB PLL output clock rate from setup structure
* @param pSetup : Pointer to a PLL setup structure
* @return System PLL output clock rate the setup structure will generate
@@ -1182,6 +1198,18 @@
*/
pll_error_t CLOCK_SetupAudioPLLPrec(pll_setup_t *pSetup, uint32_t flagcfg);
+/*! @brief Set AUDIO PLL output from AUDIOPLL setup structure using the Audio Fractional divider register(precise frequency)
+ * @param pSetup : Pointer to populated PLL setup structure
+* @param flagcfg : Flag configuration for PLL config structure
+ * @return PLL_ERROR_SUCCESS on success, or PLL setup error code
+ * @note This function will power off the PLL, setup the PLL with the
+ * new setup data, and then optionally powerup the AUDIO PLL, wait for PLL lock,
+ * and adjust system voltages to the new AUDIOPLL rate. The function will not
+ * alter any source clocks (ie, main systen clock) that may use the AUDIO PLL,
+ * so these should be setup prior to and after exiting the function.
+ */
+pll_error_t CLOCK_SetupAudioPLLPrecFract(pll_setup_t *pSetup, uint32_t flagcfg);
+
/**
* @brief Set PLL output from PLL setup structure (precise frequency)
* @param pSetup : Pointer to populated PLL setup structure
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_common.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_common.c Tue Mar 20 16:56:18 2018 +0000
@@ -1,78 +1,46 @@
/*
- * Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
- * Copyright 2016-2017 NXP
- *
- * Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
- *
- * o Redistributions of source code must retain the above copyright notice, this list
- * of conditions and the following disclaimer.
- *
- * o Redistributions in binary form must reproduce the above copyright notice, this
- * list of conditions and the following disclaimer in the documentation and/or
- * other materials provided with the distribution.
- *
- * o Neither the name of the copyright holder nor the names of its
- * contributors may be used to endorse or promote products derived from this
- * software without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
- * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
- * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
- * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
- * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
- * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
- * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
- * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
- * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
- * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
- */
+* The Clear BSD License
+* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
+ * Copyright 2016 NXP
+* All rights reserved.
+*
+*
+* Redistribution and use in source and binary forms, with or without modification,
+* are permitted (subject to the limitations in the disclaimer below) provided
+* that the following conditions are met:
+*
+* o Redistributions of source code must retain the above copyright notice, this list
+* of conditions and the following disclaimer.
+*
+* o Redistributions in binary form must reproduce the above copyright notice, this
+* list of conditions and the following disclaimer in the documentation and/or
+* other materials provided with the distribution.
+*
+* o Neither the name of the copyright holder nor the names of its
+* contributors may be used to endorse or promote products derived from this
+* software without specific prior written permission.
+*
+* NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
+* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+* ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+* LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+* SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+*/
#include "fsl_common.h"
-/* This is not needed for mbed */
-#if 0
-#include "fsl_debug_console.h"
-#ifndef NDEBUG
-#if (defined(__CC_ARM)) || (defined(__ICCARM__))
-void __aeabi_assert(const char *failedExpr, const char *file, int line)
-{
- PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" \n", failedExpr, file, line);
- for (;;)
- {
- __BKPT(0);
- }
-}
-#elif(defined(__REDLIB__))
-
-#if SDK_DEBUGCONSOLE
-void __assertion_failed(char *_Expr)
-{
- PRINTF("%s\n", _Expr);
- for (;;)
- {
- __asm("bkpt #0");
- }
-}
-#endif
-
-#elif(defined(__GNUC__))
-void __assert_func(const char *file, int line, const char *func, const char *failedExpr)
-{
- PRINTF("ASSERT ERROR \" %s \": file \"%s\" Line \"%d\" function name \"%s\" \n", failedExpr, file, line, func);
- for (;;)
- {
- __BKPT(0);
- }
-}
-#endif /* (defined(__CC_ARM)) || (defined (__ICCARM__)) */
-#endif /* NDEBUG */
-#endif
#ifndef __GIC_PRIO_BITS
+#if defined(ENABLE_RAM_VECTOR_TABLE)
uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler)
{
/* Addresses for VECTOR_TABLE and VECTOR_RAM come from the linker file */
-#if defined(__CC_ARM) || (defined(__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050))
+#if defined(__CC_ARM)
extern uint32_t Image$$VECTOR_ROM$$Base[];
extern uint32_t Image$$VECTOR_RAM$$Base[];
extern uint32_t Image$$RW_m_data$$Base[];
@@ -112,11 +80,18 @@
EnableGlobalIRQ(irqMaskValue);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
+
return ret;
}
-#endif
+#endif /* ENABLE_RAM_VECTOR_TABLE. */
+#endif /* __GIC_PRIO_BITS. */
-#ifndef CPU_QN908X
+#ifndef QN908XC_SERIES
#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
void EnableDeepSleepIRQ(IRQn_Type interrupt)
@@ -147,32 +122,5 @@
SYSCON->STARTERCLR[index] = 1u << intNumber;
}
#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
-#else
-void EnableDeepSleepIRQ(IRQn_Type interrupt)
-{
- uint32_t index = 0;
- uint32_t intNumber = (uint32_t)interrupt;
- while (intNumber >= 32u)
- {
- index++;
- intNumber -= 32u;
- }
- /* SYSCON->STARTERSET[index] = 1u << intNumber; */
- EnableIRQ(interrupt); /* also enable interrupt at NVIC */
-}
-
-void DisableDeepSleepIRQ(IRQn_Type interrupt)
-{
- uint32_t index = 0;
- uint32_t intNumber = (uint32_t)interrupt;
- while (intNumber >= 32u)
- {
- index++;
- intNumber -= 32u;
- }
-
- DisableIRQ(interrupt); /* also disable interrupt at NVIC */
- /* SYSCON->STARTERCLR[index] = 1u << intNumber; */
-}
-#endif /*CPU_QN908X */
+#endif /* QN908XC_SERIES */
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_common.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_common.h Tue Mar 20 16:56:18 2018 +0000
@@ -1,9 +1,12 @@
/*
+ * The Clear BSD License
* Copyright (c) 2015-2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
+ * All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -57,6 +61,12 @@
/*! @brief Construct the version number for drivers. */
#define MAKE_VERSION(major, minor, bugfix) (((major) << 16) | ((minor) << 8) | (bugfix))
+/*! @name Driver version */
+/*@{*/
+/*! @brief common driver version 2.0.0. */
+#define FSL_COMMON_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
/* Debug console type definition. */
#define DEBUG_CONSOLE_DEVICE_TYPE_NONE 0U /*!< No debug console. */
#define DEBUG_CONSOLE_DEVICE_TYPE_UART 1U /*!< Debug console base on UART. */
@@ -65,6 +75,7 @@
#define DEBUG_CONSOLE_DEVICE_TYPE_USBCDC 4U /*!< Debug console base on USBCDC. */
#define DEBUG_CONSOLE_DEVICE_TYPE_FLEXCOMM 5U /*!< Debug console base on USBCDC. */
#define DEBUG_CONSOLE_DEVICE_TYPE_IUART 6U /*!< Debug console base on i.MX UART. */
+#define DEBUG_CONSOLE_DEVICE_TYPE_VUSART 7U /*!< Debug console base on LPC_USART. */
/*! @brief Status group numbers. */
enum _status_groups
@@ -96,6 +107,8 @@
kStatusGroup_FLEXCOMM_I2C = 26, /*!< Group number for FLEXCOMM I2C status codes */
kStatusGroup_I2S = 27, /*!< Group number for I2S status codes */
kStatusGroup_IUART = 28, /*!< Group number for IUART status codes */
+ kStatusGroup_CSI = 29, /*!< Group number for CSI status codes */
+ kStatusGroup_MIPI_DSI = 30, /*!< Group number for MIPI DSI status codes */
kStatusGroup_SDRAMC = 35, /*!< Group number for SDRAMC status codes. */
kStatusGroup_POWER = 39, /*!< Group number for POWER status codes. */
kStatusGroup_ENET = 40, /*!< Group number for ENET status codes. */
@@ -120,11 +133,20 @@
kStatusGroup_CAAM = 63, /*!< Group number for CAAM status codes. */
kStatusGroup_ECSPI = 64, /*!< Group number for ECSPI status codes. */
kStatusGroup_USDHC = 65, /*!< Group number for USDHC status codes.*/
+ kStatusGroup_LPC_I2C = 66, /*!< Group number for LPC_I2C status codes.*/
+ kStatusGroup_DCP = 67, /*!< Group number for DCP status codes.*/
+ kStatusGroup_MSCAN = 68, /*!< Group number for MSCAN status codes.*/
kStatusGroup_ESAI = 69, /*!< Group number for ESAI status codes. */
kStatusGroup_FLEXSPI = 70, /*!< Group number for FLEXSPI status codes. */
+ kStatusGroup_MMDC = 71, /*!< Group number for MMDC status codes. */
+ kStatusGroup_MICFIL = 72, /*!< Group number for MIC status codes. */
+ kStatusGroup_SDMA = 73, /*!< Group number for SDMA status codes. */
+ kStatusGroup_ICS = 74, /*!< Group number for ICS status codes. */
+ kStatusGroup_SPDIF = 75, /*!< Group number for SPDIF status codes. */
kStatusGroup_NOTIFIER = 98, /*!< Group number for NOTIFIER status codes. */
kStatusGroup_DebugConsole = 99, /*!< Group number for debug console status codes. */
- kStatusGroup_ApplicationRangeStart = 100, /*!< Starting number for application groups. */
+ kStatusGroup_SEMC = 100, /*!< Group number for SEMC status codes. */
+ kStatusGroup_ApplicationRangeStart = 101, /*!< Starting number for application groups. */
};
/*! @brief Generic status return codes. */
@@ -168,7 +190,9 @@
/* @} */
/*! @brief Computes the number of elements in an array. */
+#if !defined(ARRAY_SIZE)
#define ARRAY_SIZE(x) (sizeof(x) / sizeof((x)[0]))
+#endif
/*! @name UINT16_MAX/UINT32_MAX value */
/* @{ */
@@ -316,77 +340,102 @@
******************************************************************************/
#if defined(__cplusplus)
-extern "C" {
+ extern "C"
+{
#endif
-/*!
- * @brief Enable specific interrupt.
- *
- * Enable the interrupt not routed from intmux.
- *
- * @param interrupt The IRQ number.
- */
-static inline void EnableIRQ(IRQn_Type interrupt)
-{
- if (NotAvail_IRQn == interrupt)
+ /*!
+ * @brief Enable specific interrupt.
+ *
+ * Enable LEVEL1 interrupt. For some devices, there might be multiple interrupt
+ * levels. For example, there are NVIC and intmux. Here the interrupts connected
+ * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
+ * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
+ * to NVIC first then routed to core.
+ *
+ * This function only enables the LEVEL1 interrupts. The number of LEVEL1 interrupts
+ * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
+ *
+ * @param interrupt The IRQ number.
+ * @retval kStatus_Success Interrupt enabled successfully
+ * @retval kStatus_Fail Failed to enable the interrupt
+ */
+ static inline status_t EnableIRQ(IRQn_Type interrupt)
{
- return;
- }
+ if (NotAvail_IRQn == interrupt)
+ {
+ return kStatus_Fail;
+ }
-#if defined(FSL_FEATURE_SOC_INTMUX_COUNT) && (FSL_FEATURE_SOC_INTMUX_COUNT > 0)
- if (interrupt < FSL_FEATURE_INTMUX_IRQ_START_INDEX)
+#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
+ if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
+ {
+ return kStatus_Fail;
+ }
#endif
- {
+
#if defined(__GIC_PRIO_BITS)
GIC_EnableIRQ(interrupt);
#else
NVIC_EnableIRQ(interrupt);
#endif
- }
-}
-
-/*!
- * @brief Disable specific interrupt.
- *
- * Disable the interrupt not routed from intmux.
- *
- * @param interrupt The IRQ number.
- */
-static inline void DisableIRQ(IRQn_Type interrupt)
-{
- if (NotAvail_IRQn == interrupt)
- {
- return;
+ return kStatus_Success;
}
-#if defined(FSL_FEATURE_SOC_INTMUX_COUNT) && (FSL_FEATURE_SOC_INTMUX_COUNT > 0)
- if (interrupt < FSL_FEATURE_INTMUX_IRQ_START_INDEX)
+ /*!
+ * @brief Disable specific interrupt.
+ *
+ * Disable LEVEL1 interrupt. For some devices, there might be multiple interrupt
+ * levels. For example, there are NVIC and intmux. Here the interrupts connected
+ * to NVIC are the LEVEL1 interrupts, because they are routed to the core directly.
+ * The interrupts connected to intmux are the LEVEL2 interrupts, they are routed
+ * to NVIC first then routed to core.
+ *
+ * This function only disables the LEVEL1 interrupts. The number of LEVEL1 interrupts
+ * is indicated by the feature macro FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS.
+ *
+ * @param interrupt The IRQ number.
+ * @retval kStatus_Success Interrupt disabled successfully
+ * @retval kStatus_Fail Failed to disable the interrupt
+ */
+ static inline status_t DisableIRQ(IRQn_Type interrupt)
+ {
+ if (NotAvail_IRQn == interrupt)
+ {
+ return kStatus_Fail;
+ }
+
+#if defined(FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS) && (FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS > 0)
+ if (interrupt >= FSL_FEATURE_NUMBER_OF_LEVEL1_INT_VECTORS)
+ {
+ return kStatus_Fail;
+ }
#endif
- {
+
#if defined(__GIC_PRIO_BITS)
GIC_DisableIRQ(interrupt);
#else
- NVIC_DisableIRQ(interrupt);
+ NVIC_DisableIRQ(interrupt);
#endif
+ return kStatus_Success;
}
-}
-/*!
- * @brief Disable the global IRQ
- *
- * Disable the global interrupt and return the current primask register. User is required to provided the primask
- * register for the EnableGlobalIRQ().
- *
- * @return Current primask value.
- */
-static inline uint32_t DisableGlobalIRQ(void)
-{
+ /*!
+ * @brief Disable the global IRQ
+ *
+ * Disable the global interrupt and return the current primask register. User is required to provided the primask
+ * register for the EnableGlobalIRQ().
+ *
+ * @return Current primask value.
+ */
+ static inline uint32_t DisableGlobalIRQ(void)
+ {
#if defined(CPSR_I_Msk)
- uint32_t cpsr = __get_CPSR() & CPSR_I_Msk;
+ uint32_t cpsr = __get_CPSR() & CPSR_I_Msk;
- __disable_irq();
+ __disable_irq();
- return cpsr;
+ return cpsr;
#else
uint32_t regPrimask = __get_PRIMASK();
@@ -394,66 +443,68 @@
return regPrimask;
#endif
-}
+ }
-/*!
- * @brief Enaable the global IRQ
- *
- * Set the primask register with the provided primask value but not just enable the primask. The idea is for the
- * convinience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to
- * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.
- *
- * @param primask value of primask register to be restored. The primask value is supposed to be provided by the
- * DisableGlobalIRQ().
- */
-static inline void EnableGlobalIRQ(uint32_t primask)
-{
+ /*!
+ * @brief Enaable the global IRQ
+ *
+ * Set the primask register with the provided primask value but not just enable the primask. The idea is for the
+ * convinience of integration of RTOS. some RTOS get its own management mechanism of primask. User is required to
+ * use the EnableGlobalIRQ() and DisableGlobalIRQ() in pair.
+ *
+ * @param primask value of primask register to be restored. The primask value is supposed to be provided by the
+ * DisableGlobalIRQ().
+ */
+ static inline void EnableGlobalIRQ(uint32_t primask)
+ {
#if defined(CPSR_I_Msk)
- __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask);
+ __set_CPSR((__get_CPSR() & ~CPSR_I_Msk) | primask);
#else
__set_PRIMASK(primask);
#endif
-}
+ }
-/*!
- * @brief install IRQ handler
- *
- * @param irq IRQ number
- * @param irqHandler IRQ handler address
- * @return The old IRQ handler address
- */
-uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
+#if defined(ENABLE_RAM_VECTOR_TABLE)
+ /*!
+ * @brief install IRQ handler
+ *
+ * @param irq IRQ number
+ * @param irqHandler IRQ handler address
+ * @return The old IRQ handler address
+ */
+ uint32_t InstallIRQHandler(IRQn_Type irq, uint32_t irqHandler);
+#endif /* ENABLE_RAM_VECTOR_TABLE. */
#if (defined(FSL_FEATURE_SOC_SYSCON_COUNT) && (FSL_FEATURE_SOC_SYSCON_COUNT > 0))
-/*!
- * @brief Enable specific interrupt for wake-up from deep-sleep mode.
- *
- * Enable the interrupt for wake-up from deep sleep mode.
- * Some interrupts are typically used in sleep mode only and will not occur during
- * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
- * those clocks (significantly increasing power consumption in the reduced power mode),
- * making these wake-ups possible.
- *
- * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internally).
- *
- * @param interrupt The IRQ number.
- */
-void EnableDeepSleepIRQ(IRQn_Type interrupt);
+ /*!
+ * @brief Enable specific interrupt for wake-up from deep-sleep mode.
+ *
+ * Enable the interrupt for wake-up from deep sleep mode.
+ * Some interrupts are typically used in sleep mode only and will not occur during
+ * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
+ * those clocks (significantly increasing power consumption in the reduced power mode),
+ * making these wake-ups possible.
+ *
+ * @note This function also enables the interrupt in the NVIC (EnableIRQ() is called internally).
+ *
+ * @param interrupt The IRQ number.
+ */
+ void EnableDeepSleepIRQ(IRQn_Type interrupt);
-/*!
- * @brief Disable specific interrupt for wake-up from deep-sleep mode.
- *
- * Disable the interrupt for wake-up from deep sleep mode.
- * Some interrupts are typically used in sleep mode only and will not occur during
- * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
- * those clocks (significantly increasing power consumption in the reduced power mode),
- * making these wake-ups possible.
- *
- * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internally).
- *
- * @param interrupt The IRQ number.
- */
-void DisableDeepSleepIRQ(IRQn_Type interrupt);
+ /*!
+ * @brief Disable specific interrupt for wake-up from deep-sleep mode.
+ *
+ * Disable the interrupt for wake-up from deep sleep mode.
+ * Some interrupts are typically used in sleep mode only and will not occur during
+ * deep-sleep mode because relevant clocks are stopped. However, it is possible to enable
+ * those clocks (significantly increasing power consumption in the reduced power mode),
+ * making these wake-ups possible.
+ *
+ * @note This function also disables the interrupt in the NVIC (DisableIRQ() is called internally).
+ *
+ * @param interrupt The IRQ number.
+ */
+ void DisableDeepSleepIRQ(IRQn_Type interrupt);
#endif /* FSL_FEATURE_SOC_SYSCON_COUNT */
#if defined(__cplusplus)
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_crc.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_crc.c Tue Mar 20 16:56:18 2018 +0000 @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_crc.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_crc.h Tue Mar 20 16:56:18 2018 +0000 @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015-2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_ctimer.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_ctimer.c Tue Mar 20 16:56:18 2018 +0000
@@ -1,9 +1,12 @@
/*
+ * The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
+ * All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -302,7 +306,11 @@
}
else
{
+#if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT
for (i = 0; i <= CTIMER_IR_CR3INT_SHIFT; i++)
+#else
+ for (i = 0; i <= CTIMER_IR_CR2INT_SHIFT; i++)
+#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */
{
mask = 0x01 << i;
/* For each status flag bit that was set call the callback function if it is valid */
@@ -312,6 +320,11 @@
}
}
}
+ /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
}
/* IRQ handler functions overloading weak symbols in the startup */
@@ -319,6 +332,11 @@
void CTIMER0_DriverIRQHandler(void)
{
CTIMER_GenericIRQHandler(0);
+ /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
}
#endif
@@ -326,6 +344,11 @@
void CTIMER1_DriverIRQHandler(void)
{
CTIMER_GenericIRQHandler(1);
+ /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
}
#endif
@@ -333,6 +356,11 @@
void CTIMER2_DriverIRQHandler(void)
{
CTIMER_GenericIRQHandler(2);
+ /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
}
#endif
@@ -340,6 +368,11 @@
void CTIMER3_DriverIRQHandler(void)
{
CTIMER_GenericIRQHandler(3);
+ /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
}
#endif
@@ -347,6 +380,11 @@
void CTIMER4_DriverIRQHandler(void)
{
CTIMER_GenericIRQHandler(4);
+ /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
}
#endif
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_ctimer.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_ctimer.h Tue Mar 20 16:56:18 2018 +0000
@@ -1,9 +1,12 @@
/*
+ * The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
+ * All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -54,7 +58,9 @@
kCTIMER_Capture_0 = 0U, /*!< Timer capture channel 0 */
kCTIMER_Capture_1, /*!< Timer capture channel 1 */
kCTIMER_Capture_2, /*!< Timer capture channel 2 */
- kCTIMER_Capture_3 /*!< Timer capture channel 3 */
+#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3
+ kCTIMER_Capture_3 /*!< Timer capture channel 3 */
+#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */
} ctimer_capture_channel_t;
/*! @brief List of capture edge options */
@@ -102,7 +108,9 @@
kCTIMER_Capture0InterruptEnable = CTIMER_CCR_CAP0I_MASK, /*!< Capture 0 interrupt */
kCTIMER_Capture1InterruptEnable = CTIMER_CCR_CAP1I_MASK, /*!< Capture 1 interrupt */
kCTIMER_Capture2InterruptEnable = CTIMER_CCR_CAP2I_MASK, /*!< Capture 2 interrupt */
+#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3
kCTIMER_Capture3InterruptEnable = CTIMER_CCR_CAP3I_MASK, /*!< Capture 3 interrupt */
+#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */
} ctimer_interrupt_enable_t;
/*! @brief List of Timer flags */
@@ -115,7 +123,9 @@
kCTIMER_Capture0Flag = CTIMER_IR_CR0INT_MASK, /*!< Capture 0 interrupt flag */
kCTIMER_Capture1Flag = CTIMER_IR_CR1INT_MASK, /*!< Capture 1 interrupt flag */
kCTIMER_Capture2Flag = CTIMER_IR_CR2INT_MASK, /*!< Capture 2 interrupt flag */
+#if defined(FSL_FEATURE_CTIMER_HAS_IR_CR3INT) && FSL_FEATURE_CTIMER_HAS_IR_CR3INT
kCTIMER_Capture3Flag = CTIMER_IR_CR3INT_MASK, /*!< Capture 3 interrupt flag */
+#endif /* FSL_FEATURE_CTIMER_HAS_IR_CR3INT */
} ctimer_status_flags_t;
typedef void (*ctimer_callback_t)(uint32_t flags);
@@ -126,9 +136,9 @@
*/
typedef enum
{
- kCTIMER_SingleCallback, /*!< Single Callback type where there is only one callback for the timer.
+ kCTIMER_SingleCallback, /*!< Single Callback type where there is only one callback for the timer.
based on the status flags different channels needs to be handled differently */
- kCTIMER_MultipleCallback /*!< Multiple Callback type where there can be 8 valid callbacks, one per channel.
+ kCTIMER_MultipleCallback /*!< Multiple Callback type where there can be 8 valid callbacks, one per channel.
for both match/capture */
} ctimer_callback_type_t;
@@ -306,10 +316,14 @@
static inline void CTIMER_EnableInterrupts(CTIMER_Type *base, uint32_t mask)
{
/* Enable match interrupts */
- base->MCR |= mask;
+ base->MCR |= mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK);
/* Enable capture interrupts */
- base->CCR |= mask;
+ base->CCR |= mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK
+#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3
+ | CTIMER_CCR_CAP3I_MASK
+#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */
+ );
}
/*!
@@ -322,10 +336,14 @@
static inline void CTIMER_DisableInterrupts(CTIMER_Type *base, uint32_t mask)
{
/* Disable match interrupts */
- base->MCR &= ~mask;
+ base->MCR &= ~(mask & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK));
/* Disable capture interrupts */
- base->CCR &= ~mask;
+ base->CCR &= ~(mask & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK
+#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3
+ | CTIMER_CCR_CAP3I_MASK
+#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */
+ ));
}
/*!
@@ -342,11 +360,14 @@
/* Get all the match interrupts enabled */
enabledIntrs =
- base->MCR & (CTIMER_MCR_MR0I_SHIFT | CTIMER_MCR_MR1I_SHIFT | CTIMER_MCR_MR2I_SHIFT | CTIMER_MCR_MR3I_SHIFT);
+ base->MCR & (CTIMER_MCR_MR0I_MASK | CTIMER_MCR_MR1I_MASK | CTIMER_MCR_MR2I_MASK | CTIMER_MCR_MR3I_MASK);
/* Get all the capture interrupts enabled */
- enabledIntrs |=
- base->CCR & (CTIMER_CCR_CAP0I_SHIFT | CTIMER_CCR_CAP1I_SHIFT | CTIMER_CCR_CAP2I_SHIFT | CTIMER_CCR_CAP3I_SHIFT);
+ enabledIntrs |= base->CCR & (CTIMER_CCR_CAP0I_MASK | CTIMER_CCR_CAP1I_MASK | CTIMER_CCR_CAP2I_MASK
+#if defined(FSL_FEATURE_CTIMER_HAS_CCR_CAP3) && FSL_FEATURE_CTIMER_HAS_CCR_CAP3
+ | CTIMER_CCR_CAP3I_MASK
+#endif /* FSL_FEATURE_CTIMER_HAS_CCR_CAP3 */
+ );
return enabledIntrs;
}
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dma.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dma.c Tue Mar 20 16:56:18 2018 +0000
@@ -1,9 +1,12 @@
/*
+ * The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
+ * All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -111,11 +115,9 @@
{
assert((channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS) && (NULL != trigger));
- uint32_t tmp = (
- DMA_CHANNEL_CFG_HWTRIGEN_MASK | DMA_CHANNEL_CFG_TRIGPOL_MASK | DMA_CHANNEL_CFG_TRIGTYPE_MASK |
- DMA_CHANNEL_CFG_TRIGBURST_MASK | DMA_CHANNEL_CFG_BURSTPOWER_MASK | DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK |
- DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK
- );
+ uint32_t tmp = (DMA_CHANNEL_CFG_HWTRIGEN_MASK | DMA_CHANNEL_CFG_TRIGPOL_MASK | DMA_CHANNEL_CFG_TRIGTYPE_MASK |
+ DMA_CHANNEL_CFG_TRIGBURST_MASK | DMA_CHANNEL_CFG_BURSTPOWER_MASK |
+ DMA_CHANNEL_CFG_SRCBURSTWRAP_MASK | DMA_CHANNEL_CFG_DSTBURSTWRAP_MASK);
tmp = base->CHANNEL[channel].CFG & (~tmp);
tmp |= (uint32_t)(trigger->type) | (uint32_t)(trigger->burst) | (uint32_t)(trigger->wrap);
base->CHANNEL[channel].CFG = tmp;
@@ -132,7 +134,7 @@
{
assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
- /* NOTE: when descriptors are chained, ACTIVE bit is set for whole chain. It makes
+ /* NOTE: when descriptors are chained, ACTIVE bit is set for whole chain. It makes
* impossible to distinguish between:
* - transfer finishes (represented by value '0x3FF')
* - and remaining 1024 bytes to transfer (value 0x3FF)
@@ -140,10 +142,9 @@
* If you decide to use this function, please use 1023 transfers as maximal value */
/* Channel not active (transfer finished) and value is 0x3FF - nothing to transfer */
- if (
- (!(base->COMMON[DMA_CHANNEL_GROUP(channel)].ACTIVE & (1U << (DMA_CHANNEL_INDEX(channel))))) &&
- (0x3FF == ((base->CHANNEL[channel].XFERCFG & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >> DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT))
- )
+ if ((!(base->COMMON[DMA_CHANNEL_GROUP(channel)].ACTIVE & (1U << (DMA_CHANNEL_INDEX(channel))))) &&
+ (0x3FF == ((base->CHANNEL[channel].XFERCFG & DMA_CHANNEL_XFERCFG_XFERCOUNT_MASK) >>
+ DMA_CHANNEL_XFERCFG_XFERCOUNT_SHIFT)))
{
return 0;
}
@@ -152,12 +153,7 @@
}
static void DMA_SetupDescriptor(
- dma_descriptor_t *desc,
- uint32_t xfercfg,
- void *srcEndAddr,
- void *dstEndAddr,
- void *nextDesc
-)
+ dma_descriptor_t *desc, uint32_t xfercfg, void *srcEndAddr, void *dstEndAddr, void *nextDesc)
{
desc->xfercfg = xfercfg;
desc->srcEndAddr = srcEndAddr;
@@ -166,10 +162,7 @@
}
/* Verify and convert dma_xfercfg_t to XFERCFG register */
-static void DMA_SetupXferCFG(
- dma_xfercfg_t *xfercfg,
- uint32_t *xfercfg_addr
-)
+static void DMA_SetupXferCFG(dma_xfercfg_t *xfercfg, uint32_t *xfercfg_addr)
{
assert(xfercfg != NULL);
/* check source increment */
@@ -187,9 +180,9 @@
/* set reload - allow link to next descriptor */
xfer |= DMA_CHANNEL_XFERCFG_RELOAD(xfercfg->reload ? 1 : 0);
/* set swtrig flag - start transfer */
- xfer |= DMA_CHANNEL_XFERCFG_SWTRIG(xfercfg->swtrig? 1 : 0);
+ xfer |= DMA_CHANNEL_XFERCFG_SWTRIG(xfercfg->swtrig ? 1 : 0);
/* set transfer count */
- xfer |= DMA_CHANNEL_XFERCFG_CLRTRIG(xfercfg->clrtrig? 1 : 0);
+ xfer |= DMA_CHANNEL_XFERCFG_CLRTRIG(xfercfg->clrtrig ? 1 : 0);
/* set INTA */
xfer |= DMA_CHANNEL_XFERCFG_SETINTA(xfercfg->intA ? 1 : 0);
/* set INTB */
@@ -210,13 +203,7 @@
*xfercfg_addr = xfer;
}
-void DMA_CreateDescriptor(
- dma_descriptor_t *desc,
- dma_xfercfg_t *xfercfg,
- void *srcAddr,
- void *dstAddr,
- void *nextDesc
-)
+void DMA_CreateDescriptor(dma_descriptor_t *desc, dma_xfercfg_t *xfercfg, void *srcAddr, void *dstAddr, void *nextDesc)
{
uint32_t xfercfg_reg = 0;
@@ -229,11 +216,9 @@
DMA_SetupXferCFG(xfercfg, &xfercfg_reg);
/* Set descriptor structure */
- DMA_SetupDescriptor(desc, xfercfg_reg,
- (uint8_t*)srcAddr + (xfercfg->srcInc * xfercfg->byteWidth * (xfercfg->transferCount - 1)),
- (uint8_t*)dstAddr + (xfercfg->dstInc * xfercfg->byteWidth * (xfercfg->transferCount - 1)),
- nextDesc
- );
+ DMA_SetupDescriptor(
+ desc, xfercfg_reg, (uint8_t *)srcAddr + (xfercfg->srcInc * xfercfg->byteWidth * (xfercfg->transferCount - 1)),
+ (uint8_t *)dstAddr + (xfercfg->dstInc * xfercfg->byteWidth * (xfercfg->transferCount - 1)), nextDesc);
}
void DMA_AbortTransfer(dma_handle_t *handle)
@@ -242,7 +227,8 @@
DMA_DisableChannel(handle->base, handle->channel);
while (handle->base->COMMON[DMA_CHANNEL_GROUP(handle->channel)].BUSY & (1U << DMA_CHANNEL_INDEX(handle->channel)))
- { }
+ {
+ }
handle->base->COMMON[DMA_CHANNEL_GROUP(handle->channel)].ABORT |= 1U << DMA_CHANNEL_INDEX(handle->channel);
DMA_EnableChannel(handle->base, handle->channel);
}
@@ -272,12 +258,12 @@
}
void DMA_PrepareTransfer(dma_transfer_config_t *config,
- void *srcAddr,
- void *dstAddr,
- uint32_t byteWidth,
- uint32_t transferBytes,
- dma_transfer_type_t type,
- void *nextDesc)
+ void *srcAddr,
+ void *dstAddr,
+ uint32_t byteWidth,
+ uint32_t transferBytes,
+ dma_transfer_type_t type,
+ void *nextDesc)
{
uint32_t xfer_count;
assert((NULL != config) && (NULL != srcAddr) && (NULL != dstAddr));
@@ -290,35 +276,35 @@
memset(config, 0, sizeof(*config));
switch (type)
{
- case kDMA_MemoryToMemory:
- config->xfercfg.srcInc = 1;
- config->xfercfg.dstInc = 1;
- config->isPeriph = false;
- break;
- case kDMA_PeripheralToMemory:
- /* Peripheral register - source doesn't increment */
- config->xfercfg.srcInc = 0;
- config->xfercfg.dstInc = 1;
- config->isPeriph = true;
- break;
- case kDMA_MemoryToPeripheral:
- /* Peripheral register - destination doesn't increment */
- config->xfercfg.srcInc = 1;
- config->xfercfg.dstInc = 0;
- config->isPeriph = true;
- break;
- case kDMA_StaticToStatic:
- config->xfercfg.srcInc = 0;
- config->xfercfg.dstInc = 0;
- config->isPeriph = true;
- break;
- default:
- return;
+ case kDMA_MemoryToMemory:
+ config->xfercfg.srcInc = 1;
+ config->xfercfg.dstInc = 1;
+ config->isPeriph = false;
+ break;
+ case kDMA_PeripheralToMemory:
+ /* Peripheral register - source doesn't increment */
+ config->xfercfg.srcInc = 0;
+ config->xfercfg.dstInc = 1;
+ config->isPeriph = true;
+ break;
+ case kDMA_MemoryToPeripheral:
+ /* Peripheral register - destination doesn't increment */
+ config->xfercfg.srcInc = 1;
+ config->xfercfg.dstInc = 0;
+ config->isPeriph = true;
+ break;
+ case kDMA_StaticToStatic:
+ config->xfercfg.srcInc = 0;
+ config->xfercfg.dstInc = 0;
+ config->isPeriph = true;
+ break;
+ default:
+ return;
}
- config->dstAddr = (uint8_t*)dstAddr;
- config->srcAddr = (uint8_t*)srcAddr;
- config->nextDesc = (uint8_t*)nextDesc;
+ config->dstAddr = (uint8_t *)dstAddr;
+ config->srcAddr = (uint8_t *)srcAddr;
+ config->nextDesc = (uint8_t *)nextDesc;
config->xfercfg.transferCount = xfer_count;
config->xfercfg.byteWidth = byteWidth;
config->xfercfg.intA = true;
@@ -333,7 +319,7 @@
/* Previous transfer has not finished */
if (DMA_ChannelIsActive(handle->base, handle->channel))
{
- return kStatus_DMA_Busy;
+ return kStatus_DMA_Busy;
}
/* enable/disable peripheral request */
@@ -346,10 +332,8 @@
DMA_DisableChannelPeriphRq(handle->base, handle->channel);
}
- DMA_CreateDescriptor(
- &s_dma_descriptor_table[ handle->channel ], &config->xfercfg,
- config->srcAddr, config->dstAddr, config->nextDesc
- );
+ DMA_CreateDescriptor(&s_dma_descriptor_table[handle->channel], &config->xfercfg, config->srcAddr, config->dstAddr,
+ config->nextDesc);
return kStatus_Success;
}
@@ -364,18 +348,18 @@
/* If HW trigger is enabled - disable SW trigger */
if (handle->base->CHANNEL[handle->channel].CFG & DMA_CHANNEL_CFG_HWTRIGEN_MASK)
{
- s_dma_descriptor_table[ handle->channel ].xfercfg &= ~(DMA_CHANNEL_XFERCFG_SWTRIG_MASK);
+ s_dma_descriptor_table[handle->channel].xfercfg &= ~(DMA_CHANNEL_XFERCFG_SWTRIG_MASK);
}
/* Otherwise enable SW trigger */
else
{
- s_dma_descriptor_table[ handle->channel ].xfercfg |= DMA_CHANNEL_XFERCFG_SWTRIG_MASK;
+ s_dma_descriptor_table[handle->channel].xfercfg |= DMA_CHANNEL_XFERCFG_SWTRIG_MASK;
}
/* Set channel XFERCFG register according first channel descriptor. */
- handle->base->CHANNEL[handle->channel].XFERCFG = s_dma_descriptor_table[ handle->channel ].xfercfg;
- /* At this moment, the channel ACTIVE bit is set and application cannot modify
- * or start another transfer using this channel. Channel ACTIVE bit is cleared by
+ handle->base->CHANNEL[handle->channel].XFERCFG = s_dma_descriptor_table[handle->channel].xfercfg;
+ /* At this moment, the channel ACTIVE bit is set and application cannot modify
+ * or start another transfer using this channel. Channel ACTIVE bit is cleared by
* 'AbortTransfer' function or when the transfer finishes */
}
@@ -416,6 +400,20 @@
(handle->callback)(handle, handle->userData, true, kDMA_IntB);
}
}
+ /* Error flag */
+ if (handle->base->COMMON[channel_group].ERRINT & (1U << channel_index))
+ {
+ /* Clear error flag */
+ handle->base->COMMON[channel_group].ERRINT = 1U << channel_index;
+ if (handle->callback)
+ {
+ (handle->callback)(handle, handle->userData, false, kDMA_IntError);
+ }
+ }
}
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
}
-
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dma.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dma.h Tue Mar 20 16:56:18 2018 +0000
@@ -1,9 +1,12 @@
/*
+ * The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
+ * All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -56,17 +60,18 @@
/* Channel index in channel group. channel_index = (channel % 32) */
#define DMA_CHANNEL_INDEX(channel) (((uint8_t)channel) & 0x1F)
-
/*! @brief DMA descriptor structure */
-typedef struct _dma_descriptor {
- uint32_t xfercfg; /*!< Transfer configuration */
- void *srcEndAddr; /*!< Last source address of DMA transfer */
- void *dstEndAddr; /*!< Last destination address of DMA transfer */
- void *linkToNextDesc; /*!< Address of next DMA descriptor in chain */
+typedef struct _dma_descriptor
+{
+ uint32_t xfercfg; /*!< Transfer configuration */
+ void *srcEndAddr; /*!< Last source address of DMA transfer */
+ void *dstEndAddr; /*!< Last destination address of DMA transfer */
+ void *linkToNextDesc; /*!< Address of next DMA descriptor in chain */
} dma_descriptor_t;
/*! @brief DMA transfer configuration */
-typedef struct _dma_xfercfg {
+typedef struct _dma_xfercfg
+{
bool valid; /*!< Descriptor is ready to transfer */
bool reload; /*!< Reload channel configuration register after
current descriptor is exhausted */
@@ -82,55 +87,74 @@
} dma_xfercfg_t;
/*! @brief DMA channel priority */
-typedef enum _dma_priority {
- kDMA_ChannelPriority0 = 0, /*!< Highest channel priority - priority 0 */
- kDMA_ChannelPriority1, /*!< Channel priority 1 */
- kDMA_ChannelPriority2, /*!< Channel priority 2 */
- kDMA_ChannelPriority3, /*!< Channel priority 3 */
- kDMA_ChannelPriority4, /*!< Channel priority 4 */
- kDMA_ChannelPriority5, /*!< Channel priority 5 */
- kDMA_ChannelPriority6, /*!< Channel priority 6 */
- kDMA_ChannelPriority7, /*!< Lowest channel priority - priority 7 */
+typedef enum _dma_priority
+{
+ kDMA_ChannelPriority0 = 0, /*!< Highest channel priority - priority 0 */
+ kDMA_ChannelPriority1, /*!< Channel priority 1 */
+ kDMA_ChannelPriority2, /*!< Channel priority 2 */
+ kDMA_ChannelPriority3, /*!< Channel priority 3 */
+ kDMA_ChannelPriority4, /*!< Channel priority 4 */
+ kDMA_ChannelPriority5, /*!< Channel priority 5 */
+ kDMA_ChannelPriority6, /*!< Channel priority 6 */
+ kDMA_ChannelPriority7, /*!< Lowest channel priority - priority 7 */
} dma_priority_t;
/*! @brief DMA interrupt flags */
-typedef enum _dma_int {
- kDMA_IntA, /*!< DMA interrupt flag A */
- kDMA_IntB, /*!< DMA interrupt flag B */
+typedef enum _dma_int
+{
+ kDMA_IntA, /*!< DMA interrupt flag A */
+ kDMA_IntB, /*!< DMA interrupt flag B */
+ kDMA_IntError, /*!< DMA interrupt flag error */
} dma_irq_t;
/*! @brief DMA trigger type*/
-typedef enum _dma_trigger_type {
- kDMA_NoTrigger = 0, /*!< Trigger is disabled */
+typedef enum _dma_trigger_type
+{
+ kDMA_NoTrigger = 0, /*!< Trigger is disabled */
kDMA_LowLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1), /*!< Low level active trigger */
- kDMA_HighLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1) | DMA_CHANNEL_CFG_TRIGPOL(1), /*!< High level active trigger */
+ kDMA_HighLevelTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGTYPE(1) |
+ DMA_CHANNEL_CFG_TRIGPOL(1), /*!< High level active trigger */
kDMA_FallingEdgeTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1), /*!< Falling edge active trigger */
- kDMA_RisingEdgeTrigger = DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGPOL(1), /*!< Rising edge active trigger */
+ kDMA_RisingEdgeTrigger =
+ DMA_CHANNEL_CFG_HWTRIGEN(1) | DMA_CHANNEL_CFG_TRIGPOL(1), /*!< Rising edge active trigger */
} dma_trigger_type_t;
/*! @brief DMA trigger burst */
-typedef enum _dma_trigger_burst {
- kDMA_SingleTransfer = 0, /*!< Single transfer */
- kDMA_LevelBurstTransfer = DMA_CHANNEL_CFG_TRIGBURST(1), /*!< Burst transfer driven by level trigger */
- kDMA_EdgeBurstTransfer1 = DMA_CHANNEL_CFG_TRIGBURST(1), /*!< Perform 1 transfer by edge trigger */
- kDMA_EdgeBurstTransfer2 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(1), /*!< Perform 2 transfers by edge trigger */
- kDMA_EdgeBurstTransfer4 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(2), /*!< Perform 4 transfers by edge trigger */
- kDMA_EdgeBurstTransfer8 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(3), /*!< Perform 8 transfers by edge trigger */
- kDMA_EdgeBurstTransfer16 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(4), /*!< Perform 16 transfers by edge trigger */
- kDMA_EdgeBurstTransfer32 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(5), /*!< Perform 32 transfers by edge trigger */
- kDMA_EdgeBurstTransfer64 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(6), /*!< Perform 64 transfers by edge trigger */
- kDMA_EdgeBurstTransfer128 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(7), /*!< Perform 128 transfers by edge trigger */
- kDMA_EdgeBurstTransfer256 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(8), /*!< Perform 256 transfers by edge trigger */
- kDMA_EdgeBurstTransfer512 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(9), /*!< Perform 512 transfers by edge trigger */
- kDMA_EdgeBurstTransfer1024 = DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(10), /*!< Perform 1024 transfers by edge trigger */
-} dma_trigger_burst_t;
+typedef enum _dma_trigger_burst
+{
+ kDMA_SingleTransfer = 0, /*!< Single transfer */
+ kDMA_LevelBurstTransfer = DMA_CHANNEL_CFG_TRIGBURST(1), /*!< Burst transfer driven by level trigger */
+ kDMA_EdgeBurstTransfer1 = DMA_CHANNEL_CFG_TRIGBURST(1), /*!< Perform 1 transfer by edge trigger */
+ kDMA_EdgeBurstTransfer2 =
+ DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(1), /*!< Perform 2 transfers by edge trigger */
+ kDMA_EdgeBurstTransfer4 =
+ DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(2), /*!< Perform 4 transfers by edge trigger */
+ kDMA_EdgeBurstTransfer8 =
+ DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(3), /*!< Perform 8 transfers by edge trigger */
+ kDMA_EdgeBurstTransfer16 =
+ DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(4), /*!< Perform 16 transfers by edge trigger */
+ kDMA_EdgeBurstTransfer32 =
+ DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(5), /*!< Perform 32 transfers by edge trigger */
+ kDMA_EdgeBurstTransfer64 =
+ DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(6), /*!< Perform 64 transfers by edge trigger */
+ kDMA_EdgeBurstTransfer128 =
+ DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(7), /*!< Perform 128 transfers by edge trigger */
+ kDMA_EdgeBurstTransfer256 =
+ DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(8), /*!< Perform 256 transfers by edge trigger */
+ kDMA_EdgeBurstTransfer512 =
+ DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(9), /*!< Perform 512 transfers by edge trigger */
+ kDMA_EdgeBurstTransfer1024 =
+ DMA_CHANNEL_CFG_TRIGBURST(1) | DMA_CHANNEL_CFG_BURSTPOWER(10), /*!< Perform 1024 transfers by edge trigger */
+} dma_trigger_burst_t;
/*! @brief DMA burst wrapping */
-typedef enum _dma_burst_wrap {
- kDMA_NoWrap = 0, /*!< Wrapping is disabled */
- kDMA_SrcWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1), /*!< Wrapping is enabled for source */
- kDMA_DstWrap = DMA_CHANNEL_CFG_DSTBURSTWRAP(1), /*!< Wrapping is enabled for destination */
- kDMA_SrcAndDstWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1) | DMA_CHANNEL_CFG_DSTBURSTWRAP(1), /*!< Wrapping is enabled for source and destination */
+typedef enum _dma_burst_wrap
+{
+ kDMA_NoWrap = 0, /*!< Wrapping is disabled */
+ kDMA_SrcWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1), /*!< Wrapping is enabled for source */
+ kDMA_DstWrap = DMA_CHANNEL_CFG_DSTBURSTWRAP(1), /*!< Wrapping is enabled for destination */
+ kDMA_SrcAndDstWrap = DMA_CHANNEL_CFG_SRCBURSTWRAP(1) |
+ DMA_CHANNEL_CFG_DSTBURSTWRAP(1), /*!< Wrapping is enabled for source and destination */
} dma_burst_wrap_t;
/*! @brief DMA transfer type */
@@ -143,27 +167,28 @@
} dma_transfer_type_t;
/*! @brief DMA channel trigger */
-typedef struct _dma_channel_trigger {
- dma_trigger_type_t type;
- dma_trigger_burst_t burst;
- dma_burst_wrap_t wrap;
+typedef struct _dma_channel_trigger
+{
+ dma_trigger_type_t type; /*!< Select hardware trigger as edge triggered or level triggered. */
+ dma_trigger_burst_t burst; /*!< Select whether hardware triggers cause a single or burst transfer. */
+ dma_burst_wrap_t wrap; /*!< Select wrap type, source wrap or dest wrap, or both. */
} dma_channel_trigger_t;
/*! @brief DMA transfer status */
enum _dma_transfer_status
{
- kStatus_DMA_Busy = MAKE_STATUS(kStatusGroup_DMA, 0), /*!< Channel is busy and can't handle the
- transfer request. */
+ kStatus_DMA_Busy = MAKE_STATUS(kStatusGroup_DMA, 0), /*!< Channel is busy and can't handle the
+ transfer request. */
};
/*! @brief DMA transfer configuration */
typedef struct _dma_transfer_config
{
- uint8_t *srcAddr; /*!< Source data address */
- uint8_t *dstAddr; /*!< Destination data address */
- uint8_t *nextDesc; /*!< Chain custom descriptor */
- dma_xfercfg_t xfercfg; /*!< Transfer options */
- bool isPeriph; /*!< DMA transfer is driven by peripheral */
+ uint8_t *srcAddr; /*!< Source data address */
+ uint8_t *dstAddr; /*!< Destination data address */
+ uint8_t *nextDesc; /*!< Chain custom descriptor */
+ dma_xfercfg_t xfercfg; /*!< Transfer options */
+ bool isPeriph; /*!< DMA transfer is driven by peripheral */
} dma_transfer_config_t;
/*! @brief Callback for DMA */
@@ -175,11 +200,11 @@
/*! @brief DMA transfer handle structure */
typedef struct _dma_handle
{
- dma_callback callback; /*!< Callback function. Invoked when transfer
- of descriptor with interrupt flag finishes */
- void *userData; /*!< Callback function parameter */
- DMA_Type *base; /*!< DMA peripheral base address */
- uint8_t channel; /*!< DMA channel number */
+ dma_callback callback; /*!< Callback function. Invoked when transfer
+ of descriptor with interrupt flag finishes */
+ void *userData; /*!< Callback function parameter */
+ DMA_Type *base; /*!< DMA peripheral base address */
+ uint8_t channel; /*!< DMA channel number */
} dma_handle_t;
/*******************************************************************************
@@ -219,13 +244,13 @@
* @{
*/
- /*!
- * @brief Return whether DMA channel is processing transfer
- *
- * @param base DMA peripheral base address.
- * @param channel DMA channel number.
- * @return True for active state, false otherwise.
- */
+/*!
+* @brief Return whether DMA channel is processing transfer
+*
+* @param base DMA peripheral base address.
+* @param channel DMA channel number.
+* @return True for active state, false otherwise.
+*/
static inline bool DMA_ChannelIsActive(DMA_Type *base, uint32_t channel)
{
assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
@@ -333,7 +358,8 @@
static inline void DMA_SetChannelPriority(DMA_Type *base, uint32_t channel, dma_priority_t priority)
{
assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
- base->CHANNEL[channel].CFG = (base->CHANNEL[channel].CFG & (~(DMA_CHANNEL_CFG_CHPRIORITY_MASK))) | DMA_CHANNEL_CFG_CHPRIORITY(priority);
+ base->CHANNEL[channel].CFG =
+ (base->CHANNEL[channel].CFG & (~(DMA_CHANNEL_CFG_CHPRIORITY_MASK))) | DMA_CHANNEL_CFG_CHPRIORITY(priority);
}
/*!
@@ -346,11 +372,12 @@
static inline dma_priority_t DMA_GetChannelPriority(DMA_Type *base, uint32_t channel)
{
assert(channel < FSL_FEATURE_DMA_NUMBER_OF_CHANNELS);
- return (dma_priority_t)((base->CHANNEL[channel].CFG & DMA_CHANNEL_CFG_CHPRIORITY_MASK) >> DMA_CHANNEL_CFG_CHPRIORITY_SHIFT);
+ return (dma_priority_t)((base->CHANNEL[channel].CFG & DMA_CHANNEL_CFG_CHPRIORITY_MASK) >>
+ DMA_CHANNEL_CFG_CHPRIORITY_SHIFT);
}
/*!
- * @brief Create application specific DMA descriptor
+ * @brief Create application specific DMA descriptor
* to be used in a chain in transfer
*
* @param desc DMA descriptor address.
@@ -359,13 +386,7 @@
* @param dstAddr Address of last item to receive.
* @param nextDesc Address of next descriptor in chain.
*/
-void DMA_CreateDescriptor(
- dma_descriptor_t *desc,
- dma_xfercfg_t *xfercfg,
- void *srcAddr,
- void *dstAddr,
- void *nextDesc
-);
+void DMA_CreateDescriptor(dma_descriptor_t *desc, dma_xfercfg_t *xfercfg, void *srcAddr, void *dstAddr, void *nextDesc);
/* @} */
@@ -379,7 +400,7 @@
*
* This function aborts DMA transfer specified by handle.
*
- * @param handle DMA handle pointer.
+ * @param handle DMA handle pointer.
*/
void DMA_AbortTransfer(dma_handle_t *handle);
@@ -425,12 +446,12 @@
* source address error(SAE).
*/
void DMA_PrepareTransfer(dma_transfer_config_t *config,
- void *srcAddr,
- void *dstAddr,
- uint32_t byteWidth,
- uint32_t transferBytes,
- dma_transfer_type_t type,
- void *nextDesc);
+ void *srcAddr,
+ void *dstAddr,
+ uint32_t byteWidth,
+ uint32_t transferBytes,
+ dma_transfer_type_t type,
+ void *nextDesc);
/*!
* @brief Submits the DMA transfer request.
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dmic.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dmic.c Tue Mar 20 16:56:18 2018 +0000
@@ -1,9 +1,12 @@
/*
+ * The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
+ * All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -223,13 +227,23 @@
{
s_dmicCallback[0]();
}
+ /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
}
/*DMIC0 HWVAD IRQ handler */
-void HWVAD0_IRQHandler(void)
+void HWVAD0_DriverIRQHandler(void)
{
if (s_dmicHwvadCallback[0] != NULL)
{
s_dmicHwvadCallback[0]();
}
+ /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
}
#endif
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dmic.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dmic.h Tue Mar 20 16:56:18 2018 +0000 @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dmic_dma.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dmic_dma.c Tue Mar 20 16:56:18 2018 +0000
@@ -1,9 +1,12 @@
/*
+ * The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
+ * All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -120,6 +124,7 @@
handle->userData = userData;
handle->rxDmaHandle = rxDmaHandle;
+ handle->dataWidth = 2U;
/* Set DMIC state to idle */
handle->state = kDMIC_Idle;
@@ -157,7 +162,7 @@
handle->transferSize = xfer->dataSize;
/* Prepare transfer. */
- DMA_PrepareTransfer(&xferConfig, (void *)&base->CHANNEL[dmic_channel].FIFO_DATA, xfer->data, sizeof(uint16_t),
+ DMA_PrepareTransfer(&xferConfig, (void *)&base->CHANNEL[dmic_channel].FIFO_DATA, xfer->data, handle->dataWidth,
xfer->dataSize, kDMA_PeripheralToMemory, NULL);
/* Submit transfer. */
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dmic_dma.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_dmic_dma.h Tue Mar 20 16:56:18 2018 +0000
@@ -1,9 +1,12 @@
/*
+ * The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
+ * All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -51,6 +55,13 @@
size_t dataSize; /*!< The byte count to be transfer. */
} dmic_transfer_t;
+/*! @brief DMIC transfer structure. */
+typedef enum dmic_bitwidth
+{
+ kDMICBitWidth16Bits = 2U, /*!< 16 bits mode.*/
+ kDMICBitWidth32Bits = 4U, /*!< 32 bits mode. */
+} dmic_bitwidth_t;
+
/* Forward declaration of the handle typedef. */
typedef struct _dmic_dma_handle dmic_dma_handle_t;
@@ -68,6 +79,7 @@
DMIC_Type *base; /*!< DMIC peripheral base address. */
dma_handle_t *rxDmaHandle; /*!< The DMA RX channel used. */
dmic_dma_transfer_callback_t callback; /*!< Callback function. */
+ uint8_t dataWidth; /*!< Data bit width */
void *userData; /*!< DMIC callback function parameter.*/
size_t transferSize; /*!< Size of the data to receive. */
volatile uint8_t state; /*!< Internal state of DMIC DMA transfer */
@@ -101,15 +113,32 @@
dma_handle_t *rxDmaHandle);
/*!
+ * @brief Configure the transfer data width.
+ *
+ * This function is optional to users, the default data width is set to 16 bits if not call this fuction.
+ * DMIC only support 16 bits and 32 bits setting. As DMA cannot support 24 bits directly, please set to 32 bits
+ * while need a 24 bits data. In 32 bit mode, the MSB 8 bits always 0, as the register can only have 24 bits valid bits.
+ *
+ * @param base DMIC peripheral base address.
+ * @param handle Pointer to usart_dma_handle_t structure.
+ * @param width DMIC width. See #dmic_bitwidth_t.
+ * @retval kStatus_Success
+ */
+static inline void DMIC_TransferSetBitWidthDMA(DMIC_Type *base, dmic_dma_handle_t *handle, dmic_bitwidth_t width)
+{
+ handle->dataWidth = width;
+}
+
+/*!
* @brief Receives data using DMA.
*
* This function receives data using DMA. This is a non-blocking function, which returns
* right away. When all data is received, the receive callback function is called.
*
- * @param base USART peripheral base address.
+ * @param base DMIC peripheral base address.
* @param handle Pointer to usart_dma_handle_t structure.
* @param xfer DMIC DMA transfer structure. See #dmic_transfer_t.
- * @param dmic_channel DMIC channel
+ * @param dmic_channel DMIC channel
* @retval kStatus_Success
*/
status_t DMIC_TransferReceiveDMA(DMIC_Type *base,
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_eeprom.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_eeprom.c Tue Mar 20 16:56:18 2018 +0000 @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_eeprom.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_eeprom.h Tue Mar 20 16:56:18 2018 +0000 @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_emc.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_emc.c Tue Mar 20 16:56:18 2018 +0000 @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_emc.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_emc.h Tue Mar 20 16:56:18 2018 +0000 @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_enet.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_enet.c Tue Mar 20 16:56:18 2018 +0000
@@ -1,9 +1,12 @@
/*
+ * The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
+ * All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -919,8 +923,8 @@
assert(config);
assert(bufferConfig);
- bool intTxEnable;
- bool intRxEnable;
+ bool intTxEnable = false;
+ bool intRxEnable = false;
bool doubleBuffEnable = (config->specialControl & kENET_DescDoubleBuffer) ? true : false;
uint8_t ringNum = config->multiqueueCfg == NULL ? 1 : 2;
uint8_t channel;
@@ -928,12 +932,12 @@
for (channel = 0; channel < ringNum; channel++)
{
intRxEnable = (base->DMA_CH[channel].DMA_CHX_INT_EN & ENET_DMA_CH_DMA_CHX_INT_EN_RIE_MASK) ? true : false;
+ intTxEnable = (base->DMA_CH[channel].DMA_CHX_INT_EN & ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK) ? true : false;
if (ENET_TxDescriptorsInit(base, bufferConfig, intTxEnable, channel) != kStatus_Success)
{
return kStatus_Fail;
}
- intTxEnable = (base->DMA_CH[channel].DMA_CHX_INT_EN & ENET_DMA_CH_DMA_CHX_INT_EN_TIE_MASK) ? true : false;
if (ENET_RxDescriptorsInit(base, bufferConfig, intRxEnable, channel, doubleBuffEnable) != kStatus_Success)
{
@@ -1244,7 +1248,7 @@
enet_rx_bd_ring_t *rxBdRing = (enet_rx_bd_ring_t *)&handle->rxBdRing[channel];
enet_rx_bd_struct_t *rxDesc = rxBdRing->rxBdBase + rxBdRing->rxGenIdx;
- uint16_t index;
+ uint16_t index = rxBdRing->rxGenIdx;
/* Reset the length to zero. */
*length = 0;
@@ -1802,9 +1806,19 @@
}
}
#endif /* ENET_PTP1588FEATURE_REQUIRED */
+ /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
}
void ETHERNET_DriverIRQHandler(void)
{
s_enetIsr(ENET, s_ENETHandle[0]);
+ /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
}
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_enet.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_enet.h Tue Mar 20 16:56:18 2018 +0000 @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_flashiap.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_flashiap.c Tue Mar 20 16:56:18 2018 +0000 @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_flashiap.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_flashiap.h Tue Mar 20 16:56:18 2018 +0000 @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_flexcomm.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_flexcomm.c Tue Mar 20 16:56:18 2018 +0000
@@ -1,9 +1,12 @@
/*
+ * The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
+ * All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -155,6 +159,11 @@
s_flexcommIrqHandler[instance] = NULL;
s_flexcommHandle[instance] = handle;
s_flexcommIrqHandler[instance] = handler;
+ /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
}
/* IRQ handler functions overloading weak symbols in the startup */
@@ -163,6 +172,11 @@
{
assert(s_flexcommIrqHandler[0]);
s_flexcommIrqHandler[0]((void *)s_flexcommBaseAddrs[0], s_flexcommHandle[0]);
+ /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
}
#endif
@@ -171,6 +185,11 @@
{
assert(s_flexcommIrqHandler[1]);
s_flexcommIrqHandler[1]((void *)s_flexcommBaseAddrs[1], s_flexcommHandle[1]);
+ /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
}
#endif
@@ -179,6 +198,11 @@
{
assert(s_flexcommIrqHandler[2]);
s_flexcommIrqHandler[2]((void *)s_flexcommBaseAddrs[2], s_flexcommHandle[2]);
+ /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
}
#endif
@@ -187,6 +211,11 @@
{
assert(s_flexcommIrqHandler[3]);
s_flexcommIrqHandler[3]((void *)s_flexcommBaseAddrs[3], s_flexcommHandle[3]);
+ /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
}
#endif
@@ -195,6 +224,11 @@
{
assert(s_flexcommIrqHandler[4]);
s_flexcommIrqHandler[4]((void *)s_flexcommBaseAddrs[4], s_flexcommHandle[4]);
+ /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
}
#endif
@@ -204,6 +238,11 @@
{
assert(s_flexcommIrqHandler[5]);
s_flexcommIrqHandler[5]((void *)s_flexcommBaseAddrs[5], s_flexcommHandle[5]);
+ /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
}
#endif
@@ -212,6 +251,11 @@
{
assert(s_flexcommIrqHandler[6]);
s_flexcommIrqHandler[6]((void *)s_flexcommBaseAddrs[6], s_flexcommHandle[6]);
+ /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
}
#endif
@@ -220,6 +264,11 @@
{
assert(s_flexcommIrqHandler[7]);
s_flexcommIrqHandler[7]((void *)s_flexcommBaseAddrs[7], s_flexcommHandle[7]);
+ /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
}
#endif
@@ -228,6 +277,11 @@
{
assert(s_flexcommIrqHandler[8]);
s_flexcommIrqHandler[8]((void *)s_flexcommBaseAddrs[8], s_flexcommHandle[8]);
+ /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
}
#endif
@@ -236,5 +290,10 @@
{
assert(s_flexcommIrqHandler[9]);
s_flexcommIrqHandler[9]((void *)s_flexcommBaseAddrs[9], s_flexcommHandle[9]);
+ /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
}
#endif
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_flexcomm.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_flexcomm.h Tue Mar 20 16:56:18 2018 +0000
@@ -1,9 +1,12 @@
/*
+ * The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
+ * All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -37,6 +41,12 @@
* @{
*/
+/*! @name Driver version */
+/*@{*/
+/*! @brief FlexCOMM driver version 2.0.0. */
+#define FSL_FLEXCOMM_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
/*! @brief FLEXCOMM peripheral modes. */
typedef enum
{
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_fmc.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_fmc.c Tue Mar 20 16:56:18 2018 +0000 @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_fmc.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_fmc.h Tue Mar 20 16:56:18 2018 +0000 @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_fmeas.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_fmeas.c Tue Mar 20 16:56:18 2018 +0000 @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_fmeas.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_fmeas.h Tue Mar 20 16:56:18 2018 +0000 @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_gint.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_gint.c Tue Mar 20 16:56:18 2018 +0000
@@ -1,9 +1,12 @@
/*
+ * The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
+ * All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -176,6 +180,11 @@
{
s_gintCallback[0]();
}
+ /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
}
#endif
@@ -189,6 +198,11 @@
{
s_gintCallback[1]();
}
+ /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
}
#endif
@@ -202,6 +216,11 @@
{
s_gintCallback[2]();
}
+ /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
}
#endif
@@ -215,6 +234,11 @@
{
s_gintCallback[3]();
}
+ /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
}
#endif
@@ -228,6 +252,11 @@
{
s_gintCallback[4]();
}
+ /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
}
#endif
@@ -241,6 +270,11 @@
{
s_gintCallback[5]();
}
+ /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
}
#endif
@@ -254,6 +288,11 @@
{
s_gintCallback[6]();
}
+ /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
}
#endif
@@ -267,5 +306,10 @@
{
s_gintCallback[7]();
}
+ /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
}
#endif
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_gint.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_gint.h Tue Mar 20 16:56:18 2018 +0000 @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_gpio.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_gpio.c Tue Mar 20 16:56:18 2018 +0000
@@ -1,9 +1,12 @@
/*
+ * The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
+ * All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -33,7 +37,10 @@
/*******************************************************************************
* Variables
******************************************************************************/
-
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+/*! @brief Array to map FGPIO instance number to clock name. */
+static const clock_ip_name_t s_gpioClockName[] = GPIO_CLOCKS;
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
/*******************************************************************************
* Prototypes
************ ******************************************************************/
@@ -41,6 +48,15 @@
/*******************************************************************************
* Code
******************************************************************************/
+void GPIO_PortInit(GPIO_Type *base, uint32_t port)
+{
+#if !(defined(FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL) && FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL)
+ assert(port < ARRAY_SIZE(s_gpioClockName));
+
+ /* Upgate the GPIO clock */
+ CLOCK_EnableClock(s_gpioClockName[port]);
+#endif /* FSL_SDK_DISABLE_DRIVER_CLOCK_CONTROL */
+}
void GPIO_PinInit(GPIO_Type *base, uint32_t port, uint32_t pin, const gpio_pin_config_t *config)
{
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_gpio.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_gpio.h Tue Mar 20 16:56:18 2018 +0000
@@ -1,9 +1,12 @@
/*
+ * The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
+ * All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -46,8 +50,8 @@
/*! @name Driver version */
/*@{*/
-/*! @brief LPC GPIO driver version 2.0.0. */
-#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*! @brief LPC GPIO driver version 2.1.1. */
+#define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
/*@}*/
/*! @brief LPC GPIO direction definition */
@@ -81,6 +85,25 @@
/*@{*/
/*!
+ * @brief Initializes the GPIO peripheral.
+ *
+ * This function ungates the GPIO clock.
+ *
+ * @param base GPIO peripheral base pointer.
+ * @param port GPIO port number.
+ */
+void GPIO_PortInit(GPIO_Type *base, uint32_t port);
+
+/*!
+ * @brief Initializes the GPIO peripheral.
+ * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortInit.
+ */
+static inline void GPIO_Init(GPIO_Type *base, uint32_t port)
+{
+ GPIO_PortInit(base, port);
+}
+
+/*!
* @brief Initializes a GPIO pin used by the board.
*
* To initialize the GPIO, define a pin configuration, either input or output, in the user file.
@@ -124,6 +147,15 @@
* - 0: corresponding pin output low-logic level.
* - 1: corresponding pin output high-logic level.
*/
+static inline void GPIO_PinWrite(GPIO_Type *base, uint32_t port, uint32_t pin, uint8_t output)
+{
+ base->B[port][pin] = output;
+}
+
+/*!
+ * @brief Sets the output level of the one GPIO pin to the logic 1 or 0.
+ * @deprecated Do not use this function. It has been superceded by @ref GPIO_PinWrite.
+ */
static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t port, uint32_t pin, uint8_t output)
{
base->B[port][pin] = output;
@@ -142,9 +174,18 @@
* - 0: corresponding pin input low-logic level.
* - 1: corresponding pin input high-logic level.
*/
+static inline uint32_t GPIO_PinRead(GPIO_Type *base, uint32_t port, uint32_t pin)
+{
+ return (uint32_t)base->B[port][pin];
+}
+
+/*!
+ * @brief Reads the current input value of the GPIO PIN.
+ * @deprecated Do not use this function. It has been superceded by @ref GPIO_PinRead.
+ */
static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t port, uint32_t pin)
{
- return (uint32_t)base->B[port][pin];
+ return GPIO_PinRead(base, port, pin);
}
/*@}*/
@@ -155,9 +196,18 @@
* @param port GPIO port number
* @param mask GPIO pin number macro
*/
+static inline void GPIO_PortSet(GPIO_Type *base, uint32_t port, uint32_t mask)
+{
+ base->SET[port] = mask;
+}
+
+/*!
+ * @brief Sets the output level of the multiple GPIO pins to the logic 1.
+ * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortSet.
+ */
static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t port, uint32_t mask)
{
- base->SET[port] = mask;
+ GPIO_PortSet(base, port, mask);
}
/*!
@@ -167,9 +217,18 @@
* @param port GPIO port number
* @param mask GPIO pin number macro
*/
+static inline void GPIO_PortClear(GPIO_Type *base, uint32_t port, uint32_t mask)
+{
+ base->CLR[port] = mask;
+}
+
+/*!
+ * @brief Sets the output level of the multiple GPIO pins to the logic 0.
+ * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortClear.
+ */
static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t port, uint32_t mask)
{
- base->CLR[port] = mask;
+ GPIO_PortClear(base, port, mask);
}
/*!
@@ -179,9 +238,18 @@
* @param port GPIO port number
* @param mask GPIO pin number macro
*/
+static inline void GPIO_PortToggle(GPIO_Type *base, uint32_t port, uint32_t mask)
+{
+ base->NOT[port] = mask;
+}
+
+/*!
+ * @brief Reverses current output logic of the multiple GPIO pins.
+ * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortToggle.
+ */
static inline void GPIO_TogglePinsOutput(GPIO_Type *base, uint32_t port, uint32_t mask)
{
- base->NOT[port] = mask;
+ GPIO_PortToggle(base, port, mask);
}
/*@}*/
@@ -191,9 +259,18 @@
* @param base GPIO peripheral base pointer(Typically GPIO)
* @param port GPIO port number
*/
+static inline uint32_t GPIO_PortRead(GPIO_Type *base, uint32_t port)
+{
+ return (uint32_t)base->PIN[port];
+}
+
+/*!
+ * @brief Reads the current input value of the whole GPIO port.
+ * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortRead
+ */
static inline uint32_t GPIO_ReadPinsInput(GPIO_Type *base, uint32_t port)
{
- return (uint32_t)base->PIN[port];
+ return GPIO_PortRead(base, port);
}
/*@}*/
@@ -207,9 +284,18 @@
* @param port GPIO port number
* @param mask GPIO pin number macro
*/
+static inline void GPIO_PortMaskedSet(GPIO_Type *base, uint32_t port, uint32_t mask)
+{
+ base->MASK[port] = mask;
+}
+
+/*!
+ * @brief Sets port mask, 0 - enable pin, 1 - disable pin.
+ * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortMaskedSet.
+ */
static inline void GPIO_SetPortMask(GPIO_Type *base, uint32_t port, uint32_t mask)
{
- base->MASK[port] = mask;
+ GPIO_PortMaskedSet(base, port, mask);
}
/*!
@@ -219,9 +305,18 @@
* @param port GPIO port number
* @param output GPIO port output value.
*/
+static inline void GPIO_PortMaskedWrite(GPIO_Type *base, uint32_t port, uint32_t output)
+{
+ base->MPIN[port] = output;
+}
+
+/*!
+ * @brief Sets the output level of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be affected.
+ * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortMaskedWrite.
+ */
static inline void GPIO_WriteMPort(GPIO_Type *base, uint32_t port, uint32_t output)
{
- base->MPIN[port] = output;
+ GPIO_PortMaskedWrite(base, port, output);
}
/*!
@@ -232,9 +327,19 @@
* @param port GPIO port number
* @retval masked GPIO port value
*/
+static inline uint32_t GPIO_PortMaskedRead(GPIO_Type *base, uint32_t port)
+{
+ return (uint32_t)base->MPIN[port];
+}
+
+/*!
+ * @brief Reads the current input value of the masked GPIO port. Only pins enabled by GPIO_SetPortMask() will be
+ * affected.
+ * @deprecated Do not use this function. It has been superceded by @ref GPIO_PortMaskedRead.
+ */
static inline uint32_t GPIO_ReadMPort(GPIO_Type *base, uint32_t port)
{
- return (uint32_t)base->MPIN[port];
+ return GPIO_PortMaskedRead(base, port);
}
/*@}*/
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2c.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2c.c Tue Mar 20 16:56:18 2018 +0000
@@ -1,9 +1,12 @@
/*
+ * The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
+ * All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -159,10 +163,23 @@
{
uint32_t status;
+#if I2C_WAIT_TIMEOUT
+ uint32_t waitTimes = I2C_WAIT_TIMEOUT;
+#endif
+
do
{
status = I2C_GetStatusFlags(base);
+#if I2C_WAIT_TIMEOUT
+ } while (((status & I2C_STAT_MSTPENDING_MASK) == 0) && (--waitTimes));
+
+ if (waitTimes == 0)
+ {
+ return kStatus_I2C_Timeout;
+ }
+#else
} while ((status & I2C_STAT_MSTPENDING_MASK) == 0);
+#endif
/* Clear controller state. */
I2C_MasterClearStatusFlags(base, I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK);
@@ -172,7 +189,12 @@
status_t I2C_MasterStart(I2C_Type *base, uint8_t address, i2c_direction_t direction)
{
- I2C_PendingStatusWait(base);
+ status_t result;
+ result = I2C_PendingStatusWait(base);
+ if (result == kStatus_I2C_Timeout)
+ {
+ return kStatus_I2C_Timeout;
+ }
/* Write Address and RW bit to data register */
base->MSTDAT = ((uint32_t)address << 1) | ((uint32_t)direction & 1u);
@@ -184,7 +206,12 @@
status_t I2C_MasterStop(I2C_Type *base)
{
- I2C_PendingStatusWait(base);
+ status_t result;
+ result = I2C_PendingStatusWait(base);
+ if (result == kStatus_I2C_Timeout)
+ {
+ return kStatus_I2C_Timeout;
+ }
base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
return kStatus_Success;
@@ -204,6 +231,10 @@
while (txSize)
{
status = I2C_PendingStatusWait(base);
+ if (status == kStatus_I2C_Timeout)
+ {
+ return kStatus_I2C_Timeout;
+ }
if (status & I2C_STAT_MSTARBLOSS_MASK)
{
@@ -245,6 +276,11 @@
status = I2C_PendingStatusWait(base);
+ if (status == kStatus_I2C_Timeout)
+ {
+ return kStatus_I2C_Timeout;
+ }
+
if ((status & (I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK)) == 0)
{
if (!(flags & kI2C_TransferNoStopFlag))
@@ -252,6 +288,10 @@
/* Initiate stop */
base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
status = I2C_PendingStatusWait(base);
+ if (status == kStatus_I2C_Timeout)
+ {
+ return kStatus_I2C_Timeout;
+ }
}
}
@@ -282,6 +322,10 @@
while (rxSize)
{
status = I2C_PendingStatusWait(base);
+ if (status == kStatus_I2C_Timeout)
+ {
+ return kStatus_I2C_Timeout;
+ }
if (status & (I2C_STAT_MSTARBLOSS_MASK | I2C_STAT_MSTSTSTPERR_MASK))
{
@@ -305,6 +349,10 @@
/* initiate NAK and stop */
base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
status = I2C_PendingStatusWait(base);
+ if (status == kStatus_I2C_Timeout)
+ {
+ return kStatus_I2C_Timeout;
+ }
}
}
break;
@@ -483,7 +531,7 @@
return kStatus_Success;
}
-void I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle)
+status_t I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle)
{
uint32_t status;
uint32_t master_state;
@@ -495,6 +543,10 @@
/* Wait until module is ready */
status = I2C_PendingStatusWait(base);
+ if (status == kStatus_I2C_Timeout)
+ {
+ return kStatus_I2C_Timeout;
+ }
/* Get the state of the I2C module */
master_state = (status & I2C_STAT_MSTSTATE_MASK) >> I2C_STAT_MSTSTATE_SHIFT;
@@ -505,12 +557,17 @@
base->MSTCTL = I2C_MSTCTL_MSTSTOP_MASK;
/* Wait until the STOP is completed */
- I2C_PendingStatusWait(base);
+ status = I2C_PendingStatusWait(base);
+ if (status == kStatus_I2C_Timeout)
+ {
+ return kStatus_I2C_Timeout;
+ }
}
/* Reset handle. */
handle->state = kIdleState;
}
+ return kStatus_Success;
}
/*!
@@ -842,10 +899,22 @@
{
uint32_t stat;
+#if I2C_WAIT_TIMEOUT
+ uint32_t waitTimes = I2C_WAIT_TIMEOUT;
+#endif
do
{
stat = base->STAT;
+#if I2C_WAIT_TIMEOUT
+ } while ((0u == (stat & I2C_STAT_SLVPENDING_MASK)) && (--waitTimes));
+
+ if (waitTimes == 0u)
+ {
+ return kStatus_I2C_Timeout;
+ }
+#else
} while (0u == (stat & I2C_STAT_SLVPENDING_MASK));
+#endif
return stat;
}
@@ -1099,6 +1168,10 @@
/* wait for SLVPENDING */
stat = I2C_SlavePollPending(base);
+ if (stat == kStatus_I2C_Timeout)
+ {
+ return kStatus_I2C_Timeout;
+ }
/* Get slave machine state */
slaveAddress = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_ADDR);
@@ -1118,6 +1191,10 @@
/* wait for SLVPENDING */
stat = I2C_SlavePollPending(base);
+ if (stat == kStatus_I2C_Timeout)
+ {
+ return kStatus_I2C_Timeout;
+ }
}
/* send bytes up to txSize */
@@ -1145,6 +1222,10 @@
{
/* wait for SLVPENDING */
stat = I2C_SlavePollPending(base);
+ if (stat == kStatus_I2C_Timeout)
+ {
+ return kStatus_I2C_Timeout;
+ }
}
}
@@ -1163,6 +1244,10 @@
/* wait for SLVPENDING */
stat = I2C_SlavePollPending(base);
+ if (stat == kStatus_I2C_Timeout)
+ {
+ return kStatus_I2C_Timeout;
+ }
/* Get slave machine state */
slaveAddress = (((stat & I2C_STAT_SLVSTATE_MASK) >> I2C_STAT_SLVSTATE_SHIFT) == I2C_STAT_SLVST_ADDR);
@@ -1182,6 +1267,10 @@
/* wait for SLVPENDING */
stat = I2C_SlavePollPending(base);
+ if (stat == kStatus_I2C_Timeout)
+ {
+ return kStatus_I2C_Timeout;
+ }
}
/* receive bytes up to rxSize */
@@ -1209,6 +1298,10 @@
{
/* wait for SLVPENDING */
stat = I2C_SlavePollPending(base);
+ if (stat == kStatus_I2C_Timeout)
+ {
+ return kStatus_I2C_Timeout;
+ }
}
}
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2c.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2c.h Tue Mar 20 16:56:18 2018 +0000
@@ -1,9 +1,12 @@
/*
+ * The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
+ * All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -49,10 +53,15 @@
/*! @name Driver version */
/*@{*/
-/*! @brief I2C driver version 1.0.0. */
-#define NXP_I2C_DRIVER_VERSION (MAKE_VERSION(1, 0, 0))
+/*! @brief I2C driver version 2.0.1. */
+#define FSL_I2C_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
/*@}*/
+/*! @brief Timeout times for waiting flag. */
+#ifndef I2C_WAIT_TIMEOUT
+#define I2C_WAIT_TIMEOUT 0U /* Define to zero means keep waiting until the flag is assert/deassert. */
+#endif
+
/* definitions for MSTCODE bits in I2C Status register STAT */
#define I2C_STAT_MSTCODE_IDLE (0) /*!< Master Idle State Code */
#define I2C_STAT_MSTCODE_RXREADY (1) /*!< Master Receive Ready State Code */
@@ -77,10 +86,11 @@
kStatus_I2C_BitError = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 4), /*!< Transferred bit was not seen on the bus. */
kStatus_I2C_ArbitrationLost = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 5), /*!< Arbitration lost error. */
kStatus_I2C_NoTransferInProgress =
- MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 7), /*!< Attempt to abort a transfer when one is not in progress. */
+ MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 6), /*!< Attempt to abort a transfer when one is not in progress. */
kStatus_I2C_DmaRequestFail = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 7), /*!< DMA request failed. */
kStatus_I2C_StartStopError = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 8),
kStatus_I2C_UnexpectedState = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 9),
+ kStatus_I2C_Timeout = MAKE_STATUS(kStatusGroup_FLEXCOMM_I2C, 10), /*!< Timeout poling status flags. */
};
/*! @} */
@@ -98,8 +108,10 @@
enum _i2c_master_flags
{
kI2C_MasterPendingFlag = I2C_STAT_MSTPENDING_MASK, /*!< The I2C module is waiting for software interaction. */
- kI2C_MasterArbitrationLostFlag = I2C_STAT_MSTARBLOSS_MASK, /*!< The arbitration of the bus was lost. There was collision on the bus */
- kI2C_MasterStartStopErrorFlag = I2C_STAT_MSTSTSTPERR_MASK /*!< There was an error during start or stop phase of the transaction. */
+ kI2C_MasterArbitrationLostFlag =
+ I2C_STAT_MSTARBLOSS_MASK, /*!< The arbitration of the bus was lost. There was collision on the bus */
+ kI2C_MasterStartStopErrorFlag =
+ I2C_STAT_MSTSTSTPERR_MASK /*!< There was an error during start or stop phase of the transaction. */
};
/*! @brief Direction of master and slave transfers. */
@@ -215,19 +227,21 @@
* @{
*/
- /*!
- * @brief I2C slave peripheral flags.
- *
- * @note These enums are meant to be OR'd together to form a bit mask.
- */
+/*!
+* @brief I2C slave peripheral flags.
+*
+* @note These enums are meant to be OR'd together to form a bit mask.
+*/
enum _i2c_slave_flags
{
kI2C_SlavePendingFlag = I2C_STAT_SLVPENDING_MASK, /*!< The I2C module is waiting for software interaction. */
- kI2C_SlaveNotStretching = I2C_STAT_SLVNOTSTR_MASK, /*!< Indicates whether the slave is currently stretching clock (0 = yes, 1 = no). */
+ kI2C_SlaveNotStretching =
+ I2C_STAT_SLVNOTSTR_MASK, /*!< Indicates whether the slave is currently stretching clock (0 = yes, 1 = no). */
kI2C_SlaveSelected = I2C_STAT_SLVSEL_MASK, /*!< Indicates whether the slave is selected by an address match. */
- kI2C_SaveDeselected = I2C_STAT_SLVDESEL_MASK /*!< Indicates that slave was previously deselected (deselect event took place, w1c). */
+ kI2C_SaveDeselected =
+ I2C_STAT_SLVDESEL_MASK /*!< Indicates that slave was previously deselected (deselect event took place, w1c). */
};
-
+
/*! @brief I2C slave address register. */
typedef enum _i2c_slave_address_register
{
@@ -621,7 +635,8 @@
* @param base The I2C peripheral base address.
* @param txBuff The pointer to the data to be transferred.
* @param txSize The length in bytes of the data to be transferred.
- * @param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers use kI2C_TransferDefaultFlag
+ * @param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers
+ * use kI2C_TransferDefaultFlag
* @retval kStatus_Success Data was sent successfully.
* @retval #kStatus_I2C_Busy Another master is currently utilizing the bus.
* @retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte.
@@ -635,7 +650,8 @@
* @param base The I2C peripheral base address.
* @param rxBuff The pointer to the data to be transferred.
* @param rxSize The length in bytes of the data to be transferred.
- * @param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers use kI2C_TransferDefaultFlag
+ * @param flags Transfer control flag to control special behavior like suppressing start or stop, for normal transfers
+ * use kI2C_TransferDefaultFlag
* @retval kStatus_Success Data was received successfully.
* @retval #kStatus_I2C_Busy Another master is currently utilizing the bus.
* @retval #kStatus_I2C_Nak The slave device sent a NAK in response to a byte.
@@ -712,9 +728,9 @@
* @param base The I2C peripheral base address.
* @param handle Pointer to the I2C master driver handle.
* @retval kStatus_Success A transaction was successfully aborted.
- * @retval #kStatus_I2C_Idle There is not a non-blocking transaction currently in progress.
+ * @retval #kStatus_I2C_Timeout Timeout during polling for flags.
*/
-void I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle);
+status_t I2C_MasterTransferAbort(I2C_Type *base, i2c_master_handle_t *handle);
/*@}*/
@@ -786,7 +802,8 @@
* This function writes new value to Slave Address register.
*
* @param base The I2C peripheral base address.
- * @param addressRegister The module supports multiple address registers. The parameter determines which one shall be changed.
+ * @param addressRegister The module supports multiple address registers. The parameter determines which one shall be
+ * changed.
* @param address The slave address to be stored to the address register for matching.
* @param addressDisable Disable matching of the specified address register.
*/
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2c_dma.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2c_dma.c Tue Mar 20 16:56:18 2018 +0000
@@ -1,9 +1,12 @@
/*
+ * The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
+ * All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -316,7 +320,7 @@
DMA_PrepareTransfer(&xferConfig, handle->subaddrBuf, (void *)&base->MSTDAT, sizeof(uint8_t),
handle->remainingSubaddr, kDMA_MemoryToPeripheral, NULL);
DMA_SubmitTransfer(handle->dmaHandle, &xferConfig);
-
+ DMA_StartTransfer(handle->dmaHandle);
handle->remainingSubaddr = 0;
if (transfer->dataSize)
{
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2c_dma.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2c_dma.h Tue Mar 20 16:56:18 2018 +0000 @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2015, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2s.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2s.c Tue Mar 20 16:56:18 2018 +0000 @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2s.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2s.h Tue Mar 20 16:56:18 2018 +0000 @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2s_dma.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2s_dma.c Tue Mar 20 16:56:18 2018 +0000 @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2s_dma.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_i2s_dma.h Tue Mar 20 16:56:18 2018 +0000
@@ -1,9 +1,12 @@
/*
+ * The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
+ * All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -46,21 +50,6 @@
* @{
*/
-/*! @file */
-
-/*! @name Driver version */
-/*@{*/
-/*! @brief I2S DMA driver version 2.0.0.
- *
- * Current version: 2.0.0
- *
- * Change log:
- * - Version 2.0.0
- * - initial version
- */
-#define FSL_I2S_DMA_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
-/*@}*/
-
/*! @brief Members not to be accessed / modified outside of the driver. */
typedef struct _i2s_dma_handle i2s_dma_handle_t;
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_inputmux.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_inputmux.c Tue Mar 20 16:56:18 2018 +0000 @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_inputmux.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_inputmux.h Tue Mar 20 16:56:18 2018 +0000 @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_inputmux_connections.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_inputmux_connections.h Tue Mar 20 16:56:18 2018 +0000
@@ -1,9 +1,13 @@
/*
- * Copyright (c) 2013-2016, NXP Semiconductors.
+ * The Clear BSD License
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright (c) 2017, NXP
* All rights reserved.
*
+ *
* Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +20,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -90,8 +95,8 @@
kINPUTMUX_WdtOscToFreqmeas = 3U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
kINPUTMUX_32KhzOscToFreqmeas = 4U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
kINPUTMUX_MainClkToFreqmeas = 5U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
- kINPUTMUX_FreqmeGpioClk_a = 5U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
- kINPUTMUX_FreqmeGpioClk_b = 6U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
+ kINPUTMUX_FreqmeGpioClk_a = 6U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
+ kINPUTMUX_FreqmeGpioClk_b = 7U + (FREQMEAS_PMUX_ID << PMUX_SHIFT),
/*!< Pin Interrupt. */
kINPUTMUX_GpioPort0Pin0ToPintsel = 0U + (PINTSEL_PMUX_ID << PMUX_SHIFT),
@@ -163,18 +168,18 @@
kINPUTMUX_Adc0SeqbIrqToDma = 1U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
kINPUTMUX_Sct0DmaReq0ToDma = 2U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
kINPUTMUX_Sct0DmaReq1ToDma = 3U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
- kINPUTMUX_Ctimer0M0ToDma = 4U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
- kINPUTMUX_Ctimer0M1ToDma = 5U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
- kINPUTMUX_Ctimer1M0ToDma = 6U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
- kINPUTMUX_Ctimer2M0ToDma = 7U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
- kINPUTMUX_Ctimer2M1ToDma = 8U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
- kINPUTMUX_Ctimer3M0ToDma = 9U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
- kINPUTMUX_Ctimer4M0ToDma = 10U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
- kINPUTMUX_Ctimer4M1ToDma = 11U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
- kINPUTMUX_PinInt0ToDma = 12U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
- kINPUTMUX_PinInt1ToDma = 13U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
- kINPUTMUX_PinInt2ToDma = 14U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
- kINPUTMUX_PinInt3ToDma = 15U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+ kINPUTMUX_PinInt0ToDma = 4U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+ kINPUTMUX_PinInt1ToDma = 5U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+ kINPUTMUX_PinInt2ToDma = 6U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+ kINPUTMUX_PinInt3ToDma = 7U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+ kINPUTMUX_Ctimer0M0ToDma = 8U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+ kINPUTMUX_Ctimer0M1ToDma = 9U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+ kINPUTMUX_Ctimer1M0ToDma = 10U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+ kINPUTMUX_Ctimer2M0ToDma = 11U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+ kINPUTMUX_Ctimer2M1ToDma = 12U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+ kINPUTMUX_Ctimer3M0ToDma = 13U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+ kINPUTMUX_Ctimer4M0ToDma = 14U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
+ kINPUTMUX_Ctimer4M1ToDma = 15U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
kINPUTMUX_Otrig0ToDma = 16U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
kINPUTMUX_Otrig1ToDma = 17U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
kINPUTMUX_Otrig2ToDma = 18U + (DMA_TRIG0_PMUX_ID << PMUX_SHIFT),
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_iocon.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_iocon.h Tue Mar 20 16:56:18 2018 +0000
@@ -1,9 +1,12 @@
/*
+ * The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
+ * All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -64,75 +68,76 @@
* @brief IOCON function and mode selection definitions
* @note See the User Manual for specific modes and functions supported by the various pins.
*/
- #if defined(FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH) && (FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH== 4)
- #define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */
- #define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */
- #define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */
- #define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */
- #define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */
- #define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */
- #define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */
- #define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */
- #define IOCON_FUNC8 0x8 /*!< Selects pin function 8 */
- #define IOCON_FUNC9 0x9 /*!< Selects pin function 9 */
- #define IOCON_FUNC10 0xA /*!< Selects pin function 10 */
- #define IOCON_FUNC11 0xB /*!< Selects pin function 11 */
- #define IOCON_FUNC12 0xC /*!< Selects pin function 12 */
- #define IOCON_FUNC13 0xD /*!< Selects pin function 13 */
- #define IOCON_FUNC14 0xE /*!< Selects pin function 14 */
- #define IOCON_FUNC15 0xF /*!< Selects pin function 15 */
- #define IOCON_MODE_INACT (0x0 << 4) /*!< No addition pin function */
- #define IOCON_MODE_PULLDOWN (0x1 << 4) /*!< Selects pull-down function */
- #define IOCON_MODE_PULLUP (0x2 << 4) /*!< Selects pull-up function */
- #define IOCON_MODE_REPEATER (0x3 << 4) /*!< Selects pin repeater function */
- #define IOCON_HYS_EN (0x1 << 6) /*!< Enables hysteresis */
- #define IOCON_GPIO_MODE (0x1 << 6) /*!< GPIO Mode */
- #define IOCON_I2C_SLEW (0x1 << 6) /*!< I2C Slew Rate Control */
- #define IOCON_INV_EN (0x1 << 7) /*!< Enables invert function on input */
- #define IOCON_ANALOG_EN (0x0 << 8) /*!< Enables analog function by setting 0 to bit 7 */
- #define IOCON_DIGITAL_EN (0x1 << 8) /*!< Enables digital function by setting 1 to bit 7(default) */
- #define IOCON_STDI2C_EN (0x1 << 9) /*!< I2C standard mode/fast-mode */
- #define IOCON_FASTI2C_EN (0x3 << 9) /*!< I2C Fast-mode Plus and high-speed slave */
- #define IOCON_INPFILT_OFF (0x1 << 9) /*!< Input filter Off for GPIO pins */
- #define IOCON_INPFILT_ON (0x0 << 9) /*!< Input filter On for GPIO pins */
- #define IOCON_OPENDRAIN_EN (0x1 << 11) /*!< Enables open-drain function */
- #define IOCON_S_MODE_0CLK (0x0 << 12) /*!< Bypass input filter */
- #define IOCON_S_MODE_1CLK (0x1 << 12) /*!< Input pulses shorter than 1 filter clock are rejected */
- #define IOCON_S_MODE_2CLK (0x2 << 12) /*!< Input pulses shorter than 2 filter clock2 are rejected */
- #define IOCON_S_MODE_3CLK (0x3 << 12) /*!< Input pulses shorter than 3 filter clock2 are rejected */
- #define IOCON_S_MODE(clks) ((clks) << 12) /*!< Select clocks for digital input filter mode */
- #define IOCON_CLKDIV(div) ((div) << 14) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */
+#if defined(FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH) && (FSL_FEATURE_IOCON_FUNC_FIELD_WIDTH == 4)
+#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */
+#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */
+#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */
+#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */
+#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */
+#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */
+#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */
+#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */
+#define IOCON_FUNC8 0x8 /*!< Selects pin function 8 */
+#define IOCON_FUNC9 0x9 /*!< Selects pin function 9 */
+#define IOCON_FUNC10 0xA /*!< Selects pin function 10 */
+#define IOCON_FUNC11 0xB /*!< Selects pin function 11 */
+#define IOCON_FUNC12 0xC /*!< Selects pin function 12 */
+#define IOCON_FUNC13 0xD /*!< Selects pin function 13 */
+#define IOCON_FUNC14 0xE /*!< Selects pin function 14 */
+#define IOCON_FUNC15 0xF /*!< Selects pin function 15 */
+#define IOCON_MODE_INACT (0x0 << 4) /*!< No addition pin function */
+#define IOCON_MODE_PULLDOWN (0x1 << 4) /*!< Selects pull-down function */
+#define IOCON_MODE_PULLUP (0x2 << 4) /*!< Selects pull-up function */
+#define IOCON_MODE_REPEATER (0x3 << 4) /*!< Selects pin repeater function */
+#define IOCON_HYS_EN (0x1 << 6) /*!< Enables hysteresis */
+#define IOCON_GPIO_MODE (0x1 << 6) /*!< GPIO Mode */
+#define IOCON_I2C_SLEW (0x0 << 6) /*!< I2C Slew Rate Control */
+#define IOCON_INV_EN (0x1 << 7) /*!< Enables invert function on input */
+#define IOCON_ANALOG_EN (0x0 << 8) /*!< Enables analog function by setting 0 to bit 7 */
+#define IOCON_DIGITAL_EN (0x1 << 8) /*!< Enables digital function by setting 1 to bit 7(default) */
+#define IOCON_STDI2C_EN (0x1 << 9) /*!< I2C standard mode/fast-mode */
+#define IOCON_FASTI2C_EN (0x3 << 9) /*!< I2C Fast-mode Plus and high-speed slave */
+#define IOCON_INPFILT_OFF (0x1 << 9) /*!< Input filter Off for GPIO pins */
+#define IOCON_INPFILT_ON (0x0 << 9) /*!< Input filter On for GPIO pins */
+#define IOCON_OPENDRAIN_EN (0x1 << 11) /*!< Enables open-drain function */
+#define IOCON_S_MODE_0CLK (0x0 << 12) /*!< Bypass input filter */
+#define IOCON_S_MODE_1CLK (0x1 << 12) /*!< Input pulses shorter than 1 filter clock are rejected */
+#define IOCON_S_MODE_2CLK (0x2 << 12) /*!< Input pulses shorter than 2 filter clock2 are rejected */
+#define IOCON_S_MODE_3CLK (0x3 << 12) /*!< Input pulses shorter than 3 filter clock2 are rejected */
+#define IOCON_S_MODE(clks) ((clks) << 12) /*!< Select clocks for digital input filter mode */
+#define IOCON_CLKDIV(div) \
+ ((div) << 14) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */
#else
- #define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */
- #define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */
- #define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */
- #define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */
- #define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */
- #define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */
- #define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */
- #define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */
- #define IOCON_MODE_INACT (0x0 << 3) /*!< No addition pin function */
- #define IOCON_MODE_PULLDOWN (0x1 << 3) /*!< Selects pull-down function */
- #define IOCON_MODE_PULLUP (0x2 << 3) /*!< Selects pull-up function */
- #define IOCON_MODE_REPEATER (0x3 << 3) /*!< Selects pin repeater function */
- #define IOCON_HYS_EN (0x1 << 5) /*!< Enables hysteresis */
- #define IOCON_GPIO_MODE (0x1 << 5) /*!< GPIO Mode */
- #define IOCON_I2C_SLEW (0x1 << 5) /*!< I2C Slew Rate Control */
- #define IOCON_INV_EN (0x1 << 6) /*!< Enables invert function on input */
- #define IOCON_ANALOG_EN (0x0 << 7) /*!< Enables analog function by setting 0 to bit 7 */
- #define IOCON_DIGITAL_EN (0x1 << 7) /*!< Enables digital function by setting 1 to bit 7(default) */
- #define IOCON_STDI2C_EN (0x1 << 8) /*!< I2C standard mode/fast-mode */
- #define IOCON_FASTI2C_EN (0x3 << 8) /*!< I2C Fast-mode Plus and high-speed slave */
- #define IOCON_INPFILT_OFF (0x1 << 8) /*!< Input filter Off for GPIO pins */
- #define IOCON_INPFILT_ON (0x0 << 8) /*!< Input filter On for GPIO pins */
- #define IOCON_OPENDRAIN_EN (0x1 << 10) /*!< Enables open-drain function */
- #define IOCON_S_MODE_0CLK (0x0 << 11) /*!< Bypass input filter */
- #define IOCON_S_MODE_1CLK (0x1 << 11) /*!< Input pulses shorter than 1 filter clock are rejected */
- #define IOCON_S_MODE_2CLK (0x2 << 11) /*!< Input pulses shorter than 2 filter clock2 are rejected */
- #define IOCON_S_MODE_3CLK (0x3 << 11) /*!< Input pulses shorter than 3 filter clock2 are rejected */
- #define IOCON_S_MODE(clks) ((clks) << 11) /*!< Select clocks for digital input filter mode */
- #define IOCON_CLKDIV(div) \
- ((div) << 13) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */
+#define IOCON_FUNC0 0x0 /*!< Selects pin function 0 */
+#define IOCON_FUNC1 0x1 /*!< Selects pin function 1 */
+#define IOCON_FUNC2 0x2 /*!< Selects pin function 2 */
+#define IOCON_FUNC3 0x3 /*!< Selects pin function 3 */
+#define IOCON_FUNC4 0x4 /*!< Selects pin function 4 */
+#define IOCON_FUNC5 0x5 /*!< Selects pin function 5 */
+#define IOCON_FUNC6 0x6 /*!< Selects pin function 6 */
+#define IOCON_FUNC7 0x7 /*!< Selects pin function 7 */
+#define IOCON_MODE_INACT (0x0 << 3) /*!< No addition pin function */
+#define IOCON_MODE_PULLDOWN (0x1 << 3) /*!< Selects pull-down function */
+#define IOCON_MODE_PULLUP (0x2 << 3) /*!< Selects pull-up function */
+#define IOCON_MODE_REPEATER (0x3 << 3) /*!< Selects pin repeater function */
+#define IOCON_HYS_EN (0x1 << 5) /*!< Enables hysteresis */
+#define IOCON_GPIO_MODE (0x1 << 5) /*!< GPIO Mode */
+#define IOCON_I2C_SLEW (0x0 << 5) /*!< I2C Slew Rate Control */
+#define IOCON_INV_EN (0x1 << 6) /*!< Enables invert function on input */
+#define IOCON_ANALOG_EN (0x0 << 7) /*!< Enables analog function by setting 0 to bit 7 */
+#define IOCON_DIGITAL_EN (0x1 << 7) /*!< Enables digital function by setting 1 to bit 7(default) */
+#define IOCON_STDI2C_EN (0x1 << 8) /*!< I2C standard mode/fast-mode */
+#define IOCON_FASTI2C_EN (0x3 << 8) /*!< I2C Fast-mode Plus and high-speed slave */
+#define IOCON_INPFILT_OFF (0x1 << 8) /*!< Input filter Off for GPIO pins */
+#define IOCON_INPFILT_ON (0x0 << 8) /*!< Input filter On for GPIO pins */
+#define IOCON_OPENDRAIN_EN (0x1 << 10) /*!< Enables open-drain function */
+#define IOCON_S_MODE_0CLK (0x0 << 11) /*!< Bypass input filter */
+#define IOCON_S_MODE_1CLK (0x1 << 11) /*!< Input pulses shorter than 1 filter clock are rejected */
+#define IOCON_S_MODE_2CLK (0x2 << 11) /*!< Input pulses shorter than 2 filter clock2 are rejected */
+#define IOCON_S_MODE_3CLK (0x3 << 11) /*!< Input pulses shorter than 3 filter clock2 are rejected */
+#define IOCON_S_MODE(clks) ((clks) << 11) /*!< Select clocks for digital input filter mode */
+#define IOCON_CLKDIV(div) \
+ ((div) << 13) /*!< Select peripheral clock divider for input filter sampling clock, 2^n, n=0-6 */
#endif
#if defined(__cplusplus)
extern "C" {
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_lcdc.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_lcdc.c Tue Mar 20 16:56:18 2018 +0000
@@ -1,9 +1,12 @@
/*
+ * The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
+ * All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -149,8 +153,8 @@
if (((kLCDC_DisplaySingleColorSTN8Bit == config->display) && (pcd < 1U)) ||
((kLCDC_DisplayDualColorSTN8Bit == config->display) && (pcd < 4U)) ||
((kLCDC_DisplaySingleMonoSTN4Bit == config->display) && (pcd < 2U)) ||
- ((kLCDC_DisplaySingleMonoSTN8Bit == config->display) && (pcd < 8U)) ||
- ((kLCDC_DisplayDualMonoSTN4Bit == config->display) && (pcd < 8U)) ||
+ ((kLCDC_DisplaySingleMonoSTN8Bit == config->display) && (pcd < 6U)) ||
+ ((kLCDC_DisplayDualMonoSTN4Bit == config->display) && (pcd < 6U)) ||
((kLCDC_DisplayDualMonoSTN8Bit == config->display) && (pcd < 14U)))
{
return false;
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_lcdc.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_lcdc.h Tue Mar 20 16:56:18 2018 +0000
@@ -1,9 +1,12 @@
/*
+ * The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
+ * All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -102,7 +106,7 @@
kLCDC_DisplayDualMonoSTN4Bit =
LCD_CTRL_LCDBW_MASK | LCD_CTRL_LCDDUAL_MASK, /*!< Dual-panel monochrome STN (4-bit bus interface). */
kLCDC_DisplayDualMonoSTN8Bit = LCD_CTRL_LCDBW_MASK | LCD_CTRL_LCDMONO8_MASK |
- LCD_CTRL_LCDDUAL_MASK, /*!< Dual-panel monochrome STN (8-bit bus interface). */
+ LCD_CTRL_LCDDUAL_MASK, /*!< Dual-panel monochrome STN (8-bit bus interface). */
kLCDC_DisplaySingleColorSTN8Bit = 0U, /*!< Single-panel color STN (8-bit bus interface). */
kLCDC_DisplayDualColorSTN8Bit = LCD_CTRL_LCDDUAL_MASK, /*!< Dual-panel coor STN (8-bit bus interface). */
} lcdc_display_t;
@@ -137,9 +141,9 @@
uint8_t lineEndDelay; /*!< The panel clocks between the last pixel of line and the start of line end. */
uint32_t upperPanelAddr; /*!< LCD upper panel base address, must be double-word(64-bit) align. */
uint32_t lowerPanelAddr; /*!< LCD lower panel base address, must be double-word(64-bit) align. */
- lcdc_bpp_t bpp; /*!< LCD bits per pixel. */
+ lcdc_bpp_t bpp; /*!< LCD bits per pixel. */
lcdc_data_format_t dataFormat; /*!< Data format. */
- bool swapRedBlue; /*!< Set true to use BGR format, set false to choose RGB format. */
+ bool swapRedBlue; /*!< Set true to use BGR format, set false to choose RGB format. */
lcdc_display_t display; /*!< The display type. */
} lcdc_config_t;
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mcan.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mcan.c Tue Mar 20 16:56:18 2018 +0000
@@ -1,9 +1,12 @@
/*
+ * The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
+ * All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -835,6 +839,11 @@
assert(s_mcanHandle[0]);
s_mcanIsr(CAN0, s_mcanHandle[0]);
+ /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
}
void CAN0_IRQ1_DriverIRQHandler(void)
@@ -842,6 +851,11 @@
assert(s_mcanHandle[0]);
s_mcanIsr(CAN0, s_mcanHandle[0]);
+ /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
}
#endif
@@ -851,6 +865,11 @@
assert(s_mcanHandle[1]);
s_mcanIsr(CAN1, s_mcanHandle[1]);
+ /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
}
void CAN1_IRQ1_DriverIRQHandler(void)
@@ -858,5 +877,10 @@
assert(s_mcanHandle[1]);
s_mcanIsr(CAN1, s_mcanHandle[1]);
+ /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
}
#endif
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mcan.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mcan.h Tue Mar 20 16:56:18 2018 +0000
@@ -1,9 +1,12 @@
/*
+ * The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
+ * All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -43,8 +47,8 @@
/*! @name Driver version */
/*@{*/
-/*! @brief MCAN driver version 2.0.0. */
-#define MCAN_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*! @brief MCAN driver version 2.0.1. */
+#define MCAN_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
/*@}*/
/*! @brief MCAN transfer status. */
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mrt.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mrt.c Tue Mar 20 16:56:18 2018 +0000 @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mrt.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_mrt.h Tue Mar 20 16:56:18 2018 +0000 @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_otp.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_otp.h Tue Mar 20 16:56:18 2018 +0000 @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_phy.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_phy.c Tue Mar 20 16:56:18 2018 +0000
@@ -1,9 +1,12 @@
/*
+ * The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
+ * All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -88,7 +92,7 @@
while ((idReg != PHY_CONTROL_ID1) && (delay != 0))
{
PHY_Read(base, phyAddr, PHY_ID1_REG, &idReg);
- delay --;
+ delay--;
}
if (!delay)
@@ -118,7 +122,7 @@
do
{
PHY_Read(base, phyAddr, PHY_SEPCIAL_CONTROL_REG, ®);
- delay --;
+ delay--;
} while (delay && ((reg & PHY_SPECIALCTL_AUTONEGDONE_MASK) == 0));
if (!delay)
@@ -180,7 +184,7 @@
status_t PHY_Read(ENET_Type *base, uint32_t phyAddr, uint32_t phyReg, uint32_t *dataPtr)
{
#if defined(FSL_FEATURE_SOC_ENET_COUNT) && (FSL_FEATURE_SOC_ENET_COUNT > 0)
- assert(dataPtr);
+ assert(dataPtr);
uint32_t counter;
@@ -216,7 +220,7 @@
;
*dataPtr = ENET_ReadSMIData(base);
#endif
- return kStatus_Success;
+ return kStatus_Success;
}
status_t PHY_GetLinkStatus(ENET_Type *base, uint32_t phyAddr, bool *status)
@@ -236,7 +240,7 @@
else
{
*status = false;
- }
+ }
}
return result;
}
@@ -272,7 +276,7 @@
else
{ /* 10M speed. */
*speed = kPHY_Speed10M;
- }
+ }
}
return result;
}
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_phy.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_phy.h Tue Mar 20 16:56:18 2018 +0000 @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -111,7 +115,7 @@ * * This function initialize the SMI interface and initialize PHY. * The SMI is the MII management interface between PHY and MAC, which should be - * firstly initialized before any other operation for PHY. + * firstly initialized before any other operation for PHY. The PHY initialize with auto-negotiation. * * @param base ENET peripheral base address. * @param phyAddr The PHY address.
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_pint.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_pint.c Tue Mar 20 16:56:18 2018 +0000
@@ -1,9 +1,12 @@
/*
+ * The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
+ * All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -303,6 +307,13 @@
{
s_pintCallback[kPINT_PinInt0](kPINT_PinInt0, pmstatus);
}
+ /* Clear Pin interrupt after callback */
+ PINT_PinInterruptClrStatus(PINT, kPINT_PinInt0);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
}
#if (FSL_FEATURE_PINT_NUMBER_OF_CONNECTED_OUTPUTS > 1U)
@@ -317,6 +328,13 @@
{
s_pintCallback[kPINT_PinInt1](kPINT_PinInt1, pmstatus);
}
+ /* Clear Pin interrupt after callback */
+ PINT_PinInterruptClrStatus(PINT, kPINT_PinInt1);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
}
#endif
@@ -332,6 +350,13 @@
{
s_pintCallback[kPINT_PinInt2](kPINT_PinInt2, pmstatus);
}
+ /* Clear Pin interrupt after callback */
+ PINT_PinInterruptClrStatus(PINT, kPINT_PinInt2);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
}
#endif
@@ -347,6 +372,13 @@
{
s_pintCallback[kPINT_PinInt3](kPINT_PinInt3, pmstatus);
}
+ /* Clear Pin interrupt after callback */
+ PINT_PinInterruptClrStatus(PINT, kPINT_PinInt3);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
}
#endif
@@ -362,6 +394,13 @@
{
s_pintCallback[kPINT_PinInt4](kPINT_PinInt4, pmstatus);
}
+ /* Clear Pin interrupt after callback */
+ PINT_PinInterruptClrStatus(PINT, kPINT_PinInt4);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
}
#endif
@@ -377,6 +416,13 @@
{
s_pintCallback[kPINT_PinInt5](kPINT_PinInt5, pmstatus);
}
+ /* Clear Pin interrupt after callback */
+ PINT_PinInterruptClrStatus(PINT, kPINT_PinInt5);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
}
#endif
@@ -392,6 +438,13 @@
{
s_pintCallback[kPINT_PinInt6](kPINT_PinInt6, pmstatus);
}
+ /* Clear Pin interrupt after callback */
+ PINT_PinInterruptClrStatus(PINT, kPINT_PinInt6);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
}
#endif
@@ -407,5 +460,12 @@
{
s_pintCallback[kPINT_PinInt7](kPINT_PinInt7, pmstatus);
}
+ /* Clear Pin interrupt after callback */
+ PINT_PinInterruptClrStatus(PINT, kPINT_PinInt7);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
}
#endif
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_pint.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_pint.h Tue Mar 20 16:56:18 2018 +0000 @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_power.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_power.c Tue Mar 20 16:56:18 2018 +0000 @@ -1,10 +1,13 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright (c) 2016, NXP * All rights reserved. * + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -17,6 +20,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_power.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_power.h Tue Mar 20 16:56:18 2018 +0000
@@ -1,10 +1,13 @@
/*
+ * The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright (c) 2016, NXP
* All rights reserved.
*
+ *
* Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -17,6 +20,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -37,6 +41,12 @@
* Definitions
******************************************************************************/
+/*! @name Driver version */
+/*@{*/
+/*! @brief power driver version 2.0.0. */
+#define FSL_POWER_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
#define MAKE_PD_BITS(reg, slot) ((reg << 8) | slot)
#define PDRCFG0 0x0U
#define PDRCFG1 0x1U
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_reset.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_reset.c Tue Mar 20 16:56:18 2018 +0000 @@ -1,10 +1,13 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright (c) 2016, NXP * All rights reserved. * + * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -17,6 +20,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_reset.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_reset.h Tue Mar 20 16:56:18 2018 +0000
@@ -1,10 +1,13 @@
/*
+ * The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright (c) 2016, NXP
* All rights reserved.
*
+ *
* Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -17,6 +20,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -47,6 +51,12 @@
* Definitions
******************************************************************************/
+/*! @name Driver version */
+/*@{*/
+/*! @brief reset driver version 2.0.0. */
+#define FSL_RESET_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
/*!
* @brief Enumeration for peripheral reset control bits
*
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rit.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rit.c Tue Mar 20 16:56:18 2018 +0000 @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rit.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rit.h Tue Mar 20 16:56:18 2018 +0000 @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rng.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rng.h Tue Mar 20 16:56:18 2018 +0000 @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rtc.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rtc.c Tue Mar 20 16:56:18 2018 +0000
@@ -1,9 +1,12 @@
/*
+ * The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
+ * All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -215,8 +219,10 @@
/* Make sure the reset bit is cleared */
base->CTRL &= ~RTC_CTRL_SWRESET_MASK;
+#if !(defined(FSL_FEATURE_RTC_HAS_NO_OSC_PD) && FSL_FEATURE_RTC_HAS_NO_OSC_PD)
/* Make sure the RTC OSC is powered up */
base->CTRL &= ~RTC_CTRL_RTC_OSC_PD_MASK;
+#endif
}
status_t RTC_SetDatetime(RTC_Type *base, const rtc_datetime_t *datetime)
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rtc.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_rtc.h Tue Mar 20 16:56:18 2018 +0000 @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sctimer.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sctimer.c Tue Mar 20 16:56:18 2018 +0000
@@ -1,9 +1,12 @@
/*
+ * The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
+ * All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -532,4 +536,9 @@
void SCT0_IRQHandler(void)
{
s_sctimerIsr(SCT0);
+ /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
}
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sctimer.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sctimer.h Tue Mar 20 16:56:18 2018 +0000 @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sdif.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sdif.c Tue Mar 20 16:56:18 2018 +0000
@@ -1,9 +1,12 @@
/*
+ * The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
+ * All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -37,6 +41,25 @@
/* Typedef for interrupt handler. */
typedef void (*sdif_isr_t)(SDIF_Type *base, sdif_handle_t *handle);
+/*! @brief convert the name here, due to RM use SDIO */
+#define SDIF_DriverIRQHandler SDIO_DriverIRQHandler
+/*! @brief define the controller support sd/sdio card version 2.0 */
+#define SDIF_SUPPORT_SD_VERSION (0x20)
+/*! @brief define the controller support mmc card version 4.4 */
+#define SDIF_SUPPORT_MMC_VERSION (0x44)
+/*! @brief define the timeout counter */
+#define SDIF_TIMEOUT_VALUE (65535U)
+/*! @brief this value can be any value */
+#define SDIF_POLL_DEMAND_VALUE (0xFFU)
+/*! @brief DMA descriptor buffer1 size */
+#define SDIF_DMA_DESCRIPTOR_BUFFER1_SIZE(x) (x & 0x1FFFU)
+/*! @brief DMA descriptor buffer2 size */
+#define SDIF_DMA_DESCRIPTOR_BUFFER2_SIZE(x) ((x & 0x1FFFU) << 13U)
+/*! @brief RX water mark value */
+#define SDIF_RX_WATERMARK (15U)
+/*! @brief TX water mark value */
+#define SDIF_TX_WATERMARK (16U)
+
/*******************************************************************************
* Prototypes
******************************************************************************/
@@ -141,9 +164,18 @@
/*
* @brief handle sdio interrupt
* This function will call the SDIO interrupt callback
+* @param SDIF base address
* @param SDIF handle
*/
-static void SDIF_TransferHandleSDIOInterrupt(sdif_handle_t *handle);
+static void SDIF_TransferHandleSDIOInterrupt(SDIF_Type *base, sdif_handle_t *handle);
+
+/*
+* @brief handle card detect
+* This function will call the cardInserted callback
+* @param SDIF base addres
+* @param SDIF handle
+*/
+static void SDIF_TransferHandleCardDetect(SDIF_Type *base, sdif_handle_t *handle);
/*******************************************************************************
* Variables
@@ -288,19 +320,18 @@
do
{
status = SDIF_GetInterruptStatus(base);
- if ((status &
- (kSDIF_ResponseError | kSDIF_ResponseCRCError | kSDIF_ResponseTimeout | kSDIF_HardwareLockError)) != 0u)
- {
- SDIF_ClearInterruptStatus(base, status & (kSDIF_ResponseError | kSDIF_ResponseCRCError |
- kSDIF_ResponseTimeout | kSDIF_HardwareLockError));
- return kStatus_SDIF_SendCmdFail;
- }
} while ((status & kSDIF_CommandDone) != kSDIF_CommandDone);
-
- /* clear the command done bit */
- SDIF_ClearInterruptStatus(base, status & kSDIF_CommandDone);
-
- return SDIF_ReadCommandResponse(base, command);
+ /* clear interrupt status flag first */
+ SDIF_ClearInterruptStatus(base, status);
+ if ((status & (kSDIF_ResponseError | kSDIF_ResponseCRCError | kSDIF_ResponseTimeout | kSDIF_HardwareLockError)) !=
+ 0u)
+ {
+ return kStatus_SDIF_SendCmdFail;
+ }
+ else
+ {
+ return SDIF_ReadCommandResponse(base, command);
+ }
}
status_t SDIF_ReleaseDMADescriptor(SDIF_Type *base, sdif_dma_config_t *dmaConfig)
@@ -675,68 +706,35 @@
void SDIF_ConfigClockDelay(uint32_t target_HZ, uint32_t divider)
{
- /*config the clock delay and pharse shift
- *should config the clk_in_drv,
- *clk_in_sample to meet the min hold and
- *setup time
- */
- if (target_HZ <= kSDIF_Freq400KHZ)
+ uint32_t sdioClkCtrl = SYSCON->SDIOCLKCTRL;
+
+ if (target_HZ >= SDIF_CLOCK_RANGE_NEED_DELAY)
{
- /*min hold time:5ns
- * min setup time: 5ns
- * delay = (x+1)*250ps
- */
- SYSCON->SDIOCLKCTRL = SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK |
- SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(SDIF_INDENTIFICATION_MODE_SAMPLE_DELAY) |
- SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK |
- SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(SDIF_INDENTIFICATION_MODE_DRV_DELAY);
- }
- else if (target_HZ >= kSDIF_Freq50MHZ)
- {
- /*
- * user need to pay attention to this parameter
- * can be change the setting for you card and board
- * min hold time:2ns
- * min setup time: 6ns
- * delay = (x+1)*250ps
- */
- SYSCON->SDIOCLKCTRL = SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK |
- SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(SDIF_HIGHSPEED_50MHZ_SAMPLE_DELAY) |
- SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK |
- SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(SDIF_HIGHSPEED_50MHZ_DRV_DELAY);
- /* means the input clock = 2 * card clock,
- * can use clock pharse shift tech
- */
if (divider == 1U)
{
- SYSCON->SDIOCLKCTRL |= SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK |
- SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE(kSDIF_ClcokPharseShift90) |
- SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE(kSDIF_ClcokPharseShift180);
+#if defined(SDIF_HIGHSPEED_SAMPLE_PHASE_SHIFT) && (SDIF_HIGHSPEED_SAMPLE_PHASE_SHIFT != 0U)
+ sdioClkCtrl |= SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK |
+ SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE(SDIF_HIGHSPEED_SAMPLE_PHASE_SHIFT);
+#endif
+#if defined(SDIF_HIGHSPEED_DRV_PHASE_SHIFT) && (SDIF_HIGHSPEED_DRV_PHASE_SHIFT != 0U)
+ sdioClkCtrl |= SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK |
+ SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE(SDIF_HIGHSPEED_DRV_PHASE_SHIFT);
+#endif
+ }
+ else
+ {
+#ifdef SDIF_HIGHSPEED_SAMPLE_DELAY
+ sdioClkCtrl |= SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK |
+ SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(SDIF_HIGHSPEED_SAMPLE_DELAY);
+#endif
+#ifdef SDIF_HIGHSPEED_DRV_DELAY
+ sdioClkCtrl |= SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK |
+ SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(SDIF_HIGHSPEED_DRV_DELAY);
+#endif
}
}
- else
- {
- /*
- * user need to pay attention to this parameter
- * can be change the setting for you card and board
- * min hold time:5ns
- * min setup time: 5ns
- * delay = (x+1)*250ps
- */
- SYSCON->SDIOCLKCTRL = SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY_ACTIVE_MASK |
- SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_DELAY(SDIF_HIGHSPEED_25MHZ_SAMPLE_DELAY) |
- SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY_ACTIVE_MASK |
- SYSCON_SDIOCLKCTRL_CCLK_DRV_DELAY(SDIF_HIGHSPEED_25MHZ_DRV_DELAY);
- /* means the input clock = 2 * card clock,
- * can use clock pharse shift tech
- */
- if (divider == 1U)
- {
- SYSCON->SDIOCLKCTRL |= SYSCON_SDIOCLKCTRL_PHASE_ACTIVE_MASK |
- SYSCON_SDIOCLKCTRL_CCLK_SAMPLE_PHASE(kSDIF_ClcokPharseShift90) |
- SYSCON_SDIOCLKCTRL_CCLK_DRV_PHASE(kSDIF_ClcokPharseShift90);
- }
- }
+
+ SYSCON->SDIOCLKCTRL = sdioClkCtrl;
}
uint32_t SDIF_SetCardClock(SDIF_Type *base, uint32_t srcClock_Hz, uint32_t target_HZ)
@@ -1098,7 +1096,7 @@
handle->callback.DMADesUnavailable = callback->DMADesUnavailable;
handle->callback.CommandReload = callback->CommandReload;
handle->callback.TransferComplete = callback->TransferComplete;
-
+ handle->callback.cardInserted = callback->cardInserted;
handle->userData = userData;
/* Save the handle in global variables to support the double weak mechanism. */
@@ -1130,26 +1128,32 @@
{
assert(handle->command);
- /* transfer error */
- if (interruptFlags & (kSDIF_ResponseError | kSDIF_ResponseCRCError | kSDIF_ResponseTimeout))
- {
- handle->callback.TransferComplete(base, handle, kStatus_SDIF_SendCmdFail, handle->userData);
- }
/* cmd buffer full, in this condition user need re-send the command */
- else if (interruptFlags & kSDIF_HardwareLockError)
+ if (interruptFlags & kSDIF_HardwareLockError)
{
if (handle->callback.CommandReload)
{
- handle->callback.CommandReload();
+ handle->callback.CommandReload(base, handle->userData);
}
}
- /* transfer command success */
+ /* transfer command done */
else
{
- SDIF_ReadCommandResponse(base, handle->command);
- if (((handle->data) == NULL) && (handle->callback.TransferComplete))
+ if ((kSDIF_CommandDone & interruptFlags) != 0U)
{
- handle->callback.TransferComplete(base, handle, kStatus_Success, handle->userData);
+ /* transfer error */
+ if (interruptFlags & (kSDIF_ResponseError | kSDIF_ResponseCRCError | kSDIF_ResponseTimeout))
+ {
+ handle->callback.TransferComplete(base, handle, kStatus_SDIF_SendCmdFail, handle->userData);
+ }
+ else
+ {
+ SDIF_ReadCommandResponse(base, handle->command);
+ if (((handle->data) == NULL) && (handle->callback.TransferComplete))
+ {
+ handle->callback.TransferComplete(base, handle, kStatus_Success, handle->userData);
+ }
+ }
}
}
}
@@ -1217,7 +1221,7 @@
{
if (handle->callback.DMADesUnavailable)
{
- handle->callback.DMADesUnavailable();
+ handle->callback.DMADesUnavailable(base, handle->userData);
}
}
else if ((interruptFlags & (kSDIF_AbnormalInterruptSummary | kSDIF_DMACardErrorSummary)) &&
@@ -1232,11 +1236,29 @@
}
}
-static void SDIF_TransferHandleSDIOInterrupt(sdif_handle_t *handle)
+static void SDIF_TransferHandleSDIOInterrupt(SDIF_Type *base, sdif_handle_t *handle)
{
if (handle->callback.SDIOInterrupt != NULL)
{
- handle->callback.SDIOInterrupt();
+ handle->callback.SDIOInterrupt(base, handle->userData);
+ }
+}
+
+static void SDIF_TransferHandleCardDetect(SDIF_Type *base, sdif_handle_t *handle)
+{
+ if (SDIF_DetectCardInsert(base, false))
+ {
+ if ((handle->callback.cardInserted) != NULL)
+ {
+ handle->callback.cardInserted(base, handle->userData);
+ }
+ }
+ else
+ {
+ if ((handle->callback.cardRemoved) != NULL)
+ {
+ handle->callback.cardRemoved(base, handle->userData);
+ }
}
}
@@ -1262,12 +1284,16 @@
}
if (interruptFlags & kSDIF_SDIOInterrupt)
{
- SDIF_TransferHandleSDIOInterrupt(handle);
+ SDIF_TransferHandleSDIOInterrupt(base, handle);
}
if (dmaInterruptFlags & kSDIF_DMAAllStatus)
{
SDIF_TransferHandleDMA(base, handle, dmaInterruptFlags);
}
+ if (interruptFlags & kSDIF_CardDetect)
+ {
+ SDIF_TransferHandleCardDetect(base, handle);
+ }
SDIF_ClearInterruptStatus(base, interruptFlags);
SDIF_ClearInternalDMAStatus(base, dmaInterruptFlags);
@@ -1289,5 +1315,10 @@
assert(s_sdifHandle[0]);
s_sdifIsr(SDIF, s_sdifHandle[0]);
+/* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
}
#endif
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sdif.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sdif.h Tue Mar 20 16:56:18 2018 +0000
@@ -1,9 +1,12 @@
/*
+ * The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
+ * All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -37,40 +41,56 @@
* @{
*/
-/******************************************************************************
+/**********************************
* Definitions.
*****************************************************************************/
/*! @name Driver version */
/*@{*/
-/*! @brief Driver version 2.0.1. */
-#define FSL_SDIF_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 1U))
+/*! @brief Driver version 2.0.4. */
+#define FSL_SDIF_DRIVER_VERSION (MAKE_VERSION(2U, 0U, 4U))
/*@}*/
-#define SDIF_DriverIRQHandler SDIO_DriverIRQHandler /*!< convert the name here, due to RM use SDIO */
-
-#define SDIF_SUPPORT_SD_VERSION (0x20) /*!< define the controller support sd/sdio card version 2.0 */
-#define SDIF_SUPPORT_MMC_VERSION (0x44) /*!< define the controller support mmc card version 4.4 */
-
-#define SDIF_TIMEOUT_VALUE (65535U) /*!< define the timeout counter */
-#define SDIF_POLL_DEMAND_VALUE (0xFFU) /*!< this value can be any value */
+/*! @brief SDIOCLKCTRL setting
+* Below clock delay setting should depend on specific platform, so
+* it can be redefined when timing mismatch issue occur.
+* Such as: response error/CRC error and so on
+*/
+/*! @brief clock range value which need to add delay to avoid timing issue */
+#ifndef SDIF_CLOCK_RANGE_NEED_DELAY
+#define SDIF_CLOCK_RANGE_NEED_DELAY (50000000U)
+#endif
-#define SDIF_DMA_DESCRIPTOR_BUFFER1_SIZE(x) (x & 0x1FFFU) /*!< DMA descriptor buffer1 size */
-#define SDIF_DMA_DESCRIPTOR_BUFFER2_SIZE(x) ((x & 0x1FFFU) << 13U) /*!<DMA descriptor buffer2 size */
-#define SDIF_RX_WATERMARK (15U) /*!<RX water mark value */
-#define SDIF_TX_WATERMARK (16U) /*!<TX water mark value */
+/*
+* Fixed delay configuration
+* min hold time:2ns
+* min setup time: 6ns
+* delay = (x+1)*250ps
+*/
+/*! @brief High speed mode clk_sample fixed delay*/
+#ifndef SDIF_HIGHSPEED_SAMPLE_DELAY
+#define SDIF_HIGHSPEED_SAMPLE_DELAY (0U)
+#endif
+/*! @brief High speed mode clk_drv fixed delay */
+#ifndef SDIF_HIGHSPEED_DRV_DELAY
+#define SDIF_HIGHSPEED_DRV_DELAY (0x1FU)
+#endif
-/*! @brief SDIOCLKCTRL setting
-* below clock delay setting should meet you board layout
-* user can change it when you meet timing mismatch issue
-* such as: response error/CRC error and so on
+/*
+* Pharse shift delay configuration
+* 0 degree: no delay
+* 90 degree: 0.25/source clk value
+* 180 degree: 0.50/source clk value
+* 270 degree: 0.75/source clk value
*/
-#define SDIF_INDENTIFICATION_MODE_SAMPLE_DELAY (0X17U)
-#define SDIF_INDENTIFICATION_MODE_DRV_DELAY (0X17U)
-#define SDIF_HIGHSPEED_25MHZ_SAMPLE_DELAY (0x10U)
-#define SDIF_HIGHSPEED_25MHZ_DRV_DELAY (0x10U)
-#define SDIF_HIGHSPEED_50MHZ_SAMPLE_DELAY (0x1FU)
-#define SDIF_HIGHSPEED_50MHZ_DRV_DELAY (0x1FU)
+/*! @brief High speed mode clk_sample pharse shift */
+#ifndef SDIF_HIGHSPEED_SAMPLE_PHASE_SHIFT
+#define SDIF_HIGHSPEED_SAMPLE_PHASE_SHIFT (0U)
+#endif
+/*! @brief High speed mode clk_drv pharse shift */
+#ifndef SDIF_HIGHSPEED_DRV_PHASE_SHIFT
+#define SDIF_HIGHSPEED_DRV_PHASE_SHIFT (1U) /* 90 degrees clk_drv pharse delay */
+#endif
/*! @brief SDIF status */
enum _sdif_status
@@ -257,22 +277,6 @@
kSDIF_DualDMAMode = 0x02U, /* dual mode is one descriptor with two buffer */
} sdif_dma_mode_t;
-/*! @brief define the card work freq mode */
-enum _sdif_card_freq
-{
- kSDIF_Freq50MHZ = 50000000U, /*!< 50MHZ mode*/
- kSDIF_Freq400KHZ = 400000U, /*!< identificatioin mode*/
-};
-
-/*! @brief define the clock pharse shift */
-enum _sdif_clock_pharse_shift
-{
- kSDIF_ClcokPharseShift0, /*!< clock pharse shift 0*/
- kSDIF_ClcokPharseShift90, /*!< clock pharse shift 90*/
- kSDIF_ClcokPharseShift180, /*!< clock pharse shift 180*/
- kSDIF_ClcokPharseShift270, /*!< clock pharse shift 270*/
-};
-
/*! @brief define the internal DMA descriptor */
typedef struct _sdif_dma_descriptor
{
@@ -368,9 +372,11 @@
/*! @brief sdif callback functions. */
typedef struct _sdif_transfer_callback
{
- void (*SDIOInterrupt)(void); /*!< SDIO card interrupt occurs */
- void (*DMADesUnavailable)(void); /*!< DMA descriptor unavailable */
- void (*CommandReload)(void); /*!< command buffer full,need re-load */
+ void (*cardInserted)(SDIF_Type *base, void *userData); /*!< card insert call back */
+ void (*cardRemoved)(SDIF_Type *base, void *userData); /*!< card remove call back */
+ void (*SDIOInterrupt)(SDIF_Type *base, void *userData); /*!< SDIO card interrupt occurs */
+ void (*DMADesUnavailable)(SDIF_Type *base, void *userData); /*!< DMA descriptor unavailable */
+ void (*CommandReload)(SDIF_Type *base, void *userData); /*!< command buffer full,need re-load */
void (*TransferComplete)(SDIF_Type *base,
void *handle,
status_t status,
@@ -448,17 +454,18 @@
* @brief SDIF module detect card insert status function.
* @param base SDIF peripheral base address.
* @param data3 indicate use data3 as card insert detect pin
- * will return the data3 PIN status in this condition
+ * @retval 1 card is inserted
+ * 0 card is removed
*/
static inline uint32_t SDIF_DetectCardInsert(SDIF_Type *base, bool data3)
{
if (data3)
{
- return base->STATUS & SDIF_STATUS_DATA_3_STATUS_MASK;
+ return (base->STATUS & SDIF_STATUS_DATA_3_STATUS_MASK) == SDIF_STATUS_DATA_3_STATUS_MASK ? 1U : 0U;
}
else
{
- return base->CDETECT & SDIF_CDETECT_CARD_DETECT_MASK;
+ return (base->CDETECT & SDIF_CDETECT_CARD_DETECT_MASK) == 0U ? 1U : 0U;
}
}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sha.c Tue Mar 20 16:56:18 2018 +0000
@@ -0,0 +1,489 @@
+/*
+ * The Clear BSD License
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+
+#include "fsl_sha.h"
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*!< SHA-1 and SHA-256 block size */
+#define SHA_BLOCK_SIZE 64
+
+/*!< Use standard C library memcpy */
+#define sha_memcpy memcpy
+
+/*! Internal states of the HASH creation process */
+typedef enum _sha_algo_state
+{
+ kSHA_HashInit = 1u, /*!< Init state, the NEW bit in SHA Control register has not been written yet. */
+ kSHA_HashUpdate, /*!< Update state, DIGEST registers contain running hash, NEW bit in SHA control register has been
+ written. */
+} sha_algo_state_t;
+
+/*! 64-byte block represented as byte array of 16 32-bit words */
+typedef union _sha_hash_block
+{
+ uint32_t w[SHA_BLOCK_SIZE / 4]; /*!< array of 32-bit words */
+ uint8_t b[SHA_BLOCK_SIZE]; /*!< byte array */
+} sha_block_t;
+
+/*! internal sha context structure */
+typedef struct _sha_ctx_internal
+{
+ sha_block_t blk; /*!< memory buffer. only full 64-byte blocks are written to SHA during hash updates */
+ size_t blksz; /*!< number of valid bytes in memory buffer */
+ sha_algo_t algo; /*!< selected algorithm from the set of supported algorithms */
+ sha_algo_state_t state; /*!< finite machine state of the hash software process */
+ size_t fullMessageSize; /*!< track message size during SHA_Update(). The value is used for padding. */
+} sha_ctx_internal_t;
+
+/*!< SHA-1 and SHA-256 digest length in bytes */
+enum _sha_digest_len
+{
+ kSHA_OutLenSha1 = 20u,
+ kSHA_OutLenSha256 = 32u,
+};
+
+/*!< macro for checking build time condition. It is used to assure the sha_ctx_internal_t can fit into sha_ctx_t */
+#define BUILD_ASSERT(condition, msg) extern int msg[1 - 2 * (!(condition))] __attribute__((unused))
+
+/*******************************************************************************
+ * Code
+ ******************************************************************************/
+
+/*!
+ * @brief LDM to SHA engine INDATA and ALIAS registers.
+ *
+ * This function writes 16 words starting from the src address (must be word aligned)
+ * to the dst address. Dst address does not increment (destination is peripheral module register INDATA).
+ * Src address increments to load 16 consecutive words.
+ *
+ * @param dst peripheral register address (word aligned)
+ * @param src address of the input 512-bit block (16 words) (word aligned)
+ *
+ */
+__STATIC_INLINE void sha_ldm_stm_16_words(volatile uint32_t *dst, const uint32_t *src)
+{
+ for (int i = 0; i < 8; i++)
+ {
+ dst[i] = src[i];
+ }
+ src += 8u;
+ for (int i = 0; i < 8; i++)
+ {
+ dst[i] = src[i];
+ }
+}
+
+/*!
+ * @brief Swap bytes withing 32-bit word.
+ *
+ * This function changes endianess of a 32-bit word.
+ *
+ * @param in 32-bit unsigned integer
+ * @return 32-bit unsigned integer with different endianess (big endian to little endian and vice versa).
+ */
+static uint32_t swap_bytes(uint32_t in)
+{
+ return (((in & 0x000000ffu) << 24) | ((in & 0x0000ff00u) << 8) | ((in & 0x00ff0000u) >> 8) |
+ ((in & 0xff000000u) >> 24));
+}
+
+/*!
+ * @brief Check validity of algoritm.
+ *
+ * This function checks the validity of input argument.
+ *
+ * @param algo Tested algorithm value.
+ * @return kStatus_Success if valid, kStatus_InvalidArgument otherwise.
+ */
+static status_t sha_check_input_alg(sha_algo_t algo)
+{
+ if ((algo != kSHA_Sha1) && (algo != kSHA_Sha256))
+ {
+ return kStatus_InvalidArgument;
+ }
+ return kStatus_Success;
+}
+
+/*!
+ * @brief Check validity of input arguments.
+ *
+ * This function checks the validity of input arguments.
+ *
+ * @param base SHA peripheral base address.
+ * @param ctx Memory buffer given by user application where the SHA_Init/SHA_Update/SHA_Finish store context.
+ * @param algo Tested algorithm value.
+ * @return kStatus_Success if valid, kStatus_InvalidArgument otherwise.
+ */
+static status_t sha_check_input_args(SHA_Type *base, sha_ctx_t *ctx, sha_algo_t algo)
+{
+ /* Check validity of input algorithm */
+ if (kStatus_Success != sha_check_input_alg(algo))
+ {
+ return kStatus_InvalidArgument;
+ }
+
+ if ((NULL == ctx) || (NULL == base))
+ {
+ return kStatus_InvalidArgument;
+ }
+
+ return kStatus_Success;
+}
+
+/*!
+ * @brief Check validity of internal software context.
+ *
+ * This function checks if the internal context structure looks correct.
+ *
+ * @param ctxInternal Internal context.
+ * @param message Input message address.
+ * @return kStatus_Success if valid, kStatus_InvalidArgument otherwise.
+ */
+static status_t sha_check_context(sha_ctx_internal_t *ctxInternal, const uint8_t *message)
+{
+ if ((NULL == message) || (NULL == ctxInternal) || (kStatus_Success != sha_check_input_alg(ctxInternal->algo)))
+ {
+ return kStatus_InvalidArgument;
+ }
+ return kStatus_Success;
+}
+
+/*!
+ * @brief Initialize the SHA engine for new hash.
+ *
+ * This function sets NEW and MODE fields in SHA Control register to start new hash.
+ *
+ * @param base SHA peripheral base address.
+ * @param ctxInternal Internal context.
+ */
+static void sha_engine_init(SHA_Type *base, sha_ctx_internal_t *ctxInternal)
+{
+ uint32_t shaCtrl;
+
+ if (kSHA_Sha1 == ctxInternal->algo)
+ {
+ shaCtrl = SHA_CTRL_MODE(1) | SHA_CTRL_NEW(1);
+ }
+ else
+ {
+ shaCtrl = SHA_CTRL_MODE(2) | SHA_CTRL_NEW(1);
+ }
+ base->CTRL = shaCtrl;
+}
+
+/*!
+ * @brief Load 512-bit block (16 words) into SHA engine.
+ *
+ * This function aligns the input block and moves it into SHA engine INDATA.
+ * CPU polls the WAITING bit and then moves data by using LDM and STM instructions.
+ *
+ * @param base SHA peripheral base address.
+ * @param blk 512-bit block
+ */
+static void sha_one_block(SHA_Type *base, const uint8_t *blk)
+{
+ uint32_t temp[SHA_BLOCK_SIZE / sizeof(uint32_t)];
+ const uint32_t *actBlk;
+
+ /* make sure the 512-bit block is word aligned */
+ if ((uintptr_t)blk & 0x3u)
+ {
+ sha_memcpy(temp, blk, SHA_BLOCK_SIZE);
+ actBlk = (const uint32_t *)(uintptr_t)temp;
+ }
+ else
+ {
+ actBlk = (const uint32_t *)(uintptr_t)blk;
+ }
+
+ /* poll waiting. */
+ while (0 == (base->STATUS & SHA_STATUS_WAITING_MASK))
+ {
+ }
+ /* feed INDATA (and ALIASes). use STM instruction. */
+ sha_ldm_stm_16_words(&base->INDATA, actBlk);
+}
+
+/*!
+ * @brief Adds message to current hash.
+ *
+ * This function merges the message to fill the internal buffer, empties the internal buffer if
+ * it becomes full, then process all remaining message data.
+ *
+ *
+ * @param base SHA peripheral base address.
+ * @param ctxInternal Internal context.
+ * @param message Input message.
+ * @param messageSize Size of input message in bytes.
+ * @return kStatus_Success.
+ */
+static status_t sha_process_message_data(SHA_Type *base,
+ sha_ctx_internal_t *ctxInternal,
+ const uint8_t *message,
+ size_t messageSize)
+{
+ /* first fill the internal buffer to full block */
+ size_t toCopy = SHA_BLOCK_SIZE - ctxInternal->blksz;
+ sha_memcpy(&ctxInternal->blk.b[ctxInternal->blksz], message, toCopy);
+ message += toCopy;
+ messageSize -= toCopy;
+
+ /* process full internal block */
+ sha_one_block(base, &ctxInternal->blk.b[0]);
+
+ /* process all full blocks in message[] */
+ while (messageSize >= SHA_BLOCK_SIZE)
+ {
+ sha_one_block(base, message);
+ message += SHA_BLOCK_SIZE;
+ messageSize -= SHA_BLOCK_SIZE;
+ }
+
+ /* copy last incomplete message bytes into internal block */
+ sha_memcpy(&ctxInternal->blk.b[0], message, messageSize);
+ ctxInternal->blksz = messageSize;
+ return kStatus_Success;
+}
+
+/*!
+ * @brief Finalize the running hash to make digest.
+ *
+ * This function empties the internal buffer, adds padding bits, and generates final digest.
+ *
+ * @param base SHA peripheral base address.
+ * @param ctxInternal Internal context.
+ * @return kStatus_Success.
+ */
+static status_t sha_finalize(SHA_Type *base, sha_ctx_internal_t *ctxInternal)
+{
+ sha_block_t lastBlock;
+
+ memset(&lastBlock, 0, sizeof(sha_block_t));
+
+ /* this is last call, so need to flush buffered message bytes along with padding */
+ if (ctxInternal->blksz <= 55u)
+ {
+ /* last data is 440 bits or less. */
+ sha_memcpy(&lastBlock.b[0], &ctxInternal->blk.b[0], ctxInternal->blksz);
+ lastBlock.b[ctxInternal->blksz] = (uint8_t)0x80U;
+ lastBlock.w[SHA_BLOCK_SIZE / 4 - 1] = swap_bytes(8u * ctxInternal->fullMessageSize);
+ sha_one_block(base, &lastBlock.b[0]);
+ }
+ else
+ {
+ if (ctxInternal->blksz < SHA_BLOCK_SIZE)
+ {
+ ctxInternal->blk.b[ctxInternal->blksz] = (uint8_t)0x80U;
+ for (uint32_t i = ctxInternal->blksz + 1u; i < SHA_BLOCK_SIZE; i++)
+ {
+ ctxInternal->blk.b[i] = 0;
+ }
+ }
+ else
+ {
+ lastBlock.b[0] = (uint8_t)0x80U;
+ }
+
+ sha_one_block(base, &ctxInternal->blk.b[0]);
+ lastBlock.w[SHA_BLOCK_SIZE / 4 - 1] = swap_bytes(8u * ctxInternal->fullMessageSize);
+ sha_one_block(base, &lastBlock.b[0]);
+ }
+ /* poll wait for final digest */
+ while (0 == (base->STATUS & SHA_STATUS_DIGEST_MASK))
+ {
+ }
+ return kStatus_Success;
+}
+
+/*!
+ * @brief Read DIGEST registers.
+ *
+ * This function copies DIGEST to output buffer.
+ *
+ * @param base SHA peripheral base address.
+ * @param[out] output Output buffer.
+ * @param Number of bytes to copy.
+ * @return kStatus_Success.
+ */
+static void sha_get_digest(SHA_Type *base, uint8_t *output, size_t outputSize)
+{
+ uint32_t digest[8];
+
+ for (int i = 0; i < 8; i++)
+ {
+ digest[i] = swap_bytes(base->DIGEST[i]);
+ }
+
+ if (outputSize > sizeof(digest))
+ {
+ outputSize = sizeof(digest);
+ }
+ sha_memcpy(output, digest, outputSize);
+}
+
+status_t SHA_Init(SHA_Type *base, sha_ctx_t *ctx, sha_algo_t algo)
+{
+ status_t status;
+
+ sha_ctx_internal_t *ctxInternal;
+ /* compile time check for the correct structure size */
+ BUILD_ASSERT(sizeof(sha_ctx_t) >= sizeof(sha_ctx_internal_t), sha_ctx_t_size);
+ uint32_t i;
+
+ status = sha_check_input_args(base, ctx, algo);
+ if (status != kStatus_Success)
+ {
+ return status;
+ }
+
+ /* set algorithm in context struct for later use */
+ ctxInternal = (sha_ctx_internal_t *)ctx;
+ ctxInternal->algo = algo;
+ ctxInternal->blksz = 0u;
+ for (i = 0; i < sizeof(ctxInternal->blk.w) / sizeof(ctxInternal->blk.w[0]); i++)
+ {
+ ctxInternal->blk.w[0] = 0u;
+ }
+ ctxInternal->state = kSHA_HashInit;
+ ctxInternal->fullMessageSize = 0;
+ return status;
+}
+
+status_t SHA_Update(SHA_Type *base, sha_ctx_t *ctx, const uint8_t *message, size_t messageSize)
+{
+ bool isUpdateState;
+ status_t status;
+ sha_ctx_internal_t *ctxInternal;
+ size_t blockSize;
+
+ if (messageSize == 0)
+ {
+ return kStatus_Success;
+ }
+
+ ctxInternal = (sha_ctx_internal_t *)ctx;
+ status = sha_check_context(ctxInternal, message);
+ if (kStatus_Success != status)
+ {
+ return status;
+ }
+
+ ctxInternal->fullMessageSize += messageSize;
+ blockSize = SHA_BLOCK_SIZE;
+ /* if we are still less than 64 bytes, keep only in context */
+ if ((ctxInternal->blksz + messageSize) <= blockSize)
+ {
+ sha_memcpy((&ctxInternal->blk.b[0]) + ctxInternal->blksz, message, messageSize);
+ ctxInternal->blksz += messageSize;
+ return status;
+ }
+ else
+ {
+ isUpdateState = ctxInternal->state == kSHA_HashUpdate;
+ if (!isUpdateState)
+ {
+ /* start NEW hash */
+ sha_engine_init(base, ctxInternal);
+ ctxInternal->state = kSHA_HashUpdate;
+ }
+ }
+
+ /* process message data */
+ status = sha_process_message_data(base, ctxInternal, message, messageSize);
+ return status;
+}
+
+status_t SHA_Finish(SHA_Type *base, sha_ctx_t *ctx, uint8_t *output, size_t *outputSize)
+{
+ size_t algOutSize = 0;
+ status_t status;
+ sha_ctx_internal_t *ctxInternal;
+ uint32_t *ctxW;
+ uint32_t i;
+
+ ctxInternal = (sha_ctx_internal_t *)ctx;
+ status = sha_check_context(ctxInternal, output);
+ if (kStatus_Success != status)
+ {
+ return status;
+ }
+
+ if (ctxInternal->state == kSHA_HashInit)
+ {
+ sha_engine_init(base, ctxInternal);
+ }
+
+ size_t outSize = 0u;
+
+ /* compute algorithm output length */
+ switch (ctxInternal->algo)
+ {
+ case kSHA_Sha1:
+ outSize = kSHA_OutLenSha1;
+ break;
+ case kSHA_Sha256:
+ outSize = kSHA_OutLenSha256;
+ break;
+ default:
+ break;
+ }
+ algOutSize = outSize;
+
+ /* flush message last incomplete block, if there is any, and add padding bits */
+ status = sha_finalize(base, ctxInternal);
+
+ if (outputSize)
+ {
+ if (algOutSize < *outputSize)
+ {
+ *outputSize = algOutSize;
+ }
+ else
+ {
+ algOutSize = *outputSize;
+ }
+ }
+
+ sha_get_digest(base, &output[0], algOutSize);
+
+ ctxW = (uint32_t *)ctx;
+ for (i = 0; i < SHA_CTX_SIZE; i++)
+ {
+ ctxW[i] = 0u;
+ }
+ return status;
+}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_sha.h Tue Mar 20 16:56:18 2018 +0000
@@ -0,0 +1,145 @@
+/*
+ * The Clear BSD License
+ * Copyright (c) 2016, Freescale Semiconductor, Inc.
+ * Copyright 2016-2017 NXP
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
+ *
+ * o Redistributions of source code must retain the above copyright notice, this list
+ * of conditions and the following disclaimer.
+ *
+ * o Redistributions in binary form must reproduce the above copyright notice, this
+ * list of conditions and the following disclaimer in the documentation and/or
+ * other materials provided with the distribution.
+ *
+ * o Neither the name of the copyright holder nor the names of its
+ * contributors may be used to endorse or promote products derived from this
+ * software without specific prior written permission.
+ *
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
+ * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
+ * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
+ * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
+ * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
+ * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
+ * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
+ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ */
+#ifndef _FSL_SHA_H_
+#define _FSL_SHA_H_
+
+#include "fsl_common.h"
+
+/*!
+ * @addtogroup sha
+ * @{
+ */
+
+/*! @file */
+
+/*******************************************************************************
+ * Definitions
+ *******************************************************************************/
+
+/*! @name Driver version */
+/*@{*/
+/*! @brief Defines LPC SHA driver version 2.0.0.
+ *
+ * Change log:
+ * - Version 2.0.0
+ * - initial version
+ */
+#define FSL_SHA_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*@}*/
+
+/*! Supported cryptographic block cipher functions for HASH creation */
+typedef enum _sha_algo_t
+{
+ kSHA_Sha1, /*!< SHA_1 */
+ kSHA_Sha256, /*!< SHA_256 */
+} sha_algo_t;
+
+/*! @brief SHA Context size. */
+#define SHA_CTX_SIZE 20
+
+/*! @brief Storage type used to save hash context. */
+typedef struct _sha_ctx_t
+{
+ uint32_t x[SHA_CTX_SIZE];
+} sha_ctx_t;
+
+/*******************************************************************************
+ * API
+ *******************************************************************************/
+
+#if defined(__cplusplus)
+extern "C" {
+#endif /* __cplusplus */
+
+/*!
+ * @name SHA Functional Operation
+ * @{
+ */
+
+/*!
+ * @addtogroup sha_algorithm_level_api
+ * @{
+ */
+/*!
+* @brief Initialize HASH context
+*
+* This function initializes new hash context.
+*
+* @param base SHA peripheral base address
+* @param[out] ctx Output hash context
+* @param algo Underlaying algorithm to use for hash computation. Either SHA-1 or SHA-256.
+* @return Status of initialization
+*/
+status_t SHA_Init(SHA_Type *base, sha_ctx_t *ctx, sha_algo_t algo);
+
+/*!
+ * @brief Add data to current HASH
+ *
+ * Add data to current HASH. This can be called repeatedly with an arbitrary amount of data to be
+ * hashed.
+ *
+ * @param base SHA peripheral base address
+ * @param[in,out] ctx HASH context
+ * @param message Input message
+ * @param messageSize Size of input message in bytes
+ * @return Status of the hash update operation
+ */
+status_t SHA_Update(SHA_Type *base, sha_ctx_t *ctx, const uint8_t *message, size_t messageSize);
+
+/*!
+ * @brief Finalize hashing
+ *
+ * Outputs the final hash and erases the context. SHA-1 or SHA-256 padding bits are automatically added by this
+ * function.
+ *
+ * @param base SHA peripheral base address
+ * @param[in,out] ctx HASH context
+ * @param[out] output Output hash data
+ * @param[in,out] outputSize On input, determines the size of bytes of the output array. On output, tells how many bytes
+ * have been written to output.
+ * @return Status of the hash finish operation
+ */
+status_t SHA_Finish(SHA_Type *base, sha_ctx_t *ctx, uint8_t *output, size_t *outputSize);
+/*!
+ *@}
+ */ /* sha_algorithm_level_api */
+
+#if defined(__cplusplus)
+}
+#endif /* __cplusplus */
+
+/*! @}*/
+/*! @}*/ /* end of group sha */
+
+#endif /* _FSL_SHA_H_ */
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spi.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spi.c Tue Mar 20 16:56:18 2018 +0000
@@ -1,9 +1,12 @@
/*
+ * The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
+ * All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -41,6 +45,7 @@
* range <0,15>. Range <8,15> represents 2B transfer */
#define SPI_COUNT_TO_BYTES(dataWidth, count) ((count) << ((dataWidth) >> 3U))
#define SPI_BYTES_TO_COUNT(dataWidth, bytes) ((bytes) >> ((dataWidth) >> 3U))
+#define SPI_SSELPOL_MASK ((SPI_CFG_SPOL0_MASK) | (SPI_CFG_SPOL1_MASK) | (SPI_CFG_SPOL2_MASK) | (SPI_CFG_SPOL3_MASK))
/*******************************************************************************
* Variables
@@ -54,6 +59,8 @@
/*! @brief IRQ name array */
static const IRQn_Type s_spiIRQ[] = SPI_IRQS;
+/* @brief Dummy data for each instance. This data is used when user's tx buffer is NULL*/
+volatile uint8_t s_dummyData[FSL_FEATURE_SOC_SPI_COUNT] = {0};
/*******************************************************************************
* Code
******************************************************************************/
@@ -75,6 +82,12 @@
return 0;
}
+void SPI_SetDummyData(SPI_Type *base, uint8_t dummyData)
+{
+ uint32_t instance = SPI_GetInstance(base);
+ s_dummyData[instance] = dummyData;
+}
+
void *SPI_GetConfig(SPI_Type *base)
{
int32_t instance;
@@ -100,6 +113,11 @@
config->sselNum = kSPI_Ssel0;
config->txWatermark = kSPI_TxFifo0;
config->rxWatermark = kSPI_RxFifo1;
+ config->sselPol = kSPI_SpolActiveAllLow;
+ config->delayConfig.preDelay = 0U;
+ config->delayConfig.postDelay = 0U;
+ config->delayConfig.frameDelay = 0U;
+ config->delayConfig.transferDelay = 0U;
}
status_t SPI_MasterInit(SPI_Type *base, const spi_master_config_t *config, uint32_t srcClock_Hz)
@@ -134,7 +152,8 @@
/* configure SPI mode */
tmp = base->CFG;
- tmp &= ~(SPI_CFG_MASTER_MASK | SPI_CFG_LSBF_MASK | SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK | SPI_CFG_LOOP_MASK | SPI_CFG_ENABLE_MASK);
+ tmp &= ~(SPI_CFG_MASTER_MASK | SPI_CFG_LSBF_MASK | SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK | SPI_CFG_LOOP_MASK |
+ SPI_CFG_ENABLE_MASK | SPI_SSELPOL_MASK);
/* phase */
tmp |= SPI_CFG_CPHA(config->phase);
/* polarity */
@@ -145,6 +164,8 @@
tmp |= SPI_CFG_MASTER(1);
/* loopback */
tmp |= SPI_CFG_LOOP(config->enableLoopback);
+ /* configure active level for all CS */
+ tmp |= ((uint32_t)config->sselPol & (SPI_SSELPOL_MASK));
base->CFG = tmp;
/* store configuration */
@@ -161,6 +182,11 @@
/* set FIFOTRIG */
base->FIFOTRIG = tmp;
+ /* Set the delay configuration. */
+ SPI_SetTransferDelay(base, &config->delayConfig);
+ /* Set the dummy data. */
+ SPI_SetDummyData(base, (uint8_t)SPI_DUMMYDATA);
+
SPI_Enable(base, config->enableMaster);
return kStatus_Success;
}
@@ -176,6 +202,7 @@
config->dataWidth = kSPI_Data8Bits;
config->txWatermark = kSPI_TxFifo0;
config->rxWatermark = kSPI_RxFifo1;
+ config->sselPol = kSPI_SpolActiveAllLow;
}
status_t SPI_SlaveInit(SPI_Type *base, const spi_slave_config_t *config)
@@ -201,13 +228,16 @@
/* configure SPI mode */
tmp = base->CFG;
- tmp &= ~(SPI_CFG_MASTER_MASK | SPI_CFG_LSBF_MASK | SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK | SPI_CFG_ENABLE_MASK);
+ tmp &= ~(SPI_CFG_MASTER_MASK | SPI_CFG_LSBF_MASK | SPI_CFG_CPHA_MASK | SPI_CFG_CPOL_MASK | SPI_CFG_ENABLE_MASK |
+ SPI_SSELPOL_MASK);
/* phase */
tmp |= SPI_CFG_CPHA(config->phase);
/* polarity */
tmp |= SPI_CFG_CPOL(config->polarity);
/* direction */
tmp |= SPI_CFG_LSBF(config->direction);
+ /* configure active level for all CS */
+ tmp |= ((uint32_t)config->sselPol & (SPI_SSELPOL_MASK));
base->CFG = tmp;
/* store configuration */
@@ -223,6 +253,8 @@
/* set FIFOTRIG */
base->FIFOTRIG = tmp;
+ SPI_SetDummyData(base, (uint8_t)SPI_DUMMYDATA);
+
SPI_Enable(base, config->enableSlave);
return kStatus_Success;
}
@@ -402,10 +434,10 @@
tx_ctrl |= (SPI_DEASSERT_ALL & (~SPI_DEASSERTNUM_SSEL(g_configs[instance].sselNum)));
/* set width of data - range asserted at entry */
tx_ctrl |= SPI_FIFOWR_LEN(dataWidth);
+ /* delay for frames */
+ tx_ctrl |= (xfer->configFlags & (uint32_t)kSPI_FrameDelay) ? (uint32_t)kSPI_FrameDelay : 0;
/* end of transfer */
last_ctrl |= (xfer->configFlags & (uint32_t)kSPI_FrameAssert) ? (uint32_t)kSPI_FrameAssert : 0;
- /* delay end of transfer */
- last_ctrl |= (xfer->configFlags & (uint32_t)kSPI_FrameDelay) ? (uint32_t)kSPI_FrameDelay : 0;
/* last index of loop */
while (txRemainingBytes || rxRemainingBytes || toReceiveCount)
{
@@ -450,7 +482,7 @@
}
else
{
- tmp32 = SPI_DUMMYDATA;
+ tmp32 = ((uint32_t)s_dummyData[instance] << 8U | (s_dummyData[instance]));
/* last transfer */
if (rxRemainingBytes == SPI_COUNT_TO_BYTES(dataWidth, toReceiveCount + 1))
{
@@ -513,6 +545,118 @@
return kStatus_Success;
}
+status_t SPI_MasterHalfDuplexTransferBlocking(SPI_Type *base, spi_half_duplex_transfer_t *xfer)
+{
+ assert(xfer);
+
+ spi_transfer_t tempXfer = {0};
+ status_t status;
+
+ if (xfer->isTransmitFirst)
+ {
+ tempXfer.txData = xfer->txData;
+ tempXfer.rxData = NULL;
+ tempXfer.dataSize = xfer->txDataSize;
+ }
+ else
+ {
+ tempXfer.txData = NULL;
+ tempXfer.rxData = xfer->rxData;
+ tempXfer.dataSize = xfer->rxDataSize;
+ }
+ /* If the pcs pin keep assert between transmit and receive. */
+ if (xfer->isPcsAssertInTransfer)
+ {
+ tempXfer.configFlags = (xfer->configFlags) & (uint32_t)(~kSPI_FrameAssert);
+ }
+ else
+ {
+ tempXfer.configFlags = (xfer->configFlags) | kSPI_FrameAssert;
+ }
+
+ status = SPI_MasterTransferBlocking(base, &tempXfer);
+
+ if (status != kStatus_Success)
+ {
+ return status;
+ }
+
+ if (xfer->isTransmitFirst)
+ {
+ tempXfer.txData = NULL;
+ tempXfer.rxData = xfer->rxData;
+ tempXfer.dataSize = xfer->rxDataSize;
+ }
+ else
+ {
+ tempXfer.txData = xfer->txData;
+ tempXfer.rxData = NULL;
+ tempXfer.dataSize = xfer->txDataSize;
+ }
+ tempXfer.configFlags = xfer->configFlags;
+
+ /* SPI transfer blocking. */
+ status = SPI_MasterTransferBlocking(base, &tempXfer);
+
+ return status;
+}
+
+status_t SPI_MasterHalfDuplexTransferNonBlocking(SPI_Type *base,
+ spi_master_handle_t *handle,
+ spi_half_duplex_transfer_t *xfer)
+{
+ assert(xfer);
+ assert(handle);
+ spi_transfer_t tempXfer = {0};
+ status_t status;
+
+ if (xfer->isTransmitFirst)
+ {
+ tempXfer.txData = xfer->txData;
+ tempXfer.rxData = NULL;
+ tempXfer.dataSize = xfer->txDataSize;
+ }
+ else
+ {
+ tempXfer.txData = NULL;
+ tempXfer.rxData = xfer->rxData;
+ tempXfer.dataSize = xfer->rxDataSize;
+ }
+ /* If the PCS pin keep assert between transmit and receive. */
+ if (xfer->isPcsAssertInTransfer)
+ {
+ tempXfer.configFlags = (xfer->configFlags) & (uint32_t)(~kSPI_FrameAssert);
+ }
+ else
+ {
+ tempXfer.configFlags = (xfer->configFlags) | kSPI_FrameAssert;
+ }
+
+ status = SPI_MasterTransferBlocking(base, &tempXfer);
+ if (status != kStatus_Success)
+ {
+ return status;
+ }
+
+ if (xfer->isTransmitFirst)
+ {
+ tempXfer.txData = NULL;
+ tempXfer.rxData = xfer->rxData;
+ tempXfer.dataSize = xfer->rxDataSize;
+ }
+ else
+ {
+ tempXfer.txData = xfer->txData;
+ tempXfer.rxData = NULL;
+ tempXfer.dataSize = xfer->txDataSize;
+ }
+ tempXfer.configFlags = xfer->configFlags;
+
+ status = SPI_MasterTransferNonBlocking(base, handle, &tempXfer);
+
+ return status;
+}
+
status_t SPI_MasterTransferGetCount(SPI_Type *base, spi_master_handle_t *handle, size_t *count)
{
assert(NULL != handle);
@@ -552,6 +696,8 @@
uint32_t tx_ctrl = 0, last_ctrl = 0, tmp32;
bool loopContinue;
uint32_t fifoDepth;
+ /* Get flexcomm instance by 'base' param */
+ uint32_t instance = SPI_GetInstance(base);
/* check params */
assert((NULL != base) && (NULL != handle) && ((NULL != handle->txData) || (NULL != handle->rxData)));
@@ -561,10 +707,10 @@
tx_ctrl |= (SPI_DEASSERT_ALL & SPI_ASSERTNUM_SSEL(handle->sselNum));
/* set width of data */
tx_ctrl |= SPI_FIFOWR_LEN(handle->dataWidth);
+ /* delay for frames */
+ tx_ctrl |= (handle->configFlags & (uint32_t)kSPI_FrameDelay) ? (uint32_t)kSPI_FrameDelay : 0;
/* end of transfer */
last_ctrl |= (handle->configFlags & (uint32_t)kSPI_FrameAssert) ? (uint32_t)kSPI_FrameAssert : 0;
- /* delay end of transfer */
- last_ctrl |= (handle->configFlags & (uint32_t)kSPI_FrameDelay) ? (uint32_t)kSPI_FrameDelay : 0;
do
{
loopContinue = false;
@@ -619,7 +765,7 @@
}
else
{
- tmp32 = SPI_DUMMYDATA;
+ tmp32 = ((uint32_t)s_dummyData[instance] << 8U | (s_dummyData[instance]));
/* last transfer */
if (handle->rxRemainingBytes == SPI_COUNT_TO_BYTES(handle->dataWidth, handle->toReceiveCount + 1))
{
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spi.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spi.h Tue Mar 20 16:56:18 2018 +0000
@@ -1,9 +1,12 @@
/*
+ * The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
+ * All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -46,11 +50,15 @@
/*! @name Driver version */
/*@{*/
-/*! @brief USART driver version 2.0.0. */
-#define FSL_SPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 0))
+/*! @brief SPI driver version 2.0.1. */
+#define FSL_SPI_DRIVER_VERSION (MAKE_VERSION(2, 0, 1))
/*@}*/
-#define SPI_DUMMYDATA (0xFFFF)
+#ifndef SPI_DUMMYDATA
+/*! @brief SPI dummy transfer data, the data is sent while txBuff is NULL. */
+#define SPI_DUMMYDATA (0xFFU)
+#endif
+
#define SPI_DATA(n) (((uint32_t)(n)) & 0xFFFF)
#define SPI_CTRLMASK (0xFFFF0000)
@@ -64,25 +72,29 @@
#define SPI_FIFOTRIG_RXLVL_GET(base) (((base)->FIFOTRIG & SPI_FIFOTRIG_RXLVL_MASK) >> SPI_FIFOTRIG_RXLVL_SHIFT)
/*! @brief SPI transfer option.*/
-typedef enum _spi_xfer_option {
+typedef enum _spi_xfer_option
+{
kSPI_FrameDelay = (SPI_FIFOWR_EOF_MASK), /*!< Delay chip select */
kSPI_FrameAssert = (SPI_FIFOWR_EOT_MASK), /*!< When transfer ends, assert chip select */
} spi_xfer_option_t;
/*! @brief SPI data shifter direction options.*/
-typedef enum _spi_shift_direction {
+typedef enum _spi_shift_direction
+{
kSPI_MsbFirst = 0U, /*!< Data transfers start with most significant bit. */
kSPI_LsbFirst = 1U /*!< Data transfers start with least significant bit. */
} spi_shift_direction_t;
/*! @brief SPI clock polarity configuration.*/
-typedef enum _spi_clock_polarity {
+typedef enum _spi_clock_polarity
+{
kSPI_ClockPolarityActiveHigh = 0x0U, /*!< Active-high SPI clock (idles low). */
kSPI_ClockPolarityActiveLow /*!< Active-low SPI clock (idles high). */
} spi_clock_polarity_t;
/*! @brief SPI clock phase configuration.*/
-typedef enum _spi_clock_phase {
+typedef enum _spi_clock_phase
+{
kSPI_ClockPhaseFirstEdge = 0x0U, /*!< First edge on SCK occurs at the middle of the first
* cycle of a data transfer. */
kSPI_ClockPhaseSecondEdge /*!< First edge on SCK occurs at the start of the
@@ -90,7 +102,8 @@
} spi_clock_phase_t;
/*! @brief txFIFO watermark values */
-typedef enum _spi_txfifo_watermark {
+typedef enum _spi_txfifo_watermark
+{
kSPI_TxFifo0 = 0, /*!< SPI tx watermark is empty */
kSPI_TxFifo1 = 1, /*!< SPI tx watermark at 1 item */
kSPI_TxFifo2 = 2, /*!< SPI tx watermark at 2 items */
@@ -102,7 +115,8 @@
} spi_txfifo_watermark_t;
/*! @brief rxFIFO watermark values */
-typedef enum _spi_rxfifo_watermark {
+typedef enum _spi_rxfifo_watermark
+{
kSPI_RxFifo1 = 0, /*!< SPI rx watermark at 1 item */
kSPI_RxFifo2 = 1, /*!< SPI rx watermark at 2 items */
kSPI_RxFifo3 = 2, /*!< SPI rx watermark at 3 items */
@@ -114,7 +128,8 @@
} spi_rxfifo_watermark_t;
/*! @brief Transfer data width */
-typedef enum _spi_data_width {
+typedef enum _spi_data_width
+{
kSPI_Data4Bits = 3, /*!< 4 bits data width */
kSPI_Data5Bits = 4, /*!< 5 bits data width */
kSPI_Data6Bits = 5, /*!< 6 bits data width */
@@ -131,13 +146,41 @@
} spi_data_width_t;
/*! @brief Slave select */
-typedef enum _spi_ssel {
+typedef enum _spi_ssel
+{
kSPI_Ssel0 = 0, /*!< Slave select 0 */
kSPI_Ssel1 = 1, /*!< Slave select 1 */
kSPI_Ssel2 = 2, /*!< Slave select 2 */
kSPI_Ssel3 = 3, /*!< Slave select 3 */
} spi_ssel_t;
+/*! @brief ssel polarity */
+typedef enum _spi_spol
+{
+ kSPI_Spol0ActiveHigh = SPI_CFG_SPOL0(1),
+ kSPI_Spol1ActiveHigh = SPI_CFG_SPOL1(1),
+ kSPI_Spol2ActiveHigh = SPI_CFG_SPOL2(1),
+ kSPI_Spol3ActiveHigh = SPI_CFG_SPOL3(1),
+ kSPI_SpolActiveAllHigh =
+ (kSPI_Spol0ActiveHigh | kSPI_Spol1ActiveHigh | kSPI_Spol2ActiveHigh | kSPI_Spol3ActiveHigh),
+ kSPI_SpolActiveAllLow = 0,
+} spi_spol_t;
+
+/*!
+ * @brief SPI delay time configure structure.
+ * Note:
+ * The DLY register controls several programmable delays related to SPI signalling,
+ * it stands for how many SPI clock time will be inserted.
+ * The maxinun value of these delay time is 15.
+ */
+typedef struct _spi_delay_config
+{
+ uint8_t preDelay; /*!< Delay between SSEL assertion and the beginning of transfer. */
+ uint8_t postDelay; /*!< Delay between the end of transfer and SSEL deassertion. */
+ uint8_t frameDelay; /*!< Delay between frame to frame. */
+ uint8_t transferDelay; /*!< Delay between transfer to transfer. */
+} spi_delay_config_t;
+
/*! @brief SPI master user configure structure.*/
typedef struct _spi_master_config
{
@@ -149,8 +192,10 @@
uint32_t baudRate_Bps; /*!< Baud Rate for SPI in Hz */
spi_data_width_t dataWidth; /*!< Width of the data */
spi_ssel_t sselNum; /*!< Slave select number */
+ spi_spol_t sselPol; /*!< Configure active CS polarity */
spi_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */
spi_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */
+ spi_delay_config_t delayConfig; /*!< Delay configuration. */
} spi_master_config_t;
/*! @brief SPI slave user configure structure.*/
@@ -161,6 +206,7 @@
spi_clock_phase_t phase; /*!< Clock phase */
spi_shift_direction_t direction; /*!< MSB or LSB */
spi_data_width_t dataWidth; /*!< Width of the data */
+ spi_spol_t sselPol; /*!< Configure active CS polarity */
spi_txfifo_watermark_t txWatermark; /*!< txFIFO watermark */
spi_rxfifo_watermark_t rxWatermark; /*!< rxFIFO watermark */
} spi_slave_config_t;
@@ -200,6 +246,19 @@
size_t dataSize; /*!< Transfer bytes */
} spi_transfer_t;
+/*! @brief SPI half-duplex(master only) transfer structure */
+typedef struct _spi_half_duplex_transfer
+{
+ uint8_t *txData; /*!< Send buffer */
+ uint8_t *rxData; /*!< Receive buffer */
+ size_t txDataSize; /*!< Transfer bytes for transmit */
+ size_t rxDataSize; /*!< Transfer bytes */
+ uint32_t configFlags; /*!< Transfer configuration flags. */
+ bool isPcsAssertInTransfer; /*!< If PCS pin keep assert between transmit and receive. true for assert and false for
+ deassert. */
+ bool isTransmitFirst; /*!< True for transmit first and false for receive first. */
+} spi_half_duplex_transfer_t;
+
/*! @brief Internal configuration structure used in 'spi' and 'spi_dma' driver */
typedef struct _spi_config
{
@@ -468,6 +527,28 @@
return base->FIFORD;
}
+/*!
+ * @brief Set delay time for transfer.
+ * the delay uint is SPI clock time, maximum value is 0xF.
+ * @param base SPI base pointer
+ * @param config configuration for delay option @ref spi_delay_config_t.
+ */
+static inline void SPI_SetTransferDelay(SPI_Type *base, const spi_delay_config_t *config)
+{
+ assert(NULL != base);
+ assert(NULL != config);
+ base->DLY = (SPI_DLY_PRE_DELAY(config->preDelay) | SPI_DLY_POST_DELAY(config->postDelay) |
+ SPI_DLY_FRAME_DELAY(config->frameDelay) | SPI_DLY_TRANSFER_DELAY(config->transferDelay));
+}
+
+/*!
+ * @brief Set up the dummy data.
+ *
+ * @param base SPI peripheral address.
+ * @param dummyData Data to be transferred when tx buffer is NULL.
+ */
+void SPI_SetDummyData(SPI_Type *base, uint8_t dummyData);
+
/*! @} */
/*!
@@ -514,6 +595,36 @@
status_t SPI_MasterTransferNonBlocking(SPI_Type *base, spi_master_handle_t *handle, spi_transfer_t *xfer);
/*!
+ * @brief Transfers a block of data using a polling method.
+ *
+ * This function will do a half-duplex transfer for SPI master, This is a blocking function,
+ * which does not retuen until all transfer have been completed. And data transfer mechanism is half-duplex,
+ * users can set transmit first or receive first.
+ *
+ * @param base SPI base pointer
+ * @param xfer pointer to spi_half_duplex_transfer_t structure
+ * @return status of status_t.
+ */
+status_t SPI_MasterHalfDuplexTransferBlocking(SPI_Type *base, spi_half_duplex_transfer_t *xfer);
+
+/*!
+ * @brief Performs a non-blocking SPI interrupt transfer.
+ *
+ * This function using polling way to do the first half transimission and using interrupts to
+ * do the second half transimission, the transfer mechanism is half-duplex.
+ * When do the second half transimission, code will return right away. When all data is transferred,
+ * the callback function is called.
+ *
+ * @param base SPI peripheral base address.
+ * @param handle pointer to spi_master_handle_t structure which stores the transfer state
+ * @param xfer pointer to spi_half_duplex_transfer_t structure
+ * @return status of status_t.
+ */
+status_t SPI_MasterHalfDuplexTransferNonBlocking(SPI_Type *base,
+ spi_master_handle_t *handle,
+ spi_half_duplex_transfer_t *xfer);
+
+/*!
* @brief Gets the master transfer count.
*
* This function gets the master transfer count.
@@ -591,7 +702,7 @@
*/
static inline status_t SPI_SlaveTransferGetCount(SPI_Type *base, spi_slave_handle_t *handle, size_t *count)
{
- return SPI_MasterTransferGetCount(base, (spi_master_handle_t*)handle, count);
+ return SPI_MasterTransferGetCount(base, (spi_master_handle_t *)handle, count);
}
/*!
@@ -604,7 +715,7 @@
*/
static inline void SPI_SlaveTransferAbort(SPI_Type *base, spi_slave_handle_t *handle)
{
- SPI_MasterTransferAbort(base, (spi_master_handle_t*)handle);
+ SPI_MasterTransferAbort(base, (spi_master_handle_t *)handle);
}
/*!
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spi_dma.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spi_dma.c Tue Mar 20 16:56:18 2018 +0000
@@ -1,9 +1,12 @@
/*
+ * The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
+ * All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -97,10 +101,13 @@
#if defined(__ICCARM__)
#pragma data_alignment = 4
static uint16_t s_rxDummy;
+static uint32_t s_txLastWord[FSL_FEATURE_SOC_SPI_COUNT];
#elif defined(__CC_ARM)
__attribute__((aligned(4))) static uint16_t s_rxDummy;
+__attribute__((aligned(4))) static uint32_t s_txLastWord[FSL_FEATURE_SOC_SPI_COUNT];
#elif defined(__GNUC__)
__attribute__((aligned(4))) static uint16_t s_rxDummy;
+__attribute__((aligned(4))) static uint32_t s_txLastWord[FSL_FEATURE_SOC_SPI_COUNT];
#endif
#if defined(__ICCARM__)
@@ -112,6 +119,8 @@
__attribute__((aligned(16))) static dma_descriptor_t s_spi_descriptor_table[FSL_FEATURE_SOC_SPI_COUNT] = {0};
#endif
+/*! @brief Global variable for dummy data value setting. */
+extern volatile uint8_t s_dummyData[];
/*******************************************************************************
* Code
******************************************************************************/
@@ -129,31 +138,31 @@
*fifowr |= SPI_FIFOWR_LEN(config->dataWidth);
}
-static void PrepareTxFIFO(uint32_t *fifo, uint32_t count, uint32_t ctrl)
+static void PrepareTxLastWord(spi_transfer_t *xfer, uint32_t *txLastWord, spi_config_t *config)
{
- assert(!(fifo == NULL));
- if (fifo == NULL)
+ if (config->dataWidth > kSPI_Data8Bits)
{
- return;
+ *txLastWord = (((uint32_t)xfer->txData[xfer->dataSize - 1] << 8U) | (xfer->txData[xfer->dataSize - 2]));
}
- /* CS deassert and CS delay are relevant only for last word */
- uint32_t tx_ctrl = ctrl & (~(SPI_FIFOWR_EOT_MASK | SPI_FIFOWR_EOF_MASK));
- uint32_t i = 0;
- for (; i + 1 < count; i++)
+ else
{
- fifo[i] = (fifo[i] & 0xFFFFU) | (tx_ctrl & 0xFFFF0000U);
+ *txLastWord = xfer->txData[xfer->dataSize - 1];
}
- if (i < count)
- {
- fifo[i] = (fifo[i] & 0xFFFFU) | (ctrl & 0xFFFF0000U);
- }
+ XferToFifoWR(xfer, txLastWord);
+ SpiConfigToFifoWR(config, txLastWord);
}
-static void SPI_SetupDummy(uint32_t *dummy, spi_transfer_t *xfer, spi_config_t *spi_config_p)
+static void SPI_SetupDummy(SPI_Type *base, spi_dma_txdummy_t *dummy, spi_transfer_t *xfer, spi_config_t *spi_config_p)
{
- *dummy = SPI_DUMMYDATA;
- XferToFifoWR(xfer, dummy);
- SpiConfigToFifoWR(spi_config_p, dummy);
+ uint32_t instance = SPI_GetInstance(base);
+ dummy->word = ((uint32_t)s_dummyData[instance] << 8U | s_dummyData[instance]);
+ dummy->lastWord = ((uint32_t)s_dummyData[instance] << 8U | s_dummyData[instance]);
+ XferToFifoWR(xfer, &dummy->word);
+ XferToFifoWR(xfer, &dummy->lastWord);
+ SpiConfigToFifoWR(spi_config_p, &dummy->word);
+ SpiConfigToFifoWR(spi_config_p, &dummy->lastWord);
+ /* Clear the end of transfer bit for continue word transfer. */
+ dummy->word &= (uint32_t)(~kSPI_FrameAssert);
}
status_t SPI_MasterTransferCreateHandleDMA(SPI_Type *base,
@@ -212,21 +221,10 @@
{
return kStatus_InvalidArgument;
}
- /* txData set and not aligned to sizeof(uint32_t) */
- assert(!((NULL != xfer->txData) && ((uint32_t)xfer->txData % sizeof(uint32_t))));
- if ((NULL != xfer->txData) && ((uint32_t)xfer->txData % sizeof(uint32_t)))
- {
- return kStatus_InvalidArgument;
- }
- /* rxData set and not aligned to sizeof(uint32_t) */
- assert(!((NULL != xfer->rxData) && ((uint32_t)xfer->rxData % sizeof(uint32_t))));
- if ((NULL != xfer->rxData) && ((uint32_t)xfer->rxData % sizeof(uint32_t)))
- {
- return kStatus_InvalidArgument;
- }
- /* byte size is zero or not aligned to sizeof(uint32_t) */
- assert(!((xfer->dataSize == 0) || (xfer->dataSize % sizeof(uint32_t))));
- if ((xfer->dataSize == 0) || (xfer->dataSize % sizeof(uint32_t)))
+
+ /* Byte size is zero. */
+ assert(!(xfer->dataSize == 0));
+ if (xfer->dataSize == 0)
{
return kStatus_InvalidArgument;
}
@@ -256,13 +254,15 @@
SPI_EnableRxDMA(base, true);
if (xfer->rxData)
{
- DMA_PrepareTransfer(&xferConfig, (void *)&base->FIFORD, xfer->rxData, sizeof(uint32_t), xfer->dataSize,
- kDMA_PeripheralToMemory, NULL);
+ DMA_PrepareTransfer(&xferConfig, (void *)&base->FIFORD, xfer->rxData,
+ ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))),
+ xfer->dataSize, kDMA_PeripheralToMemory, NULL);
}
else
{
- DMA_PrepareTransfer(&xferConfig, (void *)&base->FIFORD, &s_rxDummy, sizeof(uint32_t), xfer->dataSize,
- kDMA_StaticToStatic, NULL);
+ DMA_PrepareTransfer(&xferConfig, (void *)&base->FIFORD, &s_rxDummy,
+ ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))),
+ xfer->dataSize, kDMA_StaticToStatic, NULL);
}
DMA_SubmitTransfer(handle->rxHandle, &xferConfig);
handle->rxInProgress = true;
@@ -270,21 +270,21 @@
/* transmit */
SPI_EnableTxDMA(base, true);
+
+ if (xfer->configFlags & kSPI_FrameAssert)
+ {
+ PrepareTxLastWord(xfer, &s_txLastWord[instance], spi_config_p);
+ }
+
if (xfer->txData)
{
- tmp = 0;
- XferToFifoWR(xfer, &tmp);
- SpiConfigToFifoWR(spi_config_p, &tmp);
- PrepareTxFIFO((uint32_t *)xfer->txData, xfer->dataSize / sizeof(uint32_t), tmp);
- DMA_PrepareTransfer(&xferConfig, xfer->txData, (void *)&base->FIFOWR, sizeof(uint32_t), xfer->dataSize,
- kDMA_MemoryToPeripheral, NULL);
- DMA_SubmitTransfer(handle->txHandle, &xferConfig);
- }
- else
- {
- if ((xfer->configFlags & kSPI_FrameAssert) && (xfer->dataSize > sizeof(uint32_t)))
+ /* If end of tranfer function is enabled and data transfer frame is bigger then 1, use dma
+ * descriptor to send the last data.
+ */
+ if ((xfer->configFlags & kSPI_FrameAssert) &&
+ ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize > 2) : (xfer->dataSize > 1)))
{
- dma_xfercfg_t tmp_xfercfg = { 0 };
+ dma_xfercfg_t tmp_xfercfg = {0};
tmp_xfercfg.valid = true;
tmp_xfercfg.swtrig = true;
tmp_xfercfg.intA = true;
@@ -292,17 +292,16 @@
tmp_xfercfg.srcInc = 0;
tmp_xfercfg.dstInc = 0;
tmp_xfercfg.transferCount = 1;
- /* create chained descriptor to transmit last word */
- SPI_SetupDummy(&s_txDummy[instance].lastWord, xfer, spi_config_p);
- DMA_CreateDescriptor(&s_spi_descriptor_table[instance], &tmp_xfercfg, &s_txDummy[instance].lastWord,
- (uint32_t *)&base->FIFOWR, NULL);
- /* use common API to setup first descriptor */
- SPI_SetupDummy(&s_txDummy[instance].word, NULL, spi_config_p);
- DMA_PrepareTransfer(&xferConfig, &s_txDummy[instance].word, (void *)&base->FIFOWR, sizeof(uint32_t),
- xfer->dataSize - sizeof(uint32_t), kDMA_StaticToStatic,
- &s_spi_descriptor_table[instance]);
- /* disable interrupts for first descriptor
- * to avoid calling callback twice */
+ /* Create chained descriptor to transmit last word */
+ DMA_CreateDescriptor(&s_spi_descriptor_table[instance], &tmp_xfercfg, &s_txLastWord[instance],
+ (void *)&base->FIFOWR, NULL);
+
+ DMA_PrepareTransfer(
+ &xferConfig, xfer->txData, (void *)&base->FIFOWR,
+ ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))),
+ ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize - 2) : (xfer->dataSize - 1)),
+ kDMA_MemoryToPeripheral, &s_spi_descriptor_table[instance]);
+ /* Disable interrupts for first descriptor to avoid calling callback twice. */
xferConfig.xfercfg.intA = false;
xferConfig.xfercfg.intB = false;
result = DMA_SubmitTransfer(handle->txHandle, &xferConfig);
@@ -313,9 +312,52 @@
}
else
{
- SPI_SetupDummy(&s_txDummy[instance].word, xfer, spi_config_p);
- DMA_PrepareTransfer(&xferConfig, &s_txDummy[instance].word, (void *)&base->FIFOWR, sizeof(uint32_t),
- xfer->dataSize, kDMA_StaticToStatic, NULL);
+ DMA_PrepareTransfer(
+ &xferConfig, xfer->txData, (void *)&base->FIFOWR,
+ ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))),
+ xfer->dataSize, kDMA_MemoryToPeripheral, NULL);
+ DMA_SubmitTransfer(handle->txHandle, &xferConfig);
+ }
+ }
+ else
+ {
+ /* Setup tx dummy data. */
+ SPI_SetupDummy(base, &s_txDummy[instance], xfer, spi_config_p);
+ if ((xfer->configFlags & kSPI_FrameAssert) &&
+ ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize > 2) : (xfer->dataSize > 1)))
+ {
+ dma_xfercfg_t tmp_xfercfg = {0};
+ tmp_xfercfg.valid = true;
+ tmp_xfercfg.swtrig = true;
+ tmp_xfercfg.intA = true;
+ tmp_xfercfg.byteWidth = sizeof(uint32_t);
+ tmp_xfercfg.srcInc = 0;
+ tmp_xfercfg.dstInc = 0;
+ tmp_xfercfg.transferCount = 1;
+ /* Create chained descriptor to transmit last word */
+ DMA_CreateDescriptor(&s_spi_descriptor_table[instance], &tmp_xfercfg, &s_txDummy[instance].lastWord,
+ (uint32_t *)&base->FIFOWR, NULL);
+ /* Use common API to setup first descriptor */
+ DMA_PrepareTransfer(
+ &xferConfig, &s_txDummy[instance].word, (void *)&base->FIFOWR,
+ ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))),
+ ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize - 2) : (xfer->dataSize - 1)),
+ kDMA_StaticToStatic, &s_spi_descriptor_table[instance]);
+ /* Disable interrupts for first descriptor to avoid calling callback twice */
+ xferConfig.xfercfg.intA = false;
+ xferConfig.xfercfg.intB = false;
+ result = DMA_SubmitTransfer(handle->txHandle, &xferConfig);
+ if (result != kStatus_Success)
+ {
+ return result;
+ }
+ }
+ else
+ {
+ DMA_PrepareTransfer(
+ &xferConfig, &s_txDummy[instance].word, (void *)&base->FIFOWR,
+ ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (sizeof(uint16_t)) : (sizeof(uint8_t))),
+ xfer->dataSize, kDMA_StaticToStatic, NULL);
result = DMA_SubmitTransfer(handle->txHandle, &xferConfig);
if (result != kStatus_Success)
{
@@ -323,13 +365,89 @@
}
}
}
+
handle->txInProgress = true;
+ tmp = 0;
+ XferToFifoWR(xfer, &tmp);
+ SpiConfigToFifoWR(spi_config_p, &tmp);
+
+ /* Setup the control info.
+ * Halfword writes to just the control bits (offset 0xE22) doesn't push anything into the FIFO.
+ * And the data access type of control bits must be uint16_t, byte writes or halfword writes to FIFOWR
+ * will push the data and the current control bits into the FIFO.
+ */
+ if ((xfer->configFlags & kSPI_FrameAssert) &&
+ ((spi_config_p->dataWidth > kSPI_Data8Bits) ? (xfer->dataSize == 2U) : (xfer->dataSize == 1U)))
+ {
+ *(((uint16_t *)&(base->FIFOWR)) + 1) = (uint16_t)(tmp >> 16U);
+ }
+ else
+ {
+ /* Clear the SPI_FIFOWR_EOT_MASK bit when data is not the last. */
+ tmp &= (uint32_t)(~kSPI_FrameAssert);
+ *(((uint16_t *)&(base->FIFOWR)) + 1) = (uint16_t)(tmp >> 16U);
+ }
+
DMA_StartTransfer(handle->txHandle);
}
return result;
}
+status_t SPI_MasterHalfDuplexTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_half_duplex_transfer_t *xfer)
+{
+ assert(xfer);
+ assert(handle);
+ spi_transfer_t tempXfer = {0};
+ status_t status;
+
+ if (xfer->isTransmitFirst)
+ {
+ tempXfer.txData = xfer->txData;
+ tempXfer.rxData = NULL;
+ tempXfer.dataSize = xfer->txDataSize;
+ }
+ else
+ {
+ tempXfer.txData = NULL;
+ tempXfer.rxData = xfer->rxData;
+ tempXfer.dataSize = xfer->rxDataSize;
+ }
+ /* If the pcs pin keep assert between transmit and receive. */
+ if (xfer->isPcsAssertInTransfer)
+ {
+ tempXfer.configFlags = (xfer->configFlags) & (uint32_t)(~kSPI_FrameAssert);
+ }
+ else
+ {
+ tempXfer.configFlags = (xfer->configFlags) | kSPI_FrameAssert;
+ }
+
+ status = SPI_MasterTransferBlocking(base, &tempXfer);
+ if (status != kStatus_Success)
+ {
+ return status;
+ }
+
+ if (xfer->isTransmitFirst)
+ {
+ tempXfer.txData = NULL;
+ tempXfer.rxData = xfer->rxData;
+ tempXfer.dataSize = xfer->rxDataSize;
+ }
+ else
+ {
+ tempXfer.txData = xfer->txData;
+ tempXfer.rxData = NULL;
+ tempXfer.dataSize = xfer->txDataSize;
+ }
+ tempXfer.configFlags = xfer->configFlags;
+
+ status = SPI_MasterTransferDMA(base, handle, &tempXfer);
+
+ return status;
+}
+
static void SPI_RxDMACallback(dma_handle_t *handle, void *userData, bool transferDone, uint32_t intmode)
{
spi_dma_private_handle_t *privHandle = (spi_dma_private_handle_t *)userData;
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spi_dma.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spi_dma.h Tue Mar 20 16:56:18 2018 +0000 @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE @@ -112,6 +116,21 @@ status_t SPI_MasterTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_transfer_t *xfer); /*! + * @brief Transfers a block of data using a DMA method. + * + * This function using polling way to do the first half transimission and using DMA way to + * do the srcond half transimission, the transfer mechanism is half-duplex. + * When do the second half transimission, code will return right away. When all data is transferred, + * the callback function is called. + * + * @param base SPI base pointer + * @param handle A pointer to the spi_master_dma_handle_t structure which stores the transfer state. + * @param transfer A pointer to the spi_half_duplex_transfer_t structure. + * @return status of status_t. + */ +status_t SPI_MasterHalfDuplexTransferDMA(SPI_Type *base, spi_dma_handle_t *handle, spi_half_duplex_transfer_t *xfer); + +/*! * @brief Initialize the SPI slave DMA handle. * * This function initializes the SPI slave DMA handle which can be used for other SPI master transactional APIs.
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spifi.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spifi.c Tue Mar 20 16:56:18 2018 +0000
@@ -1,9 +1,12 @@
/*
+ * The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
+ * All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -87,7 +91,7 @@
config->disableCachePrefech = false;
config->isFeedbackClock = true;
config->spiMode = kSPIFI_SPISckLow;
- config->isReadFullClockCycle = false;
+ config->isReadFullClockCycle = true;
config->dualMode = kSPIFI_QuadMode;
}
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spifi.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spifi.h Tue Mar 20 16:56:18 2018 +0000 @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spifi_dma.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spifi_dma.c Tue Mar 20 16:56:18 2018 +0000 @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spifi_dma.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_spifi_dma.h Tue Mar 20 16:56:18 2018 +0000 @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_usart.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_usart.c Tue Mar 20 16:56:18 2018 +0000
@@ -1,9 +1,12 @@
/*
+ * The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
+ * All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -71,7 +75,7 @@
return 0;
}
-static size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle)
+size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle)
{
size_t size;
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_usart.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_usart.h Tue Mar 20 16:56:18 2018 +0000
@@ -1,9 +1,12 @@
/*
+ * The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
+ * All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -366,7 +370,19 @@
*/
static inline void USART_DisableInterrupts(USART_Type *base, uint32_t mask)
{
- base->FIFOINTENSET = ~(mask & 0xF);
+ base->FIFOINTENCLR = mask & 0xF;
+}
+
+/*!
+ * @brief Returns enabled USART interrupts.
+ *
+ * This function returns the enabled USART interrupts.
+ *
+ * @param base USART peripheral base address.
+ */
+static inline uint32_t USART_GetEnabledInterrupts(USART_Type *base)
+{
+ return base->FIFOINTENSET;
}
/*!
@@ -541,6 +557,14 @@
void USART_TransferStopRingBuffer(USART_Type *base, usart_handle_t *handle);
/*!
+ * @brief Get the length of received data in RX ring buffer.
+ *
+ * @param handle USART handle pointer.
+ * @return Length of received data in RX ring buffer.
+ */
+size_t USART_TransferGetRxRingBufferLength(usart_handle_t *handle);
+
+/*!
* @brief Aborts the interrupt-driven data transmit.
*
* This function aborts the interrupt driven data sending. The user can get the remainBtyes to find out
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_usart_dma.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_usart_dma.c Tue Mar 20 16:56:18 2018 +0000 @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_usart_dma.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_usart_dma.h Tue Mar 20 16:56:18 2018 +0000 @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_utick.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_utick.c Tue Mar 20 16:56:18 2018 +0000
@@ -1,9 +1,12 @@
/*
+ * The Clear BSD License
* Copyright (c) 2016, Freescale Semiconductor, Inc.
* Copyright 2016-2017 NXP
+ * All rights reserved.
*
* Redistribution and use in source and binary forms, with or without modification,
- * are permitted provided that the following conditions are met:
+ * are permitted (subject to the limitations in the disclaimer below) provided
+ * that the following conditions are met:
*
* o Redistributions of source code must retain the above copyright notice, this list
* of conditions and the following disclaimer.
@@ -16,6 +19,7 @@
* contributors may be used to endorse or promote products derived from this
* software without specific prior written permission.
*
+ * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE.
* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
* ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
* WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
@@ -139,17 +143,32 @@
void UTICK0_DriverIRQHandler(void)
{
s_utickIsr(UTICK0, s_utickHandle[0]);
+ /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
}
#endif
#if defined(UTICK1)
void UTICK1_DriverIRQHandler(void)
{
s_utickIsr(UTICK1, s_utickHandle[1]);
+ /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
}
#endif
#if defined(UTICK2)
void UTICK2_DriverIRQHandler(void)
{
s_utickIsr(UTICK2, s_utickHandle[2]);
+ /* Add for ARM errata 838869, affects Cortex-M4, Cortex-M4F Store immediate overlapping
+ exception return operation might vector to incorrect interrupt */
+#if defined __CORTEX_M && (__CORTEX_M == 4U)
+ __DSB();
+#endif
}
#endif
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_utick.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_utick.h Tue Mar 20 16:56:18 2018 +0000 @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_wwdt.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_wwdt.c Tue Mar 20 16:56:18 2018 +0000 @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--- a/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_wwdt.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_NXP/TARGET_MCUXpresso_MCUS/TARGET_LPC546XX/drivers/fsl_wwdt.h Tue Mar 20 16:56:18 2018 +0000 @@ -1,9 +1,12 @@ /* + * The Clear BSD License * Copyright (c) 2016, Freescale Semiconductor, Inc. * Copyright 2016-2017 NXP + * All rights reserved. * * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * are permitted (subject to the limitations in the disclaimer below) provided + * that the following conditions are met: * * o Redistributions of source code must retain the above copyright notice, this list * of conditions and the following disclaimer. @@ -16,6 +19,7 @@ * contributors may be used to endorse or promote products derived from this * software without specific prior written permission. * + * NO EXPRESS OR IMPLIED LICENSES TO ANY PARTY'S PATENT RIGHTS ARE GRANTED BY THIS LICENSE. * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_ARM/startup_NCS36510.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,208 @@ +;/* File: startup_ncs36510.s +; * Purpose: startup file for Cortex-M3 devices. Should use with +; * ARMGCC for ARM Embedded Processors +; * Version: V2.00 +; * Date: 25 Feb 2016 +; * +; */ +;/* Copyright (c) 2011 - 2014 ARM LIMITED +; +; All rights reserved. +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; - Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; - Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; - Neither the name of ARM nor the names of its contributors may be used +; to endorse or promote products derived from this software without +; specific prior written permission. +; * +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +; ---------------------------------------------------------------------------*/ + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0x3000 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + IMPORT |Image$$ARM_LIB_HEAP$$ZI$$Limit| + +__Vectors DCD |Image$$ARM_LIB_HEAP$$ZI$$Limit| ; Top of RAM + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD fIrqTim0Handler + DCD fIrqTim1Handler + DCD fIrqTim2Handler + DCD fIrqUart1Handler + DCD fIrqSpiHandler + DCD fIrqI2CHandler + DCD fIrqGpioHandler + DCD fIrqRtcHandler + DCD fIrqFlashHandler + DCD fIrqMacHwHandler + DCD fIrqAesHandler + DCD fIrqAdcHandler + DCD fIrqClockCalHandler + DCD fIrqUart2Handler + DCD fIrqUviHandler + DCD fIrqDmaHandler + DCD fIrqDbgPwrUpHandler + DCD fIrqSpi2Handler + DCD fIrqI2C2Handler + DCD fIrqFVDDHCompHandler +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + EXPORT fIrqTim0Handler [WEAK] + EXPORT fIrqTim1Handler [WEAK] + EXPORT fIrqTim2Handler [WEAK] + EXPORT fIrqUart1Handler [WEAK] + EXPORT fIrqSpiHandler [WEAK] + EXPORT fIrqI2CHandler [WEAK] + EXPORT fIrqGpioHandler [WEAK] + EXPORT fIrqRtcHandler [WEAK] + EXPORT fIrqFlashHandler [WEAK] + EXPORT fIrqMacHwHandler [WEAK] + EXPORT fIrqAesHandler [WEAK] + EXPORT fIrqAdcHandler [WEAK] + EXPORT fIrqClockCalHandler [WEAK] + EXPORT fIrqUart2Handler [WEAK] + EXPORT fIrqUviHandler [WEAK] + EXPORT fIrqDmaHandler [WEAK] + EXPORT fIrqDbgPwrUpHandler [WEAK] + EXPORT fIrqSpi2Handler [WEAK] + EXPORT fIrqI2C2Handler [WEAK] + EXPORT fIrqFVDDHCompHandler [WEAK] + +fIrqTim0Handler +fIrqTim1Handler +fIrqTim2Handler +fIrqUart1Handler +fIrqSpiHandler +fIrqI2CHandler +fIrqGpioHandler +fIrqRtcHandler +fIrqFlashHandler +fIrqMacHwHandler +fIrqAesHandler +fIrqAdcHandler +fIrqClockCalHandler +fIrqUart2Handler +fIrqUviHandler +fIrqDmaHandler +fIrqDbgPwrUpHandler +fIrqSpi2Handler +fIrqI2C2Handler +fIrqFVDDHCompHandler +DefaultISR + + B . + + ENDP + + EXPORT __user_initial_stackheap + IMPORT |Image$$ARM_LIB_HEAP$$Base| + IMPORT |Image$$ARM_LIB_HEAP$$ZI$$Limit| + +__user_initial_stackheap PROC + LDR R0, = |Image$$ARM_LIB_HEAP$$Base| + LDR R2, = |Image$$ARM_LIB_HEAP$$ZI$$Limit| + BX LR + ENDP + + ALIGN + END
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_ARM/startup_NCS36510.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,208 +0,0 @@ -;/* File: startup_ncs36510.s -; * Purpose: startup file for Cortex-M3 devices. Should use with -; * ARMGCC for ARM Embedded Processors -; * Version: V2.00 -; * Date: 25 Feb 2016 -; * -; */ -;/* Copyright (c) 2011 - 2014 ARM LIMITED -; -; All rights reserved. -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; - Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; - Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; - Neither the name of ARM nor the names of its contributors may be used -; to endorse or promote products derived from this software without -; specific prior written permission. -; * -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE -; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; POSSIBILITY OF SUCH DAMAGE. -; ---------------------------------------------------------------------------*/ - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0x3000 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - IMPORT |Image$$ARM_LIB_HEAP$$ZI$$Limit| - -__Vectors DCD |Image$$ARM_LIB_HEAP$$ZI$$Limit| ; Top of RAM - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD fIrqTim0Handler - DCD fIrqTim1Handler - DCD fIrqTim2Handler - DCD fIrqUart1Handler - DCD fIrqSpiHandler - DCD fIrqI2CHandler - DCD fIrqGpioHandler - DCD fIrqRtcHandler - DCD fIrqFlashHandler - DCD fIrqMacHwHandler - DCD fIrqAesHandler - DCD fIrqAdcHandler - DCD fIrqClockCalHandler - DCD fIrqUart2Handler - DCD fIrqUviHandler - DCD fIrqDmaHandler - DCD fIrqDbgPwrUpHandler - DCD fIrqSpi2Handler - DCD fIrqI2C2Handler - DCD fIrqFVDDHCompHandler -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - EXPORT fIrqTim0Handler [WEAK] - EXPORT fIrqTim1Handler [WEAK] - EXPORT fIrqTim2Handler [WEAK] - EXPORT fIrqUart1Handler [WEAK] - EXPORT fIrqSpiHandler [WEAK] - EXPORT fIrqI2CHandler [WEAK] - EXPORT fIrqGpioHandler [WEAK] - EXPORT fIrqRtcHandler [WEAK] - EXPORT fIrqFlashHandler [WEAK] - EXPORT fIrqMacHwHandler [WEAK] - EXPORT fIrqAesHandler [WEAK] - EXPORT fIrqAdcHandler [WEAK] - EXPORT fIrqClockCalHandler [WEAK] - EXPORT fIrqUart2Handler [WEAK] - EXPORT fIrqUviHandler [WEAK] - EXPORT fIrqDmaHandler [WEAK] - EXPORT fIrqDbgPwrUpHandler [WEAK] - EXPORT fIrqSpi2Handler [WEAK] - EXPORT fIrqI2C2Handler [WEAK] - EXPORT fIrqFVDDHCompHandler [WEAK] - -fIrqTim0Handler -fIrqTim1Handler -fIrqTim2Handler -fIrqUart1Handler -fIrqSpiHandler -fIrqI2CHandler -fIrqGpioHandler -fIrqRtcHandler -fIrqFlashHandler -fIrqMacHwHandler -fIrqAesHandler -fIrqAdcHandler -fIrqClockCalHandler -fIrqUart2Handler -fIrqUviHandler -fIrqDmaHandler -fIrqDbgPwrUpHandler -fIrqSpi2Handler -fIrqI2C2Handler -fIrqFVDDHCompHandler -DefaultISR - - B . - - ENDP - - EXPORT __user_initial_stackheap - IMPORT |Image$$ARM_LIB_HEAP$$Base| - IMPORT |Image$$ARM_LIB_HEAP$$ZI$$Limit| - -__user_initial_stackheap PROC - LDR R0, = |Image$$ARM_LIB_HEAP$$Base| - LDR R2, = |Image$$ARM_LIB_HEAP$$ZI$$Limit| - BX LR - ENDP - - ALIGN - END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_GCC_ARM/startup_NCS36510.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,214 @@ +/* File: startup_ncs36510.S + * Purpose: startup file for Cortex-M3 devices. Should use with + * GCC for ARM Embedded Processors + * Version: V2.00 + * Date: 15 Jan 2016 + * + */ +/* Copyright (c) 2011 - 2014 ARM LIMITED + + All rights reserved. + Redistribution and use in source and binary forms, with or without + modification, are permitted provided that the following conditions are met: + - Redistributions of source code must retain the above copyright + notice, this list of conditions and the following disclaimer. + - Redistributions in binary form must reproduce the above copyright + notice, this list of conditions and the following disclaimer in the + documentation and/or other materials provided with the distribution. + - Neither the name of ARM nor the names of its contributors may be used + to endorse or promote products derived from this software without + specific prior written permission. + * + THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE + ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE + LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR + CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF + SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS + INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN + CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) + ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + POSSIBILITY OF SUCH DAMAGE. + ---------------------------------------------------------------------------*/ + + +.syntax unified +.arch armv7-m + +.section .stack +.align 3 +#ifdef __STACK_SIZE +.equ Stack_Size, __STACK_SIZE +#else +.equ Stack_Size, 0x400 +#endif +.globl __StackTop +.globl __StackLimit +__StackLimit: +.space Stack_Size +.size __StackLimit, . - __StackLimit +__StackTop: +.size __StackTop, . - __StackTop + +.section .heap +.align 3 +#ifdef __HEAP_SIZE +.equ Heap_Size, __HEAP_SIZE +#else +.equ Heap_Size, 0x400 +#endif +.globl __HeapBase +.globl __HeapLimit +__HeapBase: +.space Heap_Size +.size __HeapBase, . - __HeapBase +__HeapLimit: +.size __HeapLimit, . - __HeapLimit + +.section .vector_table,"a",%progbits +.align 2 +.globl __Vectors +__Vectors: +.long __StackTop /* Top of Stack */ +.long Reset_Handler /* Reset Handler */ +.long NMI_Handler /* NMI Handler */ +.long HardFault_Handler /* Hard Fault Handler */ +.long MemManage_Handler /* MPU Fault Handler */ +.long BusFault_Handler /* Bus Fault Handler */ +.long UsageFault_Handler /* Usage Fault Handler */ +.long 0 /* Reserved */ +.long 0 /* Reserved */ +.long 0 /* Reserved */ +.long 0 /* Reserved */ +.long SVC_Handler /* SVCall Handler */ +.long DebugMon_Handler /* Debug Monitor Handler */ +.long 0 /* Reserved */ +.long PendSV_Handler /* PendSV Handler */ +.long SysTick_Handler /* SysTick Handler */ + +/* External Interrupts */ +.long fIrqTim0Handler +.long fIrqTim1Handler +.long fIrqTim2Handler +.long fIrqUart1Handler +.long fIrqSpiHandler +.long fIrqI2CHandler +.long fIrqGpioHandler +.long fIrqRtcHandler +.long fIrqFlashHandler +.long fIrqMacHwHandler +.long fIrqAesHandler +.long fIrqAdcHandler +.long fIrqClockCalHandler +.long fIrqUart2Handler +.long fIrqUviHandler +.long fIrqDmaHandler +.long fIrqDbgPwrUpHandler +.long fIrqSpi2Handler +.long fIrqI2C2Handler +.long fIrqFVDDHCompHandler + +.size __Vectors, . - __Vectors + +.section .text.Reset_Handler +.thumb +.thumb_func +.align 2 +.globl Reset_Handler +.type Reset_Handler, %function +Reset_Handler: +/* Loop to copy data from read only memory to RAM. The ranges +* of copy from/to are specified by following symbols evaluated in +* linker script. +* __etext: End of code section, i.e., begin of data sections to copy from. +* __data_start__/__data_end__: RAM address range that data should be +* copied to. Both must be aligned to 4 bytes boundary. */ + +disable_watchdog: +/*MPL - Need to implement?! */ + + ldr r1, =__etext + ldr r2, =__data_start__ + ldr r3, =__data_end__ + + subs r3, r2 + ble .Lflash_to_ram_loop_end + + movs r4, 0 +.Lflash_to_ram_loop: + ldr r0, [r1,r4] + str r0, [r2,r4] + adds r4, 4 + cmp r4, r3 + blt .Lflash_to_ram_loop +.Lflash_to_ram_loop_end: + + ldr r0, =SystemInit + blx r0 +/* TODO - Uncomment when uvisor support is added */ +/* + ldr r0, =uvisor_init + blx r0 +*/ + ldr r0, =_start + bx r0 + .pool + .size Reset_Handler, . - Reset_Handler + + .text +/* Macro to define default handlers. Default handler +* will be weak symbol and just dead loops. They can be +* overwritten by other handlers */ + .macro def_default_handler handler_name + .align 1 + .thumb_func + .weak \handler_name + .type \handler_name, %function +\handler_name : + b . + .size \handler_name, . - \handler_name + .endm + +/* Exception Handlers */ + + def_default_handler NMI_Handler + def_default_handler HardFault_Handler + def_default_handler MemManage_Handler + def_default_handler BusFault_Handler + def_default_handler UsageFault_Handler + def_default_handler SVC_Handler + def_default_handler DebugMon_Handler + def_default_handler PendSV_Handler + def_default_handler SysTick_Handler + def_default_handler Default_Handler + + .macro def_irq_default_handler handler_name + .weak \handler_name + .set \handler_name, Default_Handler + .endm + +/* IRQ Handlers */ + def_irq_default_handler fIrqTim0Handler + def_irq_default_handler fIrqTim1Handler + def_irq_default_handler fIrqTim2Handler + def_irq_default_handler fIrqUart1Handler + def_irq_default_handler fIrqSpiHandler + def_irq_default_handler fIrqI2CHandler + def_irq_default_handler fIrqGpioHandler + def_irq_default_handler fIrqRtcHandler + def_irq_default_handler fIrqFlashHandler + def_irq_default_handler fIrqMacHwHandler + def_irq_default_handler fIrqAesHandler + def_irq_default_handler fIrqAdcHandler + def_irq_default_handler fIrqClockCalHandler + def_irq_default_handler fIrqUart2Handler + def_irq_default_handler fIrqUviHandler + def_irq_default_handler fIrqDmaHandler + def_irq_default_handler fIrqDbgPwrUpHandler + def_irq_default_handler fIrqSpi2Handler + def_irq_default_handler fIrqI2C2Handler + def_irq_default_handler fIrqFVDDHCompHandler + def_irq_default_handler DefaultISR + + .end
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_GCC_ARM/startup_NCS36510.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,214 +0,0 @@ -/* File: startup_ncs36510.S - * Purpose: startup file for Cortex-M3 devices. Should use with - * GCC for ARM Embedded Processors - * Version: V2.00 - * Date: 15 Jan 2016 - * - */ -/* Copyright (c) 2011 - 2014 ARM LIMITED - - All rights reserved. - Redistribution and use in source and binary forms, with or without - modification, are permitted provided that the following conditions are met: - - Redistributions of source code must retain the above copyright - notice, this list of conditions and the following disclaimer. - - Redistributions in binary form must reproduce the above copyright - notice, this list of conditions and the following disclaimer in the - documentation and/or other materials provided with the distribution. - - Neither the name of ARM nor the names of its contributors may be used - to endorse or promote products derived from this software without - specific prior written permission. - * - THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE - ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE - LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR - CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF - SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS - INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN - CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) - ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE - POSSIBILITY OF SUCH DAMAGE. - ---------------------------------------------------------------------------*/ - - -.syntax unified -.arch armv7-m - -.section .stack -.align 3 -#ifdef __STACK_SIZE -.equ Stack_Size, __STACK_SIZE -#else -.equ Stack_Size, 0x400 -#endif -.globl __StackTop -.globl __StackLimit -__StackLimit: -.space Stack_Size -.size __StackLimit, . - __StackLimit -__StackTop: -.size __StackTop, . - __StackTop - -.section .heap -.align 3 -#ifdef __HEAP_SIZE -.equ Heap_Size, __HEAP_SIZE -#else -.equ Heap_Size, 0x400 -#endif -.globl __HeapBase -.globl __HeapLimit -__HeapBase: -.space Heap_Size -.size __HeapBase, . - __HeapBase -__HeapLimit: -.size __HeapLimit, . - __HeapLimit - -.section .vector_table,"a",%progbits -.align 2 -.globl __Vectors -__Vectors: -.long __StackTop /* Top of Stack */ -.long Reset_Handler /* Reset Handler */ -.long NMI_Handler /* NMI Handler */ -.long HardFault_Handler /* Hard Fault Handler */ -.long MemManage_Handler /* MPU Fault Handler */ -.long BusFault_Handler /* Bus Fault Handler */ -.long UsageFault_Handler /* Usage Fault Handler */ -.long 0 /* Reserved */ -.long 0 /* Reserved */ -.long 0 /* Reserved */ -.long 0 /* Reserved */ -.long SVC_Handler /* SVCall Handler */ -.long DebugMon_Handler /* Debug Monitor Handler */ -.long 0 /* Reserved */ -.long PendSV_Handler /* PendSV Handler */ -.long SysTick_Handler /* SysTick Handler */ - -/* External Interrupts */ -.long fIrqTim0Handler -.long fIrqTim1Handler -.long fIrqTim2Handler -.long fIrqUart1Handler -.long fIrqSpiHandler -.long fIrqI2CHandler -.long fIrqGpioHandler -.long fIrqRtcHandler -.long fIrqFlashHandler -.long fIrqMacHwHandler -.long fIrqAesHandler -.long fIrqAdcHandler -.long fIrqClockCalHandler -.long fIrqUart2Handler -.long fIrqUviHandler -.long fIrqDmaHandler -.long fIrqDbgPwrUpHandler -.long fIrqSpi2Handler -.long fIrqI2C2Handler -.long fIrqFVDDHCompHandler - -.size __Vectors, . - __Vectors - -.section .text.Reset_Handler -.thumb -.thumb_func -.align 2 -.globl Reset_Handler -.type Reset_Handler, %function -Reset_Handler: -/* Loop to copy data from read only memory to RAM. The ranges -* of copy from/to are specified by following symbols evaluated in -* linker script. -* __etext: End of code section, i.e., begin of data sections to copy from. -* __data_start__/__data_end__: RAM address range that data should be -* copied to. Both must be aligned to 4 bytes boundary. */ - -disable_watchdog: -/*MPL - Need to implement?! */ - - ldr r1, =__etext - ldr r2, =__data_start__ - ldr r3, =__data_end__ - - subs r3, r2 - ble .Lflash_to_ram_loop_end - - movs r4, 0 -.Lflash_to_ram_loop: - ldr r0, [r1,r4] - str r0, [r2,r4] - adds r4, 4 - cmp r4, r3 - blt .Lflash_to_ram_loop -.Lflash_to_ram_loop_end: - - ldr r0, =SystemInit - blx r0 -/* TODO - Uncomment when uvisor support is added */ -/* - ldr r0, =uvisor_init - blx r0 -*/ - ldr r0, =_start - bx r0 - .pool - .size Reset_Handler, . - Reset_Handler - - .text -/* Macro to define default handlers. Default handler -* will be weak symbol and just dead loops. They can be -* overwritten by other handlers */ - .macro def_default_handler handler_name - .align 1 - .thumb_func - .weak \handler_name - .type \handler_name, %function -\handler_name : - b . - .size \handler_name, . - \handler_name - .endm - -/* Exception Handlers */ - - def_default_handler NMI_Handler - def_default_handler HardFault_Handler - def_default_handler MemManage_Handler - def_default_handler BusFault_Handler - def_default_handler UsageFault_Handler - def_default_handler SVC_Handler - def_default_handler DebugMon_Handler - def_default_handler PendSV_Handler - def_default_handler SysTick_Handler - def_default_handler Default_Handler - - .macro def_irq_default_handler handler_name - .weak \handler_name - .set \handler_name, Default_Handler - .endm - -/* IRQ Handlers */ - def_irq_default_handler fIrqTim0Handler - def_irq_default_handler fIrqTim1Handler - def_irq_default_handler fIrqTim2Handler - def_irq_default_handler fIrqUart1Handler - def_irq_default_handler fIrqSpiHandler - def_irq_default_handler fIrqI2CHandler - def_irq_default_handler fIrqGpioHandler - def_irq_default_handler fIrqRtcHandler - def_irq_default_handler fIrqFlashHandler - def_irq_default_handler fIrqMacHwHandler - def_irq_default_handler fIrqAesHandler - def_irq_default_handler fIrqAdcHandler - def_irq_default_handler fIrqClockCalHandler - def_irq_default_handler fIrqUart2Handler - def_irq_default_handler fIrqUviHandler - def_irq_default_handler fIrqDmaHandler - def_irq_default_handler fIrqDbgPwrUpHandler - def_irq_default_handler fIrqSpi2Handler - def_irq_default_handler fIrqI2C2Handler - def_irq_default_handler fIrqFVDDHCompHandler - def_irq_default_handler DefaultISR - - .end
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_IAR/startup_NCS36510.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,310 @@ +;/****************************************************************************** +; * @file startup_ARMCM3.s +; * @brief CMSIS Cortex-M4 Core Device Startup File +; * for CM3 Device Series +; * @version V1.05 +; * @date 25. July 2011 +; * +; * @note +; * Copyright (C) 2010-2011 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ + + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + EXTERN fInitSource + EXTERN HardFault_Handler + EXTERN SVC_Handler + EXTERN PendSV_Handler + EXTERN SysTick_Handler + EXTERN fIrqTim0Handler + EXTERN fIrqTim1Handler + EXTERN fIrqTim2Handler + EXTERN fIrqGpioHandler + EXTERN fIrqSpiHandler + EXTERN fIrqUart1Handler + EXTERN fIrqUart2Handler + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler +#ifndef RAM_VECTOR_TABLE + DCD NMI_Handler + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +#endif +__vector_table_0x1c +#ifndef RAM_VECTOR_TABLE + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + DCD fIrqTim0Handler + DCD fIrqTim1Handler + DCD fIrqTim2Handler + DCD fIrqUart1Handler + DCD fIrqSpiHandler + DCD fIrqI2CHandler + DCD fIrqGpioHandler + DCD fIrqRtcHandler + DCD fIrqFlashHandler + DCD fIrqMacHwHandler + DCD fIrqAesHandler + DCD fIrqAdcHandler + DCD fIrqClockCalHandler + DCD fIrqUart2Handler + DCD fIrqUviHandler + DCD fIrqDmaHandler + DCD fIrqDbgPwrUpHandler + /* REV C/D interrupts */ + DCD fIrqSpi2Handler + DCD fIrqI2c2Handler + DCD FIrqFVDDHCompHandler /* FVDDH Supply Comparator Trip */ +#endif +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + +opt: DC32 0x2082353F /* Full featured device */ +opt_reg: DC32 0x4001E000 +enable: DC32 0x00000000 +per_en: DC32 0x4001B010 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + +;; Taken from article http://netstorage.iar.com/SuppDB/Public/UPDINFO/007040/arm/doc/infocenter/ilinkarm.ENU.html +;; If this line is removed, veneers for functions copied into RAM are flasely also placed in RAM, but are NOT +;; copied into it by __iar_copy_init3 +__iar_init$$done + + PUBLIC Reset_Handler + SECTION .text:CODE:REORDER(2) +Reset_Handler + LDR R0,= enable ;; load R0 with address of enable + LDR R0,[R0] ;; load R0 with what address R0 points to + LDR R1,= per_en ;; load R1 with address of per_en + LDR R1,[R1] ;; load R1 with what address R1 points to + STR R0,[R1] ;; store R0 into address pointed to by R1 /* Disable all peripherals */ + + LDR R0,= opt ;; load R0 with address of opt + LDR R0,[R0] ;; load R0 with what address R0 points to + LDR R1,= opt_reg ;; load R1 with address of opt_reg + LDR R1,[R1] ;; load R1 with what address R1 points to + STR R0, [R1] ;; store R0 into address pointed to by R1 /* Device option: Full featured device */ + + LDR R0,= sfe(CSTACK) + MOV SP,R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + +; PUBWEAK HardFault_Handler +; SECTION .text:CODE:REORDER:NOROOT(1) +;HardFault_Handler +; B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + +; PUBWEAK vPortSVCHandler +; SECTION .text:CODE:REORDER:NOROOT(1) +;vPortSVCHandler +; B vPortSVCHandler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + +; PUBWEAK xPortPendSVHandler +; SECTION .text:CODE:REORDER:NOROOT(1) +;xPortPendSVHandler +; B xPortPendSVHandler + +; PUBWEAK SysTick_Handler +; SECTION .text:CODE:REORDER:NOROOT(1) +;SysTick_Handler +; B SysTick_Handler + + +; PUBWEAK fIrqTim0Handler +; SECTION .text:CODE:REORDER:NOROOT(1) +;fIrqTim0Handler +; B fIrqTim0Handler + +; PUBWEAK fIrqTim1Handler +; SECTION .text:CODE:REORDER:NOROOT(1) +;fIrqTim1Handler +; B fIrqTim1Handler + +; PUBWEAK fIrqTim2Handler +; SECTION .text:CODE:REORDER:NOROOT(1) +;fIrqTim2Handler +; B fIrqTim2Handler + +; PUBWEAK fIrqUart1Handler +; SECTION .text:CODE:REORDER:NOROOT(1) +;fIrqUart1Handler +; B fIrqUart1Handler + +; PUBWEAK fIrqSpiHandler +; SECTION .text:CODE:REORDER:NOROOT(1) +;fIrqSpiHandler +; B fIrqSpiHandler + + PUBWEAK fIrqI2CHandler + SECTION .text:CODE:REORDER:NOROOT(1) +fIrqI2CHandler + B fIrqI2CHandler + +; PUBWEAK fIrqGpioHandler +; SECTION .text:CODE:REORDER:NOROOT(1) +;fIrqGpioHandler +; B fIrqGpioHandler + + PUBWEAK fIrqRtcHandler + SECTION .text:CODE:REORDER:NOROOT(1) +fIrqRtcHandler + B fIrqRtcHandler + + PUBWEAK fIrqFlashHandler + SECTION .text:CODE:REORDER:NOROOT(1) +fIrqFlashHandler + B fIrqFlashHandler + + PUBWEAK fIrqMacHwHandler + SECTION .text:CODE:REORDER:NOROOT(1) +fIrqMacHwHandler + B fIrqMacHwHandler + + PUBWEAK fIrqAesHandler + SECTION .text:CODE:REORDER:NOROOT(1) +fIrqAesHandler + B fIrqAesHandler + + PUBWEAK fIrqAdcHandler + SECTION .text:CODE:REORDER:NOROOT(1) +fIrqAdcHandler + B fIrqAdcHandler + + PUBWEAK fIrqClockCalHandler + SECTION .text:CODE:REORDER:NOROOT(1) +fIrqClockCalHandler + B fIrqClockCalHandler + +; PUBWEAK fIrqUart2Handler +; SECTION .text:CODE:REORDER:NOROOT(1) +;fIrqUart2Handler +; B fIrqUart2Handler + + PUBWEAK fIrqDbgPwrUpHandler + SECTION .text:CODE:REORDER:NOROOT(1) +fIrqDbgPwrUpHandler + B fIrqDbgPwrUpHandler + + PUBWEAK fIrqDmaHandler + SECTION .text:CODE:REORDER:NOROOT(1) +fIrqDmaHandler + B fIrqDmaHandler + + PUBWEAK fIrqUviHandler + SECTION .text:CODE:REORDER:NOROOT(1) +fIrqUviHandler + B fIrqUviHandler + + PUBWEAK fIrqSpi2Handler + SECTION .text:CODE:REORDER:NOROOT(1) +fIrqSpi2Handler + B fIrqSpi2Handler + + PUBWEAK fIrqI2c2Handler + SECTION .text:CODE:REORDER:NOROOT(1) +fIrqI2c2Handler + B fIrqI2c2Handler + + PUBWEAK FIrqFVDDHCompHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FIrqFVDDHCompHandler + B FIrqFVDDHCompHandler + + PUBWEAK DEF_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DEF_IRQHandler + B DEF_IRQHandler + + END
--- a/targets/TARGET_ONSEMI/TARGET_NCS36510/device/TOOLCHAIN_IAR/startup_NCS36510.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,310 +0,0 @@ -;/****************************************************************************** -; * @file startup_ARMCM3.s -; * @brief CMSIS Cortex-M4 Core Device Startup File -; * for CM3 Device Series -; * @version V1.05 -; * @date 25. July 2011 -; * -; * @note -; * Copyright (C) 2010-2011 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ - - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - EXTERN fInitSource - EXTERN HardFault_Handler - EXTERN SVC_Handler - EXTERN PendSV_Handler - EXTERN SysTick_Handler - EXTERN fIrqTim0Handler - EXTERN fIrqTim1Handler - EXTERN fIrqTim2Handler - EXTERN fIrqGpioHandler - EXTERN fIrqSpiHandler - EXTERN fIrqUart1Handler - EXTERN fIrqUart2Handler - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler -#ifndef RAM_VECTOR_TABLE - DCD NMI_Handler - DCD HardFault_Handler - DCD MemManage_Handler - DCD BusFault_Handler - DCD UsageFault_Handler -#endif -__vector_table_0x1c -#ifndef RAM_VECTOR_TABLE - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD SVC_Handler - DCD DebugMon_Handler - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - DCD fIrqTim0Handler - DCD fIrqTim1Handler - DCD fIrqTim2Handler - DCD fIrqUart1Handler - DCD fIrqSpiHandler - DCD fIrqI2CHandler - DCD fIrqGpioHandler - DCD fIrqRtcHandler - DCD fIrqFlashHandler - DCD fIrqMacHwHandler - DCD fIrqAesHandler - DCD fIrqAdcHandler - DCD fIrqClockCalHandler - DCD fIrqUart2Handler - DCD fIrqUviHandler - DCD fIrqDmaHandler - DCD fIrqDbgPwrUpHandler - /* REV C/D interrupts */ - DCD fIrqSpi2Handler - DCD fIrqI2c2Handler - DCD FIrqFVDDHCompHandler /* FVDDH Supply Comparator Trip */ -#endif -__Vectors_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - -opt: DC32 0x2082353F /* Full featured device */ -opt_reg: DC32 0x4001E000 -enable: DC32 0x00000000 -per_en: DC32 0x4001B010 - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - -;; Taken from article http://netstorage.iar.com/SuppDB/Public/UPDINFO/007040/arm/doc/infocenter/ilinkarm.ENU.html -;; If this line is removed, veneers for functions copied into RAM are flasely also placed in RAM, but are NOT -;; copied into it by __iar_copy_init3 -__iar_init$$done - - PUBLIC Reset_Handler - SECTION .text:CODE:REORDER(2) -Reset_Handler - LDR R0,= enable ;; load R0 with address of enable - LDR R0,[R0] ;; load R0 with what address R0 points to - LDR R1,= per_en ;; load R1 with address of per_en - LDR R1,[R1] ;; load R1 with what address R1 points to - STR R0,[R1] ;; store R0 into address pointed to by R1 /* Disable all peripherals */ - - LDR R0,= opt ;; load R0 with address of opt - LDR R0,[R0] ;; load R0 with what address R0 points to - LDR R1,= opt_reg ;; load R1 with address of opt_reg - LDR R1,[R1] ;; load R1 with what address R1 points to - STR R0, [R1] ;; store R0 into address pointed to by R1 /* Device option: Full featured device */ - - LDR R0,= sfe(CSTACK) - MOV SP,R0 - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - -; PUBWEAK HardFault_Handler -; SECTION .text:CODE:REORDER:NOROOT(1) -;HardFault_Handler -; B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B UsageFault_Handler - -; PUBWEAK vPortSVCHandler -; SECTION .text:CODE:REORDER:NOROOT(1) -;vPortSVCHandler -; B vPortSVCHandler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B DebugMon_Handler - -; PUBWEAK xPortPendSVHandler -; SECTION .text:CODE:REORDER:NOROOT(1) -;xPortPendSVHandler -; B xPortPendSVHandler - -; PUBWEAK SysTick_Handler -; SECTION .text:CODE:REORDER:NOROOT(1) -;SysTick_Handler -; B SysTick_Handler - - -; PUBWEAK fIrqTim0Handler -; SECTION .text:CODE:REORDER:NOROOT(1) -;fIrqTim0Handler -; B fIrqTim0Handler - -; PUBWEAK fIrqTim1Handler -; SECTION .text:CODE:REORDER:NOROOT(1) -;fIrqTim1Handler -; B fIrqTim1Handler - -; PUBWEAK fIrqTim2Handler -; SECTION .text:CODE:REORDER:NOROOT(1) -;fIrqTim2Handler -; B fIrqTim2Handler - -; PUBWEAK fIrqUart1Handler -; SECTION .text:CODE:REORDER:NOROOT(1) -;fIrqUart1Handler -; B fIrqUart1Handler - -; PUBWEAK fIrqSpiHandler -; SECTION .text:CODE:REORDER:NOROOT(1) -;fIrqSpiHandler -; B fIrqSpiHandler - - PUBWEAK fIrqI2CHandler - SECTION .text:CODE:REORDER:NOROOT(1) -fIrqI2CHandler - B fIrqI2CHandler - -; PUBWEAK fIrqGpioHandler -; SECTION .text:CODE:REORDER:NOROOT(1) -;fIrqGpioHandler -; B fIrqGpioHandler - - PUBWEAK fIrqRtcHandler - SECTION .text:CODE:REORDER:NOROOT(1) -fIrqRtcHandler - B fIrqRtcHandler - - PUBWEAK fIrqFlashHandler - SECTION .text:CODE:REORDER:NOROOT(1) -fIrqFlashHandler - B fIrqFlashHandler - - PUBWEAK fIrqMacHwHandler - SECTION .text:CODE:REORDER:NOROOT(1) -fIrqMacHwHandler - B fIrqMacHwHandler - - PUBWEAK fIrqAesHandler - SECTION .text:CODE:REORDER:NOROOT(1) -fIrqAesHandler - B fIrqAesHandler - - PUBWEAK fIrqAdcHandler - SECTION .text:CODE:REORDER:NOROOT(1) -fIrqAdcHandler - B fIrqAdcHandler - - PUBWEAK fIrqClockCalHandler - SECTION .text:CODE:REORDER:NOROOT(1) -fIrqClockCalHandler - B fIrqClockCalHandler - -; PUBWEAK fIrqUart2Handler -; SECTION .text:CODE:REORDER:NOROOT(1) -;fIrqUart2Handler -; B fIrqUart2Handler - - PUBWEAK fIrqDbgPwrUpHandler - SECTION .text:CODE:REORDER:NOROOT(1) -fIrqDbgPwrUpHandler - B fIrqDbgPwrUpHandler - - PUBWEAK fIrqDmaHandler - SECTION .text:CODE:REORDER:NOROOT(1) -fIrqDmaHandler - B fIrqDmaHandler - - PUBWEAK fIrqUviHandler - SECTION .text:CODE:REORDER:NOROOT(1) -fIrqUviHandler - B fIrqUviHandler - - PUBWEAK fIrqSpi2Handler - SECTION .text:CODE:REORDER:NOROOT(1) -fIrqSpi2Handler - B fIrqSpi2Handler - - PUBWEAK fIrqI2c2Handler - SECTION .text:CODE:REORDER:NOROOT(1) -fIrqI2c2Handler - B fIrqI2c2Handler - - PUBWEAK FIrqFVDDHCompHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FIrqFVDDHCompHandler - B FIrqFVDDHCompHandler - - PUBWEAK DEF_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DEF_IRQHandler - B DEF_IRQHandler - - END
--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/RZ_A1LU.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_GR_LYCHEE/device/inc/RZ_A1LU.h Tue Mar 20 16:56:18 2018 +0000 @@ -649,6 +649,7 @@ #define __L2C_PRESENT 1U /* L2C present */ #include "core_ca.h" +#include "nvic_wrapper.h" #include <system_RZ_A1LU.h> #include "iodefine.h"
--- a/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/RZ_A1H.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_RENESAS/TARGET_RZ_A1XX/TARGET_RZ_A1H/device/inc/RZ_A1H.h Tue Mar 20 16:56:18 2018 +0000 @@ -649,6 +649,7 @@ #define __L2C_PRESENT 1U /* L2C present */ #include "core_ca.h" +#include "nvic_wrapper.h" #include <system_RZ_A1H.h> #include "iodefine.h"
--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/analogin_api.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/analogin_api.c Tue Mar 20 16:56:18 2018 +0000 @@ -19,7 +19,9 @@ #include "hal_adc.h" #include "analogin_api.h" - +#ifdef CONFIG_MBED_ENABLED +#include "platform_stdlib.h" +#endif #if CONFIG_ADC_EN #include "pinmap.h"
--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/TOOLCHAIN_ARM_STD/rtl8195a.sct Tue Mar 20 16:56:18 2018 +0000
@@ -29,9 +29,6 @@
*libc.a (+RW)
*(.sdram.data*)
*lib_peripheral_mbed_arm.ar (+RW)
- }
-
- RW_IRAM2 +0 UNINIT FIXED {
*rtl8195a_crypto*.o(+ZI, COMMON)
*libc.a (+ZI, COMMON)
*(.bss.thread_stack_main)
--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_init.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/device/rtl8195a_init.c Tue Mar 20 16:56:18 2018 +0000
@@ -18,14 +18,14 @@
#if defined(__CC_ARM) || \
(defined (__ARMCC_VERSION) && __ARMCC_VERSION >= 6010050)
-extern uint8_t Image$$RW_IRAM2$$ZI$$Base[];
-extern uint8_t Image$$RW_IRAM2$$ZI$$Limit[];
+extern uint8_t Image$$RW_IRAM1$$ZI$$Base[];
+extern uint8_t Image$$RW_IRAM1$$ZI$$Limit[];
extern uint8_t Image$$TCM_OVERLAY$$ZI$$Base[];
extern uint8_t Image$$TCM_OVERLAY$$ZI$$Limit[];
extern uint8_t Image$$RW_DRAM2$$ZI$$Base[];
extern uint8_t Image$$RW_DRAM2$$ZI$$Limit[];
-#define __bss_sram_start__ Image$$RW_IRAM2$$ZI$$Base
-#define __bss_sram_end__ Image$$RW_IRAM2$$ZI$$Limit
+#define __bss_sram_start__ Image$$RW_IRAM1$$ZI$$Base
+#define __bss_sram_end__ Image$$RW_IRAM1$$ZI$$Limit
#define __bss_dtcm_start__ Image$$TCM_OVERLAY$$ZI$$Base
#define __bss_dtcm_end__ Image$$TCM_OVERLAY$$ZI$$Limit
#define __bss_dram_start__ Image$$RW_DRAM2$$ZI$$Base
--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/log_uart_api.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/log_uart_api.c Tue Mar 20 16:56:18 2018 +0000
@@ -17,6 +17,10 @@
#include "objects.h"
#include "log_uart_api.h"
+#ifdef CONFIG_MBED_ENABLED
+#include "platform_stdlib.h"
+#endif
+
#include <string.h>
const u32 log_uart_support_rate[] = {
--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/pwmout_api.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/pwmout_api.c Tue Mar 20 16:56:18 2018 +0000 @@ -18,6 +18,10 @@ #include "objects.h" #include "pinmap.h" +#ifdef CONFIG_MBED_ENABLED +#include "platform_stdlib.h" +#endif + #if DEVICE_PWMOUT #ifdef CONFIG_PWM_EN
--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/serial_api.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/serial_api.c Tue Mar 20 16:56:18 2018 +0000
@@ -17,6 +17,11 @@
#include "rtl8195a.h"
#include "objects.h"
#include "serial_api.h"
+
+#ifdef CONFIG_MBED_ENABLED
+#include "platform_stdlib.h"
+#endif
+
#if CONFIG_UART_EN
#include "pinmap.h"
@@ -68,9 +73,13 @@
#ifdef CONFIG_MBED_ENABLED
#include "log_uart_api.h"
+#include "hal_log_uart.h"
int stdio_uart_inited = 0;
serial_t stdio_uart;
log_uart_t stdio_uart_log;
+static uint32_t serial_log_irq_ids;
+static uart_irq_handler log_irq_handler;
+static uint32_t serial_log_irq_en;
#endif
static void SerialTxDoneCallBack(VOID *pAdapter);
@@ -99,7 +108,7 @@
return;
}
#ifdef CONFIG_MBED_ENABLED
- else if(uart_idx == UART_3){
+ else if (uart_idx == UART_3) {
obj->index = UART_3;
goto init_stdio;
}
@@ -158,11 +167,11 @@
{
PHAL_RUART_ADAPTER pHalRuartAdapter;
#ifdef CONFIG_GDMA_EN
- u8 uart_idx;
+ u8 uart_idx;
PUART_DMA_CONFIG pHalRuartDmaCfg;
#endif
#ifdef CONFIG_MBED_ENABLED
- if(obj->index == UART_3){
+ if (obj->index == UART_3) {
log_uart_free(&stdio_uart_log);
return;
}
@@ -189,7 +198,7 @@
void serial_baud(serial_t *obj, int baudrate)
{
#ifdef CONFIG_MBED_ENABLED
- if(obj->index == UART_3){
+ if (obj->index == UART_3) {
return;
}
#endif
@@ -204,7 +213,7 @@
void serial_format(serial_t *obj, int data_bits, SerialParity parity, int stop_bits)
{
#ifdef CONFIG_MBED_ENABLED
- if(obj->index == UART_3){
+ if (obj->index == UART_3) {
log_uart_format(&stdio_uart_log, data_bits, parity, stop_bits);
return;
}
@@ -271,30 +280,64 @@
}
}
+
+#ifdef CONFIG_MBED_ENABLED
+static void serial_loguart_irq_handler(uint32_t id, LOG_UART_INT_ID event)
+{
+ if (event == IIR_RX_RDY || event == IIR_CHAR_TIMEOUT)
+ {
+ if (log_irq_handler) {
+ log_irq_handler(serial_log_irq_ids, RxIrq);
+ }
+ } else if (event == IIR_THR_EMPTY) {
+ if (log_irq_handler) {
+ log_irq_handler(serial_log_irq_ids, TxIrq);
+ }
+ }
+ return;
+}
+#endif
+
+
+
void serial_irq_handler(serial_t *obj, uart_irq_handler handler, uint32_t id)
{
+
+#ifdef CONFIG_MBED_ENABLED
+ if (obj->index == UART_3) {
+ log_irq_handler = handler;
+ serial_log_irq_ids = id;
+ log_uart_irq_handler(&stdio_uart_log, serial_loguart_irq_handler, id);
+ return;
+ }
+#endif
PHAL_RUART_ADAPTER pHalRuartAdapter;
u8 uart_idx;
-
- pHalRuartAdapter = &(obj->hal_uart_adp);
+ pHalRuartAdapter = &(obj->hal_uart_adp);
uart_idx = pHalRuartAdapter->UartIndex;
-
irq_handler[uart_idx] = handler;
- serial_irq_ids[uart_idx] = id;
-
+ serial_irq_ids[uart_idx] = id;
pHalRuartAdapter->TxTDCallback = SerialTxDoneCallBack;
pHalRuartAdapter->TxTDCbPara = (void*)pHalRuartAdapter;
pHalRuartAdapter->RxDRCallback = SerialRxDoneCallBack;
pHalRuartAdapter->RxDRCbPara = (void*)pHalRuartAdapter;
}
-
void serial_irq_set(serial_t *obj, SerialIrq irq, uint32_t enable)
{
+#ifdef CONFIG_MBED_ENABLED
+ if (obj->index == UART_3) {
+ if (irq == RxIrq) {
+ log_uart_irq_set(&stdio_uart_log, IIR_RX_RDY, enable);
+ } else {
+ log_uart_irq_set(&stdio_uart_log, IIR_THR_EMPTY, enable);
+ }
+ return;
+ }
+#endif
PHAL_RUART_ADAPTER pHalRuartAdapter;
PHAL_RUART_OP pHalRuartOp;
u8 uart_idx;
-
pHalRuartAdapter = &(obj->hal_uart_adp);
pHalRuartOp = &(obj->hal_uart_op);
uart_idx = pHalRuartAdapter->UartIndex;
@@ -304,10 +347,12 @@
pHalRuartAdapter->Interrupts |= RUART_IER_ERBI | RUART_IER_ELSI;
serial_irq_en[uart_idx] |= SERIAL_RX_IRQ_EN;
HalRuartSetIMRRtl8195a (pHalRuartAdapter);
- } else {
+ } else {
serial_irq_en[uart_idx] |= SERIAL_TX_IRQ_EN;
}
+
pHalRuartOp->HalRuartRegIrq(pHalRuartAdapter);
+ //log_uart
pHalRuartOp->HalRuartIntEnable(pHalRuartAdapter);
} else { // disable
if (irq == RxIrq) {
@@ -318,6 +363,7 @@
serial_irq_en[uart_idx] &= ~SERIAL_TX_IRQ_EN;
}
HalRuartSetIMRRtl8195a (pHalRuartAdapter);
+
if (pHalRuartAdapter->Interrupts == 0) {
InterruptUnRegister(&pHalRuartAdapter->IrqHandle);
InterruptDis(&pHalRuartAdapter->IrqHandle);
@@ -332,7 +378,7 @@
int serial_getc(serial_t *obj)
{
#ifdef CONFIG_MBED_ENABLED
- if(obj->index == UART_3){
+ if (obj->index == UART_3) {
return log_uart_getc(&stdio_uart_log);
}
#endif
@@ -346,7 +392,7 @@
void serial_putc(serial_t *obj, int c)
{
#ifdef CONFIG_MBED_ENABLED
- if(obj->index == UART_3){
+ if (obj->index == UART_3) {
log_uart_putc(&stdio_uart_log, (char)c);
return;
}
@@ -367,7 +413,7 @@
int serial_readable(serial_t *obj)
{
#ifdef CONFIG_MBED_ENABLED
- if(obj->index == UART_3){
+ if (obj->index == UART_3) {
return log_uart_readable(&stdio_uart_log);
}
#endif
@@ -385,7 +431,7 @@
int serial_writable(serial_t *obj)
{
#ifdef CONFIG_MBED_ENABLED
- if(obj->index == UART_3){
+ if (obj->index == UART_3) {
return log_uart_writable(&stdio_uart_log);
}
#endif
@@ -393,8 +439,7 @@
PHAL_RUART_ADAPTER pHalRuartAdapter=(PHAL_RUART_ADAPTER)&(obj->hal_uart_adp);
u8 uart_idx = pHalRuartAdapter->UartIndex;
- if (HAL_RUART_READ32(uart_idx, RUART_LINE_STATUS_REG_OFF) &
- (RUART_LINE_STATUS_REG_THRE)) {
+ if (HAL_RUART_READ32(uart_idx, RUART_LINE_STATUS_REG_OFF) & (RUART_LINE_STATUS_REG_THRE)) {
return 1;
} else {
return 0;
@@ -404,7 +449,7 @@
void serial_clear(serial_t *obj)
{
#ifdef CONFIG_MBED_ENABLED
- if(obj->index == UART_3){
+ if (obj->index == UART_3) {
log_uart_clear(&stdio_uart_log);
return;
}
@@ -419,7 +464,7 @@
void serial_break_set(serial_t *obj)
{
#ifdef CONFIG_MBED_ENABLED
- if(obj->index == UART_3){
+ if (obj->index == UART_3) {
log_uart_break_set(&stdio_uart_log);
return;
}
@@ -428,7 +473,6 @@
PHAL_RUART_ADAPTER pHalRuartAdapter=(PHAL_RUART_ADAPTER)&(obj->hal_uart_adp);
u8 uart_idx = pHalRuartAdapter->UartIndex;
u32 RegValue;
-
RegValue = HAL_RUART_READ32(uart_idx, RUART_LINE_CTL_REG_OFF);
RegValue |= BIT_UART_LCR_BREAK_CTRL;
HAL_RUART_WRITE32(uart_idx, RUART_LINE_CTL_REG_OFF, RegValue);
@@ -437,16 +481,14 @@
void serial_break_clear(serial_t *obj)
{
#ifdef CONFIG_MBED_ENABLED
- if(obj->index == UART_3){
+ if (obj->index == UART_3) {
log_uart_break_clear(&stdio_uart_log);
return;
}
#endif
-
PHAL_RUART_ADAPTER pHalRuartAdapter=(PHAL_RUART_ADAPTER)&(obj->hal_uart_adp);
u8 uart_idx = pHalRuartAdapter->UartIndex;
u32 RegValue;
-
RegValue = HAL_RUART_READ32(uart_idx, RUART_LINE_CTL_REG_OFF);
RegValue &= ~(BIT_UART_LCR_BREAK_CTRL);
HAL_RUART_WRITE32(uart_idx, RUART_LINE_CTL_REG_OFF, RegValue);
--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/spi_api.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/spi_api.c Tue Mar 20 16:56:18 2018 +0000 @@ -21,6 +21,10 @@ #include "pinmap.h" #include "hal_ssi.h" +#ifdef CONFIG_MBED_ENABLED +#include "platform_stdlib.h" +#endif + extern u32 SystemGetCpuClk(VOID); extern VOID HAL_GPIO_PullCtrl(u32 pin, u32 mode);
--- a/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/trng_api.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_Realtek/TARGET_AMEBA/TARGET_RTL8195A/trng_api.c Tue Mar 20 16:56:18 2018 +0000 @@ -17,6 +17,10 @@ #include "analogin_api.h" #include "analogin_ext.h" +#ifdef CONFIG_MBED_ENABLED +#include "platform_stdlib.h" +#endif + #ifdef DEVICE_TRNG
--- a/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/api/platform/platform_stdlib.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_Realtek/TARGET_AMEBA/sdk/common/api/platform/platform_stdlib.h Tue Mar 20 16:56:18 2018 +0000 @@ -51,6 +51,7 @@ #include <stdint.h> #include "diag.h" #define strsep(str, delim) _strsep(str, delim) + #define _memset(dst, val, sz) memset(dst, val, sz) #else #include <stdio.h> #include <stdlib.h>
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/TOOLCHAIN_ARM_MICRO/startup_stm32f051x8.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,240 @@ +;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** +;* File Name : startup_stm32f051x8.s +;* Author : MCD Application Team +;* Description : STM32F051x4/STM32F051x6/STM32F051x8 devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM0 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20002000 ; Top of RAM (8 KB for STM32F030R8) + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD TSC_IRQHandler ; TS + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 + DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC + DCD 0 ; Reserved + DCD TIM14_IRQHandler ; TIM14 + DCD TIM15_IRQHandler ; TIM15 + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD I2C1_IRQHandler ; I2C1 + DCD I2C2_IRQHandler ; I2C2 + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD CEC_IRQHandler ; CEC + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT TSC_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_5_IRQHandler [WEAK] + EXPORT ADC1_COMP_IRQHandler [WEAK] + EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM14_IRQHandler [WEAK] + EXPORT TIM15_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + + +WWDG_IRQHandler +PVD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +TSC_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_3_IRQHandler +DMA1_Channel4_5_IRQHandler +ADC1_COMP_IRQHandler +TIM1_BRK_UP_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM6_DAC_IRQHandler +TIM14_IRQHandler +TIM15_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +CEC_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/TOOLCHAIN_ARM_MICRO/startup_stm32f051x8.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,240 +0,0 @@ -;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** -;* File Name : startup_stm32f051x8.s -;* Author : MCD Application Team -;* Description : STM32F051x4/STM32F051x6/STM32F051x8 devices vector table for MDK-ARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM0 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;******************************************************************************* - -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; <h> Stack Configuration -; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; </h> - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 - EXPORT __initial_sp - -Stack_Mem SPACE Stack_Size -__initial_sp EQU 0x20002000 ; Top of RAM (8 KB for STM32F030R8) - - -; <h> Heap Configuration -; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; </h> - -Heap_Size EQU 0x00000400 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 - EXPORT __heap_base - EXPORT __heap_limit - -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit EQU (__initial_sp - Stack_Size) - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_IRQHandler ; PVD through EXTI Line detect - DCD RTC_IRQHandler ; RTC through EXTI Line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 - DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 - DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 - DCD TSC_IRQHandler ; TS - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 - DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 - DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2 - DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC - DCD 0 ; Reserved - DCD TIM14_IRQHandler ; TIM14 - DCD TIM15_IRQHandler ; TIM15 - DCD TIM16_IRQHandler ; TIM16 - DCD TIM17_IRQHandler ; TIM17 - DCD I2C1_IRQHandler ; I2C1 - DCD I2C2_IRQHandler ; I2C2 - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD 0 ; Reserved - DCD CEC_IRQHandler ; CEC - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler routine -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - IMPORT SystemInit - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_1_IRQHandler [WEAK] - EXPORT EXTI2_3_IRQHandler [WEAK] - EXPORT EXTI4_15_IRQHandler [WEAK] - EXPORT TSC_IRQHandler [WEAK] - EXPORT DMA1_Channel1_IRQHandler [WEAK] - EXPORT DMA1_Channel2_3_IRQHandler [WEAK] - EXPORT DMA1_Channel4_5_IRQHandler [WEAK] - EXPORT ADC1_COMP_IRQHandler [WEAK] - EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM6_DAC_IRQHandler [WEAK] - EXPORT TIM14_IRQHandler [WEAK] - EXPORT TIM15_IRQHandler [WEAK] - EXPORT TIM16_IRQHandler [WEAK] - EXPORT TIM17_IRQHandler [WEAK] - EXPORT I2C1_IRQHandler [WEAK] - EXPORT I2C2_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT CEC_IRQHandler [WEAK] - - -WWDG_IRQHandler -PVD_IRQHandler -RTC_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_1_IRQHandler -EXTI2_3_IRQHandler -EXTI4_15_IRQHandler -TSC_IRQHandler -DMA1_Channel1_IRQHandler -DMA1_Channel2_3_IRQHandler -DMA1_Channel4_5_IRQHandler -ADC1_COMP_IRQHandler -TIM1_BRK_UP_TRG_COM_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM6_DAC_IRQHandler -TIM14_IRQHandler -TIM15_IRQHandler -TIM16_IRQHandler -TIM17_IRQHandler -I2C1_IRQHandler -I2C2_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -CEC_IRQHandler - - B . - - ENDP - - ALIGN - END - -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/TOOLCHAIN_ARM_STD/startup_stm32f051x8.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,215 @@ +;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** +;* File Name : startup_stm32f051x8.s +;* Author : MCD Application Team +;* Description : STM32F051x4/STM32F051x6/STM32F051x8 devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM0 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + + + +__initial_sp EQU 0x20002000 ; Top of RAM (8 KB for STM32F030R8) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD TSC_IRQHandler ; TS + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 + DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC + DCD 0 ; Reserved + DCD TIM14_IRQHandler ; TIM14 + DCD TIM15_IRQHandler ; TIM15 + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD I2C1_IRQHandler ; I2C1 + DCD I2C2_IRQHandler ; I2C2 + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD CEC_IRQHandler ; CEC + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT TSC_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_5_IRQHandler [WEAK] + EXPORT ADC1_COMP_IRQHandler [WEAK] + EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM14_IRQHandler [WEAK] + EXPORT TIM15_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT I2C2_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + + +WWDG_IRQHandler +PVD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +TSC_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_3_IRQHandler +DMA1_Channel4_5_IRQHandler +ADC1_COMP_IRQHandler +TIM1_BRK_UP_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM6_DAC_IRQHandler +TIM14_IRQHandler +TIM15_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +I2C1_IRQHandler +I2C2_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +CEC_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_DISCO_F051R8/device/TOOLCHAIN_ARM_STD/startup_stm32f051x8.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,215 +0,0 @@ -;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** -;* File Name : startup_stm32f051x8.s -;* Author : MCD Application Team -;* Description : STM32F051x4/STM32F051x6/STM32F051x8 devices vector table for MDK-ARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM0 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;******************************************************************************* - - - -__initial_sp EQU 0x20002000 ; Top of RAM (8 KB for STM32F030R8) - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_IRQHandler ; PVD through EXTI Line detect - DCD RTC_IRQHandler ; RTC through EXTI Line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 - DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 - DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 - DCD TSC_IRQHandler ; TS - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 - DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 - DCD ADC1_COMP_IRQHandler ; ADC1, COMP1 and COMP2 - DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC - DCD 0 ; Reserved - DCD TIM14_IRQHandler ; TIM14 - DCD TIM15_IRQHandler ; TIM15 - DCD TIM16_IRQHandler ; TIM16 - DCD TIM17_IRQHandler ; TIM17 - DCD I2C1_IRQHandler ; I2C1 - DCD I2C2_IRQHandler ; I2C2 - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD 0 ; Reserved - DCD CEC_IRQHandler ; CEC - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler routine -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - IMPORT SystemInit - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_1_IRQHandler [WEAK] - EXPORT EXTI2_3_IRQHandler [WEAK] - EXPORT EXTI4_15_IRQHandler [WEAK] - EXPORT TSC_IRQHandler [WEAK] - EXPORT DMA1_Channel1_IRQHandler [WEAK] - EXPORT DMA1_Channel2_3_IRQHandler [WEAK] - EXPORT DMA1_Channel4_5_IRQHandler [WEAK] - EXPORT ADC1_COMP_IRQHandler [WEAK] - EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM6_DAC_IRQHandler [WEAK] - EXPORT TIM14_IRQHandler [WEAK] - EXPORT TIM15_IRQHandler [WEAK] - EXPORT TIM16_IRQHandler [WEAK] - EXPORT TIM17_IRQHandler [WEAK] - EXPORT I2C1_IRQHandler [WEAK] - EXPORT I2C2_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT CEC_IRQHandler [WEAK] - - -WWDG_IRQHandler -PVD_IRQHandler -RTC_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_1_IRQHandler -EXTI2_3_IRQHandler -EXTI4_15_IRQHandler -TSC_IRQHandler -DMA1_Channel1_IRQHandler -DMA1_Channel2_3_IRQHandler -DMA1_Channel4_5_IRQHandler -ADC1_COMP_IRQHandler -TIM1_BRK_UP_TRG_COM_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM6_DAC_IRQHandler -TIM14_IRQHandler -TIM15_IRQHandler -TIM16_IRQHandler -TIM17_IRQHandler -I2C1_IRQHandler -I2C2_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -CEC_IRQHandler - - B . - - ENDP - - ALIGN - END - -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_ARM_MICRO/startup_stm32f031x6.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,224 @@ +;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** +;* File Name : startup_stm32f031x6.s +;* Author : MCD Application Team +;* Description : STM32F031x4/STM32F031x6 devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM0 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20001000 ; Top of RAM + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD 0 ; Reserved + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 + DCD ADC1_IRQHandler ; ADC1 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM14_IRQHandler ; TIM14 + DCD 0 ; Reserved + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD I2C1_IRQHandler ; I2C1 + DCD 0 ; Reserved + DCD SPI1_IRQHandler ; SPI1 + DCD 0 ; Reserved + DCD USART1_IRQHandler ; USART1 + + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_5_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM14_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + + +WWDG_IRQHandler +PVD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_3_IRQHandler +DMA1_Channel4_5_IRQHandler +ADC1_IRQHandler +TIM1_BRK_UP_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM14_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +I2C1_IRQHandler +SPI1_IRQHandler +USART1_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_ARM_MICRO/startup_stm32f031x6.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,224 +0,0 @@ -;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** -;* File Name : startup_stm32f031x6.s -;* Author : MCD Application Team -;* Description : STM32F031x4/STM32F031x6 devices vector table for MDK-ARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM0 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;******************************************************************************* - -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; <h> Stack Configuration -; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; </h> - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 - EXPORT __initial_sp - -Stack_Mem SPACE Stack_Size -__initial_sp EQU 0x20001000 ; Top of RAM - - -; <h> Heap Configuration -; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; </h> - -Heap_Size EQU 0x00000400 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 - EXPORT __heap_base - EXPORT __heap_limit - -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit EQU (__initial_sp - Stack_Size) - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_IRQHandler ; PVD through EXTI Line detect - DCD RTC_IRQHandler ; RTC through EXTI Line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 - DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 - DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 - DCD 0 ; Reserved - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 - DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 - DCD ADC1_IRQHandler ; ADC1 - DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD TIM14_IRQHandler ; TIM14 - DCD 0 ; Reserved - DCD TIM16_IRQHandler ; TIM16 - DCD TIM17_IRQHandler ; TIM17 - DCD I2C1_IRQHandler ; I2C1 - DCD 0 ; Reserved - DCD SPI1_IRQHandler ; SPI1 - DCD 0 ; Reserved - DCD USART1_IRQHandler ; USART1 - - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler routine -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - IMPORT SystemInit - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_1_IRQHandler [WEAK] - EXPORT EXTI2_3_IRQHandler [WEAK] - EXPORT EXTI4_15_IRQHandler [WEAK] - EXPORT DMA1_Channel1_IRQHandler [WEAK] - EXPORT DMA1_Channel2_3_IRQHandler [WEAK] - EXPORT DMA1_Channel4_5_IRQHandler [WEAK] - EXPORT ADC1_IRQHandler [WEAK] - EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM14_IRQHandler [WEAK] - EXPORT TIM16_IRQHandler [WEAK] - EXPORT TIM17_IRQHandler [WEAK] - EXPORT I2C1_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - - -WWDG_IRQHandler -PVD_IRQHandler -RTC_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_1_IRQHandler -EXTI2_3_IRQHandler -EXTI4_15_IRQHandler -DMA1_Channel1_IRQHandler -DMA1_Channel2_3_IRQHandler -DMA1_Channel4_5_IRQHandler -ADC1_IRQHandler -TIM1_BRK_UP_TRG_COM_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM14_IRQHandler -TIM16_IRQHandler -TIM17_IRQHandler -I2C1_IRQHandler -SPI1_IRQHandler -USART1_IRQHandler - - B . - - ENDP - - ALIGN - END - -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_ARM_STD/startup_stm32f031x6.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,197 @@ +;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** +;* File Name : startup_stm32f031x6.s +;* Author : MCD Application Team +;* Description : STM32F031x4/STM32F031x6 devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM0 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +__initial_sp EQU 0x20001000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD 0 ; Reserved + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 + DCD ADC1_IRQHandler ; ADC1 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM14_IRQHandler ; TIM14 + DCD 0 ; Reserved + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD I2C1_IRQHandler ; I2C1 + DCD 0 ; Reserved + DCD SPI1_IRQHandler ; SPI1 + DCD 0 ; Reserved + DCD USART1_IRQHandler ; USART1 + + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_5_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM14_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + + +WWDG_IRQHandler +PVD_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_3_IRQHandler +DMA1_Channel4_5_IRQHandler +ADC1_IRQHandler +TIM1_BRK_UP_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM14_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +I2C1_IRQHandler +SPI1_IRQHandler +USART1_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_ARM_STD/startup_stm32f031x6.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,197 +0,0 @@ -;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** -;* File Name : startup_stm32f031x6.s -;* Author : MCD Application Team -;* Description : STM32F031x4/STM32F031x6 devices vector table for MDK-ARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM0 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;******************************************************************************* - -__initial_sp EQU 0x20001000 ; Top of RAM - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_IRQHandler ; PVD through EXTI Line detect - DCD RTC_IRQHandler ; RTC through EXTI Line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 - DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 - DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 - DCD 0 ; Reserved - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 - DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 - DCD ADC1_IRQHandler ; ADC1 - DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD TIM14_IRQHandler ; TIM14 - DCD 0 ; Reserved - DCD TIM16_IRQHandler ; TIM16 - DCD TIM17_IRQHandler ; TIM17 - DCD I2C1_IRQHandler ; I2C1 - DCD 0 ; Reserved - DCD SPI1_IRQHandler ; SPI1 - DCD 0 ; Reserved - DCD USART1_IRQHandler ; USART1 - - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler routine -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - IMPORT SystemInit - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_1_IRQHandler [WEAK] - EXPORT EXTI2_3_IRQHandler [WEAK] - EXPORT EXTI4_15_IRQHandler [WEAK] - EXPORT DMA1_Channel1_IRQHandler [WEAK] - EXPORT DMA1_Channel2_3_IRQHandler [WEAK] - EXPORT DMA1_Channel4_5_IRQHandler [WEAK] - EXPORT ADC1_IRQHandler [WEAK] - EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM14_IRQHandler [WEAK] - EXPORT TIM16_IRQHandler [WEAK] - EXPORT TIM17_IRQHandler [WEAK] - EXPORT I2C1_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - - -WWDG_IRQHandler -PVD_IRQHandler -RTC_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_1_IRQHandler -EXTI2_3_IRQHandler -EXTI4_15_IRQHandler -DMA1_Channel1_IRQHandler -DMA1_Channel2_3_IRQHandler -DMA1_Channel4_5_IRQHandler -ADC1_IRQHandler -TIM1_BRK_UP_TRG_COM_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM14_IRQHandler -TIM16_IRQHandler -TIM17_IRQHandler -I2C1_IRQHandler -SPI1_IRQHandler -USART1_IRQHandler - - B . - - ENDP - - ALIGN - END - -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_GCC_ARM/startup_stm32f031x6.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,277 @@ +/** + ****************************************************************************** + * @file startup_stm32f031x6.s + * @author MCD Application Team + * @brief STM32F031x4/STM32F031x6 devices vector table for GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M0 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit + +/* Call the application's entry point.*/ +// bl main + bl _start + +LoopForever: + b LoopForever + + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detect */ + .word RTC_IRQHandler /* RTC through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ + .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ + .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ + .word 0 /* Reserved */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ + .word DMA1_Channel4_5_IRQHandler /* DMA1 Channel 4 and Channel 5 */ + .word ADC1_IRQHandler /* ADC1 */ + .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word TIM14_IRQHandler /* TIM14 */ + .word 0 /* Reserved */ + .word TIM16_IRQHandler /* TIM16 */ + .word TIM17_IRQHandler /* TIM17 */ + .word I2C1_IRQHandler /* I2C1 */ + .word 0 /* Reserved */ + .word SPI1_IRQHandler /* SPI1 */ + .word 0 /* Reserved */ + .word USART1_IRQHandler /* USART1 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_1_IRQHandler + .thumb_set EXTI0_1_IRQHandler,Default_Handler + + .weak EXTI2_3_IRQHandler + .thumb_set EXTI2_3_IRQHandler,Default_Handler + + .weak EXTI4_15_IRQHandler + .thumb_set EXTI4_15_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_3_IRQHandler + .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_5_IRQHandler + .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak TIM1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_GCC_ARM/startup_stm32f031x6.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,277 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32f031x6.s - * @author MCD Application Team - * @brief STM32F031x4/STM32F031x6 devices vector table for GCC toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M0 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m0 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - ldr r0, =_estack - mov sp, r0 /* set stack pointer */ - -/* Copy the data segment initializers from flash to SRAM */ - ldr r0, =_sdata - ldr r1, =_edata - ldr r2, =_sidata - movs r3, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r4, [r2, r3] - str r4, [r0, r3] - adds r3, r3, #4 - -LoopCopyDataInit: - adds r4, r0, r3 - cmp r4, r1 - bcc CopyDataInit - -/* Zero fill the bss segment. */ - ldr r2, =_sbss - ldr r4, =_ebss - movs r3, #0 - b LoopFillZerobss - -FillZerobss: - str r3, [r2] - adds r2, r2, #4 - -LoopFillZerobss: - cmp r2, r4 - bcc FillZerobss - -/* Call the clock system intitialization function.*/ - bl SystemInit - -/* Call the application's entry point.*/ -// bl main - bl _start - -LoopForever: - b LoopForever - - -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * - * @param None - * @retval : None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M0. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word 0 - .word 0 - .word PendSV_Handler - .word SysTick_Handler - .word WWDG_IRQHandler /* Window WatchDog */ - .word PVD_IRQHandler /* PVD through EXTI Line detect */ - .word RTC_IRQHandler /* RTC through the EXTI line */ - .word FLASH_IRQHandler /* FLASH */ - .word RCC_IRQHandler /* RCC */ - .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ - .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ - .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ - .word 0 /* Reserved */ - .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ - .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ - .word DMA1_Channel4_5_IRQHandler /* DMA1 Channel 4 and Channel 5 */ - .word ADC1_IRQHandler /* ADC1 */ - .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ - .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ - .word TIM2_IRQHandler /* TIM2 */ - .word TIM3_IRQHandler /* TIM3 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word TIM14_IRQHandler /* TIM14 */ - .word 0 /* Reserved */ - .word TIM16_IRQHandler /* TIM16 */ - .word TIM17_IRQHandler /* TIM17 */ - .word I2C1_IRQHandler /* I2C1 */ - .word 0 /* Reserved */ - .word SPI1_IRQHandler /* SPI1 */ - .word 0 /* Reserved */ - .word USART1_IRQHandler /* USART1 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak RTC_IRQHandler - .thumb_set RTC_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_1_IRQHandler - .thumb_set EXTI0_1_IRQHandler,Default_Handler - - .weak EXTI2_3_IRQHandler - .thumb_set EXTI2_3_IRQHandler,Default_Handler - - .weak EXTI4_15_IRQHandler - .thumb_set EXTI4_15_IRQHandler,Default_Handler - - .weak DMA1_Channel1_IRQHandler - .thumb_set DMA1_Channel1_IRQHandler,Default_Handler - - .weak DMA1_Channel2_3_IRQHandler - .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler - - .weak DMA1_Channel4_5_IRQHandler - .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler - - .weak ADC1_IRQHandler - .thumb_set ADC1_IRQHandler,Default_Handler - - .weak TIM1_BRK_UP_TRG_COM_IRQHandler - .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM14_IRQHandler - .thumb_set TIM14_IRQHandler,Default_Handler - - .weak TIM16_IRQHandler - .thumb_set TIM16_IRQHandler,Default_Handler - - .weak TIM17_IRQHandler - .thumb_set TIM17_IRQHandler,Default_Handler - - .weak I2C1_IRQHandler - .thumb_set I2C1_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ -
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_IAR/startup_stm32f031x6.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,268 @@ +;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** +;* File Name : startup_stm32f031x6.s +;* Author : MCD Application Team +;* Description : STM32F031x4/STM32F031x6 devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address, +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M0 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************* +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_IRQHandler ; PVD through EXTI Line detect + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD 0 ; Reserved + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 + DCD ADC1_IRQHandler ; ADC1 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM14_IRQHandler ; TIM14 + DCD 0 ; Reserved + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD I2C1_IRQHandler ; I2C1 + DCD 0 ; Reserved + DCD SPI1_IRQHandler ; SPI1 + DCD 0 ; Reserved + DCD USART1_IRQHandler ; USART1 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_1_IRQHandler + B EXTI0_1_IRQHandler + + PUBWEAK EXTI2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_3_IRQHandler + B EXTI2_3_IRQHandler + + PUBWEAK EXTI4_15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_15_IRQHandler + B EXTI4_15_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_3_IRQHandler + B DMA1_Channel2_3_IRQHandler + + PUBWEAK DMA1_Channel4_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel4_5_IRQHandler + B DMA1_Channel4_5_IRQHandler + + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_IRQHandler + B ADC1_IRQHandler + + PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_UP_TRG_COM_IRQHandler + B TIM1_BRK_UP_TRG_COM_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM14_IRQHandler + B TIM14_IRQHandler + + PUBWEAK TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_IRQHandler + B TIM16_IRQHandler + + PUBWEAK TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM17_IRQHandler + B TIM17_IRQHandler + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + + END +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F031K6/device/TOOLCHAIN_IAR/startup_stm32f031x6.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,268 +0,0 @@ -;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** -;* File Name : startup_stm32f031x6.s -;* Author : MCD Application Team -;* Description : STM32F031x4/STM32F031x6 devices vector table for EWARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == __iar_program_start, -;* - Set the vector table entries with the exceptions ISR -;* address, -;* - Branches to main in the C library (which eventually -;* calls main()). -;* After Reset the Cortex-M0 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;******************************************************************************* -;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;* -;******************************************************************************* -; -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler ; Reset Handler - - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_IRQHandler ; PVD through EXTI Line detect - DCD RTC_IRQHandler ; RTC through EXTI Line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 - DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 - DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 - DCD 0 ; Reserved - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 - DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 - DCD ADC1_IRQHandler ; ADC1 - DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD TIM14_IRQHandler ; TIM14 - DCD 0 ; Reserved - DCD TIM16_IRQHandler ; TIM16 - DCD TIM17_IRQHandler ; TIM17 - DCD I2C1_IRQHandler ; I2C1 - DCD 0 ; Reserved - DCD SPI1_IRQHandler ; SPI1 - DCD 0 ; Reserved - DCD USART1_IRQHandler ; USART1 - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:NOROOT:REORDER(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SVC_Handler - B SVC_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK WWDG_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -WWDG_IRQHandler - B WWDG_IRQHandler - - PUBWEAK PVD_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -PVD_IRQHandler - B PVD_IRQHandler - - PUBWEAK RTC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_IRQHandler - B RTC_IRQHandler - - PUBWEAK FLASH_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FLASH_IRQHandler - B FLASH_IRQHandler - - PUBWEAK RCC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RCC_IRQHandler - B RCC_IRQHandler - - PUBWEAK EXTI0_1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI0_1_IRQHandler - B EXTI0_1_IRQHandler - - PUBWEAK EXTI2_3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI2_3_IRQHandler - B EXTI2_3_IRQHandler - - PUBWEAK EXTI4_15_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI4_15_IRQHandler - B EXTI4_15_IRQHandler - - PUBWEAK DMA1_Channel1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel1_IRQHandler - B DMA1_Channel1_IRQHandler - - PUBWEAK DMA1_Channel2_3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel2_3_IRQHandler - B DMA1_Channel2_3_IRQHandler - - PUBWEAK DMA1_Channel4_5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel4_5_IRQHandler - B DMA1_Channel4_5_IRQHandler - - PUBWEAK ADC1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ADC1_IRQHandler - B ADC1_IRQHandler - - PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_BRK_UP_TRG_COM_IRQHandler - B TIM1_BRK_UP_TRG_COM_IRQHandler - - PUBWEAK TIM1_CC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_CC_IRQHandler - B TIM1_CC_IRQHandler - - PUBWEAK TIM2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM2_IRQHandler - B TIM2_IRQHandler - - PUBWEAK TIM3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM3_IRQHandler - B TIM3_IRQHandler - - PUBWEAK TIM14_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM14_IRQHandler - B TIM14_IRQHandler - - PUBWEAK TIM16_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM16_IRQHandler - B TIM16_IRQHandler - - PUBWEAK TIM17_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM17_IRQHandler - B TIM17_IRQHandler - - PUBWEAK I2C1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_IRQHandler - B I2C1_IRQHandler - - PUBWEAK SPI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI1_IRQHandler - B SPI1_IRQHandler - - PUBWEAK USART1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART1_IRQHandler - B USART1_IRQHandler - - - END -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_ARM_MICRO/startup_stm32f042x6.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,265 @@ +;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** +;* File Name : startup_stm32f042x6.s +;* Author : MCD Application Team +;* Description : STM32F042x4/STM32F042x6 devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM0 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20001800 ; Top of RAM + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_VDDIO2_IRQHandler ; PVD through EXTI Line detect + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_CRS_IRQHandler ; RCC and CRS + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD TSC_IRQHandler ; TS + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 + DCD ADC1_IRQHandler ; ADC1 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM14_IRQHandler ; TIM14 + DCD 0 ; Reserved + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD I2C1_IRQHandler ; I2C1 + DCD 0 ; Reserved + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD CEC_CAN_IRQHandler ; CEC and CAN + DCD USB_IRQHandler ; USB + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + + + + LDR R0, =__initial_sp ; set stack pointer + MSR MSP, R0 + +;;Check if boot space corresponds to test memory + + LDR R0,=0x00000004 + LDR R1, [R0] + LSRS R1, R1, #24 + LDR R2,=0x1F + CMP R1, R2 + + BNE ApplicationStart + +;; SYSCFG clock enable + + LDR R0,=0x40021018 + LDR R1,=0x00000001 + STR R1, [R0] + +;; Set CFGR1 register with flash memory remap at address 0 + + LDR R0,=0x40010000 + LDR R1,=0x00000000 + STR R1, [R0] +ApplicationStart + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_VDDIO2_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_CRS_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT TSC_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_5_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM14_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT CEC_CAN_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + + +WWDG_IRQHandler +PVD_VDDIO2_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_CRS_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +TSC_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_3_IRQHandler +DMA1_Channel4_5_IRQHandler +ADC1_IRQHandler +TIM1_BRK_UP_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM14_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +I2C1_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +CEC_CAN_IRQHandler +USB_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_ARM_MICRO/startup_stm32f042x6.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,265 +0,0 @@ -;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** -;* File Name : startup_stm32f042x6.s -;* Author : MCD Application Team -;* Description : STM32F042x4/STM32F042x6 devices vector table for MDK-ARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM0 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;******************************************************************************* - -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; <h> Stack Configuration -; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; </h> - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 - EXPORT __initial_sp - -Stack_Mem SPACE Stack_Size -__initial_sp EQU 0x20001800 ; Top of RAM - - -; <h> Heap Configuration -; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; </h> - -Heap_Size EQU 0x00000200 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 - EXPORT __heap_base - EXPORT __heap_limit - -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit EQU (__initial_sp - Stack_Size) - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_VDDIO2_IRQHandler ; PVD through EXTI Line detect - DCD RTC_IRQHandler ; RTC through EXTI Line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_CRS_IRQHandler ; RCC and CRS - DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 - DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 - DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 - DCD TSC_IRQHandler ; TS - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 - DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 - DCD ADC1_IRQHandler ; ADC1 - DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD TIM14_IRQHandler ; TIM14 - DCD 0 ; Reserved - DCD TIM16_IRQHandler ; TIM16 - DCD TIM17_IRQHandler ; TIM17 - DCD I2C1_IRQHandler ; I2C1 - DCD 0 ; Reserved - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD 0 ; Reserved - DCD CEC_CAN_IRQHandler ; CEC and CAN - DCD USB_IRQHandler ; USB - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler routine -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - IMPORT SystemInit - - - - LDR R0, =__initial_sp ; set stack pointer - MSR MSP, R0 - -;;Check if boot space corresponds to test memory - - LDR R0,=0x00000004 - LDR R1, [R0] - LSRS R1, R1, #24 - LDR R2,=0x1F - CMP R1, R2 - - BNE ApplicationStart - -;; SYSCFG clock enable - - LDR R0,=0x40021018 - LDR R1,=0x00000001 - STR R1, [R0] - -;; Set CFGR1 register with flash memory remap at address 0 - - LDR R0,=0x40010000 - LDR R1,=0x00000000 - STR R1, [R0] -ApplicationStart - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_VDDIO2_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_CRS_IRQHandler [WEAK] - EXPORT EXTI0_1_IRQHandler [WEAK] - EXPORT EXTI2_3_IRQHandler [WEAK] - EXPORT EXTI4_15_IRQHandler [WEAK] - EXPORT TSC_IRQHandler [WEAK] - EXPORT DMA1_Channel1_IRQHandler [WEAK] - EXPORT DMA1_Channel2_3_IRQHandler [WEAK] - EXPORT DMA1_Channel4_5_IRQHandler [WEAK] - EXPORT ADC1_IRQHandler [WEAK] - EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM14_IRQHandler [WEAK] - EXPORT TIM16_IRQHandler [WEAK] - EXPORT TIM17_IRQHandler [WEAK] - EXPORT I2C1_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT CEC_CAN_IRQHandler [WEAK] - EXPORT USB_IRQHandler [WEAK] - - -WWDG_IRQHandler -PVD_VDDIO2_IRQHandler -RTC_IRQHandler -FLASH_IRQHandler -RCC_CRS_IRQHandler -EXTI0_1_IRQHandler -EXTI2_3_IRQHandler -EXTI4_15_IRQHandler -TSC_IRQHandler -DMA1_Channel1_IRQHandler -DMA1_Channel2_3_IRQHandler -DMA1_Channel4_5_IRQHandler -ADC1_IRQHandler -TIM1_BRK_UP_TRG_COM_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM14_IRQHandler -TIM16_IRQHandler -TIM17_IRQHandler -I2C1_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -CEC_CAN_IRQHandler -USB_IRQHandler - - B . - - ENDP - - ALIGN - END - -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_ARM_STD/startup_stm32f042x6.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,238 @@ +;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** +;* File Name : startup_stm32f042x6.s +;* Author : MCD Application Team +;* Description : STM32F042x4/STM32F042x6 devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM0 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +__initial_sp EQU 0x20001800 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_VDDIO2_IRQHandler ; PVD through EXTI Line detect + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_CRS_IRQHandler ; RCC and CRS + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD TSC_IRQHandler ; TS + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 + DCD ADC1_IRQHandler ; ADC1 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM14_IRQHandler ; TIM14 + DCD 0 ; Reserved + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD I2C1_IRQHandler ; I2C1 + DCD 0 ; Reserved + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD CEC_CAN_IRQHandler ; CEC and CAN + DCD USB_IRQHandler ; USB + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler routine +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT __main + IMPORT SystemInit + + + + LDR R0, =__initial_sp ; set stack pointer + MSR MSP, R0 + +;;Check if boot space corresponds to test memory + + LDR R0,=0x00000004 + LDR R1, [R0] + LSRS R1, R1, #24 + LDR R2,=0x1F + CMP R1, R2 + + BNE ApplicationStart + +;; SYSCFG clock enable + + LDR R0,=0x40021018 + LDR R1,=0x00000001 + STR R1, [R0] + +;; Set CFGR1 register with flash memory remap at address 0 + + LDR R0,=0x40010000 + LDR R1,=0x00000000 + STR R1, [R0] +ApplicationStart + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_VDDIO2_IRQHandler [WEAK] + EXPORT RTC_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_CRS_IRQHandler [WEAK] + EXPORT EXTI0_1_IRQHandler [WEAK] + EXPORT EXTI2_3_IRQHandler [WEAK] + EXPORT EXTI4_15_IRQHandler [WEAK] + EXPORT TSC_IRQHandler [WEAK] + EXPORT DMA1_Channel1_IRQHandler [WEAK] + EXPORT DMA1_Channel2_3_IRQHandler [WEAK] + EXPORT DMA1_Channel4_5_IRQHandler [WEAK] + EXPORT ADC1_IRQHandler [WEAK] + EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM14_IRQHandler [WEAK] + EXPORT TIM16_IRQHandler [WEAK] + EXPORT TIM17_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT CEC_CAN_IRQHandler [WEAK] + EXPORT USB_IRQHandler [WEAK] + + +WWDG_IRQHandler +PVD_VDDIO2_IRQHandler +RTC_IRQHandler +FLASH_IRQHandler +RCC_CRS_IRQHandler +EXTI0_1_IRQHandler +EXTI2_3_IRQHandler +EXTI4_15_IRQHandler +TSC_IRQHandler +DMA1_Channel1_IRQHandler +DMA1_Channel2_3_IRQHandler +DMA1_Channel4_5_IRQHandler +ADC1_IRQHandler +TIM1_BRK_UP_TRG_COM_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM14_IRQHandler +TIM16_IRQHandler +TIM17_IRQHandler +I2C1_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +CEC_CAN_IRQHandler +USB_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_ARM_STD/startup_stm32f042x6.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,238 +0,0 @@ -;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** -;* File Name : startup_stm32f042x6.s -;* Author : MCD Application Team -;* Description : STM32F042x4/STM32F042x6 devices vector table for MDK-ARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM0 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;******************************************************************************* - -__initial_sp EQU 0x20001800 ; Top of RAM - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_VDDIO2_IRQHandler ; PVD through EXTI Line detect - DCD RTC_IRQHandler ; RTC through EXTI Line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_CRS_IRQHandler ; RCC and CRS - DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 - DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 - DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 - DCD TSC_IRQHandler ; TS - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 - DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 - DCD ADC1_IRQHandler ; ADC1 - DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD TIM14_IRQHandler ; TIM14 - DCD 0 ; Reserved - DCD TIM16_IRQHandler ; TIM16 - DCD TIM17_IRQHandler ; TIM17 - DCD I2C1_IRQHandler ; I2C1 - DCD 0 ; Reserved - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD 0 ; Reserved - DCD CEC_CAN_IRQHandler ; CEC and CAN - DCD USB_IRQHandler ; USB - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler routine -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT __main - IMPORT SystemInit - - - - LDR R0, =__initial_sp ; set stack pointer - MSR MSP, R0 - -;;Check if boot space corresponds to test memory - - LDR R0,=0x00000004 - LDR R1, [R0] - LSRS R1, R1, #24 - LDR R2,=0x1F - CMP R1, R2 - - BNE ApplicationStart - -;; SYSCFG clock enable - - LDR R0,=0x40021018 - LDR R1,=0x00000001 - STR R1, [R0] - -;; Set CFGR1 register with flash memory remap at address 0 - - LDR R0,=0x40010000 - LDR R1,=0x00000000 - STR R1, [R0] -ApplicationStart - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_VDDIO2_IRQHandler [WEAK] - EXPORT RTC_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_CRS_IRQHandler [WEAK] - EXPORT EXTI0_1_IRQHandler [WEAK] - EXPORT EXTI2_3_IRQHandler [WEAK] - EXPORT EXTI4_15_IRQHandler [WEAK] - EXPORT TSC_IRQHandler [WEAK] - EXPORT DMA1_Channel1_IRQHandler [WEAK] - EXPORT DMA1_Channel2_3_IRQHandler [WEAK] - EXPORT DMA1_Channel4_5_IRQHandler [WEAK] - EXPORT ADC1_IRQHandler [WEAK] - EXPORT TIM1_BRK_UP_TRG_COM_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM14_IRQHandler [WEAK] - EXPORT TIM16_IRQHandler [WEAK] - EXPORT TIM17_IRQHandler [WEAK] - EXPORT I2C1_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT CEC_CAN_IRQHandler [WEAK] - EXPORT USB_IRQHandler [WEAK] - - -WWDG_IRQHandler -PVD_VDDIO2_IRQHandler -RTC_IRQHandler -FLASH_IRQHandler -RCC_CRS_IRQHandler -EXTI0_1_IRQHandler -EXTI2_3_IRQHandler -EXTI4_15_IRQHandler -TSC_IRQHandler -DMA1_Channel1_IRQHandler -DMA1_Channel2_3_IRQHandler -DMA1_Channel4_5_IRQHandler -ADC1_IRQHandler -TIM1_BRK_UP_TRG_COM_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM14_IRQHandler -TIM16_IRQHandler -TIM17_IRQHandler -I2C1_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -CEC_CAN_IRQHandler -USB_IRQHandler - - B . - - ENDP - - ALIGN - END - -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_GCC_ARM/startup_stm32f042x6.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,322 @@ +/** + ****************************************************************************** + * @file startup_stm32f042x6.s + * @author MCD Application Team + * @brief STM32F042x4/STM32F042x6 devices vector table for GCC toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M0 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr r0, =_estack + mov sp, r0 /* set stack pointer */ + +/*Check if boot space corresponds to test memory*/ + + LDR R0,=0x00000004 + LDR R1, [R0] + LSRS R1, R1, #24 + LDR R2,=0x1F + CMP R1, R2 + BNE ApplicationStart + + /*SYSCFG clock enable*/ + + LDR R0,=0x40021018 + LDR R1,=0x00000001 + STR R1, [R0] + +/*Set CFGR1 register with flash memory remap at address 0*/ + LDR R0,=0x40010000 + LDR R1,=0x00000000 + STR R1, [R0] + +ApplicationStart: +/* Copy the data segment initializers from flash to SRAM */ + ldr r0, =_sdata + ldr r1, =_edata + ldr r2, =_sidata + movs r3, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r4, [r2, r3] + str r4, [r0, r3] + adds r3, r3, #4 + +LoopCopyDataInit: + adds r4, r0, r3 + cmp r4, r1 + bcc CopyDataInit + +/* Zero fill the bss segment. */ + ldr r2, =_sbss + ldr r4, =_ebss + movs r3, #0 + b LoopFillZerobss + +FillZerobss: + str r3, [r2] + adds r2, r2, #4 + +LoopFillZerobss: + cmp r2, r4 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit + +/* Call the application's entry point.*/ +// bl main + bl _start + +LoopForever: + b LoopForever + + +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * + * @param None + * @retval : None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M0. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_VDDIO2_IRQHandler /* PVD and VDDIO2 through EXTI Line detect */ + .word RTC_IRQHandler /* RTC through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_CRS_IRQHandler /* RCC and CRS */ + .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ + .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ + .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ + .word TSC_IRQHandler /* TSC */ + .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ + .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ + .word DMA1_Channel4_5_IRQHandler /* DMA1 Channel 4 and Channel 5 */ + .word ADC1_IRQHandler /* ADC1 */ + .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word TIM14_IRQHandler /* TIM14 */ + .word 0 /* Reserved */ + .word TIM16_IRQHandler /* TIM16 */ + .word TIM17_IRQHandler /* TIM17 */ + .word I2C1_IRQHandler /* I2C1 */ + .word 0 /* Reserved */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word 0 /* Reserved */ + .word CEC_CAN_IRQHandler /* CEC and CAN */ + .word USB_IRQHandler /* USB */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_VDDIO2_IRQHandler + .thumb_set PVD_VDDIO2_IRQHandler,Default_Handler + + .weak RTC_IRQHandler + .thumb_set RTC_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_CRS_IRQHandler + .thumb_set RCC_CRS_IRQHandler,Default_Handler + + .weak EXTI0_1_IRQHandler + .thumb_set EXTI0_1_IRQHandler,Default_Handler + + .weak EXTI2_3_IRQHandler + .thumb_set EXTI2_3_IRQHandler,Default_Handler + + .weak EXTI4_15_IRQHandler + .thumb_set EXTI4_15_IRQHandler,Default_Handler + + .weak TSC_IRQHandler + .thumb_set TSC_IRQHandler,Default_Handler + + .weak DMA1_Channel1_IRQHandler + .thumb_set DMA1_Channel1_IRQHandler,Default_Handler + + .weak DMA1_Channel2_3_IRQHandler + .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler + + .weak DMA1_Channel4_5_IRQHandler + .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler + + .weak ADC1_IRQHandler + .thumb_set ADC1_IRQHandler,Default_Handler + + .weak TIM1_BRK_UP_TRG_COM_IRQHandler + .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM14_IRQHandler + .thumb_set TIM14_IRQHandler,Default_Handler + + .weak TIM16_IRQHandler + .thumb_set TIM16_IRQHandler,Default_Handler + + .weak TIM17_IRQHandler + .thumb_set TIM17_IRQHandler,Default_Handler + + .weak I2C1_IRQHandler + .thumb_set I2C1_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak CEC_CAN_IRQHandler + .thumb_set CEC_CAN_IRQHandler,Default_Handler + + .weak USB_IRQHandler + .thumb_set USB_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ +
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_GCC_ARM/startup_stm32f042x6.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,322 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32f042x6.s - * @author MCD Application Team - * @brief STM32F042x4/STM32F042x6 devices vector table for GCC toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M0 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m0 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss - -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - ldr r0, =_estack - mov sp, r0 /* set stack pointer */ - -/*Check if boot space corresponds to test memory*/ - - LDR R0,=0x00000004 - LDR R1, [R0] - LSRS R1, R1, #24 - LDR R2,=0x1F - CMP R1, R2 - BNE ApplicationStart - - /*SYSCFG clock enable*/ - - LDR R0,=0x40021018 - LDR R1,=0x00000001 - STR R1, [R0] - -/*Set CFGR1 register with flash memory remap at address 0*/ - LDR R0,=0x40010000 - LDR R1,=0x00000000 - STR R1, [R0] - -ApplicationStart: -/* Copy the data segment initializers from flash to SRAM */ - ldr r0, =_sdata - ldr r1, =_edata - ldr r2, =_sidata - movs r3, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r4, [r2, r3] - str r4, [r0, r3] - adds r3, r3, #4 - -LoopCopyDataInit: - adds r4, r0, r3 - cmp r4, r1 - bcc CopyDataInit - -/* Zero fill the bss segment. */ - ldr r2, =_sbss - ldr r4, =_ebss - movs r3, #0 - b LoopFillZerobss - -FillZerobss: - str r3, [r2] - adds r2, r2, #4 - -LoopFillZerobss: - cmp r2, r4 - bcc FillZerobss - -/* Call the clock system intitialization function.*/ - bl SystemInit - -/* Call the application's entry point.*/ -// bl main - bl _start - -LoopForever: - b LoopForever - - -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * - * @param None - * @retval : None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M0. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word 0 - .word 0 - .word PendSV_Handler - .word SysTick_Handler - .word WWDG_IRQHandler /* Window WatchDog */ - .word PVD_VDDIO2_IRQHandler /* PVD and VDDIO2 through EXTI Line detect */ - .word RTC_IRQHandler /* RTC through the EXTI line */ - .word FLASH_IRQHandler /* FLASH */ - .word RCC_CRS_IRQHandler /* RCC and CRS */ - .word EXTI0_1_IRQHandler /* EXTI Line 0 and 1 */ - .word EXTI2_3_IRQHandler /* EXTI Line 2 and 3 */ - .word EXTI4_15_IRQHandler /* EXTI Line 4 to 15 */ - .word TSC_IRQHandler /* TSC */ - .word DMA1_Channel1_IRQHandler /* DMA1 Channel 1 */ - .word DMA1_Channel2_3_IRQHandler /* DMA1 Channel 2 and Channel 3 */ - .word DMA1_Channel4_5_IRQHandler /* DMA1 Channel 4 and Channel 5 */ - .word ADC1_IRQHandler /* ADC1 */ - .word TIM1_BRK_UP_TRG_COM_IRQHandler /* TIM1 Break, Update, Trigger and Commutation */ - .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ - .word TIM2_IRQHandler /* TIM2 */ - .word TIM3_IRQHandler /* TIM3 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word TIM14_IRQHandler /* TIM14 */ - .word 0 /* Reserved */ - .word TIM16_IRQHandler /* TIM16 */ - .word TIM17_IRQHandler /* TIM17 */ - .word I2C1_IRQHandler /* I2C1 */ - .word 0 /* Reserved */ - .word SPI1_IRQHandler /* SPI1 */ - .word SPI2_IRQHandler /* SPI2 */ - .word USART1_IRQHandler /* USART1 */ - .word USART2_IRQHandler /* USART2 */ - .word 0 /* Reserved */ - .word CEC_CAN_IRQHandler /* CEC and CAN */ - .word USB_IRQHandler /* USB */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_VDDIO2_IRQHandler - .thumb_set PVD_VDDIO2_IRQHandler,Default_Handler - - .weak RTC_IRQHandler - .thumb_set RTC_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_CRS_IRQHandler - .thumb_set RCC_CRS_IRQHandler,Default_Handler - - .weak EXTI0_1_IRQHandler - .thumb_set EXTI0_1_IRQHandler,Default_Handler - - .weak EXTI2_3_IRQHandler - .thumb_set EXTI2_3_IRQHandler,Default_Handler - - .weak EXTI4_15_IRQHandler - .thumb_set EXTI4_15_IRQHandler,Default_Handler - - .weak TSC_IRQHandler - .thumb_set TSC_IRQHandler,Default_Handler - - .weak DMA1_Channel1_IRQHandler - .thumb_set DMA1_Channel1_IRQHandler,Default_Handler - - .weak DMA1_Channel2_3_IRQHandler - .thumb_set DMA1_Channel2_3_IRQHandler,Default_Handler - - .weak DMA1_Channel4_5_IRQHandler - .thumb_set DMA1_Channel4_5_IRQHandler,Default_Handler - - .weak ADC1_IRQHandler - .thumb_set ADC1_IRQHandler,Default_Handler - - .weak TIM1_BRK_UP_TRG_COM_IRQHandler - .thumb_set TIM1_BRK_UP_TRG_COM_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM14_IRQHandler - .thumb_set TIM14_IRQHandler,Default_Handler - - .weak TIM16_IRQHandler - .thumb_set TIM16_IRQHandler,Default_Handler - - .weak TIM17_IRQHandler - .thumb_set TIM17_IRQHandler,Default_Handler - - .weak I2C1_IRQHandler - .thumb_set I2C1_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak CEC_CAN_IRQHandler - .thumb_set CEC_CAN_IRQHandler,Default_Handler - - .weak USB_IRQHandler - .thumb_set USB_IRQHandler,Default_Handler - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ -
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_IAR/startup_stm32f042x6.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,319 @@ +;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** +;* File Name : startup_stm32f042x6.s +;* Author : MCD Application Team +;* Description : STM32F042x4/STM32F042x6 devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == __iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address, +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M0 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************* +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window Watchdog + DCD PVD_VDDIO2_IRQHandler ; PVD and VDDIO2 through EXTI Line detect + DCD RTC_IRQHandler ; RTC through EXTI Line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_CRS_IRQHandler ; RCC and CRS + DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 + DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 + DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 + DCD TSC_IRQHandler ; TSC + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 + DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 + DCD ADC1_IRQHandler ; ADC1 + DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM14_IRQHandler ; TIM14 + DCD 0 ; Reserved + DCD TIM16_IRQHandler ; TIM16 + DCD TIM17_IRQHandler ; TIM17 + DCD I2C1_IRQHandler ; I2C1 + DCD 0 ; Reserved + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD CEC_CAN_IRQHandler ; CEC and CAN + DCD USB_IRQHandler ; USB + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + + LDR R0, =sfe(CSTACK) ; set stack pointer + MSR MSP, R0 + +;;Check if boot space corresponds to test memory + LDR R0,=0x00000004 + LDR R1, [R0] + LSRS R1, R1, #24 + LDR R2,=0x1F + CMP R1, R2 + + BNE ApplicationStart +;; SYSCFG clock enable + LDR R0,=0x40021018 + LDR R1,=0x00000001 + STR R1, [R0] + +;; Set CFGR1 register with flash memory remap at address 0 + + LDR R0,=0x40010000 + LDR R1,=0x00000000 + STR R1, [R0] +ApplicationStart + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_VDDIO2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_VDDIO2_IRQHandler + B PVD_VDDIO2_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_CRS_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_CRS_IRQHandler + B RCC_CRS_IRQHandler + + PUBWEAK EXTI0_1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_1_IRQHandler + B EXTI0_1_IRQHandler + + PUBWEAK EXTI2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_3_IRQHandler + B EXTI2_3_IRQHandler + + PUBWEAK EXTI4_15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_15_IRQHandler + B EXTI4_15_IRQHandler + + PUBWEAK TSC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TSC_IRQHandler + B TSC_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_3_IRQHandler + B DMA1_Channel2_3_IRQHandler + + PUBWEAK DMA1_Channel4_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel4_5_IRQHandler + B DMA1_Channel4_5_IRQHandler + + PUBWEAK ADC1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_IRQHandler + B ADC1_IRQHandler + + PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_UP_TRG_COM_IRQHandler + B TIM1_BRK_UP_TRG_COM_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM14_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM14_IRQHandler + B TIM14_IRQHandler + + PUBWEAK TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM16_IRQHandler + B TIM16_IRQHandler + + PUBWEAK TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM17_IRQHandler + B TIM17_IRQHandler + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK CEC_CAN_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CEC_CAN_IRQHandler + B CEC_CAN_IRQHandler + + PUBWEAK USB_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USB_IRQHandler + B USB_IRQHandler + + END +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- a/targets/TARGET_STM/TARGET_STM32F0/TARGET_NUCLEO_F042K6/device/TOOLCHAIN_IAR/startup_stm32f042x6.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,319 +0,0 @@ -;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** -;* File Name : startup_stm32f042x6.s -;* Author : MCD Application Team -;* Description : STM32F042x4/STM32F042x6 devices vector table for EWARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == __iar_program_start, -;* - Set the vector table entries with the exceptions ISR -;* address, -;* - Branches to main in the C library (which eventually -;* calls main()). -;* After Reset the Cortex-M0 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;******************************************************************************* -;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;* -;******************************************************************************* -; -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler ; Reset Handler - - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window Watchdog - DCD PVD_VDDIO2_IRQHandler ; PVD and VDDIO2 through EXTI Line detect - DCD RTC_IRQHandler ; RTC through EXTI Line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_CRS_IRQHandler ; RCC and CRS - DCD EXTI0_1_IRQHandler ; EXTI Line 0 and 1 - DCD EXTI2_3_IRQHandler ; EXTI Line 2 and 3 - DCD EXTI4_15_IRQHandler ; EXTI Line 4 to 15 - DCD TSC_IRQHandler ; TSC - DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 - DCD DMA1_Channel2_3_IRQHandler ; DMA1 Channel 2 and Channel 3 - DCD DMA1_Channel4_5_IRQHandler ; DMA1 Channel 4 and Channel 5 - DCD ADC1_IRQHandler ; ADC1 - DCD TIM1_BRK_UP_TRG_COM_IRQHandler ; TIM1 Break, Update, Trigger and Commutation - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD TIM14_IRQHandler ; TIM14 - DCD 0 ; Reserved - DCD TIM16_IRQHandler ; TIM16 - DCD TIM17_IRQHandler ; TIM17 - DCD I2C1_IRQHandler ; I2C1 - DCD 0 ; Reserved - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD 0 ; Reserved - DCD CEC_CAN_IRQHandler ; CEC and CAN - DCD USB_IRQHandler ; USB - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:NOROOT:REORDER(2) -Reset_Handler - - LDR R0, =sfe(CSTACK) ; set stack pointer - MSR MSP, R0 - -;;Check if boot space corresponds to test memory - LDR R0,=0x00000004 - LDR R1, [R0] - LSRS R1, R1, #24 - LDR R2,=0x1F - CMP R1, R2 - - BNE ApplicationStart -;; SYSCFG clock enable - LDR R0,=0x40021018 - LDR R1,=0x00000001 - STR R1, [R0] - -;; Set CFGR1 register with flash memory remap at address 0 - - LDR R0,=0x40010000 - LDR R1,=0x00000000 - STR R1, [R0] -ApplicationStart - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SVC_Handler - B SVC_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:NOROOT:REORDER(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK WWDG_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -WWDG_IRQHandler - B WWDG_IRQHandler - - PUBWEAK PVD_VDDIO2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -PVD_VDDIO2_IRQHandler - B PVD_VDDIO2_IRQHandler - - PUBWEAK RTC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RTC_IRQHandler - B RTC_IRQHandler - - PUBWEAK FLASH_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -FLASH_IRQHandler - B FLASH_IRQHandler - - PUBWEAK RCC_CRS_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -RCC_CRS_IRQHandler - B RCC_CRS_IRQHandler - - PUBWEAK EXTI0_1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI0_1_IRQHandler - B EXTI0_1_IRQHandler - - PUBWEAK EXTI2_3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI2_3_IRQHandler - B EXTI2_3_IRQHandler - - PUBWEAK EXTI4_15_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -EXTI4_15_IRQHandler - B EXTI4_15_IRQHandler - - PUBWEAK TSC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TSC_IRQHandler - B TSC_IRQHandler - - PUBWEAK DMA1_Channel1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel1_IRQHandler - B DMA1_Channel1_IRQHandler - - PUBWEAK DMA1_Channel2_3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel2_3_IRQHandler - B DMA1_Channel2_3_IRQHandler - - PUBWEAK DMA1_Channel4_5_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -DMA1_Channel4_5_IRQHandler - B DMA1_Channel4_5_IRQHandler - - PUBWEAK ADC1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -ADC1_IRQHandler - B ADC1_IRQHandler - - PUBWEAK TIM1_BRK_UP_TRG_COM_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_BRK_UP_TRG_COM_IRQHandler - B TIM1_BRK_UP_TRG_COM_IRQHandler - - PUBWEAK TIM1_CC_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM1_CC_IRQHandler - B TIM1_CC_IRQHandler - - PUBWEAK TIM2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM2_IRQHandler - B TIM2_IRQHandler - - PUBWEAK TIM3_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM3_IRQHandler - B TIM3_IRQHandler - - PUBWEAK TIM14_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM14_IRQHandler - B TIM14_IRQHandler - - PUBWEAK TIM16_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM16_IRQHandler - B TIM16_IRQHandler - - PUBWEAK TIM17_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -TIM17_IRQHandler - B TIM17_IRQHandler - - PUBWEAK I2C1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -I2C1_IRQHandler - B I2C1_IRQHandler - - PUBWEAK SPI1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI1_IRQHandler - B SPI1_IRQHandler - - PUBWEAK SPI2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -SPI2_IRQHandler - B SPI2_IRQHandler - - PUBWEAK USART1_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART1_IRQHandler - B USART1_IRQHandler - - PUBWEAK USART2_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USART2_IRQHandler - B USART2_IRQHandler - - PUBWEAK CEC_CAN_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -CEC_CAN_IRQHandler - B CEC_CAN_IRQHandler - - PUBWEAK USB_IRQHandler - SECTION .text:CODE:NOROOT:REORDER(1) -USB_IRQHandler - B USB_IRQHandler - - END -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/TOOLCHAIN_ARM_MICRO/startup_stm32f207xx.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,415 @@ +******************* (C) COPYRIGHT 2016 STMicroelectronics ******************** +;* File Name : startup_stm32f207xx.s +;* Author : MCD Application Team +;* Version : V2.1.1 +;* Date : 20-November-2015 +;* Description : STM32F207xx devices vector table for MDK-ARM_MICRO toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20020000 ; Top of RAM + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FSMC_IRQHandler ; FSMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD HASH_RNG_IRQHandler ; Hash and Rng + + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FSMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT HASH_RNG_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FSMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +HASH_RNG_IRQHandler + + B . + + ENDP + + ALIGN + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- a/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/TOOLCHAIN_ARM_MICRO/startup_stm32f207xx.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,415 +0,0 @@ -******************* (C) COPYRIGHT 2016 STMicroelectronics ******************** -;* File Name : startup_stm32f207xx.s -;* Author : MCD Application Team -;* Version : V2.1.1 -;* Date : 20-November-2015 -;* Description : STM32F207xx devices vector table for MDK-ARM_MICRO toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM3 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;******************************************************************************* -; -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;******************************************************************************* - -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; <h> Stack Configuration -; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; </h> - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 - EXPORT __initial_sp - -Stack_Mem SPACE Stack_Size -__initial_sp EQU 0x20020000 ; Top of RAM - - -; <h> Heap Configuration -; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; </h> - -Heap_Size EQU 0x00000200 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 - EXPORT __heap_base - EXPORT __heap_limit - -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit EQU (__initial_sp - Stack_Size) - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 - DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 - DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FSMC_IRQHandler ; FSMC - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD 0 ; Reserved - DCD HASH_RNG_IRQHandler ; Hash and Rng - - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMP_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Stream0_IRQHandler [WEAK] - EXPORT DMA1_Stream1_IRQHandler [WEAK] - EXPORT DMA1_Stream2_IRQHandler [WEAK] - EXPORT DMA1_Stream3_IRQHandler [WEAK] - EXPORT DMA1_Stream4_IRQHandler [WEAK] - EXPORT DMA1_Stream5_IRQHandler [WEAK] - EXPORT DMA1_Stream6_IRQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT CAN1_TX_IRQHandler [WEAK] - EXPORT CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_SCE_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] - EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT OTG_FS_WKUP_IRQHandler [WEAK] - EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] - EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] - EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] - EXPORT TIM8_CC_IRQHandler [WEAK] - EXPORT DMA1_Stream7_IRQHandler [WEAK] - EXPORT FSMC_IRQHandler [WEAK] - EXPORT SDIO_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT UART5_IRQHandler [WEAK] - EXPORT TIM6_DAC_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - EXPORT DMA2_Stream0_IRQHandler [WEAK] - EXPORT DMA2_Stream1_IRQHandler [WEAK] - EXPORT DMA2_Stream2_IRQHandler [WEAK] - EXPORT DMA2_Stream3_IRQHandler [WEAK] - EXPORT DMA2_Stream4_IRQHandler [WEAK] - EXPORT ETH_IRQHandler [WEAK] - EXPORT ETH_WKUP_IRQHandler [WEAK] - EXPORT CAN2_TX_IRQHandler [WEAK] - EXPORT CAN2_RX0_IRQHandler [WEAK] - EXPORT CAN2_RX1_IRQHandler [WEAK] - EXPORT CAN2_SCE_IRQHandler [WEAK] - EXPORT OTG_FS_IRQHandler [WEAK] - EXPORT DMA2_Stream5_IRQHandler [WEAK] - EXPORT DMA2_Stream6_IRQHandler [WEAK] - EXPORT DMA2_Stream7_IRQHandler [WEAK] - EXPORT USART6_IRQHandler [WEAK] - EXPORT I2C3_EV_IRQHandler [WEAK] - EXPORT I2C3_ER_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] - EXPORT OTG_HS_WKUP_IRQHandler [WEAK] - EXPORT OTG_HS_IRQHandler [WEAK] - EXPORT DCMI_IRQHandler [WEAK] - EXPORT HASH_RNG_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMP_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Stream0_IRQHandler -DMA1_Stream1_IRQHandler -DMA1_Stream2_IRQHandler -DMA1_Stream3_IRQHandler -DMA1_Stream4_IRQHandler -DMA1_Stream5_IRQHandler -DMA1_Stream6_IRQHandler -ADC_IRQHandler -CAN1_TX_IRQHandler -CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_SCE_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_TIM9_IRQHandler -TIM1_UP_TIM10_IRQHandler -TIM1_TRG_COM_TIM11_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -OTG_FS_WKUP_IRQHandler -TIM8_BRK_TIM12_IRQHandler -TIM8_UP_TIM13_IRQHandler -TIM8_TRG_COM_TIM14_IRQHandler -TIM8_CC_IRQHandler -DMA1_Stream7_IRQHandler -FSMC_IRQHandler -SDIO_IRQHandler -TIM5_IRQHandler -SPI3_IRQHandler -UART4_IRQHandler -UART5_IRQHandler -TIM6_DAC_IRQHandler -TIM7_IRQHandler -DMA2_Stream0_IRQHandler -DMA2_Stream1_IRQHandler -DMA2_Stream2_IRQHandler -DMA2_Stream3_IRQHandler -DMA2_Stream4_IRQHandler -ETH_IRQHandler -ETH_WKUP_IRQHandler -CAN2_TX_IRQHandler -CAN2_RX0_IRQHandler -CAN2_RX1_IRQHandler -CAN2_SCE_IRQHandler -OTG_FS_IRQHandler -DMA2_Stream5_IRQHandler -DMA2_Stream6_IRQHandler -DMA2_Stream7_IRQHandler -USART6_IRQHandler -I2C3_EV_IRQHandler -I2C3_ER_IRQHandler -OTG_HS_EP1_OUT_IRQHandler -OTG_HS_EP1_IN_IRQHandler -OTG_HS_WKUP_IRQHandler -OTG_HS_IRQHandler -DCMI_IRQHandler -HASH_RNG_IRQHandler - - B . - - ENDP - - ALIGN - - END - -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/TOOLCHAIN_ARM_STD/startup_stm32f207xx.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,436 @@ +******************* (C) COPYRIGHT 2016 STMicroelectronics ******************** +;* File Name : startup_stm32f207xx.s +;* Author : MCD Application Team +;* Version : V2.1.1 +;* Date : 20-November-2015 +;* Description : STM32F207xx devices vector table for MDK-ARM_STD toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20020000 + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FSMC_IRQHandler ; FSMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD HASH_RNG_IRQHandler ; Hash and Rng + + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FSMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT HASH_RNG_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FSMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +HASH_RNG_IRQHandler + + B . + + ENDP + + ALIGN + +;******************************************************************************* +; User Stack and Heap initialization +;******************************************************************************* + IF :DEF:__MICROLIB + + EXPORT __initial_sp + EXPORT __heap_base + EXPORT __heap_limit + + ELSE + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap + + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + + ALIGN + + ENDIF + + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- a/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/TOOLCHAIN_ARM_STD/startup_stm32f207xx.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,436 +0,0 @@ -******************* (C) COPYRIGHT 2016 STMicroelectronics ******************** -;* File Name : startup_stm32f207xx.s -;* Author : MCD Application Team -;* Version : V2.1.1 -;* Date : 20-November-2015 -;* Description : STM32F207xx devices vector table for MDK-ARM_STD toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM3 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;******************************************************************************* -; -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;******************************************************************************* - -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; <h> Stack Configuration -; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; </h> - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp EQU 0x20020000 - - -; <h> Heap Configuration -; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; </h> - -Heap_Size EQU 0x00000200 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 - DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 - DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FSMC_IRQHandler ; FSMC - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD 0 ; Reserved - DCD HASH_RNG_IRQHandler ; Hash and Rng - - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMP_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Stream0_IRQHandler [WEAK] - EXPORT DMA1_Stream1_IRQHandler [WEAK] - EXPORT DMA1_Stream2_IRQHandler [WEAK] - EXPORT DMA1_Stream3_IRQHandler [WEAK] - EXPORT DMA1_Stream4_IRQHandler [WEAK] - EXPORT DMA1_Stream5_IRQHandler [WEAK] - EXPORT DMA1_Stream6_IRQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT CAN1_TX_IRQHandler [WEAK] - EXPORT CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_SCE_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] - EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT OTG_FS_WKUP_IRQHandler [WEAK] - EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] - EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] - EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] - EXPORT TIM8_CC_IRQHandler [WEAK] - EXPORT DMA1_Stream7_IRQHandler [WEAK] - EXPORT FSMC_IRQHandler [WEAK] - EXPORT SDIO_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT UART5_IRQHandler [WEAK] - EXPORT TIM6_DAC_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - EXPORT DMA2_Stream0_IRQHandler [WEAK] - EXPORT DMA2_Stream1_IRQHandler [WEAK] - EXPORT DMA2_Stream2_IRQHandler [WEAK] - EXPORT DMA2_Stream3_IRQHandler [WEAK] - EXPORT DMA2_Stream4_IRQHandler [WEAK] - EXPORT ETH_IRQHandler [WEAK] - EXPORT ETH_WKUP_IRQHandler [WEAK] - EXPORT CAN2_TX_IRQHandler [WEAK] - EXPORT CAN2_RX0_IRQHandler [WEAK] - EXPORT CAN2_RX1_IRQHandler [WEAK] - EXPORT CAN2_SCE_IRQHandler [WEAK] - EXPORT OTG_FS_IRQHandler [WEAK] - EXPORT DMA2_Stream5_IRQHandler [WEAK] - EXPORT DMA2_Stream6_IRQHandler [WEAK] - EXPORT DMA2_Stream7_IRQHandler [WEAK] - EXPORT USART6_IRQHandler [WEAK] - EXPORT I2C3_EV_IRQHandler [WEAK] - EXPORT I2C3_ER_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] - EXPORT OTG_HS_WKUP_IRQHandler [WEAK] - EXPORT OTG_HS_IRQHandler [WEAK] - EXPORT DCMI_IRQHandler [WEAK] - EXPORT HASH_RNG_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMP_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Stream0_IRQHandler -DMA1_Stream1_IRQHandler -DMA1_Stream2_IRQHandler -DMA1_Stream3_IRQHandler -DMA1_Stream4_IRQHandler -DMA1_Stream5_IRQHandler -DMA1_Stream6_IRQHandler -ADC_IRQHandler -CAN1_TX_IRQHandler -CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_SCE_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_TIM9_IRQHandler -TIM1_UP_TIM10_IRQHandler -TIM1_TRG_COM_TIM11_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -OTG_FS_WKUP_IRQHandler -TIM8_BRK_TIM12_IRQHandler -TIM8_UP_TIM13_IRQHandler -TIM8_TRG_COM_TIM14_IRQHandler -TIM8_CC_IRQHandler -DMA1_Stream7_IRQHandler -FSMC_IRQHandler -SDIO_IRQHandler -TIM5_IRQHandler -SPI3_IRQHandler -UART4_IRQHandler -UART5_IRQHandler -TIM6_DAC_IRQHandler -TIM7_IRQHandler -DMA2_Stream0_IRQHandler -DMA2_Stream1_IRQHandler -DMA2_Stream2_IRQHandler -DMA2_Stream3_IRQHandler -DMA2_Stream4_IRQHandler -ETH_IRQHandler -ETH_WKUP_IRQHandler -CAN2_TX_IRQHandler -CAN2_RX0_IRQHandler -CAN2_RX1_IRQHandler -CAN2_SCE_IRQHandler -OTG_FS_IRQHandler -DMA2_Stream5_IRQHandler -DMA2_Stream6_IRQHandler -DMA2_Stream7_IRQHandler -USART6_IRQHandler -I2C3_EV_IRQHandler -I2C3_ER_IRQHandler -OTG_HS_EP1_OUT_IRQHandler -OTG_HS_EP1_IN_IRQHandler -OTG_HS_WKUP_IRQHandler -OTG_HS_IRQHandler -DCMI_IRQHandler -HASH_RNG_IRQHandler - - B . - - ENDP - - ALIGN - -;******************************************************************************* -; User Stack and Heap initialization -;******************************************************************************* - IF :DEF:__MICROLIB - - EXPORT __initial_sp - EXPORT __heap_base - EXPORT __heap_limit - - ELSE - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap - - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - - ALIGN - - ENDIF - - END - -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/TOOLCHAIN_GCC_ARM/startup_stm32f207xx.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,508 @@ +/** + ****************************************************************************** + * @file startup_stm32f207xx.s + * @author MCD Application Team + * @version V2.1.1 + * @date 20-November-2015 + * @brief STM32F207xx Devices vector table for Atollic TrueSTUDIO toolchain. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M3 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m3 + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + +/* Call the clock system initialization function.*/ + bl SystemInit +/* Call static constructors */ + //bl __libc_init_array +/* Call the application's entry point.*/ + //bl main + // Calling the crt0 'cold-start' entry point. There __libc_init_array is called + // and when existing hardware_init_hook() and software_init_hook() before + // starting main(). software_init_hook() is available and has to be called due + // to initializsation when using rtos. + bl _start + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FSMC_IRQHandler /* FSMC */ + .word SDIO_IRQHandler /* SDIO */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word ETH_IRQHandler /* Ethernet */ + .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word DCMI_IRQHandler /* DCMI */ + .word 0 /* CRYP crypto */ + .word HASH_RNG_IRQHandler /* Hash and Rng */ + + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FSMC_IRQHandler + .thumb_set FSMC_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak DCMI_IRQHandler + .thumb_set DCMI_IRQHandler,Default_Handler + + .weak HASH_RNG_IRQHandler + .thumb_set HASH_RNG_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/TOOLCHAIN_GCC_ARM/startup_stm32f207xx.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,508 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32f207xx.s - * @author MCD Application Team - * @version V2.1.1 - * @date 20-November-2015 - * @brief STM32F207xx Devices vector table for Atollic TrueSTUDIO toolchain. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M3 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m3 - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ - -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - ldr sp, =_estack /* set stack pointer */ - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - -/* Call the clock system initialization function.*/ - bl SystemInit -/* Call static constructors */ - //bl __libc_init_array -/* Call the application's entry point.*/ - //bl main - // Calling the crt0 'cold-start' entry point. There __libc_init_array is called - // and when existing hardware_init_hook() and software_init_hook() before - // starting main(). software_init_hook() is available and has to be called due - // to initializsation when using rtos. - bl _start - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -*******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - - /* External Interrupts */ - .word WWDG_IRQHandler /* Window WatchDog */ - .word PVD_IRQHandler /* PVD through EXTI Line detection */ - .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ - .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ - .word FLASH_IRQHandler /* FLASH */ - .word RCC_IRQHandler /* RCC */ - .word EXTI0_IRQHandler /* EXTI Line0 */ - .word EXTI1_IRQHandler /* EXTI Line1 */ - .word EXTI2_IRQHandler /* EXTI Line2 */ - .word EXTI3_IRQHandler /* EXTI Line3 */ - .word EXTI4_IRQHandler /* EXTI Line4 */ - .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ - .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ - .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ - .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ - .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ - .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ - .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ - .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ - .word CAN1_TX_IRQHandler /* CAN1 TX */ - .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ - .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ - .word CAN1_SCE_IRQHandler /* CAN1 SCE */ - .word EXTI9_5_IRQHandler /* External Line[9:5]s */ - .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ - .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ - .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ - .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ - .word TIM2_IRQHandler /* TIM2 */ - .word TIM3_IRQHandler /* TIM3 */ - .word TIM4_IRQHandler /* TIM4 */ - .word I2C1_EV_IRQHandler /* I2C1 Event */ - .word I2C1_ER_IRQHandler /* I2C1 Error */ - .word I2C2_EV_IRQHandler /* I2C2 Event */ - .word I2C2_ER_IRQHandler /* I2C2 Error */ - .word SPI1_IRQHandler /* SPI1 */ - .word SPI2_IRQHandler /* SPI2 */ - .word USART1_IRQHandler /* USART1 */ - .word USART2_IRQHandler /* USART2 */ - .word USART3_IRQHandler /* USART3 */ - .word EXTI15_10_IRQHandler /* External Line[15:10]s */ - .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ - .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ - .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ - .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ - .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ - .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ - .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ - .word FSMC_IRQHandler /* FSMC */ - .word SDIO_IRQHandler /* SDIO */ - .word TIM5_IRQHandler /* TIM5 */ - .word SPI3_IRQHandler /* SPI3 */ - .word UART4_IRQHandler /* UART4 */ - .word UART5_IRQHandler /* UART5 */ - .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ - .word TIM7_IRQHandler /* TIM7 */ - .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ - .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ - .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ - .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ - .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ - .word ETH_IRQHandler /* Ethernet */ - .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ - .word CAN2_TX_IRQHandler /* CAN2 TX */ - .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ - .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ - .word CAN2_SCE_IRQHandler /* CAN2 SCE */ - .word OTG_FS_IRQHandler /* USB OTG FS */ - .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ - .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ - .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ - .word USART6_IRQHandler /* USART6 */ - .word I2C3_EV_IRQHandler /* I2C3 event */ - .word I2C3_ER_IRQHandler /* I2C3 error */ - .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ - .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ - .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ - .word OTG_HS_IRQHandler /* USB OTG HS */ - .word DCMI_IRQHandler /* DCMI */ - .word 0 /* CRYP crypto */ - .word HASH_RNG_IRQHandler /* Hash and Rng */ - - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMP_STAMP_IRQHandler - .thumb_set TAMP_STAMP_IRQHandler,Default_Handler - - .weak RTC_WKUP_IRQHandler - .thumb_set RTC_WKUP_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Stream0_IRQHandler - .thumb_set DMA1_Stream0_IRQHandler,Default_Handler - - .weak DMA1_Stream1_IRQHandler - .thumb_set DMA1_Stream1_IRQHandler,Default_Handler - - .weak DMA1_Stream2_IRQHandler - .thumb_set DMA1_Stream2_IRQHandler,Default_Handler - - .weak DMA1_Stream3_IRQHandler - .thumb_set DMA1_Stream3_IRQHandler,Default_Handler - - .weak DMA1_Stream4_IRQHandler - .thumb_set DMA1_Stream4_IRQHandler,Default_Handler - - .weak DMA1_Stream5_IRQHandler - .thumb_set DMA1_Stream5_IRQHandler,Default_Handler - - .weak DMA1_Stream6_IRQHandler - .thumb_set DMA1_Stream6_IRQHandler,Default_Handler - - .weak ADC_IRQHandler - .thumb_set ADC_IRQHandler,Default_Handler - - .weak CAN1_TX_IRQHandler - .thumb_set CAN1_TX_IRQHandler,Default_Handler - - .weak CAN1_RX0_IRQHandler - .thumb_set CAN1_RX0_IRQHandler,Default_Handler - - .weak CAN1_RX1_IRQHandler - .thumb_set CAN1_RX1_IRQHandler,Default_Handler - - .weak CAN1_SCE_IRQHandler - .thumb_set CAN1_SCE_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM1_BRK_TIM9_IRQHandler - .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler - - .weak TIM1_UP_TIM10_IRQHandler - .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler - - .weak TIM1_TRG_COM_TIM11_IRQHandler - .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTC_Alarm_IRQHandler - .thumb_set RTC_Alarm_IRQHandler,Default_Handler - - .weak OTG_FS_WKUP_IRQHandler - .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler - - .weak TIM8_BRK_TIM12_IRQHandler - .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler - - .weak TIM8_UP_TIM13_IRQHandler - .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler - - .weak TIM8_TRG_COM_TIM14_IRQHandler - .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler - - .weak TIM8_CC_IRQHandler - .thumb_set TIM8_CC_IRQHandler,Default_Handler - - .weak DMA1_Stream7_IRQHandler - .thumb_set DMA1_Stream7_IRQHandler,Default_Handler - - .weak FSMC_IRQHandler - .thumb_set FSMC_IRQHandler,Default_Handler - - .weak SDIO_IRQHandler - .thumb_set SDIO_IRQHandler,Default_Handler - - .weak TIM5_IRQHandler - .thumb_set TIM5_IRQHandler,Default_Handler - - .weak SPI3_IRQHandler - .thumb_set SPI3_IRQHandler,Default_Handler - - .weak UART4_IRQHandler - .thumb_set UART4_IRQHandler,Default_Handler - - .weak UART5_IRQHandler - .thumb_set UART5_IRQHandler,Default_Handler - - .weak TIM6_DAC_IRQHandler - .thumb_set TIM6_DAC_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - - .weak DMA2_Stream0_IRQHandler - .thumb_set DMA2_Stream0_IRQHandler,Default_Handler - - .weak DMA2_Stream1_IRQHandler - .thumb_set DMA2_Stream1_IRQHandler,Default_Handler - - .weak DMA2_Stream2_IRQHandler - .thumb_set DMA2_Stream2_IRQHandler,Default_Handler - - .weak DMA2_Stream3_IRQHandler - .thumb_set DMA2_Stream3_IRQHandler,Default_Handler - - .weak DMA2_Stream4_IRQHandler - .thumb_set DMA2_Stream4_IRQHandler,Default_Handler - - .weak ETH_IRQHandler - .thumb_set ETH_IRQHandler,Default_Handler - - .weak ETH_WKUP_IRQHandler - .thumb_set ETH_WKUP_IRQHandler,Default_Handler - - .weak CAN2_TX_IRQHandler - .thumb_set CAN2_TX_IRQHandler,Default_Handler - - .weak CAN2_RX0_IRQHandler - .thumb_set CAN2_RX0_IRQHandler,Default_Handler - - .weak CAN2_RX1_IRQHandler - .thumb_set CAN2_RX1_IRQHandler,Default_Handler - - .weak CAN2_SCE_IRQHandler - .thumb_set CAN2_SCE_IRQHandler,Default_Handler - - .weak OTG_FS_IRQHandler - .thumb_set OTG_FS_IRQHandler,Default_Handler - - .weak DMA2_Stream5_IRQHandler - .thumb_set DMA2_Stream5_IRQHandler,Default_Handler - - .weak DMA2_Stream6_IRQHandler - .thumb_set DMA2_Stream6_IRQHandler,Default_Handler - - .weak DMA2_Stream7_IRQHandler - .thumb_set DMA2_Stream7_IRQHandler,Default_Handler - - .weak USART6_IRQHandler - .thumb_set USART6_IRQHandler,Default_Handler - - .weak I2C3_EV_IRQHandler - .thumb_set I2C3_EV_IRQHandler,Default_Handler - - .weak I2C3_ER_IRQHandler - .thumb_set I2C3_ER_IRQHandler,Default_Handler - - .weak OTG_HS_EP1_OUT_IRQHandler - .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler - - .weak OTG_HS_EP1_IN_IRQHandler - .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler - - .weak OTG_HS_WKUP_IRQHandler - .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler - - .weak OTG_HS_IRQHandler - .thumb_set OTG_HS_IRQHandler,Default_Handler - - .weak DCMI_IRQHandler - .thumb_set DCMI_IRQHandler,Default_Handler - - .weak HASH_RNG_IRQHandler - .thumb_set HASH_RNG_IRQHandler,Default_Handler - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/TOOLCHAIN_IAR/startup_stm32f207xx.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,633 @@ +;/******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** +;* File Name : startup_stm32f207xx.s +;* Author : MCD Application Team +;* Version : V2.1.1 +;* Date : 20-November-2015 +;* Description : STM32F20x/21x devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M3 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FSMC_IRQHandler ; FSMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD HASH_RNG_IRQHandler ; Hash and RNG + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream0_IRQHandler + B DMA1_Stream0_IRQHandler + + PUBWEAK DMA1_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream1_IRQHandler + B DMA1_Stream1_IRQHandler + + PUBWEAK DMA1_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream2_IRQHandler + B DMA1_Stream2_IRQHandler + + PUBWEAK DMA1_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream3_IRQHandler + B DMA1_Stream3_IRQHandler + + PUBWEAK DMA1_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream4_IRQHandler + B DMA1_Stream4_IRQHandler + + PUBWEAK DMA1_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream5_IRQHandler + B DMA1_Stream5_IRQHandler + + PUBWEAK DMA1_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream6_IRQHandler + B DMA1_Stream6_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK CAN1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_TX_IRQHandler + B CAN1_TX_IRQHandler + + PUBWEAK CAN1_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_RX0_IRQHandler + B CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_BRK_TIM9_IRQHandler + B TIM1_BRK_TIM9_IRQHandler + + PUBWEAK TIM1_UP_TIM10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_UP_TIM10_IRQHandler + B TIM1_UP_TIM10_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_TRG_COM_TIM11_IRQHandler + B TIM1_TRG_COM_TIM11_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_WKUP_IRQHandler + B OTG_FS_WKUP_IRQHandler + + PUBWEAK TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_BRK_TIM12_IRQHandler + B TIM8_BRK_TIM12_IRQHandler + + PUBWEAK TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_UP_TIM13_IRQHandler + B TIM8_UP_TIM13_IRQHandler + + PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_TRG_COM_TIM14_IRQHandler + B TIM8_TRG_COM_TIM14_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK DMA1_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream7_IRQHandler + B DMA1_Stream7_IRQHandler + + PUBWEAK FSMC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FSMC_IRQHandler + B FSMC_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SDIO_IRQHandler + B SDIO_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream0_IRQHandler + B DMA2_Stream0_IRQHandler + + PUBWEAK DMA2_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream1_IRQHandler + B DMA2_Stream1_IRQHandler + + PUBWEAK DMA2_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream2_IRQHandler + B DMA2_Stream2_IRQHandler + + PUBWEAK DMA2_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream3_IRQHandler + B DMA2_Stream3_IRQHandler + + PUBWEAK DMA2_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream4_IRQHandler + B DMA2_Stream4_IRQHandler + + PUBWEAK ETH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH_IRQHandler + B ETH_IRQHandler + + PUBWEAK ETH_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH_WKUP_IRQHandler + B ETH_WKUP_IRQHandler + + PUBWEAK CAN2_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_TX_IRQHandler + B CAN2_TX_IRQHandler + + PUBWEAK CAN2_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_RX0_IRQHandler + B CAN2_RX0_IRQHandler + + PUBWEAK CAN2_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_RX1_IRQHandler + B CAN2_RX1_IRQHandler + + PUBWEAK CAN2_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_SCE_IRQHandler + B CAN2_SCE_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + PUBWEAK DMA2_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream5_IRQHandler + B DMA2_Stream5_IRQHandler + + PUBWEAK DMA2_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream6_IRQHandler + B DMA2_Stream6_IRQHandler + + PUBWEAK DMA2_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream7_IRQHandler + B DMA2_Stream7_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_EP1_OUT_IRQHandler + B OTG_HS_EP1_OUT_IRQHandler + + PUBWEAK OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_EP1_IN_IRQHandler + B OTG_HS_EP1_IN_IRQHandler + + PUBWEAK OTG_HS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_WKUP_IRQHandler + B OTG_HS_WKUP_IRQHandler + + PUBWEAK OTG_HS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_IRQHandler + B OTG_HS_IRQHandler + + PUBWEAK DCMI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DCMI_IRQHandler + B DCMI_IRQHandler + + PUBWEAK HASH_RNG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +HASH_RNG_IRQHandler + B HASH_RNG_IRQHandler + + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/TOOLCHAIN_IAR/startup_stm32f207xx.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,633 +0,0 @@ -;/******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** -;* File Name : startup_stm32f207xx.s -;* Author : MCD Application Team -;* Version : V2.1.1 -;* Date : 20-November-2015 -;* Description : STM32F20x/21x devices vector table for EWARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == _iar_program_start, -;* - Set the vector table entries with the exceptions ISR -;* address. -;* - Branches to main in the C library (which eventually -;* calls main()). -;* After Reset the Cortex-M3 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;******************************************************************************** -;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;* -;******************************************************************************* -; -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler ; Reset Handler - - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 - DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 - DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FSMC_IRQHandler ; FSMC - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD 0 ; Reserved - DCD HASH_RNG_IRQHandler ; Hash and RNG - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK WWDG_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -WWDG_IRQHandler - B WWDG_IRQHandler - - PUBWEAK PVD_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PVD_IRQHandler - B PVD_IRQHandler - - PUBWEAK TAMP_STAMP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TAMP_STAMP_IRQHandler - B TAMP_STAMP_IRQHandler - - PUBWEAK RTC_WKUP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC_WKUP_IRQHandler - B RTC_WKUP_IRQHandler - - PUBWEAK FLASH_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FLASH_IRQHandler - B FLASH_IRQHandler - - PUBWEAK RCC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RCC_IRQHandler - B RCC_IRQHandler - - PUBWEAK EXTI0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI0_IRQHandler - B EXTI0_IRQHandler - - PUBWEAK EXTI1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI1_IRQHandler - B EXTI1_IRQHandler - - PUBWEAK EXTI2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI2_IRQHandler - B EXTI2_IRQHandler - - PUBWEAK EXTI3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI3_IRQHandler - B EXTI3_IRQHandler - - PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI4_IRQHandler - B EXTI4_IRQHandler - - PUBWEAK DMA1_Stream0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream0_IRQHandler - B DMA1_Stream0_IRQHandler - - PUBWEAK DMA1_Stream1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream1_IRQHandler - B DMA1_Stream1_IRQHandler - - PUBWEAK DMA1_Stream2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream2_IRQHandler - B DMA1_Stream2_IRQHandler - - PUBWEAK DMA1_Stream3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream3_IRQHandler - B DMA1_Stream3_IRQHandler - - PUBWEAK DMA1_Stream4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream4_IRQHandler - B DMA1_Stream4_IRQHandler - - PUBWEAK DMA1_Stream5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream5_IRQHandler - B DMA1_Stream5_IRQHandler - - PUBWEAK DMA1_Stream6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream6_IRQHandler - B DMA1_Stream6_IRQHandler - - PUBWEAK ADC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ADC_IRQHandler - B ADC_IRQHandler - - PUBWEAK CAN1_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN1_TX_IRQHandler - B CAN1_TX_IRQHandler - - PUBWEAK CAN1_RX0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN1_RX0_IRQHandler - B CAN1_RX0_IRQHandler - - PUBWEAK CAN1_RX1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN1_RX1_IRQHandler - B CAN1_RX1_IRQHandler - - PUBWEAK CAN1_SCE_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN1_SCE_IRQHandler - B CAN1_SCE_IRQHandler - - PUBWEAK EXTI9_5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI9_5_IRQHandler - B EXTI9_5_IRQHandler - - PUBWEAK TIM1_BRK_TIM9_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM1_BRK_TIM9_IRQHandler - B TIM1_BRK_TIM9_IRQHandler - - PUBWEAK TIM1_UP_TIM10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM1_UP_TIM10_IRQHandler - B TIM1_UP_TIM10_IRQHandler - - PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM1_TRG_COM_TIM11_IRQHandler - B TIM1_TRG_COM_TIM11_IRQHandler - - PUBWEAK TIM1_CC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM1_CC_IRQHandler - B TIM1_CC_IRQHandler - - PUBWEAK TIM2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM2_IRQHandler - B TIM2_IRQHandler - - PUBWEAK TIM3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM3_IRQHandler - B TIM3_IRQHandler - - PUBWEAK TIM4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM4_IRQHandler - B TIM4_IRQHandler - - PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C1_EV_IRQHandler - B I2C1_EV_IRQHandler - - PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C1_ER_IRQHandler - B I2C1_ER_IRQHandler - - PUBWEAK I2C2_EV_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C2_EV_IRQHandler - B I2C2_EV_IRQHandler - - PUBWEAK I2C2_ER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C2_ER_IRQHandler - B I2C2_ER_IRQHandler - - PUBWEAK SPI1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI1_IRQHandler - B SPI1_IRQHandler - - PUBWEAK SPI2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI2_IRQHandler - B SPI2_IRQHandler - - PUBWEAK USART1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART1_IRQHandler - B USART1_IRQHandler - - PUBWEAK USART2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART2_IRQHandler - B USART2_IRQHandler - - PUBWEAK USART3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART3_IRQHandler - B USART3_IRQHandler - - PUBWEAK EXTI15_10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI15_10_IRQHandler - B EXTI15_10_IRQHandler - - PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC_Alarm_IRQHandler - B RTC_Alarm_IRQHandler - - PUBWEAK OTG_FS_WKUP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -OTG_FS_WKUP_IRQHandler - B OTG_FS_WKUP_IRQHandler - - PUBWEAK TIM8_BRK_TIM12_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM8_BRK_TIM12_IRQHandler - B TIM8_BRK_TIM12_IRQHandler - - PUBWEAK TIM8_UP_TIM13_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM8_UP_TIM13_IRQHandler - B TIM8_UP_TIM13_IRQHandler - - PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM8_TRG_COM_TIM14_IRQHandler - B TIM8_TRG_COM_TIM14_IRQHandler - - PUBWEAK TIM8_CC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM8_CC_IRQHandler - B TIM8_CC_IRQHandler - - PUBWEAK DMA1_Stream7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream7_IRQHandler - B DMA1_Stream7_IRQHandler - - PUBWEAK FSMC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FSMC_IRQHandler - B FSMC_IRQHandler - - PUBWEAK SDIO_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SDIO_IRQHandler - B SDIO_IRQHandler - - PUBWEAK TIM5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM5_IRQHandler - B TIM5_IRQHandler - - PUBWEAK SPI3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI3_IRQHandler - B SPI3_IRQHandler - - PUBWEAK UART4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART4_IRQHandler - B UART4_IRQHandler - - PUBWEAK UART5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART5_IRQHandler - B UART5_IRQHandler - - PUBWEAK TIM6_DAC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM6_DAC_IRQHandler - B TIM6_DAC_IRQHandler - - PUBWEAK TIM7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM7_IRQHandler - B TIM7_IRQHandler - - PUBWEAK DMA2_Stream0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream0_IRQHandler - B DMA2_Stream0_IRQHandler - - PUBWEAK DMA2_Stream1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream1_IRQHandler - B DMA2_Stream1_IRQHandler - - PUBWEAK DMA2_Stream2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream2_IRQHandler - B DMA2_Stream2_IRQHandler - - PUBWEAK DMA2_Stream3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream3_IRQHandler - B DMA2_Stream3_IRQHandler - - PUBWEAK DMA2_Stream4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream4_IRQHandler - B DMA2_Stream4_IRQHandler - - PUBWEAK ETH_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ETH_IRQHandler - B ETH_IRQHandler - - PUBWEAK ETH_WKUP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ETH_WKUP_IRQHandler - B ETH_WKUP_IRQHandler - - PUBWEAK CAN2_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN2_TX_IRQHandler - B CAN2_TX_IRQHandler - - PUBWEAK CAN2_RX0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN2_RX0_IRQHandler - B CAN2_RX0_IRQHandler - - PUBWEAK CAN2_RX1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN2_RX1_IRQHandler - B CAN2_RX1_IRQHandler - - PUBWEAK CAN2_SCE_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN2_SCE_IRQHandler - B CAN2_SCE_IRQHandler - - PUBWEAK OTG_FS_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -OTG_FS_IRQHandler - B OTG_FS_IRQHandler - - PUBWEAK DMA2_Stream5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream5_IRQHandler - B DMA2_Stream5_IRQHandler - - PUBWEAK DMA2_Stream6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream6_IRQHandler - B DMA2_Stream6_IRQHandler - - PUBWEAK DMA2_Stream7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream7_IRQHandler - B DMA2_Stream7_IRQHandler - - PUBWEAK USART6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART6_IRQHandler - B USART6_IRQHandler - - PUBWEAK I2C3_EV_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C3_EV_IRQHandler - B I2C3_EV_IRQHandler - - PUBWEAK I2C3_ER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C3_ER_IRQHandler - B I2C3_ER_IRQHandler - - PUBWEAK OTG_HS_EP1_OUT_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -OTG_HS_EP1_OUT_IRQHandler - B OTG_HS_EP1_OUT_IRQHandler - - PUBWEAK OTG_HS_EP1_IN_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -OTG_HS_EP1_IN_IRQHandler - B OTG_HS_EP1_IN_IRQHandler - - PUBWEAK OTG_HS_WKUP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -OTG_HS_WKUP_IRQHandler - B OTG_HS_WKUP_IRQHandler - - PUBWEAK OTG_HS_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -OTG_HS_IRQHandler - B OTG_HS_IRQHandler - - PUBWEAK DCMI_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DCMI_IRQHandler - B DCMI_IRQHandler - - PUBWEAK HASH_RNG_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -HASH_RNG_IRQHandler - B HASH_RNG_IRQHandler - - - END -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/system_clock.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F2/TARGET_NUCLEO_F207ZG/device/system_clock.c Tue Mar 20 16:56:18 2018 +0000
@@ -195,7 +195,7 @@
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
- RCC_OscInitStruct.HSICalibrationValue = 16;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
RCC_OscInitStruct.PLL.PLLM = 16;
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/TARGET_DISCO_F303VC/PinNames.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/TARGET_DISCO_F303VC/PinNames.h Tue Mar 20 16:56:18 2018 +0000
@@ -181,12 +181,12 @@
#ifdef MBED_CONF_TARGET_STDIO_UART_TX
STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX,
#else
- STDIO_UART_TX = PA_2,
+ STDIO_UART_TX = PC_4,
#endif
#ifdef MBED_CONF_TARGET_STDIO_UART_RX
STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX,
#else
- STDIO_UART_RX = PA_3,
+ STDIO_UART_RX = PC_5,
#endif
// Generic signals namings
--- a/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/TARGET_DISCO_F303VC/system_clock.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/TARGET_DISCO_F303VC/system_clock.c Tue Mar 20 16:56:18 2018 +0000
@@ -17,9 +17,9 @@
/**
* This file configures the system clock as follows:
*-----------------------------------------------------------------------------
- * System clock source | 1- PLL_HSE_EXTC | 3- PLL_HSI
+ * System clock source | 1- USE_PLL_HSE_EXTC | 3- USE_PLL_HSI
* | (external 8 MHz clock) | (internal 8 MHz)
- * | 2- PLL_HSE_XTAL |
+ * | 2- USE_PLL_HSE_XTAL |
* | (external 8 MHz xtal) |
*-----------------------------------------------------------------------------
* SYSCLK(MHz) | 72 | 64
@@ -35,6 +35,7 @@
**/
#include "stm32f3xx.h"
+#include "mbed_assert.h"
/*!< Uncomment the following line if you need to relocate your vector Table in
Internal SRAM. */
@@ -42,16 +43,18 @@
#define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
This value must be a multiple of 0x200. */
-/* Select the clock sources (other than HSI) to start with (0=OFF, 1=ON) */
-#define USE_PLL_HSE_EXTC (1) /* Use external clock */
-#define USE_PLL_HSE_XTAL (1) /* Use external xtal */
-
+// clock source is selected with CLOCK_SOURCE in json config
+#define USE_PLL_HSE_EXTC 0x8 // Use external clock (ST Link MCO)
+#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (X3 on board - not provided by default)
+#define USE_PLL_HSI 0x2 // Use HSI internal clock
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
-#endif
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
/**
* @brief Setup the microcontroller system
@@ -108,22 +111,26 @@
* @param None
* @retval None
*/
+
void SetSysClock(void)
{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
/* 1- Try to start with HSE and external clock */
-#if USE_PLL_HSE_EXTC != 0
if (SetSysClock_PLL_HSE(1) == 0)
#endif
{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
/* 2- If fail try to start with HSE and external xtal */
-#if USE_PLL_HSE_XTAL != 0
if (SetSysClock_PLL_HSE(0) == 0)
#endif
{
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
/* 3- If fail start with HSI clock */
- if (SetSysClock_PLL_HSI() == 0) {
+ if (SetSysClock_PLL_HSI() == 0)
+#endif
+ {
while(1) {
- // [TODO] Put something here to tell the user that a problem occured...
+ MBED_ASSERT(1);
}
}
}
@@ -133,7 +140,7 @@
//HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_SYSCLK, RCC_MCO_DIV1); // 72 MHz or 64 MHz
}
-#if (USE_PLL_HSE_XTAL != 0) || (USE_PLL_HSE_EXTC != 0)
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
/******************************************************************************/
/* PLL (clocked by HSE) used as System clock source */
/******************************************************************************/
@@ -141,6 +148,7 @@
{
RCC_ClkInitTypeDef RCC_ClkInitStruct;
RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_PeriphCLKInitTypeDef RCC_PeriphClkInit;
/* Enable HSE oscillator and activate PLL with HSE as source */
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
@@ -167,6 +175,12 @@
return 0; // FAIL
}
+ RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
+ RCC_PeriphClkInit.USBClockSelection = RCC_USBCLKSOURCE_PLL_DIV1_5;
+ if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
+ return 0; // FAIL
+ }
+
/* Output clock on MCO1 pin(PA8) for debugging purpose */
//if (bypass == 0)
// HAL_RCC_MCOConfig(RCC_MCO, RCC_MCOSOURCE_HSE, RCC_MCO_DIV2); // 4 MHz with xtal
@@ -175,8 +189,9 @@
return 1; // OK
}
-#endif
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
/******************************************************************************/
/* PLL (clocked by HSI) used as System clock source */
/******************************************************************************/
@@ -189,7 +204,7 @@
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
- RCC_OscInitStruct.HSICalibrationValue = 16;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
RCC_OscInitStruct.PLL.PLLMUL = RCC_PLL_MUL16; // 64 MHz (8 MHz/2 * 16)
@@ -212,4 +227,4 @@
return 1; // OK
}
-
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/device/TOOLCHAIN_IAR/startup_stm32f303xc.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,562 @@ +;/******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** +;* File Name : startup_stm32f303xc.s +;* Author : MCD Application Team +;* Description : STM32F303xB/STM32F303xC devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_TSC_IRQHandler ; EXTI Line2 and Touch Sense controller + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Channel1_IRQHandler ; DMA1 Channel 1 + DCD DMA1_Channel2_IRQHandler ; DMA1 Channel 2 + DCD DMA1_Channel3_IRQHandler ; DMA1 Channel 3 + DCD DMA1_Channel4_IRQHandler ; DMA1 Channel 4 + DCD DMA1_Channel5_IRQHandler ; DMA1 Channel 5 + DCD DMA1_Channel6_IRQHandler ; DMA1 Channel 6 + DCD DMA1_Channel7_IRQHandler ; DMA1 Channel 7 + DCD ADC1_2_IRQHandler ; ADC1 and ADC2 + DCD USB_HP_CAN_TX_IRQHandler ; USB Device High Priority or CAN TX + DCD USB_LP_CAN_RX0_IRQHandler ; USB Device Low Priority or CAN RX0 + DCD CAN_RX1_IRQHandler ; CAN RX1 + DCD CAN_SCE_IRQHandler ; CAN SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM15_IRQHandler ; TIM1 Break and TIM15 + DCD TIM1_UP_TIM16_IRQHandler ; TIM1 Update and TIM16 + DCD TIM1_TRG_COM_TIM17_IRQHandler ; TIM1 Trigger and Commutation and TIM17 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD USBWakeUp_IRQHandler ; USB Wakeup through EXTI line + DCD TIM8_BRK_IRQHandler ; TIM8 Break + DCD TIM8_UP_IRQHandler ; TIM8 Update + DCD TIM8_TRG_COM_IRQHandler ; TIM8 Trigger and Commutation + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD ADC3_IRQHandler ; ADC3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Channel1_IRQHandler ; DMA2 Channel 1 + DCD DMA2_Channel2_IRQHandler ; DMA2 Channel 2 + DCD DMA2_Channel3_IRQHandler ; DMA2 Channel 3 + DCD DMA2_Channel4_IRQHandler ; DMA2 Channel 4 + DCD DMA2_Channel5_IRQHandler ; DMA2 Channel 5 + DCD ADC4_IRQHandler ; ADC4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD COMP1_2_3_IRQHandler ; COMP1, COMP2 and COMP3 + DCD COMP4_5_6_IRQHandler ; COMP4, COMP5 and COMP6 + DCD COMP7_IRQHandler ; COMP7 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD USB_HP_IRQHandler ; USB High Priority remap + DCD USB_LP_IRQHandler ; USB Low Priority remap + DCD USBWakeUp_RMP_IRQHandler ; USB Wakeup remap through EXTI + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_IRQHandler ; FPU + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:NOROOT:REORDER(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:NOROOT:REORDER(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_TSC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI2_TSC_IRQHandler + B EXTI2_TSC_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel1_IRQHandler + B DMA1_Channel1_IRQHandler + + PUBWEAK DMA1_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel2_IRQHandler + B DMA1_Channel2_IRQHandler + + PUBWEAK DMA1_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel3_IRQHandler + B DMA1_Channel3_IRQHandler + + PUBWEAK DMA1_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel4_IRQHandler + B DMA1_Channel4_IRQHandler + + PUBWEAK DMA1_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel5_IRQHandler + B DMA1_Channel5_IRQHandler + + PUBWEAK DMA1_Channel6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel6_IRQHandler + B DMA1_Channel6_IRQHandler + + PUBWEAK DMA1_Channel7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA1_Channel7_IRQHandler + B DMA1_Channel7_IRQHandler + + PUBWEAK ADC1_2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC1_2_IRQHandler + B ADC1_2_IRQHandler + + PUBWEAK USB_HP_CAN_TX_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USB_HP_CAN_TX_IRQHandler + B USB_HP_CAN_TX_IRQHandler + + PUBWEAK USB_LP_CAN_RX0_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USB_LP_CAN_RX0_IRQHandler + B USB_LP_CAN_RX0_IRQHandler + + PUBWEAK CAN_RX1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN_RX1_IRQHandler + B CAN_RX1_IRQHandler + + PUBWEAK CAN_SCE_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +CAN_SCE_IRQHandler + B CAN_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM15_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_BRK_TIM15_IRQHandler + B TIM1_BRK_TIM15_IRQHandler + + PUBWEAK TIM1_UP_TIM16_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_UP_TIM16_IRQHandler + B TIM1_UP_TIM16_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM17_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_TRG_COM_TIM17_IRQHandler + B TIM1_TRG_COM_TIM17_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK USBWakeUp_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBWakeUp_IRQHandler + B USBWakeUp_IRQHandler + + PUBWEAK TIM8_BRK_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_BRK_IRQHandler + B TIM8_BRK_IRQHandler + + PUBWEAK TIM8_UP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_UP_IRQHandler + B TIM8_UP_IRQHandler + + PUBWEAK TIM8_TRG_COM_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_TRG_COM_IRQHandler + B TIM8_TRG_COM_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK ADC3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC3_IRQHandler + B ADC3_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Channel1_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel1_IRQHandler + B DMA2_Channel1_IRQHandler + + PUBWEAK DMA2_Channel2_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel2_IRQHandler + B DMA2_Channel2_IRQHandler + + PUBWEAK DMA2_Channel3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel3_IRQHandler + B DMA2_Channel3_IRQHandler + + PUBWEAK DMA2_Channel4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel4_IRQHandler + B DMA2_Channel4_IRQHandler + + PUBWEAK DMA2_Channel5_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +DMA2_Channel5_IRQHandler + B DMA2_Channel5_IRQHandler + + + PUBWEAK ADC4_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +ADC4_IRQHandler + B ADC4_IRQHandler + + PUBWEAK COMP1_2_3_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP1_2_3_IRQHandler + B COMP1_2_3_IRQHandler + + PUBWEAK COMP4_5_6_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP4_5_6_IRQHandler + B COMP4_5_6_IRQHandler + + PUBWEAK COMP7_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +COMP7_IRQHandler + B COMP7_IRQHandler + + PUBWEAK USB_HP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USB_HP_IRQHandler + B USB_HP_IRQHandler + + PUBWEAK USB_LP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USB_LP_IRQHandler + B USB_LP_IRQHandler + + PUBWEAK USBWakeUp_RMP_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +USBWakeUp_RMP_IRQHandler + B USBWakeUp_RMP_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:NOROOT:REORDER(1) +FPU_IRQHandler + B FPU_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F3/TARGET_STM32F303xC/device/TOOLCHAIN_IAR/stm32f303xc.icf Tue Mar 20 16:56:18 2018 +0000
@@ -0,0 +1,35 @@
+/*-Specials-*/
+define symbol __intvec_start__ = 0x08000000;
+/*-Memory Regions-*/
+define symbol __region_ROM_start__ = 0x08000000;
+define symbol __region_ROM_end__ = 0x0803FFFF;
+
+define symbol __region_CCMRAM_start__ = 0x10000000;
+define symbol __region_CCMRAM_end__ = 0x10001FFF;
+
+/* [RAM = 16kb = 0x4000] Vector table dynamic copy: 98 vectors = 392 bytes (0x188) to be reserved in RAM */
+define symbol __NVIC_start__ = 0x20000000;
+define symbol __NVIC_end__ = 0x20000187; /*aligned on 8 bytes */
+define symbol __region_RAM_start__ = 0x20000188;
+define symbol __region_RAM_end__ = 0x20009FFF;
+
+
+define memory mem with size = 4G;
+define region ROM_region = mem:[from __region_ROM_start__ to __region_ROM_end__];
+define region RAM_region = mem:[from __region_RAM_start__ to __region_RAM_end__];
+define region CCMRAM_region = mem:[from __region_CCMRAM_start__ to __region_CCMRAM_end__];
+
+/* Stack and Heap */
+define symbol __size_cstack__ = 0x1000;
+define symbol __size_heap__ = 0x2000;
+define block CSTACK with alignment = 8, size = __size_cstack__ { };
+define block HEAP with alignment = 8, size = __size_heap__ { };
+define block STACKHEAP with fixed order { block HEAP, block CSTACK };
+
+initialize by copy { readwrite };
+do not initialize { section .noinit };
+
+place at address mem:__intvec_start__ { readonly section .intvec };
+
+place in ROM_region { readonly };
+place in RAM_region { readwrite, block STACKHEAP };
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_ARM_MICRO/startup_stm32f411xe.S Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_ARM_MICRO/startup_stm32f411xe.S Tue Mar 20 16:56:18 2018 +0000 @@ -1,8 +1,6 @@ -;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** ;* File Name : startup_stm32f411xe.s ;* Author : MCD Application Team -;* Version : V2.1.0 -;* Date : 19-June-2014 ;* Description : STM32F411xExx devices vector table for MDK-ARM_MICRO toolchain. ;* This module performs: ;* - Set the initial SP
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_ARM_STD/startup_stm32f411xe.S Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_ARM_STD/startup_stm32f411xe.S Tue Mar 20 16:56:18 2018 +0000 @@ -1,8 +1,6 @@ -;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** ;* File Name : startup_stm32f411xe.s ;* Author : MCD Application Team -;* Version : V2.1.0 -;* Date : 19-June-2014 ;* Description : STM32F411xExx devices vector table for MDK-ARM_STD toolchain. ;* This module performs: ;* - Set the initial SP
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_IAR/startup_stm32f411xe.S Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/TOOLCHAIN_IAR/startup_stm32f411xe.S Tue Mar 20 16:56:18 2018 +0000 @@ -1,8 +1,6 @@ -;/******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;/******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** ;* File Name : startup_stm32f411xe.s ;* Author : MCD Application Team -;* Version : V2.1.0 -;* Date : 19-June-2014 ;* Description : STM32F411xExx devices vector table for EWARM toolchain. ;* This module performs: ;* - Set the initial SP
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/stm32f4xx.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/stm32f4xx.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx.h
* @author MCD Application Team
- * @version V2.6.1
- * @date 14-February-2017
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@@ -124,11 +122,11 @@
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS version number V2.6.1
+ * @brief CMSIS version number V2.6.2
*/
#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
-#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/system_clock.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/system_clock.c Tue Mar 20 16:56:18 2018 +0000
@@ -207,7 +207,7 @@
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
- RCC_OscInitStruct.HSICalibrationValue = 16;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
//RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/system_stm32f4xx.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTB_MTS_DRAGONFLY/device/system_stm32f4xx.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file system_stm32f4xx.h * @author MCD Application Team - * @version V2.6.1 - * @date 14-February-2017 * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/TOOLCHAIN_ARM_MICRO/startup_stm32f411xe.S Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/TOOLCHAIN_ARM_MICRO/startup_stm32f411xe.S Tue Mar 20 16:56:18 2018 +0000 @@ -1,8 +1,6 @@ -;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** ;* File Name : startup_stm32f411xe.s ;* Author : MCD Application Team -;* Version : V2.1.0 -;* Date : 19-June-2014 ;* Description : STM32F411xExx devices vector table for MDK-ARM_MICRO toolchain. ;* This module performs: ;* - Set the initial SP
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/TOOLCHAIN_ARM_STD/startup_stm32f411xe.S Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/TOOLCHAIN_ARM_STD/startup_stm32f411xe.S Tue Mar 20 16:56:18 2018 +0000 @@ -1,8 +1,6 @@ -;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** ;* File Name : startup_stm32f411xe.s ;* Author : MCD Application Team -;* Version : V2.1.0 -;* Date : 19-June-2014 ;* Description : STM32F411xExx devices vector table for MDK-ARM_STD toolchain. ;* This module performs: ;* - Set the initial SP
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/TOOLCHAIN_IAR/startup_stm32f411xe.S Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/TOOLCHAIN_IAR/startup_stm32f411xe.S Tue Mar 20 16:56:18 2018 +0000 @@ -1,8 +1,6 @@ -;/******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;/******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** ;* File Name : startup_stm32f411xe.s ;* Author : MCD Application Team -;* Version : V2.1.0 -;* Date : 19-June-2014 ;* Description : STM32F411xExx devices vector table for EWARM toolchain. ;* This module performs: ;* - Set the initial SP
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/stm32f4xx.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/stm32f4xx.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx.h
* @author MCD Application Team
- * @version V2.6.1
- * @date 14-February-2017
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@@ -124,11 +122,11 @@
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS version number V2.6.1
+ * @brief CMSIS version number V2.6.2
*/
#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
-#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/system_clock.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/system_clock.c Tue Mar 20 16:56:18 2018 +0000
@@ -207,7 +207,7 @@
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
- RCC_OscInitStruct.HSICalibrationValue = 16;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
//RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/system_stm32f4xx.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_DRAGONFLY_F411RE/device/system_stm32f4xx.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file system_stm32f4xx.h * @author MCD Application Team - * @version V2.6.1 - * @date 14-February-2017 * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/TOOLCHAIN_ARM_MICRO/startup_stm32f405xx.S Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/TOOLCHAIN_ARM_MICRO/startup_stm32f405xx.S Tue Mar 20 16:56:18 2018 +0000 @@ -1,8 +1,6 @@ -;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** ;* File Name : startup_stm32f405xx.s ;* Author : MCD Application Team -;* Version : V2.1.0 -;* Date : 19-June-2014 ;* Description : STM32F405xx devices vector table for MDK-ARM_MICRO toolchain. ;* This module performs: ;* - Set the initial SP
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/TOOLCHAIN_ARM_STD/startup_stm32f405xx.S Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/TOOLCHAIN_ARM_STD/startup_stm32f405xx.S Tue Mar 20 16:56:18 2018 +0000 @@ -1,8 +1,6 @@ -;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** ;* File Name : startup_stm32f405xx.s ;* Author : MCD Application Team -;* Version : V2.1.0 -;* Date : 19-June-2014 ;* Description : STM32F405xx devices vector table for MDK-ARM_STD toolchain. ;* This module performs: ;* - Set the initial SP
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/TOOLCHAIN_IAR/startup_stm32f405xx.S Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/TOOLCHAIN_IAR/startup_stm32f405xx.S Tue Mar 20 16:56:18 2018 +0000 @@ -1,8 +1,6 @@ -;/******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;/******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** ;* File Name : startup_stm32f405xx.s ;* Author : MCD Application Team -;* Version : V2.1.0 -;* Date : 19-June-2014 ;* Description : STM32F405xx devices vector table for EWARM toolchain. ;* This module performs: ;* - Set the initial SP
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/stm32f4xx.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/stm32f4xx.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,16 +2,14 @@
******************************************************************************
* @file stm32f4xx.h
* @author MCD Application Team
- * @version V2.6.1
- * @date 14-February-2017
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
* is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select:
* - The STM32F4xx device used in the target application
- * - To use or not the peripherals drivers in application code(i.e.
- * code will be based on direct access to peripherals registers
+ * - To use or not the peripheral's drivers in application code(i.e.
+ * code will be based on direct access to peripheral's registers
* rather than drivers API), this option is controlled by
* "#define USE_HAL_DRIVER"
*
@@ -124,11 +122,11 @@
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS version number V2.6.1
+ * @brief CMSIS version number V2.6.2
*/
#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
-#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/system_stm32f4xx.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F405RG/device/system_stm32f4xx.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file system_stm32f4xx.h * @author MCD Application Team - * @version V2.6.1 - * @date 14-February-2017 * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/TOOLCHAIN_ARM_MICRO/startup_stm32f411xe.S Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/TOOLCHAIN_ARM_MICRO/startup_stm32f411xe.S Tue Mar 20 16:56:18 2018 +0000 @@ -1,8 +1,6 @@ -;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** ;* File Name : startup_stm32f411xe.s ;* Author : MCD Application Team -;* Version : V2.1.0 -;* Date : 19-June-2014 ;* Description : STM32F411xExx devices vector table for MDK-ARM_MICRO toolchain. ;* This module performs: ;* - Set the initial SP
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/TOOLCHAIN_ARM_STD/startup_stm32f411xe.S Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/TOOLCHAIN_ARM_STD/startup_stm32f411xe.S Tue Mar 20 16:56:18 2018 +0000 @@ -1,8 +1,6 @@ -;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** ;* File Name : startup_stm32f411xe.s ;* Author : MCD Application Team -;* Version : V2.1.0 -;* Date : 19-June-2014 ;* Description : STM32F411xExx devices vector table for MDK-ARM_STD toolchain. ;* This module performs: ;* - Set the initial SP
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/TOOLCHAIN_GCC_ARM/startup_stm32f411xe.S Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/TOOLCHAIN_GCC_ARM/startup_stm32f411xe.S Tue Mar 20 16:56:18 2018 +0000 @@ -2,9 +2,7 @@ ****************************************************************************** * @file startup_stm32f411xe.s * @author MCD Application Team - * @version V2.3.0 - * @date 02-March-2015 - * @brief STM32F411xExx Devices vector table for Atollic TrueSTUDIO toolchain. + * @brief STM32F411xExx Devices vector table for GCC based toolchains. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, @@ -16,7 +14,7 @@ ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2017 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -58,6 +56,10 @@ .word _sdata /* end address for the .data section. defined in linker script */ .word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss /* stack used for SystemInit_ExtMemCtl; always internal RAM used */ /** @@ -91,6 +93,18 @@ adds r2, r0, r1 cmp r2, r3 bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + /* Call the clock system intitialization function.*/ bl SystemInit /* Call static constructors */
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/TOOLCHAIN_IAR/startup_stm32f411xe.S Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/TOOLCHAIN_IAR/startup_stm32f411xe.S Tue Mar 20 16:56:18 2018 +0000 @@ -1,8 +1,6 @@ -;/******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;/******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** ;* File Name : startup_stm32f411xe.s ;* Author : MCD Application Team -;* Version : V2.1.0 -;* Date : 19-June-2014 ;* Description : STM32F411xExx devices vector table for EWARM toolchain. ;* This module performs: ;* - Set the initial SP
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/stm32f4xx.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/stm32f4xx.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx.h
* @author MCD Application Team
- * @version V2.6.1
- * @date 14-February-2017
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@@ -124,11 +122,11 @@
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS version number V2.6.1
+ * @brief CMSIS version number V2.6.2
*/
#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
-#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/system_clock.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/system_clock.c Tue Mar 20 16:56:18 2018 +0000
@@ -211,7 +211,7 @@
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
- RCC_OscInitStruct.HSICalibrationValue = 16;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/system_stm32f4xx.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_MTS_MDOT_F411RE/device/system_stm32f4xx.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file system_stm32f4xx.h * @author MCD Application Team - * @version V2.6.1 - * @date 14-February-2017 * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/TARGET_DISCO_F401VC/system_clock.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/TARGET_DISCO_F401VC/system_clock.c Tue Mar 20 16:56:18 2018 +0000
@@ -203,7 +203,7 @@
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
- RCC_OscInitStruct.HSICalibrationValue = 16;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/device/TOOLCHAIN_GCC_ARM/startup_stm32f401xc.S Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/device/TOOLCHAIN_GCC_ARM/startup_stm32f401xc.S Tue Mar 20 16:56:18 2018 +0000 @@ -2,9 +2,7 @@ ****************************************************************************** * @file startup_stm32f401xc.s * @author MCD Application Team - * @version V2.3.0 - * @date 02-March-2015 - * @brief STM32F401xCxx Devices vector table for Atollic TrueSTUDIO toolchain. + * @brief STM32F401xCxx Devices vector table for GCC based toolchains. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, @@ -16,7 +14,7 @@ ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2017 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -58,6 +56,10 @@ .word _sdata /* end address for the .data section. defined in linker script */ .word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss /* stack used for SystemInit_ExtMemCtl; always internal RAM used */ /** @@ -91,6 +93,17 @@ adds r2, r0, r1 cmp r2, r3 bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss /* Call the clock system intitialization function.*/ bl SystemInit
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/device/stm32f401xc.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/device/stm32f401xc.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f401xc.h * @author MCD Application Team - * @version V2.6.1 - * @date 14-February-2017 * @brief CMSIS STM32F401xC Device Peripheral Access Layer Header File. * * This file contains: @@ -67,9 +65,11 @@ #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */ #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +/* MBED */ #ifndef __FPU_PRESENT #define __FPU_PRESENT 1U /*!< FPU present */ #endif /* __FPU_PRESENT */ +/* MBED */ /** * @} @@ -656,7 +656,6 @@ #define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */ #define SRAM1_BASE 0x20000000U /*!< SRAM1(64 KB) base address in the alias region */ #define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */ -#define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */ #define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(64 KB) base address in the bit-band region */ #define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */ #define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */ @@ -6679,7 +6678,7 @@ #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */ #define USART_CR1_TXEIE_Pos (7U) #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */ -#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<PE Interrupt Enable */ +#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<TXE Interrupt Enable */ #define USART_CR1_PEIE_Pos (8U) #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */ #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */ @@ -7514,92 +7513,6 @@ #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */ #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */ -/******************** Bit definition for OTG register ********************/ - -#define USB_OTG_CHNUM_Pos (0U) -#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */ -#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */ -#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */ -#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */ -#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */ -#define USB_OTG_BCNT_Pos (4U) -#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */ - -#define USB_OTG_DPID_Pos (15U) -#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */ -#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */ -#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */ - -#define USB_OTG_PKTSTS_Pos (17U) -#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */ -#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */ -#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */ -#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */ -#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */ - -#define USB_OTG_EPNUM_Pos (0U) -#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */ -#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */ -#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */ -#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */ -#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */ - -#define USB_OTG_FRMNUM_Pos (21U) -#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */ -#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */ -#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */ -#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */ -#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */ -#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */ - -/******************** Bit definition for OTG register ********************/ - -#define USB_OTG_CHNUM_Pos (0U) -#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */ -#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */ -#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */ -#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */ -#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */ -#define USB_OTG_BCNT_Pos (4U) -#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */ - -#define USB_OTG_DPID_Pos (15U) -#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */ -#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */ -#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */ - -#define USB_OTG_PKTSTS_Pos (17U) -#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */ -#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */ -#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */ -#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */ -#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */ - -#define USB_OTG_EPNUM_Pos (0U) -#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */ -#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */ -#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */ -#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */ -#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */ - -#define USB_OTG_FRMNUM_Pos (21U) -#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */ -#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */ -#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */ -#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */ -#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */ -#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */ - /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/ #define USB_OTG_GRXFSIZ_RXFD_Pos (0U) #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */ @@ -8245,6 +8158,48 @@ #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */ #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */ +/* Legacy define */ +/******************** Bit definition for OTG register ********************/ +#define USB_OTG_CHNUM_Pos (0U) +#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */ +#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */ +#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */ +#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */ +#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */ +#define USB_OTG_BCNT_Pos (4U) +#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */ + +#define USB_OTG_DPID_Pos (15U) +#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */ +#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */ +#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */ + +#define USB_OTG_PKTSTS_Pos (17U) +#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */ +#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */ +#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */ +#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */ + +#define USB_OTG_EPNUM_Pos (0U) +#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */ +#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */ +#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */ +#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */ +#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */ + +#define USB_OTG_FRMNUM_Pos (21U) +#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */ +#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */ +#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */ +#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */ /** * @} */
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/device/stm32f4xx.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/device/stm32f4xx.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx.h
* @author MCD Application Team
- * @version V2.6.1
- * @date 14-February-2017
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@@ -124,11 +122,11 @@
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS version number V2.6.1
+ * @brief CMSIS version number V2.6.2
*/
#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
-#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/device/system_stm32f4xx.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xC/device/system_stm32f4xx.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file system_stm32f4xx.h * @author MCD Application Team - * @version V2.6.1 - * @date 14-February-2017 * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_NUCLEO_F401RE/system_clock.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_NUCLEO_F401RE/system_clock.c Tue Mar 20 16:56:18 2018 +0000
@@ -210,7 +210,7 @@
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
- RCC_OscInitStruct.HSICalibrationValue = 16;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_STEVAL_3DP001V1/PeripheralNames.h Tue Mar 20 16:56:18 2018 +0000
@@ -0,0 +1,77 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PERIPHERALNAMES_H
+#define MBED_PERIPHERALNAMES_H
+
+#include "cmsis.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ADC_1 = (int)ADC1_BASE
+} ADCName;
+
+typedef enum {
+ UART_1 = (int)USART1_BASE,
+ UART_2 = (int)USART2_BASE,
+ UART_6 = (int)USART6_BASE
+} UARTName;
+
+typedef enum {
+ SPI_1 = (int)SPI1_BASE,
+ SPI_2 = (int)SPI2_BASE,
+ SPI_3 = (int)SPI3_BASE,
+ SPI_4 = (int)SPI4_BASE
+} SPIName;
+
+typedef enum {
+ I2C_1 = (int)I2C1_BASE,
+ I2C_2 = (int)I2C2_BASE,
+ I2C_3 = (int)I2C3_BASE
+} I2CName;
+
+typedef enum {
+ PWM_1 = (int)TIM1_BASE,
+ PWM_2 = (int)TIM2_BASE,
+ PWM_3 = (int)TIM3_BASE,
+ PWM_4 = (int)TIM4_BASE,
+ PWM_5 = (int)TIM5_BASE,
+ PWM_9 = (int)TIM9_BASE,
+ PWM_10 = (int)TIM10_BASE,
+ PWM_11 = (int)TIM11_BASE
+} PWMName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_STEVAL_3DP001V1/PeripheralPins.c Tue Mar 20 16:56:18 2018 +0000
@@ -0,0 +1,255 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2017, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+
+#include "PeripheralPins.h"
+#include "mbed_toolchain.h"
+
+//==============================================================================
+// Notes
+//
+// - The pins mentionned Px_y_ALTz are alternative possibilities which use other
+// HW peripheral instances. You can use them the same way as any other "normal"
+// pin (i.e. PwmOut pwm(PA_7_ALT0);). These pins are not displayed on the board
+// pinout image on mbed.org.
+//
+// - The pins which are connected to other components present on the board have
+// the comment "Connected to xxx". The pin function may not work properly in this
+// case. These pins may not be displayed on the board pinout image on mbed.org.
+// Please read the board reference manual and schematic for more information.
+//
+// - Warning: some pins are connected to the default STDIO_UART_TX and STDIO_UART_RX pins.
+// See https://os.mbed.com/teams/ST/wiki/STDIO for more information.
+//
+//==============================================================================
+
+//*** ADC ***
+
+MBED_WEAK const PinMap PinMap_ADC[] = {
+ {PA_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 0, 0)}, // ADC1_IN0
+ {PA_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 1, 0)}, // ADC1_IN1
+ {PA_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 2, 0)}, // ADC1_IN2
+ {PA_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 3, 0)}, // ADC1_IN3
+ {PA_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 4, 0)}, // ADC1_IN4
+ {PA_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 5, 0)}, // ADC1_IN5
+ {PA_6, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 6, 0)}, // ADC1_IN6
+ {PA_7, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 7, 0)}, // ADC1_IN7
+ {PB_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 8, 0)}, // ADC1_IN8
+ {PB_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 9, 0)}, // ADC1_IN9
+ {PC_0, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 10, 0)}, // ADC1_IN10
+ {PC_1, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 11, 0)}, // ADC1_IN11
+ {PC_2, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 12, 0)}, // ADC1_IN12
+ {PC_3, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 13, 0)}, // ADC1_IN13
+ {PC_4, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 14, 0)}, // ADC1_IN14
+ {PC_5, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 15, 0)}, // ADC1_IN15
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_ADC_Internal[] = {
+ {ADC_TEMP, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 16, 0)}, // See in analogin_api.c the correct ADC channel used
+ {ADC_VREF, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 17, 0)}, // See in analogin_api.c the correct ADC channel used
+ {ADC_VBAT, ADC_1, STM_PIN_DATA_EXT(STM_MODE_ANALOG, GPIO_NOPULL, 0, 18, 0)}, // See in analogin_api.c the correct ADC channel used
+ {NC, NC, 0}
+};
+
+//*** I2C ***
+
+MBED_WEAK const PinMap PinMap_I2C_SDA[] = {
+ {PB_3, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C2)},
+ {PB_4, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF9_I2C3)},
+ {PB_7, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_9, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PC_9, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_I2C_SCL[] = {
+ {PA_8, I2C_3, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C3)},
+ {PB_6, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_8, I2C_1, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C1)},
+ {PB_10, I2C_2, STM_PIN_DATA(STM_MODE_AF_OD, GPIO_NOPULL, GPIO_AF4_I2C2)},
+ {NC, NC, 0}
+};
+
+//*** PWM ***
+
+MBED_WEAK const PinMap PinMap_PWM[] = {
+ {PA_0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+// {PA_0, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 1, 0)}, // TIM5_CH1 // TIM5 used by the us_ticker
+ {PA_1, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+// {PA_1, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 2, 0)}, // TIM5_CH2 // TIM5 used by the us_ticker
+ {PA_2_ALT0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
+// {PA_2, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 3, 0)}, // TIM5_CH3 // TIM5 used by the us_ticker
+ {PA_2, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1
+ {PA_3_ALT0, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 4, 0)}, // TIM2_CH4
+// {PA_3, PWM_5, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM5, 4, 0)}, // TIM5_CH4 // TIM5 used by the us_ticker
+ {PA_3, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2
+ {PA_5, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+ {PA_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PA_7, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+ {PA_7_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PA_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
+#ifdef MBED_CONF_TARGET_STDIO_UART_TX
+ {PA_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
+#endif
+#ifdef MBED_CONF_TARGET_STDIO_UART_RX
+ {PA_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
+#endif
+ {PA_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
+ {PA_15, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 1, 0)}, // TIM2_CH1
+
+ {PB_0, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+ {PB_0_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+ {PB_1, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+ {PB_1_ALT0, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+ {PB_3, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 2, 0)}, // TIM2_CH2
+ {PB_4, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PB_5, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PB_6, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
+ {PB_7, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
+ {PB_8, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
+ {PB_8_ALT0, PWM_10,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM10, 1, 0)}, // TIM10_CH1
+ {PB_9, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
+ {PB_9_ALT0, PWM_11,STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM11, 1, 0)}, // TIM11_CH1
+ {PB_10, PWM_2, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM2, 3, 0)}, // TIM2_CH3
+ {PB_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+ {PB_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+ {PB_15, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+
+ {PC_6, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 1, 0)}, // TIM3_CH1
+ {PC_7, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 2, 0)}, // TIM3_CH2
+ {PC_8, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 3, 0)}, // TIM3_CH3
+ {PC_9, PWM_3, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM3, 4, 0)}, // TIM3_CH4
+
+ {PD_12, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 1, 0)}, // TIM4_CH1
+ {PD_13, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 2, 0)}, // TIM4_CH2
+ {PD_14, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 3, 0)}, // TIM4_CH3
+ {PD_15, PWM_4, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF2_TIM4, 4, 0)}, // TIM4_CH4
+
+ {PE_5, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 1, 0)}, // TIM9_CH1
+ {PE_6, PWM_9, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF3_TIM9, 2, 0)}, // TIM9_CH2
+
+ {PE_8, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 1)}, // TIM1_CH1N
+ {PE_9, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 1, 0)}, // TIM1_CH1
+ {PE_10, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 1)}, // TIM1_CH2N
+ {PE_11, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 2, 0)}, // TIM1_CH2
+ {PE_12, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 1)}, // TIM1_CH3N
+ {PE_13, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 3, 0)}, // TIM1_CH3
+ {PE_14, PWM_1, STM_PIN_DATA_EXT(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF1_TIM1, 4, 0)}, // TIM1_CH4
+
+ {NC, NC, 0}
+};
+
+//*** SERIAL ***
+
+MBED_WEAK const PinMap PinMap_UART_TX[] = {
+ {PA_2, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_9, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to STDIO_UART_TX (default)
+ {PA_11, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PB_6, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PC_6, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PD_5, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_RX[] = {
+ {PA_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_10, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)}, // Connected to STDIO_UART_RX (default)
+ {PA_12, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PB_7, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PC_7, UART_6, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF8_USART6)},
+ {PD_6, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_RTS[] = {
+ {PA_1, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_12, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PD_4, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_UART_CTS[] = {
+ {PA_0, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {PA_11, UART_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART1)},
+ {PD_3, UART_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF7_USART2)},
+ {NC, NC, 0}
+};
+
+//*** SPI ***
+
+MBED_WEAK const PinMap PinMap_SPI_MOSI[] = {
+ {PA_7, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_5_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PB_15, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_12, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PD_6, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI3)},
+ {PE_6, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+ {PE_14, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_MISO[] = {
+ {PA_6, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PB_14, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_2, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_11, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PE_5, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+ {PE_13, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_SCLK[] = {
+ {PA_5, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_3, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI1)},
+ {PB_3_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PB_10, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PB_13, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PC_10, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF6_SPI3)},
+ {PD_3, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI2)},
+ {PE_2, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+ {PE_12, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+ {NC, NC, 0}
+};
+
+MBED_WEAK const PinMap PinMap_SPI_SSEL[] = {
+ {PA_4, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PA_4_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PA_15, SPI_1, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI1)},
+ {PA_15_ALT0, SPI_3, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF6_SPI3)},
+ {PB_9, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PB_12, SPI_2, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI2)},
+ {PE_4, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_NOPULL, GPIO_AF5_SPI4)},
+ {PE_11, SPI_4, STM_PIN_DATA(STM_MODE_AF_PP, GPIO_PULLUP, GPIO_AF5_SPI4)},
+ {NC, NC, 0}
+};
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_STEVAL_3DP001V1/PinNames.h Tue Mar 20 16:56:18 2018 +0000
@@ -0,0 +1,198 @@
+/* mbed Microcontroller Library
+ *******************************************************************************
+ * Copyright (c) 2014, STMicroelectronics
+ * All rights reserved.
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *******************************************************************************
+ */
+#ifndef MBED_PINNAMES_H
+#define MBED_PINNAMES_H
+
+#include "cmsis.h"
+#include "PinNamesTypes.h"
+
+#ifdef __cplusplus
+extern "C" {
+#endif
+
+typedef enum {
+ ALT0 = 0x100,
+ ALT1 = 0x200
+} ALTx;
+
+typedef enum {
+ PA_0 = 0x00,
+ PA_1 = 0x01,
+ PA_2 = 0x02,
+ PA_2_ALT0 = PA_2|ALT0,
+ PA_3 = 0x03,
+ PA_3_ALT0 = PA_3|ALT0,
+ PA_4 = 0x04,
+ PA_4_ALT0 = PA_4|ALT0,
+ PA_5 = 0x05,
+ PA_6 = 0x06,
+ PA_7 = 0x07,
+ PA_7_ALT0 = PA_7|ALT0,
+ PA_8 = 0x08,
+ PA_9 = 0x09,
+ PA_10 = 0x0A,
+ PA_11 = 0x0B,
+ PA_12 = 0x0C,
+ PA_13 = 0x0D,
+ PA_14 = 0x0E,
+ PA_15 = 0x0F,
+ PA_15_ALT0 = PA_15|ALT0,
+
+ PB_0 = 0x10,
+ PB_0_ALT0 = PB_0|ALT0,
+ PB_1 = 0x11,
+ PB_1_ALT0 = PB_1|ALT0,
+ PB_2 = 0x12,
+ PB_3 = 0x13,
+ PB_3_ALT0 = PB_3|ALT0,
+ PB_4 = 0x14,
+ PB_4_ALT0 = PB_4|ALT0,
+ PB_5 = 0x15,
+ PB_5_ALT0 = PB_5|ALT0,
+ PB_6 = 0x16,
+ PB_7 = 0x17,
+ PB_8 = 0x18,
+ PB_8_ALT0 = PB_8|ALT0,
+ PB_9 = 0x19,
+ PB_9_ALT0 = PB_9|ALT0,
+ PB_10 = 0x1A,
+ PB_12 = 0x1C,
+ PB_13 = 0x1D,
+ PB_14 = 0x1E,
+ PB_15 = 0x1F,
+
+ PC_0 = 0x20,
+ PC_1 = 0x21,
+ PC_2 = 0x22,
+ PC_3 = 0x23,
+ PC_4 = 0x24,
+ PC_5 = 0x25,
+ PC_6 = 0x26,
+ PC_7 = 0x27,
+ PC_8 = 0x28,
+ PC_9 = 0x29,
+ PC_10 = 0x2A,
+ PC_11 = 0x2B,
+ PC_12 = 0x2C,
+ PC_13 = 0x2D,
+ PC_14 = 0x2E,
+ PC_15 = 0x2F,
+
+ PD_0 = 0x30,
+ PD_1 = 0x31,
+ PD_2 = 0x32,
+ PD_3 = 0x33,
+ PD_4 = 0x34,
+ PD_5 = 0x35,
+ PD_6 = 0x36,
+ PD_7 = 0x37,
+ PD_8 = 0x38,
+ PD_9 = 0x39,
+ PD_10 = 0x3A,
+ PD_11 = 0x3B,
+ PD_12 = 0x3C,
+ PD_13 = 0x3D,
+ PD_14 = 0x3E,
+ PD_15 = 0x3F,
+
+ PE_0 = 0x40,
+ PE_1 = 0x41,
+ PE_2 = 0x42,
+ PE_3 = 0x43,
+ PE_4 = 0x44,
+ PE_5 = 0x45,
+ PE_6 = 0x46,
+ PE_7 = 0x47,
+ PE_8 = 0x48,
+ PE_9 = 0x49,
+ PE_10 = 0x4A,
+ PE_11 = 0x4B,
+ PE_12 = 0x4C,
+ PE_13 = 0x4D,
+ PE_14 = 0x4E,
+ PE_15 = 0x4F,
+
+ PH_0 = 0x70, // Connected to RCC_OSC_IN
+ PH_1 = 0x71, // Connected to RCC_OSC_OUT
+
+ // ADC internal channels
+ ADC_TEMP = 0xF0,
+ ADC_VREF = 0xF1,
+ ADC_VBAT = 0xF2,
+
+ // STDIO for console print
+#ifdef MBED_CONF_TARGET_STDIO_UART_TX
+ STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX,
+#else
+ STDIO_UART_TX = PA_9,
+#endif
+#ifdef MBED_CONF_TARGET_STDIO_UART_RX
+ STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX,
+#else
+ STDIO_UART_RX = PA_10,
+#endif
+
+ // Generic signals namings
+ LED1 = PA_5,
+ LED2 = PA_5,
+ LED3 = PA_5,
+ LED4 = PA_5,
+ LED_RED = LED1,
+ USER_BUTTON = PE_7,
+ // Standardized button names
+ BUTTON1 = USER_BUTTON,
+ SERIAL_TX = STDIO_UART_TX,
+ SERIAL_RX = STDIO_UART_RX,
+ USBTX = STDIO_UART_TX,
+ USBRX = STDIO_UART_RX,
+ I2C_SCL = PB_8,
+ I2C_SDA = PB_9,
+ SPI_MOSI = PA_7,
+ SPI_MISO = PA_6,
+ SPI_SCK = PA_5,
+ SPI_CS = PB_6,
+ PWM_OUT = PB_3,
+
+ //USB pins
+ USB_OTG_FS_SOF = PA_8,
+ USB_OTG_FS_VBUS = PA_9,
+ USB_OTG_FS_ID = PA_10,
+ USB_OTG_FS_DM = PA_11,
+ USB_OTG_FS_DP = PA_12,
+
+ // Not connected
+ NC = (int)0xFFFFFFFF
+} PinName;
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/TARGET_STEVAL_3DP001V1/system_clock.c Tue Mar 20 16:56:18 2018 +0000
@@ -0,0 +1,239 @@
+/* mbed Microcontroller Library
+* Copyright (c) 2006-2017 ARM Limited
+*
+* Licensed under the Apache License, Version 2.0 (the "License");
+* you may not use this file except in compliance with the License.
+* You may obtain a copy of the License at
+*
+* http://www.apache.org/licenses/LICENSE-2.0
+*
+* Unless required by applicable law or agreed to in writing, software
+* distributed under the License is distributed on an "AS IS" BASIS,
+* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+* See the License for the specific language governing permissions and
+* limitations under the License.
+*/
+
+/**
+ * This file configures the system clock as follows:
+ *-----------------------------------------------------------------------------
+ * System clock source | 1- USE_PLL_HSE_EXTC (external 25 MHz clock)
+ * | 2- USE_PLL_HSE_XTAL (external 25 MHz xtal)
+ * | 3- USE_PLL_HSI (internal 16 MHz)
+ *-----------------------------------------------------------------------------
+ * SYSCLK(MHz) | 84
+ * AHBCLK (MHz) | 84
+ * APB1CLK (MHz) | 42
+ * APB2CLK (MHz) | 84
+ * USB capable | YES
+ *-----------------------------------------------------------------------------
+**/
+
+#include "stm32f4xx.h"
+#include "mbed_assert.h"
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+ Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET 0x00 /*!< Vector Table base offset field.
+ This value must be a multiple of 0x200. */
+
+
+// clock source is selected with CLOCK_SOURCE in json config
+#define USE_PLL_HSE_EXTC 0x8 // Use external clock (Not connected on board)
+#define USE_PLL_HSE_XTAL 0x4 // Use external xtal (Y1 on board)
+#define USE_PLL_HSI 0x2 // Use HSI internal clock
+
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+uint8_t SetSysClock_PLL_HSI(void);
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
+
+
+/**
+ * @brief Setup the microcontroller system
+ * Initialize the FPU setting, vector table location and External memory
+ * configuration.
+ * @param None
+ * @retval None
+ */
+void SystemInit(void)
+{
+ /* FPU settings ------------------------------------------------------------*/
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+ SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
+#endif
+ /* Reset the RCC clock configuration to the default reset state ------------*/
+ /* Set HSION bit */
+ RCC->CR |= (uint32_t)0x00000001;
+
+ /* Reset CFGR register */
+ RCC->CFGR = 0x00000000;
+
+ /* Reset HSEON, CSSON and PLLON bits */
+ RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+ /* Reset PLLCFGR register */
+ RCC->PLLCFGR = 0x24003010;
+
+ /* Reset HSEBYP bit */
+ RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+ /* Disable all interrupts */
+ RCC->CIR = 0x00000000;
+
+#if defined (DATA_IN_ExtSRAM) || defined (DATA_IN_ExtSDRAM)
+ SystemInit_ExtMemCtl();
+#endif /* DATA_IN_ExtSRAM || DATA_IN_ExtSDRAM */
+
+ /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+ SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+ SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+
+}
+
+/*
+ * @brief Configures the System clock source, PLL Multiplier and Divider factors,
+ * AHB/APBx prescalers and Flash settings
+ * @note This function should be called only once the RCC clock configuration
+ * is reset to the default reset state (done in SystemInit() function).
+ * @param None
+ * @retval None
+ */
+
+void SetSysClock(void)
+{
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC)
+ /* 1- Try to start with HSE and external clock */
+ if (SetSysClock_PLL_HSE(1) == 0)
+#endif
+ {
+#if ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL)
+ /* 2- If fail try to start with HSE and external xtal */
+ if (SetSysClock_PLL_HSE(0) == 0)
+#endif
+ {
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+ /* 3- If fail start with HSI clock */
+ if (SetSysClock_PLL_HSI() == 0)
+#endif
+ {
+ while(1) {
+ MBED_ASSERT(1);
+ }
+ }
+ }
+ }
+
+ /* Output clock on MCO2 pin(PC9) for debugging purpose */
+ //HAL_RCC_MCOConfig(RCC_MCO2, RCC_MCO2SOURCE_SYSCLK, RCC_MCODIV_4);
+}
+
+#if ( ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) )
+/******************************************************************************/
+/* PLL (clocked by HSE) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
+
+ // Enable HSE oscillator and activate PLL with HSE as source
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE;
+ if (bypass == 0) {
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 25 MHz xtal on OSC_IN/OSC_OUT
+ } else {
+ RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 25 MHz clock on OSC_IN
+ }
+
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
+ RCC_OscInitStruct.PLL.PLLM = 25; // VCO input clock = 1 MHz (25 MHz / 25)
+ RCC_OscInitStruct.PLL.PLLN = 336; // VCO output clock = 336 MHz (1 MHz * 336)
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 84 MHz (336 MHz / 4)
+ RCC_OscInitStruct.PLL.PLLQ = 7; // USB clock = 48 MHz (336 MHz / 7) --> OK for USB
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ // Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers
+ RCC_ClkInitStruct.ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 84 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 84 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 42 MHz
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 84 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+ /*
+ if (bypass == 0)
+ HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_2); // 4 MHz
+ else
+ HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSE, RCC_MCODIV_1); // 8 MHz
+ */
+
+ return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSE_XTAL) || ((CLOCK_SOURCE) & USE_PLL_HSE_EXTC) */
+
+#if ((CLOCK_SOURCE) & USE_PLL_HSI)
+/******************************************************************************/
+/* PLL (clocked by HSI) used as System clock source */
+/******************************************************************************/
+uint8_t SetSysClock_PLL_HSI(void)
+{
+ RCC_OscInitTypeDef RCC_OscInitStruct;
+ RCC_ClkInitTypeDef RCC_ClkInitStruct;
+
+ /* The voltage scaling allows optimizing the power consumption when the device is
+ clocked below the maximum system frequency, to update the voltage scaling value
+ regarding system frequency refer to product datasheet. */
+ __HAL_RCC_PWR_CLK_ENABLE();
+ __HAL_PWR_VOLTAGESCALING_CONFIG(PWR_REGULATOR_VOLTAGE_SCALE2);
+
+ // Enable HSI oscillator and activate PLL with HSI as source
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
+ RCC_OscInitStruct.HSIState = RCC_HSI_ON;
+ RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
+ RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
+ RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
+ RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
+ RCC_OscInitStruct.PLL.PLLN = 336; // VCO output clock = 336 MHz (1 MHz * 336)
+ RCC_OscInitStruct.PLL.PLLP = RCC_PLLP_DIV4; // PLLCLK = 84 MHz (336 MHz / 4)
+ RCC_OscInitStruct.PLL.PLLQ = 7; // USB clock = 48 MHz (336 MHz / 7) --> freq is ok but not precise enough
+ if (HAL_RCC_OscConfig(&RCC_OscInitStruct) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Select PLL as system clock source and configure the HCLK, PCLK1 and PCLK2 clocks dividers */
+ RCC_ClkInitStruct.ClockType = (RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2);
+ RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK; // 84 MHz
+ RCC_ClkInitStruct.AHBCLKDivider = RCC_SYSCLK_DIV1; // 84 MHz
+ RCC_ClkInitStruct.APB1CLKDivider = RCC_HCLK_DIV2; // 42 MHz
+ RCC_ClkInitStruct.APB2CLKDivider = RCC_HCLK_DIV1; // 84 MHz
+ if (HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_2) != HAL_OK) {
+ return 0; // FAIL
+ }
+
+ /* Output clock on MCO1 pin(PA8) for debugging purpose */
+ //HAL_RCC_MCOConfig(RCC_MCO1, RCC_MCO1SOURCE_HSI, RCC_MCODIV_1); // 16 MHz
+
+ return 1; // OK
+}
+#endif /* ((CLOCK_SOURCE) & USE_PLL_HSI) */
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/TOOLCHAIN_ARM_MICRO/startup_stm32f401xe.S Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/TOOLCHAIN_ARM_MICRO/startup_stm32f401xe.S Tue Mar 20 16:56:18 2018 +0000 @@ -1,8 +1,6 @@ -;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** ;* File Name : startup_stm32f401xe.s ;* Author : MCD Application Team -;* Version : V2.1.0 -;* Date : 19-June-2014 ;* Description : STM32F401xe devices vector table for MDK-ARM_MICRO toolchain. ;* This module performs: ;* - Set the initial SP
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/TOOLCHAIN_ARM_STD/startup_stm32f401xe.S Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/TOOLCHAIN_ARM_STD/startup_stm32f401xe.S Tue Mar 20 16:56:18 2018 +0000 @@ -1,8 +1,6 @@ -;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** ;* File Name : startup_stm32f401xe.s ;* Author : MCD Application Team -;* Version : V2.1.0 -;* Date : 19-June-2014 ;* Description : STM32F401xe devices vector table for MDK-ARM_STD toolchain. ;* This module performs: ;* - Set the initial SP
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/TOOLCHAIN_GCC_ARM/startup_stm32f401xe.S Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/TOOLCHAIN_GCC_ARM/startup_stm32f401xe.S Tue Mar 20 16:56:18 2018 +0000 @@ -2,9 +2,7 @@ ****************************************************************************** * @file startup_stm32f401xe.s * @author MCD Application Team - * @version V2.3.0 - * @date 02-March-2015 - * @brief STM32F401xExx Devices vector table for Atollic TrueSTUDIO toolchain. + * @brief STM32F401xExx Devices vector table for GCC based toolchains. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, @@ -16,7 +14,7 @@ ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2017 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -58,6 +56,10 @@ .word _sdata /* end address for the .data section. defined in linker script */ .word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss /* stack used for SystemInit_ExtMemCtl; always internal RAM used */ /** @@ -91,6 +93,17 @@ adds r2, r0, r1 cmp r2, r3 bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss /* Call the clock system intitialization function.*/ bl SystemInit
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/TOOLCHAIN_IAR/startup_stm32f401xe.S Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/TOOLCHAIN_IAR/startup_stm32f401xe.S Tue Mar 20 16:56:18 2018 +0000
@@ -1,8 +1,6 @@
-;/******************** (C) COPYRIGHT 2014 STMicroelectronics ********************
+;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
;* File Name : startup_stm32f401xe.s
;* Author : MCD Application Team
-;* Version : V2.0.0
-;* Date : 18-February-2014
;* Description : STM32F401xExx devices vector table for EWARM toolchain.
;* This module performs:
;* - Set the initial SP
@@ -88,91 +86,91 @@
DCD SysTick_Handler ; SysTick Handler
; External Interrupts
- DCD WWDG_IRQHandler ; Window WatchDog
- DCD PVD_IRQHandler ; PVD through EXTI Line detection
- DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
- DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
- DCD FLASH_IRQHandler ; FLASH
- DCD RCC_IRQHandler ; RCC
- DCD EXTI0_IRQHandler ; EXTI Line0
- DCD EXTI1_IRQHandler ; EXTI Line1
- DCD EXTI2_IRQHandler ; EXTI Line2
- DCD EXTI3_IRQHandler ; EXTI Line3
- DCD EXTI4_IRQHandler ; EXTI Line4
- DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
- DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
- DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
- DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
- DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
- DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
- DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
- DCD ADC_IRQHandler ; ADC1
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD EXTI9_5_IRQHandler ; External Line[9:5]s
- DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
- DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
+ DCD WWDG_IRQHandler ; Window WatchDog
+ DCD PVD_IRQHandler ; PVD through EXTI Line detection
+ DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line
+ DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line
+ DCD FLASH_IRQHandler ; FLASH
+ DCD RCC_IRQHandler ; RCC
+ DCD EXTI0_IRQHandler ; EXTI Line0
+ DCD EXTI1_IRQHandler ; EXTI Line1
+ DCD EXTI2_IRQHandler ; EXTI Line2
+ DCD EXTI3_IRQHandler ; EXTI Line3
+ DCD EXTI4_IRQHandler ; EXTI Line4
+ DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0
+ DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1
+ DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2
+ DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3
+ DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4
+ DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5
+ DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6
+ DCD ADC_IRQHandler ; ADC1
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD EXTI9_5_IRQHandler ; External Line[9:5]s
+ DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9
+ DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10
DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11
- DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
- DCD TIM2_IRQHandler ; TIM2
- DCD TIM3_IRQHandler ; TIM3
- DCD TIM4_IRQHandler ; TIM4
- DCD I2C1_EV_IRQHandler ; I2C1 Event
- DCD I2C1_ER_IRQHandler ; I2C1 Error
- DCD I2C2_EV_IRQHandler ; I2C2 Event
- DCD I2C2_ER_IRQHandler ; I2C2 Error
- DCD SPI1_IRQHandler ; SPI1
- DCD SPI2_IRQHandler ; SPI2
- DCD USART1_IRQHandler ; USART1
- DCD USART2_IRQHandler ; USART2
- DCD 0 ; Reserved
- DCD EXTI15_10_IRQHandler ; External Line[15:10]s
- DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
- DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
- DCD 0 ; Reserved
- DCD 0 ; Reserved
+ DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare
+ DCD TIM2_IRQHandler ; TIM2
+ DCD TIM3_IRQHandler ; TIM3
+ DCD TIM4_IRQHandler ; TIM4
+ DCD I2C1_EV_IRQHandler ; I2C1 Event
+ DCD I2C1_ER_IRQHandler ; I2C1 Error
+ DCD I2C2_EV_IRQHandler ; I2C2 Event
+ DCD I2C2_ER_IRQHandler ; I2C2 Error
+ DCD SPI1_IRQHandler ; SPI1
+ DCD SPI2_IRQHandler ; SPI2
+ DCD USART1_IRQHandler ; USART1
+ DCD USART2_IRQHandler ; USART2
+ DCD 0 ; Reserved
+ DCD EXTI15_10_IRQHandler ; External Line[15:10]s
+ DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line
+ DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
+ DCD 0 ; Reserved
+ DCD SDIO_IRQHandler ; SDIO
+ DCD TIM5_IRQHandler ; TIM5
+ DCD SPI3_IRQHandler ; SPI3
+ DCD 0 ; Reserved
DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7
- DCD 0 ; Reserved
- DCD SDIO_IRQHandler ; SDIO
- DCD TIM5_IRQHandler ; TIM5
- DCD SPI3_IRQHandler ; SPI3
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
- DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
- DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
- DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
- DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD OTG_FS_IRQHandler ; USB OTG FS
- DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
- DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
- DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
- DCD USART6_IRQHandler ; USART6
- DCD I2C3_EV_IRQHandler ; I2C3 event
- DCD I2C3_ER_IRQHandler ; I2C3 error
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0
+ DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1
+ DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2
+ DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3
+ DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD OTG_FS_IRQHandler ; USB OTG FS
+ DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5
+ DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6
+ DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7
+ DCD USART6_IRQHandler ; USART6
+ DCD I2C3_EV_IRQHandler ; I2C3 event
+ DCD I2C3_ER_IRQHandler ; I2C3 error
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
DCD 0 ; Reserved
DCD FPU_IRQHandler ; FPU
- DCD 0 ; Reserved
- DCD 0 ; Reserved
- DCD SPI4_IRQHandler ; SPI4
+ DCD 0 ; Reserved
+ DCD 0 ; Reserved
+ DCD SPI4_IRQHandler ; SPI4
;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
;;
@@ -180,7 +178,7 @@
;;
THUMB
PUBWEAK Reset_Handler
- SECTION .text:CODE:REORDER(2)
+ SECTION .text:CODE:REORDER:NOROOT(2)
Reset_Handler
LDR R0, =SystemInit
@@ -189,327 +187,327 @@
BX R0
PUBWEAK NMI_Handler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
NMI_Handler
B NMI_Handler
PUBWEAK HardFault_Handler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
HardFault_Handler
B HardFault_Handler
PUBWEAK MemManage_Handler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
MemManage_Handler
B MemManage_Handler
PUBWEAK BusFault_Handler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
BusFault_Handler
B BusFault_Handler
PUBWEAK UsageFault_Handler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
UsageFault_Handler
B UsageFault_Handler
PUBWEAK SVC_Handler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
SVC_Handler
B SVC_Handler
PUBWEAK DebugMon_Handler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
DebugMon_Handler
B DebugMon_Handler
PUBWEAK PendSV_Handler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
PendSV_Handler
B PendSV_Handler
PUBWEAK SysTick_Handler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
SysTick_Handler
B SysTick_Handler
PUBWEAK WWDG_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
WWDG_IRQHandler
B WWDG_IRQHandler
PUBWEAK PVD_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
PVD_IRQHandler
B PVD_IRQHandler
PUBWEAK TAMP_STAMP_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
TAMP_STAMP_IRQHandler
B TAMP_STAMP_IRQHandler
PUBWEAK RTC_WKUP_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
RTC_WKUP_IRQHandler
B RTC_WKUP_IRQHandler
PUBWEAK FLASH_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
FLASH_IRQHandler
B FLASH_IRQHandler
PUBWEAK RCC_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
RCC_IRQHandler
B RCC_IRQHandler
PUBWEAK EXTI0_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
EXTI0_IRQHandler
B EXTI0_IRQHandler
PUBWEAK EXTI1_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
EXTI1_IRQHandler
B EXTI1_IRQHandler
PUBWEAK EXTI2_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
EXTI2_IRQHandler
B EXTI2_IRQHandler
PUBWEAK EXTI3_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
EXTI3_IRQHandler
B EXTI3_IRQHandler
PUBWEAK EXTI4_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
EXTI4_IRQHandler
B EXTI4_IRQHandler
PUBWEAK DMA1_Stream0_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Stream0_IRQHandler
B DMA1_Stream0_IRQHandler
PUBWEAK DMA1_Stream1_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Stream1_IRQHandler
B DMA1_Stream1_IRQHandler
PUBWEAK DMA1_Stream2_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Stream2_IRQHandler
B DMA1_Stream2_IRQHandler
PUBWEAK DMA1_Stream3_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Stream3_IRQHandler
B DMA1_Stream3_IRQHandler
PUBWEAK DMA1_Stream4_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Stream4_IRQHandler
B DMA1_Stream4_IRQHandler
PUBWEAK DMA1_Stream5_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Stream5_IRQHandler
B DMA1_Stream5_IRQHandler
PUBWEAK DMA1_Stream6_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Stream6_IRQHandler
B DMA1_Stream6_IRQHandler
PUBWEAK ADC_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
ADC_IRQHandler
B ADC_IRQHandler
PUBWEAK EXTI9_5_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
EXTI9_5_IRQHandler
B EXTI9_5_IRQHandler
PUBWEAK TIM1_BRK_TIM9_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_BRK_TIM9_IRQHandler
B TIM1_BRK_TIM9_IRQHandler
PUBWEAK TIM1_UP_TIM10_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_UP_TIM10_IRQHandler
B TIM1_UP_TIM10_IRQHandler
PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_TRG_COM_TIM11_IRQHandler
B TIM1_TRG_COM_TIM11_IRQHandler
PUBWEAK TIM1_CC_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
TIM1_CC_IRQHandler
B TIM1_CC_IRQHandler
PUBWEAK TIM2_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
TIM2_IRQHandler
B TIM2_IRQHandler
PUBWEAK TIM3_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
TIM3_IRQHandler
B TIM3_IRQHandler
PUBWEAK TIM4_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
TIM4_IRQHandler
B TIM4_IRQHandler
PUBWEAK I2C1_EV_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_EV_IRQHandler
B I2C1_EV_IRQHandler
PUBWEAK I2C1_ER_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
I2C1_ER_IRQHandler
B I2C1_ER_IRQHandler
PUBWEAK I2C2_EV_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_EV_IRQHandler
B I2C2_EV_IRQHandler
PUBWEAK I2C2_ER_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
I2C2_ER_IRQHandler
B I2C2_ER_IRQHandler
PUBWEAK SPI1_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
SPI1_IRQHandler
B SPI1_IRQHandler
PUBWEAK SPI2_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
SPI2_IRQHandler
B SPI2_IRQHandler
PUBWEAK USART1_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
USART1_IRQHandler
B USART1_IRQHandler
PUBWEAK USART2_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
USART2_IRQHandler
B USART2_IRQHandler
PUBWEAK EXTI15_10_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
EXTI15_10_IRQHandler
B EXTI15_10_IRQHandler
PUBWEAK RTC_Alarm_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
RTC_Alarm_IRQHandler
B RTC_Alarm_IRQHandler
PUBWEAK OTG_FS_WKUP_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
OTG_FS_WKUP_IRQHandler
B OTG_FS_WKUP_IRQHandler
PUBWEAK DMA1_Stream7_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
DMA1_Stream7_IRQHandler
B DMA1_Stream7_IRQHandler
PUBWEAK SDIO_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
SDIO_IRQHandler
B SDIO_IRQHandler
PUBWEAK TIM5_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
TIM5_IRQHandler
B TIM5_IRQHandler
PUBWEAK SPI3_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
SPI3_IRQHandler
B SPI3_IRQHandler
PUBWEAK DMA2_Stream0_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Stream0_IRQHandler
B DMA2_Stream0_IRQHandler
PUBWEAK DMA2_Stream1_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Stream1_IRQHandler
B DMA2_Stream1_IRQHandler
PUBWEAK DMA2_Stream2_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Stream2_IRQHandler
B DMA2_Stream2_IRQHandler
PUBWEAK DMA2_Stream3_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Stream3_IRQHandler
B DMA2_Stream3_IRQHandler
PUBWEAK DMA2_Stream4_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Stream4_IRQHandler
B DMA2_Stream4_IRQHandler
PUBWEAK OTG_FS_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
OTG_FS_IRQHandler
B OTG_FS_IRQHandler
PUBWEAK DMA2_Stream5_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Stream5_IRQHandler
B DMA2_Stream5_IRQHandler
PUBWEAK DMA2_Stream6_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Stream6_IRQHandler
B DMA2_Stream6_IRQHandler
PUBWEAK DMA2_Stream7_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
DMA2_Stream7_IRQHandler
B DMA2_Stream7_IRQHandler
PUBWEAK USART6_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
USART6_IRQHandler
B USART6_IRQHandler
PUBWEAK I2C3_EV_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
I2C3_EV_IRQHandler
B I2C3_EV_IRQHandler
PUBWEAK I2C3_ER_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
I2C3_ER_IRQHandler
B I2C3_ER_IRQHandler
PUBWEAK FPU_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
FPU_IRQHandler
B FPU_IRQHandler
PUBWEAK SPI4_IRQHandler
- SECTION .text:CODE:REORDER(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
SPI4_IRQHandler
B SPI4_IRQHandler
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/stm32f401xe.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/stm32f401xe.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f401xe.h * @author MCD Application Team - * @version V2.6.1 - * @date 14-February-2017 * @brief CMSIS STM32F401xE Device Peripheral Access Layer Header File. * * This file contains: @@ -67,9 +65,11 @@ #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */ #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +/* MBED */ #ifndef __FPU_PRESENT #define __FPU_PRESENT 1U /*!< FPU present */ #endif /* __FPU_PRESENT */ +/* MBED */ /** * @} @@ -656,7 +656,6 @@ #define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */ #define SRAM1_BASE 0x20000000U /*!< SRAM1(96 KB) base address in the alias region */ #define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */ -#define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */ #define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(96 KB) base address in the bit-band region */ #define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */ #define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */ @@ -6679,7 +6678,7 @@ #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */ #define USART_CR1_TXEIE_Pos (7U) #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */ -#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<PE Interrupt Enable */ +#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<TXE Interrupt Enable */ #define USART_CR1_PEIE_Pos (8U) #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */ #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */ @@ -7514,92 +7513,6 @@ #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */ #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */ -/******************** Bit definition for OTG register ********************/ - -#define USB_OTG_CHNUM_Pos (0U) -#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */ -#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */ -#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */ -#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */ -#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */ -#define USB_OTG_BCNT_Pos (4U) -#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */ - -#define USB_OTG_DPID_Pos (15U) -#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */ -#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */ -#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */ - -#define USB_OTG_PKTSTS_Pos (17U) -#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */ -#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */ -#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */ -#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */ -#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */ - -#define USB_OTG_EPNUM_Pos (0U) -#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */ -#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */ -#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */ -#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */ -#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */ - -#define USB_OTG_FRMNUM_Pos (21U) -#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */ -#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */ -#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */ -#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */ -#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */ -#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */ - -/******************** Bit definition for OTG register ********************/ - -#define USB_OTG_CHNUM_Pos (0U) -#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */ -#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */ -#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */ -#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */ -#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */ -#define USB_OTG_BCNT_Pos (4U) -#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */ - -#define USB_OTG_DPID_Pos (15U) -#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */ -#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */ -#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */ - -#define USB_OTG_PKTSTS_Pos (17U) -#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */ -#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */ -#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */ -#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */ -#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */ - -#define USB_OTG_EPNUM_Pos (0U) -#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */ -#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */ -#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */ -#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */ -#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */ - -#define USB_OTG_FRMNUM_Pos (21U) -#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */ -#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */ -#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */ -#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */ -#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */ -#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */ - /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/ #define USB_OTG_GRXFSIZ_RXFD_Pos (0U) #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */ @@ -8245,6 +8158,48 @@ #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */ #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */ +/* Legacy define */ +/******************** Bit definition for OTG register ********************/ +#define USB_OTG_CHNUM_Pos (0U) +#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */ +#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */ +#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */ +#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */ +#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */ +#define USB_OTG_BCNT_Pos (4U) +#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */ + +#define USB_OTG_DPID_Pos (15U) +#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */ +#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */ +#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */ + +#define USB_OTG_PKTSTS_Pos (17U) +#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */ +#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */ +#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */ +#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */ + +#define USB_OTG_EPNUM_Pos (0U) +#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */ +#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */ +#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */ +#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */ +#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */ + +#define USB_OTG_FRMNUM_Pos (21U) +#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */ +#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */ +#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */ +#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */ /** * @} */
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/stm32f4xx.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/stm32f4xx.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx.h
* @author MCD Application Team
- * @version V2.6.1
- * @date 14-February-2017
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@@ -124,11 +122,11 @@
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS version number V2.6.1
+ * @brief CMSIS version number V2.6.2
*/
#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
-#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/system_stm32f4xx.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F401xE/device/system_stm32f4xx.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file system_stm32f4xx.h * @author MCD Application Team - * @version V2.6.1 - * @date 14-February-2017 * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_ARCH_MAX/system_clock.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_ARCH_MAX/system_clock.c Tue Mar 20 16:56:18 2018 +0000
@@ -204,7 +204,7 @@
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
- RCC_OscInitStruct.HSICalibrationValue = 16;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/system_clock.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/TARGET_DISCO_F407VG/system_clock.c Tue Mar 20 16:56:18 2018 +0000
@@ -209,7 +209,7 @@
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
- RCC_OscInitStruct.HSICalibrationValue = 16;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_GCC_ARM/startup_stm32f407xx.S Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/TOOLCHAIN_GCC_ARM/startup_stm32f407xx.S Tue Mar 20 16:56:18 2018 +0000 @@ -2,9 +2,7 @@ ****************************************************************************** * @file startup_stm32f407xx.s * @author MCD Application Team - * @version V2.3.0 - * @date 02-March-2015 - * @brief STM32F407xx Devices vector table for Atollic TrueSTUDIO toolchain. + * @brief STM32F407xx Devices vector table for GCC based toolchains. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, @@ -16,7 +14,7 @@ ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2017 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -58,6 +56,10 @@ .word _sdata /* end address for the .data section. defined in linker script */ .word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss /* stack used for SystemInit_ExtMemCtl; always internal RAM used */ /** @@ -91,7 +93,18 @@ adds r2, r0, r1 cmp r2, r3 bcc CopyDataInit - + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + /* Call the clock system intitialization function.*/ bl SystemInit /* Call static constructors */
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/stm32f407xx.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/stm32f407xx.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f407xx.h * @author MCD Application Team - * @version V2.6.1 - * @date 14-February-2017 * @brief CMSIS STM32F407xx Device Peripheral Access Layer Header File. * * This file contains: @@ -67,9 +65,11 @@ #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */ #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +/* MBED */ #ifndef __FPU_PRESENT #define __FPU_PRESENT 1U /*!< FPU present */ #endif /* __FPU_PRESENT */ +/* MBED */ /** * @} @@ -174,9 +174,11 @@ OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */ OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */ DCMI_IRQn = 78, /*!< DCMI global interrupt */ - HASH_RNG_IRQn = 80, /*!< Hash and Rng global interrupt */ + RNG_IRQn = 80, /*!< RNG global Interrupt */ FPU_IRQn = 81 /*!< FPU global interrupt */ } IRQn_Type; +/* Legacy define */ +#define HASH_RNG_IRQn RNG_IRQn /** * @} @@ -12543,7 +12545,7 @@ #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */ #define USART_CR1_TXEIE_Pos (7U) #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */ -#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<PE Interrupt Enable */ +#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<TXE Interrupt Enable */ #define USART_CR1_PEIE_Pos (8U) #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */ #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */ @@ -14355,92 +14357,6 @@ #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */ #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */ -/******************** Bit definition for OTG register ********************/ - -#define USB_OTG_CHNUM_Pos (0U) -#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */ -#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */ -#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */ -#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */ -#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */ -#define USB_OTG_BCNT_Pos (4U) -#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */ - -#define USB_OTG_DPID_Pos (15U) -#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */ -#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */ -#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */ - -#define USB_OTG_PKTSTS_Pos (17U) -#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */ -#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */ -#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */ -#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */ -#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */ - -#define USB_OTG_EPNUM_Pos (0U) -#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */ -#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */ -#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */ -#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */ -#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */ - -#define USB_OTG_FRMNUM_Pos (21U) -#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */ -#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */ -#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */ -#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */ -#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */ -#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */ - -/******************** Bit definition for OTG register ********************/ - -#define USB_OTG_CHNUM_Pos (0U) -#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */ -#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */ -#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */ -#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */ -#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */ -#define USB_OTG_BCNT_Pos (4U) -#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */ - -#define USB_OTG_DPID_Pos (15U) -#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */ -#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */ -#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */ - -#define USB_OTG_PKTSTS_Pos (17U) -#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */ -#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */ -#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */ -#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */ -#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */ - -#define USB_OTG_EPNUM_Pos (0U) -#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */ -#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */ -#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */ -#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */ -#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */ - -#define USB_OTG_FRMNUM_Pos (21U) -#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */ -#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */ -#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */ -#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */ -#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */ -#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */ - /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/ #define USB_OTG_GRXFSIZ_RXFD_Pos (0U) #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */ @@ -15086,6 +15002,48 @@ #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */ #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */ +/* Legacy define */ +/******************** Bit definition for OTG register ********************/ +#define USB_OTG_CHNUM_Pos (0U) +#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */ +#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */ +#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */ +#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */ +#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */ +#define USB_OTG_BCNT_Pos (4U) +#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */ + +#define USB_OTG_DPID_Pos (15U) +#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */ +#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */ +#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */ + +#define USB_OTG_PKTSTS_Pos (17U) +#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */ +#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */ +#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */ +#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */ + +#define USB_OTG_EPNUM_Pos (0U) +#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */ +#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */ +#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */ +#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */ +#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */ + +#define USB_OTG_FRMNUM_Pos (21U) +#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */ +#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */ +#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */ +#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */ /** * @} */
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/stm32f4xx.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/stm32f4xx.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,23 +2,21 @@
******************************************************************************
* @file stm32f4xx.h
* @author MCD Application Team
- * @version V2.6.1
- * @date 14-February-2017
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
* is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select:
* - The STM32F4xx device used in the target application
- * - To use or not the peripherals drivers in application code(i.e.
- * code will be based on direct access to peripherals registers
+ * - To use or not the peripheral's drivers in application code(i.e.
+ * code will be based on direct access to peripheral's registers
* rather than drivers API), this option is controlled by
* "#define USE_HAL_DRIVER"
*
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -92,6 +90,9 @@
STM32F439NI, STM32F439IG and STM32F439II Devices */
/* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
/* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
+ /* #define STM32F410Tx */ /*!< STM32F410T8 and STM32F410TB Devices */
+ /* #define STM32F410Cx */ /*!< STM32F410C8 and STM32F410CB Devices */
+ /* #define STM32F410Rx */ /*!< STM32F410R8 and STM32F410RB Devices */
/* #define STM32F411xE */ /*!< STM32F411CC, STM32F411RC, STM32F411VC, STM32F411CE, STM32F411RE and STM32F411VE Devices */
/* #define STM32F446xx */ /*!< STM32F446MC, STM32F446ME, STM32F446RC, STM32F446RE, STM32F446VC, STM32F446VE, STM32F446ZC,
and STM32F446ZE Devices */
@@ -121,11 +122,11 @@
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS version number V2.6.1
+ * @brief CMSIS version number V2.6.2
*/
#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
-#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
@@ -199,20 +200,20 @@
*/
typedef enum
{
- RESET = 0,
+ RESET = 0U,
SET = !RESET
} FlagStatus, ITStatus;
typedef enum
{
- DISABLE = 0,
+ DISABLE = 0U,
ENABLE = !DISABLE
} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
typedef enum
{
- ERROR = 0,
+ ERROR = 0U,
SUCCESS = !ERROR
} ErrorStatus;
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/system_stm32f4xx.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F407xG/device/system_stm32f4xx.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,13 +2,11 @@ ****************************************************************************** * @file system_stm32f4xx.h * @author MCD Application Team - * @version V2.6.1 - * @date 14-February-2017 * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met:
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/TARGET_NUCLEO_F410RB/system_clock.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/TARGET_NUCLEO_F410RB/system_clock.c Tue Mar 20 16:56:18 2018 +0000
@@ -209,7 +209,7 @@
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
- RCC_OscInitStruct.HSICalibrationValue = 16;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
RCC_OscInitStruct.PLL.PLLM = 8;
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/TOOLCHAIN_ARM_MICRO/startup_stm32f410rx.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,374 @@ +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f410rx.s +;* Author : MCD Application Team +;* Description : STM32F410Rx devices vector table for MDK-ARM_MICRO toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20008000 ; Top of RAM + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM5_IRQHandler ; TIM5 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC + DCD 0 ; Reserved + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD RNG_IRQHandler ; RNG + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI5_IRQHandler ; SPI5 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FMPI2C1_EV_IRQHandler ; FMPI2C1 Event + DCD FMPI2C1_ER_IRQHandler ; FMPI2C1 Error + DCD LPTIM1_IRQHandler ; LP TIM1 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT FMPI2C1_EV_IRQHandler [WEAK] + EXPORT FMPI2C1_ER_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +DMA1_Stream7_IRQHandler +TIM5_IRQHandler +TIM6_DAC_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +RNG_IRQHandler +FPU_IRQHandler +SPI5_IRQHandler +FMPI2C1_EV_IRQHandler +FMPI2C1_ER_IRQHandler +LPTIM1_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/TOOLCHAIN_ARM_MICRO/startup_stm32f410xx.S Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,376 +0,0 @@ -;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** -;* File Name : startup_stm32f410rx.s -;* Author : MCD Application Team -;* Version : V2.4.1 -;* Date : 09-October-2015 -;* Description : STM32F410Rx devices vector table for MDK-ARM_MICRO toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM4 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;******************************************************************************* - -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; <h> Stack Configuration -; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; </h> - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 - EXPORT __initial_sp - -Stack_Mem SPACE Stack_Size -__initial_sp EQU 0x20008000 ; Top of RAM - - -; <h> Heap Configuration -; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; </h> - -Heap_Size EQU 0x00000200 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 - EXPORT __heap_base - EXPORT __heap_limit - -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit EQU (__initial_sp - Stack_Size) - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_IRQHandler ; TIM1 Update - DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD 0 ; Reserved - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD TIM5_IRQHandler ; TIM5 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC - DCD 0 ; Reserved - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD RNG_IRQHandler ; RNG - DCD FPU_IRQHandler ; FPU - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SPI5_IRQHandler ; SPI5 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD FMPI2C1_EV_IRQHandler ; FMPI2C1 Event - DCD FMPI2C1_ER_IRQHandler ; FMPI2C1 Error - DCD LPTIM1_IRQHandler ; LP TIM1 - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMP_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Stream0_IRQHandler [WEAK] - EXPORT DMA1_Stream1_IRQHandler [WEAK] - EXPORT DMA1_Stream2_IRQHandler [WEAK] - EXPORT DMA1_Stream3_IRQHandler [WEAK] - EXPORT DMA1_Stream4_IRQHandler [WEAK] - EXPORT DMA1_Stream5_IRQHandler [WEAK] - EXPORT DMA1_Stream6_IRQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] - EXPORT TIM1_UP_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT DMA1_Stream7_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] - EXPORT TIM6_DAC_IRQHandler [WEAK] - EXPORT DMA2_Stream0_IRQHandler [WEAK] - EXPORT DMA2_Stream1_IRQHandler [WEAK] - EXPORT DMA2_Stream2_IRQHandler [WEAK] - EXPORT DMA2_Stream3_IRQHandler [WEAK] - EXPORT DMA2_Stream4_IRQHandler [WEAK] - EXPORT DMA2_Stream4_IRQHandler [WEAK] - EXPORT DMA2_Stream5_IRQHandler [WEAK] - EXPORT DMA2_Stream6_IRQHandler [WEAK] - EXPORT DMA2_Stream7_IRQHandler [WEAK] - EXPORT USART6_IRQHandler [WEAK] - EXPORT RNG_IRQHandler [WEAK] - EXPORT FPU_IRQHandler [WEAK] - EXPORT SPI5_IRQHandler [WEAK] - EXPORT FMPI2C1_EV_IRQHandler [WEAK] - EXPORT FMPI2C1_ER_IRQHandler [WEAK] - EXPORT LPTIM1_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMP_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Stream0_IRQHandler -DMA1_Stream1_IRQHandler -DMA1_Stream2_IRQHandler -DMA1_Stream3_IRQHandler -DMA1_Stream4_IRQHandler -DMA1_Stream5_IRQHandler -DMA1_Stream6_IRQHandler -ADC_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_TIM9_IRQHandler -TIM1_UP_IRQHandler -TIM1_TRG_COM_TIM11_IRQHandler -TIM1_CC_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -DMA1_Stream7_IRQHandler -TIM5_IRQHandler -TIM6_DAC_IRQHandler -DMA2_Stream0_IRQHandler -DMA2_Stream1_IRQHandler -DMA2_Stream2_IRQHandler -DMA2_Stream3_IRQHandler -DMA2_Stream4_IRQHandler -DMA2_Stream5_IRQHandler -DMA2_Stream6_IRQHandler -DMA2_Stream7_IRQHandler -USART6_IRQHandler -RNG_IRQHandler -FPU_IRQHandler -SPI5_IRQHandler -FMPI2C1_EV_IRQHandler -FMPI2C1_ER_IRQHandler -LPTIM1_IRQHandler - - B . - - ENDP - - ALIGN - END - -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/TOOLCHAIN_ARM_STD/startup_stm32f410rx.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,348 @@ +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f410rx.s +;* Author : MCD Application Team +;* Description : STM32F410Rx devices vector table for MDK-ARM_STD toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + + +__initial_sp EQU 0x20008000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM5_IRQHandler ; TIM5 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC + DCD 0 ; Reserved + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD RNG_IRQHandler ; RNG + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI5_IRQHandler ; SPI5 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FMPI2C1_EV_IRQHandler ; FMPI2C1 Event + DCD FMPI2C1_ER_IRQHandler ; FMPI2C1 Error + DCD LPTIM1_IRQHandler ; LP TIM1 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT FMPI2C1_EV_IRQHandler [WEAK] + EXPORT FMPI2C1_ER_IRQHandler [WEAK] + EXPORT LPTIM1_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +DMA1_Stream7_IRQHandler +TIM5_IRQHandler +TIM6_DAC_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +RNG_IRQHandler +FPU_IRQHandler +SPI5_IRQHandler +FMPI2C1_EV_IRQHandler +FMPI2C1_ER_IRQHandler +LPTIM1_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/TOOLCHAIN_ARM_STD/startup_stm32f410xx.S Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,350 +0,0 @@ -;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** -;* File Name : startup_stm32f410rx.s -;* Author : MCD Application Team -;* Version : V2.4.1 -;* Date : 09-October-2015 -;* Description : STM32F410Rx devices vector table for MDK-ARM_STD toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM4 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;******************************************************************************* - - -__initial_sp EQU 0x20008000 ; Top of RAM - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_IRQHandler ; TIM1 Update - DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD 0 ; Reserved - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD TIM5_IRQHandler ; TIM5 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC - DCD 0 ; Reserved - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD RNG_IRQHandler ; RNG - DCD FPU_IRQHandler ; FPU - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SPI5_IRQHandler ; SPI5 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD FMPI2C1_EV_IRQHandler ; FMPI2C1 Event - DCD FMPI2C1_ER_IRQHandler ; FMPI2C1 Error - DCD LPTIM1_IRQHandler ; LP TIM1 - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMP_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Stream0_IRQHandler [WEAK] - EXPORT DMA1_Stream1_IRQHandler [WEAK] - EXPORT DMA1_Stream2_IRQHandler [WEAK] - EXPORT DMA1_Stream3_IRQHandler [WEAK] - EXPORT DMA1_Stream4_IRQHandler [WEAK] - EXPORT DMA1_Stream5_IRQHandler [WEAK] - EXPORT DMA1_Stream6_IRQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] - EXPORT TIM1_UP_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT DMA1_Stream7_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] - EXPORT TIM6_DAC_IRQHandler [WEAK] - EXPORT DMA2_Stream0_IRQHandler [WEAK] - EXPORT DMA2_Stream1_IRQHandler [WEAK] - EXPORT DMA2_Stream2_IRQHandler [WEAK] - EXPORT DMA2_Stream3_IRQHandler [WEAK] - EXPORT DMA2_Stream4_IRQHandler [WEAK] - EXPORT DMA2_Stream4_IRQHandler [WEAK] - EXPORT DMA2_Stream5_IRQHandler [WEAK] - EXPORT DMA2_Stream6_IRQHandler [WEAK] - EXPORT DMA2_Stream7_IRQHandler [WEAK] - EXPORT USART6_IRQHandler [WEAK] - EXPORT RNG_IRQHandler [WEAK] - EXPORT FPU_IRQHandler [WEAK] - EXPORT SPI5_IRQHandler [WEAK] - EXPORT FMPI2C1_EV_IRQHandler [WEAK] - EXPORT FMPI2C1_ER_IRQHandler [WEAK] - EXPORT LPTIM1_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMP_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Stream0_IRQHandler -DMA1_Stream1_IRQHandler -DMA1_Stream2_IRQHandler -DMA1_Stream3_IRQHandler -DMA1_Stream4_IRQHandler -DMA1_Stream5_IRQHandler -DMA1_Stream6_IRQHandler -ADC_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_TIM9_IRQHandler -TIM1_UP_IRQHandler -TIM1_TRG_COM_TIM11_IRQHandler -TIM1_CC_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -DMA1_Stream7_IRQHandler -TIM5_IRQHandler -TIM6_DAC_IRQHandler -DMA2_Stream0_IRQHandler -DMA2_Stream1_IRQHandler -DMA2_Stream2_IRQHandler -DMA2_Stream3_IRQHandler -DMA2_Stream4_IRQHandler -DMA2_Stream5_IRQHandler -DMA2_Stream6_IRQHandler -DMA2_Stream7_IRQHandler -USART6_IRQHandler -RNG_IRQHandler -FPU_IRQHandler -SPI5_IRQHandler -FMPI2C1_EV_IRQHandler -FMPI2C1_ER_IRQHandler -LPTIM1_IRQHandler - - B . - - ENDP - - ALIGN - END - -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/TOOLCHAIN_GCC_ARM/startup_stm32f410rx.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,452 @@ +/** + ****************************************************************************** + * @file startup_stm32f410rx.s + * @author MCD Application Team + * @brief STM32F410Rx Devices vector table for GCC based toolchains. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * <h2><center>© COPYRIGHT 2017 STMicroelectronics</center></h2> + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + //bl __libc_init_array +/* Call the application's entry point.*/ + //bl main + // Calling the crt0 'cold-start' entry point. There __libc_init_array is called + // and when existing hardware_init_hook() and software_init_hook() before + // starting main(). software_init_hook() is available and has to be called due + // to initializsation when using rtos. + bl _start + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_IRQHandler /* TIM1 Update */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word 0 /* Reserved */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word TIM5_IRQHandler /* TIM5 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC */ + .word 0 /* Reserved */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word RNG_IRQHandler /* RNG */ + .word FPU_IRQHandler /* FPU */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SPI5_IRQHandler /* SPI5 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word FMPI2C1_EV_IRQHandler /* FMPI2C1 Event */ + .word FMPI2C1_ER_IRQHandler /* FMPI2C1 Error */ + .word LPTIM1_IRQHandler /* LP TIM1 */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_IRQHandler + .thumb_set TIM1_UP_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak FMPI2C1_EV_IRQHandler + .thumb_set FMPI2C1_EV_IRQHandler,Default_Handler + + .weak FMPI2C1_ER_IRQHandler + .thumb_set FMPI2C1_ER_IRQHandler,Default_Handler + + .weak LPTIM1_IRQHandler + .thumb_set LPTIM1_IRQHandler,Default_Handler +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/TOOLCHAIN_GCC_ARM/startup_stm32f410xx.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,439 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32f410rx.s - * @author MCD Application Team - * @version V2.4.1 - * @date 09-October-2015 - * @brief STM32F410Rx Devices vector table for GCC based toolchains. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M4 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m4 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ - -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - ldr sp, =_estack /* set stack pointer */ - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call static constructors */ - //bl __libc_init_array -/* Call the application's entry point.*/ - //bl main - // Calling the crt0 'cold-start' entry point. There __libc_init_array is called - // and when existing hardware_init_hook() and software_init_hook() before - // starting main(). software_init_hook() is available and has to be called due - // to initializsation when using rtos. - bl _start - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -*******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - - /* External Interrupts */ - .word WWDG_IRQHandler /* Window WatchDog */ - .word PVD_IRQHandler /* PVD through EXTI Line detection */ - .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ - .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ - .word FLASH_IRQHandler /* FLASH */ - .word RCC_IRQHandler /* RCC */ - .word EXTI0_IRQHandler /* EXTI Line0 */ - .word EXTI1_IRQHandler /* EXTI Line1 */ - .word EXTI2_IRQHandler /* EXTI Line2 */ - .word EXTI3_IRQHandler /* EXTI Line3 */ - .word EXTI4_IRQHandler /* EXTI Line4 */ - .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ - .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ - .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ - .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ - .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ - .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ - .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ - .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word EXTI9_5_IRQHandler /* External Line[9:5]s */ - .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ - .word TIM1_UP_IRQHandler /* TIM1 Update */ - .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ - .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word I2C1_EV_IRQHandler /* I2C1 Event */ - .word I2C1_ER_IRQHandler /* I2C1 Error */ - .word I2C2_EV_IRQHandler /* I2C2 Event */ - .word I2C2_ER_IRQHandler /* I2C2 Error */ - .word SPI1_IRQHandler /* SPI1 */ - .word SPI2_IRQHandler /* SPI2 */ - .word USART1_IRQHandler /* USART1 */ - .word USART2_IRQHandler /* USART2 */ - .word 0 /* Reserved */ - .word EXTI15_10_IRQHandler /* External Line[15:10]s */ - .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word TIM5_IRQHandler /* TIM5 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word TIM6_DAC_IRQHandler /* TIM6 and DAC */ - .word 0 /* Reserved */ - .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ - .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ - .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ - .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ - .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ - .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ - .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ - .word USART6_IRQHandler /* USART6 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word RNG_IRQHandler /* RNG */ - .word FPU_IRQHandler /* FPU */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word SPI5_IRQHandler /* SPI5 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word FMPI2C1_EV_IRQHandler /* FMPI2C1 Event */ - .word FMPI2C1_ER_IRQHandler /* FMPI2C1 Error */ - .word LPTIM1_IRQHandler /* LP TIM1 */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMP_STAMP_IRQHandler - .thumb_set TAMP_STAMP_IRQHandler,Default_Handler - - .weak RTC_WKUP_IRQHandler - .thumb_set RTC_WKUP_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Stream0_IRQHandler - .thumb_set DMA1_Stream0_IRQHandler,Default_Handler - - .weak DMA1_Stream1_IRQHandler - .thumb_set DMA1_Stream1_IRQHandler,Default_Handler - - .weak DMA1_Stream2_IRQHandler - .thumb_set DMA1_Stream2_IRQHandler,Default_Handler - - .weak DMA1_Stream3_IRQHandler - .thumb_set DMA1_Stream3_IRQHandler,Default_Handler - - .weak DMA1_Stream4_IRQHandler - .thumb_set DMA1_Stream4_IRQHandler,Default_Handler - - .weak DMA1_Stream5_IRQHandler - .thumb_set DMA1_Stream5_IRQHandler,Default_Handler - - .weak DMA1_Stream6_IRQHandler - .thumb_set DMA1_Stream6_IRQHandler,Default_Handler - - .weak ADC_IRQHandler - .thumb_set ADC_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM1_BRK_TIM9_IRQHandler - .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler - - .weak TIM1_UP_IRQHandler - .thumb_set TIM1_UP_IRQHandler,Default_Handler - - .weak TIM1_TRG_COM_TIM11_IRQHandler - .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTC_Alarm_IRQHandler - .thumb_set RTC_Alarm_IRQHandler,Default_Handler - - .weak DMA1_Stream7_IRQHandler - .thumb_set DMA1_Stream7_IRQHandler,Default_Handler - - .weak TIM5_IRQHandler - .thumb_set TIM5_IRQHandler,Default_Handler - - .weak TIM6_DAC_IRQHandler - .thumb_set TIM6_DAC_IRQHandler,Default_Handler - - .weak DMA2_Stream0_IRQHandler - .thumb_set DMA2_Stream0_IRQHandler,Default_Handler - - .weak DMA2_Stream1_IRQHandler - .thumb_set DMA2_Stream1_IRQHandler,Default_Handler - - .weak DMA2_Stream2_IRQHandler - .thumb_set DMA2_Stream2_IRQHandler,Default_Handler - - .weak DMA2_Stream3_IRQHandler - .thumb_set DMA2_Stream3_IRQHandler,Default_Handler - - .weak DMA2_Stream4_IRQHandler - .thumb_set DMA2_Stream4_IRQHandler,Default_Handler - - .weak DMA2_Stream5_IRQHandler - .thumb_set DMA2_Stream5_IRQHandler,Default_Handler - - .weak DMA2_Stream6_IRQHandler - .thumb_set DMA2_Stream6_IRQHandler,Default_Handler - - .weak DMA2_Stream7_IRQHandler - .thumb_set DMA2_Stream7_IRQHandler,Default_Handler - - .weak USART6_IRQHandler - .thumb_set USART6_IRQHandler,Default_Handler - - .weak RNG_IRQHandler - .thumb_set RNG_IRQHandler,Default_Handler - - .weak FPU_IRQHandler - .thumb_set FPU_IRQHandler,Default_Handler - - .weak SPI5_IRQHandler - .thumb_set SPI5_IRQHandler,Default_Handler - - .weak FMPI2C1_EV_IRQHandler - .thumb_set FMPI2C1_EV_IRQHandler,Default_Handler - - .weak FMPI2C1_ER_IRQHandler - .thumb_set FMPI2C1_ER_IRQHandler,Default_Handler - - .weak LPTIM1_IRQHandler - .thumb_set LPTIM1_IRQHandler,Default_Handler -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/TOOLCHAIN_IAR/startup_stm32f410rx.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,508 @@ +;/******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f410rx.s +;* Author : MCD Application Team +;* Description : STM32F410Rx devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Configure the system clock +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_IRQHandler ; TIM1 Update + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD 0 ; Reserved + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM5_IRQHandler ; TIM5 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC + DCD 0 ; Reserved + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD RNG_IRQHandler ; RNG + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI5_IRQHandler ; SPI5 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FMPI2C1_EV_IRQHandler ; FMPI2C1 Event + DCD FMPI2C1_ER_IRQHandler ; FMPI2C1 Error + DCD LPTIM1_IRQHandler ; LP TIM1 + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream0_IRQHandler + B DMA1_Stream0_IRQHandler + + PUBWEAK DMA1_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream1_IRQHandler + B DMA1_Stream1_IRQHandler + + PUBWEAK DMA1_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream2_IRQHandler + B DMA1_Stream2_IRQHandler + + PUBWEAK DMA1_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream3_IRQHandler + B DMA1_Stream3_IRQHandler + + PUBWEAK DMA1_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream4_IRQHandler + B DMA1_Stream4_IRQHandler + + PUBWEAK DMA1_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream5_IRQHandler + B DMA1_Stream5_IRQHandler + + PUBWEAK DMA1_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream6_IRQHandler + B DMA1_Stream6_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_BRK_TIM9_IRQHandler + B TIM1_BRK_TIM9_IRQHandler + + PUBWEAK TIM1_UP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_UP_IRQHandler + B TIM1_UP_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_TRG_COM_TIM11_IRQHandler + B TIM1_TRG_COM_TIM11_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK DMA1_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream7_IRQHandler + B DMA1_Stream7_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK DMA2_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream0_IRQHandler + B DMA2_Stream0_IRQHandler + + PUBWEAK DMA2_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream1_IRQHandler + B DMA2_Stream1_IRQHandler + + PUBWEAK DMA2_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream2_IRQHandler + B DMA2_Stream2_IRQHandler + + PUBWEAK DMA2_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream3_IRQHandler + B DMA2_Stream3_IRQHandler + + PUBWEAK DMA2_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream4_IRQHandler + B DMA2_Stream4_IRQHandler + + PUBWEAK DMA2_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream5_IRQHandler + B DMA2_Stream5_IRQHandler + + PUBWEAK DMA2_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream6_IRQHandler + B DMA2_Stream6_IRQHandler + + PUBWEAK DMA2_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream7_IRQHandler + B DMA2_Stream7_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK RNG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RNG_IRQHandler + B RNG_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK SPI5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI5_IRQHandler + B SPI5_IRQHandler + + PUBWEAK FMPI2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FMPI2C1_EV_IRQHandler + B FMPI2C1_EV_IRQHandler + + PUBWEAK FMPI2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FMPI2C1_ER_IRQHandler + B FMPI2C1_ER_IRQHandler + + PUBWEAK LPTIM1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LPTIM1_IRQHandler + B LPTIM1_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/TOOLCHAIN_IAR/startup_stm32f410xx.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,510 +0,0 @@ -;/******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** -;* File Name : startup_stm32f410rx.s -;* Author : MCD Application Team -;* Version : V2.4.1 -;* Date : 09-October-2015 -;* Description : STM32F410Rx devices vector table for EWARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == _iar_program_start, -;* - Set the vector table entries with the exceptions ISR -;* address. -;* - Configure the system clock -;* - Branches to main in the C library (which eventually -;* calls main()). -;* After Reset the Cortex-M4 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;******************************************************************************** -;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;* -;******************************************************************************* -; -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler ; Reset Handler - - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_IRQHandler ; TIM1 Update - DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD 0 ; Reserved - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD TIM5_IRQHandler ; TIM5 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC - DCD 0 ; Reserved - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD RNG_IRQHandler ; RNG - DCD FPU_IRQHandler ; FPU - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SPI5_IRQHandler ; SPI5 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD FMPI2C1_EV_IRQHandler ; FMPI2C1 Event - DCD FMPI2C1_ER_IRQHandler ; FMPI2C1 Error - DCD LPTIM1_IRQHandler ; LP TIM1 - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK WWDG_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -WWDG_IRQHandler - B WWDG_IRQHandler - - PUBWEAK PVD_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PVD_IRQHandler - B PVD_IRQHandler - - PUBWEAK TAMP_STAMP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TAMP_STAMP_IRQHandler - B TAMP_STAMP_IRQHandler - - PUBWEAK RTC_WKUP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC_WKUP_IRQHandler - B RTC_WKUP_IRQHandler - - PUBWEAK FLASH_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FLASH_IRQHandler - B FLASH_IRQHandler - - PUBWEAK RCC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RCC_IRQHandler - B RCC_IRQHandler - - PUBWEAK EXTI0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI0_IRQHandler - B EXTI0_IRQHandler - - PUBWEAK EXTI1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI1_IRQHandler - B EXTI1_IRQHandler - - PUBWEAK EXTI2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI2_IRQHandler - B EXTI2_IRQHandler - - PUBWEAK EXTI3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI3_IRQHandler - B EXTI3_IRQHandler - - PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI4_IRQHandler - B EXTI4_IRQHandler - - PUBWEAK DMA1_Stream0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream0_IRQHandler - B DMA1_Stream0_IRQHandler - - PUBWEAK DMA1_Stream1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream1_IRQHandler - B DMA1_Stream1_IRQHandler - - PUBWEAK DMA1_Stream2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream2_IRQHandler - B DMA1_Stream2_IRQHandler - - PUBWEAK DMA1_Stream3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream3_IRQHandler - B DMA1_Stream3_IRQHandler - - PUBWEAK DMA1_Stream4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream4_IRQHandler - B DMA1_Stream4_IRQHandler - - PUBWEAK DMA1_Stream5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream5_IRQHandler - B DMA1_Stream5_IRQHandler - - PUBWEAK DMA1_Stream6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream6_IRQHandler - B DMA1_Stream6_IRQHandler - - PUBWEAK ADC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ADC_IRQHandler - B ADC_IRQHandler - - PUBWEAK EXTI9_5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI9_5_IRQHandler - B EXTI9_5_IRQHandler - - PUBWEAK TIM1_BRK_TIM9_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM1_BRK_TIM9_IRQHandler - B TIM1_BRK_TIM9_IRQHandler - - PUBWEAK TIM1_UP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM1_UP_IRQHandler - B TIM1_UP_IRQHandler - - PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM1_TRG_COM_TIM11_IRQHandler - B TIM1_TRG_COM_TIM11_IRQHandler - - PUBWEAK TIM1_CC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM1_CC_IRQHandler - B TIM1_CC_IRQHandler - - PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C1_EV_IRQHandler - B I2C1_EV_IRQHandler - - PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C1_ER_IRQHandler - B I2C1_ER_IRQHandler - - PUBWEAK I2C2_EV_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C2_EV_IRQHandler - B I2C2_EV_IRQHandler - - PUBWEAK I2C2_ER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C2_ER_IRQHandler - B I2C2_ER_IRQHandler - - PUBWEAK SPI1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI1_IRQHandler - B SPI1_IRQHandler - - PUBWEAK SPI2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI2_IRQHandler - B SPI2_IRQHandler - - PUBWEAK USART1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART1_IRQHandler - B USART1_IRQHandler - - PUBWEAK USART2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART2_IRQHandler - B USART2_IRQHandler - - PUBWEAK EXTI15_10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI15_10_IRQHandler - B EXTI15_10_IRQHandler - - PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC_Alarm_IRQHandler - B RTC_Alarm_IRQHandler - - PUBWEAK DMA1_Stream7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream7_IRQHandler - B DMA1_Stream7_IRQHandler - - PUBWEAK TIM5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM5_IRQHandler - B TIM5_IRQHandler - - PUBWEAK TIM6_DAC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM6_DAC_IRQHandler - B TIM6_DAC_IRQHandler - - PUBWEAK DMA2_Stream0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream0_IRQHandler - B DMA2_Stream0_IRQHandler - - PUBWEAK DMA2_Stream1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream1_IRQHandler - B DMA2_Stream1_IRQHandler - - PUBWEAK DMA2_Stream2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream2_IRQHandler - B DMA2_Stream2_IRQHandler - - PUBWEAK DMA2_Stream3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream3_IRQHandler - B DMA2_Stream3_IRQHandler - - PUBWEAK DMA2_Stream4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream4_IRQHandler - B DMA2_Stream4_IRQHandler - - PUBWEAK DMA2_Stream5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream5_IRQHandler - B DMA2_Stream5_IRQHandler - - PUBWEAK DMA2_Stream6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream6_IRQHandler - B DMA2_Stream6_IRQHandler - - PUBWEAK DMA2_Stream7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream7_IRQHandler - B DMA2_Stream7_IRQHandler - - PUBWEAK USART6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART6_IRQHandler - B USART6_IRQHandler - - PUBWEAK RNG_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RNG_IRQHandler - B RNG_IRQHandler - - PUBWEAK FPU_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FPU_IRQHandler - B FPU_IRQHandler - - PUBWEAK SPI5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI5_IRQHandler - B SPI5_IRQHandler - - PUBWEAK FMPI2C1_EV_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FMPI2C1_EV_IRQHandler - B FMPI2C1_EV_IRQHandler - - PUBWEAK FMPI2C1_ER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FMPI2C1_ER_IRQHandler - B FMPI2C1_ER_IRQHandler - - PUBWEAK LPTIM1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LPTIM1_IRQHandler - B LPTIM1_IRQHandler - - END -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/stm32f410rx.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/stm32f410rx.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f410rx.h * @author MCD Application Team - * @version V2.6.1 - * @date 14-February-2017 * @brief CMSIS STM32F410Rx Device Peripheral Access Layer Header File. * * This file contains: @@ -67,9 +65,11 @@ #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */ #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +/* MBED */ #ifndef __FPU_PRESENT #define __FPU_PRESENT 1U /*!< FPU present */ #endif /* __FPU_PRESENT */ +/* MBED */ /** * @} @@ -4199,9 +4199,15 @@ #define PWR_CSR_BRR_Pos (3U) #define PWR_CSR_BRR_Msk (0x1U << PWR_CSR_BRR_Pos) /*!< 0x00000008 */ #define PWR_CSR_BRR PWR_CSR_BRR_Msk /*!< Backup regulator ready */ -#define PWR_CSR_EWUP_Pos (8U) -#define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */ -#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */ +#define PWR_CSR_EWUP3_Pos (6U) +#define PWR_CSR_EWUP3_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000040 */ +#define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */ +#define PWR_CSR_EWUP2_Pos (7U) +#define PWR_CSR_EWUP2_Msk (0x1U << PWR_CSR_EWUP2_Pos) /*!< 0x00000080 */ +#define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */ +#define PWR_CSR_EWUP1_Pos (8U) +#define PWR_CSR_EWUP1_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */ +#define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */ #define PWR_CSR_BRE_Pos (9U) #define PWR_CSR_BRE_Msk (0x1U << PWR_CSR_BRE_Pos) /*!< 0x00000200 */ #define PWR_CSR_BRE PWR_CSR_BRE_Msk /*!< Backup regulator enable */ @@ -6789,7 +6795,7 @@ #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */ #define USART_CR1_TXEIE_Pos (7U) #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */ -#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<PE Interrupt Enable */ +#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<TXE Interrupt Enable */ #define USART_CR1_PEIE_Pos (8U) #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */ #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */ @@ -7043,7 +7049,6 @@ #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos (18U) #define DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk (0x1U << DBGMCU_APB2_FZ_DBG_TIM11_STOP_Pos) /*!< 0x00040000 */ #define DBGMCU_APB2_FZ_DBG_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP_Msk - /** * @} */
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/stm32f4xx.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/stm32f4xx.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,23 +2,21 @@
******************************************************************************
* @file stm32f4xx.h
* @author MCD Application Team
- * @version V2.6.1
- * @date 14-February-2017
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
* is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select:
* - The STM32F4xx device used in the target application
- * - To use or not the peripherals drivers in application code(i.e.
- * code will be based on direct access to peripherals registers
+ * - To use or not the peripheral's drivers in application code(i.e.
+ * code will be based on direct access to peripheral's registers
* rather than drivers API), this option is controlled by
* "#define USE_HAL_DRIVER"
*
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -124,11 +122,11 @@
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS version number V2.6.1
+ * @brief CMSIS version number V2.6.2
*/
#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
-#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
@@ -202,20 +200,20 @@
*/
typedef enum
{
- RESET = 0,
+ RESET = 0U,
SET = !RESET
} FlagStatus, ITStatus;
typedef enum
{
- DISABLE = 0,
+ DISABLE = 0U,
ENABLE = !DISABLE
} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
typedef enum
{
- ERROR = 0,
+ ERROR = 0U,
SUCCESS = !ERROR
} ErrorStatus;
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/system_stm32f4xx.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F410xB/device/system_stm32f4xx.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,13 +2,11 @@ ****************************************************************************** * @file system_stm32f4xx.h * @author MCD Application Team - * @version V2.6.1 - * @date 14-February-2017 * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met:
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/system_clock.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_ELMO_F411RE/system_clock.c Tue Mar 20 16:56:18 2018 +0000
@@ -213,7 +213,7 @@
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
- RCC_OscInitStruct.HSICalibrationValue = 16;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
//RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_NUCLEO_F411RE/system_clock.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_NUCLEO_F411RE/system_clock.c Tue Mar 20 16:56:18 2018 +0000
@@ -212,7 +212,7 @@
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
- RCC_OscInitStruct.HSICalibrationValue = 16;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8)
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_SAKURAIO_EVB_01/system_clock.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/TARGET_SAKURAIO_EVB_01/system_clock.c Tue Mar 20 16:56:18 2018 +0000
@@ -212,7 +212,7 @@
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
- RCC_OscInitStruct.HSICalibrationValue = 16;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8)
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/TOOLCHAIN_ARM_MICRO/startup_stm32f411xe.S Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/TOOLCHAIN_ARM_MICRO/startup_stm32f411xe.S Tue Mar 20 16:56:18 2018 +0000 @@ -1,8 +1,6 @@ -;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** ;* File Name : startup_stm32f411xe.s ;* Author : MCD Application Team -;* Version : V2.1.0 -;* Date : 19-June-2014 ;* Description : STM32F411xExx devices vector table for MDK-ARM_MICRO toolchain. ;* This module performs: ;* - Set the initial SP
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/TOOLCHAIN_ARM_STD/startup_stm32f411xe.S Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/TOOLCHAIN_ARM_STD/startup_stm32f411xe.S Tue Mar 20 16:56:18 2018 +0000 @@ -1,8 +1,6 @@ -;******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** ;* File Name : startup_stm32f411xe.s ;* Author : MCD Application Team -;* Version : V2.1.0 -;* Date : 19-June-2014 ;* Description : STM32F411xExx devices vector table for MDK-ARM_STD toolchain. ;* This module performs: ;* - Set the initial SP
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/TOOLCHAIN_GCC_ARM/startup_stm32f411xe.S Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/TOOLCHAIN_GCC_ARM/startup_stm32f411xe.S Tue Mar 20 16:56:18 2018 +0000 @@ -2,9 +2,7 @@ ****************************************************************************** * @file startup_stm32f411xe.s * @author MCD Application Team - * @version V2.3.0 - * @date 02-March-2015 - * @brief STM32F411xExx Devices vector table for Atollic TrueSTUDIO toolchain. + * @brief STM32F411xExx Devices vector table for GCC based toolchains. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, @@ -16,7 +14,7 @@ ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2017 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -58,6 +56,10 @@ .word _sdata /* end address for the .data section. defined in linker script */ .word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss /* stack used for SystemInit_ExtMemCtl; always internal RAM used */ /** @@ -91,6 +93,17 @@ adds r2, r0, r1 cmp r2, r3 bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss /* Call the clock system intitialization function.*/ bl SystemInit
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/TOOLCHAIN_IAR/startup_stm32f411xe.S Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/TOOLCHAIN_IAR/startup_stm32f411xe.S Tue Mar 20 16:56:18 2018 +0000 @@ -1,8 +1,6 @@ -;/******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;/******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** ;* File Name : startup_stm32f411xe.s ;* Author : MCD Application Team -;* Version : V2.1.0 -;* Date : 19-June-2014 ;* Description : STM32F411xExx devices vector table for EWARM toolchain. ;* This module performs: ;* - Set the initial SP
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/stm32f411xe.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/stm32f411xe.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f411xe.h * @author MCD Application Team - * @version V2.6.1 - * @date 14-February-2017 * @brief CMSIS STM32F411xE Device Peripheral Access Layer Header File. * * This file contains: @@ -67,9 +65,11 @@ #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */ #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +/* MBED */ #ifndef __FPU_PRESENT #define __FPU_PRESENT 1U /*!< FPU present */ #endif /* __FPU_PRESENT */ +/* MBED */ /** * @} @@ -657,7 +657,6 @@ #define FLASH_BASE 0x08000000U /*!< FLASH(up to 1 MB) base address in the alias region */ #define SRAM1_BASE 0x20000000U /*!< SRAM1(128 KB) base address in the alias region */ #define PERIPH_BASE 0x40000000U /*!< Peripheral base address in the alias region */ -#define BKPSRAM_BASE 0x40024000U /*!< Backup SRAM(4 KB) base address in the alias region */ #define SRAM1_BB_BASE 0x22000000U /*!< SRAM1(128 KB) base address in the bit-band region */ #define PERIPH_BB_BASE 0x42000000U /*!< Peripheral base address in the bit-band region */ #define BKPSRAM_BB_BASE 0x42480000U /*!< Backup SRAM(4 KB) base address in the bit-band region */ @@ -6710,7 +6709,7 @@ #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */ #define USART_CR1_TXEIE_Pos (7U) #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */ -#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<PE Interrupt Enable */ +#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<TXE Interrupt Enable */ #define USART_CR1_PEIE_Pos (8U) #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */ #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */ @@ -7545,92 +7544,6 @@ #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */ #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */ -/******************** Bit definition for OTG register ********************/ - -#define USB_OTG_CHNUM_Pos (0U) -#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */ -#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */ -#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */ -#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */ -#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */ -#define USB_OTG_BCNT_Pos (4U) -#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */ - -#define USB_OTG_DPID_Pos (15U) -#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */ -#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */ -#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */ - -#define USB_OTG_PKTSTS_Pos (17U) -#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */ -#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */ -#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */ -#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */ -#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */ - -#define USB_OTG_EPNUM_Pos (0U) -#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */ -#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */ -#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */ -#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */ -#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */ - -#define USB_OTG_FRMNUM_Pos (21U) -#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */ -#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */ -#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */ -#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */ -#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */ -#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */ - -/******************** Bit definition for OTG register ********************/ - -#define USB_OTG_CHNUM_Pos (0U) -#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */ -#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */ -#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */ -#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */ -#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */ -#define USB_OTG_BCNT_Pos (4U) -#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */ - -#define USB_OTG_DPID_Pos (15U) -#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */ -#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */ -#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */ - -#define USB_OTG_PKTSTS_Pos (17U) -#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */ -#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */ -#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */ -#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */ -#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */ - -#define USB_OTG_EPNUM_Pos (0U) -#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */ -#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */ -#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */ -#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */ -#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */ - -#define USB_OTG_FRMNUM_Pos (21U) -#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */ -#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */ -#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */ -#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */ -#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */ -#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */ - /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/ #define USB_OTG_GRXFSIZ_RXFD_Pos (0U) #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */ @@ -8276,6 +8189,48 @@ #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */ #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */ +/* Legacy define */ +/******************** Bit definition for OTG register ********************/ +#define USB_OTG_CHNUM_Pos (0U) +#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */ +#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */ +#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */ +#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */ +#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */ +#define USB_OTG_BCNT_Pos (4U) +#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */ + +#define USB_OTG_DPID_Pos (15U) +#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */ +#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */ +#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */ + +#define USB_OTG_PKTSTS_Pos (17U) +#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */ +#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */ +#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */ +#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */ + +#define USB_OTG_EPNUM_Pos (0U) +#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */ +#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */ +#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */ +#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */ +#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */ + +#define USB_OTG_FRMNUM_Pos (21U) +#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */ +#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */ +#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */ +#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */ /** * @} */
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/stm32f4xx.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/stm32f4xx.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx.h
* @author MCD Application Team
- * @version V2.6.1
- * @date 14-February-2017
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@@ -124,11 +122,11 @@
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS version number V2.6.1
+ * @brief CMSIS version number V2.6.2
*/
#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
-#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/system_stm32f4xx.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F411xE/device/system_stm32f4xx.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file system_stm32f4xx.h * @author MCD Application Team - * @version V2.6.1 - * @date 14-February-2017 * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_MTB_MXCHIP_EMW3166/system_clock.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_MTB_MXCHIP_EMW3166/system_clock.c Tue Mar 20 16:56:18 2018 +0000
@@ -230,7 +230,7 @@
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
- RCC_OscInitStruct.HSICalibrationValue = 16;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8)
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/system_clock.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/TARGET_NUCLEO_F412ZG/system_clock.c Tue Mar 20 16:56:18 2018 +0000
@@ -229,7 +229,7 @@
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
- RCC_OscInitStruct.HSICalibrationValue = 16;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8)
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_ARM_MICRO/startup_stm32f412xx.S Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,427 +0,0 @@ -;******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** -;* File Name : startup_stm32f412zx.s -;* Author : MCD Application Team -;* Version : V2.5.1 -;* Date : 28-June-2016 -;* Description : STM32F412Zx devices vector table for MDK-ARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM4 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;******************************************************************************* - -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; <h> Stack Configuration -; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; </h> - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 - EXPORT __initial_sp - -Stack_Mem SPACE Stack_Size -__initial_sp EQU 0x20040000 ; Top of RAM 256K - - -; <h> Heap Configuration -; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; </h> - -Heap_Size EQU 0x00000400 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 - EXPORT __heap_base - EXPORT __heap_limit - -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit EQU (__initial_sp - Stack_Size) - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 - DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 - DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD 0 ; Reserved - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD TIM6_IRQHandler ; TIM6 - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global interrupt - DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global interrupt - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD RNG_IRQHandler ; RNG - DCD FPU_IRQHandler ; FPU - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SPI4_IRQHandler ; SPI4 - DCD SPI5_IRQHandler ; SPI5 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD QUADSPI_IRQHandler ; QuadSPI - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD FMPI2C1_EV_IRQHandler ; FMPI2C1 Event - DCD FMPI2C1_ER_IRQHandler ; FMPI2C1 Error - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMP_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Stream0_IRQHandler [WEAK] - EXPORT DMA1_Stream1_IRQHandler [WEAK] - EXPORT DMA1_Stream2_IRQHandler [WEAK] - EXPORT DMA1_Stream3_IRQHandler [WEAK] - EXPORT DMA1_Stream4_IRQHandler [WEAK] - EXPORT DMA1_Stream5_IRQHandler [WEAK] - EXPORT DMA1_Stream6_IRQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT CAN1_TX_IRQHandler [WEAK] - EXPORT CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_SCE_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] - EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT OTG_FS_WKUP_IRQHandler [WEAK] - EXPORT OTG_FS_IRQHandler [WEAK] - EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] - EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] - EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] - EXPORT TIM8_CC_IRQHandler [WEAK] - EXPORT DMA1_Stream7_IRQHandler [WEAK] - EXPORT SDIO_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT TIM6_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - EXPORT DMA2_Stream0_IRQHandler [WEAK] - EXPORT DMA2_Stream1_IRQHandler [WEAK] - EXPORT DMA2_Stream2_IRQHandler [WEAK] - EXPORT DMA2_Stream3_IRQHandler [WEAK] - EXPORT DMA2_Stream4_IRQHandler [WEAK] - EXPORT DMA2_Stream4_IRQHandler [WEAK] - EXPORT DFSDM1_FLT0_IRQHandler [WEAK] - EXPORT DFSDM1_FLT1_IRQHandler [WEAK] - EXPORT CAN2_TX_IRQHandler [WEAK] - EXPORT CAN2_RX0_IRQHandler [WEAK] - EXPORT CAN2_RX1_IRQHandler [WEAK] - EXPORT CAN2_SCE_IRQHandler [WEAK] - EXPORT DMA2_Stream5_IRQHandler [WEAK] - EXPORT DMA2_Stream6_IRQHandler [WEAK] - EXPORT DMA2_Stream7_IRQHandler [WEAK] - EXPORT USART6_IRQHandler [WEAK] - EXPORT I2C3_EV_IRQHandler [WEAK] - EXPORT I2C3_ER_IRQHandler [WEAK] - EXPORT RNG_IRQHandler [WEAK] - EXPORT FPU_IRQHandler [WEAK] - EXPORT SPI4_IRQHandler [WEAK] - EXPORT SPI5_IRQHandler [WEAK] - EXPORT QUADSPI_IRQHandler [WEAK] - EXPORT FMPI2C1_EV_IRQHandler [WEAK] - EXPORT FMPI2C1_ER_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMP_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Stream0_IRQHandler -DMA1_Stream1_IRQHandler -DMA1_Stream2_IRQHandler -DMA1_Stream3_IRQHandler -DMA1_Stream4_IRQHandler -DMA1_Stream5_IRQHandler -DMA1_Stream6_IRQHandler -ADC_IRQHandler -CAN1_TX_IRQHandler -CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_SCE_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_TIM9_IRQHandler -TIM1_UP_TIM10_IRQHandler -TIM1_TRG_COM_TIM11_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -OTG_FS_WKUP_IRQHandler -TIM8_BRK_TIM12_IRQHandler -TIM8_UP_TIM13_IRQHandler -TIM8_TRG_COM_TIM14_IRQHandler -TIM8_CC_IRQHandler -DMA1_Stream7_IRQHandler -SDIO_IRQHandler -TIM5_IRQHandler -SPI3_IRQHandler -TIM6_IRQHandler -TIM7_IRQHandler -DMA2_Stream0_IRQHandler -DMA2_Stream1_IRQHandler -DMA2_Stream2_IRQHandler -DMA2_Stream3_IRQHandler -DMA2_Stream4_IRQHandler -DFSDM1_FLT0_IRQHandler -DFSDM1_FLT1_IRQHandler -CAN2_TX_IRQHandler -CAN2_RX0_IRQHandler -CAN2_RX1_IRQHandler -CAN2_SCE_IRQHandler -OTG_FS_IRQHandler -DMA2_Stream5_IRQHandler -DMA2_Stream6_IRQHandler -DMA2_Stream7_IRQHandler -USART6_IRQHandler -I2C3_EV_IRQHandler -I2C3_ER_IRQHandler -RNG_IRQHandler -FPU_IRQHandler -SPI4_IRQHandler -SPI5_IRQHandler -QUADSPI_IRQHandler -FMPI2C1_EV_IRQHandler -FMPI2C1_ER_IRQHandler - - B . - - ENDP - - ALIGN - END - -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_ARM_MICRO/startup_stm32f412zx.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,425 @@ +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f412zx.s +;* Author : MCD Application Team +;* Description : STM32F412Zx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20040000 ; Top of RAM 256K + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD 0 ; Reserved + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global interrupt + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD RNG_IRQHandler ; RNG + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD QUADSPI_IRQHandler ; QuadSPI + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FMPI2C1_EV_IRQHandler ; FMPI2C1 Event + DCD FMPI2C1_ER_IRQHandler ; FMPI2C1 Error + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT DFSDM1_FLT0_IRQHandler [WEAK] + EXPORT DFSDM1_FLT1_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT FMPI2C1_EV_IRQHandler [WEAK] + EXPORT FMPI2C1_ER_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +TIM6_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +DFSDM1_FLT0_IRQHandler +DFSDM1_FLT1_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +RNG_IRQHandler +FPU_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +QUADSPI_IRQHandler +FMPI2C1_EV_IRQHandler +FMPI2C1_ER_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_ARM_STD/startup_stm32f412xx.S Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,400 +0,0 @@ -;******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** -;* File Name : startup_stm32f412zx.s -;* Author : MCD Application Team -;* Version : V2.5.1 -;* Date : 28-June-2016 -;* Description : STM32F412Zx devices vector table for MDK-ARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM4 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;******************************************************************************* - -__initial_sp EQU 0x20040000 ; Top of RAM 256K - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 - DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 - DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD 0 ; Reserved - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD TIM6_IRQHandler ; TIM6 - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global interrupt - DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global interrupt - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD RNG_IRQHandler ; RNG - DCD FPU_IRQHandler ; FPU - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SPI4_IRQHandler ; SPI4 - DCD SPI5_IRQHandler ; SPI5 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD QUADSPI_IRQHandler ; QuadSPI - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD FMPI2C1_EV_IRQHandler ; FMPI2C1 Event - DCD FMPI2C1_ER_IRQHandler ; FMPI2C1 Error - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMP_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Stream0_IRQHandler [WEAK] - EXPORT DMA1_Stream1_IRQHandler [WEAK] - EXPORT DMA1_Stream2_IRQHandler [WEAK] - EXPORT DMA1_Stream3_IRQHandler [WEAK] - EXPORT DMA1_Stream4_IRQHandler [WEAK] - EXPORT DMA1_Stream5_IRQHandler [WEAK] - EXPORT DMA1_Stream6_IRQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT CAN1_TX_IRQHandler [WEAK] - EXPORT CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_SCE_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] - EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT OTG_FS_WKUP_IRQHandler [WEAK] - EXPORT OTG_FS_IRQHandler [WEAK] - EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] - EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] - EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] - EXPORT TIM8_CC_IRQHandler [WEAK] - EXPORT DMA1_Stream7_IRQHandler [WEAK] - EXPORT SDIO_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT TIM6_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - EXPORT DMA2_Stream0_IRQHandler [WEAK] - EXPORT DMA2_Stream1_IRQHandler [WEAK] - EXPORT DMA2_Stream2_IRQHandler [WEAK] - EXPORT DMA2_Stream3_IRQHandler [WEAK] - EXPORT DMA2_Stream4_IRQHandler [WEAK] - EXPORT DMA2_Stream4_IRQHandler [WEAK] - EXPORT DFSDM1_FLT0_IRQHandler [WEAK] - EXPORT DFSDM1_FLT1_IRQHandler [WEAK] - EXPORT CAN2_TX_IRQHandler [WEAK] - EXPORT CAN2_RX0_IRQHandler [WEAK] - EXPORT CAN2_RX1_IRQHandler [WEAK] - EXPORT CAN2_SCE_IRQHandler [WEAK] - EXPORT DMA2_Stream5_IRQHandler [WEAK] - EXPORT DMA2_Stream6_IRQHandler [WEAK] - EXPORT DMA2_Stream7_IRQHandler [WEAK] - EXPORT USART6_IRQHandler [WEAK] - EXPORT I2C3_EV_IRQHandler [WEAK] - EXPORT I2C3_ER_IRQHandler [WEAK] - EXPORT RNG_IRQHandler [WEAK] - EXPORT FPU_IRQHandler [WEAK] - EXPORT SPI4_IRQHandler [WEAK] - EXPORT SPI5_IRQHandler [WEAK] - EXPORT QUADSPI_IRQHandler [WEAK] - EXPORT FMPI2C1_EV_IRQHandler [WEAK] - EXPORT FMPI2C1_ER_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMP_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Stream0_IRQHandler -DMA1_Stream1_IRQHandler -DMA1_Stream2_IRQHandler -DMA1_Stream3_IRQHandler -DMA1_Stream4_IRQHandler -DMA1_Stream5_IRQHandler -DMA1_Stream6_IRQHandler -ADC_IRQHandler -CAN1_TX_IRQHandler -CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_SCE_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_TIM9_IRQHandler -TIM1_UP_TIM10_IRQHandler -TIM1_TRG_COM_TIM11_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -OTG_FS_WKUP_IRQHandler -TIM8_BRK_TIM12_IRQHandler -TIM8_UP_TIM13_IRQHandler -TIM8_TRG_COM_TIM14_IRQHandler -TIM8_CC_IRQHandler -DMA1_Stream7_IRQHandler -SDIO_IRQHandler -TIM5_IRQHandler -SPI3_IRQHandler -TIM6_IRQHandler -TIM7_IRQHandler -DMA2_Stream0_IRQHandler -DMA2_Stream1_IRQHandler -DMA2_Stream2_IRQHandler -DMA2_Stream3_IRQHandler -DMA2_Stream4_IRQHandler -DFSDM1_FLT0_IRQHandler -DFSDM1_FLT1_IRQHandler -CAN2_TX_IRQHandler -CAN2_RX0_IRQHandler -CAN2_RX1_IRQHandler -CAN2_SCE_IRQHandler -OTG_FS_IRQHandler -DMA2_Stream5_IRQHandler -DMA2_Stream6_IRQHandler -DMA2_Stream7_IRQHandler -USART6_IRQHandler -I2C3_EV_IRQHandler -I2C3_ER_IRQHandler -RNG_IRQHandler -FPU_IRQHandler -SPI4_IRQHandler -SPI5_IRQHandler -QUADSPI_IRQHandler -FMPI2C1_EV_IRQHandler -FMPI2C1_ER_IRQHandler - - B . - - ENDP - - ALIGN - END - -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_ARM_STD/startup_stm32f412zx.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,398 @@ +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f412zx.s +;* Author : MCD Application Team +;* Description : STM32F412Zx devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +__initial_sp EQU 0x20040000 ; Top of RAM 256K + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD 0 ; Reserved + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter 0 global interrupt + DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter 1 global interrupt + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD RNG_IRQHandler ; RNG + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD QUADSPI_IRQHandler ; QuadSPI + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FMPI2C1_EV_IRQHandler ; FMPI2C1 Event + DCD FMPI2C1_ER_IRQHandler ; FMPI2C1 Error + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT TIM6_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT DFSDM1_FLT0_IRQHandler [WEAK] + EXPORT DFSDM1_FLT1_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT FMPI2C1_EV_IRQHandler [WEAK] + EXPORT FMPI2C1_ER_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +TIM6_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +DFSDM1_FLT0_IRQHandler +DFSDM1_FLT1_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +RNG_IRQHandler +FPU_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +QUADSPI_IRQHandler +FMPI2C1_EV_IRQHandler +FMPI2C1_ER_IRQHandler + + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_GCC_ARM/startup_stm32f412xx.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,531 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32f412zx.s - * @author MCD Application Team - * @version V2.5.1 - * @date 28-June-2016 - * @brief STM32F412Zx Devices vector table for GCC based toolchains. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M4 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m4 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss -/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ - -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - ldr sp, =_estack /* set stack pointer */ - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - ldr r2, =_sbss - b LoopFillZerobss -/* Zero fill the bss segment. */ -FillZerobss: - movs r3, #0 - str r3, [r2], #4 - -LoopFillZerobss: - ldr r3, = _ebss - cmp r2, r3 - bcc FillZerobss - -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call static constructors */ - //bl __libc_init_array -/* Call the application's entry point.*/ - //bl main - // Calling the crt0 'cold-start' entry point. There __libc_init_array is called - // and when existing hardware_init_hook() and software_init_hook() before - // starting main(). software_init_hook() is available and has to be called due - // to initializsation when using rtos. - bl _start - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -*******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - -g_pfnVectors: - .word _estack - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - - /* External Interrupts */ - .word WWDG_IRQHandler /* Window WatchDog */ - .word PVD_IRQHandler /* PVD through EXTI Line detection */ - .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ - .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ - .word FLASH_IRQHandler /* FLASH */ - .word RCC_IRQHandler /* RCC */ - .word EXTI0_IRQHandler /* EXTI Line0 */ - .word EXTI1_IRQHandler /* EXTI Line1 */ - .word EXTI2_IRQHandler /* EXTI Line2 */ - .word EXTI3_IRQHandler /* EXTI Line3 */ - .word EXTI4_IRQHandler /* EXTI Line4 */ - .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ - .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ - .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ - .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ - .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ - .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ - .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ - .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ - .word CAN1_TX_IRQHandler /* CAN1 TX */ - .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ - .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ - .word CAN1_SCE_IRQHandler /* CAN1 SCE */ - .word EXTI9_5_IRQHandler /* External Line[9:5]s */ - .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ - .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ - .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ - .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ - .word TIM2_IRQHandler /* TIM2 */ - .word TIM3_IRQHandler /* TIM3 */ - .word TIM4_IRQHandler /* TIM4 */ - .word I2C1_EV_IRQHandler /* I2C1 Event */ - .word I2C1_ER_IRQHandler /* I2C1 Error */ - .word I2C2_EV_IRQHandler /* I2C2 Event */ - .word I2C2_ER_IRQHandler /* I2C2 Error */ - .word SPI1_IRQHandler /* SPI1 */ - .word SPI2_IRQHandler /* SPI2 */ - .word USART1_IRQHandler /* USART1 */ - .word USART2_IRQHandler /* USART2 */ - .word USART3_IRQHandler /* USART3 */ - .word EXTI15_10_IRQHandler /* External Line[15:10]s */ - .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ - .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ - .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ - .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ - .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ - .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ - .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ - .word 0 /* Reserved */ - .word SDIO_IRQHandler /* SDIO */ - .word TIM5_IRQHandler /* TIM5 */ - .word SPI3_IRQHandler /* SPI3 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word TIM6_IRQHandler /* TIM6 */ - .word TIM7_IRQHandler /* TIM7 */ - .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ - .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ - .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ - .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ - .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ - .word DFSDM1_FLT0_IRQHandler /* DFSDM1 Filter0 */ - .word DFSDM1_FLT1_IRQHandler /* DFSDM1 Filter1 */ - .word CAN2_TX_IRQHandler /* CAN2 TX */ - .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ - .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ - .word CAN2_SCE_IRQHandler /* CAN2 SCE */ - .word OTG_FS_IRQHandler /* USB OTG FS */ - .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ - .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ - .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ - .word USART6_IRQHandler /* USART6 */ - .word I2C3_EV_IRQHandler /* I2C3 event */ - .word I2C3_ER_IRQHandler /* I2C3 error */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word RNG_IRQHandler /* RNG */ - .word FPU_IRQHandler /* FPU */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word SPI4_IRQHandler /* SPI4 */ - .word SPI5_IRQHandler /* SPI5 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word QUADSPI_IRQHandler /* QuadSPI */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word FMPI2C1_EV_IRQHandler /* FMPI2C1 Event */ - .word FMPI2C1_ER_IRQHandler /* FMPI2C1 Error */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMP_STAMP_IRQHandler - .thumb_set TAMP_STAMP_IRQHandler,Default_Handler - - .weak RTC_WKUP_IRQHandler - .thumb_set RTC_WKUP_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Stream0_IRQHandler - .thumb_set DMA1_Stream0_IRQHandler,Default_Handler - - .weak DMA1_Stream1_IRQHandler - .thumb_set DMA1_Stream1_IRQHandler,Default_Handler - - .weak DMA1_Stream2_IRQHandler - .thumb_set DMA1_Stream2_IRQHandler,Default_Handler - - .weak DMA1_Stream3_IRQHandler - .thumb_set DMA1_Stream3_IRQHandler,Default_Handler - - .weak DMA1_Stream4_IRQHandler - .thumb_set DMA1_Stream4_IRQHandler,Default_Handler - - .weak DMA1_Stream5_IRQHandler - .thumb_set DMA1_Stream5_IRQHandler,Default_Handler - - .weak DMA1_Stream6_IRQHandler - .thumb_set DMA1_Stream6_IRQHandler,Default_Handler - - .weak ADC_IRQHandler - .thumb_set ADC_IRQHandler,Default_Handler - - .weak CAN1_TX_IRQHandler - .thumb_set CAN1_TX_IRQHandler,Default_Handler - - .weak CAN1_RX0_IRQHandler - .thumb_set CAN1_RX0_IRQHandler,Default_Handler - - .weak CAN1_RX1_IRQHandler - .thumb_set CAN1_RX1_IRQHandler,Default_Handler - - .weak CAN1_SCE_IRQHandler - .thumb_set CAN1_SCE_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM1_BRK_TIM9_IRQHandler - .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler - - .weak TIM1_UP_TIM10_IRQHandler - .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler - - .weak TIM1_TRG_COM_TIM11_IRQHandler - .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTC_Alarm_IRQHandler - .thumb_set RTC_Alarm_IRQHandler,Default_Handler - - .weak OTG_FS_WKUP_IRQHandler - .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler - - .weak TIM8_BRK_TIM12_IRQHandler - .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler - - .weak TIM8_UP_TIM13_IRQHandler - .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler - - .weak TIM8_TRG_COM_TIM14_IRQHandler - .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler - - .weak TIM8_CC_IRQHandler - .thumb_set TIM8_CC_IRQHandler,Default_Handler - - .weak DMA1_Stream7_IRQHandler - .thumb_set DMA1_Stream7_IRQHandler,Default_Handler - - .weak SDIO_IRQHandler - .thumb_set SDIO_IRQHandler,Default_Handler - - .weak TIM5_IRQHandler - .thumb_set TIM5_IRQHandler,Default_Handler - - .weak SPI3_IRQHandler - .thumb_set SPI3_IRQHandler,Default_Handler - - .weak TIM6_IRQHandler - .thumb_set TIM6_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - - .weak DMA2_Stream0_IRQHandler - .thumb_set DMA2_Stream0_IRQHandler,Default_Handler - - .weak DMA2_Stream1_IRQHandler - .thumb_set DMA2_Stream1_IRQHandler,Default_Handler - - .weak DMA2_Stream2_IRQHandler - .thumb_set DMA2_Stream2_IRQHandler,Default_Handler - - .weak DMA2_Stream3_IRQHandler - .thumb_set DMA2_Stream3_IRQHandler,Default_Handler - - .weak DMA2_Stream4_IRQHandler - .thumb_set DMA2_Stream4_IRQHandler,Default_Handler - - .weak DFSDM1_FLT0_IRQHandler - .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler - - .weak DFSDM1_FLT1_IRQHandler - .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler - - .weak CAN2_TX_IRQHandler - .thumb_set CAN2_TX_IRQHandler,Default_Handler - - .weak CAN2_RX0_IRQHandler - .thumb_set CAN2_RX0_IRQHandler,Default_Handler - - .weak CAN2_RX1_IRQHandler - .thumb_set CAN2_RX1_IRQHandler,Default_Handler - - .weak CAN2_SCE_IRQHandler - .thumb_set CAN2_SCE_IRQHandler,Default_Handler - - .weak OTG_FS_IRQHandler - .thumb_set OTG_FS_IRQHandler,Default_Handler - - .weak DMA2_Stream5_IRQHandler - .thumb_set DMA2_Stream5_IRQHandler,Default_Handler - - .weak DMA2_Stream6_IRQHandler - .thumb_set DMA2_Stream6_IRQHandler,Default_Handler - - .weak DMA2_Stream7_IRQHandler - .thumb_set DMA2_Stream7_IRQHandler,Default_Handler - - .weak USART6_IRQHandler - .thumb_set USART6_IRQHandler,Default_Handler - - .weak I2C3_EV_IRQHandler - .thumb_set I2C3_EV_IRQHandler,Default_Handler - - .weak I2C3_ER_IRQHandler - .thumb_set I2C3_ER_IRQHandler,Default_Handler - - .weak RNG_IRQHandler - .thumb_set RNG_IRQHandler,Default_Handler - - .weak FPU_IRQHandler - .thumb_set FPU_IRQHandler,Default_Handler - - .weak SPI4_IRQHandler - .thumb_set SPI4_IRQHandler,Default_Handler - - .weak SPI5_IRQHandler - .thumb_set SPI5_IRQHandler,Default_Handler - - .weak QUADSPI_IRQHandler - .thumb_set QUADSPI_IRQHandler,Default_Handler - - .weak FMPI2C1_EV_IRQHandler - .thumb_set FMPI2C1_EV_IRQHandler,Default_Handler - - .weak FMPI2C1_ER_IRQHandler - .thumb_set FMPI2C1_ER_IRQHandler,Default_Handler -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_GCC_ARM/startup_stm32f412zx.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,529 @@ +/** + ****************************************************************************** + * @file startup_stm32f412zx.s + * @author MCD Application Team + * @brief STM32F412Zx Devices vector table for GCC based toolchains. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * <h2><center>© COPYRIGHT 2017 STMicroelectronics</center></h2> + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + //bl __libc_init_array +/* Call the application's entry point.*/ + //bl main + // Calling the crt0 'cold-start' entry point. There __libc_init_array is called + // and when existing hardware_init_hook() and software_init_hook() before + // starting main(). software_init_hook() is available and has to be called due + // to initializsation when using rtos. + bl _start + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word 0 /* Reserved */ + .word SDIO_IRQHandler /* SDIO */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word TIM6_IRQHandler /* TIM6 */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word DFSDM1_FLT0_IRQHandler /* DFSDM1 Filter0 */ + .word DFSDM1_FLT1_IRQHandler /* DFSDM1 Filter1 */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word RNG_IRQHandler /* RNG */ + .word FPU_IRQHandler /* FPU */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word QUADSPI_IRQHandler /* QuadSPI */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word FMPI2C1_EV_IRQHandler /* FMPI2C1 Event */ + .word FMPI2C1_ER_IRQHandler /* FMPI2C1 Error */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak TIM6_IRQHandler + .thumb_set TIM6_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak DFSDM1_FLT0_IRQHandler + .thumb_set DFSDM1_FLT0_IRQHandler,Default_Handler + + .weak DFSDM1_FLT1_IRQHandler + .thumb_set DFSDM1_FLT1_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak RNG_IRQHandler + .thumb_set RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak QUADSPI_IRQHandler + .thumb_set QUADSPI_IRQHandler,Default_Handler + + .weak FMPI2C1_EV_IRQHandler + .thumb_set FMPI2C1_EV_IRQHandler,Default_Handler + + .weak FMPI2C1_ER_IRQHandler + .thumb_set FMPI2C1_ER_IRQHandler,Default_Handler +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_IAR/startup_stm32f412xx.S Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,639 +0,0 @@ -;/******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** -;* File Name : startup_stm32f412zx.s -;* Author : MCD Application Team -;* Version : V2.5.1 -;* Date : 28-June-2016 -;* Description : STM32F412Zx devices vector table for EWARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == _iar_program_start, -;* - Set the vector table entries with the exceptions ISR -;* address. -;* - Configure the system clock -;* - Branches to main in the C library (which eventually -;* calls main()). -;* After Reset the Cortex-M4 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;******************************************************************************** -;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;* -;******************************************************************************* -; -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler ; Reset Handler - - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1 - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 - DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 - DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD 0 ; Reserved - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD TIM6_IRQHandler ; TIM6 - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter0 - DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter1 - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD RNG_IRQHandler ; RNG - DCD FPU_IRQHandler ; FPU - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SPI4_IRQHandler ; SPI4 - DCD SPI5_IRQHandler ; SPI5 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD QUADSPI_IRQHandler ; QuadSPI - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD FMPI2C1_EV_IRQHandler ; FMPI2C1 Event - DCD FMPI2C1_ER_IRQHandler ; FMPI2C1 Error - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK WWDG_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -WWDG_IRQHandler - B WWDG_IRQHandler - - PUBWEAK PVD_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PVD_IRQHandler - B PVD_IRQHandler - - PUBWEAK TAMP_STAMP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TAMP_STAMP_IRQHandler - B TAMP_STAMP_IRQHandler - - PUBWEAK RTC_WKUP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC_WKUP_IRQHandler - B RTC_WKUP_IRQHandler - - PUBWEAK FLASH_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FLASH_IRQHandler - B FLASH_IRQHandler - - PUBWEAK RCC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RCC_IRQHandler - B RCC_IRQHandler - - PUBWEAK EXTI0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI0_IRQHandler - B EXTI0_IRQHandler - - PUBWEAK EXTI1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI1_IRQHandler - B EXTI1_IRQHandler - - PUBWEAK EXTI2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI2_IRQHandler - B EXTI2_IRQHandler - - PUBWEAK EXTI3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI3_IRQHandler - B EXTI3_IRQHandler - - PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI4_IRQHandler - B EXTI4_IRQHandler - - PUBWEAK DMA1_Stream0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream0_IRQHandler - B DMA1_Stream0_IRQHandler - - PUBWEAK DMA1_Stream1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream1_IRQHandler - B DMA1_Stream1_IRQHandler - - PUBWEAK DMA1_Stream2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream2_IRQHandler - B DMA1_Stream2_IRQHandler - - PUBWEAK DMA1_Stream3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream3_IRQHandler - B DMA1_Stream3_IRQHandler - - PUBWEAK DMA1_Stream4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream4_IRQHandler - B DMA1_Stream4_IRQHandler - - PUBWEAK DMA1_Stream5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream5_IRQHandler - B DMA1_Stream5_IRQHandler - - PUBWEAK DMA1_Stream6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream6_IRQHandler - B DMA1_Stream6_IRQHandler - - PUBWEAK ADC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ADC_IRQHandler - B ADC_IRQHandler - - PUBWEAK CAN1_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN1_TX_IRQHandler - B CAN1_TX_IRQHandler - - PUBWEAK CAN1_RX0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN1_RX0_IRQHandler - B CAN1_RX0_IRQHandler - - PUBWEAK CAN1_RX1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN1_RX1_IRQHandler - B CAN1_RX1_IRQHandler - - PUBWEAK CAN1_SCE_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN1_SCE_IRQHandler - B CAN1_SCE_IRQHandler - - PUBWEAK EXTI9_5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI9_5_IRQHandler - B EXTI9_5_IRQHandler - - PUBWEAK TIM1_BRK_TIM9_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM1_BRK_TIM9_IRQHandler - B TIM1_BRK_TIM9_IRQHandler - - PUBWEAK TIM1_UP_TIM10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM1_UP_TIM10_IRQHandler - B TIM1_UP_TIM10_IRQHandler - - PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM1_TRG_COM_TIM11_IRQHandler - B TIM1_TRG_COM_TIM11_IRQHandler - - PUBWEAK TIM1_CC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM1_CC_IRQHandler - B TIM1_CC_IRQHandler - - PUBWEAK TIM2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM2_IRQHandler - B TIM2_IRQHandler - - PUBWEAK TIM3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM3_IRQHandler - B TIM3_IRQHandler - - PUBWEAK TIM4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM4_IRQHandler - B TIM4_IRQHandler - - PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C1_EV_IRQHandler - B I2C1_EV_IRQHandler - - PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C1_ER_IRQHandler - B I2C1_ER_IRQHandler - - PUBWEAK I2C2_EV_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C2_EV_IRQHandler - B I2C2_EV_IRQHandler - - PUBWEAK I2C2_ER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C2_ER_IRQHandler - B I2C2_ER_IRQHandler - - PUBWEAK SPI1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI1_IRQHandler - B SPI1_IRQHandler - - PUBWEAK SPI2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI2_IRQHandler - B SPI2_IRQHandler - - PUBWEAK USART1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART1_IRQHandler - B USART1_IRQHandler - - PUBWEAK USART2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART2_IRQHandler - B USART2_IRQHandler - - PUBWEAK USART3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART3_IRQHandler - B USART3_IRQHandler - - PUBWEAK EXTI15_10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI15_10_IRQHandler - B EXTI15_10_IRQHandler - - PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC_Alarm_IRQHandler - B RTC_Alarm_IRQHandler - - PUBWEAK OTG_FS_WKUP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -OTG_FS_WKUP_IRQHandler - B OTG_FS_WKUP_IRQHandler - - PUBWEAK TIM8_BRK_TIM12_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM8_BRK_TIM12_IRQHandler - B TIM8_BRK_TIM12_IRQHandler - - PUBWEAK TIM8_UP_TIM13_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM8_UP_TIM13_IRQHandler - B TIM8_UP_TIM13_IRQHandler - - PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM8_TRG_COM_TIM14_IRQHandler - B TIM8_TRG_COM_TIM14_IRQHandler - - PUBWEAK TIM8_CC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM8_CC_IRQHandler - B TIM8_CC_IRQHandler - - PUBWEAK DMA1_Stream7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream7_IRQHandler - B DMA1_Stream7_IRQHandler - - PUBWEAK SDIO_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SDIO_IRQHandler - B SDIO_IRQHandler - - PUBWEAK TIM5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM5_IRQHandler - B TIM5_IRQHandler - - PUBWEAK SPI3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI3_IRQHandler - B SPI3_IRQHandler - - PUBWEAK TIM6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM6_IRQHandler - B TIM6_IRQHandler - - PUBWEAK TIM7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM7_IRQHandler - B TIM7_IRQHandler - - PUBWEAK DMA2_Stream0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream0_IRQHandler - B DMA2_Stream0_IRQHandler - - PUBWEAK DMA2_Stream1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream1_IRQHandler - B DMA2_Stream1_IRQHandler - - PUBWEAK DMA2_Stream2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream2_IRQHandler - B DMA2_Stream2_IRQHandler - - PUBWEAK DMA2_Stream3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream3_IRQHandler - B DMA2_Stream3_IRQHandler - - PUBWEAK DMA2_Stream4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream4_IRQHandler - B DMA2_Stream4_IRQHandler - - PUBWEAK DFSDM1_FLT0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DFSDM1_FLT0_IRQHandler - B DFSDM1_FLT0_IRQHandler - - PUBWEAK DFSDM1_FLT1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DFSDM1_FLT1_IRQHandler - B DFSDM1_FLT1_IRQHandler - - PUBWEAK CAN2_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN2_TX_IRQHandler - B CAN2_TX_IRQHandler - - PUBWEAK CAN2_RX0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN2_RX0_IRQHandler - B CAN2_RX0_IRQHandler - - PUBWEAK CAN2_RX1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN2_RX1_IRQHandler - B CAN2_RX1_IRQHandler - - PUBWEAK CAN2_SCE_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN2_SCE_IRQHandler - B CAN2_SCE_IRQHandler - - PUBWEAK OTG_FS_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -OTG_FS_IRQHandler - B OTG_FS_IRQHandler - - PUBWEAK DMA2_Stream5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream5_IRQHandler - B DMA2_Stream5_IRQHandler - - PUBWEAK DMA2_Stream6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream6_IRQHandler - B DMA2_Stream6_IRQHandler - - PUBWEAK DMA2_Stream7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream7_IRQHandler - B DMA2_Stream7_IRQHandler - - PUBWEAK USART6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART6_IRQHandler - B USART6_IRQHandler - - PUBWEAK I2C3_EV_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C3_EV_IRQHandler - B I2C3_EV_IRQHandler - - PUBWEAK I2C3_ER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C3_ER_IRQHandler - B I2C3_ER_IRQHandler - - PUBWEAK RNG_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RNG_IRQHandler - B RNG_IRQHandler - - PUBWEAK FPU_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FPU_IRQHandler - B FPU_IRQHandler - - PUBWEAK SPI4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI4_IRQHandler - B SPI4_IRQHandler - - PUBWEAK SPI5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI5_IRQHandler - B SPI5_IRQHandler - - PUBWEAK QUADSPI_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -QUADSPI_IRQHandler - B QUADSPI_IRQHandler - - PUBWEAK FMPI2C1_EV_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FMPI2C1_EV_IRQHandler - B FMPI2C1_EV_IRQHandler - - PUBWEAK FMPI2C1_ER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FMPI2C1_ER_IRQHandler - B FMPI2C1_ER_IRQHandler - - END -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/TOOLCHAIN_IAR/startup_stm32f412zx.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,637 @@ +;/******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f412zx.s +;* Author : MCD Application Team +;* Description : STM32F412Zx devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Configure the system clock +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1 + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD 0 ; Reserved + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD TIM6_IRQHandler ; TIM6 + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD DFSDM1_FLT0_IRQHandler ; DFSDM1 Filter0 + DCD DFSDM1_FLT1_IRQHandler ; DFSDM1 Filter1 + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD RNG_IRQHandler ; RNG + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD QUADSPI_IRQHandler ; QuadSPI + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FMPI2C1_EV_IRQHandler ; FMPI2C1 Event + DCD FMPI2C1_ER_IRQHandler ; FMPI2C1 Error + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream0_IRQHandler + B DMA1_Stream0_IRQHandler + + PUBWEAK DMA1_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream1_IRQHandler + B DMA1_Stream1_IRQHandler + + PUBWEAK DMA1_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream2_IRQHandler + B DMA1_Stream2_IRQHandler + + PUBWEAK DMA1_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream3_IRQHandler + B DMA1_Stream3_IRQHandler + + PUBWEAK DMA1_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream4_IRQHandler + B DMA1_Stream4_IRQHandler + + PUBWEAK DMA1_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream5_IRQHandler + B DMA1_Stream5_IRQHandler + + PUBWEAK DMA1_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream6_IRQHandler + B DMA1_Stream6_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK CAN1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_TX_IRQHandler + B CAN1_TX_IRQHandler + + PUBWEAK CAN1_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_RX0_IRQHandler + B CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_BRK_TIM9_IRQHandler + B TIM1_BRK_TIM9_IRQHandler + + PUBWEAK TIM1_UP_TIM10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_UP_TIM10_IRQHandler + B TIM1_UP_TIM10_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_TRG_COM_TIM11_IRQHandler + B TIM1_TRG_COM_TIM11_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_WKUP_IRQHandler + B OTG_FS_WKUP_IRQHandler + + PUBWEAK TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_BRK_TIM12_IRQHandler + B TIM8_BRK_TIM12_IRQHandler + + PUBWEAK TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_UP_TIM13_IRQHandler + B TIM8_UP_TIM13_IRQHandler + + PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_TRG_COM_TIM14_IRQHandler + B TIM8_TRG_COM_TIM14_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK DMA1_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream7_IRQHandler + B DMA1_Stream7_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SDIO_IRQHandler + B SDIO_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK TIM6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM6_IRQHandler + B TIM6_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream0_IRQHandler + B DMA2_Stream0_IRQHandler + + PUBWEAK DMA2_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream1_IRQHandler + B DMA2_Stream1_IRQHandler + + PUBWEAK DMA2_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream2_IRQHandler + B DMA2_Stream2_IRQHandler + + PUBWEAK DMA2_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream3_IRQHandler + B DMA2_Stream3_IRQHandler + + PUBWEAK DMA2_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream4_IRQHandler + B DMA2_Stream4_IRQHandler + + PUBWEAK DFSDM1_FLT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DFSDM1_FLT0_IRQHandler + B DFSDM1_FLT0_IRQHandler + + PUBWEAK DFSDM1_FLT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DFSDM1_FLT1_IRQHandler + B DFSDM1_FLT1_IRQHandler + + PUBWEAK CAN2_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_TX_IRQHandler + B CAN2_TX_IRQHandler + + PUBWEAK CAN2_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_RX0_IRQHandler + B CAN2_RX0_IRQHandler + + PUBWEAK CAN2_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_RX1_IRQHandler + B CAN2_RX1_IRQHandler + + PUBWEAK CAN2_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_SCE_IRQHandler + B CAN2_SCE_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + PUBWEAK DMA2_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream5_IRQHandler + B DMA2_Stream5_IRQHandler + + PUBWEAK DMA2_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream6_IRQHandler + B DMA2_Stream6_IRQHandler + + PUBWEAK DMA2_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream7_IRQHandler + B DMA2_Stream7_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK RNG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RNG_IRQHandler + B RNG_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK SPI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI4_IRQHandler + B SPI4_IRQHandler + + PUBWEAK SPI5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI5_IRQHandler + B SPI5_IRQHandler + + PUBWEAK QUADSPI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +QUADSPI_IRQHandler + B QUADSPI_IRQHandler + + PUBWEAK FMPI2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FMPI2C1_EV_IRQHandler + B FMPI2C1_EV_IRQHandler + + PUBWEAK FMPI2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FMPI2C1_ER_IRQHandler + B FMPI2C1_ER_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/stm32f412zx.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/stm32f412zx.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f412zx.h * @author MCD Application Team - * @version V2.6.1 - * @date 14-February-2017 * @brief CMSIS STM32F412Zx Device Peripheral Access Layer Header File. * * This file contains: @@ -67,9 +65,11 @@ #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */ #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +/* MBED */ #ifndef __FPU_PRESENT #define __FPU_PRESENT 1U /*!< FPU present */ #endif /* __FPU_PRESENT */ +/* MBED */ /** * @} @@ -8966,9 +8966,15 @@ #define PWR_CSR_BRR_Pos (3U) #define PWR_CSR_BRR_Msk (0x1U << PWR_CSR_BRR_Pos) /*!< 0x00000008 */ #define PWR_CSR_BRR PWR_CSR_BRR_Msk /*!< Backup regulator ready */ -#define PWR_CSR_EWUP_Pos (8U) -#define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */ -#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */ +#define PWR_CSR_EWUP3_Pos (6U) +#define PWR_CSR_EWUP3_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000040 */ +#define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */ +#define PWR_CSR_EWUP2_Pos (7U) +#define PWR_CSR_EWUP2_Msk (0x1U << PWR_CSR_EWUP2_Pos) /*!< 0x00000080 */ +#define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */ +#define PWR_CSR_EWUP1_Pos (8U) +#define PWR_CSR_EWUP1_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */ +#define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */ #define PWR_CSR_BRE_Pos (9U) #define PWR_CSR_BRE_Msk (0x1U << PWR_CSR_BRE_Pos) /*!< 0x00000200 */ #define PWR_CSR_BRE PWR_CSR_BRE_Msk /*!< Backup regulator enable */ @@ -12320,7 +12326,7 @@ #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */ #define USART_CR1_TXEIE_Pos (7U) #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */ -#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<PE Interrupt Enable */ +#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<TXE Interrupt Enable */ #define USART_CR1_PEIE_Pos (8U) #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */ #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */ @@ -13222,92 +13228,6 @@ #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */ #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */ -/******************** Bit definition for OTG register ********************/ - -#define USB_OTG_CHNUM_Pos (0U) -#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */ -#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */ -#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */ -#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */ -#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */ -#define USB_OTG_BCNT_Pos (4U) -#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */ - -#define USB_OTG_DPID_Pos (15U) -#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */ -#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */ -#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */ - -#define USB_OTG_PKTSTS_Pos (17U) -#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */ -#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */ -#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */ -#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */ -#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */ - -#define USB_OTG_EPNUM_Pos (0U) -#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */ -#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */ -#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */ -#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */ -#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */ - -#define USB_OTG_FRMNUM_Pos (21U) -#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */ -#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */ -#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */ -#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */ -#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */ -#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */ - -/******************** Bit definition for OTG register ********************/ - -#define USB_OTG_CHNUM_Pos (0U) -#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */ -#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */ -#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */ -#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */ -#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */ -#define USB_OTG_BCNT_Pos (4U) -#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */ - -#define USB_OTG_DPID_Pos (15U) -#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */ -#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */ -#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */ - -#define USB_OTG_PKTSTS_Pos (17U) -#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */ -#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */ -#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */ -#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */ -#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */ - -#define USB_OTG_EPNUM_Pos (0U) -#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */ -#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */ -#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */ -#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */ -#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */ - -#define USB_OTG_FRMNUM_Pos (21U) -#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */ -#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */ -#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */ -#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */ -#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */ -#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */ - /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/ #define USB_OTG_GRXFSIZ_RXFD_Pos (0U) #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */ @@ -14015,6 +13935,48 @@ #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */ #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */ +/* Legacy define */ +/******************** Bit definition for OTG register ********************/ +#define USB_OTG_CHNUM_Pos (0U) +#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */ +#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */ +#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */ +#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */ +#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */ +#define USB_OTG_BCNT_Pos (4U) +#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */ + +#define USB_OTG_DPID_Pos (15U) +#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */ +#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */ +#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */ + +#define USB_OTG_PKTSTS_Pos (17U) +#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */ +#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */ +#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */ +#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */ + +#define USB_OTG_EPNUM_Pos (0U) +#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */ +#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */ +#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */ +#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */ +#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */ + +#define USB_OTG_FRMNUM_Pos (21U) +#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */ +#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */ +#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */ +#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */ /** * @} */
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/stm32f4xx.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/stm32f4xx.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx.h
* @author MCD Application Team
- * @version V2.6.1
- * @date 14-February-2017
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@@ -124,11 +122,11 @@
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS version number V2.6.1
+ * @brief CMSIS version number V2.6.2
*/
#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
-#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/system_stm32f4xx.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F412xG/device/system_stm32f4xx.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file system_stm32f4xx.h * @author MCD Application Team - * @version V2.6.1 - * @date 14-February-2017 * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/system_clock.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_DISCO_F413ZH/system_clock.c Tue Mar 20 16:56:18 2018 +0000
@@ -230,7 +230,7 @@
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
- RCC_OscInitStruct.HSICalibrationValue = 16;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8)
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/system_clock.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/TARGET_NUCLEO_F413ZH/system_clock.c Tue Mar 20 16:56:18 2018 +0000
@@ -228,7 +228,7 @@
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
- RCC_OscInitStruct.HSICalibrationValue = 16;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8)
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/TOOLCHAIN_ARM_MICRO/startup_stm32f413xx.S Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/TOOLCHAIN_ARM_MICRO/startup_stm32f413xx.S Tue Mar 20 16:56:18 2018 +0000 @@ -1,8 +1,6 @@ ;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** ;* File Name : startup_stm32f413xx.s ;* Author : MCD Application Team -;* Version : V2.6.1 -;* Date : 14-February-2017 ;* Description : STM32F413xx devices vector table for MDK-ARM toolchain. ;* This module performs: ;* - Set the initial SP
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/TOOLCHAIN_ARM_STD/startup_stm32f413xx.S Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/TOOLCHAIN_ARM_STD/startup_stm32f413xx.S Tue Mar 20 16:56:18 2018 +0000 @@ -1,8 +1,6 @@ ;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** ;* File Name : startup_stm32f413xx.s ;* Author : MCD Application Team -;* Version : V2.6.1 -;* Date : 14-February-2017 ;* Description : STM32F413xx devices vector table for MDK-ARM toolchain. ;* This module performs: ;* - Set the initial SP
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/TOOLCHAIN_GCC_ARM/startup_stm32f413xx.S Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/TOOLCHAIN_GCC_ARM/startup_stm32f413xx.S Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file startup_stm32f413xx.s * @author MCD Application Team - * @version V2.6.1 - * @date 14-February-2017 * @brief STM32F413xx Devices vector table for GCC based toolchains. * This module performs: * - Set the initial SP
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/TOOLCHAIN_IAR/startup_stm32f413xx.S Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/TOOLCHAIN_IAR/startup_stm32f413xx.S Tue Mar 20 16:56:18 2018 +0000 @@ -1,8 +1,6 @@ ;/******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** ;* File Name : startup_stm32f413xx.s ;* Author : MCD Application Team -;* Version : V2.6.1 -;* Date : 14-February-2017 ;* Description : STM32F413xx devices vector table for EWARM toolchain. ;* This module performs: ;* - Set the initial SP
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/stm32f413xx.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/stm32f413xx.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,14 +2,12 @@ ****************************************************************************** * @file stm32f413xx.h * @author MCD Application Team - * @version V2.6.1 - * @date 14-February-2017 * @brief CMSIS STM32F413xx Device Peripheral Access Layer Header File. * * This file contains: * - Data structures and the address mapping for all peripherals * - peripherals registers declarations and bits definition - * - Macros to access peripheralâs registers hardware + * - Macros to access peripheral's registers hardware * ****************************************************************************** * @attention @@ -67,9 +65,11 @@ #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */ #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +/* MBED */ #ifndef __FPU_PRESENT #define __FPU_PRESENT 1U /*!< FPU present */ #endif +/* MBED */ /** * @} @@ -8883,9 +8883,15 @@ #define PWR_CSR_BRR_Pos (3U) #define PWR_CSR_BRR_Msk (0x1U << PWR_CSR_BRR_Pos) /*!< 0x00000008 */ #define PWR_CSR_BRR PWR_CSR_BRR_Msk /*!< Backup regulator ready */ -#define PWR_CSR_EWUP_Pos (8U) -#define PWR_CSR_EWUP_Msk (0x1U << PWR_CSR_EWUP_Pos) /*!< 0x00000100 */ -#define PWR_CSR_EWUP PWR_CSR_EWUP_Msk /*!< Enable WKUP pin */ +#define PWR_CSR_EWUP3_Pos (6U) +#define PWR_CSR_EWUP3_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000040 */ +#define PWR_CSR_EWUP3 PWR_CSR_EWUP3_Msk /*!< Enable WKUP pin 3 */ +#define PWR_CSR_EWUP2_Pos (7U) +#define PWR_CSR_EWUP2_Msk (0x1U << PWR_CSR_EWUP2_Pos) /*!< 0x00000080 */ +#define PWR_CSR_EWUP2 PWR_CSR_EWUP2_Msk /*!< Enable WKUP pin 2 */ +#define PWR_CSR_EWUP1_Pos (8U) +#define PWR_CSR_EWUP1_Msk (0x1U << PWR_CSR_EWUP1_Pos) /*!< 0x00000100 */ +#define PWR_CSR_EWUP1 PWR_CSR_EWUP1_Msk /*!< Enable WKUP pin 1 */ #define PWR_CSR_BRE_Pos (9U) #define PWR_CSR_BRE_Msk (0x1U << PWR_CSR_BRE_Pos) /*!< 0x00000200 */ #define PWR_CSR_BRE PWR_CSR_BRE_Msk /*!< Backup regulator enable */ @@ -12887,7 +12893,7 @@ #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */ #define USART_CR1_TXEIE_Pos (7U) #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */ -#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<PE Interrupt Enable */ +#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<TXE Interrupt Enable */ #define USART_CR1_PEIE_Pos (8U) #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */ #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */ @@ -13795,92 +13801,6 @@ #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */ #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */ -/******************** Bit definition for OTG register ********************/ - -#define USB_OTG_CHNUM_Pos (0U) -#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */ -#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */ -#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */ -#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */ -#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */ -#define USB_OTG_BCNT_Pos (4U) -#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */ - -#define USB_OTG_DPID_Pos (15U) -#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */ -#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */ -#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */ - -#define USB_OTG_PKTSTS_Pos (17U) -#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */ -#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */ -#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */ -#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */ -#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */ - -#define USB_OTG_EPNUM_Pos (0U) -#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */ -#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */ -#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */ -#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */ -#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */ - -#define USB_OTG_FRMNUM_Pos (21U) -#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */ -#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */ -#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */ -#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */ -#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */ -#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */ - -/******************** Bit definition for OTG register ********************/ - -#define USB_OTG_CHNUM_Pos (0U) -#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */ -#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */ -#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */ -#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */ -#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */ -#define USB_OTG_BCNT_Pos (4U) -#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */ - -#define USB_OTG_DPID_Pos (15U) -#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */ -#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */ -#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */ - -#define USB_OTG_PKTSTS_Pos (17U) -#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */ -#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */ -#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */ -#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */ -#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */ - -#define USB_OTG_EPNUM_Pos (0U) -#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */ -#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */ -#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */ -#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */ -#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */ - -#define USB_OTG_FRMNUM_Pos (21U) -#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */ -#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */ -#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */ -#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */ -#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */ -#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */ - /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/ #define USB_OTG_GRXFSIZ_RXFD_Pos (0U) #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */ @@ -14588,6 +14508,48 @@ #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */ #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */ +/* Legacy define */ +/******************** Bit definition for OTG register ********************/ +#define USB_OTG_CHNUM_Pos (0U) +#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */ +#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */ +#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */ +#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */ +#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */ +#define USB_OTG_BCNT_Pos (4U) +#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */ + +#define USB_OTG_DPID_Pos (15U) +#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */ +#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */ +#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */ + +#define USB_OTG_PKTSTS_Pos (17U) +#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */ +#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */ +#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */ +#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */ + +#define USB_OTG_EPNUM_Pos (0U) +#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */ +#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */ +#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */ +#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */ +#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */ + +#define USB_OTG_FRMNUM_Pos (21U) +#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */ +#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */ +#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */ +#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */ /** * @} */
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/stm32f4xx.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/stm32f4xx.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,16 +2,14 @@
******************************************************************************
* @file stm32f4xx.h
* @author MCD Application Team
- * @version V2.6.1
- * @date 14-February-2017
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
* is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select:
* - The STM32F4xx device used in the target application
- * - To use or not the peripherals drivers in application code(i.e.
- * code will be based on direct access to peripherals registers
+ * - To use or not the peripheral's drivers in application code(i.e.
+ * code will be based on direct access to peripheral's registers
* rather than drivers API), this option is controlled by
* "#define USE_HAL_DRIVER"
*
@@ -124,11 +122,11 @@
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS version number V2.6.1
+ * @brief CMSIS version number V2.6.2
*/
#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
-#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/system_stm32f4xx.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F413xH/device/system_stm32f4xx.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file system_stm32f4xx.h * @author MCD Application Team - * @version V2.6.1 - * @date 14-February-2017 * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/system_clock.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_DISCO_F429ZI/system_clock.c Tue Mar 20 16:56:18 2018 +0000
@@ -192,7 +192,7 @@
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
- RCC_OscInitStruct.HSICalibrationValue = 16;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
RCC_OscInitStruct.PLL.PLLM = 8;
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/system_clock.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/TARGET_NUCLEO_F429ZI/system_clock.c Tue Mar 20 16:56:18 2018 +0000
@@ -192,7 +192,7 @@
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
- RCC_OscInitStruct.HSICalibrationValue = 16;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
RCC_OscInitStruct.PLL.PLLM = 8;
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_ARM_MICRO/startup_stm32f429xx.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,447 @@ +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f429xx.s +;* Author : MCD Application Team +;* Description : STM32F429x devices vector table for MDK-ARM_MICRO toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20020000 ; Top of RAM + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD HASH_RNG_IRQHandler ; Hash and Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInitPre + IMPORT HAL_InitPre + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInitPre + BLX R0 + LDR R0, =HAL_InitPre + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT HASH_RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +HASH_RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_ARM_MICRO/startup_stm32f429xx.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,449 +0,0 @@ -;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** -;* File Name : startup_stm32f429xx.s -;* Author : MCD Application Team -;* Version : V2.4.0 -;* Date : 14-August-2015 -;* Description : STM32F429x devices vector table for MDK-ARM_MICRO toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM4 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;******************************************************************************* - -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; <h> Stack Configuration -; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; </h> - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 - EXPORT __initial_sp - -Stack_Mem SPACE Stack_Size -__initial_sp EQU 0x20020000 ; Top of RAM - - -; <h> Heap Configuration -; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; </h> - -Heap_Size EQU 0x00000200 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 - EXPORT __heap_base - EXPORT __heap_limit - -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit EQU (__initial_sp - Stack_Size) - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 - DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 - DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FMC_IRQHandler ; FMC - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD 0 ; Reserved - DCD HASH_RNG_IRQHandler ; Hash and Rng - DCD FPU_IRQHandler ; FPU - DCD UART7_IRQHandler ; UART7 - DCD UART8_IRQHandler ; UART8 - DCD SPI4_IRQHandler ; SPI4 - DCD SPI5_IRQHandler ; SPI5 - DCD SPI6_IRQHandler ; SPI6 - DCD SAI1_IRQHandler ; SAI1 - DCD LTDC_IRQHandler ; LTDC - DCD LTDC_ER_IRQHandler ; LTDC error - DCD DMA2D_IRQHandler ; DMA2D - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInitPre - IMPORT HAL_InitPre - IMPORT SystemInit - IMPORT __main - - LDR R0, =SystemInitPre - BLX R0 - LDR R0, =HAL_InitPre - BLX R0 - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMP_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Stream0_IRQHandler [WEAK] - EXPORT DMA1_Stream1_IRQHandler [WEAK] - EXPORT DMA1_Stream2_IRQHandler [WEAK] - EXPORT DMA1_Stream3_IRQHandler [WEAK] - EXPORT DMA1_Stream4_IRQHandler [WEAK] - EXPORT DMA1_Stream5_IRQHandler [WEAK] - EXPORT DMA1_Stream6_IRQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT CAN1_TX_IRQHandler [WEAK] - EXPORT CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_SCE_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] - EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT OTG_FS_WKUP_IRQHandler [WEAK] - EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] - EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] - EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] - EXPORT TIM8_CC_IRQHandler [WEAK] - EXPORT DMA1_Stream7_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT SDIO_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT UART5_IRQHandler [WEAK] - EXPORT TIM6_DAC_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - EXPORT DMA2_Stream0_IRQHandler [WEAK] - EXPORT DMA2_Stream1_IRQHandler [WEAK] - EXPORT DMA2_Stream2_IRQHandler [WEAK] - EXPORT DMA2_Stream3_IRQHandler [WEAK] - EXPORT DMA2_Stream4_IRQHandler [WEAK] - EXPORT ETH_IRQHandler [WEAK] - EXPORT ETH_WKUP_IRQHandler [WEAK] - EXPORT CAN2_TX_IRQHandler [WEAK] - EXPORT CAN2_RX0_IRQHandler [WEAK] - EXPORT CAN2_RX1_IRQHandler [WEAK] - EXPORT CAN2_SCE_IRQHandler [WEAK] - EXPORT OTG_FS_IRQHandler [WEAK] - EXPORT DMA2_Stream5_IRQHandler [WEAK] - EXPORT DMA2_Stream6_IRQHandler [WEAK] - EXPORT DMA2_Stream7_IRQHandler [WEAK] - EXPORT USART6_IRQHandler [WEAK] - EXPORT I2C3_EV_IRQHandler [WEAK] - EXPORT I2C3_ER_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] - EXPORT OTG_HS_WKUP_IRQHandler [WEAK] - EXPORT OTG_HS_IRQHandler [WEAK] - EXPORT DCMI_IRQHandler [WEAK] - EXPORT HASH_RNG_IRQHandler [WEAK] - EXPORT FPU_IRQHandler [WEAK] - EXPORT UART7_IRQHandler [WEAK] - EXPORT UART8_IRQHandler [WEAK] - EXPORT SPI4_IRQHandler [WEAK] - EXPORT SPI5_IRQHandler [WEAK] - EXPORT SPI6_IRQHandler [WEAK] - EXPORT SAI1_IRQHandler [WEAK] - EXPORT LTDC_IRQHandler [WEAK] - EXPORT LTDC_ER_IRQHandler [WEAK] - EXPORT DMA2D_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMP_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Stream0_IRQHandler -DMA1_Stream1_IRQHandler -DMA1_Stream2_IRQHandler -DMA1_Stream3_IRQHandler -DMA1_Stream4_IRQHandler -DMA1_Stream5_IRQHandler -DMA1_Stream6_IRQHandler -ADC_IRQHandler -CAN1_TX_IRQHandler -CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_SCE_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_TIM9_IRQHandler -TIM1_UP_TIM10_IRQHandler -TIM1_TRG_COM_TIM11_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -OTG_FS_WKUP_IRQHandler -TIM8_BRK_TIM12_IRQHandler -TIM8_UP_TIM13_IRQHandler -TIM8_TRG_COM_TIM14_IRQHandler -TIM8_CC_IRQHandler -DMA1_Stream7_IRQHandler -FMC_IRQHandler -SDIO_IRQHandler -TIM5_IRQHandler -SPI3_IRQHandler -UART4_IRQHandler -UART5_IRQHandler -TIM6_DAC_IRQHandler -TIM7_IRQHandler -DMA2_Stream0_IRQHandler -DMA2_Stream1_IRQHandler -DMA2_Stream2_IRQHandler -DMA2_Stream3_IRQHandler -DMA2_Stream4_IRQHandler -ETH_IRQHandler -ETH_WKUP_IRQHandler -CAN2_TX_IRQHandler -CAN2_RX0_IRQHandler -CAN2_RX1_IRQHandler -CAN2_SCE_IRQHandler -OTG_FS_IRQHandler -DMA2_Stream5_IRQHandler -DMA2_Stream6_IRQHandler -DMA2_Stream7_IRQHandler -USART6_IRQHandler -I2C3_EV_IRQHandler -I2C3_ER_IRQHandler -OTG_HS_EP1_OUT_IRQHandler -OTG_HS_EP1_IN_IRQHandler -OTG_HS_WKUP_IRQHandler -OTG_HS_IRQHandler -DCMI_IRQHandler -HASH_RNG_IRQHandler -FPU_IRQHandler -UART7_IRQHandler -UART8_IRQHandler -SPI4_IRQHandler -SPI5_IRQHandler -SPI6_IRQHandler -SAI1_IRQHandler -LTDC_IRQHandler -LTDC_ER_IRQHandler -DMA2D_IRQHandler - B . - - ENDP - - ALIGN - END - -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_ARM_STD/startup_stm32f429xx.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,420 @@ +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f429xx.s +;* Author : MCD Application Team +;* Description : STM32F429x devices vector table for MDK-ARM_STD toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +__initial_sp EQU 0x20030000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD HASH_RNG_IRQHandler ; Hash and Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInitPre + IMPORT HAL_InitPre + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInitPre + BLX R0 + LDR R0, =HAL_InitPre + BLX R0 + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT HASH_RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +HASH_RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_ARM_STD/startup_stm32f429xx.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,422 +0,0 @@ -;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** -;* File Name : startup_stm32f429xx.s -;* Author : MCD Application Team -;* Version : V2.4.0 -;* Date : 14-August-2015 -;* Description : STM32F429x devices vector table for MDK-ARM_STD toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM4 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;******************************************************************************* - -__initial_sp EQU 0x20030000 ; Top of RAM - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 - DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 - DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FMC_IRQHandler ; FMC - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD 0 ; Reserved - DCD HASH_RNG_IRQHandler ; Hash and Rng - DCD FPU_IRQHandler ; FPU - DCD UART7_IRQHandler ; UART7 - DCD UART8_IRQHandler ; UART8 - DCD SPI4_IRQHandler ; SPI4 - DCD SPI5_IRQHandler ; SPI5 - DCD SPI6_IRQHandler ; SPI6 - DCD SAI1_IRQHandler ; SAI1 - DCD LTDC_IRQHandler ; LTDC - DCD LTDC_ER_IRQHandler ; LTDC error - DCD DMA2D_IRQHandler ; DMA2D - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInitPre - IMPORT HAL_InitPre - IMPORT SystemInit - IMPORT __main - - LDR R0, =SystemInitPre - BLX R0 - LDR R0, =HAL_InitPre - BLX R0 - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMP_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Stream0_IRQHandler [WEAK] - EXPORT DMA1_Stream1_IRQHandler [WEAK] - EXPORT DMA1_Stream2_IRQHandler [WEAK] - EXPORT DMA1_Stream3_IRQHandler [WEAK] - EXPORT DMA1_Stream4_IRQHandler [WEAK] - EXPORT DMA1_Stream5_IRQHandler [WEAK] - EXPORT DMA1_Stream6_IRQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT CAN1_TX_IRQHandler [WEAK] - EXPORT CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_SCE_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] - EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT OTG_FS_WKUP_IRQHandler [WEAK] - EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] - EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] - EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] - EXPORT TIM8_CC_IRQHandler [WEAK] - EXPORT DMA1_Stream7_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT SDIO_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT UART5_IRQHandler [WEAK] - EXPORT TIM6_DAC_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - EXPORT DMA2_Stream0_IRQHandler [WEAK] - EXPORT DMA2_Stream1_IRQHandler [WEAK] - EXPORT DMA2_Stream2_IRQHandler [WEAK] - EXPORT DMA2_Stream3_IRQHandler [WEAK] - EXPORT DMA2_Stream4_IRQHandler [WEAK] - EXPORT ETH_IRQHandler [WEAK] - EXPORT ETH_WKUP_IRQHandler [WEAK] - EXPORT CAN2_TX_IRQHandler [WEAK] - EXPORT CAN2_RX0_IRQHandler [WEAK] - EXPORT CAN2_RX1_IRQHandler [WEAK] - EXPORT CAN2_SCE_IRQHandler [WEAK] - EXPORT OTG_FS_IRQHandler [WEAK] - EXPORT DMA2_Stream5_IRQHandler [WEAK] - EXPORT DMA2_Stream6_IRQHandler [WEAK] - EXPORT DMA2_Stream7_IRQHandler [WEAK] - EXPORT USART6_IRQHandler [WEAK] - EXPORT I2C3_EV_IRQHandler [WEAK] - EXPORT I2C3_ER_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] - EXPORT OTG_HS_WKUP_IRQHandler [WEAK] - EXPORT OTG_HS_IRQHandler [WEAK] - EXPORT DCMI_IRQHandler [WEAK] - EXPORT HASH_RNG_IRQHandler [WEAK] - EXPORT FPU_IRQHandler [WEAK] - EXPORT UART7_IRQHandler [WEAK] - EXPORT UART8_IRQHandler [WEAK] - EXPORT SPI4_IRQHandler [WEAK] - EXPORT SPI5_IRQHandler [WEAK] - EXPORT SPI6_IRQHandler [WEAK] - EXPORT SAI1_IRQHandler [WEAK] - EXPORT LTDC_IRQHandler [WEAK] - EXPORT LTDC_ER_IRQHandler [WEAK] - EXPORT DMA2D_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMP_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Stream0_IRQHandler -DMA1_Stream1_IRQHandler -DMA1_Stream2_IRQHandler -DMA1_Stream3_IRQHandler -DMA1_Stream4_IRQHandler -DMA1_Stream5_IRQHandler -DMA1_Stream6_IRQHandler -ADC_IRQHandler -CAN1_TX_IRQHandler -CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_SCE_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_TIM9_IRQHandler -TIM1_UP_TIM10_IRQHandler -TIM1_TRG_COM_TIM11_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -OTG_FS_WKUP_IRQHandler -TIM8_BRK_TIM12_IRQHandler -TIM8_UP_TIM13_IRQHandler -TIM8_TRG_COM_TIM14_IRQHandler -TIM8_CC_IRQHandler -DMA1_Stream7_IRQHandler -FMC_IRQHandler -SDIO_IRQHandler -TIM5_IRQHandler -SPI3_IRQHandler -UART4_IRQHandler -UART5_IRQHandler -TIM6_DAC_IRQHandler -TIM7_IRQHandler -DMA2_Stream0_IRQHandler -DMA2_Stream1_IRQHandler -DMA2_Stream2_IRQHandler -DMA2_Stream3_IRQHandler -DMA2_Stream4_IRQHandler -ETH_IRQHandler -ETH_WKUP_IRQHandler -CAN2_TX_IRQHandler -CAN2_RX0_IRQHandler -CAN2_RX1_IRQHandler -CAN2_SCE_IRQHandler -OTG_FS_IRQHandler -DMA2_Stream5_IRQHandler -DMA2_Stream6_IRQHandler -DMA2_Stream7_IRQHandler -USART6_IRQHandler -I2C3_EV_IRQHandler -I2C3_ER_IRQHandler -OTG_HS_EP1_OUT_IRQHandler -OTG_HS_EP1_IN_IRQHandler -OTG_HS_WKUP_IRQHandler -OTG_HS_IRQHandler -DCMI_IRQHandler -HASH_RNG_IRQHandler -FPU_IRQHandler -UART7_IRQHandler -UART8_IRQHandler -SPI4_IRQHandler -SPI5_IRQHandler -SPI6_IRQHandler -SAI1_IRQHandler -LTDC_IRQHandler -LTDC_ER_IRQHandler -DMA2D_IRQHandler - B . - - ENDP - - ALIGN - END - -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_GCC_ARM/startup_stm32f429xx.S Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_GCC_ARM/startup_stm32f429xx.S Tue Mar 20 16:56:18 2018 +0000 @@ -2,9 +2,7 @@ ****************************************************************************** * @file startup_stm32f429xx.s * @author MCD Application Team - * @version V2.3.0 - * @date 02-March-2015 - * @brief STM32F429xx Devices vector table for Atollic TrueSTUDIO toolchain. + * @brief STM32F429xx Devices vector table for GCC based toolchains. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, @@ -16,7 +14,7 @@ ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2017 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -58,6 +56,10 @@ .word _sdata /* end address for the .data section. defined in linker script */ .word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss /* stack used for SystemInit_ExtMemCtl; always internal RAM used */ /** @@ -91,6 +93,17 @@ adds r2, r0, r1 cmp r2, r3 bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss /* Call the clock system intitialization function.*/ bl SystemInitPre
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_IAR/startup_stm32f429xx.S Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/TOOLCHAIN_IAR/startup_stm32f429xx.S Tue Mar 20 16:56:18 2018 +0000 @@ -1,8 +1,6 @@ -;/******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** +;/******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** ;* File Name : startup_stm32f429xx.s ;* Author : MCD Application Team -;* Version : V2.4.0 -;* Date : 14-August-2015 ;* Description : STM32F429xx devices vector table for EWARM toolchain. ;* This module performs: ;* - Set the initial SP
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/stm32f429xx.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/stm32f429xx.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f429xx.h * @author MCD Application Team - * @version V2.6.1 - * @date 14-February-2017 * @brief CMSIS STM32F429xx Device Peripheral Access Layer Header File. * * This file contains: @@ -67,9 +65,11 @@ #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */ #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +/* MBED */ #ifndef __FPU_PRESENT #define __FPU_PRESENT 1U /*!< FPU present */ #endif /* __FPU_PRESENT */ +/* MBED */ /** * @} @@ -14097,7 +14097,7 @@ #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */ #define USART_CR1_TXEIE_Pos (7U) #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */ -#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<PE Interrupt Enable */ +#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<TXE Interrupt Enable */ #define USART_CR1_PEIE_Pos (8U) #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */ #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */ @@ -15909,92 +15909,6 @@ #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */ #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */ -/******************** Bit definition for OTG register ********************/ - -#define USB_OTG_CHNUM_Pos (0U) -#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */ -#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */ -#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */ -#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */ -#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */ -#define USB_OTG_BCNT_Pos (4U) -#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */ - -#define USB_OTG_DPID_Pos (15U) -#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */ -#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */ -#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */ - -#define USB_OTG_PKTSTS_Pos (17U) -#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */ -#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */ -#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */ -#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */ -#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */ - -#define USB_OTG_EPNUM_Pos (0U) -#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */ -#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */ -#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */ -#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */ -#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */ - -#define USB_OTG_FRMNUM_Pos (21U) -#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */ -#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */ -#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */ -#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */ -#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */ -#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */ - -/******************** Bit definition for OTG register ********************/ - -#define USB_OTG_CHNUM_Pos (0U) -#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */ -#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */ -#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */ -#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */ -#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */ -#define USB_OTG_BCNT_Pos (4U) -#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */ - -#define USB_OTG_DPID_Pos (15U) -#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */ -#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */ -#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */ - -#define USB_OTG_PKTSTS_Pos (17U) -#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */ -#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */ -#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */ -#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */ -#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */ - -#define USB_OTG_EPNUM_Pos (0U) -#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */ -#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */ -#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */ -#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */ -#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */ - -#define USB_OTG_FRMNUM_Pos (21U) -#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */ -#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */ -#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */ -#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */ -#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */ -#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */ - /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/ #define USB_OTG_GRXFSIZ_RXFD_Pos (0U) #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */ @@ -16640,6 +16554,48 @@ #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */ #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */ +/* Legacy define */ +/******************** Bit definition for OTG register ********************/ +#define USB_OTG_CHNUM_Pos (0U) +#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */ +#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */ +#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */ +#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */ +#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */ +#define USB_OTG_BCNT_Pos (4U) +#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */ + +#define USB_OTG_DPID_Pos (15U) +#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */ +#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */ +#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */ + +#define USB_OTG_PKTSTS_Pos (17U) +#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */ +#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */ +#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */ +#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */ + +#define USB_OTG_EPNUM_Pos (0U) +#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */ +#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */ +#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */ +#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */ +#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */ + +#define USB_OTG_FRMNUM_Pos (21U) +#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */ +#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */ +#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */ +#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */ /** * @} */
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/stm32f4xx.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/stm32f4xx.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx.h
* @author MCD Application Team
- * @version V2.6.1
- * @date 14-February-2017
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@@ -91,7 +89,7 @@
/* #define STM32F439xx */ /*!< STM32F439VG, STM32F439VI, STM32F439ZG, STM32F439ZI, STM32F439BG, STM32F439BI, STM32F439NG,
STM32F439NI, STM32F439IG and STM32F439II Devices */
/* #define STM32F401xC */ /*!< STM32F401CB, STM32F401CC, STM32F401RB, STM32F401RC, STM32F401VB and STM32F401VC Devices */
- /* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
+ /* #define STM32F401xE */ /*!< STM32F401CD, STM32F401RD, STM32F401VD, STM32F401CE, STM32F401RE and STM32F401VE Devices */
/* #define STM32F410Tx */ /*!< STM32F410T8 and STM32F410TB Devices */
/* #define STM32F410Cx */ /*!< STM32F410C8 and STM32F410CB Devices */
/* #define STM32F410Rx */ /*!< STM32F410R8 and STM32F410RB Devices */
@@ -124,11 +122,11 @@
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS version number V2.6.1
+ * @brief CMSIS version number V2.6.2
*/
#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
-#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/system_stm32f4xx.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F429xI/device/system_stm32f4xx.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file system_stm32f4xx.h * @author MCD Application Team - * @version V2.6.1 - * @date 14-February-2017 * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/PinNames.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/PinNames.h Tue Mar 20 16:56:18 2018 +0000
@@ -82,10 +82,17 @@
// Cellular modem (a DCE)
MDMPWRON = PE_14, // Power (active high)
MDMRST = PB_5, // Reset (active low)
+#if defined(TARGET_UBLOX_C030_R410M)
+ MDMTXD = PA_9, // Transmit Data
+ MDMRXD = PA_10, // Receive Data
+ MDMCTS = PA_11, // Clear to Send
+ MDMRTS = PA_12, // Request to Send
+#else
MDMTXD = PD_5, // Transmit Data
MDMRXD = PD_6, // Receive Data
MDMCTS = PD_3, // Clear to Send
MDMRTS = PD_4, // Request to Send
+#endif
MDMDCD = NC, // DCD line not connected
MDMDSR = NC, // DSR line not connected
MDMDTR = NC, // DTR line not connected
@@ -149,12 +156,20 @@
#ifdef MBED_CONF_TARGET_STDIO_UART_TX
STDIO_UART_TX = MBED_CONF_TARGET_STDIO_UART_TX,
#else
+#if defined(TARGET_UBLOX_C030_R410M)
+ STDIO_UART_TX = PD_5,
+#else
STDIO_UART_TX = PA_9,
#endif
+#endif
#ifdef MBED_CONF_TARGET_STDIO_UART_RX
STDIO_UART_RX = MBED_CONF_TARGET_STDIO_UART_RX,
#else
+#if defined(TARGET_UBLOX_C030_R410M)
+ STDIO_UART_RX = PD_6,
+#else
STDIO_UART_RX = PA_10,
+#endif
#endif
// ST-Link
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/battery_charger_i2c.cpp Fri Feb 16 16:09:33 2018 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,34 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2017 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "battery_charger_i2c.h"
-
-BatteryChargerI2c::BatteryChargerI2c(PinName sda, PinName scl):_i2c(), _hz(100000)
-{
- i2c_init(&_i2c, sda, scl);
-}
-
-bool BatteryChargerI2c::read_from_i2c(int i2c_address, char* data_read, int length)
-{
- int bytes_read = i2c_read(&_i2c, i2c_address, data_read, length, 1);
- return (length == bytes_read);
-}
-
-bool BatteryChargerI2c::write_to_i2c(int i2c_address, const char* data_write, int length)
-{
- int bytes_written = i2c_write(&_i2c, i2c_address, data_write, length, 1);
- return (length == bytes_written);
-}
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/battery_charger_i2c.h Fri Feb 16 16:09:33 2018 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,43 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2017 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#ifndef BATTERY_CHARGER_I2C
-#define BATTERY_CHARGER_I2C
-
-#include "hal/i2c_api.h"
-
-#ifdef __cplusplus
-extern"C"{
-#endif
-
-class BatteryChargerI2c{
-
-public:
- BatteryChargerI2c(PinName sda, PinName scl);
- bool read_from_i2c(int i2c_address, char *data_read, int length);
- bool write_to_i2c(int i2c_address, const char *data_write, int length);
- virtual ~BatteryChargerI2c() {}
-
-private:
- i2c_t _i2c;
- int _hz;
-};
-
-#ifdef __cplusplus
-}
-#endif
-
-#endif //BATTERY_CHARGER_I2C
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/min_battery_voltage.c Tue Mar 20 16:56:18 2018 +0000
@@ -0,0 +1,73 @@
+/* mbed Microcontroller Library
+ * Copyright (c) 2006-2017 ARM Limited
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License");
+ * you may not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS,
+ * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+
+#include "min_battery_voltage.h"
+
+/** Defining HAL_MspInit strong function
+ * in user defined file as described in documentation
+ */
+
+void HAL_MspInit(void)
+{
+ set_minimum_battery_voltage();
+}
+
+void set_minimum_battery_voltage()
+{
+ i2c_t i2c_obj = {0};
+ int data_read;
+ i2c_init(&i2c_obj, I2C_SDA_B, I2C_SCL_B);
+ i2c_frequency(&i2c_obj, I2C_FREQUENCY);
+
+ if (read_from_i2c(BQ24295_I2C_ADDRESS, 0, &data_read, i2c_obj)) {
+ data_read = data_read & MIN_BATTERY_VOLTAGE_MASK;
+ write_to_i2c(BQ24295_I2C_ADDRESS, 0, data_read, i2c_obj);
+ //Battery Voltage is set to 3880mV
+ } else {
+ // Minimum battery voltage could not be set. This is not a critical error, no need to stop execution
+ // It simply means that longer cabling or USB ports with lower output voltages may cause problems.
+ }
+}
+
+char write_to_i2c(int slave_addr, int reg_addr, int data_write, i2c_t i2c_obj)
+{
+ char ret_code = 0;
+ if (!i2c_start(&i2c_obj)) {
+ if ((i2c_byte_write(&i2c_obj, slave_addr << 1) == 1) &&
+ (i2c_byte_write(&i2c_obj, reg_addr) == 1) &&
+ (i2c_byte_write(&i2c_obj,data_write) ==1)) {
+ ret_code = 1;
+ }
+ i2c_stop(&i2c_obj);
+ }
+ return ret_code;
+}
+
+char read_from_i2c(int slave_addr, int reg_addr, int* data_read, i2c_t i2c_obj)
+{
+ char ret_code = 0;
+ if (!i2c_start(&i2c_obj)) {
+ if ((i2c_byte_write(&i2c_obj,(slave_addr << 1))==1) &&
+ (i2c_byte_write(&i2c_obj, reg_addr)==1) &&
+ (!i2c_start(&i2c_obj)) &&
+ (i2c_byte_write(&i2c_obj, ((slave_addr << 1) | 0x01)) == 1)) {
+ *data_read = i2c_byte_read(&i2c_obj,1);
+ ret_code = 1;
+ }
+ i2c_stop(&i2c_obj);
+ }
+ return ret_code;
+}
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/min_battery_voltage.cpp Fri Feb 16 16:09:33 2018 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,48 +0,0 @@
-/* mbed Microcontroller Library
- * Copyright (c) 2006-2017 ARM Limited
- *
- * Licensed under the Apache License, Version 2.0 (the "License");
- * you may not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS,
- * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-
-#include "min_battery_voltage.h"
-#include "battery_charger_i2c.h"
-
-/** Defining HAL_MspInit strong function
- * in user defined file as described in documentation
- */
-
-void HAL_MspInit(void)
-{
- set_minimum_battery_voltage();
-}
-
-void set_minimum_battery_voltage()
-{
- char data_write[2] = {0};
- char data_read;
- BatteryChargerI2c i2c_object(I2C_SDA_B, I2C_SCL_B);
-
- if (i2c_object.write_to_i2c(BQ24295_I2C_ADDRESS,&data_write[0] , 1)){
- i2c_object.read_from_i2c(BQ24295_I2C_ADDRESS, &data_read, 1);
- data_read = data_read & MIN_BATTERY_VOLTAGE_MASK;
- data_write[0] = 0x0;
- data_write[1] = data_read;
- if (i2c_object.write_to_i2c(BQ24295_I2C_ADDRESS,&data_write[0] , 2)){
- //Battery Voltage is set to 3880mV
- }
- }
- else{
- // Minimum battery voltage could not be set. This is not a critical error, no need to stop execution
- // It simply means that longer cabling or USB ports with lower output voltages may cause problems.
- }
-}
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/min_battery_voltage.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/min_battery_voltage.h Tue Mar 20 16:56:18 2018 +0000
@@ -17,11 +17,14 @@
#ifndef MIN_BATTERY_VOLTAGE_H
#define MIN_BATTERY_VOLTAGE_H
+#include "hal/i2c_api.h"
+
#ifdef __cplusplus
extern"C"{
#endif
-#define BQ24295_I2C_ADDRESS (0x6B << 1)
+#define BQ24295_I2C_ADDRESS (0x6B)
+#define I2C_FREQUENCY 100000
#define MIN_BATTERY_VOLTAGE_MASK (0x87)
/** Initializes an instance of class BatteryChargerI2c which is using the STM HAL I2C APIs
@@ -29,6 +32,8 @@
*/
void set_minimum_battery_voltage(void);
+char read_from_i2c(int slave_addr, int reg_addr, int* data_read, i2c_t i2c_obj);
+char write_to_i2c(int slave_addr, int reg_addr,int data_write, i2c_t i2c_obj);
#ifdef __cplusplus
}
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/onboard_modem_api.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/onboard_modem_api.c Tue Mar 20 16:56:18 2018 +0000
@@ -28,7 +28,12 @@
{
gpio_t gpio;
+#if defined(TARGET_UBLOX_C030_R410M)
+ gpio_init_inout(&gpio, MDMPWRON, PIN_OUTPUT, OpenDrain, 0);
+#else
gpio_init_out_ex(&gpio, MDMPWRON, 0);
+#endif
+
wait_us(time_us);
gpio_write(&gpio, 1);
}
@@ -51,16 +56,27 @@
void onboard_modem_power_up()
{
- /* keep the power line low for 50 microseconds */
+#if defined(TARGET_UBLOX_C030_R410M)
+ /* keep the power line low for 1 seconds */
+ press_power_button(1000000);
+#else
+ /* keep the power line low for 50 microseconds */
press_power_button(50);
+#endif
+
/* give modem a little time to respond */
wait_ms(100);
}
void onboard_modem_power_down()
{
- /* keep the power line low for 1 second */
+#if defined(TARGET_UBLOX_C030_R410M)
+ /* keep the power line low for 1.5 seconds */
+ press_power_button(1500000);
+#else
+ /* keep the power line low for 1 seconds */
press_power_button(1000000);
+#endif
}
#endif //MODEM_ON_BOARD
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/ublox_low_level_api.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/TARGET_UBLOX_C030/ublox_low_level_api.c Tue Mar 20 16:56:18 2018 +0000
@@ -26,12 +26,18 @@
// start with modem disabled
gpio_init_out_ex(&gpio, MDMRST, 0);
+#if defined(TARGET_UBLOX_C030_R410M)
+ gpio_init_inout(&gpio, MDMPWRON, PIN_OUTPUT, OpenDrain, 1);
+#else
gpio_init_out_ex(&gpio, MDMPWRON, 0);
+#endif
gpio_init_out_ex(&gpio, MDMRTS, 0);
gpio_init_in_ex(&gpio, MDMCURRENTSENSE, PullNone);
- // start with GNSS disabled
+#if !defined (TARGET_UBLOX_C030_R410M)
+ // start with GNSS disabled, this is ONLY TEMPORARY and that once the HW issue with the GNSSEN pin on the R410M board is resolved then this line will become default for all platforms.
gpio_init_inout(&gpio, GNSSEN, PIN_OUTPUT, PushPullNoPull, 0);
+#endif
// power on SD card
gpio_init_out_ex(&gpio, SDPWRON, 1);
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/TOOLCHAIN_ARM_STD/startup_stm32f437xx.S Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/TOOLCHAIN_ARM_STD/startup_stm32f437xx.S Tue Mar 20 16:56:18 2018 +0000 @@ -1,8 +1,6 @@ -;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** ;* File Name : startup_stm32f437xx.s ;* Author : MCD Application Team -;* Version : V2.4.0 -;* Date : 14-August-2015 ;* Description : STM32F437x devices vector table for MDK-ARM_STD toolchain. ;* This module performs: ;* - Set the initial SP
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/TOOLCHAIN_GCC_ARM/startup_stm32f437xx.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,563 @@ +/** + ****************************************************************************** + * @file startup_stm32f437xx.s + * @author MCD Application Team + * @brief STM32F437xx Devices vector table for GCC based toolchains. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * <h2><center>© COPYRIGHT 2017 STMicroelectronics</center></h2> + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + //bl __libc_init_array +/* Call the application's entry point.*/ + //bl main + // Calling the crt0 'cold-start' entry point. There __libc_init_array is called + // and when existing hardware_init_hook() and software_init_hook() before + // starting main(). software_init_hook() is available and has to be called due + // to initializsation when using rtos. + bl _start + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + +g_pfnVectors: + .word _estack + .word Reset_Handler + + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FMC_IRQHandler /* FMC */ + .word SDIO_IRQHandler /* SDIO */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word ETH_IRQHandler /* Ethernet */ + .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word DCMI_IRQHandler /* DCMI */ + .word CRYP_IRQHandler /* CRYP crypto */ + .word HASH_RNG_IRQHandler /* Hash and Rng */ + .word FPU_IRQHandler /* FPU */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + .word SPI6_IRQHandler /* SPI6 */ + .word SAI1_IRQHandler /* SAI1 */ + .word 0 /* Reserved */ + .word 0 /* Reserved */ + .word DMA2D_IRQHandler /* DMA2D */ + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak DCMI_IRQHandler + .thumb_set DCMI_IRQHandler,Default_Handler + + .weak CRYP_IRQHandler + .thumb_set CRYP_IRQHandler,Default_Handler + + .weak HASH_RNG_IRQHandler + .thumb_set HASH_RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak SPI6_IRQHandler + .thumb_set SPI6_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak DMA2D_IRQHandler + .thumb_set DMA2D_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + + + + +
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/TOOLCHAIN_GCC_ARM/startup_stm32f437xx.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,554 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32f437xx.s - * @author MCD Application Team - * @version V2.6.0 - * @date 04-November-2016 - * @brief STM32F437xx Devices vector table for GCC based toolchains. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M4 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m4 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* start address for the .bss section. defined in linker script */ -.word _sbss -/* end address for the .bss section. defined in linker script */ -.word _ebss -/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ - -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - ldr sp, =_estack /* set stack pointer */ - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call static constructors */ - //bl __libc_init_array -/* Call the application's entry point.*/ - //bl main - // Calling the crt0 'cold-start' entry point. There __libc_init_array is called - // and when existing hardware_init_hook() and software_init_hook() before - // starting main(). software_init_hook() is available and has to be called due - // to initializsation when using rtos. - bl _start - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -*******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - -g_pfnVectors: - .word _estack - .word Reset_Handler - - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - - /* External Interrupts */ - .word WWDG_IRQHandler /* Window WatchDog */ - .word PVD_IRQHandler /* PVD through EXTI Line detection */ - .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ - .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ - .word FLASH_IRQHandler /* FLASH */ - .word RCC_IRQHandler /* RCC */ - .word EXTI0_IRQHandler /* EXTI Line0 */ - .word EXTI1_IRQHandler /* EXTI Line1 */ - .word EXTI2_IRQHandler /* EXTI Line2 */ - .word EXTI3_IRQHandler /* EXTI Line3 */ - .word EXTI4_IRQHandler /* EXTI Line4 */ - .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ - .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ - .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ - .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ - .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ - .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ - .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ - .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ - .word CAN1_TX_IRQHandler /* CAN1 TX */ - .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ - .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ - .word CAN1_SCE_IRQHandler /* CAN1 SCE */ - .word EXTI9_5_IRQHandler /* External Line[9:5]s */ - .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ - .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ - .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ - .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ - .word TIM2_IRQHandler /* TIM2 */ - .word TIM3_IRQHandler /* TIM3 */ - .word TIM4_IRQHandler /* TIM4 */ - .word I2C1_EV_IRQHandler /* I2C1 Event */ - .word I2C1_ER_IRQHandler /* I2C1 Error */ - .word I2C2_EV_IRQHandler /* I2C2 Event */ - .word I2C2_ER_IRQHandler /* I2C2 Error */ - .word SPI1_IRQHandler /* SPI1 */ - .word SPI2_IRQHandler /* SPI2 */ - .word USART1_IRQHandler /* USART1 */ - .word USART2_IRQHandler /* USART2 */ - .word USART3_IRQHandler /* USART3 */ - .word EXTI15_10_IRQHandler /* External Line[15:10]s */ - .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ - .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ - .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ - .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ - .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ - .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ - .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ - .word FMC_IRQHandler /* FMC */ - .word SDIO_IRQHandler /* SDIO */ - .word TIM5_IRQHandler /* TIM5 */ - .word SPI3_IRQHandler /* SPI3 */ - .word UART4_IRQHandler /* UART4 */ - .word UART5_IRQHandler /* UART5 */ - .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ - .word TIM7_IRQHandler /* TIM7 */ - .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ - .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ - .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ - .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ - .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ - .word ETH_IRQHandler /* Ethernet */ - .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ - .word CAN2_TX_IRQHandler /* CAN2 TX */ - .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ - .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ - .word CAN2_SCE_IRQHandler /* CAN2 SCE */ - .word OTG_FS_IRQHandler /* USB OTG FS */ - .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ - .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ - .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ - .word USART6_IRQHandler /* USART6 */ - .word I2C3_EV_IRQHandler /* I2C3 event */ - .word I2C3_ER_IRQHandler /* I2C3 error */ - .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ - .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ - .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ - .word OTG_HS_IRQHandler /* USB OTG HS */ - .word DCMI_IRQHandler /* DCMI */ - .word CRYP_IRQHandler /* CRYP crypto */ - .word HASH_RNG_IRQHandler /* Hash and Rng */ - .word FPU_IRQHandler /* FPU */ - .word UART7_IRQHandler /* UART7 */ - .word UART8_IRQHandler /* UART8 */ - .word SPI4_IRQHandler /* SPI4 */ - .word SPI5_IRQHandler /* SPI5 */ - .word SPI6_IRQHandler /* SPI6 */ - .word SAI1_IRQHandler /* SAI1 */ - .word 0 /* Reserved */ - .word 0 /* Reserved */ - .word DMA2D_IRQHandler /* DMA2D */ - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMP_STAMP_IRQHandler - .thumb_set TAMP_STAMP_IRQHandler,Default_Handler - - .weak RTC_WKUP_IRQHandler - .thumb_set RTC_WKUP_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Stream0_IRQHandler - .thumb_set DMA1_Stream0_IRQHandler,Default_Handler - - .weak DMA1_Stream1_IRQHandler - .thumb_set DMA1_Stream1_IRQHandler,Default_Handler - - .weak DMA1_Stream2_IRQHandler - .thumb_set DMA1_Stream2_IRQHandler,Default_Handler - - .weak DMA1_Stream3_IRQHandler - .thumb_set DMA1_Stream3_IRQHandler,Default_Handler - - .weak DMA1_Stream4_IRQHandler - .thumb_set DMA1_Stream4_IRQHandler,Default_Handler - - .weak DMA1_Stream5_IRQHandler - .thumb_set DMA1_Stream5_IRQHandler,Default_Handler - - .weak DMA1_Stream6_IRQHandler - .thumb_set DMA1_Stream6_IRQHandler,Default_Handler - - .weak ADC_IRQHandler - .thumb_set ADC_IRQHandler,Default_Handler - - .weak CAN1_TX_IRQHandler - .thumb_set CAN1_TX_IRQHandler,Default_Handler - - .weak CAN1_RX0_IRQHandler - .thumb_set CAN1_RX0_IRQHandler,Default_Handler - - .weak CAN1_RX1_IRQHandler - .thumb_set CAN1_RX1_IRQHandler,Default_Handler - - .weak CAN1_SCE_IRQHandler - .thumb_set CAN1_SCE_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM1_BRK_TIM9_IRQHandler - .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler - - .weak TIM1_UP_TIM10_IRQHandler - .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler - - .weak TIM1_TRG_COM_TIM11_IRQHandler - .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTC_Alarm_IRQHandler - .thumb_set RTC_Alarm_IRQHandler,Default_Handler - - .weak OTG_FS_WKUP_IRQHandler - .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler - - .weak TIM8_BRK_TIM12_IRQHandler - .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler - - .weak TIM8_UP_TIM13_IRQHandler - .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler - - .weak TIM8_TRG_COM_TIM14_IRQHandler - .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler - - .weak TIM8_CC_IRQHandler - .thumb_set TIM8_CC_IRQHandler,Default_Handler - - .weak DMA1_Stream7_IRQHandler - .thumb_set DMA1_Stream7_IRQHandler,Default_Handler - - .weak FMC_IRQHandler - .thumb_set FMC_IRQHandler,Default_Handler - - .weak SDIO_IRQHandler - .thumb_set SDIO_IRQHandler,Default_Handler - - .weak TIM5_IRQHandler - .thumb_set TIM5_IRQHandler,Default_Handler - - .weak SPI3_IRQHandler - .thumb_set SPI3_IRQHandler,Default_Handler - - .weak UART4_IRQHandler - .thumb_set UART4_IRQHandler,Default_Handler - - .weak UART5_IRQHandler - .thumb_set UART5_IRQHandler,Default_Handler - - .weak TIM6_DAC_IRQHandler - .thumb_set TIM6_DAC_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - - .weak DMA2_Stream0_IRQHandler - .thumb_set DMA2_Stream0_IRQHandler,Default_Handler - - .weak DMA2_Stream1_IRQHandler - .thumb_set DMA2_Stream1_IRQHandler,Default_Handler - - .weak DMA2_Stream2_IRQHandler - .thumb_set DMA2_Stream2_IRQHandler,Default_Handler - - .weak DMA2_Stream3_IRQHandler - .thumb_set DMA2_Stream3_IRQHandler,Default_Handler - - .weak DMA2_Stream4_IRQHandler - .thumb_set DMA2_Stream4_IRQHandler,Default_Handler - - .weak ETH_IRQHandler - .thumb_set ETH_IRQHandler,Default_Handler - - .weak ETH_WKUP_IRQHandler - .thumb_set ETH_WKUP_IRQHandler,Default_Handler - - .weak CAN2_TX_IRQHandler - .thumb_set CAN2_TX_IRQHandler,Default_Handler - - .weak CAN2_RX0_IRQHandler - .thumb_set CAN2_RX0_IRQHandler,Default_Handler - - .weak CAN2_RX1_IRQHandler - .thumb_set CAN2_RX1_IRQHandler,Default_Handler - - .weak CAN2_SCE_IRQHandler - .thumb_set CAN2_SCE_IRQHandler,Default_Handler - - .weak OTG_FS_IRQHandler - .thumb_set OTG_FS_IRQHandler,Default_Handler - - .weak DMA2_Stream5_IRQHandler - .thumb_set DMA2_Stream5_IRQHandler,Default_Handler - - .weak DMA2_Stream6_IRQHandler - .thumb_set DMA2_Stream6_IRQHandler,Default_Handler - - .weak DMA2_Stream7_IRQHandler - .thumb_set DMA2_Stream7_IRQHandler,Default_Handler - - .weak USART6_IRQHandler - .thumb_set USART6_IRQHandler,Default_Handler - - .weak I2C3_EV_IRQHandler - .thumb_set I2C3_EV_IRQHandler,Default_Handler - - .weak I2C3_ER_IRQHandler - .thumb_set I2C3_ER_IRQHandler,Default_Handler - - .weak OTG_HS_EP1_OUT_IRQHandler - .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler - - .weak OTG_HS_EP1_IN_IRQHandler - .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler - - .weak OTG_HS_WKUP_IRQHandler - .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler - - .weak OTG_HS_IRQHandler - .thumb_set OTG_HS_IRQHandler,Default_Handler - - .weak DCMI_IRQHandler - .thumb_set DCMI_IRQHandler,Default_Handler - - .weak CRYP_IRQHandler - .thumb_set CRYP_IRQHandler,Default_Handler - - .weak HASH_RNG_IRQHandler - .thumb_set HASH_RNG_IRQHandler,Default_Handler - - .weak FPU_IRQHandler - .thumb_set FPU_IRQHandler,Default_Handler - - .weak UART7_IRQHandler - .thumb_set UART7_IRQHandler,Default_Handler - - .weak UART8_IRQHandler - .thumb_set UART8_IRQHandler,Default_Handler - - .weak SPI4_IRQHandler - .thumb_set SPI4_IRQHandler,Default_Handler - - .weak SPI5_IRQHandler - .thumb_set SPI5_IRQHandler,Default_Handler - - .weak SPI6_IRQHandler - .thumb_set SPI6_IRQHandler,Default_Handler - - .weak SAI1_IRQHandler - .thumb_set SAI1_IRQHandler,Default_Handler - - .weak DMA2D_IRQHandler - .thumb_set DMA2D_IRQHandler,Default_Handler - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - - - - -
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/TOOLCHAIN_IAR/startup_stm32f437xx.S Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/TOOLCHAIN_IAR/startup_stm32f437xx.S Tue Mar 20 16:56:18 2018 +0000 @@ -1,8 +1,6 @@ -;/******************** (C) COPYRIGHT 2014 STMicroelectronics ******************** +;/******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** ;* File Name : startup_stm32f437xx.s ;* Author : MCD Application Team -;* Version : V2.1.0 -;* Date : 19-June-2014 ;* Description : STM32F437xx devices vector table for EWARM toolchain. ;* This module performs: ;* - Set the initial SP
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/stm32f437xx.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/stm32f437xx.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f437xx.h * @author MCD Application Team - * @version V2.6.1 - * @date 14-February-2017 * @brief CMSIS STM32F437xx Device Peripheral Access Layer Header File. * * This file contains: @@ -67,9 +65,11 @@ #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */ #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +/* MBED */ #ifndef __FPU_PRESENT #define __FPU_PRESENT 1U /*!< FPU present */ #endif /* __FPU_PRESENT */ +/* MBED */ /** * @} @@ -14037,7 +14037,7 @@ #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */ #define USART_CR1_TXEIE_Pos (7U) #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */ -#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<PE Interrupt Enable */ +#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<TXE Interrupt Enable */ #define USART_CR1_PEIE_Pos (8U) #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */ #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */ @@ -15849,92 +15849,6 @@ #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */ #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */ -/******************** Bit definition for OTG register ********************/ - -#define USB_OTG_CHNUM_Pos (0U) -#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */ -#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */ -#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */ -#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */ -#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */ -#define USB_OTG_BCNT_Pos (4U) -#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */ - -#define USB_OTG_DPID_Pos (15U) -#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */ -#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */ -#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */ - -#define USB_OTG_PKTSTS_Pos (17U) -#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */ -#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */ -#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */ -#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */ -#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */ - -#define USB_OTG_EPNUM_Pos (0U) -#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */ -#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */ -#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */ -#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */ -#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */ - -#define USB_OTG_FRMNUM_Pos (21U) -#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */ -#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */ -#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */ -#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */ -#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */ -#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */ - -/******************** Bit definition for OTG register ********************/ - -#define USB_OTG_CHNUM_Pos (0U) -#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */ -#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */ -#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */ -#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */ -#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */ -#define USB_OTG_BCNT_Pos (4U) -#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */ - -#define USB_OTG_DPID_Pos (15U) -#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */ -#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */ -#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */ - -#define USB_OTG_PKTSTS_Pos (17U) -#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */ -#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */ -#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */ -#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */ -#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */ - -#define USB_OTG_EPNUM_Pos (0U) -#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */ -#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */ -#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */ -#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */ -#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */ - -#define USB_OTG_FRMNUM_Pos (21U) -#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */ -#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */ -#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */ -#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */ -#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */ -#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */ - /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/ #define USB_OTG_GRXFSIZ_RXFD_Pos (0U) #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */ @@ -16580,6 +16494,48 @@ #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */ #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */ +/* Legacy define */ +/******************** Bit definition for OTG register ********************/ +#define USB_OTG_CHNUM_Pos (0U) +#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */ +#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */ +#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */ +#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */ +#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */ +#define USB_OTG_BCNT_Pos (4U) +#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */ + +#define USB_OTG_DPID_Pos (15U) +#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */ +#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */ +#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */ + +#define USB_OTG_PKTSTS_Pos (17U) +#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */ +#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */ +#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */ +#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */ + +#define USB_OTG_EPNUM_Pos (0U) +#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */ +#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */ +#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */ +#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */ +#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */ + +#define USB_OTG_FRMNUM_Pos (21U) +#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */ +#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */ +#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */ +#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */ /** * @} */
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/stm32f4xx.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/stm32f4xx.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,16 +2,14 @@
******************************************************************************
* @file stm32f4xx.h
* @author MCD Application Team
- * @version V2.6.1
- * @date 14-February-2017
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
* is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select:
* - The STM32F4xx device used in the target application
- * - To use or not the peripherals drivers in application code(i.e.
- * code will be based on direct access to peripherals registers
+ * - To use or not the peripheral's drivers in application code(i.e.
+ * code will be based on direct access to peripheral's registers
* rather than drivers API), this option is controlled by
* "#define USE_HAL_DRIVER"
*
@@ -124,11 +122,11 @@
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS version number V2.6.1
+ * @brief CMSIS version number V2.6.2
*/
#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
-#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/system_stm32f4xx.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F437xG/device/system_stm32f4xx.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file system_stm32f4xx.h * @author MCD Application Team - * @version V2.6.1 - * @date 14-February-2017 * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MTB_UBLOX_ODIN_W2/PinNames.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_MODULE_UBLOX_ODIN_W2/TARGET_MTB_UBLOX_ODIN_W2/PinNames.h Tue Mar 20 16:56:18 2018 +0000
@@ -148,16 +148,14 @@
//P_TP11, // BOOT0
// Internal
- LED1 = PD_9,
- LED2 = PA_12,
- LED3 = PD_8,
- LED4 = PA_11,
- LED5 = PC_2,
- LED6 = PA_3,
- LED7 = PF_6,
LED_RED = PE_0,
LED_GREEN = PB_6,
LED_BLUE = PB_8,
+
+ LED1 = LED_RED,
+ LED2 = LED_GREEN,
+ LED3 = LED_BLUE,
+
SW1 = PF_2,
SW2 = PG_4,
@@ -185,7 +183,7 @@
#elif MBED_CONF_TARGET_USB_TX
STDIO_UART_TX = MBED_CONF_TARGET_USB_TX,
#else
- STDIO_UART_TX = PA_11,
+ STDIO_UART_TX = PA_9,
#endif
#ifdef MBED_CONF_TARGET_STDIO_UART_RX
@@ -193,7 +191,7 @@
#elif MBED_CONF_TARGET_USB_RX
STDIO_UART_TX = MBED_CONF_TARGET_USB_RX,
#else
- STDIO_UART_RX = PA_13,
+ STDIO_UART_RX = PA_10,
#endif
// DAPLink
@@ -208,8 +206,8 @@
TGT_SWDIO = SWDIO,
TGT_SWCLK = SWCLK,
TGT_RESET = NTRST,
- TG_TX = USBTX,
- TG_RX = USBRX,
+ TGT_TX = USBTX,
+ TGT_RX = USBRX,
TX1 = P_A15,
RX1 = P_A14,
SDA1 = P_C18,
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/system_clock.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/TARGET_NUCLEO_F439ZI/system_clock.c Tue Mar 20 16:56:18 2018 +0000
@@ -207,7 +207,7 @@
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
- RCC_OscInitStruct.HSICalibrationValue = 16;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
RCC_OscInitStruct.PLL.PLLM = 8;
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_ARM_MICRO/startup_stm32f439xx.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,443 @@ +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f439xx.s +;* Author : MCD Application Team +;* Description : STM32F439x devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20030000 ; Top of RAM + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00000200 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD CRYP_IRQHandler ; CRYPTO + DCD HASH_RNG_IRQHandler ; Hash and Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT CRYP_IRQHandler [WEAK] + EXPORT HASH_RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +CRYP_IRQHandler +HASH_RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_ARM_MICRO/startup_stm32f439xx.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,445 +0,0 @@ -;******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** -;* File Name : startup_stm32f439xx.s -;* Author : MCD Application Team -;* Version : V2.6.0 -;* Date : 04-November-2016 -;* Description : STM32F439x devices vector table for MDK-ARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM4 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;******************************************************************************* - -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; <h> Stack Configuration -; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; </h> - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 - EXPORT __initial_sp - -Stack_Mem SPACE Stack_Size -__initial_sp EQU 0x20030000 ; Top of RAM - - -; <h> Heap Configuration -; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; </h> - -Heap_Size EQU 0x00000200 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 - EXPORT __heap_base - EXPORT __heap_limit - -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit EQU (__initial_sp - Stack_Size) - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 - DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 - DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FMC_IRQHandler ; FMC - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD CRYP_IRQHandler ; CRYPTO - DCD HASH_RNG_IRQHandler ; Hash and Rng - DCD FPU_IRQHandler ; FPU - DCD UART7_IRQHandler ; UART7 - DCD UART8_IRQHandler ; UART8 - DCD SPI4_IRQHandler ; SPI4 - DCD SPI5_IRQHandler ; SPI5 - DCD SPI6_IRQHandler ; SPI6 - DCD SAI1_IRQHandler ; SAI1 - DCD LTDC_IRQHandler ; LTDC - DCD LTDC_ER_IRQHandler ; LTDC error - DCD DMA2D_IRQHandler ; DMA2D - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMP_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Stream0_IRQHandler [WEAK] - EXPORT DMA1_Stream1_IRQHandler [WEAK] - EXPORT DMA1_Stream2_IRQHandler [WEAK] - EXPORT DMA1_Stream3_IRQHandler [WEAK] - EXPORT DMA1_Stream4_IRQHandler [WEAK] - EXPORT DMA1_Stream5_IRQHandler [WEAK] - EXPORT DMA1_Stream6_IRQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT CAN1_TX_IRQHandler [WEAK] - EXPORT CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_SCE_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] - EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT OTG_FS_WKUP_IRQHandler [WEAK] - EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] - EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] - EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] - EXPORT TIM8_CC_IRQHandler [WEAK] - EXPORT DMA1_Stream7_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT SDIO_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT UART5_IRQHandler [WEAK] - EXPORT TIM6_DAC_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - EXPORT DMA2_Stream0_IRQHandler [WEAK] - EXPORT DMA2_Stream1_IRQHandler [WEAK] - EXPORT DMA2_Stream2_IRQHandler [WEAK] - EXPORT DMA2_Stream3_IRQHandler [WEAK] - EXPORT DMA2_Stream4_IRQHandler [WEAK] - EXPORT ETH_IRQHandler [WEAK] - EXPORT ETH_WKUP_IRQHandler [WEAK] - EXPORT CAN2_TX_IRQHandler [WEAK] - EXPORT CAN2_RX0_IRQHandler [WEAK] - EXPORT CAN2_RX1_IRQHandler [WEAK] - EXPORT CAN2_SCE_IRQHandler [WEAK] - EXPORT OTG_FS_IRQHandler [WEAK] - EXPORT DMA2_Stream5_IRQHandler [WEAK] - EXPORT DMA2_Stream6_IRQHandler [WEAK] - EXPORT DMA2_Stream7_IRQHandler [WEAK] - EXPORT USART6_IRQHandler [WEAK] - EXPORT I2C3_EV_IRQHandler [WEAK] - EXPORT I2C3_ER_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] - EXPORT OTG_HS_WKUP_IRQHandler [WEAK] - EXPORT OTG_HS_IRQHandler [WEAK] - EXPORT DCMI_IRQHandler [WEAK] - EXPORT CRYP_IRQHandler [WEAK] - EXPORT HASH_RNG_IRQHandler [WEAK] - EXPORT FPU_IRQHandler [WEAK] - EXPORT UART7_IRQHandler [WEAK] - EXPORT UART8_IRQHandler [WEAK] - EXPORT SPI4_IRQHandler [WEAK] - EXPORT SPI5_IRQHandler [WEAK] - EXPORT SPI6_IRQHandler [WEAK] - EXPORT SAI1_IRQHandler [WEAK] - EXPORT LTDC_IRQHandler [WEAK] - EXPORT LTDC_ER_IRQHandler [WEAK] - EXPORT DMA2D_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMP_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Stream0_IRQHandler -DMA1_Stream1_IRQHandler -DMA1_Stream2_IRQHandler -DMA1_Stream3_IRQHandler -DMA1_Stream4_IRQHandler -DMA1_Stream5_IRQHandler -DMA1_Stream6_IRQHandler -ADC_IRQHandler -CAN1_TX_IRQHandler -CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_SCE_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_TIM9_IRQHandler -TIM1_UP_TIM10_IRQHandler -TIM1_TRG_COM_TIM11_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -OTG_FS_WKUP_IRQHandler -TIM8_BRK_TIM12_IRQHandler -TIM8_UP_TIM13_IRQHandler -TIM8_TRG_COM_TIM14_IRQHandler -TIM8_CC_IRQHandler -DMA1_Stream7_IRQHandler -FMC_IRQHandler -SDIO_IRQHandler -TIM5_IRQHandler -SPI3_IRQHandler -UART4_IRQHandler -UART5_IRQHandler -TIM6_DAC_IRQHandler -TIM7_IRQHandler -DMA2_Stream0_IRQHandler -DMA2_Stream1_IRQHandler -DMA2_Stream2_IRQHandler -DMA2_Stream3_IRQHandler -DMA2_Stream4_IRQHandler -ETH_IRQHandler -ETH_WKUP_IRQHandler -CAN2_TX_IRQHandler -CAN2_RX0_IRQHandler -CAN2_RX1_IRQHandler -CAN2_SCE_IRQHandler -OTG_FS_IRQHandler -DMA2_Stream5_IRQHandler -DMA2_Stream6_IRQHandler -DMA2_Stream7_IRQHandler -USART6_IRQHandler -I2C3_EV_IRQHandler -I2C3_ER_IRQHandler -OTG_HS_EP1_OUT_IRQHandler -OTG_HS_EP1_IN_IRQHandler -OTG_HS_WKUP_IRQHandler -OTG_HS_IRQHandler -DCMI_IRQHandler -CRYP_IRQHandler -HASH_RNG_IRQHandler -FPU_IRQHandler -UART7_IRQHandler -UART8_IRQHandler -SPI4_IRQHandler -SPI5_IRQHandler -SPI6_IRQHandler -SAI1_IRQHandler -LTDC_IRQHandler -LTDC_ER_IRQHandler -DMA2D_IRQHandler - B . - - ENDP - - ALIGN - END - -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_ARM_STD/startup_stm32f439xx.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,416 @@ +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f439xx.s +;* Author : MCD Application Team +;* Description : STM32F439x devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +__initial_sp EQU 0x20030000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD CRYP_IRQHandler ; CRYPTO + DCD HASH_RNG_IRQHandler ; Hash and Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT CRYP_IRQHandler [WEAK] + EXPORT HASH_RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +CRYP_IRQHandler +HASH_RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_ARM_STD/startup_stm32f439xx.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,418 +0,0 @@ -;******************** (C) COPYRIGHT 2016 STMicroelectronics ******************** -;* File Name : startup_stm32f439xx.s -;* Author : MCD Application Team -;* Version : V2.6.0 -;* Date : 04-November-2016 -;* Description : STM32F439x devices vector table for MDK-ARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM4 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;******************************************************************************* - -__initial_sp EQU 0x20030000 ; Top of RAM - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 - DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 - DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FMC_IRQHandler ; FMC - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD CRYP_IRQHandler ; CRYPTO - DCD HASH_RNG_IRQHandler ; Hash and Rng - DCD FPU_IRQHandler ; FPU - DCD UART7_IRQHandler ; UART7 - DCD UART8_IRQHandler ; UART8 - DCD SPI4_IRQHandler ; SPI4 - DCD SPI5_IRQHandler ; SPI5 - DCD SPI6_IRQHandler ; SPI6 - DCD SAI1_IRQHandler ; SAI1 - DCD LTDC_IRQHandler ; LTDC - DCD LTDC_ER_IRQHandler ; LTDC error - DCD DMA2D_IRQHandler ; DMA2D - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMP_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Stream0_IRQHandler [WEAK] - EXPORT DMA1_Stream1_IRQHandler [WEAK] - EXPORT DMA1_Stream2_IRQHandler [WEAK] - EXPORT DMA1_Stream3_IRQHandler [WEAK] - EXPORT DMA1_Stream4_IRQHandler [WEAK] - EXPORT DMA1_Stream5_IRQHandler [WEAK] - EXPORT DMA1_Stream6_IRQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT CAN1_TX_IRQHandler [WEAK] - EXPORT CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_SCE_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] - EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT OTG_FS_WKUP_IRQHandler [WEAK] - EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] - EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] - EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] - EXPORT TIM8_CC_IRQHandler [WEAK] - EXPORT DMA1_Stream7_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT SDIO_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT UART5_IRQHandler [WEAK] - EXPORT TIM6_DAC_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - EXPORT DMA2_Stream0_IRQHandler [WEAK] - EXPORT DMA2_Stream1_IRQHandler [WEAK] - EXPORT DMA2_Stream2_IRQHandler [WEAK] - EXPORT DMA2_Stream3_IRQHandler [WEAK] - EXPORT DMA2_Stream4_IRQHandler [WEAK] - EXPORT ETH_IRQHandler [WEAK] - EXPORT ETH_WKUP_IRQHandler [WEAK] - EXPORT CAN2_TX_IRQHandler [WEAK] - EXPORT CAN2_RX0_IRQHandler [WEAK] - EXPORT CAN2_RX1_IRQHandler [WEAK] - EXPORT CAN2_SCE_IRQHandler [WEAK] - EXPORT OTG_FS_IRQHandler [WEAK] - EXPORT DMA2_Stream5_IRQHandler [WEAK] - EXPORT DMA2_Stream6_IRQHandler [WEAK] - EXPORT DMA2_Stream7_IRQHandler [WEAK] - EXPORT USART6_IRQHandler [WEAK] - EXPORT I2C3_EV_IRQHandler [WEAK] - EXPORT I2C3_ER_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] - EXPORT OTG_HS_WKUP_IRQHandler [WEAK] - EXPORT OTG_HS_IRQHandler [WEAK] - EXPORT DCMI_IRQHandler [WEAK] - EXPORT CRYP_IRQHandler [WEAK] - EXPORT HASH_RNG_IRQHandler [WEAK] - EXPORT FPU_IRQHandler [WEAK] - EXPORT UART7_IRQHandler [WEAK] - EXPORT UART8_IRQHandler [WEAK] - EXPORT SPI4_IRQHandler [WEAK] - EXPORT SPI5_IRQHandler [WEAK] - EXPORT SPI6_IRQHandler [WEAK] - EXPORT SAI1_IRQHandler [WEAK] - EXPORT LTDC_IRQHandler [WEAK] - EXPORT LTDC_ER_IRQHandler [WEAK] - EXPORT DMA2D_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMP_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Stream0_IRQHandler -DMA1_Stream1_IRQHandler -DMA1_Stream2_IRQHandler -DMA1_Stream3_IRQHandler -DMA1_Stream4_IRQHandler -DMA1_Stream5_IRQHandler -DMA1_Stream6_IRQHandler -ADC_IRQHandler -CAN1_TX_IRQHandler -CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_SCE_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_TIM9_IRQHandler -TIM1_UP_TIM10_IRQHandler -TIM1_TRG_COM_TIM11_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -OTG_FS_WKUP_IRQHandler -TIM8_BRK_TIM12_IRQHandler -TIM8_UP_TIM13_IRQHandler -TIM8_TRG_COM_TIM14_IRQHandler -TIM8_CC_IRQHandler -DMA1_Stream7_IRQHandler -FMC_IRQHandler -SDIO_IRQHandler -TIM5_IRQHandler -SPI3_IRQHandler -UART4_IRQHandler -UART5_IRQHandler -TIM6_DAC_IRQHandler -TIM7_IRQHandler -DMA2_Stream0_IRQHandler -DMA2_Stream1_IRQHandler -DMA2_Stream2_IRQHandler -DMA2_Stream3_IRQHandler -DMA2_Stream4_IRQHandler -ETH_IRQHandler -ETH_WKUP_IRQHandler -CAN2_TX_IRQHandler -CAN2_RX0_IRQHandler -CAN2_RX1_IRQHandler -CAN2_SCE_IRQHandler -OTG_FS_IRQHandler -DMA2_Stream5_IRQHandler -DMA2_Stream6_IRQHandler -DMA2_Stream7_IRQHandler -USART6_IRQHandler -I2C3_EV_IRQHandler -I2C3_ER_IRQHandler -OTG_HS_EP1_OUT_IRQHandler -OTG_HS_EP1_IN_IRQHandler -OTG_HS_WKUP_IRQHandler -OTG_HS_IRQHandler -DCMI_IRQHandler -CRYP_IRQHandler -HASH_RNG_IRQHandler -FPU_IRQHandler -UART7_IRQHandler -UART8_IRQHandler -SPI4_IRQHandler -SPI5_IRQHandler -SPI6_IRQHandler -SAI1_IRQHandler -LTDC_IRQHandler -LTDC_ER_IRQHandler -DMA2D_IRQHandler - B . - - ENDP - - ALIGN - END - -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_GCC_ARM/startup_stm32f439xx.S Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_GCC_ARM/startup_stm32f439xx.S Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file startup_stm32f439xx.s * @author MCD Application Team - * @version V2.6.0 - * @date 04-November-2016 * @brief STM32F439xx Devices vector table for GCC based toolchains. * This module performs: * - Set the initial SP @@ -16,7 +14,7 @@ ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2016 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2017 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -58,6 +56,10 @@ .word _sdata /* end address for the .data section. defined in linker script */ .word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss /* stack used for SystemInit_ExtMemCtl; always internal RAM used */ /** @@ -91,6 +93,17 @@ adds r2, r0, r1 cmp r2, r3 bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss /* Call the clock system intitialization function.*/ bl SystemInit
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_IAR/startup_stm32f439xx.S Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/TOOLCHAIN_IAR/startup_stm32f439xx.S Tue Mar 20 16:56:18 2018 +0000
@@ -1,8 +1,6 @@
-;/******************** (C) COPYRIGHT 2016 STMicroelectronics ********************
+;/******************** (C) COPYRIGHT 2017 STMicroelectronics ********************
;* File Name : startup_stm32f439xx.s
;* Author : MCD Application Team
-;* Version : V2.6.0
-;* Date : 04-November-2016
;* Description : STM32F439xx devices vector table for EWARM toolchain.
;* This module performs:
;* - Set the initial SP
@@ -649,13 +647,13 @@
B FPU_IRQHandler
PUBWEAK UART7_IRQHandler
- SECTION .text:CODE:REORDER:NOROOT(1)
+ SECTION .text:CODE:REORDER:NOROOT(1)
UART7_IRQHandler
B UART7_IRQHandler
PUBWEAK UART8_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
-UART8_IRQHandler
+UART8_IRQHandler
B UART8_IRQHandler
PUBWEAK SPI4_IRQHandler
@@ -665,7 +663,7 @@
PUBWEAK SPI5_IRQHandler
SECTION .text:CODE:REORDER:NOROOT(1)
-SPI5_IRQHandler
+SPI5_IRQHandler
B SPI5_IRQHandler
PUBWEAK SPI6_IRQHandler
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/stm32f439xx.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/stm32f439xx.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f439xx.h * @author MCD Application Team - * @version V2.6.1 - * @date 14-February-2017 * @brief CMSIS STM32F439xx Device Peripheral Access Layer Header File. * * This file contains: @@ -67,9 +65,11 @@ #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */ #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +/* MBED */ #ifndef __FPU_PRESENT #define __FPU_PRESENT 1U /*!< FPU present */ #endif /* __FPU_PRESENT */ +/* MBED */ /** * @} @@ -14385,7 +14385,7 @@ #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */ #define USART_CR1_TXEIE_Pos (7U) #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */ -#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<PE Interrupt Enable */ +#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<TXE Interrupt Enable */ #define USART_CR1_PEIE_Pos (8U) #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */ #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */ @@ -16197,92 +16197,6 @@ #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */ #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */ -/******************** Bit definition for OTG register ********************/ - -#define USB_OTG_CHNUM_Pos (0U) -#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */ -#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */ -#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */ -#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */ -#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */ -#define USB_OTG_BCNT_Pos (4U) -#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */ - -#define USB_OTG_DPID_Pos (15U) -#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */ -#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */ -#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */ - -#define USB_OTG_PKTSTS_Pos (17U) -#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */ -#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */ -#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */ -#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */ -#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */ - -#define USB_OTG_EPNUM_Pos (0U) -#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */ -#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */ -#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */ -#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */ -#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */ - -#define USB_OTG_FRMNUM_Pos (21U) -#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */ -#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */ -#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */ -#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */ -#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */ -#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */ - -/******************** Bit definition for OTG register ********************/ - -#define USB_OTG_CHNUM_Pos (0U) -#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */ -#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */ -#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */ -#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */ -#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */ -#define USB_OTG_BCNT_Pos (4U) -#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */ - -#define USB_OTG_DPID_Pos (15U) -#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */ -#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */ -#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */ - -#define USB_OTG_PKTSTS_Pos (17U) -#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */ -#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */ -#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */ -#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */ -#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */ - -#define USB_OTG_EPNUM_Pos (0U) -#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */ -#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */ -#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */ -#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */ -#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */ - -#define USB_OTG_FRMNUM_Pos (21U) -#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */ -#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */ -#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */ -#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */ -#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */ -#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */ - /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/ #define USB_OTG_GRXFSIZ_RXFD_Pos (0U) #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */ @@ -16928,6 +16842,48 @@ #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */ #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */ +/* Legacy define */ +/******************** Bit definition for OTG register ********************/ +#define USB_OTG_CHNUM_Pos (0U) +#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */ +#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */ +#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */ +#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */ +#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */ +#define USB_OTG_BCNT_Pos (4U) +#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */ + +#define USB_OTG_DPID_Pos (15U) +#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */ +#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */ +#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */ + +#define USB_OTG_PKTSTS_Pos (17U) +#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */ +#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */ +#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */ +#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */ + +#define USB_OTG_EPNUM_Pos (0U) +#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */ +#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */ +#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */ +#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */ +#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */ + +#define USB_OTG_FRMNUM_Pos (21U) +#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */ +#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */ +#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */ +#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */ /** * @} */
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/stm32f4xx.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/stm32f4xx.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx.h
* @author MCD Application Team
- * @version V2.6.1
- * @date 14-February-2017
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@@ -124,11 +122,11 @@
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS version number V2.6.1
+ * @brief CMSIS version number V2.6.2
*/
#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
-#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/system_stm32f4xx.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F439xI/device/system_stm32f4xx.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file system_stm32f4xx.h * @author MCD Application Team - * @version V2.6.1 - * @date 14-February-2017 * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_B96B_F446VE/system_clock.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_B96B_F446VE/system_clock.c Tue Mar 20 16:56:18 2018 +0000
@@ -224,7 +224,7 @@
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
- RCC_OscInitStruct.HSICalibrationValue = 16;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/system_clock.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446RE/system_clock.c Tue Mar 20 16:56:18 2018 +0000
@@ -222,7 +222,7 @@
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
- RCC_OscInitStruct.HSICalibrationValue = 16;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/system_clock.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/TARGET_NUCLEO_F446ZE/system_clock.c Tue Mar 20 16:56:18 2018 +0000
@@ -235,7 +235,7 @@
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
- RCC_OscInitStruct.HSICalibrationValue = 16;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_ARM_MICRO/startup_stm32f446xx.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,438 @@ +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f446xx.s +;* Author : MCD Application Team +;* Description : STM32F446x devices vector table for MDK-ARM_MICRO toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20020000 ; Top of RAM + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI4_IRQHandler ; SPI4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SAI1_IRQHandler ; SAI1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SAI2_IRQHandler ; SAI2 + DCD QuadSPI_IRQHandler ; QuadSPI + DCD CEC_IRQHandler ; CEC + DCD SPDIF_RX_IRQHandler ; SPDIF RX + DCD I2C4_Event_IRQHandler ; I2C 4 Event + DCD I2C4_Error_IRQHandler ; I2C 4 Error +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT SAI2_IRQHandler [WEAK] + EXPORT QuadSPI_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT SPDIF_RX_IRQHandler [WEAK] + EXPORT I2C4_Event_IRQHandler [WEAK] + EXPORT I2C4_Error_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +FPU_IRQHandler +SPI4_IRQHandler +SAI1_IRQHandler +SAI2_IRQHandler +QuadSPI_IRQHandler +CEC_IRQHandler +SPDIF_RX_IRQHandler +I2C4_Event_IRQHandler +I2C4_Error_IRQHandler + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_ARM_MICRO/startup_stm32f446xx.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,440 +0,0 @@ -;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** -;* File Name : startup_stm32f446xx.s -;* Author : MCD Application Team -;* Version : V2.3.2 -;* Date : 26-June-2015 -;* Description : STM32F446x devices vector table for MDK-ARM_MICRO toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* After Reset the CortexM4 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;******************************************************************************* - -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; <h> Stack Configuration -; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; </h> - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 - EXPORT __initial_sp - -Stack_Mem SPACE Stack_Size -__initial_sp EQU 0x20020000 ; Top of RAM - - -; <h> Heap Configuration -; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; </h> - -Heap_Size EQU 0x00000400 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 - EXPORT __heap_base - EXPORT __heap_limit - -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit EQU (__initial_sp - Stack_Size) - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 - DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 - DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FMC_IRQHandler ; FMC - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD FPU_IRQHandler ; FPU - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SPI4_IRQHandler ; SPI4 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SAI1_IRQHandler ; SAI1 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SAI2_IRQHandler ; SAI2 - DCD QuadSPI_IRQHandler ; QuadSPI - DCD CEC_IRQHandler ; CEC - DCD SPDIF_RX_IRQHandler ; SPDIF RX - DCD I2C4_Event_IRQHandler ; I2C 4 Event - DCD I2C4_Error_IRQHandler ; I2C 4 Error -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMP_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Stream0_IRQHandler [WEAK] - EXPORT DMA1_Stream1_IRQHandler [WEAK] - EXPORT DMA1_Stream2_IRQHandler [WEAK] - EXPORT DMA1_Stream3_IRQHandler [WEAK] - EXPORT DMA1_Stream4_IRQHandler [WEAK] - EXPORT DMA1_Stream5_IRQHandler [WEAK] - EXPORT DMA1_Stream6_IRQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT CAN1_TX_IRQHandler [WEAK] - EXPORT CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_SCE_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] - EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT OTG_FS_WKUP_IRQHandler [WEAK] - EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] - EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] - EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] - EXPORT TIM8_CC_IRQHandler [WEAK] - EXPORT DMA1_Stream7_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT SDIO_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT UART5_IRQHandler [WEAK] - EXPORT TIM6_DAC_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - EXPORT DMA2_Stream0_IRQHandler [WEAK] - EXPORT DMA2_Stream1_IRQHandler [WEAK] - EXPORT DMA2_Stream2_IRQHandler [WEAK] - EXPORT DMA2_Stream3_IRQHandler [WEAK] - EXPORT DMA2_Stream4_IRQHandler [WEAK] - EXPORT CAN2_TX_IRQHandler [WEAK] - EXPORT CAN2_RX0_IRQHandler [WEAK] - EXPORT CAN2_RX1_IRQHandler [WEAK] - EXPORT CAN2_SCE_IRQHandler [WEAK] - EXPORT OTG_FS_IRQHandler [WEAK] - EXPORT DMA2_Stream5_IRQHandler [WEAK] - EXPORT DMA2_Stream6_IRQHandler [WEAK] - EXPORT DMA2_Stream7_IRQHandler [WEAK] - EXPORT USART6_IRQHandler [WEAK] - EXPORT I2C3_EV_IRQHandler [WEAK] - EXPORT I2C3_ER_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] - EXPORT OTG_HS_WKUP_IRQHandler [WEAK] - EXPORT OTG_HS_IRQHandler [WEAK] - EXPORT DCMI_IRQHandler [WEAK] - EXPORT FPU_IRQHandler [WEAK] - EXPORT SPI4_IRQHandler [WEAK] - EXPORT SAI1_IRQHandler [WEAK] - EXPORT SPI4_IRQHandler [WEAK] - EXPORT SAI1_IRQHandler [WEAK] - EXPORT SAI2_IRQHandler [WEAK] - EXPORT QuadSPI_IRQHandler [WEAK] - EXPORT CEC_IRQHandler [WEAK] - EXPORT SPDIF_RX_IRQHandler [WEAK] - EXPORT I2C4_Event_IRQHandler [WEAK] - EXPORT I2C4_Error_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMP_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Stream0_IRQHandler -DMA1_Stream1_IRQHandler -DMA1_Stream2_IRQHandler -DMA1_Stream3_IRQHandler -DMA1_Stream4_IRQHandler -DMA1_Stream5_IRQHandler -DMA1_Stream6_IRQHandler -ADC_IRQHandler -CAN1_TX_IRQHandler -CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_SCE_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_TIM9_IRQHandler -TIM1_UP_TIM10_IRQHandler -TIM1_TRG_COM_TIM11_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -OTG_FS_WKUP_IRQHandler -TIM8_BRK_TIM12_IRQHandler -TIM8_UP_TIM13_IRQHandler -TIM8_TRG_COM_TIM14_IRQHandler -TIM8_CC_IRQHandler -DMA1_Stream7_IRQHandler -FMC_IRQHandler -SDIO_IRQHandler -TIM5_IRQHandler -SPI3_IRQHandler -UART4_IRQHandler -UART5_IRQHandler -TIM6_DAC_IRQHandler -TIM7_IRQHandler -DMA2_Stream0_IRQHandler -DMA2_Stream1_IRQHandler -DMA2_Stream2_IRQHandler -DMA2_Stream3_IRQHandler -DMA2_Stream4_IRQHandler -CAN2_TX_IRQHandler -CAN2_RX0_IRQHandler -CAN2_RX1_IRQHandler -CAN2_SCE_IRQHandler -OTG_FS_IRQHandler -DMA2_Stream5_IRQHandler -DMA2_Stream6_IRQHandler -DMA2_Stream7_IRQHandler -USART6_IRQHandler -I2C3_EV_IRQHandler -I2C3_ER_IRQHandler -OTG_HS_EP1_OUT_IRQHandler -OTG_HS_EP1_IN_IRQHandler -OTG_HS_WKUP_IRQHandler -OTG_HS_IRQHandler -DCMI_IRQHandler -FPU_IRQHandler -SPI4_IRQHandler -SAI1_IRQHandler -SAI2_IRQHandler -QuadSPI_IRQHandler -CEC_IRQHandler -SPDIF_RX_IRQHandler -I2C4_Event_IRQHandler -I2C4_Error_IRQHandler - B . - - ENDP - - ALIGN - END - -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_ARM_STD/startup_stm32f446xx.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,411 @@ +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f446xx.s +;* Author : MCD Application Team +;* Description : STM32F446x devices vector table for MDK-ARM_STD toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +__initial_sp EQU 0x20020000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI4_IRQHandler ; SPI4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SAI1_IRQHandler ; SAI1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SAI2_IRQHandler ; SAI2 + DCD QuadSPI_IRQHandler ; QuadSPI + DCD CEC_IRQHandler ; CEC + DCD SPDIF_RX_IRQHandler ; SPDIF RX + DCD I2C4_Event_IRQHandler ; I2C 4 Event + DCD I2C4_Error_IRQHandler ; I2C 4 Error +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT SAI2_IRQHandler [WEAK] + EXPORT QuadSPI_IRQHandler [WEAK] + EXPORT CEC_IRQHandler [WEAK] + EXPORT SPDIF_RX_IRQHandler [WEAK] + EXPORT I2C4_Event_IRQHandler [WEAK] + EXPORT I2C4_Error_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +FPU_IRQHandler +SPI4_IRQHandler +SAI1_IRQHandler +SAI2_IRQHandler +QuadSPI_IRQHandler +CEC_IRQHandler +SPDIF_RX_IRQHandler +I2C4_Event_IRQHandler +I2C4_Error_IRQHandler + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_ARM_STD/startup_stm32f446xx.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,413 +0,0 @@ -;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** -;* File Name : startup_stm32f446xx.s -;* Author : MCD Application Team -;* Version : V2.3.2 -;* Date : 26-June-2015 -;* Description : STM32F446x devices vector table for MDK-ARM_STD toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* After Reset the CortexM4 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;******************************************************************************* - -__initial_sp EQU 0x20020000 ; Top of RAM - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 - DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 - DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FMC_IRQHandler ; FMC - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD FPU_IRQHandler ; FPU - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SPI4_IRQHandler ; SPI4 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SAI1_IRQHandler ; SAI1 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SAI2_IRQHandler ; SAI2 - DCD QuadSPI_IRQHandler ; QuadSPI - DCD CEC_IRQHandler ; CEC - DCD SPDIF_RX_IRQHandler ; SPDIF RX - DCD I2C4_Event_IRQHandler ; I2C 4 Event - DCD I2C4_Error_IRQHandler ; I2C 4 Error -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMP_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Stream0_IRQHandler [WEAK] - EXPORT DMA1_Stream1_IRQHandler [WEAK] - EXPORT DMA1_Stream2_IRQHandler [WEAK] - EXPORT DMA1_Stream3_IRQHandler [WEAK] - EXPORT DMA1_Stream4_IRQHandler [WEAK] - EXPORT DMA1_Stream5_IRQHandler [WEAK] - EXPORT DMA1_Stream6_IRQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT CAN1_TX_IRQHandler [WEAK] - EXPORT CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_SCE_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] - EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT OTG_FS_WKUP_IRQHandler [WEAK] - EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] - EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] - EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] - EXPORT TIM8_CC_IRQHandler [WEAK] - EXPORT DMA1_Stream7_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT SDIO_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT UART5_IRQHandler [WEAK] - EXPORT TIM6_DAC_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - EXPORT DMA2_Stream0_IRQHandler [WEAK] - EXPORT DMA2_Stream1_IRQHandler [WEAK] - EXPORT DMA2_Stream2_IRQHandler [WEAK] - EXPORT DMA2_Stream3_IRQHandler [WEAK] - EXPORT DMA2_Stream4_IRQHandler [WEAK] - EXPORT CAN2_TX_IRQHandler [WEAK] - EXPORT CAN2_RX0_IRQHandler [WEAK] - EXPORT CAN2_RX1_IRQHandler [WEAK] - EXPORT CAN2_SCE_IRQHandler [WEAK] - EXPORT OTG_FS_IRQHandler [WEAK] - EXPORT DMA2_Stream5_IRQHandler [WEAK] - EXPORT DMA2_Stream6_IRQHandler [WEAK] - EXPORT DMA2_Stream7_IRQHandler [WEAK] - EXPORT USART6_IRQHandler [WEAK] - EXPORT I2C3_EV_IRQHandler [WEAK] - EXPORT I2C3_ER_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] - EXPORT OTG_HS_WKUP_IRQHandler [WEAK] - EXPORT OTG_HS_IRQHandler [WEAK] - EXPORT DCMI_IRQHandler [WEAK] - EXPORT FPU_IRQHandler [WEAK] - EXPORT SPI4_IRQHandler [WEAK] - EXPORT SAI1_IRQHandler [WEAK] - EXPORT SPI4_IRQHandler [WEAK] - EXPORT SAI1_IRQHandler [WEAK] - EXPORT SAI2_IRQHandler [WEAK] - EXPORT QuadSPI_IRQHandler [WEAK] - EXPORT CEC_IRQHandler [WEAK] - EXPORT SPDIF_RX_IRQHandler [WEAK] - EXPORT I2C4_Event_IRQHandler [WEAK] - EXPORT I2C4_Error_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMP_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Stream0_IRQHandler -DMA1_Stream1_IRQHandler -DMA1_Stream2_IRQHandler -DMA1_Stream3_IRQHandler -DMA1_Stream4_IRQHandler -DMA1_Stream5_IRQHandler -DMA1_Stream6_IRQHandler -ADC_IRQHandler -CAN1_TX_IRQHandler -CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_SCE_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_TIM9_IRQHandler -TIM1_UP_TIM10_IRQHandler -TIM1_TRG_COM_TIM11_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -OTG_FS_WKUP_IRQHandler -TIM8_BRK_TIM12_IRQHandler -TIM8_UP_TIM13_IRQHandler -TIM8_TRG_COM_TIM14_IRQHandler -TIM8_CC_IRQHandler -DMA1_Stream7_IRQHandler -FMC_IRQHandler -SDIO_IRQHandler -TIM5_IRQHandler -SPI3_IRQHandler -UART4_IRQHandler -UART5_IRQHandler -TIM6_DAC_IRQHandler -TIM7_IRQHandler -DMA2_Stream0_IRQHandler -DMA2_Stream1_IRQHandler -DMA2_Stream2_IRQHandler -DMA2_Stream3_IRQHandler -DMA2_Stream4_IRQHandler -CAN2_TX_IRQHandler -CAN2_RX0_IRQHandler -CAN2_RX1_IRQHandler -CAN2_SCE_IRQHandler -OTG_FS_IRQHandler -DMA2_Stream5_IRQHandler -DMA2_Stream6_IRQHandler -DMA2_Stream7_IRQHandler -USART6_IRQHandler -I2C3_EV_IRQHandler -I2C3_ER_IRQHandler -OTG_HS_EP1_OUT_IRQHandler -OTG_HS_EP1_IN_IRQHandler -OTG_HS_WKUP_IRQHandler -OTG_HS_IRQHandler -DCMI_IRQHandler -FPU_IRQHandler -SPI4_IRQHandler -SAI1_IRQHandler -SAI2_IRQHandler -QuadSPI_IRQHandler -CEC_IRQHandler -SPDIF_RX_IRQHandler -I2C4_Event_IRQHandler -I2C4_Error_IRQHandler - B . - - ENDP - - ALIGN - END - -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_GCC_ARM/startup_stm32f446xx.S Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_GCC_ARM/startup_stm32f446xx.S Tue Mar 20 16:56:18 2018 +0000 @@ -2,9 +2,7 @@ ****************************************************************************** * @file startup_stm32f446xx.s * @author MCD Application Team - * @version V2.3.0 - * @date 02-March-2015 - * @brief STM32F446xx Devices vector table for Atollic TrueSTUDIO toolchain. + * @brief STM32F446xx Devices vector table for GCC based toolchains. * This module performs: * - Set the initial SP * - Set the initial PC == Reset_Handler, @@ -16,7 +14,7 @@ ****************************************************************************** * @attention * - * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> + * <h2><center>© COPYRIGHT 2017 STMicroelectronics</center></h2> * * Redistribution and use in source and binary forms, with or without modification, * are permitted provided that the following conditions are met: @@ -58,6 +56,10 @@ .word _sdata /* end address for the .data section. defined in linker script */ .word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss /* stack used for SystemInit_ExtMemCtl; always internal RAM used */ /** @@ -91,6 +93,17 @@ adds r2, r0, r1 cmp r2, r3 bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss /* Call the clock system intitialization function.*/ bl SystemInit
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_IAR/startup_stm32f446xx.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,676 @@ +;/******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f446xx.s +;* Author : MCD Application Team +;* Description : STM32F446xx devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD FPU_IRQHandler ; FPU + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SPI4_IRQHandler ; SPI4 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SAI1_IRQHandler ; SAI1 + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SAI2_IRQHandler ; SAI2 + DCD QUADSPI_IRQHandler ; QuadSPI + DCD CEC_IRQHandler ; CEC + DCD SPDIF_RX_IRQHandler ; SPDIF RX + DCD FMPI2C1_Event_IRQHandler ; FMPI2C1 Event + DCD FMPI2C1_Error_IRQHandler ; FMPI2C1 Error + ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream0_IRQHandler + B DMA1_Stream0_IRQHandler + + PUBWEAK DMA1_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream1_IRQHandler + B DMA1_Stream1_IRQHandler + + PUBWEAK DMA1_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream2_IRQHandler + B DMA1_Stream2_IRQHandler + + PUBWEAK DMA1_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream3_IRQHandler + B DMA1_Stream3_IRQHandler + + PUBWEAK DMA1_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream4_IRQHandler + B DMA1_Stream4_IRQHandler + + PUBWEAK DMA1_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream5_IRQHandler + B DMA1_Stream5_IRQHandler + + PUBWEAK DMA1_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream6_IRQHandler + B DMA1_Stream6_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK CAN1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_TX_IRQHandler + B CAN1_TX_IRQHandler + + PUBWEAK CAN1_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_RX0_IRQHandler + B CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_BRK_TIM9_IRQHandler + B TIM1_BRK_TIM9_IRQHandler + + PUBWEAK TIM1_UP_TIM10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_UP_TIM10_IRQHandler + B TIM1_UP_TIM10_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_TRG_COM_TIM11_IRQHandler + B TIM1_TRG_COM_TIM11_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_WKUP_IRQHandler + B OTG_FS_WKUP_IRQHandler + + PUBWEAK TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_BRK_TIM12_IRQHandler + B TIM8_BRK_TIM12_IRQHandler + + PUBWEAK TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_UP_TIM13_IRQHandler + B TIM8_UP_TIM13_IRQHandler + + PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_TRG_COM_TIM14_IRQHandler + B TIM8_TRG_COM_TIM14_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK DMA1_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream7_IRQHandler + B DMA1_Stream7_IRQHandler + + PUBWEAK FMC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FMC_IRQHandler + B FMC_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SDIO_IRQHandler + B SDIO_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream0_IRQHandler + B DMA2_Stream0_IRQHandler + + PUBWEAK DMA2_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream1_IRQHandler + B DMA2_Stream1_IRQHandler + + PUBWEAK DMA2_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream2_IRQHandler + B DMA2_Stream2_IRQHandler + + PUBWEAK DMA2_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream3_IRQHandler + B DMA2_Stream3_IRQHandler + + PUBWEAK DMA2_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream4_IRQHandler + B DMA2_Stream4_IRQHandler + + PUBWEAK CAN2_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_TX_IRQHandler + B CAN2_TX_IRQHandler + + PUBWEAK CAN2_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_RX0_IRQHandler + B CAN2_RX0_IRQHandler + + PUBWEAK CAN2_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_RX1_IRQHandler + B CAN2_RX1_IRQHandler + + PUBWEAK CAN2_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_SCE_IRQHandler + B CAN2_SCE_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + PUBWEAK DMA2_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream5_IRQHandler + B DMA2_Stream5_IRQHandler + + PUBWEAK DMA2_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream6_IRQHandler + B DMA2_Stream6_IRQHandler + + PUBWEAK DMA2_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream7_IRQHandler + B DMA2_Stream7_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_EP1_OUT_IRQHandler + B OTG_HS_EP1_OUT_IRQHandler + + PUBWEAK OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_EP1_IN_IRQHandler + B OTG_HS_EP1_IN_IRQHandler + + PUBWEAK OTG_HS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_WKUP_IRQHandler + B OTG_HS_WKUP_IRQHandler + + PUBWEAK OTG_HS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_IRQHandler + B OTG_HS_IRQHandler + + PUBWEAK DCMI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DCMI_IRQHandler + B DCMI_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK SPI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI4_IRQHandler + B SPI4_IRQHandler + + PUBWEAK SAI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SAI1_IRQHandler + B SAI1_IRQHandler + + PUBWEAK SAI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SAI2_IRQHandler + B SAI2_IRQHandler + + PUBWEAK QUADSPI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +QUADSPI_IRQHandler + B QUADSPI_IRQHandler + + PUBWEAK CEC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CEC_IRQHandler + B CEC_IRQHandler + + PUBWEAK SPDIF_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPDIF_RX_IRQHandler + B SPDIF_RX_IRQHandler + + PUBWEAK FMPI2C1_Event_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FMPI2C1_Event_IRQHandler + B FMPI2C1_Event_IRQHandler + + PUBWEAK FMPI2C1_Error_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FMPI2C1_Error_IRQHandler + B FMPI2C1_Error_IRQHandler + + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/TOOLCHAIN_IAR/startup_stm32f446xx.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,678 +0,0 @@ -;/******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** -;* File Name : startup_stm32f446xx.s -;* Author : MCD Application Team -;* Version : V2.3.2 -;* Date : 26-June-2015 -;* Description : STM32F446xx devices vector table for EWARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == _iar_program_start, -;* - Set the vector table entries with the exceptions ISR -;* address. -;* - Branches to main in the C library (which eventually -;* calls main()). -;* After Reset the Cortex-M4 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;******************************************************************************** -;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;* -;******************************************************************************* -; -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler ; Reset Handler - - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 - DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 - DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FMC_IRQHandler ; FMC - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD FPU_IRQHandler ; FPU - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SPI4_IRQHandler ; SPI4 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SAI1_IRQHandler ; SAI1 - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SAI2_IRQHandler ; SAI2 - DCD QuadSPI_IRQHandler ; QuadSPI - DCD CEC_IRQHandler ; CEC - DCD SPDIF_RX_IRQHandler ; SPDIF RX - DCD FMPI2C1_Event_IRQHandler ; FMPI2C1 Event - DCD FMPI2C1_Error_IRQHandler ; FMPI2C1 Error - ;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK WWDG_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -WWDG_IRQHandler - B WWDG_IRQHandler - - PUBWEAK PVD_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PVD_IRQHandler - B PVD_IRQHandler - - PUBWEAK TAMP_STAMP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TAMP_STAMP_IRQHandler - B TAMP_STAMP_IRQHandler - - PUBWEAK RTC_WKUP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC_WKUP_IRQHandler - B RTC_WKUP_IRQHandler - - PUBWEAK FLASH_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FLASH_IRQHandler - B FLASH_IRQHandler - - PUBWEAK RCC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RCC_IRQHandler - B RCC_IRQHandler - - PUBWEAK EXTI0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI0_IRQHandler - B EXTI0_IRQHandler - - PUBWEAK EXTI1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI1_IRQHandler - B EXTI1_IRQHandler - - PUBWEAK EXTI2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI2_IRQHandler - B EXTI2_IRQHandler - - PUBWEAK EXTI3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI3_IRQHandler - B EXTI3_IRQHandler - - PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI4_IRQHandler - B EXTI4_IRQHandler - - PUBWEAK DMA1_Stream0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream0_IRQHandler - B DMA1_Stream0_IRQHandler - - PUBWEAK DMA1_Stream1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream1_IRQHandler - B DMA1_Stream1_IRQHandler - - PUBWEAK DMA1_Stream2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream2_IRQHandler - B DMA1_Stream2_IRQHandler - - PUBWEAK DMA1_Stream3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream3_IRQHandler - B DMA1_Stream3_IRQHandler - - PUBWEAK DMA1_Stream4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream4_IRQHandler - B DMA1_Stream4_IRQHandler - - PUBWEAK DMA1_Stream5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream5_IRQHandler - B DMA1_Stream5_IRQHandler - - PUBWEAK DMA1_Stream6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream6_IRQHandler - B DMA1_Stream6_IRQHandler - - PUBWEAK ADC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ADC_IRQHandler - B ADC_IRQHandler - - PUBWEAK CAN1_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN1_TX_IRQHandler - B CAN1_TX_IRQHandler - - PUBWEAK CAN1_RX0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN1_RX0_IRQHandler - B CAN1_RX0_IRQHandler - - PUBWEAK CAN1_RX1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN1_RX1_IRQHandler - B CAN1_RX1_IRQHandler - - PUBWEAK CAN1_SCE_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN1_SCE_IRQHandler - B CAN1_SCE_IRQHandler - - PUBWEAK EXTI9_5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI9_5_IRQHandler - B EXTI9_5_IRQHandler - - PUBWEAK TIM1_BRK_TIM9_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM1_BRK_TIM9_IRQHandler - B TIM1_BRK_TIM9_IRQHandler - - PUBWEAK TIM1_UP_TIM10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM1_UP_TIM10_IRQHandler - B TIM1_UP_TIM10_IRQHandler - - PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM1_TRG_COM_TIM11_IRQHandler - B TIM1_TRG_COM_TIM11_IRQHandler - - PUBWEAK TIM1_CC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM1_CC_IRQHandler - B TIM1_CC_IRQHandler - - PUBWEAK TIM2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM2_IRQHandler - B TIM2_IRQHandler - - PUBWEAK TIM3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM3_IRQHandler - B TIM3_IRQHandler - - PUBWEAK TIM4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM4_IRQHandler - B TIM4_IRQHandler - - PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C1_EV_IRQHandler - B I2C1_EV_IRQHandler - - PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C1_ER_IRQHandler - B I2C1_ER_IRQHandler - - PUBWEAK I2C2_EV_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C2_EV_IRQHandler - B I2C2_EV_IRQHandler - - PUBWEAK I2C2_ER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C2_ER_IRQHandler - B I2C2_ER_IRQHandler - - PUBWEAK SPI1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI1_IRQHandler - B SPI1_IRQHandler - - PUBWEAK SPI2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI2_IRQHandler - B SPI2_IRQHandler - - PUBWEAK USART1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART1_IRQHandler - B USART1_IRQHandler - - PUBWEAK USART2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART2_IRQHandler - B USART2_IRQHandler - - PUBWEAK USART3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART3_IRQHandler - B USART3_IRQHandler - - PUBWEAK EXTI15_10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI15_10_IRQHandler - B EXTI15_10_IRQHandler - - PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC_Alarm_IRQHandler - B RTC_Alarm_IRQHandler - - PUBWEAK OTG_FS_WKUP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -OTG_FS_WKUP_IRQHandler - B OTG_FS_WKUP_IRQHandler - - PUBWEAK TIM8_BRK_TIM12_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM8_BRK_TIM12_IRQHandler - B TIM8_BRK_TIM12_IRQHandler - - PUBWEAK TIM8_UP_TIM13_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM8_UP_TIM13_IRQHandler - B TIM8_UP_TIM13_IRQHandler - - PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM8_TRG_COM_TIM14_IRQHandler - B TIM8_TRG_COM_TIM14_IRQHandler - - PUBWEAK TIM8_CC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM8_CC_IRQHandler - B TIM8_CC_IRQHandler - - PUBWEAK DMA1_Stream7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream7_IRQHandler - B DMA1_Stream7_IRQHandler - - PUBWEAK FMC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FMC_IRQHandler - B FMC_IRQHandler - - PUBWEAK SDIO_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SDIO_IRQHandler - B SDIO_IRQHandler - - PUBWEAK TIM5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM5_IRQHandler - B TIM5_IRQHandler - - PUBWEAK SPI3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI3_IRQHandler - B SPI3_IRQHandler - - PUBWEAK UART4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART4_IRQHandler - B UART4_IRQHandler - - PUBWEAK UART5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART5_IRQHandler - B UART5_IRQHandler - - PUBWEAK TIM6_DAC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM6_DAC_IRQHandler - B TIM6_DAC_IRQHandler - - PUBWEAK TIM7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM7_IRQHandler - B TIM7_IRQHandler - - PUBWEAK DMA2_Stream0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream0_IRQHandler - B DMA2_Stream0_IRQHandler - - PUBWEAK DMA2_Stream1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream1_IRQHandler - B DMA2_Stream1_IRQHandler - - PUBWEAK DMA2_Stream2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream2_IRQHandler - B DMA2_Stream2_IRQHandler - - PUBWEAK DMA2_Stream3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream3_IRQHandler - B DMA2_Stream3_IRQHandler - - PUBWEAK DMA2_Stream4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream4_IRQHandler - B DMA2_Stream4_IRQHandler - - PUBWEAK CAN2_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN2_TX_IRQHandler - B CAN2_TX_IRQHandler - - PUBWEAK CAN2_RX0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN2_RX0_IRQHandler - B CAN2_RX0_IRQHandler - - PUBWEAK CAN2_RX1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN2_RX1_IRQHandler - B CAN2_RX1_IRQHandler - - PUBWEAK CAN2_SCE_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN2_SCE_IRQHandler - B CAN2_SCE_IRQHandler - - PUBWEAK OTG_FS_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -OTG_FS_IRQHandler - B OTG_FS_IRQHandler - - PUBWEAK DMA2_Stream5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream5_IRQHandler - B DMA2_Stream5_IRQHandler - - PUBWEAK DMA2_Stream6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream6_IRQHandler - B DMA2_Stream6_IRQHandler - - PUBWEAK DMA2_Stream7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream7_IRQHandler - B DMA2_Stream7_IRQHandler - - PUBWEAK USART6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART6_IRQHandler - B USART6_IRQHandler - - PUBWEAK I2C3_EV_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C3_EV_IRQHandler - B I2C3_EV_IRQHandler - - PUBWEAK I2C3_ER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C3_ER_IRQHandler - B I2C3_ER_IRQHandler - - PUBWEAK OTG_HS_EP1_OUT_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -OTG_HS_EP1_OUT_IRQHandler - B OTG_HS_EP1_OUT_IRQHandler - - PUBWEAK OTG_HS_EP1_IN_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -OTG_HS_EP1_IN_IRQHandler - B OTG_HS_EP1_IN_IRQHandler - - PUBWEAK OTG_HS_WKUP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -OTG_HS_WKUP_IRQHandler - B OTG_HS_WKUP_IRQHandler - - PUBWEAK OTG_HS_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -OTG_HS_IRQHandler - B OTG_HS_IRQHandler - - PUBWEAK DCMI_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DCMI_IRQHandler - B DCMI_IRQHandler - - PUBWEAK FPU_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FPU_IRQHandler - B FPU_IRQHandler - - PUBWEAK SPI4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI4_IRQHandler - B SPI4_IRQHandler - - PUBWEAK SAI1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SAI1_IRQHandler - B SAI1_IRQHandler - - PUBWEAK SAI2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SAI2_IRQHandler - B SAI2_IRQHandler - - PUBWEAK QuadSPI_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -QuadSPI_IRQHandler - B QuadSPI_IRQHandler - - PUBWEAK CEC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CEC_IRQHandler - B CEC_IRQHandler - - PUBWEAK SPDIF_RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPDIF_RX_IRQHandler - B SPDIF_RX_IRQHandler - - PUBWEAK FMPI2C1_Event_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FMPI2C1_Event_IRQHandler - B FMPI2C1_Event_IRQHandler - - PUBWEAK FMPI2C1_Error_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FMPI2C1_Error_IRQHandler - B FMPI2C1_Error_IRQHandler - - - END -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/stm32f446xx.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/stm32f446xx.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f446xx.h * @author MCD Application Team - * @version V2.6.1 - * @date 14-February-2017 * @brief CMSIS STM32F446xx Device Peripheral Access Layer Header File. * * This file contains: @@ -67,9 +65,11 @@ #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */ #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +/* MBED */ #ifndef __FPU_PRESENT #define __FPU_PRESENT 1U /*!< FPU present */ #endif /* __FPU_PRESENT */ +/* MBED */ /** * @} @@ -13770,7 +13770,7 @@ #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */ #define USART_CR1_TXEIE_Pos (7U) #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */ -#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<PE Interrupt Enable */ +#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<TXE Interrupt Enable */ #define USART_CR1_PEIE_Pos (8U) #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */ #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */ @@ -14674,92 +14674,6 @@ #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */ #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */ -/******************** Bit definition for OTG register ********************/ - -#define USB_OTG_CHNUM_Pos (0U) -#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */ -#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */ -#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */ -#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */ -#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */ -#define USB_OTG_BCNT_Pos (4U) -#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */ - -#define USB_OTG_DPID_Pos (15U) -#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */ -#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */ -#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */ - -#define USB_OTG_PKTSTS_Pos (17U) -#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */ -#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */ -#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */ -#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */ -#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */ - -#define USB_OTG_EPNUM_Pos (0U) -#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */ -#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */ -#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */ -#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */ -#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */ - -#define USB_OTG_FRMNUM_Pos (21U) -#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */ -#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */ -#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */ -#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */ -#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */ -#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */ - -/******************** Bit definition for OTG register ********************/ - -#define USB_OTG_CHNUM_Pos (0U) -#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */ -#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */ -#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */ -#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */ -#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */ -#define USB_OTG_BCNT_Pos (4U) -#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */ - -#define USB_OTG_DPID_Pos (15U) -#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */ -#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */ -#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */ - -#define USB_OTG_PKTSTS_Pos (17U) -#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */ -#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */ -#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */ -#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */ -#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */ - -#define USB_OTG_EPNUM_Pos (0U) -#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */ -#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */ -#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */ -#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */ -#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */ - -#define USB_OTG_FRMNUM_Pos (21U) -#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */ -#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */ -#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */ -#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */ -#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */ -#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */ - /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/ #define USB_OTG_GRXFSIZ_RXFD_Pos (0U) #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */ @@ -15443,6 +15357,48 @@ #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */ #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */ +/* Legacy define */ +/******************** Bit definition for OTG register ********************/ +#define USB_OTG_CHNUM_Pos (0U) +#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */ +#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */ +#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */ +#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */ +#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */ +#define USB_OTG_BCNT_Pos (4U) +#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */ + +#define USB_OTG_DPID_Pos (15U) +#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */ +#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */ +#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */ + +#define USB_OTG_PKTSTS_Pos (17U) +#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */ +#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */ +#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */ +#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */ + +#define USB_OTG_EPNUM_Pos (0U) +#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */ +#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */ +#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */ +#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */ +#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */ + +#define USB_OTG_FRMNUM_Pos (21U) +#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */ +#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */ +#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */ +#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */ /** * @} */
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/stm32f4xx.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/stm32f4xx.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx.h
* @author MCD Application Team
- * @version V2.6.1
- * @date 14-February-2017
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@@ -124,11 +122,11 @@
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS version number V2.6.1
+ * @brief CMSIS version number V2.6.2
*/
#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
-#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/system_stm32f4xx.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F446xE/device/system_stm32f4xx.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file system_stm32f4xx.h * @author MCD Application Team - * @version V2.6.1 - * @date 14-February-2017 * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/system_clock.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/TARGET_DISCO_F469NI/system_clock.c Tue Mar 20 16:56:18 2018 +0000
@@ -234,7 +234,7 @@
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
- RCC_OscInitStruct.HSICalibrationValue = 16;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_ARM_MICRO/startup_stm32f469xx.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,447 @@ +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f469xx.s +;* Author : MCD Application Team +;* Description : STM32F469x devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +; Amount of memory (in bytes) allocated for Stack +; Tailor this value to your application needs +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Stack_Size EQU 0x00000400 + + AREA STACK, NOINIT, READWRITE, ALIGN=3 + EXPORT __initial_sp + +Stack_Mem SPACE Stack_Size +__initial_sp EQU 0x20050000 ; Top of RAM + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + +Heap_Size EQU 0x00000400 + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 + EXPORT __heap_base + EXPORT __heap_limit + +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit EQU (__initial_sp - Stack_Size) + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD HASH_RNG_IRQHandler ; Hash and Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + DCD QUADSPI_IRQHandler ; QUADSPI + DCD DSI_IRQHandler ; DSI + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT HASH_RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT DSI_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +HASH_RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler +QUADSPI_IRQHandler +DSI_IRQHandler + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_ARM_MICRO/startup_stm32f469xx.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,449 +0,0 @@ -;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** -;* File Name : startup_stm32f469xx.s -;* Author : MCD Application Team -;* Version : V2.4.1 -;* Date : 09-October-2015 -;* Description : STM32F469x devices vector table for MDK-ARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM4 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;******************************************************************************* - -; Amount of memory (in bytes) allocated for Stack -; Tailor this value to your application needs -; <h> Stack Configuration -; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; </h> - -Stack_Size EQU 0x00000400 - - AREA STACK, NOINIT, READWRITE, ALIGN=3 - EXPORT __initial_sp - -Stack_Mem SPACE Stack_Size -__initial_sp EQU 0x20050000 ; Top of RAM - - -; <h> Heap Configuration -; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; </h> - -Heap_Size EQU 0x00000400 - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 - EXPORT __heap_base - EXPORT __heap_limit - -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit EQU (__initial_sp - Stack_Size) - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 - DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 - DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FMC_IRQHandler ; FMC - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD 0 ; Reserved - DCD HASH_RNG_IRQHandler ; Hash and Rng - DCD FPU_IRQHandler ; FPU - DCD UART7_IRQHandler ; UART7 - DCD UART8_IRQHandler ; UART8 - DCD SPI4_IRQHandler ; SPI4 - DCD SPI5_IRQHandler ; SPI5 - DCD SPI6_IRQHandler ; SPI6 - DCD SAI1_IRQHandler ; SAI1 - DCD LTDC_IRQHandler ; LTDC - DCD LTDC_ER_IRQHandler ; LTDC error - DCD DMA2D_IRQHandler ; DMA2D - DCD QUADSPI_IRQHandler ; QUADSPI - DCD DSI_IRQHandler ; DSI - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMP_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Stream0_IRQHandler [WEAK] - EXPORT DMA1_Stream1_IRQHandler [WEAK] - EXPORT DMA1_Stream2_IRQHandler [WEAK] - EXPORT DMA1_Stream3_IRQHandler [WEAK] - EXPORT DMA1_Stream4_IRQHandler [WEAK] - EXPORT DMA1_Stream5_IRQHandler [WEAK] - EXPORT DMA1_Stream6_IRQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT CAN1_TX_IRQHandler [WEAK] - EXPORT CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_SCE_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] - EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT OTG_FS_WKUP_IRQHandler [WEAK] - EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] - EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] - EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] - EXPORT TIM8_CC_IRQHandler [WEAK] - EXPORT DMA1_Stream7_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT SDIO_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT UART5_IRQHandler [WEAK] - EXPORT TIM6_DAC_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - EXPORT DMA2_Stream0_IRQHandler [WEAK] - EXPORT DMA2_Stream1_IRQHandler [WEAK] - EXPORT DMA2_Stream2_IRQHandler [WEAK] - EXPORT DMA2_Stream3_IRQHandler [WEAK] - EXPORT DMA2_Stream4_IRQHandler [WEAK] - EXPORT ETH_IRQHandler [WEAK] - EXPORT ETH_WKUP_IRQHandler [WEAK] - EXPORT CAN2_TX_IRQHandler [WEAK] - EXPORT CAN2_RX0_IRQHandler [WEAK] - EXPORT CAN2_RX1_IRQHandler [WEAK] - EXPORT CAN2_SCE_IRQHandler [WEAK] - EXPORT OTG_FS_IRQHandler [WEAK] - EXPORT DMA2_Stream5_IRQHandler [WEAK] - EXPORT DMA2_Stream6_IRQHandler [WEAK] - EXPORT DMA2_Stream7_IRQHandler [WEAK] - EXPORT USART6_IRQHandler [WEAK] - EXPORT I2C3_EV_IRQHandler [WEAK] - EXPORT I2C3_ER_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] - EXPORT OTG_HS_WKUP_IRQHandler [WEAK] - EXPORT OTG_HS_IRQHandler [WEAK] - EXPORT DCMI_IRQHandler [WEAK] - EXPORT HASH_RNG_IRQHandler [WEAK] - EXPORT FPU_IRQHandler [WEAK] - EXPORT UART7_IRQHandler [WEAK] - EXPORT UART8_IRQHandler [WEAK] - EXPORT SPI4_IRQHandler [WEAK] - EXPORT SPI5_IRQHandler [WEAK] - EXPORT SPI6_IRQHandler [WEAK] - EXPORT SAI1_IRQHandler [WEAK] - EXPORT LTDC_IRQHandler [WEAK] - EXPORT LTDC_ER_IRQHandler [WEAK] - EXPORT DMA2D_IRQHandler [WEAK] - EXPORT QUADSPI_IRQHandler [WEAK] - EXPORT DSI_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMP_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Stream0_IRQHandler -DMA1_Stream1_IRQHandler -DMA1_Stream2_IRQHandler -DMA1_Stream3_IRQHandler -DMA1_Stream4_IRQHandler -DMA1_Stream5_IRQHandler -DMA1_Stream6_IRQHandler -ADC_IRQHandler -CAN1_TX_IRQHandler -CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_SCE_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_TIM9_IRQHandler -TIM1_UP_TIM10_IRQHandler -TIM1_TRG_COM_TIM11_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -OTG_FS_WKUP_IRQHandler -TIM8_BRK_TIM12_IRQHandler -TIM8_UP_TIM13_IRQHandler -TIM8_TRG_COM_TIM14_IRQHandler -TIM8_CC_IRQHandler -DMA1_Stream7_IRQHandler -FMC_IRQHandler -SDIO_IRQHandler -TIM5_IRQHandler -SPI3_IRQHandler -UART4_IRQHandler -UART5_IRQHandler -TIM6_DAC_IRQHandler -TIM7_IRQHandler -DMA2_Stream0_IRQHandler -DMA2_Stream1_IRQHandler -DMA2_Stream2_IRQHandler -DMA2_Stream3_IRQHandler -DMA2_Stream4_IRQHandler -ETH_IRQHandler -ETH_WKUP_IRQHandler -CAN2_TX_IRQHandler -CAN2_RX0_IRQHandler -CAN2_RX1_IRQHandler -CAN2_SCE_IRQHandler -OTG_FS_IRQHandler -DMA2_Stream5_IRQHandler -DMA2_Stream6_IRQHandler -DMA2_Stream7_IRQHandler -USART6_IRQHandler -I2C3_EV_IRQHandler -I2C3_ER_IRQHandler -OTG_HS_EP1_OUT_IRQHandler -OTG_HS_EP1_IN_IRQHandler -OTG_HS_WKUP_IRQHandler -OTG_HS_IRQHandler -DCMI_IRQHandler -HASH_RNG_IRQHandler -FPU_IRQHandler -UART7_IRQHandler -UART8_IRQHandler -SPI4_IRQHandler -SPI5_IRQHandler -SPI6_IRQHandler -SAI1_IRQHandler -LTDC_IRQHandler -LTDC_ER_IRQHandler -DMA2D_IRQHandler -QUADSPI_IRQHandler -DSI_IRQHandler - B . - - ENDP - - ALIGN - END - -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_ARM_STD/startup_stm32f469xx.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,420 @@ +;******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f469xx.s +;* Author : MCD Application Team +;* Description : STM32F469x devices vector table for MDK-ARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == Reset_Handler +;* - Set the vector table entries with the exceptions ISR address +;* - Branches to __main in the C library (which eventually +;* calls main()). +;* After Reset the CortexM4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;* <<< Use Configuration Wizard in Context Menu >>> +;******************************************************************************* +; +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +; +;******************************************************************************* + +__initial_sp EQU 0x20050000 ; Top of RAM + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD HASH_RNG_IRQHandler ; Hash and Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + DCD QUADSPI_IRQHandler ; QUADSPI + DCD DSI_IRQHandler ; DSI + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset handler +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT WWDG_IRQHandler [WEAK] + EXPORT PVD_IRQHandler [WEAK] + EXPORT TAMP_STAMP_IRQHandler [WEAK] + EXPORT RTC_WKUP_IRQHandler [WEAK] + EXPORT FLASH_IRQHandler [WEAK] + EXPORT RCC_IRQHandler [WEAK] + EXPORT EXTI0_IRQHandler [WEAK] + EXPORT EXTI1_IRQHandler [WEAK] + EXPORT EXTI2_IRQHandler [WEAK] + EXPORT EXTI3_IRQHandler [WEAK] + EXPORT EXTI4_IRQHandler [WEAK] + EXPORT DMA1_Stream0_IRQHandler [WEAK] + EXPORT DMA1_Stream1_IRQHandler [WEAK] + EXPORT DMA1_Stream2_IRQHandler [WEAK] + EXPORT DMA1_Stream3_IRQHandler [WEAK] + EXPORT DMA1_Stream4_IRQHandler [WEAK] + EXPORT DMA1_Stream5_IRQHandler [WEAK] + EXPORT DMA1_Stream6_IRQHandler [WEAK] + EXPORT ADC_IRQHandler [WEAK] + EXPORT CAN1_TX_IRQHandler [WEAK] + EXPORT CAN1_RX0_IRQHandler [WEAK] + EXPORT CAN1_RX1_IRQHandler [WEAK] + EXPORT CAN1_SCE_IRQHandler [WEAK] + EXPORT EXTI9_5_IRQHandler [WEAK] + EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] + EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] + EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] + EXPORT TIM1_CC_IRQHandler [WEAK] + EXPORT TIM2_IRQHandler [WEAK] + EXPORT TIM3_IRQHandler [WEAK] + EXPORT TIM4_IRQHandler [WEAK] + EXPORT I2C1_EV_IRQHandler [WEAK] + EXPORT I2C1_ER_IRQHandler [WEAK] + EXPORT I2C2_EV_IRQHandler [WEAK] + EXPORT I2C2_ER_IRQHandler [WEAK] + EXPORT SPI1_IRQHandler [WEAK] + EXPORT SPI2_IRQHandler [WEAK] + EXPORT USART1_IRQHandler [WEAK] + EXPORT USART2_IRQHandler [WEAK] + EXPORT USART3_IRQHandler [WEAK] + EXPORT EXTI15_10_IRQHandler [WEAK] + EXPORT RTC_Alarm_IRQHandler [WEAK] + EXPORT OTG_FS_WKUP_IRQHandler [WEAK] + EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] + EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] + EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] + EXPORT TIM8_CC_IRQHandler [WEAK] + EXPORT DMA1_Stream7_IRQHandler [WEAK] + EXPORT FMC_IRQHandler [WEAK] + EXPORT SDIO_IRQHandler [WEAK] + EXPORT TIM5_IRQHandler [WEAK] + EXPORT SPI3_IRQHandler [WEAK] + EXPORT UART4_IRQHandler [WEAK] + EXPORT UART5_IRQHandler [WEAK] + EXPORT TIM6_DAC_IRQHandler [WEAK] + EXPORT TIM7_IRQHandler [WEAK] + EXPORT DMA2_Stream0_IRQHandler [WEAK] + EXPORT DMA2_Stream1_IRQHandler [WEAK] + EXPORT DMA2_Stream2_IRQHandler [WEAK] + EXPORT DMA2_Stream3_IRQHandler [WEAK] + EXPORT DMA2_Stream4_IRQHandler [WEAK] + EXPORT ETH_IRQHandler [WEAK] + EXPORT ETH_WKUP_IRQHandler [WEAK] + EXPORT CAN2_TX_IRQHandler [WEAK] + EXPORT CAN2_RX0_IRQHandler [WEAK] + EXPORT CAN2_RX1_IRQHandler [WEAK] + EXPORT CAN2_SCE_IRQHandler [WEAK] + EXPORT OTG_FS_IRQHandler [WEAK] + EXPORT DMA2_Stream5_IRQHandler [WEAK] + EXPORT DMA2_Stream6_IRQHandler [WEAK] + EXPORT DMA2_Stream7_IRQHandler [WEAK] + EXPORT USART6_IRQHandler [WEAK] + EXPORT I2C3_EV_IRQHandler [WEAK] + EXPORT I2C3_ER_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] + EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] + EXPORT OTG_HS_WKUP_IRQHandler [WEAK] + EXPORT OTG_HS_IRQHandler [WEAK] + EXPORT DCMI_IRQHandler [WEAK] + EXPORT HASH_RNG_IRQHandler [WEAK] + EXPORT FPU_IRQHandler [WEAK] + EXPORT UART7_IRQHandler [WEAK] + EXPORT UART8_IRQHandler [WEAK] + EXPORT SPI4_IRQHandler [WEAK] + EXPORT SPI5_IRQHandler [WEAK] + EXPORT SPI6_IRQHandler [WEAK] + EXPORT SAI1_IRQHandler [WEAK] + EXPORT LTDC_IRQHandler [WEAK] + EXPORT LTDC_ER_IRQHandler [WEAK] + EXPORT DMA2D_IRQHandler [WEAK] + EXPORT QUADSPI_IRQHandler [WEAK] + EXPORT DSI_IRQHandler [WEAK] + +WWDG_IRQHandler +PVD_IRQHandler +TAMP_STAMP_IRQHandler +RTC_WKUP_IRQHandler +FLASH_IRQHandler +RCC_IRQHandler +EXTI0_IRQHandler +EXTI1_IRQHandler +EXTI2_IRQHandler +EXTI3_IRQHandler +EXTI4_IRQHandler +DMA1_Stream0_IRQHandler +DMA1_Stream1_IRQHandler +DMA1_Stream2_IRQHandler +DMA1_Stream3_IRQHandler +DMA1_Stream4_IRQHandler +DMA1_Stream5_IRQHandler +DMA1_Stream6_IRQHandler +ADC_IRQHandler +CAN1_TX_IRQHandler +CAN1_RX0_IRQHandler +CAN1_RX1_IRQHandler +CAN1_SCE_IRQHandler +EXTI9_5_IRQHandler +TIM1_BRK_TIM9_IRQHandler +TIM1_UP_TIM10_IRQHandler +TIM1_TRG_COM_TIM11_IRQHandler +TIM1_CC_IRQHandler +TIM2_IRQHandler +TIM3_IRQHandler +TIM4_IRQHandler +I2C1_EV_IRQHandler +I2C1_ER_IRQHandler +I2C2_EV_IRQHandler +I2C2_ER_IRQHandler +SPI1_IRQHandler +SPI2_IRQHandler +USART1_IRQHandler +USART2_IRQHandler +USART3_IRQHandler +EXTI15_10_IRQHandler +RTC_Alarm_IRQHandler +OTG_FS_WKUP_IRQHandler +TIM8_BRK_TIM12_IRQHandler +TIM8_UP_TIM13_IRQHandler +TIM8_TRG_COM_TIM14_IRQHandler +TIM8_CC_IRQHandler +DMA1_Stream7_IRQHandler +FMC_IRQHandler +SDIO_IRQHandler +TIM5_IRQHandler +SPI3_IRQHandler +UART4_IRQHandler +UART5_IRQHandler +TIM6_DAC_IRQHandler +TIM7_IRQHandler +DMA2_Stream0_IRQHandler +DMA2_Stream1_IRQHandler +DMA2_Stream2_IRQHandler +DMA2_Stream3_IRQHandler +DMA2_Stream4_IRQHandler +ETH_IRQHandler +ETH_WKUP_IRQHandler +CAN2_TX_IRQHandler +CAN2_RX0_IRQHandler +CAN2_RX1_IRQHandler +CAN2_SCE_IRQHandler +OTG_FS_IRQHandler +DMA2_Stream5_IRQHandler +DMA2_Stream6_IRQHandler +DMA2_Stream7_IRQHandler +USART6_IRQHandler +I2C3_EV_IRQHandler +I2C3_ER_IRQHandler +OTG_HS_EP1_OUT_IRQHandler +OTG_HS_EP1_IN_IRQHandler +OTG_HS_WKUP_IRQHandler +OTG_HS_IRQHandler +DCMI_IRQHandler +HASH_RNG_IRQHandler +FPU_IRQHandler +UART7_IRQHandler +UART8_IRQHandler +SPI4_IRQHandler +SPI5_IRQHandler +SPI6_IRQHandler +SAI1_IRQHandler +LTDC_IRQHandler +LTDC_ER_IRQHandler +DMA2D_IRQHandler +QUADSPI_IRQHandler +DSI_IRQHandler + B . + + ENDP + + ALIGN + END + +;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_ARM_STD/startup_stm32f469xx.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,422 +0,0 @@ -;******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** -;* File Name : startup_stm32f469xx.s -;* Author : MCD Application Team -;* Version : V2.4.1 -;* Date : 09-October-2015 -;* Description : STM32F469x devices vector table for MDK-ARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == Reset_Handler -;* - Set the vector table entries with the exceptions ISR address -;* - Branches to __main in the C library (which eventually -;* calls main()). -;* After Reset the CortexM4 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;* <<< Use Configuration Wizard in Context Menu >>> -;******************************************************************************* -; -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -; -;******************************************************************************* - -__initial_sp EQU 0x20050000 ; Top of RAM - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 - DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 - DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FMC_IRQHandler ; FMC - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD 0 ; Reserved - DCD HASH_RNG_IRQHandler ; Hash and Rng - DCD FPU_IRQHandler ; FPU - DCD UART7_IRQHandler ; UART7 - DCD UART8_IRQHandler ; UART8 - DCD SPI4_IRQHandler ; SPI4 - DCD SPI5_IRQHandler ; SPI5 - DCD SPI6_IRQHandler ; SPI6 - DCD SAI1_IRQHandler ; SAI1 - DCD LTDC_IRQHandler ; LTDC - DCD LTDC_ER_IRQHandler ; LTDC error - DCD DMA2D_IRQHandler ; DMA2D - DCD QUADSPI_IRQHandler ; QUADSPI - DCD DSI_IRQHandler ; DSI - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset handler -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT WWDG_IRQHandler [WEAK] - EXPORT PVD_IRQHandler [WEAK] - EXPORT TAMP_STAMP_IRQHandler [WEAK] - EXPORT RTC_WKUP_IRQHandler [WEAK] - EXPORT FLASH_IRQHandler [WEAK] - EXPORT RCC_IRQHandler [WEAK] - EXPORT EXTI0_IRQHandler [WEAK] - EXPORT EXTI1_IRQHandler [WEAK] - EXPORT EXTI2_IRQHandler [WEAK] - EXPORT EXTI3_IRQHandler [WEAK] - EXPORT EXTI4_IRQHandler [WEAK] - EXPORT DMA1_Stream0_IRQHandler [WEAK] - EXPORT DMA1_Stream1_IRQHandler [WEAK] - EXPORT DMA1_Stream2_IRQHandler [WEAK] - EXPORT DMA1_Stream3_IRQHandler [WEAK] - EXPORT DMA1_Stream4_IRQHandler [WEAK] - EXPORT DMA1_Stream5_IRQHandler [WEAK] - EXPORT DMA1_Stream6_IRQHandler [WEAK] - EXPORT ADC_IRQHandler [WEAK] - EXPORT CAN1_TX_IRQHandler [WEAK] - EXPORT CAN1_RX0_IRQHandler [WEAK] - EXPORT CAN1_RX1_IRQHandler [WEAK] - EXPORT CAN1_SCE_IRQHandler [WEAK] - EXPORT EXTI9_5_IRQHandler [WEAK] - EXPORT TIM1_BRK_TIM9_IRQHandler [WEAK] - EXPORT TIM1_UP_TIM10_IRQHandler [WEAK] - EXPORT TIM1_TRG_COM_TIM11_IRQHandler [WEAK] - EXPORT TIM1_CC_IRQHandler [WEAK] - EXPORT TIM2_IRQHandler [WEAK] - EXPORT TIM3_IRQHandler [WEAK] - EXPORT TIM4_IRQHandler [WEAK] - EXPORT I2C1_EV_IRQHandler [WEAK] - EXPORT I2C1_ER_IRQHandler [WEAK] - EXPORT I2C2_EV_IRQHandler [WEAK] - EXPORT I2C2_ER_IRQHandler [WEAK] - EXPORT SPI1_IRQHandler [WEAK] - EXPORT SPI2_IRQHandler [WEAK] - EXPORT USART1_IRQHandler [WEAK] - EXPORT USART2_IRQHandler [WEAK] - EXPORT USART3_IRQHandler [WEAK] - EXPORT EXTI15_10_IRQHandler [WEAK] - EXPORT RTC_Alarm_IRQHandler [WEAK] - EXPORT OTG_FS_WKUP_IRQHandler [WEAK] - EXPORT TIM8_BRK_TIM12_IRQHandler [WEAK] - EXPORT TIM8_UP_TIM13_IRQHandler [WEAK] - EXPORT TIM8_TRG_COM_TIM14_IRQHandler [WEAK] - EXPORT TIM8_CC_IRQHandler [WEAK] - EXPORT DMA1_Stream7_IRQHandler [WEAK] - EXPORT FMC_IRQHandler [WEAK] - EXPORT SDIO_IRQHandler [WEAK] - EXPORT TIM5_IRQHandler [WEAK] - EXPORT SPI3_IRQHandler [WEAK] - EXPORT UART4_IRQHandler [WEAK] - EXPORT UART5_IRQHandler [WEAK] - EXPORT TIM6_DAC_IRQHandler [WEAK] - EXPORT TIM7_IRQHandler [WEAK] - EXPORT DMA2_Stream0_IRQHandler [WEAK] - EXPORT DMA2_Stream1_IRQHandler [WEAK] - EXPORT DMA2_Stream2_IRQHandler [WEAK] - EXPORT DMA2_Stream3_IRQHandler [WEAK] - EXPORT DMA2_Stream4_IRQHandler [WEAK] - EXPORT ETH_IRQHandler [WEAK] - EXPORT ETH_WKUP_IRQHandler [WEAK] - EXPORT CAN2_TX_IRQHandler [WEAK] - EXPORT CAN2_RX0_IRQHandler [WEAK] - EXPORT CAN2_RX1_IRQHandler [WEAK] - EXPORT CAN2_SCE_IRQHandler [WEAK] - EXPORT OTG_FS_IRQHandler [WEAK] - EXPORT DMA2_Stream5_IRQHandler [WEAK] - EXPORT DMA2_Stream6_IRQHandler [WEAK] - EXPORT DMA2_Stream7_IRQHandler [WEAK] - EXPORT USART6_IRQHandler [WEAK] - EXPORT I2C3_EV_IRQHandler [WEAK] - EXPORT I2C3_ER_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_OUT_IRQHandler [WEAK] - EXPORT OTG_HS_EP1_IN_IRQHandler [WEAK] - EXPORT OTG_HS_WKUP_IRQHandler [WEAK] - EXPORT OTG_HS_IRQHandler [WEAK] - EXPORT DCMI_IRQHandler [WEAK] - EXPORT HASH_RNG_IRQHandler [WEAK] - EXPORT FPU_IRQHandler [WEAK] - EXPORT UART7_IRQHandler [WEAK] - EXPORT UART8_IRQHandler [WEAK] - EXPORT SPI4_IRQHandler [WEAK] - EXPORT SPI5_IRQHandler [WEAK] - EXPORT SPI6_IRQHandler [WEAK] - EXPORT SAI1_IRQHandler [WEAK] - EXPORT LTDC_IRQHandler [WEAK] - EXPORT LTDC_ER_IRQHandler [WEAK] - EXPORT DMA2D_IRQHandler [WEAK] - EXPORT QUADSPI_IRQHandler [WEAK] - EXPORT DSI_IRQHandler [WEAK] - -WWDG_IRQHandler -PVD_IRQHandler -TAMP_STAMP_IRQHandler -RTC_WKUP_IRQHandler -FLASH_IRQHandler -RCC_IRQHandler -EXTI0_IRQHandler -EXTI1_IRQHandler -EXTI2_IRQHandler -EXTI3_IRQHandler -EXTI4_IRQHandler -DMA1_Stream0_IRQHandler -DMA1_Stream1_IRQHandler -DMA1_Stream2_IRQHandler -DMA1_Stream3_IRQHandler -DMA1_Stream4_IRQHandler -DMA1_Stream5_IRQHandler -DMA1_Stream6_IRQHandler -ADC_IRQHandler -CAN1_TX_IRQHandler -CAN1_RX0_IRQHandler -CAN1_RX1_IRQHandler -CAN1_SCE_IRQHandler -EXTI9_5_IRQHandler -TIM1_BRK_TIM9_IRQHandler -TIM1_UP_TIM10_IRQHandler -TIM1_TRG_COM_TIM11_IRQHandler -TIM1_CC_IRQHandler -TIM2_IRQHandler -TIM3_IRQHandler -TIM4_IRQHandler -I2C1_EV_IRQHandler -I2C1_ER_IRQHandler -I2C2_EV_IRQHandler -I2C2_ER_IRQHandler -SPI1_IRQHandler -SPI2_IRQHandler -USART1_IRQHandler -USART2_IRQHandler -USART3_IRQHandler -EXTI15_10_IRQHandler -RTC_Alarm_IRQHandler -OTG_FS_WKUP_IRQHandler -TIM8_BRK_TIM12_IRQHandler -TIM8_UP_TIM13_IRQHandler -TIM8_TRG_COM_TIM14_IRQHandler -TIM8_CC_IRQHandler -DMA1_Stream7_IRQHandler -FMC_IRQHandler -SDIO_IRQHandler -TIM5_IRQHandler -SPI3_IRQHandler -UART4_IRQHandler -UART5_IRQHandler -TIM6_DAC_IRQHandler -TIM7_IRQHandler -DMA2_Stream0_IRQHandler -DMA2_Stream1_IRQHandler -DMA2_Stream2_IRQHandler -DMA2_Stream3_IRQHandler -DMA2_Stream4_IRQHandler -ETH_IRQHandler -ETH_WKUP_IRQHandler -CAN2_TX_IRQHandler -CAN2_RX0_IRQHandler -CAN2_RX1_IRQHandler -CAN2_SCE_IRQHandler -OTG_FS_IRQHandler -DMA2_Stream5_IRQHandler -DMA2_Stream6_IRQHandler -DMA2_Stream7_IRQHandler -USART6_IRQHandler -I2C3_EV_IRQHandler -I2C3_ER_IRQHandler -OTG_HS_EP1_OUT_IRQHandler -OTG_HS_EP1_IN_IRQHandler -OTG_HS_WKUP_IRQHandler -OTG_HS_IRQHandler -DCMI_IRQHandler -HASH_RNG_IRQHandler -FPU_IRQHandler -UART7_IRQHandler -UART8_IRQHandler -SPI4_IRQHandler -SPI5_IRQHandler -SPI6_IRQHandler -SAI1_IRQHandler -LTDC_IRQHandler -LTDC_ER_IRQHandler -DMA2D_IRQHandler -QUADSPI_IRQHandler -DSI_IRQHandler - B . - - ENDP - - ALIGN - END - -;************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE*****
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_GCC_ARM/startup_stm32f469xx.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,577 @@ +/** + ****************************************************************************** + * @file startup_stm32f469xx.s + * @author MCD Application Team + * @brief STM32F469xx Devices vector table for GCC based toolchains. + * This module performs: + * - Set the initial SP + * - Set the initial PC == Reset_Handler, + * - Set the vector table entries with the exceptions ISR address + * - Branches to main in the C library (which eventually + * calls main()). + * After Reset the Cortex-M4 processor is in Thread mode, + * priority is Privileged, and the Stack is set to Main. + ****************************************************************************** + * @attention + * + * <h2><center>© COPYRIGHT 2017 STMicroelectronics</center></h2> + * + * Redistribution and use in source and binary forms, with or without modification, + * are permitted provided that the following conditions are met: + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright notice, + * this list of conditions and the following disclaimer in the documentation + * and/or other materials provided with the distribution. + * 3. Neither the name of STMicroelectronics nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" + * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE + * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE + * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE + * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL + * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, + * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE + * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************** + */ + + .syntax unified + .cpu cortex-m4 + .fpu softvfp + .thumb + +.global g_pfnVectors +.global Default_Handler + +/* start address for the initialization values of the .data section. +defined in linker script */ +.word _sidata +/* start address for the .data section. defined in linker script */ +.word _sdata +/* end address for the .data section. defined in linker script */ +.word _edata +/* start address for the .bss section. defined in linker script */ +.word _sbss +/* end address for the .bss section. defined in linker script */ +.word _ebss +/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ + +/** + * @brief This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + * @param None + * @retval : None +*/ + + .section .text.Reset_Handler + .weak Reset_Handler + .type Reset_Handler, %function +Reset_Handler: + ldr sp, =_estack /* set stack pointer */ + +/* Copy the data segment initializers from flash to SRAM */ + movs r1, #0 + b LoopCopyDataInit + +CopyDataInit: + ldr r3, =_sidata + ldr r3, [r3, r1] + str r3, [r0, r1] + adds r1, r1, #4 + +LoopCopyDataInit: + ldr r0, =_sdata + ldr r3, =_edata + adds r2, r0, r1 + cmp r2, r3 + bcc CopyDataInit + ldr r2, =_sbss + b LoopFillZerobss +/* Zero fill the bss segment. */ +FillZerobss: + movs r3, #0 + str r3, [r2], #4 + +LoopFillZerobss: + ldr r3, = _ebss + cmp r2, r3 + bcc FillZerobss + +/* Call the clock system intitialization function.*/ + bl SystemInit +/* Call static constructors */ + //bl __libc_init_array +/* Call the application's entry point.*/ + //bl main + // Calling the crt0 'cold-start' entry point. There __libc_init_array is called + // and when existing hardware_init_hook() and software_init_hook() before + // starting main(). software_init_hook() is available and has to be called due + // to initializsation when using rtos. + bl _start + bx lr +.size Reset_Handler, .-Reset_Handler + +/** + * @brief This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + * @param None + * @retval None +*/ + .section .text.Default_Handler,"ax",%progbits +Default_Handler: +Infinite_Loop: + b Infinite_Loop + .size Default_Handler, .-Default_Handler +/****************************************************************************** +* +* The minimal vector table for a Cortex M3. Note that the proper constructs +* must be placed on this to ensure that it ends up at physical address +* 0x0000.0000. +* +*******************************************************************************/ + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + + g_pfnVectors: + .word _estack + .word Reset_Handler + + .word NMI_Handler + .word HardFault_Handler + .word MemManage_Handler + .word BusFault_Handler + .word UsageFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word DebugMon_Handler + .word 0 + .word PendSV_Handler + .word SysTick_Handler + + /* External Interrupts */ + .word WWDG_IRQHandler /* Window WatchDog */ + .word PVD_IRQHandler /* PVD through EXTI Line detection */ + .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ + .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ + .word FLASH_IRQHandler /* FLASH */ + .word RCC_IRQHandler /* RCC */ + .word EXTI0_IRQHandler /* EXTI Line0 */ + .word EXTI1_IRQHandler /* EXTI Line1 */ + .word EXTI2_IRQHandler /* EXTI Line2 */ + .word EXTI3_IRQHandler /* EXTI Line3 */ + .word EXTI4_IRQHandler /* EXTI Line4 */ + .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ + .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ + .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ + .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ + .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ + .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ + .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ + .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ + .word CAN1_TX_IRQHandler /* CAN1 TX */ + .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ + .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ + .word CAN1_SCE_IRQHandler /* CAN1 SCE */ + .word EXTI9_5_IRQHandler /* External Line[9:5]s */ + .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ + .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ + .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ + .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ + .word TIM2_IRQHandler /* TIM2 */ + .word TIM3_IRQHandler /* TIM3 */ + .word TIM4_IRQHandler /* TIM4 */ + .word I2C1_EV_IRQHandler /* I2C1 Event */ + .word I2C1_ER_IRQHandler /* I2C1 Error */ + .word I2C2_EV_IRQHandler /* I2C2 Event */ + .word I2C2_ER_IRQHandler /* I2C2 Error */ + .word SPI1_IRQHandler /* SPI1 */ + .word SPI2_IRQHandler /* SPI2 */ + .word USART1_IRQHandler /* USART1 */ + .word USART2_IRQHandler /* USART2 */ + .word USART3_IRQHandler /* USART3 */ + .word EXTI15_10_IRQHandler /* External Line[15:10]s */ + .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ + .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ + .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ + .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ + .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ + .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ + .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ + .word FMC_IRQHandler /* FMC */ + .word SDIO_IRQHandler /* SDIO */ + .word TIM5_IRQHandler /* TIM5 */ + .word SPI3_IRQHandler /* SPI3 */ + .word UART4_IRQHandler /* UART4 */ + .word UART5_IRQHandler /* UART5 */ + .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ + .word TIM7_IRQHandler /* TIM7 */ + .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ + .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ + .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ + .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ + .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ + .word ETH_IRQHandler /* Ethernet */ + .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ + .word CAN2_TX_IRQHandler /* CAN2 TX */ + .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ + .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ + .word CAN2_SCE_IRQHandler /* CAN2 SCE */ + .word OTG_FS_IRQHandler /* USB OTG FS */ + .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ + .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ + .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ + .word USART6_IRQHandler /* USART6 */ + .word I2C3_EV_IRQHandler /* I2C3 event */ + .word I2C3_ER_IRQHandler /* I2C3 error */ + .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ + .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ + .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ + .word OTG_HS_IRQHandler /* USB OTG HS */ + .word DCMI_IRQHandler /* DCMI */ + .word 0 /* Reserved */ + .word HASH_RNG_IRQHandler /* Hash and Rng */ + .word FPU_IRQHandler /* FPU */ + .word UART7_IRQHandler /* UART7 */ + .word UART8_IRQHandler /* UART8 */ + .word SPI4_IRQHandler /* SPI4 */ + .word SPI5_IRQHandler /* SPI5 */ + .word SPI6_IRQHandler /* SPI6 */ + .word SAI1_IRQHandler /* SAI1 */ + .word LTDC_IRQHandler /* LTDC */ + .word LTDC_ER_IRQHandler /* LTDC error */ + .word DMA2D_IRQHandler /* DMA2D */ + .word QUADSPI_IRQHandler /* QUADSPI */ + .word DSI_IRQHandler /* DSI */ + + +/******************************************************************************* +* +* Provide weak aliases for each Exception handler to the Default_Handler. +* As they are weak aliases, any function with the same name will override +* this definition. +* +*******************************************************************************/ + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak MemManage_Handler + .thumb_set MemManage_Handler,Default_Handler + + .weak BusFault_Handler + .thumb_set BusFault_Handler,Default_Handler + + .weak UsageFault_Handler + .thumb_set UsageFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak DebugMon_Handler + .thumb_set DebugMon_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak WWDG_IRQHandler + .thumb_set WWDG_IRQHandler,Default_Handler + + .weak PVD_IRQHandler + .thumb_set PVD_IRQHandler,Default_Handler + + .weak TAMP_STAMP_IRQHandler + .thumb_set TAMP_STAMP_IRQHandler,Default_Handler + + .weak RTC_WKUP_IRQHandler + .thumb_set RTC_WKUP_IRQHandler,Default_Handler + + .weak FLASH_IRQHandler + .thumb_set FLASH_IRQHandler,Default_Handler + + .weak RCC_IRQHandler + .thumb_set RCC_IRQHandler,Default_Handler + + .weak EXTI0_IRQHandler + .thumb_set EXTI0_IRQHandler,Default_Handler + + .weak EXTI1_IRQHandler + .thumb_set EXTI1_IRQHandler,Default_Handler + + .weak EXTI2_IRQHandler + .thumb_set EXTI2_IRQHandler,Default_Handler + + .weak EXTI3_IRQHandler + .thumb_set EXTI3_IRQHandler,Default_Handler + + .weak EXTI4_IRQHandler + .thumb_set EXTI4_IRQHandler,Default_Handler + + .weak DMA1_Stream0_IRQHandler + .thumb_set DMA1_Stream0_IRQHandler,Default_Handler + + .weak DMA1_Stream1_IRQHandler + .thumb_set DMA1_Stream1_IRQHandler,Default_Handler + + .weak DMA1_Stream2_IRQHandler + .thumb_set DMA1_Stream2_IRQHandler,Default_Handler + + .weak DMA1_Stream3_IRQHandler + .thumb_set DMA1_Stream3_IRQHandler,Default_Handler + + .weak DMA1_Stream4_IRQHandler + .thumb_set DMA1_Stream4_IRQHandler,Default_Handler + + .weak DMA1_Stream5_IRQHandler + .thumb_set DMA1_Stream5_IRQHandler,Default_Handler + + .weak DMA1_Stream6_IRQHandler + .thumb_set DMA1_Stream6_IRQHandler,Default_Handler + + .weak ADC_IRQHandler + .thumb_set ADC_IRQHandler,Default_Handler + + .weak CAN1_TX_IRQHandler + .thumb_set CAN1_TX_IRQHandler,Default_Handler + + .weak CAN1_RX0_IRQHandler + .thumb_set CAN1_RX0_IRQHandler,Default_Handler + + .weak CAN1_RX1_IRQHandler + .thumb_set CAN1_RX1_IRQHandler,Default_Handler + + .weak CAN1_SCE_IRQHandler + .thumb_set CAN1_SCE_IRQHandler,Default_Handler + + .weak EXTI9_5_IRQHandler + .thumb_set EXTI9_5_IRQHandler,Default_Handler + + .weak TIM1_BRK_TIM9_IRQHandler + .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler + + .weak TIM1_UP_TIM10_IRQHandler + .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler + + .weak TIM1_TRG_COM_TIM11_IRQHandler + .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler + + .weak TIM1_CC_IRQHandler + .thumb_set TIM1_CC_IRQHandler,Default_Handler + + .weak TIM2_IRQHandler + .thumb_set TIM2_IRQHandler,Default_Handler + + .weak TIM3_IRQHandler + .thumb_set TIM3_IRQHandler,Default_Handler + + .weak TIM4_IRQHandler + .thumb_set TIM4_IRQHandler,Default_Handler + + .weak I2C1_EV_IRQHandler + .thumb_set I2C1_EV_IRQHandler,Default_Handler + + .weak I2C1_ER_IRQHandler + .thumb_set I2C1_ER_IRQHandler,Default_Handler + + .weak I2C2_EV_IRQHandler + .thumb_set I2C2_EV_IRQHandler,Default_Handler + + .weak I2C2_ER_IRQHandler + .thumb_set I2C2_ER_IRQHandler,Default_Handler + + .weak SPI1_IRQHandler + .thumb_set SPI1_IRQHandler,Default_Handler + + .weak SPI2_IRQHandler + .thumb_set SPI2_IRQHandler,Default_Handler + + .weak USART1_IRQHandler + .thumb_set USART1_IRQHandler,Default_Handler + + .weak USART2_IRQHandler + .thumb_set USART2_IRQHandler,Default_Handler + + .weak USART3_IRQHandler + .thumb_set USART3_IRQHandler,Default_Handler + + .weak EXTI15_10_IRQHandler + .thumb_set EXTI15_10_IRQHandler,Default_Handler + + .weak RTC_Alarm_IRQHandler + .thumb_set RTC_Alarm_IRQHandler,Default_Handler + + .weak OTG_FS_WKUP_IRQHandler + .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler + + .weak TIM8_BRK_TIM12_IRQHandler + .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler + + .weak TIM8_UP_TIM13_IRQHandler + .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler + + .weak TIM8_TRG_COM_TIM14_IRQHandler + .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler + + .weak TIM8_CC_IRQHandler + .thumb_set TIM8_CC_IRQHandler,Default_Handler + + .weak DMA1_Stream7_IRQHandler + .thumb_set DMA1_Stream7_IRQHandler,Default_Handler + + .weak FMC_IRQHandler + .thumb_set FMC_IRQHandler,Default_Handler + + .weak SDIO_IRQHandler + .thumb_set SDIO_IRQHandler,Default_Handler + + .weak TIM5_IRQHandler + .thumb_set TIM5_IRQHandler,Default_Handler + + .weak SPI3_IRQHandler + .thumb_set SPI3_IRQHandler,Default_Handler + + .weak UART4_IRQHandler + .thumb_set UART4_IRQHandler,Default_Handler + + .weak UART5_IRQHandler + .thumb_set UART5_IRQHandler,Default_Handler + + .weak TIM6_DAC_IRQHandler + .thumb_set TIM6_DAC_IRQHandler,Default_Handler + + .weak TIM7_IRQHandler + .thumb_set TIM7_IRQHandler,Default_Handler + + .weak DMA2_Stream0_IRQHandler + .thumb_set DMA2_Stream0_IRQHandler,Default_Handler + + .weak DMA2_Stream1_IRQHandler + .thumb_set DMA2_Stream1_IRQHandler,Default_Handler + + .weak DMA2_Stream2_IRQHandler + .thumb_set DMA2_Stream2_IRQHandler,Default_Handler + + .weak DMA2_Stream3_IRQHandler + .thumb_set DMA2_Stream3_IRQHandler,Default_Handler + + .weak DMA2_Stream4_IRQHandler + .thumb_set DMA2_Stream4_IRQHandler,Default_Handler + + .weak ETH_IRQHandler + .thumb_set ETH_IRQHandler,Default_Handler + + .weak ETH_WKUP_IRQHandler + .thumb_set ETH_WKUP_IRQHandler,Default_Handler + + .weak CAN2_TX_IRQHandler + .thumb_set CAN2_TX_IRQHandler,Default_Handler + + .weak CAN2_RX0_IRQHandler + .thumb_set CAN2_RX0_IRQHandler,Default_Handler + + .weak CAN2_RX1_IRQHandler + .thumb_set CAN2_RX1_IRQHandler,Default_Handler + + .weak CAN2_SCE_IRQHandler + .thumb_set CAN2_SCE_IRQHandler,Default_Handler + + .weak OTG_FS_IRQHandler + .thumb_set OTG_FS_IRQHandler,Default_Handler + + .weak DMA2_Stream5_IRQHandler + .thumb_set DMA2_Stream5_IRQHandler,Default_Handler + + .weak DMA2_Stream6_IRQHandler + .thumb_set DMA2_Stream6_IRQHandler,Default_Handler + + .weak DMA2_Stream7_IRQHandler + .thumb_set DMA2_Stream7_IRQHandler,Default_Handler + + .weak USART6_IRQHandler + .thumb_set USART6_IRQHandler,Default_Handler + + .weak I2C3_EV_IRQHandler + .thumb_set I2C3_EV_IRQHandler,Default_Handler + + .weak I2C3_ER_IRQHandler + .thumb_set I2C3_ER_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_OUT_IRQHandler + .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler + + .weak OTG_HS_EP1_IN_IRQHandler + .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler + + .weak OTG_HS_WKUP_IRQHandler + .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler + + .weak OTG_HS_IRQHandler + .thumb_set OTG_HS_IRQHandler,Default_Handler + + .weak DCMI_IRQHandler + .thumb_set DCMI_IRQHandler,Default_Handler + + .weak HASH_RNG_IRQHandler + .thumb_set HASH_RNG_IRQHandler,Default_Handler + + .weak FPU_IRQHandler + .thumb_set FPU_IRQHandler,Default_Handler + + .weak UART7_IRQHandler + .thumb_set UART7_IRQHandler,Default_Handler + + .weak UART8_IRQHandler + .thumb_set UART8_IRQHandler,Default_Handler + + .weak SPI4_IRQHandler + .thumb_set SPI4_IRQHandler,Default_Handler + + .weak SPI5_IRQHandler + .thumb_set SPI5_IRQHandler,Default_Handler + + .weak SPI6_IRQHandler + .thumb_set SPI6_IRQHandler,Default_Handler + + .weak SAI1_IRQHandler + .thumb_set SAI1_IRQHandler,Default_Handler + + .weak LTDC_IRQHandler + .thumb_set LTDC_IRQHandler,Default_Handler + + .weak LTDC_ER_IRQHandler + .thumb_set LTDC_ER_IRQHandler,Default_Handler + + .weak DMA2D_IRQHandler + .thumb_set DMA2D_IRQHandler,Default_Handler + + .weak QUADSPI_IRQHandler + .thumb_set QUADSPI_IRQHandler,Default_Handler + + .weak DSI_IRQHandler + .thumb_set DSI_IRQHandler,Default_Handler + +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ + + + + + + +
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_GCC_ARM/startup_stm32f469xx.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,564 +0,0 @@ -/** - ****************************************************************************** - * @file startup_stm32f469xx.s - * @author MCD Application Team - * @version V2.4.1 - * @date 09-October-2015 - * @brief STM32F469xx Devices vector table for GCC based toolchains. - * This module performs: - * - Set the initial SP - * - Set the initial PC == Reset_Handler, - * - Set the vector table entries with the exceptions ISR address - * - Branches to main in the C library (which eventually - * calls main()). - * After Reset the Cortex-M4 processor is in Thread mode, - * priority is Privileged, and the Stack is set to Main. - ****************************************************************************** - * @attention - * - * <h2><center>© COPYRIGHT 2015 STMicroelectronics</center></h2> - * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: - * 1. Redistributions of source code must retain the above copyright notice, - * this list of conditions and the following disclaimer. - * 2. Redistributions in binary form must reproduce the above copyright notice, - * this list of conditions and the following disclaimer in the documentation - * and/or other materials provided with the distribution. - * 3. Neither the name of STMicroelectronics nor the names of its contributors - * may be used to endorse or promote products derived from this software - * without specific prior written permission. - * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" - * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE - * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE - * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL - * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR - * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER - * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, - * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE - * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - * - ****************************************************************************** - */ - - .syntax unified - .cpu cortex-m4 - .fpu softvfp - .thumb - -.global g_pfnVectors -.global Default_Handler - -/* start address for the initialization values of the .data section. -defined in linker script */ -.word _sidata -/* start address for the .data section. defined in linker script */ -.word _sdata -/* end address for the .data section. defined in linker script */ -.word _edata -/* stack used for SystemInit_ExtMemCtl; always internal RAM used */ - -/** - * @brief This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - * @param None - * @retval : None -*/ - - .section .text.Reset_Handler - .weak Reset_Handler - .type Reset_Handler, %function -Reset_Handler: - ldr sp, =_estack /* set stack pointer */ - -/* Copy the data segment initializers from flash to SRAM */ - movs r1, #0 - b LoopCopyDataInit - -CopyDataInit: - ldr r3, =_sidata - ldr r3, [r3, r1] - str r3, [r0, r1] - adds r1, r1, #4 - -LoopCopyDataInit: - ldr r0, =_sdata - ldr r3, =_edata - adds r2, r0, r1 - cmp r2, r3 - bcc CopyDataInit - -/* Call the clock system intitialization function.*/ - bl SystemInit -/* Call static constructors */ - //bl __libc_init_array -/* Call the application's entry point.*/ - //bl main - // Calling the crt0 'cold-start' entry point. There __libc_init_array is called - // and when existing hardware_init_hook() and software_init_hook() before - // starting main(). software_init_hook() is available and has to be called due - // to initializsation when using rtos. - bl _start - bx lr -.size Reset_Handler, .-Reset_Handler - -/** - * @brief This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - * @param None - * @retval None -*/ - .section .text.Default_Handler,"ax",%progbits -Default_Handler: -Infinite_Loop: - b Infinite_Loop - .size Default_Handler, .-Default_Handler -/****************************************************************************** -* -* The minimal vector table for a Cortex M3. Note that the proper constructs -* must be placed on this to ensure that it ends up at physical address -* 0x0000.0000. -* -*******************************************************************************/ - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - - g_pfnVectors: - .word _estack - .word Reset_Handler - - .word NMI_Handler - .word HardFault_Handler - .word MemManage_Handler - .word BusFault_Handler - .word UsageFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word DebugMon_Handler - .word 0 - .word PendSV_Handler - .word SysTick_Handler - - /* External Interrupts */ - .word WWDG_IRQHandler /* Window WatchDog */ - .word PVD_IRQHandler /* PVD through EXTI Line detection */ - .word TAMP_STAMP_IRQHandler /* Tamper and TimeStamps through the EXTI line */ - .word RTC_WKUP_IRQHandler /* RTC Wakeup through the EXTI line */ - .word FLASH_IRQHandler /* FLASH */ - .word RCC_IRQHandler /* RCC */ - .word EXTI0_IRQHandler /* EXTI Line0 */ - .word EXTI1_IRQHandler /* EXTI Line1 */ - .word EXTI2_IRQHandler /* EXTI Line2 */ - .word EXTI3_IRQHandler /* EXTI Line3 */ - .word EXTI4_IRQHandler /* EXTI Line4 */ - .word DMA1_Stream0_IRQHandler /* DMA1 Stream 0 */ - .word DMA1_Stream1_IRQHandler /* DMA1 Stream 1 */ - .word DMA1_Stream2_IRQHandler /* DMA1 Stream 2 */ - .word DMA1_Stream3_IRQHandler /* DMA1 Stream 3 */ - .word DMA1_Stream4_IRQHandler /* DMA1 Stream 4 */ - .word DMA1_Stream5_IRQHandler /* DMA1 Stream 5 */ - .word DMA1_Stream6_IRQHandler /* DMA1 Stream 6 */ - .word ADC_IRQHandler /* ADC1, ADC2 and ADC3s */ - .word CAN1_TX_IRQHandler /* CAN1 TX */ - .word CAN1_RX0_IRQHandler /* CAN1 RX0 */ - .word CAN1_RX1_IRQHandler /* CAN1 RX1 */ - .word CAN1_SCE_IRQHandler /* CAN1 SCE */ - .word EXTI9_5_IRQHandler /* External Line[9:5]s */ - .word TIM1_BRK_TIM9_IRQHandler /* TIM1 Break and TIM9 */ - .word TIM1_UP_TIM10_IRQHandler /* TIM1 Update and TIM10 */ - .word TIM1_TRG_COM_TIM11_IRQHandler /* TIM1 Trigger and Commutation and TIM11 */ - .word TIM1_CC_IRQHandler /* TIM1 Capture Compare */ - .word TIM2_IRQHandler /* TIM2 */ - .word TIM3_IRQHandler /* TIM3 */ - .word TIM4_IRQHandler /* TIM4 */ - .word I2C1_EV_IRQHandler /* I2C1 Event */ - .word I2C1_ER_IRQHandler /* I2C1 Error */ - .word I2C2_EV_IRQHandler /* I2C2 Event */ - .word I2C2_ER_IRQHandler /* I2C2 Error */ - .word SPI1_IRQHandler /* SPI1 */ - .word SPI2_IRQHandler /* SPI2 */ - .word USART1_IRQHandler /* USART1 */ - .word USART2_IRQHandler /* USART2 */ - .word USART3_IRQHandler /* USART3 */ - .word EXTI15_10_IRQHandler /* External Line[15:10]s */ - .word RTC_Alarm_IRQHandler /* RTC Alarm (A and B) through EXTI Line */ - .word OTG_FS_WKUP_IRQHandler /* USB OTG FS Wakeup through EXTI line */ - .word TIM8_BRK_TIM12_IRQHandler /* TIM8 Break and TIM12 */ - .word TIM8_UP_TIM13_IRQHandler /* TIM8 Update and TIM13 */ - .word TIM8_TRG_COM_TIM14_IRQHandler /* TIM8 Trigger and Commutation and TIM14 */ - .word TIM8_CC_IRQHandler /* TIM8 Capture Compare */ - .word DMA1_Stream7_IRQHandler /* DMA1 Stream7 */ - .word FMC_IRQHandler /* FMC */ - .word SDIO_IRQHandler /* SDIO */ - .word TIM5_IRQHandler /* TIM5 */ - .word SPI3_IRQHandler /* SPI3 */ - .word UART4_IRQHandler /* UART4 */ - .word UART5_IRQHandler /* UART5 */ - .word TIM6_DAC_IRQHandler /* TIM6 and DAC1&2 underrun errors */ - .word TIM7_IRQHandler /* TIM7 */ - .word DMA2_Stream0_IRQHandler /* DMA2 Stream 0 */ - .word DMA2_Stream1_IRQHandler /* DMA2 Stream 1 */ - .word DMA2_Stream2_IRQHandler /* DMA2 Stream 2 */ - .word DMA2_Stream3_IRQHandler /* DMA2 Stream 3 */ - .word DMA2_Stream4_IRQHandler /* DMA2 Stream 4 */ - .word ETH_IRQHandler /* Ethernet */ - .word ETH_WKUP_IRQHandler /* Ethernet Wakeup through EXTI line */ - .word CAN2_TX_IRQHandler /* CAN2 TX */ - .word CAN2_RX0_IRQHandler /* CAN2 RX0 */ - .word CAN2_RX1_IRQHandler /* CAN2 RX1 */ - .word CAN2_SCE_IRQHandler /* CAN2 SCE */ - .word OTG_FS_IRQHandler /* USB OTG FS */ - .word DMA2_Stream5_IRQHandler /* DMA2 Stream 5 */ - .word DMA2_Stream6_IRQHandler /* DMA2 Stream 6 */ - .word DMA2_Stream7_IRQHandler /* DMA2 Stream 7 */ - .word USART6_IRQHandler /* USART6 */ - .word I2C3_EV_IRQHandler /* I2C3 event */ - .word I2C3_ER_IRQHandler /* I2C3 error */ - .word OTG_HS_EP1_OUT_IRQHandler /* USB OTG HS End Point 1 Out */ - .word OTG_HS_EP1_IN_IRQHandler /* USB OTG HS End Point 1 In */ - .word OTG_HS_WKUP_IRQHandler /* USB OTG HS Wakeup through EXTI */ - .word OTG_HS_IRQHandler /* USB OTG HS */ - .word DCMI_IRQHandler /* DCMI */ - .word 0 /* Reserved */ - .word HASH_RNG_IRQHandler /* Hash and Rng */ - .word FPU_IRQHandler /* FPU */ - .word UART7_IRQHandler /* UART7 */ - .word UART8_IRQHandler /* UART8 */ - .word SPI4_IRQHandler /* SPI4 */ - .word SPI5_IRQHandler /* SPI5 */ - .word SPI6_IRQHandler /* SPI6 */ - .word SAI1_IRQHandler /* SAI1 */ - .word LTDC_IRQHandler /* LTDC */ - .word LTDC_ER_IRQHandler /* LTDC error */ - .word DMA2D_IRQHandler /* DMA2D */ - .word QUADSPI_IRQHandler /* QUADSPI */ - .word DSI_IRQHandler /* DSI */ - - -/******************************************************************************* -* -* Provide weak aliases for each Exception handler to the Default_Handler. -* As they are weak aliases, any function with the same name will override -* this definition. -* -*******************************************************************************/ - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak MemManage_Handler - .thumb_set MemManage_Handler,Default_Handler - - .weak BusFault_Handler - .thumb_set BusFault_Handler,Default_Handler - - .weak UsageFault_Handler - .thumb_set UsageFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak DebugMon_Handler - .thumb_set DebugMon_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak WWDG_IRQHandler - .thumb_set WWDG_IRQHandler,Default_Handler - - .weak PVD_IRQHandler - .thumb_set PVD_IRQHandler,Default_Handler - - .weak TAMP_STAMP_IRQHandler - .thumb_set TAMP_STAMP_IRQHandler,Default_Handler - - .weak RTC_WKUP_IRQHandler - .thumb_set RTC_WKUP_IRQHandler,Default_Handler - - .weak FLASH_IRQHandler - .thumb_set FLASH_IRQHandler,Default_Handler - - .weak RCC_IRQHandler - .thumb_set RCC_IRQHandler,Default_Handler - - .weak EXTI0_IRQHandler - .thumb_set EXTI0_IRQHandler,Default_Handler - - .weak EXTI1_IRQHandler - .thumb_set EXTI1_IRQHandler,Default_Handler - - .weak EXTI2_IRQHandler - .thumb_set EXTI2_IRQHandler,Default_Handler - - .weak EXTI3_IRQHandler - .thumb_set EXTI3_IRQHandler,Default_Handler - - .weak EXTI4_IRQHandler - .thumb_set EXTI4_IRQHandler,Default_Handler - - .weak DMA1_Stream0_IRQHandler - .thumb_set DMA1_Stream0_IRQHandler,Default_Handler - - .weak DMA1_Stream1_IRQHandler - .thumb_set DMA1_Stream1_IRQHandler,Default_Handler - - .weak DMA1_Stream2_IRQHandler - .thumb_set DMA1_Stream2_IRQHandler,Default_Handler - - .weak DMA1_Stream3_IRQHandler - .thumb_set DMA1_Stream3_IRQHandler,Default_Handler - - .weak DMA1_Stream4_IRQHandler - .thumb_set DMA1_Stream4_IRQHandler,Default_Handler - - .weak DMA1_Stream5_IRQHandler - .thumb_set DMA1_Stream5_IRQHandler,Default_Handler - - .weak DMA1_Stream6_IRQHandler - .thumb_set DMA1_Stream6_IRQHandler,Default_Handler - - .weak ADC_IRQHandler - .thumb_set ADC_IRQHandler,Default_Handler - - .weak CAN1_TX_IRQHandler - .thumb_set CAN1_TX_IRQHandler,Default_Handler - - .weak CAN1_RX0_IRQHandler - .thumb_set CAN1_RX0_IRQHandler,Default_Handler - - .weak CAN1_RX1_IRQHandler - .thumb_set CAN1_RX1_IRQHandler,Default_Handler - - .weak CAN1_SCE_IRQHandler - .thumb_set CAN1_SCE_IRQHandler,Default_Handler - - .weak EXTI9_5_IRQHandler - .thumb_set EXTI9_5_IRQHandler,Default_Handler - - .weak TIM1_BRK_TIM9_IRQHandler - .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler - - .weak TIM1_UP_TIM10_IRQHandler - .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler - - .weak TIM1_TRG_COM_TIM11_IRQHandler - .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler - - .weak TIM1_CC_IRQHandler - .thumb_set TIM1_CC_IRQHandler,Default_Handler - - .weak TIM2_IRQHandler - .thumb_set TIM2_IRQHandler,Default_Handler - - .weak TIM3_IRQHandler - .thumb_set TIM3_IRQHandler,Default_Handler - - .weak TIM4_IRQHandler - .thumb_set TIM4_IRQHandler,Default_Handler - - .weak I2C1_EV_IRQHandler - .thumb_set I2C1_EV_IRQHandler,Default_Handler - - .weak I2C1_ER_IRQHandler - .thumb_set I2C1_ER_IRQHandler,Default_Handler - - .weak I2C2_EV_IRQHandler - .thumb_set I2C2_EV_IRQHandler,Default_Handler - - .weak I2C2_ER_IRQHandler - .thumb_set I2C2_ER_IRQHandler,Default_Handler - - .weak SPI1_IRQHandler - .thumb_set SPI1_IRQHandler,Default_Handler - - .weak SPI2_IRQHandler - .thumb_set SPI2_IRQHandler,Default_Handler - - .weak USART1_IRQHandler - .thumb_set USART1_IRQHandler,Default_Handler - - .weak USART2_IRQHandler - .thumb_set USART2_IRQHandler,Default_Handler - - .weak USART3_IRQHandler - .thumb_set USART3_IRQHandler,Default_Handler - - .weak EXTI15_10_IRQHandler - .thumb_set EXTI15_10_IRQHandler,Default_Handler - - .weak RTC_Alarm_IRQHandler - .thumb_set RTC_Alarm_IRQHandler,Default_Handler - - .weak OTG_FS_WKUP_IRQHandler - .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler - - .weak TIM8_BRK_TIM12_IRQHandler - .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler - - .weak TIM8_UP_TIM13_IRQHandler - .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler - - .weak TIM8_TRG_COM_TIM14_IRQHandler - .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler - - .weak TIM8_CC_IRQHandler - .thumb_set TIM8_CC_IRQHandler,Default_Handler - - .weak DMA1_Stream7_IRQHandler - .thumb_set DMA1_Stream7_IRQHandler,Default_Handler - - .weak FMC_IRQHandler - .thumb_set FMC_IRQHandler,Default_Handler - - .weak SDIO_IRQHandler - .thumb_set SDIO_IRQHandler,Default_Handler - - .weak TIM5_IRQHandler - .thumb_set TIM5_IRQHandler,Default_Handler - - .weak SPI3_IRQHandler - .thumb_set SPI3_IRQHandler,Default_Handler - - .weak UART4_IRQHandler - .thumb_set UART4_IRQHandler,Default_Handler - - .weak UART5_IRQHandler - .thumb_set UART5_IRQHandler,Default_Handler - - .weak TIM6_DAC_IRQHandler - .thumb_set TIM6_DAC_IRQHandler,Default_Handler - - .weak TIM7_IRQHandler - .thumb_set TIM7_IRQHandler,Default_Handler - - .weak DMA2_Stream0_IRQHandler - .thumb_set DMA2_Stream0_IRQHandler,Default_Handler - - .weak DMA2_Stream1_IRQHandler - .thumb_set DMA2_Stream1_IRQHandler,Default_Handler - - .weak DMA2_Stream2_IRQHandler - .thumb_set DMA2_Stream2_IRQHandler,Default_Handler - - .weak DMA2_Stream3_IRQHandler - .thumb_set DMA2_Stream3_IRQHandler,Default_Handler - - .weak DMA2_Stream4_IRQHandler - .thumb_set DMA2_Stream4_IRQHandler,Default_Handler - - .weak ETH_IRQHandler - .thumb_set ETH_IRQHandler,Default_Handler - - .weak ETH_WKUP_IRQHandler - .thumb_set ETH_WKUP_IRQHandler,Default_Handler - - .weak CAN2_TX_IRQHandler - .thumb_set CAN2_TX_IRQHandler,Default_Handler - - .weak CAN2_RX0_IRQHandler - .thumb_set CAN2_RX0_IRQHandler,Default_Handler - - .weak CAN2_RX1_IRQHandler - .thumb_set CAN2_RX1_IRQHandler,Default_Handler - - .weak CAN2_SCE_IRQHandler - .thumb_set CAN2_SCE_IRQHandler,Default_Handler - - .weak OTG_FS_IRQHandler - .thumb_set OTG_FS_IRQHandler,Default_Handler - - .weak DMA2_Stream5_IRQHandler - .thumb_set DMA2_Stream5_IRQHandler,Default_Handler - - .weak DMA2_Stream6_IRQHandler - .thumb_set DMA2_Stream6_IRQHandler,Default_Handler - - .weak DMA2_Stream7_IRQHandler - .thumb_set DMA2_Stream7_IRQHandler,Default_Handler - - .weak USART6_IRQHandler - .thumb_set USART6_IRQHandler,Default_Handler - - .weak I2C3_EV_IRQHandler - .thumb_set I2C3_EV_IRQHandler,Default_Handler - - .weak I2C3_ER_IRQHandler - .thumb_set I2C3_ER_IRQHandler,Default_Handler - - .weak OTG_HS_EP1_OUT_IRQHandler - .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler - - .weak OTG_HS_EP1_IN_IRQHandler - .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler - - .weak OTG_HS_WKUP_IRQHandler - .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler - - .weak OTG_HS_IRQHandler - .thumb_set OTG_HS_IRQHandler,Default_Handler - - .weak DCMI_IRQHandler - .thumb_set DCMI_IRQHandler,Default_Handler - - .weak HASH_RNG_IRQHandler - .thumb_set HASH_RNG_IRQHandler,Default_Handler - - .weak FPU_IRQHandler - .thumb_set FPU_IRQHandler,Default_Handler - - .weak UART7_IRQHandler - .thumb_set UART7_IRQHandler,Default_Handler - - .weak UART8_IRQHandler - .thumb_set UART8_IRQHandler,Default_Handler - - .weak SPI4_IRQHandler - .thumb_set SPI4_IRQHandler,Default_Handler - - .weak SPI5_IRQHandler - .thumb_set SPI5_IRQHandler,Default_Handler - - .weak SPI6_IRQHandler - .thumb_set SPI6_IRQHandler,Default_Handler - - .weak SAI1_IRQHandler - .thumb_set SAI1_IRQHandler,Default_Handler - - .weak LTDC_IRQHandler - .thumb_set LTDC_IRQHandler,Default_Handler - - .weak LTDC_ER_IRQHandler - .thumb_set LTDC_ER_IRQHandler,Default_Handler - - .weak DMA2D_IRQHandler - .thumb_set DMA2D_IRQHandler,Default_Handler - - .weak QUADSPI_IRQHandler - .thumb_set QUADSPI_IRQHandler,Default_Handler - - .weak DSI_IRQHandler - .thumb_set DSI_IRQHandler,Default_Handler - -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/ - - - - - - -
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_IAR/startup_stm32f469xx.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,702 @@ +;/******************** (C) COPYRIGHT 2017 STMicroelectronics ******************** +;* File Name : startup_stm32f469xx.s +;* Author : MCD Application Team +;* Description : STM32F469xx devices vector table for EWARM toolchain. +;* This module performs: +;* - Set the initial SP +;* - Set the initial PC == _iar_program_start, +;* - Set the vector table entries with the exceptions ISR +;* address. +;* - Branches to main in the C library (which eventually +;* calls main()). +;* After Reset the Cortex-M4 processor is in Thread mode, +;* priority is Privileged, and the Stack is set to Main. +;******************************************************************************** +;* +;* Redistribution and use in source and binary forms, with or without modification, +;* are permitted provided that the following conditions are met: +;* 1. Redistributions of source code must retain the above copyright notice, +;* this list of conditions and the following disclaimer. +;* 2. Redistributions in binary form must reproduce the above copyright notice, +;* this list of conditions and the following disclaimer in the documentation +;* and/or other materials provided with the distribution. +;* 3. Neither the name of STMicroelectronics nor the names of its contributors +;* may be used to endorse or promote products derived from this software +;* without specific prior written permission. +;* +;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE +;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE +;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL +;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR +;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER +;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, +;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE +;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. +;* +;******************************************************************************* +; +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + + DATA +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + DCD WWDG_IRQHandler ; Window WatchDog + DCD PVD_IRQHandler ; PVD through EXTI Line detection + DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line + DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line + DCD FLASH_IRQHandler ; FLASH + DCD RCC_IRQHandler ; RCC + DCD EXTI0_IRQHandler ; EXTI Line0 + DCD EXTI1_IRQHandler ; EXTI Line1 + DCD EXTI2_IRQHandler ; EXTI Line2 + DCD EXTI3_IRQHandler ; EXTI Line3 + DCD EXTI4_IRQHandler ; EXTI Line4 + DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 + DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 + DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 + DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 + DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 + DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 + DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 + DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s + DCD CAN1_TX_IRQHandler ; CAN1 TX + DCD CAN1_RX0_IRQHandler ; CAN1 RX0 + DCD CAN1_RX1_IRQHandler ; CAN1 RX1 + DCD CAN1_SCE_IRQHandler ; CAN1 SCE + DCD EXTI9_5_IRQHandler ; External Line[9:5]s + DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 + DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 + DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 + DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare + DCD TIM2_IRQHandler ; TIM2 + DCD TIM3_IRQHandler ; TIM3 + DCD TIM4_IRQHandler ; TIM4 + DCD I2C1_EV_IRQHandler ; I2C1 Event + DCD I2C1_ER_IRQHandler ; I2C1 Error + DCD I2C2_EV_IRQHandler ; I2C2 Event + DCD I2C2_ER_IRQHandler ; I2C2 Error + DCD SPI1_IRQHandler ; SPI1 + DCD SPI2_IRQHandler ; SPI2 + DCD USART1_IRQHandler ; USART1 + DCD USART2_IRQHandler ; USART2 + DCD USART3_IRQHandler ; USART3 + DCD EXTI15_10_IRQHandler ; External Line[15:10]s + DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line + DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line + DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 + DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 + DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 + DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare + DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 + DCD FMC_IRQHandler ; FMC + DCD SDIO_IRQHandler ; SDIO + DCD TIM5_IRQHandler ; TIM5 + DCD SPI3_IRQHandler ; SPI3 + DCD UART4_IRQHandler ; UART4 + DCD UART5_IRQHandler ; UART5 + DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors + DCD TIM7_IRQHandler ; TIM7 + DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 + DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 + DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 + DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 + DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 + DCD ETH_IRQHandler ; Ethernet + DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line + DCD CAN2_TX_IRQHandler ; CAN2 TX + DCD CAN2_RX0_IRQHandler ; CAN2 RX0 + DCD CAN2_RX1_IRQHandler ; CAN2 RX1 + DCD CAN2_SCE_IRQHandler ; CAN2 SCE + DCD OTG_FS_IRQHandler ; USB OTG FS + DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 + DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 + DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 + DCD USART6_IRQHandler ; USART6 + DCD I2C3_EV_IRQHandler ; I2C3 event + DCD I2C3_ER_IRQHandler ; I2C3 error + DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out + DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In + DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI + DCD OTG_HS_IRQHandler ; USB OTG HS + DCD DCMI_IRQHandler ; DCMI + DCD 0 ; Reserved + DCD HASH_RNG_IRQHandler ; Hash and Rng + DCD FPU_IRQHandler ; FPU + DCD UART7_IRQHandler ; UART7 + DCD UART8_IRQHandler ; UART8 + DCD SPI4_IRQHandler ; SPI4 + DCD SPI5_IRQHandler ; SPI5 + DCD SPI6_IRQHandler ; SPI6 + DCD SAI1_IRQHandler ; SAI1 + DCD LTDC_IRQHandler ; LTDC + DCD LTDC_ER_IRQHandler ; LTDC error + DCD DMA2D_IRQHandler ; DMA2D + DCD QUADSPI_IRQHandler ; QUADSPI + DCD DSI_IRQHandler ; DSI Controller + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK WWDG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WWDG_IRQHandler + B WWDG_IRQHandler + + PUBWEAK PVD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PVD_IRQHandler + B PVD_IRQHandler + + PUBWEAK TAMP_STAMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TAMP_STAMP_IRQHandler + B TAMP_STAMP_IRQHandler + + PUBWEAK RTC_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_WKUP_IRQHandler + B RTC_WKUP_IRQHandler + + PUBWEAK FLASH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FLASH_IRQHandler + B FLASH_IRQHandler + + PUBWEAK RCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RCC_IRQHandler + B RCC_IRQHandler + + PUBWEAK EXTI0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI0_IRQHandler + B EXTI0_IRQHandler + + PUBWEAK EXTI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI1_IRQHandler + B EXTI1_IRQHandler + + PUBWEAK EXTI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI2_IRQHandler + B EXTI2_IRQHandler + + PUBWEAK EXTI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI3_IRQHandler + B EXTI3_IRQHandler + + PUBWEAK EXTI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI4_IRQHandler + B EXTI4_IRQHandler + + PUBWEAK DMA1_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream0_IRQHandler + B DMA1_Stream0_IRQHandler + + PUBWEAK DMA1_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream1_IRQHandler + B DMA1_Stream1_IRQHandler + + PUBWEAK DMA1_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream2_IRQHandler + B DMA1_Stream2_IRQHandler + + PUBWEAK DMA1_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream3_IRQHandler + B DMA1_Stream3_IRQHandler + + PUBWEAK DMA1_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream4_IRQHandler + B DMA1_Stream4_IRQHandler + + PUBWEAK DMA1_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream5_IRQHandler + B DMA1_Stream5_IRQHandler + + PUBWEAK DMA1_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream6_IRQHandler + B DMA1_Stream6_IRQHandler + + PUBWEAK ADC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_IRQHandler + B ADC_IRQHandler + + PUBWEAK CAN1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_TX_IRQHandler + B CAN1_TX_IRQHandler + + PUBWEAK CAN1_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_RX0_IRQHandler + B CAN1_RX0_IRQHandler + + PUBWEAK CAN1_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_RX1_IRQHandler + B CAN1_RX1_IRQHandler + + PUBWEAK CAN1_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN1_SCE_IRQHandler + B CAN1_SCE_IRQHandler + + PUBWEAK EXTI9_5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI9_5_IRQHandler + B EXTI9_5_IRQHandler + + PUBWEAK TIM1_BRK_TIM9_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_BRK_TIM9_IRQHandler + B TIM1_BRK_TIM9_IRQHandler + + PUBWEAK TIM1_UP_TIM10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_UP_TIM10_IRQHandler + B TIM1_UP_TIM10_IRQHandler + + PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_TRG_COM_TIM11_IRQHandler + B TIM1_TRG_COM_TIM11_IRQHandler + + PUBWEAK TIM1_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM1_CC_IRQHandler + B TIM1_CC_IRQHandler + + PUBWEAK TIM2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM2_IRQHandler + B TIM2_IRQHandler + + PUBWEAK TIM3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM3_IRQHandler + B TIM3_IRQHandler + + PUBWEAK TIM4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM4_IRQHandler + B TIM4_IRQHandler + + PUBWEAK I2C1_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_EV_IRQHandler + B I2C1_EV_IRQHandler + + PUBWEAK I2C1_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_ER_IRQHandler + B I2C1_ER_IRQHandler + + PUBWEAK I2C2_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_EV_IRQHandler + B I2C2_EV_IRQHandler + + PUBWEAK I2C2_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C2_ER_IRQHandler + B I2C2_ER_IRQHandler + + PUBWEAK SPI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI1_IRQHandler + B SPI1_IRQHandler + + PUBWEAK SPI2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI2_IRQHandler + B SPI2_IRQHandler + + PUBWEAK USART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_IRQHandler + B USART1_IRQHandler + + PUBWEAK USART2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_IRQHandler + B USART2_IRQHandler + + PUBWEAK USART3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_IRQHandler + B USART3_IRQHandler + + PUBWEAK EXTI15_10_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI15_10_IRQHandler + B EXTI15_10_IRQHandler + + PUBWEAK RTC_Alarm_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Alarm_IRQHandler + B RTC_Alarm_IRQHandler + + PUBWEAK OTG_FS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_WKUP_IRQHandler + B OTG_FS_WKUP_IRQHandler + + PUBWEAK TIM8_BRK_TIM12_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_BRK_TIM12_IRQHandler + B TIM8_BRK_TIM12_IRQHandler + + PUBWEAK TIM8_UP_TIM13_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_UP_TIM13_IRQHandler + B TIM8_UP_TIM13_IRQHandler + + PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_TRG_COM_TIM14_IRQHandler + B TIM8_TRG_COM_TIM14_IRQHandler + + PUBWEAK TIM8_CC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM8_CC_IRQHandler + B TIM8_CC_IRQHandler + + PUBWEAK DMA1_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA1_Stream7_IRQHandler + B DMA1_Stream7_IRQHandler + + PUBWEAK FMC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FMC_IRQHandler + B FMC_IRQHandler + + PUBWEAK SDIO_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SDIO_IRQHandler + B SDIO_IRQHandler + + PUBWEAK TIM5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM5_IRQHandler + B TIM5_IRQHandler + + PUBWEAK SPI3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI3_IRQHandler + B SPI3_IRQHandler + + PUBWEAK UART4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART4_IRQHandler + B UART4_IRQHandler + + PUBWEAK UART5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART5_IRQHandler + B UART5_IRQHandler + + PUBWEAK TIM6_DAC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM6_DAC_IRQHandler + B TIM6_DAC_IRQHandler + + PUBWEAK TIM7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIM7_IRQHandler + B TIM7_IRQHandler + + PUBWEAK DMA2_Stream0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream0_IRQHandler + B DMA2_Stream0_IRQHandler + + PUBWEAK DMA2_Stream1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream1_IRQHandler + B DMA2_Stream1_IRQHandler + + PUBWEAK DMA2_Stream2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream2_IRQHandler + B DMA2_Stream2_IRQHandler + + PUBWEAK DMA2_Stream3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream3_IRQHandler + B DMA2_Stream3_IRQHandler + + PUBWEAK DMA2_Stream4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream4_IRQHandler + B DMA2_Stream4_IRQHandler + + PUBWEAK ETH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH_IRQHandler + B ETH_IRQHandler + + PUBWEAK ETH_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ETH_WKUP_IRQHandler + B ETH_WKUP_IRQHandler + + PUBWEAK CAN2_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_TX_IRQHandler + B CAN2_TX_IRQHandler + + PUBWEAK CAN2_RX0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_RX0_IRQHandler + B CAN2_RX0_IRQHandler + + PUBWEAK CAN2_RX1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_RX1_IRQHandler + B CAN2_RX1_IRQHandler + + PUBWEAK CAN2_SCE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CAN2_SCE_IRQHandler + B CAN2_SCE_IRQHandler + + PUBWEAK OTG_FS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_FS_IRQHandler + B OTG_FS_IRQHandler + + PUBWEAK DMA2_Stream5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream5_IRQHandler + B DMA2_Stream5_IRQHandler + + PUBWEAK DMA2_Stream6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream6_IRQHandler + B DMA2_Stream6_IRQHandler + + PUBWEAK DMA2_Stream7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2_Stream7_IRQHandler + B DMA2_Stream7_IRQHandler + + PUBWEAK USART6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART6_IRQHandler + B USART6_IRQHandler + + PUBWEAK I2C3_EV_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_EV_IRQHandler + B I2C3_EV_IRQHandler + + PUBWEAK I2C3_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C3_ER_IRQHandler + B I2C3_ER_IRQHandler + + PUBWEAK OTG_HS_EP1_OUT_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_EP1_OUT_IRQHandler + B OTG_HS_EP1_OUT_IRQHandler + + PUBWEAK OTG_HS_EP1_IN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_EP1_IN_IRQHandler + B OTG_HS_EP1_IN_IRQHandler + + PUBWEAK OTG_HS_WKUP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_WKUP_IRQHandler + B OTG_HS_WKUP_IRQHandler + + PUBWEAK OTG_HS_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +OTG_HS_IRQHandler + B OTG_HS_IRQHandler + + PUBWEAK DCMI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DCMI_IRQHandler + B DCMI_IRQHandler + + PUBWEAK HASH_RNG_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +HASH_RNG_IRQHandler + B HASH_RNG_IRQHandler + + PUBWEAK FPU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FPU_IRQHandler + B FPU_IRQHandler + + PUBWEAK UART7_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART7_IRQHandler + B UART7_IRQHandler + + PUBWEAK UART8_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART8_IRQHandler + B UART8_IRQHandler + + PUBWEAK SPI4_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI4_IRQHandler + B SPI4_IRQHandler + + PUBWEAK SPI5_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI5_IRQHandler + B SPI5_IRQHandler + + PUBWEAK SPI6_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SPI6_IRQHandler + B SPI6_IRQHandler + + PUBWEAK SAI1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SAI1_IRQHandler + B SAI1_IRQHandler + + PUBWEAK LTDC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LTDC_IRQHandler + B LTDC_IRQHandler + + PUBWEAK LTDC_ER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LTDC_ER_IRQHandler + B LTDC_ER_IRQHandler + + PUBWEAK DMA2D_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA2D_IRQHandler + B DMA2D_IRQHandler + + PUBWEAK QUADSPI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +QUADSPI_IRQHandler + B QUADSPI_IRQHandler + + PUBWEAK DSI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DSI_IRQHandler + B DSI_IRQHandler + + END +/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/TOOLCHAIN_IAR/startup_stm32f469xx.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,704 +0,0 @@ -;/******************** (C) COPYRIGHT 2015 STMicroelectronics ******************** -;* File Name : startup_stm32f469xx.s -;* Author : MCD Application Team -;* Version : V2.4.1 -;* Date : 09-October-2015 -;* Description : STM32F469xx devices vector table for EWARM toolchain. -;* This module performs: -;* - Set the initial SP -;* - Set the initial PC == _iar_program_start, -;* - Set the vector table entries with the exceptions ISR -;* address. -;* - Branches to main in the C library (which eventually -;* calls main()). -;* After Reset the Cortex-M4 processor is in Thread mode, -;* priority is Privileged, and the Stack is set to Main. -;******************************************************************************** -;* -;* Redistribution and use in source and binary forms, with or without modification, -;* are permitted provided that the following conditions are met: -;* 1. Redistributions of source code must retain the above copyright notice, -;* this list of conditions and the following disclaimer. -;* 2. Redistributions in binary form must reproduce the above copyright notice, -;* this list of conditions and the following disclaimer in the documentation -;* and/or other materials provided with the distribution. -;* 3. Neither the name of STMicroelectronics nor the names of its contributors -;* may be used to endorse or promote products derived from this software -;* without specific prior written permission. -;* -;* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -;* AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -;* IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE -;* DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE -;* FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL -;* DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR -;* SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER -;* CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, -;* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE -;* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. -;* -;******************************************************************************* -; -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - - DATA -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler ; Reset Handler - - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - DCD WWDG_IRQHandler ; Window WatchDog - DCD PVD_IRQHandler ; PVD through EXTI Line detection - DCD TAMP_STAMP_IRQHandler ; Tamper and TimeStamps through the EXTI line - DCD RTC_WKUP_IRQHandler ; RTC Wakeup through the EXTI line - DCD FLASH_IRQHandler ; FLASH - DCD RCC_IRQHandler ; RCC - DCD EXTI0_IRQHandler ; EXTI Line0 - DCD EXTI1_IRQHandler ; EXTI Line1 - DCD EXTI2_IRQHandler ; EXTI Line2 - DCD EXTI3_IRQHandler ; EXTI Line3 - DCD EXTI4_IRQHandler ; EXTI Line4 - DCD DMA1_Stream0_IRQHandler ; DMA1 Stream 0 - DCD DMA1_Stream1_IRQHandler ; DMA1 Stream 1 - DCD DMA1_Stream2_IRQHandler ; DMA1 Stream 2 - DCD DMA1_Stream3_IRQHandler ; DMA1 Stream 3 - DCD DMA1_Stream4_IRQHandler ; DMA1 Stream 4 - DCD DMA1_Stream5_IRQHandler ; DMA1 Stream 5 - DCD DMA1_Stream6_IRQHandler ; DMA1 Stream 6 - DCD ADC_IRQHandler ; ADC1, ADC2 and ADC3s - DCD CAN1_TX_IRQHandler ; CAN1 TX - DCD CAN1_RX0_IRQHandler ; CAN1 RX0 - DCD CAN1_RX1_IRQHandler ; CAN1 RX1 - DCD CAN1_SCE_IRQHandler ; CAN1 SCE - DCD EXTI9_5_IRQHandler ; External Line[9:5]s - DCD TIM1_BRK_TIM9_IRQHandler ; TIM1 Break and TIM9 - DCD TIM1_UP_TIM10_IRQHandler ; TIM1 Update and TIM10 - DCD TIM1_TRG_COM_TIM11_IRQHandler ; TIM1 Trigger and Commutation and TIM11 - DCD TIM1_CC_IRQHandler ; TIM1 Capture Compare - DCD TIM2_IRQHandler ; TIM2 - DCD TIM3_IRQHandler ; TIM3 - DCD TIM4_IRQHandler ; TIM4 - DCD I2C1_EV_IRQHandler ; I2C1 Event - DCD I2C1_ER_IRQHandler ; I2C1 Error - DCD I2C2_EV_IRQHandler ; I2C2 Event - DCD I2C2_ER_IRQHandler ; I2C2 Error - DCD SPI1_IRQHandler ; SPI1 - DCD SPI2_IRQHandler ; SPI2 - DCD USART1_IRQHandler ; USART1 - DCD USART2_IRQHandler ; USART2 - DCD USART3_IRQHandler ; USART3 - DCD EXTI15_10_IRQHandler ; External Line[15:10]s - DCD RTC_Alarm_IRQHandler ; RTC Alarm (A and B) through EXTI Line - DCD OTG_FS_WKUP_IRQHandler ; USB OTG FS Wakeup through EXTI line - DCD TIM8_BRK_TIM12_IRQHandler ; TIM8 Break and TIM12 - DCD TIM8_UP_TIM13_IRQHandler ; TIM8 Update and TIM13 - DCD TIM8_TRG_COM_TIM14_IRQHandler ; TIM8 Trigger and Commutation and TIM14 - DCD TIM8_CC_IRQHandler ; TIM8 Capture Compare - DCD DMA1_Stream7_IRQHandler ; DMA1 Stream7 - DCD FMC_IRQHandler ; FMC - DCD SDIO_IRQHandler ; SDIO - DCD TIM5_IRQHandler ; TIM5 - DCD SPI3_IRQHandler ; SPI3 - DCD UART4_IRQHandler ; UART4 - DCD UART5_IRQHandler ; UART5 - DCD TIM6_DAC_IRQHandler ; TIM6 and DAC1&2 underrun errors - DCD TIM7_IRQHandler ; TIM7 - DCD DMA2_Stream0_IRQHandler ; DMA2 Stream 0 - DCD DMA2_Stream1_IRQHandler ; DMA2 Stream 1 - DCD DMA2_Stream2_IRQHandler ; DMA2 Stream 2 - DCD DMA2_Stream3_IRQHandler ; DMA2 Stream 3 - DCD DMA2_Stream4_IRQHandler ; DMA2 Stream 4 - DCD ETH_IRQHandler ; Ethernet - DCD ETH_WKUP_IRQHandler ; Ethernet Wakeup through EXTI line - DCD CAN2_TX_IRQHandler ; CAN2 TX - DCD CAN2_RX0_IRQHandler ; CAN2 RX0 - DCD CAN2_RX1_IRQHandler ; CAN2 RX1 - DCD CAN2_SCE_IRQHandler ; CAN2 SCE - DCD OTG_FS_IRQHandler ; USB OTG FS - DCD DMA2_Stream5_IRQHandler ; DMA2 Stream 5 - DCD DMA2_Stream6_IRQHandler ; DMA2 Stream 6 - DCD DMA2_Stream7_IRQHandler ; DMA2 Stream 7 - DCD USART6_IRQHandler ; USART6 - DCD I2C3_EV_IRQHandler ; I2C3 event - DCD I2C3_ER_IRQHandler ; I2C3 error - DCD OTG_HS_EP1_OUT_IRQHandler ; USB OTG HS End Point 1 Out - DCD OTG_HS_EP1_IN_IRQHandler ; USB OTG HS End Point 1 In - DCD OTG_HS_WKUP_IRQHandler ; USB OTG HS Wakeup through EXTI - DCD OTG_HS_IRQHandler ; USB OTG HS - DCD DCMI_IRQHandler ; DCMI - DCD 0 ; Reserved - DCD HASH_RNG_IRQHandler ; Hash and Rng - DCD FPU_IRQHandler ; FPU - DCD UART7_IRQHandler ; UART7 - DCD UART8_IRQHandler ; UART8 - DCD SPI4_IRQHandler ; SPI4 - DCD SPI5_IRQHandler ; SPI5 - DCD SPI6_IRQHandler ; SPI6 - DCD SAI1_IRQHandler ; SAI1 - DCD LTDC_IRQHandler ; LTDC - DCD LTDC_ER_IRQHandler ; LTDC error - DCD DMA2D_IRQHandler ; DMA2D - DCD QUADSPI_IRQHandler ; QUADSPI - DCD DSI_IRQHandler ; DSI Controller - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK WWDG_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -WWDG_IRQHandler - B WWDG_IRQHandler - - PUBWEAK PVD_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PVD_IRQHandler - B PVD_IRQHandler - - PUBWEAK TAMP_STAMP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TAMP_STAMP_IRQHandler - B TAMP_STAMP_IRQHandler - - PUBWEAK RTC_WKUP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC_WKUP_IRQHandler - B RTC_WKUP_IRQHandler - - PUBWEAK FLASH_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FLASH_IRQHandler - B FLASH_IRQHandler - - PUBWEAK RCC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RCC_IRQHandler - B RCC_IRQHandler - - PUBWEAK EXTI0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI0_IRQHandler - B EXTI0_IRQHandler - - PUBWEAK EXTI1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI1_IRQHandler - B EXTI1_IRQHandler - - PUBWEAK EXTI2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI2_IRQHandler - B EXTI2_IRQHandler - - PUBWEAK EXTI3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI3_IRQHandler - B EXTI3_IRQHandler - - PUBWEAK EXTI4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI4_IRQHandler - B EXTI4_IRQHandler - - PUBWEAK DMA1_Stream0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream0_IRQHandler - B DMA1_Stream0_IRQHandler - - PUBWEAK DMA1_Stream1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream1_IRQHandler - B DMA1_Stream1_IRQHandler - - PUBWEAK DMA1_Stream2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream2_IRQHandler - B DMA1_Stream2_IRQHandler - - PUBWEAK DMA1_Stream3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream3_IRQHandler - B DMA1_Stream3_IRQHandler - - PUBWEAK DMA1_Stream4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream4_IRQHandler - B DMA1_Stream4_IRQHandler - - PUBWEAK DMA1_Stream5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream5_IRQHandler - B DMA1_Stream5_IRQHandler - - PUBWEAK DMA1_Stream6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream6_IRQHandler - B DMA1_Stream6_IRQHandler - - PUBWEAK ADC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ADC_IRQHandler - B ADC_IRQHandler - - PUBWEAK CAN1_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN1_TX_IRQHandler - B CAN1_TX_IRQHandler - - PUBWEAK CAN1_RX0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN1_RX0_IRQHandler - B CAN1_RX0_IRQHandler - - PUBWEAK CAN1_RX1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN1_RX1_IRQHandler - B CAN1_RX1_IRQHandler - - PUBWEAK CAN1_SCE_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN1_SCE_IRQHandler - B CAN1_SCE_IRQHandler - - PUBWEAK EXTI9_5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI9_5_IRQHandler - B EXTI9_5_IRQHandler - - PUBWEAK TIM1_BRK_TIM9_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM1_BRK_TIM9_IRQHandler - B TIM1_BRK_TIM9_IRQHandler - - PUBWEAK TIM1_UP_TIM10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM1_UP_TIM10_IRQHandler - B TIM1_UP_TIM10_IRQHandler - - PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM1_TRG_COM_TIM11_IRQHandler - B TIM1_TRG_COM_TIM11_IRQHandler - - PUBWEAK TIM1_CC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM1_CC_IRQHandler - B TIM1_CC_IRQHandler - - PUBWEAK TIM2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM2_IRQHandler - B TIM2_IRQHandler - - PUBWEAK TIM3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM3_IRQHandler - B TIM3_IRQHandler - - PUBWEAK TIM4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM4_IRQHandler - B TIM4_IRQHandler - - PUBWEAK I2C1_EV_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C1_EV_IRQHandler - B I2C1_EV_IRQHandler - - PUBWEAK I2C1_ER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C1_ER_IRQHandler - B I2C1_ER_IRQHandler - - PUBWEAK I2C2_EV_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C2_EV_IRQHandler - B I2C2_EV_IRQHandler - - PUBWEAK I2C2_ER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C2_ER_IRQHandler - B I2C2_ER_IRQHandler - - PUBWEAK SPI1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI1_IRQHandler - B SPI1_IRQHandler - - PUBWEAK SPI2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI2_IRQHandler - B SPI2_IRQHandler - - PUBWEAK USART1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART1_IRQHandler - B USART1_IRQHandler - - PUBWEAK USART2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART2_IRQHandler - B USART2_IRQHandler - - PUBWEAK USART3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART3_IRQHandler - B USART3_IRQHandler - - PUBWEAK EXTI15_10_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI15_10_IRQHandler - B EXTI15_10_IRQHandler - - PUBWEAK RTC_Alarm_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC_Alarm_IRQHandler - B RTC_Alarm_IRQHandler - - PUBWEAK OTG_FS_WKUP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -OTG_FS_WKUP_IRQHandler - B OTG_FS_WKUP_IRQHandler - - PUBWEAK TIM8_BRK_TIM12_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM8_BRK_TIM12_IRQHandler - B TIM8_BRK_TIM12_IRQHandler - - PUBWEAK TIM8_UP_TIM13_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM8_UP_TIM13_IRQHandler - B TIM8_UP_TIM13_IRQHandler - - PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM8_TRG_COM_TIM14_IRQHandler - B TIM8_TRG_COM_TIM14_IRQHandler - - PUBWEAK TIM8_CC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM8_CC_IRQHandler - B TIM8_CC_IRQHandler - - PUBWEAK DMA1_Stream7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA1_Stream7_IRQHandler - B DMA1_Stream7_IRQHandler - - PUBWEAK FMC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FMC_IRQHandler - B FMC_IRQHandler - - PUBWEAK SDIO_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SDIO_IRQHandler - B SDIO_IRQHandler - - PUBWEAK TIM5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM5_IRQHandler - B TIM5_IRQHandler - - PUBWEAK SPI3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI3_IRQHandler - B SPI3_IRQHandler - - PUBWEAK UART4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART4_IRQHandler - B UART4_IRQHandler - - PUBWEAK UART5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART5_IRQHandler - B UART5_IRQHandler - - PUBWEAK TIM6_DAC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM6_DAC_IRQHandler - B TIM6_DAC_IRQHandler - - PUBWEAK TIM7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIM7_IRQHandler - B TIM7_IRQHandler - - PUBWEAK DMA2_Stream0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream0_IRQHandler - B DMA2_Stream0_IRQHandler - - PUBWEAK DMA2_Stream1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream1_IRQHandler - B DMA2_Stream1_IRQHandler - - PUBWEAK DMA2_Stream2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream2_IRQHandler - B DMA2_Stream2_IRQHandler - - PUBWEAK DMA2_Stream3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream3_IRQHandler - B DMA2_Stream3_IRQHandler - - PUBWEAK DMA2_Stream4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream4_IRQHandler - B DMA2_Stream4_IRQHandler - - PUBWEAK ETH_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ETH_IRQHandler - B ETH_IRQHandler - - PUBWEAK ETH_WKUP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ETH_WKUP_IRQHandler - B ETH_WKUP_IRQHandler - - PUBWEAK CAN2_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN2_TX_IRQHandler - B CAN2_TX_IRQHandler - - PUBWEAK CAN2_RX0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN2_RX0_IRQHandler - B CAN2_RX0_IRQHandler - - PUBWEAK CAN2_RX1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN2_RX1_IRQHandler - B CAN2_RX1_IRQHandler - - PUBWEAK CAN2_SCE_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CAN2_SCE_IRQHandler - B CAN2_SCE_IRQHandler - - PUBWEAK OTG_FS_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -OTG_FS_IRQHandler - B OTG_FS_IRQHandler - - PUBWEAK DMA2_Stream5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream5_IRQHandler - B DMA2_Stream5_IRQHandler - - PUBWEAK DMA2_Stream6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream6_IRQHandler - B DMA2_Stream6_IRQHandler - - PUBWEAK DMA2_Stream7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2_Stream7_IRQHandler - B DMA2_Stream7_IRQHandler - - PUBWEAK USART6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART6_IRQHandler - B USART6_IRQHandler - - PUBWEAK I2C3_EV_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C3_EV_IRQHandler - B I2C3_EV_IRQHandler - - PUBWEAK I2C3_ER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C3_ER_IRQHandler - B I2C3_ER_IRQHandler - - PUBWEAK OTG_HS_EP1_OUT_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -OTG_HS_EP1_OUT_IRQHandler - B OTG_HS_EP1_OUT_IRQHandler - - PUBWEAK OTG_HS_EP1_IN_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -OTG_HS_EP1_IN_IRQHandler - B OTG_HS_EP1_IN_IRQHandler - - PUBWEAK OTG_HS_WKUP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -OTG_HS_WKUP_IRQHandler - B OTG_HS_WKUP_IRQHandler - - PUBWEAK OTG_HS_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -OTG_HS_IRQHandler - B OTG_HS_IRQHandler - - PUBWEAK DCMI_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DCMI_IRQHandler - B DCMI_IRQHandler - - PUBWEAK HASH_RNG_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -HASH_RNG_IRQHandler - B HASH_RNG_IRQHandler - - PUBWEAK FPU_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FPU_IRQHandler - B FPU_IRQHandler - - PUBWEAK UART7_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART7_IRQHandler - B UART7_IRQHandler - - PUBWEAK UART8_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART8_IRQHandler - B UART8_IRQHandler - - PUBWEAK SPI4_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI4_IRQHandler - B SPI4_IRQHandler - - PUBWEAK SPI5_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI5_IRQHandler - B SPI5_IRQHandler - - PUBWEAK SPI6_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SPI6_IRQHandler - B SPI6_IRQHandler - - PUBWEAK SAI1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SAI1_IRQHandler - B SAI1_IRQHandler - - PUBWEAK LTDC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LTDC_IRQHandler - B LTDC_IRQHandler - - PUBWEAK LTDC_ER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LTDC_ER_IRQHandler - B LTDC_ER_IRQHandler - - PUBWEAK DMA2D_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA2D_IRQHandler - B DMA2D_IRQHandler - - PUBWEAK QUADSPI_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -QUADSPI_IRQHandler - B QUADSPI_IRQHandler - - PUBWEAK DSI_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DSI_IRQHandler - B DSI_IRQHandler - - END -/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/stm32f469xx.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/stm32f469xx.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f469xx.h * @author MCD Application Team - * @version V2.6.1 - * @date 14-February-2017 * @brief CMSIS STM32F469xx Device Peripheral Access Layer Header File. * * This file contains: @@ -67,9 +65,11 @@ #define __MPU_PRESENT 1U /*!< STM32F4XX provides an MPU */ #define __NVIC_PRIO_BITS 4U /*!< STM32F4XX uses 4 Bits for the Priority Levels */ #define __Vendor_SysTickConfig 0U /*!< Set to 1 if different SysTick Config is used */ +/* MBED */ #ifndef __FPU_PRESENT #define __FPU_PRESENT 1U /*!< FPU present */ #endif /* __FPU_PRESENT */ +/* MBED */ /** * @} @@ -17113,7 +17113,7 @@ #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!<Transmission Complete Interrupt Enable */ #define USART_CR1_TXEIE_Pos (7U) #define USART_CR1_TXEIE_Msk (0x1U << USART_CR1_TXEIE_Pos) /*!< 0x00000080 */ -#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<PE Interrupt Enable */ +#define USART_CR1_TXEIE USART_CR1_TXEIE_Msk /*!<TXE Interrupt Enable */ #define USART_CR1_PEIE_Pos (8U) #define USART_CR1_PEIE_Msk (0x1U << USART_CR1_PEIE_Pos) /*!< 0x00000100 */ #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!<PE Interrupt Enable */ @@ -18970,92 +18970,6 @@ #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFU << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */ #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */ -/******************** Bit definition for OTG register ********************/ - -#define USB_OTG_CHNUM_Pos (0U) -#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */ -#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */ -#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */ -#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */ -#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */ -#define USB_OTG_BCNT_Pos (4U) -#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */ - -#define USB_OTG_DPID_Pos (15U) -#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */ -#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */ -#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */ - -#define USB_OTG_PKTSTS_Pos (17U) -#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */ -#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */ -#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */ -#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */ -#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */ - -#define USB_OTG_EPNUM_Pos (0U) -#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */ -#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */ -#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */ -#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */ -#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */ - -#define USB_OTG_FRMNUM_Pos (21U) -#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */ -#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */ -#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */ -#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */ -#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */ -#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */ - -/******************** Bit definition for OTG register ********************/ - -#define USB_OTG_CHNUM_Pos (0U) -#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */ -#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */ -#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */ -#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */ -#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */ -#define USB_OTG_BCNT_Pos (4U) -#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */ -#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */ - -#define USB_OTG_DPID_Pos (15U) -#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */ -#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */ -#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */ -#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */ - -#define USB_OTG_PKTSTS_Pos (17U) -#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */ -#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */ -#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */ -#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */ -#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */ -#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */ - -#define USB_OTG_EPNUM_Pos (0U) -#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */ -#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */ -#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */ -#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */ -#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */ -#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */ - -#define USB_OTG_FRMNUM_Pos (21U) -#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */ -#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */ -#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */ -#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */ -#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */ -#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */ - /******************** Bit definition for USB_OTG_GRXFSIZ register ********************/ #define USB_OTG_GRXFSIZ_RXFD_Pos (0U) #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFU << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */ @@ -19739,6 +19653,48 @@ #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1U << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */ #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */ +/* Legacy define */ +/******************** Bit definition for OTG register ********************/ +#define USB_OTG_CHNUM_Pos (0U) +#define USB_OTG_CHNUM_Msk (0xFU << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */ +#define USB_OTG_CHNUM_0 (0x1U << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */ +#define USB_OTG_CHNUM_1 (0x2U << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */ +#define USB_OTG_CHNUM_2 (0x4U << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */ +#define USB_OTG_CHNUM_3 (0x8U << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */ +#define USB_OTG_BCNT_Pos (4U) +#define USB_OTG_BCNT_Msk (0x7FFU << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */ +#define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */ + +#define USB_OTG_DPID_Pos (15U) +#define USB_OTG_DPID_Msk (0x3U << USB_OTG_DPID_Pos) /*!< 0x00018000 */ +#define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */ +#define USB_OTG_DPID_0 (0x1U << USB_OTG_DPID_Pos) /*!< 0x00008000 */ +#define USB_OTG_DPID_1 (0x2U << USB_OTG_DPID_Pos) /*!< 0x00010000 */ + +#define USB_OTG_PKTSTS_Pos (17U) +#define USB_OTG_PKTSTS_Msk (0xFU << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */ +#define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */ +#define USB_OTG_PKTSTS_0 (0x1U << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */ +#define USB_OTG_PKTSTS_1 (0x2U << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */ +#define USB_OTG_PKTSTS_2 (0x4U << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */ +#define USB_OTG_PKTSTS_3 (0x8U << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */ + +#define USB_OTG_EPNUM_Pos (0U) +#define USB_OTG_EPNUM_Msk (0xFU << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */ +#define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */ +#define USB_OTG_EPNUM_0 (0x1U << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */ +#define USB_OTG_EPNUM_1 (0x2U << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */ +#define USB_OTG_EPNUM_2 (0x4U << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */ +#define USB_OTG_EPNUM_3 (0x8U << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */ + +#define USB_OTG_FRMNUM_Pos (21U) +#define USB_OTG_FRMNUM_Msk (0xFU << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */ +#define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */ +#define USB_OTG_FRMNUM_0 (0x1U << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */ +#define USB_OTG_FRMNUM_1 (0x2U << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */ +#define USB_OTG_FRMNUM_2 (0x4U << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */ +#define USB_OTG_FRMNUM_3 (0x8U << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */ /** * @} */
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/stm32f4xx.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/stm32f4xx.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx.h
* @author MCD Application Team
- * @version V2.6.1
- * @date 14-February-2017
* @brief CMSIS STM32F4xx Device Peripheral Access Layer Header File.
*
* The file is the unique include file that the application programmer
@@ -124,11 +122,11 @@
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS version number V2.6.1
+ * @brief CMSIS version number V2.6.2
*/
#define __STM32F4xx_CMSIS_VERSION_MAIN (0x02U) /*!< [31:24] main version */
#define __STM32F4xx_CMSIS_VERSION_SUB1 (0x06U) /*!< [23:16] sub1 version */
-#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
+#define __STM32F4xx_CMSIS_VERSION_SUB2 (0x02U) /*!< [15:8] sub2 version */
#define __STM32F4xx_CMSIS_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F4xx_CMSIS_VERSION ((__STM32F4xx_CMSIS_VERSION_MAIN << 24)\
|(__STM32F4xx_CMSIS_VERSION_SUB1 << 16)\
--- a/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/system_stm32f4xx.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/TARGET_STM32F469xI/device/system_stm32f4xx.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file system_stm32f4xx.h * @author MCD Application Team - * @version V2.6.1 - * @date 14-February-2017 * @brief CMSIS Cortex-M4 Device System Source File for STM32F4xx devices. ****************************************************************************** * @attention
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- <h1 style="margin-bottom: 0.25in; text-align: center;" align="center"><span style="font-size: 20pt; font-family: "Verdana","sans-serif"; color: rgb(51, 102, 255);">Release Notes for STM32F4xx HAL Drivers</span><span style="font-size: 20pt; font-family: "Verdana","sans-serif";"><o:p></o:p></span></h1>
- <p class="MsoNormal" style="text-align: center;" align="center"><span style="font-size: 10pt; font-family: "Arial","sans-serif"; color: black;">Copyright
- 2017 STMicroelectronics</span><span style="color: black;"><u1:p></u1:p><o:p></o:p></span></p>
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- <h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">Update History</span></h2><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 197px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.7.1 / 14-April-2017</span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes</span></u></b></p>
-
-<ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana; font-size: 13.3333px; font-style: normal; font-variant: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">Update CHM UserManuals to support LL drivers</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">General updates
-to fix known defects and enhancements implementation</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL CAN </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add
- management of overrun error. </span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Allow
- possibility to receive messages from the 2 RX FIFOs in parallel via
- interrupt.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Fix message
- lost issue with specific sequence of transmit requests.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Handle
- transmission failure with error callback, when NART is enabled.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US">Add __HAL_CAN_CANCEL_TRANSMIT() call to abort transmission when
- timeout is reached</span></li></ul></ul>
-<ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL PWR </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_PWREx_EnterUnderDriveSTOPMode() API: remove check on UDRDY flag</span></li></ul></ul>
-<ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">LL ADC </span>update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Fix wrong ADC group injected sequence configuration</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span></li></ul><ul><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">LL_ADC_INJ_SetSequencerRanks()
-and LL_ADC_INJ_GetSequencerRanks() API's update to take in
-consideration the ADC number of conversions</span></li></ul></ul><ul><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update the </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">defined values for</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"> ADC group injected seqencer ranks </span></li></ul></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 197px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.7.0 / 17-February-2017</span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes</span></u></b></p>
-
-<ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: bold; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">Add Low Layer drivers allowing performance and footprint optimization</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Low
-Layer drivers APIs provide register level programming: require deep
-knowledge of peripherals described in STM32F4xx Reference Manuals</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">Low
-Layer drivers are available for: ADC, Cortex, CRC, DAC, DMA,
-DMA2D, EXTI, GPIO, I2C, IWDG, LPTIM, PWR, RCC, RNG, RTC, SPI, TIM,
-USART, WWDG peripherals and additionnal Low Level Bus, System and
-Utilities APIs.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana;">Low Layer drivers APIs are implemented as static inline function in new<span class="Apple-converted-space"> </span><span style="font-style: italic;">Inc/stm32f4xx_ll_ppp.h</span><span class="Apple-converted-space"> </span>files for PPP peripherals, there is no configuration file and each<span class="Apple-converted-space"> </span></span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">stm32f4xx_ll_ppp.h</span><span class="Apple-converted-space"> </span>file must be included in user code.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">General updates to fix known defects and enhancements implementation</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Fix extra warnings with GCC compiler</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">HAL drivers clean up: remove double casting 'uint32_t' and 'U'</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add new<span class="Apple-converted-space"> </span><span style="font-weight: bold;">HAL MMC</span><span class="Apple-converted-space"></span><span class="Apple-converted-space"></span><span style="font-weight: bold;"></span><span class="Apple-converted-space"> </span>driver</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">The following changes done on the HAL drivers require an update on the application code based on older HAL versions</span></span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">HAL SD</span><span class="Apple-converted-space"> </span>update</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Overall rework of the driver for a more efficient implementation</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Modify initialization API and structures</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Modify Read / Write sequences: separate transfer process and SD Cards state management </span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Adding interrupt mode for Read / Write operations</span></li></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Update the HAL_SD_IRQHandler function by optimizing the management of interrupt errors<br></span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Refer to the following example to identify the changes: BSP example and USB_Device/MSC_Standalone application</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">HAL NAND</span><span class="Apple-converted-space"> </span>update</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Modify NAND_AddressTypeDef, NAND_DeviceConfigTypeDef and NAND_HandleTypeDef structures fields</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add new HAL_NAND_ConfigDevice API</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"><span style="font-weight: bold;">HAL DFSDM</span> update</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">Add support of Multichannel Delay feature</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">Add HAL_DFSDM_ConfigMultiChannelDelay API</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">The following APIs are moved to internal static functions:
-HAL_DFSDM_ClockIn_SourceSelection, HAL_DFSDM_ClockOut_SourceSelection,
-HAL_DFSDM_DataInX_SourceSelection (X=0,2,4,6),
-HAL_DFSDM_BitStreamClkDistribution_Config</span></li></ul></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">HAL I2S</span><span class="Apple-converted-space"> </span>update</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="color: black;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US">Add specific callback API to manage I2S full duplex end of transfer process:</span></li><ul><li class="MsoNormal" style="color: black;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US"></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US">HAL_I2S_TxCpltCallback() and
-HAL_I2S_RxCpltCallback() API's will be replaced with only </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US">HAL_I2SEx_TxRxCpltCallback()</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US"> API. </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US"></span></li></ul></ul></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL </span>update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Modifiy default HAL_Delay implementation to guarantee minimum delay </span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL Cortex</span> update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Move HAL_MPU_Disable() and HAL_MPU_Enable() from stm32f4xx_hal_cortex.h to stm32f4xx_hal_cortex.c</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Clear the whole MPU control register in </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_MPU_Disable() API</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL FLASH</span> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">IS_FLASH_ADDRESS() macro update to support OTP range</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">FLASH_Program_DoubleWord(): Replace 64-bit accesses with 2 double-words operations<br></span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">LL GPIO</span><span class="Apple-converted-space"> </span>update</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update IS_GPIO_PIN() macro implementation to be more safe</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">LL RCC</span><span class="Apple-converted-space"> </span>update</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update IS_RCC_PLLQ_VALUE() macro implementation: the minimum accepted value is 2 instead of 4</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Rename RCC_LPTIM1CLKSOURCE_PCLK define to RCC_LPTIM1CLKSOURCE_PCLK1</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Fix
-compilation issue w/ __HAL_RCC_USB_OTG_FS_IS_CLK_ENABLED() and
-__HAL_RCC_USB_OTG_FS_IS_CLK_DISABLED() macros for STM32F401xx devices</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add the following is clock enabled macros for STM32F401xx devices</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"> __HAL_RCC_SDIO_IS_CLK_ENABLED()</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">__HAL_RCC_SPI4_IS_CLK_ENABLED()</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">__HAL_RCC_TIM10_IS_CLK_ENABLED()</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add the following is clock enabled macros for STM32F410xx devices</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"> __HAL_RCC_CRC_IS_CLK_ENABLED()</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">__HAL_RCC_RNG_IS_CLK_ENABLED()</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update HAL_RCC_DeInit() to reset the RCC clock configuration to the default reset state.</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Remove macros to configure BKPSRAM from STM32F401xx devices </span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update to refer to AHBPrescTable[] and APBPrescTable[] tables defined in system_stm32f4xx.c file instead of </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">APBAHBPrescTable[] table.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"><span style="font-weight: bold;">HAL FMPI2C</span> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add FMPI2C_FIRST_AND_NEXT_FRAME define in Sequential Transfer Options</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"><span style="font-weight: bold;">HAL ADC </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL_ADCEx_InjectedConfigChannel(): update the external trigger injected condition</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"><span style="font-weight: bold;">HAL DMA </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL_DMA_Init(): update to check compatibility between FIFO threshold level and size of the memory burst </span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"><span style="font-weight: bold;">HAL QSPI </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">QSPI_HandleTypeDef structure: Update transfer parameters on uint32_t instead of uint16_t</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL UART/USART/IrDA/SMARTCARD </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><p class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-style: italic;"></span>DMA Receive process; the code
-has been updated to clear the USART OVR flag before enabling DMA receive request.</span></p></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">UART_SetConfig() update to manage correctly USART6 instance that is not available on STM32F410Tx devices<br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"><span style="font-weight: bold;">HAL CAN </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Remove Lock mechanism from HAL_CAN_Transmit_IT() and HAL_CAN_Receive_IT() processes</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"><span style="font-weight: bold;">HAL TIM </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><p class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY() macro to disable Master output without check on TIM channel state. </span></p></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update HAL_TIMEx_ConfigBreakDeadTime() to fix TIM BDTR register corruption.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"><span style="font-weight: bold;">HAL I2C </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update
-HAL_I2C_Master_Transmit() and HAL_I2C_Slave_Transmit() to avoid sending
-extra bytes at the end of the transmit processes</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;" lang="EN-US"><o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update
- HAL_I2C_Mem_Read() API to fix wrong check on misused parameter Size</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;" lang="EN-US"><o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update
- I2C_MasterReceive_RXNE() and I2C_MasterReceive_BTF() static APIs to
- enhance Master sequential reception process.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"><span style="font-weight: bold;">HAL SPI </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana",sans-serif; font-size: 10pt;">Add transfer abort APIs and associated callbacks in interrupt mode</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: "Verdana",sans-serif; font-size: 10pt;"></span><span style="font-family: Verdana; font-size: 10pt;">HAL_SPI_Abort()</span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">HAL_SPI_Abort_IT()</span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; font-size: 10pt;">HAL_SPI_AbortCpltCallback()</span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"><span style="font-weight: bold;">HAL I2S </span>update</span></li><ul><li class="MsoNormal" style="color: black;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US">Add specific callback API to manage I2S full duplex end of transfer process:</span></li><ul><li class="MsoNormal" style="color: black;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US">HAL_I2S_TxCpltCallback() and
-HAL_I2S_RxCpltCallback() API's will be replaced with only </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US">HAL_I2SEx_TxRxCpltCallback()</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US"> API. </span></li></ul><li class="MsoNormal" style="color: black;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US">Update I2S Transmit/Receive polling process to manage Overrun and Underrun errors</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US"></span></li><li class="MsoNormal" style="color: black;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US">Move
-the </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US">I2S clock input frequency
-calculation </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US">to HAL RCC driver.</span></li><li class="MsoNormal" style="color: black;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US">Update the
-HAL I2SEx driver to keep only full duplex feature.</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US"></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US">HAL_I2S_Init() API updated to</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US">Fix wrong I2S clock calculation when PCM mode is used.</span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US">Return state </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US">HAL_I2S_ERROR_PRESCALER</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US"> when the I2S clock is wrongly configured</span></li></ul></ul></ul>
-<ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"><span style="font-weight: bold;">HAL LTDC </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: 'Segoe UI'; color: rgb(0, 0, 0); direction: ltr;" dir="ltr">Optimize HAL_LTDC_IRQHandler() function by using direct register read</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: 'Segoe UI'; color: rgb(0, 0, 0); direction: ltr;" dir="ltr">Rename the following API's</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: 'Segoe UI'; color: rgb(0, 0, 0); direction: ltr;" dir="ltr">HAL_LTDC_Relaod() by HAL_LTDC_Reload()</span><span style="font-size: 10pt; font-family: 'Segoe UI'; color: rgb(0, 0, 0); direction: ltr;" dir="ltr"> </span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: 'Segoe UI'; color: rgb(0, 0, 0); direction: ltr;" dir="ltr">HAL_LTDC_StructInitFromVideoConfig() by HAL_LTDCEx_StructInitFromVideoConfig()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: 'Segoe UI'; color: rgb(0, 0, 0); direction: ltr;" dir="ltr">HAL_LTDC_StructInitFromAdaptedCommandConfig() by HAL_LTDCEx_StructInitFromAdaptedCommandConfig()</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: 'Segoe UI'; color: rgb(0, 0, 0); direction: ltr;" dir="ltr">Add new defines for LTDC layers (LTDC_LAYER_1 / LTDC_LAYER_2)</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: 'Segoe UI'; color: rgb(0, 0, 0); direction: ltr;" dir="ltr">Remove unused asserts</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">HAL USB</span><span class="Apple-converted-space"> <span style="font-weight: bold;">PCD</span> </span>update</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Flush all TX FIFOs on USB Reset</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Remove Lock mechanism from HAL_PCD_EP_Transmit() and HAL_PCD_EP_Receive() API's</span></li></ul></ul><span style="font-size: 10pt; font-family: 'Segoe UI'; color: rgb(0, 0, 0); direction: ltr;" dir="ltr"></span><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">LL USB</span><span class="Apple-converted-space"> </span>update</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Enable DMA Burst mode for USB OTG HS</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">Fix SD card detection issue</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">LL SDMMC</span><span class="Apple-converted-space"> </span>update</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add new SDMMC_CmdSDEraseStartAdd, SDMMC_CmdSDEraseEndAdd, SDMMC_CmdOpCondition and SDMMC_CmdSwitch functions</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span><span style="font-size: 10pt; font-family: "Arial",sans-serif; color: rgb(0, 32, 82);" lang="EN-US"><span style=""></span></span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.6.0 / 04-November-2016</span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes</span></u></b></p>
-
-<ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">Add<span class="Apple-converted-space"> </span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;">support of<span class="Apple-converted-space"> </span><b>STM32F413xx and </b></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;"><b>STM32F423xx</b></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;"> devices</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">General updates to fix known defects and enhancements implementation</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"><span style="font-weight: bold;">HAL CAN</span> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update to add the support of 3 CAN management</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"><span style="font-weight: bold;">HAL CRYP</span> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update to add the support of AES features</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"><span style="font-weight: bold;">HAL DFSDM</span> update</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;">Add definitions for new external trigger filters</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;">Add definition for new Channels 4, 5, 6 and 7</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important;">Add functions and API for Filter state configuration and management</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;" lang="EN-US">Add new functions: </span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;" lang="EN-US">HAL_DFSDM_BitstreamClock_Start()</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;" lang="EN-US"></span><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;" lang="EN-US">HAL_DFSDM_BitstreamClock_Stop()</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif; color: black;" lang="EN-US">HAL_DFSDM_BitStreamClkDistribution_Config() </span></li></ul></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;"><span style="font-weight: bold;">HAL DMA</span></span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;">Add the support of DMA Channels from 8 to 15</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;">Update HAL_DMA_DeInit() function with the check on DMA stream instance</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><b><span style="font-size: 10pt; font-family: Verdana,sans-serif;">HAL DSI</span></b><span style="font-size: 10pt; font-family: Verdana,sans-serif;"> update</span><span style="font-size: 12pt; font-family: 'Times New Roman',serif;"><o:p></o:p></span></li><ul style="margin-bottom: 0in; margin-top: 0cm; list-style-type: circle;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">Update HAL_DSI_ConfigHostTimeouts() and HAL_DSI_Init() functions to avoid scratch in DSI_CCR register</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><b><span style="font-size: 10pt; font-family: Verdana,sans-serif;">HAL FLASH</span></b><span style="font-size: 10pt; font-family: Verdana,sans-serif;"> update</span><span style="font-size: 12pt; font-family: 'Times New Roman',serif;"><o:p></o:p></span></li><ul style="margin-bottom: 0in; margin-top: 0cm; list-style-type: circle;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">Enhance FLASH_WaitForLastOperation() function implementation</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">Update __HAL_FLASH_GET_FLAG() macro implementation<br></span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;"><span style="font-weight: bold;">HAL GPIO</span><span class="Apple-converted-space"> </span>update</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;">Add specific alternate functions definitions</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><b><span style="font-size: 10pt; font-family: Verdana,sans-serif;">HAL I2C </span></b><span style="font-size: 10pt; font-family: Verdana,sans-serif;">update</span><span style="font-size: 12pt; font-family: 'Times New Roman',serif;"><o:p></o:p></span></li><ul style="margin-bottom: 0in; margin-top: 0cm; list-style-type: circle;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">Update I2C_DMAError() function implementation to ignore DMA FIFO error</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><b><span style="font-size: 10pt; font-family: Verdana,sans-serif;">HAL I2S </span></b><span style="font-size: 10pt; font-family: Verdana,sans-serif;">update</span><span style="font-size: 12pt; font-family: 'Times New Roman',serif;"><o:p></o:p></span></li><ul style="margin-bottom: 0in; margin-top: 0cm; list-style-type: circle;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">Enhance HAL_I2S_Init() implementation to test on PCM_SHORT and PCM_LONG standards</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><b><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL IRDA</span></b><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US"><span class="Apple-converted-space"> </span>update</span><span style="font-size: 12pt; font-family: 'Times New Roman',serif;" lang="EN-US"><o:p></o:p></span></li><ul style="margin-bottom: 0in; margin-top: 0cm; list-style-type: circle;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">Add new functions and call backs for Transfer Abort<o:p></o:p></span></li><ul style="margin-bottom: 0in; margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_IRDA_Abort()<o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_IRDA_AbortTransmit()<o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_IRDA_AbortReceive()<o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_IRDA_Abort_IT()<o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_IRDA_AbortTransmit_IT()<o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_IRDA_AbortReceive_IT()<o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_IRDA_AbortCpltCallback()<o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_IRDA_AbortTransmitCpltCallback()<o:p></o:p></span></li></ul></ul><ul style="margin-bottom: 0in; margin-top: 0cm;" type="square"><ul style="margin-bottom: 0in; margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_IRDA_AbortReceiveCpltCallback()</span></li></ul></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><b><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL PCD</span></b><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US"><span class="Apple-converted-space"> </span>update</span><span style="font-size: 12pt; font-family: 'Times New Roman',serif;" lang="EN-US"><o:p></o:p></span></li><ul style="margin-bottom: 0in; margin-top: 0cm; list-style-type: circle;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">Update HAL_PCD_GetRxCount() function implementation</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;"><span style="font-weight: bold;">HAL RCC</span><span class="Apple-converted-space"> </span>update</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;">Update __HAL_RCC_HSE_CONFIG() macro implementation</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;">Update<span class="Apple-converted-space"> </span></span><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;">__HAL_RCC_LSE_CONFIG() macro implementation</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><b><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL SMARTCARD</span></b><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US"><span class="Apple-converted-space"> </span>update</span><span style="font-size: 12pt; font-family: 'Times New Roman',serif;" lang="EN-US"><o:p></o:p></span></li><ul style="margin-bottom: 0in; margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">Add new functions and call backs for Transfer Abort<o:p></o:p></span></li><ul style="margin-bottom: 0in; margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_</span><span style="color: windowtext;" lang="EN-US"><span class="Apple-converted-space"> </span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">SMARTCARD_Abort()<o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_</span><span style="color: windowtext;" lang="EN-US"><span class="Apple-converted-space"> </span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">SMARTCARD_AbortTransmit()<o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_</span><span style="color: windowtext;" lang="EN-US"><span class="Apple-converted-space"> </span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">SMARTCARD_AbortReceive()<o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_</span><span style="color: windowtext;" lang="EN-US"><span class="Apple-converted-space"> </span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">SMARTCARD_Abort_IT()<o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_</span><span style="color: windowtext;" lang="EN-US"><span class="Apple-converted-space"> </span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">SMARTCARD_AbortTransmit_IT()<o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_</span><span style="color: windowtext;" lang="EN-US"><span class="Apple-converted-space"> </span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">SMARTCARD_AbortReceive_IT()<o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_</span><span style="color: windowtext;" lang="EN-US"><span class="Apple-converted-space"> </span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">SMARTCARD_AbortCpltCallback()<o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_</span><span style="color: windowtext;" lang="EN-US"><span class="Apple-converted-space"> </span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">SMARTCARD_AbortTransmitCpltCallback()<o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_</span><span style="color: windowtext;" lang="EN-US"><span class="Apple-converted-space"> </span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">SMARTCARD_AbortReceiveCpltCallback()</span></li></ul></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;"><span style="font-weight: bold;">HAL TIM</span><span class="Apple-converted-space"><span class="Apple-converted-space"> </span></span>update</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;">Update HAL_TIMEx_RemapConfig() function to manage TIM internal trigger remap: LPTIM or TIM3_TRGO</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;"><span style="font-weight: bold;">HAL UART<span class="Apple-converted-space"> </span></span>update</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;">Add Transfer abort functions and callbacks</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;"><span style="font-weight: bold;">HAL USART<span class="Apple-converted-space"> </span></span>update</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;">Add Transfer abort functions and callbacks</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.5.2 / 22-September-2016</span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes</span></u></b></p>
-
-<ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"><span style="font-weight: bold;">HAL I2C</span> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Fix wrong
-behavior in </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US">consecutive transfers in case of single byte transmission (Master/Memory Receive <br>interfaces)</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US">Update HAL_I2C_Master_Transmit_DMA() / HAL_I2C_Master_Receive_DMA()/ HAL_I2C_Slave_Transmit_DMA() <br>and HAL_I2C_Slave_Receive_DMA() to manage addressing phase through interruption instead of polling</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US">Add a </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US">check on I2C handle state </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US"></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US">at start of all I2C API's </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US">to ensure that I2C is ready</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US"></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;">
-
-<p class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US">Update I2C API's </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US">(Polling, IT and DMA interfaces)</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US"> to manage I2C </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US">XferSize and XferCount</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US"> handle parameters instead of API size parameter to help user to get information of counter in case of error. </span></p></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;">
-
-<p class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US">Update Abort functionality to manage DMA use
-case</span></p></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"><span style="font-weight: bold;">HAL FMPI2C</span> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">Update to disable Own Address</span><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"></span><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"> before setting the </span><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">new Own Address</span><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"> configuration:</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">Update HAL_FMPI2C_Init() to disable FMPI2C_OARx_EN bit before any configuration in OARx registers</span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"><span style="font-weight: bold;">HAL CAN </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">Update CAN receive processes to set CAN RxMsg FIFONumber parameter</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"><span style="font-weight: bold;">HAL UART </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">Update UART handle </span><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">TxXferCount and RxXferCount </span><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">parameters as volatile to avoid eventual issue with High Speed optimization </span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.5.1 / 01-July-2016</span></h3><p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes</span></u></b></p>
-
-<ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"><span style="font-weight: bold;">HAL GPIO</span> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">HAL_GPIO_Init()/HAL_GPIO_DeInit() API's: update GPIO_GET_INDEX() macro implementation to support all GPIO's</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"><span style="font-weight: bold;">HAL SPI</span> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">Fix regression issue: retore HAL_SPI_DMAPause() and HAL_SPI_DMAResume() </span><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">API's</span><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"> </span><span style="color: rgb(31, 73, 125);" lang="EN-US"></span><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"><span style="font-weight: bold;">HAL RCC</span> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">Fix FSMC macros compilation warnings with STM32F412Rx devices</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"><span style="font-weight: bold;">HAL DMA </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">HAL_DMA_PollFortransfer() API clean up <br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"><span style="font-weight: bold;">HAL PPP </span>update(PPP refers to IRDA, UART, USART and SMARTCARD)</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">Update HAL_PPP_IRQHandler() to add a check on interrupt source before managing the error</span><span style="font-family: "Courier New"; color: rgb(31, 73, 125);" lang="EN-US"><span style=""><span style="font-family: "Times New Roman"; font-style: normal; font-variant: normal; font-weight: normal; font-size: 7pt; line-height: normal; font-size-adjust: none; font-stretch: normal;"> </span></span></span><span style="color: rgb(31, 73, 125);" lang="EN-US"><o:p></o:p></span></li></ul></ul>
-
-
-<ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"><span style="font-weight: bold;">HAL QSPI </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">Implement
-workaround to fix the limitation </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US">pronounced </span><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;"> in the Errata
-sheet 2.1.8 section: In some specific cases, DMA2 data corruption
-occurs when managing AHB and APB2 peripherals in a concurrent way</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.5.0 / 06-May-2016</span></h3>
-<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes</span></u></b></p>
-
-<ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; display: inline ! important; float: none;">Add<span class="Apple-converted-space"> </span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;">support of<span class="Apple-converted-space"> </span><b>STM32F412cx, </b></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;"><span class="Apple-converted-space"></span><b>STM32F412rx, </b></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;"><span class="Apple-converted-space"></span><b>STM32F412vx and </b></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;"><span class="Apple-converted-space"></span><b>STM32F412zx</b></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;"><b> </b><span class="Apple-converted-space"></span>devices</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">General updates to fix known defects and enhancements implementation</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Add new HAL driver for <span style="font-weight: bold;">DFSDM</span><span style="font-weight: bold;"> </span>peripheral</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal">
-
-<span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Enhance HAL delay and time base implementation</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">:</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add
-new drivers stm32f4xx_hal_timebase_rtc_alarm_template.c and
-stm32f4xx_hal_timebase_rtc_wakeup_template.c which override the native
-HAL time base functions (defined as weak) to either use the RTC as time
-base tick source. For more details about the usage of these drivers,
-please refer to HAL\HAL_TimeBase_RTC examples </span><span style="color: rgb(0, 0, 0); font-family: Verdana,sans-serif; font-size: 13.3333px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: left; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; float: none; display: inline ! important;">and FreeRTOS-based applications</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">The following changes done on the HAL drivers require an update on the application code based on HAL V1.4.4</span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-style: italic;">HAL UART, USART, IRDA, SMARTCARD, SPI, I2C,FMPI2C, QSPI<span class="Apple-converted-space"> </span></span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-style: italic;"></span>(referenced as<span class="Apple-converted-space"> </span><span style="font-style: italic;">PPP</span><span class="Apple-converted-space"> </span>here below)<span style="font-style: italic;"></span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-style: italic;"><span class="Apple-converted-space"> </span></span>drivers</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add PPP error management during DMA process. This requires the following updates on </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">user application:</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Configure and enable the PPP IRQ in HAL_PPP_MspInit() function<br></span></li></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">In<span class="Apple-converted-space"> </span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">stm32f4xx_it.c file,<span class="Apple-converted-space"> </span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">PPP_IRQHandler() function:<span class="Apple-converted-space"> </span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">add a call to HAL_PPP_IRQHandler() function</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add and customize the Error Callback API: HAL_PPP_ErrorCallback()<br></span></li></ul></ul></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-style: italic;">HAL I2C</span><span style="font-style: italic;"></span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-style: italic;"></span><span class="Apple-converted-space">, FMPI2C </span>(referenced as<span class="Apple-converted-space"> </span><span style="font-style: italic;">PPP</span><span class="Apple-converted-space"> </span>here below)<span style="font-style: italic;"></span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-style: italic;"><span class="Apple-converted-space"> </span></span>drivers:</span><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update to avoid waiting on<span class="Apple-converted-space"> </span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">STOPF/BTF/AF flag under DMA ISR by using the<span class="Apple-converted-space"> </span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">PPP end of transfer interrupt in the </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">DMA transfer process.</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span class="Apple-converted-space"> </span>This requires the following updates on </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">user application</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">:</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Configure and enable the PPP IRQ in HAL_PPP_MspInit() function<br></span></li></ul></ul><ul style="margin-bottom: 0in;"><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">In<span class="Apple-converted-space"> </span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">stm32f4xx_it.c file,<span class="Apple-converted-space"> </span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">PPP_IRQHandler() function:<span class="Apple-converted-space"> </span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">add a call to HAL_PPP_IRQHandler() function</span></li></ul></ul></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;"><span style="font-style: italic;">HAL I2C</span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;"><span style="font-style: italic;"></span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;"><span style="font-style: italic;"> </span>driver:</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;"></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">I2C
-transfer processes IT update: NACK during addressing phase is managed
-through I2C Error interrupt instead of HAL state</span></li></ul></ul></ul><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-style: italic;">HAL IWDG</span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-style: italic;"><span class="Apple-converted-space"> </span></span>driver: rework overall driver for better implementation</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Remove </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_IWDG_Start(),<span class="Apple-converted-space"> </span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_IWDG_MspInit() and<span class="Apple-converted-space"> </span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_IWDG_GetState() </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">APIs</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-style: italic;">HAL WWDG</span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-style: italic;"><span class="Apple-converted-space"> </span></span>driver: rework overall driver for better implementation</span><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Remove HAL_WWDG_Start(),<span class="Apple-converted-space"> </span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_WWDG_Start_IT(),</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US"><span class="Apple-converted-space"> </span>HAL_WWDG_MspDeInit() and<span class="Apple-converted-space"> </span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_WWDG_GetState() APIs </span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Update the </span><span style="font-family: Calibri,sans-serif; font-size: 11pt;" lang="EN-US"></span><span style="font-family: Calibri,sans-serif; font-size: 11pt;" lang="EN-US"></span><span style="font-family: Calibri,sans-serif; font-size: 11pt;" lang="EN-US"></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US"></span><span style="font-family: Calibri,sans-serif; font-size: 11pt;" lang="EN-US">HAL_WWDG_Refresh</span><span style="font-family: Calibri,sans-serif; font-size: 11pt;" lang="EN-US">(WWDG_HandleTypeDef *hwwdg, uint32_t counter) function and API by removing the "counter" parameter</span><span style="font-family: Calibri,sans-serif; font-size: 11pt;" lang="EN-US"></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-style: italic;"></span></span></li></ul></li></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-style: italic;">HAL QSPI driver:<span class="Apple-converted-space"> </span></span> Enhance the DMA transmit process by using PPP TC interrupt instead of waiting on TC flag under DMA ISR. </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">This requires the following updates on </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">user application</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">:</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Configure and enable the QSPI IRQ in HAL_QSPI_MspInit() function</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">In<span class="Apple-converted-space"> </span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">stm32f4xx_it.c file,<span class="Apple-converted-space"> </span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">QSPI_IRQHandler() function:<span class="Apple-converted-space"> </span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">add a call to HAL_QSPI_IRQHandler() function</span></li></ul></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-style: italic;"></span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-style: italic;"></span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-style: italic;">HAL CEC driver:<span class="Apple-converted-space"> </span></span> Overall driver rework with compatibility break versus previous HAL version</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Remove HAL CEC polling Process functions: HAL_CEC_Transmit() and HAL_CEC_Receive()</span><span style="font-family: 'Times New Roman',serif; font-size: 12pt;" lang="EN-US"><o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Remove
-HAL CEC receive interrupt process function HAL_CEC_Receive_IT()
-and enable the "receive" mode during the Init phase</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Rename HAL_CEC_GetReceivedFrameSize() funtion to HAL_CEC_GetLastReceivedFrameSize()<br></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Add new HAL APIs: HAL_CEC_SetDeviceAddress() and HAL_CEC_ChangeRxBuffer()</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Remove the <span></span>'InitiatorAddress'
-field from the CEC_InitTypeDef structure and manage
-it as a parameter in the HAL_CEC_Transmit_IT() function</span><span style="font-family: 'Times New Roman',serif; font-size: 12pt;" lang="EN-US"><o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Add new parameter 'RxFrameSize' in HAL_CEC_RxCpltCallback() function</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Move CEC Rx buffer pointer from CEC_HandleTypeDef structure to CEC_InitTypeDef structure</span></li></ul></ul></ul><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL RCC </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL_RCC_ClockConfig() function to adjust the SystemCoreClock</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Rename macros and Literals:</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">RCC_PERIPHCLK_CK48 by </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">RCC_PERIPHCLK_C<span style="font-weight: bold;">L</span>K48</span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">IS_RCC_CK48CLKSOURCE</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"> by IS_RCC_C<span style="font-weight: bold;">L</span>K48CLKSOURCE</span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">RCC_CK48CLKSOURCE_PLLSAIP by RCC_C<span style="font-weight: bold;">L</span>K48CLKSOURCE_PLLSAIP</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">RCC_SDIOCLKSOURCE_CK48 by RCC_SDIOCLKSOURCE_C<span style="font-weight: bold;">L</span>K48<br></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">RCC_CK48CLKSOURCE_PLLQ by RCC_C<span style="font-weight: bold;">L</span>K48CLKSOURCE_PLLQ<br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL_RCCEx_GetPeriphCLKConfig() and HAL_RCCEx_PeriphCLKConfig() functions to support TIM Prescaler for STM32F411xx devices</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_RCCEx_PeriphCLKConfig() API: update to fix the RTC clock configuration issue</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal">
-
-<b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL CEC </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">update</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Overall driver rework with break of compatibility with HAL V1.4.4<br></span></li></ul><ul style="margin-bottom: 0in;"><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Remove the HAL CEC polling Process: HAL_CEC_Transmit() and HAL_CEC_Receive()</span><span style="font-family: 'Times New Roman',serif; font-size: 12pt;" lang="EN-US"><o:p></o:p></span></li></ul></ul><ul style="margin-bottom: 0in; margin-top: 0cm;" type="circle"><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Remove the HAL CEC receive interrupt process (HAL_CEC_Receive_IT()) and manage the "Receive" mode enable within the Init phase</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Rename HAL_CEC_GetReceivedFrameSize() function to HAL_CEC_GetLastReceivedFrameSize() function<br></span></li></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Add new HAL APIs: HAL_CEC_SetDeviceAddress() and HAL_CEC_ChangeRxBuffer()</span></li></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Remove the <span></span>'InitiatorAddress'
-field from the CEC_InitTypeDef structure and manage
-it as a parameter in the HAL_CEC_Transmit_IT() function</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US"></span></li></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Add new parameter 'RxFrameSize' in HAL_CEC_RxCpltCallback() function</span><span style="font-family: 'Times New Roman',serif; font-size: 12pt;" lang="EN-US"><o:p></o:p></span></li></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Move CEC Rx buffer pointer from CEC_HandleTypeDef structure to CEC_InitTypeDef structure</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US"><o:p></o:p></span></li></ul></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update driver to implement the new CEC state machine:</span></li></ul><ul style="margin-bottom: 0in;"><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add new </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">"rxState"</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span class="Apple-converted-space"> </span>field in CEC_HandleTypeDef structure to provide the<span class="Apple-converted-space"> </span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">CEC<span class="Apple-converted-space"> </span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">state information related to Rx Operations</span></li></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Rename "state" field in CEC_HandleTypeDef structure to "gstate": CEC<span class="Apple-converted-space"> </span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">state information related to global Handle management and Tx Operations</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update CEC process to manage the new CEC states.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; color: black; font-size: 10pt;" lang="EN-US">Update __HAL_CEC_RESET_HANDLE_STATE() macro to handle the new CEC state parameters (gState, rxState)</span></li></ul></ul></ul><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal">
-
-<b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL UART, USART, SMARTCARD and IRDA </span></b><span style="font-size: 10pt; font-family: Verdana,sans-serif;"><span style="font-style: italic;"></span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;"><span style="font-style: italic;"></span>(referenced as <span style="font-style: italic;">PPP</span> here below)<span style="font-style: italic;"></span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;"><span style="font-style: italic;"> </span></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">update<b><o:p></o:p></b></span>
-</li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Update Polling management:</span></li></ul><ul style="margin-bottom: 0in;"><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">The user Timeout value must be estimated for the overall process duration: the Timeout measurement is cumulative</span></li></ul></ul><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update DMA process:</span></li></ul><ul style="margin-bottom: 0in;"><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update the m</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">anagement of PPP peripheral errors during DMA process. This requires the following updates in user application:</span></li></ul><ul style="margin-bottom: 0in;"><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Configure and enable the PPP IRQ in HAL_PPP_MspInit() function</span></li></ul><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">In stm32f4xx_it.c file, PPP_IRQHandler() function: add a call to HAL_PPP_IRQHandler() function</span></li></ul><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Add and customize the Error Callback API: HAL_PPP_ErrorCallback()</span></li></ul></ul></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">HAL FMC</span><span class="Apple-converted-space"> </span>update</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update FMC_NORSRAM_Init() to remove the Burst access mode configuration</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update FMC_SDRAM_Timing_Init() to fix initialization issue when configuring 2 SDRAM banks</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">HAL HCD</span><span class="Apple-converted-space"> </span>update</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update HCD_Port_IRQHandler() to unmask disconnect IT only when the port is disabled</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL I2C/FMPI2C</span></b><span style="font-size: 10pt; font-family: Verdana,sans-serif;"><span style="font-style: italic;"></span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;"><span style="font-style: italic;"> </span></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">update</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">Update<span class="Apple-converted-space"> </span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">Polling management:</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">The Timeout value must be estimated for the overall process duration: the Timeout measurement is cumulative<br></span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add the management of Abort service: Abort DMA transfer through interrupt</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">In the case of Master Abort IT transfer usage:</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add new user HAL_I2C_AbortCpltCallback() to inform user of the end of abort process</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">A new abort state is defined in the<span class="Apple-converted-space"> </span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_I2C_StateTypeDef<span class="Apple-converted-space"> </span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">structure</span></li></ul></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add
-the management of I2C peripheral errors, ACK failure and STOP condition
-detection during DMA process. This requires the following updates on
-user application:</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Configure and enable the I2C IRQ in HAL_I2C_MspInit() function</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">In stm32f4xx_it.c file, I2C_IRQHandler() function: add a call to HAL_I2C_IRQHandler() function</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add and customize the Error Callback API: HAL_I2C_ErrorCallback()</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Refer to the I2C_EEPROM or I2C_TwoBoards_ComDMA project examples usage of the API<br></span></li></ul></ul><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">NACK error during addressing phase is returned through interrupt instead of previously through I2C transfer API's</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">I2C addressing phase is updated to be managed
-using interrupt instead of polling (Only for HAL I2C driver)</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add new static functions to manage I2C SB, ADDR and ADD10 flags</span></li></ul></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><b><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL SPI<span class="Apple-converted-space"> </span></span></b><span style="font-size: 10pt; font-family: Verdana,sans-serif;">update</span></li></ul><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; margin-top: 0cm;" type="square"><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Overall driver optimization to improve performance in polling/interrupt mode to reach maximum peripheral frequency</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Polling mode:</span></li><ul style="margin-bottom: 0in;"><li><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Replace the use of SPI_WaitOnFlagUnitTimeout() function by "if" statement to check on RXNE/TXE flage while transferring data</span></li></ul></ul></ul></ul><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; margin-top: 0cm;" type="square"><ul style="margin-bottom: 0in;"><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"> Interrupt mode:</span></li><ul style="margin-bottom: 0in;"><li><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Minimize access on SPI registers</span></li></ul></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">All modes:</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add the USE_SPI_CRC switch to minimize the number of statements when CRC calculation is disabled</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update timeout management to check on global processes</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update error code management in all processes</span></li></ul></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update DMA process:<o:p></o:p></span><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add the management of SPI peripheral errors during DMA process. This requires the following updates in the user application:</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Configure and enable the SPI IRQ in HAL_SPI_MspInit() function</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">In stm32f4xx_it.c file, SPI_IRQHandler() function: add a call to HAL_SPI_IRQHandler() function</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add and customize the Error Callback API: HAL_SPI_ErrorCallback()</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Refer to the following example which describe the changes: SPI_FullDuplex_ComDMA</span></li></ul></ul></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Fix regression in polling mode:<o:p></o:p></span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Add preparing data to transmit in case of slave mode in HAL_SPI_TransmitReceive() and HAL_SPI_Transmit()<o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Add to manage properly the overrun flag at the end of a HAL_SPI_TransmitReceive()<o:p></o:p></span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Fix regression in interrupt mode:<o:p></o:p></span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Add a wait on TXE flag in SPI_CloseTx_ISR() and in SPI_CloseTxRx_ISR()<o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Add to manage properly the overrun flag in SPI_CloseRxTx_ISR() and SPI_CloseRx_ISR()</span></li></ul></ul></ul><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><b><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL DMA2D<span class="Apple-converted-space"> </span></span></b><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">update</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update the HAL_DMA2D_DeInit() function to:</span><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; list-style-type: square; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Abort transfer in case of ongoing DMA2D transfer</span></li></ul><ul style="margin-bottom: 0in;"><li><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Reset DMA2D control registers</span></li></ul></li><li><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update HAL_DMA2D_Abort() to disable DMA2D interrupts after stopping transfer</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Optimize HAL_DMA2D_IRQHandler() by reading status registers only once</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update HAL_DMA2D_ProgramLineEvent() function to:</span><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Return HAL error state in case of wrong line value</span></li></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Enable line interrupt after setting the line watermark configuration</span></li></ul></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add new HAL_DMA2D_CLUTLoad() and<span class="Apple-converted-space"> </span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_DMA2D_CLUTLoad_IT()</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span class="Apple-converted-space"> </span>functions to start DMA2D CLUT loading</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_DMA2D_CLUTLoading_Abort() function to abort the DMA2D CLUT loading</span></li></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_DMA2D_CLUTLoading_Suspend() function to suspend the DMA2D CLUT loading</span></li></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_DMA2D_CLUTLoading_Resume() function to resume the DMA2D CLUT loading</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add new DMA2D dead time management:</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_DMA2D_EnableDeadTime() function to enable DMA2D dead time feature</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_DMA2D_DisableDeadTime() function to disable DMA2D dead time feature</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_DMA2D_ConfigDeadTime() function to configure dead time</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update
-the name of DMA2D Input/Output color mode defines to be more clear for
-user (DMA2D_INPUT_XXX for input layers Colors, DMA2D_OUTPUT_XXX for
-output framebuffer Colors)</span></li></ul></ul><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><b><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL LTDC<span class="Apple-converted-space"> </span></span></b><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">update</span></li></ul><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; margin-top: 0cm;" type="square"><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update HAL_LTDC_IRQHandler() to manage the case of reload interrupt</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add new callback API HAL_LTDC_ReloadEventCallback()</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add HAL_LTDC_Reload() to configure LTDC reload feature</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add new No Reload LTDC variant APIs<br></span><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_LTDC_ConfigLayer_NoReload() to configure the LTDC Layer according to the specified without reloading</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_LTDC_SetWindowSize_NoReload() to set the LTDC window size without reloading</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_LTDC_SetWindowPosition_NoReload() to set the LTDC window position without reloading</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_LTDC_SetPixelFormat_NoReload() to reconfigure the pixel format without reloading</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_LTDC_SetAlpha_NoReload() to reconfigure the layer alpha value without reloading</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_LTDC_SetAddress_NoReload() to reconfigure the frame buffer Address without reloading</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_LTDC_SetPitch_NoReload() to reconfigure the pitch for specific cases</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_LTDC_ConfigColorKeying_NoReload() to configure the color keying without reloading</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_LTDC_EnableColorKeying_NoReload() to enable the color keying without reloading</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_LTDC_DisableColorKeying_NoReload() to disable the color keying without reloading</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_LTDC_EnableCLUT_NoReload() to enable the color lookup table without reloading</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_LTDC_DisableCLUT_NoReload() to disable the color lookup table without reloading</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="text-decoration: underline; font-style: italic;">Note:</span><span class="Apple-converted-space"> </span>Variant
-functions with _NoReload post fix allows to set the LTDC
-configuration/settings without immediate reload. This is useful in case
-when the program requires to modify several LTDC settings (on one or
-both layers) then applying (reload) these settings in one shot by
-calling the function HAL_LTDC_Reload</span></li></ul></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">HAL RTC<span class="Apple-converted-space"> </span></span>update </span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add new timeout implementation based on cpu cycles for ALRAWF, ALRBWF and WUTWF flags</span></li></ul></ul><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><b><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL SAI<span class="Apple-converted-space"> </span></span></b><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">update<o:p></o:p></span><br><span style="font-family: Verdana,sans-serif; font-size: 10pt; font-weight: normal;"></span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update SAI state in case of TIMEOUT error within the<span class="Apple-converted-space"> </span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_SAI_Transmit() / HAL_SAI_Receive()</span></li></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update HAL_SAI_IRQHandler:</span><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add error management in case DMA errors through XferAbortCallback() and HAL_DMA_Abort_IT()</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add error management in case of IT</span></li></ul></li></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Move
-SAI_BlockSynchroConfig() and SAI_GetInputClock() functions to
-stm32f4xx_hal_sai.c/.h files (extension files are kept empty for
-projects compatibility reason)</span></li></ul></ul><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><b><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL DCMI<span class="Apple-converted-space"> </span></span></b><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">update<o:p></o:p></span><br><span style="font-family: Verdana,sans-serif; font-size: 10pt; font-weight: normal;"></span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Rename DCMI_DMAConvCplt to DCMI_DMAXferCplt</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update<span class="Apple-converted-space"> </span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_DCMI_Start_DMA() function to </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Enable the DCMI peripheral</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add new timeout implementation based on cpu cycles for DCMI stop</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add HAL_DCMI_Suspend() function to suspend DCMI capture</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add HAL_DCMI_Resume() function to resume capture after DCMI suspend</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update lock mechanism for DCMI process</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update HAL_DCMI_IRQHandler() function to:</span><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add error management in case DMA errors through XferAbortCallback() and HAL_DMA_Abort_IT()</span></li></ul><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Optimize code by using direct register read</span></li></ul></li></ul></ul><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL <span style="font-style: italic;">DMA</span></span></b><span style="font-size: 10pt; font-family: Verdana,sans-serif;"><span style="font-style: italic;"> </span></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">update</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add
-new APIs HAL_DMA_RegisterCallback() and HAL_DMA_UnRegisterCallback to
-register/unregister the different callbacks identified by the enum
-typedef HAL_DMA_CallbackIDTypeDef</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add new API HAL_DMA_Abort_IT() to abort DMA transfer under interrupt context<br></span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">The new registered Abort callback is called when DMA transfer abortion is completed</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add the check of compatibility between FIFO threshold level and size of the memory burst in the HAL_DMA_Init() API</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add new Error Codes: HAL_DMA_ERROR_PARAM, HAL_DMA_ERROR_NO_XFER and HAL_DMA_ERROR_NOT_SUPPORTED</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Remove all DMA states related to MEM0/MEM1 in HAL_DMA_StateTypeDef</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL IWDG</span></b><span style="font-size: 10pt; font-family: Verdana,sans-serif;"><span style="font-style: italic;"></span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;"><span style="font-style: italic;"> </span></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">update</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Overall rework of the driver for a more efficient implementation</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Remove the following APIs:</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_IWDG_Start()</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_IWDG_MspInit()</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_IWDG_GetState()</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Update implementation:</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_IWDG_Init(): this function insures the configuration and the start of the IWDG counter</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_IWDG_Refresh(): this function insures the reload of the IWDG counter</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Refer to the following example to identify the changes: IWDG_Example</span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL LPTIM</span></b><span style="font-size: 10pt; font-family: Verdana,sans-serif;"><span style="font-style: italic;"></span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;"><span style="font-style: italic;"> </span></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">update</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">Update </span><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_LPTIM_TimeOut_Start_IT()
-and HAL_LPTIM_Counter_Start_IT( ) APIs to configure WakeUp Timer EXTI
-interrupt to be able to wakeup MCU from low power mode by </span><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">pressing the EXTI line. </span><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US"></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">Update </span><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">HAL_LPTIM_TimeOut_Stop_IT()
-and HAL_LPTIM_Counter_Stop_IT( ) APIs to disable WakeUp Timer EXTI
-interrupt. </span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">HAL NOR</span><span class="Apple-converted-space"> </span>update</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Update NOR_ADDR_SHIFT macro implementation</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">HAL PCD</span><span class="Apple-converted-space"> </span>update</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update HAL_PCD_IRQHandler() to get HCLK frequency before setting TRDT value</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL QSPI</span></b><span style="font-size: 10pt; font-family: Verdana,sans-serif;"><span style="font-style: italic;"></span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;"><span style="font-style: italic;"> </span></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">update</span></li></ul><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; margin-top: 0cm;" type="square"><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update to manage QSPI error management during DMA process</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Improve the DMA transmit process by using QSPI TC interrupt instead of waiting loop on TC flag under DMA ISR</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">These two improvements require the following updates on user application:</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Configure and enable the QSPI IRQ in HAL_QSPI_MspInit() function</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">In stm32f4xx_it.c file, QSPI_IRQHandler() function: add a call to HAL_QSPI_IRQHandler() function</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add and customize the Error Callback API: HAL_QSPI_ErrorCallback()</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add the management of non-blocking transfer abort service: HAL_QSPI_Abort_IT(). In this case the user must:</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add new callback HAL_QSPI_AbortCpltCallback() to inform user at the end of abort process</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">A new value of State in the HAL_QSPI_StateTypeDef provides the current state during the abort phase</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Polling management update:</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">The Timeout value user must be estimated for the overall process duration: the Timeout measurement is cumulative. </span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Refer to the following examples, which describe the changes:</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">QSPI_ReadWrite_DMA</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">QSPI_MemoryMapped</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">QSPI_ExecuteInPlace<br></span></li></ul></ul></ul><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; widows: 1; word-spacing: 0px; margin-top: 0cm;" type="square"><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Add two new APIs for the QSPI fifo threshold:</span><span style="font-family: 'Times New Roman',serif; font-size: 12pt;" lang="EN-US"><o:p></o:p></span><ul style="margin-bottom: 0in; margin-top: 0cm;" type="circle"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_QSPI_SetFifoThreshold(): configure the FIFO threshold of the QSPI</span><span style="font-family: 'Times New Roman',serif; font-size: 12pt;" lang="EN-US"><o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_QSPI_GetFifoThreshold(): give the current FIFO threshold</span><span style="font-family: 'Times New Roman',serif; font-size: 12pt;" lang="EN-US"><o:p></o:p></span></li></ul></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Fix wrong data size management in HAL_QSPI_Receive_DMA()</span></li></ul></ul><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL ADC</span></b><span style="font-size: 10pt; font-family: Verdana,sans-serif;"><span style="font-style: italic;"></span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;"><span style="font-style: italic;"> </span></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add
- new __HAL_ADC_PATH_INTERNAL_VBAT_DISABLE() macro </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">for STM32F42x and STM32F43x
- devices</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"> to provide the possibility to convert VrefInt channel when both
- VrefInt and Vbat channels are selected.</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">HAL SPDIFRX<span class="Apple-converted-space"> </span></span>update</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Overall driver update for wait on flag management optimization<span class="Apple-converted-space"> </span></span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">HAL WWDG<span class="Apple-converted-space"> </span></span>update </span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Overall rework of the driver for more efficient implementation</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Remove the following APIs:</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_WWDG_Start()</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_WWDG_Start_IT()</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_WWDG_MspDeInit()</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_WWDG_GetState()</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update implementation:</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_WWDG_Init()</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">A new parameter in the Init Structure: EWIMode</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_WWDG_MspInit()</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_WWDG_Refresh() </span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">This function insures the reload of the counter</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">The "counter" parameter has been removed</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_WWDG_IRQHandler()</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_WWDG_EarlyWakeupCallback() is the new prototype of HAL_WWDG_WakeUpCallback()<br></span></li></ul></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Refer to the following example to identify the changes: WWDG_Example</span></li></ul></ul>
-
-<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.4.4 / 22-January-2016</span></h3>
-<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes</span></u></b></p><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;">
-
-<b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL Generic </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">update<o:p></o:p></span><br>
-<span style="font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;"></span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">stm32f4xx_hal_conf_template.h</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Optimize HSE Startup Timeout value from 5000ms to 100 ms</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add new define LSE_STARTUP_TIMEOUT</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add new define USE_SPI_CRC for code cleanup when the CRC calculation is disabled.</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL drivers to support MISRA C 2004 rule 10.6</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal">
-
-<span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Add new template driver to configure timebase </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">using TIMER :</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal">s<span style="font-size: 10pt; font-family: "Verdana",sans-serif;">tm32f4xx_hal_timebase_tim_template.c</span></li></ul></ul></ul>
-
-
-
-
-<ul style="margin-top: 0cm;" type="square"><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal">
-
-<b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL CAN </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">update<o:p></o:p></span>
-</li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_CAN_Transmit() and HAL_CAN_Transmit_IT() functions to </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">unlock process when all Mailboxes are busy</span></li></ul></ul><ul style="margin-top: 0cm;" type="square"><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal">
-
-<b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL DSI </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">update<o:p></o:p></span><br>
-<span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_DSI_SetPHYTimings() functions to use the correct mask</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal">
-
-<b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL UART </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">update<b><o:p></o:p></b></span>
-</li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Several update on HAL UART driver to implement the new UART state machine: </span></li></ul><ul><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add new field in UART_HandleTypeDef structure: </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">"rxState", </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">UART</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"> state information related to Rx Operations</span></li></ul><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Rename "state" field in UART_HandleTypeDef structure by "gstate": </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">UART</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"> state information related to global Handle management and Tx Operations</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update UART process to manage the new UART states.</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US">Update __HAL_UART_RESET_HANDLE_STATE() macro
-to handle the new UART state parameters (gState, rxState)</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US">Update
-UART_BRR_SAMPLING16() and UART_BRR_SAMPLING8() Macros to fix wrong baudrate
-calculation.</span></li></ul></ul>
-
-
-
-
-<ul style="margin-top: 0cm;" type="square"><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal">
-
-<b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL IRDA </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">update<b><o:p></o:p></b></span>
-</li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Several update on HAL IRDA driver to implement the new UART state machine: </span></li></ul><ul><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add new field in IRDA_HandleTypeDef structure: </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">"rxState", </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">IRDA</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"> state information related to Rx Operations</span></li></ul></ul><ul><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Rename "state" field in UART_HandleTypeDef structure by "gstate": </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">IRDA</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"> state information related to global Handle management and Tx Operations</span></li></ul></ul><ul><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update IRDA process to manage the new UART states.</span></li></ul></ul><ul><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US">Update __HAL_IRDA_RESET_HANDLE_STATE() macro
-to handle the new IRDA state parameters (gState, rxState)</span></li></ul></ul><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Removal of IRDA_TIMEOUT_VALUE define</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update IRDA_BRR() Macro to fix wrong baudrate calculation</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal">
-
-<b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL SMARTCARD </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">update<b><o:p></o:p></b></span>
-</li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Several update on HAL SMARTCARD driver to implement the new UART state machine: </span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add new field in </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">SMARTCARD</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">_HandleTypeDef structure: </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">"rxState", </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">SMARTCARD</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">state information related to Rx Operations</span></li></ul><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Rename "state" field in UART_HandleTypeDef structure by "gstate": </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">SMARTCARD</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">state information related to global Handle management and Tx Operations</span></li></ul><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">SMARTCARD</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"> process to manage the new UART states.</span></li></ul><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US">Update __HAL_</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">SMARTCARD</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US">_RESET_HANDLE_STATE() macro
-to handle the new </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">SMARTCARD</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US"> state parameters (gState, rxState)</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal">
-
-<span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update SMARTCARD_BRR() macro to fix wrong baudrate
-calculation</span></li></ul></ul><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span><ul style="margin-top: 0cm;" type="square"><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal">
-
-<b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL RCC </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Add new default define value for HSI calibration "</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">RCC_HSICALIBRATION_DEFAULT"</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Optimize Internal oscillators and PLL startup timeout </span></li><li><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">Update
-to avoid the disable for HSE/LSE oscillators before setting the new RCC
-HSE/LSE configuration and add the following notes in
-HAL_RCC_OscConfig() API description:</span></li></ul></ul><span style="font-size: 10pt; font-family: "Verdana",sans-serif;"></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;"></span>
-
-
-
-<span style="font-size: 10pt; font-family: "Verdana",sans-serif;"></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;"><span style=""></span><o:p></o:p></span> <span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">
-
- * @note
-Transitions LSE Bypass to
-LSE On and LSE On to LSE Bypass are not<o:p></o:p></span>
-
-<br><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">
-
- *
- supported by this API. User should request a transition to LSE Off<o:p></o:p></span>
-
-<br><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">
-
- *
- first and then LSE On or LSE Bypass.<o:p></o:p></span>
-
-<br><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">
-
- * @note Transition HSE Bypass to HSE On
-and HSE On to HSE Bypass are not<o:p></o:p></span>
-
-<br><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">
-
- *
- supported by this API. User should request a transition to HSE Off<o:p></o:p></span>
-
-
-<br><span style="font-size: 10pt; font-family: "Verdana",sans-serif;">
-
-* first and then HSE On or HSE
-Bypass.<o:p></o:p></span>
-
-
-
-<ul><ul><li><span style="font-size: 10pt; font-family: "Verdana",sans-serif;"><span style=""></span>Optimize the HAL_RCC_ClockConfig() API implementation.</span></li></ul></ul><span style="font-size: 10pt; font-family: "Verdana",sans-serif;"></span><ul><li><span style="font-family: "Verdana",sans-serif;"></span><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL DMA2D </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update
-HAL_DMA2D_Abort() Function to end current DMA2D transfer properly</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update
-HAL_DMA2D_PollForTransfer() function to add poll for background CLUT loading
-(layer 0 and layer 1).</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update
-HAL_DMA2D_PollForTransfer() to set the corresponding ErrorCode in case of error
-occurrence</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update HAL_DMA2D_ConfigCLUT()
-function to fix wrong CLUT size and color mode settings</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Removal of useless
-macro __HAL_DMA2D_DISABLE()</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update
-HAL_DMA2D_Suspend() to manage correctly the case where no transfer is on going</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update
-HAL_DMA2D_Resume() to manage correctly the case where no transfer is on
-going</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update
-HAL_DMA2D_Start_IT() to enable all required interrupts before enabling the
-transfer.</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add
-HAL_DMA2D_CLUTLoad_IT() Function to allow loading a CLUT with interruption
-model.</span></li><li><span style="font-size: 10pt; font-family: Symbol;" lang="EN-US"><span style=""><span style="font-family: "Times New Roman"; font-style: normal; font-variant: normal; font-weight: normal; font-size: 7pt; line-height: normal; font-size-adjust: none; font-stretch: normal;"> </span></span></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update
-HAL_DMA2D_IRQHandler() to manage the following cases :</span><span style="font-size: 10pt; font-family: Symbol;" lang="EN-US"><span style=""><span style="font-family: "Times New Roman"; font-style: normal; font-variant: normal; font-weight: normal; font-size: 7pt; line-height: normal; font-size-adjust: none; font-stretch: normal;"><br></span></span></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span></li><ul><li><span style="font-size: 10pt; font-family: "Courier New";" lang="EN-US"><span style=""><span style="font-family: "Times New Roman"; font-style: normal; font-variant: normal; font-weight: normal; font-size: 7pt; line-height: normal; font-size-adjust: none; font-stretch: normal;"></span></span></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">CLUT transfer complete</span></li><li><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">CLUT access error</span></li><li><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Transfer watermark reached</span></li></ul><li><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add new Callback APIs:</span></li><ul><li><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"> HAL_DMA2D_LineEventCallback() to signal a transfer watermark reached event</span></li><li><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"> HAL_DMA2D_CLUTLoadingCpltCallback() to signal a CLUT loading complete
-event <o:p></o:p></span></li></ul></ul></ul><ul><ul><li><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Miscellaneous
-Improvement:</span></li><ul><li><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add "HAL_DMA2D_ERROR_CAE" new define for CLUT Access error management.</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span></li><li><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add </span><span style="font-size: 10pt; font-family: "Courier New";" lang="EN-US"><span style=""><span style="font-family: "Times New Roman"; font-style: normal; font-variant: normal; font-weight: normal; font-size: 7pt; line-height: normal; font-size-adjust: none; font-stretch: normal;"> </span></span></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">assert_param used for parameters check is now done on the top of the
-exported functions : before locking the process using __HAL_LOCK</span></li></ul></ul></ul>
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-HAL_I2C_GetMode()</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update I2C process to manage the new I2C states.</span></li></ul><li><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Fix wrong
-behaviour in single byte transmission </span></li><li><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update I2C_WaitOnFlagUntilTimeout() to manage the NACK feature.</span></li><li><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update I2C
-transmission process to support the case data size equal 0</span></li></ul></ul><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span><ul style="margin-top: 0cm;" type="square"><li>
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-<b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL FMPI2C </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">update</span></li><ul><li><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add support of FMPI2C repeated start feature:</span></li><ul><li><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">With the following new API's<br></span></li></ul><ul><ul><li><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL_FMPI2C_Master_Sequential_Transmit_IT()</span></li><li><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"> HAL_</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">FMP</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">I2C_Master_Sequential_Receive_IT()</span></li><li><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL_</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">FMP</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">I2C_Master_Abort_IT()</span></li><li><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL_</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">FMP</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">I2C_Slave_Sequential_Transmit_IT()</span></li><li><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL_</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">FMP</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">I2C_Slave_Sequential_Receive_IT()</span></li><li><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL_</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">FMP</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">I2C_EnableListen_IT()</span></li><li><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL_</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">FMP</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">I2C_DisableListen_IT()</span></li></ul></ul><ul><li>Add new user callbacks:<span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"><br></span></li></ul><ul><ul><li><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL_</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">FMP</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">I2C_ListenCpltCallback()</span></li></ul><ul><li><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL_</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">FMP</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">I2C_AddrCallback()</span></li></ul></ul><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Several update on HAL I2C driver to implement the new I2C state machine: </span></li><ul><li><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add new API to get the </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">FMP</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">I2C mode:
-HAL_</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">FMP</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">I2C_GetMode()</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">FMP</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">I2C process to manage the new </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">FMP</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">I2C states.</span></li></ul></ul></ul><span style="font-size: 10pt; font-family: "Verdana",sans-serif;"></span><ul style="margin-top: 0cm;" type="square"><li>
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-polling/interrupt mode to reach max frequency:</span></li><ul><li><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Polling mode :</span></li><ul><li><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Replace use of SPI_WaitOnFlagUnitTimeout() funnction by "if" statement to check on RXNE/TXE flage while transferring data.<br></span></li></ul><ul><li><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Use API data pointer instead of SPI handle data pointer.</span></li><li><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Use a Goto implementation instead of "if..else" statements.<br></span></li></ul></ul></ul></ul><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span><ul style="margin-top: 0cm;" type="square"><ul><ul><li>Interrupt mode</li><ul><li><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Minimize access on SPI registers.</span></li><li><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Split the SPI modes into dedicated static functions to minimize </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">checking statements under HAL_IRQHandler():</span></li><ul><li><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">1lines/2lines modes</span></li><li><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">8 bit/ 16 bits data formats</span></li><li><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">CRC calculation enabled/disabled.</span></li></ul><li>
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-Remove waiting loop under ISR when closing the communication.<o:p></o:p><br>
-<span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span></li></ul><li><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">All modes: </span></li><ul><li><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Adding switch USE_SPI_CRC to minimize number of statements when CRC calculation is disabled.</span></li><li><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update Timeout management to check on global process.</span></li><li><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update Error code management in all processes.</span></li></ul></ul><li>Add note to the max frequencies reached in all modes.</li><li>Add note about Master Receive mode restrictions :</li><ul><li>Master Receive mode restriction:<br>
-<span style="" lang="EN-US">
- (#) In Master unidirectional receive-only mode
-(MSTR =1, BIDIMODE=0, RXONLY=0) or <br>
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-mode (MSTR=1, BIDIMODE=1, BIDIOE=0), to ensure that the SPI <br>
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-transfer the following procedure has to be respected:<br>
- (##) HAL_SPI_DeInit()<br>
- (##) HAL_SPI_Init()</span><span style="font-size: 10pt; font-family: "Arial",sans-serif; color: rgb(0, 32, 82);" lang="EN-US"><o:p></o:p></span>
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-properly FullDuplex mode without any risk of missing data.<o:p></o:p></span>
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-<span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update the FSMC_NORSRAM_Init() function to use
-BurstAccessMode field properly</span></li></ul></ul><br><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.4.4 / 11-December-2015</span></h3><span style="font-size: 10pt; font-family: Arial; color: white;"></span><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
-Changes</span></u></b><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL Generic </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt; font-weight: normal;">update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL
-weak empty callbacks to prevent unused argument compilation warnings with some
-compilers by calling the following line:</span>
-</li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">UNUSED(hppp);</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">STM32Fxxx_User_Manual.chm files regenerated for HAL V1.4.3</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL ETH</span> update </span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL_ETH_Init() function to add timeout on the Software reset management</span><br><span style="font-size: 10pt; font-family: Arial; color: white;"></span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.4.2 / 10-November-2015</span></h3>
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- <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b><u><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;">Main Changes</span></u></b><span style="font-size: 12pt; font-family: "Times New Roman","serif";"><o:p></o:p></span></p>
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- <ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">General updates to fix known defects and enhancements implementation</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana,sans-serif;"><span style="font-weight: bold;">One change done on the HAL CRYP requires an update on the application code based on HAL V1.4.1</span></span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL_CRYP_DESECB_Decrypt() API to invert pPlainData and pCypherData parameters</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL generic</span> update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update
-HAL weak empty callbacks to prevent unused argument compilation
-warnings with some compilers by calling the following line:</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">UNUSED(hppp);<br><br></span></li></ul></ul></ul>
-<ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL CORTEX </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Remove duplication for __HAL_CORTEX_SYSTICKCLK_CONFIG() macro</span></li></ul></ul><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL HASH </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Rename HAL_HASH_STATETypeDef to HAL_HASH_StateTypeDef</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Rename HAL_HASH_PhaseTypeDef to HAL_HASH_PhaseTypeDef<br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL RCC </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Add new macros __HAL_RCC_<span style="font-style: italic;">PPP</span>_IS_CLK_ENABLED() to check on Clock enable/disable status</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Update __HAL_RCC_USB_OTG_FS_CLK_DISABLE() macro to remove the disable for the SYSCFG</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Update HAL_RCC_MCOConfig() API to use new defines for the GPIO Speed</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Generic update to improve the PLL VCO min value(100MHz): PLLN, PLLI2S and PLLSAI min value is 50 instead of 192</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL FLASH </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: rgb(2, 3, 2); font-family: Verdana;" class="MsoNormal"><span style="font-size: 11.7px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: 20px; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; display: inline ! important; float: none; background-color: rgb(255, 255, 255);">__HAL_FLASH_INSTRUCTION_CACHE_RESET() macro: update to </span><span style="font-size: 11.7px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: 20px; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; display: inline ! important; float: none; background-color: rgb(255, 255, 255);">reset </span><span style="font-size: 11.7px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: 20px; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; display: inline ! important; float: none; background-color: rgb(255, 255, 255);">ICRST </span><span style="font-size: 11.7px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: 20px; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; display: inline ! important; float: none; background-color: rgb(255, 255, 255);">bit in the ACR register after setting it.</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: rgb(2, 3, 2); font-family: Verdana;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update to support until 15 FLASH wait state (FLASH_LATENCY_15) for STM32F446xx devices </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal">
-<p class="MsoListParagraph"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL CRYP </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></p></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL_CRYP_DESECB_Decrypt() API to fix the inverted pPlainData and pCypherData parameters issue</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL I2S </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL_I2S_Init() API to call __HAL_RCC_I2S_CONFIG() macro when external I2S clock is selected</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL LTDC </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL_LTDC_SetWindowPosition() API to configure Immediate reload </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">register </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">instead of vertical blanking reload register.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL TIM </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL_TIM_ConfigClockSource() API to check only the required parameters</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL NAND </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL_NAND_Read_Page()/HAL_NAND_Write_Page()/HAL_NAND_Read_SpareArea() APIs to manage correctly the NAND Page access</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL CAN </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update to use "=" instead of "|=" to clear flags in the MSR, TSR, RF0R and RF1R registers</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL HCD </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Fix typo in __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() macro implementation</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL PCD </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL_PCD_IRQHandler() API to avoid issue when DMA mode enabled for Status Phase IN stage</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">LL FMC </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update the FMC_NORSRAM_Extended_Timing_Init() API to remove the check on CLKDIvison and DataLatency parameters</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update the </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">FMC_NORSRAM_Init() API to add a check on the PageSize parameter for STM32F42/43xx devices</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">LL FSMC </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update the FSMC_NORSRAM_Extended_Timing_Init() API to remove the check on CLKDIvison and DataLatency parameters</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.4.1 / 09-October-2015</span></h3>
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- <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b><u><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;">Main Changes</span></u></b><span style="font-size: 12pt; font-family: "Times New Roman","serif";"><o:p></o:p></span></p>
-
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- <ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL DSI </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Update TCCR register </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">assigned value</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US"> in HAL_DSI_ConfigHostTimeouts() function</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Update WPCR register </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">assigned value</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">
-in HAL_DSI_Init(), HAL_DSI_SetSlewRateAndDelayTuning(),
-HAL_DSI_SetSlewRateAndDelayTuning(), HAL_DSI_SetLowPowerRXFilter() /
-HAL_DSI_SetSDD(), HAL_DSI_SetLanePinsConfiguration(),
-HAL_DSI_SetPHYTimings(), HAL_DSI_ForceTXStopMode(),
-HAL_DSI_ForceRXLowPower(), HAL_DSI_ForceDataLanesInRX(),
-HAL_DSI_SetPullDown() and HAL_DSI_SetContentionDetectionOff() functions</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Update DSI_HS_PM_ENABLE define value</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Implement
-workaround for the hardware limitation: The time to activate the clock
-between HS transmissions is not calculated correctly<br></span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.4.0 / 14-August-2015</span></h3>
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- <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b><u><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;">Main Changes</span></u></b><span style="font-size: 12pt; font-family: "Times New Roman","serif";"><o:p></o:p></span></p>
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- <ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Add support of<span class="Apple-converted-space"> </span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US"><b>STM32F469xx</b></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;"><span class="Apple-converted-space">, <span style="font-weight: bold;">STM32F479xx</span>, <span style="font-weight: bold;">STM32F410Cx, </span></span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;"><span class="Apple-converted-space"><span style="font-weight: bold;">STM32F410Rx </span>and<span style="font-weight: bold;"> </span></span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;"><span class="Apple-converted-space"><span style="font-weight: bold;">STM32F410Tx</span></span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;"><span class="Apple-converted-space"><span style="font-weight: bold;"> </span> </span>devices</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">General updates to fix known defects and enhancements implementation</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Add new HAL drivers for <span style="font-weight: bold;">DSI </span>and<span style="font-weight: bold;"> LPTIM</span><span style="font-weight: bold;"> </span>peripherals</span></li></ul><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL ADC </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Rename ADC_CLOCKPRESCALER_PCLK_DIV2 define to ADC_CLOCK_SYNC_PCLK_DIV2</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Rename ADC_CLOCKPRESCALER_PCLK_DIV4 define to ADC_CLOCK_SYNC_PCLK_DIV4</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Rename ADC_CLOCKPRESCALER_PCLK_DIV6 define to ADC_CLOCK_SYNC_PCLK_DIV6</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Rename ADC_CLOCKPRESCALER_PCLK_DIV8 define to ADC_CLOCK_SYNC_PCLK_DIV8</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US"> </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US"></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;"></span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL CORTEX </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add specific API for MPU management</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">add MPU_Region_InitTypeDef structure</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">add new function HAL_MPU_ConfigRegion()</span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL DMA </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Overall driver update for code optimization</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">add StreamBaseAddress and StreamIndex new fields in the DMA_HandleTypeDef structure</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">add DMA_Base_Registers private structure</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">add static function DMA_CalcBaseAndBitshift()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update HAL_DMA_Init() function to use the new added static function</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update HAL_DMA_DeInit() function to optimize clear flag operations</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update HAL_DMA_Start_IT() function to optimize interrupts enable</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update HAL_DMA_PollForTransfer() function to optimize check on flags</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update HAL_DMA_IRQHandler() function to optimize interrupt flag management</span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL FLASH </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update HAL_FLASH_Program_IT() function by removing the pending flag clear</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update HAL_FLASH_IRQHandler() function to improve erase operation procedure</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update FLASH_WaitForLastOperation() function by checking on end of operation flag<br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL GPIO </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Rename GPIO_SPEED_LOW define to GPIO_SPEED_FREQ_LOW</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Rename GPIO_SPEED_MEDIUM define to GPIO_SPEED_FREQ_MEDIUM</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Rename GPIO_SPEED_FAST define to GPIO_SPEED_FREQ_HIGH</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Rename GPIO_SPEED_HIGH define to GPIO_SPEED_FREQ_VERY_HIGH</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL I2S </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Move I2S_Clock_Source defines to extension file to properly add the support of STM32F410xx devices</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL LTDC </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">rename HAL_LTDC_LineEvenCallback() function to HAL_LTDC_LineEventCallback()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">add new function HAL_LTDC_SetPitch()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">add
-new functions HAL_LTDC_StructInitFromVideoConfig() and
-HAL_LTDC_StructInitFromAdaptedCommandConfig() applicable only to
-STM32F469xx and STM32F479xx devices<br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL PWR </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">move __HAL_PWR_VOLTAGESCALING_CONFIG() macro to extension file</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">move PWR_WAKEUP_PIN2 define to extension file</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">add PWR_WAKEUP_PIN3 define, applicable only to STM32F10xx devices<br></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">add
-new functions HAL_PWREx_EnableWakeUpPinPolarityRisingEdge() and
-HAL_PWREx_EnableWakeUpPinPolarityFallingEdge(), applicable only to </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">STM32F469xx and STM32F479xx devices</span></li></ul></ul><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL RTC </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Update HAL_RTCEx_SetWakeUpTimer() and HAL_RTCEx_SetWakeUpTimer_IT() functions to properly check on the WUTWF flag</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL TIM </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">add
-new defines TIM_SYSTEMBREAKINPUT_HARDFAULT,
-TIM_SYSTEMBREAKINPUT_PVD and TIM_SYSTEMBREAKINPUT_HARDFAULT_PVD,
-applicable only to STM32F410xx devices</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.3.2 / 26-June-2015</span></h3>
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- <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b><u><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;">Main Changes</span></u></b><span style="font-size: 12pt; font-family: "Times New Roman","serif";"><o:p></o:p></span></p>
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- <ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">General updates to fix known defects and enhancements implementation</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;"><span style="font-weight: bold;">One changes done on the HAL may require an update on the application code based on HAL V1.3.1</span></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">HASH IT process: </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update to call the HAL_HASH_InCpltCallback() at the end of the complete buffer instead of</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"> every each 512 bits</span><span style="font-size: 10pt; font-family: Verdana,sans-serif;"></span></li></ul></ul><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL RCC </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">HAL_RCCEx_PeriphCLKConfig() updates:</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Update
-the LSE check condition after backup domain reset: update to
-check LSE ready flag when LSE oscillator is already enabled
-instead of check on LSE oscillator only when LSE is used as RTC clock
-source</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Use the right macro to check the PLLI2SQ parameters <br></span></li></ul></ul></ul><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL RTC </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">__HAL_RTC_TAMPER_TIMESTAMP_EXTI_GET_FLAG() macro: fix implementation issue</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">__HAL_RTC_ALARM_GET_IT(),
-__HAL_RTC_ALARM_CLEAR_FLAG(), __HAL_RTC_WAKEUPTIMER_CLEAR_FLAG(),
-__HAL_RTC_TIMESTAMP_CLEAR_FLAG() and __HAL_RTC_TAMPER_CLEAR_FLAG()
-macros implementation changed: remove unused cast</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">IS_RTC_TAMPER() macro: update to use literal instead of hardcoded value </span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add new parameter </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">SecondFraction </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">in RTC_TimeTypeDef structure<br></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_RTC_GetTime() API update to support the new parameter SecondFraction <br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL ADC </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Add
-new literal: ADC_INJECTED_SOFTWARE_START to be used as possible value
-for the ExternalTrigInjecConvEdge parameter in the ADC_InitTypeDef
-structure to select the ADC software trigger mode.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL FLASH </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">FLASH_OB_GetRDP() API update to return uint8_t instead of FlagStatus</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"> __HAL_FLASH_GET_LATENCY() new macro </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">add to get the flash latency</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL SPI </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Fix the wrong definition of HAL_SPI_ERROR_FLAG literal</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL I2S </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_I2S_Transmit() API update to check on busy flag only for I2S slave mode</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL CRC </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">__HAL_CRC_SET_IDR() macro implementation change to use WRITE_REG() instead of MODIFY_REG()</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL DMA2D </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_DMA2D_ConfigLayer() API update to use "=" instead of "|=" to erase </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">BGCOLR and</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"> FGCOLR registers before setting the new configuration</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL HASH </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_HASH_<span style="font-weight: bold;">MODE</span>_Start_IT() </span><span style="font-size: 10pt; font-family: Verdana,sans-serif;">(</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">MODE </span>stands for </span><span style="font-size: 10pt; font-family: Verdana,sans-serif;">MD5, SHA1, SHA224 and SHA36) updates:</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Fix processing fail for small input buffers</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update
-to unlock the process and call return HAL_OK at the end of HASH
-processing to avoid incorrectly repeating software</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update to properly manage the HashITCounter</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update to call the HAL_HASH_InCpltCallback() at the end of the complete buffer instead of</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"> every each 512 bits </span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">__HAL_HASH_GET_FLAG() update to check the right register when the DINNE flag is selected</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_HASH_SHA1_Accumulate() updates:</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add a call to the new IS_HASH_SHA1_BUFFER_SIZE() macro to check the size parameter. </span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add the following note in API description</span></li></ul></ul></ul><div style="margin-left: 120px;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"> * @note Input buffer size in bytes must be a multiple of 4 otherwise the digest computation is corrupted.</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></div><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL RTC </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update to define </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">hardware </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US">independent l</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">iterals names</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif; color: black;" lang="EN-US"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">:</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Rename RTC_TAMPERPIN_PC13 by RTC_TAMPERPIN_DEFAULT</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Rename RTC_TAMPERPIN_PA0 by RTC_TAMPERPIN_POS1</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Rename RTC_TAMPERPIN_PI8 by RTC_TAMPERPIN_POS1</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Rename RTC_TIMESTAMPPIN_PC13 by RTC_TIMESTAMPPIN_DEFAULT</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Rename RTC_TIMESTAMPPIN_PA0 by RTC_TIMESTAMPPIN_POS1</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Rename RTC_TIMESTAMPPIN_PI8 by RTC_TIMESTAMPPIN_POS1<br></span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL ETH </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Remove duplicated IS_ETH_DUPLEX_MODE() and IS_ETH_RX_MODE() macros</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Remove illegal space ETH_MAC_READCONTROLLER_FLUSHING macro</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update ETH_MAC_READCONTROLLER_XXX defined values (XXX can be IDLE, READING_DATA and READING_STATUS)<br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL PCD </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_PCD_IRQHandler API: fix the bad Configuration of Turnaround Time</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL HCD </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update to use local variable in USB Host channel re-activation</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">LL FMC </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">FMC_SDRAM_SendCommand() API: remove the following line: return HAL_ERROR;</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">LL USB </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">USB_FlushTxFifo API: update to flush all Tx FIFO</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update to use local variable in USB Host channel re-activation</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.3.1 / 25-Mars-2015</span></h3>
-
- <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b><u><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;">Main Changes</span></u></b><span style="font-size: 12pt; font-family: "Times New Roman","serif";"><o:p></o:p></span></p>
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- <ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL PWR </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Fix compilation issue with STM32F417xx product: update <span style="font-weight: bold;">STM32F17xx</span> by </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">STM32F417xx</span></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL SPI </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Remove unused variable to avoid warning with TrueSTUDIO </span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL I2C </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">I2C Polling/IT/DMA processes: move the wait loop on busy flag at the top of the processes, </span><span style="font-size: 10pt; font-family: Verdana,sans-serif;">to ensure that software not perform any write access to I2C_CR1 register before hardware clearing STOP bit </span><span style="font-size: 10pt; font-family: Verdana,sans-serif;">and to avoid also the waiting loop on BUSY flag under I2C/DMA ISR.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Update busy flag Timeout value</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">I2C Master Receive Processes update to disable ACK before generate the STOP </span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL DAC </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Fix
-V1.3.0 regression issue with DAC software trigger configuration</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.3.0 / 09-Mars-2015</span></h3>
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- <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b><u><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;">Main Changes</span></u></b><span style="font-size: 12pt; font-family: "Times New Roman","serif";"><o:p></o:p></span></p>
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- <ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Add support of<span class="Apple-converted-space"> </span></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US"><b>STM32F446xx</b></span><span style="font-size: 10pt; font-family: Verdana,sans-serif;"><span class="Apple-converted-space"> </span>devices</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">General updates to fix known defects and enhancements implementation</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Add new HAL drivers for <span style="font-weight: bold;">CEC, QSPI, FMPI2C </span>and <span style="font-weight: bold;">SPDIFRX </span>peripherals</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;"><span style="font-weight: bold;">Two changes done on the HAL requires an update on the application code based on HAL V1.2.0</span></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">Overall <span style="font-weight: bold;">SAI</span> <span style="font-weight: bold;">driver rework</span> to have exhaustive support of the peripheral features: details are provided in <span style="font-weight: bold;">HAL SAI </span>update section below --> <span style="font-weight: bold;">Compatibility with previous version is impacted</span></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;"><span style="font-style: italic;">CRYP</span><span style="font-style: italic;"> </span>driver updated to support multi instance,so user must ensure that the new parameter </span><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Instance</span><span style="font-size: 10pt; font-family: Verdana,sans-serif;"> is initalized in his application(CRYPHandle.Instance = CRYP) </span></li></ul></ul><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL Generic </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">stm32f4xx_hal_def.h</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Remove NULL definition </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">and add include for stdio.h</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">stm32_hal_legacy.h</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update method to manage deference in </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">alias</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"> implementation between all STM32 families</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">stm32f4xx_hal_ppp.c</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_PPP_Init(): update to force the HAL_PPP_STATE_RESET before calling the <span style="font-style: italic;">HAL_PPP_MspInit()</span><br></span></li></ul></ul></ul><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL RCC </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add new function HAL_RCCEx_GetPeriphCLKFreq()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Move RCC_PLLInitTypeDef structure to extension file and add the new PLLR field specific to STM32F446xx devices</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Move
-the following functions to extension file and add a __weak attribute in generic
-driver : this update is related to new system clock source (<span style="font-style: italic;">PLL/PLLR</span>) added and only available for
-STM32F44xx <span></span>devices <o:p></o:p></span></li><ul><li style="font-style: italic; margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">HAL_RCC_OscConfig()<o:p></o:p></span></li></ul><ul><li style="font-style: italic; margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">HAL_RCC_GetSysClockFreq()<o:p></o:p></span></li></ul><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US"><span style="font-style: italic;">HAL_RCC_GetOscConfig()</span></span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Move the following macro to extension file as they have device dependent implementation</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US"></span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US"><span style="font-style: italic;">__HAL_RCC_PLL_CONFIG()</span>
-<o:p></o:p></span></li></ul><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US"><span style="font-style: italic;">__HAL_RCC_PLLI2S_CONFIG()</span></span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US"><span style="font-style: italic;">__HAL_RCC_I2S_CONFIG()</span></span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Add new
-structure <span style="font-style: italic;">RCC_PLLI2SInitTypeDef</span>
-containing new <span style="font-style: italic;">PLLI2S</span> division factors
-used only w/ STM32F446xx devices<o:p></o:p></span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Add new
-structure <span style="font-style: italic;">RCC_PLLSAIInitTypeDef</span>
-containing new <span style="font-style: italic;">PLLSAI</span> division factors
-used only w/ STM32F446xx devices<o:p></o:p></span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Add new
-<span style="font-style: italic;">RCC_PeriphCLKInitTypeDef</span> to support the
-peripheral source clock selection for (<span style="font-style: italic;">I2S,
-SAI, SDIO, FMPI2C, CEC, SPDIFRX and CLK48</span>)<o:p></o:p></span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Update
-the <span style="font-style: italic;">HAL_RCCEx_PeriphCLKConfig()</span> and
-<span style="font-style: italic;">HAL_RCCEx_GetPeriphCLKConfig() </span>
-functions to support the new peripherals Clock source
-selection<o:p></o:p></span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Add
-<span style="font-style: italic;">__HAL_RCC_PLL_CONFIG()</span> macro (the
-number of parameter and the implementation depend on the device part
-number)<o:p></o:p></span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Add
-<span style="font-style: italic;">__HAL_RCC_PLLI2S_CONFIG()</span> macro(the number of parameter and the implementation depend on
-device part number)<o:p></o:p></span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Update
-<span style="font-style: italic;">__HAL_RCC_PLLSAI_CONFIG()</span> macro to
-support new PLLSAI factors <span style="font-style: italic;">(PLLSAIM and
-PLLSAIP)</span><o:p></o:p></span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Add new
-macros for clock enable/Disable for the following peripherals <span style="font-style: italic;">(CEC, SPDIFRX, SAI2,
-QUADSPI)</span><o:p></o:p></span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Add the
-following new macros for clock source selection :<o:p></o:p></span></li><ul><li style="font-style: italic; margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">__HAL_RCC_SAI1_CONFIG() /
-__HAL_RCC_GET_SAI1_SOURCE()<o:p></o:p></span></li></ul><ul><li style="font-style: italic; margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">__HAL_RCC_SAI2_CONFIG() /
-__HAL_RCC_GET_SAI2_SOURCE()<o:p></o:p></span></li></ul><ul><li style="font-style: italic; margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">__HAL_RCC_I2S1_CONFIG() /
-__HAL_RCC_GET_I2S1_SOURCE()<o:p></o:p></span></li></ul><ul><li style="font-style: italic; margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">__HAL_RCC_I2S2_CONFIG() /
-__HAL_RCC_GET_I2S2_SOURCE()<o:p></o:p></span></li></ul><ul><li style="font-style: italic; margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">__HAL_RCC_CEC_CONFIG() / __HAL_RCC__GET_CEC_SOURCE()
-<o:p></o:p></span></li></ul><ul><li style="font-style: italic; margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">__HAL_RCC_FMPI2C1_CONFIG() / __HAL_RCC_GET_FMPI2C1_SOURCE()
-<o:p></o:p></span></li></ul><ul><li style="font-style: italic; margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">__HAL_RCC_SDIO_CONFIG() / __HAL_RCC_GET_SDIO_SOURCE()
-<o:p></o:p></span></li></ul><ul><li style="font-style: italic; margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">__HAL_RCC_CLK48_CONFIG() / __HAL_RCC_GET_CLK48_SOURCE()
-<o:p></o:p></span></li></ul><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US"><span style="font-style: italic;">__HAL_RCC_SPDIFRXCLK_CONFIG() /
-__HAL_RCC_GET_SPDIFRX_SOURCE()</span></span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US"><span style="font-family: Verdana;">__HAL_RCC_PPP_CLK_ENABLE(): Implement workaround to cover RCC limitation regarding peripheral enable dela</span>y</span><span style="font-family: 'Helvetica Neue',Helvetica,Arial,sans-serif; font-size: 13.5031px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: 20px; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; display: inline ! important; float: none; background-color: rgb(252, 252, 252); color: rgb(2, 3, 2);"></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_RCC_OscConfig() fix issues: </span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add a check on LSERDY flag when </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">LSE_BYPASS is selected as new state for LSE oscillator.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; font-family: Verdana;"><span style="font-size: 10pt;" lang="EN-US">Add new possible value <span style="font-style: italic;">RCC_PERIPHCLK_PLLI2S </span>to be selected as<span style="font-style: italic;"> PeriphClockSelection </span>parameter
-in the RCC_PeriphCLKInitTypeDef structure to allow the
-possibility to output the PLLI2S on MCO without activating the I2S or
-the SAI.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US"></span><span style="color: rgb(98, 98, 98); font-size: 11.7px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: 20px; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; display: inline ! important; float: none; background-color: rgb(255, 255, 255); font-family: Verdana;"><span style="color: rgb(12, 12, 12);">__HAL_RCC_HSE_CONFIG()</span> </span><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;">macro: add the comment below:</span></span></li></ul></ul><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">
- </span>
- <div style="margin-left: 120px;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-style: italic;"> <span style="font-family: Verdana;">* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro. </span><br style="font-family: Verdana;"><span style="font-family: Verdana;"> * User should request a
-transition to HSE Off first and then HSE On or HSE Bypass.</span></span></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></div><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;"></span></span><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US"></span><span style="color: rgb(98, 98, 98); font-family: helvetica,arial,sans-serif; font-size: 11.7px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: 20px; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; display: inline ! important; float: none; background-color: rgb(255, 255, 255);"><span style="color: rgb(12, 12, 12);">__HAL_RCC_LSE_CONFIG()</span> </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-style: italic;">macro: add the comment below:</span></span></li></ul></ul><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">
- </span>
- <div style="margin-left: 120px;"><span style="font-size: 10pt; font-family: Verdana;"><span style="font-style: italic;"> * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.<br>
-* User should request a
-transition to LSE Off first and then LSE On or LSE Bypass.</span></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></div><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Add the
-following new macros for PLL source and PLLM selection :<o:p></o:p></span></li><ul><li style="font-style: italic; margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">__HAL_RCC_PLL_PLLSOURCE_CONFIG()<o:p></o:p></span></li></ul><ul><li style="font-style: italic; margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">__HAL_RCC_PLL_PLLM_CONFIG()</span></li></ul><li style="font-style: italic; margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Macros rename:</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US"></span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_RCC_OTGHS_FORCE_RESET() by </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_RCC_USB_OTG_HS_FORCE_RESET</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">()</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_RCC_OTGHS_RELEASE_RESET() by </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_RCC_USB_OTG_HS_RELEASE_RESET</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">()</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_RCC_OTGHS_CLK_SLEEP_ENABLE() by </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">()</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_RCC_OTGHS_CLK_SLEEP_DISABLE() by </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">()</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE() by </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">()</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE() by </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">()</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black; font-family: Verdana;" class="MsoNormal"><span style="font-size: 10pt;">Add __HAL_RCC_SYSCLK_CONFIG() </span><span style="font-size: 10pt;">new macro</span><span style="font-size: 10pt;"> to configure the system clock source (</span><span style="font-size: 10pt;">SYSCLK</span><span style="font-size: 10pt;">)</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_RCC_GET_SYSCLK_SOURCE() updates:</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add new RCC Literals:</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">RCC_SYSCLKSOURCE_STATUS_HSI</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">RCC_SYSCLKSOURCE_STATUS_HSE</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">RCC_SYSCLKSOURCE_STATUS_PLLCLK</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">RCC_SYSCLKSOURCE_STATUS_PLLRCLK</span></li></ul></ul><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"> </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Update macro description to refer to the literals above</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"> </span><span style="color: rgb(71, 71, 71); font-family: helvetica,arial,sans-serif; font-size: 26px; font-style: normal; font-variant: normal; font-weight: bold; letter-spacing: normal; line-height: 20px; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; display: inline ! important; float: none; background-color: rgb(255, 255, 255);"></span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL PWR </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add new define PWR_WAKEUP_PIN2</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add new API to Control/Get </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">VOS bits of CR register</span></li><ul><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_PWR_HAL_PWREx_ControlVoltageScaling()</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_PWREx_GetVoltageRange()</span></li></ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">__HAL_PWR_</span><span style="font-size: 11pt; font-family: "Calibri","sans-serif"; color: black;" lang="EN-US"> VOLTAGESCALING_CONFIG</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">(): Implement workaround to cover VOS limitation delay when PLL is enabled after setting the VOS configuration</span><span style="background: rgb(252, 252, 252) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; font-size: 10pt; font-family: "Helvetica","sans-serif"; color: rgb(2, 3, 2);" lang="EN-US"><span style="text-align: start; float: none; word-spacing: 0px;"> </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL GPIO </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Add the
-new Alternate functions literals related to remap for <span style="font-style: italic; font-weight: bold;">SPI, USART, I2C, SPDIFRX, CEC and
-QSPI</span></span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 11pt; font-family: "Calibri","sans-serif"; color: black;" lang="EN-US"><small><span style="font-family: Verdana;">HAL_GPIO_DeInit():
-Update to check if GPIO Pin x is already used in EXTI mode on
-another GPIO Port before De-Initialize the EXTI register</span></small>s</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL FLASH </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: rgb(2, 3, 2); font-family: Verdana;" class="MsoNormal"><span style="font-size: 11.7px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: 20px; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; display: inline ! important; float: none; background-color: rgb(255, 255, 255);">__HAL_FLASH_INSTRUCTION_CACHE_RESET() macro: update to </span><span style="font-size: 11.7px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: 20px; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; display: inline ! important; float: none; background-color: rgb(255, 255, 255);">reset </span><span style="font-size: 11.7px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: 20px; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; display: inline ! important; float: none; background-color: rgb(255, 255, 255);">ICRST </span><span style="font-size: 11.7px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: 20px; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; display: inline ! important; float: none; background-color: rgb(255, 255, 255);">bit in the ACR register after setting it.</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: rgb(5, 5, 5); font-family: Verdana;" class="MsoNormal"><big><big><span style="font-size: 11.7px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: 20px; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; display: inline ! important; float: none; background-color: rgb(255, 255, 255); color: rgb(2, 3, 2);">__HAL_FLASH_DATA_CACHE_RESET() macro: update to reset DCRST bit in the ACR register after setting it.</span></big></big></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL ADC </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Add new literal: ADC_SOFTWARE_START to be used as possible value for the <span style="font-style: italic;">ExternalTrigConv</span> parameter in the ADC_InitTypeDef structure to select the ADC software trigger mode.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">IS_ADC_CHANNEL() macro update to don't assert stop the <span style="font-style: italic;">ADC_CHANNEL_TEMPSENSOR</span> value</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 11pt; font-family: "Calibri","sans-serif"; color: black;" lang="EN-US">HAL_ADC_PollForConversion():
-update to manage particular case when ADC configured in DMA mode and
-ADC sequencer with several ranks and polling for end of each conversion</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 11pt; font-family: "Calibri","sans-serif"; color: black;" lang="EN-US">HAL_ADC_Start()/</span><span style="font-size: 11pt; font-family: "Calibri","sans-serif"; color: black;" lang="EN-US">HAL_ADC_Start_IT() /</span><span style="font-size: 11pt; font-family: "Calibri","sans-serif"; color: black;" lang="EN-US">HAL_ADC_Start_DMA() update:</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 11pt; font-family: "Calibri","sans-serif"; color: black;" lang="EN-US">unlock the process before starting the ADC software conversion.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 11pt; font-family: "Calibri","sans-serif"; color: black;" lang="EN-US">Optimize the ADC stabilization delays</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 11pt; font-family: "Calibri","sans-serif"; color: black;" lang="EN-US">__HAL_ADC_GET_IT_SOURCE() update macro implementation</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 11pt; font-family: "Calibri","sans-serif"; color: black;" lang="EN-US">Add more details in 'How to use this driver' section</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL DAC </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal">
-
-<p class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Add new macro to check if the specified DAC interrupt source is enabled or disabled<o:p></o:p></span></p>
-</li><ul><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">__HAL_DAC_GET_IT_SOURCE()</span></li></ul><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">HAL_DACEx_TriangleWaveGeneration() update to use DAC CR bit mask definition</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">HAL_DACEx_NoiseWaveGeneration() update to use DAC CR bit mask definition</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL CAN </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">CanTxMsgTypeDef structure: update </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">to use<span style="font-weight: bold;"> </span>uint8_t Data[8] instead of uint32_t Data[8]</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">CanRxMsgTypeDef structure: update </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">to use<span style="font-weight: bold;"> </span>uint8_t Data[8]<span style="font-weight: bold;"> </span>instead of uint32_t Data[8]</span></li></ul></ul><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL RTC </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Update to use CMSIS mask definition instead of hardcoded values (</span><span style="font-family: helvetica,arial,sans-serif; font-size: 11.7px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: 20px; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; display: inline ! important; float: none; background-color: rgb(255, 255, 255); color: rgb(7, 7, 7);">EXTI_IMR_IM17, EXTI_IMR_IM19..</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">)</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL LTDC </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">LTDC_SetConfig() update to allow the drawing of partial bitmap in active layer.</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US"></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL USART </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">HAL_USART_Init() fix USART baud rate configuration issue: USART baud rate is twice Higher than expected</span><span style="color: rgb(98, 98, 98); font-family: helvetica,arial,sans-serif; font-size: 11.7px; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: 20px; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; display: inline ! important; float: none; background-color: rgb(255, 255, 255);"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US"></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL SMARTCARD </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">HAL_SMARTCARD_Transmit_IT() update to force the disable for the ERR interrupt to avoid the OVR interrupt</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">HAL_SMARTCARD_IRQHandler() update check condition </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">for transmission end </span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Clean up: remove the following literals that aren't used in smartcard mode</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 11pt; font-family: "Calibri","sans-serif"; color: black;" lang="EN-US">SMARTCARD_PARITY_NONE</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 11pt; font-family: "Calibri","sans-serif"; color: black;" lang="EN-US">SMARTCARD_WORDLENGTH_8B</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 11pt; font-family: "Calibri","sans-serif"; color: black;" lang="EN-US">SMARTCARD_STOPBITS_1</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 11pt; font-family: "Calibri","sans-serif"; color: black;" lang="EN-US">SMARTCADR_STOPBITS_2<br></span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL SPI </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_SPI_Transmit_DMA()/HAL_SPI_Receive_DMA()/</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_SPI_TarnsmitReceive_DMA()</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"> update to unlock the process before enabling the SPI peripheral</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 11pt; font-family: "Calibri","sans-serif";" lang="EN-US">HAL_SPI_Transmit_DMA() update to manage correctly the DMA RX stream in SPI Full duplex mode</span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Section SPI_Exported_Functions_Group2 update to </span><span style="font-family: Verdana; color: black; font-size: 10pt;">remove duplication in *.chm UM</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL CRYP </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update to manage multi instance:</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add new parameter Instance in the CRYP_HandleTypeDef Handle structure.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add new parameter in all HAL CRYP macros</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">example: __HAL_CRYP_ENABLE() updated by __HAL_CRYP_ENABLE(__HANDLE__)<br></span></li></ul></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL DCMI </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Add an
-extension driver stm32f4xx_hal_dcmi_ex.c/h to manage the support of new Black and White feature</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US"></span><span style="font-family: 'Times New Roman','serif'; font-size: 12pt;" lang="EN-US"><o:p></o:p></span>
-</li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Add <span style="font-style: italic;"> __weak</span> attribute for <span style="font-style: italic;">HAL_DCMI_Init()</span> function and add a new
-implementation in the extension driver to manage the black and white configuration
-only available in the STM32F446xx devices.</span><span style="font-family: 'Times New Roman','serif'; font-size: 12pt;" lang="EN-US"><o:p></o:p></span>
-</li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">Move
-DCMI_InitTypeDef structure to extension driver and add the
-following new fields related to black and white feature:
-ByteSelectMode, ByteSelectStart, LineSelectMode and </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">LineSelectStart</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL PCD </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add the support of LPM feature</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">add PCD_LPM_StateTypeDef enum</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update PCD_HandleTypeDef structure to support the LPM feature</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">add
-new functions HAL_PCDEx_ActivateLPM(), HAL_PCDEx_DeActivateLPM() and
-HAL_PCDEx_LPM_Callback() in the stm32f4xx_hal_pcd_ex.h/.c files</span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL TIM </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"> TIM_TIM11_SPDIFRX define</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL SAI </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add
-stm32f4xx_hal_sai_ex.h/.c files for the SAI_BlockSynchroConfig() and the
-SAI_GetInputClock() management</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add new defines
-HAL_SAI_ERROR_AFSDET, HAL_SAI_ERROR_LFSDET, HAL_SAI_ERROR_CNREADY,
-HAL_SAI_ERROR_WCKCFG, HAL_SAI_ERROR_TIMEOUT in the SAI_Error_Code group</span>
-</li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add new defines
-SAI_SYNCEXT_DISABLE, SAI_SYNCEXT_IN_ENABLE, SAI_SYNCEXT_OUTBLOCKA_ENABLE,
-SAI_SYNCEXT_OUTBLOCKB_ENABLE for the SAI External synchronization </span>
-</li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add new defines
-SAI_I2S_STANDARD, SAI_I2S_MSBJUSTIFIED, SAI_I2S_LSBJUSTIFIED, SAI_PCM_LONG and
-SAI_PCM_SHORT for the SAI Supported protocol</span>
-</li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add new defines
-SAI_PROTOCOL_DATASIZE_16BIT, SAI_PROTOCOL_DATASIZE_16BITEXTENDED,
-SAI_PROTOCOL_DATASIZE_24BIT and SAI_PROTOCOL_DATASIZE_32BIT for SAI protocol
-data size<br></span>
-</li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add SAI Callback
-prototype definition</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">SAI_InitTypeDef structure by adding new fields: SynchroExt, Mckdiv, MonoStereoMode, CompandingMode, TriState</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update SAI_HandleTypeDef structure:</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">remove
-uint16_t *pTxBuffPtr, *pRxBuffPtr, TxXferSize, RxXferSize, TxXferCount
-and RxXferCount and replace them respectively by uint8_t *pBuffPtr,
-uint16_t XferSize and uint16_t XferCount</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">add mutecallback field</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">add struct __SAI_HandleTypeDef *hsai field</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Remove SAI_CLKSOURCE_PLLR and SAI_CLOCK_PLLSRC defines</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add SAI_CLKSOURCE_NA define</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add SAI_AUDIO_FREQUENCY_MCKDIV define</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add SAI_SPDIF_PROTOCOL define</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add SAI_SYNCHRONOUS_EXT define</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add
-new functions HAL_SAI_InitProtocol(), HAL_SAI_Abort(),
-HAL_SAI_EnableTxMuteMode(), HAL_SAI_DisableTxMuteMode(),
-HAL_SAI_EnableRxMuteMode(), HAL_SAI_DisableRxMuteMode()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update
-HAL_SAI_Transmit(), HAL_SAI_Receive(), HAL_SAI_Transmit_IT(),
-HAL_SAI_Receive_IT(), HAL_SAI_Transmit_DMA(), HAL_SAI_Receive_DMA()
-functions to use<span style="font-weight: bold;"> uint8_t *pData </span>instead of <span style="font-weight: bold;">uint16_t *pData --> This update is mainly impacting the compatibility with previous driver version.</span></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL I2S </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Split </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">the
-following functions between Generic and Extended API based on full
-duplex management and add the attribute __weak in the Generic API</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">HAL_</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">I2S_Init(), HAL_I2S_DMAPause(), </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">HAL_I2S_DMAStop(), </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">HAL_I2S_DMAResume(), </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US">HAL_I2S_IRQHandle()</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;" lang="EN-US"> <o:p></o:p></span></li></ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Move the following static functions from generic to extension driver</span></li><ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"> I2S_DMARxCplt() and I2S_DMATxCplt()</span></li></ul><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Remove static attribute from I2S_Transmit_IT() and I2S_Receive_IT() functions</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Move I2SxEXT() macro to extension file</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add I2S_CLOCK_PLLR and </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">I2S_CLOCK_PLLSRC defines for I2S clock source</span></li><li style="margin: 4.5pt 0in; font-family: 'Times New Roman',serif; color: black; font-size: 12pt;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add new function I2S_GetInputClock()<br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL LL FMC </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add WriteFifo and PageSize fields in the FMC_NORSRAM_InitTypeDef structure</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add
-FMC_PAGE_SIZE_NONE, FMC_PAGE_SIZE_128, FMC_PAGE_SIZE_256,
-FMC_PAGE_SIZE_1024, FMC_WRITE_FIFO_DISABLE, FMC_WRITE_FIFO_ENABLE
-defines</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update FMC_NORSRAM_Init(), FMC_NORSRAM_DeInit() and FMC_NORSRAM_Extended_Timing_Init() functions</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL LL USB </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update USB_OTG_CfgTypeDef structure to support LPM, </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">lpm_enable </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">field added</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update USB_HostInit() and USB_DevInit() functions to support the VBUS Sensing B activation</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 202px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.2.0 / 26-December-2014</span></h3>
-
-
-
- <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b><u><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;">Main Changes</span></u></b><span style="font-size: 12pt; font-family: "Times New Roman","serif";"><o:p></o:p></span></p>
-
-
-
-
-
-
-
-
- <ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;"><span style="font-weight: bold;">Maintenance release to fix known defects and enhancements implementation</span><br>
-</span></li></ul>
-
-
- <ul style="margin-top: 0cm; list-style-type: square;"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"><span style="font-weight: bold;">Macros and literals renaming to ensure compatibles
- across STM32 series</span>, backward compatibility maintained thanks to new added file </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"><i>stm32_hal_legacy.h </i></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">under /Inc/<i>Legacy</i></span><b><u><span style="font-family: Verdana; color: black; font-size: 10pt;"></span></u></b></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana; color: black; font-size: 10pt;">Add *.chm UM for all drivers, a UM is provided for each superset RPN</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana; font-size: 10pt; font-weight: normal;">Update
-drivers to be C++ compliant</span>
-</li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana; font-size: 10pt; font-weight: normal;">Several
-update on source code formatting, for better UM generation (i.e. Doxygen tags
-updated)</span></li>
- <li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: Verdana,sans-serif;"><span style="font-weight: bold;">Two changes done on the HAL requires an update on the application code based on HAL V1.1.0</span><br>
- </span></li>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;"><span style="font-style: italic;">LSI_VALUE</span> constant has been corrected in </span><span style="font-size: 10pt; font-family: Verdana,sans-serif;">stm32f4xx_hal_conf.h file, its value changed </span><span style="font-size: 10pt; font-family: Verdana,sans-serif;">from 40 KHz to 32 KHz</span><span style="font-size: 10pt; font-family: Verdana,sans-serif;"></span></li>
- </ul>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;"><span style="font-style: italic;">UART</span>, <span style="font-style: italic;">USART</span>, <span style="font-style: italic;">IRDA</span> and <span style="font-style: italic;">SMARTCARD </span>(referenced as <span style="font-style: italic;">PPP</span> here below)<span style="font-style: italic;"> </span>drivers: in DMA transmit process, the code has been updated to avoid waiting on TC flag under DMA ISR, <span style="font-style: italic;">PPP</span> TC interrupt is used instead. Below the update to be done on user application:</span></li>
- </ul>
- <ul>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Configure and enable the USART IRQ in HAL_PPP_MspInit() function<br>
-</span></li>
- </ul>
- </ul>
- <ul>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">In </span><span style="font-size: 10pt; font-family: Verdana,sans-serif;">stm32f4xx_it.c file, </span><span style="font-size: 10pt; font-family: Verdana,sans-serif;">PPP_IRQHandler() function: </span><span style="font-size: 10pt; font-family: Verdana,sans-serif;">add a call to HAL_PPP_IRQHandler() function</span></li>
- </ul>
- </ul>
-</ul><ul style="margin-top: 0cm; list-style-type: square;"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL generic</span> update</span></li></ul>
-<ul style="margin-top: 0cm; list-style-type: square;"><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">stm32f4xx_hal_def.h</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update NULL definition </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">to
-fix C++ compilation issue</span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add UNUSED() macro</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;">
-
-<p class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Add a new define __NOINLINE to be used for the no inline
-code independent from tool chain<o:p></o:p></span></p>
-</li></ul></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">stm32f4xx_hal_conf_template.h</span></li></ul><ul style="color: black;"><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-style: italic;">LSI_VALUE</span> constant has been corrected</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">, its value changed </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">from 40 KHz to 32
-KHz</span></li></ul></ul></ul><ul style="margin-top: 0cm; list-style-type: square;"><ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update all macros and literals naming to be uper case</span></li>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">ErrorCode
-parameter in </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">PPP_HandleTypeDef structure updated </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">to uint32_t instead of </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">enum <span style="font-style: italic;">HAL_PPP_ErrorTypeDef</span></span></li>
-<li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Remove the unused FLAG and IT assert macros<br>
-</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL ADC </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul style="color: black;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;">
-
-<p class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Fix temperature sensor channel configuration issue for STM32F427/437xx and STM32F429/439xx devices</span></p></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL DAC </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;">
-
-<p class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL_DAC_ConfigChannel():
-update the access to the DAC peripheral registers via the hdac handle instance</span></p></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL_DAC_IRQHandler(): update to check on both DAC_FLAG_DMAUDR1 and </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">DAC_FLAG_DMAUDR</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">2<span style="color: red;"></span></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL_DACEx_NoiseWaveGenerate(): update to reset DAC CR register before setting the new DAC configuration</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL_DACEx_TriangleWaveGenerate()</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">: update to reset DAC CR register before setting the new DAC configuration</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL CAN </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;">
-
-<p class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"><span style="color: black;">Unlock the CAN process when communication error
-occurred</span><o:p></o:p></span></p>
-</li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL CORTEX </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add new macro <span style="font-style: italic;">IS_NVIC_DEVICE_IRQ()</span> to check on negative values of IRQn </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">parameter</span></li></ul></ul><ul style="list-style-type: square; margin-top: 0cm;"><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal">
-<p class="MsoListParagraph"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL CRYP </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></p></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_CRYP_DESECB_Decrypt_DMA(): fix the inverted pPlainData and pCypherData parameters issue</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">CRYPEx_GCMCCM_SetInitVector(): remove the </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">IVSize parameter as the key length 192bits and 256bits are not supported by this version</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">restriction</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"> for the CCM Encrypt/Decrypt API's that<span style="color: red;"> <span style="color: black;">only DataType equal to 8bits is supported</span><br>
- </span></span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_CRYPEx_AESGCM_Finish():</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">restriction</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"> that </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">the
-implementation is limited to 32bits inputs data length (Plain/Cyphertext, Header) compared with GCM stadards
-specifications (800-38D)</span></li></ul><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update Size parameter on 32bits instead of 16bits</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Fix issue with 16-bit Data Type: update to use intrinsic __ROR() instead of __REV16()</span></li></ul></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal">
-<p class="MsoListParagraph"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL DCMI </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></p></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal">
-
-<p class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL_DCMI_ConfigCROP(): Invert
-assert macros to check <span style="color: black;">Y0</span> and Ysize parameters</span></p></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal">
-<p class="MsoListParagraph"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL DMA </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></p></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal">
-
-<p class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL_DMA_Init(): </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update to clear the DBM bit in the SxCR register before setting the new configuration</span></p></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">DMA_SetConfig(): add </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">to clear the DBM bit in the SxCR register</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal">
-<p class="MsoListParagraph"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL FLASH </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></p></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Add "HAL_" prefix in the defined values for the FLASH error code</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Example: <span style="font-style: italic;">FLASH_ERROR_PGP</span> renamed by <span style="font-style: italic;"><span style="font-weight: bold;">HAL_</span>FLASH_ERROR_PGP</span></span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Clear the Flash ErrorCode in the FLASH_WaitForLastOperation() function</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Update FLASH_SetErrorCode() function to use "|=" operant to update the Flash ErrorCode parameter in the FLASH handle</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"><span style="font-style: italic;">IS_FLASH_ADDRESS()</span>: Update the macro check using '<=' </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">condition </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">instead of '<'</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"><span style="font-style: italic;">IS_OPTIONBYTE()</span></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">: Update the macro check using '<=' </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">condition </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">instead of '<'</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"><span style="font-style: italic;"></span><br></span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">A<span style="color: black;">dd "FLASH_" prefix in the defined values of FLASH Type Program parameter<br>
- </span></span></li><ul style="color: black;"><li style="margin-top: 4.5pt; margin-bottom: 4.5pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Example: <span style="font-style: italic;">TYPEPROGRAM_BYTE</span> renamed by <span style="font-style: italic;"><span style="font-weight: bold;">FLASH_</span>TYPEPROGRAM_BYTE</span></span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Add "FLASH_" prefix in the defined values </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"><span style="color: black;">of </span></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">FLASH Type Erase</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"><span style="color: black;"> parameter</span></span></li><ul style="color: black;"><li style="margin-top: 4.5pt; margin-bottom: 4.5pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Example: <span style="font-style: italic;">TYPEERASE_SECTORS</span> renamed by <span style="font-style: italic;"><span style="font-weight: bold;">FLASH_</span>TYPEERASE_SECTORS</span></span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Add "FLASH_" prefix in the defined values </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"><span style="color: black;">of </span></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"> FLASH Voltage Range </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"><span style="color: black;">parameter</span></span></li><ul style="color: black;"><li style="margin-top: 4.5pt; margin-bottom: 4.5pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Example: <span style="font-style: italic;">VOLTAGE_RANGE_1</span> renamed by <span style="font-style: italic;"><span style="font-weight: bold;">FLASH_</span>VOLTAGE_RANGE_1</span></span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Add "OB_" prefix in the defined values</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"> </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"><span style="color: black;">of </span></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">FLASH WRP State </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"><span style="color: black;">parameter</span></span></li><ul style="color: black;"><li style="margin-top: 4.5pt; margin-bottom: 4.5pt;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Example: <span style="font-style: italic;">WRPSTATE_ENABLE</span> renamed by <span style="font-style: italic;"><span style="font-weight: bold;">OB_</span>WRPSTATE_ENABLE</span></span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Add "OB_" prefix in the defined values</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"> </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"><span style="color: black;">of </span></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">the FLASH PCROP State </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"><span style="color: black;">parameter</span></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"><span style="font-style: italic;"></span></span></li><ul style="color: black;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-style: italic;">PCROPSTATE_DISABLE</span><span style=""> updated </span>by <span style="font-style: italic;"><span style="font-weight: bold;">OB_</span>PCROP<span style="font-weight: bold;">_</span>STATE_DISABLE</span></span></li></ul><ul style="color: black;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; font-style: italic;">PCROPSTATE_ENABLE</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style=""> updated </span>by <span style="font-style: italic;"><span style="font-weight: bold;">OB_</span>PCROP<span style="font-weight: bold;">_</span>STATE_ENABLE</span></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-style: italic;">Change "OBEX" prefix by </span></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-style: italic;">"OPTIONBYTE" prefix in these defines:</span></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-style: italic;">OBEX_PCROP by OPTIONBYTE_PCROP </span></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-style: italic;">OBEX_BOOTCONFIG by OPTIONBYTE_BOOTCONFIG</span></span></li></ul></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal">
-<p class="MsoListParagraph"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL ETH </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></p></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Fix macros naming typo</span></li></ul></ul>
-
-<ul style="margin-top: 0cm;" type="disc"><ul><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Update __HAL_ETH_EXTI_SET_RISING_E<span style="font-weight: bold;">GD</span>E_TRIGGER() by
- __HAL_ETH_EXTI_SET_RISING_E<span style="font-weight: bold;">DG</span>E_TRIGGER()<o:p></o:p></span></li></ul></ul><ul><ul><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Update __HAL_ETH_EXTI_SET_FALLING_E<span style="font-weight: bold;">GD</span>E_TRIGGER() by __HAL_ETH_EXTI_SET_FALLING_E<span style="font-weight: bold;">DG</span>E_TRIGGER()
- <o:p></o:p></span></li></ul></ul></ul>
-<ul style="margin-top: 0cm; list-style-type: square;"><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal">
-<p class="MsoListParagraph"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL PWR </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></p>
-<ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add new API to
-manage </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">SLEEPONEXIT and
-SEVONPEND bits of SCR register</span></li><ul><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_PWR_DisableSleepOnExit()</span>
-</li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_PWR_EnableSleepOnExit()</span>
-</li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_PWR_EnableSEVOnPend()</span>
-</li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_PWR_DisableSEVOnPend()</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_PWR_EnterSTOPMode()</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Update to clear the CORTEX SLEEPDEEP bit of SCR register before entering in sleep mode</span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Update
-usage of __WFE() in low power entry function: if there is a pending
-event, calling __WFE() will not enter the CortexM4 core to sleep mode.
-The solution is to made the call below; the first __WFE() is always
-ignored and clears the event if one was already pending, the second is
-always applied<br>
- </span></li></ul></ul></li></ul>
- <div style="margin-left: 120px;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__SEV()</span><br>
- <span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__WFE()</span><br>
- <span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__WFE()</span></div><ul style="margin-top: 0cm; list-style-type: square;"><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal">
-
-<p class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Add new PVD configuration
-modes<o:p></o:p></span></p>
-</li><ul><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">PWR_PVD_MODE_NORMAL</span>
-</li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">PWR_PVD_MODE_EVENT_RISING </span>
-</li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">PWR_PVD_MODE_EVENT_FALLING</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">PWR_PVD_MODE_EVENT_RISING_FALLING<br></span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal">
-
-<p class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Add new macros to manage PVD
-Trigger<o:p></o:p></span></p>
-</li><ul><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">__HAL_PWR_PVD_EXTI_ENABLE_RISING_EDGE()</span>
-</li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">__HAL_PWR_PVD_EXTI_DISABLE_RISING_EDGE(</span>
-</li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">__HAL_PWR_PVD_EXTI_ENABLE_FALLING_EDGE()</span>
-</li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">__HAL_PWR_PVD_EXTI_DISABLE_FALLING_EDGE()</span></li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">__HAL_PWR_PVD_EXTI_ENABLE_RISING_FALLING_EDGE()</span>
-</li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">__HAL_PWR_PVD_EXTI_DISABLE_RISING_FALLING_EDGE()</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal">
-
-<p class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">PVD macros:<o:p></o:p></span></p>
-</li><ul><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Remove the __EXTILINE__ parameter</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Update to use prefix
- "__HAL_PWR_PVD_" instead of prefix "__HAL_PVD"</span></li></ul></ul></ul>
-<ul style="margin-top: 0cm; list-style-type: square;"><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Rename HAL_PWR_PVDConfig() by </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_PWR_ConfigPVD()</span></li>
- <li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Rename HAL_PWREx_ActivateOverDrive() by HAL_PWREx_EnableOverDrive() </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></li>
-<li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span class="MsoNormal"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Rename HAL_PWREx_DeactivateOverDrive() by HAL_PWREx_DisableOverDrive() </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL GPIO </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;">
-
-<p class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"><span style="font-style: italic;">HAL_GPIO_Init()/</span></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"><span style="font-style: italic;">HAL_GPIO_DeInit()</span></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"><span style="font-style: italic;">:</span> add a call to the CMSIS </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">assert macro to check GPIO instance: IS_GPIO_ALL_INSTANCE() </span></p></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"><span style="font-style: italic;">HAL_GPIO_WritePin():</span> update to write in BSRR register</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Rename <span style="font-style: italic;">GPIO_GET_SOURCE() </span>by<span style="font-style: italic;"> </span></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"><span style="font-style: italic;">GET_GPIO_INDEX() </span>and move this later</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"> to file stm32f4xx_hal_gpio_ex.h</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Add new define for alternate function<span style="font-style: italic;"> GPIO_AF5_SPI3</span> for STM32F429xx/439xx and </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">STM32F427xx/437xx devices</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL HASH </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"><span style="font-style: italic;">HAL_HASH_MD5_Start_IT(): </span>fix input address management issue<br></span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL RCC</span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;"> </span>update<o:p></o:p></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Rename the following Macros</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__PPP_CLK_ENABLE()<span style=""> </span>by __HAL_RCC_PPP_CLK_ENABLE()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">PPP_CLK_DISABLE</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">()<span style=""> </span>by __HAL_RCC_PPP_CLK_DISABLE()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__PPP_FORCE_RESET()<span style=""> </span>by __HAL_RCC_PPP_FORCE_RESET()</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__PPP_RELEASE_RESET()<span style=""> </span>by __HAL_RCC_PPP_RELEASE_RESET()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__PPP_CLK_SLEEP_ENABLE() by </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_RCC_PPP_CLK_SLEEP_ENABLE()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__PPP_CLK_SLEEP_DISABLE() by </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_RCC_PPP_CLK_SLEEP_DISABLE()</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">IS_RCC_PLLSAIN_VALUE() macro: update the check condition<br>
-</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add description of RCC known Limitations</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Rename HAL_RCC_C<span style="font-weight: bold;">C</span>SCallback() by HAL_RCC_C<span style="font-weight: bold;">S</span>SCallback()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_RCC_OscConfig() fix issues: </span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Remove the disable of HSE oscillator </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">when HSE_BYPASS is </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">used as system clock source or as PPL clock source<br>
-</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add a check on HSERDY flag when </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HSE_BYPASS is selected as new state for HSE oscillator.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Rename __HAL_RCC_I2SCLK() by __HAL_RCC_I2S_Config()</span></li></ul></ul><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><ul style="margin-top: 0cm; list-style-type: square;"><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal">
-<p class="MsoListParagraph"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL I2S </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></p>
-<ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;"></span><span style="font-weight: bold;"></span><span style="font-style: italic;">HAL_I2S_Init()</span>: add check on I2S instance using </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">CMSIS macro</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"> <span style="font-style: italic;">IS_I2S_ALL_INSTANCE() </span></span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_I2S_IRQHandler() update for compliancy w/ C++</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add use of tmpreg variable in __HAL_I2S_CLEAR_OVRFLAG() and __HAL_I2S_CLEAR_UDRFLAG() macro for compliancy with C++</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-style: italic;">HAL_I2S_GetError()</span>: update to return uint32_t instead of HAL_I2S_ErrorTypeDef enumeration<br></span></li></ul></li></ul><ul style="margin-top: 0cm; list-style-type: square;"><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal">
-<p class="MsoListParagraph"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL I2C </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></p></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update to clear the POS bit in the CR1 register at the end of </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_I2C_Master_Read_IT() and HAL_I2C_Mem_Read_IT() process</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Rename HAL_I2CEx_DigitalFilter_Config() by HAL_I2CEx_ConfigDigitalFilter() </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Rename HAL_I2CEx_AnalogFilter_Config() by HAL_I2CEx_ConfigAnalogFilter() </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add use of tmpreg variable in __HAL_I2C_CLEAR_ADDRFLAG() and __HAL_I2C_CLEAR_STOPFLAG() macro for</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"> compliancy with C++</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL IrDA </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">DMA transmit process; the code
-has been updated to avoid waiting on TC flag under DMA ISR, IrDA TC interrupt is used instead. Below the
-update to be done on user application:</span></li></ul><ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Configure and enable
-the USART IRQ in HAL_IRDA_MspInit() function</span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">In </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">stm32f4xx_it.c file, </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">UASRTx_IRQHandler()
-function: </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">add a call to
-HAL_IRDA_IRQHandler() function</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">IT transmit process; the code
-has been updated to avoid waiting on TC flag under IRDA ISR, IrDA TC interrupt is used instead. No impact on user application</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Rename Macros: add prefix "__HAL"</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">__IRDA_ENABLE() by __HAL_</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">IRDA</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">_ENABLE()</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">__</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">IRDA</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">_DISABLE() by __HAL_</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">IRDA</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">_DISABLE()</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add new user macros to manage the sample method feature</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">__HAL_</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">IRDA</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">_ONE_BIT_SAMPLE_ENABLE()</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">__HAL_</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">IRDA</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">_ONE_BIT_SAMPLE_DISABLE()</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt; font-style: italic;">HAL_IRDA_Transmit_IT(): </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">update to remove the enable of the parity error interrupt</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add use of tmpreg variable in __HAL_IRDA_CLEAR_PEFLAG() macro for</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"> compliancy with C++</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-style: italic;">HAL_</span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">IRDA</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-style: italic;">_Transmit_DMA() </span>update to follow the right </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">procedure</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"> "Transmission using DMA" in the reference manual</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add clear the TC flag in the SR register before enabling the DMA transmit request</span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL IWDG </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Rename the defined IWDG keys: </span></li></ul><ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">KR_KEY_RELOAD by IWDG_KEY_RELOAD</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">KR_KEY_ENABLE by IWDG_KEY_ENABLE</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">KR_KEY_EWA by IWDG_KEY_WRITE_ACCESS_ENABLE</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">KR_KEY_DWA by IWDG_KEY_WRITE_ACCESS_DISABLE<br></span></li></ul></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"> <span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add new macros __HAL_IWDG_RESET_HANDLE_STATE() and __HAL_IWDG_CLEAR_FLAG() </span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Update __HAL_IWDG_ENABLE_WRITE_ACCESS() and __HAL_IWDG_DISABLE_WRITE_ACCESS() as private macro<br></span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><p class="MsoListParagraph"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL SPI </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></p></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_SPI_TransmitReceive_DMA() update to remove the DMA Tx Error Callback initialization when SPI RxOnly mode is selected<br></span></li></ul><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add use of
-UNUSED(tmpreg) in __HAL_SPI_CLEAR_MODFFLAG(), __HAL_SPI_CLEAR_OVRFLAG(),
-__HAL_SPI_CLEAR_FREFLAG() to </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">fix </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">"Unused variable"
-warning with TrueSTUDIO</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">.</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Rename Literals: </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">remove "D" from "</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">DISABLED" and "</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">ENABLED"</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">SPI_TIMODE_DISABLE<span style="font-weight: bold;">D</span> by SPI_TIMODE_DISABLE</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">SPI_TIMODE_ENABLE<span style="font-weight: bold;">D</span> by </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">SPI_TIMODE_ENABLE</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">SPI_CRCCALCULATION_DISABLE<span style="font-weight: bold;">D</span> by SPI_CRCCALCULATION_DISABLE</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">SPI_CRCCALCULATION_ENABLE<span style="font-weight: bold;">D</span> by SPI_CRCCALCULATION_ENABLE</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add
-use of tmpreg variable in __HAL_SPI_CLEAR_MODFFLAG(),
-__HAL_SPI_CLEAR_FREFLAG() and __HAL_SPI_CLEAR_OVRFLAG() macros for</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"> compliancy with C++</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal">
-<p class="MsoListParagraph"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL SDMMC </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span><span style="font-size: 8pt; font-family: "Verdana","sans-serif"; color: black;"></span></p></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal">
-
-<p class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">IS_SDIO_ALL_INSTANCE()
- macro moved to CMSIS files</span></p></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL LTDC </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;">
-
-<p class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">HAL_LTDC_ConfigCLUT: optimize the function when
-pixel format is LTDC_PIXEL_FORMAT_AL44 </span></p></li><ul style="color: black;"><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Update the size of color look up table to 16 </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">instead of 256 </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">when
-the pixel format is LTDC_PIXEL_FORMAT_AL44 <br>
- </span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL NAND </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update<span style="font-style: italic;"></span></span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Rename NAND Address structure to NAND_AddressType<span style="font-weight: bold;">D</span>ef instead of NAND_AddressTypedef</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Update
-the used algorithm of these functions</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_NAND_Read_Page()</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_NAND_Write_Page()</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_NAND_Read_SpareArea()</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_NAND_Write_SpareArea()</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal">
-
-<p class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">HAL_NAND_Write_Page(): move
-initialization of tickstart before while loop</span></p></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">HAL_NAND_Erase_Block(): <span style="color: black;">add whait until NAND status is ready before exiting this function</span><br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL NOR </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;">
-
-<p class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Rename NOR Address structure to NOR_AddressType<span style="font-weight: bold;">D</span>ef instead of NOR_AddressTypedef</span></p></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">NOR Status literals renamed</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">NOR_SUCCESS by HAL_NOR_STATUS_SUCCESS</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">NOR_ONGOING by HAL_NOR_STATUS_ONGOING</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">NOR_ERROR by HAL_NOR_STATUS_ERROR<br></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">NOR_TIMEOUT by HAL_NOR_STATUS_TIMEOUT</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;">
-
-<p class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">HAL_NOR_GetStatus() update to fix Timeout issue and </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">exit from waiting loop when timeout occurred<br></span></p></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL PCCARD </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Rename PCCARD Address structure to </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_PCCARD_StatusType<span style="font-weight: bold;">D</span>ef</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"> instead of </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">CF_StatusTypedef</span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">PCCARD Status </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">literals</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"> renamed</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">CF_SUCCESS by HAL_PCCARD_STATUS_SUCCESS</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">CF_ONGOING by HAL_PCCARD_STATUS_ONGOING</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">CF_ERROR by HAL_PCCARD_STATUS_ERROR<br></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">CF_TIMEOUT by HAL_PCCARD_STATUS_TIMEOUT</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update "CF" by "PCCARD" in functions, literals and macros</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL PCD </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update<span style="font-style: italic;"></span></span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Rename functions</span></li></ul><ul><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_PCD_<span style="font-weight: bold;">Active</span>RemoteWakeup() by HAL_PCD_<span style="font-weight: bold;">Activate</span>RemoteWakeup()</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_PCD_<span style="font-weight: bold;">DeActive</span>RemoteWakeup() by HAL_PCD_<span style="font-weight: bold;">DeActivate</span>RemoteWakeup()</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Rename literals</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">USB_FS_EXTI_TRIGGER_RISING_EDGE by USB_OTG_FS_WAKEUP_EXTI_RISING_EDGE</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">USB_FS_EXTI_TRIGGER_FALLING_EDGE by USB_OTG_FS_WAKEUP_EXTI_FALLING_EDGE</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">USB_FS_EXTI_TRIGGER_BOTH_EDGE() by USB_OTG_FS_WAKEUP_EXTI_RISING_FALLING_EDGE</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">USB_HS_EXTI_TRIGGER_RISING_EDGE by USB_OTG_HS_WAKEUP_EXTI_RISING_EDGE </span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">USB_HS_EXTI_TRIGGER_FALLING_EDGE by USB_OTG_HS_WAKEUP_EXTI_FALLING_EDGE</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">USB_HS_EXTI_TRIGGER_BOTH_EDGE by USB_OTG_HS_WAKEUP_EXTI_RISING_FALLING_EDGE</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">USB_HS_EXTI_LINE_WAKEUP by USB_OTG_HS_EXTI_LINE_WAKEUP</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">USB_FS_EXTI_LINE_WAKEUP by USB_OTG_FS_EXTI_LINE_WAKEUP</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Rename</span><span style="font-size: 12pt; font-family: Symbol;"></span><span style="font-size: 12pt; font-family: "Times New Roman","serif";" lang="EN-US"><span style=""></span></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US"> USB EXTI macros</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"> </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-style: italic;">(FS,</span> <span style="font-style: italic;">HS </span>referenced as </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US"><b style="">SUBBLOCK </b></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">here below)<span style="font-style: italic;"></span></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US"><o:p></o:p></span>
-
-</li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">__HAL_USB_</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US"><b style="">SUBBLOCK</b></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">_EXTI_ENABLE_IT()
- by __HAL_USB_OTG_</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US"><b style="">SUBBLOCK</b></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">_WAKEUP_EXTI_ENABLE_IT() <o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">__HAL_USB_</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US"><b style="">SUBBLOCK</b></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">_EXTI_DISABLE_IT()
- by __HAL_USB_OTG_</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US"><b style="">SUBBLOCK</b></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">_WAKEUP_EXTI_DISABLE_IT()<o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">__HAL_USB_</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US"><b style="">SUBBLOCK</b></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">_EXTI_GET_FLAG()
- by __HAL_USB_OTG_</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US"><b style="">SUBBLOCK</b></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">_WAKEUP_EXTI_GET_FLAG() <o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">__HAL_USB_</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US"><b style="">SUBBLOCK</b></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">_EXTI_CLEAR_FLAG()
- by __HAL_USB_OTG_</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US"><b style="">SUBBLOCK</b></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">_WAKEUP_EXTI_CLEAR_FLAG()<o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">__HAL_USB_</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US"><b style="">SUBBLOCK</b></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">_EXTI_SET_RISING_EGDE_TRIGGER()
- by __HAL_USB_OTG_</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US"><b style="">SUBBLOCK</b></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">_WAKEUP_EXTI_ENABLE_RISING_EDGE()<o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">__HAL_USB_</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US"><b style="">SUBBLOCK</b></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">_EXTI_SET_FALLING_EGDE_TRIGGER()
- by __HAL_USB_OTG_</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US"><b style="">SUBBLOCK</b></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">_WAKEUP_EXTI_ENABLE_FALLING_EDGE()<o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">__HAL_USB_</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US"><b style="">SUBBLOCK</b></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">_EXTI_SET_FALLINGRISING_TRIGGER()
- by __HAL_USB_OTG_</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US"><b style="">SUBBLOCK</b></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE()<o:p></o:p></span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">__HAL_USB_</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US"><b style="">SUBBLOCK</b></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">_EXTI_GENERATE_SWIT()
- by __HAL_USB_OTG_</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US"><b style="">SUBBLOCK</b></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">_WAKEUP_EXTI_GENERATE_SWIT() </span>
-<br><span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span></li></ul></ul></ul>
-<ul style="margin-top: 0cm; list-style-type: square;"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL RNG </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add new functions</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;">
-
-
-
-<p class="MsoNormal" style=""><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_RNG_GenerateRandomNumber(): to generate a 32-bits random number,</span> <span style="font-size: 10pt; font-family: "Verdana","sans-serif";">return random value in argument and return HAL
-status.</span></p></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;">
-
-<p class="MsoNormal" style=""><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_RNG_GenerateRandomNumber_IT(): </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">to start generation of the 32-bits random number</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">, user should call the </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_RNG_ReadLastRandomNumber() function under the </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_RNG_ReadyCallback()</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"> to get the generated random value.</span></p></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><p class="MsoNormal" style=""><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_RNG_ReadLastRandomNumber(): to return the last random value stored in the RNG handle</span></p></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_RNG_GetRandomNumber(): </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">return value update
-(obsolete), replaced by HAL_RNG_GenerateRandomNumber()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;">
-
-
-
-<p class="MsoNormal" style=""><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_RNG_GetRandomNumber_IT(): wrong implementation (obsolete), replaced by HAL_RNG_GenerateRandomNumber_IT()</span></p></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;">
-
-<p class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_RNG_CLEAR_FLAG() macro (obsolete), replaced by new __HAL_RNG_CLEAR_IT() macro</span></p></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add new define for RNG ready interrupt: RNG_IT_DRDY</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL RTC </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-style: italic;">HAL_RTC_GetTime() and HAL_RTC_GetDate(): add the comment below<br>
-</span></span></li></ul></ul>
- <div style="margin-left: 40px;">
- <div style="margin-left: 40px;"><font size="-2"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-style: italic;"> * @note You must call HAL_RTC_GetDate() after HAL_RTC_GetTime() to unlock the values </span></span></font><font size="-1"><br>
- <span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-style: italic;"> * in the higher-order calendar shadow registers to ensure consistency between the time and date values.</span></span><br>
- <span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-style: italic;"> * Reading RTC current time locks the values in calendar shadow registers until Current date is read. </span></span></font><br>
- </div>
- <span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span></div>
- <ul style="margin-top: 0cm; list-style-type: square;">
-<ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Rename literals: add prefix "__HAL"</span></li></ul><ul><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">FORMAT_BIN by HAL_FORMAT_BIN</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">FORMAT_BCD by HAL_FORMAT_BCD</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Rename macros </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-style: italic;">(ALARM,</span> WAKEUPTIMER and <span style="font-style: italic;">TIMESTAMP </span>referenced as </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US"><b style="">SUBBLOCK </b></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">here below)<span style="font-style: italic;"></span></span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">__HAL_RTC_EXTI_ENABLE_IT() by __HAL_RTC</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">_<b style="">SUBBLOCK</b>_</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">EXTI_ENABLE_IT()</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">__HAL_RTC_EXTI_DISABLE_IT() by __HAL_RTC</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">_<b style="">SUBBLOCK</b>_</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">EXTI_DISABLE_IT()</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal">
-
-<p class="MsoNormal" style="margin: 4.5pt 0cm;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">__HAL_RTC_EXTI_CLEAR_FLAG() by __HAL_RTC_<b style="">SUBBLOCK</b>_EXTI_CLEAR_FLAG()</span></p></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">__HAL_RTC_EXTI_GENERATE_SWIT() by </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">__HAL_RTC</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">_<b style="">SUBBLOCK</b>_</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">EXTI_GENERATE_SWIT()</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add new macros </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-style: italic;">(ALARM,</span> WAKEUPTIMER and <span style="font-style: italic;">TAMPER_TIMESTAMP </span>referenced as </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US"><b style="">SUBBLOCK </b></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">here below)<span style="font-style: italic;"></span></span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">__HAL_RTC_</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US"><b style="">SUBBLOCK</b>_</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">GET_IT_SOURCE() </span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">__HAL_RTC</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">_</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US"><b style="">SUBBLOCK</b>_</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">EXTI_ENABLE_EVENT()</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">__HAL_RTC</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">_</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US"><b style="">SUBBLOCK</b>_</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">EXTI_DISABLE_EVENT()</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">__HAL_RTC_</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US"><b style="">SUBBLOCK</b></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">_EXTI_ENABLE_FALLING_EDGE()</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">__HAL_RTC_</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US"><b style="">SUBBLOCK</b></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">_</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">EXTI_DISABLE_FALLING_EDGE()</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">__HAL_RTC_</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US"><b style="">SUBBLOCK</b></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">_</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">EXTI_ENABLE_RISING_EDGE()</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">__HAL_RTC_</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US"><b style="">SUBBLOCK</b></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">_</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">EXTI_DISABLE_RISING_EDGE()</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US"> __HAL_RTC_</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US"><b style="">SUBBLOCK</b></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">_</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">EXTI_ENABLE_RISING_FALLING_EDGE()</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US"> __HAL_RTC_</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US"><b style="">SUBBLOCK</b></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">_</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">EXTI_DISABLE_RISING_FALLING_EDGE()</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US"> __HAL_RTC_</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US"><b style="">SUBBLOCK</b></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">_</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;" lang="EN-US">EXTI_GET_FLAG()<br></span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL SAI </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update SAI_STREOMODE by </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">SAI_ST<span style="font-weight: bold;">E</span>REOMODE</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update FIFO status Level defines in upper case</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Rename literals: remove "D" from "</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">DISABLED" and "</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">ENABLED"</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">SAI_OUTPUTDRIVE_DISABLED by SAI_OUTPUTDRIVE_DISABLE</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">SAI_OUTPUTDRIVE_ENABLED by SAI_OUTPUTDRIVE_ENABLE</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">SAI_MASTERDIVIDER_ENABLED by SAI_MASTERDIVIDER_ENABLE</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">SAI_MASTERDIVIDER_DISABLED by SAI_MASTERDIVIDER_DISABLE</span></li></ul></ul>
- </ul>
-<span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span><ul style="margin-top: 0cm; list-style-type: square;"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL SD </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Rename SD_CMD_SD_APP_STAUS by </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">SD_CMD_SD_APP_STA<span style="font-weight: bold;">T</span>US</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-style: italic; color: black;">SD_PowerON() </span><span style="color: black;">updated to add 1ms required power up waiting time before starting the SD initialization sequence</span><br></span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-style: italic;">SD_DMA_RxCplt()/SD_DMA_TxCplt(): </span>add a call to HAL_DMA_Abort()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-style: italic;">HAL_SD_ReadBlocks() </span>update to set the defined DATA_BLOCK_SIZE as SDIO DataBlockSize parameter</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_SD_ReadBlocks_DMA()/</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_SD_WriteBlocks_DMA() update to call the </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_DMA_Start_IT() function with </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">DMA Datalength set to BlockSize/4 </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">as the DMA is configured in word </span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL SMARTCARD </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span> <span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">DMA transmit process; the code
-has been updated to avoid waiting on TC flag under DMA ISR, SMARTCARD TC interrupt is used instead. Below the
-update to be done on user application:</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Configure and enable
-the USART IRQ in HAL_SAMRTCARD_MspInit() function</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">In </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">stm32f4xx_it.c file, </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">UASRTx_IRQHandler()
-function: </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">add a call to
-HAL_SMARTCARD_IRQHandler() function</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">IT transmit process; the code
-has been updated to avoid waiting on TC flag under SMARTCARD ISR, </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">SMARTCARD</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"> TC interrupt is used instead. No impact on user application</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Rename macros: add prefix "__HAL"</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">__SMARTCARD_ENABLE() by __HAL_SMARTCARD_ENABLE()</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">__SMARTCARD_DISABLE() by __HAL_SMARTCARD_DISABLE()</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">__SMARTCARD_ENABLE_IT() by __HAL_SMARTCARD_ENABLE_IT()</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">__SMARTCARD_DISABLE_IT() by __HAL_SMARTCARD_DISABLE_IT()</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">__SMARTCARD_DMA_REQUEST_ENABLE() by </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">__HAL_SMARTCARD_DMA_REQUEST_ENABLE()</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">__SMARTCARD_DMA_REQUEST_DISABLE() by </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">__HAL_SMARTCARD_DMA_REQUEST_DISABLE()</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Rename literals: </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">remove "D" from "</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">DISABLED" and "</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">ENABLED"</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">SMARTCARD_NACK_ENABLED by SMARTCARD_NACK_ENABLE</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">SMARTCARD_NACK_DISABLED by </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">SMARTCARD_NACK_DISABLE</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add new user macros to manage the sample method feature</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">__HAL_</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">SMARTCARD</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">_ONE_BIT_SAMPLE_ENABLE()</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">__HAL_</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">SMARTCARD</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">_ONE_BIT_SAMPLE_DISABLE()</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add use of tmpreg variable in __HAL_SMARTCARD_CLEAR_PEFLAG() macro for</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"> compliancy with C++</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-style: italic;">HAL_</span></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">SMARTCARD</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-style: italic;">_Transmit_DMA() </span>update to follow the right </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">procedure</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"> "Transmission using DMA" in the reference manual</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add clear the TC flag in the SR register before enabling the DMA transmit request</span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL TIM </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"> Add TIM_CHANNEL_ALL as possible value for a</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">ll Encoder Start/Stop APIs Description</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL_TIM_OC_ConfigChannel() remove call to IS_TIM_FAST_STATE() assert macro</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL_TIM_PWM_ConfigChannel()</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"> add a call to IS_TIM_FAST_STATE() assert macro to check the OCFastMode parameter</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL_TIM_DMADelayPulseCplt() Update to set the TIM Channel before to call HAL_TIM_PWM_PulseFinishedCallback()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL_TIM_DMACaptureCplt() update to set the TIM Channel before to call HAL_TIM_IC_CaptureCallback()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">TIM_ICx_ConfigChannel() update to fix Timer CCMR1 register corruption when setting ICFilter parameter</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL_TIM_DMABurst_WriteStop()/HAL_TIM_DMABurst_ReadStop() update to abort the DMA transfer for the specifc TIM channel</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">Add new function for TIM Slave configuration in IT mode: <span style="font-style: italic;">HAL_TIM_SlaveConfigSynchronization_IT() </span></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL_TIMEx_ConfigBreakDeadTime() add an assert check on Break & DeadTime parameters values</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US">HAL_TIMEx_OCN_Start_IT() add the enable of Break Interrupt for all output modes</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add new macros to ENABLE/DISABLE URS bit in TIM CR1 register:</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">__HAL_TIM_URS_ENABLE()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">__HAL_TIM_URS_DISABLE()</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add new macro for TIM Edge modification</span>:<span style="font-size: 10pt; font-family: "Verdana","sans-serif";" lang="EN-US"><span style="font-style: italic;"> __HAL_TIM_SET_CAPTUREPOLARITY()</span></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL UART </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;">
-
-<p class="MsoNormal"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add IS_LIN_WORD_LENGTH() and IS_LIN_OVERSAMPLING() </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"> macros:</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"> to
-check respectively WordLength and OverSampling parameters in LIN mode</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-style: italic;"></span></span></p></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><p class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-style: italic;"></span>DMA transmit process; the code
-has been updated to avoid waiting on TC flag under DMA ISR, UART TC interrupt is used instead. Below the
-update to be done on user application:</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span></p></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Configure and enable
-the USART IRQ in HAL_UART_MspInit() function</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">In </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">stm32f4xx_it.c file, </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">USARTx_IRQHandler()
-function: </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">add a call to
-HAL_UART_IRQHandler() function</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">IT transmit process; the code
-has been updated to avoid waiting on TC flag under UART ISR, UART</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"> TC interrupt is used instead. No impact on user application</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Rename macros:</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">__HAL_UART_ONEBIT_ENABLE() by __HAL_UART_ONE_BIT_SAMPLE_ENABLE()</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">__HAL_UART_ONEBIT_DISABLE() by __HAL_UART_ONE_BIT_SAMPLE_DISABLE()</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Rename literals:</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">UART_WAKEUPMETHODE_IDLELINE by UART_WAKEUPMETHOD_IDLELINE</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">UART_WAKEUPMETHODE_ADDRESSMARK by UART_WAKEUPMETHOD_ADDRESSMARK</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add use of tmpreg variable in __HAL_UART_CLEAR_PEFLAG() macro for</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"> compliancy with C++</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-style: italic;">HAL_UART_Transmit_DMA() </span>update to follow the right </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">procedure </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">"Transmission using DMA" in the reference manual</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add clear the TC flag in the SR register before enabling the DMA transmit request<br></span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL USART </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><p class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-style: italic;"></span>DMA transmit process; the code
-has been updated to avoid waiting on TC flag under DMA ISR, USART TC interrupt is used instead. Below the
-update to be done on user application:</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"></span></p></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Configure and enable
-the USART IRQ in HAL_USART_MspInit() function</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">In </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">stm32f4xx_it.c file, </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">USARTx_IRQHandler()
-function: </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">add a call to
-HAL_USART_IRQHandler() function</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">IT transmit process; the code
-has been updated to avoid waiting on TC flag under USART ISR, USART</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"> TC interrupt is used instead. No impact on user application</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-style: italic;">HAL_USART_Init()</span> update to enable the USART oversampling by 8 by default in order to </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">reach max USART frequencies</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">USART_DMAReceiveCplt() update to set the new USART state after checking on the old state</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-style: italic;">HAL_USART_Transmit_DMA()/HAL_USART_TransmitReceive_DMA() </span>update to follow the right </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">procedure</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"> "Transmission using DMA" in the reference manual</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add clear the TC flag in the SR register before enabling the DMA transmit request</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Rename macros:</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">__USART_ENABLE() by __HAL_USART_ENABLE()</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">__USART_DISABLE() by __HAL_USART_DISABLE()</span></li></ul><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">__USART_ENABLE_IT() by __HAL_USART_ENABLE_IT()</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">__USART_DISABLE_IT() by __HAL_USART_DISABLE_IT()</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Rename literals: </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">remove "D" from "</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">DISABLED" and "</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">ENABLED"</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">USART_CLOCK_DISABLED by USART_CLOCK_DISABLE</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">USART_CLOCK_ENABLED by USART_CLOCK_ENABLE</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">USARTNACK_ENABLED by USART_NACK_ENABLE</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">USARTNACK_DISABLED by USART_NACK_DISABLE</span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add new user macros to manage the sample method feature</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">__HAL_USART_ONE_BIT_SAMPLE_ENABLE()</span></li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">__HAL_USART_ONE_BIT_SAMPLE_DISABLE()<br></span></li></ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add use of tmpreg variable in __HAL_USART_CLEAR_PEFLAG() macro for</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"> compliancy with C++</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL WWDG </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">update</span></li><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add new parameter in __HAL_WWDG_ENABLE_IT() macro</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span></li></ul><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add new macros
-to manage WWDG IT & correction:</span></li></ul><ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">__HAL_WWDG_DISABLE()</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">__HAL_WWDG_DISABLE_IT()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">__HAL_WWDG_GET_IT()</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">__HAL_WWDG_GET_IT_SOURCE()</span></li></ul></ul></ul><ul style="margin-top: 0cm; list-style-type: square;"></ul>
-
-
-
- <h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.1.0 / 19-June-2014</span></h3>
-
- <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b><u><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;">Main Changes</span></u></b><span style="font-size: 12pt; font-family: "Times New Roman","serif";"><o:p></o:p></span></p>
-
-
-
-
-
-
- <ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;">Add support of<span class="Apple-converted-space"> </span><b>STM32F411xE</b><span class="Apple-converted-space"> </span>devices</span></li></ul>
- <ul style="margin-top: 0cm; list-style-type: square;">
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL generic</span> update</span></li>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Enhance HAL delay and </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">time base</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"> implementation<br>
- </span></li>
- </ul>
- <ul>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Systick
-timer is used by default as source of time base, but user can
-eventually implement his proper time base source (a general purpose
-timer for example or other time source)</span></li>
- </ul>
- </ul>
- <ul>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Functions
-affecting time base configurations are declared as __Weak to make
-override possible in case of other implementations in user file, for
-more details please refer to HAL_TimeBase example</span></li>
- </ul>
- </ul>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Fix flag clear procedure: use atomic write operation "=" instead of ready-modify-write operation "|=" or "&="</span></li>
- </ul>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Fix
-on Timeout management, Timeout value set to 0 passed to API
-automatically exits the function after checking the flag without any
-wait</span></li>
- </ul>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Common update for the following communication peripherals: SPI, UART, USART and IRDA</span></li>
- </ul>
- <ul>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add DMA circular mode support</span></li>
- </ul>
- </ul>
- <ul>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Remove lock from recursive process</span></li>
- </ul>
- </ul>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add new macro __HAL_RESET_HANDLE_STATE to reset a given handle state</span></li>
- </ul>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add a new attribute for functions executed from internal SRAM and depending from Compiler implementation</span></li>
- </ul>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">When USE_RTOS == 1 (in stm32l0xx_hal_conf.h), the __HAL_LOCK() is not defined instead of being defined empty</span></li>
- </ul>
-
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Miscellaneous comments and formatting update</span><br>
- <span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span></li>
- </ul>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">stm32f4xx_hal_conf_template.h</span></li>
- </ul>
- <ul>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add a new define for LSI default value LSI_VALUE</span></li>
- </ul>
- </ul>
- <ul>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add a new define for LSE default value LSE_VALUE</span></li>
- </ul>
- </ul>
- <ul>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add a new define for Tick interrupt priority TICK_INT_PRIORITY (needed for the enhanced </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">time base</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"> implementation)</span></li>
- </ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; line-height: 115%; font-family: "Verdana","sans-serif"; color: windowtext;"><span style="text-decoration: underline; font-style: italic;">Important Note:</span> aliases has been added for any API naming change, to keep compatibility with previous version</span></li>
-
- </ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL GPIO</span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;"> </span>update</span></li>
-<ul style="margin-top: 0cm;" type="circle">
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add a new macro
- <span style="font-style: italic;">__HAL_GPIO_EXTI_GENERATE_SWIT()</span> to manage the generation of software interrupt
- on selected EXTI line</span></li>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_GPIO_Init():
-use temporary variable when modifying the registers, to avoid
-unexpected transition in the GPIO pin configuration<br>
-</span></li>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Remove IS_GET_GPIO_PIN macro</span></li>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add a new function HAL_GPIO_LockPin()</span></li>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Private Macro __HAL_GET_GPIO_SOURCE renamed into GET_GPIO_SOURCE</span></li>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add the support of STM32F411xx devices : add the new Alternate functions values related to new remap added for SPI, USART, I2C<br>
- </span></li>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Update the following HAL GPIO macros description: rename EXTI_Linex by GPIO_PIN_x<o:p></o:p></span></li>
-<ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_GPIO_EXTI_CLEAR_IT()<o:p></o:p></span></li>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_GPIO_EXTI_GET_IT()<o:p></o:p></span></li>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_GPIO_EXTI_CLEAR_FLAG()<o:p></o:p></span></li>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_GPIO_EXTI_GET_FLAG()</span></li>
-</ul></ul>
- <li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;">
- <p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL DMA</span> update</span></p></li>
- <ul>
- <li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Fix in HAL_DMA_PollForTransfer() to:</span></li>
- <ul>
- <li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">set DMA error code in case of HAL_ERROR status <br>
- </span></li>
- <li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">set HAL Unlock before DMA state update</span></li>
- </ul>
- </ul>
- <li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;">
- <p class="MsoListParagraph"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL DMA2D</span> update</span></p></li>
- <ul>
-<li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add configuration of source address in case of A8 or A4 M2M_PFC DMA2D mode</span></li>
- </ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL FLASH </span>update</span></li>
- </ul>
-
- <span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span>
- <ul style="margin-top: 0cm;" type="circle">
-<ul style="margin-top: 0cm;" type="circle"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Functions reorganization update, depending on the features supported by each STM32F4 device<o:p></o:p></span></li>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add new driver (stm32f4xx_hal_flash_ramfunc.h/.c) to manage function
- executed from RAM, these functions are available only for STM32F411xx
- Devices<o:p></o:p></span></li>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-style: italic;">FLASH_StopFlashInterfaceClk()</span><span style=""> </span>: Stop the flash interface while System
- Run<o:p></o:p></span></li>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-style: italic;">FLASH_StartFlashInterfaceClk()</span> :
- Stop the flash interface while System Run<o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-style: italic;">FLASH_EnableFlashSleepMode()</span> :
- Enable the flash sleep while System Run<o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-style: italic;">FLASH_DisableFlashSleepMode()</span>
- :<span style=""> </span>Disable the flash sleep while
- System Run</span></li>
- </ul>
-</ul>
- </ul>
-
-
-
-
- <ul style="margin-top: 0cm; list-style-type: square;">
- <li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL PWR</span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;"> </span>update<o:p></o:p></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;"></span></li>
- </ul>
-<ul>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-style: italic;">HAL_PWR_PVDConfig()</span>: add clear of the EXTI trigger before new configuration </span><br>
-<span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></li>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Fix
-in HAL_PWR_EnterSTANDBYMode() to not clear Wakeup flag (WUF), which
-need to be cleared at application level before to call this function</span></li>
-
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_PWR_EnterSLEEPMode()</span></li>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Remove disable and enable of SysTick Timer</span></li>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Update
-usage of __WFE() in low power entry function: if there is a pending
-event, calling __WFE() will not enter the CortexM4 core to sleep mode.
-The solution is to made the call below; the first __WFE() is always
-ignored and clears the event if one was already pending, the second is
-always applied<br>
- </span></li>
- </ul>
-</ul></ul>
- <div style="margin-left: 120px;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__SEV()</span><br>
- <span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__WFE()</span><br>
- <span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__WFE()</span></div>
- <ul>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add new macro for software event generation __HAL_PVD_EXTI_GENERATE_SWIT()</span></li>
-
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Remove
-the following defines form Generic driver and add them under extension
-driver because they are only used within extension functions.</span></li>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">CR_FPDS_BB: used within HAL_PWREx_EnableFlashPowerDown() function</span></li>
- </ul>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">CSR_BRE_BB: used within HAL_PWREx_EnableBkUpReg() function</span></li>
- </ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add the support of STM32F411xx
- devices add the define STM32F411xE<o:p></o:p></span></li>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">For STM32F401xC, STM32F401xE and
- STM32F411xE devices add the following functions used to enable or disable
- the low voltage mode for regulators<o:p></o:p></span></li>
- </ul>
-<ul style="margin-top: 0cm;" type="circle"><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_PWREx_EnableMainRegulatorLowVoltage()<o:p></o:p></span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_PWREx_DisableMainRegulatorLowVoltage()<o:p></o:p></span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_PWREx_EnableLowRegulatorLowVoltage()<o:p></o:p></span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_PWREx_DisableLowRegulatorLowVoltage()<o:p></o:p></span></li></ul></ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">For STM32F42xxx/43xxx devices,
- add a new function for Under Driver management as the macro already added
- for this mode is not sufficient: HAL_PWREx_EnterUnderDriveSTOPMode()</span><span style="font-size: 10pt; font-family: "Courier New"; color: red;" lang="EN-US"><span style=""></span></span></li>
-
- </ul>
-
- </ul>
-<ul style="list-style-type: square;"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-weight: bold;"></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL RCC</span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;"> </span>update<o:p></o:p></span></li><ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">In <span style="font-style: italic;">HAL_RCC_ClockConfig()</span>
- function: update the AHB clock divider before clock switch to new source</span></li>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Allow to calibrate the HSI when it is used as system clock source</span><br>
-<span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></li>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Rename the following macros<o:p></o:p></span></li>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; font-style: italic;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__OTGFS_FORCE_RESET ()<span style=""> </span>by __USB_OTG_FS_FORCE_RESET()<o:p></o:p></span></li>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; font-style: italic;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__OTGFS_RELEASE_RESET ()<span style=""> </span>by<span style="">
- </span>__USB_OTG_FS_RELEASE_RESET()<o:p></o:p></span></li>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt; font-style: italic;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__OTGFS_CLK_SLEEP_ENABLE ()<span style=""> </span>by<span style="">
- </span>__USB_OTG_FS_CLK_SLEEP_ENABLE()<o:p></o:p></span></li>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-style: italic;">__OTGFS_CLK_SLEEP_DISABLE ()
- by
- __USB_OTG_FS_CLK_SLEEP_DISABLE()</span></span></li>
- </ul>
-</ul></ul><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><o:p></o:p></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;"><o:p></o:p></span>
- <ul>
-<ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add new field PLLI2SM in
- RCC_PLLI2SInitTypeDef structure, this division factor is added for PLLI2S
- VCO input clock only STM32F411xE devices => the FW compatibility is
- broken vs. STM32F401xx devices <o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Update <span style=""></span><span style="font-style: italic;">HAL_RCCEx_PeriphCLKConfig()</span> and<span style=""> </span><span style="font-style: italic;">HAL_RCCEx_GetPeriphCLKConfig()</span><span style=""> </span>functions to support the new PLLI2SM <o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add new function to manage the
- new LSE mode : HAL_RCCEx_SelectLSEMode()</span></li><li><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Reorganize the macros depending
- from Part number used and make them more clear</span></li></ul>
- </ul>
-
-<ul style="list-style-type: square; margin-top: 0cm;">
- <li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal WordSection1">
- <p class="MsoListParagraph"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL </span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">UART </span>update<o:p></o:p></span></p>
-
-<ul><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add new macros to control CTS and RTS</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><br></span>
-</li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add specific macros
-to manage the flags cleared only by a software sequence<o:p></o:p></span>
-<ul style="font-style: italic;"><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">__HAL_UART_CLEAR_PEFLAG()<o:p></o:p></span>
-</li></ul>
-<ul style="font-style: italic;"><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">__HAL_UART_CLEAR_FEFLAG()<o:p></o:p></span>
-</li></ul>
-<ul style="font-style: italic;"><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">__HAL_UART_CLEAR_NEFLAG()<o:p></o:p></span>
-</li></ul>
-<ul style="font-style: italic;"><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">__HAL_UART_CLEAR_OREFLAG()<o:p></o:p></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span>
-</li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">__HAL_UART_CLEAR_IDLEFLAG()</span>
-</li></ul>
-</li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add several
-enhancements without affecting the driver functionalities <o:p></o:p></span>
-<ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Remove the check on
-RXNE set after reading the Data in the DR register<o:p></o:p></span> </li></ul>
-<ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update the transmit
-processes to use TXE instead of TC</span>
-</li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update <span style="font-style: italic;">HAL_UART_Transmit_IT()</span> to enable <span style="font-style: italic;">UART_IT_TXE</span> instead of <span style="font-style: italic;">UART_IT_TC</span></span> </li></ul></li></ul>
- </li>
-<li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal">
-<p class="MsoListParagraph"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL USART</span> update<br></span></p>
-<ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add specific macros
-to manage the flags cleared only by a software sequence</span>
-<ul style="font-style: italic;"><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">__HAL_USART_CLEAR_PEFLAG()<o:p></o:p></span>
-</li></ul>
-<ul style="font-style: italic;"><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">__HAL_USART_CLEAR_FEFLAG()<o:p></o:p></span>
-</li></ul>
-<ul style="font-style: italic;"><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">__HAL_USART_CLEAR_NEFLAG()<o:p></o:p></span>
-</li></ul>
-<ul style="font-style: italic;"><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">__HAL_USART_CLEAR_OREFLAG()<o:p></o:p></span>
-</li></ul>
-<ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-style: italic;">__HAL_USART_CLEAR_IDLEFLAG()</span></span> </li></ul>
-</li><li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update
-<span style="font-style: italic;">HAL_USART_Transmit_IT()</span> to enable <span style="font-style: italic;">USART_IT_TXE</span> instead of <span style="font-style: italic;">USART_IT_TC</span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span> </li></ul>
-</li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal">
-<p class="MsoListParagraph"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL IRDA</span> update<br></span></p>
-<ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add specific macros
-to manage the flags cleared only by a software sequence</span>
-<ul><li style="font-style: italic; margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">__HAL_IRDA_CLEAR_PEFLAG()<o:p></o:p></span>
-</li><li style="font-style: italic; margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">__HAL_ IRDA
-_CLEAR_FEFLAG()<o:p></o:p></span>
-</li><li style="font-style: italic; margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">__HAL_ IRDA
-_CLEAR_NEFLAG()<o:p></o:p></span>
-</li><li style="font-style: italic; margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">__HAL_ IRDA
-_CLEAR_OREFLAG()<o:p></o:p></span>
-</li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-style: italic;">__HAL_ IRDA
-_CLEAR_IDLEFLAG()</span><o:p></o:p></span> </li></ul>
-</li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add several
-enhancements without affecting the driver functionalities</span>
-<ul style="margin-top: 0cm;" type="circle"><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Remove the check on
-RXNE set after reading the Data in the DR register</span><br><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span>
-</li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update <span style="font-style: italic;">HAL_IRDA_Transmit_IT()</span> to enable <span style="font-style: italic;">IRDA_IT_TXE</span> instead of <span style="font-style: italic;">IRDA_IT_TC</span></span> </li></ul>
-</li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add the following
-APIs used within DMA process <o:p></o:p></span>
-<ul><li style="font-style: italic; margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_StatusTypeDef
-HAL_IRDA_DMAPause(IRDA_HandleTypeDef *hirda);<o:p></o:p></span> </li></ul>
-<ul><li style="font-style: italic; margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_StatusTypeDef
-HAL_IRDA_DMAResume(IRDA_HandleTypeDef *hirda);<o:p></o:p></span>
-</li><li style="font-style: italic; margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_StatusTypeDef
-HAL_IRDA_DMAStop(IRDA_HandleTypeDef *hirda); <o:p></o:p></span>
-</li><li style="font-style: italic; margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">void
-HAL_IRDA_TxHalfCpltCallback(IRDA_HandleTypeDef *hirda);<o:p></o:p></span>
-</li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-style: italic;">void HAL_IRDA_RxHalfCpltCallback(IRDA_HandleTypeDef
-*hirda);</span></span> </li></ul></li></ul>
-</li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal">
-<p class="MsoListParagraph"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL SMARTCARD</span> update<br></span></p>
-<ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add specific macros
-to manage the flags cleared only by a software sequence</span>
-<ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">__HAL_SMARTCARD_CLEAR_PEFLAG()<o:p></o:p></span>
-</li></ul>
-<ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">__HAL_SMARTCARD_CLEAR_FEFLAG()<o:p></o:p></span>
-</li></ul>
-<ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">__HAL_SMARTCARD_CLEAR_NEFLAG()<o:p></o:p></span>
-</li></ul>
-<ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">__HAL_SMARTCARD_CLEAR_OREFLAG()<o:p></o:p></span>
-</li></ul>
-<ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-style: italic;">__HAL_SMARTCARD_CLEAR_IDLEFLAG()</span><o:p></o:p></span>
-</li></ul>
-</li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add several
-enhancements without affecting the driver functionalities</span>
-<ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add a new state
-<span style="font-style: italic;">HAL_SMARTCARD_STATE_BUSY_TX_RX</span> and all
-processes has been updated accordingly</span> </li></ul>
-<ul>
- <li><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update
-<span style="font-style: italic;">HAL_SMARTCARD_Transmit_IT()</span> to enable
-<span style="font-style: italic;">SMARTCARD_IT_TXE</span> instead of <span style="font-style: italic;">SMARTCARD_IT_TC</span></span>
- </li>
-</ul></li></ul></li></ul><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-style: italic;"></span></span>
-<ul style="list-style-type: square; margin-top: 0cm;"><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL SPI</span> update</span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><o:p></o:p></span>
-<ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Bugs fix</span>
-<ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">SPI interface is
-used in synchronous polling mode: at high clock rates like SPI prescaler 2 and
-4, calling <br>HAL_SPI_TransmitReceive() returns with error HAL_TIMEOUT</span>
-</li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-style: italic;">HAL_SPI_TransmitReceive_DMA()</span> does not clean
-up the TX DMA, so any subsequent SPI calls return the DMA error</span>
-</li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-style: italic;">HAL_SPI_Transmit_DMA()</span> is failing when data
-size is equal to 1 byte</span> </li></ul>
-</li><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add the following
-APIs used within the DMA process<o:p></o:p></span> </li></ul>
-<ul style="margin-top: 0cm;" type="circle"><ul style="font-style: italic;"><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_StatusTypeDef
-HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);<o:p></o:p></span></li></ul><ul style="font-style: italic;"><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_StatusTypeDef
-HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);<o:p></o:p></span></li></ul><ul style="font-style: italic;"><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_StatusTypeDef
-HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);<o:p></o:p></span></li></ul><ul style="font-style: italic;"><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">void
-HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);<o:p></o:p></span></li></ul><ul style="font-style: italic;"><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">void
-HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);<o:p></o:p></span></li></ul><ul><li style="margin-top: 4.5pt; margin-bottom: 4.5pt; color: black;" class="MsoNormal"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-style: italic;">void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef
-*hspi);</span><o:p></o:p></span></li></ul></ul></li></ul>
-<ul style="margin-top: 0cm; list-style-type: square;">
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL RNG </span>update</span></li>
- <ul style="margin-top: 0cm;" type="circle">
-<ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style=""> </span><o:p></o:p></span>
-
-
-
-<span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add a conditional define to make
- this driver visible for all STM32F4xx devices except STM32F401xx and
- STM32F411xx Devices.<span style=""> <br>
-</span></span></li></ul>
- </ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL CRC </span>update</span></li>
- <ul style="margin-top: 0cm;" type="circle">
-<ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style=""> </span><o:p></o:p></span>
-
-
-
-<span style="font-size: 10pt; font-family: "Verdana","sans-serif";">These macros are added to read/write the CRC IDR register: __HAL_CRC_SET_IDR() and __HAL_CRC_GET_IDR()<span style=""></span></span></li></ul>
- </ul>
-</ul><ul style="margin-top: 0cm; list-style-type: square;">
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL DAC </span>update</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"> <o:p></o:p></span></li>
- <ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Enhance the DMA channel
- configuration when used with <span style=""></span>DAC <o:p></o:p></span></li>
- </ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL TIM </span>update</span></li>
- <ul>
-
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_TIM_IRQHandler(): </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">update to check the input capture channel 3 and 4 in CCMR2 instead of CCMR1</span></li>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_TIM_PRESCALER() updated to use '=' instead of '|='<br>
- </span></li>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"> Add the
- following macro in TIM HAL driver</span></li>
-
- </ul>
-<ul style="font-style: italic;"><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_TIM_GetCompare() <o:p></o:p></span></li></ul></ul><ul style="font-style: italic;"><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_TIM_GetCounter() <o:p></o:p></span></li></ul></ul><ul style="font-style: italic;"><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_TIM_GetAutoreload() <o:p></o:p></span></li></ul></ul><ul style="font-style: italic;"><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_TIM_GetClockDivision() <o:p></o:p></span></li></ul></ul><ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-style: italic;">__HAL_TIM_GetICPrescaler()</span></span></li></ul></ul>
-
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL SDMMC</span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;"> </span>update</span></li>
- <ul style="margin-top: 0cm;" type="circle">
- <li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Use of CMSIS constants instead of magic values</span><br>
- <span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"></span></li>
- <li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Miscellaneous update in functions internal coding<br>
- </span></li>
- </ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL NAND</span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;"> </span>update</span></li>
- <ul style="margin-top: 0cm;" type="circle">
-<li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;">Fix issue of macros returning wrong address for NAND blocks</span></li>
- <li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;">Fix issue for read/write NAND page/spare area</span></li>
- </ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL NOR</span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;"> </span>update</span></li>
- <ul style="margin-top: 0cm;" type="circle">
-<li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;">Add the NOR address
- bank macro used within the API</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><o:p></o:p></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;"></span></li><li class="MsoNormal" style="margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;">Update NOR API
- implementation to avoid the use of NOR address bank hard coded</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><o:p></o:p></span></li>
- </ul>
-
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL HCD</span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;"> </span>update</span></li>
- <ul style="margin-top: 0cm;" type="circle">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HCD_StateTypeDef structure members renamed</span></li>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">These macro are renamed</span></li>
- <ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_GET_FLAG(__HANDLE__, __INTERRUPT__) by __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__)</span></li>
- </ul>
- <ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) by __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) <br>
- </span></li>
- </ul>
- <ul>
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_IS_INVALID_INTERRUPT(__HANDLE__) by __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) <br>
- </span></li>
- </ul>
- </ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL PCD</span></span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;"> </span>update</span></li>
-
- <ul style="margin-top: 0cm;" type="circle">
-<li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_PCD_SetTxFiFo() and HAL_PCD_SetRxFiFo() renamed into </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">HAL_PCDEx_SetTxFiFo() and HAL_PCDEx_SetRxFiFo() and moved to the extension files stm32f4xx_hal_pcd_ex.h/.c<br>
- </span></li>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">PCD_StateTypeDef structure members renamed</span></li>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Fix incorrect masking of TxFIFOEmpty</span><br>
- <span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></li>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">stm32f4xx_ll_usb.c: fix issue in HS mode<br>
- </span></li>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">New macros added<br>
- </span></li>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_PCD_IS_PHY_SUSPENDED()</span></li>
- </ul>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_USB_HS_EXTI_GENERATE_SWIT()</span></li>
- </ul>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_USB_FS_EXTI_GENERATE_SWIT()</span></li>
- </ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">These macro are renamed</span></li>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_GET_FLAG(__HANDLE__, __INTERRUPT__) by __HAL_PCD_GET_FLAG(__HANDLE__, __INTERRUPT__)</span></li>
- </ul>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) by __HAL_PCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) <br>
- </span></li>
- </ul>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_IS_INVALID_INTERRUPT(__HANDLE__) by __HAL_PCD_IS_INVALID_INTERRUPT(__HANDLE__) <br>
- </span></li>
- </ul>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_PCD_UNGATE_CLOCK(__HANDLE__) by __HAL_PCD_UNGATE_PHYCLOCK(__HANDLE__)</span></li>
- </ul>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_PCD_GATE_CLOCK(__HANDLE__) by __HAL_PCD_GATE_PHYCLOCK(__HANDLE__)</span></li>
- </ul>
-</ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL ETH </span>update</span></li>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Update HAL_ETH_GetReceivedFrame_IT() function to return HAL_ERROR if the received packet is not complete</span></li>
-
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Use HAL_Delay() instead of counting loop<br>
- </span></li>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"> __HAL_ETH_MAC_CLEAR_FLAG() macro is removed: the MACSR register is read only</span></li>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add the following macros used to
- Wake up the device from STOP mode by Ethernet event :</span><span style="font-size: 12pt; font-family: "Times New Roman","serif";"><o:p></o:p></span></li>
-
-<ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_ETH_EXTI_ENABLE_IT()<o:p></o:p></span></li>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_ETH_EXTI_DISABLE_IT()<o:p></o:p></span></li>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_ETH_EXTI_GET_FLAG()<o:p></o:p></span></li>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-style: italic;">__HAL_ETH_EXTI_CLEAR_FLAG()</span><o:p></o:p></span></li>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_ETH_EXTI_SET_RISING_EGDE_TRIGGER()<o:p></o:p></span></li>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER()</span></li>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-style: italic;">__HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER()</span></span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></li>
-</ul>
-
- </ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL WWDG</span> update <br>
- </span></li>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Update macro parameters to use underscore: __XXX__</span></li>
- </ul>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Use of CMSIS constants instead of magic values<br>
- </span></li>
- </ul>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Use MODIFY_REG macro in HAL_WWDG_Init()</span></li>
- </ul>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add IS_WWDG_ALL_INSTANCE in HAL_WWDG_Init() and HAL_WWDG_DeInit()</span></li>
- </ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-weight: bold;">HAL IWDG</span> update</span></li>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Use WRITE_REG instead of SET_BIT for all IWDG macros</span></li>
- </ul>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">__HAL_IWDG_CLEAR_FLAG removed: no IWDG flag cleared by access to SR register</span></li>
- </ul>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Use MODIFY_REG macro in HAL_IWDG_Init()</span></li>
- </ul>
- <ul>
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">Add IS_IWDG_ALL_INSTANCE in HAL_IWDG_Init()Add the following macros used to
- Wake</span></li>
- </ul>
-
-</ul>
-<span style="font-size: 10pt; font-family: "Verdana","sans-serif";"><span style="font-style: italic;"></span></span><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 180px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.0.0 / 18-February-2014</span></h3>
-
- <p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b><u><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;">Main Changes</span></u></b><span style="font-size: 12pt; font-family: "Times New Roman","serif";"><o:p></o:p></span></p>
-
-
-
-
-
-
- <ul style="margin-top: 0cm;" type="square">
- <li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: Verdana;">First official release</span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";"></span></li></ul><h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="License"></a><span style="font-size: 12pt; color: white;">License<o:p></o:p></span></h2>
- <div style="text-align: justify;">
- <div style="text-align: justify;"><font size="-1"><span style="font-family: "Verdana","sans-serif";">
-Redistribution and use in source and binary forms, with or without
-modification, are permitted provided that the following conditions are
-met:</span><br>
- </font>
- <ol><li><font size="-1"><span style="font-family: "Verdana","sans-serif";">Redistributions of source code must retain the above copyright notice, this list of conditions and the following disclaimer.</span><span style="font-family: "Verdana","sans-serif";"></span></font></li><li><font size="-1"><span style="font-family: "Verdana","sans-serif";">Redistributions
-in binary form must reproduce the above copyright notice, this list of
-conditions and the following disclaimer in </span><span style="font-family: "Verdana","sans-serif";">the documentation and/or other materials provided with the distribution.</span><span style="font-family: "Verdana","sans-serif";"></span></font></li><li><font size="-1"><span style="font-family: "Verdana","sans-serif";">Neither the name of STMicroelectronics nor the names of its contributors may be used to endorse or promote products derived </span><br>
- </font>
- </li></ol>
- <font size="-1"><span style="font-family: "Verdana","sans-serif";"> from this software without specific prior written permission.</span><br>
- <span style="font-family: "Verdana","sans-serif";"></span><br>
- <span style="font-family: "Verdana","sans-serif";">THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND ANY EXPRESS OR IMPLIED</span><span style="font-family: "Verdana","sans-serif";"> WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A </span><span style="font-family: "Verdana","sans-serif";">PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY </span><span style="font-family: "Verdana","sans-serif";">DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, </span><span style="font-family: "Verdana","sans-serif";">PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER</span><span style="font-family: "Verdana","sans-serif";"> CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR </span><span style="font-family: "Verdana","sans-serif";">OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.</span></font>
-
- </div>
-<span style="font-family: "Verdana","sans-serif";"></span></div>
-<span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;"></span>
- <div class="MsoNormal" style="text-align: center;" align="center"><span style="color: black;">
- <hr align="center" size="2" width="100%">
- </span></div>
- <p class="MsoNormal" style="margin: 4.5pt 0in 4.5pt 0.25in; text-align: center;" align="center"><span style="font-size: 10pt; font-family: "Verdana","sans-serif"; color: black;">For
- complete documentation on </span><span style="font-size: 10pt; font-family: "Verdana","sans-serif";">STM32<span style="color: black;">
- Microcontrollers visit </span><u><span style="color: blue;"><a href="http://www.st.com/internet/mcu/family/141.jsp" target="_blank">www.st.com/STM32</a></span></u></span><span style="color: black;"><o:p></o:p></span></p>
- </td>
- </tr>
- </tbody></table>
- <p class="MsoNormal"><span style="font-size: 10pt;"><o:p></o:p></span></p>
- </td>
- </tr>
-</tbody></table>
-
-</div>
-
-<p class="MsoNormal"><o:p> </o:p></p>
-
-</div>
-
-</body></html>
\ No newline at end of file
--- a/targets/TARGET_STM/TARGET_STM32F4/device/hal_init_pre.c Fri Feb 16 16:09:33 2018 +0000
+++ /dev/null Thu Jan 01 00:00:00 1970 +0000
@@ -1,29 +0,0 @@
-/*
- * Copyright (c) 2015-2015, ARM Limited, All Rights Reserved
- * SPDX-License-Identifier: Apache-2.0
- *
- * Licensed under the Apache License, Version 2.0 (the "License"); you may
- * not use this file except in compliance with the License.
- * You may obtain a copy of the License at
- *
- * http://www.apache.org/licenses/LICENSE-2.0
- *
- * Unless required by applicable law or agreed to in writing, software
- * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
- * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
- * See the License for the specific language governing permissions and
- * limitations under the License.
- */
-#include "stm32f4xx_hal.h"
-
-/* this function is needed to peform hardware initialization that must happen
- * before the uVisor; the whole SystemInit function for the STM32F4 cannot be
- * put here as it depends on some APIs that need uVisor to be enabled */
-HAL_StatusTypeDef HAL_InitPre(void)
-{
- /* Set Interrupt Group Priority */
- HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
-
- /* Return function status */
- return HAL_OK;
-}
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32_hal_legacy.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32_hal_legacy.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,9 +2,7 @@
******************************************************************************
* @file stm32_hal_legacy.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
- * @brief This file contains aliases definition for the STM32Cube HAL constants
+ * @brief This file contains aliases definition for the STM32Cube HAL constants
* macros and functions maintained for legacy purpose.
******************************************************************************
* @attention
@@ -60,7 +58,7 @@
/**
* @}
*/
-
+
/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
* @{
*/
@@ -92,10 +90,10 @@
#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6
#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8
-#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
-#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
-#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
-#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
+#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
+#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
+#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
+#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
@@ -111,21 +109,21 @@
#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC
#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL
#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL
-#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1
+#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1
/**
* @}
*/
-
+
/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
* @{
- */
-
-#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
+ */
+
+#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
/**
* @}
- */
-
+ */
+
/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
* @{
*/
@@ -138,7 +136,9 @@
#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5
#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
-#define COMP_LPTIMCONNECTION_ENABLED COMP_LPTIMCONNECTION_IN1_ENABLED /*!< COMPX output is connected to LPTIM input 1 */
+#if defined(STM32L0)
+#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */
+#endif
#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
#if defined(STM32F373xC) || defined(STM32F378xx)
#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
@@ -154,7 +154,7 @@
#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4
#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5
#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6
-
+
#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT
#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT
#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT
@@ -226,7 +226,7 @@
/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
* @{
*/
-
+
#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
@@ -255,28 +255,27 @@
/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
* @{
*/
-#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2
-#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4
-#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5
-#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4
-#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2
+#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2
+#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4
+#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5
+#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4
+#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2
#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6
-#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
-#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
-#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
-#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
-#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
-#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
-#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
-#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6
-
-#define IS_HAL_REMAPDMA IS_DMA_REMAP
+#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
+#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
+#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
+#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
+#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
+#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
+#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6
+
+#define IS_HAL_REMAPDMA IS_DMA_REMAP
#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
-
-
-
+
+
+
/**
* @}
*/
@@ -284,7 +283,7 @@
/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
* @{
*/
-
+
#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE
#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD
#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD
@@ -360,11 +359,11 @@
/**
* @}
*/
-
+
/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
* @{
*/
-
+
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
@@ -377,12 +376,12 @@
/**
* @}
*/
-
+
/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
* @{
*/
-#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7)
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
@@ -400,7 +399,7 @@
/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
* @{
*/
-
+
#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef
#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef
/**
@@ -432,18 +431,18 @@
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
-#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7)
-#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
-#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
-#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
-#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
-#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */
-
-#if defined(STM32L1)
- #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
- #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
- #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
- #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
+#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4)
+#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
+#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
+#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
+#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
+#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 */
+
+#if defined(STM32L1)
+ #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
+ #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
+ #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
+ #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
#endif /* STM32L1 */
#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
@@ -457,6 +456,78 @@
* @}
*/
+/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#if defined(STM32H7)
+ #define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE
+ #define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE
+ #define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET
+ #define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET
+ #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
+ #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
+
+ #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
+ #define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2
+
+ #define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
+ #define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
+
+ #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
+ #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
+ #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
+ #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
+ #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
+ #define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
+ #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
+ #define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
+
+ #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
+ #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
+ #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
+ #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
+ #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
+ #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
+ #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
+ #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
+ #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
+ #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
+ #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
+ #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
+ #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
+ #define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
+ #define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
+ #define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
+ #define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
+ #define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT
+ #define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT
+ #define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP
+ #define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0
+ #define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2
+ #define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
+ #define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT
+ #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
+ #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
+ #define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT
+ #define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
+ #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
+ #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
+
+ #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
+ #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
+ #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
+ #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
+
+
+#endif /* STM32H7 */
+
+
+/**
+ * @}
+ */
+
+
/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
* @{
*/
@@ -469,7 +540,7 @@
#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
-
+
#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER
#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER
#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD
@@ -542,7 +613,7 @@
#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS
#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS
/* The following 3 definition have also been present in a temporary version of lptim.h */
/* They need to be renamed also to the right name, just in case */
@@ -572,7 +643,7 @@
/**
* @}
*/
-
+
/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
* @{
*/
@@ -596,11 +667,11 @@
#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1
#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2
#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3
-
+
#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0
#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1
#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2
-#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
+#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
@@ -609,14 +680,14 @@
#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0
-#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
+#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1
-
-#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
-#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
-#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
-
+
+#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
+#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
+#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
+
/**
* @}
*/
@@ -625,7 +696,7 @@
* @{
*/
#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
-#if defined(STM32F7)
+#if defined(STM32F7)
#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
#endif
/**
@@ -637,18 +708,18 @@
*/
/* Compact Flash-ATA registers description */
-#define CF_DATA ATA_DATA
-#define CF_SECTOR_COUNT ATA_SECTOR_COUNT
-#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
-#define CF_CYLINDER_LOW ATA_CYLINDER_LOW
-#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
-#define CF_CARD_HEAD ATA_CARD_HEAD
-#define CF_STATUS_CMD ATA_STATUS_CMD
+#define CF_DATA ATA_DATA
+#define CF_SECTOR_COUNT ATA_SECTOR_COUNT
+#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
+#define CF_CYLINDER_LOW ATA_CYLINDER_LOW
+#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
+#define CF_CARD_HEAD ATA_CARD_HEAD
+#define CF_STATUS_CMD ATA_STATUS_CMD
#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE
-#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
+#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
/* Compact Flash-ATA commands */
-#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
+#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD
#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD
#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD
@@ -661,31 +732,27 @@
/**
* @}
*/
-
+
/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
* @{
*/
-
+
#define FORMAT_BIN RTC_FORMAT_BIN
#define FORMAT_BCD RTC_FORMAT_BCD
#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
-#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
-#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
-#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
+#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
-#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
-#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
-#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
-#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
-#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
+#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
+#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
-#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
@@ -693,15 +760,15 @@
#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1
#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1
-#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
-#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
+#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
+#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
/**
* @}
*/
-
+
/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
* @{
*/
@@ -722,7 +789,7 @@
* @}
*/
-
+
/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
* @{
*/
@@ -740,7 +807,7 @@
/**
* @}
*/
-
+
/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
* @{
*/
@@ -756,13 +823,13 @@
/**
* @}
*/
-
+
/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
* @{
*/
#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK
#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK
-
+
#define TIM_DMABase_CR1 TIM_DMABASE_CR1
#define TIM_DMABase_CR2 TIM_DMABASE_CR2
#define TIM_DMABase_SMCR TIM_DMABASE_SMCR
@@ -863,7 +930,7 @@
* @}
*/
-
+
/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
* @{
*/
@@ -903,7 +970,7 @@
/**
* @}
*/
-
+
/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
* @{
*/
@@ -928,7 +995,7 @@
#define ETH_MMCRFCECR 0x00000194U
#define ETH_MMCRFAECR 0x00000198U
#define ETH_MMCRGUFCR 0x000001C4U
-
+
#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
@@ -946,9 +1013,12 @@
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */
#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */
+#if defined(STM32F1)
+#else
#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */
#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */
#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */
+#endif
#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */
#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */
#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */
@@ -960,7 +1030,7 @@
/**
* @}
*/
-
+
/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
* @{
*/
@@ -975,39 +1045,39 @@
/**
* @}
- */
-
+ */
+
#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\
defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
* @{
*/
#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888
-#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888
-#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565
+#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888
+#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565
#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555
#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444
#define CM_ARGB8888 DMA2D_INPUT_ARGB8888
-#define CM_RGB888 DMA2D_INPUT_RGB888
-#define CM_RGB565 DMA2D_INPUT_RGB565
+#define CM_RGB888 DMA2D_INPUT_RGB888
+#define CM_RGB565 DMA2D_INPUT_RGB565
#define CM_ARGB1555 DMA2D_INPUT_ARGB1555
#define CM_ARGB4444 DMA2D_INPUT_ARGB4444
-#define CM_L8 DMA2D_INPUT_L8
-#define CM_AL44 DMA2D_INPUT_AL44
-#define CM_AL88 DMA2D_INPUT_AL88
-#define CM_L4 DMA2D_INPUT_L4
-#define CM_A8 DMA2D_INPUT_A8
-#define CM_A4 DMA2D_INPUT_A4
+#define CM_L8 DMA2D_INPUT_L8
+#define CM_AL44 DMA2D_INPUT_AL44
+#define CM_AL88 DMA2D_INPUT_AL88
+#define CM_L4 DMA2D_INPUT_L4
+#define CM_A8 DMA2D_INPUT_A8
+#define CM_A4 DMA2D_INPUT_A4
/**
* @}
- */
+ */
#endif /* STM32L4 || STM32F7*/
/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
* @{
*/
-
+
/**
* @}
*/
@@ -1020,11 +1090,11 @@
#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
/**
* @}
- */
+ */
/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
* @{
- */
+ */
#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef
#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef
#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
@@ -1034,12 +1104,12 @@
/*HASH Algorithm Selection*/
-#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
+#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
-#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
+#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
@@ -1047,7 +1117,7 @@
/**
* @}
*/
-
+
/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
* @{
*/
@@ -1128,6 +1198,8 @@
#define CR_OFFSET_BB PWR_CR_OFFSET_BB
#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB
+#define PMODE_BIT_NUMBER VOS_BIT_NUMBER
+#define CR_PMODE_BB CR_VOS_BB
#define DBP_BitNumber DBP_BIT_NUMBER
#define PVDE_BitNumber PVDE_BIT_NUMBER
@@ -1141,17 +1213,17 @@
#define BRE_BitNumber BRE_BIT_NUMBER
#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
-
+
/**
* @}
- */
-
+ */
+
/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
* @{
*/
#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT
-#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
-#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
+#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
+#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
/**
* @}
*/
@@ -1162,7 +1234,7 @@
#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo
/**
* @}
- */
+ */
/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
* @{
@@ -1174,31 +1246,31 @@
/**
* @}
*/
-
+
/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
* @{
- */
+ */
#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
/**
* @}
*/
-
+
/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
* @{
- */
+ */
#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
#define HAL_LTDC_Relaod HAL_LTDC_Reload
#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig
#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig
/**
* @}
- */
-
-
+ */
+
+
/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
* @{
*/
-
+
/**
* @}
*/
@@ -1213,8 +1285,8 @@
#define AES_FLAG_CCF CRYP_FLAG_CCF
/**
* @}
- */
-
+ */
+
/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
* @{
*/
@@ -1223,7 +1295,7 @@
#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM
#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC
-#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
+#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC
#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI
#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK
@@ -1231,6 +1303,7 @@
#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE
#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE
+#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE
#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
@@ -1242,7 +1315,7 @@
* @}
*/
-
+
/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
* @{
*/
@@ -1312,7 +1385,6 @@
#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
-#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
#define __HAL_ADC_JSQR ADC_JSQR
#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
@@ -1339,7 +1411,7 @@
/**
* @}
*/
-
+
/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
* @{
*/
@@ -1412,7 +1484,7 @@
#define COMP_START __HAL_COMP_ENABLE
#define COMP_STOP __HAL_COMP_DISABLE
#define COMP_LOCK __HAL_COMP_LOCK
-
+
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
@@ -1599,7 +1671,7 @@
#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
((WAVE) == DAC_WAVE_NOISE)|| \
((WAVE) == DAC_WAVE_TRIANGLE))
-
+
/**
* @}
*/
@@ -1618,11 +1690,11 @@
/**
* @}
*/
-
+
/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
* @{
*/
-
+
#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
#define __HAL_I2C_GENERATE_START I2C_GENERATE_START
#if defined(STM32F1)
@@ -1645,11 +1717,11 @@
/**
* @}
*/
-
+
/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
* @{
*/
-
+
#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
@@ -1660,7 +1732,7 @@
/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
* @{
*/
-
+
#define __IRDA_DISABLE __HAL_IRDA_DISABLE
#define __IRDA_ENABLE __HAL_IRDA_ENABLE
@@ -1669,7 +1741,7 @@
#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
-#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
+#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
/**
@@ -1698,8 +1770,8 @@
/**
* @}
*/
-
-
+
+
/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
* @{
*/
@@ -1764,7 +1836,7 @@
#if defined (STM32F4)
#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()
#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()
-#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
+#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
#else
@@ -1772,37 +1844,37 @@
#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT
#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT
#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT
-#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
+#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
#endif /* STM32F4 */
-/**
+/**
* @}
- */
-
-
+ */
+
+
/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
* @{
*/
-
+
#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI
#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
-#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
-#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
-#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
-#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
-#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
-#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
-#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
-#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
-#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
-#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
-#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
-#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
-#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
-#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
+#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
+#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
+#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
+#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
+#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
+#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
+#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
+#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
+#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
+#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
+#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
+#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
+#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
+#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
@@ -1819,7 +1891,7 @@
#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
-#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
+#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
@@ -2047,6 +2119,21 @@
#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
+
+#if defined(STM32WB)
+#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE
+#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE
+#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET
+#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET
+#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED
+#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED
+#define QSPI_IRQHandler QUADSPI_IRQHandler
+#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */
+
#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
@@ -2238,13 +2325,13 @@
#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
-#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
+#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
-#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
+#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
@@ -2297,111 +2384,111 @@
#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE
#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE
#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
-#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
+#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
-#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
+#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
-#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
+#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
-#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
+#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE
-#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
+#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE
#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET
#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET
#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE
#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE
-#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
+#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE
#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE
#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET
#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET
#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
-#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
+#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE
#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE
#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET
#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET
#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
-#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
+#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE
#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE
#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET
#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET
-#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
+#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
-#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
+#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
-#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
+#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
-#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
+#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
-#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
+#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
-#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
+#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
-#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
+#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE
#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE
#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
-#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
+#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
-#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
+#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE
#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE
#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET
#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET
#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE
-#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
+#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE
#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE
#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET
#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET
#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
-#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
+#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE
#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE
#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET
#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET
#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
-#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
+#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE
#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE
#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET
#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET
#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
-#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
+#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE
#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE
#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET
#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
-#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
+#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE
-#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
+#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE
#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE
#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET
#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET
#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
-#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
+#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE
-#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
+#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
-#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
+#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
-#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
+#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
@@ -2409,29 +2496,28 @@
#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
-#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
+#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
-#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
-#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
-#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
-#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
+#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
-#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
+#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
-#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
+#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
-#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
+#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
-#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
+#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
-#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
+#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
-#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
+#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
@@ -2447,8 +2533,6 @@
#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE
#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE
-#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
-#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE
#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE
#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE
@@ -2470,8 +2554,6 @@
#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET
#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET
-#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
-#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET
#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET
#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET
@@ -2635,7 +2717,7 @@
#define SdioClockSelection Sdmmc1ClockSelection
#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1
#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG
-#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE
+#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE
#endif
#if defined(STM32F7)
@@ -2643,6 +2725,30 @@
#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
#endif
+#if defined(STM32H7)
+#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET()
+#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE()
+
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET()
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE()
+#endif
+
#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
@@ -2696,7 +2802,12 @@
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
+#if defined(STM32L4)
+#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
+#elif defined(STM32WB) || defined(STM32G0)
+#else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
+#endif
#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1
#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL
@@ -2812,17 +2923,19 @@
/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
* @{
*/
-#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
+#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
/**
* @}
*/
-
+
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
* @{
*/
-
+#if defined (STM32G0)
+#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
+#endif
#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
@@ -2858,7 +2971,7 @@
#define IS_ALARM_MASK IS_RTC_ALARM_MASK
#define IS_TAMPER IS_RTC_TAMPER
#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE
-#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
+#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT
#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE
#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION
@@ -2883,26 +2996,26 @@
#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
-#if defined(STM32F4)
+#if defined(STM32F4) || defined(STM32F2)
#define SD_SDMMC_DISABLED SD_SDIO_DISABLED
-#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
-#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED
-#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION
-#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND
-#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT
-#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED
-#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE
-#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE
-#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE
-#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
-#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT
-#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT
-#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG
-#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG
-#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT
-#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT
-#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS
-#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT
+#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
+#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED
+#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION
+#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND
+#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT
+#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED
+#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE
+#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE
+#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE
+#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
+#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT
+#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT
+#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG
+#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG
+#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT
+#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT
+#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS
+#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT
#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND
/* alias CMSIS */
#define SDMMC1_IRQn SDIO_IRQn
@@ -2911,8 +3024,8 @@
#if defined(STM32F7) || defined(STM32L4)
#define SD_SDIO_DISABLED SD_SDMMC_DISABLED
-#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY
-#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED
+#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY
+#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED
#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION
#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND
#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT
@@ -2942,6 +3055,16 @@
#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef
#endif
+#if defined(STM32H7)
+#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
+#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
+#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
+#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback
+#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback
+#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback
+#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback
+#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback
+#endif
/**
* @}
*/
@@ -2960,7 +3083,7 @@
#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
-#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
+#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
/**
* @}
@@ -2992,7 +3115,7 @@
/**
* @}
*/
-
+
/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
* @{
*/
@@ -3004,8 +3127,8 @@
#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD
-#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
-#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
+#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
+#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
/**
* @}
@@ -3110,7 +3233,7 @@
/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
* @{
*/
-
+
#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG
@@ -3119,7 +3242,7 @@
#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
-#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
+#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE
#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE
/**
@@ -3156,11 +3279,22 @@
* @}
*/
+/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#if defined(STM32H7)
+#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow
+#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT
+#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA
+#endif
+/**
+ * @}
+ */
/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
* @{
*/
-
+
/**
* @}
*/
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief HAL module driver.
* This is the common part of the HAL initialization
*
@@ -68,11 +66,11 @@
* @{
*/
/**
- * @brief STM32F4xx HAL Driver version number V1.7.1
+ * @brief STM32F4xx HAL Driver version number V1.7.3
*/
#define __STM32F4xx_HAL_VERSION_MAIN (0x01U) /*!< [31:24] main version */
#define __STM32F4xx_HAL_VERSION_SUB1 (0x07U) /*!< [23:16] sub1 version */
-#define __STM32F4xx_HAL_VERSION_SUB2 (0x01U) /*!< [15:8] sub2 version */
+#define __STM32F4xx_HAL_VERSION_SUB2 (0x03U) /*!< [15:8] sub2 version */
#define __STM32F4xx_HAL_VERSION_RC (0x00U) /*!< [7:0] release candidate */
#define __STM32F4xx_HAL_VERSION ((__STM32F4xx_HAL_VERSION_MAIN << 24U)\
|(__STM32F4xx_HAL_VERSION_SUB1 << 16U)\
@@ -86,19 +84,19 @@
/* --- MEMRMP Register ---*/
/* Alias word address of UFB_MODE bit */
#define MEMRMP_OFFSET SYSCFG_OFFSET
-#define UFB_MODE_BIT_NUMBER POSITION_VAL(SYSCFG_MEMRMP_UFB_MODE)
+#define UFB_MODE_BIT_NUMBER SYSCFG_MEMRMP_UFB_MODE_Pos
#define UFB_MODE_BB (uint32_t)(PERIPH_BB_BASE + (MEMRMP_OFFSET * 32U) + (UFB_MODE_BIT_NUMBER * 4U))
/* --- CMPCR Register ---*/
/* Alias word address of CMP_PD bit */
#define CMPCR_OFFSET (SYSCFG_OFFSET + 0x20U)
-#define CMP_PD_BIT_NUMBER POSITION_VAL(SYSCFG_CMPCR_CMP_PD)
+#define CMP_PD_BIT_NUMBER SYSCFG_CMPCR_CMP_PD_Pos
#define CMPCR_CMP_PD_BB (uint32_t)(PERIPH_BB_BASE + (CMPCR_OFFSET * 32U) + (CMP_PD_BIT_NUMBER * 4U))
/* --- MCHDLYCR Register ---*/
/* Alias word address of BSCKSEL bit */
#define MCHDLYCR_OFFSET (SYSCFG_OFFSET + 0x30U)
-#define BSCKSEL_BIT_NUMBER POSITION_VAL(SYSCFG_MCHDLYCR_BSCKSEL)
+#define BSCKSEL_BIT_NUMBER SYSCFG_MCHDLYCR_BSCKSEL_Pos
#define MCHDLYCR_BSCKSEL_BB (uint32_t)(PERIPH_BB_BASE + (MCHDLYCR_OFFSET * 32U) + (BSCKSEL_BIT_NUMBER * 4U))
/**
* @}
@@ -110,6 +108,8 @@
* @{
*/
__IO uint32_t uwTick;
+uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
+HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */
/**
* @}
*/
@@ -125,16 +125,16 @@
*
@verbatim
===============================================================================
- ##### Initialization and de-initialization functions #####
+ ##### Initialization and Configuration functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initializes the Flash interface the NVIC allocation and initial clock
configuration. It initializes the systick also when timeout is needed
and the backup domain when enabled.
- (+) de-Initializes common part of the HAL
- (+) Configure The time base source to have 1ms time base with a dedicated
+ (+) De-Initializes common part of the HAL.
+ (+) Configure the time base source to have 1ms time base with a dedicated
Tick interrupt priority.
- (++) Systick timer is used by default as source of time base, but user
+ (++) SysTick timer is used by default as source of time base, but user
can eventually implement his proper time base source (a general purpose
timer for example or other time source), keeping in mind that Time base
duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
@@ -174,23 +174,29 @@
{
/* Configure Flash prefetch, Instruction cache, Data cache */
#if (INSTRUCTION_CACHE_ENABLE != 0U)
- __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
+ __HAL_FLASH_INSTRUCTION_CACHE_ENABLE();
#endif /* INSTRUCTION_CACHE_ENABLE */
#if (DATA_CACHE_ENABLE != 0U)
- __HAL_FLASH_DATA_CACHE_ENABLE();
+ __HAL_FLASH_DATA_CACHE_ENABLE();
#endif /* DATA_CACHE_ENABLE */
#if (PREFETCH_ENABLE != 0U)
__HAL_FLASH_PREFETCH_BUFFER_ENABLE();
#endif /* PREFETCH_ENABLE */
+ /* Set Interrupt Group Priority */
+/* MBED : moved to HAL_InitPre() */
+#if !defined (TARGET_STM32F429xI)
+ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+#endif
+
/* Use systick as time base source and configure 1ms tick (default clock after Reset is HSI) */
HAL_InitTick(TICK_INT_PRIORITY);
-
+
/* Init the low level hardware */
HAL_MspInit();
-
+
/* Return function status */
return HAL_OK;
}
@@ -226,12 +232,12 @@
}
/**
- * @brief Initializes the MSP.
+ * @brief Initialize the MSP.
* @retval None
*/
__weak void HAL_MspInit(void)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_MspInit could be implemented in the user file
*/
}
@@ -242,7 +248,7 @@
*/
__weak void HAL_MspDeInit(void)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_MspDeInit could be implemented in the user file
*/
}
@@ -256,20 +262,31 @@
* @note In the default implementation, SysTick timer is the source of time base.
* It is used to generate interrupts at regular time intervals.
* Care must be taken if HAL_Delay() is called from a peripheral ISR process,
- * The the SysTick interrupt must have higher priority (numerically lower)
+ * The SysTick interrupt must have higher priority (numerically lower)
* than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
* The function is declared as __weak to be overwritten in case of other
* implementation in user file.
- * @param TickPriority: Tick interrupt priority.
+ * @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
- /*Configure the SysTick to have interrupt in 1ms time basis*/
- HAL_SYSTICK_Config(SystemCoreClock/1000U);
+ /* Configure the SysTick to have interrupt in 1ms time basis*/
+ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
+ {
+ return HAL_ERROR;
+ }
- /*Configure the SysTick IRQ priority */
- HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
+ /* Configure the SysTick IRQ priority */
+ if (TickPriority < (1UL << __NVIC_PRIO_BITS))
+ {
+ HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
+ uwTickPrio = TickPriority;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
/* Return function status */
return HAL_OK;
@@ -306,14 +323,14 @@
* @brief This function is called to increment a global variable "uwTick"
* used as application time base.
* @note In the default implementation, this variable is incremented each 1ms
- * in Systick ISR.
+ * in SysTick ISR.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
- uwTick++;
+ uwTick += uwTickFreq;
}
/**
@@ -328,6 +345,44 @@
}
/**
+ * @brief This function returns a tick priority.
+ * @retval tick priority
+ */
+uint32_t HAL_GetTickPrio(void)
+{
+ return uwTickPrio;
+}
+
+/**
+ * @brief Set new tick Freq.
+ * @retval Status
+ */
+HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ assert_param(IS_TICKFREQ(Freq));
+
+ if (uwTickFreq != Freq)
+ {
+ uwTickFreq = Freq;
+
+ /* Apply the new tick Freq */
+ status = HAL_InitTick(uwTickPrio);
+ }
+
+ return status;
+}
+
+/**
+ * @brief Return tick frequency.
+ * @retval tick period in Hz
+ */
+HAL_TickFreqTypeDef HAL_GetTickFreq(void)
+{
+ return uwTickFreq;
+}
+
+/**
* @brief This function provides minimum delay (in milliseconds) based
* on variable incremented.
* @note In the default implementation , SysTick timer is the source of time base.
@@ -335,20 +390,20 @@
* is incremented.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
- * @param Delay: specifies the delay time length, in milliseconds.
+ * @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
-__weak void HAL_Delay(__IO uint32_t Delay)
+__weak void HAL_Delay(uint32_t Delay)
{
uint32_t tickstart = HAL_GetTick();
uint32_t wait = Delay;
-
- /* Add a period to guarantee minimum wait */
+
+ /* Add a freq to guarantee minimum wait */
if (wait < HAL_MAX_DELAY)
{
- wait++;
+ wait += (uint32_t)(uwTickFreq);
}
-
+
while((HAL_GetTick() - tickstart) < wait)
{
}
@@ -392,7 +447,7 @@
*/
uint32_t HAL_GetHalVersion(void)
{
- return __STM32F4xx_HAL_VERSION;
+ return __STM32F4xx_HAL_VERSION;
}
/**
@@ -401,7 +456,7 @@
*/
uint32_t HAL_GetREVID(void)
{
- return((DBGMCU->IDCODE) >> 16U);
+ return((DBGMCU->IDCODE) >> 16U);
}
/**
@@ -410,7 +465,7 @@
*/
uint32_t HAL_GetDEVID(void)
{
- return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
+ return((DBGMCU->IDCODE) & IDCODE_DEVID_MASK);
}
/**
@@ -491,7 +546,7 @@
/**
* @brief Return the unique device identifier (UID based on 96 bits)
- * @param UID: pointer to 3 words array.
+ * @param UID pointer to 3 words array.
* @retval Device identifier
*/
void HAL_GetUID(uint32_t *UID)
@@ -530,7 +585,6 @@
*/
void HAL_DisableMemorySwappingBank(void)
{
-
*(__IO uint32_t *)UFB_MODE_BB = (uint32_t)DISABLE;
}
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F469xx || STM32F479xx */
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief This file contains all the functions prototypes for the HAL
* module driver.
******************************************************************************
@@ -58,6 +56,28 @@
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
+/** @defgroup HAL_Exported_Constants HAL Exported Constants
+ * @{
+ */
+
+/** @defgroup HAL_TICK_FREQ Tick Frequency
+ * @{
+ */
+typedef enum
+{
+ HAL_TICK_FREQ_10HZ = 100U,
+ HAL_TICK_FREQ_100HZ = 10U,
+ HAL_TICK_FREQ_1KHZ = 1U,
+ HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
+} HAL_TickFreqTypeDef;
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
/* Exported macro ------------------------------------------------------------*/
/** @defgroup HAL_Exported_Macros HAL Exported Macros
* @{
@@ -183,6 +203,16 @@
* @}
*/
+/** @defgroup HAL_Private_Macros HAL Private Macros
+ * @{
+ */
+#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \
+ ((FREQ) == HAL_TICK_FREQ_100HZ) || \
+ ((FREQ) == HAL_TICK_FREQ_1KHZ))
+/**
+ * @}
+ */
+
/* Exported functions --------------------------------------------------------*/
/** @addtogroup HAL_Exported_Functions
* @{
@@ -190,8 +220,7 @@
/** @addtogroup HAL_Exported_Functions_Group1
* @{
*/
-/* Initialization and de-initialization functions ******************************/
-HAL_StatusTypeDef HAL_InitPre(void);
+/* Initialization and Configuration functions ******************************/
HAL_StatusTypeDef HAL_Init(void);
HAL_StatusTypeDef HAL_DeInit(void);
void HAL_MspInit(void);
@@ -206,8 +235,11 @@
*/
/* Peripheral Control functions ************************************************/
void HAL_IncTick(void);
-void HAL_Delay(__IO uint32_t Delay);
+void HAL_Delay(uint32_t Delay);
uint32_t HAL_GetTick(void);
+uint32_t HAL_GetTickPrio(void);
+HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
+HAL_TickFreqTypeDef HAL_GetTickFreq(void);
void HAL_SuspendTick(void);
void HAL_ResumeTick(void);
uint32_t HAL_GetHalVersion(void);
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_adc.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_adc.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_adc.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) peripheral: * + Initialization and de-initialization functions @@ -251,7 +249,7 @@ * External trigger source and edge, DMA continuous request after the * last transfer and End of conversion selection). * - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval HAL status */ @@ -329,7 +327,7 @@ /** * @brief Deinitializes the ADCx peripheral registers to their default reset values. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval HAL status */ @@ -376,7 +374,7 @@ /** * @brief Initializes the ADC MSP. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ @@ -391,7 +389,7 @@ /** * @brief DeInitializes the ADC MSP. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ @@ -430,7 +428,7 @@ /** * @brief Enables ADC and starts conversion of the regular channels. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval HAL status */ @@ -536,7 +534,7 @@ * * @note Caution: This function will stop also injected channels. * - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * * @retval HAL status. @@ -579,9 +577,9 @@ * In this case, DMA resets the flag EOC and polling cannot be * performed on each conversion. Nevertheless, polling can still * be performed on the complete sequence. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param Timeout: Timeout value in millisecond. + * @param Timeout Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) @@ -660,13 +658,13 @@ /** * @brief Poll for conversion event - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param EventType: the ADC event type. + * @param EventType the ADC event type. * This parameter can be one of the following values: * @arg ADC_AWD_EVENT: ADC Analog watch Dog event. * @arg ADC_OVR_EVENT: ADC Overrun event. - * @param Timeout: Timeout value in millisecond. + * @param Timeout Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout) @@ -727,7 +725,7 @@ /** * @brief Enables the interrupt and starts ADC conversion of regular channels. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval HAL status. */ @@ -836,7 +834,7 @@ * * @note Caution: This function will stop also injected channels. * - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval HAL status. */ @@ -873,7 +871,7 @@ /** * @brief Handles ADC interrupt request - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ @@ -1016,10 +1014,10 @@ /** * @brief Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param pData: The destination Buffer address. - * @param Length: The length of data to be transferred from ADC peripheral to memory. + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from ADC peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) @@ -1143,7 +1141,7 @@ /** * @brief Disables ADC DMA (Single-ADC mode) and disables ADC peripheral - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval HAL status */ @@ -1189,7 +1187,7 @@ /** * @brief Gets the converted value from data register of regular channel. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval Converted value */ @@ -1201,7 +1199,7 @@ /** * @brief Regular conversion complete callback in non blocking mode - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ @@ -1216,7 +1214,7 @@ /** * @brief Regular conversion half DMA transfer callback in non blocking mode - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ @@ -1231,7 +1229,7 @@ /** * @brief Analog watchdog callback in non blocking mode - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ @@ -1252,7 +1250,7 @@ * - If needed, restart a new ADC conversion using function * "HAL_ADC_Start_DMA()" * (this function is also clearing overrun flag) - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ @@ -1289,9 +1287,9 @@ /** * @brief Configures for the selected ADC regular channel its corresponding * rank in the sequencer and its sample time. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param sConfig: ADC configuration structure. + * @param sConfig ADC configuration structure. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) @@ -1400,9 +1398,9 @@ * Considering that registers write delay may happen due to * bus activity, this might cause an uncertainty on the * effective timing of the new programmed threshold values. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param AnalogWDGConfig : pointer to an ADC_AnalogWDGConfTypeDef structure + * @param AnalogWDGConfig pointer to an ADC_AnalogWDGConfTypeDef structure * that contains the configuration information of ADC analog watchdog. * @retval HAL status */ @@ -1484,7 +1482,7 @@ /** * @brief return the ADC state - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval HAL state */ @@ -1496,7 +1494,7 @@ /** * @brief Return the ADC error code - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval ADC Error Code */ @@ -1516,7 +1514,7 @@ /** * @brief Initializes the ADCx peripheral according to the specified parameters * in the ADC_InitStruct without initializing the ADC MSP. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ @@ -1604,7 +1602,7 @@ /** * @brief DMA transfer complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1657,7 +1655,7 @@ /** * @brief DMA half transfer complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1670,7 +1668,7 @@ /** * @brief DMA error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_adc.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_adc.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_adc.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file containing functions prototypes of ADC HAL library. ****************************************************************************** * @attention @@ -455,60 +453,60 @@ */ /** @brief Reset ADC handle state - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval None */ #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET) /** * @brief Enable the ADC peripheral. - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval None */ #define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON) /** * @brief Disable the ADC peripheral. - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval None */ #define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON) /** * @brief Enable the ADC end of conversion interrupt. - * @param __HANDLE__: specifies the ADC Handle. - * @param __INTERRUPT__: ADC Interrupt. + * @param __HANDLE__ specifies the ADC Handle. + * @param __INTERRUPT__ ADC Interrupt. * @retval None */ #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__)) /** * @brief Disable the ADC end of conversion interrupt. - * @param __HANDLE__: specifies the ADC Handle. - * @param __INTERRUPT__: ADC interrupt. + * @param __HANDLE__ specifies the ADC Handle. + * @param __INTERRUPT__ ADC interrupt. * @retval None */ #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__)) /** @brief Check if the specified ADC interrupt source is enabled or disabled. - * @param __HANDLE__: specifies the ADC Handle. - * @param __INTERRUPT__: specifies the ADC interrupt source to check. + * @param __HANDLE__ specifies the ADC Handle. + * @param __INTERRUPT__ specifies the ADC interrupt source to check. * @retval The new state of __IT__ (TRUE or FALSE). */ #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) /** * @brief Clear the ADC's pending flags. - * @param __HANDLE__: specifies the ADC Handle. - * @param __FLAG__: ADC flag. + * @param __HANDLE__ specifies the ADC Handle. + * @param __FLAG__ ADC flag. * @retval None */ #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__)) /** * @brief Get the selected ADC's flag status. - * @param __HANDLE__: specifies the ADC Handle. - * @param __FLAG__: ADC flag. + * @param __HANDLE__ specifies the ADC Handle. + * @param __FLAG__ ADC flag. * @retval None */ #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) @@ -616,7 +614,7 @@ /** * @brief Verification of ADC state: enabled or disabled - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval SET (ADC enabled) or RESET (ADC disabled) */ #define ADC_IS_ENABLE(__HANDLE__) \ @@ -626,7 +624,7 @@ /** * @brief Test if conversion trigger of regular group is software start * or external trigger. - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval SET (software start) or RESET (external trigger) */ #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ @@ -635,7 +633,7 @@ /** * @brief Test if conversion trigger of injected group is software start * or external trigger. - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval SET (software start) or RESET (external trigger) */ #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ @@ -652,7 +650,7 @@ /** * @brief Clear ADC error code (set it to error code: "no error") - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval None */ #define ADC_CLEAR_ERRORCODE(__HANDLE__) \ @@ -742,89 +740,89 @@ /** * @brief Set ADC Regular channel sequence length. - * @param _NbrOfConversion_: Regular channel sequence length. + * @param _NbrOfConversion_ Regular channel sequence length. * @retval None */ #define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1U) << 20U) /** * @brief Set the ADC's sample time for channel numbers between 10 and 18. - * @param _SAMPLETIME_: Sample time parameter. - * @param _CHANNELNB_: Channel number. + * @param _SAMPLETIME_ Sample time parameter. + * @param _CHANNELNB_ Channel number. * @retval None */ #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10U))) /** * @brief Set the ADC's sample time for channel numbers between 0 and 9. - * @param _SAMPLETIME_: Sample time parameter. - * @param _CHANNELNB_: Channel number. + * @param _SAMPLETIME_ Sample time parameter. + * @param _CHANNELNB_ Channel number. * @retval None */ #define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3U * ((uint32_t)((uint16_t)(_CHANNELNB_))))) /** * @brief Set the selected regular channel rank for rank between 1 and 6. - * @param _CHANNELNB_: Channel number. - * @param _RANKNB_: Rank number. + * @param _CHANNELNB_ Channel number. + * @param _RANKNB_ Rank number. * @retval None */ #define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 1U))) /** * @brief Set the selected regular channel rank for rank between 7 and 12. - * @param _CHANNELNB_: Channel number. - * @param _RANKNB_: Rank number. + * @param _CHANNELNB_ Channel number. + * @param _RANKNB_ Rank number. * @retval None */ #define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 7U))) /** * @brief Set the selected regular channel rank for rank between 13 and 16. - * @param _CHANNELNB_: Channel number. - * @param _RANKNB_: Rank number. + * @param _CHANNELNB_ Channel number. + * @param _RANKNB_ Rank number. * @retval None */ #define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * ((_RANKNB_) - 13U))) /** * @brief Enable ADC continuous conversion mode. - * @param _CONTINUOUS_MODE_: Continuous mode. + * @param _CONTINUOUS_MODE_ Continuous mode. * @retval None */ #define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1U) /** * @brief Configures the number of discontinuous conversions for the regular group channels. - * @param _NBR_DISCONTINUOUSCONV_: Number of discontinuous conversions. + * @param _NBR_DISCONTINUOUSCONV_ Number of discontinuous conversions. * @retval None */ -#define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1U) << POSITION_VAL(ADC_CR1_DISCNUM)) +#define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1U) << ADC_CR1_DISCNUM_Pos) /** * @brief Enable ADC scan mode. - * @param _SCANCONV_MODE_: Scan conversion mode. + * @param _SCANCONV_MODE_ Scan conversion mode. * @retval None */ #define ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8U) /** * @brief Enable the ADC end of conversion selection. - * @param _EOCSelection_MODE_: End of conversion selection mode. + * @param _EOCSelection_MODE_ End of conversion selection mode. * @retval None */ #define ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10U) /** * @brief Enable the ADC DMA continuous request. - * @param _DMAContReq_MODE_: DMA continuous request mode. + * @param _DMAContReq_MODE_ DMA continuous request mode. * @retval None */ #define ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9U) /** * @brief Return resolution bits in CR1 register. - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval None */ #define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES)
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_adc_ex.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_adc_ex.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_adc_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief This file provides firmware functions to manage the following * functionalities of the ADC extension peripheral: * + Extended features functions @@ -170,7 +168,7 @@ /** * @brief Enables the selected ADC software start conversion of the injected channels. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval HAL status */ @@ -264,7 +262,7 @@ /** * @brief Enables the interrupt and starts ADC conversion of injected channels. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * * @retval HAL status. @@ -369,7 +367,7 @@ * @note If injected group mode auto-injection is enabled, * function HAL_ADC_Stop must be used. * @note In case of auto-injection mode, HAL_ADC_Stop must be used. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval None */ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) @@ -421,9 +419,9 @@ /** * @brief Poll for injected conversion complete - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param Timeout: Timeout value in millisecond. + * @param Timeout Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) @@ -490,7 +488,7 @@ * injected and regular groups, and disable the ADC. * @note If injected group mode auto-injection is enabled, * function HAL_ADC_Stop must be used. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval None */ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) @@ -545,9 +543,9 @@ /** * @brief Gets the converted value from data register of injected channel. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param InjectedRank: the ADC injected rank. + * @param InjectedRank the ADC injected rank. * This parameter can be one of the following values: * @arg ADC_INJECTED_RANK_1: Injected Channel1 selected * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected @@ -600,10 +598,10 @@ * * @note Caution: This function must be used only with the ADC master. * - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param pData: Pointer to buffer in which transferred from ADC peripheral to memory will be stored. - * @param Length: The length of data to be transferred from ADC peripheral to memory. + * @param pData Pointer to buffer in which transferred from ADC peripheral to memory will be stored. + * @param Length The length of data to be transferred from ADC peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) @@ -721,7 +719,7 @@ /** * @brief Disables ADC DMA (multi-ADC mode) and disables ADC peripheral - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval HAL status */ @@ -774,7 +772,7 @@ /** * @brief Returns the last ADC1, ADC2 and ADC3 regular conversions results * data in the selected multi mode. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval The converted data value. */ @@ -793,7 +791,7 @@ /** * @brief Injected conversion complete callback in non blocking mode - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ @@ -809,9 +807,9 @@ /** * @brief Configures for the selected ADC injected channel its corresponding * rank in the sequencer and its sample time. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param sConfigInjected: ADC configuration structure for injected channel. + * @param sConfigInjected ADC configuration structure for injected channel. * @retval None */ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected) @@ -972,9 +970,9 @@ /** * @brief Configures the ADC multi-mode - * @param hadc : pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param multimode : pointer to an ADC_MultiModeTypeDef structure that contains + * @param multimode pointer to an ADC_MultiModeTypeDef structure that contains * the configuration information for multimode. * @retval HAL status */ @@ -1021,7 +1019,7 @@ /** * @brief DMA transfer complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1074,7 +1072,7 @@ /** * @brief DMA half transfer complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1087,7 +1085,7 @@ /** * @brief DMA error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_adc_ex.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_adc_ex.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_adc_ex.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief Header file of ADC HAL module.
******************************************************************************
* @attention
@@ -232,10 +230,14 @@
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || \
defined(STM32F410Rx) || defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || \
- defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
+ defined(STM32F412Cx)
#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_16)
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx || STM32F412Zx ||
- STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+ STM32F412Vx || STM32F412Rx || STM32F412Cx */
+
+#if defined(STM32F413xx) || defined(STM32F423xx)
+#define ADC_CHANNEL_TEMPSENSOR ((uint32_t)ADC_CHANNEL_18)
+#endif /* STM32F413xx || STM32F423xx */
#if defined(STM32F411xE) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
@@ -377,9 +379,9 @@
/**
* @brief Set the selected injected Channel rank.
- * @param _CHANNELNB_: Channel number.
- * @param _RANKNB_: Rank number.
- * @param _JSQR_JL_: Sequence length.
+ * @param _CHANNELNB_ Channel number.
+ * @param _RANKNB_ Rank number.
+ * @param _JSQR_JL_ Sequence length.
* @retval None
*/
#define ADC_JSQR(_CHANNELNB_, _RANKNB_, _JSQR_JL_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5U * (uint8_t)(((_RANKNB_) + 3U) - (_JSQR_JL_))))
@@ -387,7 +389,7 @@
/**
* @brief Defines if the selected ADC is within ADC common register ADC123 or ADC1
* if available (ADC2, ADC3 availability depends on STM32 product)
- * @param __HANDLE__: ADC handle
+ * @param __HANDLE__ ADC handle
* @retval Common control register ADC123 or ADC1
*/
#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx) || defined(STM32F427xx) || defined(STM32F429xx) || defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_can.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_can.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,82 +2,135 @@
******************************************************************************
* @file stm32f4xx_hal_can.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
- * @brief This file provides firmware functions to manage the following
+ * @brief CAN HAL module driver.
+ * This file provides firmware functions to manage the following
* functionalities of the Controller Area Network (CAN) peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral Control functions
+ * + Initialization and de-initialization functions
+ * + Configuration functions
+ * + Control functions
+ * + Interrupts management
+ * + Callbacks functions
* + Peripheral State and Error functions
*
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
- [..]
- (#) Enable the CAN controller interface clock using
- __HAL_RCC_CAN1_CLK_ENABLE() for CAN1, __HAL_RCC_CAN2_CLK_ENABLE() for CAN2
- and __HAL_RCC_CAN3_CLK_ENABLE() for CAN3
- -@- In case you are using CAN2 only, you have to enable the CAN1 clock.
-
- (#) CAN pins configuration
- (++) Enable the clock for the CAN GPIOs using the following function:
- __GPIOx_CLK_ENABLE()
- (++) Connect and configure the involved CAN pins to AF9 using the
- following function HAL_GPIO_Init()
-
- (#) Initialize and configure the CAN using CAN_Init() function.
-
- (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function.
+ [..]
+ (#) Initialize the CAN low level resources by implementing the
+ HAL_CAN_MspInit():
+ (++) Enable the CAN interface clock using __HAL_RCC_CANx_CLK_ENABLE()
+ (++) Configure CAN pins
+ (+++) Enable the clock for the CAN GPIOs
+ (+++) Configure CAN pins as alternate function open-drain
+ (++) In case of using interrupts (e.g. HAL_CAN_ActivateNotification())
+ (+++) Configure the CAN interrupt priority using
+ HAL_NVIC_SetPriority()
+ (+++) Enable the CAN IRQ handler using HAL_NVIC_EnableIRQ()
+ (+++) In CAN IRQ handler, call HAL_CAN_IRQHandler()
+
+ (#) Initialize the CAN peripheral using HAL_CAN_Init() function. This
+ function resorts to HAL_CAN_MspInit() for low-level initialization.
+
+ (#) Configure the reception filters using the following configuration
+ functions:
+ (++) HAL_CAN_ConfigFilter()
+
+ (#) Start the CAN module using HAL_CAN_Start() function. At this level
+ the node is active on the bus: it receive messages, and can send
+ messages.
- (#) Or transmit the desired CAN frame using HAL_CAN_Transmit_IT() function.
-
- (#) Receive a CAN frame using HAL_CAN_Receive() function.
+ (#) To manage messages transmission, the following Tx control functions
+ can be used:
+ (++) HAL_CAN_AddTxMessage() to request transmission of a new
+ message.
+ (++) HAL_CAN_AbortTxRequest() to abort transmission of a pending
+ message.
+ (++) HAL_CAN_GetTxMailboxesFreeLevel() to get the number of free Tx
+ mailboxes.
+ (++) HAL_CAN_IsTxMessagePending() to check if a message is pending
+ in a Tx mailbox.
+ (++) HAL_CAN_GetTxTimestamp() to get the timestamp of Tx message
+ sent, if time triggered communication mode is enabled.
- (#) Or receive a CAN frame using HAL_CAN_Receive_IT() function.
+ (#) When a message is received into the CAN Rx FIFOs, it can be retrieved
+ using the HAL_CAN_GetRxMessage() function. The function
+ HAL_CAN_GetRxFifoFillLevel() allows to know how many Rx message are
+ stored in the Rx Fifo.
+
+ (#) Calling the HAL_CAN_Stop() function stops the CAN module.
+
+ (#) The deinitialization is achieved with HAL_CAN_DeInit() function.
+
+
+ *** Polling mode operation ***
+ ==============================
+ [..]
+ (#) Reception:
+ (++) Monitor reception of message using HAL_CAN_GetRxFifoFillLevel()
+ until at least one message is received.
+ (++) Then get the message using HAL_CAN_GetRxMessage().
- *** Polling mode IO operation ***
- =================================
- [..]
- (+) Start the CAN peripheral transmission and wait the end of this operation
- using HAL_CAN_Transmit(), at this stage user can specify the value of timeout
- according to his end application
- (+) Start the CAN peripheral reception and wait the end of this operation
- using HAL_CAN_Receive(), at this stage user can specify the value of timeout
- according to his end application
-
- *** Interrupt mode IO operation ***
- ===================================
- [..]
- (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT()
- (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT()
- (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine
- (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can
- add his own code by customization of function pointer HAL_CAN_TxCpltCallback
- (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_CAN_ErrorCallback
-
- *** CAN HAL driver macros list ***
- =============================================
- [..]
- Below the list of most used macros in CAN HAL driver.
-
- (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts
- (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts
- (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled
- (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags
- (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status
-
- [..]
- (@) You can refer to the CAN HAL driver header file for more useful macros
-
+ (#) Transmission:
+ (++) Monitor the Tx mailboxes availability until at least one Tx
+ mailbox is free, using HAL_CAN_GetTxMailboxesFreeLevel().
+ (++) Then request transmission of a message using
+ HAL_CAN_AddTxMessage().
+
+
+ *** Interrupt mode operation ***
+ ================================
+ [..]
+ (#) Notifications are activated using HAL_CAN_ActivateNotification()
+ function. Then, the process can be controlled through the
+ available user callbacks: HAL_CAN_xxxCallback(), using same APIs
+ HAL_CAN_GetRxMessage() and HAL_CAN_AddTxMessage().
+
+ (#) Notifications can be deactivated using
+ HAL_CAN_DeactivateNotification() function.
+
+ (#) Special care should be taken for CAN_IT_RX_FIFO0_MSG_PENDING and
+ CAN_IT_RX_FIFO1_MSG_PENDING notifications. These notifications trig
+ the callbacks HAL_CAN_RxFIFO0MsgPendingCallback() and
+ HAL_CAN_RxFIFO1MsgPendingCallback(). User has two possible options
+ here.
+ (++) Directly get the Rx message in the callback, using
+ HAL_CAN_GetRxMessage().
+ (++) Or deactivate the notification in the callback without
+ getting the Rx message. The Rx message can then be got later
+ using HAL_CAN_GetRxMessage(). Once the Rx message have been
+ read, the notification can be activated again.
+
+
+ *** Sleep mode ***
+ ==================
+ [..]
+ (#) The CAN peripheral can be put in sleep mode (low power), using
+ HAL_CAN_RequestSleep(). The sleep mode will be entered as soon as the
+ current CAN activity (transmission or reception of a CAN frame) will
+ be completed.
+
+ (#) A notification can be activated to be informed when the sleep mode
+ will be entered.
+
+ (#) It can be checked if the sleep mode is entered using
+ HAL_CAN_IsSleepActive().
+ Note that the CAN state (accessible from the API HAL_CAN_GetState())
+ is HAL_CAN_STATE_SLEEP_PENDING as soon as the sleep mode request is
+ submitted (the sleep mode is not yet entered), and become
+ HAL_CAN_STATE_SLEEP_ACTIVE when the sleep mode is effective.
+
+ (#) The wake-up from sleep mode can be trigged by two ways:
+ (++) Using HAL_CAN_WakeUp(). When returning from this function,
+ the sleep mode is exited (if return status is HAL_OK).
+ (++) When a start of Rx CAN frame is detected by the CAN peripheral,
+ if automatic wake up mode is enabled.
+
@endverbatim
-
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -111,586 +164,622 @@
* @{
*/
+#if defined(CAN1)
+
/** @defgroup CAN CAN
* @brief CAN driver modules
* @{
- */
-
-#ifdef HAL_CAN_MODULE_ENABLED
+ */
+
+#ifdef HAL_CAN_MODULE_ENABLED
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
- defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
- defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
- defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
- defined(STM32F423xx)
-
+#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
+ #error "The CAN driver cannot be used with its legacy, Please enable only one CAN module at once"
+#endif
+
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/** @addtogroup CAN_Private_Constants
+/** @defgroup CAN_Private_Constants CAN Private Constants
* @{
*/
-#define CAN_TIMEOUT_VALUE 10U
+#define CAN_TIMEOUT_VALUE 10U
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup CAN_Private_Functions
- * @{
- */
-static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber);
-static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan);
-/**
- * @}
- */
+/* Exported functions --------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
/** @defgroup CAN_Exported_Functions CAN Exported Functions
* @{
*/
-/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
+/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
*
-@verbatim
+@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
==============================================================================
[..] This section provides functions allowing to:
- (+) Initialize and configure the CAN.
- (+) De-initialize the CAN.
-
+ (+) HAL_CAN_Init : Initialize and configure the CAN.
+ (+) HAL_CAN_DeInit : De-initialize the CAN.
+ (+) HAL_CAN_MspInit : Initialize the CAN MSP.
+ (+) HAL_CAN_MspDeInit : DeInitialize the CAN MSP.
+
@endverbatim
* @{
*/
-
+
/**
* @brief Initializes the CAN peripheral according to the specified
* parameters in the CAN_InitStruct.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
+HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan)
{
- uint32_t InitStatus = CAN_INITSTATUS_FAILED;
uint32_t tickstart = 0U;
-
+
/* Check CAN handle */
- if(hcan == NULL)
+ if (hcan == NULL)
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
-
+
/* Check the parameters */
assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
- assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM));
- assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM));
- assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM));
- assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART));
- assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM));
- assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TimeTriggeredMode));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoBusOff));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoWakeUp));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoRetransmission));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ReceiveFifoLocked));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TransmitFifoPriority));
assert_param(IS_CAN_MODE(hcan->Init.Mode));
- assert_param(IS_CAN_SJW(hcan->Init.SJW));
- assert_param(IS_CAN_BS1(hcan->Init.BS1));
- assert_param(IS_CAN_BS2(hcan->Init.BS2));
+ assert_param(IS_CAN_SJW(hcan->Init.SyncJumpWidth));
+ assert_param(IS_CAN_BS1(hcan->Init.TimeSeg1));
+ assert_param(IS_CAN_BS2(hcan->Init.TimeSeg2));
assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));
-
- if(hcan->State == HAL_CAN_STATE_RESET)
+ if (hcan->State == HAL_CAN_STATE_RESET)
{
- /* Allocate lock resource and initialize it */
- hcan->Lock = HAL_UNLOCKED;
- /* Init the low level hardware */
+ /* Init the low level hardware: CLOCK, NVIC */
HAL_CAN_MspInit(hcan);
}
-
- /* Initialize the CAN state*/
- hcan->State = HAL_CAN_STATE_BUSY;
-
+
/* Exit from sleep mode */
- hcan->Instance->MCR &= (~(uint32_t)CAN_MCR_SLEEP);
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
- /* Request initialisation */
- hcan->Instance->MCR |= CAN_MCR_INRQ ;
-
/* Get tick */
tickstart = HAL_GetTick();
- /* Wait the acknowledge */
- while((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
+ /* Check Sleep mode leave acknowledge */
+ while ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET)
{
- if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE)
+ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
{
- hcan->State= HAL_CAN_STATE_TIMEOUT;
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
- return HAL_TIMEOUT;
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_ERROR;
+
+ return HAL_ERROR;
}
}
- /* Check acknowledge */
- if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
- {
- /* Set the time triggered communication mode */
- if (hcan->Init.TTCM == ENABLE)
- {
- hcan->Instance->MCR |= CAN_MCR_TTCM;
- }
- else
- {
- hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TTCM;
- }
-
- /* Set the automatic bus-off management */
- if (hcan->Init.ABOM == ENABLE)
- {
- hcan->Instance->MCR |= CAN_MCR_ABOM;
- }
- else
- {
- hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_ABOM;
- }
-
- /* Set the automatic wake-up mode */
- if (hcan->Init.AWUM == ENABLE)
- {
- hcan->Instance->MCR |= CAN_MCR_AWUM;
- }
- else
- {
- hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_AWUM;
- }
-
- /* Set the no automatic retransmission */
- if (hcan->Init.NART == ENABLE)
- {
- hcan->Instance->MCR |= CAN_MCR_NART;
- }
- else
- {
- hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_NART;
- }
-
- /* Set the receive FIFO locked mode */
- if (hcan->Init.RFLM == ENABLE)
- {
- hcan->Instance->MCR |= CAN_MCR_RFLM;
- }
- else
- {
- hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_RFLM;
- }
-
- /* Set the transmit FIFO priority */
- if (hcan->Init.TXFP == ENABLE)
- {
- hcan->Instance->MCR |= CAN_MCR_TXFP;
- }
- else
- {
- hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TXFP;
- }
-
- /* Set the bit timing register */
- hcan->Instance->BTR = (uint32_t)((uint32_t)hcan->Init.Mode) | \
- ((uint32_t)hcan->Init.SJW) | \
- ((uint32_t)hcan->Init.BS1) | \
- ((uint32_t)hcan->Init.BS2) | \
- ((uint32_t)hcan->Init.Prescaler - 1U);
-
- /* Request leave initialisation */
- hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ;
+ /* Request initialisation */
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
/* Get tick */
tickstart = HAL_GetTick();
- /* Wait the acknowledge */
- while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
- {
- if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE)
- {
- hcan->State= HAL_CAN_STATE_TIMEOUT;
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
- return HAL_TIMEOUT;
- }
- }
+ /* Wait initialisation acknowledge */
+ while ((hcan->Instance->MSR & CAN_MSR_INAK) == RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
- /* Check acknowledged */
- if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
- {
- InitStatus = CAN_INITSTATUS_SUCCESS;
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_ERROR;
+
+ return HAL_ERROR;
}
}
-
- if(InitStatus == CAN_INITSTATUS_SUCCESS)
+
+ /* Set the time triggered communication mode */
+ if (hcan->Init.TimeTriggeredMode == ENABLE)
{
- /* Set CAN error code to none */
- hcan->ErrorCode = HAL_CAN_ERROR_NONE;
-
- /* Initialize the CAN state */
- hcan->State = HAL_CAN_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
}
else
{
- /* Initialize the CAN state */
- hcan->State = HAL_CAN_STATE_ERROR;
-
- /* Return function status */
- return HAL_ERROR;
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
}
-}
-/**
- * @brief Configures the CAN reception filter according to the specified
- * parameters in the CAN_FilterInitStruct.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @param sFilterConfig: pointer to a CAN_FilterConfTypeDef structure that
- * contains the filter configuration information.
- * @retval None
- */
-HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig)
-{
- uint32_t filternbrbitpos = 0U;
- CAN_TypeDef *can_ip;
-
- /* Prevent unused argument(s) compilation warning */
- UNUSED(hcan);
+ /* Set the automatic bus-off management */
+ if (hcan->Init.AutoBusOff == ENABLE)
+ {
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
+ }
+ else
+ {
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
+ }
- /* Check the parameters */
- assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber));
- assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));
- assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));
- assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));
- assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation));
- assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber));
-
- filternbrbitpos = 1U << sFilterConfig->FilterNumber;
-#if defined (CAN3)
- /* Check the CAN instance */
- if(hcan->Instance == CAN3)
- {
- can_ip = CAN3;
+ /* Set the automatic wake-up mode */
+ if (hcan->Init.AutoWakeUp == ENABLE)
+ {
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
}
else
{
- can_ip = CAN1;
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
}
-#else
- can_ip = CAN1;
-#endif
-
- /* Initialisation mode for the filter */
- can_ip->FMR |= (uint32_t)CAN_FMR_FINIT;
-
-#if defined (CAN2)
- /* Select the start slave bank */
- can_ip->FMR &= ~((uint32_t)CAN_FMR_CAN2SB);
- can_ip->FMR |= (uint32_t)(sFilterConfig->BankNumber << 8U);
-#endif
-
- /* Filter Deactivation */
- can_ip->FA1R &= ~(uint32_t)filternbrbitpos;
- /* Filter Scale */
- if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
+ /* Set the automatic retransmission */
+ if (hcan->Init.AutoRetransmission == ENABLE)
{
- /* 16-bit scale for the filter */
- can_ip->FS1R &= ~(uint32_t)filternbrbitpos;
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART);
+ }
+ else
+ {
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_NART);
+ }
- /* First 16-bit identifier and First 16-bit mask */
- /* Or First 16-bit identifier and Second 16-bit identifier */
- can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
- ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
- (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
-
- /* Second 16-bit identifier and Second 16-bit mask */
- /* Or Third 16-bit identifier and Fourth 16-bit identifier */
- can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
- ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
- (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh);
+ /* Set the receive FIFO locked mode */
+ if (hcan->Init.ReceiveFifoLocked == ENABLE)
+ {
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
+ }
+ else
+ {
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
}
- if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
+ /* Set the transmit FIFO priority */
+ if (hcan->Init.TransmitFifoPriority == ENABLE)
{
- /* 32-bit scale for the filter */
- can_ip->FS1R |= filternbrbitpos;
-
- /* 32-bit identifier or First 32-bit identifier */
- can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
- ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
- (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
- /* 32-bit mask or Second 32-bit identifier */
- can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
- ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
- (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow);
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
+ }
+ else
+ {
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
}
- /* Filter Mode */
- if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
- {
- /*Id/Mask mode for the filter*/
- can_ip->FM1R &= ~(uint32_t)filternbrbitpos;
- }
- else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
- {
- /*Identifier list mode for the filter*/
- can_ip->FM1R |= (uint32_t)filternbrbitpos;
- }
+ /* Set the bit timing register */
+ WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode |
+ hcan->Init.SyncJumpWidth |
+ hcan->Init.TimeSeg1 |
+ hcan->Init.TimeSeg2 |
+ (hcan->Init.Prescaler - 1U)));
- /* Filter FIFO assignment */
- if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
- {
- /* FIFO 0 assignation for the filter */
- can_ip->FFA1R &= ~(uint32_t)filternbrbitpos;
- }
+ /* Initialize the error code */
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;
- if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO1)
- {
- /* FIFO 1 assignation for the filter */
- can_ip->FFA1R |= (uint32_t)filternbrbitpos;
- }
-
- /* Filter activation */
- if (sFilterConfig->FilterActivation == ENABLE)
- {
- can_ip->FA1R |= filternbrbitpos;
- }
+ /* Initialize the CAN state */
+ hcan->State = HAL_CAN_STATE_READY;
- /* Leave the initialisation mode for the filter */
- can_ip->FMR &= ~((uint32_t)CAN_FMR_FINIT);
-
/* Return function status */
return HAL_OK;
}
/**
- * @brief Deinitializes the CANx peripheral registers to their default reset values.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
+ * @brief Deinitializes the CAN peripheral registers to their default
+ * reset values.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan)
+HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan)
{
/* Check CAN handle */
- if(hcan == NULL)
+ if (hcan == NULL)
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
-
+
/* Check the parameters */
assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
-
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY;
-
- /* DeInit the low level hardware */
+
+ /* Stop the CAN module */
+ HAL_CAN_Stop(hcan);
+
+ /* DeInit the low level hardware: CLOCK, NVIC */
HAL_CAN_MspDeInit(hcan);
-
+
+ /* Reset the CAN peripheral */
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_RESET);
+
+ /* Reset the CAN ErrorCode */
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+
/* Change CAN state */
hcan->State = HAL_CAN_STATE_RESET;
- /* Release Lock */
- __HAL_UNLOCK(hcan);
-
/* Return function status */
return HAL_OK;
}
/**
* @brief Initializes the CAN MSP.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
* @retval None
*/
-__weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
+__weak void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcan);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_MspInit could be implemented in the user file
- */
+ */
}
/**
* @brief DeInitializes the CAN MSP.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
* @retval None
*/
-__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
+__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcan);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_MspDeInit could be implemented in the user file
- */
+ */
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Exported_Functions_Group2 Configuration functions
+ * @brief Configuration functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Configuration functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) HAL_CAN_ConfigFilter : Configure the CAN reception filters
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the CAN reception filter according to the specified
+ * parameters in the CAN_FilterInitStruct.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param sFilterConfig pointer to a CAN_FilterTypeDef structure that
+ * contains the filter configuration information.
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig)
+{
+ uint32_t filternbrbitpos = 0U;
+ CAN_TypeDef *can_ip = hcan->Instance;
+
+ if ((hcan->State == HAL_CAN_STATE_READY) ||
+ (hcan->State == HAL_CAN_STATE_LISTENING))
+ {
+ /* Check the parameters */
+ assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdHigh));
+ assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdLow));
+ assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdHigh));
+ assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdLow));
+ assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));
+ assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));
+ assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));
+ assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation));
+
+#if defined(CAN3)
+ /* Check the CAN instance */
+ if (hcan->Instance == CAN3)
+ {
+ /* CAN3 is single instance with 14 dedicated filters banks */
+
+ /* Check the parameters */
+ assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank));
+ }
+ else
+ {
+ /* CAN1 and CAN2 are dual instances with 28 common filters banks */
+ /* Select master instance to access the filter banks */
+ can_ip = CAN1;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->FilterBank));
+ assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->SlaveStartFilterBank));
+ }
+#elif defined(CAN2)
+ /* CAN1 and CAN2 are dual instances with 28 common filters banks */
+ /* Select master instance to access the filter banks */
+ can_ip = CAN1;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->FilterBank));
+ assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->SlaveStartFilterBank));
+#else
+ /* CAN1 is single instance with 14 dedicated filters banks */
+
+ /* Check the parameters */
+ assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank));
+#endif
+
+ /* Initialisation mode for the filter */
+ SET_BIT(can_ip->FMR, CAN_FMR_FINIT);
+
+#if defined(CAN3)
+ /* Check the CAN instance */
+ if (can_ip == CAN1)
+ {
+ /* Select the start filter number of CAN2 slave instance */
+ CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB);
+ SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos);
+ }
+
+#elif defined(CAN2)
+ /* Select the start filter number of CAN2 slave instance */
+ CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB);
+ SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos);
+
+#endif
+ /* Convert filter number into bit position */
+ filternbrbitpos = (1U) << sFilterConfig->FilterBank;
+
+ /* Filter Deactivation */
+ CLEAR_BIT(can_ip->FA1R, filternbrbitpos);
+
+ /* Filter Scale */
+ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
+ {
+ /* 16-bit scale for the filter */
+ CLEAR_BIT(can_ip->FS1R, filternbrbitpos);
+
+ /* First 16-bit identifier and First 16-bit mask */
+ /* Or First 16-bit identifier and Second 16-bit identifier */
+ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
+
+ /* Second 16-bit identifier and Second 16-bit mask */
+ /* Or Third 16-bit identifier and Fourth 16-bit identifier */
+ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh);
+ }
+
+ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
+ {
+ /* 32-bit scale for the filter */
+ SET_BIT(can_ip->FS1R, filternbrbitpos);
+
+ /* 32-bit identifier or First 32-bit identifier */
+ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
+
+ /* 32-bit mask or Second 32-bit identifier */
+ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow);
+ }
+
+ /* Filter Mode */
+ if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
+ {
+ /* Id/Mask mode for the filter*/
+ CLEAR_BIT(can_ip->FM1R, filternbrbitpos);
+ }
+ else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
+ {
+ /* Identifier list mode for the filter*/
+ SET_BIT(can_ip->FM1R, filternbrbitpos);
+ }
+
+ /* Filter FIFO assignment */
+ if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
+ {
+ /* FIFO 0 assignation for the filter */
+ CLEAR_BIT(can_ip->FFA1R, filternbrbitpos);
+ }
+ else
+ {
+ /* FIFO 1 assignation for the filter */
+ SET_BIT(can_ip->FFA1R, filternbrbitpos);
+ }
+
+ /* Filter activation */
+ if (sFilterConfig->FilterActivation == ENABLE)
+ {
+ SET_BIT(can_ip->FA1R, filternbrbitpos);
+ }
+
+ /* Leave the initialisation mode for the filter */
+ CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
}
/**
* @}
*/
-/** @defgroup CAN_Exported_Functions_Group2 IO operation functions
- * @brief IO operation functions
+/** @defgroup CAN_Exported_Functions_Group3 Control functions
+ * @brief Control functions
*
-@verbatim
+@verbatim
==============================================================================
- ##### IO operation functions #####
+ ##### Control functions #####
==============================================================================
[..] This section provides functions allowing to:
- (+) Transmit a CAN frame message.
- (+) Receive a CAN frame message.
- (+) Enter CAN peripheral in sleep mode.
- (+) Wake up the CAN peripheral from sleep mode.
-
+ (+) HAL_CAN_Start : Start the CAN module
+ (+) HAL_CAN_Stop : Stop the CAN module
+ (+) HAL_CAN_RequestSleep : Request sleep mode entry.
+ (+) HAL_CAN_WakeUp : Wake up from sleep mode.
+ (+) HAL_CAN_IsSleepActive : Check is sleep mode is active.
+ (+) HAL_CAN_AddTxMessage : Add a message to the Tx mailboxes
+ and activate the corresponding
+ transmission request
+ (+) HAL_CAN_AbortTxRequest : Abort transmission request
+ (+) HAL_CAN_GetTxMailboxesFreeLevel : Return Tx mailboxes free level
+ (+) HAL_CAN_IsTxMessagePending : Check if a transmission request is
+ pending on the selected Tx mailbox
+ (+) HAL_CAN_GetRxMessage : Get a CAN frame from the Rx FIFO
+ (+) HAL_CAN_GetRxFifoFillLevel : Return Rx FIFO fill level
+
@endverbatim
* @{
*/
/**
- * @brief Initiates and transmits a CAN frame message.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @param Timeout: Specify Timeout value
+ * @brief Start the CAN module.
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
+HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan)
{
- uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
uint32_t tickstart = 0U;
- /* Check the parameters */
- assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
- assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
- assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
+ if (hcan->State == HAL_CAN_STATE_READY)
+ {
+ /* Change CAN peripheral state */
+ hcan->State = HAL_CAN_STATE_LISTENING;
- if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
- ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
- ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
- {
- /* Process locked */
- __HAL_LOCK(hcan);
-
- /* Change CAN state */
- switch(hcan->State)
- {
- case(HAL_CAN_STATE_BUSY_RX0):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
- break;
- case(HAL_CAN_STATE_BUSY_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
- break;
- default: /* HAL_CAN_STATE_READY */
- hcan->State = HAL_CAN_STATE_BUSY_TX;
- break;
- }
-
- /* Select one empty transmit mailbox */
- if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
- {
- transmitmailbox = CAN_TXMAILBOX_0;
- }
- else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
- {
- transmitmailbox = CAN_TXMAILBOX_1;
- }
- else
- {
- transmitmailbox = CAN_TXMAILBOX_2;
- }
+ /* Request leave initialisation */
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
- /* Set up the Id */
- hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
- if (hcan->pTxMsg->IDE == CAN_ID_STD)
- {
- assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
- hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21U) | \
- hcan->pTxMsg->RTR);
- }
- else
- {
- assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
- hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3U) | \
- hcan->pTxMsg->IDE | \
- hcan->pTxMsg->RTR);
- }
-
- /* Set up the DLC */
- hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
- hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U;
- hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
-
- /* Set up the data field */
- hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3U] << 24U) |
- ((uint32_t)hcan->pTxMsg->Data[2U] << 16U) |
- ((uint32_t)hcan->pTxMsg->Data[1U] << 8U) |
- ((uint32_t)hcan->pTxMsg->Data[0U]));
- hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7U] << 24U) |
- ((uint32_t)hcan->pTxMsg->Data[6U] << 16U) |
- ((uint32_t)hcan->pTxMsg->Data[5U] << 8U) |
- ((uint32_t)hcan->pTxMsg->Data[4U]));
- /* Request transmission */
- hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
-
/* Get tick */
tickstart = HAL_GetTick();
-
- /* Check End of transmission flag */
- while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox)))
+
+ /* Wait the acknowledge */
+ while ((hcan->Instance->MSR & CAN_MSR_INAK) != RESET)
{
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
{
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- hcan->State = HAL_CAN_STATE_TIMEOUT;
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
- __HAL_CAN_CANCEL_TRANSMIT(hcan, transmitmailbox);
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_ERROR;
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
}
- /* Change CAN state */
- switch(hcan->State)
- {
- case(HAL_CAN_STATE_BUSY_TX_RX0):
- hcan->State = HAL_CAN_STATE_BUSY_RX0;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
- break;
- default: /* HAL_CAN_STATE_BUSY_TX */
- hcan->State = HAL_CAN_STATE_READY;
- break;
- }
+ /* Reset the CAN ErrorCode */
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
-
/* Return function status */
return HAL_OK;
}
else
{
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_ERROR;
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Stop the CAN module and enable access to configuration registers.
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan)
+{
+ uint32_t tickstart = 0U;
+
+ if (hcan->State == HAL_CAN_STATE_LISTENING)
+ {
+ /* Request initialisation */
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait the acknowledge */
+ while ((hcan->Instance->MSR & CAN_MSR_INAK) == RESET)
+ {
+ /* Check for the Timeout */
+ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Exit from sleep mode */
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
+
+ /* Change CAN peripheral state */
+ hcan->State = HAL_CAN_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_STARTED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Request the sleep mode (low power) entry.
+ * When returning from this function, Sleep mode will be entered
+ * as soon as the current CAN activity (transmission or reception
+ * of a CAN frame) has been completed.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan)
+{
+ if ((hcan->State == HAL_CAN_STATE_READY) ||
+ (hcan->State == HAL_CAN_STATE_LISTENING))
+ {
+ /* Request Sleep mode */
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
/* Return function status */
return HAL_ERROR;
@@ -698,744 +787,1084 @@
}
/**
- * @brief Initiates and transmits a CAN frame message.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
+ * @brief Wake up from sleep mode.
+ * When returning with HAL_OK status from this function, Sleep mode
+ * is exited.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan)
+{
+ __IO uint32_t count = 0;
+ uint32_t timeout = 1000000U;
+
+ if ((hcan->State == HAL_CAN_STATE_READY) ||
+ (hcan->State == HAL_CAN_STATE_LISTENING))
+ {
+ /* Wake up request */
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
+
+ /* Wait sleep mode is exited */
+ do
+ {
+ /* Check if timeout is reached */
+ if (++count > timeout)
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
+
+ return HAL_ERROR;
+ }
+ }
+ while ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Check is sleep mode is active.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval Status
+ * - 0 : Sleep mode is not active.
+ * - 1 : Sleep mode is active.
+ */
+uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan)
+{
+ uint32_t status = 0U;
+
+ if ((hcan->State == HAL_CAN_STATE_READY) ||
+ (hcan->State == HAL_CAN_STATE_LISTENING))
+ {
+ /* Check Sleep mode */
+ if ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET)
+ {
+ status = 1U;
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Add a message to the first free Tx mailbox and activate the
+ * corresponding transmission request.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param pHeader pointer to a CAN_TxHeaderTypeDef structure.
+ * @param aData array containing the payload of the Tx frame.
+ * @param pTxMailbox pointer to a variable where the function will return
+ * the TxMailbox used to store the Tx message.
+ * This parameter can be a value of @arg CAN_Tx_Mailboxes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
+HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox)
{
- uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
-
+ uint32_t transmitmailbox;
+
/* Check the parameters */
- assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
- assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
- assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
-
- if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
- ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
- ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
+ assert_param(IS_CAN_IDTYPE(pHeader->IDE));
+ assert_param(IS_CAN_RTR(pHeader->RTR));
+ assert_param(IS_CAN_DLC(pHeader->DLC));
+ if (pHeader->IDE == CAN_ID_STD)
+ {
+ assert_param(IS_CAN_STDID(pHeader->StdId));
+ }
+ else
{
- /* Process Locked */
- __HAL_LOCK(hcan);
+ assert_param(IS_CAN_EXTID(pHeader->ExtId));
+ }
+ assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime));
- /* Select one empty transmit mailbox */
- if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
+ if ((hcan->State == HAL_CAN_STATE_READY) ||
+ (hcan->State == HAL_CAN_STATE_LISTENING))
+ {
+ /* Check that all the Tx mailboxes are not full */
+ if (((hcan->Instance->TSR & CAN_TSR_TME0) != RESET) ||
+ ((hcan->Instance->TSR & CAN_TSR_TME1) != RESET) ||
+ ((hcan->Instance->TSR & CAN_TSR_TME2) != RESET))
{
- transmitmailbox = CAN_TXMAILBOX_0;
- }
- else if((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
- {
- transmitmailbox = CAN_TXMAILBOX_1;
- }
- else
- {
- transmitmailbox = CAN_TXMAILBOX_2;
- }
+ /* Select an empty transmit mailbox */
+ transmitmailbox = (hcan->Instance->TSR & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos;
+
+ /* Store the Tx mailbox */
+ *pTxMailbox = 1U << transmitmailbox;
+
+ /* Set up the Id */
+ if (pHeader->IDE == CAN_ID_STD)
+ {
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) |
+ pHeader->RTR);
+ }
+ else
+ {
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
+ pHeader->IDE |
+ pHeader->RTR);
+ }
+
+ /* Set up the DLC */
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC);
- /* Set up the Id */
- hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
- if(hcan->pTxMsg->IDE == CAN_ID_STD)
- {
- assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
- hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21U) | \
- hcan->pTxMsg->RTR);
+ /* Set up the Transmit Global Time mode */
+ if (pHeader->TransmitGlobalTime == ENABLE)
+ {
+ SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT);
+ }
+
+ /* Set up the data field */
+ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR,
+ ((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) |
+ ((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) |
+ ((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) |
+ ((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos));
+ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR,
+ ((uint32_t)aData[3] << CAN_TDL0R_DATA3_Pos) |
+ ((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) |
+ ((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) |
+ ((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos));
+
+ /* Request transmission */
+ SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ);
+
+ /* Return function status */
+ return HAL_OK;
}
else
{
- assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
- hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3U) | \
- hcan->pTxMsg->IDE | \
- hcan->pTxMsg->RTR);
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
+
+ return HAL_ERROR;
}
-
- /* Set up the DLC */
- hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
- hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U;
- hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
+ }
+ else
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
- /* Set up the data field */
- hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3U] << 24U) |
- ((uint32_t)hcan->pTxMsg->Data[2U] << 16U) |
- ((uint32_t)hcan->pTxMsg->Data[1U] << 8U) |
- ((uint32_t)hcan->pTxMsg->Data[0U]));
- hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7U] << 24U) |
- ((uint32_t)hcan->pTxMsg->Data[6U] << 16U) |
- ((uint32_t)hcan->pTxMsg->Data[5U] << 8U) |
- ((uint32_t)hcan->pTxMsg->Data[4U]));
+/**
+ * @brief Abort transmission requests
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param TxMailboxes List of the Tx Mailboxes to abort.
+ * This parameter can be any combination of @arg CAN_Tx_Mailboxes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes)
+{
+ /* Check function parameters */
+ assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes));
- /* Change CAN state */
- switch(hcan->State)
+ if ((hcan->State == HAL_CAN_STATE_READY) ||
+ (hcan->State == HAL_CAN_STATE_LISTENING))
+ {
+ /* Check Tx Mailbox 0 */
+ if ((TxMailboxes & CAN_TX_MAILBOX0) != RESET)
{
- case(HAL_CAN_STATE_BUSY_RX0):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
- break;
- case(HAL_CAN_STATE_BUSY_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
- break;
- default: /* HAL_CAN_STATE_READY */
- hcan->State = HAL_CAN_STATE_BUSY_TX;
- break;
+ /* Add cancellation request for Tx Mailbox 0 */
+ SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ0);
}
- /* Set CAN error code to none */
- hcan->ErrorCode = HAL_CAN_ERROR_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcan);
-
- /* Request transmission */
- hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
+ /* Check Tx Mailbox 1 */
+ if ((TxMailboxes & CAN_TX_MAILBOX1) != RESET)
+ {
+ /* Add cancellation request for Tx Mailbox 1 */
+ SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ1);
+ }
- /* Enable Error warning, Error passive, Bus-off,
- Last error and Error Interrupts */
- __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
- CAN_IT_EPV |
- CAN_IT_BOF |
- CAN_IT_LEC |
- CAN_IT_ERR |
- CAN_IT_TME);
+ /* Check Tx Mailbox 2 */
+ if ((TxMailboxes & CAN_TX_MAILBOX2) != RESET)
+ {
+ /* Add cancellation request for Tx Mailbox 2 */
+ SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ2);
+ }
+
+ /* Return function status */
+ return HAL_OK;
}
else
{
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_ERROR;
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
- /* Return function status */
return HAL_ERROR;
}
-
- return HAL_OK;
+}
+
+/**
+ * @brief Return Tx Mailboxes free level: number of free Tx Mailboxes.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval Number of free Tx Mailboxes.
+ */
+uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan)
+{
+ uint32_t freelevel = 0U;
+
+ if ((hcan->State == HAL_CAN_STATE_READY) ||
+ (hcan->State == HAL_CAN_STATE_LISTENING))
+ {
+ /* Check Tx Mailbox 0 status */
+ if ((hcan->Instance->TSR & CAN_TSR_TME0) != RESET)
+ {
+ freelevel++;
+ }
+
+ /* Check Tx Mailbox 1 status */
+ if ((hcan->Instance->TSR & CAN_TSR_TME1) != RESET)
+ {
+ freelevel++;
+ }
+
+ /* Check Tx Mailbox 2 status */
+ if ((hcan->Instance->TSR & CAN_TSR_TME2) != RESET)
+ {
+ freelevel++;
+ }
+ }
+
+ /* Return Tx Mailboxes free level */
+ return freelevel;
+}
+
+/**
+ * @brief Check if a transmission request is pending on the selected Tx
+ * Mailboxes.
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param TxMailboxes List of Tx Mailboxes to check.
+ * This parameter can be any combination of @arg CAN_Tx_Mailboxes.
+ * @retval Status
+ * - 0 : No pending transmission request on any selected Tx Mailboxes.
+ * - 1 : Pending transmission request on at least one of the selected
+ * Tx Mailbox.
+ */
+uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes)
+{
+ uint32_t status = 0U;
+
+ /* Check function parameters */
+ assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes));
+
+ if ((hcan->State == HAL_CAN_STATE_READY) ||
+ (hcan->State == HAL_CAN_STATE_LISTENING))
+ {
+ /* Check pending transmission request on the selected Tx Mailboxes */
+ if ((hcan->Instance->TSR & (TxMailboxes << CAN_TSR_TME0_Pos)) != (TxMailboxes << CAN_TSR_TME0_Pos))
+ {
+ status = 1U;
+ }
+ }
+
+ /* Return status */
+ return status;
+}
+
+/**
+ * @brief Return timestamp of Tx message sent, if time triggered communication
+ mode is enabled.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param TxMailbox Tx Mailbox where the timestamp of message sent will be
+ * read.
+ * This parameter can be one value of @arg CAN_Tx_Mailboxes.
+ * @retval Timestamp of message sent from Tx Mailbox.
+ */
+uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox)
+{
+ uint32_t timestamp = 0U;
+ uint32_t transmitmailbox;
+
+ /* Check function parameters */
+ assert_param(IS_CAN_TX_MAILBOX(TxMailbox));
+
+ if ((hcan->State == HAL_CAN_STATE_READY) ||
+ (hcan->State == HAL_CAN_STATE_LISTENING))
+ {
+ /* Select the Tx mailbox */
+ transmitmailbox = POSITION_VAL(TxMailbox);
+
+ /* Get timestamp */
+ timestamp = (hcan->Instance->sTxMailBox[transmitmailbox].TDTR & CAN_TDT0R_TIME) >> CAN_TDT0R_TIME_Pos;
+ }
+
+ /* Return the timestamp */
+ return timestamp;
}
/**
- * @brief Receives a correct CAN frame.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @param FIFONumber: FIFO Number value
- * @param Timeout: Specify Timeout value
+ * @brief Get an CAN frame from the Rx FIFO zone into the message RAM.
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param RxFifo Fifo number of the received message to be read.
+ * This parameter can be a value of @arg CAN_receive_FIFO_number.
+ * @param pHeader pointer to a CAN_RxHeaderTypeDef structure where the header
+ * of the Rx frame will be stored.
+ * @param aData array where the payload of the Rx frame will be stored.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout)
+HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[])
{
- uint32_t tickstart = 0U;
- CanRxMsgTypeDef* pRxMsg = NULL;
-
- /* Check the parameters */
- assert_param(IS_CAN_FIFO(FIFONumber));
+ assert_param(IS_CAN_RX_FIFO(RxFifo));
- /* Check if CAN state is not busy for RX FIFO0 */
- if ((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \
- (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \
- (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
- (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
- {
- return HAL_BUSY;
- }
-
- /* Check if CAN state is not busy for RX FIFO1 */
- if ((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \
- (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \
- (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
- (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
- {
- return HAL_BUSY;
- }
-
- /* Process locked */
- __HAL_LOCK(hcan);
-
- /* Change CAN state */
- if (FIFONumber == CAN_FIFO0)
+ if ((hcan->State == HAL_CAN_STATE_READY) ||
+ (hcan->State == HAL_CAN_STATE_LISTENING))
{
- switch(hcan->State)
+ /* Check the Rx FIFO */
+ if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */
+ {
+ /* Check that the Rx FIFO 0 is not empty */
+ if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == RESET)
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
+
+ return HAL_ERROR;
+ }
+ }
+ else if (RxFifo == CAN_RX_FIFO1) /* Rx element is assigned to Rx FIFO 1 */
+ {
+ /* Check that the Rx FIFO 1 is not empty */
+ if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == RESET)
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Get the header */
+ pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR;
+ if (pHeader->IDE == CAN_ID_STD)
+ {
+ pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos;
+ }
+ else
{
- case(HAL_CAN_STATE_BUSY_TX):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
- break;
- case(HAL_CAN_STATE_BUSY_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
- break;
- default: /* HAL_CAN_STATE_READY */
- hcan->State = HAL_CAN_STATE_BUSY_RX0;
- break;
+ pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos;
}
+ pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_RTR_Pos;
+ pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos;
+ pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos;
+ pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos;
+
+ /* Get the data */
+ aData[0] = (CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos;
+ aData[1] = (CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos;
+ aData[2] = (CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos;
+ aData[3] = (CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos;
+ aData[4] = (CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos;
+ aData[5] = (CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos;
+ aData[6] = (CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos;
+ aData[7] = (CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos;
+
+ /* Release the FIFO */
+ if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */
+ {
+ /* Release RX FIFO 0 */
+ SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0);
+ }
+ else if (RxFifo == CAN_RX_FIFO1) /* Rx element is assigned to Rx FIFO 1 */
+ {
+ /* Release RX FIFO 1 */
+ SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1);
+ }
+
+ /* Return function status */
+ return HAL_OK;
}
- else /* FIFONumber == CAN_FIFO1 */
+ else
{
- switch(hcan->State)
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Return Rx FIFO fill level.
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param RxFifo Rx FIFO.
+ * This parameter can be a value of @arg CAN_receive_FIFO_number.
+ * @retval Number of messages available in Rx FIFO.
+ */
+uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo)
+{
+ uint32_t filllevel = 0U;
+
+ /* Check function parameters */
+ assert_param(IS_CAN_RX_FIFO(RxFifo));
+
+ if ((hcan->State == HAL_CAN_STATE_READY) ||
+ (hcan->State == HAL_CAN_STATE_LISTENING))
+ {
+ if (RxFifo == CAN_RX_FIFO0)
{
- case(HAL_CAN_STATE_BUSY_TX):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_RX0):
- hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX0):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
- break;
- default: /* HAL_CAN_STATE_READY */
- hcan->State = HAL_CAN_STATE_BUSY_RX1;
- break;
+ filllevel = hcan->Instance->RF0R & CAN_RF0R_FMP0;
+ }
+ else /* RxFifo == CAN_RX_FIFO1 */
+ {
+ filllevel = hcan->Instance->RF1R & CAN_RF1R_FMP1;
}
}
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Check pending message */
- while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0U)
+ /* Return Rx FIFO fill level */
+ return filllevel;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Exported_Functions_Group4 Interrupts management
+ * @brief Interrupts management
+ *
+@verbatim
+ ==============================================================================
+ ##### Interrupts management #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) HAL_CAN_ActivateNotification : Enable interrupts
+ (+) HAL_CAN_DeactivateNotification : Disable interrupts
+ (+) HAL_CAN_IRQHandler : Handles CAN interrupt request
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enable interrupts.
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param ActiveITs indicates which interrupts will be enabled.
+ * This parameter can be any combination of @arg CAN_Interrupts.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs)
+{
+ /* Check function parameters */
+ assert_param(IS_CAN_IT(ActiveITs));
+
+ if ((hcan->State == HAL_CAN_STATE_READY) ||
+ (hcan->State == HAL_CAN_STATE_LISTENING))
+ {
+ /* Enable the selected interrupts */
+ __HAL_CAN_ENABLE_IT(hcan, ActiveITs);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Disable interrupts.
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param InactiveITs indicates which interrupts will be disabled.
+ * This parameter can be any combination of @arg CAN_Interrupts.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs)
+{
+ /* Check function parameters */
+ assert_param(IS_CAN_IT(InactiveITs));
+
+ if ((hcan->State == HAL_CAN_STATE_READY) ||
+ (hcan->State == HAL_CAN_STATE_LISTENING))
+ {
+ /* Disable the selected interrupts */
+ __HAL_CAN_DISABLE_IT(hcan, InactiveITs);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
{
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Handles CAN interrupt request
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
+{
+ uint32_t errorcode = HAL_CAN_ERROR_NONE;
+ uint32_t interrupts = READ_REG(hcan->Instance->IER);
+ uint32_t msrflags = READ_REG(hcan->Instance->MSR);
+ uint32_t tsrflags = READ_REG(hcan->Instance->TSR);
+ uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R);
+ uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R);
+ uint32_t esrflags = READ_REG(hcan->Instance->ESR);
+
+ /* Transmit Mailbox empty interrupt management *****************************/
+ if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != RESET)
+ {
+ /* Transmit Mailbox 0 management *****************************************/
+ if ((tsrflags & CAN_TSR_RQCP0) != RESET)
{
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0);
+
+ if ((tsrflags & CAN_TSR_TXOK0) != RESET)
+ {
+ /* Transmission Mailbox 0 complete callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_TxMailbox0CompleteCallback(hcan);
+ }
+ else
{
- hcan->State = HAL_CAN_STATE_TIMEOUT;
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
- return HAL_TIMEOUT;
+ if ((tsrflags & CAN_TSR_ALST0) != RESET)
+ {
+ /* Update error code */
+ errorcode |= HAL_CAN_ERROR_TX_ALST0;
+ }
+ else if ((tsrflags & CAN_TSR_TERR0) != RESET)
+ {
+ /* Update error code */
+ errorcode |= HAL_CAN_ERROR_TX_TERR0;
+ }
+ else
+ {
+ /* Transmission Mailbox 0 abort callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_TxMailbox0AbortCallback(hcan);
+ }
+ }
+ }
+
+ /* Transmit Mailbox 1 management *****************************************/
+ if ((tsrflags & CAN_TSR_RQCP1) != RESET)
+ {
+ /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1);
+
+ if ((tsrflags & CAN_TSR_TXOK1) != RESET)
+ {
+ /* Transmission Mailbox 1 complete callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_TxMailbox1CompleteCallback(hcan);
+ }
+ else
+ {
+ if ((tsrflags & CAN_TSR_ALST1) != RESET)
+ {
+ /* Update error code */
+ errorcode |= HAL_CAN_ERROR_TX_ALST1;
+ }
+ else if ((tsrflags & CAN_TSR_TERR1) != RESET)
+ {
+ /* Update error code */
+ errorcode |= HAL_CAN_ERROR_TX_TERR1;
+ }
+ else
+ {
+ /* Transmission Mailbox 1 abort callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_TxMailbox1AbortCallback(hcan);
+ }
+ }
+ }
+
+ /* Transmit Mailbox 2 management *****************************************/
+ if ((tsrflags & CAN_TSR_RQCP2) != RESET)
+ {
+ /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2);
+
+ if ((tsrflags & CAN_TSR_TXOK2) != RESET)
+ {
+ /* Transmission Mailbox 2 complete callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_TxMailbox2CompleteCallback(hcan);
+ }
+ else
+ {
+ if ((tsrflags & CAN_TSR_ALST2) != RESET)
+ {
+ /* Update error code */
+ errorcode |= HAL_CAN_ERROR_TX_ALST2;
+ }
+ else if ((tsrflags & CAN_TSR_TERR2) != RESET)
+ {
+ /* Update error code */
+ errorcode |= HAL_CAN_ERROR_TX_TERR2;
+ }
+ else
+ {
+ /* Transmission Mailbox 2 abort callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_TxMailbox2AbortCallback(hcan);
+ }
}
}
}
- /* Set RxMsg pointer */
- if(FIFONumber == CAN_FIFO0)
+ /* Receive FIFO 0 overrun interrupt management *****************************/
+ if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != RESET)
+ {
+ if ((rf0rflags & CAN_RF0R_FOVR0) != RESET)
+ {
+ /* Set CAN error code to Rx Fifo 0 overrun error */
+ errorcode |= HAL_CAN_ERROR_RX_FOV0;
+
+ /* Clear FIFO0 Overrun Flag */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0);
+ }
+ }
+
+ /* Receive FIFO 0 full interrupt management ********************************/
+ if ((interrupts & CAN_IT_RX_FIFO0_FULL) != RESET)
{
- pRxMsg = hcan->pRxMsg;
+ if ((rf0rflags & CAN_RF0R_FULL0) != RESET)
+ {
+ /* Clear FIFO 0 full Flag */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0);
+
+ /* Receive FIFO 0 full Callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_RxFifo0FullCallback(hcan);
+ }
}
- else /* FIFONumber == CAN_FIFO1 */
+
+ /* Receive FIFO 0 message pending interrupt management *********************/
+ if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != RESET)
{
- pRxMsg = hcan->pRx1Msg;
+ /* Check if message is still pending */
+ if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != RESET)
+ {
+ /* Receive FIFO 0 mesage pending Callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_RxFifo0MsgPendingCallback(hcan);
+ }
}
- /* Get the Id */
- pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
- if (pRxMsg->IDE == CAN_ID_STD)
- {
- pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
- }
- else
+ /* Receive FIFO 1 overrun interrupt management *****************************/
+ if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != RESET)
{
- pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
- }
-
- pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
- /* Get the DLC */
- pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
- /* Get the FMI */
- pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
- /* Get the FIFONumber */
- pRxMsg->FIFONumber = FIFONumber;
- /* Get the data field */
- pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
- pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
- pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
- pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
- pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
- pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
- pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
- pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
+ if ((rf1rflags & CAN_RF1R_FOVR1) != RESET)
+ {
+ /* Set CAN error code to Rx Fifo 1 overrun error */
+ errorcode |= HAL_CAN_ERROR_RX_FOV1;
- /* Release the FIFO */
- if(FIFONumber == CAN_FIFO0)
- {
- /* Release FIFO0 */
- __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
- }
- else /* FIFONumber == CAN_FIFO1 */
- {
- /* Release FIFO1 */
- __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
+ /* Clear FIFO1 Overrun Flag */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1);
+ }
}
- /* Change CAN state */
- if (FIFONumber == CAN_FIFO0)
+ /* Receive FIFO 1 full interrupt management ********************************/
+ if ((interrupts & CAN_IT_RX_FIFO1_FULL) != RESET)
{
- switch(hcan->State)
+ if ((rf1rflags & CAN_RF1R_FULL1) != RESET)
{
- case(HAL_CAN_STATE_BUSY_TX_RX0):
- hcan->State = HAL_CAN_STATE_BUSY_TX;
- break;
- case(HAL_CAN_STATE_BUSY_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
- break;
- default: /* HAL_CAN_STATE_BUSY_RX0 */
- hcan->State = HAL_CAN_STATE_READY;
- break;
+ /* Clear FIFO 1 full Flag */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1);
+
+ /* Receive FIFO 1 full Callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_RxFifo1FullCallback(hcan);
}
}
- else /* FIFONumber == CAN_FIFO1 */
+
+ /* Receive FIFO 1 message pending interrupt management *********************/
+ if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != RESET)
{
- switch(hcan->State)
+ /* Check if message is still pending */
+ if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != RESET)
{
- case(HAL_CAN_STATE_BUSY_TX_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX;
- break;
- case(HAL_CAN_STATE_BUSY_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_RX0;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
- break;
- default: /* HAL_CAN_STATE_BUSY_RX1 */
- hcan->State = HAL_CAN_STATE_READY;
- break;
+ /* Receive FIFO 1 mesage pending Callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_RxFifo1MsgPendingCallback(hcan);
+ }
+ }
+
+ /* Sleep interrupt management *********************************************/
+ if ((interrupts & CAN_IT_SLEEP_ACK) != RESET)
+ {
+ if ((msrflags & CAN_MSR_SLAKI) != RESET)
+ {
+ /* Clear Sleep interrupt Flag */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI);
+
+ /* Sleep Callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_SleepCallback(hcan);
}
}
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Receives a correct CAN frame.
- * @param hcan: Pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @param FIFONumber: Specify the FIFO number
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
-{
- /* Check the parameters */
- assert_param(IS_CAN_FIFO(FIFONumber));
-
- /* Check if CAN state is not busy for RX FIFO0 */
- if((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \
- (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \
- (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
- (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
+ /* WakeUp interrupt management *********************************************/
+ if ((interrupts & CAN_IT_WAKEUP) != RESET)
{
- return HAL_BUSY;
- }
-
- /* Check if CAN state is not busy for RX FIFO1 */
- if((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \
- (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \
- (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
- (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
- {
- return HAL_BUSY;
- }
-
- /* Process locked */
- __HAL_LOCK(hcan);
-
- /* Change CAN state */
- if(FIFONumber == CAN_FIFO0)
- {
- switch(hcan->State)
- {
- case(HAL_CAN_STATE_BUSY_TX):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
- break;
- case(HAL_CAN_STATE_BUSY_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
- break;
- default: /* HAL_CAN_STATE_READY */
- hcan->State = HAL_CAN_STATE_BUSY_RX0;
- break;
- }
- }
- else /* FIFONumber == CAN_FIFO1 */
- {
- switch(hcan->State)
+ if ((msrflags & CAN_MSR_WKUI) != RESET)
{
- case(HAL_CAN_STATE_BUSY_TX):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_RX0):
- hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX0):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
- break;
- default: /* HAL_CAN_STATE_READY */
- hcan->State = HAL_CAN_STATE_BUSY_RX1;
- break;
- }
- }
- /* Set CAN error code to none */
- hcan->ErrorCode = HAL_CAN_ERROR_NONE;
-
- /* Enable interrupts: */
- /* - Enable Error warning Interrupt */
- /* - Enable Error passive Interrupt */
- /* - Enable Bus-off Interrupt */
- /* - Enable Last error code Interrupt */
- /* - Enable Error Interrupt */
- /* - Enable Transmit mailbox empty Interrupt */
- __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
- CAN_IT_EPV |
- CAN_IT_BOF |
- CAN_IT_LEC |
- CAN_IT_ERR |
- CAN_IT_TME);
-
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
-
- if(FIFONumber == CAN_FIFO0)
- {
- /* Enable FIFO 0 overrun and message pending Interrupt */
- __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0);
- }
- else
- {
- /* Enable FIFO 1 overrun and message pending Interrupt */
- __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1);
- }
+ /* Clear WakeUp Flag */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU);
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Enters the Sleep (low power) mode.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @retval HAL status.
- */
-HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan)
-{
- uint32_t tickstart = 0U;
-
- /* Process locked */
- __HAL_LOCK(hcan);
-
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY;
-
- /* Request Sleep mode */
- hcan->Instance->MCR = (((hcan->Instance->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
-
- /* Sleep mode status */
- if ((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)
- {
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
-
- /* Return function status */
- return HAL_ERROR;
- }
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Wait the acknowledge */
- while((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)
- {
- if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
- {
- hcan->State = HAL_CAN_STATE_TIMEOUT;
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
- return HAL_TIMEOUT;
+ /* WakeUp Callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_WakeUpFromRxMsgCallback(hcan);
}
}
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_READY;
+ /* Error interrupts management *********************************************/
+ if ((interrupts & CAN_IT_ERROR) != RESET)
+ {
+ if ((msrflags & CAN_MSR_ERRI) != RESET)
+ {
+ /* Check Error Warning Flag */
+ if (((interrupts & CAN_IT_ERROR_WARNING) != RESET) &&
+ ((esrflags & CAN_ESR_EWGF) != RESET))
+ {
+ /* Set CAN error code to Error Warning */
+ errorcode |= HAL_CAN_ERROR_EWG;
+
+ /* No need for clear of Error Warning Flag as read-only */
+ }
+
+ /* Check Error Passive Flag */
+ if (((interrupts & CAN_IT_ERROR_PASSIVE) != RESET) &&
+ ((esrflags & CAN_ESR_EPVF) != RESET))
+ {
+ /* Set CAN error code to Error Passive */
+ errorcode |= HAL_CAN_ERROR_EPV;
+
+ /* No need for clear of Error Passive Flag as read-only */
+ }
+
+ /* Check Bus-off Flag */
+ if (((interrupts & CAN_IT_BUSOFF) != RESET) &&
+ ((esrflags & CAN_ESR_BOFF) != RESET))
+ {
+ /* Set CAN error code to Bus-Off */
+ errorcode |= HAL_CAN_ERROR_BOF;
+
+ /* No need for clear of Error Bus-Off as read-only */
+ }
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
+ /* Check Last Error Code Flag */
+ if (((interrupts & CAN_IT_LAST_ERROR_CODE) != RESET) &&
+ ((esrflags & CAN_ESR_LEC) != RESET))
+ {
+ switch (esrflags & CAN_ESR_LEC)
+ {
+ case (CAN_ESR_LEC_0):
+ /* Set CAN error code to Stuff error */
+ errorcode |= HAL_CAN_ERROR_STF;
+ break;
+ case (CAN_ESR_LEC_1):
+ /* Set CAN error code to Form error */
+ errorcode |= HAL_CAN_ERROR_FOR;
+ break;
+ case (CAN_ESR_LEC_1 | CAN_ESR_LEC_0):
+ /* Set CAN error code to Acknowledgement error */
+ errorcode |= HAL_CAN_ERROR_ACK;
+ break;
+ case (CAN_ESR_LEC_2):
+ /* Set CAN error code to Bit recessive error */
+ errorcode |= HAL_CAN_ERROR_BR;
+ break;
+ case (CAN_ESR_LEC_2 | CAN_ESR_LEC_0):
+ /* Set CAN error code to Bit Dominant error */
+ errorcode |= HAL_CAN_ERROR_BD;
+ break;
+ case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
+ /* Set CAN error code to CRC error */
+ errorcode |= HAL_CAN_ERROR_CRC;
+ break;
+ default:
+ break;
+ }
- /* Return function status */
- return HAL_OK;
+ /* Clear Last error code Flag */
+ CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC);
+ }
+ }
+
+ /* Clear ERRI Flag */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI);
+ }
+
+ /* Call the Error call Back in case of Errors */
+ if (errorcode != HAL_CAN_ERROR_NONE)
+ {
+ /* Update error code in handle */
+ hcan->ErrorCode |= errorcode;
+
+ /* Call Error callback function */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_ErrorCallback(hcan);
+ }
}
/**
- * @brief Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral
- * is in the normal mode.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @retval HAL status.
+ * @}
*/
-HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan)
-{
- uint32_t tickstart = 0U;
-
- /* Process locked */
- __HAL_LOCK(hcan);
-
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY;
-
- /* Wake up request */
- hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_SLEEP;
-
- /* Get tick */
- tickstart = HAL_GetTick();
- /* Sleep mode status */
- while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
- {
- if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
- {
- hcan->State= HAL_CAN_STATE_TIMEOUT;
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
- return HAL_TIMEOUT;
- }
- }
- if((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
- {
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
-
- /* Return function status */
- return HAL_ERROR;
- }
-
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
-
- /* Return function status */
- return HAL_OK;
-}
+/** @defgroup CAN_Exported_Functions_Group5 Callback functions
+ * @brief CAN Callback functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Callback functions #####
+ ==============================================================================
+ [..]
+ This subsection provides the following callback functions:
+ (+) HAL_CAN_TxMailbox0CompleteCallback
+ (+) HAL_CAN_TxMailbox1CompleteCallback
+ (+) HAL_CAN_TxMailbox2CompleteCallback
+ (+) HAL_CAN_TxMailbox0AbortCallback
+ (+) HAL_CAN_TxMailbox1AbortCallback
+ (+) HAL_CAN_TxMailbox2AbortCallback
+ (+) HAL_CAN_RxFifo0MsgPendingCallback
+ (+) HAL_CAN_RxFifo0FullCallback
+ (+) HAL_CAN_RxFifo1MsgPendingCallback
+ (+) HAL_CAN_RxFifo1FullCallback
+ (+) HAL_CAN_SleepCallback
+ (+) HAL_CAN_WakeUpFromRxMsgCallback
+ (+) HAL_CAN_ErrorCallback
+
+@endverbatim
+ * @{
+ */
/**
- * @brief Handles CAN interrupt request
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * @brief Transmission Mailbox 0 complete callback.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
-void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
-{
- uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U;
- uint32_t errorcode = HAL_CAN_ERROR_NONE;
-
- /* Check Overrun flag for FIFO0 */
- tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV0);
- tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV0);
- if(tmp1 && tmp2)
- {
- /* Set CAN error code to FOV0 error */
- errorcode |= HAL_CAN_ERROR_FOV0;
-
- /* Clear FIFO0 Overrun Flag */
- __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0);
- }
- /* Check Overrun flag for FIFO1 */
- tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV1);
- tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV1);
-
- if(tmp1 && tmp2)
- {
- /* Set CAN error code to FOV1 error */
- errorcode |= HAL_CAN_ERROR_FOV1;
-
- /* Clear FIFO1 Overrun Flag */
- __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1);
- }
-
- /* Check End of transmission flag */
- if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME))
- {
- tmp1 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0);
- tmp2 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1);
- tmp3 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2);
- if(tmp1 || tmp2 || tmp3)
- {
- tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK0);
- tmp2 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK1);
- tmp3 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK2);
- /* Check Transmit success */
- if(tmp1 || tmp2 || tmp3)
- {
- /* Call transmit function */
- CAN_Transmit_IT(hcan);
- }
- else /* Transmit failure */
- {
- /* Set CAN error code to TXFAIL error */
- errorcode |= HAL_CAN_ERROR_TXFAIL;
- }
-
- /* Clear transmission status flags (RQCPx and TXOKx) */
- SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP0 | CAN_TSR_RQCP1 | CAN_TSR_RQCP2 | \
- CAN_FLAG_TXOK0 | CAN_FLAG_TXOK1 | CAN_FLAG_TXOK2);
- }
- }
-
- tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0);
- tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0);
- /* Check End of reception flag for FIFO0 */
- if((tmp1 != 0U) && tmp2)
- {
- /* Call receive function */
- CAN_Receive_IT(hcan, CAN_FIFO0);
- }
-
- tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1);
- tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1);
- /* Check End of reception flag for FIFO1 */
- if((tmp1 != 0U) && tmp2)
- {
- /* Call receive function */
- CAN_Receive_IT(hcan, CAN_FIFO1);
- }
-
- /* Set error code in handle */
- hcan->ErrorCode |= errorcode;
-
- tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG);
- tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG);
- tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
- /* Check Error Warning Flag */
- if(tmp1 && tmp2 && tmp3)
- {
- /* Set CAN error code to EWG error */
- hcan->ErrorCode |= HAL_CAN_ERROR_EWG;
- }
-
- tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV);
- tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV);
- tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
- /* Check Error Passive Flag */
- if(tmp1 && tmp2 && tmp3)
- {
- /* Set CAN error code to EPV error */
- hcan->ErrorCode |= HAL_CAN_ERROR_EPV;
- }
-
- tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF);
- tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF);
- tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
- /* Check Bus-Off Flag */
- if(tmp1 && tmp2 && tmp3)
- {
- /* Set CAN error code to BOF error */
- hcan->ErrorCode |= HAL_CAN_ERROR_BOF;
- }
-
- tmp1 = HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC);
- tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC);
- tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
- /* Check Last error code Flag */
- if((!tmp1) && tmp2 && tmp3)
- {
- tmp1 = (hcan->Instance->ESR) & CAN_ESR_LEC;
- switch(tmp1)
- {
- case(CAN_ESR_LEC_0):
- /* Set CAN error code to STF error */
- hcan->ErrorCode |= HAL_CAN_ERROR_STF;
- break;
- case(CAN_ESR_LEC_1):
- /* Set CAN error code to FOR error */
- hcan->ErrorCode |= HAL_CAN_ERROR_FOR;
- break;
- case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0):
- /* Set CAN error code to ACK error */
- hcan->ErrorCode |= HAL_CAN_ERROR_ACK;
- break;
- case(CAN_ESR_LEC_2):
- /* Set CAN error code to BR error */
- hcan->ErrorCode |= HAL_CAN_ERROR_BR;
- break;
- case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0):
- /* Set CAN error code to BD error */
- hcan->ErrorCode |= HAL_CAN_ERROR_BD;
- break;
- case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
- /* Set CAN error code to CRC error */
- hcan->ErrorCode |= HAL_CAN_ERROR_CRC;
- break;
- default:
- break;
- }
-
- /* Clear Last error code Flag */
- hcan->Instance->ESR &= ~(CAN_ESR_LEC);
- }
-
- /* Call the Error call Back in case of Errors */
- if(hcan->ErrorCode != HAL_CAN_ERROR_NONE)
- {
- /* Clear ERRI Flag */
- hcan->Instance->MSR = CAN_MSR_ERRI;
- /* Set the CAN state ready to be able to start again the process */
- hcan->State = HAL_CAN_STATE_READY;
-
- /* Disable interrupts: */
- /* - Disable Error warning Interrupt */
- /* - Disable Error passive Interrupt */
- /* - Disable Bus-off Interrupt */
- /* - Disable Last error code Interrupt */
- /* - Disable Error Interrupt */
- /* - Disable FIFO 0 message pending Interrupt */
- /* - Disable FIFO 0 Overrun Interrupt */
- /* - Disable FIFO 1 message pending Interrupt */
- /* - Disable FIFO 1 Overrun Interrupt */
- /* - Disable Transmit mailbox empty Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
- CAN_IT_EPV |
- CAN_IT_BOF |
- CAN_IT_LEC |
- CAN_IT_ERR |
- CAN_IT_FMP0|
- CAN_IT_FOV0|
- CAN_IT_FMP1|
- CAN_IT_FOV1|
- CAN_IT_TME);
-
- /* Call Error callback function */
- HAL_CAN_ErrorCallback(hcan);
- }
-}
-
-/**
- * @brief Transmission complete callback in non blocking mode
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @retval None
- */
-__weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan)
+__weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcan);
+
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_CAN_TxCpltCallback could be implemented in the user file
+ the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the
+ user file
*/
}
/**
- * @brief Transmission complete callback in non blocking mode
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * @brief Transmission Mailbox 1 complete callback.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the
+ user file
+ */
+}
+
+/**
+ * @brief Transmission Mailbox 2 complete callback.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the
+ user file
+ */
+}
+
+/**
+ * @brief Transmission Mailbox 0 Cancellation callback.
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_TxMailbox0AbortCallback could be implemented in the
+ user file
+ */
+}
+
+/**
+ * @brief Transmission Mailbox 1 Cancellation callback.
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_TxMailbox1AbortCallback could be implemented in the
+ user file
+ */
+}
+
+/**
+ * @brief Transmission Mailbox 2 Cancellation callback.
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_TxMailbox2AbortCallback could be implemented in the
+ user file
+ */
+}
+
+/**
+ * @brief Rx FIFO 0 message pending callback.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
-__weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan)
+__weak void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_RxFifo0MsgPendingCallback could be implemented in the
+ user file
+ */
+}
+
+/**
+ * @brief Rx FIFO 0 full callback.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_RxFifo0FullCallback could be implemented in the user
+ file
+ */
+}
+
+/**
+ * @brief Rx FIFO 1 message pending callback.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcan);
+
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_CAN_RxCpltCallback could be implemented in the user file
+ the HAL_CAN_RxFifo1MsgPendingCallback could be implemented in the
+ user file
+ */
+}
+
+/**
+ * @brief Rx FIFO 1 full callback.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_RxFifo1FullCallback could be implemented in the user
+ file
+ */
+}
+
+/**
+ * @brief Sleep callback.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_SleepCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief WakeUp from Rx message callback.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the
+ user file
*/
}
/**
* @brief Error CAN callback.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
@@ -1443,6 +1872,7 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcan);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_ErrorCallback could be implemented in the user file
*/
@@ -1452,232 +1882,112 @@
* @}
*/
-/** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
- * @brief CAN Peripheral State functions
- *
-@verbatim
+/** @defgroup CAN_Exported_Functions_Group6 Peripheral State and Error functions
+ * @brief CAN Peripheral State functions
+ *
+@verbatim
==============================================================================
##### Peripheral State and Error functions #####
==============================================================================
[..]
This subsection provides functions allowing to :
- (+) Check the CAN state.
- (+) Check CAN Errors detected during interrupt process
-
+ (+) HAL_CAN_GetState() : Return the CAN state.
+ (+) HAL_CAN_GetError() : Return the CAN error codes if any.
+ (+) HAL_CAN_ResetError(): Reset the CAN error codes if any.
+
@endverbatim
* @{
*/
/**
- * @brief return the CAN state
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * @brief Return the CAN state.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval HAL state
*/
-HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan)
+HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan)
{
+ HAL_CAN_StateTypeDef state = hcan->State;
+
+ if ((hcan->State == HAL_CAN_STATE_READY) ||
+ (hcan->State == HAL_CAN_STATE_LISTENING))
+ {
+ /* Check sleep mode acknowledge flag */
+ if ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET)
+ {
+ /* Sleep mode is active */
+ state = HAL_CAN_STATE_SLEEP_ACTIVE;
+ }
+ /* Check sleep mode request flag */
+ else if ((hcan->Instance->MCR & CAN_MCR_SLEEP) != RESET)
+ {
+ /* Sleep mode request is pending */
+ state = HAL_CAN_STATE_SLEEP_PENDING;
+ }
+ }
+
/* Return CAN state */
- return hcan->State;
+ return state;
}
/**
- * @brief Return the CAN error code
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * @brief Return the CAN error code.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval CAN Error Code
*/
uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan)
{
+ /* Return CAN error code */
return hcan->ErrorCode;
}
/**
- * @}
- */
-/**
- * @brief Initiates and transmits a CAN frame message.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
+ * @brief Reset the CAN error code.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
* @retval HAL status
*/
-static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
+HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan)
{
- /* Disable Transmit mailbox empty Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME);
-
- if(hcan->State == HAL_CAN_STATE_BUSY_TX)
- {
- /* Disable Error warning, Error passive, Bus-off, Last error code
- and Error Interrupts */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
- CAN_IT_EPV |
- CAN_IT_BOF |
- CAN_IT_LEC |
- CAN_IT_ERR );
- }
-
- /* Change CAN state */
- switch(hcan->State)
- {
- case(HAL_CAN_STATE_BUSY_TX_RX0):
- hcan->State = HAL_CAN_STATE_BUSY_RX0;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
- break;
- default: /* HAL_CAN_STATE_BUSY_TX */
- hcan->State = HAL_CAN_STATE_READY;
- break;
- }
+ HAL_StatusTypeDef status = HAL_OK;
- /* Transmission complete callback */
- HAL_CAN_TxCpltCallback(hcan);
-
- return HAL_OK;
-}
-
-/**
- * @brief Receives a correct CAN frame.
- * @param hcan: Pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @param FIFONumber: Specify the FIFO number
- * @retval HAL status
- * @retval None
- */
-static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
-{
- uint32_t tmp1 = 0U;
- CanRxMsgTypeDef* pRxMsg = NULL;
-
- /* Set RxMsg pointer */
- if(FIFONumber == CAN_FIFO0)
+ if ((hcan->State == HAL_CAN_STATE_READY) ||
+ (hcan->State == HAL_CAN_STATE_LISTENING))
{
- pRxMsg = hcan->pRxMsg;
- }
- else /* FIFONumber == CAN_FIFO1 */
- {
- pRxMsg = hcan->pRx1Msg;
- }
-
- /* Get the Id */
- pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
- if (pRxMsg->IDE == CAN_ID_STD)
- {
- pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
+ /* Reset CAN error code */
+ hcan->ErrorCode = 0U;
}
else
{
- pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
- }
-
- pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
- /* Get the DLC */
- pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
- /* Get the FIFONumber */
- pRxMsg->FIFONumber = FIFONumber;
- /* Get the FMI */
- pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
- /* Get the data field */
- pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
- pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
- pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
- pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
- pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
- pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
- pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
- pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
- /* Release the FIFO */
- /* Release FIFO0 */
- if (FIFONumber == CAN_FIFO0)
- {
- __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
- /* Disable FIFO 0 overrun and message pending Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0);
- }
- /* Release FIFO1 */
- else /* FIFONumber == CAN_FIFO1 */
- {
- __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
-
- /* Disable FIFO 1 overrun and message pending Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1);
- }
-
- tmp1 = hcan->State;
- if((tmp1 == HAL_CAN_STATE_BUSY_RX0) || (tmp1 == HAL_CAN_STATE_BUSY_RX1))
- {
- /* Disable Error warning, Error passive, Bus-off, Last error code
- and Error Interrupts */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
- CAN_IT_EPV |
- CAN_IT_BOF |
- CAN_IT_LEC |
- CAN_IT_ERR);
+ status = HAL_ERROR;
}
- /* Change CAN state */
- if (FIFONumber == CAN_FIFO0)
- {
- switch(hcan->State)
- {
- case(HAL_CAN_STATE_BUSY_TX_RX0):
- hcan->State = HAL_CAN_STATE_BUSY_TX;
- break;
- case(HAL_CAN_STATE_BUSY_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
- break;
- default: /* HAL_CAN_STATE_BUSY_RX0 */
- hcan->State = HAL_CAN_STATE_READY;
- break;
- }
- }
- else /* FIFONumber == CAN_FIFO1 */
- {
- switch(hcan->State)
- {
- case(HAL_CAN_STATE_BUSY_TX_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX;
- break;
- case(HAL_CAN_STATE_BUSY_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_RX0;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
- break;
- default: /* HAL_CAN_STATE_BUSY_RX1 */
- hcan->State = HAL_CAN_STATE_READY;
- break;
- }
- }
-
- /* Receive complete callback */
- HAL_CAN_RxCpltCallback(hcan);
-
- /* Return function status */
- return HAL_OK;
+ /* Return the status */
+ return status;
}
/**
* @}
*/
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
- STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
- STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
-
-#endif /* HAL_CAN_MODULE_ENABLED */
-/**
- * @}
- */
/**
* @}
*/
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+#endif /* CAN1 */
+
+/**
+ * @}
+ */
+
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_can.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_can.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,13 +2,11 @@
******************************************************************************
* @file stm32f4xx_hal_can.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief Header file of CAN HAL module.
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -36,18 +34,13 @@
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F4xx_HAL_CAN_H
-#define __STM32F4xx_HAL_CAN_H
+#ifndef STM32F4xx_HAL_CAN_H
+#define STM32F4xx_HAL_CAN_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
- defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
- defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
- defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
- defined(STM32F423xx)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
@@ -55,6 +48,7 @@
* @{
*/
+#if defined (CAN1)
/** @addtogroup CAN
* @{
*/
@@ -63,7 +57,6 @@
/** @defgroup CAN_Exported_Types CAN Exported Types
* @{
*/
-
/**
* @brief HAL State structures definition
*/
@@ -71,59 +64,53 @@
{
HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */
HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */
- HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */
- HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */
- HAL_CAN_STATE_BUSY_RX0 = 0x22U, /*!< CAN process is ongoing */
- HAL_CAN_STATE_BUSY_RX1 = 0x32U, /*!< CAN process is ongoing */
- HAL_CAN_STATE_BUSY_TX_RX0 = 0x42U, /*!< CAN process is ongoing */
- HAL_CAN_STATE_BUSY_TX_RX1 = 0x52U, /*!< CAN process is ongoing */
- HAL_CAN_STATE_BUSY_RX0_RX1 = 0x62U, /*!< CAN process is ongoing */
- HAL_CAN_STATE_BUSY_TX_RX0_RX1 = 0x72U, /*!< CAN process is ongoing */
- HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< CAN in Timeout state */
- HAL_CAN_STATE_ERROR = 0x04U /*!< CAN error state */
+ HAL_CAN_STATE_LISTENING = 0x02U, /*!< CAN receive process is ongoing */
+ HAL_CAN_STATE_SLEEP_PENDING = 0x03U, /*!< CAN sleep request is pending */
+ HAL_CAN_STATE_SLEEP_ACTIVE = 0x04U, /*!< CAN sleep mode is active */
+ HAL_CAN_STATE_ERROR = 0x05U /*!< CAN error state */
-}HAL_CAN_StateTypeDef;
+} HAL_CAN_StateTypeDef;
/**
* @brief CAN init structure definition
*/
typedef struct
{
- uint32_t Prescaler; /*!< Specifies the length of a time quantum.
- This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
+ uint32_t Prescaler; /*!< Specifies the length of a time quantum.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */
- uint32_t Mode; /*!< Specifies the CAN operating mode.
- This parameter can be a value of @ref CAN_operating_mode */
+ uint32_t Mode; /*!< Specifies the CAN operating mode.
+ This parameter can be a value of @ref CAN_operating_mode */
- uint32_t SJW; /*!< Specifies the maximum number of time quanta
- the CAN hardware is allowed to lengthen or
- shorten a bit to perform resynchronization.
- This parameter can be a value of @ref CAN_synchronisation_jump_width */
+ uint32_t SyncJumpWidth; /*!< Specifies the maximum number of time quanta the CAN hardware
+ is allowed to lengthen or shorten a bit to perform resynchronization.
+ This parameter can be a value of @ref CAN_synchronisation_jump_width */
- uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1.
- This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
+ uint32_t TimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1.
+ This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
- uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
- This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
+ uint32_t TimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2.
+ This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
- uint32_t TTCM; /*!< Enable or disable the time triggered communication mode.
- This parameter can be set to ENABLE or DISABLE. */
+ FunctionalState TimeTriggeredMode; /*!< Enable or disable the time triggered communication mode.
+ This parameter can be set to ENABLE or DISABLE. */
- uint32_t ABOM; /*!< Enable or disable the automatic bus-off management.
- This parameter can be set to ENABLE or DISABLE */
+ FunctionalState AutoBusOff; /*!< Enable or disable the automatic bus-off management.
+ This parameter can be set to ENABLE or DISABLE. */
- uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode.
- This parameter can be set to ENABLE or DISABLE */
+ FunctionalState AutoWakeUp; /*!< Enable or disable the automatic wake-up mode.
+ This parameter can be set to ENABLE or DISABLE. */
- uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode.
- This parameter can be set to ENABLE or DISABLE */
+ FunctionalState AutoRetransmission; /*!< Enable or disable the non-automatic retransmission mode.
+ This parameter can be set to ENABLE or DISABLE. */
- uint32_t RFLM; /*!< Enable or disable the receive FIFO Locked mode.
- This parameter can be set to ENABLE or DISABLE */
+ FunctionalState ReceiveFifoLocked; /*!< Enable or disable the Receive FIFO Locked mode.
+ This parameter can be set to ENABLE or DISABLE. */
- uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority.
- This parameter can be set to ENABLE or DISABLE */
-}CAN_InitTypeDef;
+ FunctionalState TransmitFifoPriority;/*!< Enable or disable the transmit FIFO priority.
+ This parameter can be set to ENABLE or DISABLE. */
+
+} CAN_InitTypeDef;
/**
* @brief CAN filter configuration structure definition
@@ -132,27 +119,30 @@
{
uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
configuration, first one for a 16-bit configuration).
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
configuration, second one for a 16-bit configuration).
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
according to the mode (MSBs for a 32-bit configuration,
first one for a 16-bit configuration).
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
according to the mode (LSBs for a 32-bit configuration,
second one for a 16-bit configuration).
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
- uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
+ uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter.
This parameter can be a value of @ref CAN_filter_FIFO */
- uint32_t FilterNumber; /*!< Specifies the filter which will be initialized.
- This parameter must be a number between Min_Data = 0 and Max_Data = 27 */
+ uint32_t FilterBank; /*!< Specifies the filter bank which will be initialized.
+ For single CAN instance(14 dedicated filter banks),
+ this parameter must be a number between Min_Data = 0 and Max_Data = 13.
+ For dual CAN instances(28 filter banks shared),
+ this parameter must be a number between Min_Data = 0 and Max_Data = 27. */
uint32_t FilterMode; /*!< Specifies the filter mode to be initialized.
This parameter can be a value of @ref CAN_filter_mode */
@@ -163,95 +153,94 @@
uint32_t FilterActivation; /*!< Enable or disable the filter.
This parameter can be set to ENABLE or DISABLE. */
- uint32_t BankNumber; /*!< Select the start slave bank filter.
- This parameter must be a number between Min_Data = 0 and Max_Data = 28 */
+ uint32_t SlaveStartFilterBank; /*!< Select the start filter bank for the slave CAN instance.
+ For single CAN instances, this parameter is meaningless.
+ For dual CAN instances, all filter banks with lower index are assigned to master
+ CAN instance, whereas all filter banks with greater index are assigned to slave
+ CAN instance.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 27. */
-}CAN_FilterConfTypeDef;
+} CAN_FilterTypeDef;
/**
- * @brief CAN Tx message structure definition
+ * @brief CAN Tx message header structure definition
*/
typedef struct
{
uint32_t StdId; /*!< Specifies the standard identifier.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
uint32_t ExtId; /*!< Specifies the extended identifier.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
- This parameter can be a value of @ref CAN_Identifier_Type */
+ This parameter can be a value of @ref CAN_identifier_type */
uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
This parameter can be a value of @ref CAN_remote_transmission_request */
uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
- This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
+ This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
- uint8_t Data[8]; /*!< Contains the data to be transmitted.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
+ FunctionalState TransmitGlobalTime; /*!< Specifies whether the timestamp counter value captured on start
+ of frame transmission, is sent in DATA6 and DATA7 replacing pData[6] and pData[7].
+ @note: Time Triggered Communication Mode must be enabled.
+ @note: DLC must be programmed as 8 bytes, in order these 2 bytes are sent.
+ This parameter can be set to ENABLE or DISABLE. */
-}CanTxMsgTypeDef;
+} CAN_TxHeaderTypeDef;
/**
- * @brief CAN Rx message structure definition
+ * @brief CAN Rx message header structure definition
*/
typedef struct
{
- uint32_t StdId; /*!< Specifies the standard identifier.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
+ uint32_t StdId; /*!< Specifies the standard identifier.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
- uint32_t ExtId; /*!< Specifies the extended identifier.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
+ uint32_t ExtId; /*!< Specifies the extended identifier.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
- uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received.
- This parameter can be a value of @ref CAN_Identifier_Type */
+ uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
+ This parameter can be a value of @ref CAN_identifier_type */
- uint32_t RTR; /*!< Specifies the type of frame for the received message.
- This parameter can be a value of @ref CAN_remote_transmission_request */
+ uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
+ This parameter can be a value of @ref CAN_remote_transmission_request */
- uint32_t DLC; /*!< Specifies the length of the frame that will be received.
- This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
-
- uint8_t Data[8]; /*!< Contains the data to be received.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
+ uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
- uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
+ uint32_t Timestamp; /*!< Specifies the timestamp counter value captured on start of frame reception.
+ @note: Time Triggered Communication Mode must be enabled.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0xFFFF. */
- uint32_t FIFONumber; /*!< Specifies the receive FIFO number.
- This parameter can be CAN_FIFO0 or CAN_FIFO1 */
+ uint32_t FilterMatchIndex; /*!< Specifies the index of matching acceptance filter element.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
-}CanRxMsgTypeDef;
+} CAN_RxHeaderTypeDef;
/**
* @brief CAN handle Structure definition
*/
-typedef struct
+typedef struct __CAN_HandleTypeDef
{
- CAN_TypeDef *Instance; /*!< Register base address */
+ CAN_TypeDef *Instance; /*!< Register base address */
- CAN_InitTypeDef Init; /*!< CAN required parameters */
-
- CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */
-
- CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure for RX FIFO0 msg */
+ CAN_InitTypeDef Init; /*!< CAN required parameters */
- CanRxMsgTypeDef* pRx1Msg; /*!< Pointer to reception structure for RX FIFO1 msg */
-
- __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
+ __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
- HAL_LockTypeDef Lock; /*!< CAN locking object */
+ __IO uint32_t ErrorCode; /*!< CAN Error code.
+ This parameter can be a value of @ref CAN_Error_Code */
- __IO uint32_t ErrorCode; /*!< CAN Error code */
-
-}CAN_HandleTypeDef;
+} CAN_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
+
/** @defgroup CAN_Exported_Constants CAN Exported Constants
* @{
*/
@@ -259,19 +248,30 @@
/** @defgroup CAN_Error_Code CAN Error Code
* @{
*/
-#define HAL_CAN_ERROR_NONE 0x00000000U /*!< No error */
-#define HAL_CAN_ERROR_EWG 0x00000001U /*!< EWG error */
-#define HAL_CAN_ERROR_EPV 0x00000002U /*!< EPV error */
-#define HAL_CAN_ERROR_BOF 0x00000004U /*!< BOF error */
-#define HAL_CAN_ERROR_STF 0x00000008U /*!< Stuff error */
-#define HAL_CAN_ERROR_FOR 0x00000010U /*!< Form error */
-#define HAL_CAN_ERROR_ACK 0x00000020U /*!< Acknowledgment error */
-#define HAL_CAN_ERROR_BR 0x00000040U /*!< Bit recessive */
-#define HAL_CAN_ERROR_BD 0x00000080U /*!< LEC dominant */
-#define HAL_CAN_ERROR_CRC 0x00000100U /*!< LEC transfer error */
-#define HAL_CAN_ERROR_FOV0 0x00000200U /*!< FIFO0 overrun error */
-#define HAL_CAN_ERROR_FOV1 0x00000400U /*!< FIFO1 overrun error */
-#define HAL_CAN_ERROR_TXFAIL 0x00000800U /*!< Transmit failure */
+#define HAL_CAN_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_CAN_ERROR_EWG (0x00000001U) /*!< Protocol Error Warning */
+#define HAL_CAN_ERROR_EPV (0x00000002U) /*!< Error Passive */
+#define HAL_CAN_ERROR_BOF (0x00000004U) /*!< Bus-off error */
+#define HAL_CAN_ERROR_STF (0x00000008U) /*!< Stuff error */
+#define HAL_CAN_ERROR_FOR (0x00000010U) /*!< Form error */
+#define HAL_CAN_ERROR_ACK (0x00000020U) /*!< Acknowledgment error */
+#define HAL_CAN_ERROR_BR (0x00000040U) /*!< Bit recessive error */
+#define HAL_CAN_ERROR_BD (0x00000080U) /*!< Bit dominant error */
+#define HAL_CAN_ERROR_CRC (0x00000100U) /*!< CRC error */
+#define HAL_CAN_ERROR_RX_FOV0 (0x00000200U) /*!< Rx FIFO0 overrun error */
+#define HAL_CAN_ERROR_RX_FOV1 (0x00000400U) /*!< Rx FIFO1 overrun error */
+#define HAL_CAN_ERROR_TX_ALST0 (0x00000800U) /*!< TxMailbox 0 transmit failure due to arbitration lost */
+#define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 1 transmit failure due to tranmit error */
+#define HAL_CAN_ERROR_TX_ALST1 (0x00002000U) /*!< TxMailbox 0 transmit failure due to arbitration lost */
+#define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to tranmit error */
+#define HAL_CAN_ERROR_TX_ALST2 (0x00008000U) /*!< TxMailbox 0 transmit failure due to arbitration lost */
+#define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 1 transmit failure due to tranmit error */
+#define HAL_CAN_ERROR_TIMEOUT (0x00020000U) /*!< Timeout error */
+#define HAL_CAN_ERROR_NOT_INITIALIZED (0x00040000U) /*!< Peripheral not initialized */
+#define HAL_CAN_ERROR_NOT_READY (0x00080000U) /*!< Peripheral not ready */
+#define HAL_CAN_ERROR_NOT_STARTED (0x00100000U) /*!< Peripheral not started */
+#define HAL_CAN_ERROR_PARAM (0x00200000U) /*!< Parameter error */
+
/**
* @}
*/
@@ -279,8 +279,8 @@
/** @defgroup CAN_InitStatus CAN InitStatus
* @{
*/
-#define CAN_INITSTATUS_FAILED ((uint8_t)0x00) /*!< CAN initialization failed */
-#define CAN_INITSTATUS_SUCCESS ((uint8_t)0x01) /*!< CAN initialization OK */
+#define CAN_INITSTATUS_FAILED (0x00000000U) /*!< CAN initialization failed */
+#define CAN_INITSTATUS_SUCCESS (0x00000001U) /*!< CAN initialization OK */
/**
* @}
*/
@@ -288,7 +288,7 @@
/** @defgroup CAN_operating_mode CAN Operating Mode
* @{
*/
-#define CAN_MODE_NORMAL 0x00000000U /*!< Normal mode */
+#define CAN_MODE_NORMAL (0x00000000U) /*!< Normal mode */
#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */
#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */
#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */
@@ -296,10 +296,11 @@
* @}
*/
-/** @defgroup CAN_synchronisation_jump_width CAN Synchronisation Jump Width
+
+/** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width
* @{
*/
-#define CAN_SJW_1TQ 0x00000000U /*!< 1 time quantum */
+#define CAN_SJW_1TQ (0x00000000U) /*!< 1 time quantum */
#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */
#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */
#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */
@@ -307,10 +308,10 @@
* @}
*/
-/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in bit segment 1
+/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1
* @{
*/
-#define CAN_BS1_1TQ 0x00000000U /*!< 1 time quantum */
+#define CAN_BS1_1TQ (0x00000000U) /*!< 1 time quantum */
#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */
#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */
#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */
@@ -330,10 +331,10 @@
* @}
*/
-/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in bit segment 2
+/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2
* @{
*/
-#define CAN_BS2_1TQ 0x00000000U /*!< 1 time quantum */
+#define CAN_BS2_1TQ (0x00000000U) /*!< 1 time quantum */
#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */
#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */
#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */
@@ -345,11 +346,11 @@
* @}
*/
-/** @defgroup CAN_filter_mode CAN Filter Mode
+/** @defgroup CAN_filter_mode CAN Filter Mode
* @{
*/
-#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */
-#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */
+#define CAN_FILTERMODE_IDMASK (0x00000000U) /*!< Identifier mask mode */
+#define CAN_FILTERMODE_IDLIST (0x00000001U) /*!< Identifier list mode */
/**
* @}
*/
@@ -357,8 +358,8 @@
/** @defgroup CAN_filter_scale CAN Filter Scale
* @{
*/
-#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */
-#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */
+#define CAN_FILTERSCALE_16BIT (0x00000000U) /*!< Two 16-bit filters */
+#define CAN_FILTERSCALE_32BIT (0x00000001U) /*!< One 32-bit filter */
/**
* @}
*/
@@ -366,17 +367,17 @@
/** @defgroup CAN_filter_FIFO CAN Filter FIFO
* @{
*/
-#define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
-#define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
+#define CAN_FILTER_FIFO0 (0x00000000U) /*!< Filter FIFO 0 assignment for filter x */
+#define CAN_FILTER_FIFO1 (0x00000001U) /*!< Filter FIFO 1 assignment for filter x */
/**
* @}
*/
-/** @defgroup CAN_Identifier_Type CAN Identifier Type
+/** @defgroup CAN_identifier_type CAN Identifier Type
* @{
*/
-#define CAN_ID_STD 0x00000000U /*!< Standard Id */
-#define CAN_ID_EXT 0x00000004U /*!< Extended Id */
+#define CAN_ID_STD (0x00000000U) /*!< Standard Id */
+#define CAN_ID_EXT (0x00000004U) /*!< Extended Id */
/**
* @}
*/
@@ -384,17 +385,27 @@
/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
* @{
*/
-#define CAN_RTR_DATA 0x00000000U /*!< Data frame */
-#define CAN_RTR_REMOTE 0x00000002U /*!< Remote frame */
+#define CAN_RTR_DATA (0x00000000U) /*!< Data frame */
+#define CAN_RTR_REMOTE (0x00000002U) /*!< Remote frame */
/**
* @}
*/
-/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number Constants
+/** @defgroup CAN_receive_FIFO_number CAN Receive FIFO Number
* @{
*/
-#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
-#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
+#define CAN_RX_FIFO0 (0x00000000U) /*!< CAN receive FIFO 0 */
+#define CAN_RX_FIFO1 (0x00000001U) /*!< CAN receive FIFO 1 */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Tx_Mailboxes CAN Tx Mailboxes
+ * @{
+ */
+#define CAN_TX_MAILBOX0 (0x00000001U) /*!< Tx Mailbox 0 */
+#define CAN_TX_MAILBOX1 (0x00000002U) /*!< Tx Mailbox 1 */
+#define CAN_TX_MAILBOX2 (0x00000004U) /*!< Tx Mailbox 2 */
/**
* @}
*/
@@ -402,80 +413,72 @@
/** @defgroup CAN_flags CAN Flags
* @{
*/
-/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
- and CAN_ClearFlag() functions. */
-/* If the flag is 0x1XXXXXXX, it means that it can only be used with
- CAN_GetFlagStatus() function. */
-
/* Transmit Flags */
-#define CAN_FLAG_RQCP0 0x00000500U /*!< Request MailBox0 flag */
-#define CAN_FLAG_RQCP1 0x00000508U /*!< Request MailBox1 flag */
-#define CAN_FLAG_RQCP2 0x00000510U /*!< Request MailBox2 flag */
-#define CAN_FLAG_TXOK0 0x00000501U /*!< Transmission OK MailBox0 flag */
-#define CAN_FLAG_TXOK1 0x00000509U /*!< Transmission OK MailBox1 flag */
-#define CAN_FLAG_TXOK2 0x00000511U /*!< Transmission OK MailBox2 flag */
-#define CAN_FLAG_TME0 0x0000051AU /*!< Transmit mailbox 0 empty flag */
-#define CAN_FLAG_TME1 0x0000051BU /*!< Transmit mailbox 0 empty flag */
-#define CAN_FLAG_TME2 0x0000051CU /*!< Transmit mailbox 0 empty flag */
+#define CAN_FLAG_RQCP0 (0x00000500U) /*!< Request complete MailBox 0 flag */
+#define CAN_FLAG_TXOK0 (0x00000501U) /*!< Transmission OK MailBox 0 flag */
+#define CAN_FLAG_ALST0 (0x00000502U) /*!< Arbitration Lost MailBox 0 flag */
+#define CAN_FLAG_TERR0 (0x00000503U) /*!< Transmission error MailBox 0 flag */
+#define CAN_FLAG_RQCP1 (0x00000508U) /*!< Request complete MailBox1 flag */
+#define CAN_FLAG_TXOK1 (0x00000509U) /*!< Transmission OK MailBox 1 flag */
+#define CAN_FLAG_ALST1 (0x0000050AU) /*!< Arbitration Lost MailBox 1 flag */
+#define CAN_FLAG_TERR1 (0x0000050BU) /*!< Transmission error MailBox 1 flag */
+#define CAN_FLAG_RQCP2 (0x00000510U) /*!< Request complete MailBox2 flag */
+#define CAN_FLAG_TXOK2 (0x00000511U) /*!< Transmission OK MailBox 2 flag */
+#define CAN_FLAG_ALST2 (0x00000512U) /*!< Arbitration Lost MailBox 2 flag */
+#define CAN_FLAG_TERR2 (0x00000513U) /*!< Transmission error MailBox 2 flag */
+#define CAN_FLAG_TME0 (0x0000051AU) /*!< Transmit mailbox 0 empty flag */
+#define CAN_FLAG_TME1 (0x0000051BU) /*!< Transmit mailbox 1 empty flag */
+#define CAN_FLAG_TME2 (0x0000051CU) /*!< Transmit mailbox 2 empty flag */
+#define CAN_FLAG_LOW0 (0x0000051DU) /*!< Lowest priority mailbox 0 flag */
+#define CAN_FLAG_LOW1 (0x0000051EU) /*!< Lowest priority mailbox 1 flag */
+#define CAN_FLAG_LOW2 (0x0000051FU) /*!< Lowest priority mailbox 2 flag */
/* Receive Flags */
-#define CAN_FLAG_FF0 0x00000203U /*!< FIFO 0 Full flag */
-#define CAN_FLAG_FOV0 0x00000204U /*!< FIFO 0 Overrun flag */
-
-#define CAN_FLAG_FF1 0x00000403U /*!< FIFO 1 Full flag */
-#define CAN_FLAG_FOV1 0x00000404U /*!< FIFO 1 Overrun flag */
+#define CAN_FLAG_FF0 (0x00000203U) /*!< RX FIFO 0 Full flag */
+#define CAN_FLAG_FOV0 (0x00000204U) /*!< RX FIFO 0 Overrun flag */
+#define CAN_FLAG_FF1 (0x00000403U) /*!< RX FIFO 1 Full flag */
+#define CAN_FLAG_FOV1 (0x00000404U) /*!< RX FIFO 1 Overrun flag */
/* Operating Mode Flags */
-#define CAN_FLAG_INAK 0x00000100U /*!< Initialization acknowledge flag */
-#define CAN_FLAG_SLAK 0x00000101U /*!< Sleep acknowledge flag */
-#define CAN_FLAG_ERRI 0x00000102U /*!< Error flag */
-#define CAN_FLAG_WKU 0x00000103U /*!< Wake up flag */
-#define CAN_FLAG_SLAKI 0x00000104U /*!< Sleep acknowledge flag */
-
-/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
- In this case the SLAK bit can be polled.*/
+#define CAN_FLAG_INAK (0x00000100U) /*!< Initialization acknowledge flag */
+#define CAN_FLAG_SLAK (0x00000101U) /*!< Sleep acknowledge flag */
+#define CAN_FLAG_ERRI (0x00000102U) /*!< Error flag */
+#define CAN_FLAG_WKU (0x00000103U) /*!< Wake up interrupt flag */
+#define CAN_FLAG_SLAKI (0x00000104U) /*!< Sleep acknowledge interrupt flag */
/* Error Flags */
-#define CAN_FLAG_EWG 0x00000300U /*!< Error warning flag */
-#define CAN_FLAG_EPV 0x00000301U /*!< Error passive flag */
-#define CAN_FLAG_BOF 0x00000302U /*!< Bus-Off flag */
+#define CAN_FLAG_EWG (0x00000300U) /*!< Error warning flag */
+#define CAN_FLAG_EPV (0x00000301U) /*!< Error passive flag */
+#define CAN_FLAG_BOF (0x00000302U) /*!< Bus-Off flag */
/**
* @}
*/
+
/** @defgroup CAN_Interrupts CAN Interrupts
* @{
*/
-#define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */
+/* Transmit Interrupt */
+#define CAN_IT_TX_MAILBOX_EMPTY ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */
/* Receive Interrupts */
-#define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */
-#define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */
-#define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */
-#define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */
-#define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */
-#define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */
+#define CAN_IT_RX_FIFO0_MSG_PENDING ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */
+#define CAN_IT_RX_FIFO0_FULL ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */
+#define CAN_IT_RX_FIFO0_OVERRUN ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */
+#define CAN_IT_RX_FIFO1_MSG_PENDING ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */
+#define CAN_IT_RX_FIFO1_FULL ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */
+#define CAN_IT_RX_FIFO1_OVERRUN ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */
/* Operating Mode Interrupts */
-#define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */
-#define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */
+#define CAN_IT_WAKEUP ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */
+#define CAN_IT_SLEEP_ACK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */
/* Error Interrupts */
-#define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */
-#define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */
-#define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */
-#define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
-#define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */
-/**
- * @}
- */
-
-/** @defgroup CAN_Mailboxes_Definition CAN Mailboxes Definition
- * @{
- */
-#define CAN_TXMAILBOX_0 ((uint8_t)0x00)
-#define CAN_TXMAILBOX_1 ((uint8_t)0x01)
-#define CAN_TXMAILBOX_2 ((uint8_t)0x02)
+#define CAN_IT_ERROR_WARNING ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */
+#define CAN_IT_ERROR_PASSIVE ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */
+#define CAN_IT_BUSOFF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */
+#define CAN_IT_LAST_ERROR_CODE ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
+#define CAN_IT_ERROR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */
/**
* @}
*/
@@ -484,213 +487,198 @@
* @}
*/
-/* Exported macro ------------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
/** @defgroup CAN_Exported_Macros CAN Exported Macros
* @{
*/
-/** @brief Reset CAN handle state
- * @param __HANDLE__: specifies the CAN Handle.
+/** @brief Reset CAN handle state
+ * @param __HANDLE__ CAN handle.
* @retval None
*/
#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
/**
* @brief Enable the specified CAN interrupts.
- * @param __HANDLE__: CAN handle
- * @param __INTERRUPT__: CAN Interrupt
+ * @param __HANDLE__ CAN handle.
+ * @param __INTERRUPT__ CAN Interrupt sources to enable.
+ * This parameter can be any combination of @arg CAN_Interrupts
* @retval None
*/
#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
/**
* @brief Disable the specified CAN interrupts.
- * @param __HANDLE__: CAN handle
- * @param __INTERRUPT__: CAN Interrupt
+ * @param __HANDLE__ CAN handle.
+ * @param __INTERRUPT__ CAN Interrupt sources to disable.
+ * This parameter can be any combination of @arg CAN_Interrupts
* @retval None
*/
#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
-/**
- * @brief Return the number of pending received messages.
- * @param __HANDLE__: CAN handle
- * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
- * @retval The number of pending message.
+/** @brief Check if the specified CAN interrupt source is enabled or disabled.
+ * @param __HANDLE__ specifies the CAN Handle.
+ * @param __INTERRUPT__ specifies the CAN interrupt source to check.
+ * This parameter can be a value of @arg CAN_Interrupts
+ * @retval The state of __IT__ (TRUE or FALSE).
*/
-#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
-((uint8_t)((__HANDLE__)->Instance->RF0R&0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R & 0x03U)))
+#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) & (__INTERRUPT__))
/** @brief Check whether the specified CAN flag is set or not.
- * @param __HANDLE__: CAN Handle
- * @param __FLAG__: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg CAN_TSR_RQCP0: Request MailBox0 Flag
- * @arg CAN_TSR_RQCP1: Request MailBox1 Flag
- * @arg CAN_TSR_RQCP2: Request MailBox2 Flag
- * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
- * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
- * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
- * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
- * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
- * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
- * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
- * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
- * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
- * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
- * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
- * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
- * @arg CAN_FLAG_WKU: Wake up Flag
- * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
- * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
- * @arg CAN_FLAG_EWG: Error Warning Flag
- * @arg CAN_FLAG_EPV: Error Passive Flag
- * @arg CAN_FLAG_BOF: Bus-Off Flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
+ * @param __HANDLE__ specifies the CAN Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of @arg CAN_flags
+ * @retval The state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
-((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))))
+ ((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 3U)? ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)
/** @brief Clear the specified CAN pending flag.
- * @param __HANDLE__: CAN Handle.
- * @param __FLAG__: specifies the flag to check.
+ * @param __HANDLE__ specifies the CAN Handle.
+ * @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
- * @arg CAN_TSR_RQCP0: Request MailBox0 Flag
- * @arg CAN_TSR_RQCP1: Request MailBox1 Flag
- * @arg CAN_TSR_RQCP2: Request MailBox2 Flag
- * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
- * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
- * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
- * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
- * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
- * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
- * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
- * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
- * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
- * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
- * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
- * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
- * @arg CAN_FLAG_WKU: Wake up Flag
- * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
- * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
+ * @arg CAN_FLAG_RQCP0: Request complete MailBox 0 Flag
+ * @arg CAN_FLAG_TXOK0: Transmission OK MailBox 0 Flag
+ * @arg CAN_FLAG_ALST0: Arbitration Lost MailBox 0 Flag
+ * @arg CAN_FLAG_TERR0: Transmission error MailBox 0 Flag
+ * @arg CAN_FLAG_RQCP1: Request complete MailBox 1 Flag
+ * @arg CAN_FLAG_TXOK1: Transmission OK MailBox 1 Flag
+ * @arg CAN_FLAG_ALST1: Arbitration Lost MailBox 1 Flag
+ * @arg CAN_FLAG_TERR1: Transmission error MailBox 1 Flag
+ * @arg CAN_FLAG_RQCP2: Request complete MailBox 2 Flag
+ * @arg CAN_FLAG_TXOK2: Transmission OK MailBox 2 Flag
+ * @arg CAN_FLAG_ALST2: Arbitration Lost MailBox 2 Flag
+ * @arg CAN_FLAG_TERR2: Transmission error MailBox 2 Flag
+ * @arg CAN_FLAG_FF0: RX FIFO 0 Full Flag
+ * @arg CAN_FLAG_FOV0: RX FIFO 0 Overrun Flag
+ * @arg CAN_FLAG_FF1: RX FIFO 1 Full Flag
+ * @arg CAN_FLAG_FOV1: RX FIFO 1 Overrun Flag
+ * @arg CAN_FLAG_WKUI: Wake up Interrupt Flag
+ * @arg CAN_FLAG_SLAKI: Sleep acknowledge Interrupt Flag
+ * @retval None
*/
#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
-((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__HANDLE__)->Instance->MSR) = ((uint32_t)1U << ((__FLAG__) & CAN_FLAG_MASK))))
-
-/** @brief Check if the specified CAN interrupt source is enabled or disabled.
- * @param __HANDLE__: CAN Handle
- * @param __INTERRUPT__: specifies the CAN interrupt source to check.
- * This parameter can be one of the following values:
- * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
- * @arg CAN_IT_FMP0: FIFO0 message pending interrupt enable
- * @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+ ((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)
/**
- * @brief Check the transmission status of a CAN Frame.
- * @param __HANDLE__: CAN Handle
- * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
- * @retval The new status of transmission (TRUE or FALSE).
- */
-#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\
-(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\
- ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\
- ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)))
-
-/**
- * @brief Release the specified receive FIFO.
- * @param __HANDLE__: CAN handle
- * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
- * @retval None
- */
-#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
-((__HANDLE__)->Instance->RF0R = CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R = CAN_RF1R_RFOM1))
-
-/**
- * @brief Cancel a transmit request.
- * @param __HANDLE__: CAN Handle
- * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
- * @retval None
- */
-#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
-(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ0) :\
- ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ1) :\
- ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ2))
-
-/**
- * @brief Enable or disable the DBG Freeze for CAN.
- * @param __HANDLE__: CAN Handle
- * @param __NEWSTATE__: new state of the CAN peripheral.
- * This parameter can be: ENABLE (CAN reception/transmission is frozen
- * during debug. Reception FIFOs can still be accessed/controlled normally)
- * or DISABLE (CAN is working during debug).
- * @retval None
- */
-#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
-((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))
-
-/**
- * @}
- */
+ * @}
+ */
/* Exported functions --------------------------------------------------------*/
-/** @addtogroup CAN_Exported_Functions
+/** @addtogroup CAN_Exported_Functions CAN Exported Functions
* @{
*/
-/** @addtogroup CAN_Exported_Functions_Group1
- * @{
- */
-/* Initialization/de-initialization functions ***********************************/
-HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);
-HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);
-HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);
-void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
-void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
+/** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan);
+void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan);
+void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan);
+
/**
- * @}
- */
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group2 Configuration functions
+ * @brief Configuration functions
+ * @{
+ */
+
+/* Configuration functions ****************************************************/
+HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig);
-/** @addtogroup CAN_Exported_Functions_Group2
- * @{
- */
-/* I/O operation functions ******************************************************/
-HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);
-HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);
-HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group3 Control functions
+ * @brief Control functions
+ * @{
+ */
+
+/* Control functions **********************************************************/
+HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan);
HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
-void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);
-void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);
-void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
-void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
-/**
- * @}
- */
-
-/** @addtogroup CAN_Exported_Functions_Group3
- * @{
- */
-/* Peripheral State functions ***************************************************/
-uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
-HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
-/**
- * @}
- */
+uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox);
+HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes);
+uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan);
+uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes);
+uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox);
+HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]);
+uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo);
/**
- * @}
- */
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group4 Interrupts management
+ * @brief Interrupts management
+ * @{
+ */
+/* Interrupts management ******************************************************/
+HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs);
+HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs);
+void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan);
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group5 Callback functions
+ * @brief Callback functions
+ * @{
+ */
+/* Callbacks functions ********************************************************/
+
+void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group6 Peripheral State and Error functions
+ * @brief CAN Peripheral State functions
+ * @{
+ */
+/* Peripheral State and Error functions ***************************************/
+HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan);
+uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
/* Private types -------------------------------------------------------------*/
/** @defgroup CAN_Private_Types CAN Private Types
@@ -708,71 +696,80 @@
/**
* @}
- */
+ */
/* Private constants ---------------------------------------------------------*/
/** @defgroup CAN_Private_Constants CAN Private Constants
* @{
*/
-#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
-#define CAN_FLAG_MASK 0x000000FFU
+#define CAN_FLAG_MASK (0x000000FFU)
/**
* @}
*/
-/* Private macros ------------------------------------------------------------*/
+/* Private Macros -----------------------------------------------------------*/
/** @defgroup CAN_Private_Macros CAN Private Macros
* @{
*/
+
#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
((MODE) == CAN_MODE_LOOPBACK)|| \
((MODE) == CAN_MODE_SILENT) || \
((MODE) == CAN_MODE_SILENT_LOOPBACK))
-#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
+#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ) || \
((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
-#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
-#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
+#define IS_CAN_BS1(BS1) (((BS1) == CAN_BS1_1TQ) || ((BS1) == CAN_BS1_2TQ) || \
+ ((BS1) == CAN_BS1_3TQ) || ((BS1) == CAN_BS1_4TQ) || \
+ ((BS1) == CAN_BS1_5TQ) || ((BS1) == CAN_BS1_6TQ) || \
+ ((BS1) == CAN_BS1_7TQ) || ((BS1) == CAN_BS1_8TQ) || \
+ ((BS1) == CAN_BS1_9TQ) || ((BS1) == CAN_BS1_10TQ)|| \
+ ((BS1) == CAN_BS1_11TQ)|| ((BS1) == CAN_BS1_12TQ)|| \
+ ((BS1) == CAN_BS1_13TQ)|| ((BS1) == CAN_BS1_14TQ)|| \
+ ((BS1) == CAN_BS1_15TQ)|| ((BS1) == CAN_BS1_16TQ))
+#define IS_CAN_BS2(BS2) (((BS2) == CAN_BS2_1TQ) || ((BS2) == CAN_BS2_2TQ) || \
+ ((BS2) == CAN_BS2_3TQ) || ((BS2) == CAN_BS2_4TQ) || \
+ ((BS2) == CAN_BS2_5TQ) || ((BS2) == CAN_BS2_6TQ) || \
+ ((BS2) == CAN_BS2_7TQ) || ((BS2) == CAN_BS2_8TQ))
#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U))
-#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27U)
+#define IS_CAN_FILTER_ID_HALFWORD(HALFWORD) ((HALFWORD) <= 0xFFFFU)
+#define IS_CAN_FILTER_BANK_DUAL(BANK) ((BANK) <= 27U)
+#define IS_CAN_FILTER_BANK_SINGLE(BANK) ((BANK) <= 13U)
#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
((MODE) == CAN_FILTERMODE_IDLIST))
#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
((SCALE) == CAN_FILTERSCALE_32BIT))
#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
((FIFO) == CAN_FILTER_FIFO1))
-#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U)
-
-#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
-#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FFU))
+#define IS_CAN_TX_MAILBOX(TRANSMITMAILBOX) (((TRANSMITMAILBOX) == CAN_TX_MAILBOX0 ) || \
+ ((TRANSMITMAILBOX) == CAN_TX_MAILBOX1 ) || \
+ ((TRANSMITMAILBOX) == CAN_TX_MAILBOX2 ))
+#define IS_CAN_TX_MAILBOX_LIST(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= (CAN_TX_MAILBOX0 | CAN_TX_MAILBOX1 | CAN_TX_MAILBOX2))
+#define IS_CAN_STDID(STDID) ((STDID) <= 0x7FFU)
#define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU)
-#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
-
+#define IS_CAN_DLC(DLC) ((DLC) <= 8U)
#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
((IDTYPE) == CAN_ID_EXT))
#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
-#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
+#define IS_CAN_RX_FIFO(FIFO) (((FIFO) == CAN_RX_FIFO0) || ((FIFO) == CAN_RX_FIFO1))
+#define IS_CAN_IT(IT) ((IT) <= (CAN_IT_TX_MAILBOX_EMPTY | CAN_IT_RX_FIFO0_MSG_PENDING | \
+ CAN_IT_RX_FIFO0_FULL | CAN_IT_RX_FIFO0_OVERRUN | \
+ CAN_IT_RX_FIFO1_MSG_PENDING | CAN_IT_RX_FIFO1_FULL | \
+ CAN_IT_RX_FIFO1_OVERRUN | CAN_IT_WAKEUP | \
+ CAN_IT_SLEEP_ACK | CAN_IT_ERROR_WARNING | \
+ CAN_IT_ERROR_PASSIVE | CAN_IT_BUSOFF | \
+ CAN_IT_LAST_ERROR_CODE | CAN_IT_ERROR))
+
+/**
+ * @}
+ */
+/* End of private macros -----------------------------------------------------*/
/**
* @}
*/
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup CAN_Private_Functions CAN Private Functions
- * @{
- */
-/**
- * @}
- */
-
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
- STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
- STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
-
-/**
- * @}
- */
-
+#endif /* CAN1 */
/**
* @}
*/
@@ -781,7 +778,7 @@
}
#endif
-#endif /* __STM32F4xx_CAN_H */
+#endif /* STM32F4xx_HAL_CAN_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_can_legacy.c Tue Mar 20 16:56:18 2018 +0000
@@ -0,0 +1,1697 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_can.c
+ * @author MCD Application Team
+ * @brief This file provides firmware functions to manage the following
+ * functionalities of the Controller Area Network (CAN) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State and Error functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### User NOTE #####
+ ==============================================================================
+ [..]
+ (#) This HAL CAN driver is deprecated, it contains some CAN Tx/Rx FIFO management limitations.
+ Another HAL CAN driver version has been designed with new API's, to fix these limitations.
+
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Enable the CAN controller interface clock using
+ __HAL_RCC_CAN1_CLK_ENABLE() for CAN1, __HAL_RCC_CAN2_CLK_ENABLE() for CAN2
+ and __HAL_RCC_CAN3_CLK_ENABLE() for CAN3
+ -@- In case you are using CAN2 only, you have to enable the CAN1 clock.
+
+ (#) CAN pins configuration
+ (++) Enable the clock for the CAN GPIOs using the following function:
+ __GPIOx_CLK_ENABLE()
+ (++) Connect and configure the involved CAN pins to AF9 using the
+ following function HAL_GPIO_Init()
+
+ (#) Initialize and configure the CAN using CAN_Init() function.
+
+ (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function.
+
+ (#) Or transmit the desired CAN frame using HAL_CAN_Transmit_IT() function.
+
+ (#) Receive a CAN frame using HAL_CAN_Receive() function.
+
+ (#) Or receive a CAN frame using HAL_CAN_Receive_IT() function.
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Start the CAN peripheral transmission and wait the end of this operation
+ using HAL_CAN_Transmit(), at this stage user can specify the value of timeout
+ according to his end application
+ (+) Start the CAN peripheral reception and wait the end of this operation
+ using HAL_CAN_Receive(), at this stage user can specify the value of timeout
+ according to his end application
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT()
+ (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT()
+ (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine
+ (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_CAN_TxCpltCallback
+ (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_CAN_ErrorCallback
+
+ *** CAN HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in CAN HAL driver.
+
+ (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts
+ (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts
+ (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled
+ (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags
+ (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status
+
+ [..]
+ (@) You can refer to the CAN Legacy HAL driver header file for more useful macros
+
+ @endverbatim
+
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup CAN CAN
+ * @brief CAN driver modules
+ * @{
+ */
+
+#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
+ defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
+ defined(STM32F423xx)
+
+#ifdef HAL_CAN_MODULE_ENABLED
+/* Select HAL CAN module in stm32f4xx_hal_conf.h file:
+ (#) HAL_CAN_MODULE_ENABLED for new HAL CAN driver fixing FIFO limitations
+ (#) HAL_CAN_LEGACY_MODULE_ENABLED for legacy HAL CAN driver */
+#error 'The HAL CAN driver cannot be used with its legacy, Please ensure to enable only one HAL CAN module at once in stm32f4xx_hal_conf.h file'
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#warning 'Legacy HAL CAN driver is enabled! It can be used with known limitations, refer to the release notes. However it is recommended to use rather the new HAL CAN driver'
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup CAN_Private_Constants
+ * @{
+ */
+#define CAN_TIMEOUT_VALUE 10U
+/**
+ * @}
+ */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup CAN_Private_Functions
+ * @{
+ */
+static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber);
+static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CAN_Exported_Functions CAN Exported Functions
+ * @{
+ */
+
+/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de-initialization functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize and configure the CAN.
+ (+) De-initialize the CAN.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the CAN peripheral according to the specified
+ * parameters in the CAN_InitStruct.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
+{
+ uint32_t InitStatus = CAN_INITSTATUS_FAILED;
+ uint32_t tickstart = 0U;
+
+ /* Check CAN handle */
+ if(hcan == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP));
+ assert_param(IS_CAN_MODE(hcan->Init.Mode));
+ assert_param(IS_CAN_SJW(hcan->Init.SJW));
+ assert_param(IS_CAN_BS1(hcan->Init.BS1));
+ assert_param(IS_CAN_BS2(hcan->Init.BS2));
+ assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));
+
+
+ if(hcan->State == HAL_CAN_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hcan->Lock = HAL_UNLOCKED;
+ /* Init the low level hardware */
+ HAL_CAN_MspInit(hcan);
+ }
+
+ /* Initialize the CAN state*/
+ hcan->State = HAL_CAN_STATE_BUSY;
+
+ /* Exit from sleep mode */
+ hcan->Instance->MCR &= (~(uint32_t)CAN_MCR_SLEEP);
+
+ /* Request initialisation */
+ hcan->Instance->MCR |= CAN_MCR_INRQ ;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait the acknowledge */
+ while((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
+ {
+ if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE)
+ {
+ hcan->State= HAL_CAN_STATE_TIMEOUT;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Check acknowledge */
+ if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
+ {
+ /* Set the time triggered communication mode */
+ if (hcan->Init.TTCM == ENABLE)
+ {
+ hcan->Instance->MCR |= CAN_MCR_TTCM;
+ }
+ else
+ {
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TTCM;
+ }
+
+ /* Set the automatic bus-off management */
+ if (hcan->Init.ABOM == ENABLE)
+ {
+ hcan->Instance->MCR |= CAN_MCR_ABOM;
+ }
+ else
+ {
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_ABOM;
+ }
+
+ /* Set the automatic wake-up mode */
+ if (hcan->Init.AWUM == ENABLE)
+ {
+ hcan->Instance->MCR |= CAN_MCR_AWUM;
+ }
+ else
+ {
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_AWUM;
+ }
+
+ /* Set the no automatic retransmission */
+ if (hcan->Init.NART == ENABLE)
+ {
+ hcan->Instance->MCR |= CAN_MCR_NART;
+ }
+ else
+ {
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_NART;
+ }
+
+ /* Set the receive FIFO locked mode */
+ if (hcan->Init.RFLM == ENABLE)
+ {
+ hcan->Instance->MCR |= CAN_MCR_RFLM;
+ }
+ else
+ {
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_RFLM;
+ }
+
+ /* Set the transmit FIFO priority */
+ if (hcan->Init.TXFP == ENABLE)
+ {
+ hcan->Instance->MCR |= CAN_MCR_TXFP;
+ }
+ else
+ {
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TXFP;
+ }
+
+ /* Set the bit timing register */
+ hcan->Instance->BTR = (uint32_t)((uint32_t)hcan->Init.Mode) | \
+ ((uint32_t)hcan->Init.SJW) | \
+ ((uint32_t)hcan->Init.BS1) | \
+ ((uint32_t)hcan->Init.BS2) | \
+ ((uint32_t)hcan->Init.Prescaler - 1U);
+
+ /* Request leave initialisation */
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait the acknowledge */
+ while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
+ {
+ if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE)
+ {
+ hcan->State= HAL_CAN_STATE_TIMEOUT;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Check acknowledged */
+ if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
+ {
+ InitStatus = CAN_INITSTATUS_SUCCESS;
+ }
+ }
+
+ if(InitStatus == CAN_INITSTATUS_SUCCESS)
+ {
+ /* Set CAN error code to none */
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+
+ /* Initialize the CAN state */
+ hcan->State = HAL_CAN_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Initialize the CAN state */
+ hcan->State = HAL_CAN_STATE_ERROR;
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Configures the CAN reception filter according to the specified
+ * parameters in the CAN_FilterInitStruct.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param sFilterConfig pointer to a CAN_FilterConfTypeDef structure that
+ * contains the filter configuration information.
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig)
+{
+ uint32_t filternbrbitpos = 0U;
+ CAN_TypeDef *can_ip;
+
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* Check the parameters */
+ assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber));
+ assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));
+ assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));
+ assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));
+ assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation));
+ assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber));
+
+ filternbrbitpos = 1U << sFilterConfig->FilterNumber;
+#if defined (CAN3)
+ /* Check the CAN instance */
+ if(hcan->Instance == CAN3)
+ {
+ can_ip = CAN3;
+ }
+ else
+ {
+ can_ip = CAN1;
+ }
+#else
+ can_ip = CAN1;
+#endif
+
+ /* Initialisation mode for the filter */
+ can_ip->FMR |= (uint32_t)CAN_FMR_FINIT;
+
+#if defined (CAN2)
+ /* Select the start slave bank */
+ can_ip->FMR &= ~((uint32_t)CAN_FMR_CAN2SB);
+ can_ip->FMR |= (uint32_t)(sFilterConfig->BankNumber << 8U);
+#endif
+
+ /* Filter Deactivation */
+ can_ip->FA1R &= ~(uint32_t)filternbrbitpos;
+
+ /* Filter Scale */
+ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
+ {
+ /* 16-bit scale for the filter */
+ can_ip->FS1R &= ~(uint32_t)filternbrbitpos;
+
+ /* First 16-bit identifier and First 16-bit mask */
+ /* Or First 16-bit identifier and Second 16-bit identifier */
+ can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
+
+ /* Second 16-bit identifier and Second 16-bit mask */
+ /* Or Third 16-bit identifier and Fourth 16-bit identifier */
+ can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh);
+ }
+
+ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
+ {
+ /* 32-bit scale for the filter */
+ can_ip->FS1R |= filternbrbitpos;
+
+ /* 32-bit identifier or First 32-bit identifier */
+ can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
+ /* 32-bit mask or Second 32-bit identifier */
+ can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow);
+ }
+
+ /* Filter Mode */
+ if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
+ {
+ /*Id/Mask mode for the filter*/
+ can_ip->FM1R &= ~(uint32_t)filternbrbitpos;
+ }
+ else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
+ {
+ /*Identifier list mode for the filter*/
+ can_ip->FM1R |= (uint32_t)filternbrbitpos;
+ }
+
+ /* Filter FIFO assignment */
+ if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
+ {
+ /* FIFO 0 assignation for the filter */
+ can_ip->FFA1R &= ~(uint32_t)filternbrbitpos;
+ }
+
+ if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO1)
+ {
+ /* FIFO 1 assignation for the filter */
+ can_ip->FFA1R |= (uint32_t)filternbrbitpos;
+ }
+
+ /* Filter activation */
+ if (sFilterConfig->FilterActivation == ENABLE)
+ {
+ can_ip->FA1R |= filternbrbitpos;
+ }
+
+ /* Leave the initialisation mode for the filter */
+ can_ip->FMR &= ~((uint32_t)CAN_FMR_FINIT);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Deinitializes the CANx peripheral registers to their default reset values.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan)
+{
+ /* Check CAN handle */
+ if(hcan == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY;
+
+ /* DeInit the low level hardware */
+ HAL_CAN_MspDeInit(hcan);
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CAN MSP.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the CAN MSP.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Exported_Functions_Group2 IO operation functions
+ * @brief IO operation functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Transmit a CAN frame message.
+ (+) Receive a CAN frame message.
+ (+) Enter CAN peripheral in sleep mode.
+ (+) Wake up the CAN peripheral from sleep mode.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initiates and transmits a CAN frame message.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param Timeout Specify Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
+{
+ uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
+ uint32_t tickstart = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
+ assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
+ assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
+
+ if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
+ ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
+ ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
+ {
+ /* Process locked */
+ __HAL_LOCK(hcan);
+
+ /* Change CAN state */
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_READY */
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ break;
+ }
+
+ /* Select one empty transmit mailbox */
+ if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
+ {
+ transmitmailbox = CAN_TXMAILBOX_0;
+ }
+ else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
+ {
+ transmitmailbox = CAN_TXMAILBOX_1;
+ }
+ else
+ {
+ transmitmailbox = CAN_TXMAILBOX_2;
+ }
+
+ /* Set up the Id */
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
+ if (hcan->pTxMsg->IDE == CAN_ID_STD)
+ {
+ assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21U) | \
+ hcan->pTxMsg->RTR);
+ }
+ else
+ {
+ assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3U) | \
+ hcan->pTxMsg->IDE | \
+ hcan->pTxMsg->RTR);
+ }
+
+ /* Set up the DLC */
+ hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U;
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
+
+ /* Set up the data field */
+ hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3U] << 24U) |
+ ((uint32_t)hcan->pTxMsg->Data[2U] << 16U) |
+ ((uint32_t)hcan->pTxMsg->Data[1U] << 8U) |
+ ((uint32_t)hcan->pTxMsg->Data[0U]));
+ hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7U] << 24U) |
+ ((uint32_t)hcan->pTxMsg->Data[6U] << 16U) |
+ ((uint32_t)hcan->pTxMsg->Data[5U] << 8U) |
+ ((uint32_t)hcan->pTxMsg->Data[4U]));
+ /* Request transmission */
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Check End of transmission flag */
+ while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox)))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ hcan->State = HAL_CAN_STATE_TIMEOUT;
+
+ __HAL_CAN_CANCEL_TRANSMIT(hcan, transmitmailbox);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Change CAN state */
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_BUSY_TX */
+ hcan->State = HAL_CAN_STATE_READY;
+ break;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_ERROR;
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Initiates and transmits a CAN frame message.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
+{
+ uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
+ assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
+ assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
+
+ if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
+ ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
+ ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcan);
+
+ /* Select one empty transmit mailbox */
+ if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
+ {
+ transmitmailbox = CAN_TXMAILBOX_0;
+ }
+ else if((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
+ {
+ transmitmailbox = CAN_TXMAILBOX_1;
+ }
+ else
+ {
+ transmitmailbox = CAN_TXMAILBOX_2;
+ }
+
+ /* Set up the Id */
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
+ if(hcan->pTxMsg->IDE == CAN_ID_STD)
+ {
+ assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21U) | \
+ hcan->pTxMsg->RTR);
+ }
+ else
+ {
+ assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3U) | \
+ hcan->pTxMsg->IDE | \
+ hcan->pTxMsg->RTR);
+ }
+
+ /* Set up the DLC */
+ hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U;
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
+
+ /* Set up the data field */
+ hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3U] << 24U) |
+ ((uint32_t)hcan->pTxMsg->Data[2U] << 16U) |
+ ((uint32_t)hcan->pTxMsg->Data[1U] << 8U) |
+ ((uint32_t)hcan->pTxMsg->Data[0U]));
+ hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7U] << 24U) |
+ ((uint32_t)hcan->pTxMsg->Data[6U] << 16U) |
+ ((uint32_t)hcan->pTxMsg->Data[5U] << 8U) |
+ ((uint32_t)hcan->pTxMsg->Data[4U]));
+
+ /* Change CAN state */
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_READY */
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ break;
+ }
+
+ /* Set CAN error code to none */
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Request transmission */
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
+
+ /* Enable Error warning, Error passive, Bus-off,
+ Last error and Error Interrupts */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
+ CAN_IT_EPV |
+ CAN_IT_BOF |
+ CAN_IT_LEC |
+ CAN_IT_ERR |
+ CAN_IT_TME);
+ }
+ else
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_ERROR;
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Receives a correct CAN frame.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param FIFONumber FIFO Number value
+ * @param Timeout Specify Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+ CanRxMsgTypeDef* pRxMsg = NULL;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_FIFO(FIFONumber));
+
+ /* Check if CAN state is not busy for RX FIFO0 */
+ if ((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
+ {
+ return HAL_BUSY;
+ }
+
+ /* Check if CAN state is not busy for RX FIFO1 */
+ if ((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hcan);
+
+ /* Change CAN state */
+ if (FIFONumber == CAN_FIFO0)
+ {
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_READY */
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
+ break;
+ }
+ }
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_READY */
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
+ break;
+ }
+ }
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Check pending message */
+ while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0U)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ hcan->State = HAL_CAN_STATE_TIMEOUT;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Set RxMsg pointer */
+ if(FIFONumber == CAN_FIFO0)
+ {
+ pRxMsg = hcan->pRxMsg;
+ }
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ pRxMsg = hcan->pRx1Msg;
+ }
+
+ /* Get the Id */
+ pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+ if (pRxMsg->IDE == CAN_ID_STD)
+ {
+ pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
+ }
+ else
+ {
+ pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
+ }
+
+ pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+ /* Get the DLC */
+ pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
+ /* Get the FMI */
+ pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
+ /* Get the FIFONumber */
+ pRxMsg->FIFONumber = FIFONumber;
+ /* Get the data field */
+ pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
+ pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
+ pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
+ pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
+ pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
+ pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
+ pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
+ pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
+
+ /* Release the FIFO */
+ if(FIFONumber == CAN_FIFO0)
+ {
+ /* Release FIFO0 */
+ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
+ }
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ /* Release FIFO1 */
+ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
+ }
+
+ /* Change CAN state */
+ if (FIFONumber == CAN_FIFO0)
+ {
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+ break;
+ default: /* HAL_CAN_STATE_BUSY_RX0 */
+ hcan->State = HAL_CAN_STATE_READY;
+ break;
+ }
+ }
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+ break;
+ default: /* HAL_CAN_STATE_BUSY_RX1 */
+ hcan->State = HAL_CAN_STATE_READY;
+ break;
+ }
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Receives a correct CAN frame.
+ * @param hcan Pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param FIFONumber Specify the FIFO number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_FIFO(FIFONumber));
+
+ /* Check if CAN state is not busy for RX FIFO0 */
+ if((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
+ {
+ return HAL_BUSY;
+ }
+
+ /* Check if CAN state is not busy for RX FIFO1 */
+ if((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hcan);
+
+ /* Change CAN state */
+ if(FIFONumber == CAN_FIFO0)
+ {
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_READY */
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
+ break;
+ }
+ }
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_READY */
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
+ break;
+ }
+ }
+ /* Set CAN error code to none */
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+
+ /* Enable interrupts: */
+ /* - Enable Error warning Interrupt */
+ /* - Enable Error passive Interrupt */
+ /* - Enable Bus-off Interrupt */
+ /* - Enable Last error code Interrupt */
+ /* - Enable Error Interrupt */
+ /* - Enable Transmit mailbox empty Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
+ CAN_IT_EPV |
+ CAN_IT_BOF |
+ CAN_IT_LEC |
+ CAN_IT_ERR |
+ CAN_IT_TME);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ if(FIFONumber == CAN_FIFO0)
+ {
+ /* Enable FIFO 0 overrun and message pending Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0);
+ }
+ else
+ {
+ /* Enable FIFO 1 overrun and message pending Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Enters the Sleep (low power) mode.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan)
+{
+ uint32_t tickstart = 0U;
+
+ /* Process locked */
+ __HAL_LOCK(hcan);
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY;
+
+ /* Request Sleep mode */
+ hcan->Instance->MCR = (((hcan->Instance->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
+
+ /* Sleep mode status */
+ if ((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait the acknowledge */
+ while((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)
+ {
+ if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
+ {
+ hcan->State = HAL_CAN_STATE_TIMEOUT;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral
+ * is in the normal mode.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan)
+{
+ uint32_t tickstart = 0U;
+
+ /* Process locked */
+ __HAL_LOCK(hcan);
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY;
+
+ /* Wake up request */
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_SLEEP;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Sleep mode status */
+ while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
+ {
+ if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
+ {
+ hcan->State= HAL_CAN_STATE_TIMEOUT;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+ return HAL_TIMEOUT;
+ }
+ }
+ if((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Handles CAN interrupt request
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
+{
+ uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U;
+ uint32_t errorcode = HAL_CAN_ERROR_NONE;
+
+ /* Check Overrun flag for FIFO0 */
+ tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV0);
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV0);
+ if(tmp1 && tmp2)
+ {
+ /* Set CAN error code to FOV0 error */
+ errorcode |= HAL_CAN_ERROR_FOV0;
+
+ /* Clear FIFO0 Overrun Flag */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0);
+ }
+ /* Check Overrun flag for FIFO1 */
+ tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV1);
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV1);
+
+ if(tmp1 && tmp2)
+ {
+ /* Set CAN error code to FOV1 error */
+ errorcode |= HAL_CAN_ERROR_FOV1;
+
+ /* Clear FIFO1 Overrun Flag */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1);
+ }
+
+ /* Check End of transmission flag */
+ if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME))
+ {
+ tmp1 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0);
+ tmp2 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1);
+ tmp3 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2);
+ if(tmp1 || tmp2 || tmp3)
+ {
+ tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK0);
+ tmp2 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK1);
+ tmp3 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK2);
+ /* Check Transmit success */
+ if(tmp1 || tmp2 || tmp3)
+ {
+ /* Call transmit function */
+ CAN_Transmit_IT(hcan);
+ }
+ else /* Transmit failure */
+ {
+ /* Set CAN error code to TXFAIL error */
+ errorcode |= HAL_CAN_ERROR_TXFAIL;
+ }
+
+ /* Clear transmission status flags (RQCPx and TXOKx) */
+ SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP0 | CAN_TSR_RQCP1 | CAN_TSR_RQCP2 | \
+ CAN_FLAG_TXOK0 | CAN_FLAG_TXOK1 | CAN_FLAG_TXOK2);
+ }
+ }
+
+ tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0);
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0);
+ /* Check End of reception flag for FIFO0 */
+ if((tmp1 != 0U) && tmp2)
+ {
+ /* Call receive function */
+ CAN_Receive_IT(hcan, CAN_FIFO0);
+ }
+
+ tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1);
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1);
+ /* Check End of reception flag for FIFO1 */
+ if((tmp1 != 0U) && tmp2)
+ {
+ /* Call receive function */
+ CAN_Receive_IT(hcan, CAN_FIFO1);
+ }
+
+ /* Set error code in handle */
+ hcan->ErrorCode |= errorcode;
+
+ tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG);
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG);
+ tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
+ /* Check Error Warning Flag */
+ if(tmp1 && tmp2 && tmp3)
+ {
+ /* Set CAN error code to EWG error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_EWG;
+ }
+
+ tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV);
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV);
+ tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
+ /* Check Error Passive Flag */
+ if(tmp1 && tmp2 && tmp3)
+ {
+ /* Set CAN error code to EPV error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_EPV;
+ }
+
+ tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF);
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF);
+ tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
+ /* Check Bus-Off Flag */
+ if(tmp1 && tmp2 && tmp3)
+ {
+ /* Set CAN error code to BOF error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_BOF;
+ }
+
+ tmp1 = HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC);
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC);
+ tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
+ /* Check Last error code Flag */
+ if((!tmp1) && tmp2 && tmp3)
+ {
+ tmp1 = (hcan->Instance->ESR) & CAN_ESR_LEC;
+ switch(tmp1)
+ {
+ case(CAN_ESR_LEC_0):
+ /* Set CAN error code to STF error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_STF;
+ break;
+ case(CAN_ESR_LEC_1):
+ /* Set CAN error code to FOR error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_FOR;
+ break;
+ case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0):
+ /* Set CAN error code to ACK error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_ACK;
+ break;
+ case(CAN_ESR_LEC_2):
+ /* Set CAN error code to BR error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_BR;
+ break;
+ case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0):
+ /* Set CAN error code to BD error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_BD;
+ break;
+ case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
+ /* Set CAN error code to CRC error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_CRC;
+ break;
+ default:
+ break;
+ }
+
+ /* Clear Last error code Flag */
+ hcan->Instance->ESR &= ~(CAN_ESR_LEC);
+ }
+
+ /* Call the Error call Back in case of Errors */
+ if(hcan->ErrorCode != HAL_CAN_ERROR_NONE)
+ {
+ /* Clear ERRI Flag */
+ hcan->Instance->MSR = CAN_MSR_ERRI;
+ /* Set the CAN state ready to be able to start again the process */
+ hcan->State = HAL_CAN_STATE_READY;
+
+ /* Disable interrupts: */
+ /* - Disable Error warning Interrupt */
+ /* - Disable Error passive Interrupt */
+ /* - Disable Bus-off Interrupt */
+ /* - Disable Last error code Interrupt */
+ /* - Disable Error Interrupt */
+ /* - Disable FIFO 0 message pending Interrupt */
+ /* - Disable FIFO 0 Overrun Interrupt */
+ /* - Disable FIFO 1 message pending Interrupt */
+ /* - Disable FIFO 1 Overrun Interrupt */
+ /* - Disable Transmit mailbox empty Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
+ CAN_IT_EPV |
+ CAN_IT_BOF |
+ CAN_IT_LEC |
+ CAN_IT_ERR |
+ CAN_IT_FMP0|
+ CAN_IT_FOV0|
+ CAN_IT_FMP1|
+ CAN_IT_FOV1|
+ CAN_IT_TME);
+
+ /* Call Error callback function */
+ HAL_CAN_ErrorCallback(hcan);
+ }
+}
+
+/**
+ * @brief Transmission complete callback in non blocking mode
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Transmission complete callback in non blocking mode
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_RxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Error CAN callback.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
+ * @brief CAN Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State and Error functions #####
+ ==============================================================================
+ [..]
+ This subsection provides functions allowing to :
+ (+) Check the CAN state.
+ (+) Check CAN Errors detected during interrupt process
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief return the CAN state
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL state
+ */
+HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan)
+{
+ /* Return CAN state */
+ return hcan->State;
+}
+
+/**
+ * @brief Return the CAN error code
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval CAN Error Code
+ */
+uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan)
+{
+ return hcan->ErrorCode;
+}
+
+/**
+ * @}
+ */
+/**
+ * @brief Initiates and transmits a CAN frame message.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
+{
+ /* Disable Transmit mailbox empty Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME);
+
+ if(hcan->State == HAL_CAN_STATE_BUSY_TX)
+ {
+ /* Disable Error warning, Error passive, Bus-off, Last error code
+ and Error Interrupts */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
+ CAN_IT_EPV |
+ CAN_IT_BOF |
+ CAN_IT_LEC |
+ CAN_IT_ERR );
+ }
+
+ /* Change CAN state */
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_BUSY_TX */
+ hcan->State = HAL_CAN_STATE_READY;
+ break;
+ }
+
+ /* Transmission complete callback */
+ HAL_CAN_TxCpltCallback(hcan);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Receives a correct CAN frame.
+ * @param hcan Pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param FIFONumber Specify the FIFO number
+ * @retval HAL status
+ * @retval None
+ */
+static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
+{
+ uint32_t tmp1 = 0U;
+ CanRxMsgTypeDef* pRxMsg = NULL;
+
+ /* Set RxMsg pointer */
+ if(FIFONumber == CAN_FIFO0)
+ {
+ pRxMsg = hcan->pRxMsg;
+ }
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ pRxMsg = hcan->pRx1Msg;
+ }
+
+ /* Get the Id */
+ pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+ if (pRxMsg->IDE == CAN_ID_STD)
+ {
+ pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
+ }
+ else
+ {
+ pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
+ }
+
+ pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+ /* Get the DLC */
+ pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
+ /* Get the FIFONumber */
+ pRxMsg->FIFONumber = FIFONumber;
+ /* Get the FMI */
+ pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
+ /* Get the data field */
+ pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
+ pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
+ pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
+ pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
+ pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
+ pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
+ pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
+ pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
+ /* Release the FIFO */
+ /* Release FIFO0 */
+ if (FIFONumber == CAN_FIFO0)
+ {
+ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
+
+ /* Disable FIFO 0 overrun and message pending Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0);
+ }
+ /* Release FIFO1 */
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
+
+ /* Disable FIFO 1 overrun and message pending Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1);
+ }
+
+ tmp1 = hcan->State;
+ if((tmp1 == HAL_CAN_STATE_BUSY_RX0) || (tmp1 == HAL_CAN_STATE_BUSY_RX1))
+ {
+ /* Disable Error warning, Error passive, Bus-off, Last error code
+ and Error Interrupts */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
+ CAN_IT_EPV |
+ CAN_IT_BOF |
+ CAN_IT_LEC |
+ CAN_IT_ERR);
+ }
+
+ /* Change CAN state */
+ if (FIFONumber == CAN_FIFO0)
+ {
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+ break;
+ default: /* HAL_CAN_STATE_BUSY_RX0 */
+ hcan->State = HAL_CAN_STATE_READY;
+ break;
+ }
+ }
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+ break;
+ default: /* HAL_CAN_STATE_BUSY_RX1 */
+ hcan->State = HAL_CAN_STATE_READY;
+ break;
+ }
+ }
+
+ /* Receive complete callback */
+ HAL_CAN_RxCpltCallback(hcan);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
+ STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
+ STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_can_legacy.h Tue Mar 20 16:56:18 2018 +0000
@@ -0,0 +1,785 @@
+/**
+ ******************************************************************************
+ * @file stm32f4xx_hal_can_legacy.h
+ * @author MCD Application Team
+ * @brief Header file of CAN HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HAL_CAN_LEGACY_H
+#define __STM32F4xx_HAL_CAN_LEGACY_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
+ defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
+ defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) ||\
+ defined(STM32F423xx)
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hal_def.h"
+
+/** @addtogroup STM32F4xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CAN
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CAN_Exported_Types CAN Exported Types
+ * @{
+ */
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */
+ HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */
+ HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_RX0 = 0x22U, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_RX1 = 0x32U, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_TX_RX0 = 0x42U, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_TX_RX1 = 0x52U, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_RX0_RX1 = 0x62U, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_TX_RX0_RX1 = 0x72U, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< CAN in Timeout state */
+ HAL_CAN_STATE_ERROR = 0x04U /*!< CAN error state */
+
+}HAL_CAN_StateTypeDef;
+
+/**
+ * @brief CAN init structure definition
+ */
+typedef struct
+{
+ uint32_t Prescaler; /*!< Specifies the length of a time quantum.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
+
+ uint32_t Mode; /*!< Specifies the CAN operating mode.
+ This parameter can be a value of @ref CAN_operating_mode */
+
+ uint32_t SJW; /*!< Specifies the maximum number of time quanta
+ the CAN hardware is allowed to lengthen or
+ shorten a bit to perform resynchronization.
+ This parameter can be a value of @ref CAN_synchronisation_jump_width */
+
+ uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1.
+ This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
+
+ uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
+ This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
+
+ uint32_t TTCM; /*!< Enable or disable the time triggered communication mode.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ uint32_t ABOM; /*!< Enable or disable the automatic bus-off management.
+ This parameter can be set to ENABLE or DISABLE */
+
+ uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode.
+ This parameter can be set to ENABLE or DISABLE */
+
+ uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode.
+ This parameter can be set to ENABLE or DISABLE */
+
+ uint32_t RFLM; /*!< Enable or disable the receive FIFO Locked mode.
+ This parameter can be set to ENABLE or DISABLE */
+
+ uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority.
+ This parameter can be set to ENABLE or DISABLE */
+}CAN_InitTypeDef;
+
+/**
+ * @brief CAN filter configuration structure definition
+ */
+typedef struct
+{
+ uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
+ configuration, first one for a 16-bit configuration).
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+ uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
+ configuration, second one for a 16-bit configuration).
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+ uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
+ according to the mode (MSBs for a 32-bit configuration,
+ first one for a 16-bit configuration).
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+ uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
+ according to the mode (LSBs for a 32-bit configuration,
+ second one for a 16-bit configuration).
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+ uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
+ This parameter can be a value of @ref CAN_filter_FIFO */
+
+ uint32_t FilterNumber; /*!< Specifies the filter which will be initialized.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 27 */
+
+ uint32_t FilterMode; /*!< Specifies the filter mode to be initialized.
+ This parameter can be a value of @ref CAN_filter_mode */
+
+ uint32_t FilterScale; /*!< Specifies the filter scale.
+ This parameter can be a value of @ref CAN_filter_scale */
+
+ uint32_t FilterActivation; /*!< Enable or disable the filter.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ uint32_t BankNumber; /*!< Select the start slave bank filter.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 28 */
+
+}CAN_FilterConfTypeDef;
+
+/**
+ * @brief CAN Tx message structure definition
+ */
+typedef struct
+{
+ uint32_t StdId; /*!< Specifies the standard identifier.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
+
+ uint32_t ExtId; /*!< Specifies the extended identifier.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
+
+ uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
+ This parameter can be a value of @ref CAN_Identifier_Type */
+
+ uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
+ This parameter can be a value of @ref CAN_remote_transmission_request */
+
+ uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
+
+ uint8_t Data[8]; /*!< Contains the data to be transmitted.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
+
+}CanTxMsgTypeDef;
+
+/**
+ * @brief CAN Rx message structure definition
+ */
+typedef struct
+{
+ uint32_t StdId; /*!< Specifies the standard identifier.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
+
+ uint32_t ExtId; /*!< Specifies the extended identifier.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
+
+ uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received.
+ This parameter can be a value of @ref CAN_Identifier_Type */
+
+ uint32_t RTR; /*!< Specifies the type of frame for the received message.
+ This parameter can be a value of @ref CAN_remote_transmission_request */
+
+ uint32_t DLC; /*!< Specifies the length of the frame that will be received.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
+
+ uint8_t Data[8]; /*!< Contains the data to be received.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
+
+ uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
+
+ uint32_t FIFONumber; /*!< Specifies the receive FIFO number.
+ This parameter can be CAN_FIFO0 or CAN_FIFO1 */
+
+}CanRxMsgTypeDef;
+
+/**
+ * @brief CAN handle Structure definition
+ */
+typedef struct
+{
+ CAN_TypeDef *Instance; /*!< Register base address */
+
+ CAN_InitTypeDef Init; /*!< CAN required parameters */
+
+ CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */
+
+ CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure for RX FIFO0 msg */
+
+ CanRxMsgTypeDef* pRx1Msg; /*!< Pointer to reception structure for RX FIFO1 msg */
+
+ __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
+
+ HAL_LockTypeDef Lock; /*!< CAN locking object */
+
+ __IO uint32_t ErrorCode; /*!< CAN Error code */
+
+}CAN_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CAN_Exported_Constants CAN Exported Constants
+ * @{
+ */
+
+/** @defgroup CAN_Error_Code CAN Error Code
+ * @{
+ */
+#define HAL_CAN_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_CAN_ERROR_EWG 0x00000001U /*!< EWG error */
+#define HAL_CAN_ERROR_EPV 0x00000002U /*!< EPV error */
+#define HAL_CAN_ERROR_BOF 0x00000004U /*!< BOF error */
+#define HAL_CAN_ERROR_STF 0x00000008U /*!< Stuff error */
+#define HAL_CAN_ERROR_FOR 0x00000010U /*!< Form error */
+#define HAL_CAN_ERROR_ACK 0x00000020U /*!< Acknowledgment error */
+#define HAL_CAN_ERROR_BR 0x00000040U /*!< Bit recessive */
+#define HAL_CAN_ERROR_BD 0x00000080U /*!< LEC dominant */
+#define HAL_CAN_ERROR_CRC 0x00000100U /*!< LEC transfer error */
+#define HAL_CAN_ERROR_FOV0 0x00000200U /*!< FIFO0 overrun error */
+#define HAL_CAN_ERROR_FOV1 0x00000400U /*!< FIFO1 overrun error */
+#define HAL_CAN_ERROR_TXFAIL 0x00000800U /*!< Transmit failure */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_InitStatus CAN InitStatus
+ * @{
+ */
+#define CAN_INITSTATUS_FAILED ((uint8_t)0x00) /*!< CAN initialization failed */
+#define CAN_INITSTATUS_SUCCESS ((uint8_t)0x01) /*!< CAN initialization OK */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_operating_mode CAN Operating Mode
+ * @{
+ */
+#define CAN_MODE_NORMAL 0x00000000U /*!< Normal mode */
+#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */
+#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */
+#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_synchronisation_jump_width CAN Synchronisation Jump Width
+ * @{
+ */
+#define CAN_SJW_1TQ 0x00000000U /*!< 1 time quantum */
+#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */
+#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */
+#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in bit segment 1
+ * @{
+ */
+#define CAN_BS1_1TQ 0x00000000U /*!< 1 time quantum */
+#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */
+#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */
+#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */
+#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */
+#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */
+#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */
+#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */
+#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */
+#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */
+#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */
+#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */
+#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */
+#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */
+#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */
+#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in bit segment 2
+ * @{
+ */
+#define CAN_BS2_1TQ 0x00000000U /*!< 1 time quantum */
+#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */
+#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */
+#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */
+#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */
+#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */
+#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */
+#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_mode CAN Filter Mode
+ * @{
+ */
+#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */
+#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_scale CAN Filter Scale
+ * @{
+ */
+#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */
+#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_FIFO CAN Filter FIFO
+ * @{
+ */
+#define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
+#define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Identifier_Type CAN Identifier Type
+ * @{
+ */
+#define CAN_ID_STD 0x00000000U /*!< Standard Id */
+#define CAN_ID_EXT 0x00000004U /*!< Extended Id */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
+ * @{
+ */
+#define CAN_RTR_DATA 0x00000000U /*!< Data frame */
+#define CAN_RTR_REMOTE 0x00000002U /*!< Remote frame */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number Constants
+ * @{
+ */
+#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
+#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_flags CAN Flags
+ * @{
+ */
+/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
+ and CAN_ClearFlag() functions. */
+/* If the flag is 0x1XXXXXXX, it means that it can only be used with
+ CAN_GetFlagStatus() function. */
+
+/* Transmit Flags */
+#define CAN_FLAG_RQCP0 0x00000500U /*!< Request MailBox0 flag */
+#define CAN_FLAG_RQCP1 0x00000508U /*!< Request MailBox1 flag */
+#define CAN_FLAG_RQCP2 0x00000510U /*!< Request MailBox2 flag */
+#define CAN_FLAG_TXOK0 0x00000501U /*!< Transmission OK MailBox0 flag */
+#define CAN_FLAG_TXOK1 0x00000509U /*!< Transmission OK MailBox1 flag */
+#define CAN_FLAG_TXOK2 0x00000511U /*!< Transmission OK MailBox2 flag */
+#define CAN_FLAG_TME0 0x0000051AU /*!< Transmit mailbox 0 empty flag */
+#define CAN_FLAG_TME1 0x0000051BU /*!< Transmit mailbox 0 empty flag */
+#define CAN_FLAG_TME2 0x0000051CU /*!< Transmit mailbox 0 empty flag */
+
+/* Receive Flags */
+#define CAN_FLAG_FF0 0x00000203U /*!< FIFO 0 Full flag */
+#define CAN_FLAG_FOV0 0x00000204U /*!< FIFO 0 Overrun flag */
+
+#define CAN_FLAG_FF1 0x00000403U /*!< FIFO 1 Full flag */
+#define CAN_FLAG_FOV1 0x00000404U /*!< FIFO 1 Overrun flag */
+
+/* Operating Mode Flags */
+#define CAN_FLAG_INAK 0x00000100U /*!< Initialization acknowledge flag */
+#define CAN_FLAG_SLAK 0x00000101U /*!< Sleep acknowledge flag */
+#define CAN_FLAG_ERRI 0x00000102U /*!< Error flag */
+#define CAN_FLAG_WKU 0x00000103U /*!< Wake up flag */
+#define CAN_FLAG_SLAKI 0x00000104U /*!< Sleep acknowledge flag */
+
+/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
+ In this case the SLAK bit can be polled.*/
+
+/* Error Flags */
+#define CAN_FLAG_EWG 0x00000300U /*!< Error warning flag */
+#define CAN_FLAG_EPV 0x00000301U /*!< Error passive flag */
+#define CAN_FLAG_BOF 0x00000302U /*!< Bus-Off flag */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Interrupts CAN Interrupts
+ * @{
+ */
+#define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */
+
+/* Receive Interrupts */
+#define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */
+#define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */
+#define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */
+#define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */
+#define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */
+#define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */
+
+/* Operating Mode Interrupts */
+#define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */
+#define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */
+
+/* Error Interrupts */
+#define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */
+#define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */
+#define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */
+#define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
+#define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Mailboxes_Definition CAN Mailboxes Definition
+ * @{
+ */
+#define CAN_TXMAILBOX_0 ((uint8_t)0x00)
+#define CAN_TXMAILBOX_1 ((uint8_t)0x01)
+#define CAN_TXMAILBOX_2 ((uint8_t)0x02)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup CAN_Exported_Macros CAN Exported Macros
+ * @{
+ */
+
+/** @brief Reset CAN handle state
+ * @param __HANDLE__ specifies the CAN Handle.
+ * @retval None
+ */
+#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
+
+/**
+ * @brief Enable the specified CAN interrupts.
+ * @param __HANDLE__ CAN handle
+ * @param __INTERRUPT__ CAN Interrupt
+ * @retval None
+ */
+#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the specified CAN interrupts.
+ * @param __HANDLE__ CAN handle
+ * @param __INTERRUPT__ CAN Interrupt
+ * @retval None
+ */
+#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
+
+/**
+ * @brief Return the number of pending received messages.
+ * @param __HANDLE__ CAN handle
+ * @param __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+ * @retval The number of pending message.
+ */
+#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
+((uint8_t)((__HANDLE__)->Instance->RF0R&0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R & 0x03U)))
+
+/** @brief Check whether the specified CAN flag is set or not.
+ * @param __HANDLE__ CAN Handle
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg CAN_TSR_RQCP0: Request MailBox0 Flag
+ * @arg CAN_TSR_RQCP1: Request MailBox1 Flag
+ * @arg CAN_TSR_RQCP2: Request MailBox2 Flag
+ * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
+ * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
+ * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
+ * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
+ * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
+ * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
+ * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
+ * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
+ * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
+ * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
+ * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
+ * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
+ * @arg CAN_FLAG_WKU: Wake up Flag
+ * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
+ * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
+ * @arg CAN_FLAG_EWG: Error Warning Flag
+ * @arg CAN_FLAG_EPV: Error Passive Flag
+ * @arg CAN_FLAG_BOF: Bus-Off Flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
+((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))))
+
+/** @brief Clear the specified CAN pending flag.
+ * @param __HANDLE__ CAN Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg CAN_TSR_RQCP0: Request MailBox0 Flag
+ * @arg CAN_TSR_RQCP1: Request MailBox1 Flag
+ * @arg CAN_TSR_RQCP2: Request MailBox2 Flag
+ * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
+ * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
+ * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
+ * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
+ * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
+ * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
+ * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
+ * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
+ * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
+ * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
+ * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
+ * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
+ * @arg CAN_FLAG_WKU: Wake up Flag
+ * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
+ * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__HANDLE__)->Instance->MSR) = ((uint32_t)1U << ((__FLAG__) & CAN_FLAG_MASK))))
+
+/** @brief Check if the specified CAN interrupt source is enabled or disabled.
+ * @param __HANDLE__ CAN Handle
+ * @param __INTERRUPT__ specifies the CAN interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
+ * @arg CAN_IT_FMP0: FIFO0 message pending interrupt enable
+ * @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/**
+ * @brief Check the transmission status of a CAN Frame.
+ * @param __HANDLE__ CAN Handle
+ * @param __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission.
+ * @retval The new status of transmission (TRUE or FALSE).
+ */
+#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\
+(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\
+ ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\
+ ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)))
+
+/**
+ * @brief Release the specified receive FIFO.
+ * @param __HANDLE__ CAN handle
+ * @param __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+ * @retval None
+ */
+#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
+((__HANDLE__)->Instance->RF0R = CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R = CAN_RF1R_RFOM1))
+
+/**
+ * @brief Cancel a transmit request.
+ * @param __HANDLE__ CAN Handle
+ * @param __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission.
+ * @retval None
+ */
+#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
+(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ0) :\
+ ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ1) :\
+ ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ2))
+
+/**
+ * @brief Enable or disable the DBG Freeze for CAN.
+ * @param __HANDLE__ CAN Handle
+ * @param __NEWSTATE__ new state of the CAN peripheral.
+ * This parameter can be: ENABLE (CAN reception/transmission is frozen
+ * during debug. Reception FIFOs can still be accessed/controlled normally)
+ * or DISABLE (CAN is working during debug).
+ * @retval None
+ */
+#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
+((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CAN_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization/de-initialization functions ***********************************/
+HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);
+HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);
+HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);
+void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
+void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group2
+ * @{
+ */
+/* I/O operation functions ******************************************************/
+HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);
+HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
+void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);
+void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);
+void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
+void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral State functions ***************************************************/
+uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
+HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup CAN_Private_Types CAN Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup CAN_Private_Variables CAN Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup CAN_Private_Constants CAN Private Constants
+ * @{
+ */
+#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
+#define CAN_FLAG_MASK 0x000000FFU
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CAN_Private_Macros CAN Private Macros
+ * @{
+ */
+#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
+ ((MODE) == CAN_MODE_LOOPBACK)|| \
+ ((MODE) == CAN_MODE_SILENT) || \
+ ((MODE) == CAN_MODE_SILENT_LOOPBACK))
+#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
+ ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
+#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
+#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
+#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U))
+#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27U)
+#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
+ ((MODE) == CAN_FILTERMODE_IDLIST))
+#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
+ ((SCALE) == CAN_FILTERSCALE_32BIT))
+#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
+ ((FIFO) == CAN_FILTER_FIFO1))
+#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U)
+
+#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
+#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FFU))
+#define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU)
+#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
+
+#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
+ ((IDTYPE) == CAN_ID_EXT))
+#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
+#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup CAN_Private_Functions CAN Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx ||\
+ STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
+ STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_HAL_CAN_LEGACY_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cec.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cec.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_cec.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief CEC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the High Definition Multimedia Interface @@ -143,7 +141,7 @@ /** * @brief Initializes the CEC mode according to the specified * parameters in the CEC_InitTypeDef and creates the associated handle . - * @param hcec: CEC handle + * @param hcec CEC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec) @@ -213,7 +211,7 @@ /** * @brief DeInitializes the CEC peripheral - * @param hcec: CEC handle + * @param hcec CEC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec) @@ -266,8 +264,8 @@ /** * @brief Initializes the Own Address of the CEC device - * @param hcec: CEC handle - * @param CEC_OwnAddress: The CEC own address. + * @param hcec CEC handle + * @param CEC_OwnAddress The CEC own address. * @retval HAL status */ HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress) @@ -313,7 +311,7 @@ /** * @brief CEC MSP Init - * @param hcec: CEC handle + * @param hcec CEC handle * @retval None */ __weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec) @@ -327,7 +325,7 @@ /** * @brief CEC MSP DeInit - * @param hcec: CEC handle + * @param hcec CEC handle * @retval None */ __weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec) @@ -379,11 +377,11 @@ /** * @brief Send data in interrupt mode - * @param hcec: CEC handle - * @param InitiatorAddress: Initiator logical address - * @param DestinationAddress: destination logical address - * @param pData: pointer to input byte data buffer - * @param Size: amount of data to be sent in bytes (without counting the header). + * @param hcec CEC handle + * @param InitiatorAddress Initiator logical address + * @param DestinationAddress destination logical address + * @param pData pointer to input byte data buffer + * @param Size amount of data to be sent in bytes (without counting the header). * 0 means only the header is sent (ping operation). * Maximum TX size is 15 bytes (1 opcode and up to 14 operands). * @retval HAL status @@ -439,7 +437,7 @@ /** * @brief Get size of the received frame. - * @param hcec: CEC handle + * @param hcec CEC handle * @retval Frame size */ uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec) @@ -449,8 +447,8 @@ /** * @brief Change Rx Buffer. - * @param hcec: CEC handle - * @param Rxbuffer: Rx Buffer + * @param hcec CEC handle + * @param Rxbuffer Rx Buffer * @note This function can be called only inside the HAL_CEC_RxCpltCallback() * @retval Frame size */ @@ -461,7 +459,7 @@ /** * @brief This function handles CEC interrupt requests. - * @param hcec: CEC handle + * @param hcec CEC handle * @retval None */ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) @@ -566,7 +564,7 @@ /** * @brief Tx Transfer completed callback - * @param hcec: CEC handle + * @param hcec CEC handle * @retval None */ __weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec) @@ -580,8 +578,8 @@ /** * @brief Rx Transfer completed callback - * @param hcec: CEC handle - * @param RxFrameSize: Size of frame + * @param hcec CEC handle + * @param RxFrameSize Size of frame * @retval None */ __weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize) @@ -596,7 +594,7 @@ /** * @brief CEC error callbacks - * @param hcec: CEC handle + * @param hcec CEC handle * @retval None */ __weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec) @@ -627,7 +625,7 @@ */ /** * @brief return the CEC state - * @param hcec: pointer to a CEC_HandleTypeDef structure that contains + * @param hcec pointer to a CEC_HandleTypeDef structure that contains * the configuration information for the specified CEC module. * @retval HAL state */ @@ -642,7 +640,7 @@ /** * @brief Return the CEC error code - * @param hcec : pointer to a CEC_HandleTypeDef structure that contains + * @param hcec pointer to a CEC_HandleTypeDef structure that contains * the configuration information for the specified CEC. * @retval CEC Error Code */
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cec.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cec.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_cec.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief Header file of CEC HAL module.
******************************************************************************
* @attention
@@ -426,7 +424,7 @@
*/
/** @brief Reset CEC handle gstate & RxState
- * @param __HANDLE__: CEC handle.
+ * @param __HANDLE__ CEC handle.
* @retval None
*/
#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \
@@ -435,8 +433,8 @@
} while(0)
/** @brief Checks whether or not the specified CEC interrupt flag is set.
- * @param __HANDLE__: specifies the CEC Handle.
- * @param __FLAG__: specifies the flag to check.
+ * @param __HANDLE__ specifies the CEC Handle.
+ * @param __FLAG__ specifies the flag to check.
* @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
* @arg CEC_FLAG_TXERR: Tx Error.
* @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
@@ -455,8 +453,8 @@
#define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
/** @brief Clears the interrupt or status flag when raised (write at 1)
- * @param __HANDLE__: specifies the CEC Handle.
- * @param __FLAG__: specifies the interrupt/status flag to clear.
+ * @param __HANDLE__ specifies the CEC Handle.
+ * @param __FLAG__ specifies the interrupt/status flag to clear.
* This parameter can be one of the following values:
* @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
* @arg CEC_FLAG_TXERR: Tx Error.
@@ -476,8 +474,8 @@
#define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__))
/** @brief Enables the specified CEC interrupt.
- * @param __HANDLE__: specifies the CEC Handle.
- * @param __INTERRUPT__: specifies the CEC interrupt to enable.
+ * @param __HANDLE__ specifies the CEC Handle.
+ * @param __INTERRUPT__ specifies the CEC interrupt to enable.
* This parameter can be one of the following values:
* @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
* @arg CEC_IT_TXERR: Tx Error IT Enable
@@ -497,8 +495,8 @@
#define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
/** @brief Disables the specified CEC interrupt.
- * @param __HANDLE__: specifies the CEC Handle.
- * @param __INTERRUPT__: specifies the CEC interrupt to disable.
+ * @param __HANDLE__ specifies the CEC Handle.
+ * @param __INTERRUPT__ specifies the CEC interrupt to disable.
* This parameter can be one of the following values:
* @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
* @arg CEC_IT_TXERR: Tx Error IT Enable
@@ -518,8 +516,8 @@
#define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
/** @brief Checks whether or not the specified CEC interrupt is enabled.
- * @param __HANDLE__: specifies the CEC Handle.
- * @param __INTERRUPT__: specifies the CEC interrupt to check.
+ * @param __HANDLE__ specifies the CEC Handle.
+ * @param __INTERRUPT__ specifies the CEC interrupt to check.
* This parameter can be one of the following values:
* @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
* @arg CEC_IT_TXERR: Tx Error IT Enable
@@ -539,52 +537,52 @@
#define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
/** @brief Enables the CEC device
- * @param __HANDLE__: specifies the CEC Handle.
+ * @param __HANDLE__ specifies the CEC Handle.
* @retval none
*/
#define __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN)
/** @brief Disables the CEC device
- * @param __HANDLE__: specifies the CEC Handle.
+ * @param __HANDLE__ specifies the CEC Handle.
* @retval none
*/
#define __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN)
/** @brief Set Transmission Start flag
- * @param __HANDLE__: specifies the CEC Handle.
+ * @param __HANDLE__ specifies the CEC Handle.
* @retval none
*/
#define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM)
/** @brief Set Transmission End flag
- * @param __HANDLE__: specifies the CEC Handle.
+ * @param __HANDLE__ specifies the CEC Handle.
* @retval none
* If the CEC message consists of only one byte, TXEOM must be set before of TXSOM.
*/
#define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM)
/** @brief Get Transmission Start flag
- * @param __HANDLE__: specifies the CEC Handle.
+ * @param __HANDLE__ specifies the CEC Handle.
* @retval FlagStatus
*/
#define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)
/** @brief Get Transmission End flag
- * @param __HANDLE__: specifies the CEC Handle.
+ * @param __HANDLE__ specifies the CEC Handle.
* @retval FlagStatus
*/
#define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)
/** @brief Clear OAR register
- * @param __HANDLE__: specifies the CEC Handle.
+ * @param __HANDLE__ specifies the CEC Handle.
* @retval none
*/
#define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)
/** @brief Set OAR register (without resetting previously set address in case of multi-address mode)
* To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand
- * @param __HANDLE__: specifies the CEC Handle.
- * @param __ADDRESS__: Own Address value (CEC logical address is identified by bit position)
+ * @param __HANDLE__ specifies the CEC Handle.
+ * @param __ADDRESS__ Own Address value (CEC logical address is identified by bit position)
* @retval none
*/
#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
@@ -699,21 +697,21 @@
* The message size is the payload size: without counting the header,
* it varies from 0 byte (ping operation, one header only, no payload) to
* 15 bytes (1 opcode and up to 14 operands following the header).
- * @param __SIZE__: CEC message size.
+ * @param __SIZE__ CEC message size.
* @retval Test result (TRUE or FALSE).
*/
#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10U)
/** @brief Check CEC device Own Address Register (OAR) setting.
* OAR address is written in a 15-bit field within CEC_CFGR register.
- * @param __ADDRESS__: CEC own address.
+ * @param __ADDRESS__ CEC own address.
* @retval Test result (TRUE or FALSE).
*/
#define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFFU)
/** @brief Check CEC initiator or destination logical address setting.
* Initiator and destination addresses are coded over 4 bits.
- * @param __ADDRESS__: CEC initiator or logical address.
+ * @param __ADDRESS__ CEC initiator or logical address.
* @retval Test result (TRUE or FALSE).
*/
#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x0FU)
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_conf.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_conf.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_conf.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief HAL configuration file. ****************************************************************************** * @attention @@ -52,7 +50,8 @@ */ #define HAL_MODULE_ENABLED #define HAL_ADC_MODULE_ENABLED -#define HAL_CAN_MODULE_ENABLED +/* #define HAL_CAN_MODULE_ENABLED */ +#define HAL_CAN_LEGACY_MODULE_ENABLED #define HAL_CRC_MODULE_ENABLED #define HAL_CEC_MODULE_ENABLED #define HAL_CRYP_MODULE_ENABLED @@ -273,6 +272,10 @@ #include "stm32f4xx_hal_can.h" #endif /* HAL_CAN_MODULE_ENABLED */ +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + #include "stm32f4xx_hal_can_legacy.h" +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ + #ifdef HAL_CRC_MODULE_ENABLED #include "stm32f4xx_hal_crc.h" #endif /* HAL_CRC_MODULE_ENABLED */
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cortex.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cortex.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_cortex.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief CORTEX HAL module driver. * This file provides firmware functions to manage the following * functionalities of the CORTEX: @@ -142,7 +140,7 @@ /** * @brief Sets the priority grouping field (preemption priority and subpriority) * using the required unlock sequence. - * @param PriorityGroup: The priority grouping bits length. + * @param PriorityGroup The priority grouping bits length. * This parameter can be one of the following values: * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority * 4 bits for subpriority @@ -169,13 +167,13 @@ /** * @brief Sets the priority of an interrupt. - * @param IRQn: External interrupt number. + * @param IRQn External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) - * @param PreemptPriority: The preemption priority for the IRQn channel. + * @param PreemptPriority The preemption priority for the IRQn channel. * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority - * @param SubPriority: the subpriority level for the IRQ channel. + * @param SubPriority the subpriority level for the IRQ channel. * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None @@ -240,7 +238,7 @@ /** * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. * Counter is in free running mode to generate periodic interrupts. - * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. + * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ @@ -287,7 +285,7 @@ /** * @brief Enable the MPU. - * @param MPU_Control: Specifies the control mode of the MPU during hard fault, + * @param MPU_Control Specifies the control mode of the MPU during hard fault, * NMI, FAULTMASK and privileged access to the default memory * This parameter can be one of the following values: * @arg MPU_HFNMI_PRIVDEF_NONE @@ -311,7 +309,7 @@ /** * @brief Initializes and configures the Region and the memory to be protected. - * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains + * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains * the initialization and configuration information. * @retval None */ @@ -367,10 +365,10 @@ /** * @brief Gets the priority of an interrupt. - * @param IRQn: External interrupt number. + * @param IRQn External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f4xxxx.h)) - * @param PriorityGroup: the priority grouping bits length. + * @param PriorityGroup the priority grouping bits length. * This parameter can be one of the following values: * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority * 4 bits for subpriority @@ -382,8 +380,8 @@ * 1 bits for subpriority * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority * 0 bits for subpriority - * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0). - * @param pSubPriority: Pointer on the Subpriority value (starting from 0). + * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0). + * @param pSubPriority Pointer on the Subpriority value (starting from 0). * @retval None */ void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) @@ -463,7 +461,7 @@ /** * @brief Configures the SysTick clock source. - * @param CLKSource: specifies the SysTick clock source. + * @param CLKSource specifies the SysTick clock source. * This parameter can be one of the following values: * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cortex.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cortex.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_cortex.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of CORTEX HAL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_crc.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_crc.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_crc.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief CRC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Cyclic Redundancy Check (CRC) peripheral: @@ -105,7 +103,7 @@ /** * @brief Initializes the CRC according to the specified * parameters in the CRC_InitTypeDef and creates the associated handle. - * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains + * @param hcrc pointer to a CRC_HandleTypeDef structure that contains * the configuration information for CRC * @retval HAL status */ @@ -140,7 +138,7 @@ /** * @brief DeInitializes the CRC peripheral. - * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains + * @param hcrc pointer to a CRC_HandleTypeDef structure that contains * the configuration information for CRC * @retval HAL status */ @@ -173,7 +171,7 @@ /** * @brief Initializes the CRC MSP. - * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains + * @param hcrc pointer to a CRC_HandleTypeDef structure that contains * the configuration information for CRC * @retval None */ @@ -188,7 +186,7 @@ /** * @brief DeInitializes the CRC MSP. - * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains + * @param hcrc pointer to a CRC_HandleTypeDef structure that contains * the configuration information for CRC * @retval None */ @@ -225,10 +223,10 @@ /** * @brief Computes the 32-bit CRC of 32-bit data buffer using combination * of the previous CRC value and the new one. - * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains + * @param hcrc pointer to a CRC_HandleTypeDef structure that contains * the configuration information for CRC - * @param pBuffer: pointer to the buffer containing the data to be computed - * @param BufferLength: length of the buffer to be computed + * @param pBuffer pointer to the buffer containing the data to be computed + * @param BufferLength length of the buffer to be computed * @retval 32-bit CRC */ uint32_t HAL_CRC_Accumulate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) @@ -260,10 +258,10 @@ /** * @brief Computes the 32-bit CRC of 32-bit data buffer independently * of the previous CRC value. - * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains + * @param hcrc pointer to a CRC_HandleTypeDef structure that contains * the configuration information for CRC - * @param pBuffer: Pointer to the buffer containing the data to be computed - * @param BufferLength: Length of the buffer to be computed + * @param pBuffer Pointer to the buffer containing the data to be computed + * @param BufferLength Length of the buffer to be computed * @retval 32-bit CRC */ uint32_t HAL_CRC_Calculate(CRC_HandleTypeDef *hcrc, uint32_t pBuffer[], uint32_t BufferLength) @@ -317,7 +315,7 @@ /** * @brief Returns the CRC state. - * @param hcrc: pointer to a CRC_HandleTypeDef structure that contains + * @param hcrc pointer to a CRC_HandleTypeDef structure that contains * the configuration information for CRC * @retval HAL state */
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_crc.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_crc.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_crc.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of CRC HAL module. ****************************************************************************** * @attention @@ -103,29 +101,29 @@ */ /** @brief Resets CRC handle state - * @param __HANDLE__: CRC handle + * @param __HANDLE__ CRC handle * @retval None */ #define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET) /** * @brief Resets CRC Data Register. - * @param __HANDLE__: CRC handle + * @param __HANDLE__ CRC handle * @retval None */ #define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET) /** * @brief Stores a 8-bit data in the Independent Data(ID) register. - * @param __HANDLE__: CRC handle - * @param __VALUE__: 8-bit value to be stored in the ID register + * @param __HANDLE__ CRC handle + * @param __VALUE__ 8-bit value to be stored in the ID register * @retval None */ #define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, (__VALUE__))) /** * @brief Returns the 8-bit data stored in the Independent Data(ID) register. - * @param __HANDLE__: CRC handle + * @param __HANDLE__ CRC handle * @retval 8-bit value of the ID register */ #define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cryp.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cryp.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_cryp.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief CRYP HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Cryptography (CRYP) peripheral: @@ -155,7 +153,7 @@ /** * @brief DMA CRYP Input Data process complete callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma) @@ -172,7 +170,7 @@ /** * @brief DMA CRYP Output Data process complete callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) @@ -195,7 +193,7 @@ /** * @brief DMA CRYP communication error callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void CRYP_DMAError(DMA_HandleTypeDef *hdma) @@ -207,10 +205,10 @@ /** * @brief Writes the Key in Key registers. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param Key: Pointer to Key buffer - * @param KeySize: Size of Key + * @param Key Pointer to Key buffer + * @param KeySize Size of Key * @retval None */ static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize) @@ -266,10 +264,10 @@ /** * @brief Writes the InitVector/InitCounter in IV registers. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param InitVector: Pointer to InitVector/InitCounter buffer - * @param IVSize: Size of the InitVector/InitCounter + * @param InitVector Pointer to InitVector/InitCounter buffer + * @param IVSize Size of the InitVector/InitCounter * @retval None */ static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector, uint32_t IVSize) @@ -305,12 +303,12 @@ /** * @brief Process Data: Writes Input data in polling mode and read the output data - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param Input: Pointer to the Input buffer - * @param Ilength: Length of the Input buffer, must be a multiple of 16. - * @param Output: Pointer to the returned buffer - * @param Timeout: Timeout value + * @param Input Pointer to the Input buffer + * @param Ilength Length of the Input buffer, must be a multiple of 16. + * @param Output Pointer to the returned buffer + * @param Timeout Timeout value * @retval None */ static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout) @@ -369,12 +367,12 @@ /** * @brief Process Data: Write Input data in polling mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param Input: Pointer to the Input buffer - * @param Ilength: Length of the Input buffer, must be a multiple of 8 - * @param Output: Pointer to the returned buffer - * @param Timeout: Specify Timeout value + * @param Input Pointer to the Input buffer + * @param Ilength Length of the Input buffer, must be a multiple of 8 + * @param Output Pointer to the returned buffer + * @param Timeout Specify Timeout value * @retval None */ static HAL_StatusTypeDef CRYP_ProcessData2Words(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout) @@ -425,11 +423,11 @@ /** * @brief Set the DMA configuration and start the DMA transfer - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param inputaddr: address of the Input buffer - * @param Size: Size of the Input buffer, must be a multiple of 16. - * @param outputaddr: address of the Output buffer + * @param inputaddr address of the Input buffer + * @param Size Size of the Input buffer, must be a multiple of 16. + * @param outputaddr address of the Output buffer * @retval None */ static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr) @@ -463,9 +461,9 @@ /** * @brief Sets the CRYP peripheral in DES ECB mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param Direction: Encryption or decryption + * @param Direction Encryption or decryption * @retval None */ static void CRYP_SetDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction) @@ -490,9 +488,9 @@ /** * @brief Sets the CRYP peripheral in DES CBC mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param Direction: Encryption or decryption + * @param Direction Encryption or decryption * @retval None */ static void CRYP_SetDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction) @@ -520,9 +518,9 @@ /** * @brief Sets the CRYP peripheral in TDES ECB mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param Direction: Encryption or decryption + * @param Direction Encryption or decryption * @retval None */ static void CRYP_SetTDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction) @@ -546,9 +544,9 @@ /** * @brief Sets the CRYP peripheral in TDES CBC mode - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param Direction: Encryption or decryption + * @param Direction Encryption or decryption * @retval None */ static void CRYP_SetTDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction) @@ -603,7 +601,7 @@ /** * @brief Initializes the CRYP according to the specified * parameters in the CRYP_InitTypeDef and creates the associated handle. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval HAL status */ @@ -649,7 +647,7 @@ /** * @brief DeInitializes the CRYP peripheral. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval HAL status */ @@ -689,7 +687,7 @@ /** * @brief Initializes the CRYP MSP. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -704,7 +702,7 @@ /** * @brief DeInitializes CRYP MSP. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -743,12 +741,12 @@ /** * @brief Initializes the CRYP peripheral in AES ECB encryption mode * then encrypt pPlainData. The cypher data are available in pCypherData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) @@ -797,12 +795,12 @@ /** * @brief Initializes the CRYP peripheral in AES CBC encryption mode * then encrypt pPlainData. The cypher data are available in pCypherData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) @@ -854,12 +852,12 @@ /** * @brief Initializes the CRYP peripheral in AES CTR encryption mode * then encrypt pPlainData. The cypher data are available in pCypherData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) @@ -913,12 +911,12 @@ /** * @brief Initializes the CRYP peripheral in AES ECB decryption mode * then decrypted pCypherData. The cypher data are available in pPlainData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer - * @param Timeout: Specify Timeout value + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16. + * @param pPlainData Pointer to the plaintext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) @@ -1001,12 +999,12 @@ /** * @brief Initializes the CRYP peripheral in AES ECB decryption mode * then decrypted pCypherData. The cypher data are available in pPlainData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer - * @param Timeout: Specify Timeout value + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16. + * @param pPlainData Pointer to the plaintext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) @@ -1090,12 +1088,12 @@ /** * @brief Initializes the CRYP peripheral in AES CTR decryption mode * then decrypted pCypherData. The cypher data are available in pPlainData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer - * @param Timeout: Specify Timeout value + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16. + * @param pPlainData Pointer to the plaintext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) @@ -1146,11 +1144,11 @@ /** * @brief Initializes the CRYP peripheral in AES ECB encryption mode using Interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -1247,11 +1245,11 @@ /** * @brief Initializes the CRYP peripheral in AES CBC encryption mode using Interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -1350,11 +1348,11 @@ /** * @brief Initializes the CRYP peripheral in AES CTR encryption mode using Interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -1454,11 +1452,11 @@ /** * @brief Initializes the CRYP peripheral in AES ECB decryption mode using Interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16. + * @param pPlainData Pointer to the plaintext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -1583,11 +1581,11 @@ /** * @brief Initializes the CRYP peripheral in AES CBC decryption mode using IT. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 + * @param pPlainData Pointer to the plaintext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -1720,11 +1718,11 @@ /** * @brief Initializes the CRYP peripheral in AES CTR decryption mode using Interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 + * @param pPlainData Pointer to the plaintext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -1825,11 +1823,11 @@ /** * @brief Initializes the CRYP peripheral in AES ECB encryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -1880,11 +1878,11 @@ /** * @brief Initializes the CRYP peripheral in AES CBC encryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -1938,11 +1936,11 @@ /** * @brief Initializes the CRYP peripheral in AES CTR encryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -1997,11 +1995,11 @@ /** * @brief Initializes the CRYP peripheral in AES ECB decryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes + * @param pPlainData Pointer to the plaintext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -2081,11 +2079,11 @@ /** * @brief Initializes the CRYP peripheral in AES CBC encryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes + * @param pPlainData Pointer to the plaintext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -2168,11 +2166,11 @@ /** * @brief Initializes the CRYP peripheral in AES CTR decryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 + * @param pPlainData Pointer to the plaintext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -2251,12 +2249,12 @@ /** * @brief Initializes the CRYP peripheral in DES ECB encryption mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) @@ -2291,12 +2289,12 @@ /** * @brief Initializes the CRYP peripheral in DES ECB decryption mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pPlainData: Pointer to the plaintext buffer - * @param Timeout: Specify Timeout value + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pPlainData Pointer to the plaintext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) @@ -2331,12 +2329,12 @@ /** * @brief Initializes the CRYP peripheral in DES CBC encryption mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) @@ -2371,12 +2369,12 @@ /** * @brief Initializes the CRYP peripheral in DES ECB decryption mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pPlainData: Pointer to the plaintext buffer - * @param Timeout: Specify Timeout value + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pPlainData Pointer to the plaintext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) @@ -2411,11 +2409,11 @@ /** * @brief Initializes the CRYP peripheral in DES ECB encryption mode using IT. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -2496,11 +2494,11 @@ /** * @brief Initializes the CRYP peripheral in DES CBC encryption mode using interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -2582,11 +2580,11 @@ /** * @brief Initializes the CRYP peripheral in DES ECB decryption mode using IT. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -2667,11 +2665,11 @@ /** * @brief Initializes the CRYP peripheral in DES ECB decryption mode using interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -2752,11 +2750,11 @@ /** * @brief Initializes the CRYP peripheral in DES ECB encryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -2795,11 +2793,11 @@ /** * @brief Initializes the CRYP peripheral in DES CBC encryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -2838,11 +2836,11 @@ /** * @brief Initializes the CRYP peripheral in DES ECB decryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -2881,11 +2879,11 @@ /** * @brief Initializes the CRYP peripheral in DES ECB decryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -2948,12 +2946,12 @@ /** * @brief Initializes the CRYP peripheral in TDES ECB encryption mode * then encrypt pPlainData. The cypher data are available in pCypherData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) @@ -2989,12 +2987,12 @@ /** * @brief Initializes the CRYP peripheral in TDES ECB decryption mode * then decrypted pCypherData. The cypher data are available in pPlainData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) @@ -3030,12 +3028,12 @@ /** * @brief Initializes the CRYP peripheral in TDES CBC encryption mode * then encrypt pPlainData. The cypher data are available in pCypherData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) @@ -3071,12 +3069,12 @@ /** * @brief Initializes the CRYP peripheral in TDES CBC decryption mode * then decrypted pCypherData. The cypher data are available in pPlainData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pPlainData: Pointer to the plaintext buffer - * @param Timeout: Specify Timeout value + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pPlainData Pointer to the plaintext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) @@ -3111,11 +3109,11 @@ /** * @brief Initializes the CRYP peripheral in TDES ECB encryption mode using interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -3196,11 +3194,11 @@ /** * @brief Initializes the CRYP peripheral in TDES CBC encryption mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -3280,11 +3278,11 @@ /** * @brief Initializes the CRYP peripheral in TDES ECB decryption mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -3364,11 +3362,11 @@ /** * @brief Initializes the CRYP peripheral in TDES CBC decryption mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pPlainData Pointer to the plaintext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -3448,11 +3446,11 @@ /** * @brief Initializes the CRYP peripheral in TDES ECB encryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -3491,11 +3489,11 @@ /** * @brief Initializes the CRYP peripheral in TDES CBC encryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -3534,11 +3532,11 @@ /** * @brief Initializes the CRYP peripheral in TDES ECB decryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -3577,11 +3575,11 @@ /** * @brief Initializes the CRYP peripheral in TDES CBC decryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pPlainData Pointer to the plaintext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -3640,7 +3638,7 @@ /** * @brief Input FIFO transfer completed callbacks. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -3655,7 +3653,7 @@ /** * @brief Output FIFO transfer completed callbacks. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -3670,7 +3668,7 @@ /** * @brief CRYP error callbacks. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -3702,7 +3700,7 @@ /** * @brief This function handles CRYP interrupt request. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -3791,7 +3789,7 @@ /** * @brief Returns the CRYP state. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval HAL state */ @@ -4092,7 +4090,7 @@ /** * @brief DeInitialize the CRYP peripheral. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval HAL status */ @@ -4132,7 +4130,7 @@ /** * @brief Initialize the CRYP MSP. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -4148,7 +4146,7 @@ /** * @brief DeInitialize CRYP MSP. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -4188,12 +4186,12 @@ /** * @brief Encrypt pPlainData in AES ECB encryption mode. The cypher data are available in pCypherData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Specify Timeout value * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). * @retval HAL status @@ -4219,12 +4217,12 @@ /** * @brief Encrypt pPlainData in AES CBC encryption mode with key derivation. The cypher data are available in pCypherData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Specify Timeout value * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). * @retval HAL status @@ -4250,12 +4248,12 @@ /** * @brief Encrypt pPlainData in AES CTR encryption mode. The cypher data are available in pCypherData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Specify Timeout value * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). * @retval HAL status @@ -4281,12 +4279,12 @@ /** * @brief Decrypt pCypherData in AES ECB decryption mode with key derivation, * the decyphered data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer - * @param Timeout: Specify Timeout value + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pPlainData Pointer to the plaintext buffer + * @param Timeout Specify Timeout value * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). * @retval HAL status @@ -4312,12 +4310,12 @@ /** * @brief Decrypt pCypherData in AES ECB decryption mode with key derivation, * the decyphered data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer - * @param Timeout: Specify Timeout value + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pPlainData Pointer to the plaintext buffer + * @param Timeout Specify Timeout value * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). * @retval HAL status @@ -4343,12 +4341,12 @@ /** * @brief Decrypt pCypherData in AES CTR decryption mode, * the decyphered data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer - * @param Timeout: Specify Timeout value + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pPlainData Pointer to the plaintext buffer + * @param Timeout Specify Timeout value * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). * @retval HAL status @@ -4374,11 +4372,11 @@ /** * @brief Encrypt pPlainData in AES ECB encryption mode using Interrupt, * the cypher data are available in pCypherData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). * @retval HAL status @@ -4404,11 +4402,11 @@ /** * @brief Encrypt pPlainData in AES CBC encryption mode using Interrupt, * the cypher data are available in pCypherData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). * @retval HAL status @@ -4435,11 +4433,11 @@ /** * @brief Encrypt pPlainData in AES CTR encryption mode using Interrupt, * the cypher data are available in pCypherData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). * @retval HAL status @@ -4465,11 +4463,11 @@ /** * @brief Decrypt pCypherData in AES ECB decryption mode using Interrupt, * the decyphered data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer. + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pPlainData Pointer to the plaintext buffer. * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). * @retval HAL status @@ -4495,11 +4493,11 @@ /** * @brief Decrypt pCypherData in AES CBC decryption mode using Interrupt, * the decyphered data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pPlainData Pointer to the plaintext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). * @retval HAL status @@ -4525,11 +4523,11 @@ /** * @brief Decrypt pCypherData in AES CTR decryption mode using Interrupt, * the decyphered data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pPlainData Pointer to the plaintext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). * @retval HAL status @@ -4555,11 +4553,11 @@ /** * @brief Encrypt pPlainData in AES ECB encryption mode using DMA, * the cypher data are available in pCypherData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended). * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. @@ -4588,11 +4586,11 @@ /** * @brief Encrypt pPlainData in AES CBC encryption mode using DMA, * the cypher data are available in pCypherData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended). * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. @@ -4619,11 +4617,11 @@ /** * @brief Encrypt pPlainData in AES CTR encryption mode using DMA, * the cypher data are available in pCypherData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer. + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer. * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended). * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. @@ -4650,11 +4648,11 @@ /** * @brief Decrypt pCypherData in AES ECB decryption mode using DMA, * the decyphered data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pPlainData Pointer to the plaintext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended). * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. @@ -4681,11 +4679,11 @@ /** * @brief Decrypt pCypherData in AES CBC decryption mode using DMA, * the decyphered data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pPlainData Pointer to the plaintext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended). * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. @@ -4712,11 +4710,11 @@ /** * @brief Decrypt pCypherData in AES CTR decryption mode using DMA, * the decyphered data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pPlainData Pointer to the plaintext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended). * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. @@ -4763,7 +4761,7 @@ /** * @brief CRYP error callback. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -4779,7 +4777,7 @@ /** * @brief Input DMA transfer complete callback. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -4795,7 +4793,7 @@ /** * @brief Output DMA transfer complete callback. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -4828,7 +4826,7 @@ /** * @brief Handle AES interrupt request. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -4913,7 +4911,7 @@ /** * @brief Return the CRYP handle state. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval HAL state */ @@ -4925,7 +4923,7 @@ /** * @brief Return the CRYP peripheral error. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @note The returned error is a bit-map combination of possible errors * @retval Error bit-map @@ -4950,7 +4948,7 @@ /** * @brief Write the Key in KeyRx registers. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -4991,7 +4989,7 @@ /** * @brief Write the InitVector/InitCounter in IVRx registers. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -5034,7 +5032,7 @@ * @brief Handle CRYP block input/output data handling under interruption. * @note The function is called under interruption only, once * interruptions have been enabled by HAL_CRYPEx_AES_IT(). - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. * @retval HAL status */
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cryp.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cryp.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_cryp.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief Header file of CRYP HAL module.
******************************************************************************
* @attention
@@ -260,14 +258,14 @@
*/
/** @brief Reset CRYP handle state
- * @param __HANDLE__: specifies the CRYP handle.
+ * @param __HANDLE__ specifies the CRYP handle.
* @retval None
*/
#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRYP_STATE_RESET)
/**
* @brief Enable/Disable the CRYP peripheral.
- * @param __HANDLE__: specifies the CRYP handle.
+ * @param __HANDLE__ specifies the CRYP handle.
* @retval None
*/
#define __HAL_CRYP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_CRYPEN)
@@ -275,22 +273,22 @@
/**
* @brief Flush the data FIFO.
- * @param __HANDLE__: specifies the CRYP handle.
+ * @param __HANDLE__ specifies the CRYP handle.
* @retval None
*/
#define __HAL_CRYP_FIFO_FLUSH(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_FFLUSH)
/**
* @brief Set the algorithm mode: AES-ECB, AES-CBC, AES-CTR, DES-ECB, DES-CBC.
- * @param __HANDLE__: specifies the CRYP handle.
- * @param MODE: The algorithm mode.
+ * @param __HANDLE__ specifies the CRYP handle.
+ * @param MODE The algorithm mode.
* @retval None
*/
#define __HAL_CRYP_SET_MODE(__HANDLE__, MODE) ((__HANDLE__)->Instance->CR |= (uint32_t)(MODE))
/** @brief Check whether the specified CRYP flag is set or not.
- * @param __HANDLE__: specifies the CRYP handle.
- * @param __FLAG__: specifies the flag to check.
+ * @param __HANDLE__ specifies the CRYP handle.
+ * @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data
* or a key preparation (for AES decryption).
@@ -307,8 +305,8 @@
((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)))
/** @brief Check whether the specified CRYP interrupt is set or not.
- * @param __HANDLE__: specifies the CRYP handle.
- * @param __INTERRUPT__: specifies the interrupt to check.
+ * @param __HANDLE__ specifies the CRYP handle.
+ * @param __INTERRUPT__ specifies the interrupt to check.
* This parameter can be one of the following values:
* @arg CRYP_IT_INRIS: Input FIFO service raw interrupt is pending
* @arg CRYP_IT_OUTRIS: Output FIFO service raw interrupt is pending
@@ -318,16 +316,16 @@
/**
* @brief Enable the CRYP interrupt.
- * @param __HANDLE__: specifies the CRYP handle.
- * @param __INTERRUPT__: CRYP Interrupt.
+ * @param __HANDLE__ specifies the CRYP handle.
+ * @param __INTERRUPT__ CRYP Interrupt.
* @retval None
*/
#define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) |= (__INTERRUPT__))
/**
* @brief Disable the CRYP interrupt.
- * @param __HANDLE__: specifies the CRYP handle.
- * @param __INTERRUPT__: CRYP interrupt.
+ * @param __HANDLE__ specifies the CRYP handle.
+ * @param __INTERRUPT__ CRYP interrupt.
* @retval None
*/
#define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) &= ~(__INTERRUPT__))
@@ -821,7 +819,7 @@
*/
/** @brief Reset CRYP handle state.
- * @param __HANDLE__: specifies the CRYP handle.
+ * @param __HANDLE__ specifies the CRYP handle.
* @retval None
*/
#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRYP_STATE_RESET)
@@ -840,7 +838,7 @@
/**
* @brief Set the algorithm operating mode.
- * @param __OPERATING_MODE__: specifies the operating mode
+ * @param __OPERATING_MODE__ specifies the operating mode
* This parameter can be one of the following values:
* @arg @ref CRYP_ALGOMODE_ENCRYPT encryption
* @arg @ref CRYP_ALGOMODE_KEYDERIVATION key derivation
@@ -853,7 +851,7 @@
/**
* @brief Set the algorithm chaining mode.
- * @param __CHAINING_MODE__: specifies the chaining mode
+ * @param __CHAINING_MODE__ specifies the chaining mode
* This parameter can be one of the following values:
* @arg @ref CRYP_CHAINMODE_AES_ECB Electronic CodeBook
* @arg @ref CRYP_CHAINMODE_AES_CBC Cipher Block Chaining
@@ -867,7 +865,7 @@
/** @brief Check whether the specified CRYP status flag is set or not.
- * @param __FLAG__: specifies the flag to check.
+ * @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref CRYP_FLAG_BUSY GCM process suspension forbidden
* @arg @ref CRYP_IT_WRERR Write Error
@@ -879,7 +877,7 @@
/** @brief Clear the CRYP pending status flag.
- * @param __FLAG__: specifies the flag to clear.
+ * @param __FLAG__ specifies the flag to clear.
* This parameter can be one of the following values:
* @arg @ref CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear
* @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear
@@ -890,7 +888,7 @@
/** @brief Check whether the specified CRYP interrupt source is enabled or not.
- * @param __INTERRUPT__: CRYP interrupt source to check
+ * @param __INTERRUPT__ CRYP interrupt source to check
* This parameter can be one of the following values:
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
@@ -900,7 +898,7 @@
/** @brief Check whether the specified CRYP interrupt is set or not.
- * @param __INTERRUPT__: specifies the interrupt to check.
+ * @param __INTERRUPT__ specifies the interrupt to check.
* This parameter can be one of the following values:
* @arg @ref CRYP_IT_WRERR Write Error
* @arg @ref CRYP_IT_RDERR Read Error
@@ -912,7 +910,7 @@
/** @brief Clear the CRYP pending interrupt.
- * @param __INTERRUPT__: specifies the IT to clear.
+ * @param __INTERRUPT__ specifies the IT to clear.
* This parameter can be one of the following values:
* @arg @ref CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear
* @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear
@@ -923,7 +921,7 @@
/**
* @brief Enable the CRYP interrupt.
- * @param __INTERRUPT__: CRYP Interrupt.
+ * @param __INTERRUPT__ CRYP Interrupt.
* This parameter can be one of the following values:
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
@@ -934,7 +932,7 @@
/**
* @brief Disable the CRYP interrupt.
- * @param __INTERRUPT__: CRYP Interrupt.
+ * @param __INTERRUPT__ CRYP Interrupt.
* This parameter can be one of the following values:
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
@@ -953,7 +951,7 @@
/**
* @brief Verify the key size length.
- * @param __KEYSIZE__: Ciphering/deciphering algorithm key size.
+ * @param __KEYSIZE__ Ciphering/deciphering algorithm key size.
* @retval SET (__KEYSIZE__ is a valid value) or RESET (__KEYSIZE__ is invalid)
*/
#define IS_CRYP_KEYSIZE(__KEYSIZE__) (((__KEYSIZE__) == CRYP_KEYSIZE_128B) || \
@@ -961,7 +959,7 @@
/**
* @brief Verify the input data type.
- * @param __DATATYPE__: Ciphering/deciphering algorithm input data type.
+ * @param __DATATYPE__ Ciphering/deciphering algorithm input data type.
* @retval SET (__DATATYPE__ is valid) or RESET (__DATATYPE__ is invalid)
*/
#define IS_CRYP_DATATYPE(__DATATYPE__) (((__DATATYPE__) == CRYP_DATATYPE_32B) || \
@@ -971,7 +969,7 @@
/**
* @brief Verify the CRYP AES IP running mode.
- * @param __MODE__: CRYP AES IP running mode.
+ * @param __MODE__ CRYP AES IP running mode.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
*/
#define IS_CRYP_AES(__MODE__) (((__MODE__) == CRYP_AES_DISABLE) || \
@@ -979,7 +977,7 @@
/**
* @brief Verify the selected CRYP algorithm.
- * @param __ALGOMODE__: Selected CRYP algorithm (ciphering, deciphering, key derivation or a combination of the latter).
+ * @param __ALGOMODE__ Selected CRYP algorithm (ciphering, deciphering, key derivation or a combination of the latter).
* @retval SET (__ALGOMODE__ is valid) or RESET (__ALGOMODE__ is invalid)
*/
#define IS_CRYP_ALGOMODE(__ALGOMODE__) (((__ALGOMODE__) == CRYP_ALGOMODE_ENCRYPT) || \
@@ -990,7 +988,7 @@
/**
* @brief Verify the selected CRYP chaining algorithm.
- * @param __CHAINMODE__: Selected CRYP chaining algorithm.
+ * @param __CHAINMODE__ Selected CRYP chaining algorithm.
* @retval SET (__CHAINMODE__ is valid) or RESET (__CHAINMODE__ is invalid)
*/
#if defined(AES_CR_NPBLB)
@@ -1009,7 +1007,7 @@
/**
* @brief Verify the deciphering key write option.
- * @param __WRITE__: deciphering key write option.
+ * @param __WRITE__ deciphering key write option.
* @retval SET (__WRITE__ is valid) or RESET (__WRITE__ is invalid)
*/
#define IS_CRYP_WRITE(__WRITE__) (((__WRITE__) == CRYP_KEY_WRITE_ENABLE) || \
@@ -1017,7 +1015,7 @@
/**
* @brief Verify the CRYP input data DMA mode.
- * @param __MODE__: CRYP input data DMA mode.
+ * @param __MODE__ CRYP input data DMA mode.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
*/
#define IS_CRYP_DMAIN(__MODE__) (((__MODE__) == CRYP_DMAIN_DISABLE) || \
@@ -1025,7 +1023,7 @@
/**
* @brief Verify the CRYP output data DMA mode.
- * @param __MODE__: CRYP output data DMA mode.
+ * @param __MODE__ CRYP output data DMA mode.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
*/
#define IS_CRYP_DMAOUT(__MODE__) (((__MODE__) == CRYP_DMAOUT_DISABLE) || \
@@ -1033,7 +1031,7 @@
/**
* @brief Verify the CRYP AES ciphering/deciphering/authentication algorithm phase.
- * @param __PHASE__: CRYP AES ciphering/deciphering/authentication algorithm phase.
+ * @param __PHASE__ CRYP AES ciphering/deciphering/authentication algorithm phase.
* @retval SET (__PHASE__ is valid) or RESET (__PHASE__ is invalid)
*/
#define IS_CRYP_GCMCMAC_PHASE(__PHASE__) (((__PHASE__) == CRYP_GCM_INIT_PHASE) || \
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cryp_ex.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cryp_ex.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_cryp_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Extended CRYP HAL module driver * This file provides firmware functions to manage the following * functionalities of CRYP extension peripheral: @@ -147,7 +145,7 @@ /** * @brief DMA CRYP Input Data process complete callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void CRYPEx_GCMCCM_DMAInCplt(DMA_HandleTypeDef *hdma) @@ -164,7 +162,7 @@ /** * @brief DMA CRYP Output Data process complete callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void CRYPEx_GCMCCM_DMAOutCplt(DMA_HandleTypeDef *hdma) @@ -187,7 +185,7 @@ /** * @brief DMA CRYP communication error callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void CRYPEx_GCMCCM_DMAError(DMA_HandleTypeDef *hdma) @@ -199,10 +197,10 @@ /** * @brief Writes the Key in Key registers. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param Key: Pointer to Key buffer - * @param KeySize: Size of Key + * @param Key Pointer to Key buffer + * @param KeySize Size of Key * @retval None */ static void CRYPEx_GCMCCM_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize) @@ -258,9 +256,9 @@ /** * @brief Writes the InitVector/InitCounter in IV registers. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param InitVector: Pointer to InitVector/InitCounter buffer + * @param InitVector Pointer to InitVector/InitCounter buffer * @retval None */ static void CRYPEx_GCMCCM_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector) @@ -278,12 +276,12 @@ /** * @brief Process Data: Writes Input data in polling mode and read the Output data. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param Input: Pointer to the Input buffer. - * @param Ilength: Length of the Input buffer, must be a multiple of 16 - * @param Output: Pointer to the returned buffer - * @param Timeout: Timeout value + * @param Input Pointer to the Input buffer. + * @param Ilength Length of the Input buffer, must be a multiple of 16 + * @param Output Pointer to the returned buffer + * @param Timeout Timeout value * @retval None */ static HAL_StatusTypeDef CRYPEx_GCMCCM_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t *Input, uint16_t Ilength, uint8_t *Output, uint32_t Timeout) @@ -341,11 +339,11 @@ /** * @brief Sets the header phase - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param Input: Pointer to the Input buffer. - * @param Ilength: Length of the Input buffer, must be a multiple of 16 - * @param Timeout: Timeout value + * @param Input Pointer to the Input buffer. + * @param Ilength Length of the Input buffer, must be a multiple of 16 + * @param Timeout Timeout value * @retval None */ static HAL_StatusTypeDef CRYPEx_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint32_t Timeout) @@ -427,11 +425,11 @@ /** * @brief Sets the DMA configuration and start the DMA transfer. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param inputaddr: Address of the Input buffer - * @param Size: Size of the Input buffer, must be a multiple of 16 - * @param outputaddr: Address of the Output buffer + * @param inputaddr Address of the Input buffer + * @param Size Size of the Input buffer, must be a multiple of 16 + * @param outputaddr Address of the Output buffer * @retval None */ static void CRYPEx_GCMCCM_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr) @@ -495,12 +493,12 @@ /** * @brief Initializes the CRYP peripheral in AES CCM encryption mode then * encrypt pPlainData. The cypher data are available in pCypherData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Timeout duration + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) @@ -751,12 +749,12 @@ /** * @brief Initializes the CRYP peripheral in AES GCM encryption mode then * encrypt pPlainData. The cypher data are available in pCypherData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Timeout duration + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) @@ -849,12 +847,12 @@ /** * @brief Initializes the CRYP peripheral in AES GCM decryption mode then * decrypted pCypherData. The cypher data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the cyphertext buffer, must be a multiple of 16 - * @param pPlainData: Pointer to the plaintext buffer - * @param Timeout: Timeout duration + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the cyphertext buffer, must be a multiple of 16 + * @param pPlainData Pointer to the plaintext buffer + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) @@ -942,11 +940,11 @@ /** * @brief Computes the authentication TAG. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param Size: Total length of the plain/cyphertext buffer - * @param AuthTag: Pointer to the authentication buffer - * @param Timeout: Timeout duration + * @param Size Total length of the plain/cyphertext buffer + * @param AuthTag Pointer to the authentication buffer + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Finish(CRYP_HandleTypeDef *hcryp, uint32_t Size, uint8_t *AuthTag, uint32_t Timeout) @@ -1051,10 +1049,10 @@ /** * @brief Computes the authentication TAG for AES CCM mode. * @note This API is called after HAL_AES_CCM_Encrypt()/HAL_AES_CCM_Decrypt() - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param AuthTag: Pointer to the authentication buffer - * @param Timeout: Timeout duration + * @param AuthTag Pointer to the authentication buffer + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Finish(CRYP_HandleTypeDef *hcryp, uint8_t *AuthTag, uint32_t Timeout) @@ -1143,12 +1141,12 @@ /** * @brief Initializes the CRYP peripheral in AES CCM decryption mode then * decrypted pCypherData. The cypher data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Timeout duration + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) @@ -1395,11 +1393,11 @@ /** * @brief Initializes the CRYP peripheral in AES GCM encryption mode using IT. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -1546,11 +1544,11 @@ /** * @brief Initializes the CRYP peripheral in AES CCM encryption mode using interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -1845,11 +1843,11 @@ /** * @brief Initializes the CRYP peripheral in AES GCM decryption mode using IT. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the cyphertext buffer, must be a multiple of 16 - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the cyphertext buffer, must be a multiple of 16 + * @param pPlainData Pointer to the plaintext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -1993,11 +1991,11 @@ /** * @brief Initializes the CRYP peripheral in AES CCM decryption mode using interrupt * then decrypted pCypherData. The cypher data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 + * @param pPlainData Pointer to the plaintext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -2283,11 +2281,11 @@ /** * @brief Initializes the CRYP peripheral in AES GCM encryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -2380,11 +2378,11 @@ /** * @brief Initializes the CRYP peripheral in AES CCM encryption mode using interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -2634,11 +2632,11 @@ /** * @brief Initializes the CRYP peripheral in AES GCM decryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer. - * @param Size: Length of the cyphertext buffer, must be a multiple of 16 - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer. + * @param Size Length of the cyphertext buffer, must be a multiple of 16 + * @param pPlainData Pointer to the plaintext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -2724,11 +2722,11 @@ /** * @brief Initializes the CRYP peripheral in AES CCM decryption mode using DMA * then decrypted pCypherData. The cypher data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 + * @param pPlainData Pointer to the plaintext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -2995,7 +2993,7 @@ /** * @brief This function handles CRYPEx interrupt request. - * @param hcryp: pointer to a CRYPEx_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYPEx_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -3095,7 +3093,7 @@ /** * @brief Computation completed callbacks. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -3144,17 +3142,17 @@ * @brief Carry out in polling mode the ciphering or deciphering operation according to * hcryp->Init structure fields, all operating modes (encryption, key derivation and/or decryption) and * chaining modes ECB, CBC and CTR are managed by this function in polling mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pInputData: Pointer to the plain text in case of encryption or cipher text in case of decryption + * @param pInputData Pointer to the plain text in case of encryption or cipher text in case of decryption * or key derivation+decryption. * Parameter is meaningless in case of key derivation. - * @param Size: Length of the input data buffer in bytes, must be a multiple of 16. + * @param Size Length of the input data buffer in bytes, must be a multiple of 16. * Parameter is meaningless in case of key derivation. - * @param pOutputData: Pointer to the cipher text in case of encryption or plain text in case of + * @param pOutputData Pointer to the cipher text in case of encryption or plain text in case of * decryption/key derivation+decryption, or pointer to the derivative keys in * case of key derivation only. - * @param Timeout: Specify Timeout value + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AES(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData, uint32_t Timeout) @@ -3223,14 +3221,14 @@ * @brief Carry out in interrupt mode the ciphering or deciphering operation according to * hcryp->Init structure fields, all operating modes (encryption, key derivation and/or decryption) and * chaining modes ECB, CBC and CTR are managed by this function in interrupt mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pInputData: Pointer to the plain text in case of encryption or cipher text in case of decryption + * @param pInputData Pointer to the plain text in case of encryption or cipher text in case of decryption * or key derivation+decryption. * Parameter is meaningless in case of key derivation. - * @param Size: Length of the input data buffer in bytes, must be a multiple of 16. + * @param Size Length of the input data buffer in bytes, must be a multiple of 16. * Parameter is meaningless in case of key derivation. - * @param pOutputData: Pointer to the cipher text in case of encryption or plain text in case of + * @param pOutputData Pointer to the cipher text in case of encryption or plain text in case of * decryption/key derivation+decryption, or pointer to the derivative keys in * case of key derivation only. * @retval HAL status @@ -3313,12 +3311,12 @@ /** * @brief Carry out in DMA mode the ciphering or deciphering operation according to * hcryp->Init structure fields. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pInputData: Pointer to the plain text in case of encryption or cipher text in case of decryption + * @param pInputData Pointer to the plain text in case of encryption or cipher text in case of decryption * or key derivation+decryption. - * @param Size: Length of the input data buffer in bytes, must be a multiple of 16. - * @param pOutputData: Pointer to the cipher text in case of encryption or plain text in case of + * @param Size Length of the input data buffer in bytes, must be a multiple of 16. + * @param pOutputData Pointer to the cipher text in case of encryption or plain text in case of * decryption/key derivation+decryption. * @note Chaining modes ECB, CBC and CTR are managed by this function in DMA mode. * @note Supported operating modes are encryption, decryption and key derivation with decryption. @@ -3378,24 +3376,24 @@ /** * @brief Carry out in polling mode the authentication tag generation as well as the ciphering or deciphering * operation according to hcryp->Init structure fields. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pInputData: + * @param pInputData * - pointer to payload data in GCM payload phase, * - pointer to B0 block in CMAC header phase, * - pointer to C block in CMAC final phase. * - Parameter is meaningless in case of GCM/GMAC init, header and final phases. - * @param Size: + * @param Size * - length of the input payload data buffer in bytes, * - length of B0 block (in bytes) in CMAC header phase, * - length of C block (in bytes) in CMAC final phase. * - Parameter is meaningless in case of GCM/GMAC init and header phases. - * @param pOutputData: + * @param pOutputData * - pointer to plain or cipher text in GCM payload phase, * - pointer to authentication tag in GCM/GMAC and CMAC final phases. * - Parameter is meaningless in case of GCM/GMAC init and header phases * and in case of CMAC header phase. - * @param Timeout: Specify Timeout value + * @param Timeout Specify Timeout value * @note Supported operating modes are encryption and decryption, supported chaining modes are GCM, GMAC, CMAC and CCM when the latter is applicable. * @note Phases are singly processed according to hcryp->Init.GCMCMACPhase so that steps in these specific chaining modes * can be skipped by the user if so required. @@ -3860,19 +3858,19 @@ /** * @brief Carry out in interrupt mode the authentication tag generation as well as the ciphering or deciphering * operation according to hcryp->Init structure fields. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pInputData: + * @param pInputData * - pointer to payload data in GCM payload phase, * - pointer to B0 block in CMAC header phase, * - pointer to C block in CMAC final phase. * Parameter is meaningless in case of GCM/GMAC init, header and final phases. - * @param Size: + * @param Size * - length of the input payload data buffer in bytes, * - length of B0 block (in bytes) in CMAC header phase, * - length of C block (in bytes) in CMAC final phase. * - Parameter is meaningless in case of GCM/GMAC init and header phases. - * @param pOutputData: + * @param pOutputData * - pointer to plain or cipher text in GCM payload phase, * - pointer to authentication tag in GCM/GMAC and CMAC final phases. * - Parameter is meaningless in case of GCM/GMAC init and header phases @@ -4271,19 +4269,19 @@ /** * @brief Carry out in DMA mode the authentication tag generation as well as the ciphering or deciphering * operation according to hcryp->Init structure fields. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pInputData: + * @param pInputData * - pointer to payload data in GCM payload phase, * - pointer to B0 block in CMAC header phase, * - pointer to C block in CMAC final phase. * - Parameter is meaningless in case of GCM/GMAC init, header and final phases. - * @param Size: + * @param Size * - length of the input payload data buffer in bytes, * - length of B block (in bytes) in CMAC header phase, * - length of C block (in bytes) in CMAC final phase. * - Parameter is meaningless in case of GCM/GMAC init and header phases. - * @param pOutputData: + * @param pOutputData * - pointer to plain or cipher text in GCM payload phase, * - pointer to authentication tag in GCM/GMAC and CMAC final phases. * - Parameter is meaningless in case of GCM/GMAC init and header phases @@ -4696,9 +4694,9 @@ /** * @brief In case of message processing suspension, read the Initialization Vector. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param Output: Pointer to the buffer containing the saved Initialization Vector. + * @param Output Pointer to the buffer containing the saved Initialization Vector. * @note This value has to be stored for reuse by writing the AES_IVRx registers * as soon as the interrupted processing has to be resumed. * Applicable to all chaining modes. @@ -4721,9 +4719,9 @@ /** * @brief In case of message processing resumption, rewrite the Initialization * Vector in the AES_IVRx registers. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param Input: Pointer to the buffer containing the saved Initialization Vector to + * @param Input Pointer to the buffer containing the saved Initialization Vector to * write back in the CRYP hardware block. * @note Applicable to all chaining modes. * @note AES must be disabled when reading or resetting the IV values. @@ -4745,9 +4743,9 @@ /** * @brief In case of message GCM/GMAC or CMAC processing suspension, read the Suspend Registers. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param Output: Pointer to the buffer containing the saved Suspend Registers. + * @param Output Pointer to the buffer containing the saved Suspend Registers. * @note These values have to be stored for reuse by writing back the AES_SUSPxR registers * as soon as the interrupted processing has to be resumed. * @retval None @@ -4793,9 +4791,9 @@ /** * @brief In case of message GCM/GMAC or CMAC processing resumption, rewrite the Suspend * Registers in the AES_SUSPxR registers. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param Input: Pointer to the buffer containing the saved suspend registers to + * @param Input Pointer to the buffer containing the saved suspend registers to * write back in the CRYP hardware block. * @retval None */ @@ -4823,10 +4821,10 @@ /** * @brief In case of message GCM/GMAC or CMAC processing suspension, read the Key Registers. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param Output: Pointer to the buffer containing the saved Key Registers. - * @param KeySize: Indicates the key size (128 or 256 bits). + * @param Output Pointer to the buffer containing the saved Key Registers. + * @param KeySize Indicates the key size (128 or 256 bits). * @note These values have to be stored for reuse by writing back the AES_KEYRx registers * as soon as the interrupted processing has to be resumed. * @retval None @@ -4859,11 +4857,11 @@ /** * @brief In case of message GCM/GMAC or CMAC processing resumption, rewrite the Key * Registers in the AES_KEYRx registers. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param Input: Pointer to the buffer containing the saved key registers to + * @param Input Pointer to the buffer containing the saved key registers to * write back in the CRYP hardware block. - * @param KeySize: Indicates the key size (128 or 256 bits) + * @param KeySize Indicates the key size (128 or 256 bits) * @retval None */ void HAL_CRYPEx_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint32_t KeySize) @@ -4894,9 +4892,9 @@ /** * @brief In case of message GCM/GMAC or CMAC processing suspension, read the Control Register. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param Output: Pointer to the buffer containing the saved Control Register. + * @param Output Pointer to the buffer containing the saved Control Register. * @note This values has to be stored for reuse by writing back the AES_CR register * as soon as the interrupted processing has to be resumed. * @retval None @@ -4909,9 +4907,9 @@ /** * @brief In case of message GCM/GMAC or CMAC processing resumption, rewrite the Control * Registers in the AES_CR register. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param Input: Pointer to the buffer containing the saved Control Register to + * @param Input Pointer to the buffer containing the saved Control Register to * write back in the CRYP hardware block. * @retval None */ @@ -4925,7 +4923,7 @@ /** * @brief Request CRYP processing suspension when in polling or interruption mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. * @note Set the handle field SuspendRequest to the appropriate value so that * the on-going CRYP processing is suspended as soon as the required @@ -4959,7 +4957,7 @@ * in the case of header phase where no output data DMA * transfer is on-going (only input data transfer is enabled * in such a case). - * @param hdma: DMA handle. + * @param hdma DMA handle. * @retval None */ static void CRYP_GCMCMAC_DMAInCplt(DMA_HandleTypeDef *hdma) @@ -5000,7 +4998,7 @@ * @brief DMA CRYP Output Data process complete callback * for GCM, GMAC or CMAC chainging modes. * @note This callback is called only in the payload phase. - * @param hdma: DMA handle. + * @param hdma DMA handle. * @retval None */ static void CRYP_GCMCMAC_DMAOutCplt(DMA_HandleTypeDef *hdma) @@ -5036,7 +5034,7 @@ /** * @brief DMA CRYP communication error callback * for GCM, GMAC or CMAC chainging modes. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void CRYP_GCMCMAC_DMAError(DMA_HandleTypeDef *hdma) @@ -5055,7 +5053,7 @@ * for GCM, GMAC or CMAC chaining modes. * @note The function is called under interruption only, once * interruptions have been enabled by HAL_CRYPEx_AES_Auth_IT(). - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval HAL status */ @@ -5511,11 +5509,11 @@ /** * @brief Set the DMA configuration and start the DMA transfer * for GCM, GMAC or CMAC chainging modes. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param inputaddr: Address of the Input buffer. - * @param Size: Size of the Input buffer un bytes, must be a multiple of 16. - * @param outputaddr: Address of the Output buffer, null pointer when no output DMA stream + * @param inputaddr Address of the Input buffer. + * @param Size Size of the Input buffer un bytes, must be a multiple of 16. + * @param outputaddr Address of the Output buffer, null pointer when no output DMA stream * has to be configured. * @retval None */ @@ -5557,12 +5555,12 @@ /** * @brief Write/read input/output data in polling mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param Input: Pointer to the Input buffer. - * @param Ilength: Length of the Input buffer in bytes, must be a multiple of 16. - * @param Output: Pointer to the returned buffer. - * @param Timeout: Specify Timeout value. + * @param Input Pointer to the Input buffer. + * @param Ilength Length of the Input buffer in bytes, must be a multiple of 16. + * @param Output Pointer to the returned buffer. + * @param Timeout Specify Timeout value. * @retval HAL status */ static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout) @@ -5633,10 +5631,10 @@ /** * @brief Read derivative key in polling mode when CRYP hardware block is set * in key derivation operating mode (mode 2). - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param Output: Pointer to the returned buffer. - * @param Timeout: Specify Timeout value. + * @param Output Pointer to the returned buffer. + * @param Timeout Specify Timeout value. * @retval HAL status */ static HAL_StatusTypeDef CRYP_ReadKey(CRYP_HandleTypeDef *hcryp, uint8_t* Output, uint32_t Timeout) @@ -5680,11 +5678,11 @@ /** * @brief Set the DMA configuration and start the DMA transfer. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param inputaddr: Address of the Input buffer. - * @param Size: Size of the Input buffer in bytes, must be a multiple of 16. - * @param outputaddr: Address of the Output buffer. + * @param inputaddr Address of the Input buffer. + * @param Size Size of the Input buffer in bytes, must be a multiple of 16. + * @param outputaddr Address of the Output buffer. * @retval None */ static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr) @@ -5714,9 +5712,9 @@ /** * @brief Handle CRYP hardware block Timeout when waiting for CCF flag to be raised. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param Timeout: Timeout duration. + * @param Timeout Timeout duration. * @retval HAL status */ static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) @@ -5742,9 +5740,9 @@ /** * @brief Wait for Busy Flag to be reset during a GCM payload encryption process suspension. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param Timeout: Timeout duration. + * @param Timeout Timeout duration. * @retval HAL status */ static HAL_StatusTypeDef CRYP_WaitOnBusyFlagReset(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) @@ -5770,7 +5768,7 @@ /** * @brief DMA CRYP Input Data process complete callback. - * @param hdma: DMA handle. + * @param hdma DMA handle. * @retval None */ static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma) @@ -5786,7 +5784,7 @@ /** * @brief DMA CRYP Output Data process complete callback. - * @param hdma: DMA handle. + * @param hdma DMA handle. * @retval None */ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) @@ -5811,7 +5809,7 @@ /** * @brief DMA CRYP communication error callback. - * @param hdma: DMA handle. + * @param hdma DMA handle. * @retval None */ static void CRYP_DMAError(DMA_HandleTypeDef *hdma) @@ -5827,10 +5825,10 @@ /** * @brief Last header or payload block padding when size is not a multiple of 128 bits. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param difflength: size remainder after having fed all complete 128-bit blocks. - * @param polling: specifies whether or not polling on CCF must be done after having + * @param difflength size remainder after having fed all complete 128-bit blocks. + * @param polling specifies whether or not polling on CCF must be done after having * entered a complete block. * @retval None */
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cryp_ex.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_cryp_ex.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_cryp_ex.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief Header file of CRYP HAL Extension module.
******************************************************************************
* @attention
@@ -100,8 +98,8 @@
/**
* @brief Set the phase: Init, header, payload, final.
* This is relevant only for GCM and CCM modes.
- * @param __HANDLE__: specifies the CRYP handle.
- * @param __PHASE__: The phase.
+ * @param __HANDLE__ specifies the CRYP handle.
+ * @param __PHASE__ The phase.
* @retval None
*/
#define __HAL_CRYP_SET_PHASE(__HANDLE__, __PHASE__) do{(__HANDLE__)->Instance->CR &= (uint32_t)(~CRYP_CR_GCM_CCMPH);\
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dac.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dac.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_dac.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief DAC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Digital to Analog Converter (DAC) peripheral: @@ -225,7 +223,7 @@ /** * @brief Initializes the DAC peripheral according to the specified parameters * in the DAC_InitStruct. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval HAL status */ @@ -262,7 +260,7 @@ /** * @brief Deinitializes the DAC peripheral registers to their default reset values. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval HAL status */ @@ -298,7 +296,7 @@ /** * @brief Initializes the DAC MSP. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -313,7 +311,7 @@ /** * @brief DeInitializes the DAC MSP. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -350,9 +348,9 @@ /** * @brief Enables DAC and starts conversion of channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected @@ -409,9 +407,9 @@ /** * @brief Disables DAC and stop conversion of channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected @@ -434,15 +432,15 @@ /** * @brief Enables DAC and starts conversion of channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @param pData: The destination peripheral Buffer address. - * @param Length: The length of data to be transferred from memory to DAC peripheral - * @param Alignment: Specifies the data alignment for DAC channel. + * @param pData The destination peripheral Buffer address. + * @param Length The length of data to be transferred from memory to DAC peripheral + * @param Alignment Specifies the data alignment for DAC channel. * This parameter can be one of the following values: * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected @@ -560,9 +558,9 @@ /** * @brief Disables DAC and stop conversion of channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected @@ -610,9 +608,9 @@ /** * @brief Returns the last data output value of the selected DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected @@ -636,7 +634,7 @@ /** * @brief Handles DAC interrupt request - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -682,7 +680,7 @@ /** * @brief Conversion complete callback in non blocking mode for Channel1 - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -697,7 +695,7 @@ /** * @brief Conversion half DMA transfer callback in non blocking mode for Channel1 - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -712,7 +710,7 @@ /** * @brief Error DAC callback for Channel1. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -727,7 +725,7 @@ /** * @brief DMA underrun DAC callback for channel1. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -761,10 +759,10 @@ /** * @brief Configures the selected DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param sConfig: DAC configuration structure. - * @param Channel: The selected DAC channel. + * @param sConfig DAC configuration structure. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected @@ -812,18 +810,18 @@ /** * @brief Set the specified data holding register value for DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @param Alignment: Specifies the data alignment. + * @param Alignment Specifies the data alignment. * This parameter can be one of the following values: * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected - * @param Data: Data to be loaded in the selected data holding register. + * @param Data Data to be loaded in the selected data holding register. * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data) @@ -874,7 +872,7 @@ /** * @brief return the DAC state - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval HAL state */ @@ -887,7 +885,7 @@ /** * @brief Return the DAC error code - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval DAC Error Code */ @@ -902,7 +900,7 @@ /** * @brief DMA conversion complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -917,7 +915,7 @@ /** * @brief DMA half transfer complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -930,7 +928,7 @@ /** * @brief DMA error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dac.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dac.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_dac.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief Header file of DAC HAL module.
******************************************************************************
* @attention
@@ -201,42 +199,42 @@
*/
/** @brief Reset DAC handle state
- * @param __HANDLE__: specifies the DAC handle.
+ * @param __HANDLE__ specifies the DAC handle.
* @retval None
*/
#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
/** @brief Enable the DAC channel
- * @param __HANDLE__: specifies the DAC handle.
- * @param __DAC_Channel__: specifies the DAC channel
+ * @param __HANDLE__ specifies the DAC handle.
+ * @param __DAC_Channel__ specifies the DAC channel
* @retval None
*/
#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_Channel__)))
/** @brief Disable the DAC channel
- * @param __HANDLE__: specifies the DAC handle
- * @param __DAC_Channel__: specifies the DAC channel.
+ * @param __HANDLE__ specifies the DAC handle
+ * @param __DAC_Channel__ specifies the DAC channel.
* @retval None
*/
#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_Channel__) ((__HANDLE__)->Instance->CR &= ~(DAC_CR_EN1 << (__DAC_Channel__)))
/** @brief Enable the DAC interrupt
- * @param __HANDLE__: specifies the DAC handle
- * @param __INTERRUPT__: specifies the DAC interrupt.
+ * @param __HANDLE__ specifies the DAC handle
+ * @param __INTERRUPT__ specifies the DAC interrupt.
* @retval None
*/
#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
/** @brief Disable the DAC interrupt
- * @param __HANDLE__: specifies the DAC handle
- * @param __INTERRUPT__: specifies the DAC interrupt.
+ * @param __HANDLE__ specifies the DAC handle
+ * @param __INTERRUPT__ specifies the DAC interrupt.
* @retval None
*/
#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
/** @brief Checks if the specified DAC interrupt source is enabled or disabled.
- * @param __HANDLE__: DAC handle
- * @param __INTERRUPT__: DAC interrupt source to check
+ * @param __HANDLE__ DAC handle
+ * @param __INTERRUPT__ DAC interrupt source to check
* This parameter can be any combination of the following values:
* @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
* @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
@@ -245,8 +243,8 @@
#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
/** @brief Get the selected DAC's flag status.
- * @param __HANDLE__: specifies the DAC handle.
- * @param __FLAG__: specifies the flag to clear.
+ * @param __HANDLE__ specifies the DAC handle.
+ * @param __FLAG__ specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag
* @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag
@@ -255,8 +253,8 @@
#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
/** @brief Clear the DAC's flag.
- * @param __HANDLE__: specifies the DAC handle.
- * @param __FLAG__: specifies the flag to clear.
+ * @param __HANDLE__ specifies the DAC handle.
+ * @param __FLAG__ specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag
* @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag
@@ -364,19 +362,19 @@
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
/** @brief Set DHR12R1 alignment
- * @param __ALIGNMENT__: specifies the DAC alignment
+ * @param __ALIGNMENT__ specifies the DAC alignment
* @retval None
*/
#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (0x00000008U + (__ALIGNMENT__))
/** @brief Set DHR12R2 alignment
- * @param __ALIGNMENT__: specifies the DAC alignment
+ * @param __ALIGNMENT__ specifies the DAC alignment
* @retval None
*/
#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014U) + (__ALIGNMENT__))
/** @brief Set DHR12RD alignment
- * @param __ALIGNMENT__: specifies the DAC alignment
+ * @param __ALIGNMENT__ specifies the DAC alignment
* @retval None
*/
#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (0x00000020U + (__ALIGNMENT__))
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dac_ex.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dac_ex.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_dac_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief DAC HAL module driver. * This file provides firmware functions to manage the following * functionalities of DAC extension peripheral: @@ -103,7 +101,7 @@ /** * @brief Returns the last data output value of the selected DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval The selected DAC channel data output value. */ @@ -121,12 +119,12 @@ /** * @brief Enables or disables the selected DAC channel wave generation. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * DAC_CHANNEL_1 / DAC_CHANNEL_2 - * @param Amplitude: Select max triangle amplitude. + * @param Amplitude Select max triangle amplitude. * This parameter can be one of the following values: * @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1 * @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3 @@ -169,12 +167,12 @@ /** * @brief Enables or disables the selected DAC channel wave generation. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * DAC_CHANNEL_1 / DAC_CHANNEL_2 - * @param Amplitude: Unmask DAC channel LFSR for noise wave generation. + * @param Amplitude Unmask DAC channel LFSR for noise wave generation. * This parameter can be one of the following values: * @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation * @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation @@ -217,15 +215,15 @@ /** * @brief Set the specified data holding register value for dual DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Alignment: Specifies the data alignment for dual channel DAC. + * @param Alignment Specifies the data alignment for dual channel DAC. * This parameter can be one of the following values: * DAC_ALIGN_8B_R: 8bit right data alignment selected * DAC_ALIGN_12B_L: 12bit left data alignment selected * DAC_ALIGN_12B_R: 12bit right data alignment selected - * @param Data1: Data for DAC Channel2 to be loaded in the selected data holding register. - * @param Data2: Data for DAC Channel1 to be loaded in the selected data holding register. + * @param Data1 Data for DAC Channel2 to be loaded in the selected data holding register. + * @param Data2 Data for DAC Channel1 to be loaded in the selected data holding register. * @note In dual mode, a unique register access is required to write in both * DAC channels at the same time. * @retval HAL status @@ -265,7 +263,7 @@ /** * @brief Conversion complete callback in non blocking mode for Channel2 - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -280,7 +278,7 @@ /** * @brief Conversion half DMA transfer callback in non blocking mode for Channel2 - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -295,7 +293,7 @@ /** * @brief Error DAC callback for Channel2. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -310,7 +308,7 @@ /** * @brief DMA underrun DAC callback for channel2. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -325,7 +323,7 @@ /** * @brief DMA conversion complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -340,7 +338,7 @@ /** * @brief DMA half transfer complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -353,7 +351,7 @@ /** * @brief DMA error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dac_ex.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dac_ex.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_dac.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of DAC HAL Extension module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dcmi.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dcmi.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_dcmi.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief DCMI HAL module driver * This file provides firmware functions to manage the following * functionalities of the Digital Camera Interface (DCMI) peripheral: @@ -139,7 +137,7 @@ /** * @brief Initializes the DCMI according to the specified * parameters in the DCMI_InitTypeDef and create the associated handle. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. * @retval HAL status */ @@ -205,7 +203,7 @@ /** * @brief Deinitializes the DCMI peripheral registers to their default reset * values. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. * @retval HAL status */ @@ -229,7 +227,7 @@ /** * @brief Initializes the DCMI MSP. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. * @retval None */ @@ -244,7 +242,7 @@ /** * @brief DeInitializes the DCMI MSP. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. * @retval None */ @@ -279,11 +277,11 @@ /** * @brief Enables DCMI DMA request and enables DCMI capture - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. - * @param DCMI_Mode: DCMI capture mode snapshot or continuous grab. - * @param pData: The destination memory Buffer address (LCD Frame buffer). - * @param Length: The length of capture to be transferred. + * @param DCMI_Mode DCMI capture mode snapshot or continuous grab. + * @param pData The destination memory Buffer address (LCD Frame buffer). + * @param Length The length of capture to be transferred. * @retval HAL status */ HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length) @@ -365,7 +363,7 @@ /** * @brief Disable DCMI DMA request and Disable DCMI capture - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. * @retval HAL status */ @@ -417,7 +415,7 @@ /** * @brief Suspend DCMI capture - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. * @retval HAL status */ @@ -463,7 +461,7 @@ /** * @brief Resume DCMI capture - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. * @retval HAL status */ @@ -489,7 +487,7 @@ /** * @brief Handles DCMI interrupt request. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for the DCMI. * @retval None */ @@ -571,7 +569,7 @@ /** * @brief Error DCMI callback. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. * @retval None */ @@ -586,7 +584,7 @@ /** * @brief Line Event callback. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. * @retval None */ @@ -601,7 +599,7 @@ /** * @brief VSYNC Event callback. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. * @retval None */ @@ -616,7 +614,7 @@ /** * @brief Frame Event callback. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. * @retval None */ @@ -650,12 +648,12 @@ /** * @brief Configure the DCMI CROP coordinate. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. - * @param X0: DCMI window X offset - * @param Y0: DCMI window Y offset - * @param XSize: DCMI Pixel per line - * @param YSize: DCMI Line number + * @param X0 DCMI window X offset + * @param Y0 DCMI window Y offset + * @param XSize DCMI Pixel per line + * @param YSize DCMI Line number * @retval HAL status */ HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize) @@ -687,7 +685,7 @@ /** * @brief Disable the Crop feature. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. * @retval HAL status */ @@ -713,7 +711,7 @@ /** * @brief Enable the Crop feature. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. * @retval HAL status */ @@ -759,7 +757,7 @@ /** * @brief Return the DCMI state - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. * @retval HAL state */ @@ -770,7 +768,7 @@ /** * @brief Return the DCMI error code - * @param hdcmi : pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. * @retval DCMI Error Code */ @@ -790,7 +788,7 @@ /** * @brief DMA conversion complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -847,7 +845,7 @@ /** * @brief DMA error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dcmi.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dcmi.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_dcmi.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief Header file of DCMI HAL module.
******************************************************************************
* @attention
@@ -233,8 +231,8 @@
/** @defgroup DCMI_Window_Vertical_Line DCMI Window Vertical Line
* @{
*/
-#define DCMI_POSITION_CWSIZE_VLINE (uint32_t)POSITION_VAL(DCMI_CWSIZE_VLINE) /*!< Required left shift to set crop window vertical line count */
-#define DCMI_POSITION_CWSTRT_VST (uint32_t)POSITION_VAL(DCMI_CWSTRT_VST) /*!< Required left shift to set crop window vertical start line count */
+#define DCMI_POSITION_CWSIZE_VLINE (uint32_t)DCMI_CWSIZE_VLINE_Pos /*!< Required left shift to set crop window vertical line count */
+#define DCMI_POSITION_CWSTRT_VST (uint32_t)DCMI_CWSTRT_VST_Pos /*!< Required left shift to set crop window vertical start line count */
/**
* @}
@@ -292,21 +290,21 @@
*/
/** @brief Reset DCMI handle state
- * @param __HANDLE__: specifies the DCMI handle.
+ * @param __HANDLE__ specifies the DCMI handle.
* @retval None
*/
#define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DCMI_STATE_RESET)
/**
* @brief Enable the DCMI.
- * @param __HANDLE__: DCMI handle
+ * @param __HANDLE__ DCMI handle
* @retval None
*/
#define __HAL_DCMI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DCMI_CR_ENABLE)
/**
* @brief Disable the DCMI.
- * @param __HANDLE__: DCMI handle
+ * @param __HANDLE__ DCMI handle
* @retval None
*/
#define __HAL_DCMI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(DCMI_CR_ENABLE))
@@ -314,8 +312,8 @@
/* Interrupt & Flag management */
/**
* @brief Get the DCMI pending flag.
- * @param __HANDLE__: DCMI handle
- * @param __FLAG__: Get the specified flag.
+ * @param __HANDLE__ DCMI handle
+ * @param __FLAG__ Get the specified flag.
* This parameter can be one of the following values (no combination allowed)
* @arg DCMI_FLAG_HSYNC: HSYNC pin state (active line / synchronization between lines)
* @arg DCMI_FLAG_VSYNC: VSYNC pin state (active frame / synchronization between frames)
@@ -338,8 +336,8 @@
/**
* @brief Clear the DCMI pending flags.
- * @param __HANDLE__: DCMI handle
- * @param __FLAG__: specifies the flag to clear.
+ * @param __HANDLE__ DCMI handle
+ * @param __FLAG__ specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask
* @arg DCMI_FLAG_OVRRI: Overrun flag mask
@@ -352,8 +350,8 @@
/**
* @brief Enable the specified DCMI interrupts.
- * @param __HANDLE__: DCMI handle
- * @param __INTERRUPT__: specifies the DCMI interrupt sources to be enabled.
+ * @param __HANDLE__ DCMI handle
+ * @param __INTERRUPT__ specifies the DCMI interrupt sources to be enabled.
* This parameter can be any combination of the following values:
* @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
* @arg DCMI_IT_OVR: Overrun interrupt mask
@@ -366,8 +364,8 @@
/**
* @brief Disable the specified DCMI interrupts.
- * @param __HANDLE__: DCMI handle
- * @param __INTERRUPT__: specifies the DCMI interrupt sources to be enabled.
+ * @param __HANDLE__ DCMI handle
+ * @param __INTERRUPT__ specifies the DCMI interrupt sources to be enabled.
* This parameter can be any combination of the following values:
* @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
* @arg DCMI_IT_OVR: Overrun interrupt mask
@@ -380,8 +378,8 @@
/**
* @brief Check whether the specified DCMI interrupt has occurred or not.
- * @param __HANDLE__: DCMI handle
- * @param __INTERRUPT__: specifies the DCMI interrupt source to check.
+ * @param __HANDLE__ DCMI handle
+ * @param __INTERRUPT__ specifies the DCMI interrupt source to check.
* This parameter can be one of the following values:
* @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
* @arg DCMI_IT_OVR: Overrun interrupt mask
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dcmi_ex.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dcmi_ex.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_dcmi_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief DCMI Extension HAL module driver * This file provides firmware functions to manage the following * functionalities of DCMI extension peripheral: @@ -91,7 +89,7 @@ /** * @brief Initializes the DCMI according to the specified * parameters in the DCMI_InitTypeDef and create the associated handle. - * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains + * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains * the configuration information for DCMI. * @retval HAL status */
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dcmi_ex.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dcmi_ex.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_dcmi_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of DCMI Extension HAL module. ****************************************************************************** * @attention @@ -180,9 +178,9 @@ /* Private types -------------------------------------------------------------*/ /* Private variables ---------------------------------------------------------*/ /* Private constants ---------------------------------------------------------*/ -#define DCMI_POSITION_ESCR_LSC (uint32_t)POSITION_VAL(DCMI_ESCR_LSC) /*!< Required left shift to set line start delimiter */ -#define DCMI_POSITION_ESCR_LEC (uint32_t)POSITION_VAL(DCMI_ESCR_LEC) /*!< Required left shift to set line end delimiter */ -#define DCMI_POSITION_ESCR_FEC (uint32_t)POSITION_VAL(DCMI_ESCR_FEC) /*!< Required left shift to set frame end delimiter */ +#define DCMI_POSITION_ESCR_LSC (uint32_t)DCMI_ESCR_LSC_Pos /*!< Required left shift to set line start delimiter */ +#define DCMI_POSITION_ESCR_LEC (uint32_t)DCMI_ESCR_LEC_Pos /*!< Required left shift to set line end delimiter */ +#define DCMI_POSITION_ESCR_FEC (uint32_t)DCMI_ESCR_FEC_Pos /*!< Required left shift to set frame end delimiter */ /* Private macro -------------------------------------------------------------*/ #if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_def.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_def.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_def.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief This file contains HAL common defines, enumeration, macros and
* structures definitions.
******************************************************************************
@@ -46,7 +44,9 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx.h"
+/* MBED */
#include "stm32_hal_legacy.h"
+/* MBED */
#include <stdio.h>
/* Exported types ------------------------------------------------------------*/
@@ -86,7 +86,7 @@
#define UNUSED(x) ((void)(x))
/** @brief Reset the Handle's State field.
- * @param __HANDLE__: specifies the Peripheral Handle.
+ * @param __HANDLE__ specifies the Peripheral Handle.
* @note This macro can be used for the following purpose:
* - When the Handle is declared as local variable; before passing it as parameter
* to HAL_PPP_Init() for the first time, it is mandatory to use this macro
@@ -122,6 +122,8 @@
do{ \
(__HANDLE__)->Lock = HAL_UNLOCKED; \
}while (0U)
+
+/* MBED */
#if defined (__CC_ARM)
#pragma diag_suppress 3731
#endif
@@ -143,10 +145,11 @@
} while (__STREXW(newValue, ptr));
}
+/* MBED */
#endif /* USE_RTOS */
-#if defined ( __GNUC__ ) && !defined ( __CC_ARM )
+#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
#ifndef __weak
#define __weak __attribute__((weak))
#endif /* __weak */
@@ -157,7 +160,7 @@
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
-#if defined (__GNUC__) /* GNU Compiler */
+#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4)))
#endif /* __ALIGN_END */
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dfsdm.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dfsdm.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_dfsdm.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief This file provides firmware functions to manage the following
* functionalities of the Digital Filter for Sigma-Delta Modulators
* (DFSDM) peripherals:
@@ -206,27 +204,9 @@
/** @defgroup DFSDM_Private_Define DFSDM Private Define
* @{
*/
-#define DFSDM_CHCFGR1_CLK_DIV_OFFSET POSITION_VAL(DFSDM_CHCFGR1_CKOUTDIV)
-#define DFSDM_CHAWSCDR_BKSCD_OFFSET POSITION_VAL(DFSDM_CHAWSCDR_BKSCD)
-#define DFSDM_CHAWSCDR_FOSR_OFFSET POSITION_VAL(DFSDM_CHAWSCDR_AWFOSR)
-#define DFSDM_CHCFGR2_OFFSET_OFFSET POSITION_VAL(DFSDM_CHCFGR2_OFFSET)
-#define DFSDM_CHCFGR2_DTRBS_OFFSET POSITION_VAL(DFSDM_CHCFGR2_DTRBS)
-#define DFSDM_FLTFCR_FOSR_OFFSET POSITION_VAL(DFSDM_FLTFCR_FOSR)
+
#define DFSDM_FLTCR1_MSB_RCH_OFFSET 8U
-#define DFSDM_FLTCR2_EXCH_OFFSET POSITION_VAL(DFSDM_FLTCR2_EXCH)
-#define DFSDM_FLTCR2_AWDCH_OFFSET POSITION_VAL(DFSDM_FLTCR2_AWDCH)
-#define DFSDM_FLTISR_CKABF_OFFSET POSITION_VAL(DFSDM_FLTISR_CKABF)
-#define DFSDM_FLTISR_SCDF_OFFSET POSITION_VAL(DFSDM_FLTISR_SCDF)
-#define DFSDM_FLTICR_CLRCKABF_OFFSET POSITION_VAL(DFSDM_FLTICR_CLRCKABF)
-#define DFSDM_FLTICR_CLRSCDF_OFFSET POSITION_VAL(DFSDM_FLTICR_CLRSCSDF)
-#define DFSDM_FLTRDATAR_DATA_OFFSET POSITION_VAL(DFSDM_FLTRDATAR_RDATA)
-#define DFSDM_FLTJDATAR_DATA_OFFSET POSITION_VAL(DFSDM_FLTJDATAR_JDATA)
-#define DFSDM_FLTAWHTR_THRESHOLD_OFFSET POSITION_VAL(DFSDM_FLTAWHTR_AWHT)
-#define DFSDM_FLTAWLTR_THRESHOLD_OFFSET POSITION_VAL(DFSDM_FLTAWLTR_AWLT)
-#define DFSDM_FLTEXMAX_DATA_OFFSET POSITION_VAL(DFSDM_FLTEXMAX_EXMAX)
-#define DFSDM_FLTEXMIN_DATA_OFFSET POSITION_VAL(DFSDM_FLTEXMIN_EXMIN)
-#define DFSDM_FLTCNVTIMR_DATA_OFFSET POSITION_VAL(DFSDM_FLTCNVTIMR_CNVCNT)
-#define DFSDM_FLTAWSR_HIGH_OFFSET POSITION_VAL(DFSDM_FLTAWSR_AWHTF)
+
#define DFSDM_MSB_MASK 0xFFFF0000U
#define DFSDM_LSB_MASK 0x0000FFFFU
#define DFSDM_CKAB_TIMEOUT 5000U
@@ -303,7 +283,7 @@
/**
* @brief Initialize the DFSDM channel according to the specified parameters
* in the DFSDM_ChannelInitTypeDef structure and initialize the associated handle.
- * @param hdfsdm_channel : DFSDM channel handle.
+ * @param hdfsdm_channel DFSDM channel handle.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
@@ -375,7 +355,7 @@
assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(hdfsdm_channel->Init.OutputClock.Divider));
/* Set the output clock divider */
channel0Instance->CHCFGR1 |= (uint32_t) ((hdfsdm_channel->Init.OutputClock.Divider - 1U) <<
- DFSDM_CHCFGR1_CLK_DIV_OFFSET);
+ DFSDM_CHCFGR1_CKOUTDIV_Pos);
}
/* enable the DFSDM global interface */
@@ -397,12 +377,12 @@
/* Set analog watchdog parameters */
hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_AWFORD | DFSDM_CHAWSCDR_AWFOSR);
hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder |
- ((hdfsdm_channel->Init.Awd.Oversampling - 1U) << DFSDM_CHAWSCDR_FOSR_OFFSET));
+ ((hdfsdm_channel->Init.Awd.Oversampling - 1U) << DFSDM_CHAWSCDR_AWFOSR_Pos));
/* Set channel offset and right bit shift */
hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET | DFSDM_CHCFGR2_DTRBS);
- hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_OFFSET) |
- (hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_OFFSET));
+ hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_Pos) |
+ (hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_Pos));
/* Enable DFSDM channel */
hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CHEN;
@@ -441,7 +421,7 @@
assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(hdfsdm_channel->Init.OutputClock.Divider));
/* Set the output clock divider */
DFSDM1_Channel0->CHCFGR1 |= (uint32_t) ((hdfsdm_channel->Init.OutputClock.Divider - 1U) <<
- DFSDM_CHCFGR1_CLK_DIV_OFFSET);
+ DFSDM_CHCFGR1_CKOUTDIV_Pos);
}
/* enable the DFSDM global interface */
@@ -463,12 +443,12 @@
/* Set analog watchdog parameters */
hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_AWFORD | DFSDM_CHAWSCDR_AWFOSR);
hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder |
- ((hdfsdm_channel->Init.Awd.Oversampling - 1U) << DFSDM_CHAWSCDR_FOSR_OFFSET));
+ ((hdfsdm_channel->Init.Awd.Oversampling - 1U) << DFSDM_CHAWSCDR_AWFOSR_Pos));
/* Set channel offset and right bit shift */
hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET | DFSDM_CHCFGR2_DTRBS);
- hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_OFFSET) |
- (hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_OFFSET));
+ hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_Pos) |
+ (hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_Pos));
/* Enable DFSDM channel */
hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CHEN;
@@ -485,7 +465,7 @@
/**
* @brief De-initialize the DFSDM channel.
- * @param hdfsdm_channel : DFSDM channel handle.
+ * @param hdfsdm_channel DFSDM channel handle.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
@@ -580,7 +560,7 @@
/**
* @brief Initialize the DFSDM channel MSP.
- * @param hdfsdm_channel : DFSDM channel handle.
+ * @param hdfsdm_channel DFSDM channel handle.
* @retval None
*/
__weak void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
@@ -594,7 +574,7 @@
/**
* @brief De-initialize the DFSDM channel MSP.
- * @param hdfsdm_channel : DFSDM channel handle.
+ * @param hdfsdm_channel DFSDM channel handle.
* @retval None
*/
__weak void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
@@ -632,7 +612,7 @@
* @note If clock is not available on this channel during 5 seconds,
* clock absence detection will not be activated and function
* will return HAL_TIMEOUT error.
- * @param hdfsdm_channel : DFSDM channel handle.
+ * @param hdfsdm_channel DFSDM channel handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
@@ -673,9 +653,9 @@
tickstart = HAL_GetTick();
/* Clear clock absence flag */
- while((((filter0Instance->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1U) != 0U)
+ while((((filter0Instance->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) != 0U)
{
- filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
+ filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
/* Check the Timeout */
if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT)
@@ -693,9 +673,9 @@
tickstart = HAL_GetTick();
/* Clear clock absence flag */
- while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1U) != 0U)
+ while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) != 0U)
{
- DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
+ DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
/* Check the Timeout */
if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT)
@@ -719,8 +699,8 @@
/**
* @brief This function allows to poll for the clock absence detection.
- * @param hdfsdm_channel : DFSDM channel handle.
- * @param Timeout : Timeout value in milliseconds.
+ * @param hdfsdm_channel DFSDM channel handle.
+ * @param Timeout Timeout value in milliseconds.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
@@ -762,7 +742,7 @@
tickstart = HAL_GetTick();
/* Wait clock absence detection */
- while((((filter0Instance->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1U) == 0U)
+ while((((filter0Instance->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) == 0U)
{
/* Check the Timeout */
if(Timeout != HAL_MAX_DELAY)
@@ -776,7 +756,7 @@
}
/* Clear clock absence detection flag */
- filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
+ filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
#else
/* Get channel number from channel instance */
channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
@@ -785,7 +765,7 @@
tickstart = HAL_GetTick();
/* Wait clock absence detection */
- while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1U) == 0U)
+ while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) == 0U)
{
/* Check the Timeout */
if(Timeout != HAL_MAX_DELAY)
@@ -799,7 +779,7 @@
}
/* Clear clock absence detection flag */
- DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
+ DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
#endif /* defined(DFSDM2_Channel0) */
/* Return function status */
return HAL_OK;
@@ -808,7 +788,7 @@
/**
* @brief This function allows to stop clock absence detection in polling mode.
- * @param hdfsdm_channel : DFSDM channel handle.
+ * @param hdfsdm_channel DFSDM channel handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
@@ -847,7 +827,7 @@
/* Clear clock absence flag */
channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
- filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
+ filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
#else
/* Stop clock absence detection */
@@ -855,7 +835,7 @@
/* Clear clock absence flag */
channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
- DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
+ DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
#endif /* DFSDM2_Channel0 */
}
/* Return function status */
@@ -868,7 +848,7 @@
* @note If clock is not available on this channel during 5 seconds,
* clock absence detection will not be activated and function
* will return HAL_TIMEOUT error.
- * @param hdfsdm_channel : DFSDM channel handle.
+ * @param hdfsdm_channel DFSDM channel handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
@@ -910,9 +890,9 @@
tickstart = HAL_GetTick();
/* Clear clock absence flag */
- while((((filter0Instance->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1U) != 0U)
+ while((((filter0Instance->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) != 0U)
{
- filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
+ filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
/* Check the Timeout */
if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT)
@@ -939,9 +919,9 @@
tickstart = HAL_GetTick();
/* Clear clock absence flag */
- while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1U) != 0U)
+ while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1U) != 0U)
{
- DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
+ DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
/* Check the Timeout */
if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT)
@@ -969,7 +949,7 @@
/**
* @brief Clock absence detection callback.
- * @param hdfsdm_channel : DFSDM channel handle.
+ * @param hdfsdm_channel DFSDM channel handle.
* @retval None
*/
__weak void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
@@ -984,7 +964,7 @@
/**
* @brief This function allows to stop clock absence detection in interrupt mode.
* @note Interrupt will be disabled for all channels
- * @param hdfsdm_channel : DFSDM channel handle.
+ * @param hdfsdm_channel DFSDM channel handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
@@ -1023,7 +1003,7 @@
/* Clear clock absence flag */
channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
- filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
+ filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
/* Disable clock absence detection interrupt */
filter0Instance->FLTCR2 &= ~(DFSDM_FLTCR2_CKABIE);
@@ -1034,7 +1014,7 @@
/* Clear clock absence flag */
channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
- DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
+ DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
/* Disable clock absence detection interrupt */
DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_CKABIE);
@@ -1048,10 +1028,10 @@
/**
* @brief This function allows to start short circuit detection in polling mode.
* @note Same mode has to be used for all channels
- * @param hdfsdm_channel : DFSDM channel handle.
- * @param Threshold : Short circuit detector threshold.
+ * @param hdfsdm_channel DFSDM channel handle.
+ * @param Threshold Short circuit detector threshold.
* This parameter must be a number between Min_Data = 0 and Max_Data = 255.
- * @param BreakSignal : Break signals assigned to short circuit event.
+ * @param BreakSignal Break signals assigned to short circuit event.
* This parameter can be a values combination of @ref DFSDM_BreakSignals.
* @retval HAL status
*/
@@ -1076,7 +1056,7 @@
{
/* Configure threshold and break signals */
hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT);
- hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_OFFSET) | \
+ hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_Pos) | \
Threshold);
/* Start short circuit detection */
@@ -1088,8 +1068,8 @@
/**
* @brief This function allows to poll for the short circuit detection.
- * @param hdfsdm_channel : DFSDM channel handle.
- * @param Timeout : Timeout value in milliseconds.
+ * @param hdfsdm_channel DFSDM channel handle.
+ * @param Timeout Timeout value in milliseconds.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
@@ -1130,7 +1110,7 @@
tickstart = HAL_GetTick();
/* Wait short circuit detection */
- while(((filter0Instance->FLTISR & DFSDM_FLTISR_SCDF) >> (DFSDM_FLTISR_SCDF_OFFSET + channel)) == 0U)
+ while(((filter0Instance->FLTISR & DFSDM_FLTISR_SCDF) >> (DFSDM_FLTISR_SCDF_Pos + channel)) == 0U)
{
/* Check the Timeout */
if(Timeout != HAL_MAX_DELAY)
@@ -1144,14 +1124,14 @@
}
/* Clear short circuit detection flag */
- filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel));
+ filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCSDF_Pos + channel));
#else
/* Get timeout */
tickstart = HAL_GetTick();
/* Wait short circuit detection */
- while(((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_SCDF) >> (DFSDM_FLTISR_SCDF_OFFSET + channel)) == 0U)
+ while(((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_SCDF) >> (DFSDM_FLTISR_SCDF_Pos + channel)) == 0U)
{
/* Check the Timeout */
if(Timeout != HAL_MAX_DELAY)
@@ -1165,7 +1145,7 @@
}
/* Clear short circuit detection flag */
- DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel));
+ DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRSCSDF_Pos + channel));
#endif /* DFSDM2_Channel0 */
/* Return function status */
@@ -1175,7 +1155,7 @@
/**
* @brief This function allows to stop short circuit detection in polling mode.
- * @param hdfsdm_channel : DFSDM channel handle.
+ * @param hdfsdm_channel DFSDM channel handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
@@ -1214,9 +1194,9 @@
filter0Instance = DFSDM2_Filter0;
}
- filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel));
+ filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCSDF_Pos + channel));
#else
- DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel));
+ DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRSCSDF_Pos + channel));
#endif /* DFSDM2_Channel0*/
}
/* Return function status */
@@ -1226,10 +1206,10 @@
/**
* @brief This function allows to start short circuit detection in interrupt mode.
* @note Same mode has to be used for all channels
- * @param hdfsdm_channel : DFSDM channel handle.
- * @param Threshold : Short circuit detector threshold.
+ * @param hdfsdm_channel DFSDM channel handle.
+ * @param Threshold Short circuit detector threshold.
* This parameter must be a number between Min_Data = 0 and Max_Data = 255.
- * @param BreakSignal : Break signals assigned to short circuit event.
+ * @param BreakSignal Break signals assigned to short circuit event.
* This parameter can be a values combination of @ref DFSDM_BreakSignals.
* @retval HAL status
*/
@@ -1274,7 +1254,7 @@
/* Configure threshold and break signals */
hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT);
- hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_OFFSET) | \
+ hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_Pos) | \
Threshold);
/* Start short circuit detection */
@@ -1286,7 +1266,7 @@
/**
* @brief Short circuit detection callback.
- * @param hdfsdm_channel : DFSDM channel handle.
+ * @param hdfsdm_channel DFSDM channel handle.
* @retval None
*/
__weak void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
@@ -1301,7 +1281,7 @@
/**
* @brief This function allows to stop short circuit detection in interrupt mode.
* @note Interrupt will be disabled for all channels
- * @param hdfsdm_channel : DFSDM channel handle.
+ * @param hdfsdm_channel DFSDM channel handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
@@ -1339,12 +1319,12 @@
filter0Instance = DFSDM2_Filter0;
}
- filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel));
+ filter0Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCSDF_Pos + channel));
/* Disable short circuit detection interrupt */
filter0Instance->FLTCR2 &= ~(DFSDM_FLTCR2_SCDIE);
#else
- DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel));
+ DFSDM1_Filter0->FLTICR = (1U << (DFSDM_FLTICR_CLRSCSDF_Pos + channel));
/* Disable short circuit detection interrupt */
DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_SCDIE);
@@ -1356,7 +1336,7 @@
/**
* @brief This function allows to get channel analog watchdog value.
- * @param hdfsdm_channel : DFSDM channel handle.
+ * @param hdfsdm_channel DFSDM channel handle.
* @retval Channel analog watchdog value.
*/
int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
@@ -1366,8 +1346,8 @@
/**
* @brief This function allows to modify channel offset value.
- * @param hdfsdm_channel : DFSDM channel handle.
- * @param Offset : DFSDM channel offset.
+ * @param hdfsdm_channel DFSDM channel handle.
+ * @param Offset DFSDM channel offset.
* This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607.
* @retval HAL status.
*/
@@ -1390,7 +1370,7 @@
{
/* Modify channel offset */
hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET);
- hdfsdm_channel->Instance->CHCFGR2 |= ((uint32_t) Offset << DFSDM_CHCFGR2_OFFSET_OFFSET);
+ hdfsdm_channel->Instance->CHCFGR2 |= ((uint32_t) Offset << DFSDM_CHCFGR2_OFFSET_Pos);
}
/* Return function status */
return status;
@@ -1415,7 +1395,7 @@
/**
* @brief This function allows to get the current DFSDM channel handle state.
- * @param hdfsdm_channel : DFSDM channel handle.
+ * @param hdfsdm_channel DFSDM channel handle.
* @retval DFSDM channel state.
*/
HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
@@ -1445,7 +1425,7 @@
/**
* @brief Initialize the DFSDM filter according to the specified parameters
* in the DFSDM_FilterInitTypeDef structure and initialize the associated handle.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@@ -1543,7 +1523,7 @@
/* Set filter parameters */
hdfsdm_filter->Instance->FLTFCR &= ~(DFSDM_FLTFCR_FORD | DFSDM_FLTFCR_FOSR | DFSDM_FLTFCR_IOSR);
hdfsdm_filter->Instance->FLTFCR |= (hdfsdm_filter->Init.FilterParam.SincOrder |
- ((hdfsdm_filter->Init.FilterParam.Oversampling - 1U) << DFSDM_FLTFCR_FOSR_OFFSET) |
+ ((hdfsdm_filter->Init.FilterParam.Oversampling - 1U) << DFSDM_FLTFCR_FOSR_Pos) |
(hdfsdm_filter->Init.FilterParam.IntOversampling - 1U));
/* Store regular and injected triggers and injected scan mode*/
@@ -1563,7 +1543,7 @@
/**
* @brief De-initializes the DFSDM filter.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@@ -1591,7 +1571,7 @@
/**
* @brief Initializes the DFSDM filter MSP.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval None
*/
__weak void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@@ -1605,7 +1585,7 @@
/**
* @brief De-initializes the DFSDM filter MSP.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval None
*/
__weak void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@@ -1638,10 +1618,10 @@
/**
* @brief This function allows to select channel and to enable/disable
* continuous mode for regular conversion.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @param Channel : Channel for regular conversion.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @param Channel Channel for regular conversion.
* This parameter can be a value of @ref DFSDM_Channel_Selection.
- * @param ContinuousMode : Enable/disable continuous mode for regular conversion.
+ * @param ContinuousMode Enable/disable continuous mode for regular conversion.
* This parameter can be a value of @ref DFSDM_ContinuousMode.
* @retval HAL status
*/
@@ -1685,8 +1665,8 @@
/**
* @brief This function allows to select channels for injected conversion.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @param Channel : Channels for injected conversion.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @param Channel Channels for injected conversion.
* This parameter can be a values combination of @ref DFSDM_Channel_Selection.
* @retval HAL status
*/
@@ -1757,7 +1737,7 @@
* @brief This function allows to start regular conversion in polling mode.
* @note This function should be called only when DFSDM filter instance is
* in idle state or if injected conversion is ongoing.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@@ -1785,8 +1765,8 @@
/**
* @brief This function allows to poll for the end of regular conversion.
* @note This function should be called only if regular conversion is ongoing.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @param Timeout : Timeout value in milliseconds.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @param Timeout Timeout value in milliseconds.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
@@ -1847,7 +1827,7 @@
/**
* @brief This function allows to stop regular conversion in polling mode.
* @note This function should be called only if regular conversion is ongoing.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@@ -1877,7 +1857,7 @@
* @brief This function allows to start regular conversion in interrupt mode.
* @note This function should be called only when DFSDM filter instance is
* in idle state or if injected conversion is ongoing.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@@ -1908,7 +1888,7 @@
/**
* @brief This function allows to stop regular conversion in interrupt mode.
* @note This function should be called only if regular conversion is ongoing.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@@ -1944,9 +1924,9 @@
* Please note that data on buffer will contain signed regular conversion
* value on 24 most significant bits and corresponding channel on 3 least
* significant bits.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @param pData : The destination buffer address.
- * @param Length : The length of data to be transferred from DFSDM filter to memory.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @param pData The destination buffer address.
+ * @param Length The length of data to be transferred from DFSDM filter to memory.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
@@ -2021,9 +2001,9 @@
* in idle state or if injected conversion is ongoing.
* Please note that data on buffer will contain signed 16 most significant
* bits of regular conversion.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @param pData : The destination buffer address.
- * @param Length : The length of data to be transferred from DFSDM filter to memory.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @param pData The destination buffer address.
+ * @param Length The length of data to be transferred from DFSDM filter to memory.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
@@ -2094,7 +2074,7 @@
/**
* @brief This function allows to stop regular conversion in DMA mode.
* @note This function should be called only if regular conversion is ongoing.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@@ -2132,8 +2112,8 @@
/**
* @brief This function allows to get regular conversion value.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @param Channel : Corresponding channel of regular conversion.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @param Channel Corresponding channel of regular conversion.
* @retval Regular conversion value
*/
int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
@@ -2151,7 +2131,7 @@
/* Extract channel and regular conversion value */
*Channel = (reg & DFSDM_FLTRDATAR_RDATACH);
- value = ((int32_t)(reg & DFSDM_FLTRDATAR_RDATA) >> DFSDM_FLTRDATAR_DATA_OFFSET);
+ value = ((int32_t)(reg & DFSDM_FLTRDATAR_RDATA) >> DFSDM_FLTRDATAR_RDATA_Pos);
/* return regular conversion value */
return value;
@@ -2161,7 +2141,7 @@
* @brief This function allows to start injected conversion in polling mode.
* @note This function should be called only when DFSDM filter instance is
* in idle state or if regular conversion is ongoing.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@@ -2189,8 +2169,8 @@
/**
* @brief This function allows to poll for the end of injected conversion.
* @note This function should be called only if injected conversion is ongoing.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @param Timeout : Timeout value in milliseconds.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @param Timeout Timeout value in milliseconds.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
@@ -2261,7 +2241,7 @@
/**
* @brief This function allows to stop injected conversion in polling mode.
* @note This function should be called only if injected conversion is ongoing.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@@ -2291,7 +2271,7 @@
* @brief This function allows to start injected conversion in interrupt mode.
* @note This function should be called only when DFSDM filter instance is
* in idle state or if regular conversion is ongoing.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@@ -2322,7 +2302,7 @@
/**
* @brief This function allows to stop injected conversion in interrupt mode.
* @note This function should be called only if injected conversion is ongoing.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@@ -2358,9 +2338,9 @@
* Please note that data on buffer will contain signed injected conversion
* value on 24 most significant bits and corresponding channel on 3 least
* significant bits.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @param pData : The destination buffer address.
- * @param Length : The length of data to be transferred from DFSDM filter to memory.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @param pData The destination buffer address.
+ * @param Length The length of data to be transferred from DFSDM filter to memory.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
@@ -2433,9 +2413,9 @@
* in idle state or if regular conversion is ongoing.
* Please note that data on buffer will contain signed 16 most significant
* bits of injected conversion.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @param pData : The destination buffer address.
- * @param Length : The length of data to be transferred from DFSDM filter to memory.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @param pData The destination buffer address.
+ * @param Length The length of data to be transferred from DFSDM filter to memory.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
@@ -2504,7 +2484,7 @@
/**
* @brief This function allows to stop injected conversion in DMA mode.
* @note This function should be called only if injected conversion is ongoing.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@@ -2542,8 +2522,8 @@
/**
* @brief This function allows to get injected conversion value.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @param Channel : Corresponding channel of injected conversion.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @param Channel Corresponding channel of injected conversion.
* @retval Injected conversion value
*/
int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
@@ -2561,7 +2541,7 @@
/* Extract channel and injected conversion value */
*Channel = (reg & DFSDM_FLTJDATAR_JDATACH);
- value = ((int32_t)(reg & DFSDM_FLTJDATAR_JDATA) >> DFSDM_FLTJDATAR_DATA_OFFSET);
+ value = ((int32_t)(reg & DFSDM_FLTJDATAR_JDATA) >> DFSDM_FLTJDATAR_JDATA_Pos);
/* return regular conversion value */
return value;
@@ -2569,8 +2549,8 @@
/**
* @brief This function allows to start filter analog watchdog in interrupt mode.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @param awdParam : DFSDM filter analog watchdog parameters.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @param awdParam DFSDM filter analog watchdog parameters.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
@@ -2602,15 +2582,15 @@
/* Set thresholds and break signals */
hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH);
- hdfsdm_filter->Instance->FLTAWHTR |= (((uint32_t) awdParam->HighThreshold << DFSDM_FLTAWHTR_THRESHOLD_OFFSET) | \
+ hdfsdm_filter->Instance->FLTAWHTR |= (((uint32_t) awdParam->HighThreshold << DFSDM_FLTAWHTR_AWHT_Pos) | \
awdParam->HighBreakSignal);
hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL);
- hdfsdm_filter->Instance->FLTAWLTR |= (((uint32_t) awdParam->LowThreshold << DFSDM_FLTAWLTR_THRESHOLD_OFFSET) | \
+ hdfsdm_filter->Instance->FLTAWLTR |= (((uint32_t) awdParam->LowThreshold << DFSDM_FLTAWLTR_AWLT_Pos) | \
awdParam->LowBreakSignal);
/* Set channels and interrupt for analog watchdog */
hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_AWDCH);
- hdfsdm_filter->Instance->FLTCR2 |= (((awdParam->Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_AWDCH_OFFSET) | \
+ hdfsdm_filter->Instance->FLTCR2 |= (((awdParam->Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_AWDCH_Pos) | \
DFSDM_FLTCR2_AWDIE);
}
/* Return function status */
@@ -2619,7 +2599,7 @@
/**
* @brief This function allows to stop filter analog watchdog in interrupt mode.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@@ -2657,8 +2637,8 @@
/**
* @brief This function allows to start extreme detector feature.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @param Channel : Channels where extreme detector is enabled.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @param Channel Channels where extreme detector is enabled.
* This parameter can be a values combination of @ref DFSDM_Channel_Selection.
* @retval HAL status
*/
@@ -2682,7 +2662,7 @@
{
/* Set channels for extreme detector */
hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_EXCH);
- hdfsdm_filter->Instance->FLTCR2 |= ((Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_EXCH_OFFSET);
+ hdfsdm_filter->Instance->FLTCR2 |= ((Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_EXCH_Pos);
}
/* Return function status */
return status;
@@ -2690,7 +2670,7 @@
/**
* @brief This function allows to stop extreme detector feature.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@@ -2726,8 +2706,8 @@
/**
* @brief This function allows to get extreme detector maximum value.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @param Channel : Corresponding channel.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @param Channel Corresponding channel.
* @retval Extreme detector maximum value
* This value is between Min_Data = -8388608 and Max_Data = 8388607.
*/
@@ -2746,7 +2726,7 @@
/* Extract channel and extreme detector maximum value */
*Channel = (reg & DFSDM_FLTEXMAX_EXMAXCH);
- value = ((int32_t)(reg & DFSDM_FLTEXMAX_EXMAX) >> DFSDM_FLTEXMAX_DATA_OFFSET);
+ value = ((int32_t)(reg & DFSDM_FLTEXMAX_EXMAX) >> DFSDM_FLTEXMAX_EXMAX_Pos);
/* return extreme detector maximum value */
return value;
@@ -2754,8 +2734,8 @@
/**
* @brief This function allows to get extreme detector minimum value.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @param Channel : Corresponding channel.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @param Channel Corresponding channel.
* @retval Extreme detector minimum value
* This value is between Min_Data = -8388608 and Max_Data = 8388607.
*/
@@ -2774,7 +2754,7 @@
/* Extract channel and extreme detector minimum value */
*Channel = (reg & DFSDM_FLTEXMIN_EXMINCH);
- value = ((int32_t)(reg & DFSDM_FLTEXMIN_EXMIN) >> DFSDM_FLTEXMIN_DATA_OFFSET);
+ value = ((int32_t)(reg & DFSDM_FLTEXMIN_EXMIN) >> DFSDM_FLTEXMIN_EXMIN_Pos);
/* return extreme detector minimum value */
return value;
@@ -2782,7 +2762,7 @@
/**
* @brief This function allows to get conversion time value.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval Conversion time value
* @note To get time in second, this value has to be divided by DFSDM clock frequency.
*/
@@ -2798,7 +2778,7 @@
reg = hdfsdm_filter->Instance->FLTCNVTIMR;
/* Extract conversion time value */
- value = ((reg & DFSDM_FLTCNVTIMR_CNVCNT) >> DFSDM_FLTCNVTIMR_DATA_OFFSET);
+ value = ((reg & DFSDM_FLTCNVTIMR_CNVCNT) >> DFSDM_FLTCNVTIMR_CNVCNT_Pos);
/* return extreme detector minimum value */
return value;
@@ -2806,7 +2786,7 @@
/**
* @brief This function handles the DFSDM interrupts.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval None
*/
void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@@ -2895,7 +2875,7 @@
threshold = ((reg & DFSDM_FLTAWSR_AWLTF) != 0U) ? DFSDM_AWD_LOW_THRESHOLD : DFSDM_AWD_HIGH_THRESHOLD;
if(threshold == DFSDM_AWD_HIGH_THRESHOLD)
{
- reg = reg >> DFSDM_FLTAWSR_HIGH_OFFSET;
+ reg = reg >> DFSDM_FLTAWSR_AWHTF_Pos;
}
while((reg & 1U) == 0U)
{
@@ -2904,7 +2884,7 @@
}
/* Clear analog watchdog flag */
hdfsdm_filter->Instance->FLTAWCFR = (threshold == DFSDM_AWD_HIGH_THRESHOLD) ? \
- (1U << (DFSDM_FLTAWSR_HIGH_OFFSET + channel)) : \
+ (1U << (DFSDM_FLTAWSR_AWHTF_Pos + channel)) : \
(1U << channel);
/* Call analog watchdog callback */
@@ -2918,7 +2898,7 @@
uint32_t reg = 0U;
uint32_t channel = 0U;
- reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) >> DFSDM_FLTISR_CKABF_OFFSET);
+ reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) >> DFSDM_FLTISR_CKABF_Pos);
while(channel < DFSDM1_CHANNEL_NUMBER)
{
@@ -2929,7 +2909,7 @@
if((a_dfsdm1ChannelHandle[channel]->Instance->CHCFGR1 & DFSDM_CHCFGR1_CKABEN) != 0U)
{
/* Clear clock absence flag */
- hdfsdm_filter->Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
+ hdfsdm_filter->Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
/* Call clock absence callback */
HAL_DFSDM_ChannelCkabCallback(a_dfsdm1ChannelHandle[channel]);
@@ -2948,7 +2928,7 @@
uint32_t reg = 0U;
uint32_t channel = 0U;
- reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) >> DFSDM_FLTISR_CKABF_OFFSET);
+ reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) >> DFSDM_FLTISR_CKABF_Pos);
while(channel < DFSDM2_CHANNEL_NUMBER)
{
@@ -2959,7 +2939,7 @@
if((a_dfsdm2ChannelHandle[channel]->Instance->CHCFGR1 & DFSDM_CHCFGR1_CKABEN) != 0U)
{
/* Clear clock absence flag */
- hdfsdm_filter->Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
+ hdfsdm_filter->Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
/* Call clock absence callback */
HAL_DFSDM_ChannelCkabCallback(a_dfsdm2ChannelHandle[channel]);
@@ -2979,7 +2959,7 @@
uint32_t channel = 0U;
/* Get channel */
- reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) >> DFSDM_FLTISR_SCDF_OFFSET);
+ reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) >> DFSDM_FLTISR_SCDF_Pos);
while((reg & 1U) == 0U)
{
channel++;
@@ -2987,7 +2967,7 @@
}
/* Clear short circuit detection flag */
- hdfsdm_filter->Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel));
+ hdfsdm_filter->Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCSDF_Pos + channel));
/* Call short circuit detection callback */
HAL_DFSDM_ChannelScdCallback(a_dfsdm1ChannelHandle[channel]);
@@ -3002,7 +2982,7 @@
uint32_t channel = 0U;
/* Get channel */
- reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) >> DFSDM_FLTISR_SCDF_OFFSET);
+ reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) >> DFSDM_FLTISR_SCDF_Pos);
while((reg & 1U) == 0U)
{
channel++;
@@ -3010,7 +2990,7 @@
}
/* Clear short circuit detection flag */
- hdfsdm_filter->Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel));
+ hdfsdm_filter->Instance->FLTICR = (1U << (DFSDM_FLTICR_CLRSCSDF_Pos + channel));
/* Call short circuit detection callback */
HAL_DFSDM_ChannelScdCallback(a_dfsdm2ChannelHandle[channel]);
@@ -3022,7 +3002,7 @@
* @brief Regular conversion complete callback.
* @note In interrupt mode, user has to read conversion value in this function
* using HAL_DFSDM_FilterGetRegularValue.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval None
*/
__weak void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@@ -3036,7 +3016,7 @@
/**
* @brief Half regular conversion complete callback.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval None
*/
__weak void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@@ -3052,7 +3032,7 @@
* @brief Injected conversion complete callback.
* @note In interrupt mode, user has to read conversion value in this function
* using HAL_DFSDM_FilterGetInjectedValue.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval None
*/
__weak void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@@ -3066,7 +3046,7 @@
/**
* @brief Half injected conversion complete callback.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval None
*/
__weak void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@@ -3080,9 +3060,9 @@
/**
* @brief Filter analog watchdog callback.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @param Channel : Corresponding channel.
- * @param Threshold : Low or high threshold has been reached.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @param Channel Corresponding channel.
+ * @param Threshold Low or high threshold has been reached.
* @retval None
*/
__weak void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
@@ -3100,7 +3080,7 @@
/**
* @brief Error callback.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval None
*/
__weak void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@@ -3132,7 +3112,7 @@
/**
* @brief This function allows to get the current DFSDM filter handle state.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval DFSDM filter state.
*/
HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@@ -3143,7 +3123,7 @@
/**
* @brief This function allows to get the current DFSDM filter error.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval DFSDM filter error code.
*/
uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@@ -3201,8 +3181,8 @@
/**
* @brief Disable Delay Clock for DFSDM1/2.
- * @param MCHDLY: HAL_MCHDLY_CLOCK_DFSDM2.
- * HAL_MCHDLY_CLOCK_DFSDM1.
+ * @param MCHDLY HAL_MCHDLY_CLOCK_DFSDM2.
+ * HAL_MCHDLY_CLOCK_DFSDM1.
* @note The SYSCFG clock marco __HAL_RCC_SYSCFG_CLK_ENABLE() must be called
* before HAL_DFSDM_DisableDelayClock()
* @retval None
@@ -3228,8 +3208,8 @@
/**
* @brief Enable Delay Clock for DFSDM1/2.
- * @param MCHDLY: HAL_MCHDLY_CLOCK_DFSDM2.
- * HAL_MCHDLY_CLOCK_DFSDM1.
+ * @param MCHDLY HAL_MCHDLY_CLOCK_DFSDM2.
+ * HAL_MCHDLY_CLOCK_DFSDM1.
* @note The SYSCFG clock marco __HAL_RCC_SYSCFG_CLK_ENABLE() must be called
* before HAL_DFSDM_EnableDelayClock()
* @retval None
@@ -3248,10 +3228,10 @@
/**
* @brief Select the source for CKin signals for DFSDM1/2.
- * @param source: DFSDM2_CKIN_PAD.
- * DFSDM2_CKIN_DM.
- * DFSDM1_CKIN_PAD.
- * DFSDM1_CKIN_DM.
+ * @param source DFSDM2_CKIN_PAD.
+ * DFSDM2_CKIN_DM.
+ * DFSDM1_CKIN_PAD.
+ * DFSDM1_CKIN_DM.
* @retval None
*/
void HAL_DFSDM_ClockIn_SourceSelection(uint32_t source)
@@ -3284,7 +3264,7 @@
* @param source: DFSDM2_CKOUT_DFSDM2.
* DFSDM2_CKOUT_M27.
* DFSDM1_CKOUT_DFSDM1.
- * DFSDM1_CKOUT_M27.
+ * DFSDM1_CKOUT_M27.
* @retval None
*/
void HAL_DFSDM_ClockOut_SourceSelection(uint32_t source)
@@ -3314,10 +3294,10 @@
/**
* @brief Select the source for DataIn0 signals for DFSDM1/2.
- * @param source: DATAIN0_DFSDM2_PAD.
- * DATAIN0_DFSDM2_DATAIN1.
- * DATAIN0_DFSDM1_PAD.
- * DATAIN0_DFSDM1_DATAIN1.
+ * @param source DATAIN0_DFSDM2_PAD.
+ * DATAIN0_DFSDM2_DATAIN1.
+ * DATAIN0_DFSDM1_PAD.
+ * DATAIN0_DFSDM1_DATAIN1.
* @retval None
*/
void HAL_DFSDM_DataIn0_SourceSelection(uint32_t source)
@@ -3345,10 +3325,10 @@
/**
* @brief Select the source for DataIn2 signals for DFSDM1/2.
- * @param source: DATAIN2_DFSDM2_PAD.
- * DATAIN2_DFSDM2_DATAIN3.
- * DATAIN2_DFSDM1_PAD.
- * DATAIN2_DFSDM1_DATAIN3.
+ * @param source DATAIN2_DFSDM2_PAD.
+ * DATAIN2_DFSDM2_DATAIN3.
+ * DATAIN2_DFSDM1_PAD.
+ * DATAIN2_DFSDM1_DATAIN3.
* @retval None
*/
void HAL_DFSDM_DataIn2_SourceSelection(uint32_t source)
@@ -3376,8 +3356,8 @@
/**
* @brief Select the source for DataIn4 signals for DFSDM2.
- * @param source: DATAIN4_DFSDM2_PAD.
- * DATAIN4_DFSDM2_DATAIN5
+ * @param source DATAIN4_DFSDM2_PAD.
+ * DATAIN4_DFSDM2_DATAIN5
* @retval None
*/
void HAL_DFSDM_DataIn4_SourceSelection(uint32_t source)
@@ -3394,8 +3374,8 @@
/**
* @brief Select the source for DataIn6 signals for DFSDM2.
- * @param source: DATAIN6_DFSDM2_PAD.
- * DATAIN6_DFSDM2_DATAIN7.
+ * @param source DATAIN6_DFSDM2_PAD.
+ * DATAIN6_DFSDM2_DATAIN7.
* @retval None
*/
void HAL_DFSDM_DataIn6_SourceSelection(uint32_t source)
@@ -3414,18 +3394,18 @@
/**
* @brief Configure the distribution of the bitstream clock gated from TIM4_OC
* for DFSDM1 or TIM3_OC for DFSDM2
- * @param source: DFSDM1_CLKIN0_TIM4OC2
- * DFSDM1_CLKIN2_TIM4OC2
- * DFSDM1_CLKIN1_TIM4OC1
- * DFSDM1_CLKIN3_TIM4OC1
- * DFSDM2_CLKIN0_TIM3OC4
- * DFSDM2_CLKIN4_TIM3OC4
- * DFSDM2_CLKIN1_TIM3OC3
- * DFSDM2_CLKIN5_TIM3OC3
- * DFSDM2_CLKIN2_TIM3OC2
- * DFSDM2_CLKIN6_TIM3OC2
- * DFSDM2_CLKIN3_TIM3OC1
- * DFSDM2_CLKIN7_TIM3OC1
+ * @param source DFSDM1_CLKIN0_TIM4OC2
+ * DFSDM1_CLKIN2_TIM4OC2
+ * DFSDM1_CLKIN1_TIM4OC1
+ * DFSDM1_CLKIN3_TIM4OC1
+ * DFSDM2_CLKIN0_TIM3OC4
+ * DFSDM2_CLKIN4_TIM3OC4
+ * DFSDM2_CLKIN1_TIM3OC3
+ * DFSDM2_CLKIN5_TIM3OC3
+ * DFSDM2_CLKIN2_TIM3OC2
+ * DFSDM2_CLKIN6_TIM3OC2
+ * DFSDM2_CLKIN3_TIM3OC1
+ * DFSDM2_CLKIN7_TIM3OC1
* @retval None
*/
void HAL_DFSDM_BitStreamClkDistribution_Config(uint32_t source)
@@ -3479,7 +3459,7 @@
* or demuxes: M1, M2, M3, M4, M5, M6, M7, M8, DM1, DM2, DM3, DM4, DM5, DM6,
* M9, M10, M11, M12, M13, M14, M15, M16, M17, M18, M19, M20 based on the
* contains of the DFSDM_MultiChannelConfigTypeDef structure
- * @param mchdlystruct: Structure of multi channel configuration
+ * @param mchdlystruct Structure of multi channel configuration
* @retval None
* @note The SYSCFG clock marco __HAL_RCC_SYSCFG_CLK_ENABLE() must be called
* before HAL_DFSDM_ConfigMultiChannelDelay()
@@ -3523,7 +3503,7 @@
/**
* @brief DMA half transfer complete callback for regular conversion.
- * @param hdma : DMA handle.
+ * @param hdma DMA handle.
* @retval None
*/
static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma)
@@ -3537,7 +3517,7 @@
/**
* @brief DMA transfer complete callback for regular conversion.
- * @param hdma : DMA handle.
+ * @param hdma DMA handle.
* @retval None
*/
static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma)
@@ -3551,7 +3531,7 @@
/**
* @brief DMA half transfer complete callback for injected conversion.
- * @param hdma : DMA handle.
+ * @param hdma DMA handle.
* @retval None
*/
static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma)
@@ -3565,7 +3545,7 @@
/**
* @brief DMA transfer complete callback for injected conversion.
- * @param hdma : DMA handle.
+ * @param hdma DMA handle.
* @retval None
*/
static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma)
@@ -3579,7 +3559,7 @@
/**
* @brief DMA error callback.
- * @param hdma : DMA handle.
+ * @param hdma DMA handle.
* @retval None
*/
static void DFSDM_DMAError(DMA_HandleTypeDef *hdma)
@@ -3596,7 +3576,7 @@
/**
* @brief This function allows to get the number of injected channels.
- * @param Channels : bitfield of injected channels.
+ * @param Channels bitfield of injected channels.
* @retval Number of injected channels.
*/
static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels)
@@ -3619,7 +3599,7 @@
/**
* @brief This function allows to get the channel number from channel instance.
- * @param Instance : DFSDM channel instance.
+ * @param Instance DFSDM channel instance.
* @retval Channel number.
*/
static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance)
@@ -3684,7 +3664,7 @@
/**
* @brief This function allows to really start regular conversion.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval None
*/
static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
@@ -3725,7 +3705,7 @@
/**
* @brief This function allows to really stop regular conversion.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval None
*/
static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
@@ -3761,7 +3741,7 @@
/**
* @brief This function allows to really start injected conversion.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval None
*/
static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
@@ -3805,7 +3785,7 @@
/**
* @brief This function allows to really stop injected conversion.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval None
*/
static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dfsdm.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dfsdm.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_dfsdm.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of DFSDM HAL module. ****************************************************************************** * @attention @@ -692,13 +690,13 @@ */ /** @brief Reset DFSDM channel handle state. - * @param __HANDLE__: DFSDM channel handle. + * @param __HANDLE__ DFSDM channel handle. * @retval None */ #define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET) /** @brief Reset DFSDM filter handle state. - * @param __HANDLE__: DFSDM filter handle. + * @param __HANDLE__ DFSDM filter handle. * @retval None */ #define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET)
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_dma.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief DMA HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -182,7 +180,7 @@
/**
* @brief Initialize the DMA according to the specified
* parameters in the DMA_InitTypeDef and create the associated handle.
- * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval HAL status
*/
@@ -321,7 +319,7 @@
/**
* @brief DeInitializes the DMA peripheral
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval HAL status
*/
@@ -408,11 +406,11 @@
/**
* @brief Starts the DMA Transfer.
- * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
- * @param SrcAddress: The source memory Buffer address
- * @param DstAddress: The destination memory Buffer address
- * @param DataLength: The length of data to be transferred from source to destination
+ * @param SrcAddress The source memory Buffer address
+ * @param DstAddress The destination memory Buffer address
+ * @param DataLength The length of data to be transferred from source to destination
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
@@ -452,11 +450,11 @@
/**
* @brief Start the DMA Transfer with interrupt enabled.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
- * @param SrcAddress: The source memory Buffer address
- * @param DstAddress: The destination memory Buffer address
- * @param DataLength: The length of data to be transferred from source to destination
+ * @param SrcAddress The source memory Buffer address
+ * @param DstAddress The destination memory Buffer address
+ * @param DataLength The length of data to be transferred from source to destination
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
@@ -512,7 +510,7 @@
/**
* @brief Aborts the DMA Transfer.
- * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
*
* @note After disabling a DMA Stream, a check for wait until the DMA Stream is
@@ -585,7 +583,7 @@
/**
* @brief Aborts the DMA Transfer in Interrupt mode.
- * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval HAL status
*/
@@ -610,13 +608,13 @@
/**
* @brief Polling for transfer complete.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
- * @param CompleteLevel: Specifies the DMA level complete.
+ * @param CompleteLevel Specifies the DMA level complete.
* @note The polling mode is kept in this version for legacy. it is recommanded to use the IT model instead.
* This model could be used for debug purpose.
* @note The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode).
- * @param Timeout: Timeout duration.
+ * @param Timeout Timeout duration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
@@ -708,7 +706,6 @@
/* Clear the Direct Mode error flag */
regs->IFCR = DMA_FLAG_DMEIF0_4 << hdma->StreamIndex;
}
- tmpisr = regs->ISR;
}
if(hdma->ErrorCode != HAL_DMA_ERROR_NONE)
@@ -752,7 +749,7 @@
/**
* @brief Handles DMA interrupt request.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval None
*/
@@ -969,11 +966,11 @@
/**
* @brief Register callbacks
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
- * @param CallbackID: User Callback identifer
+ * @param CallbackID User Callback identifer
* a DMA_HandleTypeDef structure as parameter.
- * @param pCallback: pointer to private callbacsk function which has pointer to
+ * @param pCallback pointer to private callbacsk function which has pointer to
* a DMA_HandleTypeDef structure as parameter.
* @retval HAL status
*/
@@ -1031,9 +1028,9 @@
/**
* @brief UnRegister callbacks
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
- * @param CallbackID: User Callback identifer
+ * @param CallbackID User Callback identifer
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
* @retval HAL status
*/
@@ -1118,7 +1115,7 @@
/**
* @brief Returns the DMA state.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval HAL state
*/
@@ -1129,7 +1126,7 @@
/**
* @brief Return the DMA error code
- * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval DMA Error Code
*/
@@ -1152,11 +1149,11 @@
/**
* @brief Sets the DMA Transfer parameter.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
- * @param SrcAddress: The source memory Buffer address
- * @param DstAddress: The destination memory Buffer address
- * @param DataLength: The length of data to be transferred from source to destination
+ * @param SrcAddress The source memory Buffer address
+ * @param DstAddress The destination memory Buffer address
+ * @param DataLength The length of data to be transferred from source to destination
* @retval HAL status
*/
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
@@ -1167,7 +1164,7 @@
/* Configure DMA Stream data length */
hdma->Instance->NDTR = DataLength;
- /* Peripheral to Memory */
+ /* Memory to Peripheral */
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
{
/* Configure DMA Stream destination address */
@@ -1176,7 +1173,7 @@
/* Configure DMA Stream source address */
hdma->Instance->M0AR = SrcAddress;
}
- /* Memory to Peripheral */
+ /* Peripheral to Memory */
else
{
/* Configure DMA Stream source address */
@@ -1189,7 +1186,7 @@
/**
* @brief Returns the DMA Stream base address depending on stream number
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval Stream base address
*/
@@ -1217,7 +1214,7 @@
/**
* @brief Check compatibility between FIFO threshold level and size of the memory burst
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval HAL status
*/
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_dma.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief Header file of DMA HAL module.
******************************************************************************
* @attention
@@ -378,8 +376,8 @@
* @brief DMA flag definitions
* @{
*/
-#define DMA_FLAG_FEIF0_4 0x00800001U
-#define DMA_FLAG_DMEIF0_4 0x00800004U
+#define DMA_FLAG_FEIF0_4 0x00000001U
+#define DMA_FLAG_DMEIF0_4 0x00000004U
#define DMA_FLAG_TEIF0_4 0x00000008U
#define DMA_FLAG_HTIF0_4 0x00000010U
#define DMA_FLAG_TCIF0_4 0x00000020U
@@ -409,14 +407,14 @@
/* Exported macro ------------------------------------------------------------*/
/** @brief Reset DMA handle state
- * @param __HANDLE__: specifies the DMA handle.
+ * @param __HANDLE__ specifies the DMA handle.
* @retval None
*/
#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
/**
* @brief Return the current DMA Stream FIFO filled level.
- * @param __HANDLE__: DMA handle
+ * @param __HANDLE__ DMA handle
* @retval The FIFO filling state.
* - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
* and not empty.
@@ -430,14 +428,14 @@
/**
* @brief Enable the specified DMA Stream.
- * @param __HANDLE__: DMA handle
+ * @param __HANDLE__ DMA handle
* @retval None
*/
#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN)
/**
* @brief Disable the specified DMA Stream.
- * @param __HANDLE__: DMA handle
+ * @param __HANDLE__ DMA handle
* @retval None
*/
#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)
@@ -446,7 +444,7 @@
/**
* @brief Return the current DMA Stream transfer complete flag.
- * @param __HANDLE__: DMA handle
+ * @param __HANDLE__ DMA handle
* @retval The specified transfer complete flag index.
*/
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
@@ -466,7 +464,7 @@
/**
* @brief Return the current DMA Stream half transfer complete flag.
- * @param __HANDLE__: DMA handle
+ * @param __HANDLE__ DMA handle
* @retval The specified half transfer complete flag index.
*/
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
@@ -486,7 +484,7 @@
/**
* @brief Return the current DMA Stream transfer error flag.
- * @param __HANDLE__: DMA handle
+ * @param __HANDLE__ DMA handle
* @retval The specified transfer error flag index.
*/
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
@@ -506,7 +504,7 @@
/**
* @brief Return the current DMA Stream FIFO error flag.
- * @param __HANDLE__: DMA handle
+ * @param __HANDLE__ DMA handle
* @retval The specified FIFO error flag index.
*/
#define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
@@ -526,7 +524,7 @@
/**
* @brief Return the current DMA Stream direct mode error flag.
- * @param __HANDLE__: DMA handle
+ * @param __HANDLE__ DMA handle
* @retval The specified direct mode error flag index.
*/
#define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
@@ -546,8 +544,8 @@
/**
* @brief Get the DMA Stream pending flags.
- * @param __HANDLE__: DMA handle
- * @param __FLAG__: Get the specified flag.
+ * @param __HANDLE__ DMA handle
+ * @param __FLAG__ Get the specified flag.
* This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCIFx: Transfer complete flag.
* @arg DMA_FLAG_HTIFx: Half transfer complete flag.
@@ -564,8 +562,8 @@
/**
* @brief Clear the DMA Stream pending flags.
- * @param __HANDLE__: DMA handle
- * @param __FLAG__: specifies the flag to clear.
+ * @param __HANDLE__ DMA handle
+ * @param __FLAG__ specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCIFx: Transfer complete flag.
* @arg DMA_FLAG_HTIFx: Half transfer complete flag.
@@ -582,8 +580,8 @@
/**
* @brief Enable the specified DMA Stream interrupts.
- * @param __HANDLE__: DMA handle
- * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
+ * @param __HANDLE__ DMA handle
+ * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg DMA_IT_TC: Transfer complete interrupt mask.
* @arg DMA_IT_HT: Half transfer complete interrupt mask.
@@ -597,8 +595,8 @@
/**
* @brief Disable the specified DMA Stream interrupts.
- * @param __HANDLE__: DMA handle
- * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
+ * @param __HANDLE__ DMA handle
+ * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg DMA_IT_TC: Transfer complete interrupt mask.
* @arg DMA_IT_HT: Half transfer complete interrupt mask.
@@ -612,8 +610,8 @@
/**
* @brief Check whether the specified DMA Stream interrupt is enabled or disabled.
- * @param __HANDLE__: DMA handle
- * @param __INTERRUPT__: specifies the DMA interrupt source to check.
+ * @param __HANDLE__ DMA handle
+ * @param __INTERRUPT__ specifies the DMA interrupt source to check.
* This parameter can be one of the following values:
* @arg DMA_IT_TC: Transfer complete interrupt mask.
* @arg DMA_IT_HT: Half transfer complete interrupt mask.
@@ -628,8 +626,8 @@
/**
* @brief Writes the number of data units to be transferred on the DMA Stream.
- * @param __HANDLE__: DMA handle
- * @param __COUNTER__: Number of data units to be transferred (from 0 to 65535)
+ * @param __HANDLE__ DMA handle
+ * @param __COUNTER__ Number of data units to be transferred (from 0 to 65535)
* Number of data items depends only on the Peripheral data format.
*
* @note If Peripheral data format is Bytes: number of data units is equal
@@ -647,7 +645,7 @@
/**
* @brief Returns the number of remaining data units in the current DMAy Streamx transfer.
- * @param __HANDLE__: DMA handle
+ * @param __HANDLE__ DMA handle
*
* @retval The number of remaining data units in the current DMA Stream transfer.
*/
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma2d.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma2d.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_dma2d.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief DMA2D HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the DMA2D peripheral:
@@ -159,21 +157,21 @@
/** @defgroup DMA2D_Shifts DMA2D Shifts
* @{
*/
-#define DMA2D_POSITION_FGPFCCR_CS (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CS) /*!< Required left shift to set foreground CLUT size */
-#define DMA2D_POSITION_BGPFCCR_CS (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_CS) /*!< Required left shift to set background CLUT size */
+#define DMA2D_POSITION_FGPFCCR_CS (uint32_t)DMA2D_FGPFCCR_CS_Pos /*!< Required left shift to set foreground CLUT size */
+#define DMA2D_POSITION_BGPFCCR_CS (uint32_t)DMA2D_BGPFCCR_CS_Pos /*!< Required left shift to set background CLUT size */
-#define DMA2D_POSITION_FGPFCCR_CCM (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CCM) /*!< Required left shift to set foreground CLUT color mode */
-#define DMA2D_POSITION_BGPFCCR_CCM (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_CCM) /*!< Required left shift to set background CLUT color mode */
+#define DMA2D_POSITION_FGPFCCR_CCM (uint32_t)DMA2D_FGPFCCR_CCM_Pos /*!< Required left shift to set foreground CLUT color mode */
+#define DMA2D_POSITION_BGPFCCR_CCM (uint32_t)DMA2D_BGPFCCR_CCM_Pos /*!< Required left shift to set background CLUT color mode */
-#define DMA2D_POSITION_AMTCR_DT (uint32_t)POSITION_VAL(DMA2D_AMTCR_DT) /*!< Required left shift to set deadtime value */
+#define DMA2D_POSITION_AMTCR_DT (uint32_t)DMA2D_AMTCR_DT_Pos /*!< Required left shift to set deadtime value */
-#define DMA2D_POSITION_FGPFCCR_AM (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_AM) /*!< Required left shift to set foreground alpha mode */
-#define DMA2D_POSITION_BGPFCCR_AM (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_AM) /*!< Required left shift to set background alpha mode */
+#define DMA2D_POSITION_FGPFCCR_AM (uint32_t)DMA2D_FGPFCCR_AM_Pos /*!< Required left shift to set foreground alpha mode */
+#define DMA2D_POSITION_BGPFCCR_AM (uint32_t)DMA2D_BGPFCCR_AM_Pos /*!< Required left shift to set background alpha mode */
-#define DMA2D_POSITION_FGPFCCR_ALPHA (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_ALPHA) /*!< Required left shift to set foreground alpha value */
-#define DMA2D_POSITION_BGPFCCR_ALPHA (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_ALPHA) /*!< Required left shift to set background alpha value */
+#define DMA2D_POSITION_FGPFCCR_ALPHA (uint32_t)DMA2D_FGPFCCR_ALPHA_Pos /*!< Required left shift to set foreground alpha value */
+#define DMA2D_POSITION_BGPFCCR_ALPHA (uint32_t)DMA2D_BGPFCCR_ALPHA_Pos /*!< Required left shift to set background alpha value */
-#define DMA2D_POSITION_NLR_PL (uint32_t)POSITION_VAL(DMA2D_NLR_PL) /*!< Required left shift to set pixels per lines value */
+#define DMA2D_POSITION_NLR_PL (uint32_t)DMA2D_NLR_PL_Pos /*!< Required left shift to set pixels per lines value */
/**
* @}
*/
@@ -218,7 +216,7 @@
/**
* @brief Initialize the DMA2D according to the specified
* parameters in the DMA2D_InitTypeDef and create the associated handle.
- * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @retval HAL status
*/
@@ -268,7 +266,7 @@
/**
* @brief Deinitializes the DMA2D peripheral registers to their default reset
* values.
- * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @retval None
*/
@@ -345,7 +343,7 @@
/**
* @brief Initializes the DMA2D MSP.
- * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @retval None
*/
@@ -361,7 +359,7 @@
/**
* @brief DeInitializes the DMA2D MSP.
- * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @retval None
*/
@@ -415,15 +413,15 @@
/**
* @brief Start the DMA2D Transfer.
- * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
- * @param pdata: Configure the source memory Buffer address if
+ * @param pdata Configure the source memory Buffer address if
* Memory-to-Memory or Memory-to-Memory with pixel format
* conversion mode is selected, or configure
* the color value if Register-to-Memory mode is selected.
- * @param DstAddress: The destination memory Buffer address.
- * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line).
- * @param Height: The height of data to be transferred from source to destination (expressed in number of lines).
+ * @param DstAddress The destination memory Buffer address.
+ * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line).
+ * @param Height The height of data to be transferred from source to destination (expressed in number of lines).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
@@ -449,15 +447,15 @@
/**
* @brief Start the DMA2D Transfer with interrupt enabled.
- * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
- * @param pdata: Configure the source memory Buffer address if
+ * @param pdata Configure the source memory Buffer address if
* the Memory-to-Memory or Memory-to-Memory with pixel format
* conversion mode is selected, or configure
* the color value if Register-to-Memory mode is selected.
- * @param DstAddress: The destination memory Buffer address.
- * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line).
- * @param Height: The height of data to be transferred from source to destination (expressed in number of lines).
+ * @param DstAddress The destination memory Buffer address.
+ * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line).
+ * @param Height The height of data to be transferred from source to destination (expressed in number of lines).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
@@ -486,13 +484,13 @@
/**
* @brief Start the multi-source DMA2D Transfer.
- * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
- * @param SrcAddress1: The source memory Buffer address for the foreground layer.
- * @param SrcAddress2: The source memory Buffer address for the background layer.
- * @param DstAddress: The destination memory Buffer address.
- * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line).
- * @param Height: The height of data to be transferred from source to destination (expressed in number of lines).
+ * @param SrcAddress1 The source memory Buffer address for the foreground layer.
+ * @param SrcAddress2 The source memory Buffer address for the background layer.
+ * @param DstAddress The destination memory Buffer address.
+ * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line).
+ * @param Height The height of data to be transferred from source to destination (expressed in number of lines).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
@@ -521,13 +519,13 @@
/**
* @brief Start the multi-source DMA2D Transfer with interrupt enabled.
- * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
- * @param SrcAddress1: The source memory Buffer address for the foreground layer.
- * @param SrcAddress2: The source memory Buffer address for the background layer.
- * @param DstAddress: The destination memory Buffer address.
- * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line).
- * @param Height: The height of data to be transferred from source to destination (expressed in number of lines).
+ * @param SrcAddress1 The source memory Buffer address for the foreground layer.
+ * @param SrcAddress2 The source memory Buffer address for the background layer.
+ * @param DstAddress The destination memory Buffer address.
+ * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line).
+ * @param Height The height of data to be transferred from source to destination (expressed in number of lines).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
@@ -559,7 +557,7 @@
/**
* @brief Abort the DMA2D Transfer.
- * @param hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @retval HAL status
*/
@@ -608,7 +606,7 @@
/**
* @brief Suspend the DMA2D Transfer.
- * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @retval HAL status
*/
@@ -658,7 +656,7 @@
/**
* @brief Resume the DMA2D Transfer.
- * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @retval HAL status
*/
@@ -682,9 +680,9 @@
/**
* @brief Enable the DMA2D CLUT Transfer.
- * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
- * @param LayerIdx: DMA2D Layer index.
+ * @param LayerIdx DMA2D Layer index.
* This parameter can be one of the following values:
* 0(background) / 1(foreground)
* @retval HAL status
@@ -716,11 +714,11 @@
/**
* @brief Start DMA2D CLUT Loading.
- * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
- * @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
+ * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
* the configuration information for the color look up table.
- * @param LayerIdx: DMA2D Layer index.
+ * @param LayerIdx DMA2D Layer index.
* This parameter can be one of the following values:
* 0(background) / 1(foreground)
* @note Invoking this API is similar to calling HAL_DMA2D_ConfigCLUT() then HAL_DMA2D_EnableCLUT().
@@ -771,11 +769,11 @@
/**
* @brief Start DMA2D CLUT Loading with interrupt enabled.
- * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
- * @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
+ * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
* the configuration information for the color look up table.
- * @param LayerIdx: DMA2D Layer index.
+ * @param LayerIdx DMA2D Layer index.
* This parameter can be one of the following values:
* 0(background) / 1(foreground)
* @retval HAL status
@@ -831,9 +829,9 @@
/**
* @brief Abort the DMA2D CLUT loading.
- * @param hdma2d : Pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
- * @param LayerIdx: DMA2D Layer index.
+ * @param LayerIdx DMA2D Layer index.
* This parameter can be one of the following values:
* 0(background) / 1(foreground)
* @retval HAL status
@@ -887,9 +885,9 @@
/**
* @brief Suspend the DMA2D CLUT loading.
- * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
- * @param LayerIdx: DMA2D Layer index.
+ * @param LayerIdx DMA2D Layer index.
* This parameter can be one of the following values:
* 0(background) / 1(foreground)
* @retval HAL status
@@ -944,9 +942,9 @@
/**
* @brief Resume the DMA2D CLUT loading.
- * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
- * @param LayerIdx: DMA2D Layer index.
+ * @param LayerIdx DMA2D Layer index.
* This parameter can be one of the following values:
* 0(background) / 1(foreground)
* @retval HAL status
@@ -983,9 +981,9 @@
/**
* @brief Polling for transfer complete or CLUT loading.
- * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
- * @param Timeout: Timeout duration
+ * @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
@@ -1110,7 +1108,7 @@
}
/**
* @brief Handle DMA2D interrupt request.
- * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @retval HAL status
*/
@@ -1270,7 +1268,7 @@
/**
* @brief Transfer watermark callback.
- * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @retval None
*/
@@ -1286,7 +1284,7 @@
/**
* @brief CLUT Transfer Complete callback.
- * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @retval None
*/
@@ -1325,9 +1323,9 @@
/**
* @brief Configure the DMA2D Layer according to the specified
* parameters in the DMA2D_InitTypeDef and create the associated handle.
- * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
- * @param LayerIdx: DMA2D Layer index.
+ * @param LayerIdx DMA2D Layer index.
* This parameter can be one of the following values:
* 0(background) / 1(foreground)
* @retval HAL status
@@ -1408,11 +1406,11 @@
/**
* @brief Configure the DMA2D CLUT Transfer.
- * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
- * @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
+ * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
* the configuration information for the color look up table.
- * @param LayerIdx: DMA2D Layer index.
+ * @param LayerIdx DMA2D Layer index.
* This parameter can be one of the following values:
* 0(background) / 1(foreground)
* @retval HAL status
@@ -1462,9 +1460,9 @@
/**
* @brief Configure the line watermark.
- * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
- * @param Line: Line Watermark configuration (maximum 16-bit long value expected).
+ * @param Line Line Watermark configuration (maximum 16-bit long value expected).
* @note HAL_DMA2D_ProgramLineEvent() API enables the transfer watermark interrupt.
* @note The transfer watermark interrupt is disabled once it has occurred.
* @retval HAL status
@@ -1505,7 +1503,7 @@
/**
* @brief Enable DMA2D dead time feature.
- * @param hdma2d: DMA2D handle.
+ * @param hdma2d DMA2D handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d)
@@ -1528,7 +1526,7 @@
/**
* @brief Disable DMA2D dead time feature.
- * @param hdma2d: DMA2D handle.
+ * @param hdma2d DMA2D handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d)
@@ -1553,8 +1551,8 @@
* @brief Configure dead time.
* @note The dead time value represents the guaranteed minimum number of cycles between
* two consecutive transactions on the AHB bus.
- * @param hdma2d: DMA2D handle.
- * @param DeadTime: dead time value.
+ * @param hdma2d DMA2D handle.
+ * @param DeadTime dead time value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime)
@@ -1597,7 +1595,7 @@
/**
* @brief Return the DMA2D state
- * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @retval HAL state
*/
@@ -1608,7 +1606,7 @@
/**
* @brief Return the DMA2D error code
- * @param hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for DMA2D.
* @retval DMA2D Error Code
*/
@@ -1631,12 +1629,12 @@
/**
* @brief Set the DMA2D transfer parameters.
- * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the specified DMA2D.
- * @param pdata: The source memory Buffer address
- * @param DstAddress: The destination memory Buffer address
- * @param Width: The width of data to be transferred from source to destination.
- * @param Height: The height of data to be transferred from source to destination.
+ * @param pdata The source memory Buffer address
+ * @param DstAddress The destination memory Buffer address
+ * @param Width The width of data to be transferred from source to destination.
+ * @param Height The height of data to be transferred from source to destination.
* @retval HAL status
*/
static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma2d.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma2d.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_dma2d.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of DMA2D HAL module. ****************************************************************************** * @attention @@ -292,14 +290,14 @@ */ /** @brief Reset DMA2D handle state - * @param __HANDLE__: specifies the DMA2D handle. + * @param __HANDLE__ specifies the DMA2D handle. * @retval None */ #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET) /** * @brief Enable the DMA2D. - * @param __HANDLE__: DMA2D handle + * @param __HANDLE__ DMA2D handle * @retval None. */ #define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START) @@ -307,8 +305,8 @@ /* Interrupt & Flag management */ /** * @brief Get the DMA2D pending flags. - * @param __HANDLE__: DMA2D handle - * @param __FLAG__: flag to check. + * @param __HANDLE__ DMA2D handle + * @param __FLAG__ flag to check. * This parameter can be any combination of the following values: * @arg DMA2D_FLAG_CE: Configuration error flag * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag @@ -322,8 +320,8 @@ /** * @brief Clear the DMA2D pending flags. - * @param __HANDLE__: DMA2D handle - * @param __FLAG__: specifies the flag to clear. + * @param __HANDLE__ DMA2D handle + * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: * @arg DMA2D_FLAG_CE: Configuration error flag * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag @@ -337,8 +335,8 @@ /** * @brief Enable the specified DMA2D interrupts. - * @param __HANDLE__: DMA2D handle - * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be enabled. + * @param __HANDLE__ DMA2D handle + * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be enabled. * This parameter can be any combination of the following values: * @arg DMA2D_IT_CE: Configuration error interrupt mask * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask @@ -352,8 +350,8 @@ /** * @brief Disable the specified DMA2D interrupts. - * @param __HANDLE__: DMA2D handle - * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be disabled. + * @param __HANDLE__ DMA2D handle + * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be disabled. * This parameter can be any combination of the following values: * @arg DMA2D_IT_CE: Configuration error interrupt mask * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask @@ -367,8 +365,8 @@ /** * @brief Check whether the specified DMA2D interrupt source is enabled or not. - * @param __HANDLE__: DMA2D handle - * @param __INTERRUPT__: specifies the DMA2D interrupt source to check. + * @param __HANDLE__ DMA2D handle + * @param __INTERRUPT__ specifies the DMA2D interrupt source to check. * This parameter can be one of the following values: * @arg DMA2D_IT_CE: Configuration error interrupt mask * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma_ex.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma_ex.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_dma_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief DMA Extension HAL module driver * This file provides firmware functions to manage the following * functionalities of the DMA Extension peripheral: @@ -108,12 +106,12 @@ /** * @brief Starts the multi_buffer DMA Transfer. - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer - * @param DataLength: The length of data to be transferred from source to destination + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param SecondMemAddress The second memory Buffer address in case of multi buffer Transfer + * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength) @@ -162,12 +160,12 @@ /** * @brief Starts the multi_buffer DMA Transfer with interrupt enabled. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer - * @param DataLength: The length of data to be transferred from source to destination + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param SecondMemAddress The second memory Buffer address in case of multi buffer Transfer + * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength) @@ -243,10 +241,10 @@ /** * @brief Change the memory0 or memory1 address on the fly. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. - * @param Address: The new address - * @param memory: the memory to be changed, This parameter can be one of + * @param Address The new address + * @param memory the memory to be changed, This parameter can be one of * the following values: * MEMORY0 / * MEMORY1 @@ -285,11 +283,11 @@ /** * @brief Set the DMA Transfer parameter. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param DataLength: The length of data to be transferred from source to destination + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma_ex.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dma_ex.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_dma_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of DMA HAL extension module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dsi.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dsi.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,14 +2,12 @@
******************************************************************************
* @file stm32f4xx_hal_dsi.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief DSI HAL module driver.
- * This file provides firmware functions to manage the following
+ * This file provides firmware functions to manage the following
* functionalities of the DSI peripheral:
* + Initialization and de-initialization functions
* + IO operation functions
- * + Peripheral Control functions
+ * + Peripheral Control functions
* + Peripheral State and Errors functions
******************************************************************************
* @attention
@@ -39,7 +37,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
- */
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal.h"
@@ -47,14 +45,15 @@
/** @addtogroup STM32F4xx_HAL_Driver
* @{
*/
+
+#ifdef HAL_DSI_MODULE_ENABLED
+
+#if defined(DSI)
+
/** @addtogroup DSI
* @{
*/
-#ifdef HAL_DSI_MODULE_ENABLED
-
-#if defined(STM32F469xx) || defined(STM32F479xx)
-
/* Private types -------------------------------------------------------------*/
/* Private defines -----------------------------------------------------------*/
/** @addtogroup DSI_Private_Constants
@@ -88,16 +87,16 @@
/* Private functions ---------------------------------------------------------*/
/**
* @brief Generic DSI packet header configuration
- * @param DSIx: Pointer to DSI register base
- * @param ChannelID: Virtual channel ID of the header packet
- * @param DataType: Packet data type of the header packet
+ * @param DSIx Pointer to DSI register base
+ * @param ChannelID Virtual channel ID of the header packet
+ * @param DataType Packet data type of the header packet
* This parameter can be any value of :
* @ref DSI_SHORT_WRITE_PKT_Data_Type
* or @ref DSI_LONG_WRITE_PKT_Data_Type
* or @ref DSI_SHORT_READ_PKT_Data_Type
* or DSI_MAX_RETURN_PKT_SIZE
- * @param Data0: Word count LSB
- * @param Data1: Word count MSB
+ * @param Data0 Word count LSB
+ * @param Data1 Word count MSB
* @retval None
*/
static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx,
@@ -118,142 +117,142 @@
/** @defgroup DSI_Group1 Initialization and Configuration functions
* @brief Initialization and Configuration functions
*
-@verbatim
+@verbatim
===============================================================================
##### Initialization and Configuration functions #####
- ===============================================================================
+ ===============================================================================
[..] This section provides functions allowing to:
(+) Initialize and configure the DSI
- (+) De-initialize the DSI
+ (+) De-initialize the DSI
@endverbatim
* @{
*/
-
+
/**
* @brief Initializes the DSI according to the specified
* parameters in the DSI_InitTypeDef and create the associated handle.
- * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
- * @param PLLInit: pointer to a DSI_PLLInitTypeDef structure that contains
- * the PLL Clock structure definition for the DSI.
+ * @param PLLInit pointer to a DSI_PLLInitTypeDef structure that contains
+ * the PLL Clock structure definition for the DSI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_Init(DSI_HandleTypeDef *hdsi, DSI_PLLInitTypeDef *PLLInit)
{
- uint32_t tickstart = 0U;
- uint32_t unitIntervalx4 = 0U;
- uint32_t tempIDF = 0U;
-
+ uint32_t tickstart;
+ uint32_t unitIntervalx4;
+ uint32_t tempIDF;
+
/* Check the DSI handle allocation */
if(hdsi == NULL)
{
return HAL_ERROR;
}
-
+
/* Check function parameters */
assert_param(IS_DSI_PLL_NDIV(PLLInit->PLLNDIV));
assert_param(IS_DSI_PLL_IDF(PLLInit->PLLIDF));
assert_param(IS_DSI_PLL_ODF(PLLInit->PLLODF));
assert_param(IS_DSI_AUTO_CLKLANE_CONTROL(hdsi->Init.AutomaticClockLaneControl));
assert_param(IS_DSI_NUMBER_OF_LANES(hdsi->Init.NumberOfLanes));
-
+
if(hdsi->State == HAL_DSI_STATE_RESET)
{
/* Initialize the low level hardware */
HAL_DSI_MspInit(hdsi);
}
-
+
/* Change DSI peripheral state */
hdsi->State = HAL_DSI_STATE_BUSY;
-
+
/**************** Turn on the regulator and enable the DSI PLL ****************/
-
- /* Enable the regulator */
- __HAL_DSI_REG_ENABLE(hdsi);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Wait until the regulator is ready */
- while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_RRS) == RESET)
+
+ /* Enable the regulator */
+ __HAL_DSI_REG_ENABLE(hdsi);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait until the regulator is ready */
+ while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_RRS) == RESET)
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
{
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
+ return HAL_TIMEOUT;
}
-
- /* Set the PLL division factors */
- hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV | DSI_WRPCR_PLL_IDF | DSI_WRPCR_PLL_ODF);
- hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV)<<2U) | ((PLLInit->PLLIDF)<<11U) | ((PLLInit->PLLODF)<<16U));
-
- /* Enable the DSI PLL */
- __HAL_DSI_PLL_ENABLE(hdsi);
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Wait for the lock of the PLL */
- while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET)
+ }
+
+ /* Set the PLL division factors */
+ hdsi->Instance->WRPCR &= ~(DSI_WRPCR_PLL_NDIV | DSI_WRPCR_PLL_IDF | DSI_WRPCR_PLL_ODF);
+ hdsi->Instance->WRPCR |= (((PLLInit->PLLNDIV)<<2U) | ((PLLInit->PLLIDF)<<11U) | ((PLLInit->PLLODF)<<16U));
+
+ /* Enable the DSI PLL */
+ __HAL_DSI_PLL_ENABLE(hdsi);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait for the lock of the PLL */
+ while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET)
+ {
+ /* Check for the Timeout */
+ if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
{
- /* Check for the Timeout */
- if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
+ return HAL_TIMEOUT;
}
-
+ }
+
/*************************** Set the PHY parameters ***************************/
-
- /* D-PHY clock and digital enable*/
- hdsi->Instance->PCTLR |= (DSI_PCTLR_CKE | DSI_PCTLR_DEN);
-
- /* Clock lane configuration */
- hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR);
- hdsi->Instance->CLCR |= (DSI_CLCR_DPCC | hdsi->Init.AutomaticClockLaneControl);
-
- /* Configure the number of active data lanes */
- hdsi->Instance->PCONFR &= ~DSI_PCONFR_NL;
- hdsi->Instance->PCONFR |= hdsi->Init.NumberOfLanes;
-
+
+ /* D-PHY clock and digital enable*/
+ hdsi->Instance->PCTLR |= (DSI_PCTLR_CKE | DSI_PCTLR_DEN);
+
+ /* Clock lane configuration */
+ hdsi->Instance->CLCR &= ~(DSI_CLCR_DPCC | DSI_CLCR_ACR);
+ hdsi->Instance->CLCR |= (DSI_CLCR_DPCC | hdsi->Init.AutomaticClockLaneControl);
+
+ /* Configure the number of active data lanes */
+ hdsi->Instance->PCONFR &= ~DSI_PCONFR_NL;
+ hdsi->Instance->PCONFR |= hdsi->Init.NumberOfLanes;
+
/************************ Set the DSI clock parameters ************************/
-
- /* Set the TX escape clock division factor */
- hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV;
- hdsi->Instance->CCR |= hdsi->Init.TXEscapeCkdiv;
-
- /* Calculate the bit period in high-speed mode in unit of 0.25 ns (UIX4) */
- /* The equation is : UIX4 = IntegerPart( (1000/F_PHY_Mhz) * 4 ) */
- /* Where : F_PHY_Mhz = (NDIV * HSE_Mhz) / (IDF * ODF) */
- tempIDF = (PLLInit->PLLIDF > 0U) ? PLLInit->PLLIDF : 1U;
- unitIntervalx4 = (4000000U * tempIDF * (1U << PLLInit->PLLODF)) / ((HSE_VALUE/1000U) * PLLInit->PLLNDIV);
-
- /* Set the bit period in high-speed mode */
- hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_UIX4;
- hdsi->Instance->WPCR[0U] |= unitIntervalx4;
-
+
+ /* Set the TX escape clock division factor */
+ hdsi->Instance->CCR &= ~DSI_CCR_TXECKDIV;
+ hdsi->Instance->CCR |= hdsi->Init.TXEscapeCkdiv;
+
+ /* Calculate the bit period in high-speed mode in unit of 0.25 ns (UIX4) */
+ /* The equation is : UIX4 = IntegerPart( (1000/F_PHY_Mhz) * 4 ) */
+ /* Where : F_PHY_Mhz = (NDIV * HSE_Mhz) / (IDF * ODF) */
+ tempIDF = (PLLInit->PLLIDF > 0U) ? PLLInit->PLLIDF : 1U;
+ unitIntervalx4 = (4000000U * tempIDF * (1U << PLLInit->PLLODF)) / ((HSE_VALUE/1000U) * PLLInit->PLLNDIV);
+
+ /* Set the bit period in high-speed mode */
+ hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_UIX4;
+ hdsi->Instance->WPCR[0U] |= unitIntervalx4;
+
/****************************** Error management *****************************/
-
- /* Disable all error interrupts and reset the Error Mask */
- hdsi->Instance->IER[0U] = 0U;
- hdsi->Instance->IER[1U] = 0U;
- hdsi->ErrorMsk = 0U;
-
- /* Initialise the error code */
- hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
-
+
+ /* Disable all error interrupts and reset the Error Mask */
+ hdsi->Instance->IER[0U] = 0U;
+ hdsi->Instance->IER[1U] = 0U;
+ hdsi->ErrorMsk = 0U;
+
+ /* Initialise the error code */
+ hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
+
/* Initialize the DSI state*/
hdsi->State = HAL_DSI_STATE_READY;
-
+
return HAL_OK;
}
/**
* @brief De-initializes the DSI peripheral registers to their default reset
* values.
- * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @retval HAL status
*/
@@ -264,140 +263,128 @@
{
return HAL_ERROR;
}
-
+
/* Change DSI peripheral state */
hdsi->State = HAL_DSI_STATE_BUSY;
-
+
/* Disable the DSI wrapper */
__HAL_DSI_WRAPPER_DISABLE(hdsi);
-
+
/* Disable the DSI host */
__HAL_DSI_DISABLE(hdsi);
-
+
/* D-PHY clock and digital disable */
hdsi->Instance->PCTLR &= ~(DSI_PCTLR_CKE | DSI_PCTLR_DEN);
-
+
/* Turn off the DSI PLL */
__HAL_DSI_PLL_DISABLE(hdsi);
-
+
/* Disable the regulator */
__HAL_DSI_REG_DISABLE(hdsi);
-
+
/* DeInit the low level hardware */
- HAL_DSI_MspDeInit(hdsi);
-
+ HAL_DSI_MspDeInit(hdsi);
+
/* Initialise the error code */
hdsi->ErrorCode = HAL_DSI_ERROR_NONE;
-
+
/* Initialize the DSI state*/
hdsi->State = HAL_DSI_STATE_RESET;
-
+
/* Release Lock */
__HAL_UNLOCK(hdsi);
-
+
return HAL_OK;
}
/**
- * @brief Return the DSI error code
- * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * @brief Enable the error monitor flags
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
- * @retval DSI Error Code
- */
-uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi)
-{
- /* Get the error code */
- return hdsi->ErrorCode;
-}
-
-/**
- * @brief Enable the error monitor flags
- * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
- * the configuration information for the DSI.
- * @param ActiveErrors: indicates which error interrupts will be enabled.
+ * @param ActiveErrors indicates which error interrupts will be enabled.
* This parameter can be any combination of @ref DSI_Error_Data_Type.
- * @retval HAL status
+ * @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_ConfigErrorMonitor(DSI_HandleTypeDef *hdsi, uint32_t ActiveErrors)
{
/* Process locked */
__HAL_LOCK(hdsi);
-
+
hdsi->Instance->IER[0U] = 0U;
hdsi->Instance->IER[1U] = 0U;
-
+
/* Store active errors to the handle */
hdsi->ErrorMsk = ActiveErrors;
-
+
if((ActiveErrors & HAL_DSI_ERROR_ACK) != RESET)
{
/* Enable the interrupt generation on selected errors */
hdsi->Instance->IER[0U] |= DSI_ERROR_ACK_MASK;
}
-
+
if((ActiveErrors & HAL_DSI_ERROR_PHY) != RESET)
{
/* Enable the interrupt generation on selected errors */
hdsi->Instance->IER[0U] |= DSI_ERROR_PHY_MASK;
}
-
+
if((ActiveErrors & HAL_DSI_ERROR_TX) != RESET)
{
/* Enable the interrupt generation on selected errors */
hdsi->Instance->IER[1U] |= DSI_ERROR_TX_MASK;
}
-
+
if((ActiveErrors & HAL_DSI_ERROR_RX) != RESET)
{
/* Enable the interrupt generation on selected errors */
hdsi->Instance->IER[1U] |= DSI_ERROR_RX_MASK;
}
-
+
if((ActiveErrors & HAL_DSI_ERROR_ECC) != RESET)
{
/* Enable the interrupt generation on selected errors */
hdsi->Instance->IER[1U] |= DSI_ERROR_ECC_MASK;
}
-
+
if((ActiveErrors & HAL_DSI_ERROR_CRC) != RESET)
{
/* Enable the interrupt generation on selected errors */
hdsi->Instance->IER[1U] |= DSI_ERROR_CRC_MASK;
}
-
+
if((ActiveErrors & HAL_DSI_ERROR_PSE) != RESET)
{
/* Enable the interrupt generation on selected errors */
hdsi->Instance->IER[1U] |= DSI_ERROR_PSE_MASK;
}
-
+
if((ActiveErrors & HAL_DSI_ERROR_EOT) != RESET)
{
/* Enable the interrupt generation on selected errors */
hdsi->Instance->IER[1U] |= DSI_ERROR_EOT_MASK;
}
-
+
if((ActiveErrors & HAL_DSI_ERROR_OVF) != RESET)
{
/* Enable the interrupt generation on selected errors */
hdsi->Instance->IER[1U] |= DSI_ERROR_OVF_MASK;
}
-
+
if((ActiveErrors & HAL_DSI_ERROR_GEN) != RESET)
{
/* Enable the interrupt generation on selected errors */
hdsi->Instance->IER[1U] |= DSI_ERROR_GEN_MASK;
}
-
+
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
-
+
return HAL_OK;
}
/**
* @brief Initializes the DSI MSP.
- * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @retval None
*/
@@ -407,12 +394,12 @@
UNUSED(hdsi);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_DSI_MspInit could be implemented in the user file
- */
+ */
}
/**
* @brief De-initializes the DSI MSP.
- * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @retval None
*/
@@ -428,14 +415,14 @@
/**
* @}
*/
-
-/** @defgroup DSI_Group2 IO operation functions
- * @brief IO operation functions
+
+/** @defgroup DSI_Group2 IO operation functions
+ * @brief IO operation functions
*
@verbatim
===============================================================================
##### IO operation functions #####
- ===============================================================================
+ ===============================================================================
[..] This section provides function allowing to:
(+) Handle DSI interrupt request
@@ -444,14 +431,14 @@
*/
/**
* @brief Handles DSI interrupt request.
- * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
- * the configuration information for the DSI.
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
* @retval HAL status
*/
void HAL_DSI_IRQHandler(DSI_HandleTypeDef *hdsi)
{
uint32_t ErrorStatus0, ErrorStatus1;
-
+
/* Tearing Effect Interrupt management ***************************************/
if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_TE) != RESET)
{
@@ -459,12 +446,12 @@
{
/* Clear the Tearing Effect Interrupt Flag */
__HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_TE);
-
+
/* Tearing Effect Callback */
HAL_DSI_TearingEffectCallback(hdsi);
}
}
-
+
/* End of Refresh Interrupt management ***************************************/
if(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_ER) != RESET)
{
@@ -472,12 +459,12 @@
{
/* Clear the End of Refresh Interrupt Flag */
__HAL_DSI_CLEAR_FLAG(hdsi, DSI_FLAG_ER);
-
+
/* End of Refresh Callback */
HAL_DSI_EndOfRefreshCallback(hdsi);
}
}
-
+
/* Error Interrupts management ***********************************************/
if(hdsi->ErrorMsk != 0U)
{
@@ -485,57 +472,57 @@
ErrorStatus0 &= hdsi->Instance->IER[0U];
ErrorStatus1 = hdsi->Instance->ISR[1U];
ErrorStatus1 &= hdsi->Instance->IER[1U];
-
+
if((ErrorStatus0 & DSI_ERROR_ACK_MASK) != RESET)
{
hdsi->ErrorCode |= HAL_DSI_ERROR_ACK;
}
-
+
if((ErrorStatus0 & DSI_ERROR_PHY_MASK) != RESET)
{
hdsi->ErrorCode |= HAL_DSI_ERROR_PHY;
}
-
+
if((ErrorStatus1 & DSI_ERROR_TX_MASK) != RESET)
{
hdsi->ErrorCode |= HAL_DSI_ERROR_TX;
}
-
+
if((ErrorStatus1 & DSI_ERROR_RX_MASK) != RESET)
{
hdsi->ErrorCode |= HAL_DSI_ERROR_RX;
}
-
+
if((ErrorStatus1 & DSI_ERROR_ECC_MASK) != RESET)
{
hdsi->ErrorCode |= HAL_DSI_ERROR_ECC;
}
-
+
if((ErrorStatus1 & DSI_ERROR_CRC_MASK) != RESET)
{
hdsi->ErrorCode |= HAL_DSI_ERROR_CRC;
}
-
+
if((ErrorStatus1 & DSI_ERROR_PSE_MASK) != RESET)
{
hdsi->ErrorCode |= HAL_DSI_ERROR_PSE;
}
-
+
if((ErrorStatus1 & DSI_ERROR_EOT_MASK) != RESET)
{
hdsi->ErrorCode |= HAL_DSI_ERROR_EOT;
}
-
+
if((ErrorStatus1 & DSI_ERROR_OVF_MASK) != RESET)
{
hdsi->ErrorCode |= HAL_DSI_ERROR_OVF;
}
-
+
if((ErrorStatus1 & DSI_ERROR_GEN_MASK) != RESET)
{
hdsi->ErrorCode |= HAL_DSI_ERROR_GEN;
}
-
+
/* Check only selected errors */
if(hdsi->ErrorCode != HAL_DSI_ERROR_NONE)
{
@@ -547,7 +534,7 @@
/**
* @brief Tearing Effect DSI callback.
- * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @retval None
*/
@@ -562,7 +549,7 @@
/**
* @brief End of Refresh DSI callback.
- * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @retval None
*/
@@ -577,7 +564,7 @@
/**
* @brief Operation Error DSI callback.
- * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @retval None
*/
@@ -595,12 +582,40 @@
*/
/** @defgroup DSI_Group3 Peripheral Control functions
- * @brief Peripheral Control functions
+ * @brief Peripheral Control functions
*
@verbatim
===============================================================================
##### Peripheral Control functions #####
===============================================================================
+ [..] This section provides functions allowing to:
+ (+) Configure the Generic interface read-back Virtual Channel ID
+ (+) Select video mode and configure the corresponding parameters
+ (+) Configure command transmission mode: High-speed or Low-power
+ (+) Configure the flow control
+ (+) Configure the DSI PHY timer
+ (+) Configure the DSI HOST timeout
+ (+) Configure the DSI HOST timeout
+ (+) Start/Stop the DSI module
+ (+) Refresh the display in command mode
+ (+) Controls the display color mode in Video mode
+ (+) Control the display shutdown in Video mode
+ (+) write short DCS or short Generic command
+ (+) write long DCS or long Generic command
+ (+) Read command (DCS or generic)
+ (+) Enter/Exit the Ultra Low Power Mode on data only (D-PHY PLL running)
+ (+) Enter/Exit the Ultra Low Power Mode on data only and clock (D-PHY PLL turned off)
+ (+) Start/Stop test pattern generation
+ (+) Slew-Rate And Delay Tuning
+ (+) Low-Power Reception Filter Tuning
+ (+) Activate an additional current path on all lanes to meet the SDDTx parameter
+ (+) Custom lane pins configuration
+ (+) Set custom timing for the PHY
+ (+) Force the Clock/Data Lane in TX Stop Mode
+ (+) Force LP Receiver in Low-Power Mode
+ (+) Force Data Lanes in RX Mode after a BTA
+ (+) Enable a pull-down on the lanes to prevent from floating states when unused
+ (+) Switch off the contention detection on data lanes
@endverbatim
* @{
@@ -608,39 +623,39 @@
/**
* @brief Configure the Generic interface read-back Virtual Channel ID.
- * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
- * @param VirtualChannelID: Virtual channel ID
+ * @param VirtualChannelID Virtual channel ID
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID)
{
/* Process locked */
__HAL_LOCK(hdsi);
-
+
/* Update the GVCID register */
hdsi->Instance->GVCIDR &= ~DSI_GVCIDR_VCID;
hdsi->Instance->GVCIDR |= VirtualChannelID;
-
+
/* Process unlocked */
__HAL_UNLOCK(hdsi);
-
+
return HAL_OK;
}
/**
* @brief Select video mode and configure the corresponding parameters
- * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
- * @param VidCfg: pointer to a DSI_VidCfgTypeDef structure that contains
- * the DSI video mode configuration parameters
+ * @param VidCfg pointer to a DSI_VidCfgTypeDef structure that contains
+ * the DSI video mode configuration parameters
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_ConfigVideoMode(DSI_HandleTypeDef *hdsi, DSI_VidCfgTypeDef *VidCfg)
{
/* Process locked */
__HAL_LOCK(hdsi);
-
+
/* Check the parameters */
assert_param(IS_DSI_COLOR_CODING(VidCfg->ColorCoding));
assert_param(IS_DSI_VIDEO_MODE_TYPE(VidCfg->Mode));
@@ -660,129 +675,129 @@
{
assert_param(IS_DSI_LOOSELY_PACKED(VidCfg->LooselyPacked));
}
-
+
/* Select video mode by resetting CMDM and DSIM bits */
hdsi->Instance->MCR &= ~DSI_MCR_CMDM;
hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM;
-
+
/* Configure the video mode transmission type */
hdsi->Instance->VMCR &= ~DSI_VMCR_VMT;
hdsi->Instance->VMCR |= VidCfg->Mode;
-
+
/* Configure the video packet size */
hdsi->Instance->VPCR &= ~DSI_VPCR_VPSIZE;
hdsi->Instance->VPCR |= VidCfg->PacketSize;
-
+
/* Set the chunks number to be transmitted through the DSI link */
hdsi->Instance->VCCR &= ~DSI_VCCR_NUMC;
hdsi->Instance->VCCR |= VidCfg->NumberOfChunks;
-
+
/* Set the size of the null packet */
hdsi->Instance->VNPCR &= ~DSI_VNPCR_NPSIZE;
hdsi->Instance->VNPCR |= VidCfg->NullPacketSize;
-
+
/* Select the virtual channel for the LTDC interface traffic */
hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID;
hdsi->Instance->LVCIDR |= VidCfg->VirtualChannelID;
-
+
/* Configure the polarity of control signals */
hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP);
hdsi->Instance->LPCR |= (VidCfg->DEPolarity | VidCfg->VSPolarity | VidCfg->HSPolarity);
-
+
/* Select the color coding for the host */
hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC;
hdsi->Instance->LCOLCR |= VidCfg->ColorCoding;
-
+
/* Select the color coding for the wrapper */
hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX;
hdsi->Instance->WCFGR |= ((VidCfg->ColorCoding)<<1U);
-
+
/* Enable/disable the loosely packed variant to 18-bit configuration */
if(VidCfg->ColorCoding == DSI_RGB666)
{
hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_LPE;
hdsi->Instance->LCOLCR |= VidCfg->LooselyPacked;
}
-
+
/* Set the Horizontal Synchronization Active (HSA) in lane byte clock cycles */
hdsi->Instance->VHSACR &= ~DSI_VHSACR_HSA;
hdsi->Instance->VHSACR |= VidCfg->HorizontalSyncActive;
-
+
/* Set the Horizontal Back Porch (HBP) in lane byte clock cycles */
hdsi->Instance->VHBPCR &= ~DSI_VHBPCR_HBP;
hdsi->Instance->VHBPCR |= VidCfg->HorizontalBackPorch;
-
+
/* Set the total line time (HLINE=HSA+HBP+HACT+HFP) in lane byte clock cycles */
hdsi->Instance->VLCR &= ~DSI_VLCR_HLINE;
hdsi->Instance->VLCR |= VidCfg->HorizontalLine;
-
+
/* Set the Vertical Synchronization Active (VSA) */
hdsi->Instance->VVSACR &= ~DSI_VVSACR_VSA;
hdsi->Instance->VVSACR |= VidCfg->VerticalSyncActive;
-
+
/* Set the Vertical Back Porch (VBP)*/
hdsi->Instance->VVBPCR &= ~DSI_VVBPCR_VBP;
hdsi->Instance->VVBPCR |= VidCfg->VerticalBackPorch;
-
+
/* Set the Vertical Front Porch (VFP)*/
hdsi->Instance->VVFPCR &= ~DSI_VVFPCR_VFP;
hdsi->Instance->VVFPCR |= VidCfg->VerticalFrontPorch;
-
+
/* Set the Vertical Active period*/
hdsi->Instance->VVACR &= ~DSI_VVACR_VA;
hdsi->Instance->VVACR |= VidCfg->VerticalActive;
-
+
/* Configure the command transmission mode */
hdsi->Instance->VMCR &= ~DSI_VMCR_LPCE;
hdsi->Instance->VMCR |= VidCfg->LPCommandEnable;
-
+
/* Low power largest packet size */
hdsi->Instance->LPMCR &= ~DSI_LPMCR_LPSIZE;
hdsi->Instance->LPMCR |= ((VidCfg->LPLargestPacketSize)<<16U);
-
+
/* Low power VACT largest packet size */
hdsi->Instance->LPMCR &= ~DSI_LPMCR_VLPSIZE;
hdsi->Instance->LPMCR |= VidCfg->LPVACTLargestPacketSize;
-
+
/* Enable LP transition in HFP period */
hdsi->Instance->VMCR &= ~DSI_VMCR_LPHFPE;
hdsi->Instance->VMCR |= VidCfg->LPHorizontalFrontPorchEnable;
-
+
/* Enable LP transition in HBP period */
hdsi->Instance->VMCR &= ~DSI_VMCR_LPHBPE;
hdsi->Instance->VMCR |= VidCfg->LPHorizontalBackPorchEnable;
-
+
/* Enable LP transition in VACT period */
hdsi->Instance->VMCR &= ~DSI_VMCR_LPVAE;
hdsi->Instance->VMCR |= VidCfg->LPVerticalActiveEnable;
-
+
/* Enable LP transition in VFP period */
hdsi->Instance->VMCR &= ~DSI_VMCR_LPVFPE;
hdsi->Instance->VMCR |= VidCfg->LPVerticalFrontPorchEnable;
-
+
/* Enable LP transition in VBP period */
hdsi->Instance->VMCR &= ~DSI_VMCR_LPVBPE;
hdsi->Instance->VMCR |= VidCfg->LPVerticalBackPorchEnable;
-
+
/* Enable LP transition in vertical sync period */
hdsi->Instance->VMCR &= ~DSI_VMCR_LPVSAE;
hdsi->Instance->VMCR |= VidCfg->LPVerticalSyncActiveEnable;
-
+
/* Enable the request for an acknowledge response at the end of a frame */
hdsi->Instance->VMCR &= ~DSI_VMCR_FBTAAE;
hdsi->Instance->VMCR |= VidCfg->FrameBTAAcknowledgeEnable;
-
+
/* Process unlocked */
__HAL_UNLOCK(hdsi);
-
+
return HAL_OK;
}
/**
* @brief Select adapted command mode and configure the corresponding parameters
- * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
- * @param CmdCfg: pointer to a DSI_CmdCfgTypeDef structure that contains
+ * @param CmdCfg pointer to a DSI_CmdCfgTypeDef structure that contains
* the DSI command mode configuration parameters
* @retval HAL status
*/
@@ -790,7 +805,7 @@
{
/* Process locked */
__HAL_LOCK(hdsi);
-
+
/* Check the parameters */
assert_param(IS_DSI_COLOR_CODING(CmdCfg->ColorCoding));
assert_param(IS_DSI_TE_SOURCE(CmdCfg->TearingEffectSource));
@@ -801,58 +816,58 @@
assert_param(IS_DSI_DE_POLARITY(CmdCfg->DEPolarity));
assert_param(IS_DSI_VSYNC_POLARITY(CmdCfg->VSPolarity));
assert_param(IS_DSI_HSYNC_POLARITY(CmdCfg->HSPolarity));
-
+
/* Select command mode by setting CMDM and DSIM bits */
hdsi->Instance->MCR |= DSI_MCR_CMDM;
hdsi->Instance->WCFGR &= ~DSI_WCFGR_DSIM;
hdsi->Instance->WCFGR |= DSI_WCFGR_DSIM;
-
+
/* Select the virtual channel for the LTDC interface traffic */
hdsi->Instance->LVCIDR &= ~DSI_LVCIDR_VCID;
hdsi->Instance->LVCIDR |= CmdCfg->VirtualChannelID;
-
+
/* Configure the polarity of control signals */
hdsi->Instance->LPCR &= ~(DSI_LPCR_DEP | DSI_LPCR_VSP | DSI_LPCR_HSP);
hdsi->Instance->LPCR |= (CmdCfg->DEPolarity | CmdCfg->VSPolarity | CmdCfg->HSPolarity);
-
+
/* Select the color coding for the host */
hdsi->Instance->LCOLCR &= ~DSI_LCOLCR_COLC;
hdsi->Instance->LCOLCR |= CmdCfg->ColorCoding;
-
+
/* Select the color coding for the wrapper */
hdsi->Instance->WCFGR &= ~DSI_WCFGR_COLMUX;
hdsi->Instance->WCFGR |= ((CmdCfg->ColorCoding)<<1U);
-
+
/* Configure the maximum allowed size for write memory command */
hdsi->Instance->LCCR &= ~DSI_LCCR_CMDSIZE;
hdsi->Instance->LCCR |= CmdCfg->CommandSize;
-
+
/* Configure the tearing effect source and polarity and select the refresh mode */
hdsi->Instance->WCFGR &= ~(DSI_WCFGR_TESRC | DSI_WCFGR_TEPOL | DSI_WCFGR_AR | DSI_WCFGR_VSPOL);
hdsi->Instance->WCFGR |= (CmdCfg->TearingEffectSource | CmdCfg->TearingEffectPolarity | CmdCfg->AutomaticRefresh | CmdCfg->VSyncPol);
-
+
/* Configure the tearing effect acknowledge request */
hdsi->Instance->CMCR &= ~DSI_CMCR_TEARE;
hdsi->Instance->CMCR |= CmdCfg->TEAcknowledgeRequest;
-
+
/* Enable the Tearing Effect interrupt */
__HAL_DSI_ENABLE_IT(hdsi, DSI_IT_TE);
-
+
/* Enable the End of Refresh interrupt */
__HAL_DSI_ENABLE_IT(hdsi, DSI_IT_ER);
-
+
/* Process unlocked */
__HAL_UNLOCK(hdsi);
-
+
return HAL_OK;
}
/**
* @brief Configure command transmission mode: High-speed or Low-power
* and enable/disable acknowledge request after packet transmission
- * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
- * @param LPCmd: pointer to a DSI_LPCmdTypeDef structure that contains
+ * @param LPCmd pointer to a DSI_LPCmdTypeDef structure that contains
* the DSI command transmission mode configuration parameters
* @retval HAL status
*/
@@ -860,7 +875,7 @@
{
/* Process locked */
__HAL_LOCK(hdsi);
-
+
assert_param(IS_DSI_LP_GSW0P(LPCmd->LPGenShortWriteNoP));
assert_param(IS_DSI_LP_GSW1P(LPCmd->LPGenShortWriteOneP));
assert_param(IS_DSI_LP_GSW2P(LPCmd->LPGenShortWriteTwoP));
@@ -874,7 +889,7 @@
assert_param(IS_DSI_LP_DLW(LPCmd->LPDcsLongWrite));
assert_param(IS_DSI_LP_MRDP(LPCmd->LPMaxReadPacket));
assert_param(IS_DSI_ACK_REQUEST(LPCmd->AcknowledgeRequest));
-
+
/* Select High-speed or Low-power for command transmission */
hdsi->Instance->CMCR &= ~(DSI_CMCR_GSW0TX |\
DSI_CMCR_GSW1TX |\
@@ -900,22 +915,22 @@
LPCmd->LPDcsShortReadNoP |\
LPCmd->LPDcsLongWrite |\
LPCmd->LPMaxReadPacket);
-
+
/* Configure the acknowledge request after each packet transmission */
hdsi->Instance->CMCR &= ~DSI_CMCR_ARE;
hdsi->Instance->CMCR |= LPCmd->AcknowledgeRequest;
-
+
/* Process unlocked */
__HAL_UNLOCK(hdsi);
-
+
return HAL_OK;
}
/**
* @brief Configure the flow control parameters
- * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
- * @param FlowControl: flow control feature(s) to be enabled.
+ * @param FlowControl flow control feature(s) to be enabled.
* This parameter can be any combination of @ref DSI_FlowControl.
* @retval HAL status
*/
@@ -923,25 +938,25 @@
{
/* Process locked */
__HAL_LOCK(hdsi);
-
+
/* Check the parameters */
assert_param(IS_DSI_FLOW_CONTROL(FlowControl));
-
+
/* Set the DSI Host Protocol Configuration Register */
hdsi->Instance->PCR &= ~DSI_FLOW_CONTROL_ALL;
hdsi->Instance->PCR |= FlowControl;
-
+
/* Process unlocked */
__HAL_UNLOCK(hdsi);
-
+
return HAL_OK;
}
/**
* @brief Configure the DSI PHY timer parameters
- * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
- * @param PhyTimers: DSI_PHY_TimerTypeDef structure that contains
+ * @param PhyTimers DSI_PHY_TimerTypeDef structure that contains
* the DSI PHY timing parameters
* @retval HAL status
*/
@@ -950,7 +965,7 @@
uint32_t maxTime;
/* Process locked */
__HAL_LOCK(hdsi);
-
+
maxTime = (PhyTimers->ClockLaneLP2HSTime > PhyTimers->ClockLaneHS2LPTime)? PhyTimers->ClockLaneLP2HSTime: PhyTimers->ClockLaneHS2LPTime;
/* Clock lane timer configuration */
@@ -966,26 +981,26 @@
*/
hdsi->Instance->CLTCR &= ~(DSI_CLTCR_LP2HS_TIME | DSI_CLTCR_HS2LP_TIME);
hdsi->Instance->CLTCR |= (maxTime | ((maxTime)<<16U));
-
+
/* Data lane timer configuration */
hdsi->Instance->DLTCR &= ~(DSI_DLTCR_MRD_TIME | DSI_DLTCR_LP2HS_TIME | DSI_DLTCR_HS2LP_TIME);
hdsi->Instance->DLTCR |= (PhyTimers->DataLaneMaxReadTime | ((PhyTimers->DataLaneLP2HSTime)<<16U) | ((PhyTimers->DataLaneHS2LPTime)<<24U));
-
+
/* Configure the wait period to request HS transmission after a stop state */
hdsi->Instance->PCONFR &= ~DSI_PCONFR_SW_TIME;
hdsi->Instance->PCONFR |= ((PhyTimers->StopWaitTime)<<8U);
-
+
/* Process unlocked */
__HAL_UNLOCK(hdsi);
-
+
return HAL_OK;
}
/**
* @brief Configure the DSI HOST timeout parameters
- * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
- * @param HostTimeouts: DSI_HOST_TimeoutTypeDef structure that contains
+ * @param HostTimeouts DSI_HOST_TimeoutTypeDef structure that contains
* the DSI host timeout parameters
* @retval HAL status
*/
@@ -993,52 +1008,52 @@
{
/* Process locked */
__HAL_LOCK(hdsi);
-
+
/* Set the timeout clock division factor */
hdsi->Instance->CCR &= ~DSI_CCR_TOCKDIV;
hdsi->Instance->CCR |= ((HostTimeouts->TimeoutCkdiv)<<8U);
-
+
/* High-speed transmission timeout */
hdsi->Instance->TCCR[0U] &= ~DSI_TCCR0_HSTX_TOCNT;
hdsi->Instance->TCCR[0U] |= ((HostTimeouts->HighSpeedTransmissionTimeout)<<16U);
-
+
/* Low-power reception timeout */
hdsi->Instance->TCCR[0U] &= ~DSI_TCCR0_LPRX_TOCNT;
hdsi->Instance->TCCR[0U] |= HostTimeouts->LowPowerReceptionTimeout;
-
+
/* High-speed read timeout */
hdsi->Instance->TCCR[1U] &= ~DSI_TCCR1_HSRD_TOCNT;
hdsi->Instance->TCCR[1U] |= HostTimeouts->HighSpeedReadTimeout;
-
+
/* Low-power read timeout */
hdsi->Instance->TCCR[2U] &= ~DSI_TCCR2_LPRD_TOCNT;
hdsi->Instance->TCCR[2U] |= HostTimeouts->LowPowerReadTimeout;
-
+
/* High-speed write timeout */
hdsi->Instance->TCCR[3U] &= ~DSI_TCCR3_HSWR_TOCNT;
hdsi->Instance->TCCR[3U] |= HostTimeouts->HighSpeedWriteTimeout;
-
+
/* High-speed write presp mode */
hdsi->Instance->TCCR[3U] &= ~DSI_TCCR3_PM;
hdsi->Instance->TCCR[3U] |= HostTimeouts->HighSpeedWritePrespMode;
-
+
/* Low-speed write timeout */
hdsi->Instance->TCCR[4U] &= ~DSI_TCCR4_LPWR_TOCNT;
hdsi->Instance->TCCR[4U] |= HostTimeouts->LowPowerWriteTimeout;
-
+
/* BTA timeout */
hdsi->Instance->TCCR[5U] &= ~DSI_TCCR5_BTA_TOCNT;
hdsi->Instance->TCCR[5U] |= HostTimeouts->BTATimeout;
-
+
/* Process unlocked */
__HAL_UNLOCK(hdsi);
-
+
return HAL_OK;
}
/**
* @brief Start the DSI module
- * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @retval HAL status
*/
@@ -1046,22 +1061,22 @@
{
/* Process locked */
__HAL_LOCK(hdsi);
-
+
/* Enable the DSI host */
__HAL_DSI_ENABLE(hdsi);
-
+
/* Enable the DSI wrapper */
__HAL_DSI_WRAPPER_ENABLE(hdsi);
-
+
/* Process unlocked */
__HAL_UNLOCK(hdsi);
-
+
return HAL_OK;
}
/**
* @brief Stop the DSI module
- * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @retval HAL status
*/
@@ -1069,22 +1084,22 @@
{
/* Process locked */
__HAL_LOCK(hdsi);
-
+
/* Disable the DSI host */
__HAL_DSI_DISABLE(hdsi);
-
+
/* Disable the DSI wrapper */
__HAL_DSI_WRAPPER_DISABLE(hdsi);
-
+
/* Process unlocked */
__HAL_UNLOCK(hdsi);
-
+
return HAL_OK;
}
/**
* @brief Refresh the display in command mode
- * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @retval HAL status
*/
@@ -1092,21 +1107,21 @@
{
/* Process locked */
__HAL_LOCK(hdsi);
-
+
/* Update the display */
hdsi->Instance->WCR |= DSI_WCR_LTDCEN;
-
+
/* Process unlocked */
__HAL_UNLOCK(hdsi);
-
+
return HAL_OK;
}
/**
* @brief Controls the display color mode in Video mode
- * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
- * @param ColorMode: Color mode (full or 8-colors).
+ * @param ColorMode Color mode (full or 8-colors).
* This parameter can be any value of @ref DSI_Color_Mode
* @retval HAL status
*/
@@ -1114,25 +1129,25 @@
{
/* Process locked */
__HAL_LOCK(hdsi);
-
+
/* Check the parameters */
assert_param(IS_DSI_COLOR_MODE(ColorMode));
-
+
/* Update the display color mode */
hdsi->Instance->WCR &= ~DSI_WCR_COLM;
hdsi->Instance->WCR |= ColorMode;
-
+
/* Process unlocked */
__HAL_UNLOCK(hdsi);
-
+
return HAL_OK;
}
/**
* @brief Control the display shutdown in Video mode
- * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
- * @param Shutdown: Shut-down (Display-ON or Display-OFF).
+ * @param Shutdown Shut-down (Display-ON or Display-OFF).
* This parameter can be any value of @ref DSI_ShutDown
* @retval HAL status
*/
@@ -1140,31 +1155,31 @@
{
/* Process locked */
__HAL_LOCK(hdsi);
-
+
/* Check the parameters */
assert_param(IS_DSI_SHUT_DOWN(Shutdown));
-
+
/* Update the display Shutdown */
hdsi->Instance->WCR &= ~DSI_WCR_SHTDN;
hdsi->Instance->WCR |= Shutdown;
-
+
/* Process unlocked */
__HAL_UNLOCK(hdsi);
-
+
return HAL_OK;
}
/**
- * @brief DCS or Generic short write command
- * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * @brief write short DCS or short Generic command
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
- * @param ChannelID: Virtual channel ID.
- * @param Mode: DSI short packet data type.
+ * @param ChannelID Virtual channel ID.
+ * @param Mode DSI short packet data type.
* This parameter can be any value of @ref DSI_SHORT_WRITE_PKT_Data_Type.
- * @param Param1: DSC command or first generic parameter.
+ * @param Param1 DSC command or first generic parameter.
* This parameter can be any value of @ref DSI_DCS_Command or a
* generic command code.
- * @param Param2: DSC parameter or second generic parameter.
+ * @param Param2 DSC parameter or second generic parameter.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi,
@@ -1173,17 +1188,17 @@
uint32_t Param1,
uint32_t Param2)
{
- uint32_t tickstart = 0U;
+ uint32_t tickstart;
/* Process locked */
__HAL_LOCK(hdsi);
-
+
/* Check the parameters */
assert_param(IS_DSI_SHORT_WRITE_PACKET_TYPE(Mode));
-
- /* Get tick */
+
+ /* Get tick */
tickstart = HAL_GetTick();
-
+
/* Wait for Command FIFO Empty */
while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == 0U)
{
@@ -1192,36 +1207,36 @@
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
-
+
return HAL_TIMEOUT;
}
}
-
+
/* Configure the packet to send a short DCS command with 0 or 1 parameter */
DSI_ConfigPacketHeader(hdsi->Instance,
ChannelID,
Mode,
Param1,
Param2);
-
+
/* Process unlocked */
__HAL_UNLOCK(hdsi);
-
+
return HAL_OK;
}
/**
- * @brief DCS or Generic long write command
- * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * @brief write long DCS or long Generic command
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
- * @param ChannelID: Virtual channel ID.
- * @param Mode: DSI long packet data type.
+ * @param ChannelID Virtual channel ID.
+ * @param Mode DSI long packet data type.
* This parameter can be any value of @ref DSI_LONG_WRITE_PKT_Data_Type.
- * @param NbParams: Number of parameters.
- * @param Param1: DSC command or first generic parameter.
- * This parameter can be any value of @ref DSI_DCS_Command or a
+ * @param NbParams Number of parameters.
+ * @param Param1 DSC command or first generic parameter.
+ * This parameter can be any value of @ref DSI_DCS_Command or a
* generic command code
- * @param ParametersTable: Pointer to parameter values table.
+ * @param ParametersTable Pointer to parameter values table.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi,
@@ -1231,19 +1246,20 @@
uint32_t Param1,
uint8_t* ParametersTable)
{
- uint32_t uicounter = 0U, nbBytes = 0U, count = 0U;
- uint32_t tickstart = 0U;
- uint32_t fifoword = 0U;
-
+ uint32_t uicounter, nbBytes, count;
+ uint32_t tickstart;
+ uint32_t fifoword;
+ uint8_t* pparams = ParametersTable;
+
/* Process locked */
__HAL_LOCK(hdsi);
-
+
/* Check the parameters */
assert_param(IS_DSI_LONG_WRITE_PACKET_TYPE(Mode));
-
- /* Get tick */
+
+ /* Get tick */
tickstart = HAL_GetTick();
-
+
/* Wait for Command FIFO Empty */
while((hdsi->Instance->GPSR & DSI_GPSR_CMDFE) == RESET)
{
@@ -1252,23 +1268,23 @@
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
-
+
return HAL_TIMEOUT;
}
}
-
+
/* Set the DCS code on payload byte 1, and the other parameters on the write FIFO command*/
fifoword = Param1;
nbBytes = (NbParams < 3U) ? NbParams : 3U;
-
+
for(count = 0U; count < nbBytes; count++)
{
- fifoword |= (((uint32_t)(*(ParametersTable + count))) << (8U + (8U*count)));
+ fifoword |= (((uint32_t)(*(pparams + count))) << (8U + (8U*count)));
}
hdsi->Instance->GPDR = fifoword;
-
+
uicounter = NbParams - nbBytes;
- ParametersTable += nbBytes;
+ pparams += nbBytes;
/* Set the Next parameters on the write FIFO command*/
while(uicounter != 0U)
{
@@ -1276,38 +1292,38 @@
fifoword = 0U;
for(count = 0U; count < nbBytes; count++)
{
- fifoword |= (((uint32_t)(*(ParametersTable + count))) << (8U*count));
+ fifoword |= (((uint32_t)(*(pparams + count))) << (8U*count));
}
hdsi->Instance->GPDR = fifoword;
-
+
uicounter -= nbBytes;
- ParametersTable += nbBytes;
+ pparams += nbBytes;
}
-
+
/* Configure the packet to send a long DCS command */
DSI_ConfigPacketHeader(hdsi->Instance,
ChannelID,
Mode,
((NbParams+1U)&0x00FFU),
(((NbParams+1U)&0xFF00U)>>8U));
-
+
/* Process unlocked */
__HAL_UNLOCK(hdsi);
-
+
return HAL_OK;
}
/**
* @brief Read command (DCS or generic)
- * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
- * @param ChannelNbr: Virtual channel ID
- * @param Array: pointer to a buffer to store the payload of a read back operation.
- * @param Size: Data size to be read (in byte).
- * @param Mode: DSI read packet data type.
+ * @param ChannelNbr Virtual channel ID
+ * @param Array pointer to a buffer to store the payload of a read back operation.
+ * @param Size Data size to be read (in byte).
+ * @param Mode DSI read packet data type.
* This parameter can be any value of @ref DSI_SHORT_READ_PKT_Data_Type.
- * @param DCSCmd: DCS get/read command.
- * @param ParametersTable: Pointer to parameter values table.
+ * @param DCSCmd DCS get/read command.
+ * @param ParametersTable Pointer to parameter values table.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi,
@@ -1318,20 +1334,28 @@
uint32_t DCSCmd,
uint8_t* ParametersTable)
{
- uint32_t tickstart = 0U;
-
+ uint32_t tickstart;
+ uint8_t* pdata = Array;
+ uint32_t datasize = Size;
+
/* Process locked */
__HAL_LOCK(hdsi);
-
+
/* Check the parameters */
assert_param(IS_DSI_READ_PACKET_TYPE(Mode));
-
- if(Size > 2U)
+
+ if(datasize > 2U)
{
/* set max return packet size */
- HAL_DSI_ShortWrite(hdsi, ChannelNbr, DSI_MAX_RETURN_PKT_SIZE, ((Size)&0xFFU), (((Size)>>8U)&0xFFU));
+ if (HAL_DSI_ShortWrite(hdsi, ChannelNbr, DSI_MAX_RETURN_PKT_SIZE, ((datasize)&0xFFU), (((datasize)>>8U)&0xFFU)) != HAL_OK)
+ {
+ /* Process Unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_ERROR;
+ }
}
-
+
/* Configure the packet to read command */
if (Mode == DSI_DCS_SHORT_PKT_READ)
{
@@ -1353,13 +1377,13 @@
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
-
- return HAL_ERROR;
+
+ return HAL_ERROR;
}
-
- /* Get tick */
+
+ /* Get tick */
tickstart = HAL_GetTick();
-
+
/* Check that the payload read FIFO is not empty */
while((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == DSI_GPSR_PRDFE)
{
@@ -1368,258 +1392,279 @@
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
-
+
return HAL_TIMEOUT;
}
}
-
+
/* Get the first byte */
- *((uint32_t *)Array) = (hdsi->Instance->GPDR);
- if (Size > 4U)
+ *((uint32_t *)pdata) = (hdsi->Instance->GPDR);
+ if (datasize > 4U)
{
- Size -= 4U;
- Array += 4U;
+ datasize -= 4U;
+ pdata += 4U;
}
else
{
/* Process unlocked */
__HAL_UNLOCK(hdsi);
-
+
return HAL_OK;
}
-
- /* Get tick */
+
+ /* Get tick */
tickstart = HAL_GetTick();
-
+
/* Get the remaining bytes if any */
- while(((int)(Size)) > 0U)
+ while(((int)(datasize)) > 0)
{
if((hdsi->Instance->GPSR & DSI_GPSR_PRDFE) == 0U)
{
- *((uint32_t *)Array) = (hdsi->Instance->GPDR);
- Size -= 4U;
- Array += 4U;
+ *((uint32_t *)pdata) = (hdsi->Instance->GPDR);
+ datasize -= 4U;
+ pdata += 4U;
}
-
+
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
-
+
return HAL_TIMEOUT;
- }
+ }
}
-
+
/* Process unlocked */
__HAL_UNLOCK(hdsi);
-
+
return HAL_OK;
}
/**
* @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL running
* (only data lanes are in ULPM)
- * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_EnterULPMData(DSI_HandleTypeDef *hdsi)
{
- uint32_t tickstart = 0U;
-
+ uint32_t tickstart;
+
/* Process locked */
__HAL_LOCK(hdsi);
-
+
/* ULPS Request on Data Lanes */
hdsi->Instance->PUCR |= DSI_PUCR_URDL;
-
- /* Get tick */
+
+ /* Get tick */
tickstart = HAL_GetTick();
-
+
/* Wait until the D-PHY active lanes enter into ULPM */
if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
{
- while((hdsi->Instance->PSR & DSI_PSR_UAN0) != RESET)
+ while((hdsi->Instance->PSR & DSI_PSR_UAN0) != RESET)
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
-
+
return HAL_TIMEOUT;
}
}
}
else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
{
- while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != RESET)
+ while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != RESET)
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
-
+
return HAL_TIMEOUT;
}
}
}
-
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_ERROR;
+ }
+
/* Process unlocked */
__HAL_UNLOCK(hdsi);
-
+
return HAL_OK;
}
/**
* @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL running
* (only data lanes are in ULPM)
- * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_ExitULPMData(DSI_HandleTypeDef *hdsi)
{
- uint32_t tickstart = 0U;
-
+ uint32_t tickstart;
+
/* Process locked */
__HAL_LOCK(hdsi);
-
+
/* Exit ULPS on Data Lanes */
hdsi->Instance->PUCR |= DSI_PUCR_UEDL;
-
- /* Get tick */
+
+ /* Get tick */
tickstart = HAL_GetTick();
-
+
/* Wait until all active lanes exit ULPM */
if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
{
- while((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0)
+ while((hdsi->Instance->PSR & DSI_PSR_UAN0) != DSI_PSR_UAN0)
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
-
+
return HAL_TIMEOUT;
}
}
}
else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
{
- while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1))
+ while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1))
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
-
+
return HAL_TIMEOUT;
}
}
}
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_ERROR;
+ }
/* wait for 1 ms*/
HAL_Delay(1U);
-
+
/* De-assert the ULPM requests and the ULPM exit bits */
hdsi->Instance->PUCR = 0U;
-
+
/* Process unlocked */
__HAL_UNLOCK(hdsi);
-
+
return HAL_OK;
}
/**
* @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off
* (both data and clock lanes are in ULPM)
- * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_EnterULPM(DSI_HandleTypeDef *hdsi)
{
- uint32_t tickstart = 0U;
-
+ uint32_t tickstart;
+
/* Process locked */
__HAL_LOCK(hdsi);
-
+
/* Clock lane configuration: no more HS request */
hdsi->Instance->CLCR &= ~DSI_CLCR_DPCC;
-
+
/* Use system PLL as byte lane clock source before stopping DSIPHY clock source */
__HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_PLLR);
-
+
/* ULPS Request on Clock and Data Lanes */
hdsi->Instance->PUCR |= (DSI_PUCR_URCL | DSI_PUCR_URDL);
-
- /* Get tick */
+
+ /* Get tick */
tickstart = HAL_GetTick();
-
+
/* Wait until all active lanes exit ULPM */
if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
{
- while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != RESET)
+ while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != RESET)
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
-
+
return HAL_TIMEOUT;
}
}
}
else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
{
- while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != RESET)
+ while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != RESET)
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
-
+
return HAL_TIMEOUT;
}
}
}
-
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_ERROR;
+ }
+
/* Turn off the DSI PLL */
__HAL_DSI_PLL_DISABLE(hdsi);
-
+
/* Process unlocked */
__HAL_UNLOCK(hdsi);
-
+
return HAL_OK;
}
/**
* @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off
* (both data and clock lanes are in ULPM)
- * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_ExitULPM(DSI_HandleTypeDef *hdsi)
{
- uint32_t tickstart = 0U;
-
+ uint32_t tickstart;
+
/* Process locked */
__HAL_LOCK(hdsi);
-
+
/* Turn on the DSI PLL */
__HAL_DSI_PLL_ENABLE(hdsi);
-
- /* Get tick */
+
+ /* Get tick */
tickstart = HAL_GetTick();
-
+
/* Wait for the lock of the PLL */
while(__HAL_DSI_GET_FLAG(hdsi, DSI_FLAG_PLLLS) == RESET)
{
@@ -1628,74 +1673,81 @@
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
-
+
return HAL_TIMEOUT;
}
}
-
+
/* Exit ULPS on Clock and Data Lanes */
hdsi->Instance->PUCR |= (DSI_PUCR_UECL | DSI_PUCR_UEDL);
-
- /* Get tick */
+
+ /* Get tick */
tickstart = HAL_GetTick();
-
+
/* Wait until all active lanes exit ULPM */
if((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_ONE_DATA_LANE)
{
- while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UANC))
+ while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UANC))
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
-
+
return HAL_TIMEOUT;
}
}
}
else if ((hdsi->Instance->PCONFR & DSI_PCONFR_NL) == DSI_TWO_DATA_LANES)
{
- while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC))
+ while((hdsi->Instance->PSR & (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC)) != (DSI_PSR_UAN0 | DSI_PSR_UAN1 | DSI_PSR_UANC))
{
/* Check for the Timeout */
if((HAL_GetTick() - tickstart ) > DSI_TIMEOUT_VALUE)
{
/* Process Unlocked */
__HAL_UNLOCK(hdsi);
-
+
return HAL_TIMEOUT;
}
}
}
-
- /* wait for 1 ms*/
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_ERROR;
+ }
+
+ /* wait for 1 ms */
HAL_Delay(1U);
-
+
/* De-assert the ULPM requests and the ULPM exit bits */
hdsi->Instance->PUCR = 0U;
-
+
/* Switch the lanbyteclock source in the RCC from system PLL to D-PHY */
__HAL_RCC_DSI_CONFIG(RCC_DSICLKSOURCE_DSIPHY);
-
+
/* Restore clock lane configuration to HS */
hdsi->Instance->CLCR |= DSI_CLCR_DPCC;
-
+
/* Process unlocked */
__HAL_UNLOCK(hdsi);
-
+
return HAL_OK;
}
/**
* @brief Start test pattern generation
- * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
- * @param Mode: Pattern generator mode
+ * @param Mode Pattern generator mode
* This parameter can be one of the following values:
* 0 : Color bars (horizontal or vertical)
* 1 : BER pattern (vertical only)
- * @param Orientation: Pattern generator orientation
+ * @param Orientation Pattern generator orientation
* This parameter can be one of the following values:
* 0 : Vertical color bars
* 1 : Horizontal color bars
@@ -1705,23 +1757,23 @@
{
/* Process locked */
__HAL_LOCK(hdsi);
-
+
/* Configure pattern generator mode and orientation */
hdsi->Instance->VMCR &= ~(DSI_VMCR_PGM | DSI_VMCR_PGO);
hdsi->Instance->VMCR |= ((Mode<<20U) | (Orientation<<24U));
-
+
/* Enable pattern generator by setting PGE bit */
hdsi->Instance->VMCR |= DSI_VMCR_PGE;
-
+
/* Process unlocked */
__HAL_UNLOCK(hdsi);
-
+
return HAL_OK;
}
/**
* @brief Stop test pattern generation
- * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @retval HAL status
*/
@@ -1729,36 +1781,36 @@
{
/* Process locked */
__HAL_LOCK(hdsi);
-
+
/* Disable pattern generator by clearing PGE bit */
hdsi->Instance->VMCR &= ~DSI_VMCR_PGE;
-
+
/* Process unlocked */
__HAL_UNLOCK(hdsi);
-
+
return HAL_OK;
}
/**
* @brief Set Slew-Rate And Delay Tuning
- * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
- * @param CommDelay: Communication delay to be adjusted.
+ * @param CommDelay Communication delay to be adjusted.
* This parameter can be any value of @ref DSI_Communication_Delay
- * @param Lane: select between clock or data lanes.
+ * @param Lane select between clock or data lanes.
* This parameter can be any value of @ref DSI_Lane_Group
- * @param Value: Custom value of the slew-rate or delay
+ * @param Value Custom value of the slew-rate or delay
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, uint32_t Value)
{
/* Process locked */
__HAL_LOCK(hdsi);
-
+
/* Check function parameters */
assert_param(IS_DSI_COMMUNICATION_DELAY(CommDelay));
assert_param(IS_DSI_LANE_GROUP(Lane));
-
+
switch(CommDelay)
{
case DSI_SLEW_RATE_HSTX:
@@ -1774,6 +1826,13 @@
hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXSRCDL;
hdsi->Instance->WPCR[1U] |= Value<<18U;
}
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_ERROR;
+ }
break;
case DSI_SLEW_RATE_LPTX:
if(Lane == DSI_CLOCK_LANE)
@@ -1788,6 +1847,13 @@
hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPSRCDL;
hdsi->Instance->WPCR[1U] |= Value<<8U;
}
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_ERROR;
+ }
break;
case DSI_HS_DELAY:
if(Lane == DSI_CLOCK_LANE)
@@ -1802,90 +1868,97 @@
hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_HSTXDDL;
hdsi->Instance->WPCR[1U] |= Value<<2U;
}
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_ERROR;
+ }
break;
default:
break;
}
-
+
/* Process unlocked */
__HAL_UNLOCK(hdsi);
-
+
return HAL_OK;
}
/**
* @brief Low-Power Reception Filter Tuning
- * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
- * @param Frequency: cutoff frequency of low-pass filter at the input of LPRX
+ * @param Frequency cutoff frequency of low-pass filter at the input of LPRX
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency)
{
/* Process locked */
__HAL_LOCK(hdsi);
-
+
/* Low-Power RX low-pass Filtering Tuning */
hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_LPRXFT;
hdsi->Instance->WPCR[1U] |= Frequency<<25U;
-
+
/* Process unlocked */
__HAL_UNLOCK(hdsi);
-
+
return HAL_OK;
}
/**
* @brief Activate an additional current path on all lanes to meet the SDDTx parameter
* defined in the MIPI D-PHY specification
- * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
- * @param State: ENABLE or DISABLE
+ * @param State ENABLE or DISABLE
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State)
{
/* Process locked */
__HAL_LOCK(hdsi);
-
+
/* Check function parameters */
assert_param(IS_FUNCTIONAL_STATE(State));
-
+
/* Activate/Disactivate additional current path on all lanes */
hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_SDDC;
hdsi->Instance->WPCR[1U] |= ((uint32_t)State << 12U);
-
+
/* Process unlocked */
__HAL_UNLOCK(hdsi);
-
+
return HAL_OK;
}
/**
* @brief Custom lane pins configuration
- * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
- * @param CustomLane: Function to be applyed on selected lane.
+ * @param CustomLane Function to be applyed on selected lane.
* This parameter can be any value of @ref DSI_CustomLane
- * @param Lane: select between clock or data lane 0 or data lane 1.
+ * @param Lane select between clock or data lane 0 or data lane 1.
* This parameter can be any value of @ref DSI_Lane_Select
- * @param State: ENABLE or DISABLE
+ * @param State ENABLE or DISABLE
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, FunctionalState State)
{
/* Process locked */
__HAL_LOCK(hdsi);
-
+
/* Check function parameters */
assert_param(IS_DSI_CUSTOM_LANE(CustomLane));
assert_param(IS_DSI_LANE(Lane));
assert_param(IS_FUNCTIONAL_STATE(State));
-
+
switch(CustomLane)
{
case DSI_SWAP_LANE_PINS:
- if(Lane == DSI_CLOCK_LANE)
+ if(Lane == DSI_CLK_LANE)
{
/* Swap pins on clock lane */
hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWCL;
@@ -1903,9 +1976,16 @@
hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_SWDL1;
hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 8U);
}
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_ERROR;
+ }
break;
case DSI_INVERT_HS_SIGNAL:
- if(Lane == DSI_CLOCK_LANE)
+ if(Lane == DSI_CLK_LANE)
{
/* Invert HS signal on clock lane */
hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSICL;
@@ -1923,183 +2003,190 @@
hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_HSIDL1;
hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 11U);
}
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_ERROR;
+ }
break;
default:
break;
}
-
+
/* Process unlocked */
__HAL_UNLOCK(hdsi);
-
+
return HAL_OK;
}
/**
* @brief Set custom timing for the PHY
- * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
- * @param Timing: PHY timing to be adjusted.
+ * @param Timing PHY timing to be adjusted.
* This parameter can be any value of @ref DSI_PHY_Timing
- * @param State: ENABLE or DISABLE
- * @param Value: Custom value of the timing
+ * @param State ENABLE or DISABLE
+ * @param Value Custom value of the timing
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value)
{
/* Process locked */
__HAL_LOCK(hdsi);
-
+
/* Check function parameters */
assert_param(IS_DSI_PHY_TIMING(Timing));
assert_param(IS_FUNCTIONAL_STATE(State));
-
+
switch(Timing)
{
case DSI_TCLK_POST:
/* Enable/Disable custom timing setting */
hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPOSTEN;
hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 27U);
-
- if(State)
+
+ if(State != DISABLE)
{
/* Set custom value */
hdsi->Instance->WPCR[4U] &= ~DSI_WPCR4_TCLKPOST;
hdsi->Instance->WPCR[4U] |= Value & DSI_WPCR4_TCLKPOST;
}
-
+
break;
case DSI_TLPX_CLK:
/* Enable/Disable custom timing setting */
hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXCEN;
hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 26U);
-
- if(State)
+
+ if(State != DISABLE)
{
/* Set custom value */
hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXC;
hdsi->Instance->WPCR[3U] |= (Value << 24U) & DSI_WPCR3_TLPXC;
}
-
+
break;
case DSI_THS_EXIT:
/* Enable/Disable custom timing setting */
hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSEXITEN;
hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 25U);
-
- if(State)
+
+ if(State != DISABLE)
{
/* Set custom value */
hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSEXIT;
hdsi->Instance->WPCR[3U] |= (Value << 16U) & DSI_WPCR3_THSEXIT;
}
-
+
break;
case DSI_TLPX_DATA:
/* Enable/Disable custom timing setting */
hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TLPXDEN;
hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 24U);
-
- if(State)
+
+ if(State != DISABLE)
{
/* Set custom value */
hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_TLPXD;
hdsi->Instance->WPCR[3U] |= (Value << 8U) & DSI_WPCR3_TLPXD;
}
-
+
break;
case DSI_THS_ZERO:
/* Enable/Disable custom timing setting */
hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSZEROEN;
hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 23U);
-
- if(State)
+
+ if(State != DISABLE)
{
/* Set custom value */
hdsi->Instance->WPCR[3U] &= ~DSI_WPCR3_THSZERO;
hdsi->Instance->WPCR[3U] |= Value & DSI_WPCR3_THSZERO;
}
-
+
break;
case DSI_THS_TRAIL:
/* Enable/Disable custom timing setting */
hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSTRAILEN;
hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 22U);
-
- if(State)
+
+ if(State != DISABLE)
{
/* Set custom value */
hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSTRAIL;
hdsi->Instance->WPCR[2U] |= (Value << 24U) & DSI_WPCR2_THSTRAIL;
}
-
+
break;
case DSI_THS_PREPARE:
/* Enable/Disable custom timing setting */
hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_THSPREPEN;
hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 21U);
-
- if(State)
+
+ if(State != DISABLE)
{
/* Set custom value */
hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_THSPREP;
hdsi->Instance->WPCR[2U] |= (Value << 16U) & DSI_WPCR2_THSPREP;
}
-
+
break;
case DSI_TCLK_ZERO:
/* Enable/Disable custom timing setting */
hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKZEROEN;
hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 20U);
-
- if(State)
+
+ if(State != DISABLE)
{
/* Set custom value */
hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKZERO;
hdsi->Instance->WPCR[2U] |= (Value << 8U) & DSI_WPCR2_TCLKZERO;
}
-
+
break;
case DSI_TCLK_PREPARE:
/* Enable/Disable custom timing setting */
hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TCLKPREPEN;
hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 19U);
-
- if(State)
+
+ if(State != DISABLE)
{
/* Set custom value */
hdsi->Instance->WPCR[2U] &= ~DSI_WPCR2_TCLKPREP;
hdsi->Instance->WPCR[2U] |= Value & DSI_WPCR2_TCLKPREP;
}
-
+
break;
default:
break;
}
-
+
/* Process unlocked */
__HAL_UNLOCK(hdsi);
-
+
return HAL_OK;
}
/**
* @brief Force the Clock/Data Lane in TX Stop Mode
- * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
- * @param Lane: select between clock or data lanes.
+ * @param Lane select between clock or data lanes.
* This parameter can be any value of @ref DSI_Lane_Group
- * @param State: ENABLE or DISABLE
+ * @param State ENABLE or DISABLE
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State)
{
/* Process locked */
__HAL_LOCK(hdsi);
-
+
/* Check function parameters */
assert_param(IS_DSI_LANE_GROUP(Lane));
assert_param(IS_FUNCTIONAL_STATE(State));
-
+
if(Lane == DSI_CLOCK_LANE)
{
/* Force/Unforce the Clock Lane in TX Stop Mode */
@@ -2112,110 +2199,117 @@
hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_FTXSMDL;
hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 13U);
}
-
+ else
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hdsi);
+
+ return HAL_ERROR;
+ }
+
/* Process unlocked */
__HAL_UNLOCK(hdsi);
-
+
return HAL_OK;
}
/**
- * @brief Forces LP Receiver in Low-Power Mode
- * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * @brief Force LP Receiver in Low-Power Mode
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
- * @param State: ENABLE or DISABLE
+ * @param State ENABLE or DISABLE
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State)
{
/* Process locked */
__HAL_LOCK(hdsi);
-
+
/* Check function parameters */
assert_param(IS_FUNCTIONAL_STATE(State));
-
+
/* Force/Unforce LP Receiver in Low-Power Mode */
hdsi->Instance->WPCR[1U] &= ~DSI_WPCR1_FLPRXLPM;
hdsi->Instance->WPCR[1U] |= ((uint32_t)State << 22U);
-
+
/* Process unlocked */
__HAL_UNLOCK(hdsi);
-
+
return HAL_OK;
}
/**
* @brief Force Data Lanes in RX Mode after a BTA
- * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
- * @param State: ENABLE or DISABLE
+ * @param State ENABLE or DISABLE
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State)
{
/* Process locked */
__HAL_LOCK(hdsi);
-
+
/* Check function parameters */
assert_param(IS_FUNCTIONAL_STATE(State));
-
+
/* Force Data Lanes in RX Mode */
hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_TDDL;
hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 16U);
-
+
/* Process unlocked */
__HAL_UNLOCK(hdsi);
-
+
return HAL_OK;
}
/**
* @brief Enable a pull-down on the lanes to prevent from floating states when unused
- * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
- * @param State: ENABLE or DISABLE
+ * @param State ENABLE or DISABLE
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State)
{
/* Process locked */
__HAL_LOCK(hdsi);
-
+
/* Check function parameters */
assert_param(IS_FUNCTIONAL_STATE(State));
-
+
/* Enable/Disable pull-down on lanes */
hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_PDEN;
hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 18U);
-
+
/* Process unlocked */
__HAL_UNLOCK(hdsi);
-
+
return HAL_OK;
}
/**
* @brief Switch off the contention detection on data lanes
- * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
- * @param State: ENABLE or DISABLE
+ * @param State ENABLE or DISABLE
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State)
{
/* Process locked */
__HAL_LOCK(hdsi);
-
+
/* Check function parameters */
assert_param(IS_FUNCTIONAL_STATE(State));
-
+
/* Contention Detection on Data Lanes OFF */
hdsi->Instance->WPCR[0U] &= ~DSI_WPCR0_CDOFFDL;
hdsi->Instance->WPCR[0U] |= ((uint32_t)State << 14U);
-
+
/* Process unlocked */
__HAL_UNLOCK(hdsi);
-
+
return HAL_OK;
}
@@ -2224,24 +2318,24 @@
*/
/** @defgroup DSI_Group4 Peripheral State and Errors functions
- * @brief Peripheral State and Errors functions
+ * @brief Peripheral State and Errors functions
*
-@verbatim
+@verbatim
===============================================================================
##### Peripheral State and Errors functions #####
- ===============================================================================
+ ===============================================================================
[..]
This subsection provides functions allowing to
(+) Check the DSI state.
- (+) Get error code.
+ (+) Get error code.
@endverbatim
* @{
- */
+ */
/**
* @brief Return the DSI state
- * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
* the configuration information for the DSI.
* @retval HAL state
*/
@@ -2251,20 +2345,35 @@
}
/**
- * @}
+ * @brief Return the DSI error code
+ * @param hdsi pointer to a DSI_HandleTypeDef structure that contains
+ * the configuration information for the DSI.
+ * @retval DSI Error Code
*/
+uint32_t HAL_DSI_GetError(DSI_HandleTypeDef *hdsi)
+{
+ /* Get the error code */
+ return hdsi->ErrorCode;
+}
/**
* @}
*/
-#endif /* STM32F469xx || STM32F479xx */
-#endif /* HAL_DSI_MODULE_ENABLED */
-/**
- * @}
- */
/**
* @}
*/
+/**
+ * @}
+ */
+
+#endif /* DSI */
+
+#endif /* HAL_DSI_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dsi.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_dsi.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_dsi.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief Header file of DSI HAL module.
******************************************************************************
* @attention
@@ -43,7 +41,7 @@
extern "C" {
#endif
-#if defined(STM32F469xx) || defined(STM32F479xx)
+#if defined(DSI)
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal_def.h"
@@ -54,10 +52,10 @@
/** @defgroup DSI DSI
* @brief DSI HAL module driver
* @{
- */
+ */
/* Exported types ------------------------------------------------------------*/
-/**
+/**
* @brief DSI Init Structure definition
*/
typedef struct
@@ -73,8 +71,8 @@
}DSI_InitTypeDef;
-/**
- * @brief DSI PLL Clock structure definition
+/**
+ * @brief DSI PLL Clock structure definition
*/
typedef struct
{
@@ -89,95 +87,95 @@
}DSI_PLLInitTypeDef;
-/**
+/**
* @brief DSI Video mode configuration
*/
-typedef struct
+typedef struct
{
uint32_t VirtualChannelID; /*!< Virtual channel ID */
-
+
uint32_t ColorCoding; /*!< Color coding for LTDC interface
This parameter can be any value of @ref DSI_Color_Coding */
-
+
uint32_t LooselyPacked; /*!< Enable or disable loosely packed stream (needed only when using
18-bit configuration).
This parameter can be any value of @ref DSI_LooselyPacked */
-
+
uint32_t Mode; /*!< Video mode type
This parameter can be any value of @ref DSI_Video_Mode_Type */
-
+
uint32_t PacketSize; /*!< Video packet size */
-
+
uint32_t NumberOfChunks; /*!< Number of chunks */
-
+
uint32_t NullPacketSize; /*!< Null packet size */
-
+
uint32_t HSPolarity; /*!< HSYNC pin polarity
This parameter can be any value of @ref DSI_HSYNC_Polarity */
-
+
uint32_t VSPolarity; /*!< VSYNC pin polarity
This parameter can be any value of @ref DSI_VSYNC_Active_Polarity */
-
+
uint32_t DEPolarity; /*!< Data Enable pin polarity
This parameter can be any value of @ref DSI_DATA_ENABLE_Polarity */
-
+
uint32_t HorizontalSyncActive; /*!< Horizontal synchronism active duration (in lane byte clock cycles) */
-
+
uint32_t HorizontalBackPorch; /*!< Horizontal back-porch duration (in lane byte clock cycles) */
-
+
uint32_t HorizontalLine; /*!< Horizontal line duration (in lane byte clock cycles) */
-
+
uint32_t VerticalSyncActive; /*!< Vertical synchronism active duration */
-
+
uint32_t VerticalBackPorch; /*!< Vertical back-porch duration */
-
+
uint32_t VerticalFrontPorch; /*!< Vertical front-porch duration */
-
+
uint32_t VerticalActive; /*!< Vertical active duration */
-
+
uint32_t LPCommandEnable; /*!< Low-power command enable
This parameter can be any value of @ref DSI_LP_Command */
-
+
uint32_t LPLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that
can fit in a line during VSA, VBP and VFP regions */
-
+
uint32_t LPVACTLargestPacketSize; /*!< The size, in bytes, of the low power largest packet that
can fit in a line during VACT region */
-
+
uint32_t LPHorizontalFrontPorchEnable; /*!< Low-power horizontal front-porch enable
This parameter can be any value of @ref DSI_LP_HFP */
-
+
uint32_t LPHorizontalBackPorchEnable; /*!< Low-power horizontal back-porch enable
This parameter can be any value of @ref DSI_LP_HBP */
-
+
uint32_t LPVerticalActiveEnable; /*!< Low-power vertical active enable
This parameter can be any value of @ref DSI_LP_VACT */
-
+
uint32_t LPVerticalFrontPorchEnable; /*!< Low-power vertical front-porch enable
This parameter can be any value of @ref DSI_LP_VFP */
-
+
uint32_t LPVerticalBackPorchEnable; /*!< Low-power vertical back-porch enable
This parameter can be any value of @ref DSI_LP_VBP */
-
+
uint32_t LPVerticalSyncActiveEnable; /*!< Low-power vertical sync active enable
This parameter can be any value of @ref DSI_LP_VSYNC */
-
+
uint32_t FrameBTAAcknowledgeEnable; /*!< Frame bus-turn-around acknowledge enable
This parameter can be any value of @ref DSI_FBTA_acknowledge */
-
+
}DSI_VidCfgTypeDef;
-/**
+/**
* @brief DSI Adapted command mode configuration
*/
-typedef struct
+typedef struct
{
uint32_t VirtualChannelID; /*!< Virtual channel ID */
uint32_t ColorCoding; /*!< Color coding for LTDC interface
This parameter can be any value of @ref DSI_Color_Coding */
- uint32_t CommandSize; /*!< Maximum allowed size for an LTDC write memory command, measured in
+ uint32_t CommandSize; /*!< Maximum allowed size for an LTDC write memory command, measured in
pixels. This parameter can be any value between 0x00 and 0xFFFFU */
uint32_t TearingEffectSource; /*!< Tearing effect source
@@ -206,10 +204,10 @@
}DSI_CmdCfgTypeDef;
-/**
+/**
* @brief DSI command transmission mode configuration
*/
-typedef struct
+typedef struct
{
uint32_t LPGenShortWriteNoP; /*!< Generic Short Write Zero parameters Transmission
This parameter can be any value of @ref DSI_LP_LPGenShortWriteNoP */
@@ -252,10 +250,10 @@
}DSI_LPCmdTypeDef;
-/**
+/**
* @brief DSI PHY Timings definition
*/
-typedef struct
+typedef struct
{
uint32_t ClockLaneHS2LPTime; /*!< The maximum time that the D-PHY clock lane takes to go from high-speed
to low-power transmission */
@@ -276,10 +274,10 @@
}DSI_PHY_TimerTypeDef;
-/**
+/**
* @brief DSI HOST Timeouts definition
*/
-typedef struct
+typedef struct
{
uint32_t TimeoutCkdiv; /*!< Time-out clock division */
@@ -305,7 +303,7 @@
/**
* @brief DSI States Structure definition
*/
-typedef enum
+typedef enum
{
HAL_DSI_STATE_RESET = 0x00U,
HAL_DSI_STATE_READY = 0x01U,
@@ -863,7 +861,7 @@
/** @defgroup DSI_Lane_Select DSI Lane Select
* @{
*/
-#define DSI_CLOCK_LANE 0x00000000U
+#define DSI_CLK_LANE 0x00000000U
#define DSI_DATA_LANE0 0x00000001U
#define DSI_DATA_LANE1 0x00000002U
/**
@@ -889,67 +887,115 @@
/* Exported macros -----------------------------------------------------------*/
/**
* @brief Enables the DSI host.
- * @param __HANDLE__: DSI handle
+ * @param __HANDLE__ DSI handle
* @retval None.
*/
-#define __HAL_DSI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DSI_CR_EN)
+#define __HAL_DSI_ENABLE(__HANDLE__) do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
+ /* Delay after an DSI Host enabling */ \
+ tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
+ UNUSED(tmpreg); \
+ }while(0U)
/**
* @brief Disables the DSI host.
- * @param __HANDLE__: DSI handle
+ * @param __HANDLE__ DSI handle
* @retval None.
*/
-#define __HAL_DSI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DSI_CR_EN)
+#define __HAL_DSI_DISABLE(__HANDLE__) do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ CLEAR_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
+ /* Delay after an DSI Host disabling */ \
+ tmpreg = READ_BIT((__HANDLE__)->Instance->CR, DSI_CR_EN);\
+ UNUSED(tmpreg); \
+ }while(0U)
/**
* @brief Enables the DSI wrapper.
- * @param __HANDLE__: DSI handle
+ * @param __HANDLE__ DSI handle
* @retval None.
*/
-#define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->WCR |= DSI_WCR_DSIEN)
+#define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
+ /* Delay after an DSI warpper enabling */ \
+ tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
+ UNUSED(tmpreg); \
+ }while(0U)
/**
* @brief Disable the DSI wrapper.
- * @param __HANDLE__: DSI handle
+ * @param __HANDLE__ DSI handle
* @retval None.
*/
-#define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->WCR &= ~DSI_WCR_DSIEN)
+#define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ CLEAR_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
+ /* Delay after an DSI warpper disabling*/ \
+ tmpreg = READ_BIT((__HANDLE__)->Instance->WCR, DSI_WCR_DSIEN);\
+ UNUSED(tmpreg); \
+ }while(0U)
/**
* @brief Enables the DSI PLL.
- * @param __HANDLE__: DSI handle
+ * @param __HANDLE__ DSI handle
* @retval None.
*/
-#define __HAL_DSI_PLL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR |= DSI_WRPCR_PLLEN)
+#define __HAL_DSI_PLL_ENABLE(__HANDLE__) do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
+ /* Delay after an DSI PLL enabling */ \
+ tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
+ UNUSED(tmpreg); \
+ }while(0U)
/**
* @brief Disables the DSI PLL.
- * @param __HANDLE__: DSI handle
+ * @param __HANDLE__ DSI handle
* @retval None.
*/
-#define __HAL_DSI_PLL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR &= ~DSI_WRPCR_PLLEN)
+#define __HAL_DSI_PLL_DISABLE(__HANDLE__) do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
+ /* Delay after an DSI PLL disabling */ \
+ tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_PLLEN);\
+ UNUSED(tmpreg); \
+ }while(0U)
/**
* @brief Enables the DSI regulator.
- * @param __HANDLE__: DSI handle
+ * @param __HANDLE__ DSI handle
* @retval None.
*/
-#define __HAL_DSI_REG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR |= DSI_WRPCR_REGEN)
+#define __HAL_DSI_REG_ENABLE(__HANDLE__) do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ SET_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
+ /* Delay after an DSI regulator enabling */ \
+ tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
+ UNUSED(tmpreg); \
+ }while(0U)
/**
* @brief Disables the DSI regulator.
- * @param __HANDLE__: DSI handle
+ * @param __HANDLE__ DSI handle
* @retval None.
*/
-#define __HAL_DSI_REG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR &= ~DSI_WRPCR_REGEN)
+#define __HAL_DSI_REG_DISABLE(__HANDLE__) do { \
+ __IO uint32_t tmpreg = 0x00U; \
+ CLEAR_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
+ /* Delay after an DSI regulator disabling */ \
+ tmpreg = READ_BIT((__HANDLE__)->Instance->WRPCR, DSI_WRPCR_REGEN);\
+ UNUSED(tmpreg); \
+ }while(0U)
/**
* @brief Get the DSI pending flags.
- * @param __HANDLE__: DSI handle.
- * @param __FLAG__: Get the specified flag.
+ * @param __HANDLE__ DSI handle.
+ * @param __FLAG__ Get the specified flag.
* This parameter can be any combination of the following values:
- * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag
- * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag
+ * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag
+ * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag
* @arg DSI_FLAG_BUSY : Busy Flag
* @arg DSI_FLAG_PLLLS: PLL Lock Status
* @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag
@@ -962,11 +1008,11 @@
/**
* @brief Clears the DSI pending flags.
- * @param __HANDLE__: DSI handle.
- * @param __FLAG__: specifies the flag to clear.
+ * @param __HANDLE__ DSI handle.
+ * @param __FLAG__ specifies the flag to clear.
* This parameter can be any combination of the following values:
- * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag
- * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag
+ * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag
+ * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag
* @arg DSI_FLAG_PLLL : PLL Lock Interrupt Flag
* @arg DSI_FLAG_PLLU : PLL Unlock Interrupt Flag
* @arg DSI_FLAG_RR : Regulator Ready Interrupt Flag
@@ -976,8 +1022,8 @@
/**
* @brief Enables the specified DSI interrupts.
- * @param __HANDLE__: DSI handle.
- * @param __INTERRUPT__: specifies the DSI interrupt sources to be enabled.
+ * @param __HANDLE__ DSI handle.
+ * @param __INTERRUPT__ specifies the DSI interrupt sources to be enabled.
* This parameter can be any combination of the following values:
* @arg DSI_IT_TE : Tearing Effect Interrupt
* @arg DSI_IT_ER : End of Refresh Interrupt
@@ -990,8 +1036,8 @@
/**
* @brief Disables the specified DSI interrupts.
- * @param __HANDLE__: DSI handle
- * @param __INTERRUPT__: specifies the DSI interrupt sources to be disabled.
+ * @param __HANDLE__ DSI handle
+ * @param __INTERRUPT__ specifies the DSI interrupt sources to be disabled.
* This parameter can be any combination of the following values:
* @arg DSI_IT_TE : Tearing Effect Interrupt
* @arg DSI_IT_ER : End of Refresh Interrupt
@@ -1003,9 +1049,9 @@
#define __HAL_DSI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->WIER &= ~(__INTERRUPT__))
/**
- * @brief Checks whether the specified DSI interrupt has occurred or not.
- * @param __HANDLE__: DSI handle
- * @param __INTERRUPT__: specifies the DSI interrupt source to check.
+ * @brief Checks whether the specified DSI interrupt source is enabled or not.
+ * @param __HANDLE__ DSI handle
+ * @param __INTERRUPT__ specifies the DSI interrupt source to check.
* This parameter can be one of the following values:
* @arg DSI_IT_TE : Tearing Effect Interrupt
* @arg DSI_IT_ER : End of Refresh Interrupt
@@ -1093,7 +1139,7 @@
/**
* @}
- */
+ */
/* Private defines -----------------------------------------------------------*/
/** @defgroup DSI_Private_Defines DSI Private Defines
@@ -1102,8 +1148,8 @@
/**
* @}
- */
-
+ */
+
/* Private variables ---------------------------------------------------------*/
/** @defgroup DSI_Private_Variables DSI Private Variables
* @{
@@ -1111,16 +1157,16 @@
/**
* @}
- */
+ */
/* Private constants ---------------------------------------------------------*/
/** @defgroup DSI_Private_Constants DSI Private Constants
* @{
*/
-#define DSI_MAX_RETURN_PKT_SIZE ((uint32_t)0x00000037U) /*!< Maximum return packet configuration */
+#define DSI_MAX_RETURN_PKT_SIZE (0x00000037U) /*!< Maximum return packet configuration */
/**
* @}
- */
+ */
/* Private macros ------------------------------------------------------------*/
/** @defgroup DSI_Private_Macros DSI Private Macros
@@ -1204,7 +1250,7 @@
/**
* @}
- */
+ */
/* Private functions prototypes ----------------------------------------------*/
/** @defgroup DSI_Private_Functions_Prototypes DSI Private Functions Prototypes
@@ -1231,8 +1277,8 @@
/**
* @}
*/
-#endif /* STM32F469xx || STM32F479xx */
-
+#endif /* DSI */
+
#ifdef __cplusplus
}
#endif
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_eth.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_eth.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_eth.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief ETH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Ethernet (ETH) peripheral: @@ -173,7 +171,7 @@ /** * @brief Initializes the Ethernet MAC and DMA according to default * parameters. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL status */ @@ -445,7 +443,7 @@ /** * @brief De-Initializes the ETH peripheral. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL status */ @@ -469,11 +467,11 @@ /** * @brief Initializes the DMA Tx descriptors in chain mode. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @param DMATxDescTab: Pointer to the first Tx desc list - * @param TxBuff: Pointer to the first TxBuffer list - * @param TxBuffCount: Number of the used Tx desc in the list + * @param DMATxDescTab Pointer to the first Tx desc list + * @param TxBuff Pointer to the first TxBuffer list + * @param TxBuffCount Number of the used Tx desc in the list * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount) @@ -536,11 +534,11 @@ /** * @brief Initializes the DMA Rx descriptors in chain mode. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @param DMARxDescTab: Pointer to the first Rx desc list - * @param RxBuff: Pointer to the first RxBuffer list - * @param RxBuffCount: Number of the used Rx desc in the list + * @param DMARxDescTab Pointer to the first Rx desc list + * @param RxBuff Pointer to the first RxBuffer list + * @param RxBuffCount Number of the used Rx desc in the list * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount) @@ -606,7 +604,7 @@ /** * @brief Initializes the ETH MSP. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ @@ -621,7 +619,7 @@ /** * @brief DeInitializes ETH MSP. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ @@ -663,9 +661,9 @@ /** * @brief Sends an Ethernet frame. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @param FrameLength: Amount of data to be sent + * @param FrameLength Amount of data to be sent * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength) @@ -777,7 +775,7 @@ /** * @brief Checks for received frames. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL status */ @@ -857,7 +855,7 @@ /** * @brief Gets the Received frame in interrupt mode. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL status */ @@ -942,7 +940,7 @@ /** * @brief This function handles ETH interrupt request. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL status */ @@ -1002,7 +1000,7 @@ /** * @brief Tx Transfer completed callbacks. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ @@ -1017,7 +1015,7 @@ /** * @brief Rx Transfer completed callbacks. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ @@ -1032,7 +1030,7 @@ /** * @brief Ethernet transfer error callbacks - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ @@ -1047,14 +1045,14 @@ /** * @brief Reads a PHY register - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @param PHYReg: PHY register address, is the index of one of the 32 PHY register. + * @param PHYReg PHY register address, is the index of one of the 32 PHY register. * This parameter can be one of the following values: * PHY_BCR: Transceiver Basic Control Register, * PHY_BSR: Transceiver Basic Status Register. * More PHY register could be read depending on the used PHY - * @param RegValue: PHY register value + * @param RegValue PHY register value * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue) @@ -1120,13 +1118,13 @@ /** * @brief Writes to a PHY register. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @param PHYReg: PHY register address, is the index of one of the 32 PHY register. + * @param PHYReg PHY register address, is the index of one of the 32 PHY register. * This parameter can be one of the following values: * PHY_BCR: Transceiver Control Register. * More PHY register could be written depending on the used PHY - * @param RegValue: the value to write + * @param RegValue the value to write * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue) @@ -1217,7 +1215,7 @@ /** * @brief Enables Ethernet MAC and DMA reception/transmission - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL status */ @@ -1256,7 +1254,7 @@ /** * @brief Stop Ethernet MAC and DMA reception/transmission - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL status */ @@ -1295,9 +1293,9 @@ /** * @brief Set ETH MAC Configuration. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @param macconf: MAC Configuration structure + * @param macconf MAC Configuration structure * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf) @@ -1462,9 +1460,9 @@ /** * @brief Sets ETH DMA Configuration. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @param dmaconf: DMA Configuration structure + * @param dmaconf DMA Configuration structure * @retval HAL status */ HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf) @@ -1570,7 +1568,7 @@ /** * @brief Return the ETH HAL state - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval HAL state */ @@ -1594,9 +1592,9 @@ /** * @brief Configures Ethernet MAC and DMA with default parameters. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @param err: Ethernet Init error + * @param err Ethernet Init error * @retval HAL status */ static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err) @@ -1851,15 +1849,15 @@ /** * @brief Configures the selected MAC address. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module - * @param MacAddr: The MAC address to configure + * @param MacAddr The MAC address to configure * This parameter can be one of the following values: * @arg ETH_MAC_Address0: MAC Address0 * @arg ETH_MAC_Address1: MAC Address1 * @arg ETH_MAC_Address2: MAC Address2 * @arg ETH_MAC_Address3: MAC Address3 - * @param Addr: Pointer to MAC address buffer data (6 bytes) + * @param Addr Pointer to MAC address buffer data (6 bytes) * @retval HAL status */ static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr) @@ -1885,7 +1883,7 @@ /** * @brief Enables the MAC transmission. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ @@ -1905,7 +1903,7 @@ /** * @brief Disables the MAC transmission. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ @@ -1925,7 +1923,7 @@ /** * @brief Enables the MAC reception. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ @@ -1945,7 +1943,7 @@ /** * @brief Disables the MAC reception. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ @@ -1965,7 +1963,7 @@ /** * @brief Enables the DMA transmission. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ @@ -1977,7 +1975,7 @@ /** * @brief Disables the DMA transmission. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ @@ -1989,7 +1987,7 @@ /** * @brief Enables the DMA reception. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ @@ -2001,7 +1999,7 @@ /** * @brief Disables the DMA reception. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ @@ -2013,7 +2011,7 @@ /** * @brief Clears the ETHERNET transmit FIFO. - * @param heth: pointer to a ETH_HandleTypeDef structure that contains + * @param heth pointer to a ETH_HandleTypeDef structure that contains * the configuration information for ETHERNET module * @retval None */ @@ -2033,7 +2031,7 @@ /** * @brief This function provides delay (in milliseconds) based on CPU cycles method. - * @param mdelay: specifies the delay time length, in milliseconds. + * @param mdelay specifies the delay time length, in milliseconds. * @retval None */ static void ETH_Delay(uint32_t mdelay)
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_eth.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_eth.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_eth.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief Header file of ETH HAL module.
******************************************************************************
* @attention
@@ -1589,80 +1587,80 @@
*/
/** @brief Reset ETH handle state
- * @param __HANDLE__: specifies the ETH handle.
+ * @param __HANDLE__ specifies the ETH handle.
* @retval None
*/
#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
/**
* @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
- * @param __HANDLE__: ETH Handle
- * @param __FLAG__: specifies the flag of TDES0 to check.
+ * @param __HANDLE__ ETH Handle
+ * @param __FLAG__ specifies the flag of TDES0 to check.
* @retval the ETH_DMATxDescFlag (SET or RESET).
*/
#define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
/**
* @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.
- * @param __HANDLE__: ETH Handle
- * @param __FLAG__: specifies the flag of RDES0 to check.
+ * @param __HANDLE__ ETH Handle
+ * @param __FLAG__ specifies the flag of RDES0 to check.
* @retval the ETH_DMATxDescFlag (SET or RESET).
*/
#define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
/**
* @brief Enables the specified DMA Rx Desc receive interrupt.
- * @param __HANDLE__: ETH Handle
+ * @param __HANDLE__ ETH Handle
* @retval None
*/
#define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
/**
* @brief Disables the specified DMA Rx Desc receive interrupt.
- * @param __HANDLE__: ETH Handle
+ * @param __HANDLE__ ETH Handle
* @retval None
*/
#define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC)
/**
* @brief Set the specified DMA Rx Desc Own bit.
- * @param __HANDLE__: ETH Handle
+ * @param __HANDLE__ ETH Handle
* @retval None
*/
#define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN)
/**
* @brief Returns the specified ETHERNET DMA Tx Desc collision count.
- * @param __HANDLE__: ETH Handle
+ * @param __HANDLE__ ETH Handle
* @retval The Transmit descriptor collision counter value.
*/
#define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
/**
* @brief Set the specified DMA Tx Desc Own bit.
- * @param __HANDLE__: ETH Handle
+ * @param __HANDLE__ ETH Handle
* @retval None
*/
#define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN)
/**
* @brief Enables the specified DMA Tx Desc Transmit interrupt.
- * @param __HANDLE__: ETH Handle
+ * @param __HANDLE__ ETH Handle
* @retval None
*/
#define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC)
/**
* @brief Disables the specified DMA Tx Desc Transmit interrupt.
- * @param __HANDLE__: ETH Handle
+ * @param __HANDLE__ ETH Handle
* @retval None
*/
#define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
/**
* @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
- * @param __HANDLE__: ETH Handle
- * @param __CHECKSUM__: specifies is the DMA Tx desc checksum insertion.
+ * @param __HANDLE__ ETH Handle
+ * @param __CHECKSUM__ specifies is the DMA Tx desc checksum insertion.
* This parameter can be one of the following values:
* @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass
* @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum
@@ -1674,36 +1672,36 @@
/**
* @brief Enables the DMA Tx Desc CRC.
- * @param __HANDLE__: ETH Handle
+ * @param __HANDLE__ ETH Handle
* @retval None
*/
#define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
/**
* @brief Disables the DMA Tx Desc CRC.
- * @param __HANDLE__: ETH Handle
+ * @param __HANDLE__ ETH Handle
* @retval None
*/
#define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC)
/**
* @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes.
- * @param __HANDLE__: ETH Handle
+ * @param __HANDLE__ ETH Handle
* @retval None
*/
#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
/**
* @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes.
- * @param __HANDLE__: ETH Handle
+ * @param __HANDLE__ ETH Handle
* @retval None
*/
#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP)
/**
* @brief Enables the specified ETHERNET MAC interrupts.
- * @param __HANDLE__ : ETH Handle
- * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
+ * @param __HANDLE__ ETH Handle
+ * @param __INTERRUPT__ specifies the ETHERNET MAC interrupt sources to be
* enabled or disabled.
* This parameter can be any combination of the following values:
* @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
@@ -1714,8 +1712,8 @@
/**
* @brief Disables the specified ETHERNET MAC interrupts.
- * @param __HANDLE__ : ETH Handle
- * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
+ * @param __HANDLE__ ETH Handle
+ * @param __INTERRUPT__ specifies the ETHERNET MAC interrupt sources to be
* enabled or disabled.
* This parameter can be any combination of the following values:
* @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
@@ -1726,36 +1724,36 @@
/**
* @brief Initiate a Pause Control Frame (Full-duplex only).
- * @param __HANDLE__: ETH Handle
+ * @param __HANDLE__ ETH Handle
* @retval None
*/
#define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
/**
* @brief Checks whether the ETHERNET flow control busy bit is set or not.
- * @param __HANDLE__: ETH Handle
+ * @param __HANDLE__ ETH Handle
* @retval The new state of flow control busy status bit (SET or RESET).
*/
#define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
/**
* @brief Enables the MAC Back Pressure operation activation (Half-duplex only).
- * @param __HANDLE__: ETH Handle
+ * @param __HANDLE__ ETH Handle
* @retval None
*/
#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
/**
* @brief Disables the MAC BackPressure operation activation (Half-duplex only).
- * @param __HANDLE__: ETH Handle
+ * @param __HANDLE__ ETH Handle
* @retval None
*/
#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
/**
* @brief Checks whether the specified ETHERNET MAC flag is set or not.
- * @param __HANDLE__: ETH Handle
- * @param __FLAG__: specifies the flag to check.
+ * @param __HANDLE__ ETH Handle
+ * @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
* @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
@@ -1768,8 +1766,8 @@
/**
* @brief Enables the specified ETHERNET DMA interrupts.
- * @param __HANDLE__ : ETH Handle
- * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
+ * @param __HANDLE__ ETH Handle
+ * @param __INTERRUPT__ specifies the ETHERNET DMA interrupt sources to be
* enabled @ref ETH_DMA_Interrupts
* @retval None
*/
@@ -1777,8 +1775,8 @@
/**
* @brief Disables the specified ETHERNET DMA interrupts.
- * @param __HANDLE__ : ETH Handle
- * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
+ * @param __HANDLE__ ETH Handle
+ * @param __INTERRUPT__ specifies the ETHERNET DMA interrupt sources to be
* disabled. @ref ETH_DMA_Interrupts
* @retval None
*/
@@ -1786,32 +1784,32 @@
/**
* @brief Clears the ETHERNET DMA IT pending bit.
- * @param __HANDLE__ : ETH Handle
- * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
+ * @param __HANDLE__ ETH Handle
+ * @param __INTERRUPT__ specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
* @retval None
*/
#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
/**
* @brief Checks whether the specified ETHERNET DMA flag is set or not.
-* @param __HANDLE__: ETH Handle
- * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Flags
+* @param __HANDLE__ ETH Handle
+ * @param __FLAG__ specifies the flag to check. @ref ETH_DMA_Flags
* @retval The new state of ETH_DMA_FLAG (SET or RESET).
*/
#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
/**
* @brief Checks whether the specified ETHERNET DMA flag is set or not.
- * @param __HANDLE__: ETH Handle
- * @param __FLAG__: specifies the flag to clear. @ref ETH_DMA_Flags
+ * @param __HANDLE__ ETH Handle
+ * @param __FLAG__ specifies the flag to clear. @ref ETH_DMA_Flags
* @retval The new state of ETH_DMA_FLAG (SET or RESET).
*/
#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__))
/**
* @brief Checks whether the specified ETHERNET DMA overflow flag is set or not.
- * @param __HANDLE__: ETH Handle
- * @param __OVERFLOW__: specifies the DMA overflow flag to check.
+ * @param __HANDLE__ ETH Handle
+ * @param __OVERFLOW__ specifies the DMA overflow flag to check.
* This parameter can be one of the following values:
* @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter
* @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter
@@ -1821,8 +1819,8 @@
/**
* @brief Set the DMA Receive status watchdog timer register value
- * @param __HANDLE__: ETH Handle
- * @param __VALUE__: DMA Receive status watchdog timer register value
+ * @param __HANDLE__ ETH Handle
+ * @param __VALUE__ DMA Receive status watchdog timer register value
* @retval None
*/
#define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
@@ -1830,7 +1828,7 @@
/**
* @brief Enables any unicast packet filtered by the MAC address
* recognition to be a wake-up frame.
- * @param __HANDLE__: ETH Handle.
+ * @param __HANDLE__ ETH Handle.
* @retval None
*/
#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU)
@@ -1838,57 +1836,57 @@
/**
* @brief Disables any unicast packet filtered by the MAC address
* recognition to be a wake-up frame.
- * @param __HANDLE__: ETH Handle.
+ * @param __HANDLE__ ETH Handle.
* @retval None
*/
#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
/**
* @brief Enables the MAC Wake-Up Frame Detection.
- * @param __HANDLE__: ETH Handle.
+ * @param __HANDLE__ ETH Handle.
* @retval None
*/
#define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE)
/**
* @brief Disables the MAC Wake-Up Frame Detection.
- * @param __HANDLE__: ETH Handle.
+ * @param __HANDLE__ ETH Handle.
* @retval None
*/
#define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
/**
* @brief Enables the MAC Magic Packet Detection.
- * @param __HANDLE__: ETH Handle.
+ * @param __HANDLE__ ETH Handle.
* @retval None
*/
#define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE)
/**
* @brief Disables the MAC Magic Packet Detection.
- * @param __HANDLE__: ETH Handle.
+ * @param __HANDLE__ ETH Handle.
* @retval None
*/
#define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
/**
* @brief Enables the MAC Power Down.
- * @param __HANDLE__: ETH Handle
+ * @param __HANDLE__ ETH Handle
* @retval None
*/
#define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD)
/**
* @brief Disables the MAC Power Down.
- * @param __HANDLE__: ETH Handle
+ * @param __HANDLE__ ETH Handle
* @retval None
*/
#define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
/**
* @brief Checks whether the specified ETHERNET PMT flag is set or not.
- * @param __HANDLE__: ETH Handle.
- * @param __FLAG__: specifies the flag to check.
+ * @param __HANDLE__ ETH Handle.
+ * @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset
* @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received
@@ -1899,14 +1897,14 @@
/**
* @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
- * @param __HANDLE__: ETH Handle.
+ * @param __HANDLE__ ETH Handle.
* @retval None
*/
#define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP))
/**
* @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)
- * @param __HANDLE__: ETH Handle.
+ * @param __HANDLE__ ETH Handle.
* @retval None
*/
#define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
@@ -1914,57 +1912,57 @@
/**
* @brief Enables the MMC Counter Freeze.
- * @param __HANDLE__: ETH Handle.
+ * @param __HANDLE__ ETH Handle.
* @retval None
*/
#define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF)
/**
* @brief Disables the MMC Counter Freeze.
- * @param __HANDLE__: ETH Handle.
+ * @param __HANDLE__ ETH Handle.
* @retval None
*/
#define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
/**
* @brief Enables the MMC Reset On Read.
- * @param __HANDLE__: ETH Handle.
+ * @param __HANDLE__ ETH Handle.
* @retval None
*/
#define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR)
/**
* @brief Disables the MMC Reset On Read.
- * @param __HANDLE__: ETH Handle.
+ * @param __HANDLE__ ETH Handle.
* @retval None
*/
#define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
/**
* @brief Enables the MMC Counter Stop Rollover.
- * @param __HANDLE__: ETH Handle.
+ * @param __HANDLE__ ETH Handle.
* @retval None
*/
#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
/**
* @brief Disables the MMC Counter Stop Rollover.
- * @param __HANDLE__: ETH Handle.
+ * @param __HANDLE__ ETH Handle.
* @retval None
*/
#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR)
/**
* @brief Resets the MMC Counters.
- * @param __HANDLE__: ETH Handle.
+ * @param __HANDLE__ ETH Handle.
* @retval None
*/
#define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR)
/**
* @brief Enables the specified ETHERNET MMC Rx interrupts.
- * @param __HANDLE__: ETH Handle.
- * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
+ * @param __HANDLE__ ETH Handle.
+ * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
* This parameter can be one of the following values:
* @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
* @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
@@ -1974,8 +1972,8 @@
#define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFFU)
/**
* @brief Disables the specified ETHERNET MMC Rx interrupts.
- * @param __HANDLE__: ETH Handle.
- * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
+ * @param __HANDLE__ ETH Handle.
+ * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
* This parameter can be one of the following values:
* @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
* @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
@@ -1985,8 +1983,8 @@
#define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFFU)
/**
* @brief Enables the specified ETHERNET MMC Tx interrupts.
- * @param __HANDLE__: ETH Handle.
- * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
+ * @param __HANDLE__ ETH Handle.
+ * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
* This parameter can be one of the following values:
* @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
* @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
@@ -1997,8 +1995,8 @@
/**
* @brief Disables the specified ETHERNET MMC Tx interrupts.
- * @param __HANDLE__: ETH Handle.
- * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
+ * @param __HANDLE__ ETH Handle.
+ * @param __INTERRUPT__ specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
* This parameter can be one of the following values:
* @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
* @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_flash.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the internal FLASH memory:
@@ -164,10 +162,10 @@
/**
* @brief Program byte, halfword, word or double word at a specified address
- * @param TypeProgram: Indicate the way to program at a specified address.
+ * @param TypeProgram Indicate the way to program at a specified address.
* This parameter can be a value of @ref FLASH_Type_Program
- * @param Address: specifies the address to be programmed.
- * @param Data: specifies the data to be programmed
+ * @param Address specifies the address to be programmed.
+ * @param Data specifies the data to be programmed
*
* @retval HAL_StatusTypeDef HAL Status
*/
@@ -222,10 +220,10 @@
/**
* @brief Program byte, halfword, word or double word at a specified address with interrupt enabled.
- * @param TypeProgram: Indicate the way to program at a specified address.
+ * @param TypeProgram Indicate the way to program at a specified address.
* This parameter can be a value of @ref FLASH_Type_Program
- * @param Address: specifies the address to be programmed.
- * @param Data: specifies the data to be programmed
+ * @param Address specifies the address to be programmed.
+ * @param Data specifies the data to be programmed
*
* @retval HAL Status
*/
@@ -392,7 +390,7 @@
/**
* @brief FLASH end of operation interrupt callback
- * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure
+ * @param ReturnValue The value saved in this parameter depends on the ongoing procedure
* Mass Erase: Bank number which has been requested to erase
* Sectors Erase: Sector which has been erased
* (if 0xFFFFFFFFU, it means that all the selected sectors have been erased)
@@ -410,7 +408,7 @@
/**
* @brief FLASH operation error interrupt callback
- * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure
+ * @param ReturnValue The value saved in this parameter depends on the ongoing procedure
* Mass Erase: Bank number which has been requested to erase
* Sectors Erase: Sector number which returned an error
* Program: Address which was selected for data program
@@ -450,18 +448,22 @@
*/
HAL_StatusTypeDef HAL_FLASH_Unlock(void)
{
- if((FLASH->CR & FLASH_CR_LOCK) != RESET)
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
{
/* Authorize the FLASH Registers access */
- FLASH->KEYR = FLASH_KEY1;
- FLASH->KEYR = FLASH_KEY2;
+ WRITE_REG(FLASH->KEYR, FLASH_KEY1);
+ WRITE_REG(FLASH->KEYR, FLASH_KEY2);
+
+ /* Verify Flash is unlocked */
+ if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
+ {
+ status = HAL_ERROR;
+ }
}
- else
- {
- return HAL_ERROR;
- }
-
- return HAL_OK;
+
+ return status;
}
/**
@@ -560,7 +562,7 @@
/**
* @brief Wait for a FLASH operation to complete.
- * @param Timeout: maximum flash operationtimeout
+ * @param Timeout maximum flash operationtimeout
* @retval HAL Status
*/
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
@@ -619,8 +621,8 @@
* @note If an erase and a program operations are requested simultaneously,
* the erase operation is performed before the program one.
*
- * @param Address: specifies the address to be programmed.
- * @param Data: specifies the data to be programmed.
+ * @param Address specifies the address to be programmed.
+ * @param Data specifies the data to be programmed.
* @retval None
*/
static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
@@ -647,8 +649,8 @@
* @note If an erase and a program operations are requested simultaneously,
* the erase operation is performed before the program one.
*
- * @param Address: specifies the address to be programmed.
- * @param Data: specifies the data to be programmed.
+ * @param Address specifies the address to be programmed.
+ * @param Data specifies the data to be programmed.
* @retval None
*/
static void FLASH_Program_Word(uint32_t Address, uint32_t Data)
@@ -672,8 +674,8 @@
* @note If an erase and a program operations are requested simultaneously,
* the erase operation is performed before the program one.
*
- * @param Address: specifies the address to be programmed.
- * @param Data: specifies the data to be programmed.
+ * @param Address specifies the address to be programmed.
+ * @param Data specifies the data to be programmed.
* @retval None
*/
static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
@@ -697,8 +699,8 @@
* @note If an erase and a program operations are requested simultaneously,
* the erase operation is performed before the program one.
*
- * @param Address: specifies the address to be programmed.
- * @param Data: specifies the data to be programmed.
+ * @param Address specifies the address to be programmed.
+ * @param Data specifies the data to be programmed.
* @retval None
*/
static void FLASH_Program_Byte(uint32_t Address, uint8_t Data)
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_flash.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief Header file of FLASH HAL module.
******************************************************************************
* @attention
@@ -189,7 +187,7 @@
*/
/**
* @brief Set the FLASH Latency.
- * @param __LATENCY__: FLASH Latency
+ * @param __LATENCY__ FLASH Latency
* The value of this parameter depend on device used within the same series
* @retval none
*/
@@ -257,7 +255,7 @@
}while(0U)
/**
* @brief Enable the specified FLASH interrupt.
- * @param __INTERRUPT__ : FLASH interrupt
+ * @param __INTERRUPT__ FLASH interrupt
* This parameter can be any combination of the following values:
* @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
* @arg FLASH_IT_ERR: Error Interrupt
@@ -267,7 +265,7 @@
/**
* @brief Disable the specified FLASH interrupt.
- * @param __INTERRUPT__ : FLASH interrupt
+ * @param __INTERRUPT__ FLASH interrupt
* This parameter can be any combination of the following values:
* @arg FLASH_IT_EOP: End of FLASH Operation Interrupt
* @arg FLASH_IT_ERR: Error Interrupt
@@ -277,7 +275,7 @@
/**
* @brief Get the specified FLASH flag status.
- * @param __FLAG__: specifies the FLASH flags to check.
+ * @param __FLAG__ specifies the FLASH flags to check.
* This parameter can be any combination of the following values:
* @arg FLASH_FLAG_EOP : FLASH End of Operation flag
* @arg FLASH_FLAG_OPERR : FLASH operation Error flag
@@ -294,7 +292,7 @@
/**
* @brief Clear the specified FLASH flags.
- * @param __FLAG__: specifies the FLASH flags to clear.
+ * @param __FLAG__ specifies the FLASH flags to clear.
* This parameter can be any combination of the following values:
* @arg FLASH_FLAG_EOP : FLASH End of Operation flag
* @arg FLASH_FLAG_OPERR : FLASH operation Error flag
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash_ex.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash_ex.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_flash_ex.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief Extended FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the FLASH extension peripheral:
@@ -168,10 +166,10 @@
*/
/**
* @brief Perform a mass erase or erase the specified FLASH memory sectors
- * @param[in] pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
+ * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
* contains the configuration information for the erasing.
*
- * @param[out] SectorError: pointer to variable that
+ * @param[out] SectorError pointer to variable that
* contains the configuration information on faulty sector in case of error
* (0xFFFFFFFFU means that all the sectors have been correctly erased)
*
@@ -243,7 +241,7 @@
/**
* @brief Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled
- * @param pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that
+ * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that
* contains the configuration information for the erasing.
*
* @retval HAL Status
@@ -296,7 +294,7 @@
/**
* @brief Program option bytes
- * @param pOBInit: pointer to an FLASH_OBInitStruct structure that
+ * @param pOBInit pointer to an FLASH_OBInitStruct structure that
* contains the configuration information for the programming.
*
* @retval HAL Status
@@ -355,7 +353,7 @@
/**
* @brief Get the Option byte configuration
- * @param pOBInit: pointer to an FLASH_OBInitStruct structure that
+ * @param pOBInit pointer to an FLASH_OBInitStruct structure that
* contains the configuration information for the programming.
*
* @retval None
@@ -384,7 +382,7 @@
defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
/**
* @brief Program option bytes
- * @param pAdvOBInit: pointer to an FLASH_AdvOBProgramInitTypeDef structure that
+ * @param pAdvOBInit pointer to an FLASH_AdvOBProgramInitTypeDef structure that
* contains the configuration information for the programming.
*
* @retval HAL Status
@@ -440,7 +438,7 @@
/**
* @brief Get the OBEX byte configuration
- * @param pAdvOBInit: pointer to an FLASH_AdvOBProgramInitTypeDef structure that
+ * @param pAdvOBInit pointer to an FLASH_AdvOBProgramInitTypeDef structure that
* contains the configuration information for the programming.
*
* @retval None
@@ -538,7 +536,7 @@
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
/**
* @brief Full erase of FLASH memory sectors
- * @param VoltageRange: The device voltage range which defines the erase parallelism.
+ * @param VoltageRange The device voltage range which defines the erase parallelism.
* This parameter can be one of the following values:
* @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
* the operation will be done by byte (8-bit)
@@ -549,7 +547,7 @@
* @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
* the operation will be done by double word (64-bit)
*
- * @param Banks: Banks to be erased
+ * @param Banks Banks to be erased
* This parameter can be one of the following values:
* @arg FLASH_BANK_1: Bank1 to be erased
* @arg FLASH_BANK_2: Bank2 to be erased
@@ -586,9 +584,9 @@
/**
* @brief Erase the specified FLASH memory sector
- * @param Sector: FLASH sector to erase
+ * @param Sector FLASH sector to erase
* The value of this parameter depend on device used within the same series
- * @param VoltageRange: The device voltage range which defines the erase parallelism.
+ * @param VoltageRange The device voltage range which defines the erase parallelism.
* This parameter can be one of the following values:
* @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
* the operation will be done by byte (8-bit)
@@ -635,7 +633,7 @@
CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
FLASH->CR |= tmp_psize;
CLEAR_BIT(FLASH->CR, FLASH_CR_SNB);
- FLASH->CR |= FLASH_CR_SER | (Sector << POSITION_VAL(FLASH_CR_SNB));
+ FLASH->CR |= FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos);
FLASH->CR |= FLASH_CR_STRT;
}
@@ -647,13 +645,13 @@
* debug features are connected or boot code is executed in RAM, even if nWRPi = 1
* @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
*
- * @param WRPSector: specifies the sector(s) to be write protected.
+ * @param WRPSector specifies the sector(s) to be write protected.
* This parameter can be one of the following values:
* @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_23
* @arg OB_WRP_SECTOR_All
* @note BANK2 starts from OB_WRP_SECTOR_12
*
- * @param Banks: Enable write protection on all the sectors for the specific bank
+ * @param Banks Enable write protection on all the sectors for the specific bank
* This parameter can be one of the following values:
* @arg FLASH_BANK_1: WRP on all sectors of bank1
* @arg FLASH_BANK_2: WRP on all sectors of bank2
@@ -718,13 +716,13 @@
* debug features are connected or boot code is executed in RAM, even if nWRPi = 1
* @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
*
- * @param WRPSector: specifies the sector(s) to be write protected.
+ * @param WRPSector specifies the sector(s) to be write protected.
* This parameter can be one of the following values:
* @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_23
* @arg OB_WRP_Sector_All
* @note BANK2 starts from OB_WRP_SECTOR_12
*
- * @param Banks: Disable write protection on all the sectors for the specific bank
+ * @param Banks Disable write protection on all the sectors for the specific bank
* This parameter can be one of the following values:
* @arg FLASH_BANK_1: Bank1 to be erased
* @arg FLASH_BANK_2: Bank2 to be erased
@@ -951,7 +949,7 @@
defined(STM32F423xx)
/**
* @brief Mass erase of FLASH memory
- * @param VoltageRange: The device voltage range which defines the erase parallelism.
+ * @param VoltageRange The device voltage range which defines the erase parallelism.
* This parameter can be one of the following values:
* @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
* the operation will be done by byte (8-bit)
@@ -962,7 +960,7 @@
* @arg FLASH_VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp,
* the operation will be done by double word (64-bit)
*
- * @param Banks: Banks to be erased
+ * @param Banks Banks to be erased
* This parameter can be one of the following values:
* @arg FLASH_BANK_1: Bank1 to be erased
*
@@ -982,9 +980,9 @@
/**
* @brief Erase the specified FLASH memory sector
- * @param Sector: FLASH sector to erase
+ * @param Sector FLASH sector to erase
* The value of this parameter depend on device used within the same series
- * @param VoltageRange: The device voltage range which defines the erase parallelism.
+ * @param VoltageRange The device voltage range which defines the erase parallelism.
* This parameter can be one of the following values:
* @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V,
* the operation will be done by byte (8-bit)
@@ -1026,7 +1024,7 @@
CLEAR_BIT(FLASH->CR, FLASH_CR_PSIZE);
FLASH->CR |= tmp_psize;
CLEAR_BIT(FLASH->CR, FLASH_CR_SNB);
- FLASH->CR |= FLASH_CR_SER | (Sector << POSITION_VAL(FLASH_CR_SNB));
+ FLASH->CR |= FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos);
FLASH->CR |= FLASH_CR_STRT;
}
@@ -1038,10 +1036,10 @@
* debug features are connected or boot code is executed in RAM, even if nWRPi = 1
* @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
*
- * @param WRPSector: specifies the sector(s) to be write protected.
+ * @param WRPSector specifies the sector(s) to be write protected.
* The value of this parameter depend on device used within the same series
*
- * @param Banks: Enable write protection on all the sectors for the specific bank
+ * @param Banks Enable write protection on all the sectors for the specific bank
* This parameter can be one of the following values:
* @arg FLASH_BANK_1: WRP on all sectors of bank1
*
@@ -1074,10 +1072,10 @@
* debug features are connected or boot code is executed in RAM, even if nWRPi = 1
* @note Active value of nWRPi bits is inverted when PCROP mode is active (SPRMOD =1).
*
- * @param WRPSector: specifies the sector(s) to be write protected.
+ * @param WRPSector specifies the sector(s) to be write protected.
* The value of this parameter depend on device used within the same series
*
- * @param Banks: Enable write protection on all the sectors for the specific bank
+ * @param Banks Enable write protection on all the sectors for the specific bank
* This parameter can be one of the following values:
* @arg FLASH_BANK_1: WRP on all sectors of bank1
*
@@ -1167,7 +1165,7 @@
/**
* @brief Set the read protection level.
- * @param Level: specifies the read protection level.
+ * @param Level specifies the read protection level.
* This parameter can be one of the following values:
* @arg OB_RDP_LEVEL_0: No protection
* @arg OB_RDP_LEVEL_1: Read protection of the memory
@@ -1197,15 +1195,15 @@
/**
* @brief Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.
- * @param Iwdg: Selects the IWDG mode
+ * @param Iwdg Selects the IWDG mode
* This parameter can be one of the following values:
* @arg OB_IWDG_SW: Software IWDG selected
* @arg OB_IWDG_HW: Hardware IWDG selected
- * @param Stop: Reset event when entering STOP mode.
+ * @param Stop Reset event when entering STOP mode.
* This parameter can be one of the following values:
* @arg OB_STOP_NO_RST: No reset generated when entering in STOP
* @arg OB_STOP_RST: Reset generated when entering in STOP
- * @param Stdby: Reset event when entering Standby mode.
+ * @param Stdby Reset event when entering Standby mode.
* This parameter can be one of the following values:
* @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY
* @arg OB_STDBY_RST: Reset generated when entering in STANDBY
@@ -1238,7 +1236,7 @@
/**
* @brief Set the BOR Level.
- * @param Level: specifies the Option Bytes BOR Reset Level.
+ * @param Level specifies the Option Bytes BOR Reset Level.
* This parameter can be one of the following values:
* @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
* @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash_ex.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash_ex.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_flash_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of FLASH HAL Extension module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash_ramfunc.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash_ramfunc.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_flash_ramfunc.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief FLASH RAMFUNC module driver. * This file provides a FLASH firmware functions which should be * executed from internal SRAM
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash_ramfunc.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_flash_ramfunc.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_flash_ramfunc.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of FLASH RAMFUNC driver. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_fmpi2c.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_fmpi2c.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_fmpi2c.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief FMPI2C HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Inter Integrated Circuit (FMPI2C) peripheral:
@@ -30,13 +28,13 @@
(+++) Configure the FMPI2Cx interrupt priority
(+++) Enable the NVIC FMPI2C IRQ Channel
(##) DMA Configuration if you need to use DMA process
- (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive channel
+ (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream
(+++) Enable the DMAx interface clock using
(+++) Configure the DMA handle parameters
- (+++) Configure the DMA Tx or Rx channel
+ (+++) Configure the DMA Tx or Rx stream
(+++) Associate the initialized DMA handle to the hfmpi2c DMA Tx or Rx handle
(+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
- the DMA Tx or Rx channel
+ the DMA Tx or Rx stream
(#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
Own Address2, Own Address2 Mask, General call and Nostretch mode in the hfmpi2c Init structure.
@@ -81,20 +79,20 @@
(+) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and user can
add his own code by customization of function pointer HAL_FMPI2C_ErrorCallback()
(+) Abort a master FMPI2C process communication with Interrupt using HAL_FMPI2C_Master_Abort_IT()
- (+) End of abort process, HAL_FMPI2C_MasterRxCpltCallback() or HAL_FMPI2C_MasterTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_FMPI2C_MasterRxCpltCallback() or HAL_FMPI2C_MasterTxCpltCallback()
+ (+) End of abort process, HAL_FMPI2C_AbortCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_AbortCpltCallback()
(+) Discard a slave FMPI2C process communication using __HAL_FMPI2C_GENERATE_NACK() macro.
This action will inform Master to generate a Stop condition to discard the communication.
*** Interrupt mode IO sequential operation ***
- ===================================
+ ==============================================
[..]
(@) These interfaces allow to manage a sequential transfer with a repeated start condition
when a direction change during transfer
[..]
(+) A specific option field manage the different steps of a sequential transfer
- (+) Option field values are defined through FMPI2C_XFEROPTIONS and are listed below:
+ (+) Option field values are defined through @ref FMPI2C_XFEROPTIONS and are listed below:
(++) FMPI2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
(++) FMPI2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
and data to transfer without a final stop condition
@@ -107,6 +105,12 @@
(++) FMPI2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
and with new data to transfer if the direction change or manage only the new data to transfer
if no direction change and with a final stop condition in both cases
+ (++) FMPI2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential
+ interface several times (link with option FMPI2C_FIRST_AND_NEXT_FRAME).
+ Usage can, transfer several bytes one by one using HAL_FMPI2C_Master_Sequential_Transmit_IT(option FMPI2C_FIRST_AND_NEXT_FRAME then FMPI2C_NEXT_FRAME)
+ or HAL_FMPI2C_Master_Sequential_Receive_IT(option FMPI2C_FIRST_AND_NEXT_FRAME then FMPI2C_NEXT_FRAME).
+ Then usage of this option FMPI2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the oposite interface Receive or Transmit
+ without stopping the communication and so generate a restart condition.
(+) Differents sequential FMPI2C interfaces are listed below:
(++) Sequential transmit in master FMPI2C mode an amount of data in non-blocking mode using HAL_FMPI2C_Master_Sequential_Transmit_IT()
@@ -118,8 +122,6 @@
(++) Abort a master FMPI2C process communication with Interrupt using HAL_FMPI2C_Master_Abort_IT()
(+++) End of abort process, HAL_FMPI2C_AbortCpltCallback() is executed and user can
add his own code by customization of function pointer HAL_FMPI2C_AbortCpltCallback()
- (+++) mean HAL_FMPI2C_MasterTxCpltCallback() in case of previous state was master transmit
- (+++) mean HAL_FMPI2C_MasterRxCpltCallback() in case of previous state was master receive
(++) Enable/disable the Address listen mode in slave FMPI2C mode using HAL_FMPI2C_EnableListen_IT() HAL_FMPI2C_DisableListen_IT()
(+++) When address slave FMPI2C match, HAL_FMPI2C_AddrCallback() is executed and user can
add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
@@ -175,8 +177,8 @@
(+) In case of transfer Error, HAL_FMPI2C_ErrorCallback() function is executed and user can
add his own code by customization of function pointer HAL_FMPI2C_ErrorCallback()
(+) Abort a master FMPI2C process communication with Interrupt using HAL_FMPI2C_Master_Abort_IT()
- (+) End of abort process, HAL_FMPI2C_MasterRxCpltCallback() or HAL_FMPI2C_MasterTxCpltCallback() is executed and user can
- add his own code by customization of function pointer HAL_FMPI2C_MasterRxCpltCallback() or HAL_FMPI2C_MasterTxCpltCallback()
+ (+) End of abort process, HAL_FMPI2C_AbortCpltCallback() is executed and user can
+ add his own code by customization of function pointer HAL_FMPI2C_AbortCpltCallback()
(+) Discard a slave FMPI2C process communication using __HAL_FMPI2C_GENERATE_NACK() macro.
This action will inform Master to generate a Stop condition to discard the communication.
@@ -240,7 +242,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
- */
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal.h"
@@ -265,24 +267,24 @@
/** @defgroup FMPI2C_Private_Define FMPI2C Private Define
* @{
*/
-#define TIMING_CLEAR_MASK 0xF0FFFFFFU /*!< FMPI2C TIMING clear register Mask */
-#define FMPI2C_TIMEOUT_ADDR 10000U /*!< 10 s */
-#define FMPI2C_TIMEOUT_BUSY 25U /*!< 25 ms */
-#define FMPI2C_TIMEOUT_DIR 25U /*!< 25 ms */
-#define FMPI2C_TIMEOUT_RXNE 25U /*!< 25 ms */
-#define FMPI2C_TIMEOUT_STOPF 25U /*!< 25 ms */
-#define FMPI2C_TIMEOUT_TC 25U /*!< 25 ms */
-#define FMPI2C_TIMEOUT_TCR 25U /*!< 25 ms */
-#define FMPI2C_TIMEOUT_TXIS 25U /*!< 25 ms */
-#define FMPI2C_TIMEOUT_FLAG 25U /*!< 25 ms */
-
-#define MAX_NBYTE_SIZE 255U
-#define SlaveAddr_SHIFT 7U
-#define SlaveAddr_MSK 0x06U
+#define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< FMPI2C TIMING clear register Mask */
+#define FMPI2C_TIMEOUT_ADDR (10000U) /*!< 10 s */
+#define FMPI2C_TIMEOUT_BUSY (25U) /*!< 25 ms */
+#define FMPI2C_TIMEOUT_DIR (25U) /*!< 25 ms */
+#define FMPI2C_TIMEOUT_RXNE (25U) /*!< 25 ms */
+#define FMPI2C_TIMEOUT_STOPF (25U) /*!< 25 ms */
+#define FMPI2C_TIMEOUT_TC (25U) /*!< 25 ms */
+#define FMPI2C_TIMEOUT_TCR (25U) /*!< 25 ms */
+#define FMPI2C_TIMEOUT_TXIS (25U) /*!< 25 ms */
+#define FMPI2C_TIMEOUT_FLAG (25U) /*!< 25 ms */
+
+#define MAX_NBYTE_SIZE 255U
+#define SlaveAddr_SHIFT 7U
+#define SlaveAddr_MSK 0x06U
/* Private define for @ref PreviousState usage */
#define FMPI2C_STATE_MSK ((uint32_t)((HAL_FMPI2C_STATE_BUSY_TX | HAL_FMPI2C_STATE_BUSY_RX) & (~((uint32_t)HAL_FMPI2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */
-#define FMPI2C_STATE_NONE ((uint32_t)(HAL_FMPI2C_MODE_NONE)) /*!< Default Value */
+#define FMPI2C_STATE_NONE ((uint32_t)(HAL_FMPI2C_MODE_NONE)) /*!< Default Value */
#define FMPI2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_FMPI2C_STATE_BUSY_TX & FMPI2C_STATE_MSK) | HAL_FMPI2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */
#define FMPI2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_FMPI2C_STATE_BUSY_RX & FMPI2C_STATE_MSK) | HAL_FMPI2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */
#define FMPI2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_FMPI2C_STATE_BUSY_TX & FMPI2C_STATE_MSK) | HAL_FMPI2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */
@@ -292,24 +294,24 @@
/* Private define to centralize the enable/disable of Interrupts */
-#define FMPI2C_XFER_TX_IT 0x00000001U
-#define FMPI2C_XFER_RX_IT 0x00000002U
-#define FMPI2C_XFER_LISTEN_IT 0x00000004U
-
-#define FMPI2C_XFER_ERROR_IT 0x00000011U
-#define FMPI2C_XFER_CPLT_IT 0x00000012U
-#define FMPI2C_XFER_RELOAD_IT 0x00000012U
+#define FMPI2C_XFER_TX_IT (0x00000001U)
+#define FMPI2C_XFER_RX_IT (0x00000002U)
+#define FMPI2C_XFER_LISTEN_IT (0x00000004U)
+
+#define FMPI2C_XFER_ERROR_IT (0x00000011U)
+#define FMPI2C_XFER_CPLT_IT (0x00000012U)
+#define FMPI2C_XFER_RELOAD_IT (0x00000012U)
/* Private define Sequential Transfer Options default/reset value */
-#define FMPI2C_NO_OPTION_FRAME 0xFFFF0000U
+#define FMPI2C_NO_OPTION_FRAME (0xFFFF0000U)
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
#define FMPI2C_GET_DMA_REMAIN_DATA(__HANDLE__) ((((__HANDLE__)->State) == HAL_FMPI2C_STATE_BUSY_TX) ? \
- ((uint32_t)((__HANDLE__)->hdmatx->Instance->NDTR)) : \
- ((uint32_t)((__HANDLE__)->hdmarx->Instance->NDTR)))
+ ((uint32_t)(((DMA_Stream_TypeDef *)(__HANDLE__)->hdmatx->Instance)->NDTR)) : \
+ ((uint32_t)(((DMA_Stream_TypeDef *)(__HANDLE__)->hdmarx->Instance)->NDTR)))
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
@@ -326,17 +328,17 @@
static void FMPI2C_DMAAbort(DMA_HandleTypeDef *hdma);
/* Private functions to handle IT transfer */
-static void FMPI2C_ITAddrCplt (FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags);
-static void FMPI2C_ITMasterSequentialCplt (FMPI2C_HandleTypeDef *hfmpi2c);
-static void FMPI2C_ITSlaveSequentialCplt (FMPI2C_HandleTypeDef *hfmpi2c);
-static void FMPI2C_ITMasterCplt (FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags);
-static void FMPI2C_ITSlaveCplt (FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags);
-static void FMPI2C_ITListenCplt (FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags);
-static void FMPI2C_ITError (FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags);
+static void FMPI2C_ITAddrCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags);
+static void FMPI2C_ITMasterSequentialCplt(FMPI2C_HandleTypeDef *hfmpi2c);
+static void FMPI2C_ITSlaveSequentialCplt(FMPI2C_HandleTypeDef *hfmpi2c);
+static void FMPI2C_ITMasterCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags);
+static void FMPI2C_ITSlaveCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags);
+static void FMPI2C_ITListenCplt(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags);
+static void FMPI2C_ITError(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ErrorCode);
/* Private functions to handle IT transfer */
-static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef FMPI2C_RequestMemoryRead (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef FMPI2C_RequestMemoryRead(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
/* Private functions for FMPI2C transfer IRQ handler */
static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources);
@@ -345,21 +347,21 @@
static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources);
/* Private functions to handle flags during polling transfer */
-static HAL_StatusTypeDef FMPI2C_WaitOnFlagUntilTimeout (FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef FMPI2C_WaitOnTXISFlagUntilTimeout (FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef FMPI2C_WaitOnRXNEFlagUntilTimeout (FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef FMPI2C_WaitOnSTOPFlagUntilTimeout (FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart);
-static HAL_StatusTypeDef FMPI2C_IsAcknowledgeFailed (FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef FMPI2C_WaitOnFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef FMPI2C_WaitOnTXISFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef FMPI2C_WaitOnRXNEFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef FMPI2C_WaitOnSTOPFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart);
+static HAL_StatusTypeDef FMPI2C_IsAcknowledgeFailed(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart);
/* Private functions to centralize the enable/disable of Interrupts */
-static HAL_StatusTypeDef FMPI2C_Enable_IRQ (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptRequest);
-static HAL_StatusTypeDef FMPI2C_Disable_IRQ (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptRequest);
+static HAL_StatusTypeDef FMPI2C_Enable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptRequest);
+static HAL_StatusTypeDef FMPI2C_Disable_IRQ(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t InterruptRequest);
/* Private functions to flush TXDR register */
-static void FMPI2C_Flush_TXDR (FMPI2C_HandleTypeDef *hfmpi2c);
+static void FMPI2C_Flush_TXDR(FMPI2C_HandleTypeDef *hfmpi2c);
/* Private functions to handle start, restart or stop a transfer */
-static void FMPI2C_TransferConfig (FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
+static void FMPI2C_TransferConfig(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
/**
* @}
*/
@@ -371,7 +373,7 @@
*/
/** @defgroup FMPI2C_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
+ * @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
@@ -411,7 +413,7 @@
HAL_StatusTypeDef HAL_FMPI2C_Init(FMPI2C_HandleTypeDef *hfmpi2c)
{
/* Check the FMPI2C handle allocation */
- if(hfmpi2c == NULL)
+ if (hfmpi2c == NULL)
{
return HAL_ERROR;
}
@@ -426,7 +428,7 @@
assert_param(IS_FMPI2C_GENERAL_CALL(hfmpi2c->Init.GeneralCallMode));
assert_param(IS_FMPI2C_NO_STRETCH(hfmpi2c->Init.NoStretchMode));
- if(hfmpi2c->State == HAL_FMPI2C_STATE_RESET)
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hfmpi2c->Lock = HAL_UNLOCKED;
@@ -449,21 +451,18 @@
hfmpi2c->Instance->OAR1 &= ~FMPI2C_OAR1_OA1EN;
/* Configure FMPI2Cx: Own Address1 and ack own address1 mode */
- if(hfmpi2c->Init.OwnAddress1 != 0U)
+ if (hfmpi2c->Init.AddressingMode == FMPI2C_ADDRESSINGMODE_7BIT)
{
- if(hfmpi2c->Init.AddressingMode == FMPI2C_ADDRESSINGMODE_7BIT)
- {
- hfmpi2c->Instance->OAR1 = (FMPI2C_OAR1_OA1EN | hfmpi2c->Init.OwnAddress1);
- }
- else /* FMPI2C_ADDRESSINGMODE_10BIT */
- {
- hfmpi2c->Instance->OAR1 = (FMPI2C_OAR1_OA1EN | FMPI2C_OAR1_OA1MODE | hfmpi2c->Init.OwnAddress1);
- }
+ hfmpi2c->Instance->OAR1 = (FMPI2C_OAR1_OA1EN | hfmpi2c->Init.OwnAddress1);
+ }
+ else /* FMPI2C_ADDRESSINGMODE_10BIT */
+ {
+ hfmpi2c->Instance->OAR1 = (FMPI2C_OAR1_OA1EN | FMPI2C_OAR1_OA1MODE | hfmpi2c->Init.OwnAddress1);
}
/*---------------------------- FMPI2Cx CR2 Configuration ----------------------*/
/* Configure FMPI2Cx: Addressing Master mode */
- if(hfmpi2c->Init.AddressingMode == FMPI2C_ADDRESSINGMODE_10BIT)
+ if (hfmpi2c->Init.AddressingMode == FMPI2C_ADDRESSINGMODE_10BIT)
{
hfmpi2c->Instance->CR2 = (FMPI2C_CR2_ADD10);
}
@@ -501,7 +500,7 @@
HAL_StatusTypeDef HAL_FMPI2C_DeInit(FMPI2C_HandleTypeDef *hfmpi2c)
{
/* Check the FMPI2C handle allocation */
- if(hfmpi2c == NULL)
+ if (hfmpi2c == NULL)
{
return HAL_ERROR;
}
@@ -565,7 +564,7 @@
*/
/** @defgroup FMPI2C_Exported_Functions_Group2 Input and Output operation functions
- * @brief Data transfers functions
+ * @brief Data transfers functions
*
@verbatim
===============================================================================
@@ -577,7 +576,7 @@
(#) There are two modes of transfer:
(++) Blocking mode : The communication is performed in the polling mode.
- The status of all data processing is returned by the same function
+ The status of all data processing is returned by the same function
after finishing transfer.
(++) No-Blocking mode : The communication is performed using Interrupts
or DMA. These functions return the status of the transfer startup.
@@ -622,7 +621,6 @@
(++) HAL_FMPI2C_SlaveTxCpltCallback()
(++) HAL_FMPI2C_SlaveRxCpltCallback()
(++) HAL_FMPI2C_ErrorCallback()
- (++) HAL_FMPI2C_AbortCpltCallback()
@endverbatim
* @{
@@ -632,8 +630,8 @@
* @brief Transmits in master mode an amount of data in blocking mode.
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
* the configuration information for the specified FMPI2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param Timeout Timeout duration
@@ -643,7 +641,7 @@
{
uint32_t tickstart = 0U;
- if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hfmpi2c);
@@ -651,7 +649,7 @@
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
- if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, FMPI2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+ if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, FMPI2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -659,7 +657,7 @@
hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_TX;
hfmpi2c->Mode = HAL_FMPI2C_MODE_MASTER;
hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
-
+
/* Prepare transfer parameters */
hfmpi2c->pBuffPtr = pData;
hfmpi2c->XferCount = Size;
@@ -667,7 +665,7 @@
/* Send Slave Address */
/* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- if(hfmpi2c->XferCount > MAX_NBYTE_SIZE)
+ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_WRITE);
@@ -678,12 +676,12 @@
FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_WRITE);
}
- while(hfmpi2c->XferSize > 0U)
+ while (hfmpi2c->XferCount > 0U)
{
/* Wait until TXIS flag is set */
- if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK)
+ if (FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK)
{
- if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
{
return HAL_ERROR;
}
@@ -697,15 +695,15 @@
hfmpi2c->XferCount--;
hfmpi2c->XferSize--;
- if((hfmpi2c->XferSize == 0U) && (hfmpi2c->XferCount!=0U))
+ if ((hfmpi2c->XferSize == 0U) && (hfmpi2c->XferCount != 0U))
{
/* Wait until TCR flag is set */
- if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+ if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
- if(hfmpi2c->XferCount > MAX_NBYTE_SIZE)
+ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
@@ -720,9 +718,9 @@
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is set */
- if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK)
+ if (FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK)
{
- if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
{
return HAL_ERROR;
}
@@ -756,8 +754,8 @@
* @brief Receives in master mode an amount of data in blocking mode.
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
* the configuration information for the specified FMPI2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param Timeout Timeout duration
@@ -767,15 +765,15 @@
{
uint32_t tickstart = 0U;
- if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
- {
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
/* Process Locked */
__HAL_LOCK(hfmpi2c);
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
- if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, FMPI2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+ if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, FMPI2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -791,7 +789,7 @@
/* Send Slave Address */
/* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- if(hfmpi2c->XferCount > MAX_NBYTE_SIZE)
+ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_READ);
@@ -802,12 +800,12 @@
FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_READ);
}
- while(hfmpi2c->XferSize > 0U)
+ while (hfmpi2c->XferCount > 0U)
{
/* Wait until RXNE flag is set */
- if(FMPI2C_WaitOnRXNEFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK)
+ if (FMPI2C_WaitOnRXNEFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK)
{
- if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
{
return HAL_ERROR;
}
@@ -822,15 +820,15 @@
hfmpi2c->XferSize--;
hfmpi2c->XferCount--;
- if((hfmpi2c->XferSize == 0U) && (hfmpi2c->XferCount != 0U))
+ if ((hfmpi2c->XferSize == 0U) && (hfmpi2c->XferCount != 0U))
{
/* Wait until TCR flag is set */
- if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+ if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
- if(hfmpi2c->XferCount > MAX_NBYTE_SIZE)
+ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
@@ -845,9 +843,9 @@
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is set */
- if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK)
+ if (FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK)
{
- if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
{
return HAL_ERROR;
}
@@ -856,7 +854,7 @@
return HAL_TIMEOUT;
}
}
-
+
/* Clear STOP Flag */
__HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
@@ -878,7 +876,7 @@
}
/**
- * @brief Transmits in slave mode an amount of data in blocking mode.
+ * @brief Transmits in slave mode an amount of data in blocking mode.
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
* the configuration information for the specified FMPI2C.
* @param pData Pointer to data buffer
@@ -890,15 +888,15 @@
{
uint32_t tickstart = 0U;
- if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
{
- if((pData == NULL ) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
/* Process Locked */
__HAL_LOCK(hfmpi2c);
-
+
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
@@ -915,7 +913,7 @@
hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK;
/* Wait until ADDR flag is set */
- if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+ if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
@@ -923,13 +921,13 @@
}
/* Clear ADDR flag */
- __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_ADDR);
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR);
/* If 10bit addressing mode is selected */
- if(hfmpi2c->Init.AddressingMode == FMPI2C_ADDRESSINGMODE_10BIT)
+ if (hfmpi2c->Init.AddressingMode == FMPI2C_ADDRESSINGMODE_10BIT)
{
/* Wait until ADDR flag is set */
- if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+ if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
@@ -937,26 +935,26 @@
}
/* Clear ADDR flag */
- __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_ADDR);
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR);
}
/* Wait until DIR flag is set Transmitter mode */
- if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
+ if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
return HAL_TIMEOUT;
}
- while(hfmpi2c->XferCount > 0U)
+ while (hfmpi2c->XferCount > 0U)
{
/* Wait until TXIS flag is set */
- if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK)
+ if (FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
- if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
{
return HAL_ERROR;
}
@@ -972,16 +970,16 @@
}
/* Wait until STOP flag is set */
- if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK)
+ if (FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
- if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
{
- /* Normal use case for Transmitter mode */
- /* A NACK is generated to confirm the end of transfer */
- hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+ /* Normal use case for Transmitter mode */
+ /* A NACK is generated to confirm the end of transfer */
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
}
else
{
@@ -990,10 +988,10 @@
}
/* Clear STOP flag */
- __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_STOPF);
-
- /* Wait until BUSY flag is reset */
- if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Wait until BUSY flag is reset */
+ if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
@@ -1030,9 +1028,9 @@
{
uint32_t tickstart = 0U;
- if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
- {
- if((pData == NULL ) || (Size == 0U))
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -1055,7 +1053,7 @@
hfmpi2c->Instance->CR2 &= ~FMPI2C_CR2_NACK;
/* Wait until ADDR flag is set */
- if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+ if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
@@ -1063,33 +1061,33 @@
}
/* Clear ADDR flag */
- __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_ADDR);
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR);
/* Wait until DIR flag is reset Receiver mode */
- if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
+ if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
return HAL_TIMEOUT;
}
- while(hfmpi2c->XferCount > 0U)
+ while (hfmpi2c->XferCount > 0U)
{
/* Wait until RXNE flag is set */
- if(FMPI2C_WaitOnRXNEFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK)
+ if (FMPI2C_WaitOnRXNEFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
/* Store Last receive data if any */
- if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_RXNE) == SET)
+ if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_RXNE) == SET)
{
/* Read data from RXDR */
(*hfmpi2c->pBuffPtr++) = hfmpi2c->Instance->RXDR;
hfmpi2c->XferCount--;
}
- if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_TIMEOUT)
+ if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_TIMEOUT)
{
return HAL_TIMEOUT;
}
@@ -1105,12 +1103,12 @@
}
/* Wait until STOP flag is set */
- if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK)
+ if (FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
- if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
{
return HAL_ERROR;
}
@@ -1121,10 +1119,10 @@
}
/* Clear STOP flag */
- __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_STOPF);
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
/* Wait until BUSY flag is reset */
- if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
+ if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
@@ -1152,8 +1150,8 @@
* @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
* the configuration information for the specified FMPI2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @retval HAL status
@@ -1162,9 +1160,9 @@
{
uint32_t xfermode = 0U;
- if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
{
- if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
+ if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
{
return HAL_BUSY;
}
@@ -1181,8 +1179,8 @@
hfmpi2c->XferCount = Size;
hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
hfmpi2c->XferISR = FMPI2C_Master_ISR_IT;
-
- if(hfmpi2c->XferCount > MAX_NBYTE_SIZE)
+
+ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = FMPI2C_RELOAD_MODE;
@@ -1198,7 +1196,7 @@
FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_WRITE);
/* Process Unlocked */
- __HAL_UNLOCK(hfmpi2c);
+ __HAL_UNLOCK(hfmpi2c);
/* Note : The FMPI2C interrupts must be enabled after unlocking current process
to avoid the risk of FMPI2C interrupt handle execution before current
@@ -1221,8 +1219,8 @@
* @brief Receive in master mode an amount of data in non-blocking mode with Interrupt
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
* the configuration information for the specified FMPI2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @retval HAL status
@@ -1231,9 +1229,9 @@
{
uint32_t xfermode = 0U;
- if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
{
- if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
+ if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
{
return HAL_BUSY;
}
@@ -1250,8 +1248,8 @@
hfmpi2c->XferCount = Size;
hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
hfmpi2c->XferISR = FMPI2C_Master_ISR_IT;
-
- if(hfmpi2c->XferCount > MAX_NBYTE_SIZE)
+
+ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = FMPI2C_RELOAD_MODE;
@@ -1265,7 +1263,7 @@
/* Send Slave Address */
/* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE */
FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_READ);
-
+
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
@@ -1296,7 +1294,7 @@
*/
HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size)
{
- if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hfmpi2c);
@@ -1336,7 +1334,7 @@
}
/**
- * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt
+ * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
* the configuration information for the specified FMPI2C.
* @param pData Pointer to data buffer
@@ -1345,7 +1343,7 @@
*/
HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size)
{
- if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hfmpi2c);
@@ -1388,8 +1386,8 @@
* @brief Transmit in master mode an amount of data in non-blocking mode with DMA
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
* the configuration information for the specified FMPI2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @retval HAL status
@@ -1398,9 +1396,9 @@
{
uint32_t xfermode = 0U;
- if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
{
- if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
+ if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
{
return HAL_BUSY;
}
@@ -1417,8 +1415,8 @@
hfmpi2c->XferCount = Size;
hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
hfmpi2c->XferISR = FMPI2C_Master_ISR_DMA;
-
- if(hfmpi2c->XferCount > MAX_NBYTE_SIZE)
+
+ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = FMPI2C_RELOAD_MODE;
@@ -1429,37 +1427,60 @@
xfermode = FMPI2C_AUTOEND_MODE;
}
- /* Set the FMPI2C DMA transfer complete callback */
- hfmpi2c->hdmatx->XferCpltCallback = FMPI2C_DMAMasterTransmitCplt;
-
- /* Set the DMA error callback */
- hfmpi2c->hdmatx->XferErrorCallback = FMPI2C_DMAError;
-
- /* Set the unused DMA callbacks to NULL */
- hfmpi2c->hdmatx->XferHalfCpltCallback = NULL;
- hfmpi2c->hdmatx->XferAbortCallback = NULL;
-
- /* Enable the DMA channel */
- HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize);
-
- /* Send Slave Address */
- /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_WRITE);
-
- /* Update XferCount value */
- hfmpi2c->XferCount -= hfmpi2c->XferSize;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hfmpi2c);
-
- /* Note : The FMPI2C interrupts must be enabled after unlocking current process
- to avoid the risk of FMPI2C interrupt handle execution before current
- process unlock */
- /* Enable ERR and NACK interrupts */
- FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_ERROR_IT);
-
- /* Enable DMA Request */
- hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN;
+ if (hfmpi2c->XferSize > 0U)
+ {
+ /* Set the FMPI2C DMA transfer complete callback */
+ hfmpi2c->hdmatx->XferCpltCallback = FMPI2C_DMAMasterTransmitCplt;
+
+ /* Set the DMA error callback */
+ hfmpi2c->hdmatx->XferErrorCallback = FMPI2C_DMAError;
+
+ /* Set the unused DMA callbacks to NULL */
+ hfmpi2c->hdmatx->XferHalfCpltCallback = NULL;
+ hfmpi2c->hdmatx->XferAbortCallback = NULL;
+
+ /* Enable the DMA stream */
+ HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize);
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_WRITE);
+
+ /* Update XferCount value */
+ hfmpi2c->XferCount -= hfmpi2c->XferSize;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+ to avoid the risk of FMPI2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR and NACK interrupts */
+ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_ERROR_IT);
+
+ /* Enable DMA Request */
+ hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN;
+ }
+ else
+ {
+ /* Update Transfer ISR function pointer */
+ hfmpi2c->XferISR = FMPI2C_Master_ISR_IT;
+
+ /* Send Slave Address */
+ /* Set NBYTES to write and generate START condition */
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_WRITE);
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+ to avoid the risk of FMPI2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */
+ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT);
+ }
return HAL_OK;
}
@@ -1473,8 +1494,8 @@
* @brief Receive in master mode an amount of data in non-blocking mode with DMA
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
* the configuration information for the specified FMPI2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @retval HAL status
@@ -1483,9 +1504,9 @@
{
uint32_t xfermode = 0U;
- if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
{
- if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
+ if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
{
return HAL_BUSY;
}
@@ -1502,8 +1523,8 @@
hfmpi2c->XferCount = Size;
hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
hfmpi2c->XferISR = FMPI2C_Master_ISR_DMA;
-
- if(hfmpi2c->XferCount > MAX_NBYTE_SIZE)
+
+ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = FMPI2C_RELOAD_MODE;
@@ -1514,7 +1535,7 @@
xfermode = FMPI2C_AUTOEND_MODE;
}
- if(hfmpi2c->XferSize > 0U)
+ if (hfmpi2c->XferSize > 0U)
{
/* Set the FMPI2C DMA transfer complete callback */
hfmpi2c->hdmarx->XferCpltCallback = FMPI2C_DMAMasterReceiveCplt;
@@ -1526,12 +1547,12 @@
hfmpi2c->hdmarx->XferHalfCpltCallback = NULL;
hfmpi2c->hdmarx->XferAbortCallback = NULL;
- /* Enable the DMA channel */
+ /* Enable the DMA stream */
HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)pData, hfmpi2c->XferSize);
/* Send Slave Address */
- /* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_READ);
+ /* Set NBYTES to read and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_READ);
/* Update XferCount value */
hfmpi2c->XferCount -= hfmpi2c->XferSize;
@@ -1550,11 +1571,23 @@
}
else
{
- hfmpi2c->State = HAL_FMPI2C_STATE_READY;
- hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+ /* Update Transfer ISR function pointer */
+ hfmpi2c->XferISR = FMPI2C_Master_ISR_IT;
+
+ /* Send Slave Address */
+ /* Set NBYTES to read and generate START condition */
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_GENERATE_START_READ);
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
+
+ /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+ to avoid the risk of FMPI2C interrupt handle execution before current
+ process unlock */
+ /* Enable ERR, TC, STOP, NACK, TXI interrupt */
+ /* possible to enable all of these */
+ /* FMPI2C_IT_ERRI | FMPI2C_IT_TCI| FMPI2C_IT_STOPI| FMPI2C_IT_NACKI | FMPI2C_IT_ADDRI | FMPI2C_IT_RXI | FMPI2C_IT_TXI */
+ FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT);
}
return HAL_OK;
}
@@ -1574,12 +1607,12 @@
*/
HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size)
{
- if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
- }
+ }
/* Process Locked */
__HAL_LOCK(hfmpi2c);
@@ -1604,7 +1637,7 @@
hfmpi2c->hdmatx->XferHalfCpltCallback = NULL;
hfmpi2c->hdmatx->XferAbortCallback = NULL;
- /* Enable the DMA channel */
+ /* Enable the DMA stream */
HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize);
/* Enable Address Acknowledge */
@@ -1620,7 +1653,7 @@
FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT);
/* Enable DMA Request */
- hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN;
+ hfmpi2c->Instance->CR1 |= FMPI2C_CR1_TXDMAEN;
return HAL_OK;
}
@@ -1640,12 +1673,12 @@
*/
HAL_StatusTypeDef HAL_FMPI2C_Slave_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size)
{
- if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
- }
+ }
/* Process Locked */
__HAL_LOCK(hfmpi2c);
@@ -1670,7 +1703,7 @@
hfmpi2c->hdmarx->XferHalfCpltCallback = NULL;
hfmpi2c->hdmarx->XferAbortCallback = NULL;
- /* Enable the DMA channel */
+ /* Enable the DMA stream */
HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)pData, hfmpi2c->XferSize);
/* Enable Address Acknowledge */
@@ -1699,7 +1732,8 @@
* @brief Write an amount of data in blocking mode to a specific memory address
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
* the configuration information for the specified FMPI2C.
- * @param DevAddress Target device address
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
* @param pData Pointer to data buffer
@@ -1714,9 +1748,9 @@
/* Check the parameters */
assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize));
- if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -1727,7 +1761,7 @@
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
- if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, FMPI2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+ if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, FMPI2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -1742,9 +1776,9 @@
hfmpi2c->XferISR = NULL;
/* Send Slave Address and Memory Address */
- if(FMPI2C_RequestMemoryWrite(hfmpi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
+ if (FMPI2C_RequestMemoryWrite(hfmpi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
{
- if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
{
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
@@ -1759,7 +1793,7 @@
}
/* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE */
- if(hfmpi2c->XferCount > MAX_NBYTE_SIZE)
+ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
@@ -1773,9 +1807,9 @@
do
{
/* Wait until TXIS flag is set */
- if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK)
+ if (FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK)
{
- if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
{
return HAL_ERROR;
}
@@ -1790,15 +1824,15 @@
hfmpi2c->XferCount--;
hfmpi2c->XferSize--;
- if((hfmpi2c->XferSize == 0U) && (hfmpi2c->XferCount!=0U))
+ if ((hfmpi2c->XferSize == 0U) && (hfmpi2c->XferCount != 0U))
{
/* Wait until TCR flag is set */
- if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+ if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
- if(hfmpi2c->XferCount > MAX_NBYTE_SIZE)
+ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
@@ -1810,13 +1844,14 @@
}
}
- }while(hfmpi2c->XferCount > 0U);
+ }
+ while (hfmpi2c->XferCount > 0U);
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
- /* Wait until STOPF flag is reset */
- if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK)
+ /* Wait until STOPF flag is reset */
+ if (FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK)
{
- if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
{
return HAL_ERROR;
}
@@ -1850,7 +1885,8 @@
* @brief Read an amount of data in blocking mode from a specific memory address
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
* the configuration information for the specified FMPI2C.
- * @param DevAddress Target device address
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
* @param pData Pointer to data buffer
@@ -1865,9 +1901,9 @@
/* Check the parameters */
assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize));
- if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -1878,7 +1914,7 @@
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
- if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, FMPI2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+ if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_BUSY, SET, FMPI2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -1893,9 +1929,9 @@
hfmpi2c->XferISR = NULL;
/* Send Slave Address and Memory Address */
- if(FMPI2C_RequestMemoryRead(hfmpi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
+ if (FMPI2C_RequestMemoryRead(hfmpi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
{
- if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
{
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
@@ -1911,7 +1947,7 @@
/* Send Slave Address */
/* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- if(hfmpi2c->XferCount > MAX_NBYTE_SIZE)
+ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_READ);
@@ -1925,7 +1961,7 @@
do
{
/* Wait until RXNE flag is set */
- if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
+ if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -1935,15 +1971,15 @@
hfmpi2c->XferSize--;
hfmpi2c->XferCount--;
- if((hfmpi2c->XferSize == 0U) && (hfmpi2c->XferCount != 0U))
+ if ((hfmpi2c->XferSize == 0U) && (hfmpi2c->XferCount != 0U))
{
/* Wait until TCR flag is set */
- if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+ if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
- if(hfmpi2c->XferCount > MAX_NBYTE_SIZE)
+ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
@@ -1954,13 +1990,14 @@
FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, FMPI2C_AUTOEND_MODE, FMPI2C_NO_STARTSTOP);
}
}
- }while(hfmpi2c->XferCount > 0U);
+ }
+ while (hfmpi2c->XferCount > 0U);
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
- /* Wait until STOPF flag is reset */
- if(FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK)
+ /* Wait until STOPF flag is reset */
+ if (FMPI2C_WaitOnSTOPFlagUntilTimeout(hfmpi2c, Timeout, tickstart) != HAL_OK)
{
- if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
{
return HAL_ERROR;
}
@@ -1993,7 +2030,8 @@
* @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
* the configuration information for the specified FMPI2C.
- * @param DevAddress Target device address
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
* @param pData Pointer to data buffer
@@ -2008,14 +2046,14 @@
/* Check the parameters */
assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize));
- if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
-
- if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
+
+ if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
{
return HAL_BUSY;
}
@@ -2035,8 +2073,8 @@
hfmpi2c->XferCount = Size;
hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
hfmpi2c->XferISR = FMPI2C_Master_ISR_IT;
-
- if(hfmpi2c->XferCount > MAX_NBYTE_SIZE)
+
+ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = FMPI2C_RELOAD_MODE;
@@ -2048,9 +2086,9 @@
}
/* Send Slave Address and Memory Address */
- if(FMPI2C_RequestMemoryWrite(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+ if (FMPI2C_RequestMemoryWrite(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
{
- if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
{
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
@@ -2065,12 +2103,12 @@
}
/* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- FMPI2C_TransferConfig(hfmpi2c,DevAddress, hfmpi2c->XferSize, xfermode, FMPI2C_NO_STARTSTOP);
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, xfermode, FMPI2C_NO_STARTSTOP);
/* Process Unlocked */
- __HAL_UNLOCK(hfmpi2c);
-
- /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+ __HAL_UNLOCK(hfmpi2c);
+
+ /* Note : The FMPI2C interrupts must be enabled after unlocking current process
to avoid the risk of FMPI2C interrupt handle execution before current
process unlock */
@@ -2091,7 +2129,8 @@
* @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
* the configuration information for the specified FMPI2C.
- * @param DevAddress Target device address
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
* @param pData Pointer to data buffer
@@ -2106,14 +2145,14 @@
/* Check the parameters */
assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize));
- if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
-
- if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
+
+ if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
{
return HAL_BUSY;
}
@@ -2133,8 +2172,8 @@
hfmpi2c->XferCount = Size;
hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
hfmpi2c->XferISR = FMPI2C_Master_ISR_IT;
-
- if(hfmpi2c->XferCount > MAX_NBYTE_SIZE)
+
+ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = FMPI2C_RELOAD_MODE;
@@ -2146,9 +2185,9 @@
}
/* Send Slave Address and Memory Address */
- if(FMPI2C_RequestMemoryRead(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+ if (FMPI2C_RequestMemoryRead(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
{
- if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
{
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
@@ -2163,7 +2202,7 @@
}
/* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- FMPI2C_TransferConfig(hfmpi2c,DevAddress,hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_READ);
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_READ);
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
@@ -2182,13 +2221,14 @@
else
{
return HAL_BUSY;
- }
+ }
}
/**
* @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
* the configuration information for the specified FMPI2C.
- * @param DevAddress Target device address
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
* @param pData Pointer to data buffer
@@ -2203,14 +2243,14 @@
/* Check the parameters */
assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize));
- if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
- if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
+ if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
{
return HAL_BUSY;
}
@@ -2230,8 +2270,8 @@
hfmpi2c->XferCount = Size;
hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
hfmpi2c->XferISR = FMPI2C_Master_ISR_DMA;
-
- if(hfmpi2c->XferCount > MAX_NBYTE_SIZE)
+
+ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = FMPI2C_RELOAD_MODE;
@@ -2243,9 +2283,9 @@
}
/* Send Slave Address and Memory Address */
- if(FMPI2C_RequestMemoryWrite(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+ if (FMPI2C_RequestMemoryWrite(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
{
- if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
{
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
@@ -2269,7 +2309,7 @@
hfmpi2c->hdmatx->XferHalfCpltCallback = NULL;
hfmpi2c->hdmatx->XferAbortCallback = NULL;
- /* Enable the DMA channel */
+ /* Enable the DMA stream */
HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)pData, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize);
/* Send Slave Address */
@@ -2303,7 +2343,8 @@
* @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address.
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
* the configuration information for the specified FMPI2C.
- * @param DevAddress Target device address
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
* @param pData Pointer to data buffer
@@ -2317,15 +2358,15 @@
/* Check the parameters */
assert_param(IS_FMPI2C_MEMADD_SIZE(MemAddSize));
-
- if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
- if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
+ if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
{
return HAL_BUSY;
}
@@ -2345,8 +2386,8 @@
hfmpi2c->XferCount = Size;
hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
hfmpi2c->XferISR = FMPI2C_Master_ISR_DMA;
-
- if(hfmpi2c->XferCount > MAX_NBYTE_SIZE)
+
+ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = FMPI2C_RELOAD_MODE;
@@ -2358,9 +2399,9 @@
}
/* Send Slave Address and Memory Address */
- if(FMPI2C_RequestMemoryRead(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+ if (FMPI2C_RequestMemoryRead(hfmpi2c, DevAddress, MemAddress, MemAddSize, FMPI2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
{
- if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
{
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
@@ -2384,11 +2425,11 @@
hfmpi2c->hdmarx->XferHalfCpltCallback = NULL;
hfmpi2c->hdmarx->XferAbortCallback = NULL;
- /* Enable the DMA channel */
+ /* Enable the DMA stream */
HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)pData, hfmpi2c->XferSize);
/* Set NBYTES to write and reload if hfmpi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- FMPI2C_TransferConfig(hfmpi2c,DevAddress, hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_READ);
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, xfermode, FMPI2C_GENERATE_START_READ);
/* Update XferCount value */
hfmpi2c->XferCount -= hfmpi2c->XferSize;
@@ -2418,20 +2459,21 @@
* @note This function is used with Memory devices
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
* the configuration information for the specified FMPI2C.
- * @param DevAddress Target device address
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param Trials Number of trials
* @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
-{
+{
uint32_t tickstart = 0U;
__IO uint32_t FMPI2C_Trials = 0U;
- if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
{
- if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
+ if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_BUSY) == SET)
{
return HAL_BUSY;
}
@@ -2445,16 +2487,16 @@
do
{
/* Generate Start */
- hfmpi2c->Instance->CR2 = FMPI2C_GENERATE_START(hfmpi2c->Init.AddressingMode,DevAddress);
-
+ hfmpi2c->Instance->CR2 = FMPI2C_GENERATE_START(hfmpi2c->Init.AddressingMode, DevAddress);
+
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is set or a NACK flag is set*/
tickstart = HAL_GetTick();
- while((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == RESET) && (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) == RESET) && (hfmpi2c->State != HAL_FMPI2C_STATE_TIMEOUT))
+ while ((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == RESET) && (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) == RESET) && (hfmpi2c->State != HAL_FMPI2C_STATE_TIMEOUT))
{
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
{
/* Device is ready */
hfmpi2c->State = HAL_FMPI2C_STATE_READY;
@@ -2462,14 +2504,14 @@
__HAL_UNLOCK(hfmpi2c);
return HAL_TIMEOUT;
}
- }
+ }
}
/* Check if the NACKF flag has not been set */
if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) == RESET)
{
- /* Wait until STOPF flag is reset */
- if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
+ /* Wait until STOPF flag is reset */
+ if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -2487,8 +2529,8 @@
}
else
{
- /* Wait until STOPF flag is reset */
- if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
+ /* Wait until STOPF flag is reset */
+ if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -2505,9 +2547,9 @@
{
/* Generate Stop */
hfmpi2c->Instance->CR2 |= FMPI2C_CR2_STOP;
-
- /* Wait until STOPF flag is reset */
- if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
+
+ /* Wait until STOPF flag is reset */
+ if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -2515,7 +2557,8 @@
/* Clear STOP Flag */
__HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
}
- }while(FMPI2C_Trials < Trials);
+ }
+ while (FMPI2C_Trials < Trials);
hfmpi2c->State = HAL_FMPI2C_STATE_READY;
@@ -2535,8 +2578,8 @@
* @note This interface allow to manage repeated start condition when a direction change during transfer
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
* the configuration information for the specified FMPI2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param XferOptions Options of Transfer, value of @ref FMPI2C_XFEROPTIONS
@@ -2550,7 +2593,7 @@
/* Check the parameters */
assert_param(IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
- if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hfmpi2c);
@@ -2566,7 +2609,7 @@
hfmpi2c->XferISR = FMPI2C_Master_ISR_IT;
/* If size > MAX_NBYTE_SIZE, use reload mode */
- if(hfmpi2c->XferCount > MAX_NBYTE_SIZE)
+ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = FMPI2C_RELOAD_MODE;
@@ -2576,10 +2619,10 @@
hfmpi2c->XferSize = hfmpi2c->XferCount;
xfermode = hfmpi2c->XferOptions;
}
-
+
/* If transfer direction not change, do not generate Restart Condition */
/* Mean Previous state is same as current state */
- if(hfmpi2c->PreviousState == FMPI2C_STATE_SLAVE_BUSY_TX)
+ if (hfmpi2c->PreviousState == FMPI2C_STATE_MASTER_BUSY_TX)
{
xferrequest = FMPI2C_NO_STARTSTOP;
}
@@ -2588,7 +2631,7 @@
FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, xfermode, xferrequest);
/* Process Unlocked */
- __HAL_UNLOCK(hfmpi2c);
+ __HAL_UNLOCK(hfmpi2c);
/* Note : The FMPI2C interrupts must be enabled after unlocking current process
to avoid the risk of FMPI2C interrupt handle execution before current
@@ -2608,8 +2651,8 @@
* @note This interface allow to manage repeated start condition when a direction change during transfer
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
* the configuration information for the specified FMPI2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param XferOptions Options of Transfer, value of @ref FMPI2C_XFEROPTIONS
@@ -2623,7 +2666,7 @@
/* Check the parameters */
assert_param(IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
- if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hfmpi2c);
@@ -2639,7 +2682,7 @@
hfmpi2c->XferISR = FMPI2C_Master_ISR_IT;
/* If hfmpi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
- if(hfmpi2c->XferCount > MAX_NBYTE_SIZE)
+ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = FMPI2C_RELOAD_MODE;
@@ -2652,16 +2695,16 @@
/* If transfer direction not change, do not generate Restart Condition */
/* Mean Previous state is same as current state */
- if(hfmpi2c->PreviousState == FMPI2C_STATE_MASTER_BUSY_RX)
+ if (hfmpi2c->PreviousState == FMPI2C_STATE_MASTER_BUSY_RX)
{
xferrequest = FMPI2C_NO_STARTSTOP;
}
/* Send Slave Address and set NBYTES to read */
- FMPI2C_TransferConfig(hfmpi2c,DevAddress, hfmpi2c->XferSize, xfermode, xferrequest);
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, hfmpi2c->XferSize, xfermode, xferrequest);
/* Process Unlocked */
- __HAL_UNLOCK(hfmpi2c);
+ __HAL_UNLOCK(hfmpi2c);
/* Note : The FMPI2C interrupts must be enabled after unlocking current process
to avoid the risk of FMPI2C interrupt handle execution before current
@@ -2691,9 +2734,9 @@
/* Check the parameters */
assert_param(IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
- if((hfmpi2c->State & HAL_FMPI2C_STATE_LISTEN) == HAL_FMPI2C_STATE_LISTEN)
+ if ((hfmpi2c->State & HAL_FMPI2C_STATE_LISTEN) == HAL_FMPI2C_STATE_LISTEN)
{
- if((pData == NULL) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -2706,12 +2749,12 @@
/* FMPI2C cannot manage full duplex exchange so disable previous IT enabled if any */
/* and then toggle the HAL slave RX state to TX state */
- if(hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX_LISTEN)
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX_LISTEN)
{
/* Disable associated Interrupts */
FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT);
}
-
+
hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_TX_LISTEN;
hfmpi2c->Mode = HAL_FMPI2C_MODE_SLAVE;
hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
@@ -2726,15 +2769,15 @@
hfmpi2c->XferOptions = XferOptions;
hfmpi2c->XferISR = FMPI2C_Slave_ISR_IT;
- if(FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_RECEIVE)
+ if (FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_RECEIVE)
{
/* Clear ADDR flag after prepare the transfer parameters */
/* This action will generate an acknowledge to the Master */
- __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_ADDR);
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR);
}
/* Process Unlocked */
- __HAL_UNLOCK(hfmpi2c);
+ __HAL_UNLOCK(hfmpi2c);
/* Note : The FMPI2C interrupts must be enabled after unlocking current process
to avoid the risk of FMPI2C interrupt handle execution before current
@@ -2765,9 +2808,9 @@
/* Check the parameters */
assert_param(IS_FMPI2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
- if((hfmpi2c->State & HAL_FMPI2C_STATE_LISTEN) == HAL_FMPI2C_STATE_LISTEN)
+ if ((hfmpi2c->State & HAL_FMPI2C_STATE_LISTEN) == HAL_FMPI2C_STATE_LISTEN)
{
- if((pData == NULL) || (Size == 0))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -2780,12 +2823,12 @@
/* FMPI2C cannot manage full duplex exchange so disable previous IT enabled if any */
/* and then toggle the HAL slave TX state to RX state */
- if(hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX_LISTEN)
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX_LISTEN)
{
/* Disable associated Interrupts */
FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT);
}
-
+
hfmpi2c->State = HAL_FMPI2C_STATE_BUSY_RX_LISTEN;
hfmpi2c->Mode = HAL_FMPI2C_MODE_SLAVE;
hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
@@ -2800,11 +2843,11 @@
hfmpi2c->XferOptions = XferOptions;
hfmpi2c->XferISR = FMPI2C_Slave_ISR_IT;
- if(FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_TRANSMIT)
+ if (FMPI2C_GET_DIR(hfmpi2c) == FMPI2C_DIRECTION_TRANSMIT)
{
/* Clear ADDR flag after prepare the transfer parameters */
/* This action will generate an acknowledge to the Master */
- __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_ADDR);
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR);
}
/* Process Unlocked */
@@ -2832,7 +2875,7 @@
*/
HAL_StatusTypeDef HAL_FMPI2C_EnableListen_IT(FMPI2C_HandleTypeDef *hfmpi2c)
{
- if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
{
hfmpi2c->State = HAL_FMPI2C_STATE_LISTEN;
hfmpi2c->XferISR = FMPI2C_Slave_ISR_IT;
@@ -2860,14 +2903,14 @@
uint32_t tmp;
/* Disable Address listen mode only if a transfer is not ongoing */
- if(hfmpi2c->State == HAL_FMPI2C_STATE_LISTEN)
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_LISTEN)
{
tmp = (uint32_t)(hfmpi2c->State) & FMPI2C_STATE_MSK;
hfmpi2c->PreviousState = tmp | (uint32_t)(hfmpi2c->Mode);
hfmpi2c->State = HAL_FMPI2C_STATE_READY;
hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
hfmpi2c->XferISR = NULL;
-
+
/* Disable the Address Match interrupt */
FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT);
@@ -2883,13 +2926,13 @@
* @brief Abort a master FMPI2C IT or DMA process communication with Interrupt.
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
* the configuration information for the specified FMPI2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FMPI2C_Master_Abort_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress)
{
- if(hfmpi2c->Mode == HAL_FMPI2C_MODE_MASTER)
+ if (hfmpi2c->Mode == HAL_FMPI2C_MODE_MASTER)
{
/* Process Locked */
__HAL_LOCK(hfmpi2c);
@@ -2908,11 +2951,11 @@
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
- /* Note : The FMPI2C interrupts must be enabled after unlocking current process
+ /* Note : The FMPI2C interrupts must be enabled after unlocking current process
to avoid the risk of FMPI2C interrupt handle execution before current
process unlock */
FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_CPLT_IT);
-
+
return HAL_OK;
}
else
@@ -2929,7 +2972,7 @@
/** @defgroup FMPI2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
* @{
- */
+ */
/**
* @brief This function handles FMPI2C event interrupt request.
@@ -2944,7 +2987,7 @@
uint32_t itsources = READ_REG(hfmpi2c->Instance->CR1);
/* FMPI2C events treatment -------------------------------------*/
- if(hfmpi2c->XferISR != NULL)
+ if (hfmpi2c->XferISR != NULL)
{
hfmpi2c->XferISR(hfmpi2c, itflags, itsources);
}
@@ -2962,7 +3005,7 @@
uint32_t itsources = READ_REG(hfmpi2c->Instance->CR1);
/* FMPI2C Bus error interrupt occurred ------------------------------------*/
- if(((itflags & FMPI2C_FLAG_BERR) != RESET) && ((itsources & FMPI2C_IT_ERRI) != RESET))
+ if (((itflags & FMPI2C_FLAG_BERR) != RESET) && ((itsources & FMPI2C_IT_ERRI) != RESET))
{
hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_BERR;
@@ -2971,7 +3014,7 @@
}
/* FMPI2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
- if(((itflags & FMPI2C_FLAG_OVR) != RESET) && ((itsources & FMPI2C_IT_ERRI) != RESET))
+ if (((itflags & FMPI2C_FLAG_OVR) != RESET) && ((itsources & FMPI2C_IT_ERRI) != RESET))
{
hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_OVR;
@@ -2980,7 +3023,7 @@
}
/* FMPI2C Arbitration Loss error interrupt occurred -------------------------------------*/
- if(((itflags & FMPI2C_FLAG_ARLO) != RESET) && ((itsources & FMPI2C_IT_ERRI) != RESET))
+ if (((itflags & FMPI2C_FLAG_ARLO) != RESET) && ((itsources & FMPI2C_IT_ERRI) != RESET))
{
hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_ARLO;
@@ -2989,7 +3032,7 @@
}
/* Call the Error Callback in case of Error detected */
- if((hfmpi2c->ErrorCode & (HAL_FMPI2C_ERROR_BERR | HAL_FMPI2C_ERROR_OVR | HAL_FMPI2C_ERROR_ARLO)) != HAL_FMPI2C_ERROR_NONE)
+ if ((hfmpi2c->ErrorCode & (HAL_FMPI2C_ERROR_BERR | HAL_FMPI2C_ERROR_OVR | HAL_FMPI2C_ERROR_ARLO)) != HAL_FMPI2C_ERROR_NONE)
{
FMPI2C_ITError(hfmpi2c, hfmpi2c->ErrorCode);
}
@@ -3062,8 +3105,8 @@
* @brief Slave Address Match callback.
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
* the configuration information for the specified FMPI2C.
- * @param TransferDirection: Master request Transfer Direction (Write/Read), value of @ref FMPI2C_XFEROPTIONS
- * @param AddrMatchCode: Address Match Code
+ * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref FMPI2C_XFERDIRECTION
+ * @param AddrMatchCode Address Match Code
* @retval None
*/
__weak void HAL_FMPI2C_AddrCallback(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
@@ -3213,7 +3256,7 @@
/**
* @}
- */
+ */
/**
* @}
@@ -3231,14 +3274,14 @@
* @param ITSources Interrupt sources enabled.
* @retval HAL status
*/
-static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources)
+static HAL_StatusTypeDef FMPI2C_Master_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources)
{
- uint16_t devaddress = 0;
+ uint16_t devaddress = 0U;
/* Process Locked */
__HAL_LOCK(hfmpi2c);
- if(((ITFlags & FMPI2C_FLAG_AF) != RESET) && ((ITSources & FMPI2C_IT_NACKI) != RESET))
+ if (((ITFlags & FMPI2C_FLAG_AF) != RESET) && ((ITSources & FMPI2C_IT_NACKI) != RESET))
{
/* Clear NACK Flag */
__HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
@@ -3251,27 +3294,27 @@
/* Flush TX register */
FMPI2C_Flush_TXDR(hfmpi2c);
}
- else if(((ITFlags & FMPI2C_FLAG_RXNE) != RESET) && ((ITSources & FMPI2C_IT_RXI) != RESET))
+ else if (((ITFlags & FMPI2C_FLAG_RXNE) != RESET) && ((ITSources & FMPI2C_IT_RXI) != RESET))
{
/* Read data from RXDR */
(*hfmpi2c->pBuffPtr++) = hfmpi2c->Instance->RXDR;
hfmpi2c->XferSize--;
hfmpi2c->XferCount--;
}
- else if(((ITFlags & FMPI2C_FLAG_TXIS) != RESET) && ((ITSources & FMPI2C_IT_TXI) != RESET))
+ else if (((ITFlags & FMPI2C_FLAG_TXIS) != RESET) && ((ITSources & FMPI2C_IT_TXI) != RESET))
{
/* Write data to TXDR */
hfmpi2c->Instance->TXDR = (*hfmpi2c->pBuffPtr++);
hfmpi2c->XferSize--;
- hfmpi2c->XferCount--;
+ hfmpi2c->XferCount--;
}
- else if(((ITFlags & FMPI2C_FLAG_TCR) != RESET) && ((ITSources & FMPI2C_IT_TCI) != RESET))
+ else if (((ITFlags & FMPI2C_FLAG_TCR) != RESET) && ((ITSources & FMPI2C_IT_TCI) != RESET))
{
- if((hfmpi2c->XferSize == 0U) && (hfmpi2c->XferCount != 0U))
+ if ((hfmpi2c->XferSize == 0U) && (hfmpi2c->XferCount != 0U))
{
devaddress = (hfmpi2c->Instance->CR2 & FMPI2C_CR2_SADD);
-
- if(hfmpi2c->XferCount > MAX_NBYTE_SIZE)
+
+ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
FMPI2C_TransferConfig(hfmpi2c, devaddress, hfmpi2c->XferSize, FMPI2C_RELOAD_MODE, FMPI2C_NO_STARTSTOP);
@@ -3279,7 +3322,7 @@
else
{
hfmpi2c->XferSize = hfmpi2c->XferCount;
- if(hfmpi2c->XferOptions != FMPI2C_NO_OPTION_FRAME)
+ if (hfmpi2c->XferOptions != FMPI2C_NO_OPTION_FRAME)
{
FMPI2C_TransferConfig(hfmpi2c, devaddress, hfmpi2c->XferSize, hfmpi2c->XferOptions, FMPI2C_NO_STARTSTOP);
}
@@ -3292,7 +3335,7 @@
else
{
/* Call TxCpltCallback() if no stop mode is set */
- if((FMPI2C_GET_STOP_MODE(hfmpi2c) != FMPI2C_AUTOEND_MODE)&&(hfmpi2c->Mode == HAL_FMPI2C_MODE_MASTER))
+ if (FMPI2C_GET_STOP_MODE(hfmpi2c) != FMPI2C_AUTOEND_MODE)
{
/* Call FMPI2C Master Sequential complete process */
FMPI2C_ITMasterSequentialCplt(hfmpi2c);
@@ -3305,14 +3348,23 @@
}
}
}
- else if(((ITFlags & FMPI2C_FLAG_TC) != RESET) && ((ITSources & FMPI2C_IT_TCI) != RESET))
+ else if (((ITFlags & FMPI2C_FLAG_TC) != RESET) && ((ITSources & FMPI2C_IT_TCI) != RESET))
{
- if(hfmpi2c->XferCount == 0U)
+ if (hfmpi2c->XferCount == 0U)
{
- if((FMPI2C_GET_STOP_MODE(hfmpi2c) != FMPI2C_AUTOEND_MODE)&&(hfmpi2c->Mode == HAL_FMPI2C_MODE_MASTER))
+ if (FMPI2C_GET_STOP_MODE(hfmpi2c) != FMPI2C_AUTOEND_MODE)
{
- /* Call FMPI2C Master Sequential complete process */
- FMPI2C_ITMasterSequentialCplt(hfmpi2c);
+ /* Generate a stop condition in case of no transfer option */
+ if (hfmpi2c->XferOptions == FMPI2C_NO_OPTION_FRAME)
+ {
+ /* Generate Stop */
+ hfmpi2c->Instance->CR2 |= FMPI2C_CR2_STOP;
+ }
+ else
+ {
+ /* Call FMPI2C Master Sequential complete process */
+ FMPI2C_ITMasterSequentialCplt(hfmpi2c);
+ }
}
}
else
@@ -3323,7 +3375,7 @@
}
}
- if(((ITFlags & FMPI2C_FLAG_STOPF) != RESET) && ((ITSources & FMPI2C_IT_STOPI) != RESET))
+ if (((ITFlags & FMPI2C_FLAG_STOPF) != RESET) && ((ITSources & FMPI2C_IT_STOPI) != RESET))
{
/* Call FMPI2C Master complete process */
FMPI2C_ITMasterCplt(hfmpi2c, ITFlags);
@@ -3343,26 +3395,26 @@
* @param ITSources Interrupt sources enabled.
* @retval HAL status
*/
-static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources)
+static HAL_StatusTypeDef FMPI2C_Slave_ISR_IT(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources)
{
/* Process locked */
__HAL_LOCK(hfmpi2c);
-
- if(((ITFlags & FMPI2C_FLAG_AF) != RESET) && ((ITSources & FMPI2C_IT_NACKI) != RESET))
+
+ if (((ITFlags & FMPI2C_FLAG_AF) != RESET) && ((ITSources & FMPI2C_IT_NACKI) != RESET))
{
/* Check that FMPI2C transfer finished */
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
/* Mean XferCount == 0*/
/* So clear Flag NACKF only */
- if(hfmpi2c->XferCount == 0U)
+ if (hfmpi2c->XferCount == 0U)
{
- if(((hfmpi2c->XferOptions == FMPI2C_FIRST_AND_LAST_FRAME) || (hfmpi2c->XferOptions == FMPI2C_LAST_FRAME)) && \
- (hfmpi2c->State == HAL_FMPI2C_STATE_LISTEN))
+ if (((hfmpi2c->XferOptions == FMPI2C_FIRST_AND_LAST_FRAME) || (hfmpi2c->XferOptions == FMPI2C_LAST_FRAME)) && \
+ (hfmpi2c->State == HAL_FMPI2C_STATE_LISTEN))
{
/* Call FMPI2C Listen complete process */
FMPI2C_ITListenCplt(hfmpi2c, ITFlags);
}
- else if((hfmpi2c->XferOptions != FMPI2C_NO_OPTION_FRAME) && (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX_LISTEN))
+ else if ((hfmpi2c->XferOptions != FMPI2C_NO_OPTION_FRAME) && (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX_LISTEN))
{
/* Clear NACK Flag */
__HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
@@ -3390,9 +3442,9 @@
hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
}
}
- else if(((ITFlags & FMPI2C_FLAG_RXNE) != RESET) && ((ITSources & FMPI2C_IT_RXI) != RESET))
+ else if (((ITFlags & FMPI2C_FLAG_RXNE) != RESET) && ((ITSources & FMPI2C_IT_RXI) != RESET))
{
- if(hfmpi2c->XferCount > 0U)
+ if (hfmpi2c->XferCount > 0U)
{
/* Read data from RXDR */
(*hfmpi2c->pBuffPtr++) = hfmpi2c->Instance->RXDR;
@@ -3400,24 +3452,24 @@
hfmpi2c->XferCount--;
}
- if((hfmpi2c->XferCount == 0U) && \
- (hfmpi2c->XferOptions != FMPI2C_NO_OPTION_FRAME))
+ if ((hfmpi2c->XferCount == 0U) && \
+ (hfmpi2c->XferOptions != FMPI2C_NO_OPTION_FRAME))
{
/* Call FMPI2C Slave Sequential complete process */
FMPI2C_ITSlaveSequentialCplt(hfmpi2c);
- }
+ }
}
- else if(((ITFlags & FMPI2C_FLAG_ADDR) != RESET) && ((ITSources & FMPI2C_IT_ADDRI) != RESET))
+ else if (((ITFlags & FMPI2C_FLAG_ADDR) != RESET) && ((ITSources & FMPI2C_IT_ADDRI) != RESET))
{
FMPI2C_ITAddrCplt(hfmpi2c, ITFlags);
}
- else if(((ITFlags & FMPI2C_FLAG_TXIS) != RESET) && ((ITSources & FMPI2C_IT_TXI) != RESET))
+ else if (((ITFlags & FMPI2C_FLAG_TXIS) != RESET) && ((ITSources & FMPI2C_IT_TXI) != RESET))
{
/* Write data to TXDR only if XferCount not reach "0" */
/* A TXIS flag can be set, during STOP treatment */
/* Check if all Datas have already been sent */
/* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
- if(hfmpi2c->XferCount > 0U)
+ if (hfmpi2c->XferCount > 0U)
{
/* Write data to TXDR */
hfmpi2c->Instance->TXDR = (*hfmpi2c->pBuffPtr++);
@@ -3426,7 +3478,7 @@
}
else
{
- if((hfmpi2c->XferOptions == FMPI2C_NEXT_FRAME) || (hfmpi2c->XferOptions == FMPI2C_FIRST_FRAME))
+ if ((hfmpi2c->XferOptions == FMPI2C_NEXT_FRAME) || (hfmpi2c->XferOptions == FMPI2C_FIRST_FRAME))
{
/* Last Byte is Transmitted */
/* Call FMPI2C Slave Sequential complete process */
@@ -3436,7 +3488,7 @@
}
/* Check if STOPF is set */
- if(((ITFlags & FMPI2C_FLAG_STOPF) != RESET) && ((ITSources & FMPI2C_IT_STOPI) != RESET))
+ if (((ITFlags & FMPI2C_FLAG_STOPF) != RESET) && ((ITSources & FMPI2C_IT_STOPI) != RESET))
{
/* Call FMPI2C Slave complete process */
FMPI2C_ITSlaveCplt(hfmpi2c, ITFlags);
@@ -3456,22 +3508,22 @@
* @param ITSources Interrupt sources enabled.
* @retval HAL status
*/
-static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources)
+static HAL_StatusTypeDef FMPI2C_Master_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources)
{
- uint16_t devaddress = 0;
+ uint16_t devaddress = 0U;
uint32_t xfermode = 0U;
/* Process Locked */
__HAL_LOCK(hfmpi2c);
- if(((ITFlags & FMPI2C_FLAG_AF) != RESET) && ((ITSources & FMPI2C_IT_NACKI) != RESET))
+ if (((ITFlags & FMPI2C_FLAG_AF) != RESET) && ((ITSources & FMPI2C_IT_NACKI) != RESET))
{
/* Clear NACK Flag */
__HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
/* Set corresponding Error Code */
hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
-
+
/* No need to generate STOP, it is automatically done */
/* But enable STOP interrupt, to treat it */
/* Error callback will be send during stop flag treatment */
@@ -3480,18 +3532,18 @@
/* Flush TX register */
FMPI2C_Flush_TXDR(hfmpi2c);
}
- else if(((ITFlags & FMPI2C_FLAG_TCR) != RESET) && ((ITSources & FMPI2C_IT_TCI) != RESET))
+ else if (((ITFlags & FMPI2C_FLAG_TCR) != RESET) && ((ITSources & FMPI2C_IT_TCI) != RESET))
{
/* Disable TC interrupt */
__HAL_FMPI2C_DISABLE_IT(hfmpi2c, FMPI2C_IT_TCI);
-
- if(hfmpi2c->XferCount != 0U)
+
+ if (hfmpi2c->XferCount != 0U)
{
/* Recover Slave address */
devaddress = (hfmpi2c->Instance->CR2 & FMPI2C_CR2_SADD);
-
+
/* Prepare the new XferSize to transfer */
- if(hfmpi2c->XferCount > MAX_NBYTE_SIZE)
+ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = FMPI2C_RELOAD_MODE;
@@ -3509,7 +3561,7 @@
hfmpi2c->XferCount -= hfmpi2c->XferSize;
/* Enable DMA Request */
- if(hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX)
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX)
{
hfmpi2c->Instance->CR1 |= FMPI2C_CR1_RXDMAEN;
}
@@ -3525,7 +3577,7 @@
FMPI2C_ITError(hfmpi2c, HAL_FMPI2C_ERROR_SIZE);
}
}
- else if(((ITFlags & FMPI2C_FLAG_STOPF) != RESET) && ((ITSources & FMPI2C_IT_STOPI) != RESET))
+ else if (((ITFlags & FMPI2C_FLAG_STOPF) != RESET) && ((ITSources & FMPI2C_IT_STOPI) != RESET))
{
/* Call FMPI2C Master complete process */
FMPI2C_ITMasterCplt(hfmpi2c, ITFlags);
@@ -3545,18 +3597,18 @@
* @param ITSources Interrupt sources enabled.
* @retval HAL status
*/
-static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources)
+static HAL_StatusTypeDef FMPI2C_Slave_ISR_DMA(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources)
{
/* Process locked */
__HAL_LOCK(hfmpi2c);
-
- if(((ITFlags & FMPI2C_FLAG_AF) != RESET) && ((ITSources & FMPI2C_IT_NACKI) != RESET))
+
+ if (((ITFlags & FMPI2C_FLAG_AF) != RESET) && ((ITSources & FMPI2C_IT_NACKI) != RESET))
{
/* Check that FMPI2C transfer finished */
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
/* Mean XferCount == 0 */
/* So clear Flag NACKF only */
- if(FMPI2C_GET_DMA_REMAIN_DATA(hfmpi2c) == 0U)
+ if (FMPI2C_GET_DMA_REMAIN_DATA(hfmpi2c) == 0U)
{
/* Clear NACK Flag */
__HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
@@ -3566,17 +3618,17 @@
/* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
/* Clear NACK Flag */
__HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
-
+
/* Set ErrorCode corresponding to a Non-Acknowledge */
hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
}
}
- else if(((ITFlags & FMPI2C_FLAG_ADDR) != RESET) && ((ITSources & FMPI2C_IT_ADDRI) != RESET))
+ else if (((ITFlags & FMPI2C_FLAG_ADDR) != RESET) && ((ITSources & FMPI2C_IT_ADDRI) != RESET))
{
/* Clear ADDR flag */
__HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR);
}
- else if(((ITFlags & FMPI2C_FLAG_STOPF) != RESET) && ((ITSources & FMPI2C_IT_STOPI) != RESET))
+ else if (((ITFlags & FMPI2C_FLAG_STOPF) != RESET) && ((ITSources & FMPI2C_IT_STOPI) != RESET))
{
/* Call FMPI2C Slave complete process */
FMPI2C_ITSlaveCplt(hfmpi2c, ITFlags);
@@ -3592,7 +3644,8 @@
* @brief Master sends target device address followed by internal memory address for write request.
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
* the configuration information for the specified FMPI2C.
- * @param DevAddress Target device address
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
* @param Timeout Timeout duration
@@ -3601,12 +3654,12 @@
*/
static HAL_StatusTypeDef FMPI2C_RequestMemoryWrite(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
{
- FMPI2C_TransferConfig(hfmpi2c,DevAddress,MemAddSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_WRITE);
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, MemAddSize, FMPI2C_RELOAD_MODE, FMPI2C_GENERATE_START_WRITE);
/* Wait until TXIS flag is set */
- if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout, Tickstart) != HAL_OK)
+ if (FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout, Tickstart) != HAL_OK)
{
- if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
{
return HAL_ERROR;
}
@@ -3617,7 +3670,7 @@
}
/* If Memory address size is 8Bit */
- if(MemAddSize == FMPI2C_MEMADD_SIZE_8BIT)
+ if (MemAddSize == FMPI2C_MEMADD_SIZE_8BIT)
{
/* Send Memory Address */
hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_LSB(MemAddress);
@@ -3629,9 +3682,9 @@
hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_MSB(MemAddress);
/* Wait until TXIS flag is set */
- if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout, Tickstart) != HAL_OK)
+ if (FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout, Tickstart) != HAL_OK)
{
- if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
{
return HAL_ERROR;
}
@@ -3640,25 +3693,26 @@
return HAL_TIMEOUT;
}
}
-
+
/* Send LSB of Memory Address */
hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_LSB(MemAddress);
}
/* Wait until TCR flag is set */
- if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
+ if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
-return HAL_OK;
+ return HAL_OK;
}
/**
* @brief Master sends target device address followed by internal memory address for read request.
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
* the configuration information for the specified FMPI2C.
- * @param DevAddress Target device address
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
* @param Timeout Timeout duration
@@ -3667,12 +3721,12 @@
*/
static HAL_StatusTypeDef FMPI2C_RequestMemoryRead(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
{
- FMPI2C_TransferConfig(hfmpi2c,DevAddress,MemAddSize, FMPI2C_SOFTEND_MODE, FMPI2C_GENERATE_START_WRITE);
+ FMPI2C_TransferConfig(hfmpi2c, DevAddress, MemAddSize, FMPI2C_SOFTEND_MODE, FMPI2C_GENERATE_START_WRITE);
/* Wait until TXIS flag is set */
- if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout, Tickstart) != HAL_OK)
+ if (FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout, Tickstart) != HAL_OK)
{
- if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
{
return HAL_ERROR;
}
@@ -3683,7 +3737,7 @@
}
/* If Memory address size is 8Bit */
- if(MemAddSize == FMPI2C_MEMADD_SIZE_8BIT)
+ if (MemAddSize == FMPI2C_MEMADD_SIZE_8BIT)
{
/* Send Memory Address */
hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_LSB(MemAddress);
@@ -3695,9 +3749,9 @@
hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_MSB(MemAddress);
/* Wait until TXIS flag is set */
- if(FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout, Tickstart) != HAL_OK)
+ if (FMPI2C_WaitOnTXISFlagUntilTimeout(hfmpi2c, Timeout, Tickstart) != HAL_OK)
{
- if(hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
+ if (hfmpi2c->ErrorCode == HAL_FMPI2C_ERROR_AF)
{
return HAL_ERROR;
}
@@ -3706,17 +3760,17 @@
return HAL_TIMEOUT;
}
}
-
+
/* Send LSB of Memory Address */
hfmpi2c->Instance->TXDR = FMPI2C_MEM_ADD_LSB(MemAddress);
}
/* Wait until TC flag is set */
- if(FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
+ if (FMPI2C_WaitOnFlagUntilTimeout(hfmpi2c, FMPI2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
-
+
return HAL_OK;
}
@@ -3733,8 +3787,11 @@
uint16_t ownadd1code = 0;
uint16_t ownadd2code = 0;
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(ITFlags);
+
/* In case of Listen state, need to inform upper layer of address match code event */
- if((hfmpi2c->State & HAL_FMPI2C_STATE_LISTEN) == HAL_FMPI2C_STATE_LISTEN)
+ if ((hfmpi2c->State & HAL_FMPI2C_STATE_LISTEN) == HAL_FMPI2C_STATE_LISTEN)
{
transferdirection = FMPI2C_GET_DIR(hfmpi2c);
slaveaddrcode = FMPI2C_GET_ADDR_MATCH(hfmpi2c);
@@ -3742,19 +3799,19 @@
ownadd2code = FMPI2C_GET_OWN_ADDRESS2(hfmpi2c);
/* If 10bits addressing mode is selected */
- if(hfmpi2c->Init.AddressingMode == FMPI2C_ADDRESSINGMODE_10BIT)
+ if (hfmpi2c->Init.AddressingMode == FMPI2C_ADDRESSINGMODE_10BIT)
{
- if((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK))
+ if ((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK))
{
slaveaddrcode = ownadd1code;
hfmpi2c->AddrEventCount++;
- if(hfmpi2c->AddrEventCount == 2U)
+ if (hfmpi2c->AddrEventCount == 2U)
{
- /* Reset Address Event counter */
+ /* Reset Address Event counter */
hfmpi2c->AddrEventCount = 0U;
/* Clear ADDR flag */
- __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_ADDR);
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR);
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
@@ -3855,8 +3912,8 @@
{
/* Reset FMPI2C handle mode */
hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
-
- if(hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX_LISTEN)
+
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX_LISTEN)
{
/* Remove HAL_FMPI2C_STATE_SLAVE_BUSY_TX, keep only HAL_FMPI2C_STATE_LISTEN */
hfmpi2c->State = HAL_FMPI2C_STATE_LISTEN;
@@ -3872,7 +3929,7 @@
HAL_FMPI2C_SlaveTxCpltCallback(hfmpi2c);
}
- else if(hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX_LISTEN)
+ else if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX_LISTEN)
{
/* Remove HAL_FMPI2C_STATE_SLAVE_BUSY_RX, keep only HAL_FMPI2C_STATE_LISTEN */
hfmpi2c->State = HAL_FMPI2C_STATE_LISTEN;
@@ -3908,7 +3965,7 @@
hfmpi2c->XferISR = NULL;
hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
- if((ITFlags & FMPI2C_FLAG_AF) != RESET)
+ if ((ITFlags & FMPI2C_FLAG_AF) != RESET)
{
/* Clear NACK Flag */
__HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_AF);
@@ -3919,21 +3976,21 @@
/* Flush TX register */
FMPI2C_Flush_TXDR(hfmpi2c);
-
+
/* Disable Interrupts */
- FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT| FMPI2C_XFER_RX_IT);
+ FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_TX_IT | FMPI2C_XFER_RX_IT);
/* Call the corresponding callback to inform upper layer of End of Transfer */
- if((hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE) || (hfmpi2c->State == HAL_FMPI2C_STATE_ABORT))
+ if ((hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE) || (hfmpi2c->State == HAL_FMPI2C_STATE_ABORT))
{
/* Call the corresponding callback to inform upper layer of End of Transfer */
FMPI2C_ITError(hfmpi2c, hfmpi2c->ErrorCode);
}
/* hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX */
- else if(hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX)
+ else if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX)
{
hfmpi2c->State = HAL_FMPI2C_STATE_READY;
-
+
if (hfmpi2c->Mode == HAL_FMPI2C_MODE_MEM)
{
hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
@@ -3956,10 +4013,10 @@
}
}
/* hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX */
- else if(hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX)
+ else if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX)
{
hfmpi2c->State = HAL_FMPI2C_STATE_READY;
-
+
if (hfmpi2c->Mode == HAL_FMPI2C_MODE_MEM)
{
hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
@@ -3993,7 +4050,7 @@
__HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
/* Clear ADDR flag */
- __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c,FMPI2C_FLAG_ADDR);
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_ADDR);
/* Disable all interrupts */
FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT | FMPI2C_XFER_TX_IT | FMPI2C_XFER_RX_IT);
@@ -4008,52 +4065,52 @@
FMPI2C_Flush_TXDR(hfmpi2c);
/* If a DMA is ongoing, Update handle size context */
- if(((hfmpi2c->Instance->CR1 & FMPI2C_CR1_TXDMAEN) == FMPI2C_CR1_TXDMAEN) ||
- ((hfmpi2c->Instance->CR1 & FMPI2C_CR1_RXDMAEN) == FMPI2C_CR1_RXDMAEN))
+ if (((hfmpi2c->Instance->CR1 & FMPI2C_CR1_TXDMAEN) == FMPI2C_CR1_TXDMAEN) ||
+ ((hfmpi2c->Instance->CR1 & FMPI2C_CR1_RXDMAEN) == FMPI2C_CR1_RXDMAEN))
{
hfmpi2c->XferCount = FMPI2C_GET_DMA_REMAIN_DATA(hfmpi2c);
}
-
+
/* All data are not transferred, so set error code accordingly */
- if(hfmpi2c->XferCount != 0U)
+ if (hfmpi2c->XferCount != 0U)
{
/* Set ErrorCode corresponding to a Non-Acknowledge */
hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
}
-
+
/* Store Last receive data if any */
- if(((ITFlags & FMPI2C_FLAG_RXNE) != RESET))
+ if (((ITFlags & FMPI2C_FLAG_RXNE) != RESET))
{
/* Read data from RXDR */
(*hfmpi2c->pBuffPtr++) = hfmpi2c->Instance->RXDR;
-
- if((hfmpi2c->XferSize > 0U))
+
+ if ((hfmpi2c->XferSize > 0U))
{
hfmpi2c->XferSize--;
hfmpi2c->XferCount--;
-
+
/* Set ErrorCode corresponding to a Non-Acknowledge */
hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
}
}
-
+
hfmpi2c->PreviousState = FMPI2C_STATE_NONE;
hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
hfmpi2c->XferISR = NULL;
-
- if(hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
+
+ if (hfmpi2c->ErrorCode != HAL_FMPI2C_ERROR_NONE)
{
/* Call the corresponding callback to inform upper layer of End of Transfer */
FMPI2C_ITError(hfmpi2c, hfmpi2c->ErrorCode);
/* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
- if(hfmpi2c->State == HAL_FMPI2C_STATE_LISTEN)
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_LISTEN)
{
/* Call FMPI2C Listen complete process */
FMPI2C_ITListenCplt(hfmpi2c, ITFlags);
}
}
- else if(hfmpi2c->XferOptions != FMPI2C_NO_OPTION_FRAME)
+ else if (hfmpi2c->XferOptions != FMPI2C_NO_OPTION_FRAME)
{
hfmpi2c->XferOptions = FMPI2C_NO_OPTION_FRAME;
hfmpi2c->State = HAL_FMPI2C_STATE_READY;
@@ -4065,7 +4122,7 @@
HAL_FMPI2C_ListenCpltCallback(hfmpi2c);
}
/* Call the corresponding callback to inform upper layer of End of Transfer */
- else if(hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX)
+ else if (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX)
{
hfmpi2c->State = HAL_FMPI2C_STATE_READY;
@@ -4086,7 +4143,7 @@
HAL_FMPI2C_SlaveTxCpltCallback(hfmpi2c);
}
}
-
+
/**
* @brief FMPI2C Listen complete process.
* @param hfmpi2c FMPI2C handle.
@@ -4103,16 +4160,16 @@
hfmpi2c->XferISR = NULL;
/* Store Last receive data if any */
- if(((ITFlags & FMPI2C_FLAG_RXNE) != RESET))
+ if (((ITFlags & FMPI2C_FLAG_RXNE) != RESET))
{
/* Read data from RXDR */
(*hfmpi2c->pBuffPtr++) = hfmpi2c->Instance->RXDR;
-
- if((hfmpi2c->XferSize > 0U))
+
+ if ((hfmpi2c->XferSize > 0U))
{
hfmpi2c->XferSize--;
hfmpi2c->XferCount--;
-
+
/* Set ErrorCode corresponding to a Non-Acknowledge */
hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_AF;
}
@@ -4148,13 +4205,13 @@
hfmpi2c->ErrorCode |= ErrorCode;
/* Disable Interrupts */
- if((hfmpi2c->State == HAL_FMPI2C_STATE_LISTEN) ||
- (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX_LISTEN) ||
- (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX_LISTEN))
+ if ((hfmpi2c->State == HAL_FMPI2C_STATE_LISTEN) ||
+ (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_TX_LISTEN) ||
+ (hfmpi2c->State == HAL_FMPI2C_STATE_BUSY_RX_LISTEN))
{
/* Disable all interrupts, except interrupts related to LISTEN state */
FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_RX_IT | FMPI2C_XFER_TX_IT);
-
+
/* keep HAL_FMPI2C_STATE_LISTEN if set */
hfmpi2c->State = HAL_FMPI2C_STATE_LISTEN;
hfmpi2c->PreviousState = FMPI2C_STATE_NONE;
@@ -4164,10 +4221,10 @@
{
/* Disable all interrupts */
FMPI2C_Disable_IRQ(hfmpi2c, FMPI2C_XFER_LISTEN_IT | FMPI2C_XFER_RX_IT | FMPI2C_XFER_TX_IT);
-
+
/* If state is an abort treatment on goind, don't change state */
/* This change will be do later */
- if(hfmpi2c->State != HAL_FMPI2C_STATE_ABORT)
+ if (hfmpi2c->State != HAL_FMPI2C_STATE_ABORT)
{
/* Set HAL_FMPI2C_STATE_READY */
hfmpi2c->State = HAL_FMPI2C_STATE_READY;
@@ -4177,45 +4234,47 @@
}
/* Abort DMA TX transfer if any */
- if((hfmpi2c->Instance->CR1 & FMPI2C_CR1_TXDMAEN) == FMPI2C_CR1_TXDMAEN)
+ if ((hfmpi2c->Instance->CR1 & FMPI2C_CR1_TXDMAEN) == FMPI2C_CR1_TXDMAEN)
{
hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_TXDMAEN;
- /* Set the FMPI2C DMA Abort callback :
+ /* Set the FMPI2C DMA Abort callback :
will lead to call HAL_FMPI2C_ErrorCallback() at end of DMA abort procedure */
hfmpi2c->hdmatx->XferAbortCallback = FMPI2C_DMAAbort;
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
- if(HAL_DMA_Abort_IT(hfmpi2c->hdmatx) != HAL_OK)
+ /* Abort DMA TX */
+ if (HAL_DMA_Abort_IT(hfmpi2c->hdmatx) != HAL_OK)
{
/* Call Directly XferAbortCallback function in case of error */
hfmpi2c->hdmatx->XferAbortCallback(hfmpi2c->hdmatx);
}
}
/* Abort DMA RX transfer if any */
- else if((hfmpi2c->Instance->CR1 & FMPI2C_CR1_RXDMAEN) == FMPI2C_CR1_RXDMAEN)
+ else if ((hfmpi2c->Instance->CR1 & FMPI2C_CR1_RXDMAEN) == FMPI2C_CR1_RXDMAEN)
{
hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_RXDMAEN;
- /* Set the FMPI2C DMA Abort callback :
+ /* Set the FMPI2C DMA Abort callback :
will lead to call HAL_FMPI2C_ErrorCallback() at end of DMA abort procedure */
hfmpi2c->hdmarx->XferAbortCallback = FMPI2C_DMAAbort;
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
- if(HAL_DMA_Abort_IT(hfmpi2c->hdmarx) != HAL_OK)
+ /* Abort DMA RX */
+ if (HAL_DMA_Abort_IT(hfmpi2c->hdmarx) != HAL_OK)
{
- /* Call Directly XferAbortCallback function in case of error */
+ /* Call Directly hfmpi2c->hdmarx->XferAbortCallback function in case of error */
hfmpi2c->hdmarx->XferAbortCallback(hfmpi2c->hdmarx);
}
}
- else if(hfmpi2c->State == HAL_FMPI2C_STATE_ABORT)
+ else if (hfmpi2c->State == HAL_FMPI2C_STATE_ABORT)
{
hfmpi2c->State = HAL_FMPI2C_STATE_READY;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
@@ -4241,13 +4300,13 @@
{
/* If a pending TXIS flag is set */
/* Write a dummy data in TXDR to clear it */
- if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TXIS) != RESET)
+ if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TXIS) != RESET)
{
- hfmpi2c->Instance->TXDR = 0x00U;
+ hfmpi2c->Instance->TXDR = 0x00U;
}
/* Flush TX register if not empty */
- if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TXE) == RESET)
+ if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TXE) == RESET)
{
__HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_TXE);
}
@@ -4260,13 +4319,13 @@
*/
static void FMPI2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
{
- FMPI2C_HandleTypeDef* hfmpi2c = (FMPI2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ FMPI2C_HandleTypeDef *hfmpi2c = (FMPI2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Disable DMA Request */
hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_TXDMAEN;
/* If last transfer, enable STOP interrupt */
- if(hfmpi2c->XferCount == 0U)
+ if (hfmpi2c->XferCount == 0U)
{
/* Enable STOP interrupt */
FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_CPLT_IT);
@@ -4278,7 +4337,7 @@
hfmpi2c->pBuffPtr += hfmpi2c->XferSize;
/* Set the XferSize to transfer */
- if(hfmpi2c->XferCount > MAX_NBYTE_SIZE)
+ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
}
@@ -4287,7 +4346,7 @@
hfmpi2c->XferSize = hfmpi2c->XferCount;
}
- /* Enable the DMA channel */
+ /* Enable the DMA stream */
HAL_DMA_Start_IT(hfmpi2c->hdmatx, (uint32_t)hfmpi2c->pBuffPtr, (uint32_t)&hfmpi2c->Instance->TXDR, hfmpi2c->XferSize);
/* Enable TC interrupts */
@@ -4302,6 +4361,9 @@
*/
static void FMPI2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdma);
+
/* No specific action, Master fully manage the generation of STOP condition */
/* Mean that this generation can arrive at any time, at the end or during DMA process */
/* So STOP condition should be manage through Interrupt treatment */
@@ -4314,13 +4376,13 @@
*/
static void FMPI2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
{
- FMPI2C_HandleTypeDef* hfmpi2c = (FMPI2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ FMPI2C_HandleTypeDef *hfmpi2c = (FMPI2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Disable DMA Request */
hfmpi2c->Instance->CR1 &= ~FMPI2C_CR1_RXDMAEN;
/* If last transfer, enable STOP interrupt */
- if(hfmpi2c->XferCount == 0U)
+ if (hfmpi2c->XferCount == 0U)
{
/* Enable STOP interrupt */
FMPI2C_Enable_IRQ(hfmpi2c, FMPI2C_XFER_CPLT_IT);
@@ -4332,7 +4394,7 @@
hfmpi2c->pBuffPtr += hfmpi2c->XferSize;
/* Set the XferSize to transfer */
- if(hfmpi2c->XferCount > MAX_NBYTE_SIZE)
+ if (hfmpi2c->XferCount > MAX_NBYTE_SIZE)
{
hfmpi2c->XferSize = MAX_NBYTE_SIZE;
}
@@ -4341,7 +4403,7 @@
hfmpi2c->XferSize = hfmpi2c->XferCount;
}
- /* Enable the DMA channel */
+ /* Enable the DMA stream */
HAL_DMA_Start_IT(hfmpi2c->hdmarx, (uint32_t)&hfmpi2c->Instance->RXDR, (uint32_t)hfmpi2c->pBuffPtr, hfmpi2c->XferSize);
/* Enable TC interrupts */
@@ -4356,6 +4418,9 @@
*/
static void FMPI2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hdma);
+
/* No specific action, Master fully manage the generation of STOP condition */
/* Mean that this generation can arrive at any time, at the end or during DMA process */
/* So STOP condition should be manage through Interrupt treatment */
@@ -4368,7 +4433,7 @@
*/
static void FMPI2C_DMAError(DMA_HandleTypeDef *hdma)
{
- FMPI2C_HandleTypeDef* hfmpi2c = ( FMPI2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ FMPI2C_HandleTypeDef *hfmpi2c = (FMPI2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Disable Acknowledge */
hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
@@ -4380,12 +4445,12 @@
/**
* @brief DMA FMPI2C communication abort callback
* (To be called at end of DMA Abort procedure).
- * @param hdma: DMA handle.
+ * @param hdma DMA handle.
* @retval None
*/
static void FMPI2C_DMAAbort(DMA_HandleTypeDef *hdma)
{
- FMPI2C_HandleTypeDef* hfmpi2c = ( FMPI2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ FMPI2C_HandleTypeDef *hfmpi2c = (FMPI2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Disable Acknowledge */
hfmpi2c->Instance->CR2 |= FMPI2C_CR2_NACK;
@@ -4395,10 +4460,10 @@
hfmpi2c->hdmarx->XferAbortCallback = NULL;
/* Check if come from abort from user */
- if(hfmpi2c->State == HAL_FMPI2C_STATE_ABORT)
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_ABORT)
{
hfmpi2c->State = HAL_FMPI2C_STATE_READY;
-
+
/* Call the corresponding callback to inform upper layer of End of Transfer */
HAL_FMPI2C_AbortCpltCallback(hfmpi2c);
}
@@ -4421,14 +4486,14 @@
*/
static HAL_StatusTypeDef FMPI2C_WaitOnFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
{
- while(__HAL_FMPI2C_GET_FLAG(hfmpi2c, Flag) == Status)
+ while (__HAL_FMPI2C_GET_FLAG(hfmpi2c, Flag) == Status)
{
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
+ if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
{
- hfmpi2c->State= HAL_FMPI2C_STATE_READY;
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
/* Process Unlocked */
@@ -4450,21 +4515,21 @@
*/
static HAL_StatusTypeDef FMPI2C_WaitOnTXISFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart)
{
- while(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TXIS) == RESET)
+ while (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_TXIS) == RESET)
{
/* Check if a NACK is detected */
- if(FMPI2C_IsAcknowledgeFailed(hfmpi2c, Timeout, Tickstart) != HAL_OK)
+ if (FMPI2C_IsAcknowledgeFailed(hfmpi2c, Timeout, Tickstart) != HAL_OK)
{
return HAL_ERROR;
}
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout))
+ if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
{
hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
- hfmpi2c->State= HAL_FMPI2C_STATE_READY;
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
/* Process Unlocked */
@@ -4487,19 +4552,19 @@
*/
static HAL_StatusTypeDef FMPI2C_WaitOnSTOPFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart)
{
- while(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == RESET)
+ while (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == RESET)
{
/* Check if a NACK is detected */
- if(FMPI2C_IsAcknowledgeFailed(hfmpi2c, Timeout, Tickstart) != HAL_OK)
+ if (FMPI2C_IsAcknowledgeFailed(hfmpi2c, Timeout, Tickstart) != HAL_OK)
{
return HAL_ERROR;
}
/* Check for the Timeout */
- if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout))
+ if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
{
hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
- hfmpi2c->State= HAL_FMPI2C_STATE_READY;
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
/* Process Unlocked */
@@ -4521,38 +4586,49 @@
*/
static HAL_StatusTypeDef FMPI2C_WaitOnRXNEFlagUntilTimeout(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart)
{
- while(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_RXNE) == RESET)
+ while (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_RXNE) == RESET)
{
/* Check if a NACK is detected */
- if(FMPI2C_IsAcknowledgeFailed(hfmpi2c, Timeout, Tickstart) != HAL_OK)
+ if (FMPI2C_IsAcknowledgeFailed(hfmpi2c, Timeout, Tickstart) != HAL_OK)
{
return HAL_ERROR;
}
/* Check if a STOPF is detected */
- if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == SET)
+ if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == SET)
{
- /* Clear STOP Flag */
- __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
-
- /* Clear Configuration Register 2 */
- FMPI2C_RESET_CR2(hfmpi2c);
-
- hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
- hfmpi2c->State= HAL_FMPI2C_STATE_READY;
- hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hfmpi2c);
-
- return HAL_ERROR;
+ /* Check if an RXNE is pending */
+ /* Store Last receive data if any */
+ if ((__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_RXNE) == SET) && (hfmpi2c->XferSize > 0U))
+ {
+ /* Return HAL_OK */
+ /* The Reading of data from RXDR will be done in caller function */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Clear STOP Flag */
+ __HAL_FMPI2C_CLEAR_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ FMPI2C_RESET_CR2(hfmpi2c);
+
+ hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_NONE;
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
+ hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hfmpi2c);
+
+ return HAL_ERROR;
+ }
}
/* Check for the Timeout */
- if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout))
+ if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
{
hfmpi2c->ErrorCode |= HAL_FMPI2C_ERROR_TIMEOUT;
- hfmpi2c->State= HAL_FMPI2C_STATE_READY;
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
@@ -4573,18 +4649,18 @@
*/
static HAL_StatusTypeDef FMPI2C_IsAcknowledgeFailed(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t Timeout, uint32_t Tickstart)
{
- if(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) == SET)
+ if (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_AF) == SET)
{
/* Wait until STOP Flag is reset */
/* AutoEnd should be initiate after AF */
- while(__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == RESET)
+ while (__HAL_FMPI2C_GET_FLAG(hfmpi2c, FMPI2C_FLAG_STOPF) == RESET)
{
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout))
+ if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
{
- hfmpi2c->State= HAL_FMPI2C_STATE_READY;
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
/* Process Unlocked */
@@ -4607,7 +4683,7 @@
FMPI2C_RESET_CR2(hfmpi2c);
hfmpi2c->ErrorCode = HAL_FMPI2C_ERROR_AF;
- hfmpi2c->State= HAL_FMPI2C_STATE_READY;
+ hfmpi2c->State = HAL_FMPI2C_STATE_READY;
hfmpi2c->Mode = HAL_FMPI2C_MODE_NONE;
/* Process Unlocked */
@@ -4639,25 +4715,14 @@
*/
static void FMPI2C_TransferConfig(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
{
- uint32_t tmpreg = 0U;
-
/* Check the parameters */
assert_param(IS_FMPI2C_ALL_INSTANCE(hfmpi2c->Instance));
assert_param(IS_TRANSFER_MODE(Mode));
assert_param(IS_TRANSFER_REQUEST(Request));
- /* Get the CR2 register value */
- tmpreg = hfmpi2c->Instance->CR2;
-
- /* clear tmpreg specific bits */
- tmpreg &= (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_AUTOEND | FMPI2C_CR2_RD_WRN | FMPI2C_CR2_START | FMPI2C_CR2_STOP));
-
- /* update tmpreg */
- tmpreg |= (uint32_t)(((uint32_t)DevAddress & FMPI2C_CR2_SADD) | (((uint32_t)Size << 16U) & FMPI2C_CR2_NBYTES) | \
- (uint32_t)Mode | (uint32_t)Request);
-
/* update CR2 register */
- hfmpi2c->Instance->CR2 = tmpreg;
+ MODIFY_REG(hfmpi2c->Instance->CR2, ((FMPI2C_CR2_SADD | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_AUTOEND | (FMPI2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - FMPI2C_CR2_RD_WRN_Pos))) | FMPI2C_CR2_START | FMPI2C_CR2_STOP)), \
+ (uint32_t)(((uint32_t)DevAddress & FMPI2C_CR2_SADD) | (((uint32_t)Size << FMPI2C_CR2_NBYTES_Pos) & FMPI2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));
}
/**
@@ -4671,28 +4736,28 @@
{
uint32_t tmpisr = 0U;
- if((hfmpi2c->XferISR == FMPI2C_Master_ISR_DMA) || \
- (hfmpi2c->XferISR == FMPI2C_Slave_ISR_DMA))
+ if ((hfmpi2c->XferISR == FMPI2C_Master_ISR_DMA) || \
+ (hfmpi2c->XferISR == FMPI2C_Slave_ISR_DMA))
{
- if((InterruptRequest & FMPI2C_XFER_LISTEN_IT) == FMPI2C_XFER_LISTEN_IT)
+ if ((InterruptRequest & FMPI2C_XFER_LISTEN_IT) == FMPI2C_XFER_LISTEN_IT)
{
/* Enable ERR, STOP, NACK and ADDR interrupts */
tmpisr |= FMPI2C_IT_ADDRI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_ERRI;
}
- if((InterruptRequest & FMPI2C_XFER_ERROR_IT) == FMPI2C_XFER_ERROR_IT)
+ if ((InterruptRequest & FMPI2C_XFER_ERROR_IT) == FMPI2C_XFER_ERROR_IT)
{
/* Enable ERR and NACK interrupts */
tmpisr |= FMPI2C_IT_ERRI | FMPI2C_IT_NACKI;
}
- if((InterruptRequest & FMPI2C_XFER_CPLT_IT) == FMPI2C_XFER_CPLT_IT)
+ if ((InterruptRequest & FMPI2C_XFER_CPLT_IT) == FMPI2C_XFER_CPLT_IT)
{
/* Enable STOP interrupts */
tmpisr |= FMPI2C_IT_STOPI;
}
-
- if((InterruptRequest & FMPI2C_XFER_RELOAD_IT) == FMPI2C_XFER_RELOAD_IT)
+
+ if ((InterruptRequest & FMPI2C_XFER_RELOAD_IT) == FMPI2C_XFER_RELOAD_IT)
{
/* Enable TC interrupts */
tmpisr |= FMPI2C_IT_TCI;
@@ -4700,31 +4765,31 @@
}
else
{
- if((InterruptRequest & FMPI2C_XFER_LISTEN_IT) == FMPI2C_XFER_LISTEN_IT)
+ if ((InterruptRequest & FMPI2C_XFER_LISTEN_IT) == FMPI2C_XFER_LISTEN_IT)
{
/* Enable ERR, STOP, NACK, and ADDR interrupts */
tmpisr |= FMPI2C_IT_ADDRI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_ERRI;
}
- if((InterruptRequest & FMPI2C_XFER_TX_IT) == FMPI2C_XFER_TX_IT)
+ if ((InterruptRequest & FMPI2C_XFER_TX_IT) == FMPI2C_XFER_TX_IT)
{
/* Enable ERR, TC, STOP, NACK and RXI interrupts */
tmpisr |= FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_TXI;
}
- if((InterruptRequest & FMPI2C_XFER_RX_IT) == FMPI2C_XFER_RX_IT)
+ if ((InterruptRequest & FMPI2C_XFER_RX_IT) == FMPI2C_XFER_RX_IT)
{
/* Enable ERR, TC, STOP, NACK and TXI interrupts */
tmpisr |= FMPI2C_IT_ERRI | FMPI2C_IT_TCI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_RXI;
}
- if((InterruptRequest & FMPI2C_XFER_CPLT_IT) == FMPI2C_XFER_CPLT_IT)
+ if ((InterruptRequest & FMPI2C_XFER_CPLT_IT) == FMPI2C_XFER_CPLT_IT)
{
/* Enable STOP interrupts */
tmpisr |= FMPI2C_IT_STOPI;
}
}
-
+
/* Enable interrupts only at the end */
/* to avoid the risk of FMPI2C interrupt handle execution before */
/* all interrupts requested done */
@@ -4744,49 +4809,49 @@
{
uint32_t tmpisr = 0U;
- if((InterruptRequest & FMPI2C_XFER_TX_IT) == FMPI2C_XFER_TX_IT)
+ if ((InterruptRequest & FMPI2C_XFER_TX_IT) == FMPI2C_XFER_TX_IT)
{
/* Disable TC and TXI interrupts */
tmpisr |= FMPI2C_IT_TCI | FMPI2C_IT_TXI;
- if((hfmpi2c->State & HAL_FMPI2C_STATE_LISTEN) != HAL_FMPI2C_STATE_LISTEN)
+ if ((hfmpi2c->State & HAL_FMPI2C_STATE_LISTEN) != HAL_FMPI2C_STATE_LISTEN)
{
/* Disable NACK and STOP interrupts */
tmpisr |= FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_ERRI;
}
}
- if((InterruptRequest & FMPI2C_XFER_RX_IT) == FMPI2C_XFER_RX_IT)
+ if ((InterruptRequest & FMPI2C_XFER_RX_IT) == FMPI2C_XFER_RX_IT)
{
/* Disable TC and RXI interrupts */
tmpisr |= FMPI2C_IT_TCI | FMPI2C_IT_RXI;
- if((hfmpi2c->State & HAL_FMPI2C_STATE_LISTEN) != HAL_FMPI2C_STATE_LISTEN)
+ if ((hfmpi2c->State & HAL_FMPI2C_STATE_LISTEN) != HAL_FMPI2C_STATE_LISTEN)
{
/* Disable NACK and STOP interrupts */
tmpisr |= FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_ERRI;
}
}
- if((InterruptRequest & FMPI2C_XFER_LISTEN_IT) == FMPI2C_XFER_LISTEN_IT)
+ if ((InterruptRequest & FMPI2C_XFER_LISTEN_IT) == FMPI2C_XFER_LISTEN_IT)
{
/* Disable ADDR, NACK and STOP interrupts */
tmpisr |= FMPI2C_IT_ADDRI | FMPI2C_IT_STOPI | FMPI2C_IT_NACKI | FMPI2C_IT_ERRI;
}
- if((InterruptRequest & FMPI2C_XFER_ERROR_IT) == FMPI2C_XFER_ERROR_IT)
+ if ((InterruptRequest & FMPI2C_XFER_ERROR_IT) == FMPI2C_XFER_ERROR_IT)
{
/* Enable ERR and NACK interrupts */
tmpisr |= FMPI2C_IT_ERRI | FMPI2C_IT_NACKI;
}
- if((InterruptRequest & FMPI2C_XFER_CPLT_IT) == FMPI2C_XFER_CPLT_IT)
+ if ((InterruptRequest & FMPI2C_XFER_CPLT_IT) == FMPI2C_XFER_CPLT_IT)
{
/* Enable STOP interrupts */
tmpisr |= FMPI2C_IT_STOPI;
}
-
- if((InterruptRequest & FMPI2C_XFER_RELOAD_IT) == FMPI2C_XFER_RELOAD_IT)
+
+ if ((InterruptRequest & FMPI2C_XFER_RELOAD_IT) == FMPI2C_XFER_RELOAD_IT)
{
/* Enable TC interrupts */
tmpisr |= FMPI2C_IT_TCI;
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_fmpi2c.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_fmpi2c.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_fmpi2c.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief Header file of FMPI2C HAL module.
******************************************************************************
* @attention
@@ -40,14 +38,14 @@
#define __STM32F4xx_HAL_FMPI2C_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
/* Includes ------------------------------------------------------------------*/
-#include "stm32f4xx_hal_def.h"
+#include "stm32f4xx_hal_def.h"
/** @addtogroup STM32F4xx_HAL_Driver
* @{
@@ -55,7 +53,7 @@
/** @addtogroup FMPI2C
* @{
- */
+ */
/* Exported types ------------------------------------------------------------*/
/** @defgroup FMPI2C_Exported_Types FMPI2C Exported Types
@@ -63,13 +61,13 @@
*/
/** @defgroup FMPI2C_Configuration_Structure_definition FMPI2C Configuration Structure definition
- * @brief FMPI2C Configuration Structure definition
+ * @brief FMPI2C Configuration Structure definition
* @{
*/
typedef struct
{
uint32_t Timing; /*!< Specifies the FMPI2C_TIMINGR_register value.
- This parameter calculated by referring to FMPI2C initialization
+ This parameter calculated by referring to FMPI2C initialization
section in Reference manual */
uint32_t OwnAddress1; /*!< Specifies the first device own address.
@@ -93,56 +91,56 @@
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
This parameter can be a value of @ref FMPI2C_NOSTRETCH_MODE */
-}FMPI2C_InitTypeDef;
+} FMPI2C_InitTypeDef;
-/**
+/**
* @}
*/
/** @defgroup HAL_state_structure_definition HAL state structure definition
* @brief HAL State structure definition
- * @note HAL FMPI2C State value coding follow below described bitmap :
- * b7-b6 Error information
- * 00 : No Error
- * 01 : Abort (Abort user request on going)
- * 10 : Timeout
- * 11 : Error
- * b5 IP initilisation status
- * 0 : Reset (IP not initialized)
- * 1 : Init done (IP initialized and ready to use. HAL FMPI2C Init function called)
- * b4 (not used)
- * x : Should be set to 0
- * b3
- * 0 : Ready or Busy (No Listen mode ongoing)
- * 1 : Listen (IP in Address Listen Mode)
- * b2 Intrinsic process state
- * 0 : Ready
- * 1 : Busy (IP busy with some configuration or internal operations)
- * b1 Rx state
- * 0 : Ready (no Rx operation ongoing)
- * 1 : Busy (Rx operation ongoing)
- * b0 Tx state
- * 0 : Ready (no Tx operation ongoing)
+ * @note HAL FMPI2C State value coding follow below described bitmap :\n
+ * b7-b6 Error information\n
+ * 00 : No Error\n
+ * 01 : Abort (Abort user request on going)\n
+ * 10 : Timeout\n
+ * 11 : Error\n
+ * b5 IP initilisation status\n
+ * 0 : Reset (IP not initialized)\n
+ * 1 : Init done (IP initialized and ready to use. HAL FMPI2C Init function called)\n
+ * b4 (not used)\n
+ * x : Should be set to 0\n
+ * b3\n
+ * 0 : Ready or Busy (No Listen mode ongoing)\n
+ * 1 : Listen (IP in Address Listen Mode)\n
+ * b2 Intrinsic process state\n
+ * 0 : Ready\n
+ * 1 : Busy (IP busy with some configuration or internal operations)\n
+ * b1 Rx state\n
+ * 0 : Ready (no Rx operation ongoing)\n
+ * 1 : Busy (Rx operation ongoing)\n
+ * b0 Tx state\n
+ * 0 : Ready (no Tx operation ongoing)\n
* 1 : Busy (Tx operation ongoing)
* @{
- */
+ */
typedef enum
{
HAL_FMPI2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
HAL_FMPI2C_STATE_READY = 0x20U, /*!< Peripheral Initialized and ready for use */
HAL_FMPI2C_STATE_BUSY = 0x24U, /*!< An internal process is ongoing */
- HAL_FMPI2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */
+ HAL_FMPI2C_STATE_BUSY_TX = 0x21U, /*!< Data Transmission process is ongoing */
HAL_FMPI2C_STATE_BUSY_RX = 0x22U, /*!< Data Reception process is ongoing */
HAL_FMPI2C_STATE_LISTEN = 0x28U, /*!< Address Listen Mode is ongoing */
HAL_FMPI2C_STATE_BUSY_TX_LISTEN = 0x29U, /*!< Address Listen Mode and Data Transmission
- process is ongoing */
+ process is ongoing */
HAL_FMPI2C_STATE_BUSY_RX_LISTEN = 0x2AU, /*!< Address Listen Mode and Data Reception
- process is ongoing */
+ process is ongoing */
HAL_FMPI2C_STATE_ABORT = 0x60U, /*!< Abort user request ongoing */
HAL_FMPI2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
- HAL_FMPI2C_STATE_ERROR = 0xE0U /*!< Error */
+ HAL_FMPI2C_STATE_ERROR = 0xE0U /*!< Error */
-}HAL_FMPI2C_StateTypeDef;
+} HAL_FMPI2C_StateTypeDef;
/**
* @}
@@ -150,19 +148,19 @@
/** @defgroup HAL_mode_structure_definition HAL mode structure definition
* @brief HAL Mode structure definition
- * @note HAL FMPI2C Mode value coding follow below described bitmap :
- * b7 (not used)
- * x : Should be set to 0
- * b6
- * 0 : None
- * 1 : Memory (HAL FMPI2C communication is in Memory Mode)
- * b5
- * 0 : None
- * 1 : Slave (HAL FMPI2C communication is in Slave Mode)
- * b4
- * 0 : None
- * 1 : Master (HAL FMPI2C communication is in Master Mode)
- * b3-b2-b1-b0 (not used)
+ * @note HAL FMPI2C Mode value coding follow below described bitmap :\n
+ * b7 (not used)\n
+ * x : Should be set to 0\n
+ * b6\n
+ * 0 : None\n
+ * 1 : Memory (HAL FMPI2C communication is in Memory Mode)\n
+ * b5\n
+ * 0 : None\n
+ * 1 : Slave (HAL FMPI2C communication is in Slave Mode)\n
+ * b4\n
+ * 0 : None\n
+ * 1 : Master (HAL FMPI2C communication is in Master Mode)\n
+ * b3-b2-b1-b0 (not used)\n
* xxxx : Should be set to 0000
* @{
*/
@@ -173,30 +171,30 @@
HAL_FMPI2C_MODE_SLAVE = 0x20U, /*!< FMPI2C communication is in Slave Mode */
HAL_FMPI2C_MODE_MEM = 0x40U /*!< FMPI2C communication is in Memory Mode */
-}HAL_FMPI2C_ModeTypeDef;
+} HAL_FMPI2C_ModeTypeDef;
-/**
+/**
* @}
*/
/** @defgroup FMPI2C_Error_Code_definition FMPI2C Error Code definition
- * @brief FMPI2C Error Code definition
+ * @brief FMPI2C Error Code definition
* @{
*/
-#define HAL_FMPI2C_ERROR_NONE 0x00000000U /*!< No error */
-#define HAL_FMPI2C_ERROR_BERR 0x00000001U /*!< BERR error */
-#define HAL_FMPI2C_ERROR_ARLO 0x00000002U /*!< ARLO error */
-#define HAL_FMPI2C_ERROR_AF 0x00000004U /*!< ACKF error */
-#define HAL_FMPI2C_ERROR_OVR 0x00000008U /*!< OVR error */
-#define HAL_FMPI2C_ERROR_DMA 0x00000010U /*!< DMA transfer error */
-#define HAL_FMPI2C_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */
-#define HAL_FMPI2C_ERROR_SIZE 0x00000040U /*!< Size Management error */
+#define HAL_FMPI2C_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_FMPI2C_ERROR_BERR (0x00000001U) /*!< BERR error */
+#define HAL_FMPI2C_ERROR_ARLO (0x00000002U) /*!< ARLO error */
+#define HAL_FMPI2C_ERROR_AF (0x00000004U) /*!< ACKF error */
+#define HAL_FMPI2C_ERROR_OVR (0x00000008U) /*!< OVR error */
+#define HAL_FMPI2C_ERROR_DMA (0x00000010U) /*!< DMA transfer error */
+#define HAL_FMPI2C_ERROR_TIMEOUT (0x00000020U) /*!< Timeout error */
+#define HAL_FMPI2C_ERROR_SIZE (0x00000040U) /*!< Size Management error */
/**
* @}
*/
/** @defgroup FMPI2C_handle_Structure_definition FMPI2C handle Structure definition
- * @brief FMPI2C handle Structure definition
+ * @brief FMPI2C handle Structure definition
* @{
*/
typedef struct __FMPI2C_HandleTypeDef
@@ -205,33 +203,33 @@
FMPI2C_InitTypeDef Init; /*!< FMPI2C communication parameters */
- uint8_t *pBuffPtr; /*!< Pointer to FMPI2C transfer buffer */
+ uint8_t *pBuffPtr; /*!< Pointer to FMPI2C transfer buffer */
- uint16_t XferSize; /*!< FMPI2C transfer size */
+ uint16_t XferSize; /*!< FMPI2C transfer size */
- __IO uint16_t XferCount; /*!< FMPI2C transfer counter */
+ __IO uint16_t XferCount; /*!< FMPI2C transfer counter */
- __IO uint32_t XferOptions; /*!< FMPI2C sequantial transfer options, this parameter can
+ __IO uint32_t XferOptions; /*!< FMPI2C sequantial transfer options, this parameter can
be a value of @ref FMPI2C_XFEROPTIONS */
- __IO uint32_t PreviousState; /*!< FMPI2C communication Previous state */
+ __IO uint32_t PreviousState; /*!< FMPI2C communication Previous state */
- HAL_StatusTypeDef (*XferISR)(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources); /*!< FMPI2C transfer IRQ handler function pointer */
+ HAL_StatusTypeDef(*XferISR)(struct __FMPI2C_HandleTypeDef *hfmpi2c, uint32_t ITFlags, uint32_t ITSources); /*!< FMPI2C transfer IRQ handler function pointer */
- DMA_HandleTypeDef *hdmatx; /*!< FMPI2C Tx DMA handle parameters */
+ DMA_HandleTypeDef *hdmatx; /*!< FMPI2C Tx DMA handle parameters */
- DMA_HandleTypeDef *hdmarx; /*!< FMPI2C Rx DMA handle parameters */
+ DMA_HandleTypeDef *hdmarx; /*!< FMPI2C Rx DMA handle parameters */
- HAL_LockTypeDef Lock; /*!< FMPI2C locking object */
+ HAL_LockTypeDef Lock; /*!< FMPI2C locking object */
__IO HAL_FMPI2C_StateTypeDef State; /*!< FMPI2C communication state */
__IO HAL_FMPI2C_ModeTypeDef Mode; /*!< FMPI2C communication mode */
- __IO uint32_t ErrorCode; /*!< FMPI2C Error code */
+ __IO uint32_t ErrorCode; /*!< FMPI2C Error code */
- __IO uint32_t AddrEventCount; /*!< FMPI2C Address Event counter */
-}FMPI2C_HandleTypeDef;
+ __IO uint32_t AddrEventCount; /*!< FMPI2C Address Event counter */
+} FMPI2C_HandleTypeDef;
/**
* @}
*/
@@ -253,6 +251,7 @@
#define FMPI2C_NEXT_FRAME ((uint32_t)(FMPI2C_RELOAD_MODE | FMPI2C_SOFTEND_MODE))
#define FMPI2C_FIRST_AND_LAST_FRAME ((uint32_t)FMPI2C_AUTOEND_MODE)
#define FMPI2C_LAST_FRAME ((uint32_t)FMPI2C_AUTOEND_MODE)
+#define FMPI2C_LAST_FRAME_NO_STOP ((uint32_t)FMPI2C_SOFTEND_MODE)
/**
* @}
*/
@@ -260,8 +259,8 @@
/** @defgroup FMPI2C_ADDRESSING_MODE FMPI2C Addressing Mode
* @{
*/
-#define FMPI2C_ADDRESSINGMODE_7BIT 0x00000001U
-#define FMPI2C_ADDRESSINGMODE_10BIT 0x00000002U
+#define FMPI2C_ADDRESSINGMODE_7BIT (0x00000001U)
+#define FMPI2C_ADDRESSINGMODE_10BIT (0x00000002U)
/**
* @}
*/
@@ -269,7 +268,7 @@
/** @defgroup FMPI2C_DUAL_ADDRESSING_MODE FMPI2C Dual Addressing Mode
* @{
*/
-#define FMPI2C_DUALADDRESS_DISABLE 0x00000000U
+#define FMPI2C_DUALADDRESS_DISABLE (0x00000000U)
#define FMPI2C_DUALADDRESS_ENABLE FMPI2C_OAR2_OA2EN
/**
* @}
@@ -278,7 +277,6 @@
/** @defgroup FMPI2C_OWN_ADDRESS2_MASKS FMPI2C Own Address2 Masks
* @{
*/
-
#define FMPI2C_OA2_NOMASK ((uint8_t)0x00)
#define FMPI2C_OA2_MASK01 ((uint8_t)0x01)
#define FMPI2C_OA2_MASK02 ((uint8_t)0x02)
@@ -287,7 +285,6 @@
#define FMPI2C_OA2_MASK05 ((uint8_t)0x05)
#define FMPI2C_OA2_MASK06 ((uint8_t)0x06)
#define FMPI2C_OA2_MASK07 ((uint8_t)0x07)
-
/**
* @}
*/
@@ -295,7 +292,7 @@
/** @defgroup FMPI2C_GENERAL_CALL_ADDRESSING_MODE FMPI2C General Call Addressing Mode
* @{
*/
-#define FMPI2C_GENERALCALL_DISABLE 0x00000000U
+#define FMPI2C_GENERALCALL_DISABLE (0x00000000U)
#define FMPI2C_GENERALCALL_ENABLE FMPI2C_CR1_GCEN
/**
* @}
@@ -304,7 +301,7 @@
/** @defgroup FMPI2C_NOSTRETCH_MODE FMPI2C No-Stretch Mode
* @{
*/
-#define FMPI2C_NOSTRETCH_DISABLE 0x00000000U
+#define FMPI2C_NOSTRETCH_DISABLE (0x00000000U)
#define FMPI2C_NOSTRETCH_ENABLE FMPI2C_CR1_NOSTRETCH
/**
* @}
@@ -313,19 +310,17 @@
/** @defgroup FMPI2C_MEMORY_ADDRESS_SIZE FMPI2C Memory Address Size
* @{
*/
-#define FMPI2C_MEMADD_SIZE_8BIT 0x00000001U
-#define FMPI2C_MEMADD_SIZE_16BIT 0x00000002U
-
+#define FMPI2C_MEMADD_SIZE_8BIT (0x00000001U)
+#define FMPI2C_MEMADD_SIZE_16BIT (0x00000002U)
/**
* @}
*/
-
-/** @defgroup FMPI2C_XferDirection FMPI2C Transfer Direction
+
+/** @defgroup FMPI2C_XFERDIRECTION FMPI2C Transfer Direction Master Point of View
* @{
*/
-#define FMPI2C_DIRECTION_RECEIVE 0x00000000U
-#define FMPI2C_DIRECTION_TRANSMIT 0x00000001U
-
+#define FMPI2C_DIRECTION_TRANSMIT (0x00000000U)
+#define FMPI2C_DIRECTION_RECEIVE (0x00000001U)
/**
* @}
*/
@@ -335,8 +330,7 @@
*/
#define FMPI2C_RELOAD_MODE FMPI2C_CR2_RELOAD
#define FMPI2C_AUTOEND_MODE FMPI2C_CR2_AUTOEND
-#define FMPI2C_SOFTEND_MODE 0x00000000U
-
+#define FMPI2C_SOFTEND_MODE (0x00000000U)
/**
* @}
*/
@@ -344,12 +338,10 @@
/** @defgroup FMPI2C_START_STOP_MODE FMPI2C Start or Stop Mode
* @{
*/
-
-#define FMPI2C_NO_STARTSTOP 0x00000000U
-#define FMPI2C_GENERATE_STOP FMPI2C_CR2_STOP
-#define FMPI2C_GENERATE_START_READ (uint32_t)(FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN)
-#define FMPI2C_GENERATE_START_WRITE FMPI2C_CR2_START
-
+#define FMPI2C_NO_STARTSTOP (0x00000000U)
+#define FMPI2C_GENERATE_STOP (uint32_t)(0x80000000U | FMPI2C_CR2_STOP)
+#define FMPI2C_GENERATE_START_READ (uint32_t)(0x80000000U | FMPI2C_CR2_START | FMPI2C_CR2_RD_WRN)
+#define FMPI2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | FMPI2C_CR2_START)
/**
* @}
*/
@@ -373,7 +365,7 @@
/** @defgroup FMPI2C_Flag_definition FMPI2C Flag definition
* @{
- */
+ */
#define FMPI2C_FLAG_TXE FMPI2C_ISR_TXE
#define FMPI2C_FLAG_TXIS FMPI2C_ISR_TXIS
#define FMPI2C_FLAG_RXNE FMPI2C_ISR_RXNE
@@ -399,7 +391,7 @@
*/
/* Exported macros -----------------------------------------------------------*/
-
+
/** @defgroup FMPI2C_Exported_Macros FMPI2C Exported Macros
* @{
*/
@@ -437,11 +429,11 @@
* @arg @ref FMPI2C_IT_ADDRI Address match interrupt enable
* @arg @ref FMPI2C_IT_RXI RX interrupt enable
* @arg @ref FMPI2C_IT_TXI TX interrupt enable
- *
+ *
* @retval None
*/
#define __HAL_FMPI2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
-
+
/** @brief Check whether the specified FMPI2C interrupt source is enabled or not.
* @param __HANDLE__ specifies the FMPI2C Handle.
* @param __INTERRUPT__ specifies the FMPI2C interrupt source to check.
@@ -493,16 +485,16 @@
* @arg @ref FMPI2C_FLAG_STOPF STOP detection flag
* @arg @ref FMPI2C_FLAG_BERR Bus error
* @arg @ref FMPI2C_FLAG_ARLO Arbitration lost
- * @arg @ref FMPI2C_FLAG_OVR Overrun/Underrun
+ * @arg @ref FMPI2C_FLAG_OVR Overrun/Underrun
* @arg @ref FMPI2C_FLAG_PECERR PEC error in reception
- * @arg @ref FMPI2C_FLAG_TIMEOUT Timeout or Tlow detection flag
+ * @arg @ref FMPI2C_FLAG_TIMEOUT Timeout or Tlow detection flag
* @arg @ref FMPI2C_FLAG_ALERT SMBus alert
*
* @retval None
*/
#define __HAL_FMPI2C_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) == FMPI2C_FLAG_TXE) ? ((__HANDLE__)->Instance->ISR |= (__FLAG__)) \
: ((__HANDLE__)->Instance->ICR = (__FLAG__)))
-
+
/** @brief Enable the specified FMPI2C peripheral.
* @param __HANDLE__ specifies the FMPI2C Handle.
* @retval None
@@ -516,7 +508,7 @@
#define __HAL_FMPI2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, FMPI2C_CR1_PE))
/** @brief Generate a Non-Acknowledge FMPI2C peripheral in Slave mode.
- * @param __HANDLE__: specifies the FMPI2C Handle.
+ * @param __HANDLE__ specifies the FMPI2C Handle.
* @retval None
*/
#define __HAL_FMPI2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, FMPI2C_CR2_NACK))
@@ -537,7 +529,7 @@
*/
/* Initialization and de-initialization functions******************************/
HAL_StatusTypeDef HAL_FMPI2C_Init(FMPI2C_HandleTypeDef *hfmpi2c);
-HAL_StatusTypeDef HAL_FMPI2C_DeInit (FMPI2C_HandleTypeDef *hfmpi2c);
+HAL_StatusTypeDef HAL_FMPI2C_DeInit(FMPI2C_HandleTypeDef *hfmpi2c);
void HAL_FMPI2C_MspInit(FMPI2C_HandleTypeDef *hfmpi2c);
void HAL_FMPI2C_MspDeInit(FMPI2C_HandleTypeDef *hfmpi2c);
/**
@@ -548,7 +540,7 @@
* @{
*/
/* IO operation functions ****************************************************/
- /******* Blocking mode: Polling */
+/******* Blocking mode: Polling */
HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_FMPI2C_Master_Receive(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
@@ -557,7 +549,7 @@
HAL_StatusTypeDef HAL_FMPI2C_Mem_Read(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_FMPI2C_IsDeviceReady(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
- /******* Non-Blocking mode: Interrupt */
+/******* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size);
@@ -573,7 +565,7 @@
HAL_StatusTypeDef HAL_FMPI2C_DisableListen_IT(FMPI2C_HandleTypeDef *hfmpi2c);
HAL_StatusTypeDef HAL_FMPI2C_Master_Abort_IT(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress);
- /******* Non-Blocking mode: DMA */
+/******* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_FMPI2C_Master_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_FMPI2C_Master_Receive_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_FMPI2C_Slave_Transmit_DMA(FMPI2C_HandleTypeDef *hfmpi2c, uint8_t *pData, uint16_t Size);
@@ -602,7 +594,7 @@
void HAL_FMPI2C_AbortCpltCallback(FMPI2C_HandleTypeDef *hfmpi2c);
/**
* @}
- */
+ */
/** @addtogroup FMPI2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
* @{
@@ -614,11 +606,11 @@
/**
* @}
- */
+ */
/**
* @}
- */
+ */
/* Private constants ---------------------------------------------------------*/
/** @defgroup FMPI2C_Private_Constants FMPI2C Private Constants
@@ -627,7 +619,7 @@
/**
* @}
- */
+ */
/* Private macros ------------------------------------------------------------*/
/** @defgroup FMPI2C_Private_Macro FMPI2C Private Macros
@@ -635,19 +627,19 @@
*/
#define IS_FMPI2C_ADDRESSING_MODE(MODE) (((MODE) == FMPI2C_ADDRESSINGMODE_7BIT) || \
- ((MODE) == FMPI2C_ADDRESSINGMODE_10BIT))
+ ((MODE) == FMPI2C_ADDRESSINGMODE_10BIT))
#define IS_FMPI2C_DUAL_ADDRESS(ADDRESS) (((ADDRESS) == FMPI2C_DUALADDRESS_DISABLE) || \
- ((ADDRESS) == FMPI2C_DUALADDRESS_ENABLE))
+ ((ADDRESS) == FMPI2C_DUALADDRESS_ENABLE))
#define IS_FMPI2C_OWN_ADDRESS2_MASK(MASK) (((MASK) == FMPI2C_OA2_NOMASK) || \
- ((MASK) == FMPI2C_OA2_MASK01) || \
- ((MASK) == FMPI2C_OA2_MASK02) || \
- ((MASK) == FMPI2C_OA2_MASK03) || \
- ((MASK) == FMPI2C_OA2_MASK04) || \
- ((MASK) == FMPI2C_OA2_MASK05) || \
- ((MASK) == FMPI2C_OA2_MASK06) || \
- ((MASK) == FMPI2C_OA2_MASK07))
+ ((MASK) == FMPI2C_OA2_MASK01) || \
+ ((MASK) == FMPI2C_OA2_MASK02) || \
+ ((MASK) == FMPI2C_OA2_MASK03) || \
+ ((MASK) == FMPI2C_OA2_MASK04) || \
+ ((MASK) == FMPI2C_OA2_MASK05) || \
+ ((MASK) == FMPI2C_OA2_MASK06) || \
+ ((MASK) == FMPI2C_OA2_MASK07))
#define IS_FMPI2C_GENERAL_CALL(CALL) (((CALL) == FMPI2C_GENERALCALL_DISABLE) || \
((CALL) == FMPI2C_GENERALCALL_ENABLE))
@@ -671,7 +663,8 @@
((REQUEST) == FMPI2C_FIRST_AND_NEXT_FRAME) || \
((REQUEST) == FMPI2C_NEXT_FRAME) || \
((REQUEST) == FMPI2C_FIRST_AND_LAST_FRAME) || \
- ((REQUEST) == FMPI2C_LAST_FRAME))
+ ((REQUEST) == FMPI2C_LAST_FRAME) || \
+ ((REQUEST) == FMPI2C_LAST_FRAME_NO_STOP))
#define FMPI2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(FMPI2C_CR2_SADD | FMPI2C_CR2_HEAD10R | FMPI2C_CR2_NBYTES | FMPI2C_CR2_RELOAD | FMPI2C_CR2_RD_WRN)))
@@ -684,14 +677,14 @@
#define IS_FMPI2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x000003FFU)
#define IS_FMPI2C_OWN_ADDRESS2(ADDRESS2) ((ADDRESS2) <= (uint16_t)0x00FF)
-#define FMPI2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)0xFF00)) >> 8U)))
-#define FMPI2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)0x00FF)))
+#define FMPI2C_MEM_ADD_MSB(__ADDRESS__) ((uint8_t)((uint16_t)(((uint16_t)((__ADDRESS__) & (uint16_t)(0xFF00))) >> 8U)))
+#define FMPI2C_MEM_ADD_LSB(__ADDRESS__) ((uint8_t)((uint16_t)((__ADDRESS__) & (uint16_t)(0x00FF))))
#define FMPI2C_GENERATE_START(__ADDMODE__,__ADDRESS__) (((__ADDMODE__) == FMPI2C_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_START) | (FMPI2C_CR2_AUTOEND)) & (~FMPI2C_CR2_RD_WRN)) : \
(uint32_t)((((uint32_t)(__ADDRESS__) & (FMPI2C_CR2_SADD)) | (FMPI2C_CR2_ADD10) | (FMPI2C_CR2_START)) & (~FMPI2C_CR2_RD_WRN)))
/**
* @}
- */
+ */
/* Private Functions ---------------------------------------------------------*/
/** @defgroup FMPI2C_Private_Functions FMPI2C Private Functions
@@ -700,11 +693,11 @@
/* Private functions are defined in stm32f4xx_hal_fmpi2c.c file */
/**
* @}
- */
+ */
/**
* @}
- */
+ */
/**
* @}
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_fmpi2c_ex.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_fmpi2c_ex.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,36 +2,31 @@
******************************************************************************
* @file stm32f4xx_hal_fmpi2c_ex.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief FMPI2C Extended HAL module driver.
- * This file provides firmware functions to manage the following
+ * This file provides firmware functions to manage the following
* functionalities of FMPI2C Extended peripheral:
* + Extended features functions
- *
+ *
@verbatim
==============================================================================
##### FMPI2C peripheral Extended features #####
==============================================================================
-
+
[..] Comparing to other previous devices, the FMPI2C interface for STM32F4xx
devices contains the following additional features
-
+
(+) Possibility to disable or enable Analog Noise Filter
(+) Use of a configured Digital Noise Filter
- (+) Disable or enable wakeup from Stop mode
-
+ (+) Disable or enable Fast Mode Plus
+
##### How to use this driver #####
==============================================================================
[..] This driver provides functions to configure Noise Filter and Wake Up Feature
(#) Configure FMPI2C Analog noise filter using the function HAL_FMPI2CEx_ConfigAnalogFilter()
(#) Configure FMPI2C Digital noise filter using the function HAL_FMPI2CEx_ConfigDigitalFilter()
- (#) Configure the enable or disable of FMPI2C Wake Up Mode using the functions :
- (++) HAL_FMPI2CEx_EnableWakeUp()
- (++) HAL_FMPI2CEx_DisableWakeUp()
(#) Configure the enable or disable of fast mode plus driving capability using the functions :
(++) HAL_FMPI2CEx_EnableFastModePlus()
- (++) HAL_FMPI2CEx_DisbleFastModePlus()
+ (++) HAL_FMPI2CEx_DisableFastModePlus()
@endverbatim
******************************************************************************
* @attention
@@ -60,7 +55,7 @@
* OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
- ******************************************************************************
+ ******************************************************************************
*/
/* Includes ------------------------------------------------------------------*/
@@ -93,21 +88,21 @@
/** @defgroup FMPI2CEx_Exported_Functions_Group1 Extended features functions
* @brief Extended features functions
- *
-@verbatim
+ *
+@verbatim
===============================================================================
##### Extended features functions #####
- ===============================================================================
+ ===============================================================================
[..] This section provides functions allowing to:
- (+) Configure Noise Filters
- (+) Configure Wake Up Feature
+ (+) Configure Noise Filters
+ (+) Configure Fast Mode Plus
@endverbatim
* @{
*/
-
+
/**
- * @brief Configure FMPI2C Analog noise filter.
+ * @brief Configure FMPI2C Analog noise filter.
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
* the configuration information for the specified FMPI2Cx peripheral.
* @param AnalogFilter New state of the Analog filter.
@@ -119,8 +114,8 @@
assert_param(IS_FMPI2C_ALL_INSTANCE(hfmpi2c->Instance));
assert_param(IS_FMPI2C_ANALOG_FILTER(AnalogFilter));
- if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
- {
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ {
/* Process Locked */
__HAL_LOCK(hfmpi2c);
@@ -142,7 +137,7 @@
/* Process Unlocked */
__HAL_UNLOCK(hfmpi2c);
- return HAL_OK;
+ return HAL_OK;
}
else
{
@@ -151,10 +146,10 @@
}
/**
- * @brief Configure FMPI2C Digital noise filter.
+ * @brief Configure FMPI2C Digital noise filter.
* @param hfmpi2c Pointer to a FMPI2C_HandleTypeDef structure that contains
* the configuration information for the specified FMPI2Cx peripheral.
- * @param DigitalFilter Coefficient of digital noise filter between 0x00 and 0x0F.
+ * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_FMPI2CEx_ConfigDigitalFilter(FMPI2C_HandleTypeDef *hfmpi2c, uint32_t DigitalFilter)
@@ -165,7 +160,7 @@
assert_param(IS_FMPI2C_ALL_INSTANCE(hfmpi2c->Instance));
assert_param(IS_FMPI2C_DIGITAL_FILTER(DigitalFilter));
- if(hfmpi2c->State == HAL_FMPI2C_STATE_READY)
+ if (hfmpi2c->State == HAL_FMPI2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hfmpi2c);
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_fmpi2c_ex.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_fmpi2c_ex.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_fmpi2c_ex.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief Header file of FMPI2C HAL Extended module.
******************************************************************************
* @attention
@@ -40,7 +38,7 @@
#define __STM32F4xx_HAL_FMPI2C_EX_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F412Zx) ||\
@@ -55,7 +53,7 @@
/** @addtogroup FMPI2CEx
* @{
- */
+ */
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
@@ -67,8 +65,8 @@
/** @defgroup FMPI2CEx_Analog_Filter FMPI2C Extended Analog Filter
* @{
*/
-#define FMPI2C_ANALOGFILTER_ENABLE 0x00000000U
-#define FMPI2C_ANALOGFILTER_DISABLE FMPI2C_CR1_ANFOFF
+#define FMPI2C_ANALOGFILTER_ENABLE 0x00000000U
+#define FMPI2C_ANALOGFILTER_DISABLE FMPI2C_CR1_ANFOFF
/**
* @}
*/
@@ -84,8 +82,8 @@
/**
* @}
- */
-
+ */
+
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
@@ -111,7 +109,7 @@
/**
* @}
- */
+ */
/* Private macros ------------------------------------------------------------*/
/** @defgroup FMPI2CEx_Private_Macro FMPI2C Extended Private Macros
@@ -159,5 +157,4 @@
#endif /* __STM32F4xx_HAL_FMPI2C_EX_H */
-
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_gpio.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_gpio.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_gpio.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief GPIO HAL module driver. * This file provides firmware functions to manage the following * functionalities of the General Purpose Input/Output (GPIO) peripheral: @@ -180,9 +178,9 @@ /** * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F429X device or + * @param GPIOx where x can be (A..K) to select the GPIO peripheral for STM32F429X device or * x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices. - * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains + * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ @@ -305,9 +303,9 @@ /** * @brief De-initializes the GPIOx peripheral registers to their default reset values. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F429X device or + * @param GPIOx where x can be (A..K) to select the GPIO peripheral for STM32F429X device or * x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices. - * @param GPIO_Pin: specifies the port bit to be written. + * @param GPIO_Pin specifies the port bit to be written. * This parameter can be one of GPIO_PIN_x where x can be (0..15). * @retval None */ @@ -386,9 +384,9 @@ /** * @brief Reads the specified input port pin. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F429X device or + * @param GPIOx where x can be (A..K) to select the GPIO peripheral for STM32F429X device or * x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices. - * @param GPIO_Pin: specifies the port bit to read. + * @param GPIO_Pin specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ @@ -417,11 +415,11 @@ * accesses. In this way, there is no risk of an IRQ occurring between * the read and the modify access. * - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral for STM32F429X device or + * @param GPIOx where x can be (A..K) to select the GPIO peripheral for STM32F429X device or * x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices. - * @param GPIO_Pin: specifies the port bit to be written. + * @param GPIO_Pin specifies the port bit to be written. * This parameter can be one of GPIO_PIN_x where x can be (0..15). - * @param PinState: specifies the value to be written to the selected bit. + * @param PinState specifies the value to be written to the selected bit. * This parameter can be one of the GPIO_PinState enum values: * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin @@ -445,9 +443,9 @@ /** * @brief Toggles the specified GPIO pins. - * @param GPIOx: Where x can be (A..K) to select the GPIO peripheral for STM32F429X device or + * @param GPIOx Where x can be (A..K) to select the GPIO peripheral for STM32F429X device or * x can be (A..I) to select the GPIO peripheral for STM32F40XX and STM32F427X devices. - * @param GPIO_Pin: Specifies the pins to be toggled. + * @param GPIO_Pin Specifies the pins to be toggled. * @retval None */ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) @@ -464,8 +462,8 @@ * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. * @note The configuration of the locked GPIO pins can no longer be modified * until the next reset. - * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F4 family - * @param GPIO_Pin: specifies the port bit to be locked. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F4 family + * @param GPIO_Pin specifies the port bit to be locked. * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). * @retval None */ @@ -499,7 +497,7 @@ /** * @brief This function handles EXTI interrupt request. - * @param GPIO_Pin: Specifies the pins connected EXTI line + * @param GPIO_Pin Specifies the pins connected EXTI line * @retval None */ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) @@ -514,7 +512,7 @@ /** * @brief EXTI line detection callbacks. - * @param GPIO_Pin: Specifies the pins connected EXTI line + * @param GPIO_Pin Specifies the pins connected EXTI line * @retval None */ __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_gpio.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_gpio.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_gpio.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of GPIO HAL module. ****************************************************************************** * @attention @@ -187,7 +185,7 @@ /** * @brief Checks whether the specified EXTI line flag is set or not. - * @param __EXTI_LINE__: specifies the EXTI line flag to check. + * @param __EXTI_LINE__ specifies the EXTI line flag to check. * This parameter can be GPIO_PIN_x where x can be(0..15) * @retval The new state of __EXTI_LINE__ (SET or RESET). */ @@ -195,7 +193,7 @@ /** * @brief Clears the EXTI's line pending flags. - * @param __EXTI_LINE__: specifies the EXTI lines flags to clear. + * @param __EXTI_LINE__ specifies the EXTI lines flags to clear. * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) * @retval None */ @@ -203,7 +201,7 @@ /** * @brief Checks whether the specified EXTI line is asserted or not. - * @param __EXTI_LINE__: specifies the EXTI line to check. + * @param __EXTI_LINE__ specifies the EXTI line to check. * This parameter can be GPIO_PIN_x where x can be(0..15) * @retval The new state of __EXTI_LINE__ (SET or RESET). */ @@ -211,7 +209,7 @@ /** * @brief Clears the EXTI's line pending bits. - * @param __EXTI_LINE__: specifies the EXTI lines to clear. + * @param __EXTI_LINE__ specifies the EXTI lines to clear. * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) * @retval None */ @@ -219,7 +217,7 @@ /** * @brief Generates a Software interrupt on selected EXTI line. - * @param __EXTI_LINE__: specifies the EXTI line to check. + * @param __EXTI_LINE__ specifies the EXTI line to check. * This parameter can be GPIO_PIN_x where x can be(0..15) * @retval None */
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_gpio_ex.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_gpio_ex.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_gpio_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of GPIO HAL Extension module. ****************************************************************************** * @attention @@ -544,6 +542,7 @@ */ #define GPIO_AF5_SPI1 ((uint8_t)0x05) /* SPI1 Alternate Function mapping */ #define GPIO_AF5_SPI2 ((uint8_t)0x05) /* SPI2/I2S2 Alternate Function mapping */ +#define GPIO_AF5_SPI3 ((uint8_t)0x05) /* SPI3 Alternate Function mapping */ #define GPIO_AF5_SPI4 ((uint8_t)0x05) /* SPI4 Alternate Function mapping */ #define GPIO_AF5_I2S3ext ((uint8_t)0x05) /* I2S3ext_SD Alternate Function mapping */
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_hash.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_hash.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_hash.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief HASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the HASH peripheral:
@@ -134,7 +132,7 @@
/**
* @brief DMA HASH Input Data complete callback.
- * @param hdma: DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma)
@@ -206,7 +204,7 @@
/**
* @brief DMA HASH communication error callback.
- * @param hdma: DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void HASH_DMAError(DMA_HandleTypeDef *hdma)
@@ -218,8 +216,8 @@
/**
* @brief Writes the input buffer in data register.
- * @param pInBuffer: Pointer to input buffer
- * @param Size: The size of input buffer
+ * @param pInBuffer Pointer to input buffer
+ * @param Size The size of input buffer
* @retval None
*/
static void HASH_WriteData(uint8_t *pInBuffer, uint32_t Size)
@@ -236,8 +234,8 @@
/**
* @brief Provides the message digest result.
- * @param pMsgDigest: Pointer to the message digest
- * @param Size: The size of the message digest in bytes
+ * @param pMsgDigest Pointer to the message digest
+ * @param Size The size of the message digest in bytes
* @retval None
*/
static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size)
@@ -338,7 +336,7 @@
/**
* @brief Initializes the HASH according to the specified parameters in the
HASH_HandleTypeDef and creates the associated handle.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @retval HAL status
*/
@@ -385,7 +383,7 @@
/**
* @brief DeInitializes the HASH peripheral.
* @note This API must be called before starting a new processing.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @retval HAL status
*/
@@ -423,7 +421,7 @@
/**
* @brief Initializes the HASH MSP.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @retval None
*/
@@ -438,7 +436,7 @@
/**
* @brief DeInitializes HASH MSP.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @retval None
*/
@@ -453,7 +451,7 @@
/**
* @brief Input data transfer complete callback.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @retval None
*/
@@ -468,7 +466,7 @@
/**
* @brief Data transfer Error callback.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @retval None
*/
@@ -484,7 +482,7 @@
/**
* @brief Digest computation complete callback. It is used only with interrupt.
* @note This callback is not relevant with DMA.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @retval None
*/
@@ -520,15 +518,15 @@
/**
* @brief Initializes the HASH peripheral in MD5 mode then processes pInBuffer.
The digest is available in pOutBuffer.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
* If the Size is multiple of 64 bytes, appending the input buffer is possible.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware
* and appending the input buffer is no more possible.
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes.
- * @param Timeout: Timeout value
+ * @param pOutBuffer Pointer to the computed digest. Its size must be 16 bytes.
+ * @param Timeout Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
@@ -597,10 +595,10 @@
/**
* @brief Initializes the HASH peripheral in MD5 mode then writes the pInBuffer.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
* If the Size is multiple of 64 bytes, appending the input buffer is possible.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware
* and appending the input buffer is no more possible.
@@ -644,13 +642,13 @@
/**
* @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
The digest is available in pOutBuffer.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
- * @param Timeout: Timeout value
+ * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.
+ * @param Timeout Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
@@ -719,10 +717,10 @@
/**
* @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
* @note Input buffer size in bytes must be a multiple of 4 otherwise the digest computation is corrupted.
* @retval HAL status
@@ -788,12 +786,12 @@
/**
* @brief Initializes the HASH peripheral in MD5 mode then processes pInBuffer.
* The digest is available in pOutBuffer.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes.
+ * @param pOutBuffer Pointer to the computed digest. Its size must be 16 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
@@ -947,12 +945,12 @@
/**
* @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
* The digest is available in pOutBuffer.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
+ * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
@@ -1105,7 +1103,7 @@
/**
* @brief This function handles HASH interrupt request.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @retval None
*/
@@ -1149,10 +1147,10 @@
/**
* @brief Initializes the HASH peripheral in MD5 mode then enables DMA to
control data transfer. Use HAL_HASH_MD5_Finish() to get the digest.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
* @retval HAL status
*/
@@ -1200,10 +1198,10 @@
/**
* @brief Returns the computed digest in MD5 mode
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes.
- * @param Timeout: Timeout value
+ * @param pOutBuffer Pointer to the computed digest. Its size must be 16 bytes.
+ * @param Timeout Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
@@ -1253,10 +1251,10 @@
/**
* @brief Initializes the HASH peripheral in SHA1 mode then enables DMA to
control data transfer. Use HAL_HASH_SHA1_Finish() to get the digest.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
* @retval HAL status
*/
@@ -1305,10 +1303,10 @@
/**
* @brief Returns the computed digest in SHA1 mode.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
- * @param Timeout: Timeout value
+ * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.
+ * @param Timeout Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
@@ -1378,13 +1376,13 @@
/**
* @brief Initializes the HASH peripheral in HMAC MD5 mode
* then processes pInBuffer. The digest is available in pOutBuffer
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
- * @param Timeout: Timeout value
+ * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.
+ * @param Timeout Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
@@ -1523,13 +1521,13 @@
/**
* @brief Initializes the HASH peripheral in HMAC SHA1 mode
* then processes pInBuffer. The digest is available in pOutBuffer.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
- * @param Timeout: Timeout value
+ * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.
+ * @param Timeout Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
@@ -1687,10 +1685,10 @@
/**
* @brief Initializes the HASH peripheral in HMAC MD5 mode
* then enables DMA to control data transfer.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
* @retval HAL status
*/
@@ -1754,10 +1752,10 @@
/**
* @brief Initializes the HASH peripheral in HMAC SHA1 mode
* then enables DMA to control data transfer.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
* @retval HAL status
*/
@@ -1838,7 +1836,7 @@
/**
* @brief return the HASH state
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @retval HAL state
*/
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_hash.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_hash.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_hash.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief Header file of HASH HAL module.
******************************************************************************
* @attention
@@ -226,13 +224,13 @@
*/
/** @brief Reset HASH handle state
- * @param __HANDLE__: specifies the HASH handle.
+ * @param __HANDLE__ specifies the HASH handle.
* @retval None
*/
#define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HASH_STATE_RESET)
/** @brief Check whether the specified HASH flag is set or not.
- * @param __FLAG__: specifies the flag to check.
+ * @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg HASH_FLAG_DINIS: A new block can be entered into the input buffer.
* @arg HASH_FLAG_DCIS: Digest calculation complete
@@ -265,7 +263,7 @@
/**
* @brief Set the number of valid bits in last word written in Data register
- * @param SIZE: size in byte of last data written in Data register.
+ * @param SIZE size in byte of last data written in Data register.
* @retval None
*/
#define __HAL_HASH_SET_NBVALIDBITS(SIZE) do{HASH->STR &= ~(HASH_STR_NBLW);\
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_hash_ex.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_hash_ex.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_hash_ex.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief HASH HAL Extension module driver.
* This file provides firmware functions to manage the following
* functionalities of HASH peripheral:
@@ -132,8 +130,8 @@
/**
* @brief Writes the input buffer in data register.
- * @param pInBuffer: Pointer to input buffer
- * @param Size: The size of input buffer
+ * @param pInBuffer Pointer to input buffer
+ * @param Size The size of input buffer
* @retval None
*/
static void HASHEx_WriteData(uint8_t *pInBuffer, uint32_t Size)
@@ -150,8 +148,8 @@
/**
* @brief Provides the message digest result.
- * @param pMsgDigest: Pointer to the message digest
- * @param Size: The size of the message digest in bytes
+ * @param pMsgDigest Pointer to the message digest
+ * @param Size The size of the message digest in bytes
* @retval None
*/
static void HASHEx_GetDigest(uint8_t *pMsgDigest, uint8_t Size)
@@ -223,7 +221,7 @@
/**
* @brief DMA HASH Input Data complete callback.
- * @param hdma: DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void HASHEx_DMAXferCplt(DMA_HandleTypeDef *hdma)
@@ -295,7 +293,7 @@
/**
* @brief DMA HASH communication error callback.
- * @param hdma: DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void HASHEx_DMAError(DMA_HandleTypeDef *hdma)
@@ -333,13 +331,13 @@
/**
* @brief Initializes the HASH peripheral in SHA224 mode
* then processes pInBuffer. The digest is available in pOutBuffer
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 28 bytes.
- * @param Timeout: Specify Timeout value
+ * @param pOutBuffer Pointer to the computed digest. Its size must be 28 bytes.
+ * @param Timeout Specify Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
@@ -409,13 +407,13 @@
/**
* @brief Initializes the HASH peripheral in SHA256 mode then processes pInBuffer.
The digest is available in pOutBuffer.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 32 bytes.
- * @param Timeout: Specify Timeout value
+ * @param pOutBuffer Pointer to the computed digest. Its size must be 32 bytes.
+ * @param Timeout Specify Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
@@ -486,10 +484,10 @@
/**
* @brief Initializes the HASH peripheral in SHA224 mode
* then processes pInBuffer. The digest is available in pOutBuffer
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
* @retval HAL status
*/
@@ -532,10 +530,10 @@
/**
* @brief Initializes the HASH peripheral in SHA256 mode then processes pInBuffer.
The digest is available in pOutBuffer.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
* @retval HAL status
*/
@@ -598,13 +596,13 @@
/**
* @brief Initializes the HASH peripheral in HMAC SHA224 mode
* then processes pInBuffer. The digest is available in pOutBuffer.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
- * @param Timeout: Timeout value
+ * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.
+ * @param Timeout Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
@@ -742,13 +740,13 @@
/**
* @brief Initializes the HASH peripheral in HMAC SHA256 mode
* then processes pInBuffer. The digest is available in pOutBuffer
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
- * @param Timeout: Timeout value
+ * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.
+ * @param Timeout Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
@@ -909,12 +907,12 @@
/**
* @brief Initializes the HASH peripheral in SHA224 mode then processes pInBuffer.
* The digest is available in pOutBuffer.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
+ * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
@@ -1060,12 +1058,12 @@
/**
* @brief Initializes the HASH peripheral in SHA256 mode then processes pInBuffer.
* The digest is available in pOutBuffer.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
+ * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
@@ -1209,7 +1207,7 @@
/**
* @brief This function handles HASH interrupt request.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @retval None
*/
@@ -1255,10 +1253,10 @@
/**
* @brief Initializes the HASH peripheral in SHA224 mode then enables DMA to
control data transfer. Use HAL_HASH_SHA224_Finish() to get the digest.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
* @retval HAL status
*/
@@ -1306,10 +1304,10 @@
/**
* @brief Returns the computed digest in SHA224
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 28 bytes.
- * @param Timeout: Timeout value
+ * @param pOutBuffer Pointer to the computed digest. Its size must be 28 bytes.
+ * @param Timeout Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
@@ -1359,10 +1357,10 @@
/**
* @brief Initializes the HASH peripheral in SHA256 mode then enables DMA to
control data transfer. Use HAL_HASH_SHA256_Finish() to get the digest.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
* @retval HAL status
*/
@@ -1410,10 +1408,10 @@
/**
* @brief Returns the computed digest in SHA256.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 32 bytes.
- * @param Timeout: Timeout value
+ * @param pOutBuffer Pointer to the computed digest. Its size must be 32 bytes.
+ * @param Timeout Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
@@ -1483,10 +1481,10 @@
/**
* @brief Initializes the HASH peripheral in HMAC SHA224 mode
* then enables DMA to control data transfer.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
* @retval HAL status
*/
@@ -1550,10 +1548,10 @@
/**
* @brief Initializes the HASH peripheral in HMAC SHA256 mode
* then enables DMA to control data transfer.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
* @retval HAL status
*/
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_hash_ex.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_hash_ex.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_hash_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of HASH HAL Extension module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_hcd.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_hcd.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_hcd.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief HCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@@ -125,7 +123,7 @@
/**
* @brief Initialize the host driver.
- * @param hhcd: HCD handle
+ * @param hhcd HCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
@@ -163,25 +161,25 @@
/**
* @brief Initialize a host channel.
- * @param hhcd: HCD handle
- * @param ch_num: Channel number.
+ * @param hhcd HCD handle
+ * @param ch_num Channel number.
* This parameter can be a value from 1 to 15
- * @param epnum: Endpoint number.
+ * @param epnum Endpoint number.
* This parameter can be a value from 1 to 15
- * @param dev_address : Current device address
+ * @param dev_address Current device address
* This parameter can be a value from 0 to 255
- * @param speed: Current device speed.
+ * @param speed Current device speed.
* This parameter can be one of these values:
* HCD_SPEED_HIGH: High speed mode,
* HCD_SPEED_FULL: Full speed mode,
* HCD_SPEED_LOW: Low speed mode
- * @param ep_type: Endpoint Type.
+ * @param ep_type Endpoint Type.
* This parameter can be one of these values:
* EP_TYPE_CTRL: Control type,
* EP_TYPE_ISOC: Isochronous type,
* EP_TYPE_BULK: Bulk type,
* EP_TYPE_INTR: Interrupt type
- * @param mps: Max Packet Size.
+ * @param mps Max Packet Size.
* This parameter can be a value from 0 to32K
* @retval HAL status
*/
@@ -201,12 +199,14 @@
hhcd->hc[ch_num].max_packet = mps;
hhcd->hc[ch_num].ch_num = ch_num;
hhcd->hc[ch_num].ep_type = ep_type;
- hhcd->hc[ch_num].ep_num = epnum & 0x7FU;
- hhcd->hc[ch_num].ep_is_in = ((epnum & 0x80U) == 0x80U);
+ hhcd->hc[ch_num].ep_num = epnum & 0x7F;
+ hhcd->hc[ch_num].ep_is_in = ((epnum & 0x80) == 0x80);
hhcd->hc[ch_num].speed = speed;
+/* MBED */
/* reset to 0 */
hhcd->hc[ch_num].toggle_out = 0;
hhcd->hc[ch_num].toggle_in = 0;
+/* MBED */
status = USB_HC_Init(hhcd->Instance,
ch_num,
@@ -222,8 +222,8 @@
/**
* @brief Halt a host channel.
- * @param hhcd: HCD handle
- * @param ch_num: Channel number.
+ * @param hhcd HCD handle
+ * @param ch_num Channel number.
* This parameter can be a value from 1 to 15
* @retval HAL status
*/
@@ -240,7 +240,7 @@
/**
* @brief DeInitialize the host driver.
- * @param hhcd: HCD handle
+ * @param hhcd HCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd)
@@ -265,7 +265,7 @@
/**
* @brief Initialize the HCD MSP.
- * @param hhcd: HCD handle
+ * @param hhcd HCD handle
* @retval None
*/
__weak void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd)
@@ -279,7 +279,7 @@
/**
* @brief DeInitialize the HCD MSP.
- * @param hhcd: HCD handle
+ * @param hhcd HCD handle
* @retval None
*/
__weak void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd)
@@ -311,24 +311,24 @@
/**
* @brief Submit a new URB for processing.
- * @param hhcd: HCD handle
- * @param ch_num: Channel number.
+ * @param hhcd HCD handle
+ * @param ch_num Channel number.
* This parameter can be a value from 1 to 15
- * @param direction: Channel number.
+ * @param direction Channel number.
* This parameter can be one of these values:
* 0 : Output / 1 : Input
- * @param ep_type: Endpoint Type.
+ * @param ep_type Endpoint Type.
* This parameter can be one of these values:
* EP_TYPE_CTRL: Control type/
* EP_TYPE_ISOC: Isochronous type/
* EP_TYPE_BULK: Bulk type/
* EP_TYPE_INTR: Interrupt type/
- * @param token: Endpoint Type.
+ * @param token Endpoint Type.
* This parameter can be one of these values:
* 0: HC_PID_SETUP / 1: HC_PID_DATA1
- * @param pbuff: pointer to URB data
- * @param length: Length of URB data
- * @param do_ping: activate do ping protocol (for high speed only).
+ * @param pbuff pointer to URB data
+ * @param length Length of URB data
+ * @param do_ping activate do ping protocol (for high speed only).
* This parameter can be one of these values:
* 0 : do ping inactive / 1 : do ping active
* @retval HAL status
@@ -342,6 +342,7 @@
uint16_t length,
uint8_t do_ping)
{
+/* MBED */
if ((hhcd->hc[ch_num].ep_is_in != direction)) {
if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL)){
/* reconfigure the endpoint !!! from tx -> rx, and rx ->tx */
@@ -361,9 +362,10 @@
if (direction == 1) hhcd->hc[ch_num].toggle_in=1;
}
}
+/* MBED */
hhcd->hc[ch_num].ep_type = ep_type;
- if(token == 0U)
+ if(token == 0)
{
hhcd->hc[ch_num].data_pid = HC_PID_SETUP;
}
@@ -397,6 +399,7 @@
hhcd->hc[ch_num].do_ping = do_ping;
}
}
+/* MBED */
else if ((token == 1) && (direction == 1))
{
if( hhcd->hc[ch_num].toggle_in == 0)
@@ -408,6 +411,7 @@
hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
}
}
+/* MBED */
break;
case EP_TYPE_BULK:
@@ -483,7 +487,7 @@
/**
* @brief Handle HCD interrupt request.
- * @param hhcd: HCD handle
+ * @param hhcd HCD handle
* @retval None
*/
void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
@@ -586,7 +590,7 @@
/**
* @brief SOF callback.
- * @param hhcd: HCD handle
+ * @param hhcd HCD handle
* @retval None
*/
__weak void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd)
@@ -600,7 +604,7 @@
/**
* @brief Connection Event callback.
- * @param hhcd: HCD handle
+ * @param hhcd HCD handle
* @retval None
*/
__weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd)
@@ -614,7 +618,7 @@
/**
* @brief Disconnection Event callback.
- * @param hhcd: HCD handle
+ * @param hhcd HCD handle
* @retval None
*/
__weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd)
@@ -628,8 +632,8 @@
/**
* @brief Notify URB state change callback.
- * @param hhcd: HCD handle
- * @param chnum: Channel number.
+ * @param hhcd HCD handle
+ * @param chnum Channel number.
* This parameter can be a value from 1 to 15
* @param urb_state:
* This parameter can be one of these values:
@@ -673,7 +677,7 @@
/**
* @brief Start the host driver.
- * @param hhcd: HCD handle
+ * @param hhcd HCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd)
@@ -687,7 +691,7 @@
/**
* @brief Stop the host driver.
- * @param hhcd: HCD handle
+ * @param hhcd HCD handle
* @retval HAL status
*/
@@ -701,7 +705,7 @@
/**
* @brief Reset the host port.
- * @param hhcd: HCD handle
+ * @param hhcd HCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd)
@@ -730,7 +734,7 @@
/**
* @brief Return the HCD handle state.
- * @param hhcd: HCD handle
+ * @param hhcd HCD handle
* @retval HAL state
*/
HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd)
@@ -740,8 +744,8 @@
/**
* @brief Return URB state for a channel.
- * @param hhcd: HCD handle
- * @param chnum: Channel number.
+ * @param hhcd HCD handle
+ * @param chnum Channel number.
* This parameter can be a value from 1 to 15
* @retval URB state.
* This parameter can be one of these values:
@@ -760,8 +764,8 @@
/**
* @brief Return the last host transfer size.
- * @param hhcd: HCD handle
- * @param chnum: Channel number.
+ * @param hhcd HCD handle
+ * @param chnum Channel number.
* This parameter can be a value from 1 to 15
* @retval last transfer size in byte
*/
@@ -772,8 +776,8 @@
/**
* @brief Return the Host Channel state.
- * @param hhcd: HCD handle
- * @param chnum: Channel number.
+ * @param hhcd HCD handle
+ * @param chnum Channel number.
* This parameter can be a value from 1 to 15
* @retval Host channel state
* This parameter can be one of these values:
@@ -794,7 +798,7 @@
/**
* @brief Return the current Host frame number.
- * @param hhcd: HCD handle
+ * @param hhcd HCD handle
* @retval Current Host frame number
*/
uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd)
@@ -804,7 +808,7 @@
/**
* @brief Return the Host enumeration speed.
- * @param hhcd: HCD handle
+ * @param hhcd HCD handle
* @retval Enumeration speed
*/
uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd)
@@ -825,8 +829,8 @@
*/
/**
* @brief Handle Host Channel IN interrupt requests.
- * @param hhcd: HCD handle
- * @param chnum: Channel number.
+ * @param hhcd HCD handle
+ * @param chnum Channel number.
* This parameter can be a value from 1 to 15
* @retval None
*/
@@ -902,7 +906,9 @@
}
else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_CHH)
{
+/* MBED */
int reactivate=0;
+/* MBED */
__HAL_HCD_MASK_HALT_HC_INT(chnum);
if(hhcd->hc[chnum].state == HC_XFRC)
@@ -931,16 +937,20 @@
/* re-activate the channel */
tmpreg = USBx_HC(chnum)->HCCHAR;
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+/* MBED */
if ( hhcd->hc[chnum].urb_state != URB_ERROR) {
tmpreg |= USB_OTG_HCCHAR_CHENA;
reactivate = 1;
}
+/* MBED */
USBx_HC(chnum)->HCCHAR = tmpreg;
}
+/* MBED */
if (hhcd->hc[chnum].state == 0) reactivate = 1;
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
if (reactivate == 0) HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
+/* MBED */
}
else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_TXERR)
@@ -977,8 +987,8 @@
/**
* @brief Handle Host Channel OUT interrupt requests.
- * @param hhcd: HCD handle
- * @param chnum: Channel number.
+ * @param hhcd HCD handle
+ * @param chnum Channel number.
* This parameter can be a value from 1 to 15
* @retval None
*/
@@ -1115,7 +1125,7 @@
/**
* @brief Handle Rx Queue Level interrupt requests.
- * @param hhcd: HCD handle
+ * @param hhcd HCD handle
* @retval None
*/
static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd)
@@ -1168,7 +1178,7 @@
/**
* @brief Handle Host Port interrupt requests.
- * @param hhcd: HCD handle
+ * @param hhcd HCD handle
* @retval None
*/
static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd)
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_hcd.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_hcd.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_hcd.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of HCD HAL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2c.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2c.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_i2c.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief I2C HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Inter Integrated Circuit (I2C) peripheral:
@@ -349,7 +347,7 @@
/**
* @brief Initializes the I2C according to the specified parameters
* in the I2C_InitTypeDef and create the associated handle.
- * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * @param hi2c pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @retval HAL status
*/
@@ -431,7 +429,7 @@
/**
* @brief DeInitializes the I2C peripheral.
- * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * @param hi2c pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @retval HAL status
*/
@@ -467,7 +465,7 @@
/**
* @brief I2C MSP Init.
- * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * @param hi2c pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @retval None
*/
@@ -482,7 +480,7 @@
/**
* @brief I2C MSP DeInit
- * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains
+ * @param hi2c pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
* @retval None
*/
@@ -567,8 +565,8 @@
* @brief Transmits in master mode an amount of data in blocking mode.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param Timeout Timeout duration
@@ -699,8 +697,8 @@
* @brief Receives in master mode an amount of data in blocking mode.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param Timeout Timeout duration
@@ -1187,8 +1185,8 @@
* @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @retval HAL status
@@ -1264,8 +1262,8 @@
* @brief Receive in master mode an amount of data in non-blocking mode with Interrupt
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @retval HAL status
@@ -1346,8 +1344,8 @@
* @note This interface allow to manage repeated start condition when a direction change during transfer
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
@@ -1449,8 +1447,8 @@
* @note This interface allow to manage repeated start condition when a direction change during transfer
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param XferOptions Options of Transfer, value of @ref I2C_XferOptions_definition
@@ -1911,8 +1909,8 @@
* @brief Transmit in master mode an amount of data in non-blocking mode with DMA
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @retval HAL status
@@ -2031,8 +2029,8 @@
* @brief Receive in master mode an amount of data in non-blocking mode with DMA
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @retval HAL status
@@ -2152,8 +2150,8 @@
* @note This abort can be called only if state is ready
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
@@ -3937,6 +3935,7 @@
/* Read data from DR */
(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
hi2c->XferCount--;
+/* MBED */
}
else if((tmp == 2U) || (tmp == 3U))
{
@@ -3959,6 +3958,7 @@
/* Enable Pos */
hi2c->Instance->CR1 |= I2C_CR1_POS;
}
+/* MBED */
/* Disable EVT, BUF and ERR interrupt */
__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_EVT | I2C_IT_BUF | I2C_IT_ERR);
@@ -3996,6 +3996,7 @@
/* Declaration of temporary variables to prevent undefined behavior of volatile usage */
uint32_t CurrentXferOptions = hi2c->XferOptions;
+/* MBED */
if(hi2c->XferCount == 3U)
{
if((CurrentXferOptions == I2C_FIRST_AND_LAST_FRAME) || (CurrentXferOptions == I2C_LAST_FRAME) || (CurrentXferOptions == I2C_NO_OPTION_FRAME))
@@ -4003,6 +4004,7 @@
/* Disable Acknowledge */
hi2c->Instance->CR1 &= ~I2C_CR1_ACK;
}
+/* MBED */
/* Read data from DR */
(*hi2c->pBuffPtr++) = hi2c->Instance->DR;
@@ -4011,6 +4013,7 @@
else if(hi2c->XferCount == 2U)
{
/* Prepare next transfer or stop current transfer */
+/* MBED */
if((CurrentXferOptions != I2C_FIRST_AND_LAST_FRAME) && (CurrentXferOptions != I2C_LAST_FRAME) && (CurrentXferOptions != I2C_NO_OPTION_FRAME))
{
/* Disable Acknowledge */
@@ -4021,6 +4024,7 @@
/* Generate ReStart */
hi2c->Instance->CR1 |= I2C_CR1_START;
}
+/* MBED */
}
else
{
@@ -4684,8 +4688,8 @@
/**
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
@@ -4760,8 +4764,8 @@
* @brief Master sends target device address for read request.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for I2C module
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * @param DevAddress Target device address The device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param Timeout Timeout duration
* @param Tickstart Tick start value
* @retval HAL status
@@ -5179,7 +5183,7 @@
/**
* @brief DMA I2C communication abort callback
* (To be called at end of DMA Abort procedure).
- * @param hdma: DMA handle.
+ * @param hdma DMA handle.
* @retval None
*/
static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2c.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2c.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_i2c.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief Header file of I2C HAL module.
******************************************************************************
* @attention
@@ -348,16 +346,16 @@
*/
/** @brief Reset I2C handle state
- * @param __HANDLE__: specifies the I2C Handle.
+ * @param __HANDLE__ specifies the I2C Handle.
* This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
* @retval None
*/
#define __HAL_I2C_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2C_STATE_RESET)
/** @brief Enable or disable the specified I2C interrupts.
- * @param __HANDLE__: specifies the I2C Handle.
+ * @param __HANDLE__ specifies the I2C Handle.
* This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
- * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
+ * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
* This parameter can be one of the following values:
* @arg I2C_IT_BUF: Buffer interrupt enable
* @arg I2C_IT_EVT: Event interrupt enable
@@ -368,9 +366,9 @@
#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
/** @brief Checks if the specified I2C interrupt source is enabled or disabled.
- * @param __HANDLE__: specifies the I2C Handle.
+ * @param __HANDLE__ specifies the I2C Handle.
* This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
- * @param __INTERRUPT__: specifies the I2C interrupt source to check.
+ * @param __INTERRUPT__ specifies the I2C interrupt source to check.
* This parameter can be one of the following values:
* @arg I2C_IT_BUF: Buffer interrupt enable
* @arg I2C_IT_EVT: Event interrupt enable
@@ -380,9 +378,9 @@
#define __HAL_I2C_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Checks whether the specified I2C flag is set or not.
- * @param __HANDLE__: specifies the I2C Handle.
+ * @param __HANDLE__ specifies the I2C Handle.
* This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
- * @param __FLAG__: specifies the flag to check.
+ * @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg I2C_FLAG_SMBALERT: SMBus Alert flag
* @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
@@ -412,9 +410,9 @@
((((__HANDLE__)->Instance->SR2) & ((__FLAG__) & I2C_FLAG_MASK)) == ((__FLAG__) & I2C_FLAG_MASK)))
/** @brief Clears the I2C pending flags which are cleared by writing 0 in a specific bit.
- * @param __HANDLE__: specifies the I2C Handle.
+ * @param __HANDLE__ specifies the I2C Handle.
* This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
- * @param __FLAG__: specifies the flag to clear.
+ * @param __FLAG__ specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg I2C_FLAG_SMBALERT: SMBus Alert flag
* @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
@@ -428,7 +426,7 @@
#define __HAL_I2C_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR1 = ~((__FLAG__) & I2C_FLAG_MASK))
/** @brief Clears the I2C ADDR pending flag.
- * @param __HANDLE__: specifies the I2C Handle.
+ * @param __HANDLE__ specifies the I2C Handle.
* This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
* @retval None
*/
@@ -441,7 +439,7 @@
} while(0)
/** @brief Clears the I2C STOPF pending flag.
- * @param __HANDLE__: specifies the I2C Handle.
+ * @param __HANDLE__ specifies the I2C Handle.
* This parameter can be I2C where x: 1, 2, or 3 to select the I2C peripheral.
* @retval None
*/
@@ -454,14 +452,14 @@
} while(0)
/** @brief Enable the I2C peripheral.
- * @param __HANDLE__: specifies the I2C Handle.
+ * @param __HANDLE__ specifies the I2C Handle.
* This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral.
* @retval None
*/
#define __HAL_I2C_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= I2C_CR1_PE)
/** @brief Disable the I2C peripheral.
- * @param __HANDLE__: specifies the I2C Handle.
+ * @param __HANDLE__ specifies the I2C Handle.
* This parameter can be I2Cx where x: 1 or 2 to select the I2C peripheral.
* @retval None
*/
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2c_ex.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2c_ex.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_i2c_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief I2C Extension HAL module driver. * This file provides firmware functions to manage the following * functionalities of I2C extension peripheral: @@ -101,9 +99,9 @@ /** * @brief Configures I2C Analog noise filter. - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * @param hi2c pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2Cx peripheral. - * @param AnalogFilter: new state of the Analog filter. + * @param AnalogFilter new state of the Analog filter. * @retval HAL status */ HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter) @@ -139,9 +137,9 @@ /** * @brief Configures I2C Digital noise filter. - * @param hi2c: pointer to a I2C_HandleTypeDef structure that contains + * @param hi2c pointer to a I2C_HandleTypeDef structure that contains * the configuration information for the specified I2Cx peripheral. - * @param DigitalFilter: Coefficient of digital noise filter between 0x00 and 0x0F. + * @param DigitalFilter Coefficient of digital noise filter between 0x00 and 0x0F. * @retval HAL status */ HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter)
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2c_ex.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2c_ex.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_i2c_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of I2C HAL Extension module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2s.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2s.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_i2s.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief I2S HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Integrated Interchip Sound (I2S) peripheral: @@ -210,7 +208,7 @@ /** * @brief Initializes the I2S according to the specified parameters * in the I2S_InitTypeDef and create the associated handle. - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval HAL status */ @@ -407,7 +405,7 @@ /** * @brief DeInitializes the I2S peripheral - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval HAL status */ @@ -435,7 +433,7 @@ /** * @brief I2S MSP Init - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval None */ @@ -450,7 +448,7 @@ /** * @brief I2S MSP DeInit - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval None */ @@ -510,15 +508,15 @@ /** * @brief Transmit an amount of data in blocking mode - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module - * @param pData: a 16-bit pointer to data buffer. - * @param Size: number of data sample to be sent: + * @param pData a 16-bit pointer to data buffer. + * @param Size number of data sample to be sent: * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected * the Size parameter means the number of 16-bit data length. - * @param Timeout: Timeout duration + * @param Timeout Timeout duration * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * between Master and Slave(example: audio streaming). * @retval HAL status @@ -607,15 +605,15 @@ /** * @brief Receive an amount of data in blocking mode - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module - * @param pData: a 16-bit pointer to data buffer - * @param Size: number of data sample to be sent: + * @param pData a 16-bit pointer to data buffer + * @param Size number of data sample to be sent: * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected * the Size parameter means the number of 16-bit data length. - * @param Timeout: Timeout duration + * @param Timeout Timeout duration * @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization * between Master and Slave(example: audio streaming) * @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate @@ -715,10 +713,10 @@ /** * @brief Transmit an amount of data in non-blocking mode with Interrupt - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module - * @param pData: a 16-bit pointer to data buffer. - * @param Size: number of data sample to be sent: + * @param pData a 16-bit pointer to data buffer. + * @param Size number of data sample to be sent: * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected @@ -780,10 +778,10 @@ /** * @brief Receive an amount of data in non-blocking mode with Interrupt - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module - * @param pData: a 16-bit pointer to the Receive data buffer. - * @param Size: number of data sample to be sent: + * @param pData a 16-bit pointer to the Receive data buffer. + * @param Size number of data sample to be sent: * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected @@ -847,10 +845,10 @@ /** * @brief Transmit an amount of data in non-blocking mode with DMA - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module - * @param pData: a 16-bit pointer to the Transmit data buffer. - * @param Size: number of data sample to be sent: + * @param pData a 16-bit pointer to the Transmit data buffer. + * @param Size number of data sample to be sent: * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected @@ -930,10 +928,10 @@ /** * @brief Receive an amount of data in non-blocking mode with DMA - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module - * @param pData: a 16-bit pointer to the Receive data buffer. - * @param Size: number of data sample to be sent: + * @param pData a 16-bit pointer to the Receive data buffer. + * @param Size number of data sample to be sent: * @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S * configuration phase, the Size parameter means the number of 16-bit data length * in the transaction and when a 24-bit data frame or a 32-bit data frame is selected @@ -1020,7 +1018,7 @@ /** * @brief Pauses the audio stream playing from the Media. - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval HAL status */ @@ -1056,7 +1054,7 @@ /** * @brief Resumes the audio stream playing from the Media. - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval HAL status */ @@ -1106,7 +1104,7 @@ /** * @brief Resumes the audio stream playing from the Media. - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval HAL status */ @@ -1160,7 +1158,7 @@ /** * @brief This function handles I2S interrupt request. - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval None */ @@ -1172,7 +1170,7 @@ /** * @brief Tx Transfer Half completed callbacks - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval None */ @@ -1187,7 +1185,7 @@ /** * @brief Tx Transfer completed callbacks - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval None */ @@ -1202,7 +1200,7 @@ /** * @brief Rx Transfer half completed callbacks - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval None */ @@ -1217,7 +1215,7 @@ /** * @brief Rx Transfer completed callbacks - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval None */ @@ -1232,7 +1230,7 @@ /** * @brief I2S error callbacks - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval None */ @@ -1266,7 +1264,7 @@ /** * @brief Return the I2S state - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval HAL state */ @@ -1277,7 +1275,7 @@ /** * @brief Return the I2S error code - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval I2S Error Code */ @@ -1298,7 +1296,7 @@ */ /** * @brief DMA I2S transmit process complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1318,7 +1316,7 @@ } /** * @brief DMA I2S transmit process half complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1331,7 +1329,7 @@ /** * @brief DMA I2S receive process complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1351,7 +1349,7 @@ /** * @brief DMA I2S receive process half complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1364,7 +1362,7 @@ /** * @brief DMA I2S communication error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1385,7 +1383,7 @@ /** * @brief Transmit an amount of data in non-blocking mode with Interrupt - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval HAL status */ @@ -1407,7 +1405,7 @@ /** * @brief Receive an amount of data in non-blocking mode with Interrupt - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval HAL status */ @@ -1429,7 +1427,7 @@ /** * @brief This function handles I2S interrupt request. - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module * @retval None */ @@ -1493,11 +1491,11 @@ /** * @brief This function handles I2S Communication Timeout. - * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains + * @param hi2s pointer to a I2S_HandleTypeDef structure that contains * the configuration information for I2S module - * @param Flag: Flag checked - * @param State: Value of the flag expected - * @param Timeout: Duration of the timeout + * @param Flag Flag checked + * @param State Value of the flag expected + * @param Timeout Duration of the timeout * @retval HAL status */ static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag, uint32_t State,
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2s.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2s.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_i2s.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of I2S HAL module. ****************************************************************************** * @attention @@ -310,21 +308,21 @@ */ /** @brief Reset I2S handle state - * @param __HANDLE__: specifies the I2S Handle. + * @param __HANDLE__ specifies the I2S Handle. * @retval None */ #define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET) /** @brief Enable or disable the specified SPI peripheral (in I2S mode). - * @param __HANDLE__: specifies the I2S Handle. + * @param __HANDLE__ specifies the I2S Handle. * @retval None */ #define __HAL_I2S_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE) #define __HAL_I2S_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR &=(uint16_t)(~SPI_I2SCFGR_I2SE)) /** @brief Enable or disable the specified I2S interrupts. - * @param __HANDLE__: specifies the I2S Handle. - * @param __INTERRUPT__: specifies the interrupt source to enable or disable. + * @param __HANDLE__ specifies the I2S Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable or disable. * This parameter can be one of the following values: * @arg I2S_IT_TXE: Tx buffer empty interrupt enable * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable @@ -335,9 +333,9 @@ #define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &=(uint16_t)(~(__INTERRUPT__))) /** @brief Checks if the specified I2S interrupt source is enabled or disabled. - * @param __HANDLE__: specifies the I2S Handle. + * @param __HANDLE__ specifies the I2S Handle. * This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral. - * @param __INTERRUPT__: specifies the I2S interrupt source to check. + * @param __INTERRUPT__ specifies the I2S interrupt source to check. * This parameter can be one of the following values: * @arg I2S_IT_TXE: Tx buffer empty interrupt enable * @arg I2S_IT_RXNE: RX buffer not empty interrupt enable @@ -347,8 +345,8 @@ #define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Checks whether the specified I2S flag is set or not. - * @param __HANDLE__: specifies the I2S Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the I2S Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg I2S_FLAG_RXNE: Receive buffer not empty flag * @arg I2S_FLAG_TXE: Transmit buffer empty flag @@ -362,7 +360,7 @@ #define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) /** @brief Clears the I2S OVR pending flag. - * @param __HANDLE__: specifies the I2S Handle. + * @param __HANDLE__ specifies the I2S Handle. * @retval None */ #define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) \ @@ -374,7 +372,7 @@ } while(0) /** @brief Clears the I2S UDR pending flag. - * @param __HANDLE__: specifies the I2S Handle. + * @param __HANDLE__ specifies the I2S Handle. * @retval None */ #define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) \
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2s_ex.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2s_ex.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_i2s_ex.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief I2S HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of I2S extension peripheral:
@@ -136,6 +134,7 @@
/** @defgroup I2SEx_Private_Functions I2S Extended Private Functions
* @{
*/
+static void I2SEx_TxRxDMAHalfCplt(DMA_HandleTypeDef *hdma);
static void I2SEx_TxRxDMACplt(DMA_HandleTypeDef *hdma);
static void I2SEx_TxRxDMAError(DMA_HandleTypeDef *hdma);
static void I2SEx_FullDuplexTx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUsed);
@@ -199,16 +198,16 @@
*/
/**
* @brief Full-Duplex Transmit/Receive data in blocking mode.
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
- * @param pTxData: a 16-bit pointer to the Transmit data buffer.
- * @param pRxData: a 16-bit pointer to the Receive data buffer.
- * @param Size: number of data sample to be sent:
+ * @param pTxData a 16-bit pointer to the Transmit data buffer.
+ * @param pRxData a 16-bit pointer to the Receive data buffer.
+ * @param Size number of data sample to be sent:
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
* configuration phase, the Size parameter means the number of 16-bit data length
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
* the Size parameter means the number of 16-bit data length.
- * @param Timeout: Timeout duration
+ * @param Timeout Timeout duration
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
* between Master and Slave(example: audio streaming).
* @retval HAL status
@@ -454,11 +453,11 @@
/**
* @brief Full-Duplex Transmit/Receive data in non-blocking mode using Interrupt
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
- * @param pTxData: a 16-bit pointer to the Transmit data buffer.
- * @param pRxData: a 16-bit pointer to the Receive data buffer.
- * @param Size: number of data sample to be sent:
+ * @param pTxData a 16-bit pointer to the Transmit data buffer.
+ * @param pRxData a 16-bit pointer to the Receive data buffer.
+ * @param Size number of data sample to be sent:
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
* configuration phase, the Size parameter means the number of 16-bit data length
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
@@ -610,11 +609,11 @@
/**
* @brief Full-Duplex Transmit/Receive data in non-blocking mode using DMA
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
- * @param pTxData: a 16-bit pointer to the Transmit data buffer.
- * @param pRxData: a 16-bit pointer to the Receive data buffer.
- * @param Size: number of data sample to be sent:
+ * @param pTxData a 16-bit pointer to the Transmit data buffer.
+ * @param pRxData a 16-bit pointer to the Receive data buffer.
+ * @param Size number of data sample to be sent:
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
* configuration phase, the Size parameter means the number of 16-bit data length
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
@@ -665,12 +664,18 @@
hi2s->ErrorCode = HAL_I2S_ERROR_NONE;
hi2s->State = HAL_I2S_STATE_BUSY_TX_RX;
+ /* Set the I2S Rx DMA Half transfer complete callback */
+ hi2s->hdmarx->XferHalfCpltCallback = I2SEx_TxRxDMAHalfCplt;
+
/* Set the I2S Rx DMA transfer complete callback */
hi2s->hdmarx->XferCpltCallback = I2SEx_TxRxDMACplt;
/* Set the I2S Rx DMA error callback */
hi2s->hdmarx->XferErrorCallback = I2SEx_TxRxDMAError;
+ /* Set the I2S Tx DMA Half transfer complete callback */
+ hi2s->hdmatx->XferHalfCpltCallback = I2SEx_TxRxDMAHalfCplt;
+
/* Set the I2S Tx DMA transfer complete callback */
hi2s->hdmatx->XferCpltCallback = I2SEx_TxRxDMACplt;
@@ -751,7 +756,7 @@
/**
* @brief This function handles I2S/I2Sext interrupt requests in full-duplex mode.
- * @param hi2s: I2S handle
+ * @param hi2s I2S handle
* @retval HAL status
*/
void HAL_I2SEx_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s)
@@ -875,8 +880,23 @@
}
/**
+ * @brief Tx and Rx Transfer half completed callback
+ * @param hi2s I2S handle
+ * @retval None
+ */
+__weak void HAL_I2SEx_TxRxHalfCpltCallback(I2S_HandleTypeDef *hi2s)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hi2s);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_I2SEx_TxRxHalfCpltCallback could be implemented in the user file
+ */
+}
+
+/**
* @brief Tx and Rx Transfer completed callback
- * @param hi2s: I2S handle
+ * @param hi2s I2S handle
* @retval None
*/
__weak void HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef *hi2s)
@@ -885,7 +905,7 @@
UNUSED(hi2s);
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_I2SEx_TxRxCpltCallback could be implenetd in the user file
+ the HAL_I2SEx_TxRxCpltCallback could be implemented in the user file
*/
}
@@ -902,8 +922,21 @@
*/
/**
+ * @brief DMA I2S transmit receive process half complete callback
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
+ * the configuration information for the specified DMA module.
+ * @retval None
+ */
+static void I2SEx_TxRxDMAHalfCplt(DMA_HandleTypeDef *hdma)
+{
+ I2S_HandleTypeDef* hi2s = (I2S_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+
+ HAL_I2SEx_TxRxHalfCpltCallback(hi2s);
+}
+
+/**
* @brief DMA I2S transmit receive process complete callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -964,7 +997,7 @@
/**
* @brief DMA I2S communication error callback
- * @param hdma : DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void I2SEx_TxRxDMAError(DMA_HandleTypeDef *hdma)
@@ -987,8 +1020,8 @@
/**
* @brief Full-Duplex IT handler transmit function
- * @param hi2s: I2S handle
- * @param i2sUsed: indicate if I2Sx or I2Sx_ext is concerned
+ * @param hi2s I2S handle
+ * @param i2sUsed indicate if I2Sx or I2Sx_ext is concerned
* @retval None
*/
static void I2SEx_FullDuplexTx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUsed)
@@ -1033,8 +1066,8 @@
/**
* @brief Full-Duplex IT handler receive function
- * @param hi2s: I2S handle
- * @param i2sUsed: indicate if I2Sx or I2Sx_ext is concerned
+ * @param hi2s I2S handle
+ * @param i2sUsed indicate if I2Sx or I2Sx_ext is concerned
* @retval None
*/
static void I2SEx_FullDuplexRx_IT(I2S_HandleTypeDef *hi2s, I2S_UseTypeDef i2sUsed)
@@ -1079,11 +1112,11 @@
/**
* @brief This function handles I2S Communication Timeout.
- * @param hi2s: I2S handle
- * @param Flag: Flag checked
- * @param State: Value of the flag expected
- * @param Timeout: Duration of the timeout
- * @param i2sUsed: I2S instance reference
+ * @param hi2s I2S handle
+ * @param Flag Flag checked
+ * @param State Value of the flag expected
+ * @param Timeout Duration of the timeout
+ * @param i2sUsed I2S instance reference
* @retval HAL status
*/
static HAL_StatusTypeDef I2SEx_FullDuplexWaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag,
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2s_ex.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_i2s_ex.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_i2s_ex.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief Header file of I2S HAL module.
******************************************************************************
* @attention
@@ -64,15 +62,15 @@
#define I2SxEXT(__INSTANCE__) ((__INSTANCE__) == (SPI2)? (SPI_TypeDef *)(I2S2ext_BASE): (SPI_TypeDef *)(I2S3ext_BASE))
/** @brief Enable or disable the specified I2SExt peripheral.
- * @param __HANDLE__: specifies the I2S Handle.
+ * @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2SEXT_ENABLE(__HANDLE__) (I2SxEXT((__HANDLE__)->Instance)->I2SCFGR |= SPI_I2SCFGR_I2SE)
#define __HAL_I2SEXT_DISABLE(__HANDLE__) (I2SxEXT((__HANDLE__)->Instance)->I2SCFGR &= ~SPI_I2SCFGR_I2SE)
/** @brief Enable or disable the specified I2SExt interrupts.
- * @param __HANDLE__: specifies the I2S Handle.
- * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
+ * @param __HANDLE__ specifies the I2S Handle.
+ * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
* This parameter can be one of the following values:
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
@@ -83,9 +81,9 @@
#define __HAL_I2SEXT_DISABLE_IT(__HANDLE__, __INTERRUPT__) (I2SxEXT((__HANDLE__)->Instance)->CR2 &= ~(__INTERRUPT__))
/** @brief Checks if the specified I2SExt interrupt source is enabled or disabled.
- * @param __HANDLE__: specifies the I2S Handle.
+ * @param __HANDLE__ specifies the I2S Handle.
* This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
- * @param __INTERRUPT__: specifies the I2S interrupt source to check.
+ * @param __INTERRUPT__ specifies the I2S interrupt source to check.
* This parameter can be one of the following values:
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
@@ -95,8 +93,8 @@
#define __HAL_I2SEXT_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((I2SxEXT((__HANDLE__)->Instance)->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Checks whether the specified I2SExt flag is set or not.
- * @param __HANDLE__: specifies the I2S Handle.
- * @param __FLAG__: specifies the flag to check.
+ * @param __HANDLE__ specifies the I2S Handle.
+ * @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg I2S_FLAG_RXNE: Receive buffer not empty flag
* @arg I2S_FLAG_TXE: Transmit buffer empty flag
@@ -110,7 +108,7 @@
#define __HAL_I2SEXT_GET_FLAG(__HANDLE__, __FLAG__) (((I2SxEXT((__HANDLE__)->Instance)->SR) & (__FLAG__)) == (__FLAG__))
/** @brief Clears the I2SExt OVR pending flag.
- * @param __HANDLE__: specifies the I2S Handle.
+ * @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2SEXT_CLEAR_OVRFLAG(__HANDLE__) do{ \
@@ -120,7 +118,7 @@
UNUSED(tmpreg_ovr); \
}while(0U)
/** @brief Clears the I2SExt UDR pending flag.
- * @param __HANDLE__: specifies the I2S Handle.
+ * @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2SEXT_CLEAR_UDRFLAG(__HANDLE__) do{ \
@@ -153,6 +151,7 @@
uint16_t Size);
/* I2S IRQHandler and Callbacks used in non blocking modes (Interrupt and DMA) */
void HAL_I2SEx_FullDuplex_IRQHandler(I2S_HandleTypeDef *hi2s);
+void HAL_I2SEx_TxRxHalfCpltCallback(I2S_HandleTypeDef *hi2s);
void HAL_I2SEx_TxRxCpltCallback(I2S_HandleTypeDef *hi2s);
/**
* @}
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_irda.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_irda.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_irda.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief IRDA HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the IrDA SIR ENDEC block (IrDA):
@@ -213,7 +211,7 @@
/**
* @brief Initializes the IRDA mode according to the specified
* parameters in the IRDA_InitTypeDef and create the associated handle.
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval HAL status
*/
@@ -274,7 +272,7 @@
/**
* @brief DeInitializes the IRDA peripheral
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval HAL status
*/
@@ -310,7 +308,7 @@
/**
* @brief IRDA MSP Init.
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval None
*/
@@ -325,7 +323,7 @@
/**
* @brief IRDA MSP DeInit.
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval None
*/
@@ -394,11 +392,11 @@
/**
* @brief Sends an amount of data in blocking mode.
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be sent
- * @param Timeout: Specify timeout value
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param Timeout Specify timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Transmit(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
@@ -476,11 +474,11 @@
/**
* @brief Receive an amount of data in blocking mode.
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be received
- * @param Timeout: Specify timeout value
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be received
+ * @param Timeout Specify timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Receive(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size, uint32_t Timeout)
@@ -562,10 +560,10 @@
/**
* @brief Send an amount of data in non blocking mode.
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be sent
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Transmit_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
@@ -602,10 +600,10 @@
/**
* @brief Receives an amount of data in non blocking mode.
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be received
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be received
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Receive_IT(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
@@ -646,10 +644,10 @@
/**
* @brief Sends an amount of data in non blocking mode.
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be sent
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_IRDA_Transmit_DMA(IRDA_HandleTypeDef *hirda, uint8_t *pData, uint16_t Size)
@@ -709,10 +707,10 @@
/**
* @brief Receives an amount of data in non blocking mode.
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be received
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be received
* @note When the IRDA parity is enabled (PCE = 1) the data received contain the parity bit.
* @retval HAL status
*/
@@ -778,7 +776,7 @@
/**
* @brief Pauses the DMA Transfer.
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval HAL status
*/
@@ -815,7 +813,7 @@
/**
* @brief Resumes the DMA Transfer.
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval HAL status
*/
@@ -850,7 +848,7 @@
/**
* @brief Stops the DMA Transfer.
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval HAL status
*/
@@ -1297,7 +1295,7 @@
/**
* @brief This function handles IRDA interrupt request.
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval None
*/
@@ -1424,7 +1422,7 @@
/**
* @brief End ongoing Tx transfer on IRDA peripheral (following error detection or Transmit completion).
- * @param hirda: IRDA handle.
+ * @param hirda IRDA handle.
* @retval None
*/
static void IRDA_EndTxTransfer(IRDA_HandleTypeDef *hirda)
@@ -1438,7 +1436,7 @@
/**
* @brief End ongoing Rx transfer on IRDA peripheral (following error detection or Reception completion).
- * @param hirda: IRDA handle.
+ * @param hirda IRDA handle.
* @retval None
*/
static void IRDA_EndRxTransfer(IRDA_HandleTypeDef *hirda)
@@ -1586,7 +1584,7 @@
/**
* @brief Tx Transfer complete callbacks.
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval None
*/
@@ -1601,7 +1599,7 @@
/**
* @brief Tx Half Transfer completed callbacks.
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval None
*/
@@ -1616,7 +1614,7 @@
/**
* @brief Rx Transfer complete callbacks.
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval None
*/
@@ -1631,7 +1629,7 @@
/**
* @brief Rx Half Transfer complete callbacks.
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval None
*/
@@ -1646,7 +1644,7 @@
/**
* @brief IRDA error callbacks.
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval None
*/
@@ -1727,7 +1725,7 @@
/**
* @brief Returns the IRDA state.
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval HAL state
*/
@@ -1742,7 +1740,7 @@
/**
* @brief Return the IARDA error code
- * @param hirda : pointer to a IRDA_HandleTypeDef structure that contains
+ * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA.
* @retval IRDA Error Code
*/
@@ -1757,7 +1755,7 @@
/**
* @brief DMA IRDA transmit process complete callback.
- * @param hdma : DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void IRDA_DMATransmitCplt(DMA_HandleTypeDef *hdma)
@@ -1784,7 +1782,7 @@
/**
* @brief DMA IRDA receive process half complete callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -1797,7 +1795,7 @@
/**
* @brief DMA IRDA receive process complete callback.
- * @param hdma: DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void IRDA_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
@@ -1825,7 +1823,7 @@
/**
* @brief DMA IRDA receive process half complete callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -1837,7 +1835,7 @@
/**
* @brief DMA IRDA communication error callback.
- * @param hdma: DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void IRDA_DMAError(DMA_HandleTypeDef *hdma)
@@ -1905,7 +1903,7 @@
/**
* @brief Send an amount of data in non blocking mode.
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval HAL status
*/
@@ -1953,7 +1951,7 @@
/**
* @brief Wraps up transmission in non blocking mode.
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval HAL status
*/
@@ -1975,7 +1973,7 @@
/**
* @brief Receives an amount of data in non blocking mode.
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval HAL status
*/
@@ -2042,7 +2040,7 @@
/**
* @brief Configures the IRDA peripheral.
- * @param hirda: pointer to a IRDA_HandleTypeDef structure that contains
+ * @param hirda pointer to a IRDA_HandleTypeDef structure that contains
* the configuration information for the specified IRDA module.
* @retval None
*/
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_irda.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_irda.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_irda.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief Header file of IRDA HAL module.
******************************************************************************
* @attention
@@ -294,7 +292,7 @@
*/
/** @brief Reset IRDA handle gstate & RxState
- * @param __HANDLE__: specifies the USART Handle.
+ * @param __HANDLE__ specifies the USART Handle.
* This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* UART peripheral.
* @retval None
@@ -305,17 +303,17 @@
} while(0U)
/** @brief Flushs the IRDA DR register
- * @param __HANDLE__: specifies the USART Handle.
+ * @param __HANDLE__ specifies the USART Handle.
* This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* UART peripheral.
*/
#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
/** @brief Checks whether the specified IRDA flag is set or not.
- * @param __HANDLE__: specifies the USART Handle.
+ * @param __HANDLE__ specifies the USART Handle.
* This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* UART peripheral.
- * @param __FLAG__: specifies the flag to check.
+ * @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg IRDA_FLAG_TXE: Transmit data register empty flag
* @arg IRDA_FLAG_TC: Transmission Complete flag
@@ -330,10 +328,10 @@
#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
/** @brief Clears the specified IRDA pending flag.
- * @param __HANDLE__: specifies the USART Handle.
+ * @param __HANDLE__ specifies the USART Handle.
* This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* UART peripheral.
- * @param __FLAG__: specifies the flag to check.
+ * @param __FLAG__ specifies the flag to check.
* This parameter can be any combination of the following values:
* @arg IRDA_FLAG_TC: Transmission Complete flag.
* @arg IRDA_FLAG_RXNE: Receive data register not empty flag.
@@ -352,7 +350,7 @@
#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
/** @brief Clear the IRDA PE pending flag.
- * @param __HANDLE__: specifies the USART Handle.
+ * @param __HANDLE__ specifies the USART Handle.
* This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* UART peripheral.
* @retval None
@@ -365,7 +363,7 @@
} while(0U)
/** @brief Clear the IRDA FE pending flag.
- * @param __HANDLE__: specifies the USART Handle.
+ * @param __HANDLE__ specifies the USART Handle.
* This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* UART peripheral.
* @retval None
@@ -373,7 +371,7 @@
#define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
/** @brief Clear the IRDA NE pending flag.
- * @param __HANDLE__: specifies the USART Handle.
+ * @param __HANDLE__ specifies the USART Handle.
* This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* UART peripheral.
* @retval None
@@ -381,7 +379,7 @@
#define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
/** @brief Clear the IRDA ORE pending flag.
- * @param __HANDLE__: specifies the USART Handle.
+ * @param __HANDLE__ specifies the USART Handle.
* This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* UART peripheral.
* @retval None
@@ -389,7 +387,7 @@
#define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
/** @brief Clear the IRDA IDLE pending flag.
- * @param __HANDLE__: specifies the USART Handle.
+ * @param __HANDLE__ specifies the USART Handle.
* This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* UART peripheral.
* @retval None
@@ -397,10 +395,10 @@
#define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__)
/** @brief Enables or disables the specified IRDA interrupt.
- * @param __HANDLE__: specifies the USART Handle.
+ * @param __HANDLE__ specifies the USART Handle.
* This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* UART peripheral.
- * @param __INTERRUPT__: specifies the IRDA interrupt source to check.
+ * @param __INTERRUPT__ specifies the IRDA interrupt source to check.
* This parameter can be one of the following values:
* @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
* @arg IRDA_IT_TC: Transmission complete interrupt
@@ -418,10 +416,10 @@
((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & IRDA_IT_MASK)))
/** @brief Checks whether the specified IRDA interrupt has occurred or not.
- * @param __HANDLE__: specifies the USART Handle.
+ * @param __HANDLE__ specifies the USART Handle.
* This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* UART peripheral.
- * @param __IT__: specifies the IRDA interrupt source to check.
+ * @param __IT__ specifies the IRDA interrupt source to check.
* This parameter can be one of the following values:
* @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
* @arg IRDA_IT_TC: Transmission complete interrupt
@@ -435,19 +433,19 @@
(__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & IRDA_IT_MASK))
/** @brief Macro to enable the IRDA's one bit sample method
- * @param __HANDLE__: specifies the IRDA Handle.
+ * @param __HANDLE__ specifies the IRDA Handle.
* @retval None
*/
#define __HAL_IRDA_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
/** @brief Macro to disable the IRDA's one bit sample method
- * @param __HANDLE__: specifies the IRDA Handle.
+ * @param __HANDLE__ specifies the IRDA Handle.
* @retval None
*/
#define __HAL_IRDA_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
/** @brief Enable UART/USART associated to IRDA Handle
- * @param __HANDLE__: specifies the IRDA Handle.
+ * @param __HANDLE__ specifies the IRDA Handle.
* IRDA Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
* @retval None
@@ -455,7 +453,7 @@
#define __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
/** @brief Disable UART/USART associated to IRDA Handle
- * @param __HANDLE__: specifies the IRDA Handle.
+ * @param __HANDLE__ specifies the IRDA Handle.
* IRDA Handle selects the USARTx or UARTy peripheral
* (USART,UART availability and x,y values depending on device).
* @retval None
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_iwdg.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_iwdg.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_iwdg.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief IWDG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Independent Watchdog (IWDG) peripheral:
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_iwdg.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_iwdg.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_iwdg.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of IWDG HAL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_lptim.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_lptim.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_lptim.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief LPTIM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Low Power Timer (LPTIM) peripheral:
@@ -222,7 +220,7 @@
/**
* @brief Initializes the LPTIM according to the specified parameters in the
* LPTIM_InitTypeDef and creates the associated handle.
- * @param hlptim: LPTIM handle
+ * @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
@@ -315,7 +313,7 @@
/**
* @brief DeInitializes the LPTIM peripheral.
- * @param hlptim: LPTIM handle
+ * @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim)
@@ -347,7 +345,7 @@
/**
* @brief Initializes the LPTIM MSP.
- * @param hlptim: LPTIM handle
+ * @param hlptim LPTIM handle
* @retval None
*/
__weak void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim)
@@ -361,7 +359,7 @@
/**
* @brief DeInitializes LPTIM MSP.
- * @param hlptim: LPTIM handle
+ * @param hlptim LPTIM handle
* @retval None
*/
__weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim)
@@ -405,10 +403,10 @@
/**
* @brief Starts the LPTIM PWM generation.
- * @param hlptim : LPTIM handle
- * @param Period : Specifies the Autoreload value.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
* This parameter must be a value between 0x0000 and 0xFFFF.
- * @param Pulse : Specifies the compare value.
+ * @param Pulse Specifies the compare value.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
*/
@@ -446,7 +444,7 @@
/**
* @brief Stops the LPTIM PWM generation.
- * @param hlptim : LPTIM handle
+ * @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim)
@@ -469,10 +467,10 @@
/**
* @brief Starts the LPTIM PWM generation in interrupt mode.
- * @param hlptim : LPTIM handle
- * @param Period : Specifies the Autoreload value.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
* This parameter must be a value between 0x0000 and 0xFFFF
- * @param Pulse : Specifies the compare value.
+ * @param Pulse Specifies the compare value.
* This parameter must be a value between 0x0000 and 0xFFFF
* @retval HAL status
*/
@@ -529,7 +527,7 @@
/**
* @brief Stops the LPTIM PWM generation in interrupt mode.
- * @param hlptim : LPTIM handle
+ * @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim)
@@ -571,10 +569,10 @@
/**
* @brief Starts the LPTIM One pulse generation.
- * @param hlptim : LPTIM handle
- * @param Period : Specifies the Autoreload value.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
* This parameter must be a value between 0x0000 and 0xFFFF.
- * @param Pulse : Specifies the compare value.
+ * @param Pulse Specifies the compare value.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
*/
@@ -612,7 +610,7 @@
/**
* @brief Stops the LPTIM One pulse generation.
- * @param hlptim : LPTIM handle
+ * @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim)
@@ -635,10 +633,10 @@
/**
* @brief Starts the LPTIM One pulse generation in interrupt mode.
- * @param hlptim : LPTIM handle
- * @param Period : Specifies the Autoreload value.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
* This parameter must be a value between 0x0000 and 0xFFFF.
- * @param Pulse : Specifies the compare value.
+ * @param Pulse Specifies the compare value.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
*/
@@ -695,7 +693,7 @@
/**
* @brief Stops the LPTIM One pulse generation in interrupt mode.
- * @param hlptim : LPTIM handle
+ * @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim)
@@ -737,10 +735,10 @@
/**
* @brief Starts the LPTIM in Set once mode.
- * @param hlptim : LPTIM handle
- * @param Period : Specifies the Autoreload value.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
* This parameter must be a value between 0x0000 and 0xFFFF.
- * @param Pulse : Specifies the compare value.
+ * @param Pulse Specifies the compare value.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
*/
@@ -778,7 +776,7 @@
/**
* @brief Stops the LPTIM Set once mode.
- * @param hlptim : LPTIM handle
+ * @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim)
@@ -801,10 +799,10 @@
/**
* @brief Starts the LPTIM Set once mode in interrupt mode.
- * @param hlptim : LPTIM handle
- * @param Period : Specifies the Autoreload value.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
* This parameter must be a value between 0x0000 and 0xFFFF.
- * @param Pulse : Specifies the compare value.
+ * @param Pulse Specifies the compare value.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
*/
@@ -861,7 +859,7 @@
/**
* @brief Stops the LPTIM Set once mode in interrupt mode.
- * @param hlptim : LPTIM handle
+ * @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim)
@@ -903,8 +901,8 @@
/**
* @brief Starts the Encoder interface.
- * @param hlptim : LPTIM handle
- * @param Period : Specifies the Autoreload value.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
*/
@@ -955,7 +953,7 @@
/**
* @brief Stops the Encoder interface.
- * @param hlptim : LPTIM handle
+ * @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim)
@@ -981,8 +979,8 @@
/**
* @brief Starts the Encoder interface in interrupt mode.
- * @param hlptim : LPTIM handle
- * @param Period : Specifies the Autoreload value.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
*/
@@ -1040,7 +1038,7 @@
/**
* @brief Stops the Encoder interface in interrupt mode.
- * @param hlptim : LPTIM handle
+ * @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim)
@@ -1074,10 +1072,10 @@
* @brief Starts the Timeout function. The first trigger event will start the
* timer, any successive trigger event will reset the counter and
* the timer restarts.
- * @param hlptim : LPTIM handle
- * @param Period : Specifies the Autoreload value.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
* This parameter must be a value between 0x0000 and 0xFFFF.
- * @param Timeout : Specifies the TimeOut value to rest the counter.
+ * @param Timeout Specifies the TimeOut value to rest the counter.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
*/
@@ -1115,7 +1113,7 @@
/**
* @brief Stops the Timeout function.
- * @param hlptim : LPTIM handle
+ * @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim)
@@ -1143,10 +1141,10 @@
* @brief Starts the Timeout function in interrupt mode. The first trigger
* event will start the timer, any successive trigger event will reset
* the counter and the timer restarts.
- * @param hlptim : LPTIM handle
- * @param Period : Specifies the Autoreload value.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
* This parameter must be a value between 0x0000 and 0xFFFF.
- * @param Timeout : Specifies the TimeOut value to rest the counter.
+ * @param Timeout Specifies the TimeOut value to rest the counter.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
*/
@@ -1193,7 +1191,7 @@
/**
* @brief Stops the Timeout function in interrupt mode.
- * @param hlptim : LPTIM handle
+ * @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim)
@@ -1228,8 +1226,8 @@
/**
* @brief Starts the Counter mode.
- * @param hlptim : LPTIM handle
- * @param Period : Specifies the Autoreload value.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
*/
@@ -1269,7 +1267,7 @@
/**
* @brief Stops the Counter mode.
- * @param hlptim : LPTIM handle
+ * @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim)
@@ -1292,8 +1290,8 @@
/**
* @brief Starts the Counter mode in interrupt mode.
- * @param hlptim : LPTIM handle
- * @param Period : Specifies the Autoreload value.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
*/
@@ -1345,7 +1343,7 @@
/**
* @brief Stops the Counter mode in interrupt mode.
- * @param hlptim : LPTIM handle
+ * @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim)
@@ -1399,7 +1397,7 @@
/**
* @brief This function returns the current counter value.
- * @param hlptim: LPTIM handle
+ * @param hlptim LPTIM handle
* @retval Counter value.
*/
uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim)
@@ -1412,7 +1410,7 @@
/**
* @brief This function return the current Autoreload (Period) value.
- * @param hlptim: LPTIM handle
+ * @param hlptim LPTIM handle
* @retval Autoreload value.
*/
uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim)
@@ -1425,7 +1423,7 @@
/**
* @brief This function return the current Compare (Pulse) value.
- * @param hlptim: LPTIM handle
+ * @param hlptim LPTIM handle
* @retval Compare value.
*/
uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim)
@@ -1457,7 +1455,7 @@
/**
* @brief This function handles LPTIM interrupt request.
- * @param hlptim: LPTIM handle
+ * @param hlptim LPTIM handle
* @retval None
*/
void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim)
@@ -1550,7 +1548,7 @@
/**
* @brief Compare match callback in non blocking mode
- * @param hlptim : LPTIM handle
+ * @param hlptim LPTIM handle
* @retval None
*/
__weak void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim)
@@ -1564,7 +1562,7 @@
/**
* @brief Autoreload match callback in non blocking mode
- * @param hlptim : LPTIM handle
+ * @param hlptim LPTIM handle
* @retval None
*/
__weak void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim)
@@ -1578,7 +1576,7 @@
/**
* @brief Trigger detected callback in non blocking mode
- * @param hlptim : LPTIM handle
+ * @param hlptim LPTIM handle
* @retval None
*/
__weak void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim)
@@ -1592,7 +1590,7 @@
/**
* @brief Compare write callback in non blocking mode
- * @param hlptim : LPTIM handle
+ * @param hlptim LPTIM handle
* @retval None
*/
__weak void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim)
@@ -1606,7 +1604,7 @@
/**
* @brief Autoreload write callback in non blocking mode
- * @param hlptim : LPTIM handle
+ * @param hlptim LPTIM handle
* @retval None
*/
__weak void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim)
@@ -1620,7 +1618,7 @@
/**
* @brief Direction counter changed from Down to Up callback in non blocking mode
- * @param hlptim : LPTIM handle
+ * @param hlptim LPTIM handle
* @retval None
*/
__weak void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim)
@@ -1634,7 +1632,7 @@
/**
* @brief Direction counter changed from Up to Down callback in non blocking mode
- * @param hlptim : LPTIM handle
+ * @param hlptim LPTIM handle
* @retval None
*/
__weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim)
@@ -1666,7 +1664,7 @@
/**
* @brief Returns the LPTIM state.
- * @param hlptim: LPTIM handle
+ * @param hlptim LPTIM handle
* @retval HAL state
*/
HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim)
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_lptim.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_lptim.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_lptim.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief Header file of LPTIM HAL module.
******************************************************************************
* @attention
@@ -342,14 +340,14 @@
*/
/** @brief Reset LPTIM handle state
- * @param __HANDLE__: LPTIM handle
+ * @param __HANDLE__ LPTIM handle
* @retval None
*/
#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)
/**
* @brief Enable/Disable the LPTIM peripheral.
- * @param __HANDLE__: LPTIM handle
+ * @param __HANDLE__ LPTIM handle
* @retval None
*/
#define __HAL_LPTIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))
@@ -357,7 +355,7 @@
/**
* @brief Starts the LPTIM peripheral in Continuous or in single mode.
- * @param __HANDLE__: DMA handle
+ * @param __HANDLE__ DMA handle
* @retval None
*/
#define __HAL_LPTIM_START_CONTINUOUS(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT)
@@ -366,24 +364,24 @@
/**
* @brief Writes the passed parameter in the Autoreload register.
- * @param __HANDLE__: LPTIM handle
- * @param __VALUE__ : Autoreload value
+ * @param __HANDLE__ LPTIM handle
+ * @param __VALUE__ Autoreload value
* @retval None
*/
#define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__))
/**
* @brief Writes the passed parameter in the Compare register.
- * @param __HANDLE__: LPTIM handle
- * @param __VALUE__ : Compare value
+ * @param __HANDLE__ LPTIM handle
+ * @param __VALUE__ Compare value
* @retval None
*/
#define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__))
/**
* @brief Checks whether the specified LPTIM flag is set or not.
- * @param __HANDLE__: LPTIM handle
- * @param __FLAG__ : LPTIM flag to check
+ * @param __HANDLE__ LPTIM handle
+ * @param __FLAG__ LPTIM flag to check
* This parameter can be a value of:
* @arg LPTIM_FLAG_DOWN : Counter direction change up Flag.
* @arg LPTIM_FLAG_UP : Counter direction change down to up Flag.
@@ -398,8 +396,8 @@
/**
* @brief Clears the specified LPTIM flag.
- * @param __HANDLE__: LPTIM handle.
- * @param __FLAG__ : LPTIM flag to clear.
+ * @param __HANDLE__ LPTIM handle.
+ * @param __FLAG__ LPTIM flag to clear.
* This parameter can be a value of:
* @arg LPTIM_FLAG_DOWN : Counter direction change up Flag.
* @arg LPTIM_FLAG_UP : Counter direction change down to up Flag.
@@ -414,8 +412,8 @@
/**
* @brief Enable the specified LPTIM interrupt.
- * @param __HANDLE__ : LPTIM handle.
- * @param __INTERRUPT__ : LPTIM interrupt to set.
+ * @param __HANDLE__ LPTIM handle.
+ * @param __INTERRUPT__ LPTIM interrupt to set.
* This parameter can be a value of:
* @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
* @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
@@ -430,8 +428,8 @@
/**
* @brief Disable the specified LPTIM interrupt.
- * @param __HANDLE__ : LPTIM handle.
- * @param __INTERRUPT__ : LPTIM interrupt to set.
+ * @param __HANDLE__ LPTIM handle.
+ * @param __INTERRUPT__ LPTIM interrupt to set.
* This parameter can be a value of:
* @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
* @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
@@ -446,8 +444,8 @@
/**
* @brief Checks whether the specified LPTIM interrupt is set or not.
- * @param __HANDLE__ : LPTIM handle.
- * @param __INTERRUPT__ : LPTIM interrupt to check.
+ * @param __HANDLE__ LPTIM handle.
+ * @param __INTERRUPT__ LPTIM interrupt to check.
* This parameter can be a value of:
* @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
* @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
@@ -462,8 +460,8 @@
#define __HAL_LPTIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief LPTIM Option Register
- * @param __HANDLE__: LPTIM handle
- * @param __VALUE__: This parameter can be a value of :
+ * @param __HANDLE__ LPTIM handle
+ * @param __VALUE__ This parameter can be a value of :
* @arg LPTIM_OP_PAD_AF
* @arg LPTIM_OP_PAD_PA4
* @arg LPTIM_OP_PAD_PB9
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_ltdc.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_ltdc.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_ltdc.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief LTDC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the LTDC peripheral:
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_ltdc.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_ltdc.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_ltdc.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of LTDC HAL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_ltdc_ex.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_ltdc_ex.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_ltdc_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief LTDC Extension HAL module driver. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_ltdc_ex.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_ltdc_ex.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_ltdc_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of LTDC HAL Extension module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_mmc.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_mmc.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_mmc.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief MMC card HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Secure Digital (MMC) peripheral:
@@ -299,7 +297,7 @@
/**
* @brief Initializes the MMC according to the specified parameters in the
MMC_HandleTypeDef and create the associated handle.
- * @param hmmc: Pointer to the MMC handle
+ * @param hmmc Pointer to the MMC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc)
@@ -346,7 +344,7 @@
/**
* @brief Initializes the MMC Card.
- * @param hmmc: Pointer to MMC handle
+ * @param hmmc Pointer to MMC handle
* @note This function initializes the MMC card. It could be used when a card
re-initialization is needed.
* @retval HAL status
@@ -403,7 +401,7 @@
/**
* @brief De-Initializes the MMC card.
- * @param hmmc: Pointer to MMC handle
+ * @param hmmc Pointer to MMC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc)
@@ -434,7 +432,7 @@
/**
* @brief Initializes the MMC MSP.
- * @param hmmc: Pointer to MMC handle
+ * @param hmmc Pointer to MMC handle
* @retval None
*/
__weak void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc)
@@ -449,7 +447,7 @@
/**
* @brief De-Initialize MMC MSP.
- * @param hmmc: Pointer to MMC handle
+ * @param hmmc Pointer to MMC handle
* @retval None
*/
__weak void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc)
@@ -486,11 +484,11 @@
* is managed by polling mode.
* @note This API should be followed by a check on the card state through
* HAL_MMC_GetCardState().
- * @param hmmc: Pointer to MMC handle
- * @param pData: pointer to the buffer that will contain the received data
- * @param BlockAdd: Block Address from where data is to be read
- * @param NumberOfBlocks: Number of MMC blocks to read
- * @param Timeout: Specify timeout value
+ * @param hmmc Pointer to MMC handle
+ * @param pData pointer to the buffer that will contain the received data
+ * @param BlockAdd Block Address from where data is to be read
+ * @param NumberOfBlocks Number of MMC blocks to read
+ * @param Timeout Specify timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
@@ -674,11 +672,11 @@
* transfer is managed by polling mode.
* @note This API should be followed by a check on the card state through
* HAL_MMC_GetCardState().
- * @param hmmc: Pointer to MMC handle
- * @param pData: pointer to the buffer that will contain the data to transmit
- * @param BlockAdd: Block Address where data will be written
- * @param NumberOfBlocks: Number of MMC blocks to write
- * @param Timeout: Specify timeout value
+ * @param hmmc Pointer to MMC handle
+ * @param pData pointer to the buffer that will contain the data to transmit
+ * @param BlockAdd Block Address where data will be written
+ * @param NumberOfBlocks Number of MMC blocks to write
+ * @param Timeout Specify timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
@@ -721,7 +719,7 @@
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
@@ -745,7 +743,7 @@
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
@@ -780,7 +778,7 @@
if((Timeout == 0U)||((HAL_GetTick()-tickstart) >= Timeout))
{
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_TIMEOUT;
@@ -795,7 +793,7 @@
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
@@ -849,10 +847,10 @@
* HAL_MMC_GetCardState().
* @note You could also check the IT transfer process through the MMC Rx
* interrupt event.
- * @param hmmc: Pointer to MMC handle
- * @param pData: Pointer to the buffer that will contain the received data
- * @param BlockAdd: Block Address from where data is to be read
- * @param NumberOfBlocks: Number of blocks to read.
+ * @param hmmc Pointer to MMC handle
+ * @param pData Pointer to the buffer that will contain the received data
+ * @param BlockAdd Block Address from where data is to be read
+ * @param NumberOfBlocks Number of blocks to read.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
@@ -906,7 +904,7 @@
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
@@ -951,10 +949,10 @@
* HAL_MMC_GetCardState().
* @note You could also check the IT transfer process through the MMC Tx
* interrupt event.
- * @param hmmc: Pointer to MMC handle
- * @param pData: Pointer to the buffer that will contain the data to transmit
- * @param BlockAdd: Block Address where data will be written
- * @param NumberOfBlocks: Number of blocks to write
+ * @param hmmc Pointer to MMC handle
+ * @param pData Pointer to the buffer that will contain the data to transmit
+ * @param BlockAdd Block Address where data will be written
+ * @param NumberOfBlocks Number of blocks to write
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
@@ -1000,7 +998,7 @@
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
@@ -1024,7 +1022,7 @@
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
@@ -1054,10 +1052,10 @@
* HAL_MMC_GetCardState().
* @note You could also check the DMA transfer process through the MMC Rx
* interrupt event.
- * @param hmmc: Pointer MMC handle
- * @param pData: Pointer to the buffer that will contain the received data
- * @param BlockAdd: Block Address from where data is to be read
- * @param NumberOfBlocks: Number of blocks to read.
+ * @param hmmc Pointer MMC handle
+ * @param pData Pointer to the buffer that will contain the received data
+ * @param BlockAdd Block Address from where data is to be read
+ * @param NumberOfBlocks Number of blocks to read.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
@@ -1127,7 +1125,7 @@
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
@@ -1151,7 +1149,7 @@
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
@@ -1172,10 +1170,10 @@
* HAL_MMC_GetCardState().
* @note You could also check the DMA transfer process through the MMC Tx
* interrupt event.
- * @param hmmc: Pointer to MMC handle
- * @param pData: Pointer to the buffer that will contain the data to transmit
- * @param BlockAdd: Block Address where data will be written
- * @param NumberOfBlocks: Number of blocks to write
+ * @param hmmc Pointer to MMC handle
+ * @param pData Pointer to the buffer that will contain the data to transmit
+ * @param BlockAdd Block Address where data will be written
+ * @param NumberOfBlocks Number of blocks to write
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
@@ -1231,7 +1229,7 @@
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
@@ -1255,7 +1253,7 @@
if(errorstate != HAL_MMC_ERROR_NONE)
{
/* Clear all the static flags */
- __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
+ __HAL_MMC_CLEAR_FLAG(hmmc, SDIO_STATIC_FLAGS);
hmmc->ErrorCode |= errorstate;
hmmc->State = HAL_MMC_STATE_READY;
return HAL_ERROR;
@@ -1288,9 +1286,9 @@
* @brief Erases the specified memory area of the given MMC card.
* @note This API should be followed by a check on the card state through
* HAL_MMC_GetCardState().
- * @param hmmc: Pointer to MMC handle
- * @param BlockStartAdd: Start Block address
- * @param BlockEndAdd: End Block address
+ * @param hmmc Pointer to MMC handle
+ * @param BlockStartAdd Start Block address
+ * @param BlockEndAdd End Block address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd)
@@ -1386,7 +1384,7 @@
/**
* @brief This function handles MMC card interrupt request.
- * @param hmmc: Pointer to MMC handle
+ * @param hmmc Pointer to MMC handle
* @retval None
*/
void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc)
@@ -1608,7 +1606,7 @@
/**
* @brief return the MMC state
- * @param hmmc: Pointer to mmc handle
+ * @param hmmc Pointer to mmc handle
* @retval HAL state
*/
HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc)
@@ -1618,7 +1616,7 @@
/**
* @brief Return the MMC error code
-* @param hmmc : Pointer to a MMC_HandleTypeDef structure that contains
+* @param hmmc Pointer to a MMC_HandleTypeDef structure that contains
* the configuration information.
* @retval MMC Error Code
*/
@@ -1629,7 +1627,7 @@
/**
* @brief Tx Transfer completed callbacks
- * @param hmmc: Pointer to MMC handle
+ * @param hmmc Pointer to MMC handle
* @retval None
*/
__weak void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc)
@@ -1644,7 +1642,7 @@
/**
* @brief Rx Transfer completed callbacks
- * @param hmmc: Pointer MMC handle
+ * @param hmmc Pointer MMC handle
* @retval None
*/
__weak void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc)
@@ -1659,7 +1657,7 @@
/**
* @brief MMC error callbacks
- * @param hmmc: Pointer MMC handle
+ * @param hmmc Pointer MMC handle
* @retval None
*/
__weak void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc)
@@ -1674,7 +1672,7 @@
/**
* @brief MMC Abort callbacks
- * @param hmmc: Pointer MMC handle
+ * @param hmmc Pointer MMC handle
* @retval None
*/
__weak void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc)
@@ -1710,8 +1708,8 @@
/**
* @brief Returns information the information of the card which are stored on
* the CID register.
- * @param hmmc: Pointer to MMC handle
- * @param pCID: Pointer to a HAL_MMC_CIDTypedef structure that
+ * @param hmmc Pointer to MMC handle
+ * @param pCID Pointer to a HAL_MMC_CIDTypedef structure that
* contains all CID register parameters
* @retval HAL status
*/
@@ -1791,8 +1789,8 @@
/**
* @brief Returns information the information of the card which are stored on
* the CSD register.
- * @param hmmc: Pointer to MMC handle
- * @param pCSD: Pointer to a HAL_MMC_CardInfoTypeDef structure that
+ * @param hmmc Pointer to MMC handle
+ * @param pCSD Pointer to a HAL_MMC_CardInfoTypeDef structure that
* contains all CSD register parameters
* @retval HAL status
*/
@@ -1905,8 +1903,8 @@
/**
* @brief Gets the MMC card info.
- * @param hmmc: Pointer to MMC handle
- * @param pCardInfo: Pointer to the HAL_MMC_CardInfoTypeDef structure that
+ * @param hmmc Pointer to MMC handle
+ * @param pCardInfo Pointer to the HAL_MMC_CardInfoTypeDef structure that
* will contain the MMC card status information
* @retval HAL status
*/
@@ -1926,8 +1924,8 @@
/**
* @brief Enables wide bus operation for the requested card if supported by
* card.
- * @param hmmc: Pointer to MMC handle
- * @param WideMode: Specifies the MMC card wide bus mode
+ * @param hmmc Pointer to MMC handle
+ * @param WideMode Specifies the MMC card wide bus mode
* This parameter can be one of the following values:
* @arg SDIO_BUS_WIDE_8B: 8-bit data transfer
* @arg SDIO_BUS_WIDE_4B: 4-bit data transfer
@@ -2061,7 +2059,7 @@
/**
* @brief Gets the current mmc card data state.
- * @param hmmc: pointer to MMC handle
+ * @param hmmc pointer to MMC handle
* @retval Card state
*/
HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc)
@@ -2083,7 +2081,7 @@
/**
* @brief Abort the current transfer and disable the MMC.
- * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains
+ * @param hmmc pointer to a MMC_HandleTypeDef structure that contains
* the configuration information for MMC module.
* @retval HAL status
*/
@@ -2130,7 +2128,7 @@
/**
* @brief Abort the current transfer and disable the MMC (IT mode).
- * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains
+ * @param hmmc pointer to a MMC_HandleTypeDef structure that contains
* the configuration information for MMC module.
* @retval HAL status
*/
@@ -2207,7 +2205,7 @@
/**
* @brief DMA MMC transmit process complete callback
- * @param hdma: DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void MMC_DMATransmitCplt(DMA_HandleTypeDef *hdma)
@@ -2220,7 +2218,7 @@
/**
* @brief DMA MMC receive process complete callback
- * @param hdma: DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void MMC_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
@@ -2253,7 +2251,7 @@
/**
* @brief DMA MMC communication error callback
- * @param hdma: DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void MMC_DMAError(DMA_HandleTypeDef *hdma)
@@ -2285,7 +2283,7 @@
/**
* @brief DMA MMC Tx Abort callback
- * @param hdma: DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void MMC_DMATxAbort(DMA_HandleTypeDef *hdma)
@@ -2322,7 +2320,7 @@
/**
* @brief DMA MMC Rx Abort callback
- * @param hdma: DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void MMC_DMARxAbort(DMA_HandleTypeDef *hdma)
@@ -2360,7 +2358,7 @@
/**
* @brief Initializes the mmc card.
- * @param hmmc: Pointer to MMC handle
+ * @param hmmc Pointer to MMC handle
* @retval MMC Card error state
*/
static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc)
@@ -2441,7 +2439,7 @@
* @brief Enquires cards about their operating voltage and configures clock
* controls and stores MMC information that will be needed in future
* in the MMC handle.
- * @param hmmc: Pointer to MMC handle
+ * @param hmmc Pointer to MMC handle
* @retval error state
*/
static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc)
@@ -2495,7 +2493,7 @@
/**
* @brief Turns the SDIO output signals off.
- * @param hmmc: Pointer to MMC handle
+ * @param hmmc Pointer to MMC handle
* @retval HAL status
*/
static HAL_StatusTypeDef MMC_PowerOFF(MMC_HandleTypeDef *hmmc)
@@ -2508,8 +2506,8 @@
/**
* @brief Returns the current card's status.
- * @param hmmc: Pointer to MMC handle
- * @param pCardStatus: pointer to the buffer that will contain the MMC card
+ * @param hmmc Pointer to MMC handle
+ * @param pCardStatus pointer to the buffer that will contain the MMC card
* status (Card Status register)
* @retval error state
*/
@@ -2537,7 +2535,7 @@
/**
* @brief Wrap up reading in non-blocking mode.
- * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains
+ * @param hmmc pointer to a MMC_HandleTypeDef structure that contains
* the configuration information.
* @retval HAL status
*/
@@ -2561,7 +2559,7 @@
/**
* @brief Wrap up writing in non-blocking mode.
- * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains
+ * @param hmmc pointer to a MMC_HandleTypeDef structure that contains
* the configuration information.
* @retval HAL status
*/
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_mmc.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_mmc.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_mmc.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of MMC HAL module. ****************************************************************************** * @attention @@ -393,8 +391,8 @@ /** * @brief Enable the MMC device interrupt. - * @param __HANDLE__: MMC Handle - * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled. + * @param __HANDLE__ MMC Handle + * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled. * This parameter can be one or a combination of the following values: * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -424,8 +422,8 @@ /** * @brief Disable the MMC device interrupt. - * @param __HANDLE__: MMC Handle - * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled. + * @param __HANDLE__ MMC Handle + * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled. * This parameter can be one or a combination of the following values: * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -455,8 +453,8 @@ /** * @brief Check whether the specified MMC flag is set or not. - * @param __HANDLE__: MMC Handle - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ MMC Handle + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) @@ -486,8 +484,8 @@ /** * @brief Clear the MMC's pending flags. - * @param __HANDLE__: MMC Handle - * @param __FLAG__: specifies the flag to clear. + * @param __HANDLE__ MMC Handle + * @param __FLAG__ specifies the flag to clear. * This parameter can be one or a combination of the following values: * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) @@ -506,8 +504,8 @@ /** * @brief Check whether the specified MMC interrupt has occurred or not. - * @param __HANDLE__: MMC Handle - * @param __INTERRUPT__: specifies the SDMMC interrupt source to check. + * @param __HANDLE__ MMC Handle + * @param __INTERRUPT__ specifies the SDMMC interrupt source to check. * This parameter can be one of the following values: * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -537,8 +535,8 @@ /** * @brief Clear the MMC's interrupt pending bits. - * @param __HANDLE__: MMC Handle - * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * @param __HANDLE__ MMC Handle + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. * This parameter can be one or a combination of the following values: * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_nand.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_nand.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_nand.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief NAND HAL module driver.
* This file provides a generic firmware to drive NAND memories mounted
* as external device.
@@ -146,10 +144,10 @@
/**
* @brief Perform NAND memory Initialization sequence
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
- * @param ComSpace_Timing: pointer to Common space timing structure
- * @param AttSpace_Timing: pointer to Attribute space timing structure
+ * @param ComSpace_Timing pointer to Common space timing structure
+ * @param AttSpace_Timing pointer to Attribute space timing structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
@@ -188,7 +186,7 @@
/**
* @brief Perform NAND memory De-Initialization sequence
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval HAL status
*/
@@ -211,7 +209,7 @@
/**
* @brief NAND MSP Init
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval None
*/
@@ -226,7 +224,7 @@
/**
* @brief NAND MSP DeInit
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval None
*/
@@ -242,7 +240,7 @@
/**
* @brief This function handles NAND device interrupt request.
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval HAL status
*/
@@ -291,7 +289,7 @@
/**
* @brief NAND interrupt feature callback
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval None
*/
@@ -325,9 +323,9 @@
/**
* @brief Read the NAND memory electronic signature
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
- * @param pNAND_ID: NAND ID structure
+ * @param pNAND_ID NAND ID structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
@@ -400,7 +398,7 @@
/**
* @brief NAND memory reset
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval HAL status
*/
@@ -446,9 +444,9 @@
/**
* @brief Configure the device: Enter the physical parameters of the device
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
- * @param pDeviceConfig : pointer to NAND_DeviceConfigTypeDef structure
+ * @param pDeviceConfig pointer to NAND_DeviceConfigTypeDef structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig)
@@ -466,11 +464,11 @@
/**
* @brief Read Page(s) from NAND memory block (8-bits addressing)
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
- * @param pAddress : pointer to NAND address structure
- * @param pBuffer : pointer to destination read buffer
- * @param NumPageToRead : number of pages to read from block
+ * @param pAddress pointer to NAND address structure
+ * @param pBuffer pointer to destination read buffer
+ * @param NumPageToRead number of pages to read from block
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
@@ -598,11 +596,11 @@
/**
* @brief Read Page(s) from NAND memory block (16-bits addressing)
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
- * @param pAddress : pointer to NAND address structure
- * @param pBuffer : pointer to destination read buffer. pBuffer should be 16bits aligned
- * @param NumPageToRead : number of pages to read from block
+ * @param pAddress pointer to NAND address structure
+ * @param pBuffer pointer to destination read buffer. pBuffer should be 16bits aligned
+ * @param NumPageToRead number of pages to read from block
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead)
@@ -729,11 +727,11 @@
/**
* @brief Write Page(s) to NAND memory block (8-bits addressing)
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
- * @param pAddress : pointer to NAND address structure
- * @param pBuffer : pointer to source buffer to write
- * @param NumPageToWrite : number of pages to write to block
+ * @param pAddress pointer to NAND address structure
+ * @param pBuffer pointer to source buffer to write
+ * @param NumPageToWrite number of pages to write to block
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
@@ -857,11 +855,11 @@
/**
* @brief Write Page(s) to NAND memory block (16-bits addressing)
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
- * @param pAddress : pointer to NAND address structure
- * @param pBuffer : pointer to source buffer to write. pBuffer should be 16bits aligned
- * @param NumPageToWrite : number of pages to write to block
+ * @param pAddress pointer to NAND address structure
+ * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned
+ * @param NumPageToWrite number of pages to write to block
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite)
@@ -984,11 +982,11 @@
/**
* @brief Read Spare area(s) from NAND memory
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
- * @param pAddress : pointer to NAND address structure
- * @param pBuffer: pointer to source buffer to write
- * @param NumSpareAreaToRead: Number of spare area to read
+ * @param pAddress pointer to NAND address structure
+ * @param pBuffer pointer to source buffer to write
+ * @param NumSpareAreaToRead Number of spare area to read
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
@@ -1120,11 +1118,11 @@
/**
* @brief Read Spare area(s) from NAND memory (16-bits addressing)
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
- * @param pAddress : pointer to NAND address structure
- * @param pBuffer: pointer to source buffer to write. pBuffer should be 16bits aligned.
- * @param NumSpareAreaToRead: Number of spare area to read
+ * @param pAddress pointer to NAND address structure
+ * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned.
+ * @param NumSpareAreaToRead Number of spare area to read
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead)
@@ -1256,11 +1254,11 @@
/**
* @brief Write Spare area(s) to NAND memory
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
- * @param pAddress : pointer to NAND address structure
- * @param pBuffer : pointer to source buffer to write
- * @param NumSpareAreaTowrite : number of spare areas to write to block
+ * @param pAddress pointer to NAND address structure
+ * @param pBuffer pointer to source buffer to write
+ * @param NumSpareAreaTowrite number of spare areas to write to block
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
@@ -1388,11 +1386,11 @@
/**
* @brief Write Spare area(s) to NAND memory (16-bits addressing)
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
- * @param pAddress : pointer to NAND address structure
- * @param pBuffer : pointer to source buffer to write. pBuffer should be 16bits aligned.
- * @param NumSpareAreaTowrite : number of spare areas to write to block
+ * @param pAddress pointer to NAND address structure
+ * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned.
+ * @param NumSpareAreaTowrite number of spare areas to write to block
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
@@ -1520,9 +1518,9 @@
/**
* @brief NAND memory Block erase
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
- * @param pAddress : pointer to NAND address structure
+ * @param pAddress pointer to NAND address structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
@@ -1587,7 +1585,7 @@
/**
* @brief NAND memory read status
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval NAND status
*/
@@ -1627,9 +1625,9 @@
/**
* @brief Increment the NAND memory address
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
- * @param pAddress: pointer to NAND address structure
+ * @param pAddress pointer to NAND address structure
* @retval The new status of the increment address operation. It can be:
* - NAND_VALID_ADDRESS: When the new address is valid address
* - NAND_INVALID_ADDRESS: When the new address is invalid address
@@ -1683,7 +1681,7 @@
/**
* @brief Enables dynamically NAND ECC feature.
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval HAL status
*/
@@ -1709,7 +1707,7 @@
/**
* @brief Disables dynamically FMC_NAND ECC feature.
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval HAL status
*/
@@ -1735,10 +1733,10 @@
/**
* @brief Disables dynamically NAND ECC feature.
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
- * @param ECCval: pointer to ECC value
- * @param Timeout: maximum timeout to wait
+ * @param ECCval pointer to ECC value
+ * @param Timeout maximum timeout to wait
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
@@ -1785,7 +1783,7 @@
/**
* @brief return the NAND state
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval HAL state
*/
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_nand.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_nand.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_nand.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of NAND HAL module. ****************************************************************************** * @attention @@ -166,7 +164,7 @@ */ /** @brief Reset NAND handle state - * @param __HANDLE__: specifies the NAND handle. + * @param __HANDLE__ specifies the NAND handle. * @retval None */ #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET) @@ -299,8 +297,8 @@ /** * @brief NAND memory address computation. - * @param __ADDRESS__: NAND memory address. - * @param __HANDLE__: NAND handle. + * @param __ADDRESS__ NAND memory address. + * @param __HANDLE__ NAND handle. * @retval NAND Raw address value */ #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \ @@ -308,14 +306,14 @@ /** * @brief NAND memory Column address computation. - * @param __HANDLE__: NAND handle. + * @param __HANDLE__ NAND handle. * @retval NAND Raw address value */ #define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize) /** * @brief NAND memory address cycling. - * @param __ADDRESS__: NAND memory address. + * @param __ADDRESS__ NAND memory address. * @retval NAND address cycling value. */ #define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */ @@ -325,7 +323,7 @@ /** * @brief NAND memory Columns cycling. - * @param __ADDRESS__: NAND memory address. + * @param __ADDRESS__ NAND memory address. * @retval NAND Column address cycling value. */ #define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st Column addressing cycle */
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_nor.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_nor.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_nor.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief NOR HAL module driver.
* This file provides a generic firmware to drive NOR memories mounted
* as external device.
@@ -97,7 +95,7 @@
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
- defined(STM32F412Vx) || defined(STM32F413xx) || defined(STM32F423xx)
+ defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
@@ -173,10 +171,10 @@
/**
* @brief Perform the NOR memory Initialization sequence
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
- * @param Timing: pointer to NOR control timing structure
- * @param ExtTiming: pointer to NOR extended mode timing structure
+ * @param Timing pointer to NOR control timing structure
+ * @param ExtTiming pointer to NOR extended mode timing structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
@@ -225,7 +223,7 @@
/**
* @brief Perform NOR memory De-Initialization sequence
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @retval HAL status
*/
@@ -248,7 +246,7 @@
/**
* @brief NOR MSP Init
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @retval None
*/
@@ -263,7 +261,7 @@
/**
* @brief NOR MSP DeInit
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @retval None
*/
@@ -278,9 +276,9 @@
/**
* @brief NOR MSP Wait for Ready/Busy signal
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
- * @param Timeout: Maximum timeout value
+ * @param Timeout Maximum timeout value
* @retval None
*/
__weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
@@ -314,9 +312,9 @@
/**
* @brief Read NOR flash IDs
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
- * @param pNOR_ID : pointer to NOR ID structure
+ * @param pNOR_ID pointer to NOR ID structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
@@ -375,7 +373,7 @@
/**
* @brief Returns the NOR memory to Read mode.
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @retval HAL status
*/
@@ -423,10 +421,10 @@
/**
* @brief Read data from NOR memory
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
- * @param pAddress: pointer to Device address
- * @param pData : pointer to read data
+ * @param pAddress pointer to Device address
+ * @param pData pointer to read data
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
@@ -482,10 +480,10 @@
/**
* @brief Program data to NOR memory
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
- * @param pAddress: Device address
- * @param pData : pointer to the data to write
+ * @param pAddress Device address
+ * @param pData pointer to the data to write
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
@@ -541,11 +539,11 @@
/**
* @brief Reads a half-word buffer from the NOR memory.
- * @param hnor: pointer to the NOR handle
- * @param uwAddress: NOR memory internal address to read from.
- * @param pData: pointer to the buffer that receives the data read from the
+ * @param hnor pointer to the NOR handle
+ * @param uwAddress NOR memory internal address to read from.
+ * @param pData pointer to the buffer that receives the data read from the
* NOR memory.
- * @param uwBufferSize : number of Half word to read.
+ * @param uwBufferSize number of Half word to read.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
@@ -607,10 +605,10 @@
/**
* @brief Writes a half-word buffer to the NOR memory. This function must be used
only with S29GL128P NOR memory.
- * @param hnor: pointer to the NOR handle
- * @param uwAddress: NOR memory internal start write address
- * @param pData: pointer to source data buffer.
- * @param uwBufferSize: Size of the buffer to write
+ * @param hnor pointer to the NOR handle
+ * @param uwAddress NOR memory internal start write address
+ * @param pData pointer to source data buffer.
+ * @param uwBufferSize Size of the buffer to write
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
@@ -687,10 +685,10 @@
/**
* @brief Erase the specified block of the NOR memory
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
- * @param BlockAddress : Block to erase address
- * @param Address: Device address
+ * @param BlockAddress Block to erase address
+ * @param Address Device address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
@@ -747,9 +745,9 @@
/**
* @brief Erase the entire NOR chip.
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
- * @param Address : Device address
+ * @param Address Device address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
@@ -808,9 +806,9 @@
/**
* @brief Read NOR flash CFI IDs
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
- * @param pNOR_CFI : pointer to NOR CFI IDs structure
+ * @param pNOR_CFI pointer to NOR CFI IDs structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
@@ -886,7 +884,7 @@
/**
* @brief Enables dynamically NOR write operation.
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @retval HAL status
*/
@@ -909,7 +907,7 @@
/**
* @brief Disables dynamically NOR write operation.
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @retval HAL status
*/
@@ -954,7 +952,7 @@
/**
* @brief return the NOR controller state
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @retval NOR controller state
*/
@@ -965,10 +963,10 @@
/**
* @brief Returns the NOR operation status.
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
- * @param Address: Device address
- * @param Timeout: NOR programming Timeout
+ * @param Address Device address
+ * @param Timeout NOR programming Timeout
* @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
* or HAL_NOR_STATUS_TIMEOUT
*/
@@ -1038,7 +1036,8 @@
*/
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx ||\
STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx ||\
- STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F413xx || STM32F423xx */
+ STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx ||\
+ STM32F423xx */
#endif /* HAL_NOR_MODULE_ENABLED */
/**
* @}
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_nor.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_nor.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_nor.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief Header file of NOR HAL module.
******************************************************************************
* @attention
@@ -45,9 +43,9 @@
/* Includes ------------------------------------------------------------------*/
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F412Zx) ||\
- defined(STM32F412Vx) || defined(STM32F413xx) || defined(STM32F423xx)
+ defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
#include "stm32f4xx_ll_fsmc.h"
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F413xx || STM32F423xx */
+#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
@@ -65,7 +63,7 @@
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) ||\
defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
- defined(STM32F412Vx) || defined(STM32F413xx) || defined(STM32F423xx)
+ defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F413xx) || defined(STM32F423xx)
/* Exported typedef ----------------------------------------------------------*/
/** @defgroup NOR_Exported_Types NOR Exported Types
@@ -156,7 +154,7 @@
* @{
*/
/** @brief Reset NOR handle state
- * @param __HANDLE__: specifies the NOR handle.
+ * @param __HANDLE__ specifies the NOR handle.
* @retval None
*/
#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
@@ -265,9 +263,9 @@
*/
/**
* @brief NOR memory address shifting.
- * @param __NOR_ADDRESS__: NOR base address
- * @param NOR_MEMORY_WIDTH: NOR memory width
- * @param ADDRESS: NOR memory address
+ * @param __NOR_ADDRESS__ NOR base address
+ * @param NOR_MEMORY_WIDTH NOR memory width
+ * @param ADDRESS NOR memory address
* @retval NOR shifted address value
*/
#define NOR_ADDR_SHIFT(__NOR_ADDRESS__, NOR_MEMORY_WIDTH, ADDRESS) (uint32_t)(((NOR_MEMORY_WIDTH) == NOR_MEMORY_16B)? ((uint32_t)((__NOR_ADDRESS__) + (2U * (ADDRESS)))):\
@@ -275,8 +273,8 @@
/**
* @brief NOR memory write data to specified address.
- * @param ADDRESS: NOR memory address
- * @param DATA: Data to write
+ * @param ADDRESS NOR memory address
+ * @param DATA Data to write
* @retval None
*/
#define NOR_WRITE(ADDRESS, DATA) (*(__IO uint16_t *)((uint32_t)(ADDRESS)) = (DATA))
@@ -287,7 +285,7 @@
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx ||\
STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||\
STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx ||\
- STM32F412Vx || STM32F413xx || STM32F423xx */
+ STM32F412Vx || STM32F412Rx || STM32F413xx || STM32F423xx */
/**
* @}
*/
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pccard.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pccard.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_pccard.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief PCCARD HAL module driver.
* This file provides a generic firmware to drive PCCARD memories mounted
* as external device.
@@ -133,11 +131,11 @@
/**
* @brief Perform the PCCARD memory Initialization sequence
- * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
- * @param ComSpaceTiming: Common space timing structure
- * @param AttSpaceTiming: Attribute space timing structure
- * @param IOSpaceTiming: IO space timing structure
+ * @param ComSpaceTiming Common space timing structure
+ * @param AttSpaceTiming Attribute space timing structure
+ * @param IOSpaceTiming IO space timing structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCCARD_Init(PCCARD_HandleTypeDef *hpccard, FMC_NAND_PCC_TimingTypeDef *ComSpaceTiming, FMC_NAND_PCC_TimingTypeDef *AttSpaceTiming, FMC_NAND_PCC_TimingTypeDef *IOSpaceTiming)
@@ -183,7 +181,7 @@
/**
* @brief Perform the PCCARD memory De-initialization sequence
- * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
* @retval HAL status
*/
@@ -206,7 +204,7 @@
/**
* @brief PCCARD MSP Init
- * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
* @retval None
*/
@@ -221,7 +219,7 @@
/**
* @brief PCCARD MSP DeInit
- * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
* @retval None
*/
@@ -254,10 +252,10 @@
/**
* @brief Read Compact Flash's ID.
- * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
- * @param CompactFlash_ID: Compact flash ID structure.
- * @param pStatus: pointer to compact flash status
+ * @param CompactFlash_ID Compact flash ID structure.
+ * @param pStatus pointer to compact flash status
* @retval HAL status
*
*/
@@ -317,11 +315,11 @@
/**
* @brief Read sector from PCCARD memory
- * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
- * @param pBuffer: pointer to destination read buffer
- * @param SectorAddress: Sector address to read
- * @param pStatus: pointer to PCCARD status
+ * @param pBuffer pointer to destination read buffer
+ * @param SectorAddress Sector address to read
+ * @param pStatus pointer to PCCARD status
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCCARD_Read_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus)
@@ -393,11 +391,11 @@
/**
* @brief Write sector to PCCARD memory
- * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
- * @param pBuffer: pointer to source write buffer
- * @param SectorAddress: Sector address to write
- * @param pStatus: pointer to PCCARD status
+ * @param pBuffer pointer to source write buffer
+ * @param SectorAddress Sector address to write
+ * @param pStatus pointer to PCCARD status
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCCARD_Write_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t *pBuffer, uint16_t SectorAddress, uint8_t *pStatus)
@@ -467,10 +465,10 @@
/**
* @brief Erase sector from PCCARD memory
- * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
- * @param SectorAddress: Sector address to erase
- * @param pStatus: pointer to PCCARD status
+ * @param SectorAddress Sector address to erase
+ * @param pStatus pointer to PCCARD status
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCCARD_Erase_Sector(PCCARD_HandleTypeDef *hpccard, uint16_t SectorAddress, uint8_t *pStatus)
@@ -526,7 +524,7 @@
/**
* @brief Reset the PCCARD memory
- * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
* @retval HAL status
*/
@@ -564,7 +562,7 @@
/**
* @brief This function handles PCCARD device interrupt request.
- * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
* @retval HAL status
*/
@@ -613,7 +611,7 @@
/**
* @brief PCCARD interrupt feature callback
- * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
* @retval None
*/
@@ -647,7 +645,7 @@
/**
* @brief return the PCCARD controller state
- * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
* @retval HAL state
*/
@@ -658,7 +656,7 @@
/**
* @brief Get the compact flash memory status
- * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
* @retval New status of the PCCARD operation. This parameter can be:
* - CompactFlash_TIMEOUT_ERROR: when the previous operation generate
@@ -694,7 +692,7 @@
/**
* @brief Reads the Compact Flash memory status using the Read status command
- * @param hpccard: pointer to a PCCARD_HandleTypeDef structure that contains
+ * @param hpccard pointer to a PCCARD_HandleTypeDef structure that contains
* the configuration information for PCCARD module.
* @retval The status of the Compact Flash memory. This parameter can be:
* - CompactFlash_BUSY: when memory is busy
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pccard.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pccard.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_pccard.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief Header file of PCCARD HAL module.
******************************************************************************
* @attention
@@ -111,7 +109,7 @@
* @{
*/
/** @brief Reset PCCARD handle state
- * @param __HANDLE__: specifies the PCCARD handle.
+ * @param __HANDLE__ specifies the PCCARD handle.
* @retval None
*/
#define __HAL_PCCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_PCCARD_STATE_RESET)
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pcd.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pcd.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_pcd.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@@ -133,7 +131,7 @@
/**
* @brief Initializes the PCD according to the specified
* parameters in the PCD_InitTypeDef and initialize the associated handle.
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
@@ -148,6 +146,7 @@
/* Check the parameters */
assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
+/* MBED */
if(hpcd->State == HAL_PCD_STATE_RESET)
{
/* Allocate lock resource and initialize it */
@@ -159,6 +158,7 @@
}
hpcd->State = HAL_PCD_STATE_BUSY;
+/* MBED */
/* Disable the Interrupts */
__HAL_PCD_DISABLE(hpcd);
@@ -196,6 +196,7 @@
hpcd->Instance->DIEPTXF[i] = 0U;
}
+
/* Init Device */
USB_DevInit(hpcd->Instance, hpcd->Init);
@@ -223,7 +224,7 @@
/**
* @brief DeInitializes the PCD peripheral.
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
@@ -249,7 +250,7 @@
/**
* @brief Initializes the PCD MSP.
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval None
*/
__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
@@ -263,7 +264,7 @@
/**
* @brief DeInitializes PCD MSP.
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval None
*/
__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
@@ -296,36 +297,44 @@
/**
* @brief Start The USB OTG Device.
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
{
+/* MBED */
//__HAL_LOCK(hpcd);
+/* MBED */
USB_DevConnect (hpcd->Instance);
__HAL_PCD_ENABLE(hpcd);
+/* MBED */
//__HAL_UNLOCK(hpcd);
+/* MBED */
return HAL_OK;
}
/**
* @brief Stop The USB OTG Device.
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
{
+/* MBED */
//__HAL_LOCK(hpcd);
+/* MBED */
__HAL_PCD_DISABLE(hpcd);
USB_StopDevice(hpcd->Instance);
USB_DevDisconnect(hpcd->Instance);
+/* MBED */
//__HAL_UNLOCK(hpcd);
+/* MBED */
return HAL_OK;
}
/**
* @brief Handles PCD interrupt request.
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval HAL status
*/
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
@@ -426,8 +435,10 @@
if(( epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC)
{
fifoemptymsk = 0x1U << epnum;
-
+
+/* MBED */
atomic_clr_u32(&USBx_DEVICE->DIEPEMPMSK,fifoemptymsk);
+/* MBED */
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC);
@@ -723,8 +734,8 @@
/**
* @brief Data OUT stage callback.
- * @param hpcd: PCD handle
- * @param epnum: endpoint number
+ * @param hpcd PCD handle
+ * @param epnum endpoint number
* @retval None
*/
__weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
@@ -739,8 +750,8 @@
/**
* @brief Data IN stage callback.
- * @param hpcd: PCD handle
- * @param epnum: endpoint number
+ * @param hpcd PCD handle
+ * @param epnum endpoint number
* @retval None
*/
__weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
@@ -754,7 +765,7 @@
}
/**
* @brief Setup stage callback.
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval None
*/
__weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
@@ -768,7 +779,7 @@
/**
* @brief USB Start Of Frame callback.
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval None
*/
__weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
@@ -782,7 +793,7 @@
/**
* @brief USB Reset callback.
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval None
*/
__weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
@@ -796,7 +807,7 @@
/**
* @brief Suspend event callback.
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval None
*/
__weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
@@ -810,7 +821,7 @@
/**
* @brief Resume event callback.
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval None
*/
__weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
@@ -824,8 +835,8 @@
/**
* @brief Incomplete ISO OUT callback.
- * @param hpcd: PCD handle
- * @param epnum: endpoint number
+ * @param hpcd PCD handle
+ * @param epnum endpoint number
* @retval None
*/
__weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
@@ -840,8 +851,8 @@
/**
* @brief Incomplete ISO IN callback.
- * @param hpcd: PCD handle
- * @param epnum: endpoint number
+ * @param hpcd PCD handle
+ * @param epnum endpoint number
* @retval None
*/
__weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
@@ -856,7 +867,7 @@
/**
* @brief Connection event callback.
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval None
*/
__weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
@@ -870,7 +881,7 @@
/**
* @brief Disconnection event callback.
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval None
*/
__weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
@@ -903,7 +914,7 @@
/**
* @brief Connect the USB device.
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
@@ -916,7 +927,7 @@
/**
* @brief Disconnect the USB device.
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
@@ -929,8 +940,8 @@
/**
* @brief Set the USB Device address.
- * @param hpcd: PCD handle
- * @param address: new device address
+ * @param hpcd PCD handle
+ * @param address new device address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
@@ -942,10 +953,10 @@
}
/**
* @brief Open and configure an endpoint.
- * @param hpcd: PCD handle
- * @param ep_addr: endpoint address
- * @param ep_mps: endpoint max packet size
- * @param ep_type: endpoint type
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
+ * @param ep_mps endpoint max packet size
+ * @param ep_type endpoint type
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
@@ -953,17 +964,17 @@
HAL_StatusTypeDef ret = HAL_OK;
USB_OTG_EPTypeDef *ep;
- if ((ep_addr & 0x80U) == 0x80U)
+ if ((ep_addr & 0x80) == 0x80)
{
- ep = &hpcd->IN_ep[ep_addr & 0x7FU];
+ ep = &hpcd->IN_ep[ep_addr & 0x7F];
}
else
{
- ep = &hpcd->OUT_ep[ep_addr & 0x7FU];
+ ep = &hpcd->OUT_ep[ep_addr & 0x7F];
}
- ep->num = ep_addr & 0x7FU;
+ ep->num = ep_addr & 0x7F;
- ep->is_in = (0x80U & ep_addr) != 0U;
+ ep->is_in = (0x80 & ep_addr) != 0;
ep->maxpacket = ep_mps;
ep->type = ep_type;
if (ep->is_in)
@@ -977,71 +988,77 @@
ep->data_pid_start = 0U;
}
+/* MBED */
__HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7FU]);
USB_ActivateEndpoint(hpcd->Instance , ep);
__HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7FU]);
+/* MBED */
return ret;
}
/**
* @brief Deactivate an endpoint.
- * @param hpcd: PCD handle
- * @param ep_addr: endpoint address
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
USB_OTG_EPTypeDef *ep;
- if ((ep_addr & 0x80U) == 0x80U)
+ if ((ep_addr & 0x80) == 0x80)
{
- ep = &hpcd->IN_ep[ep_addr & 0x7FU];
+ ep = &hpcd->IN_ep[ep_addr & 0x7F];
}
else
{
- ep = &hpcd->OUT_ep[ep_addr & 0x7FU];
+ ep = &hpcd->OUT_ep[ep_addr & 0x7F];
}
- ep->num = ep_addr & 0x7FU;
+ ep->num = ep_addr & 0x7F;
- ep->is_in = (0x80U & ep_addr) != 0U;
+ ep->is_in = (0x80 & ep_addr) != 0;
+/* MBED */
__HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7FU]);
USB_DeactivateEndpoint(hpcd->Instance , ep);
__HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7FU]);
+/* MBED */
return HAL_OK;
}
/**
* @brief Receive an amount of data.
- * @param hpcd: PCD handle
- * @param ep_addr: endpoint address
- * @param pBuf: pointer to the reception buffer
- * @param len: amount of data to be received
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
+ * @param pBuf pointer to the reception buffer
+ * @param len amount of data to be received
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
{
USB_OTG_EPTypeDef *ep;
- ep = &hpcd->OUT_ep[ep_addr & 0x7FU];
+ ep = &hpcd->OUT_ep[ep_addr & 0x7F];
/*setup and start the Xfer */
ep->xfer_buff = pBuf;
ep->xfer_len = len;
ep->xfer_count = 0U;
ep->is_in = 0U;
- ep->num = ep_addr & 0x7FU;
+ ep->num = ep_addr & 0x7F;
if (hpcd->Init.dma_enable == 1U)
{
ep->dma_addr = (uint32_t)pBuf;
}
+/* MBED */
__HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7FU]);
+/* MBED */
- if ((ep_addr & 0x7FU) == 0U)
+ if ((ep_addr & 0x7F) == 0)
{
USB_EP0StartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
}
@@ -1049,50 +1066,56 @@
{
USB_EPStartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
}
+/* MBED */
__HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7FU]);
+/* MBED */
return HAL_OK;
}
/**
* @brief Get Received Data Size.
- * @param hpcd: PCD handle
- * @param ep_addr: endpoint address
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
* @retval Data Size
*/
uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
+/* MBED */
return hpcd->OUT_ep[ep_addr & 0x7FU].xfer_count;
+/* MBED */
}
/**
* @brief Send an amount of data.
- * @param hpcd: PCD handle
- * @param ep_addr: endpoint address
- * @param pBuf: pointer to the transmission buffer
- * @param len: amount of data to be sent
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
+ * @param pBuf pointer to the transmission buffer
+ * @param len amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
{
USB_OTG_EPTypeDef *ep;
- ep = &hpcd->IN_ep[ep_addr & 0x7FU];
+ ep = &hpcd->IN_ep[ep_addr & 0x7F];
/*setup and start the Xfer */
ep->xfer_buff = pBuf;
ep->xfer_len = len;
ep->xfer_count = 0U;
ep->is_in = 1U;
- ep->num = ep_addr & 0x7FU;
+ ep->num = ep_addr & 0x7F;
if (hpcd->Init.dma_enable == 1U)
{
ep->dma_addr = (uint32_t)pBuf;
}
-
+
+/* MBED */
__HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7FU]);
-
- if ((ep_addr & 0x7FU) == 0U)
+/* MBED */
+
+ if ((ep_addr & 0x7F) == 0)
{
USB_EP0StartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
}
@@ -1100,25 +1123,27 @@
{
USB_EPStartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
}
-
+
+/* MBED */
__HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7FU]);
-
+/* MBED */
+
return HAL_OK;
}
/**
* @brief Set a STALL condition over an endpoint.
- * @param hpcd: PCD handle
- * @param ep_addr: endpoint address
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
USB_OTG_EPTypeDef *ep;
- if ((0x80U & ep_addr) == 0x80U)
+ if ((0x80 & ep_addr) == 0x80)
{
- ep = &hpcd->IN_ep[ep_addr & 0x7FU];
+ ep = &hpcd->IN_ep[ep_addr & 0x7F];
}
else
{
@@ -1126,34 +1151,38 @@
}
ep->is_stall = 1U;
- ep->num = ep_addr & 0x7FU;
- ep->is_in = ((ep_addr & 0x80U) == 0x80U);
+ ep->num = ep_addr & 0x7F;
+ ep->is_in = ((ep_addr & 0x80) == 0x80);
+/* MBED */
__HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7FU]);
+/* MBED */
USB_EPSetStall(hpcd->Instance , ep);
- if((ep_addr & 0x7FU) == 0U)
+ if((ep_addr & 0x7F) == 0)
{
USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
}
+/* MBED */
__HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7FU]);
+/* MBED */
return HAL_OK;
}
/**
* @brief Clear a STALL condition over in an endpoint.
- * @param hpcd: PCD handle
- * @param ep_addr: endpoint address
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
USB_OTG_EPTypeDef *ep;
- if ((0x80U & ep_addr) == 0x80U)
+ if ((0x80 & ep_addr) == 0x80)
{
- ep = &hpcd->IN_ep[ep_addr & 0x7FU];
+ ep = &hpcd->IN_ep[ep_addr & 0x7F];
}
else
{
@@ -1161,42 +1190,49 @@
}
ep->is_stall = 0U;
- ep->num = ep_addr & 0x7FU;
- ep->is_in = ((ep_addr & 0x80U) == 0x80U);
-
+ ep->num = ep_addr & 0x7F;
+ ep->is_in = ((ep_addr & 0x80) == 0x80);
+
+/* MBED */
__HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7FU]);
USB_EPClearStall(hpcd->Instance , ep);
__HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7FU]);
-
+/* MBED */
+
return HAL_OK;
}
/**
* @brief Flush an endpoint.
- * @param hpcd: PCD handle
- * @param ep_addr: endpoint address
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
+/* MBED */
__HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7FU]);
- if ((ep_addr & 0x80U) == 0x80U)
+/* MBED */
+
+ if ((ep_addr & 0x80) == 0x80)
{
- USB_FlushTxFifo(hpcd->Instance, ep_addr & 0x7FU);
+ USB_FlushTxFifo(hpcd->Instance, ep_addr & 0x7F);
}
else
{
USB_FlushRxFifo(hpcd->Instance);
}
-
+
+/* MBED */
__HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7FU]);
-
+/* MBED */
+
return HAL_OK;
}
/**
* @brief Activate remote wakeup signalling.
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
@@ -1213,7 +1249,7 @@
/**
* @brief De-activate remote wakeup signalling.
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
@@ -1245,7 +1281,7 @@
/**
* @brief Return the PCD handle state.
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval HAL state
*/
PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
@@ -1267,8 +1303,8 @@
/**
* @brief Check FIFO for the next packet to be loaded.
- * @param hpcd: PCD handle
- * @param epnum : endpoint number
+ * @param hpcd PCD handle
+ * @param epnum endpoint number
* @retval HAL status
*/
static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum)
@@ -1312,7 +1348,9 @@
if(len <= 0U)
{
fifoemptymsk = 0x1U << epnum;
+/* MBED */
atomic_clr_u32(&USBx_DEVICE->DIEPEMPMSK, fifoemptymsk);
+/* MBED */
}
return HAL_OK;
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pcd.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pcd.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_pcd.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief Header file of PCD HAL module.
******************************************************************************
* @attention
@@ -94,10 +92,12 @@
* @brief PCD Handle Structure definition
*/
+/* MBED */
typedef struct
{
HAL_LockTypeDef Lock;
} PCD_EPLockDef;
+/* MBED */
typedef struct
{
@@ -106,7 +106,9 @@
PCD_EPTypeDef IN_ep[16U]; /*!< IN endpoint parameters */
PCD_EPTypeDef OUT_ep[16U]; /*!< OUT endpoint parameters */
HAL_LockTypeDef Lock; /*!< PCD peripheral status */
+/* MBED */
PCD_EPLockDef EPLock[15]; /*!< PCD endpoint peripheral status */
+/* MBED */
__IO PCD_StateTypeDef State; /*!< PCD communication state */
uint32_t Setup[12U]; /*!< Setup packet buffer */
#ifdef USB_OTG_GLPMCFG_LPMEN
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pcd_ex.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pcd_ex.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_pcd_ex.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief PCD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
@@ -83,9 +81,9 @@
/**
* @brief Set Tx FIFO
- * @param hpcd: PCD handle
- * @param fifo: The number of Tx fifo
- * @param size: Fifo size
+ * @param hpcd PCD handle
+ * @param fifo The number of Tx fifo
+ * @param size Fifo size
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size)
@@ -126,8 +124,8 @@
/**
* @brief Set Rx FIFO
- * @param hpcd: PCD handle
- * @param size: Size of Rx fifo
+ * @param hpcd PCD handle
+ * @param size Size of Rx fifo
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size)
@@ -141,7 +139,7 @@
defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
/**
* @brief Activate LPM feature
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd)
@@ -158,7 +156,7 @@
/**
* @brief Deactivate LPM feature.
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd)
@@ -174,8 +172,8 @@
/**
* @brief Send LPM message to user layer callback.
- * @param hpcd: PCD handle
- * @param msg: LPM message
+ * @param hpcd PCD handle
+ * @param msg LPM message
* @retval HAL status
*/
__weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
@@ -189,7 +187,7 @@
#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
/**
* @brief HAL_PCDEx_BCD_VBUSDetect : handle BatteryCharging Process
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval HAL status
*/
void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd)
@@ -260,7 +258,7 @@
/**
* @brief HAL_PCDEx_ActivateBCD : active BatteryCharging feature
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd)
@@ -275,7 +273,7 @@
/**
* @brief HAL_PCDEx_DeActivateBCD : de-active BatteryCharging feature
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd)
@@ -288,8 +286,8 @@
/**
* @brief HAL_PCDEx_BatteryCharging_Callback : Send BatteryCharging message to user layer
- * @param hpcd: PCD handle
- * @param msg: LPM message
+ * @param hpcd PCD handle
+ * @param msg LPM message
* @retval HAL status
*/
__weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg)
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pcd_ex.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pcd_ex.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_pcd_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of PCD HAL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pwr.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pwr.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_pwr.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Power Controller (PWR) peripheral:
@@ -168,7 +166,7 @@
forced in input pull-down configuration and is active on rising edges.
(+) There is one Wake-up pin: Wake-up Pin 1 on PA.00.
(++) For STM32F446xx there are two Wake-Up pins: Pin1 on PA.00 and Pin2 on PC.13
- (++) For STM32F410xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx there are three Wake-Up pins: Pin1 on PA.00, Pin2 on PC.00 and Pin3 on PC.01
+ (++) For STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx there are three Wake-Up pins: Pin1 on PA.00, Pin2 on PC.00 and Pin3 on PC.01
*** Low Power modes configuration ***
=====================================
@@ -260,7 +258,7 @@
/**
* @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
- * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration
+ * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration
* information for the PVD.
* @note Refer to the electrical characteristics of your device datasheet for
* more details about the voltage threshold corresponding to each
@@ -326,11 +324,11 @@
/**
* @brief Enables the Wake-up PINx functionality.
- * @param WakeUpPinx: Specifies the Power Wake-Up pin to enable.
+ * @param WakeUpPinx Specifies the Power Wake-Up pin to enable.
* This parameter can be one of the following values:
* @arg PWR_WAKEUP_PIN1
- * @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx devices
- * @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412xx devices
+ * @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412xx/STM32F413xx/STM32F423xx devices
+ * @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx devices
* @retval None
*/
void HAL_PWR_EnableWakeUpPin(uint32_t WakeUpPinx)
@@ -344,11 +342,11 @@
/**
* @brief Disables the Wake-up PINx functionality.
- * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
+ * @param WakeUpPinx Specifies the Power Wake-Up pin to disable.
* This parameter can be one of the following values:
* @arg PWR_WAKEUP_PIN1
- * @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx devices
- * @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412Zx/STM32F412Rx/STM32F412Vx/STM32F412Cx devices
+ * @arg PWR_WAKEUP_PIN2 available only on STM32F410xx/STM32F446xx/STM32F412xx/STM32F413xx/STM32F423xx devices
+ * @arg PWR_WAKEUP_PIN3 available only on STM32F410xx/STM32F412xx/STM32F413xx/STM32F423xx devices
* @retval None
*/
void HAL_PWR_DisableWakeUpPin(uint32_t WakeUpPinx)
@@ -368,13 +366,13 @@
* @note In Sleep mode, the systick is stopped to avoid exit from this mode with
* systick interrupt when used as time base for Timeout
*
- * @param Regulator: Specifies the regulator state in SLEEP mode.
+ * @param Regulator Specifies the regulator state in SLEEP mode.
* This parameter can be one of the following values:
* @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
* @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
* @note This parameter is not used for the STM32F4 family and is kept as parameter
* just to maintain compatibility with the lower power families.
- * @param SLEEPEntry: Specifies if SLEEP mode in entered with WFI or WFE instruction.
+ * @param SLEEPEntry Specifies if SLEEP mode in entered with WFI or WFE instruction.
* This parameter can be one of the following values:
* @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
* @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
@@ -413,11 +411,11 @@
* startup delay is incurred when waking up from Stop mode.
* By keeping the internal regulator ON during Stop mode, the consumption
* is higher although the startup time is reduced.
- * @param Regulator: Specifies the regulator state in Stop mode.
+ * @param Regulator Specifies the regulator state in Stop mode.
* This parameter can be one of the following values:
* @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
* @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
- * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.
+ * @param STOPEntry Specifies if Stop mode in entered with WFI or WFE instruction.
* This parameter can be one of the following values:
* @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
* @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pwr.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pwr.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_pwr.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of PWR HAL module. ****************************************************************************** * @attention @@ -169,7 +167,7 @@ */ /** @brief Check PWR flag is set or not. - * @param __FLAG__: specifies the flag to check. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event * was received from the WKUP pin or from the RTC alarm (Alarm A @@ -192,7 +190,7 @@ #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR & (__FLAG__)) == (__FLAG__)) /** @brief Clear the PWR's pending flags. - * @param __FLAG__: specifies the flag to clear. + * @param __FLAG__ specifies the flag to clear. * This parameter can be one of the following values: * @arg PWR_FLAG_WU: Wake Up flag * @arg PWR_FLAG_SB: StandBy flag @@ -375,16 +373,16 @@ */ /* --- CR Register ---*/ /* Alias word address of DBP bit */ -#define DBP_BIT_NUMBER POSITION_VAL(PWR_CR_DBP) +#define DBP_BIT_NUMBER PWR_CR_DBP_Pos #define CR_DBP_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (DBP_BIT_NUMBER * 4U)) /* Alias word address of PVDE bit */ -#define PVDE_BIT_NUMBER POSITION_VAL(PWR_CR_PVDE) +#define PVDE_BIT_NUMBER PWR_CR_PVDE_Pos #define CR_PVDE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PVDE_BIT_NUMBER * 4U)) -/* Alias word address of PMODE bit */ -#define PMODE_BIT_NUMBER POSITION_VAL(PWR_CR_PMODE) -#define CR_PMODE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (PMODE_BIT_NUMBER * 4U)) +/* Alias word address of VOS bit */ +#define VOS_BIT_NUMBER PWR_CR_VOS_Pos +#define CR_VOS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (VOS_BIT_NUMBER * 4U)) /** * @} */ @@ -394,7 +392,7 @@ */ /* --- CSR Register ---*/ /* Alias word address of EWUP bit */ -#define EWUP_BIT_NUMBER POSITION_VAL(PWR_CSR_EWUP) +#define EWUP_BIT_NUMBER PWR_CSR_EWUP_Pos #define CSR_EWUP_BB (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (EWUP_BIT_NUMBER * 4U)) /** * @}
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pwr_ex.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pwr_ex.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_pwr_ex.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief Extended PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of PWR extension peripheral:
@@ -236,7 +234,7 @@
#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
/**
* @brief Configures the main internal regulator output voltage.
- * @param VoltageScaling: specifies the regulator output voltage to achieve
+ * @param VoltageScaling specifies the regulator output voltage to achieve
* a tradeoff between performance and power consumption.
* This parameter can be one of the following values:
* @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode,
@@ -281,7 +279,7 @@
defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
/**
* @brief Configures the main internal regulator output voltage.
- * @param VoltageScaling: specifies the regulator output voltage to achieve
+ * @param VoltageScaling specifies the regulator output voltage to achieve
* a tradeoff between performance and power consumption.
* This parameter can be one of the following values:
* @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode,
@@ -561,13 +559,13 @@
* By keeping the internal regulator ON during Stop mode, the consumption
* is higher although the startup time is reduced.
*
- * @param Regulator: specifies the regulator state in STOP mode.
+ * @param Regulator specifies the regulator state in STOP mode.
* This parameter can be one of the following values:
* @arg PWR_MAINREGULATOR_UNDERDRIVE_ON: Main Regulator in under-drive mode
* and Flash memory in power-down when the device is in Stop under-drive mode
* @arg PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON: Low Power Regulator in under-drive mode
* and Flash memory in power-down when the device is in Stop under-drive mode
- * @param STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
+ * @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction.
* This parameter can be one of the following values:
* @arg PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction
* @arg PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pwr_ex.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_pwr_ex.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_pwr_ex.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief Header file of PWR HAL Extension module.
******************************************************************************
* @attention
@@ -126,7 +124,7 @@
#if defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F415xx) || defined(STM32F417xx)
/** @brief macros configure the main internal regulator output voltage.
- * @param __REGULATOR__: specifies the regulator output voltage to achieve
+ * @param __REGULATOR__ specifies the regulator output voltage to achieve
* a tradeoff between performance and power consumption when the device does
* not operate at the maximum frequency (refer to the datasheets for more details).
* This parameter can be one of the following values:
@@ -143,7 +141,7 @@
} while(0U)
#else
/** @brief macros configure the main internal regulator output voltage.
- * @param __REGULATOR__: specifies the regulator output voltage to achieve
+ * @param __REGULATOR__ specifies the regulator output voltage to achieve
* a tradeoff between performance and power consumption when the device does
* not operate at the maximum frequency (refer to the datasheets for more details).
* This parameter can be one of the following values:
@@ -190,7 +188,7 @@
/** @brief Check PWR flag is set or not.
* @note These macros can be used only for STM32F42xx/STM3243xx devices.
- * @param __FLAG__: specifies the flag to check.
+ * @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode
* is ready
@@ -269,23 +267,23 @@
/* ------------- PWR registers bit address in the alias region ---------------*/
/* --- CR Register ---*/
/* Alias word address of FPDS bit */
-#define FPDS_BIT_NUMBER POSITION_VAL(PWR_CR_FPDS)
+#define FPDS_BIT_NUMBER PWR_CR_FPDS_Pos
#define CR_FPDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (FPDS_BIT_NUMBER * 4U))
/* Alias word address of ODEN bit */
-#define ODEN_BIT_NUMBER POSITION_VAL(PWR_CR_ODEN)
+#define ODEN_BIT_NUMBER PWR_CR_ODEN_Pos
#define CR_ODEN_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (ODEN_BIT_NUMBER * 4U))
/* Alias word address of ODSWEN bit */
-#define ODSWEN_BIT_NUMBER POSITION_VAL(PWR_CR_ODSWEN)
+#define ODSWEN_BIT_NUMBER PWR_CR_ODSWEN_Pos
#define CR_ODSWEN_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (ODSWEN_BIT_NUMBER * 4U))
/* Alias word address of MRLVDS bit */
-#define MRLVDS_BIT_NUMBER POSITION_VAL(PWR_CR_MRLVDS)
+#define MRLVDS_BIT_NUMBER PWR_CR_MRLVDS_Pos
#define CR_MRLVDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (MRLVDS_BIT_NUMBER * 4U))
/* Alias word address of LPLVDS bit */
-#define LPLVDS_BIT_NUMBER POSITION_VAL(PWR_CR_LPLVDS)
+#define LPLVDS_BIT_NUMBER PWR_CR_LPLVDS_Pos
#define CR_LPLVDS_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CR_OFFSET_BB * 32U) + (LPLVDS_BIT_NUMBER * 4U))
/**
@@ -297,12 +295,12 @@
*/
/* --- CSR Register ---*/
/* Alias word address of BRE bit */
-#define BRE_BIT_NUMBER POSITION_VAL(PWR_CSR_BRE)
+#define BRE_BIT_NUMBER PWR_CSR_BRE_Pos
#define CSR_BRE_BB (uint32_t)(PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (BRE_BIT_NUMBER * 4U))
#if defined(STM32F469xx) || defined(STM32F479xx)
/* Alias word address of WUPP bit */
-#define WUPP_BIT_NUMBER POSITION_VAL(PWR_CSR_WUPP)
+#define WUPP_BIT_NUMBER PWR_CSR_WUPP_Pos
#define CSR_WUPP_BB (PERIPH_BB_BASE + (PWR_CSR_OFFSET_BB * 32U) + (WUPP_BIT_NUMBER * 4U))
#endif /* STM32F469xx || STM32F479xx */
/**
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_qspi.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_qspi.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_qspi.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief QSPI HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the QuadSPI interface (QSPI).
@@ -248,7 +246,7 @@
/**
* @brief Initializes the QSPI mode according to the specified parameters
* in the QSPI_InitTypeDef and creates the associated handle.
- * @param hqspi: qspi handle
+ * @param hqspi qspi handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
@@ -327,7 +325,7 @@
/**
* @brief DeInitializes the QSPI peripheral
- * @param hqspi: qspi handle
+ * @param hqspi qspi handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
@@ -361,7 +359,7 @@
/**
* @brief QSPI MSP Init
- * @param hqspi: QSPI handle
+ * @param hqspi QSPI handle
* @retval None
*/
__weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
@@ -376,7 +374,7 @@
/**
* @brief QSPI MSP DeInit
- * @param hqspi: QSPI handle
+ * @param hqspi QSPI handle
* @retval None
*/
__weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
@@ -415,7 +413,7 @@
/**
* @brief This function handles QSPI interrupt request.
- * @param hqspi: QSPI handle
+ * @param hqspi QSPI handle
* @retval None.
*/
void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
@@ -635,9 +633,9 @@
/**
* @brief Sets the command configuration.
- * @param hqspi: QSPI handle
- * @param cmd : structure that contains the command configuration information
- * @param Timeout : Time out duration
+ * @param hqspi QSPI handle
+ * @param cmd structure that contains the command configuration information
+ * @param Timeout Time out duration
* @note This function is used only in Indirect Read or Write Modes
* @retval HAL status
*/
@@ -726,8 +724,8 @@
/**
* @brief Sets the command configuration in interrupt mode.
- * @param hqspi: QSPI handle
- * @param cmd : structure that contains the command configuration information
+ * @param hqspi QSPI handle
+ * @param cmd structure that contains the command configuration information
* @note This function is used only in Indirect Read or Write Modes
* @retval HAL status
*/
@@ -835,9 +833,9 @@
/**
* @brief Transmit an amount of data in blocking mode.
- * @param hqspi: QSPI handle
- * @param pData: pointer to data buffer
- * @param Timeout : Time out duration
+ * @param hqspi QSPI handle
+ * @param pData pointer to data buffer
+ * @param Timeout Time out duration
* @note This function is used only in Indirect Write Mode
* @retval HAL status
*/
@@ -919,9 +917,9 @@
/**
* @brief Receive an amount of data in blocking mode
- * @param hqspi: QSPI handle
- * @param pData: pointer to data buffer
- * @param Timeout : Time out duration
+ * @param hqspi QSPI handle
+ * @param pData pointer to data buffer
+ * @param Timeout Time out duration
* @note This function is used only in Indirect Read Mode
* @retval HAL status
*/
@@ -1005,8 +1003,8 @@
/**
* @brief Send an amount of data in interrupt mode
- * @param hqspi: QSPI handle
- * @param pData: pointer to data buffer
+ * @param hqspi QSPI handle
+ * @param pData pointer to data buffer
* @note This function is used only in Indirect Write Mode
* @retval HAL status
*/
@@ -1065,8 +1063,8 @@
/**
* @brief Receive an amount of data in no-blocking mode with Interrupt
- * @param hqspi: QSPI handle
- * @param pData: pointer to data buffer
+ * @param hqspi QSPI handle
+ * @param pData pointer to data buffer
* @note This function is used only in Indirect Read Mode
* @retval HAL status
*/
@@ -1129,8 +1127,8 @@
/**
* @brief Sends an amount of data in non blocking mode with DMA.
- * @param hqspi: QSPI handle
- * @param pData: pointer to data buffer
+ * @param hqspi QSPI handle
+ * @param pData pointer to data buffer
* @note This function is used only in Indirect Write Mode
* @note If DMA peripheral access is configured as halfword, the number
* of data and the fifo threshold should be aligned on halfword
@@ -1285,8 +1283,8 @@
/**
* @brief Receives an amount of data in non blocking mode with DMA.
- * @param hqspi: QSPI handle
- * @param pData: pointer to data buffer.
+ * @param hqspi QSPI handle
+ * @param pData pointer to data buffer.
* @note This function is used only in Indirect Read Mode
* @note If DMA peripheral access is configured as halfword, the number
* of data and the fifo threshold should be aligned on halfword
@@ -1470,10 +1468,10 @@
/**
* @brief Configure the QSPI Automatic Polling Mode in blocking mode.
- * @param hqspi: QSPI handle
- * @param cmd: structure that contains the command configuration information.
- * @param cfg: structure that contains the polling configuration information.
- * @param Timeout : Time out duration
+ * @param hqspi QSPI handle
+ * @param cmd structure that contains the command configuration information.
+ * @param cfg structure that contains the polling configuration information.
+ * @param Timeout Time out duration
* @note This function is used only in Automatic Polling Mode
* @retval HAL status
*/
@@ -1571,9 +1569,9 @@
/**
* @brief Configure the QSPI Automatic Polling Mode in non-blocking mode.
- * @param hqspi: QSPI handle
- * @param cmd: structure that contains the command configuration information.
- * @param cfg: structure that contains the polling configuration information.
+ * @param hqspi QSPI handle
+ * @param cmd structure that contains the command configuration information.
+ * @param cfg structure that contains the polling configuration information.
* @note This function is used only in Automatic Polling Mode
* @retval HAL status
*/
@@ -1685,9 +1683,9 @@
/**
* @brief Configure the Memory Mapped mode.
- * @param hqspi: QSPI handle
- * @param cmd: structure that contains the command configuration information.
- * @param cfg: structure that contains the memory mapped configuration information.
+ * @param hqspi QSPI handle
+ * @param cmd structure that contains the command configuration information.
+ * @param cfg structure that contains the memory mapped configuration information.
* @note This function is used only in Memory mapped Mode
* @retval HAL status
*/
@@ -1774,7 +1772,7 @@
/**
* @brief Transfer Error callbacks
- * @param hqspi: QSPI handle
+ * @param hqspi QSPI handle
* @retval None
*/
__weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
@@ -1789,7 +1787,7 @@
/**
* @brief Abort completed callback.
- * @param hqspi: QSPI handle
+ * @param hqspi QSPI handle
* @retval None
*/
__weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi)
@@ -1804,7 +1802,7 @@
/**
* @brief Command completed callback.
- * @param hqspi: QSPI handle
+ * @param hqspi QSPI handle
* @retval None
*/
__weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
@@ -1819,7 +1817,7 @@
/**
* @brief Rx Transfer completed callbacks.
- * @param hqspi: QSPI handle
+ * @param hqspi QSPI handle
* @retval None
*/
__weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
@@ -1834,7 +1832,7 @@
/**
* @brief Tx Transfer completed callbacks.
- * @param hqspi: QSPI handle
+ * @param hqspi QSPI handle
* @retval None
*/
__weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
@@ -1849,7 +1847,7 @@
/**
* @brief Rx Half Transfer completed callbacks.
- * @param hqspi: QSPI handle
+ * @param hqspi QSPI handle
* @retval None
*/
__weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
@@ -1864,7 +1862,7 @@
/**
* @brief Tx Half Transfer completed callbacks.
- * @param hqspi: QSPI handle
+ * @param hqspi QSPI handle
* @retval None
*/
__weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
@@ -1879,7 +1877,7 @@
/**
* @brief FIFO Threshold callbacks
- * @param hqspi: QSPI handle
+ * @param hqspi QSPI handle
* @retval None
*/
__weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
@@ -1894,7 +1892,7 @@
/**
* @brief Status Match callbacks
- * @param hqspi: QSPI handle
+ * @param hqspi QSPI handle
* @retval None
*/
__weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
@@ -1909,7 +1907,7 @@
/**
* @brief Timeout callbacks
- * @param hqspi: QSPI handle
+ * @param hqspi QSPI handle
* @retval None
*/
__weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
@@ -1945,7 +1943,7 @@
/**
* @brief Return the QSPI handle state.
- * @param hqspi: QSPI handle
+ * @param hqspi QSPI handle
* @retval HAL state
*/
HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
@@ -1956,7 +1954,7 @@
/**
* @brief Return the QSPI error code
-* @param hqspi: QSPI handle
+* @param hqspi QSPI handle
* @retval QSPI Error Code
*/
uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
@@ -1966,7 +1964,7 @@
/**
* @brief Abort the current transmission
-* @param hqspi: QSPI handle
+* @param hqspi QSPI handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
@@ -2019,7 +2017,7 @@
/**
* @brief Abort the current transmission (non-blocking function)
-* @param hqspi: QSPI handle
+* @param hqspi QSPI handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)
@@ -2064,8 +2062,8 @@
}
/** @brief Set QSPI timeout
- * @param hqspi: QSPI handle.
- * @param Timeout: Timeout for the QSPI memory access.
+ * @param hqspi QSPI handle.
+ * @param Timeout Timeout for the QSPI memory access.
* @retval None
*/
void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
@@ -2074,8 +2072,8 @@
}
/** @brief Set QSPI Fifo threshold.
- * @param hqspi: QSPI handle.
- * @param Threshold: Threshold of the Fifo (value between 1 and 16).
+ * @param hqspi QSPI handle.
+ * @param Threshold Threshold of the Fifo (value between 1 and 16).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold)
@@ -2092,7 +2090,7 @@
/* Configure QSPI FIFO Threshold */
MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
- ((hqspi->Init.FifoThreshold - 1U) << POSITION_VAL(QUADSPI_CR_FTHRES)));
+ ((hqspi->Init.FifoThreshold - 1U) << QUADSPI_CR_FTHRES_Pos));
}
else
{
@@ -2107,12 +2105,12 @@
}
/** @brief Get QSPI Fifo threshold.
- * @param hqspi: QSPI handle.
+ * @param hqspi QSPI handle.
* @retval Fifo threshold (value between 1 and 16)
*/
uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi)
{
- return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> POSITION_VAL(QUADSPI_CR_FTHRES)) + 1U);
+ return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> QUADSPI_CR_FTHRES_Pos) + 1U);
}
/**
@@ -2123,7 +2121,7 @@
/**
* @brief DMA QSPI receive process complete callback.
- * @param hdma: DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma)
@@ -2137,7 +2135,7 @@
/**
* @brief DMA QSPI transmit process complete callback.
- * @param hdma: DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma)
@@ -2151,7 +2149,7 @@
/**
* @brief DMA QSPI receive process half complete callback
- * @param hdma : DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
@@ -2163,7 +2161,7 @@
/**
* @brief DMA QSPI transmit process half complete callback
- * @param hdma : DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
@@ -2175,7 +2173,7 @@
/**
* @brief DMA QSPI communication error callback.
- * @param hdma: DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void QSPI_DMAError(DMA_HandleTypeDef *hdma)
@@ -2199,7 +2197,7 @@
/**
* @brief DMA QSPI abort complete callback.
- * @param hdma: DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma)
@@ -2233,11 +2231,11 @@
}
/**
* @brief Wait for a flag state until timeout.
- * @param hqspi: QSPI handle
- * @param Flag: Flag checked
- * @param State: Value of the flag expected
- * @param Timeout: Duration of the time out
- * @param tickstart: tick start value
+ * @param hqspi QSPI handle
+ * @param Flag Flag checked
+ * @param State Value of the flag expected
+ * @param Timeout Duration of the time out
+ * @param tickstart tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
@@ -2263,9 +2261,9 @@
/**
* @brief Configure the communication registers.
- * @param hqspi: QSPI handle
- * @param cmd: structure that contains the command configuration information
- * @param FunctionalMode: functional mode to configured
+ * @param hqspi QSPI handle
+ * @param cmd structure that contains the command configuration information
+ * @param FunctionalMode functional mode to configured
* This parameter can be one of the following values:
* @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode
* @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_qspi.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_qspi.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_qspi.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of QSPI HAL module. ****************************************************************************** * @attention @@ -433,26 +431,26 @@ */ /** @brief Reset QSPI handle state - * @param __HANDLE__: QSPI handle. + * @param __HANDLE__ QSPI handle. * @retval None */ #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET) /** @brief Enable QSPI - * @param __HANDLE__: specifies the QSPI Handle. + * @param __HANDLE__ specifies the QSPI Handle. * @retval None */ #define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) /** @brief Disable QSPI - * @param __HANDLE__: specifies the QSPI Handle. + * @param __HANDLE__ specifies the QSPI Handle. * @retval None */ #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) /** @brief Enables the specified QSPI interrupt. - * @param __HANDLE__: specifies the QSPI Handle. - * @param __INTERRUPT__: specifies the QSPI interrupt source to enable. + * @param __HANDLE__ specifies the QSPI Handle. + * @param __INTERRUPT__ specifies the QSPI interrupt source to enable. * This parameter can be one of the following values: * @arg QSPI_IT_TO: QSPI Time out interrupt * @arg QSPI_IT_SM: QSPI Status match interrupt @@ -465,8 +463,8 @@ /** @brief Disables the specified QSPI interrupt. - * @param __HANDLE__: specifies the QSPI Handle. - * @param __INTERRUPT__: specifies the QSPI interrupt source to disable. + * @param __HANDLE__ specifies the QSPI Handle. + * @param __INTERRUPT__ specifies the QSPI interrupt source to disable. * This parameter can be one of the following values: * @arg QSPI_IT_TO: QSPI Timeout interrupt * @arg QSPI_IT_SM: QSPI Status match interrupt @@ -478,8 +476,8 @@ #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) /** @brief Checks whether the specified QSPI interrupt source is enabled. - * @param __HANDLE__: specifies the QSPI Handle. - * @param __INTERRUPT__: specifies the QSPI interrupt source to check. + * @param __HANDLE__ specifies the QSPI Handle. + * @param __INTERRUPT__ specifies the QSPI interrupt source to check. * This parameter can be one of the following values: * @arg QSPI_IT_TO: QSPI Time out interrupt * @arg QSPI_IT_SM: QSPI Status match interrupt @@ -492,8 +490,8 @@ /** * @brief Get the selected QSPI's flag status. - * @param __HANDLE__: specifies the QSPI Handle. - * @param __FLAG__: specifies the QSPI flag to check. + * @param __HANDLE__ specifies the QSPI Handle. + * @param __FLAG__ specifies the QSPI flag to check. * This parameter can be one of the following values: * @arg QSPI_FLAG_BUSY: QSPI Busy flag * @arg QSPI_FLAG_TO: QSPI Time out flag @@ -506,8 +504,8 @@ #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0U) /** @brief Clears the specified QSPI's flag status. - * @param __HANDLE__: specifies the QSPI Handle. - * @param __FLAG__: specifies the QSPI clear register flag that needs to be set + * @param __HANDLE__ specifies the QSPI Handle. + * @param __FLAG__ specifies the QSPI clear register flag that needs to be set * This parameter can be one of the following values: * @arg QSPI_FLAG_TO: QSPI Time out flag * @arg QSPI_FLAG_SM: QSPI Status match flag
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,21 +2,19 @@
******************************************************************************
* @file stm32f4xx_hal_rcc.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief RCC HAL module driver.
- * This file provides firmware functions to manage the following
+ * This file provides firmware functions to manage the following
* functionalities of the Reset and Clock Control (RCC) peripheral:
* + Initialization and de-initialization functions
* + Peripheral Control functions
- *
- @verbatim
+ *
+ @verbatim
==============================================================================
##### RCC specific features #####
==============================================================================
- [..]
- After reset the device is running from Internal High Speed oscillator
- (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
+ [..]
+ After reset the device is running from Internal High Speed oscillator
+ (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
and I-Cache are disabled, and all peripherals are off except internal
SRAM, Flash and JTAG.
(+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
@@ -24,12 +22,12 @@
(+) The clock for all peripherals is switched off, except the SRAM and FLASH.
(+) All GPIOs are in input floating state, except the JTAG pins which
are assigned to be used for debug purpose.
-
- [..]
- Once the device started from reset, the user application has to:
+
+ [..]
+ Once the device started from reset, the user application has to:
(+) Configure the clock source to be used to drive the System clock
(if the application needs higher frequency/performance)
- (+) Configure the System clock frequency and Flash settings
+ (+) Configure the System clock frequency and Flash settings
(+) Configure the AHB and APB busses prescalers
(+) Enable the clock for the peripheral(s) to be used
(+) Configure the clock source(s) for peripherals which clocks are not
@@ -37,17 +35,17 @@
##### RCC Limitations #####
==============================================================================
- [..]
- A delay between an RCC peripheral clock enable and the effective peripheral
- enabling should be taken into account in order to manage the peripheral read/write
+ [..]
+ A delay between an RCC peripheral clock enable and the effective peripheral
+ enabling should be taken into account in order to manage the peripheral read/write
from/to registers.
(+) This delay depends on the peripheral mapping.
- (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
+ (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
after the clock enable bit is set on the hardware register
- (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
+ (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
after the clock enable bit is set on the hardware register
- [..]
+ [..]
Implemented Workaround:
(+) For AHB & APB peripherals, a dummy read to the peripheral register has been
inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
@@ -81,7 +79,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
- */
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal.h"
@@ -102,12 +100,11 @@
/** @addtogroup RCC_Private_Constants
* @{
*/
-#define CLOCKSWITCH_TIMEOUT_VALUE 5000U /* 5 s */
/* Private macro -------------------------------------------------------------*/
#define __MCO1_CLK_ENABLE() __HAL_RCC_GPIOA_CLK_ENABLE()
#define MCO1_GPIO_PORT GPIOA
-#define MCO1_PIN GPIO_PIN_8
+#define MCO1_PIN GPIO_PIN_8
#define __MCO2_CLK_ENABLE() __HAL_RCC_GPIOC_CLK_ENABLE()
#define MCO2_GPIO_PORT GPIOC
@@ -119,7 +116,7 @@
/* Private variables ---------------------------------------------------------*/
/** @defgroup RCC_Private_Variables RCC Private Variables
* @{
- */
+ */
/**
* @}
*/
@@ -130,16 +127,16 @@
* @{
*/
-/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
+/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
*
-@verbatim
+@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..]
This section provides functions allowing to configure the internal/external oscillators
- (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1
+ (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System busses clocks (SYSCLK, AHB, APB1
and APB2).
[..] Internal/external clock and PLL configuration
@@ -152,7 +149,7 @@
(#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
through the PLL as System clock source. Can be used also as RTC clock source.
- (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
+ (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
(#) PLL (clocked by HSI or HSE), featuring two different output clocks:
(++) The first output is used to generate the high speed system clock (up to 168 MHz)
@@ -160,10 +157,10 @@
the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
(#) CSS (Clock security system), once enable using the macro __HAL_RCC_CSS_ENABLE()
- and if a HSE clock failure occurs(HSE used directly or through PLL as System
+ and if a HSE clock failure occurs(HSE used directly or through PLL as System
clock source), the System clocks automatically switched to HSI and an interrupt
- is generated if enabled. The interrupt is linked to the Cortex-M4 NMI
- (Non-Maskable Interrupt) exception vector.
+ is generated if enabled. The interrupt is linked to the Cortex-M4 NMI
+ (Non-Maskable Interrupt) exception vector.
(#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
clock (through a configurable prescaler) on PA8 pin.
@@ -171,36 +168,36 @@
(#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
clock (through a configurable prescaler) on PC9 pin.
- [..] System, AHB and APB busses clocks configuration
+ [..] System, AHB and APB busses clocks configuration
(#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
HSE and PLL.
- The AHB clock (HCLK) is derived from System clock through configurable
- prescaler and used to clock the CPU, memory and peripherals mapped
- on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
- from AHB clock through configurable prescalers and used to clock
- the peripherals mapped on these busses. You can use
- "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
+ The AHB clock (HCLK) is derived from System clock through configurable
+ prescaler and used to clock the CPU, memory and peripherals mapped
+ on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
+ from AHB clock through configurable prescalers and used to clock
+ the peripherals mapped on these busses. You can use
+ "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
(#) For the STM32F405xx/07xx and STM32F415xx/17xx devices, the maximum
- frequency of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz.
+ frequency of the SYSCLK and HCLK is 168 MHz, PCLK2 84 MHz and PCLK1 42 MHz.
Depending on the device voltage range, the maximum frequency should
be adapted accordingly (refer to the product datasheets for more details).
(#) For the STM32F42xxx, STM32F43xxx, STM32F446xx, STM32F469xx and STM32F479xx devices,
- the maximum frequency of the SYSCLK and HCLK is 180 MHz, PCLK2 90 MHz and PCLK1 45 MHz.
+ the maximum frequency of the SYSCLK and HCLK is 180 MHz, PCLK2 90 MHz and PCLK1 45 MHz.
Depending on the device voltage range, the maximum frequency should
be adapted accordingly (refer to the product datasheets for more details).
-
+
(#) For the STM32F401xx, the maximum frequency of the SYSCLK and HCLK is 84 MHz,
- PCLK2 84 MHz and PCLK1 42 MHz.
+ PCLK2 84 MHz and PCLK1 42 MHz.
Depending on the device voltage range, the maximum frequency should
be adapted accordingly (refer to the product datasheets for more details).
-
+
(#) For the STM32F41xxx, the maximum frequency of the SYSCLK and HCLK is 100 MHz,
- PCLK2 100 MHz and PCLK1 50 MHz.
+ PCLK2 100 MHz and PCLK1 50 MHz.
Depending on the device voltage range, the maximum frequency should
be adapted accordingly (refer to the product datasheets for more details).
-
+
@endverbatim
* @{
*/
@@ -214,17 +211,19 @@
* - CSS, MCO1 and MCO2 OFF
* - All interrupts disabled
* @note This function doesn't modify the configuration of the
- * - Peripheral clocks
- * - LSI, LSE and RTC clocks
- * @retval None
+ * - Peripheral clocks
+ * - LSI, LSE and RTC clocks
+ * @retval HAL status
*/
-__weak void HAL_RCC_DeInit(void)
-{}
+__weak HAL_StatusTypeDef HAL_RCC_DeInit(void)
+{
+ return HAL_OK;
+}
/**
* @brief Initializes the RCC Oscillators according to the specified parameters in the
* RCC_OscInitTypeDef.
- * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
+ * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
* contains the configuration information for the RCC Oscillators.
* @note The PLL is not disabled when used as system clock.
* @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
@@ -237,11 +236,17 @@
*/
__weak HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
- uint32_t tickstart = 0U;
-
+ uint32_t tickstart;
+
+ /* Check Null pointer */
+ if(RCC_OscInitStruct == NULL)
+ {
+ return HAL_ERROR;
+ }
+
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
- /*------------------------------- HSE Configuration ------------------------*/
+ /*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
{
/* Check the parameters */
@@ -259,25 +264,25 @@
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
-
+
/* Check the HSE State */
if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
{
- /* Get Start Tick*/
+ /* Get Start Tick */
tickstart = HAL_GetTick();
-
- /* Wait till HSE is ready */
+
+ /* Wait till HSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
+ }
}
}
else
{
- /* Get Start Tick*/
+ /* Get Start Tick */
tickstart = HAL_GetTick();
/* Wait till HSE is bypassed or disabled */
@@ -286,7 +291,7 @@
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
+ }
}
}
}
@@ -297,7 +302,7 @@
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
-
+
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_PLL) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
@@ -325,16 +330,16 @@
/* Get Start Tick*/
tickstart = HAL_GetTick();
- /* Wait till HSI is ready */
+ /* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
- }
-
- /* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
+ }
+ }
+
+ /* Adjusts the Internal High Speed oscillator (HSI) calibration value. */
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
}
else
@@ -344,15 +349,15 @@
/* Get Start Tick*/
tickstart = HAL_GetTick();
-
- /* Wait till HSI is ready */
+
+ /* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
- }
+ }
+ }
}
}
}
@@ -367,58 +372,68 @@
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
-
+
/* Get Start Tick*/
tickstart = HAL_GetTick();
-
+
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
+ }
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
-
- /* Get Start Tick*/
+
+ /* Get Start Tick */
tickstart = HAL_GetTick();
-
- /* Wait till LSI is ready */
+
+ /* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
- }
+ }
+ }
}
}
- /*------------------------------ LSE Configuration -------------------------*/
+ /*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
{
+ FlagStatus pwrclkchanged = RESET;
+
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
-
- /* Enable Power Clock*/
- __HAL_RCC_PWR_CLK_ENABLE();
-
- /* Enable write access to Backup domain */
- PWR->CR |= PWR_CR_DBP;
-
- /* Wait for Backup domain Write protection enable */
- tickstart = HAL_GetTick();
-
- while((PWR->CR & PWR_CR_DBP) == RESET)
+
+ /* Update LSE configuration in Backup Domain control register */
+ /* Requires to enable write access to Backup Domain of necessary */
+ if(__HAL_RCC_PWR_IS_CLK_DISABLED())
+ {
+ __HAL_RCC_PWR_CLK_ENABLE();
+ pwrclkchanged = SET;
+ }
+
+ if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
{
- if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
+ /* Enable write access to Backup domain */
+ SET_BIT(PWR->CR, PWR_CR_DBP);
+
+ /* Wait for Backup domain Write protection disable */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
{
- return HAL_TIMEOUT;
- }
+ if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
}
/* Set the new LSE configuration -----------------------------------------*/
@@ -428,30 +443,36 @@
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
-
- /* Wait till LSE is ready */
+
+ /* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
+ }
}
}
else
{
- /* Get Start Tick*/
+ /* Get Start Tick */
tickstart = HAL_GetTick();
-
- /* Wait till LSE is ready */
+
+ /* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
+ }
}
}
+
+ /* Restore clock configuration if changed */
+ if(pwrclkchanged == SET)
+ {
+ __HAL_RCC_PWR_CLK_DISABLE();
+ }
}
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
@@ -460,7 +481,7 @@
{
/* Check if the PLL is used as system clock or not */
if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
- {
+ {
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
{
/* Check the parameters */
@@ -469,52 +490,52 @@
assert_param(IS_RCC_PLLN_VALUE(RCC_OscInitStruct->PLL.PLLN));
assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
-
+
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
-
- /* Get Start Tick*/
+
+ /* Get Start Tick */
tickstart = HAL_GetTick();
-
- /* Wait till PLL is ready */
+
+ /* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
- }
+ }
/* Configure the main PLL clock source, multiplication and division factors. */
WRITE_REG(RCC->PLLCFGR, (RCC_OscInitStruct->PLL.PLLSource | \
RCC_OscInitStruct->PLL.PLLM | \
- (RCC_OscInitStruct->PLL.PLLN << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
- (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \
- (RCC_OscInitStruct->PLL.PLLQ << POSITION_VAL(RCC_PLLCFGR_PLLQ))));
+ (RCC_OscInitStruct->PLL.PLLN << RCC_PLLCFGR_PLLN_Pos) | \
+ (((RCC_OscInitStruct->PLL.PLLP >> 1U) - 1U) << RCC_PLLCFGR_PLLP_Pos) | \
+ (RCC_OscInitStruct->PLL.PLLQ << RCC_PLLCFGR_PLLQ_Pos)));
/* Enable the main PLL. */
__HAL_RCC_PLL_ENABLE();
- /* Get Start Tick*/
+ /* Get Start Tick */
tickstart = HAL_GetTick();
-
- /* Wait till PLL is ready */
+
+ /* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
+ }
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
-
- /* Get Start Tick*/
+
+ /* Get Start Tick */
tickstart = HAL_GetTick();
-
- /* Wait till PLL is ready */
+
+ /* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
@@ -531,27 +552,27 @@
}
return HAL_OK;
}
-
+
/**
- * @brief Initializes the CPU, AHB and APB busses clocks according to the specified
+ * @brief Initializes the CPU, AHB and APB busses clocks according to the specified
* parameters in the RCC_ClkInitStruct.
- * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
+ * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
* contains the configuration information for the RCC peripheral.
- * @param FLatency: FLASH Latency, this parameter depend on device selected
- *
- * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
+ * @param FLatency FLASH Latency, this parameter depend on device selected
+ *
+ * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
* and updated by HAL_RCC_GetHCLKFreq() function called within this function
*
* @note The HSI is used (enabled by hardware) as system clock source after
* startup from Reset, wake-up from STOP and STANDBY mode, or in case
* of failure of the HSE used directly or indirectly as system clock
* (if the Clock Security System CSS is enabled).
- *
+ *
* @note A switch from one clock source to another occurs only if the target
- * clock source is ready (clock stable after startup delay or PLL locked).
+ * clock source is ready (clock stable after startup delay or PLL locked).
* If a clock source which is not yet ready is selected, the switch will
- * occur when the clock source will be ready.
- *
+ * occur when the clock source will be ready.
+ *
* @note Depending on the device voltage range, the software has to set correctly
* HPRE[3:0] bits to ensure that HCLK not exceed the maximum allowed frequency
* (for more details refer to section above "Initialization/de-initialization functions")
@@ -559,56 +580,74 @@
*/
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency)
{
- uint32_t tickstart = 0U;
-
+ uint32_t tickstart;
+
+ /* Check Null pointer */
+ if(RCC_ClkInitStruct == NULL)
+ {
+ return HAL_ERROR;
+ }
+
/* Check the parameters */
assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
assert_param(IS_FLASH_LATENCY(FLatency));
-
- /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
- must be correctly programmed according to the frequency of the CPU clock
+
+ /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
+ must be correctly programmed according to the frequency of the CPU clock
(HCLK) and the supply voltage of the device. */
-
+
/* Increasing the number of wait states because of higher CPU frequency */
- if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
- {
+ if(FLatency > __HAL_FLASH_GET_LATENCY())
+ {
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
-
+
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
- if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
+ if(__HAL_FLASH_GET_LATENCY() != FLatency)
{
return HAL_ERROR;
}
}
-
+
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
{
+ /* Set the highest APBx dividers in order to ensure that we do not go through
+ a non-spec phase whatever we decrease or increase HCLK. */
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+ {
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
+ }
+
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+ {
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
+ }
+
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
}
-
- /*------------------------- SYSCLK Configuration ---------------------------*/
+
+ /*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
- {
+ {
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
-
+
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
{
- /* Check the HSE ready flag */
+ /* Check the HSE ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
{
return HAL_ERROR;
}
}
/* PLL is selected as System Clock Source */
- else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
+ else if((RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK) ||
(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK))
{
- /* Check the PLL ready flag */
+ /* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
{
return HAL_ERROR;
@@ -617,81 +656,49 @@
/* HSI is selected as System Clock Source */
else
{
- /* Check the HSI ready flag */
+ /* Check the HSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
{
return HAL_ERROR;
}
}
-
+
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
- /* Get Start Tick*/
+
+ /* Get Start Tick */
tickstart = HAL_GetTick();
-
- if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
{
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
+ if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
{
- if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
- {
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
- {
- if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
+ return HAL_TIMEOUT;
}
}
- else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLRCLK)
- {
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLRCLK)
- {
- if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else
- {
- while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
- {
- if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- }
-
+ }
+
/* Decreasing the number of wait states because of lower CPU frequency */
- if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))
- {
+ if(FLatency < __HAL_FLASH_GET_LATENCY())
+ {
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
-
+
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
- if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
+ if(__HAL_FLASH_GET_LATENCY() != FLatency)
{
return HAL_ERROR;
}
- }
+ }
- /*-------------------------- PCLK1 Configuration ---------------------------*/
+ /*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
}
-
- /*-------------------------- PCLK2 Configuration ---------------------------*/
+
+ /*-------------------------- PCLK2 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
@@ -699,11 +706,11 @@
}
/* Update the SystemCoreClock global variable */
- SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
+ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
- /* Configure the source of time base considering new system clocks settings*/
+ /* Configure the source of time base considering new system clocks settings */
HAL_InitTick (TICK_INT_PRIORITY);
-
+
return HAL_OK;
}
@@ -711,17 +718,17 @@
* @}
*/
-/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
- * @brief RCC clocks control functions
+/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
+ * @brief RCC clocks control functions
*
-@verbatim
+@verbatim
===============================================================================
##### Peripheral Control functions #####
- ===============================================================================
+ ===============================================================================
[..]
- This subsection provides a set of functions allowing to control the RCC Clocks
+ This subsection provides a set of functions allowing to control the RCC Clocks
frequencies.
-
+
@endverbatim
* @{
*/
@@ -729,22 +736,22 @@
/**
* @brief Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
* @note PA8/PC9 should be configured in alternate function mode.
- * @param RCC_MCOx: specifies the output direction for the clock source.
+ * @param RCC_MCOx specifies the output direction for the clock source.
* This parameter can be one of the following values:
* @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8).
* @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9).
- * @param RCC_MCOSource: specifies the clock source to output.
+ * @param RCC_MCOSource specifies the clock source to output.
* This parameter can be one of the following values:
* @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
* @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
* @arg RCC_MCO1SOURCE_HSE: HSE clock selected as MCO1 source
* @arg RCC_MCO1SOURCE_PLLCLK: main PLL clock selected as MCO1 source
* @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
- * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx
- * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices
+ * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx
+ * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices
* @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
* @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
- * @param RCC_MCODiv: specifies the MCOx prescaler.
+ * @param RCC_MCODiv specifies the MCOx prescaler.
* This parameter can be one of the following values:
* @arg RCC_MCODIV_1: no division applied to MCOx clock
* @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
@@ -765,34 +772,34 @@
if(RCC_MCOx == RCC_MCO1)
{
assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
-
+
/* MCO1 Clock Enable */
__MCO1_CLK_ENABLE();
-
- /* Configure the MCO1 pin in alternate function mode */
+
+ /* Configure the MCO1 pin in alternate function mode */
GPIO_InitStruct.Pin = MCO1_PIN;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Speed = GPIO_SPEED_FREQ_VERY_HIGH;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
-
+
/* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */
MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv));
-
+
/* This RCC MCO1 enable feature is available only on STM32F410xx devices */
#if defined(RCC_CFGR_MCO1EN)
__HAL_RCC_MCO1_ENABLE();
-#endif /* RCC_CFGR_MCO1EN */
+#endif /* RCC_CFGR_MCO1EN */
}
#if defined(RCC_CFGR_MCO2)
else
{
assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));
-
+
/* MCO2 Clock Enable */
__MCO2_CLK_ENABLE();
-
+
/* Configure the MCO2 pin in alternate function mode */
GPIO_InitStruct.Pin = MCO2_PIN;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
@@ -800,7 +807,7 @@
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);
-
+
/* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */
MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3U)));
@@ -817,8 +824,8 @@
* @note If a failure is detected on the HSE oscillator clock, this oscillator
* is automatically disabled and an interrupt is generated to inform the
* software about the failure (Clock Security System Interrupt, CSSI),
- * allowing the MCU to perform rescue operations. The CSSI is linked to
- * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
+ * allowing the MCU to perform rescue operations. The CSSI is linked to
+ * the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.
* @retval None
*/
void HAL_RCC_EnableCSS(void)
@@ -837,14 +844,14 @@
/**
* @brief Returns the SYSCLK frequency
- *
- * @note The system frequency computed by this function is not the real
- * frequency in the chip. It is calculated based on the predefined
+ *
+ * @note The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
* @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
* @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
- * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
- * or HSI_VALUE(*) multiplied/divided by the PLL factors.
+ * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.
* @note (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
* 16 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
@@ -852,17 +859,17 @@
* 25 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may
* have wrong result.
- *
+ *
* @note The result of this function could be not correct when using fractional
* value for HSE crystal.
- *
- * @note This function can be used by the user application to compute the
+ *
+ * @note This function can be used by the user application to compute the
* baudrate for the communication peripherals or configure other parameters.
- *
+ *
* @note Each time SYSCLK changes, this function must be called to update the
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
- *
- *
+ *
+ *
* @retval SYSCLK frequency
*/
__weak uint32_t HAL_RCC_GetSysClockFreq(void)
@@ -891,15 +898,15 @@
if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
{
/* HSE used as PLL clock source */
- pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
+ pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
}
else
{
/* HSI used as PLL clock source */
- pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
+ pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
}
- pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> POSITION_VAL(RCC_PLLCFGR_PLLP)) + 1U) *2U);
-
+ pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) *2U);
+
sysclockfreq = pllvco/pllp;
break;
}
@@ -913,11 +920,11 @@
}
/**
- * @brief Returns the HCLK frequency
+ * @brief Returns the HCLK frequency
* @note Each time HCLK changes, this function must be called to update the
* right HCLK value. Otherwise, any configuration based on this function will be incorrect.
- *
- * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
+ *
+ * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
* and updated within this function
* @retval HCLK frequency
*/
@@ -927,19 +934,19 @@
}
/**
- * @brief Returns the PCLK1 frequency
+ * @brief Returns the PCLK1 frequency
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
-{
+{
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
- return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);
+ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> RCC_CFGR_PPRE1_Pos]);
}
/**
- * @brief Returns the PCLK2 frequency
+ * @brief Returns the PCLK2 frequency
* @note Each time PCLK2 changes, this function must be called to update the
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK2 frequency
@@ -947,13 +954,13 @@
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
- return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);
-}
+ return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> RCC_CFGR_PPRE2_Pos]);
+}
/**
- * @brief Configures the RCC_OscInitStruct according to the internal
+ * @brief Configures the RCC_OscInitStruct according to the internal
* RCC configuration registers.
- * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
+ * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
* will be configured.
* @retval None
*/
@@ -961,7 +968,7 @@
{
/* Set all possible values for the Oscillator type parameter ---------------*/
RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
-
+
/* Get the HSE configuration -----------------------------------------------*/
if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
{
@@ -975,7 +982,7 @@
{
RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
}
-
+
/* Get the HSI configuration -----------------------------------------------*/
if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
{
@@ -985,9 +992,9 @@
{
RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
}
-
- RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
-
+
+ RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
+
/* Get the LSE configuration -----------------------------------------------*/
if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
{
@@ -1001,7 +1008,7 @@
{
RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
}
-
+
/* Get the LSI configuration -----------------------------------------------*/
if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
{
@@ -1011,7 +1018,7 @@
{
RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
}
-
+
/* Get the PLL configuration -----------------------------------------------*/
if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
{
@@ -1023,38 +1030,38 @@
}
RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
- RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
- RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1U) >> POSITION_VAL(RCC_PLLCFGR_PLLP));
- RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ));
+ RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+ RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1U) >> RCC_PLLCFGR_PLLP_Pos);
+ RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos);
}
/**
- * @brief Configures the RCC_ClkInitStruct according to the internal
+ * @brief Configures the RCC_ClkInitStruct according to the internal
* RCC configuration registers.
- * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that
+ * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that
* will be configured.
- * @param pFLatency: Pointer on the Flash Latency.
+ * @param pFLatency Pointer on the Flash Latency.
* @retval None
*/
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
{
/* Set all possible values for the Clock type parameter --------------------*/
RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
-
- /* Get the SYSCLK configuration --------------------------------------------*/
+
+ /* Get the SYSCLK configuration --------------------------------------------*/
RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
-
- /* Get the HCLK configuration ----------------------------------------------*/
- RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
-
- /* Get the APB1 configuration ----------------------------------------------*/
- RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
-
- /* Get the APB2 configuration ----------------------------------------------*/
+
+ /* Get the HCLK configuration ----------------------------------------------*/
+ RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
+
+ /* Get the APB1 configuration ----------------------------------------------*/
+ RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
+
+ /* Get the APB2 configuration ----------------------------------------------*/
RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3U);
-
- /* Get the Flash Wait State (Latency) configuration ------------------------*/
- *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
+
+ /* Get the Flash Wait State (Latency) configuration ------------------------*/
+ *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
}
/**
@@ -1083,7 +1090,7 @@
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_RCC_CSSCallback could be implemented in the user file
- */
+ */
}
/**
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_rcc.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief Header file of RCC HAL module.
******************************************************************************
* @attention
@@ -54,7 +52,7 @@
* @{
*/
-/** @addtogroup RCC
+/** @addtogroup RCC
* @{
*/
@@ -62,9 +60,9 @@
/** @defgroup RCC_Exported_Types RCC Exported Types
* @{
*/
-
+
/**
- * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
+ * @brief RCC Internal/External Oscillator (HSE, HSI, LSE and LSI) configuration structure definition
*/
typedef struct
{
@@ -90,7 +88,7 @@
}RCC_OscInitTypeDef;
/**
- * @brief RCC System, AHB and APB busses clock configuration structure definition
+ * @brief RCC System, AHB and APB busses clock configuration structure definition
*/
typedef struct
{
@@ -212,8 +210,8 @@
/**
* @}
*/
-
-/** @defgroup RCC_System_Clock_Source System Clock Source
+
+/** @defgroup RCC_System_Clock_Source System Clock Source
* @note The RCC_SYSCLKSOURCE_PLLRCLK parameter is available only for
* STM32F446xx devices.
* @{
@@ -253,8 +251,8 @@
#define RCC_SYSCLK_DIV512 RCC_CFGR_HPRE_DIV512
/**
* @}
- */
-
+ */
+
/** @defgroup RCC_APB1_APB2_Clock_Source APB1/APB2 Clock Source
* @{
*/
@@ -265,13 +263,15 @@
#define RCC_HCLK_DIV16 RCC_CFGR_PPRE1_DIV16
/**
* @}
- */
+ */
/** @defgroup RCC_RTC_Clock_Source RTC Clock Source
* @{
*/
+#define RCC_RTCCLKSOURCE_NO_CLK 0x00000000U
#define RCC_RTCCLKSOURCE_LSE 0x00000100U
#define RCC_RTCCLKSOURCE_LSI 0x00000200U
+#define RCC_RTCCLKSOURCE_HSE_DIVX 0x00000300U
#define RCC_RTCCLKSOURCE_HSE_DIV2 0x00020300U
#define RCC_RTCCLKSOURCE_HSE_DIV3 0x00030300U
#define RCC_RTCCLKSOURCE_HSE_DIV4 0x00040300U
@@ -351,7 +351,7 @@
/**
* @}
*/
-
+
/** @defgroup RCC_Flag Flags
* Elements values convention: 0XXYYYYYb
* - YYYYY : Flag position in the register
@@ -381,7 +381,7 @@
#define RCC_FLAG_LPWRRST ((uint8_t)0x7F)
/**
* @}
- */
+ */
/**
* @}
@@ -395,8 +395,8 @@
/** @defgroup RCC_AHB1_Clock_Enable_Disable AHB1 Peripheral Clock Enable Disable
* @brief Enable or disable the AHB1 peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
- * using it.
+ * is disabled and the application software has to enable this clock before
+ * using it.
* @{
*/
#define __HAL_RCC_GPIOA_CLK_ENABLE() do { \
@@ -459,23 +459,23 @@
* using it.
* @{
*/
-#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) != RESET)
-#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) != RESET)
-#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) != RESET)
-#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) != RESET)
-#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) != RESET)
-#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) != RESET)
+#define __HAL_RCC_GPIOA_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) != RESET)
+#define __HAL_RCC_GPIOB_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) != RESET)
+#define __HAL_RCC_GPIOC_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) != RESET)
+#define __HAL_RCC_GPIOH_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) != RESET)
+#define __HAL_RCC_DMA1_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) != RESET)
+#define __HAL_RCC_DMA2_IS_CLK_ENABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) != RESET)
-#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) == RESET)
-#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) == RESET)
+#define __HAL_RCC_GPIOA_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOAEN)) == RESET)
+#define __HAL_RCC_GPIOB_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOBEN)) == RESET)
#define __HAL_RCC_GPIOC_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOCEN)) == RESET)
-#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) == RESET)
+#define __HAL_RCC_GPIOH_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_GPIOHEN)) == RESET)
#define __HAL_RCC_DMA1_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA1EN)) == RESET)
-#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) == RESET)
+#define __HAL_RCC_DMA2_IS_CLK_DISABLED() ((RCC->AHB1ENR &(RCC_AHB1ENR_DMA2EN)) == RESET)
/**
* @}
- */
-
+ */
+
/** @defgroup RCC_APB1_Clock_Enable_Disable APB1 Peripheral Clock Enable Disable
* @brief Enable or disable the Low Speed APB (APB1) peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
@@ -539,7 +539,7 @@
#define __HAL_RCC_USART2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_USART2EN))
#define __HAL_RCC_I2C1_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C1EN))
#define __HAL_RCC_I2C2_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_I2C2EN))
-#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
+#define __HAL_RCC_PWR_CLK_DISABLE() (RCC->APB1ENR &= ~(RCC_APB1ENR_PWREN))
/**
* @}
*/
@@ -565,15 +565,15 @@
#define __HAL_RCC_USART2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_USART2EN)) == RESET)
#define __HAL_RCC_I2C1_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C1EN)) == RESET)
#define __HAL_RCC_I2C2_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_I2C2EN)) == RESET)
-#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
+#define __HAL_RCC_PWR_IS_CLK_DISABLED() ((RCC->APB1ENR & (RCC_APB1ENR_PWREN)) == RESET)
/**
* @}
- */
-
+ */
+
/** @defgroup RCC_APB2_Clock_Enable_Disable APB2 Peripheral Clock Enable Disable
* @brief Enable or disable the High Speed APB (APB2) peripheral clock.
* @note After reset, the peripheral clock (used for registers read/write access)
- * is disabled and the application software has to enable this clock before
+ * is disabled and the application software has to enable this clock before
* using it.
* @{
*/
@@ -660,7 +660,7 @@
#define __HAL_RCC_SPI1_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) != RESET)
#define __HAL_RCC_SYSCFG_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) != RESET)
#define __HAL_RCC_TIM9_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) != RESET)
-#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
+#define __HAL_RCC_TIM11_IS_CLK_ENABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) != RESET)
#define __HAL_RCC_TIM1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM1EN)) == RESET)
#define __HAL_RCC_USART1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_USART1EN)) == RESET)
@@ -669,15 +669,15 @@
#define __HAL_RCC_SPI1_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SPI1EN)) == RESET)
#define __HAL_RCC_SYSCFG_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_SYSCFGEN)) == RESET)
#define __HAL_RCC_TIM9_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM9EN)) == RESET)
-#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
+#define __HAL_RCC_TIM11_IS_CLK_DISABLED() ((RCC->APB2ENR & (RCC_APB2ENR_TIM11EN)) == RESET)
/**
* @}
- */
-
-/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Force Release Reset
+ */
+
+/** @defgroup RCC_AHB1_Force_Release_Reset AHB1 Force Release Reset
* @brief Force or release AHB1 peripheral reset.
* @{
- */
+ */
#define __HAL_RCC_AHB1_FORCE_RESET() (RCC->AHB1RSTR = 0xFFFFFFFFU)
#define __HAL_RCC_GPIOA_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOARST))
#define __HAL_RCC_GPIOB_FORCE_RESET() (RCC->AHB1RSTR |= (RCC_AHB1RSTR_GPIOBRST))
@@ -697,11 +697,11 @@
* @}
*/
-/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
+/** @defgroup RCC_APB1_Force_Release_Reset APB1 Force Release Reset
* @brief Force or release APB1 peripheral reset.
* @{
*/
-#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_APB1_FORCE_RESET() (RCC->APB1RSTR = 0xFFFFFFFFU)
#define __HAL_RCC_TIM5_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_TIM5RST))
#define __HAL_RCC_WWDG_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_WWDGRST))
#define __HAL_RCC_SPI2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_SPI2RST))
@@ -710,7 +710,7 @@
#define __HAL_RCC_I2C2_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_I2C2RST))
#define __HAL_RCC_PWR_FORCE_RESET() (RCC->APB1RSTR |= (RCC_APB1RSTR_PWRRST))
-#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U)
+#define __HAL_RCC_APB1_RELEASE_RESET() (RCC->APB1RSTR = 0x00U)
#define __HAL_RCC_TIM5_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_TIM5RST))
#define __HAL_RCC_WWDG_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_WWDGRST))
#define __HAL_RCC_SPI2_RELEASE_RESET() (RCC->APB1RSTR &= ~(RCC_APB1RSTR_SPI2RST))
@@ -722,11 +722,11 @@
* @}
*/
-/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
+/** @defgroup RCC_APB2_Force_Release_Reset APB2 Force Release Reset
* @brief Force or release APB2 peripheral reset.
* @{
*/
-#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
+#define __HAL_RCC_APB2_FORCE_RESET() (RCC->APB2RSTR = 0xFFFFFFFFU)
#define __HAL_RCC_TIM1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_TIM1RST))
#define __HAL_RCC_USART1_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART1RST))
#define __HAL_RCC_USART6_FORCE_RESET() (RCC->APB2RSTR |= (RCC_APB2RSTR_USART6RST))
@@ -749,7 +749,7 @@
* @}
*/
-/** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
+/** @defgroup RCC_AHB1_LowPower_Enable_Disable AHB1 Peripheral Low Power Enable Disable
* @brief Enable or disable the AHB1 peripheral clock during Low Power (Sleep) mode.
* @note Peripheral clock gating in SLEEP mode can be used to further reduce
* power consumption.
@@ -831,23 +831,23 @@
*/
/** @defgroup RCC_HSI_Configuration HSI Configuration
- * @{
- */
-
+ * @{
+ */
+
/** @brief Macros to enable or disable the Internal High Speed oscillator (HSI).
* @note The HSI is stopped by hardware when entering STOP and STANDBY modes.
* It is used (enabled by hardware) as system clock source after startup
* from Reset, wake-up from STOP and STANDBY mode, or in case of failure
* of the HSE used directly or indirectly as system clock (if the Clock
- * Security System CSS is enabled).
+ * Security System CSS is enabled).
* @note HSI can not be stopped if it is used as system clock source. In this case,
- * you have to select another source of the system clock then stop the HSI.
+ * you have to select another source of the system clock then stop the HSI.
* @note After enabling the HSI, the application software should wait on HSIRDY
* flag to be set indicating that HSI clock is stable and can be used as
- * system clock source.
+ * system clock source.
* This parameter can be: ENABLE or DISABLE.
* @note When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
- * clock cycles.
+ * clock cycles.
*/
#define __HAL_RCC_HSI_ENABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = ENABLE)
#define __HAL_RCC_HSI_DISABLE() (*(__IO uint32_t *) RCC_CR_HSION_BB = DISABLE)
@@ -855,27 +855,27 @@
/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
* @note The calibration is used to compensate for the variations in voltage
* and temperature that influence the frequency of the internal HSI RC.
- * @param __HSICalibrationValue__: specifies the calibration trimming value.
+ * @param __HSICalibrationValue__ specifies the calibration trimming value.
* (default is RCC_HSICALIBRATION_DEFAULT).
* This parameter must be a number between 0 and 0x1F.
*/
#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICalibrationValue__) (MODIFY_REG(RCC->CR,\
- RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << POSITION_VAL(RCC_CR_HSITRIM)))
+ RCC_CR_HSITRIM, (uint32_t)(__HSICalibrationValue__) << RCC_CR_HSITRIM_Pos))
/**
* @}
*/
/** @defgroup RCC_LSI_Configuration LSI Configuration
- * @{
- */
+ * @{
+ */
/** @brief Macros to enable or disable the Internal Low Speed oscillator (LSI).
- * @note After enabling the LSI, the application software should wait on
+ * @note After enabling the LSI, the application software should wait on
* LSIRDY flag to be set indicating that LSI clock is stable and can
* be used to clock the IWDG and/or the RTC.
* @note LSI can not be disabled if the IWDG is running.
* @note When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
- * clock cycles.
+ * clock cycles.
*/
#define __HAL_RCC_LSI_ENABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = ENABLE)
#define __HAL_RCC_LSI_DISABLE() (*(__IO uint32_t *) RCC_CSR_LSION_BB = DISABLE)
@@ -884,12 +884,12 @@
*/
/** @defgroup RCC_HSE_Configuration HSE Configuration
- * @{
- */
+ * @{
+ */
/**
* @brief Macro to configure the External High Speed oscillator (HSE).
- * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro.
+ * @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not supported by this macro.
* User should request a transition to HSE Off first and then HSE On or HSE Bypass.
* @note After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
* software should wait on HSERDY flag to be set indicating that HSE clock
@@ -897,11 +897,11 @@
* @note HSE state can not be changed if it is used directly or through the
* PLL as system clock. In this case, you have to select another source
* of the system clock then change the HSE state (ex. disable it).
- * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
+ * @note The HSE is stopped by hardware when entering STOP and STANDBY modes.
* @note This function reset the CSSON bit, so if the clock security system(CSS)
* was previously enabled you have to enable it again after calling this
- * function.
- * @param __STATE__: specifies the new state of the HSE.
+ * function.
+ * @param __STATE__ specifies the new state of the HSE.
* This parameter can be one of the following values:
* @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
* 6 HSE oscillator clock cycles.
@@ -930,21 +930,21 @@
*/
/** @defgroup RCC_LSE_Configuration LSE Configuration
- * @{
+ * @{
*/
/**
* @brief Macro to configure the External Low Speed oscillator (LSE).
- * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
+ * @note Transition LSE Bypass to LSE On and LSE On to LSE Bypass are not supported by this macro.
* User should request a transition to LSE Off first and then LSE On or LSE Bypass.
* @note As the LSE is in the Backup domain and write access is denied to
- * this domain after reset, you have to enable write access using
+ * this domain after reset, you have to enable write access using
* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
- * (to be done once after reset).
+ * (to be done once after reset).
* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
* software should wait on LSERDY flag to be set indicating that LSE clock
* is stable and can be used to clock the RTC.
- * @param __STATE__: specifies the new state of the LSE.
+ * @param __STATE__ specifies the new state of the LSE.
* This parameter can be one of the following values:
* @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
* 6 LSE oscillator clock cycles.
@@ -973,7 +973,7 @@
*/
/** @defgroup RCC_Internal_RTC_Clock_Configuration RTC Clock Configuration
- * @{
+ * @{
*/
/** @brief Macros to enable or disable the RTC clock.
@@ -986,34 +986,52 @@
* @note As the RTC clock configuration bits are in the Backup domain and write
* access is denied to this domain after reset, you have to enable write
* access using the Power Backup Access macro before to configure
- * the RTC clock source (to be done once after reset).
- * @note Once the RTC clock is configured it can't be changed unless the
+ * the RTC clock source (to be done once after reset).
+ * @note Once the RTC clock is configured it can't be changed unless the
* Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
* a Power On Reset (POR).
- * @param __RTCCLKSource__: specifies the RTC clock source.
+ * @param __RTCCLKSource__ specifies the RTC clock source.
* This parameter can be one of the following values:
- * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
- * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
- * @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected
- * as RTC clock, where x:[2,31]
+ @arg @ref RCC_RTCCLKSOURCE_NO_CLK: No clock selected as RTC clock.
+ * @arg @ref RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
+ * @arg @ref RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
+ * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected
+ * as RTC clock, where x:[2,31]
* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
* work in STOP and STANDBY modes, and can be used as wake-up source.
* However, when the HSE clock is used as RTC clock source, the RTC
- * cannot be used in STOP and STANDBY modes.
+ * cannot be used in STOP and STANDBY modes.
* @note The maximum input clock frequency for RTC is 1MHz (when using HSE as
* RTC clock source).
*/
#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFFU)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
-
+
#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFFU); \
} while(0U)
+/** @brief Macro to get the RTC clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
+ * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
+ * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
+ * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()
+ */
+#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
+
+/**
+ * @brief Get the RTC and HSE clock divider (RTCPRE).
+ * @retval Returned value can be one of the following values:
+ * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected
+ * as RTC clock, where x:[2,31]
+ */
+#define __HAL_RCC_GET_RTC_HSE_PRESCALER() (READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) | RCC_BDCR_RTCSEL)
+
/** @brief Macros to force or release the Backup domain reset.
* @note This function resets the RTC peripheral (including the backup registers)
* and the RTC clock source selection in RCC_CSR register.
- * @note The BKPSRAM is not affected by this reset.
+ * @note The BKPSRAM is not affected by this reset.
*/
#define __HAL_RCC_BACKUPRESET_FORCE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = ENABLE)
#define __HAL_RCC_BACKUPRESET_RELEASE() (*(__IO uint32_t *) RCC_BDCR_BDRST_BB = DISABLE)
@@ -1022,11 +1040,11 @@
*/
/** @defgroup RCC_PLL_Configuration PLL Configuration
- * @{
+ * @{
*/
/** @brief Macros to enable or disable the main PLL.
- * @note After enabling the main PLL, the application software should wait on
+ * @note After enabling the main PLL, the application software should wait on
* PLLRDY flag to be set indicating that PLL clock is stable and can
* be used as system clock source.
* @note The main PLL can not be disabled if it is used as system clock source
@@ -1037,22 +1055,22 @@
/** @brief Macro to configure the PLL clock source.
* @note This function must be used only when the main PLL is disabled.
- * @param __PLLSOURCE__: specifies the PLL entry clock source.
+ * @param __PLLSOURCE__ specifies the PLL entry clock source.
* This parameter can be one of the following values:
* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
- *
+ *
*/
#define __HAL_RCC_PLL_PLLSOURCE_CONFIG(__PLLSOURCE__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, (__PLLSOURCE__))
/** @brief Macro to configure the PLL multiplication factor.
* @note This function must be used only when the main PLL is disabled.
- * @param __PLLM__: specifies the division factor for PLL VCO input clock
+ * @param __PLLM__ specifies the division factor for PLL VCO input clock
* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
* @note You have to set the PLLM parameter correctly to ensure that the VCO input
* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
* of 2 MHz to limit PLL jitter.
- *
+ *
*/
#define __HAL_RCC_PLL_PLLM_CONFIG(__PLLM__) MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLM, (__PLLM__))
/**
@@ -1060,16 +1078,16 @@
*/
/** @defgroup RCC_Get_Clock_source Get Clock source
- * @{
+ * @{
*/
/**
* @brief Macro to configure the system clock source.
- * @param __RCC_SYSCLKSOURCE__: specifies the system clock source.
+ * @param __RCC_SYSCLKSOURCE__ specifies the system clock source.
* This parameter can be one of the following values:
* - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
* - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
* - RCC_SYSCLKSOURCE_PLLCLK: PLL output is used as system clock source.
- * - RCC_SYSCLKSOURCE_PLLRCLK: PLLR output is used as system clock source. This
+ * - RCC_SYSCLKSOURCE_PLLRCLK: PLLR output is used as system clock source. This
* parameter is available only for STM32F446xx devices.
*/
#define __HAL_RCC_SYSCLK_CONFIG(__RCC_SYSCLKSOURCE__) MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, (__RCC_SYSCLKSOURCE__))
@@ -1082,8 +1100,8 @@
* - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
* - RCC_SYSCLKSOURCE_STATUS_PLLRCLK: PLLR used as system clock. This parameter
* is available only for STM32F446xx devices.
- */
-#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
+ */
+#define __HAL_RCC_GET_SYSCLK_SOURCE() (RCC->CFGR & RCC_CFGR_SWS)
/** @brief Macro to get the oscillator used as PLL clock source.
* @retval The oscillator used as PLL clock source. The returned value can be one
@@ -1097,9 +1115,9 @@
*/
/** @defgroup RCCEx_MCOx_Clock_Config RCC Extended MCOx Clock Config
- * @{
- */
-
+ * @{
+ */
+
/** @brief Macro to configure the MCO1 clock.
* @param __MCOCLKSOURCE__ specifies the MCO clock source.
* This parameter can be one of the following values:
@@ -1122,8 +1140,8 @@
* @param __MCOCLKSOURCE__ specifies the MCO clock source.
* This parameter can be one of the following values:
* @arg RCC_MCO2SOURCE_SYSCLK: System clock (SYSCLK) selected as MCO2 source
- * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx
- * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices
+ * @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source, available for all STM32F4 devices except STM32F410xx
+ * @arg RCC_MCO2SOURCE_I2SCLK: I2SCLK clock selected as MCO2 source, available only for STM32F410Rx devices
* @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
* @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
* @param __MCODIV__ specifies the MCO clock prescaler.
@@ -1141,7 +1159,7 @@
/**
* @}
*/
-
+
/** @defgroup RCC_Flags_Interrupts_Management Flags Interrupts Management
* @brief macros to manage the specified RCC Flags and interrupts.
* @{
@@ -1149,7 +1167,7 @@
/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
* the selected interrupts).
- * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
+ * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
* This parameter can be any combination of the following values:
* @arg RCC_IT_LSIRDY: LSI ready interrupt.
* @arg RCC_IT_LSERDY: LSE ready interrupt.
@@ -1160,9 +1178,9 @@
*/
#define __HAL_RCC_ENABLE_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE1_ADDRESS |= (__INTERRUPT__))
-/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
+/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
* the selected interrupts).
- * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
+ * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
* This parameter can be any combination of the following values:
* @arg RCC_IT_LSIRDY: LSI ready interrupt.
* @arg RCC_IT_LSERDY: LSE ready interrupt.
@@ -1175,20 +1193,20 @@
/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
* bits to clear the selected interrupt pending bits.
- * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
+ * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
* This parameter can be any combination of the following values:
* @arg RCC_IT_LSIRDY: LSI ready interrupt.
* @arg RCC_IT_LSERDY: LSE ready interrupt.
* @arg RCC_IT_HSIRDY: HSI ready interrupt.
* @arg RCC_IT_HSERDY: HSE ready interrupt.
* @arg RCC_IT_PLLRDY: Main PLL ready interrupt.
- * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
+ * @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt.
* @arg RCC_IT_CSS: Clock Security System interrupt
*/
#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
/** @brief Check the RCC's interrupt has occurred or not.
- * @param __INTERRUPT__: specifies the RCC interrupt source to check.
+ * @param __INTERRUPT__ specifies the RCC interrupt source to check.
* This parameter can be one of the following values:
* @arg RCC_IT_LSIRDY: LSI ready interrupt.
* @arg RCC_IT_LSERDY: LSE ready interrupt.
@@ -1201,13 +1219,13 @@
*/
#define __HAL_RCC_GET_IT(__INTERRUPT__) ((RCC->CIR & (__INTERRUPT__)) == (__INTERRUPT__))
-/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
+/** @brief Set RMVF bit to clear the reset flags: RCC_FLAG_PINRST, RCC_FLAG_PORRST,
* RCC_FLAG_SFTRST, RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST and RCC_FLAG_LPWRRST.
*/
#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
/** @brief Check RCC flag is set or not.
- * @param __FLAG__: specifies the flag to check.
+ * @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
@@ -1230,7 +1248,7 @@
/**
* @}
*/
-
+
/**
* @}
*/
@@ -1242,9 +1260,9 @@
/** @addtogroup RCC_Exported_Functions_Group1
* @{
- */
+ */
/* Initialization and de-initialization functions ******************************/
-void HAL_RCC_DeInit(void);
+HAL_StatusTypeDef HAL_RCC_DeInit(void);
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
/**
@@ -1268,7 +1286,7 @@
/* CSS NMI IRQ handler */
void HAL_RCC_NMI_IRQHandler(void);
-/* User Callbacks in non blocking mode (IT mode) */
+/* User Callbacks in non blocking mode (IT mode) */
void HAL_RCC_CSSCallback(void);
/**
@@ -1291,7 +1309,7 @@
* @{
*/
#define RCC_OFFSET (RCC_BASE - PERIPH_BASE)
-/* --- CR Register ---*/
+/* --- CR Register --- */
/* Alias word address of HSION bit */
#define RCC_CR_OFFSET (RCC_OFFSET + 0x00U)
#define RCC_HSION_BIT_NUMBER 0x00U
@@ -1303,7 +1321,7 @@
#define RCC_PLLON_BIT_NUMBER 0x18U
#define RCC_CR_PLLON_BB (PERIPH_BB_BASE + (RCC_CR_OFFSET * 32U) + (RCC_PLLON_BIT_NUMBER * 4U))
-/* --- BDCR Register ---*/
+/* --- BDCR Register --- */
/* Alias word address of RTCEN bit */
#define RCC_BDCR_OFFSET (RCC_OFFSET + 0x70U)
#define RCC_RTCEN_BIT_NUMBER 0x0FU
@@ -1312,7 +1330,7 @@
#define RCC_BDRST_BIT_NUMBER 0x10U
#define RCC_BDCR_BDRST_BB (PERIPH_BB_BASE + (RCC_BDCR_OFFSET * 32U) + (RCC_BDRST_BIT_NUMBER * 4U))
-/* --- CSR Register ---*/
+/* --- CSR Register --- */
/* Alias word address of LSION bit */
#define RCC_CSR_OFFSET (RCC_OFFSET + 0x74U)
#define RCC_LSION_BIT_NUMBER 0x00U
@@ -1336,6 +1354,7 @@
#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
#define HSI_TIMEOUT_VALUE 2U /* 2 ms */
#define LSI_TIMEOUT_VALUE 2U /* 2 ms */
+#define CLOCKSWITCH_TIMEOUT_VALUE 5000U /* 5 s */
/**
* @}
@@ -1349,10 +1368,10 @@
/** @defgroup RCC_Private_Macros RCC Private Macros
* @{
*/
-
+
/** @defgroup RCC_IS_RCC_Definitions RCC Private macros to check input parameters
* @{
- */
+ */
#define IS_RCC_OSCILLATORTYPE(OSCILLATOR) ((OSCILLATOR) <= 15U)
#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
@@ -1407,7 +1426,7 @@
((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV29) || \
((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV30) || \
((__SOURCE__) == RCC_RTCCLKSOURCE_HSE_DIV31))
-
+
#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63U)
#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2U) || ((VALUE) == 4U) || ((VALUE) == 6U) || ((VALUE) == 8U))
@@ -1433,7 +1452,7 @@
#define IS_RCC_MCODIV(DIV) (((DIV) == RCC_MCODIV_1) || ((DIV) == RCC_MCODIV_2) || \
((DIV) == RCC_MCODIV_3) || ((DIV) == RCC_MCODIV_4) || \
- ((DIV) == RCC_MCODIV_5))
+ ((DIV) == RCC_MCODIV_5))
#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1FU)
/**
@@ -1446,7 +1465,7 @@
/**
* @}
- */
+ */
/**
* @}
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc_ex.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc_ex.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,13 +2,11 @@
******************************************************************************
* @file stm32f4xx_hal_rcc_ex.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief Extension RCC HAL module driver.
- * This file provides firmware functions to manage the following
+ * This file provides firmware functions to manage the following
* functionalities RCC extension peripheral:
* + Extended Peripheral Control functions
- *
+ *
******************************************************************************
* @attention
*
@@ -37,7 +35,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
- */
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f4xx_hal.h"
@@ -60,7 +58,7 @@
*/
/**
* @}
- */
+ */
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
@@ -69,37 +67,37 @@
* @{
*/
-/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
- * @brief Extended Peripheral Control functions
+/** @defgroup RCCEx_Exported_Functions_Group1 Extended Peripheral Control functions
+ * @brief Extended Peripheral Control functions
*
-@verbatim
+@verbatim
===============================================================================
##### Extended Peripheral Control functions #####
===============================================================================
[..]
- This subsection provides a set of functions allowing to control the RCC Clocks
+ This subsection provides a set of functions allowing to control the RCC Clocks
frequencies.
- [..]
+ [..]
(@) Important note: Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to
- select the RTC clock source; in this case the Backup domain will be reset in
- order to modify the RTC Clock source, as consequence RTC registers (including
+ select the RTC clock source; in this case the Backup domain will be reset in
+ order to modify the RTC Clock source, as consequence RTC registers (including
the backup registers) and RCC_BDCR register are set to their reset values.
-
+
@endverbatim
* @{
*/
-#if defined(STM32F446xx)
+#if defined(STM32F446xx)
/**
* @brief Initializes the RCC extended peripherals clocks according to the specified
* parameters in the RCC_PeriphCLKInitTypeDef.
- * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
+ * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
* contains the configuration information for the Extended Peripherals
* clocks(I2S, SAI, LTDC RTC and TIM).
- *
- * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
- * the RTC clock source; in this case the Backup domain will be reset in
- * order to modify the RTC Clock source, as consequence RTC registers (including
+ *
+ * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
+ * the RTC clock source; in this case the Backup domain will be reset in
+ * order to modify the RTC Clock source, as consequence RTC registers (including
* the backup registers) and RCC_BDCR register are set to their reset values.
*
* @retval HAL status
@@ -115,100 +113,100 @@
uint32_t pllsaiq = 0U;
uint32_t plli2sused = 0U;
uint32_t pllsaiused = 0U;
-
+
/* Check the peripheral clock selection parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
-
+
/*------------------------ I2S APB1 configuration --------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1))
{
/* Check the parameters */
assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection));
-
+
/* Configure I2S Clock source */
__HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection);
/* Enable the PLLI2S when it's used as clock source for I2S */
if(PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)
{
- plli2sused = 1U;
+ plli2sused = 1U;
}
}
/*--------------------------------------------------------------------------*/
-
+
/*---------------------------- I2S APB2 configuration ----------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2))
{
/* Check the parameters */
assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection));
-
+
/* Configure I2S Clock source */
__HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection);
/* Enable the PLLI2S when it's used as clock source for I2S */
if(PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)
{
- plli2sused = 1U;
+ plli2sused = 1U;
}
}
/*--------------------------------------------------------------------------*/
-
+
/*--------------------------- SAI1 configuration ---------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == (RCC_PERIPHCLK_SAI1))
{
/* Check the parameters */
assert_param(IS_RCC_SAI1CLKSOURCE(PeriphClkInit->Sai1ClockSelection));
-
+
/* Configure SAI1 Clock source */
__HAL_RCC_SAI1_CONFIG(PeriphClkInit->Sai1ClockSelection);
/* Enable the PLLI2S when it's used as clock source for SAI */
if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)
{
- plli2sused = 1U;
+ plli2sused = 1U;
}
/* Enable the PLLSAI when it's used as clock source for SAI */
if(PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)
{
- pllsaiused = 1U;
+ pllsaiused = 1U;
}
}
/*--------------------------------------------------------------------------*/
-
+
/*-------------------------- SAI2 configuration ----------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == (RCC_PERIPHCLK_SAI2))
{
/* Check the parameters */
assert_param(IS_RCC_SAI2CLKSOURCE(PeriphClkInit->Sai2ClockSelection));
-
+
/* Configure SAI2 Clock source */
__HAL_RCC_SAI2_CONFIG(PeriphClkInit->Sai2ClockSelection);
-
+
/* Enable the PLLI2S when it's used as clock source for SAI */
if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)
{
- plli2sused = 1U;
+ plli2sused = 1U;
}
/* Enable the PLLSAI when it's used as clock source for SAI */
if(PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)
{
- pllsaiused = 1U;
+ pllsaiused = 1U;
}
}
/*--------------------------------------------------------------------------*/
-
+
/*----------------------------- RTC configuration --------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
{
/* Check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
-
+
/* Enable Power Clock*/
__HAL_RCC_PWR_CLK_ENABLE();
-
+
/* Enable write access to Backup domain */
PWR->CR |= PWR_CR_DBP;
-
+
/* Get tick */
tickstart = HAL_GetTick();
-
+
while((PWR->CR & PWR_CR_DBP) == RESET)
{
if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
@@ -216,7 +214,7 @@
return HAL_TIMEOUT;
}
}
- /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
+ /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
{
@@ -233,8 +231,8 @@
{
/* Get tick */
tickstart = HAL_GetTick();
-
- /* Wait till LSE is ready */
+
+ /* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
@@ -247,7 +245,7 @@
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
}
/*--------------------------------------------------------------------------*/
-
+
/*---------------------------- TIM configuration ---------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
{
@@ -255,80 +253,80 @@
__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
}
/*--------------------------------------------------------------------------*/
-
+
/*---------------------------- FMPI2C1 Configuration -----------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1)
{
/* Check the parameters */
assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection));
-
+
/* Configure the FMPI2C1 clock source */
__HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection);
}
/*--------------------------------------------------------------------------*/
-
+
/*------------------------------ CEC Configuration -------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CEC) == RCC_PERIPHCLK_CEC)
{
/* Check the parameters */
assert_param(IS_RCC_CECCLKSOURCE(PeriphClkInit->CecClockSelection));
-
+
/* Configure the CEC clock source */
__HAL_RCC_CEC_CONFIG(PeriphClkInit->CecClockSelection);
}
/*--------------------------------------------------------------------------*/
-
+
/*----------------------------- CLK48 Configuration ------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
{
/* Check the parameters */
assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));
-
+
/* Configure the CLK48 clock source */
__HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
/* Enable the PLLSAI when it's used as clock source for CLK48 */
if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP)
{
- pllsaiused = 1U;
+ pllsaiused = 1U;
}
}
/*--------------------------------------------------------------------------*/
-
+
/*----------------------------- SDIO Configuration -------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO)
{
/* Check the parameters */
assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection));
-
+
/* Configure the SDIO clock source */
__HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection);
}
/*--------------------------------------------------------------------------*/
-
+
/*------------------------------ SPDIFRX Configuration ---------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX)
{
/* Check the parameters */
assert_param(IS_RCC_SPDIFRXCLKSOURCE(PeriphClkInit->SpdifClockSelection));
-
+
/* Configure the SPDIFRX clock source */
__HAL_RCC_SPDIFRX_CONFIG(PeriphClkInit->SpdifClockSelection);
/* Enable the PLLI2S when it's used as clock source for SPDIFRX */
if(PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP)
{
- plli2sused = 1U;
+ plli2sused = 1U;
}
}
/*--------------------------------------------------------------------------*/
-
+
/*---------------------------- PLLI2S Configuration ------------------------*/
/* PLLI2S is configured when a peripheral will use it as source clock : SAI1, SAI2, I2S on APB1,
I2S on APB2 or SPDIFRX */
if((plli2sused == 1U) || (PeriphClkInit->PeriphClockSelection == RCC_PERIPHCLK_PLLI2S))
{
/* Disable the PLLI2S */
- __HAL_RCC_PLLI2S_DISABLE();
+ __HAL_RCC_PLLI2S_DISABLE();
/* Get tick */
tickstart = HAL_GetTick();
/* Wait till PLLI2S is disabled */
@@ -338,66 +336,66 @@
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
- }
+ }
}
-
+
/* check for common PLLI2S Parameters */
assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));
assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
-
- /*------ In Case of PLLI2S is selected as source clock for I2S -----------*/
+
+ /*------ In Case of PLLI2S is selected as source clock for I2S -----------*/
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) ||
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)))
{
/* check for Parameters */
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
-
+
/* Read PLLI2SP/PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
- plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1U) << 1U);
- plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
+ plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U);
+ plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , plli2sp, plli2sq, PeriphClkInit->PLLI2S.PLLI2SR);
}
-
- /*------- In Case of PLLI2S is selected as source clock for SAI ----------*/
+
+ /*------- In Case of PLLI2S is selected as source clock for SAI ----------*/
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLI2S)) ||
- ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
+ ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLI2S)))
{
/* Check for PLLI2S Parameters */
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
/* Check for PLLI2S/DIVQ parameters */
assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
-
+
/* Read PLLI2SP/PLLI2SR value from PLLI2SCFGR register (this value is not needed for SAI configuration) */
- plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1U) << 1U);
- plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
- /* Configure the PLLI2S division factors */
+ plli2sp = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U);
+ plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
+ /* Configure the PLLI2S division factors */
/* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , plli2sp, PeriphClkInit->PLLI2S.PLLI2SQ, plli2sr);
-
- /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
- __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
- }
-
- /*------ In Case of PLLI2S is selected as source clock for SPDIFRX -------*/
+
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
+ __HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
+ }
+
+ /*------ In Case of PLLI2S is selected as source clock for SPDIFRX -------*/
if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SPDIFRX) == RCC_PERIPHCLK_SPDIFRX) && (PeriphClkInit->SpdifClockSelection == RCC_SPDIFRXCLKSOURCE_PLLI2SP))
{
/* check for Parameters */
assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
/* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
- plli2sq = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1U) << 1U);
- plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
+ plli2sq = ((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U);
+ plli2sr = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
/* SPDIFRXCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, plli2sq, plli2sr);
- }
-
- /*----------------- In Case of PLLI2S is just selected -----------------*/
+ }
+
+ /*----------------- In Case of PLLI2S is just selected -----------------*/
if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
{
/* Check for Parameters */
@@ -408,8 +406,8 @@
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SP, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
- }
-
+ }
+
/* Enable the PLLI2S */
__HAL_RCC_PLLI2S_ENABLE();
/* Get tick */
@@ -423,32 +421,32 @@
return HAL_TIMEOUT;
}
}
- }
+ }
/*--------------------------------------------------------------------------*/
-
+
/*----------------------------- PLLSAI Configuration -----------------------*/
/* PLLSAI is configured when a peripheral will use it as source clock : SAI1, SAI2, CLK48 or SDIO */
if(pllsaiused == 1U)
{
/* Disable PLLSAI Clock */
- __HAL_RCC_PLLSAI_DISABLE();
+ __HAL_RCC_PLLSAI_DISABLE();
/* Get tick */
tickstart = HAL_GetTick();
/* Wait till PLLSAI is disabled */
while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
{
if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
- {
+ {
/* return in case of Timeout detected */
return HAL_TIMEOUT;
}
}
-
+
/* Check the PLLSAI division factors */
assert_param(IS_RCC_PLLSAIM_VALUE(PeriphClkInit->PLLSAI.PLLSAIM));
assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
-
- /*------ In Case of PLLSAI is selected as source clock for SAI -----------*/
+
+ /*------ In Case of PLLSAI is selected as source clock for SAI -----------*/
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI1) == RCC_PERIPHCLK_SAI1) && (PeriphClkInit->Sai1ClockSelection == RCC_SAI1CLKSOURCE_PLLSAI)) ||
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI2) == RCC_PERIPHCLK_SAI2) && (PeriphClkInit->Sai2ClockSelection == RCC_SAI2CLKSOURCE_PLLSAI)))
{
@@ -456,31 +454,31 @@
assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
/* check for PLLSAI/DIVQ Parameter */
assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
-
+
/* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
- pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) + 1U) << 1U);
+ pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U);
/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN , pllsaip, PeriphClkInit->PLLSAI.PLLSAIQ, 0U);
-
- /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
+
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
__HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
- }
-
- /*------ In Case of PLLSAI is selected as source clock for CLK48 ---------*/
- /* In Case of PLLI2S is selected as source clock for CLK48 */
+ }
+
+ /*------ In Case of PLLSAI is selected as source clock for CLK48 ---------*/
+ /* In Case of PLLI2S is selected as source clock for CLK48 */
if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP))
{
/* check for Parameters */
assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
/* Read PLLSAIQ value from PLLI2SCFGR register (this value is not need for SAI configuration) */
- pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
+ pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
/* Configure the PLLSAI division factors */
/* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * (PLLI2SN/PLLSAIM) */
/* 48CLK = f(PLLSAI clock output) = f(VCO clock) / PLLSAIP */
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIM, PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIP, pllsaiq, 0U);
- }
+ }
/* Enable PLLSAI Clock */
__HAL_RCC_PLLSAI_ENABLE();
@@ -490,11 +488,11 @@
while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
{
if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
- {
+ {
/* return in case of Timeout detected */
return HAL_TIMEOUT;
}
- }
+ }
}
return HAL_OK;
}
@@ -502,14 +500,14 @@
/**
* @brief Get the RCC_PeriphCLKInitTypeDef according to the internal
* RCC configuration registers.
- * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
+ * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
* will be configured.
* @retval None
*/
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
uint32_t tempreg;
-
+
/* Set all possible values for the extended clock type parameter------------*/
PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1 | RCC_PERIPHCLK_I2S_APB2 |\
RCC_PERIPHCLK_SAI1 | RCC_PERIPHCLK_SAI2 |\
@@ -517,53 +515,53 @@
RCC_PERIPHCLK_CEC | RCC_PERIPHCLK_FMPI2C1 |\
RCC_PERIPHCLK_CLK48 | RCC_PERIPHCLK_SDIO |\
RCC_PERIPHCLK_SPDIFRX;
-
+
/* Get the PLLI2S Clock configuration --------------------------------------*/
- PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SM));
- PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
- PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) + 1U) << 1U);
- PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
- PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
+ PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM) >> RCC_PLLI2SCFGR_PLLI2SM_Pos);
+ PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
+ PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) << 1U);
+ PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
+ PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
/* Get the PLLSAI Clock configuration --------------------------------------*/
- PeriphClkInit->PLLSAI.PLLSAIM = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIM));
- PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN));
- PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) + 1U) << 1U);
- PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
+ PeriphClkInit->PLLSAI.PLLSAIM = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM) >> RCC_PLLSAICFGR_PLLSAIM_Pos);
+ PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos);
+ PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U);
+ PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
/* Get the PLLSAI/PLLI2S division factors ----------------------------------*/
- PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLI2SDIVQ));
- PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLSAIDIVQ));
+ PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos);
+ PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos);
/* Get the SAI1 clock configuration ----------------------------------------*/
PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
-
+
/* Get the SAI2 clock configuration ----------------------------------------*/
PeriphClkInit->Sai2ClockSelection = __HAL_RCC_GET_SAI2_SOURCE();
-
+
/* Get the I2S APB1 clock configuration ------------------------------------*/
PeriphClkInit->I2sApb1ClockSelection = __HAL_RCC_GET_I2S_APB1_SOURCE();
-
+
/* Get the I2S APB2 clock configuration ------------------------------------*/
PeriphClkInit->I2sApb2ClockSelection = __HAL_RCC_GET_I2S_APB2_SOURCE();
-
+
/* Get the RTC Clock configuration -----------------------------------------*/
tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
-
+
/* Get the CEC clock configuration -----------------------------------------*/
PeriphClkInit->CecClockSelection = __HAL_RCC_GET_CEC_SOURCE();
-
+
/* Get the FMPI2C1 clock configuration -------------------------------------*/
PeriphClkInit->Fmpi2c1ClockSelection = __HAL_RCC_GET_FMPI2C1_SOURCE();
-
+
/* Get the CLK48 clock configuration ----------------------------------------*/
PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
-
+
/* Get the SDIO clock configuration ----------------------------------------*/
PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE();
-
+
/* Get the SPDIFRX clock configuration -------------------------------------*/
PeriphClkInit->SpdifClockSelection = __HAL_RCC_GET_SPDIFRX_SOURCE();
-
+
/* Get the TIM Prescaler configuration -------------------------------------*/
if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
{
@@ -576,9 +574,9 @@
}
/**
- * @brief Return the peripheral clock frequency for a given peripheral(SAI..)
+ * @brief Return the peripheral clock frequency for a given peripheral(SAI..)
* @note Return 0 if peripheral clock identifier not managed by this API
- * @param PeriphClk: Peripheral clock identifier
+ * @param PeriphClk Peripheral clock identifier
* This parameter can be one of the following values:
* @arg RCC_PERIPHCLK_SAI1: SAI1 peripheral clock
* @arg RCC_PERIPHCLK_SAI2: SAI2 peripheral clock
@@ -601,16 +599,16 @@
switch (PeriphClk)
{
case RCC_PERIPHCLK_SAI1:
- case RCC_PERIPHCLK_SAI2:
+ case RCC_PERIPHCLK_SAI2:
{
- saiclocksource = RCC->DCKCFGR;
+ saiclocksource = RCC->DCKCFGR;
saiclocksource &= (RCC_DCKCFGR_SAI1SRC | RCC_DCKCFGR_SAI2SRC);
switch (saiclocksource)
{
- case 0U: /* PLLSAI is the clock source for SAI*/
+ case 0U: /* PLLSAI is the clock source for SAI*/
{
/* Configure the PLLSAI division factor */
- /* PLLSAI_VCO Input = PLL_SOURCE/PLLSAIM */
+ /* PLLSAI_VCO Input = PLL_SOURCE/PLLSAIM */
if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
{
/* In Case the PLL Source is HSI (Internal Clock) */
@@ -620,22 +618,22 @@
{
/* In Case the PLL Source is HSE (External Clock) */
vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIM)));
- }
+ }
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
tmpreg1 = (RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> 24U;
frequency = (vcoinput * ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> 6U))/(tmpreg1);
-
+
/* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
tmpreg1 = (((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> 8U) + 1U);
- frequency = frequency/(tmpreg1);
- break;
+ frequency = frequency/(tmpreg1);
+ break;
}
case RCC_DCKCFGR_SAI1SRC_0: /* PLLI2S is the clock source for SAI*/
case RCC_DCKCFGR_SAI2SRC_0: /* PLLI2S is the clock source for SAI*/
- {
+ {
/* Configure the PLLI2S division factor */
- /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
+ /* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
{
/* In Case the PLL Source is HSI (Internal Clock) */
@@ -646,22 +644,22 @@
/* In Case the PLL Source is HSE (External Clock) */
vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM)));
}
-
+
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
tmpreg1 = (RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> 24U;
frequency = (vcoinput * ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U))/(tmpreg1);
-
+
/* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
- tmpreg1 = ((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) + 1U);
+ tmpreg1 = ((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) + 1U);
frequency = frequency/(tmpreg1);
- break;
+ break;
}
case RCC_DCKCFGR_SAI1SRC_1: /* PLLR is the clock source for SAI*/
case RCC_DCKCFGR_SAI2SRC_1: /* PLLR is the clock source for SAI*/
{
/* Configure the PLLI2S division factor */
- /* PLL_VCO Input = PLL_SOURCE/PLLM */
+ /* PLL_VCO Input = PLL_SOURCE/PLLM */
if((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLSOURCE_HSI)
{
/* In Case the PLL Source is HSI (Internal Clock) */
@@ -672,17 +670,17 @@
/* In Case the PLL Source is HSE (External Clock) */
vcoinput = ((HSE_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM)));
}
-
+
/* PLL_VCO Output = PLL_VCO Input * PLLN */
/* SAI_CLK_x = PLL_VCO Output/PLLR */
tmpreg1 = (RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> 28U;
frequency = (vcoinput * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U))/(tmpreg1);
- break;
+ break;
}
case RCC_DCKCFGR_SAI1SRC: /* External clock is the clock source for SAI*/
{
frequency = EXTERNAL_CLOCK_VALUE;
- break;
+ break;
}
case RCC_DCKCFGR_SAI2SRC: /* PLLSRC(HSE or HSI) is the clock source for SAI*/
{
@@ -696,12 +694,12 @@
/* In Case the PLL Source is HSE (External Clock) */
frequency = (uint32_t)(HSE_VALUE);
}
- break;
- }
+ break;
+ }
default :
{
break;
- }
+ }
}
break;
}
@@ -711,8 +709,8 @@
srcclk = __HAL_RCC_GET_I2S_APB1_SOURCE();
switch (srcclk)
{
- /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
- case RCC_I2SAPB1CLKSOURCE_EXT:
+ /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
+ case RCC_I2SAPB1CLKSOURCE_EXT:
{
/* Set the I2S clock to the external clock value */
frequency = EXTERNAL_CLOCK_VALUE;
@@ -733,7 +731,7 @@
/* Get the I2S source clock value */
vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
}
-
+
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
/* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
@@ -755,7 +753,7 @@
/* Get the I2S source clock value */
vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
}
-
+
/* PLL_VCO Output = PLL_VCO Input * PLLN */
vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U)));
/* I2S_CLK = PLL_VCO Output/PLLR */
@@ -782,15 +780,15 @@
break;
}
}
- break;
- }
+ break;
+ }
case RCC_PERIPHCLK_I2S_APB2:
{
/* Get the current I2S source */
srcclk = __HAL_RCC_GET_I2S_APB2_SOURCE();
switch (srcclk)
{
- /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
+ /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
case RCC_I2SAPB2CLKSOURCE_EXT:
{
/* Set the I2S clock to the external clock value */
@@ -812,7 +810,7 @@
/* Get the I2S source clock value */
vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
}
-
+
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
/* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
@@ -834,7 +832,7 @@
/* Get the I2S source clock value */
vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
}
-
+
/* PLL_VCO Output = PLL_VCO Input * PLLN */
vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U)));
/* I2S_CLK = PLL_VCO Output/PLLR */
@@ -859,12 +857,12 @@
{
frequency = 0U;
break;
- }
+ }
}
break;
}
}
- return frequency;
+ return frequency;
}
#endif /* STM32F446xx */
@@ -872,13 +870,13 @@
/**
* @brief Initializes the RCC extended peripherals clocks according to the specified
* parameters in the RCC_PeriphCLKInitTypeDef.
- * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
+ * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
* contains the configuration information for the Extended Peripherals
* clocks(I2S, SAI, LTDC, RTC and TIM).
- *
- * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
- * the RTC clock source; in this case the Backup domain will be reset in
- * order to modify the RTC Clock source, as consequence RTC registers (including
+ *
+ * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
+ * the RTC clock source; in this case the Backup domain will be reset in
+ * order to modify the RTC Clock source, as consequence RTC registers (including
* the backup registers) and RCC_BDCR register are set to their reset values.
*
* @retval HAL status
@@ -890,45 +888,45 @@
uint32_t pllsaip = 0U;
uint32_t pllsaiq = 0U;
uint32_t pllsair = 0U;
-
+
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
-
+
/*--------------------------- CLK48 Configuration --------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
{
/* Check the parameters */
assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));
-
+
/* Configure the CLK48 clock source */
__HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
- }
+ }
/*--------------------------------------------------------------------------*/
-
+
/*------------------------------ SDIO Configuration ------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO)
{
/* Check the parameters */
assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection));
-
+
/* Configure the SDIO clock source */
__HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection);
}
/*--------------------------------------------------------------------------*/
-
+
/*----------------------- SAI/I2S Configuration (PLLI2S) -------------------*/
/*------------------- Common configuration SAI/I2S -------------------------*/
- /* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division
- factor is common parameters for both peripherals */
- if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) ||
+ /* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division
+ factor is common parameters for both peripherals */
+ if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) ||
(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S) ||
(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S))
{
/* check for Parameters */
assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
-
+
/* Disable the PLLI2S */
- __HAL_RCC_PLLI2S_DISABLE();
+ __HAL_RCC_PLLI2S_DISABLE();
/* Get tick */
tickstart = HAL_GetTick();
/* Wait till PLLI2S is disabled */
@@ -940,10 +938,10 @@
return HAL_TIMEOUT;
}
}
-
+
/*---------------------- I2S configuration -------------------------------*/
- /* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added
- only for I2S configuration */
+ /* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added
+ only for I2S configuration */
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
{
/* check for Parameters */
@@ -953,38 +951,38 @@
/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
}
-
- /*---------------------------- SAI configuration -------------------------*/
- /* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must
- be added only for SAI configuration */
+
+ /*---------------------------- SAI configuration -------------------------*/
+ /* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must
+ be added only for SAI configuration */
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S))
{
/* Check the PLLI2S division factors */
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
-
+
/* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
- tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
- /* Configure the PLLI2S division factors */
+ tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
+ /* Configure the PLLI2S division factors */
/* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
__HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ , tmpreg1);
- /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
}
-
- /*----------------- In Case of PLLI2S is just selected -----------------*/
+
+ /*----------------- In Case of PLLI2S is just selected -----------------*/
if((PeriphClkInit->PeriphClockSelection & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S)
{
/* Check for Parameters */
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
-
+
/* Configure the PLLI2S multiplication and division factors */
__HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
- }
-
+ }
+
/* Enable the PLLI2S */
__HAL_RCC_PLLI2S_ENABLE();
/* Get tick */
@@ -1000,53 +998,53 @@
}
}
/*--------------------------------------------------------------------------*/
-
+
/*----------------------- SAI/LTDC Configuration (PLLSAI) ------------------*/
/*----------------------- Common configuration SAI/LTDC --------------------*/
/* In Case of SAI, LTDC or CLK48 Clock Configuration through PLLSAI, PLLSAIN division
- factor is common parameters for these peripherals */
- if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) ||
- (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) ||
+ factor is common parameters for these peripherals */
+ if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) ||
+ (((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC) ||
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) &&
(PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP)))
{
/* Check the PLLSAI division factors */
assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
-
+
/* Disable PLLSAI Clock */
- __HAL_RCC_PLLSAI_DISABLE();
+ __HAL_RCC_PLLSAI_DISABLE();
/* Get tick */
tickstart = HAL_GetTick();
/* Wait till PLLSAI is disabled */
while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
{
if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
- {
+ {
/* return in case of Timeout detected */
return HAL_TIMEOUT;
}
}
-
+
/*---------------------------- SAI configuration -------------------------*/
- /* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must
- be added only for SAI configuration */
+ /* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must
+ be added only for SAI configuration */
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI))
{
assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
-
+
/* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
- pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) + 1U) << 1U);
+ pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U);
/* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
- pllsair = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
+ pllsair = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
- __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, PeriphClkInit->PLLSAI.PLLSAIQ, pllsair);
- /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
+ __HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, PeriphClkInit->PLLSAI.PLLSAIQ, pllsair);
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
__HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
}
-
+
/*---------------------------- LTDC configuration ------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
{
@@ -1054,34 +1052,34 @@
assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
/* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
- pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) + 1U) << 1U);
+ pllsaip = ((((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U) << 1U);
/* Read PLLSAIQ value from PLLSAICFGR register (this value is not need for SAI configuration) */
- pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
+ pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
/* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, pllsaip, pllsaiq, PeriphClkInit->PLLSAI.PLLSAIR);
- /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
+ /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
__HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
- }
-
+ }
+
/*---------------------------- CLK48 configuration ------------------------*/
/* Configure the PLLSAI when it is used as clock source for CLK48 */
- if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == (RCC_PERIPHCLK_CLK48)) &&
+ if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == (RCC_PERIPHCLK_CLK48)) &&
(PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLSAIP))
{
assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
-
+
/* Read PLLSAIQ value from PLLSAICFGR register (this value is not need for SAI configuration) */
- pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
+ pllsaiq = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
/* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
- pllsair = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
+ pllsair = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
/* CLK48_CLK(first level) = PLLSAI_VCO Output/PLLSAIP */
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN, PeriphClkInit->PLLSAI.PLLSAIP, pllsaiq, pllsair);
}
-
+
/* Enable PLLSAI Clock */
__HAL_RCC_PLLSAI_ENABLE();
/* Get tick */
@@ -1090,30 +1088,30 @@
while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
{
if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
- {
+ {
/* return in case of Timeout detected */
return HAL_TIMEOUT;
}
- }
+ }
}
/*--------------------------------------------------------------------------*/
-
+
/*---------------------------- RTC configuration ---------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
{
/* Check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
-
+
/* Enable Power Clock*/
__HAL_RCC_PWR_CLK_ENABLE();
-
+
/* Enable write access to Backup domain */
PWR->CR |= PWR_CR_DBP;
-
+
/* Get tick */
tickstart = HAL_GetTick();
-
+
while((PWR->CR & PWR_CR_DBP) == RESET)
{
if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
@@ -1121,7 +1119,7 @@
return HAL_TIMEOUT;
}
}
- /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
+ /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
{
@@ -1132,14 +1130,14 @@
__HAL_RCC_BACKUPRESET_RELEASE();
/* Restore the Content of BDCR register */
RCC->BDCR = tmpreg1;
-
+
/* Wait for LSE reactivation if LSE was enable prior to Backup Domain reset */
if(HAL_IS_BIT_SET(RCC->BDCR, RCC_BDCR_LSEON))
{
/* Get tick */
tickstart = HAL_GetTick();
-
- /* Wait till LSE is ready */
+
+ /* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
@@ -1162,44 +1160,44 @@
}
/**
- * @brief Configures the RCC_PeriphCLKInitTypeDef according to the internal
+ * @brief Configures the RCC_PeriphCLKInitTypeDef according to the internal
* RCC configuration registers.
- * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
+ * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
* will be configured.
* @retval None
*/
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
uint32_t tempreg;
-
+
/* Set all possible values for the extended clock type parameter------------*/
PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_SAI_PLLSAI |\
RCC_PERIPHCLK_SAI_PLLI2S | RCC_PERIPHCLK_LTDC |\
RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC |\
RCC_PERIPHCLK_CLK48 | RCC_PERIPHCLK_SDIO;
-
+
/* Get the PLLI2S Clock configuration --------------------------------------*/
- PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
- PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
- PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
+ PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
+ PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
+ PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
/* Get the PLLSAI Clock configuration --------------------------------------*/
- PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN));
- PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
- PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
+ PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos);
+ PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
+ PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
/* Get the PLLSAI/PLLI2S division factors ----------------------------------*/
- PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLI2SDIVQ));
- PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLSAIDIVQ));
+ PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos);
+ PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos);
PeriphClkInit->PLLSAIDivR = (uint32_t)(RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVR);
/* Get the RTC Clock configuration -----------------------------------------*/
tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
-
+
/* Get the CLK48 clock configuration -------------------------------------*/
PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
-
+
/* Get the SDIO clock configuration ----------------------------------------*/
PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE();
-
+
if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
{
PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
@@ -1211,9 +1209,9 @@
}
/**
- * @brief Return the peripheral clock frequency for a given peripheral(SAI..)
+ * @brief Return the peripheral clock frequency for a given peripheral(SAI..)
* @note Return 0 if peripheral clock identifier not managed by this API
- * @param PeriphClk: Peripheral clock identifier
+ * @param PeriphClk Peripheral clock identifier
* This parameter can be one of the following values:
* @arg RCC_PERIPHCLK_I2S: I2S peripheral clock
* @retval Frequency in KHz
@@ -1235,8 +1233,8 @@
srcclk = __HAL_RCC_GET_I2S_SOURCE();
switch (srcclk)
{
- /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
- case RCC_I2SCLKSOURCE_EXT:
+ /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
+ case RCC_I2SCLKSOURCE_EXT:
{
/* Set the I2S clock to the external clock value */
frequency = EXTERNAL_CLOCK_VALUE;
@@ -1257,7 +1255,7 @@
/* Get the I2S source clock value */
vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
}
-
+
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
/* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
@@ -1269,7 +1267,7 @@
{
frequency = 0U;
break;
- }
+ }
}
break;
}
@@ -1282,13 +1280,13 @@
/**
* @brief Initializes the RCC extended peripherals clocks according to the specified
* parameters in the RCC_PeriphCLKInitTypeDef.
- * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
+ * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
* contains the configuration information for the Extended Peripherals
* clocks(I2S, LTDC RTC and TIM).
- *
- * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
- * the RTC clock source; in this case the Backup domain will be reset in
- * order to modify the RTC Clock source, as consequence RTC registers (including
+ *
+ * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
+ * the RTC clock source; in this case the Backup domain will be reset in
+ * order to modify the RTC Clock source, as consequence RTC registers (including
* the backup registers) and RCC_BDCR register are set to their reset values.
*
* @retval HAL status
@@ -1304,106 +1302,106 @@
/* Check the peripheral clock selection parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
-
+
/*----------------------------------- I2S APB1 configuration ---------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == (RCC_PERIPHCLK_I2S_APB1))
{
/* Check the parameters */
assert_param(IS_RCC_I2SAPB1CLKSOURCE(PeriphClkInit->I2sApb1ClockSelection));
-
+
/* Configure I2S Clock source */
__HAL_RCC_I2S_APB1_CONFIG(PeriphClkInit->I2sApb1ClockSelection);
/* Enable the PLLI2S when it's used as clock source for I2S */
if(PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)
{
- plli2sused = 1U;
+ plli2sused = 1U;
}
}
/*--------------------------------------------------------------------------*/
-
+
/*----------------------------------- I2S APB2 configuration ---------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == (RCC_PERIPHCLK_I2S_APB2))
{
/* Check the parameters */
assert_param(IS_RCC_I2SAPB2CLKSOURCE(PeriphClkInit->I2sApb2ClockSelection));
-
+
/* Configure I2S Clock source */
__HAL_RCC_I2S_APB2_CONFIG(PeriphClkInit->I2sApb2ClockSelection);
/* Enable the PLLI2S when it's used as clock source for I2S */
if(PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)
{
- plli2sused = 1U;
+ plli2sused = 1U;
}
}
/*--------------------------------------------------------------------------*/
-
+
#if defined(STM32F413xx) || defined(STM32F423xx)
/*----------------------- SAI1 Block A configuration -----------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIA) == (RCC_PERIPHCLK_SAIA))
{
/* Check the parameters */
assert_param(IS_RCC_SAIACLKSOURCE(PeriphClkInit->SaiAClockSelection));
-
+
/* Configure SAI1 Clock source */
__HAL_RCC_SAI_BLOCKACLKSOURCE_CONFIG(PeriphClkInit->SaiAClockSelection);
/* Enable the PLLI2S when it's used as clock source for SAI */
if(PeriphClkInit->SaiAClockSelection == RCC_SAIACLKSOURCE_PLLI2SR)
{
- plli2sused = 1U;
+ plli2sused = 1U;
}
/* Enable the PLLSAI when it's used as clock source for SAI */
if(PeriphClkInit->SaiAClockSelection == RCC_SAIACLKSOURCE_PLLR)
{
/* Check for PLL/DIVR parameters */
assert_param(IS_RCC_PLL_DIVR_VALUE(PeriphClkInit->PLLDivR));
-
- /* SAI_CLK_x = SAI_CLK(first level)/PLLDIVR */
+
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLDIVR */
__HAL_RCC_PLL_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLDivR);
}
}
/*--------------------------------------------------------------------------*/
-
+
/*---------------------- SAI1 Block B configuration ------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIB) == (RCC_PERIPHCLK_SAIB))
{
/* Check the parameters */
assert_param(IS_RCC_SAIBCLKSOURCE(PeriphClkInit->SaiBClockSelection));
-
+
/* Configure SAI1 Clock source */
__HAL_RCC_SAI_BLOCKBCLKSOURCE_CONFIG(PeriphClkInit->SaiBClockSelection);
/* Enable the PLLI2S when it's used as clock source for SAI */
if(PeriphClkInit->SaiBClockSelection == RCC_SAIBCLKSOURCE_PLLI2SR)
{
- plli2sused = 1U;
+ plli2sused = 1U;
}
/* Enable the PLLSAI when it's used as clock source for SAI */
if(PeriphClkInit->SaiBClockSelection == RCC_SAIBCLKSOURCE_PLLR)
{
/* Check for PLL/DIVR parameters */
assert_param(IS_RCC_PLL_DIVR_VALUE(PeriphClkInit->PLLDivR));
-
- /* SAI_CLK_x = SAI_CLK(first level)/PLLDIVR */
+
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLDIVR */
__HAL_RCC_PLL_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLDivR);
}
}
/*--------------------------------------------------------------------------*/
#endif /* STM32F413xx || STM32F423xx */
-
+
/*------------------------------------ RTC configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
{
/* Check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
-
+
/* Enable Power Clock*/
__HAL_RCC_PWR_CLK_ENABLE();
-
+
/* Enable write access to Backup domain */
PWR->CR |= PWR_CR_DBP;
-
+
/* Get tick */
tickstart = HAL_GetTick();
-
+
while((PWR->CR & PWR_CR_DBP) == RESET)
{
if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
@@ -1411,7 +1409,7 @@
return HAL_TIMEOUT;
}
}
- /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
+ /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
{
@@ -1428,8 +1426,8 @@
{
/* Get tick */
tickstart = HAL_GetTick();
-
- /* Wait till LSE is ready */
+
+ /* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
@@ -1442,7 +1440,7 @@
__HAL_RCC_RTC_CONFIG(PeriphClkInit->RTCClockSelection);
}
/*--------------------------------------------------------------------------*/
-
+
/*------------------------------------ TIM configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_TIM) == (RCC_PERIPHCLK_TIM))
{
@@ -1450,46 +1448,46 @@
__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
}
/*--------------------------------------------------------------------------*/
-
+
/*------------------------------------- FMPI2C1 Configuration --------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1)
{
/* Check the parameters */
assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection));
-
+
/* Configure the FMPI2C1 clock source */
__HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection);
}
/*--------------------------------------------------------------------------*/
-
+
/*------------------------------------- CLK48 Configuration ----------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48)
{
/* Check the parameters */
assert_param(IS_RCC_CLK48CLKSOURCE(PeriphClkInit->Clk48ClockSelection));
-
+
/* Configure the SDIO clock source */
__HAL_RCC_CLK48_CONFIG(PeriphClkInit->Clk48ClockSelection);
/* Enable the PLLI2S when it's used as clock source for CLK48 */
if(PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ)
{
- plli2sused = 1U;
+ plli2sused = 1U;
}
}
/*--------------------------------------------------------------------------*/
-
+
/*------------------------------------- SDIO Configuration -----------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SDIO) == RCC_PERIPHCLK_SDIO)
{
/* Check the parameters */
assert_param(IS_RCC_SDIOCLKSOURCE(PeriphClkInit->SdioClockSelection));
-
+
/* Configure the SDIO clock source */
__HAL_RCC_SDIO_CONFIG(PeriphClkInit->SdioClockSelection);
}
/*--------------------------------------------------------------------------*/
-
+
/*-------------------------------------- PLLI2S Configuration --------------*/
/* PLLI2S is configured when a peripheral will use it as source clock : I2S on APB1 or
I2S on APB2*/
@@ -1515,8 +1513,8 @@
assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
/*-------------------- Set the PLL I2S clock -----------------------------*/
__HAL_RCC_PLL_I2S_CONFIG(PeriphClkInit->PLLI2SSelection);
-
- /*------- In Case of PLLI2S is selected as source clock for I2S ----------*/
+
+ /*------- In Case of PLLI2S is selected as source clock for I2S ----------*/
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB1) == RCC_PERIPHCLK_I2S_APB1) && (PeriphClkInit->I2sApb1ClockSelection == RCC_I2SAPB1CLKSOURCE_PLLI2S)) ||
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S_APB2) == RCC_PERIPHCLK_I2S_APB2) && (PeriphClkInit->I2sApb2ClockSelection == RCC_I2SAPB2CLKSOURCE_PLLI2S)) ||
((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_CLK48) == RCC_PERIPHCLK_CLK48) && (PeriphClkInit->Clk48ClockSelection == RCC_CLK48CLKSOURCE_PLLI2SQ)) ||
@@ -1531,28 +1529,28 @@
/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ, PeriphClkInit->PLLI2S.PLLI2SR);
}
-
+
#if defined(STM32F413xx) || defined(STM32F423xx)
- /*------- In Case of PLLI2S is selected as source clock for SAI ----------*/
+ /*------- In Case of PLLI2S is selected as source clock for SAI ----------*/
if(((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIA) == RCC_PERIPHCLK_SAIA) && (PeriphClkInit->SaiAClockSelection == RCC_SAIACLKSOURCE_PLLI2SR)) ||
- ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIB) == RCC_PERIPHCLK_SAIB) && (PeriphClkInit->SaiBClockSelection == RCC_SAIBCLKSOURCE_PLLI2SR)))
+ ((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAIB) == RCC_PERIPHCLK_SAIB) && (PeriphClkInit->SaiBClockSelection == RCC_SAIBCLKSOURCE_PLLI2SR)))
{
/* Check for PLLI2S Parameters */
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
/* Check for PLLI2S/DIVR parameters */
assert_param(IS_RCC_PLLI2S_DIVR_VALUE(PeriphClkInit->PLLI2SDivR));
-
+
/* Read PLLI2SQ value from PLLI2SCFGR register (this value is not needed for SAI configuration) */
- plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
- /* Configure the PLLI2S division factors */
+ plli2sq = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
+ /* Configure the PLLI2S division factors */
/* PLLI2S_VCO Input = PLL_SOURCE/PLLI2SM */
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, plli2sq, PeriphClkInit->PLLI2S.PLLI2SR);
-
- /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVR */
- __HAL_RCC_PLLI2S_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLI2SDivR);
- }
+
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVR */
+ __HAL_RCC_PLLI2S_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLI2SDivR);
+ }
#endif /* STM32F413xx || STM32F423xx */
/*----------------- In Case of PLLI2S is just selected ------------------*/
@@ -1605,8 +1603,8 @@
__HAL_RCC_DFSDM1AUDIO_CONFIG(PeriphClkInit->Dfsdm1AudioClockSelection);
}
/*--------------------------------------------------------------------------*/
-
-#if defined(STM32F413xx) || defined(STM32F423xx)
+
+#if defined(STM32F413xx) || defined(STM32F423xx)
/*-------------------- DFSDM2 clock source configuration -------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_DFSDM2) == RCC_PERIPHCLK_DFSDM2)
{
@@ -1628,13 +1626,13 @@
__HAL_RCC_DFSDM2AUDIO_CONFIG(PeriphClkInit->Dfsdm2AudioClockSelection);
}
/*--------------------------------------------------------------------------*/
-
+
/*---------------------------- LPTIM1 Configuration ------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
{
/* Check the parameters */
assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));
-
+
/* Configure the LPTIM1 clock source */
__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
}
@@ -1647,14 +1645,14 @@
/**
* @brief Get the RCC_PeriphCLKInitTypeDef according to the internal
* RCC configuration registers.
- * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
+ * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
* will be configured.
* @retval None
*/
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
uint32_t tempreg;
-
+
/* Set all possible values for the extended clock type parameter------------*/
#if defined(STM32F413xx) || defined(STM32F423xx)
PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S_APB1 | RCC_PERIPHCLK_I2S_APB2 |\
@@ -1671,26 +1669,26 @@
RCC_PERIPHCLK_SDIO | RCC_PERIPHCLK_DFSDM1 |\
RCC_PERIPHCLK_DFSDM1_AUDIO;
#endif /* STM32F413xx || STM32F423xx */
-
-
-
+
+
+
/* Get the PLLI2S Clock configuration --------------------------------------*/
- PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SM));
- PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
- PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
- PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
+ PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM) >> RCC_PLLI2SCFGR_PLLI2SM_Pos);
+ PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
+ PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
+ PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
#if defined(STM32F413xx) || defined(STM32F423xx)
/* Get the PLL/PLLI2S division factors -------------------------------------*/
- PeriphClkInit->PLLI2SDivR = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVR) >> POSITION_VAL(RCC_DCKCFGR_PLLI2SDIVR));
- PeriphClkInit->PLLDivR = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLDIVR) >> POSITION_VAL(RCC_DCKCFGR_PLLDIVR));
+ PeriphClkInit->PLLI2SDivR = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVR) >> RCC_DCKCFGR_PLLI2SDIVR_Pos);
+ PeriphClkInit->PLLDivR = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLDIVR) >> RCC_DCKCFGR_PLLDIVR_Pos);
#endif /* STM32F413xx || STM32F423xx */
-
+
/* Get the I2S APB1 clock configuration ------------------------------------*/
PeriphClkInit->I2sApb1ClockSelection = __HAL_RCC_GET_I2S_APB1_SOURCE();
-
+
/* Get the I2S APB2 clock configuration ------------------------------------*/
PeriphClkInit->I2sApb2ClockSelection = __HAL_RCC_GET_I2S_APB2_SOURCE();
-
+
/* Get the RTC Clock configuration -----------------------------------------*/
tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
@@ -1700,29 +1698,29 @@
/* Get the CLK48 clock configuration ---------------------------------------*/
PeriphClkInit->Clk48ClockSelection = __HAL_RCC_GET_CLK48_SOURCE();
-
+
/* Get the SDIO clock configuration ----------------------------------------*/
PeriphClkInit->SdioClockSelection = __HAL_RCC_GET_SDIO_SOURCE();
-
+
/* Get the DFSDM1 clock configuration --------------------------------------*/
PeriphClkInit->Dfsdm1ClockSelection = __HAL_RCC_GET_DFSDM1_SOURCE();
-
+
/* Get the DFSDM1 Audio clock configuration --------------------------------*/
PeriphClkInit->Dfsdm1AudioClockSelection = __HAL_RCC_GET_DFSDM1AUDIO_SOURCE();
#if defined(STM32F413xx) || defined(STM32F423xx)
/* Get the DFSDM2 clock configuration --------------------------------------*/
PeriphClkInit->Dfsdm2ClockSelection = __HAL_RCC_GET_DFSDM2_SOURCE();
-
+
/* Get the DFSDM2 Audio clock configuration --------------------------------*/
PeriphClkInit->Dfsdm2AudioClockSelection = __HAL_RCC_GET_DFSDM2AUDIO_SOURCE();
-
+
/* Get the LPTIM1 clock configuration --------------------------------------*/
PeriphClkInit->Lptim1ClockSelection = __HAL_RCC_GET_LPTIM1_SOURCE();
-
+
/* Get the SAI1 Block Aclock configuration ---------------------------------*/
PeriphClkInit->SaiAClockSelection = __HAL_RCC_GET_SAI_BLOCKA_SOURCE();
-
+
/* Get the SAI1 Block B clock configuration --------------------------------*/
PeriphClkInit->SaiBClockSelection = __HAL_RCC_GET_SAI_BLOCKB_SOURCE();
#endif /* STM32F413xx || STM32F423xx */
@@ -1739,9 +1737,9 @@
}
/**
- * @brief Return the peripheral clock frequency for a given peripheral(I2S..)
+ * @brief Return the peripheral clock frequency for a given peripheral(I2S..)
* @note Return 0 if peripheral clock identifier not managed by this API
- * @param PeriphClk: Peripheral clock identifier
+ * @param PeriphClk Peripheral clock identifier
* This parameter can be one of the following values:
* @arg RCC_PERIPHCLK_I2S_APB1: I2S APB1 peripheral clock
* @arg RCC_PERIPHCLK_I2S_APB2: I2S APB2 peripheral clock
@@ -1764,8 +1762,8 @@
srcclk = __HAL_RCC_GET_I2S_APB1_SOURCE();
switch (srcclk)
{
- /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
- case RCC_I2SAPB1CLKSOURCE_EXT:
+ /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
+ case RCC_I2SAPB1CLKSOURCE_EXT:
{
/* Set the I2S clock to the external clock value */
frequency = EXTERNAL_CLOCK_VALUE;
@@ -1792,7 +1790,7 @@
{
/* Get the I2S source clock value */
vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
- }
+ }
}
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
@@ -1815,7 +1813,7 @@
/* Get the I2S source clock value */
vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
}
-
+
/* PLL_VCO Output = PLL_VCO Input * PLLN */
vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U)));
/* I2S_CLK = PLL_VCO Output/PLLR */
@@ -1840,7 +1838,7 @@
{
frequency = 0U;
break;
- }
+ }
}
break;
}
@@ -1850,8 +1848,8 @@
srcclk = __HAL_RCC_GET_I2S_APB2_SOURCE();
switch (srcclk)
{
- /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
- case RCC_I2SAPB2CLKSOURCE_EXT:
+ /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
+ case RCC_I2SAPB2CLKSOURCE_EXT:
{
/* Set the I2S clock to the external clock value */
frequency = EXTERNAL_CLOCK_VALUE;
@@ -1878,7 +1876,7 @@
{
/* Get the I2S source clock value */
vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM));
- }
+ }
}
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
@@ -1901,7 +1899,7 @@
/* Get the I2S source clock value */
vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
}
-
+
/* PLL_VCO Output = PLL_VCO Input * PLLN */
vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U)));
/* I2S_CLK = PLL_VCO Output/PLLR */
@@ -1926,12 +1924,12 @@
{
frequency = 0U;
break;
- }
+ }
}
break;
}
}
- return frequency;
+ return frequency;
}
#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
@@ -1939,38 +1937,38 @@
/**
* @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the
* RCC_PeriphCLKInitTypeDef.
- * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
+ * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
* contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks).
- *
- * @note A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case
- * the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup
+ *
+ * @note A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case
+ * the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup
* domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset
- *
+ *
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
uint32_t tickstart = 0U;
uint32_t tmpreg1 = 0U;
-
+
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
-
+
/*---------------------------- RTC configuration ---------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
{
/* Check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
-
+
/* Enable Power Clock*/
__HAL_RCC_PWR_CLK_ENABLE();
-
+
/* Enable write access to Backup domain */
PWR->CR |= PWR_CR_DBP;
-
+
/* Get tick */
tickstart = HAL_GetTick();
-
+
while((PWR->CR & PWR_CR_DBP) == RESET)
{
if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
@@ -1978,7 +1976,7 @@
return HAL_TIMEOUT;
}
}
- /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
+ /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
{
@@ -1995,8 +1993,8 @@
{
/* Get tick */
tickstart = HAL_GetTick();
-
- /* Wait till LSE is ready */
+
+ /* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
@@ -2016,24 +2014,24 @@
__HAL_RCC_TIMCLKPRESCALER(PeriphClkInit->TIMPresSelection);
}
/*--------------------------------------------------------------------------*/
-
+
/*---------------------------- FMPI2C1 Configuration -----------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_FMPI2C1) == RCC_PERIPHCLK_FMPI2C1)
{
/* Check the parameters */
assert_param(IS_RCC_FMPI2C1CLKSOURCE(PeriphClkInit->Fmpi2c1ClockSelection));
-
+
/* Configure the FMPI2C1 clock source */
__HAL_RCC_FMPI2C1_CONFIG(PeriphClkInit->Fmpi2c1ClockSelection);
}
/*--------------------------------------------------------------------------*/
-
+
/*---------------------------- LPTIM1 Configuration ------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LPTIM1) == RCC_PERIPHCLK_LPTIM1)
{
/* Check the parameters */
assert_param(IS_RCC_LPTIM1CLKSOURCE(PeriphClkInit->Lptim1ClockSelection));
-
+
/* Configure the LPTIM1 clock source */
__HAL_RCC_LPTIM1_CONFIG(PeriphClkInit->Lptim1ClockSelection);
}
@@ -2043,7 +2041,7 @@
{
/* Check the parameters */
assert_param(IS_RCC_I2SAPBCLKSOURCE(PeriphClkInit->I2SClockSelection));
-
+
/* Configure the I2S clock source */
__HAL_RCC_I2S_CONFIG(PeriphClkInit->I2SClockSelection);
}
@@ -2052,9 +2050,9 @@
}
/**
- * @brief Configures the RCC_OscInitStruct according to the internal
+ * @brief Configures the RCC_OscInitStruct according to the internal
* RCC configuration registers.
- * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
+ * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
* will be configured.
* @retval None
*/
@@ -2064,10 +2062,10 @@
/* Set all possible values for the extended clock type parameter------------*/
PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_FMPI2C1 | RCC_PERIPHCLK_LPTIM1 | RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC;
-
+
tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
-
+
if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
{
PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
@@ -2082,12 +2080,12 @@
/* Get the I2S clock configuration -----------------------------------------*/
PeriphClkInit->I2SClockSelection = __HAL_RCC_GET_I2S_SOURCE();
-
+
}
/**
- * @brief Return the peripheral clock frequency for a given peripheral(SAI..)
+ * @brief Return the peripheral clock frequency for a given peripheral(SAI..)
* @note Return 0 if peripheral clock identifier not managed by this API
- * @param PeriphClk: Peripheral clock identifier
+ * @param PeriphClk Peripheral clock identifier
* This parameter can be one of the following values:
* @arg RCC_PERIPHCLK_I2S: I2S peripheral clock
* @retval Frequency in KHz
@@ -2109,8 +2107,8 @@
srcclk = __HAL_RCC_GET_I2S_SOURCE();
switch (srcclk)
{
- /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
- case RCC_I2SAPBCLKSOURCE_EXT:
+ /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
+ case RCC_I2SAPBCLKSOURCE_EXT:
{
/* Set the I2S clock to the external clock value */
frequency = EXTERNAL_CLOCK_VALUE;
@@ -2131,7 +2129,7 @@
/* Get the I2S source clock value */
vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
}
-
+
/* PLL_VCO Output = PLL_VCO Input * PLLN */
vcooutput = (uint32_t)(vcoinput * (((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6U) & (RCC_PLLCFGR_PLLN >> 6U)));
/* I2S_CLK = PLL_VCO Output/PLLR */
@@ -2161,7 +2159,7 @@
break;
}
}
- return frequency;
+ return frequency;
}
#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
@@ -2169,13 +2167,13 @@
/**
* @brief Initializes the RCC extended peripherals clocks according to the specified
* parameters in the RCC_PeriphCLKInitTypeDef.
- * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
+ * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
* contains the configuration information for the Extended Peripherals
* clocks(I2S, SAI, LTDC RTC and TIM).
- *
- * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
- * the RTC clock source; in this case the Backup domain will be reset in
- * order to modify the RTC Clock source, as consequence RTC registers (including
+ *
+ * @note Care must be taken when HAL_RCCEx_PeriphCLKConfig() is used to select
+ * the RTC clock source; in this case the Backup domain will be reset in
+ * order to modify the RTC Clock source, as consequence RTC registers (including
* the backup registers) and RCC_BDCR register are set to their reset values.
*
* @retval HAL status
@@ -2184,22 +2182,22 @@
{
uint32_t tickstart = 0U;
uint32_t tmpreg1 = 0U;
-
+
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
-
+
/*----------------------- SAI/I2S Configuration (PLLI2S) -------------------*/
/*----------------------- Common configuration SAI/I2S ---------------------*/
- /* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division
- factor is common parameters for both peripherals */
- if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) ||
+ /* In Case of SAI or I2S Clock Configuration through PLLI2S, PLLI2SN division
+ factor is common parameters for both peripherals */
+ if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) ||
(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == RCC_PERIPHCLK_SAI_PLLI2S))
{
/* check for Parameters */
assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
-
+
/* Disable the PLLI2S */
- __HAL_RCC_PLLI2S_DISABLE();
+ __HAL_RCC_PLLI2S_DISABLE();
/* Get tick */
tickstart = HAL_GetTick();
/* Wait till PLLI2S is disabled */
@@ -2211,10 +2209,10 @@
return HAL_TIMEOUT;
}
}
-
+
/*---------------------------- I2S configuration -------------------------*/
- /* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added
- only for I2S configuration */
+ /* In Case of I2S Clock Configuration through PLLI2S, PLLI2SR must be added
+ only for I2S configuration */
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == (RCC_PERIPHCLK_I2S))
{
/* check for Parameters */
@@ -2224,27 +2222,27 @@
/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
}
-
- /*---------------------------- SAI configuration -------------------------*/
- /* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must
- be added only for SAI configuration */
+
+ /*---------------------------- SAI configuration -------------------------*/
+ /* In Case of SAI Clock Configuration through PLLI2S, PLLI2SQ and PLLI2S_DIVQ must
+ be added only for SAI configuration */
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLI2S) == (RCC_PERIPHCLK_SAI_PLLI2S))
{
/* Check the PLLI2S division factors */
assert_param(IS_RCC_PLLI2SQ_VALUE(PeriphClkInit->PLLI2S.PLLI2SQ));
assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
-
+
/* Read PLLI2SR value from PLLI2SCFGR register (this value is not need for SAI configuration) */
- tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
- /* Configure the PLLI2S division factors */
+ tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
+ /* Configure the PLLI2S division factors */
/* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
/* SAI_CLK(first level) = PLLI2S_VCO Output/PLLI2SQ */
__HAL_RCC_PLLI2S_SAICLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SQ , tmpreg1);
- /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLI2SDIVQ */
__HAL_RCC_PLLI2S_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLI2SDivQ);
}
-
+
/* Enable the PLLI2S */
__HAL_RCC_PLLI2S_ENABLE();
/* Get tick */
@@ -2260,64 +2258,64 @@
}
}
/*--------------------------------------------------------------------------*/
-
+
/*----------------------- SAI/LTDC Configuration (PLLSAI) ------------------*/
/*----------------------- Common configuration SAI/LTDC --------------------*/
/* In Case of SAI or LTDC Clock Configuration through PLLSAI, PLLSAIN division
- factor is common parameters for both peripherals */
- if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) ||
+ factor is common parameters for both peripherals */
+ if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == RCC_PERIPHCLK_SAI_PLLSAI) ||
(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == RCC_PERIPHCLK_LTDC))
{
/* Check the PLLSAI division factors */
assert_param(IS_RCC_PLLSAIN_VALUE(PeriphClkInit->PLLSAI.PLLSAIN));
-
+
/* Disable PLLSAI Clock */
- __HAL_RCC_PLLSAI_DISABLE();
+ __HAL_RCC_PLLSAI_DISABLE();
/* Get tick */
tickstart = HAL_GetTick();
/* Wait till PLLSAI is disabled */
while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
{
if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
- {
+ {
/* return in case of Timeout detected */
return HAL_TIMEOUT;
}
}
-
+
/*---------------------------- SAI configuration -------------------------*/
- /* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must
- be added only for SAI configuration */
+ /* In Case of SAI Clock Configuration through PLLSAI, PLLSAIQ and PLLSAI_DIVQ must
+ be added only for SAI configuration */
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_SAI_PLLSAI) == (RCC_PERIPHCLK_SAI_PLLSAI))
{
assert_param(IS_RCC_PLLSAIQ_VALUE(PeriphClkInit->PLLSAI.PLLSAIQ));
assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
-
+
/* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
- tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
+ tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , PeriphClkInit->PLLSAI.PLLSAIQ, tmpreg1);
- /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
+ /* SAI_CLK_x = SAI_CLK(first level)/PLLSAIDIVQ */
__HAL_RCC_PLLSAI_PLLSAICLKDIVQ_CONFIG(PeriphClkInit->PLLSAIDivQ);
}
-
+
/*---------------------------- LTDC configuration ------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_LTDC) == (RCC_PERIPHCLK_LTDC))
{
assert_param(IS_RCC_PLLSAIR_VALUE(PeriphClkInit->PLLSAI.PLLSAIR));
assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
-
+
/* Read PLLSAIR value from PLLSAICFGR register (this value is not need for SAI configuration) */
- tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
+ tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
/* LTDC_CLK(first level) = PLLSAI_VCO Output/PLLSAIR */
__HAL_RCC_PLLSAI_CONFIG(PeriphClkInit->PLLSAI.PLLSAIN , tmpreg1, PeriphClkInit->PLLSAI.PLLSAIR);
- /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
+ /* LTDC_CLK = LTDC_CLK(first level)/PLLSAIDIVR */
__HAL_RCC_PLLSAI_PLLSAICLKDIVR_CONFIG(PeriphClkInit->PLLSAIDivR);
- }
+ }
/* Enable PLLSAI Clock */
__HAL_RCC_PLLSAI_ENABLE();
/* Get tick */
@@ -2326,29 +2324,29 @@
while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
{
if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
- {
+ {
/* return in case of Timeout detected */
return HAL_TIMEOUT;
}
- }
+ }
}
/*--------------------------------------------------------------------------*/
-
+
/*---------------------------- RTC configuration ---------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
{
/* Check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
-
+
/* Enable Power Clock*/
__HAL_RCC_PWR_CLK_ENABLE();
-
+
/* Enable write access to Backup domain */
PWR->CR |= PWR_CR_DBP;
-
+
/* Get tick */
tickstart = HAL_GetTick();
-
+
while((PWR->CR & PWR_CR_DBP) == RESET)
{
if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
@@ -2356,7 +2354,7 @@
return HAL_TIMEOUT;
}
}
- /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
+ /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
{
@@ -2373,8 +2371,8 @@
{
/* Get tick */
tickstart = HAL_GetTick();
-
- /* Wait till LSE is ready */
+
+ /* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
@@ -2397,35 +2395,35 @@
}
/**
- * @brief Configures the PeriphClkInit according to the internal
+ * @brief Configures the PeriphClkInit according to the internal
* RCC configuration registers.
- * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
+ * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
* will be configured.
* @retval None
*/
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
uint32_t tempreg;
-
+
/* Set all possible values for the extended clock type parameter------------*/
PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_SAI_PLLSAI | RCC_PERIPHCLK_SAI_PLLI2S | RCC_PERIPHCLK_LTDC | RCC_PERIPHCLK_TIM | RCC_PERIPHCLK_RTC;
-
+
/* Get the PLLI2S Clock configuration -----------------------------------------------*/
- PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
- PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
- PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
+ PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
+ PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
+ PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
/* Get the PLLSAI Clock configuration -----------------------------------------------*/
- PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN));
- PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
- PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
+ PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos);
+ PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
+ PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
/* Get the PLLSAI/PLLI2S division factors -----------------------------------------------*/
- PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLI2SDIVQ));
- PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR_PLLSAIDIVQ));
+ PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLI2SDIVQ) >> RCC_DCKCFGR_PLLI2SDIVQ_Pos);
+ PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVQ) >> RCC_DCKCFGR_PLLSAIDIVQ_Pos);
PeriphClkInit->PLLSAIDivR = (uint32_t)(RCC->DCKCFGR & RCC_DCKCFGR_PLLSAIDIVR);
/* Get the RTC Clock configuration -----------------------------------------------*/
tempreg = (RCC->CFGR & RCC_CFGR_RTCPRE);
PeriphClkInit->RTCClockSelection = (uint32_t)((tempreg) | (RCC->BDCR & RCC_BDCR_RTCSEL));
-
+
if ((RCC->DCKCFGR & RCC_DCKCFGR_TIMPRE) == RESET)
{
PeriphClkInit->TIMPresSelection = RCC_TIMPRES_DESACTIVATED;
@@ -2437,9 +2435,9 @@
}
/**
- * @brief Return the peripheral clock frequency for a given peripheral(SAI..)
+ * @brief Return the peripheral clock frequency for a given peripheral(SAI..)
* @note Return 0 if peripheral clock identifier not managed by this API
- * @param PeriphClk: Peripheral clock identifier
+ * @param PeriphClk Peripheral clock identifier
* This parameter can be one of the following values:
* @arg RCC_PERIPHCLK_I2S: I2S peripheral clock
* @retval Frequency in KHz
@@ -2461,8 +2459,8 @@
srcclk = __HAL_RCC_GET_I2S_SOURCE();
switch (srcclk)
{
- /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
- case RCC_I2SCLKSOURCE_EXT:
+ /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
+ case RCC_I2SCLKSOURCE_EXT:
{
/* Set the I2S clock to the external clock value */
frequency = EXTERNAL_CLOCK_VALUE;
@@ -2483,7 +2481,7 @@
/* Get the I2S source clock value */
vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
}
-
+
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
/* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
@@ -2495,12 +2493,12 @@
{
frequency = 0U;
break;
- }
+ }
}
break;
}
}
- return frequency;
+ return frequency;
}
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
@@ -2509,23 +2507,23 @@
/**
* @brief Initializes the RCC extended peripherals clocks according to the specified parameters in the
* RCC_PeriphCLKInitTypeDef.
- * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
+ * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
* contains the configuration information for the Extended Peripherals clocks(I2S and RTC clocks).
- *
- * @note A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case
- * the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup
+ *
+ * @note A caution to be taken when HAL_RCCEx_PeriphCLKConfig() is used to select RTC clock selection, in this case
+ * the Reset of Backup domain will be applied in order to modify the RTC Clock source as consequence all backup
* domain (RTC and RCC_BDCR register expect BKPSRAM) will be reset
- *
+ *
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
uint32_t tickstart = 0U;
uint32_t tmpreg1 = 0U;
-
+
/* Check the parameters */
assert_param(IS_RCC_PERIPHCLOCK(PeriphClkInit->PeriphClockSelection));
-
+
/*---------------------------- I2S configuration ---------------------------*/
if((((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_I2S) == RCC_PERIPHCLK_I2S) ||
(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_PLLI2S) == RCC_PERIPHCLK_PLLI2S))
@@ -2533,7 +2531,7 @@
/* check for Parameters */
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
assert_param(IS_RCC_PLLI2SN_VALUE(PeriphClkInit->PLLI2S.PLLI2SN));
-#if defined(STM32F411xE)
+#if defined(STM32F411xE)
assert_param(IS_RCC_PLLI2SM_VALUE(PeriphClkInit->PLLI2S.PLLI2SM));
#endif /* STM32F411xE */
/* Disable the PLLI2S */
@@ -2547,13 +2545,13 @@
{
/* return in case of Timeout detected */
return HAL_TIMEOUT;
- }
+ }
}
#if defined(STM32F411xE)
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
- /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
+ /* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
__HAL_RCC_PLLI2S_I2SCLK_CONFIG(PeriphClkInit->PLLI2S.PLLI2SM, PeriphClkInit->PLLI2S.PLLI2SN, PeriphClkInit->PLLI2S.PLLI2SR);
#else
/* Configure the PLLI2S division factors */
@@ -2561,7 +2559,7 @@
/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
__HAL_RCC_PLLI2S_CONFIG(PeriphClkInit->PLLI2S.PLLI2SN , PeriphClkInit->PLLI2S.PLLI2SR);
#endif /* STM32F411xE */
-
+
/* Enable the PLLI2S */
__HAL_RCC_PLLI2S_ENABLE();
/* Get tick */
@@ -2576,22 +2574,22 @@
}
}
}
-
+
/*---------------------------- RTC configuration ---------------------------*/
if(((PeriphClkInit->PeriphClockSelection) & RCC_PERIPHCLK_RTC) == (RCC_PERIPHCLK_RTC))
{
/* Check for RTC Parameters used to output RTCCLK */
assert_param(IS_RCC_RTCCLKSOURCE(PeriphClkInit->RTCClockSelection));
-
+
/* Enable Power Clock*/
__HAL_RCC_PWR_CLK_ENABLE();
-
+
/* Enable write access to Backup domain */
PWR->CR |= PWR_CR_DBP;
-
+
/* Get tick */
tickstart = HAL_GetTick();
-
+
while((PWR->CR & PWR_CR_DBP) == RESET)
{
if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
@@ -2599,7 +2597,7 @@
return HAL_TIMEOUT;
}
}
- /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
+ /* Reset the Backup domain only if the RTC Clock source selection is modified from reset value */
tmpreg1 = (RCC->BDCR & RCC_BDCR_RTCSEL);
if((tmpreg1 != 0x00000000U) && ((tmpreg1) != (PeriphClkInit->RTCClockSelection & RCC_BDCR_RTCSEL)))
{
@@ -2616,8 +2614,8 @@
{
/* Get tick */
tickstart = HAL_GetTick();
-
- /* Wait till LSE is ready */
+
+ /* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
@@ -2640,22 +2638,22 @@
}
/**
- * @brief Configures the RCC_OscInitStruct according to the internal
+ * @brief Configures the RCC_OscInitStruct according to the internal
* RCC configuration registers.
- * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
+ * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
* will be configured.
* @retval None
*/
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
{
uint32_t tempreg;
-
+
/* Set all possible values for the extended clock type parameter------------*/
PeriphClkInit->PeriphClockSelection = RCC_PERIPHCLK_I2S | RCC_PERIPHCLK_RTC;
-
+
/* Get the PLLI2S Clock configuration --------------------------------------*/
- PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
- PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
+ PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
+ PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
#if defined(STM32F411xE)
PeriphClkInit->PLLI2S.PLLI2SM = (uint32_t)(RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SM);
#endif /* STM32F411xE */
@@ -2673,13 +2671,13 @@
{
PeriphClkInit->TIMPresSelection = RCC_TIMPRES_ACTIVATED;
}
-#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
+#endif /* STM32F401xC || STM32F401xE || STM32F411xE */
}
/**
- * @brief Return the peripheral clock frequency for a given peripheral(SAI..)
+ * @brief Return the peripheral clock frequency for a given peripheral(SAI..)
* @note Return 0 if peripheral clock identifier not managed by this API
- * @param PeriphClk: Peripheral clock identifier
+ * @param PeriphClk Peripheral clock identifier
* This parameter can be one of the following values:
* @arg RCC_PERIPHCLK_I2S: I2S peripheral clock
* @retval Frequency in KHz
@@ -2701,8 +2699,8 @@
srcclk = __HAL_RCC_GET_I2S_SOURCE();
switch (srcclk)
{
- /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
- case RCC_I2SCLKSOURCE_EXT:
+ /* Check if I2S clock selection is External clock mapped on the I2S_CKIN pin used as I2S clock */
+ case RCC_I2SCLKSOURCE_EXT:
{
/* Set the I2S clock to the external clock value */
frequency = EXTERNAL_CLOCK_VALUE;
@@ -2737,7 +2735,7 @@
/* Get the I2S source clock value */
vcoinput = (uint32_t)(HSI_VALUE / (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM));
}
-#endif /* STM32F411xE */
+#endif /* STM32F411xE */
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
vcooutput = (uint32_t)(vcoinput * (((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6U) & (RCC_PLLI2SCFGR_PLLI2SN >> 6U)));
/* I2S_CLK = PLLI2S_VCO Output/PLLI2SR */
@@ -2749,12 +2747,12 @@
{
frequency = 0U;
break;
- }
+ }
}
break;
}
}
- return frequency;
+ return frequency;
}
#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F411xE */
@@ -2762,10 +2760,10 @@
defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
/**
* @brief Select LSE mode
- *
+ *
* @note This mode is only available for STM32F410xx/STM32F411xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices.
- *
- * @param Mode: specifies the LSE mode.
+ *
+ * @param Mode specifies the LSE mode.
* This parameter can be one of the following values:
* @arg RCC_LSE_LOWPOWER_MODE: LSE oscillator in low power mode selection
* @arg RCC_LSE_HIGHDRIVE_MODE: LSE oscillator in High Drive mode selection
@@ -2787,20 +2785,255 @@
#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+/** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions
+ * @brief Extended Clock management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended clock management functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the
+ activation or deactivation of PLLI2S, PLLSAI.
+@endverbatim
+ * @{
+ */
+
+#if defined(RCC_PLLI2S_SUPPORT)
+/**
+ * @brief Enable PLLI2S.
+ * @param PLLI2SInit pointer to an RCC_PLLI2SInitTypeDef structure that
+ * contains the configuration information for the PLLI2S
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit)
+{
+ uint32_t tickstart;
+
+ /* Check for parameters */
+ assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SInit->PLLI2SN));
+ assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SInit->PLLI2SR));
+#if defined(RCC_PLLI2SCFGR_PLLI2SM)
+ assert_param(IS_RCC_PLLI2SM_VALUE(PLLI2SInit->PLLI2SM));
+#endif /* RCC_PLLI2SCFGR_PLLI2SM */
+#if defined(RCC_PLLI2SCFGR_PLLI2SP)
+ assert_param(IS_RCC_PLLI2SP_VALUE(PLLI2SInit->PLLI2SP));
+#endif /* RCC_PLLI2SCFGR_PLLI2SP */
+#if defined(RCC_PLLI2SCFGR_PLLI2SQ)
+ assert_param(IS_RCC_PLLI2SQ_VALUE(PLLI2SInit->PLLI2SQ));
+#endif /* RCC_PLLI2SCFGR_PLLI2SQ */
+
+ /* Disable the PLLI2S */
+ __HAL_RCC_PLLI2S_DISABLE();
+
+ /* Wait till PLLI2S is disabled */
+ tickstart = HAL_GetTick();
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+ {
+ /* return in case of Timeout detected */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Configure the PLLI2S division factors */
+#if defined(STM32F446xx)
+ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
+ /* I2SPCLK = PLLI2S_VCO / PLLI2SP */
+ /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */
+ /* I2SRCLK = PLLI2S_VCO / PLLI2SR */
+ __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SM, PLLI2SInit->PLLI2SN, \
+ PLLI2SInit->PLLI2SP, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR);
+#elif defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
+ defined(STM32F413xx) || defined(STM32F423xx)
+ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM)*/
+ /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */
+ /* I2SRCLK = PLLI2S_VCO / PLLI2SR */
+ __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SM, PLLI2SInit->PLLI2SN, \
+ PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR);
+#elif defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) ||\
+ defined(STM32F469xx) || defined(STM32F479xx)
+ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * PLLI2SN */
+ /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */
+ /* I2SRCLK = PLLI2S_VCO / PLLI2SR */
+ __HAL_RCC_PLLI2S_SAICLK_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR);
+#elif defined(STM32F411xE)
+ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * (PLLI2SN/PLLI2SM) */
+ /* I2SRCLK = PLLI2S_VCO / PLLI2SR */
+ __HAL_RCC_PLLI2S_I2SCLK_CONFIG(PLLI2SInit->PLLI2SM, PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SR);
+#else
+ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x PLLI2SN */
+ /* I2SRCLK = PLLI2S_VCO / PLLI2SR */
+ __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SR);
+#endif /* STM32F446xx */
+
+ /* Enable the PLLI2S */
+ __HAL_RCC_PLLI2S_ENABLE();
+
+ /* Wait till PLLI2S is ready */
+ tickstart = HAL_GetTick();
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+ {
+ /* return in case of Timeout detected */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable PLLI2S.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void)
+{
+ uint32_t tickstart;
+
+ /* Disable the PLLI2S */
+ __HAL_RCC_PLLI2S_DISABLE();
+
+ /* Wait till PLLI2S is disabled */
+ tickstart = HAL_GetTick();
+ while(READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
+ {
+ /* return in case of Timeout detected */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ return HAL_OK;
+}
+
+#endif /* RCC_PLLI2S_SUPPORT */
+
+#if defined(RCC_PLLSAI_SUPPORT)
+/**
+ * @brief Enable PLLSAI.
+ * @param PLLSAIInit pointer to an RCC_PLLSAIInitTypeDef structure that
+ * contains the configuration information for the PLLSAI
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit)
+{
+ uint32_t tickstart;
+
+ /* Check for parameters */
+ assert_param(IS_RCC_PLLSAIN_VALUE(PLLSAIInit->PLLSAIN));
+ assert_param(IS_RCC_PLLSAIQ_VALUE(PLLSAIInit->PLLSAIQ));
+#if defined(RCC_PLLSAICFGR_PLLSAIM)
+ assert_param(IS_RCC_PLLSAIM_VALUE(PLLSAIInit->PLLSAIM));
+#endif /* RCC_PLLSAICFGR_PLLSAIM */
+#if defined(RCC_PLLSAICFGR_PLLSAIP)
+ assert_param(IS_RCC_PLLSAIP_VALUE(PLLSAIInit->PLLSAIP));
+#endif /* RCC_PLLSAICFGR_PLLSAIP */
+#if defined(RCC_PLLSAICFGR_PLLSAIR)
+ assert_param(IS_RCC_PLLSAIR_VALUE(PLLSAIInit->PLLSAIR));
+#endif /* RCC_PLLSAICFGR_PLLSAIR */
+
+ /* Disable the PLLSAI */
+ __HAL_RCC_PLLSAI_DISABLE();
+
+ /* Wait till PLLSAI is disabled */
+ tickstart = HAL_GetTick();
+ while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
+ {
+ /* return in case of Timeout detected */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Configure the PLLSAI division factors */
+#if defined(STM32F446xx)
+ /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * (PLLSAIN/PLLSAIM) */
+ /* SAIPCLK = PLLSAI_VCO / PLLSAIP */
+ /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */
+ /* SAIRCLK = PLLSAI_VCO / PLLSAIR */
+ __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIM, PLLSAIInit->PLLSAIN, \
+ PLLSAIInit->PLLSAIP, PLLSAIInit->PLLSAIQ, 0U);
+#elif defined(STM32F469xx) || defined(STM32F479xx)
+ /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * PLLSAIN */
+ /* SAIPCLK = PLLSAI_VCO / PLLSAIP */
+ /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */
+ /* SAIRCLK = PLLSAI_VCO / PLLSAIR */
+ __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIP, \
+ PLLSAIInit->PLLSAIQ, PLLSAIInit->PLLSAIR);
+#else
+ /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x PLLSAIN */
+ /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */
+ /* SAIRCLK = PLLSAI_VCO / PLLSAIR */
+ __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIQ, PLLSAIInit->PLLSAIR);
+#endif /* STM32F446xx */
+
+ /* Enable the PLLSAI */
+ __HAL_RCC_PLLSAI_ENABLE();
+
+ /* Wait till PLLSAI is ready */
+ tickstart = HAL_GetTick();
+ while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
+ {
+ /* return in case of Timeout detected */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable PLLSAI.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void)
+{
+ uint32_t tickstart;
+
+ /* Disable the PLLSAI */
+ __HAL_RCC_PLLSAI_DISABLE();
+
+ /* Wait till PLLSAI is disabled */
+ tickstart = HAL_GetTick();
+ while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
+ {
+ if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
+ {
+ /* return in case of Timeout detected */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ return HAL_OK;
+}
+
+#endif /* RCC_PLLSAI_SUPPORT */
+
+/**
+ * @}
+ */
+
#if defined(STM32F446xx)
/**
* @brief Returns the SYSCLK frequency
- *
+ *
* @note This function implementation is valid only for STM32F446xx devices.
* @note This function add the PLL/PLLR System clock source
*
- * @note The system frequency computed by this function is not the real
- * frequency in the chip. It is calculated based on the predefined
+ * @note The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
* @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
* @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
- * @note If SYSCLK source is PLL or PLLR, function returns values based on HSE_VALUE(**)
- * or HSI_VALUE(*) multiplied/divided by the PLL factors.
+ * @note If SYSCLK source is PLL or PLLR, function returns values based on HSE_VALUE(**)
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.
* @note (*) HSI_VALUE is a constant defined in stm32f4xx_hal_conf.h file (default value
* 16 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
@@ -2808,17 +3041,17 @@
* 25 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may
* have wrong result.
- *
+ *
* @note The result of this function could be not correct when using fractional
* value for HSE crystal.
- *
- * @note This function can be used by the user application to compute the
+ *
+ * @note This function can be used by the user application to compute the
* baudrate for the communication peripherals or configure other parameters.
- *
+ *
* @note Each time SYSCLK changes, this function must be called to update the
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
- *
- *
+ *
+ *
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
@@ -2850,15 +3083,15 @@
if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
{
/* HSE used as PLL clock source */
- pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
+ pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
}
else
{
/* HSI used as PLL clock source */
- pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
+ pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
}
- pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> POSITION_VAL(RCC_PLLCFGR_PLLP)) + 1U) *2U);
-
+ pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1U) *2U);
+
sysclockfreq = pllvco/pllp;
break;
}
@@ -2870,15 +3103,15 @@
if(__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLSOURCE_HSI)
{
/* HSE used as PLL clock source */
- pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
+ pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
}
else
{
/* HSI used as PLL clock source */
- pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
+ pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
}
- pllr = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR));
-
+ pllr = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos);
+
sysclockfreq = pllvco/pllr;
break;
}
@@ -2900,11 +3133,6 @@
* @}
*/
-#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || \
- defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || \
- defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F411xE) || defined(STM32F446xx) || \
- defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) || defined(STM32F412Vx) || \
- defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
/**
* @brief Resets the RCC clock configuration to the default reset state.
* @note The default reset state of the clock configuration is given below:
@@ -2914,110 +3142,188 @@
* - CSS, MCO1 and MCO2 OFF
* - All interrupts disabled
* @note This function doesn't modify the configuration of the
- * - Peripheral clocks
- * - LSI, LSE and RTC clocks
- * @retval None
+ * - Peripheral clocks
+ * - LSI, LSE and RTC clocks
+ * @retval HAL status
*/
-void HAL_RCC_DeInit(void)
+HAL_StatusTypeDef HAL_RCC_DeInit(void)
{
- /* Set HSION bit */
- SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4);
+ uint32_t tickstart;
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Set HSION bit to the reset value */
+ SET_BIT(RCC->CR, RCC_CR_HSION);
+
+ /* Wait till HSI is ready */
+ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set HSITRIM[4:0] bits to the reset value */
+ SET_BIT(RCC->CR, RCC_CR_HSITRIM_4);
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
/* Reset CFGR register */
CLEAR_REG(RCC->CFGR);
- /* Reset HSEON, CSSON, PLLON, PLLI2S bits */
- CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_CSSON | RCC_CR_PLLON | RCC_CR_PLLI2SON);
-
-#if defined(STM32F427xx) || defined(STM32F429xx) || defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
+ /* Wait till clock switch is ready */
+ while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Clear HSEON, HSEBYP and CSSON bits */
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_CSSON);
+
+ /* Wait till HSE is disabled */
+ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Clear PLLON bit */
+ CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
+
+ /* Wait till PLL is disabled */
+ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+#if defined(RCC_PLLI2S_SUPPORT)
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Reset PLLI2SON bit */
+ CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON);
+
+ /* Wait till PLLI2S is disabled */
+ while (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+#endif /* RCC_PLLI2S_SUPPORT */
+
+#if defined(RCC_PLLSAI_SUPPORT)
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
/* Reset PLLSAI bit */
CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION);
-#endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
-
- /* Reset PLLCFGR register */
- CLEAR_REG(RCC->PLLCFGR);
+
+ /* Wait till PLLSAI is disabled */
+ while (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) != RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+#endif /* RCC_PLLSAI_SUPPORT */
+
+ /* Once PLL, PLLI2S and PLLSAI are OFF, reset PLLCFGR register to default value */
#if defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || \
defined(STM32F423xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
- SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLR_1);
+ RCC->PLLCFGR = RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLR_1;
+#elif defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+ RCC->PLLCFGR = RCC_PLLCFGR_PLLR_0 | RCC_PLLCFGR_PLLR_1 | RCC_PLLCFGR_PLLR_2 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_0 | RCC_PLLCFGR_PLLQ_1 | RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLQ_3;
#else
- SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2);
+ RCC->PLLCFGR = RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2;
#endif /* STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx || STM32F446xx || STM32F469xx || STM32F479xx */
- /* Reset PLLI2SCFGR register */
- CLEAR_REG(RCC->PLLI2SCFGR);
+ /* Reset PLLI2SCFGR register to default value */
#if defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || \
defined(STM32F423xx) || defined(STM32F446xx)
- SET_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SR_1);
+ RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SR_1;
#elif defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx)
- SET_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1);
+ RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1;
+#elif defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+ RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SR_1;
#elif defined(STM32F411xE)
- SET_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1);
-#else
- SET_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SR_1);
+ RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SM_4 | RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1;
#endif /* STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx || STM32F446xx */
/* Reset PLLSAICFGR register */
#if defined(STM32F427xx) || defined(STM32F429xx) || defined(STM32F437xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
- CLEAR_REG(RCC->PLLSAICFGR);
- SET_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN_6 | RCC_PLLSAICFGR_PLLSAIN_7 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIR_1);
+ RCC->PLLSAICFGR = RCC_PLLSAICFGR_PLLSAIN_6 | RCC_PLLSAICFGR_PLLSAIN_7 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIR_1;
#elif defined(STM32F446xx)
- CLEAR_REG(RCC->PLLSAICFGR);
- SET_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIN_6 | RCC_PLLSAICFGR_PLLSAIN_7 | RCC_PLLSAICFGR_PLLSAIQ_2);
+ RCC->PLLSAICFGR = RCC_PLLSAICFGR_PLLSAIM_4 | RCC_PLLSAICFGR_PLLSAIN_6 | RCC_PLLSAICFGR_PLLSAIN_7 | RCC_PLLSAICFGR_PLLSAIQ_2;
#endif /* STM32F427xx || STM32F429xx || STM32F437xx || STM32F439xx || STM32F469xx || STM32F479xx */
/* Disable all interrupts */
- CLEAR_REG(RCC->CIR);
+ CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE | RCC_CIR_LSERDYIE | RCC_CIR_HSIRDYIE | RCC_CIR_HSERDYIE | RCC_CIR_PLLRDYIE);
+
+#if defined(RCC_CIR_PLLI2SRDYIE)
+ CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
+#endif /* RCC_CIR_PLLI2SRDYIE */
+
+#if defined(RCC_CIR_PLLSAIRDYIE)
+ CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);
+#endif /* RCC_CIR_PLLSAIRDYIE */
+
+ /* Clear all interrupt flags */
+ SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_CSSC);
+
+#if defined(RCC_CIR_PLLI2SRDYC)
+ SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC);
+#endif /* RCC_CIR_PLLI2SRDYC */
+
+#if defined(RCC_CIR_PLLSAIRDYC)
+ SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC);
+#endif /* RCC_CIR_PLLSAIRDYC */
+
+ /* Clear LSION bit */
+ CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
+
+ /* Reset all CSR flags */
+ SET_BIT(RCC->CSR, RCC_CSR_RMVF);
/* Update the SystemCoreClock global variable */
SystemCoreClock = HSI_VALUE;
+
+ /* Adapt Systick interrupt period */
+ if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_OK;
+ }
}
-#endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx ||
- STM32F401xC || STM32F401xE || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx ||
- STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
-
-#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
-/**
- * @brief Resets the RCC clock configuration to the default reset state.
- * @note The default reset state of the clock configuration is given below:
- * - HSI ON and used as system clock source
- * - HSE and PLL OFF
- * - AHB, APB1 and APB2 prescaler set to 1.
- * - CSS, MCO1 and MCO2 OFF
- * - All interrupts disabled
- * @note This function doesn't modify the configuration of the
- * - Peripheral clocks
- * - LSI, LSE and RTC clocks
- * @retval None
- */
-void HAL_RCC_DeInit(void)
-{
- /* Set HSION bit */
- SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4);
-
- /* Reset CFGR register */
- CLEAR_REG(RCC->CFGR);
-
- /* Reset HSEON, HSEBYP, CSSON, PLLON */
- CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_CSSON | RCC_CR_PLLON);
-
- /* Reset PLLCFGR register */
- CLEAR_REG(RCC->PLLCFGR);
- SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR_0 | RCC_PLLCFGR_PLLR_1 | RCC_PLLCFGR_PLLR_2 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_0 | RCC_PLLCFGR_PLLQ_1 | RCC_PLLCFGR_PLLQ_2 | RCC_PLLCFGR_PLLQ_3);
-
- /* Disable all interrupts */
- CLEAR_REG(RCC->CIR);
-
- /* Update the SystemCoreClock global variable */
- SystemCoreClock = HSI_VALUE;
-}
-#endif /* STM32F410Tx || STM32F410Cx || STM32F410Rx */
#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) || defined(STM32F412Zx) ||\
defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
/**
* @brief Initializes the RCC Oscillators according to the specified parameters in the
* RCC_OscInitTypeDef.
- * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
+ * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
* contains the configuration information for the RCC Oscillators.
* @note The PLL is not disabled when used as system clock.
* @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
@@ -3026,17 +3332,17 @@
* @note Transition HSE Bypass to HSE On and HSE On to HSE Bypass are not
* supported by this API. User should request a transition to HSE Off
* first and then HSE On or HSE Bypass.
- * @note This function add the PLL/PLLR factor management during PLL configuration this feature
- * is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices
+ * @note This function add the PLL/PLLR factor management during PLL configuration this feature
+ * is only available in STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
- uint32_t tickstart = 0U;
-
+ uint32_t tickstart = 0U;
+
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
- /*------------------------------- HSE Configuration ------------------------*/
+ /*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
{
/* Check the parameters */
@@ -3060,20 +3366,20 @@
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
-
+
/* Check the HSE State */
if((RCC_OscInitStruct->HSEState) != RCC_HSE_OFF)
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
-
- /* Wait till HSE is ready */
+
+ /* Wait till HSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
+ }
}
}
else
@@ -3087,7 +3393,7 @@
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
+ }
}
}
}
@@ -3098,7 +3404,7 @@
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
-
+
/* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
#if defined(STM32F446xx)
if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_CFGR_SWS_HSI) ||\
@@ -3132,15 +3438,15 @@
/* Get Start Tick*/
tickstart = HAL_GetTick();
- /* Wait till HSI is ready */
+ /* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
- }
-
+ }
+ }
+
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
}
@@ -3151,15 +3457,15 @@
/* Get Start Tick*/
tickstart = HAL_GetTick();
-
- /* Wait till HSI is ready */
+
+ /* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
- }
+ }
+ }
}
}
}
@@ -3174,60 +3480,70 @@
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
-
+
/* Get Start Tick*/
tickstart = HAL_GetTick();
-
+
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
+ }
}
}
else
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
-
+
/* Get Start Tick*/
tickstart = HAL_GetTick();
-
- /* Wait till LSI is ready */
+
+ /* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
- }
+ }
+ }
}
}
/*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
{
+ FlagStatus pwrclkchanged = RESET;
+
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
-
- /* Enable Power Clock*/
- __HAL_RCC_PWR_CLK_ENABLE();
-
- /* Enable write access to Backup domain */
- PWR->CR |= PWR_CR_DBP;
-
- /* Wait for Backup domain Write protection disable */
- tickstart = HAL_GetTick();
-
- while((PWR->CR & PWR_CR_DBP) == RESET)
+
+ /* Update LSE configuration in Backup Domain control register */
+ /* Requires to enable write access to Backup Domain of necessary */
+ if(__HAL_RCC_PWR_IS_CLK_DISABLED())
+ {
+ __HAL_RCC_PWR_CLK_ENABLE();
+ pwrclkchanged = SET;
+ }
+
+ if(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
{
- if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
+ /* Enable write access to Backup domain */
+ SET_BIT(PWR->CR, PWR_CR_DBP);
+
+ /* Wait for Backup domain Write protection disable */
+ tickstart = HAL_GetTick();
+
+ while(HAL_IS_BIT_CLR(PWR->CR, PWR_CR_DBP))
{
- return HAL_TIMEOUT;
+ if((HAL_GetTick() - tickstart) > RCC_DBP_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
}
}
-
+
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
/* Check the LSE State */
@@ -3235,8 +3551,8 @@
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
-
- /* Wait till LSE is ready */
+
+ /* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
@@ -3249,16 +3565,22 @@
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
-
- /* Wait till LSE is ready */
+
+ /* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
+ }
}
}
+
+ /* Restore clock configuration if changed */
+ if(pwrclkchanged == SET)
+ {
+ __HAL_RCC_PWR_CLK_DISABLE();
+ }
}
/*-------------------------------- PLL Configuration -----------------------*/
/* Check the parameters */
@@ -3267,7 +3589,7 @@
{
/* Check if the PLL is used as system clock or not */
if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_CFGR_SWS_PLL)
- {
+ {
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
{
/* Check the parameters */
@@ -3277,21 +3599,21 @@
assert_param(IS_RCC_PLLP_VALUE(RCC_OscInitStruct->PLL.PLLP));
assert_param(IS_RCC_PLLQ_VALUE(RCC_OscInitStruct->PLL.PLLQ));
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
-
+
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
-
+
/* Get Start Tick*/
tickstart = HAL_GetTick();
-
- /* Wait till PLL is ready */
+
+ /* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
}
- }
+ }
/* Configure the main PLL clock source, multiplication and division factors. */
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
@@ -3306,25 +3628,25 @@
/* Get Start Tick*/
tickstart = HAL_GetTick();
-
- /* Wait till PLL is ready */
+
+ /* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
+ }
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
-
+
/* Get Start Tick*/
tickstart = HAL_GetTick();
-
- /* Wait till PLL is ready */
+
+ /* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
@@ -3343,9 +3665,9 @@
}
/**
- * @brief Configures the RCC_OscInitStruct according to the internal
+ * @brief Configures the RCC_OscInitStruct according to the internal
* RCC configuration registers.
- * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that will be configured.
+ * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that will be configured.
*
* @note This function is only available in case of STM32F410xx/STM32F446xx/STM32F469xx/STM32F479xx/STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx devices.
* @note This function add the PLL/PLLR factor management
@@ -3355,7 +3677,7 @@
{
/* Set all possible values for the Oscillator type parameter ---------------*/
RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
-
+
/* Get the HSE configuration -----------------------------------------------*/
if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
{
@@ -3369,7 +3691,7 @@
{
RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
}
-
+
/* Get the HSI configuration -----------------------------------------------*/
if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
{
@@ -3379,9 +3701,9 @@
{
RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
}
-
- RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
-
+
+ RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
+
/* Get the LSE configuration -----------------------------------------------*/
if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
{
@@ -3395,7 +3717,7 @@
{
RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
}
-
+
/* Get the LSI configuration -----------------------------------------------*/
if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
{
@@ -3405,7 +3727,7 @@
{
RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
}
-
+
/* Get the PLL configuration -----------------------------------------------*/
if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
{
@@ -3417,10 +3739,10 @@
}
RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
- RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
- RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1U) >> POSITION_VAL(RCC_PLLCFGR_PLLP));
- RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ));
- RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR));
+ RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+ RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1U) >> RCC_PLLCFGR_PLLP_Pos);
+ RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos);
+ RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> RCC_PLLCFGR_PLLR_Pos);
}
#endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc_ex.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rcc_ex.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_rcc_ex.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief Header file of RCC HAL Extension module.
******************************************************************************
* @attention
@@ -310,6 +308,7 @@
#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
+
/**
* @brief PLLI2S Clock structure definition
*/
@@ -734,6 +733,7 @@
/**
* @}
*/
+
#endif /* STM32F446xx */
#if defined(STM32F413xx) || defined(STM32F423xx)
@@ -871,6 +871,7 @@
#endif /* STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
+
/** @defgroup RCCEx_I2S_APB_Clock_Source RCC I2S APB Clock Source
* @{
*/
@@ -5720,32 +5721,32 @@
defined(STM32F412Rx) || defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
* @note This function must be used only when the main PLL is disabled.
- * @param __RCC_PLLSource__: specifies the PLL entry clock source.
+ * @param __RCC_PLLSource__ specifies the PLL entry clock source.
* This parameter can be one of the following values:
* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
* @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
- * @param __PLLM__: specifies the division factor for PLL VCO input clock
+ * @param __PLLM__ specifies the division factor for PLL VCO input clock
* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
* @note You have to set the PLLM parameter correctly to ensure that the VCO input
* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
* of 2 MHz to limit PLL jitter.
- * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
+ * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock
* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
* @note You have to set the PLLN parameter correctly to ensure that the VCO
* output frequency is between 100 and 432 MHz.
*
- * @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
+ * @param __PLLP__ specifies the division factor for main system clock (SYSCLK)
* This parameter must be a number in the range {2, 4, 6, or 8}.
*
- * @param __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks
+ * @param __PLLQ__ specifies the division factor for OTG FS, SDIO and RNG clocks
* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
* @note If the USB OTG FS is used in your application, you have to set the
* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
* the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
* correctly.
*
- * @param __PLLR__: PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.
+ * @param __PLLR__ PLL division factor for I2S, SAI, SYSTEM, SPDIFRX clocks.
* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
* @note This parameter is only available in STM32F446xx/STM32F469xx/STM32F479xx/
STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/STM32F413xx/STM32F423xx devices.
@@ -5753,33 +5754,33 @@
*/
#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \
(RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__) | \
- ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
- ((((__PLLP__) >> 1U) -1U) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \
- ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ)) | \
- ((__PLLR__) << POSITION_VAL(RCC_PLLCFGR_PLLR))))
+ ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \
+ ((((__PLLP__) >> 1U) -1U) << RCC_PLLCFGR_PLLP_Pos) | \
+ ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos) | \
+ ((__PLLR__) << RCC_PLLCFGR_PLLR_Pos)))
#else
/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
* @note This function must be used only when the main PLL is disabled.
- * @param __RCC_PLLSource__: specifies the PLL entry clock source.
+ * @param __RCC_PLLSource__ specifies the PLL entry clock source.
* This parameter can be one of the following values:
* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
* @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
- * @param __PLLM__: specifies the division factor for PLL VCO input clock
+ * @param __PLLM__ specifies the division factor for PLL VCO input clock
* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
* @note You have to set the PLLM parameter correctly to ensure that the VCO input
* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
* of 2 MHz to limit PLL jitter.
- * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
+ * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock
* This parameter must be a number between Min_Data = 50 and Max_Data = 432
* Except for STM32F411xE devices where Min_Data = 192.
* @note You have to set the PLLN parameter correctly to ensure that the VCO
* output frequency is between 100 and 432 MHz, Except for STM32F411xE devices
* where frequency is between 192 and 432 MHz.
- * @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
+ * @param __PLLP__ specifies the division factor for main system clock (SYSCLK)
* This parameter must be a number in the range {2, 4, 6, or 8}.
*
- * @param __PLLQ__: specifies the division factor for OTG FS, SDIO and RNG clocks
+ * @param __PLLQ__ specifies the division factor for OTG FS, SDIO and RNG clocks
* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
* @note If the USB OTG FS is used in your application, you have to set the
* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
@@ -5789,9 +5790,9 @@
*/
#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \
(RCC->PLLCFGR = (0x20000000U | (__RCC_PLLSource__) | (__PLLM__)| \
- ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
- ((((__PLLP__) >> 1U) -1U) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \
- ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))
+ ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \
+ ((((__PLLP__) >> 1U) -1U) << RCC_PLLCFGR_PLLP_Pos) | \
+ ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos)))
#endif /* STM32F410xx || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx */
/*----------------------------------------------------------------------------*/
@@ -5816,84 +5817,84 @@
* @note This macro must be used only when the PLLI2S is disabled.
* @note PLLI2S clock source is common with the main PLL (configured in
* HAL_RCC_ClockConfig() API).
- * @param __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock
+ * @param __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock
* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
* @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
* of 1 MHz to limit PLLI2S jitter.
*
- * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
+ * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock
* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
*
- * @param __PLLI2SP__: specifies division factor for SPDIFRX Clock.
+ * @param __PLLI2SP__ specifies division factor for SPDIFRX Clock.
* This parameter must be a number in the range {2, 4, 6, or 8}.
* @note the PLLI2SP parameter is only available with STM32F446xx Devices
*
- * @param __PLLI2SR__: specifies the division factor for I2S clock
+ * @param __PLLI2SR__ specifies the division factor for I2S clock
* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
* on the I2S clock frequency.
*
- * @param __PLLI2SQ__: specifies the division factor for SAI clock
+ * @param __PLLI2SQ__ specifies the division factor for SAI clock
* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
*/
#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \
(RCC->PLLI2SCFGR = ((__PLLI2SM__) |\
- ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\
- ((((__PLLI2SP__) >> 1U) -1U) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) |\
- ((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)) |\
- ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
+ ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\
+ ((((__PLLI2SP__) >> 1U) -1U) << RCC_PLLI2SCFGR_PLLI2SP_Pos) |\
+ ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) |\
+ ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)))
#elif defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
defined(STM32F413xx) || defined(STM32F423xx)
/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
* @note This macro must be used only when the PLLI2S is disabled.
* @note PLLI2S clock source is common with the main PLL (configured in
* HAL_RCC_ClockConfig() API).
- * @param __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock
+ * @param __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock
* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
* @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
* of 1 MHz to limit PLLI2S jitter.
*
- * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
+ * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock
* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
*
- * @param __PLLI2SR__: specifies the division factor for I2S clock
+ * @param __PLLI2SR__ specifies the division factor for I2S clock
* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
* on the I2S clock frequency.
*
- * @param __PLLI2SQ__: specifies the division factor for SAI clock
+ * @param __PLLI2SQ__ specifies the division factor for SAI clock
* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
*/
#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) \
(RCC->PLLI2SCFGR = ((__PLLI2SM__) |\
- ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\
- ((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)) |\
- ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
+ ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\
+ ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) |\
+ ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)))
#else
/** @brief Macro to configure the PLLI2S clock multiplication and division factors .
* @note This macro must be used only when the PLLI2S is disabled.
* @note PLLI2S clock source is common with the main PLL (configured in
* HAL_RCC_ClockConfig() API).
- * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
+ * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock
* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
*
- * @param __PLLI2SR__: specifies the division factor for I2S clock
+ * @param __PLLI2SR__ specifies the division factor for I2S clock
* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
* on the I2S clock frequency.
*
*/
#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SR__) \
- (RCC->PLLI2SCFGR = (((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\
- ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
+ (RCC->PLLI2SCFGR = (((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\
+ ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)))
#endif /* STM32F446xx */
#if defined(STM32F411xE)
@@ -5902,24 +5903,24 @@
* @note This macro must be used only when the PLLI2S is disabled.
* @note PLLI2S clock source is common with the main PLL (configured in
* HAL_RCC_ClockConfig() API).
- * @param __PLLI2SM__: specifies the division factor for PLLI2S VCO input clock
+ * @param __PLLI2SM__ specifies the division factor for PLLI2S VCO input clock
* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
* @note The PLLI2SM parameter is only used with STM32F411xE/STM32F410xx Devices
* @note You have to set the PLLI2SM parameter correctly to ensure that the VCO input
* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
* of 2 MHz to limit PLLI2S jitter.
- * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock
+ * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock
* This parameter must be a number between Min_Data = 192 and Max_Data = 432.
* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
* output frequency is between Min_Data = 192 and Max_Data = 432 MHz.
- * @param __PLLI2SR__: specifies the division factor for I2S clock
+ * @param __PLLI2SR__ specifies the division factor for I2S clock
* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
* on the I2S clock frequency.
*/
#define __HAL_RCC_PLLI2S_I2SCLK_CONFIG(__PLLI2SM__, __PLLI2SN__, __PLLI2SR__) (RCC->PLLI2SCFGR = ((__PLLI2SM__) |\
- ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\
- ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR))))
+ ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\
+ ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos)))
#endif /* STM32F411xE */
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
@@ -5927,15 +5928,15 @@
* @note This macro must be used only when the PLLI2S is disabled.
* @note PLLI2S clock source is common with the main PLL (configured in
* HAL_RCC_ClockConfig() API)
- * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
+ * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock.
* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
- * @param __PLLI2SQ__: specifies the division factor for SAI1 clock.
+ * @param __PLLI2SQ__ specifies the division factor for SAI1 clock.
* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
* @note the PLLI2SQ parameter is only available with STM32F427xx/437xx/429xx/439xx/469xx/479xx
* Devices and can be configured using the __HAL_RCC_PLLI2S_PLLSAICLK_CONFIG() macro
- * @param __PLLI2SR__: specifies the division factor for I2S clock
+ * @param __PLLI2SR__ specifies the division factor for I2S clock
* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
* on the I2S clock frequency.
@@ -5958,79 +5959,79 @@
#if defined(STM32F446xx)
/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
*
- * @param __PLLSAIM__: specifies the division factor for PLLSAI VCO input clock
+ * @param __PLLSAIM__ specifies the division factor for PLLSAI VCO input clock
* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
* @note You have to set the PLLSAIM parameter correctly to ensure that the VCO input
* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
* of 1 MHz to limit PLLI2S jitter.
* @note The PLLSAIM parameter is only used with STM32F446xx Devices
*
- * @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
+ * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock.
* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
*
- * @param __PLLSAIP__: specifies division factor for OTG FS, SDIO and RNG clocks.
+ * @param __PLLSAIP__ specifies division factor for OTG FS, SDIO and RNG clocks.
* This parameter must be a number in the range {2, 4, 6, or 8}.
* @note the PLLSAIP parameter is only available with STM32F446xx Devices
*
- * @param __PLLSAIQ__: specifies the division factor for SAI clock
+ * @param __PLLSAIQ__ specifies the division factor for SAI clock
* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
*
- * @param __PLLSAIR__: specifies the division factor for LTDC clock
+ * @param __PLLSAIR__ specifies the division factor for LTDC clock
* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
* @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices
*/
#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIM__, __PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
(RCC->PLLSAICFGR = ((__PLLSAIM__) | \
- ((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) | \
- ((((__PLLSAIP__) >> 1U) -1U) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) | \
- ((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ))))
+ ((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) | \
+ ((((__PLLSAIP__) >> 1U) -1U) << RCC_PLLSAICFGR_PLLSAIP_Pos) | \
+ ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos)))
#endif /* STM32F446xx */
#if defined(STM32F469xx) || defined(STM32F479xx)
/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
*
- * @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
+ * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock.
* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
*
- * @param __PLLSAIP__: specifies division factor for SDIO and CLK48 clocks.
+ * @param __PLLSAIP__ specifies division factor for SDIO and CLK48 clocks.
* This parameter must be a number in the range {2, 4, 6, or 8}.
*
- * @param __PLLSAIQ__: specifies the division factor for SAI clock
+ * @param __PLLSAIQ__ specifies the division factor for SAI clock
* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
*
- * @param __PLLSAIR__: specifies the division factor for LTDC clock
+ * @param __PLLSAIR__ specifies the division factor for LTDC clock
* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
*/
#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
- (RCC->PLLSAICFGR = (((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) |\
- ((((__PLLSAIP__) >> 1U) -1U) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) |\
- ((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)) |\
- ((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR))))
+ (RCC->PLLSAICFGR = (((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) |\
+ ((((__PLLSAIP__) >> 1U) -1U) << RCC_PLLSAICFGR_PLLSAIP_Pos) |\
+ ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos) |\
+ ((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos)))
#endif /* STM32F469xx || STM32F479xx */
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
*
- * @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
+ * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock.
* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
*
- * @param __PLLSAIQ__: specifies the division factor for SAI clock
+ * @param __PLLSAIQ__ specifies the division factor for SAI clock
* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
*
- * @param __PLLSAIR__: specifies the division factor for LTDC clock
+ * @param __PLLSAIR__ specifies the division factor for LTDC clock
* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
* @note the PLLI2SR parameter is only available with STM32F427/437/429/439xx Devices
*/
#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIQ__, __PLLSAIR__) \
- (RCC->PLLSAICFGR = (((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) | \
- ((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)) | \
- ((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR))))
+ (RCC->PLLSAICFGR = (((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) | \
+ ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos) | \
+ ((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos)))
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx */
#endif /* STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */
@@ -6040,14 +6041,14 @@
#if defined(STM32F413xx) || defined(STM32F423xx)
/** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
* @note This function must be called before enabling the PLLI2S.
- * @param __PLLI2SDivR__: specifies the PLLI2S division factor for SAI1 clock.
+ * @param __PLLI2SDivR__ specifies the PLLI2S division factor for SAI1 clock.
* This parameter must be a number between 1 and 32.
* SAI1 clock frequency = f(PLLI2SR) / __PLLI2SDivR__
*/
#define __HAL_RCC_PLLI2S_PLLSAICLKDIVR_CONFIG(__PLLI2SDivR__) (MODIFY_REG(RCC->DCKCFGR, RCC_DCKCFGR_PLLI2SDIVR, (__PLLI2SDivR__)-1U))
/** @brief Macro to configure the SAI clock Divider coming from PLL.
- * @param __PLLDivR__: specifies the PLL division factor for SAI1 clock.
+ * @param __PLLDivR__ specifies the PLL division factor for SAI1 clock.
* This parameter must be a number between 1 and 32.
* SAI1 clock frequency = f(PLLR) / __PLLDivR__
*/
@@ -6058,7 +6059,7 @@
defined(STM32F469xx) || defined(STM32F479xx)
/** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
* @note This function must be called before enabling the PLLI2S.
- * @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock.
+ * @param __PLLI2SDivQ__ specifies the PLLI2S division factor for SAI1 clock.
* This parameter must be a number between 1 and 32.
* SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__
*/
@@ -6066,7 +6067,7 @@
/** @brief Macro to configure the SAI clock Divider coming from PLLSAI.
* @note This function must be called before enabling the PLLSAI.
- * @param __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock .
+ * @param __PLLSAIDivQ__ specifies the PLLSAI division factor for SAI1 clock .
* This parameter must be a number between Min_Data = 1 and Max_Data = 32.
* SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__
*/
@@ -6078,7 +6079,7 @@
*
* @note The LTDC peripheral is only available with STM32F427/437/429/439/469/479xx Devices.
* @note This function must be called before enabling the PLLSAI.
- * @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock .
+ * @param __PLLSAIDivR__ specifies the PLLSAI division factor for LTDC clock .
* This parameter must be a number between Min_Data = 2 and Max_Data = 16.
* LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__
*/
@@ -6093,7 +6094,7 @@
defined(STM32F479xx)
/** @brief Macro to configure the I2S clock source (I2SCLK).
* @note This function must be called before enabling the I2S APB clock.
- * @param __SOURCE__: specifies the I2S clock source.
+ * @param __SOURCE__ specifies the I2S clock source.
* This parameter can be one of the following values:
* @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
* @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
@@ -6117,7 +6118,7 @@
* @note The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices.
* @note This function must be called before enabling PLLSAI, PLLI2S and
* the SAI clock.
- * @param __SOURCE__: specifies the SAI Block A clock source.
+ * @param __SOURCE__ specifies the SAI Block A clock source.
* This parameter can be one of the following values:
* @arg RCC_SAIACLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
* as SAI1 Block A clock.
@@ -6132,7 +6133,7 @@
* @note The SAI peripheral is only available with STM32F427/437/429/439/469/479xx Devices.
* @note This function must be called before enabling PLLSAI, PLLI2S and
* the SAI clock.
- * @param __SOURCE__: specifies the SAI Block B clock source.
+ * @param __SOURCE__ specifies the SAI Block B clock source.
* This parameter can be one of the following values:
* @arg RCC_SAIBCLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
* as SAI1 Block B clock.
@@ -6149,7 +6150,7 @@
* @note This configuration is only available with STM32F446xx Devices.
* @note This function must be called before enabling PLL, PLLSAI, PLLI2S and
* the SAI clock.
- * @param __SOURCE__: specifies the SAI1 clock source.
+ * @param __SOURCE__ specifies the SAI1 clock source.
* This parameter can be one of the following values:
* @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI1 clock.
* @arg RCC_SAI1CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI1 clock.
@@ -6172,7 +6173,7 @@
* @note This configuration is only available with STM32F446xx Devices.
* @note This function must be called before enabling PLL, PLLSAI, PLLI2S and
* the SAI clock.
- * @param __SOURCE__: specifies the SAI2 clock source.
+ * @param __SOURCE__ specifies the SAI2 clock source.
* This parameter can be one of the following values:
* @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used as SAI2 clock.
* @arg RCC_SAI2CLKSOURCE_PLLSAI: PLLISAI_Q clock divided by PLLSAIDIVQ used as SAI2 clock.
@@ -6193,7 +6194,7 @@
/** @brief Macro to configure I2S APB1 clock source selection.
* @note This function must be called before enabling PLL, PLLI2S and the I2S clock.
- * @param __SOURCE__: specifies the I2S APB1 clock source.
+ * @param __SOURCE__ specifies the I2S APB1 clock source.
* This parameter can be one of the following values:
* @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
* @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB1 clock.
@@ -6213,7 +6214,7 @@
/** @brief Macro to configure I2S APB2 clock source selection.
* @note This function must be called before enabling PLL, PLLI2S and the I2S clock.
- * @param __SOURCE__: specifies the SAI Block A clock source.
+ * @param __SOURCE__ specifies the SAI Block A clock source.
* This parameter can be one of the following values:
* @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR used as I2S clock.
* @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as I2S APB2 clock.
@@ -6232,7 +6233,7 @@
#define __HAL_RCC_GET_I2S_APB2_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S2SRC))
/** @brief Macro to configure the CEC clock.
- * @param __SOURCE__: specifies the CEC clock source.
+ * @param __SOURCE__ specifies the CEC clock source.
* This parameter can be one of the following values:
* @arg RCC_CECCLKSOURCE_HSI: HSI selected as CEC clock
* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
@@ -6247,7 +6248,7 @@
#define __HAL_RCC_GET_CEC_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL))
/** @brief Macro to configure the FMPI2C1 clock.
- * @param __SOURCE__: specifies the FMPI2C1 clock source.
+ * @param __SOURCE__ specifies the FMPI2C1 clock source.
* This parameter can be one of the following values:
* @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
@@ -6264,7 +6265,7 @@
#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
/** @brief Macro to configure the CLK48 clock.
- * @param __SOURCE__: specifies the CLK48 clock source.
+ * @param __SOURCE__ specifies the CLK48 clock source.
* This parameter can be one of the following values:
* @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
* @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock.
@@ -6279,7 +6280,7 @@
#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))
/** @brief Macro to configure the SDIO clock.
- * @param __SOURCE__: specifies the SDIO clock source.
+ * @param __SOURCE__ specifies the SDIO clock source.
* This parameter can be one of the following values:
* @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
@@ -6294,7 +6295,7 @@
#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_SDIOSEL))
/** @brief Macro to configure the SPDIFRX clock.
- * @param __SOURCE__: specifies the SPDIFRX clock source.
+ * @param __SOURCE__ specifies the SPDIFRX clock source.
* This parameter can be one of the following values:
* @arg RCC_SPDIFRXCLKSOURCE_PLLR: PLL VCO Output divided by PLLR used as SPDIFRX clock.
* @arg RCC_SPDIFRXCLKSOURCE_PLLI2SP: PLLI2S VCO Output divided by PLLI2SP used as SPDIFRX clock.
@@ -6312,7 +6313,7 @@
#if defined(STM32F469xx) || defined(STM32F479xx)
/** @brief Macro to configure the CLK48 clock.
- * @param __SOURCE__: specifies the CLK48 clock source.
+ * @param __SOURCE__ specifies the CLK48 clock source.
* This parameter can be one of the following values:
* @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
* @arg RCC_CLK48CLKSOURCE_PLLSAIP: PLLSAI VCO Output divided by PLLSAIP used as CLK48 clock.
@@ -6327,7 +6328,7 @@
#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_CK48MSEL))
/** @brief Macro to configure the SDIO clock.
- * @param __SOURCE__: specifies the SDIO clock source.
+ * @param __SOURCE__ specifies the SDIO clock source.
* This parameter can be one of the following values:
* @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
@@ -6342,7 +6343,7 @@
#define __HAL_RCC_GET_SDIO_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SDIOSEL))
/** @brief Macro to configure the DSI clock.
- * @param __SOURCE__: specifies the DSI clock source.
+ * @param __SOURCE__ specifies the DSI clock source.
* This parameter can be one of the following values:
* @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock.
* @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock.
@@ -6361,7 +6362,7 @@
#if defined(STM32F412Zx) || defined(STM32F412Vx) || defined(STM32F412Rx) || defined(STM32F412Cx) ||\
defined(STM32F413xx) || defined(STM32F423xx)
/** @brief Macro to configure the DFSDM1 clock.
- * @param __DFSDM1_CLKSOURCE__: specifies the DFSDM1 clock source.
+ * @param __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source.
* This parameter can be one of the following values:
* @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock.
* @arg RCC_DFSDM1CLKSOURCE_SYSCLK: System clock used as kernal clock.
@@ -6379,7 +6380,7 @@
/** @brief Macro to configure DFSDM1 Audio clock source selection.
* @note This configuration is only available with STM32F412Zx/STM32F412Vx/STM32F412Rx/STM32F412Cx/
STM32F413xx/STM32F423xx Devices.
- * @param __SOURCE__: specifies the DFSDM1 Audio clock source.
+ * @param __SOURCE__ specifies the DFSDM1 Audio clock source.
* This parameter can be one of the following values:
* @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock
* @arg RCC_DFSDM1AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock
@@ -6397,7 +6398,7 @@
#if defined(STM32F413xx) || defined(STM32F423xx)
/** @brief Macro to configure the DFSDM2 clock.
- * @param __DFSDM2_CLKSOURCE__: specifies the DFSDM1 clock source.
+ * @param __DFSDM2_CLKSOURCE__ specifies the DFSDM1 clock source.
* This parameter can be one of the following values:
* @arg RCC_DFSDM2CLKSOURCE_PCLK2: PCLK2 clock used as kernel clock.
* @arg RCC_DFSDM2CLKSOURCE_SYSCLK: System clock used as kernal clock.
@@ -6414,7 +6415,7 @@
/** @brief Macro to configure DFSDM1 Audio clock source selection.
* @note This configuration is only available with STM32F413xx/STM32F423xx Devices.
- * @param __SOURCE__: specifies the DFSDM2 Audio clock source.
+ * @param __SOURCE__ specifies the DFSDM2 Audio clock source.
* This parameter can be one of the following values:
* @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S1: CK_I2S_PCLK1 selected as audio clock
* @arg RCC_DFSDM2AUDIOCLKSOURCE_I2S2: CK_I2S_PCLK2 selected as audio clock
@@ -6433,7 +6434,7 @@
* @note The SAI peripheral is only available with STM32F413xx/STM32F423xx Devices.
* @note This function must be called before enabling PLLSAI, PLLI2S and
* the SAI clock.
- * @param __SOURCE__: specifies the SAI Block A clock source.
+ * @param __SOURCE__ specifies the SAI Block A clock source.
* This parameter can be one of the following values:
* @arg RCC_SAIACLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock.
* @arg RCC_SAIACLKSOURCE_EXT: External clock mapped on the I2S_CKIN pinused as SAI1 Block A clock.
@@ -6456,7 +6457,7 @@
* @note The SAI peripheral is only available with STM32F413xx/STM32F423xx Devices.
* @note This function must be called before enabling PLLSAI, PLLI2S and
* the SAI clock.
- * @param __SOURCE__: specifies the SAI Block B clock source.
+ * @param __SOURCE__ specifies the SAI Block B clock source.
* This parameter can be one of the following values:
* @arg RCC_SAIBCLKSOURCE_PLLI2SR: PLLI2S_R clock divided (R2) used as SAI1 Block A clock.
* @arg RCC_SAIBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin used as SAI1 Block A clock.
@@ -6476,7 +6477,7 @@
#define __HAL_RCC_GET_SAI_BLOCKB_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_SAI1BSRC))
/** @brief Macro to configure the LPTIM1 clock.
- * @param __SOURCE__: specifies the LPTIM1 clock source.
+ * @param __SOURCE__ specifies the LPTIM1 clock source.
* This parameter can be one of the following values:
* @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock
* @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
@@ -6496,7 +6497,7 @@
#endif /* STM32F413xx || STM32F423xx */
/** @brief Macro to configure I2S APB1 clock source selection.
- * @param __SOURCE__: specifies the I2S APB1 clock source.
+ * @param __SOURCE__ specifies the I2S APB1 clock source.
* This parameter can be one of the following values:
* @arg RCC_I2SAPB1CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
* @arg RCC_I2SAPB1CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
@@ -6515,7 +6516,7 @@
#define __HAL_RCC_GET_I2S_APB1_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2S1SRC))
/** @brief Macro to configure I2S APB2 clock source selection.
- * @param __SOURCE__: specifies the I2S APB2 clock source.
+ * @param __SOURCE__ specifies the I2S APB2 clock source.
* This parameter can be one of the following values:
* @arg RCC_I2SAPB2CLKSOURCE_PLLI2S: PLLI2S VCO output clock divided by PLLI2SR.
* @arg RCC_I2SAPB2CLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
@@ -6535,7 +6536,7 @@
/** @brief Macro to configure the PLL I2S clock source (PLLI2SCLK).
* @note This macro must be called before enabling the I2S APB clock.
- * @param __SOURCE__: specifies the I2S clock source.
+ * @param __SOURCE__ specifies the I2S clock source.
* This parameter can be one of the following values:
* @arg RCC_PLLI2SCLKSOURCE_PLLSRC: HSI or HSE depending from PLL source Clock.
* @arg RCC_PLLI2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
@@ -6544,7 +6545,7 @@
#define __HAL_RCC_PLL_I2S_CONFIG(__SOURCE__) (*(__IO uint32_t *) RCC_PLLI2SCFGR_PLLI2SSRC_BB = (__SOURCE__))
/** @brief Macro to configure the FMPI2C1 clock.
- * @param __SOURCE__: specifies the FMPI2C1 clock source.
+ * @param __SOURCE__ specifies the FMPI2C1 clock source.
* This parameter can be one of the following values:
* @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
@@ -6561,7 +6562,7 @@
#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
/** @brief Macro to configure the CLK48 clock.
- * @param __SOURCE__: specifies the CLK48 clock source.
+ * @param __SOURCE__ specifies the CLK48 clock source.
* This parameter can be one of the following values:
* @arg RCC_CLK48CLKSOURCE_PLLQ: PLL VCO Output divided by PLLQ used as CLK48 clock.
* @arg RCC_CLK48CLKSOURCE_PLLI2SQ: PLLI2S VCO Output divided by PLLI2SQ used as CLK48 clock.
@@ -6576,7 +6577,7 @@
#define __HAL_RCC_GET_CLK48_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL))
/** @brief Macro to configure the SDIO clock.
- * @param __SOURCE__: specifies the SDIO clock source.
+ * @param __SOURCE__ specifies the SDIO clock source.
* This parameter can be one of the following values:
* @arg RCC_SDIOCLKSOURCE_CLK48: CLK48 output used as SDIO clock.
* @arg RCC_SDIOCLKSOURCE_SYSCLK: System clock output used as SDIO clock.
@@ -6594,7 +6595,7 @@
#if defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx)
/** @brief Macro to configure I2S clock source selection.
- * @param __SOURCE__: specifies the I2S clock source.
+ * @param __SOURCE__ specifies the I2S clock source.
* This parameter can be one of the following values:
* @arg RCC_I2SAPBCLKSOURCE_PLLR: PLL VCO output clock divided by PLLR.
* @arg RCC_I2SAPBCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin.
@@ -6611,7 +6612,7 @@
#define __HAL_RCC_GET_I2S_SOURCE() (READ_BIT(RCC->DCKCFGR, RCC_DCKCFGR_I2SSRC))
/** @brief Macro to configure the FMPI2C1 clock.
- * @param __SOURCE__: specifies the FMPI2C1 clock source.
+ * @param __SOURCE__ specifies the FMPI2C1 clock source.
* This parameter can be one of the following values:
* @arg RCC_FMPI2C1CLKSOURCE_PCLK1: PCLK1 selected as FMPI2C1 clock
* @arg RCC_FMPI2C1CLKSOURCE_SYSCLK: SYS clock selected as FMPI2C1 clock
@@ -6628,7 +6629,7 @@
#define __HAL_RCC_GET_FMPI2C1_SOURCE() (READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_FMPI2C1SEL))
/** @brief Macro to configure the LPTIM1 clock.
- * @param __SOURCE__: specifies the LPTIM1 clock source.
+ * @param __SOURCE__ specifies the LPTIM1 clock source.
* This parameter can be one of the following values:
* @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK1 selected as LPTIM1 clock
* @arg RCC_LPTIM1CLKSOURCE_HSI: HSI clock selected as LPTIM1 clock
@@ -6654,7 +6655,7 @@
defined(STM32F412Cx) || defined(STM32F413xx) || defined(STM32F423xx)
/** @brief Macro to configure the Timers clocks prescalers
* @note This feature is only available with STM32F429x/439x Devices.
- * @param __PRESC__ : specifies the Timers clocks prescalers selection
+ * @param __PRESC__ specifies the Timers clocks prescalers selection
* This parameter can be one of the following values:
* @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
* equal to HPRE if PPREx is corresponding to division by 1 or 2,
@@ -6734,6 +6735,14 @@
defined(STM32F423xx)
void HAL_RCCEx_SelectLSEMode(uint8_t Mode);
#endif /* STM32F410xx || STM32F411xE || STM32F446xx || STM32F469xx || STM32F479xx || STM32F412Zx || STM32F412Vx || STM32F412Rx || STM32F412Cx || STM32F413xx || STM32F423xx */
+#if defined(RCC_PLLI2S_SUPPORT)
+HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit);
+HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void);
+#endif /* RCC_PLLI2S_SUPPORT */
+#if defined(RCC_PLLSAI_SUPPORT)
+HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit);
+HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void);
+#endif /* RCC_PLLSAI_SUPPORT */
/**
* @}
*/
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rng.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rng.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_rng.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief RNG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Random Number Generator (RNG) peripheral:
@@ -116,7 +114,7 @@
/**
* @brief Initializes the RNG peripheral and creates the associated handle.
- * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval HAL status
*/
@@ -127,9 +125,7 @@
{
return HAL_ERROR;
}
-
- __HAL_LOCK(hrng);
-
+
if(hrng->State == HAL_RNG_STATE_RESET)
{
/* Allocate lock resource and initialize it */
@@ -146,16 +142,14 @@
/* Initialize the RNG state */
hrng->State = HAL_RNG_STATE_READY;
-
- __HAL_UNLOCK(hrng);
-
+
/* Return function status */
return HAL_OK;
}
/**
* @brief DeInitializes the RNG peripheral.
- * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval HAL status
*/
@@ -187,7 +181,7 @@
/**
* @brief Initializes the RNG MSP.
- * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval None
*/
@@ -202,7 +196,7 @@
/**
* @brief DeInitializes the RNG MSP.
- * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval None
*/
@@ -239,9 +233,9 @@
* @brief Generates a 32-bit random number.
* @note Each time the random number data is read the RNG_FLAG_DRDY flag
* is automatically cleared.
- * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
- * @param random32bit: pointer to generated random number variable if successful.
+ * @param random32bit pointer to generated random number variable if successful.
* @retval HAL status
*/
@@ -295,7 +289,7 @@
/**
* @brief Generates a 32-bit random number in interrupt mode.
- * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval HAL status
*/
@@ -345,7 +339,7 @@
* the RNG peripheral to reinitialize and restart the RNG.
* @note User-written HAL_RNG_ErrorCallback() API is called once whether SEIS
* or CEIS are set.
- * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval None
@@ -388,7 +382,7 @@
/**
* @brief Returns generated random number in polling mode (Obsolete)
* Use HAL_RNG_GenerateRandomNumber() API instead.
- * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval Random value
*/
@@ -407,7 +401,7 @@
/**
* @brief Returns a 32-bit random number with interrupt enabled (Obsolete),
* Use HAL_RNG_GenerateRandomNumber_IT() API instead.
- * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval 32-bit random number
*/
@@ -433,7 +427,7 @@
/**
* @brief Read latest generated random number.
- * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval random value
*/
@@ -444,9 +438,9 @@
/**
* @brief Data Ready callback in non-blocking mode.
- * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
- * @param random32bit: generated random number.
+ * @param random32bit generated random number.
* @retval None
*/
__weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit)
@@ -461,7 +455,7 @@
/**
* @brief RNG error callbacks.
- * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval None
*/
@@ -495,7 +489,7 @@
/**
* @brief Returns the RNG state.
- * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval HAL state
*/
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rng.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rng.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_rng.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief Header file of RNG HAL module.
******************************************************************************
* @attention
@@ -145,29 +143,29 @@
*/
/** @brief Reset RNG handle state
- * @param __HANDLE__: RNG Handle
+ * @param __HANDLE__ RNG Handle
* @retval None
*/
#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)
/**
* @brief Enables the RNG peripheral.
- * @param __HANDLE__: RNG Handle
+ * @param __HANDLE__ RNG Handle
* @retval None
*/
#define __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_RNGEN)
/**
* @brief Disables the RNG peripheral.
- * @param __HANDLE__: RNG Handle
+ * @param __HANDLE__ RNG Handle
* @retval None
*/
#define __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
/**
* @brief Check the selected RNG flag status.
- * @param __HANDLE__: RNG Handle
- * @param __FLAG__: RNG flag
+ * @param __HANDLE__ RNG Handle
+ * @param __FLAG__ RNG flag
* This parameter can be one of the following values:
* @arg RNG_FLAG_DRDY: Data ready
* @arg RNG_FLAG_CECS: Clock error current status
@@ -178,8 +176,8 @@
/**
* @brief Clears the selected RNG flag status.
- * @param __HANDLE__: RNG handle
- * @param __FLAG__: RNG flag to clear
+ * @param __HANDLE__ RNG handle
+ * @param __FLAG__ RNG flag to clear
* @note WARNING: This is a dummy macro for HAL code alignment,
* flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only.
* @retval None
@@ -190,22 +188,22 @@
/**
* @brief Enables the RNG interrupts.
- * @param __HANDLE__: RNG Handle
+ * @param __HANDLE__ RNG Handle
* @retval None
*/
#define __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_IE)
/**
* @brief Disables the RNG interrupts.
- * @param __HANDLE__: RNG Handle
+ * @param __HANDLE__ RNG Handle
* @retval None
*/
#define __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)
/**
* @brief Checks whether the specified RNG interrupt has occurred or not.
- * @param __HANDLE__: RNG Handle
- * @param __INTERRUPT__: specifies the RNG interrupt status flag to check.
+ * @param __HANDLE__ RNG Handle
+ * @param __INTERRUPT__ specifies the RNG interrupt status flag to check.
* This parameter can be one of the following values:
* @arg RNG_IT_DRDY: Data ready interrupt
* @arg RNG_IT_CEI: Clock error interrupt
@@ -216,8 +214,8 @@
/**
* @brief Clear the RNG interrupt status flags.
- * @param __HANDLE__: RNG Handle
- * @param __INTERRUPT__: specifies the RNG interrupt status flag to clear.
+ * @param __HANDLE__ RNG Handle
+ * @param __INTERRUPT__ specifies the RNG interrupt status flag to clear.
* This parameter can be one of the following values:
* @arg RNG_IT_CEI: Clock error interrupt
* @arg RNG_IT_SEI: Seed error interrupt
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rtc.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rtc.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_rtc.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief RTC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Real Time Clock (RTC) peripheral:
@@ -196,7 +194,7 @@
/**
* @brief Initializes the RTC peripheral
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval HAL status
*/
@@ -254,7 +252,21 @@
/* Exit Initialization mode */
hrtc->Instance->ISR &= (uint32_t)~RTC_ISR_INIT;
-
+
+ /* If CR_BYPSHAD bit = 0, wait for synchro else this check is not needed */
+ if((hrtc->Instance->CR & RTC_CR_BYPSHAD) == RESET)
+ {
+ if(HAL_RTC_WaitForSynchro(hrtc) != HAL_OK)
+ {
+ /* Enable the write protection for RTC registers */
+ __HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
+
+ hrtc->State = HAL_RTC_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+ }
+
hrtc->Instance->TAFCR &= (uint32_t)~RTC_TAFCR_ALARMOUTTYPE;
hrtc->Instance->TAFCR |= (uint32_t)(hrtc->Init.OutPutType);
@@ -270,7 +282,7 @@
/**
* @brief DeInitializes the RTC peripheral
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @note This function doesn't reset the RTC Backup Data registers.
* @retval HAL status
@@ -371,7 +383,7 @@
/**
* @brief Initializes the RTC MSP.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval None
*/
@@ -386,7 +398,7 @@
/**
* @brief DeInitializes the RTC MSP.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval None
*/
@@ -419,10 +431,10 @@
/**
* @brief Sets RTC current time.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
- * @param sTime: Pointer to Time structure
- * @param Format: Specifies the format of the entered parameters.
+ * @param sTime Pointer to Time structure
+ * @param Format Specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg RTC_FORMAT_BIN: Binary data format
* @arg RTC_FORMAT_BCD: BCD data format
@@ -544,10 +556,10 @@
/**
* @brief Gets RTC current time.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
- * @param sTime: Pointer to Time structure
- * @param Format: Specifies the format of the entered parameters.
+ * @param sTime Pointer to Time structure
+ * @param Format Specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg RTC_FORMAT_BIN: Binary data format
* @arg RTC_FORMAT_BCD: BCD data format
@@ -596,10 +608,10 @@
/**
* @brief Sets RTC current date.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
- * @param sDate: Pointer to date structure
- * @param Format: specifies the format of the entered parameters.
+ * @param sDate Pointer to date structure
+ * @param Format specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg RTC_FORMAT_BIN: Binary data format
* @arg RTC_FORMAT_BCD: BCD data format
@@ -638,9 +650,7 @@
else
{
assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year)));
- datetmpreg = RTC_Bcd2ToByte(sDate->Month);
assert_param(IS_RTC_MONTH(datetmpreg));
- datetmpreg = RTC_Bcd2ToByte(sDate->Date);
assert_param(IS_RTC_DATE(datetmpreg));
datetmpreg = ((((uint32_t)sDate->Year) << 16U) | \
@@ -705,10 +715,10 @@
/**
* @brief Gets RTC current date.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
- * @param sDate: Pointer to Date structure
- * @param Format: Specifies the format of the entered parameters.
+ * @param sDate Pointer to Date structure
+ * @param Format Specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg RTC_FORMAT_BIN: Binary data format
* @arg RTC_FORMAT_BCD: BCD data format
@@ -763,10 +773,10 @@
*/
/**
* @brief Sets the specified RTC Alarm.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
- * @param sAlarm: Pointer to Alarm structure
- * @param Format: Specifies the format of the entered parameters.
+ * @param sAlarm Pointer to Alarm structure
+ * @param Format Specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg RTC_FORMAT_BIN: Binary data format
* @arg RTC_FORMAT_BCD: BCD data format
@@ -949,10 +959,10 @@
/**
* @brief Sets the specified RTC Alarm with Interrupt
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
- * @param sAlarm: Pointer to Alarm structure
- * @param Format: Specifies the format of the entered parameters.
+ * @param sAlarm Pointer to Alarm structure
+ * @param Format Specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg RTC_FORMAT_BIN: Binary data format
* @arg RTC_FORMAT_BCD: BCD data format
@@ -1136,9 +1146,9 @@
/**
* @brief Deactivate the specified RTC Alarm
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
- * @param Alarm: Specifies the Alarm.
+ * @param Alarm Specifies the Alarm.
* This parameter can be one of the following values:
* @arg RTC_ALARM_A: AlarmA
* @arg RTC_ALARM_B: AlarmB
@@ -1228,14 +1238,14 @@
/**
* @brief Gets the RTC Alarm value and masks.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
- * @param sAlarm: Pointer to Date structure
- * @param Alarm: Specifies the Alarm.
+ * @param sAlarm Pointer to Date structure
+ * @param Alarm Specifies the Alarm.
* This parameter can be one of the following values:
* @arg RTC_ALARM_A: AlarmA
* @arg RTC_ALARM_B: AlarmB
- * @param Format: Specifies the format of the entered parameters.
+ * @param Format Specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg RTC_FORMAT_BIN: Binary data format
* @arg RTC_FORMAT_BCD: BCD data format
@@ -1288,7 +1298,7 @@
/**
* @brief This function handles Alarm interrupt request.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval None
*/
@@ -1329,7 +1339,7 @@
/**
* @brief Alarm A callback.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval None
*/
@@ -1344,9 +1354,9 @@
/**
* @brief This function handles AlarmA Polling request.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
- * @param Timeout: Timeout duration
+ * @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
@@ -1407,7 +1417,7 @@
* The software must then wait until it is set again before reading
* the calendar, which means that the calendar registers have been
* correctly copied into the RTC_TR and RTC_DR shadow registers.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval HAL status
*/
@@ -1453,7 +1463,7 @@
*/
/**
* @brief Returns the RTC state.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval HAL state
*/
@@ -1470,7 +1480,7 @@
* @brief Enters the RTC Initialization mode.
* @note The RTC Initialization mode is write protected, use the
* __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval HAL status
*/
@@ -1503,7 +1513,7 @@
/**
* @brief Converts a 2 digit decimal to BCD format.
- * @param Value: Byte to be converted
+ * @param Value Byte to be converted
* @retval Converted byte
*/
uint8_t RTC_ByteToBcd2(uint8_t Value)
@@ -1521,7 +1531,7 @@
/**
* @brief Converts from 2 digit BCD to Binary.
- * @param Value: BCD value to be converted
+ * @param Value BCD value to be converted
* @retval Converted word
*/
uint8_t RTC_Bcd2ToByte(uint8_t Value)
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rtc.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rtc.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_rtc.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of RTC HAL module. ****************************************************************************** * @attention @@ -424,14 +422,14 @@ */ /** @brief Reset RTC handle state - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET) /** * @brief Disable the write protection for RTC registers. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \ @@ -442,7 +440,7 @@ /** * @brief Enable the write protection for RTC registers. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \ @@ -452,36 +450,36 @@ /** * @brief Enable the RTC ALARMA peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE)) /** * @brief Disable the RTC ALARMA peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE)) /** * @brief Enable the RTC ALARMB peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE)) /** * @brief Disable the RTC ALARMB peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE)) /** * @brief Enable the RTC Alarm interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg RTC_IT_ALRA: Alarm A interrupt * @arg RTC_IT_ALRB: Alarm B interrupt @@ -491,8 +489,8 @@ /** * @brief Disable the RTC Alarm interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled. * This parameter can be any combination of the following values: * @arg RTC_IT_ALRA: Alarm A interrupt * @arg RTC_IT_ALRB: Alarm B interrupt @@ -502,8 +500,8 @@ /** * @brief Check whether the specified RTC Alarm interrupt has occurred or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Alarm interrupt to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Alarm interrupt to check. * This parameter can be: * @arg RTC_IT_ALRA: Alarm A interrupt * @arg RTC_IT_ALRB: Alarm B interrupt @@ -513,8 +511,8 @@ /** * @brief Get the selected RTC Alarm's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Alarm Flag to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Alarm Flag to check. * This parameter can be: * @arg RTC_FLAG_ALRAF * @arg RTC_FLAG_ALRBF @@ -526,8 +524,8 @@ /** * @brief Clear the RTC Alarm's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Alarm Flag sources to be enabled or disabled. * This parameter can be: * @arg RTC_FLAG_ALRAF * @arg RTC_FLAG_ALRBF @@ -538,8 +536,8 @@ /** * @brief Check whether the specified RTC Alarm interrupt has been enabled or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to check. * This parameter can be: * @arg RTC_IT_ALRA: Alarm A interrupt * @arg RTC_IT_ALRB: Alarm B interrupt
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rtc_ex.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rtc_ex.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_rtc_ex.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief RTC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Real Time Clock (RTC) Extension peripheral:
@@ -138,16 +136,16 @@
/**
* @brief Sets TimeStamp.
* @note This API must be called before enabling the TimeStamp feature.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
- * @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is
+ * @param TimeStampEdge Specifies the pin edge on which the TimeStamp is
* activated.
* This parameter can be one of the following values:
* @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
* rising edge of the related pin.
* @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
* falling edge of the related pin.
- * @param RTC_TimeStampPin: specifies the RTC TimeStamp Pin.
+ * @param RTC_TimeStampPin specifies the RTC TimeStamp Pin.
* This parameter can be one of the following values:
* @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
* @arg RTC_TIMESTAMPPIN_POS1: PI8/PA0 is selected as RTC TimeStamp Pin.
@@ -199,17 +197,17 @@
/**
* @brief Sets TimeStamp with Interrupt.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @note This API must be called before enabling the TimeStamp feature.
- * @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is
+ * @param TimeStampEdge Specifies the pin edge on which the TimeStamp is
* activated.
* This parameter can be one of the following values:
* @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
* rising edge of the related pin.
* @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
* falling edge of the related pin.
- * @param RTC_TimeStampPin: Specifies the RTC TimeStamp Pin.
+ * @param RTC_TimeStampPin Specifies the RTC TimeStamp Pin.
* This parameter can be one of the following values:
* @arg RTC_TIMESTAMPPIN_DEFAULT: PC13 is selected as RTC TimeStamp Pin.
* @arg RTC_TIMESTAMPPIN_PI8: PI8 is selected as RTC TimeStamp Pin. (not applicable in the case of STM32F446xx, STM32F412xx, STM32F413xx and STM32F423xx devices)
@@ -269,7 +267,7 @@
/**
* @brief Deactivates TimeStamp.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval HAL status
*/
@@ -307,11 +305,11 @@
/**
* @brief Gets the RTC TimeStamp value.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
- * @param sTimeStamp: Pointer to Time structure
- * @param sTimeStampDate: Pointer to Date structure
- * @param Format: specifies the format of the entered parameters.
+ * @param sTimeStamp Pointer to Time structure
+ * @param sTimeStampDate Pointer to Date structure
+ * @param Format specifies the format of the entered parameters.
* This parameter can be one of the following values:
* RTC_FORMAT_BIN: Binary data format
* RTC_FORMAT_BCD: BCD data format
@@ -364,9 +362,9 @@
/**
* @brief Sets Tamper
* @note By calling this API we disable the tamper interrupt for all tampers.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
- * @param sTamper: Pointer to Tamper Structure.
+ * @param sTamper Pointer to Tamper Structure.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
@@ -414,9 +412,9 @@
/**
* @brief Sets Tamper with interrupt.
* @note By calling this API we force the tamper interrupt for all tampers.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
- * @param sTamper: Pointer to RTC Tamper.
+ * @param sTamper Pointer to RTC Tamper.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
@@ -483,9 +481,9 @@
/**
* @brief Deactivates Tamper.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
- * @param Tamper: Selected tamper pin.
+ * @param Tamper Selected tamper pin.
* This parameter can be RTC_Tamper_1 and/or RTC_TAMPER_2.
* @retval HAL status
*/
@@ -511,7 +509,7 @@
/**
* @brief This function handles TimeStamp interrupt request.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval None
*/
@@ -566,7 +564,7 @@
/**
* @brief TimeStamp callback.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval None
*/
@@ -581,7 +579,7 @@
/**
* @brief Tamper 1 callback.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval None
*/
@@ -596,7 +594,7 @@
/**
* @brief Tamper 2 callback.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval None
*/
@@ -611,9 +609,9 @@
/**
* @brief This function handles TimeStamp polling request.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
- * @param Timeout: Timeout duration
+ * @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
@@ -654,9 +652,9 @@
/**
* @brief This function handles Tamper1 Polling.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
- * @param Timeout: Timeout duration
+ * @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
@@ -690,9 +688,9 @@
/**
* @brief This function handles Tamper2 Polling.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
- * @param Timeout: Timeout duration
+ * @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
@@ -744,10 +742,10 @@
/**
* @brief Sets wake up timer.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
- * @param WakeUpCounter: Wake up counter
- * @param WakeUpClock: Wake up clock
+ * @param WakeUpCounter Wake up counter
+ * @param WakeUpClock Wake up clock
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
@@ -835,10 +833,10 @@
/**
* @brief Sets wake up timer with interrupt
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
- * @param WakeUpCounter: Wake up counter
- * @param WakeUpClock: Wake up clock
+ * @param WakeUpCounter Wake up counter
+ * @param WakeUpClock Wake up clock
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
@@ -937,7 +935,7 @@
/**
* @brief Deactivates wake up timer counter.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval HAL status
*/
@@ -992,7 +990,7 @@
/**
* @brief Gets wake up timer counter.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval Counter value
*/
@@ -1004,7 +1002,7 @@
/**
* @brief This function handles Wake Up Timer interrupt request.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval None
*/
@@ -1032,7 +1030,7 @@
/**
* @brief Wake Up Timer callback.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval None
*/
@@ -1047,9 +1045,9 @@
/**
* @brief This function handles Wake Up Timer Polling.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
- * @param Timeout: Timeout duration
+ * @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
@@ -1114,12 +1112,12 @@
/**
* @brief Writes a data in a specified RTC Backup data register.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
- * @param BackupRegister: RTC Backup data Register number.
+ * @param BackupRegister RTC Backup data Register number.
* This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
* specify the register.
- * @param Data: Data to be written in the specified RTC Backup data register.
+ * @param Data Data to be written in the specified RTC Backup data register.
* @retval None
*/
void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
@@ -1138,9 +1136,9 @@
/**
* @brief Reads data from the specified RTC Backup data Register.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
- * @param BackupRegister: RTC Backup data Register number.
+ * @param BackupRegister RTC Backup data Register number.
* This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
* specify the register.
* @retval Read value
@@ -1161,13 +1159,13 @@
/**
* @brief Sets the Coarse calibration parameters.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
- * @param CalibSign: Specifies the sign of the coarse calibration value.
+ * @param CalibSign Specifies the sign of the coarse calibration value.
* This parameter can be one of the following values :
* @arg RTC_CALIBSIGN_POSITIVE: The value sign is positive
* @arg RTC_CALIBSIGN_NEGATIVE: The value sign is negative
- * @param Value: value of coarse calibration expressed in ppm (coded on 5 bits).
+ * @param Value value of coarse calibration expressed in ppm (coded on 5 bits).
*
* @note This Calibration value should be between 0 and 63 when using negative
* sign with a 2-ppm step.
@@ -1230,7 +1228,7 @@
/**
* @brief Deactivates the Coarse calibration parameters.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval HAL status
*/
@@ -1281,18 +1279,18 @@
/**
* @brief Sets the Smooth calibration parameters.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
- * @param SmoothCalibPeriod: Select the Smooth Calibration Period.
+ * @param SmoothCalibPeriod Select the Smooth Calibration Period.
* This parameter can be can be one of the following values :
* @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s.
* @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s.
* @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s.
- * @param SmoothCalibPlusPulses: Select to Set or reset the CALP bit.
+ * @param SmoothCalibPlusPulses Select to Set or reset the CALP bit.
* This parameter can be one of the following values:
* @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulse every 2*11 pulses.
* @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added.
- * @param SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits.
+ * @param SmouthCalibMinusPulsesValue Select the value of CALM[80] bits.
* This parameter can be one any value from 0 to 0x000001FF.
* @note To deactivate the smooth calibration, the field SmoothCalibPlusPulses
* must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field
@@ -1359,13 +1357,13 @@
/**
* @brief Configures the Synchronization Shift Control Settings.
* @note When REFCKON is set, firmware must not write to Shift control register.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
- * @param ShiftAdd1S: Select to add or not 1 second to the time calendar.
+ * @param ShiftAdd1S Select to add or not 1 second to the time calendar.
* This parameter can be one of the following values :
* @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar.
* @arg RTC_SHIFTADD1S_RESET: No effect.
- * @param ShiftSubFS: Select the number of Second Fractions to substitute.
+ * @param ShiftSubFS Select the number of Second Fractions to substitute.
* This parameter can be one any value from 0 to 0x7FFF.
* @retval HAL status
*/
@@ -1456,9 +1454,9 @@
/**
* @brief Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
- * @param CalibOutput: Select the Calibration output Selection .
+ * @param CalibOutput Select the Calibration output Selection .
* This parameter can be one of the following values:
* @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz.
* @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz.
@@ -1499,7 +1497,7 @@
/**
* @brief Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval HAL status
*/
@@ -1529,7 +1527,7 @@
/**
* @brief Enables the RTC reference clock detection.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval HAL status
*/
@@ -1579,7 +1577,7 @@
/**
* @brief Disable the RTC reference clock detection.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval HAL status
*/
@@ -1629,7 +1627,7 @@
/**
* @brief Enables the Bypass Shadow feature.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @note When the Bypass Shadow is enabled the calendar value are taken
* directly from the Calendar counter.
@@ -1662,7 +1660,7 @@
/**
* @brief Disables the Bypass Shadow feature.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @note When the Bypass Shadow is enabled the calendar value are taken
* directly from the Calendar counter.
@@ -1714,7 +1712,7 @@
/**
* @brief Alarm B callback.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval None
*/
@@ -1729,9 +1727,9 @@
/**
* @brief This function handles AlarmB Polling request.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
- * @param Timeout: Timeout duration
+ * @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rtc_ex.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_rtc_ex.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_rtc_ex.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief Header file of RTC HAL Extension module.
******************************************************************************
* @attention
@@ -334,22 +332,22 @@
/**
* @brief Enable the RTC WakeUp Timer peripheral.
- * @param __HANDLE__: specifies the RTC handle.
+ * @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE))
/**
* @brief Disable the RTC Wake-up Timer peripheral.
- * @param __HANDLE__: specifies the RTC handle.
+ * @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE))
/**
* @brief Enable the RTC WakeUpTimer interrupt.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
* This parameter can be:
* @arg RTC_IT_WUT: WakeUpTimer A interrupt
* @retval None
@@ -358,8 +356,8 @@
/**
* @brief Disable the RTC WakeUpTimer interrupt.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled.
* This parameter can be:
* @arg RTC_IT_WUT: WakeUpTimer A interrupt
* @retval None
@@ -368,8 +366,8 @@
/**
* @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt to check.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt to check.
* This parameter can be:
* @arg RTC_IT_WUT: WakeUpTimer A interrupt
* @retval None
@@ -378,8 +376,8 @@
/**
* @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC Wake Up timer interrupt sources to check.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check.
* This parameter can be:
* @arg RTC_IT_WUT: WakeUpTimer interrupt
* @retval None
@@ -388,8 +386,8 @@
/**
* @brief Get the selected RTC WakeUpTimer's flag status.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC WakeUpTimer Flag to check.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __FLAG__ specifies the RTC WakeUpTimer Flag to check.
* This parameter can be:
* @arg RTC_FLAG_WUTF
* @arg RTC_FLAG_WUTWF
@@ -399,8 +397,8 @@
/**
* @brief Clear the RTC Wake Up timer's pending flags.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __FLAG__ specifies the RTC Tamper Flag sources to be enabled or disabled.
* This parameter can be:
* @arg RTC_FLAG_WUTF
* @retval None
@@ -501,22 +499,22 @@
/**
* @brief Enable the RTC TimeStamp peripheral.
- * @param __HANDLE__: specifies the RTC handle.
+ * @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE))
/**
* @brief Disable the RTC TimeStamp peripheral.
- * @param __HANDLE__: specifies the RTC handle.
+ * @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE))
/**
* @brief Enable the RTC TimeStamp interrupt.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt sources to be enabled or disabled.
* This parameter can be:
* @arg RTC_IT_TS: TimeStamp interrupt
* @retval None
@@ -525,8 +523,8 @@
/**
* @brief Disable the RTC TimeStamp interrupt.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt sources to be enabled or disabled.
* This parameter can be:
* @arg RTC_IT_TS: TimeStamp interrupt
* @retval None
@@ -535,8 +533,8 @@
/**
* @brief Check whether the specified RTC TimeStamp interrupt has occurred or not.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt to check.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt to check.
* This parameter can be:
* @arg RTC_IT_TS: TimeStamp interrupt
* @retval None
@@ -545,8 +543,8 @@
/**
* @brief Check whether the specified RTC Time Stamp interrupt has been enabled or not.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC Time Stamp interrupt source to check.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC Time Stamp interrupt source to check.
* This parameter can be:
* @arg RTC_IT_TS: TimeStamp interrupt
* @retval None
@@ -555,8 +553,8 @@
/**
* @brief Get the selected RTC TimeStamp's flag status.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC TimeStamp flag to check.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __FLAG__ specifies the RTC TimeStamp flag to check.
* This parameter can be:
* @arg RTC_FLAG_TSF
* @arg RTC_FLAG_TSOVF
@@ -566,8 +564,8 @@
/**
* @brief Clear the RTC Time Stamp's pending flags.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __FLAG__ specifies the RTC Alarm Flag sources to be enabled or disabled.
* This parameter can be:
* @arg RTC_FLAG_TSF
* @retval None
@@ -585,14 +583,14 @@
/**
* @brief Enable the RTC Tamper1 input detection.
- * @param __HANDLE__: specifies the RTC handle.
+ * @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP1E))
/**
* @brief Disable the RTC Tamper1 input detection.
- * @param __HANDLE__: specifies the RTC handle.
+ * @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP1E))
@@ -600,14 +598,14 @@
#if !defined(STM32F412Zx) && !defined(STM32F412Vx) && !defined(STM32F412Rx) && !defined(STM32F412Cx) && !defined(STM32F413xx) && !defined(STM32F423xx)
/**
* @brief Enable the RTC Tamper2 input detection.
- * @param __HANDLE__: specifies the RTC handle.
+ * @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR |= (RTC_TAFCR_TAMP2E))
/**
* @brief Disable the RTC Tamper2 input detection.
- * @param __HANDLE__: specifies the RTC handle.
+ * @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAFCR &= ~(RTC_TAFCR_TAMP2E))
@@ -615,8 +613,8 @@
/**
* @brief Check whether the specified RTC Tamper interrupt has occurred or not.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC Tamper interrupt to check.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC Tamper interrupt to check.
* This parameter can be:
* @arg RTC_IT_TAMP1
* @arg RTC_IT_TAMP2
@@ -626,8 +624,8 @@
/**
* @brief Check whether the specified RTC Tamper interrupt has been enabled or not.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC Tamper interrupt source to check.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC Tamper interrupt source to check.
* This parameter can be:
* @arg RTC_IT_TAMP: Tamper interrupt
* @retval None
@@ -636,8 +634,8 @@
/**
* @brief Get the selected RTC Tamper's flag status.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC Tamper Flag sources to be enabled or disabled.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __FLAG__ specifies the RTC Tamper Flag sources to be enabled or disabled.
* This parameter can be:
* @arg RTC_FLAG_TAMP1F
* @arg RTC_FLAG_TAMP2F
@@ -647,8 +645,8 @@
/**
* @brief Clear the RTC Tamper's pending flags.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC Tamper Flag to clear.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __FLAG__ specifies the RTC Tamper Flag to clear.
* This parameter can be:
* @arg RTC_FLAG_TAMP1F
* @arg RTC_FLAG_TAMP2F
@@ -757,50 +755,50 @@
/**
* @brief Enable the Coarse calibration process.
- * @param __HANDLE__: specifies the RTC handle.
+ * @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_COARSE_CALIB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_DCE))
/**
* @brief Disable the Coarse calibration process.
- * @param __HANDLE__: specifies the RTC handle.
+ * @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_COARSE_CALIB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_DCE))
/**
* @brief Enable the RTC calibration output.
- * @param __HANDLE__: specifies the RTC handle.
+ * @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE))
/**
* @brief Disable the calibration output.
- * @param __HANDLE__: specifies the RTC handle.
+ * @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE))
/**
* @brief Enable the clock reference detection.
- * @param __HANDLE__: specifies the RTC handle.
+ * @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON))
/**
* @brief Disable the clock reference detection.
- * @param __HANDLE__: specifies the RTC handle.
+ * @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON))
/**
* @brief Get the selected RTC shift operation's flag status.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC shift operation Flag is pending or not.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __FLAG__ specifies the RTC shift operation Flag is pending or not.
* This parameter can be:
* @arg RTC_FLAG_SHPF
* @retval None
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sai.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sai.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_sai.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief SAI HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Serial Audio Interface (SAI) peripheral:
@@ -208,7 +206,6 @@
*/
#define SAI_FIFO_SIZE 8U
#define SAI_DEFAULT_TIMEOUT 4U /* 4ms */
-#define SAI_xCR2_MUTECNT_OFFSET POSITION_VAL(SAI_xCR2_MUTECNT)
/**
* @}
*/
@@ -284,12 +281,12 @@
* @brief Initialize the structure FrameInit, SlotInit and the low part of
* Init according to the specified parameters and call the function
* HAL_SAI_Init to initialize the SAI block.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
- * @param protocol: one of the supported protocol @ref SAI_Protocol
- * @param datasize: one of the supported datasize @ref SAI_Protocol_DataSize
+ * @param protocol one of the supported protocol @ref SAI_Protocol
+ * @param datasize one of the supported datasize @ref SAI_Protocol_DataSize
* the configuration information for SAI module.
- * @param nbslot: Number of slot.
+ * @param nbslot Number of slot.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
@@ -327,7 +324,7 @@
/**
* @brief Initialize the SAI according to the specified parameters.
* in the SAI_InitTypeDef structure and initialize the associated handle.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval HAL status
*/
@@ -498,7 +495,7 @@
/**
* @brief DeInitialize the SAI peripheral.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval HAL status
*/
@@ -539,7 +536,7 @@
/**
* @brief Initialize the SAI MSP.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval None
*/
@@ -555,7 +552,7 @@
/**
* @brief DeInitialize the SAI MSP.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval None
*/
@@ -597,17 +594,14 @@
(+) Blocking mode functions are :
(++) HAL_SAI_Transmit()
(++) HAL_SAI_Receive()
- (++) HAL_SAI_TransmitReceive()
(+) Non Blocking mode functions with Interrupt are :
(++) HAL_SAI_Transmit_IT()
(++) HAL_SAI_Receive_IT()
- (++) HAL_SAI_TransmitReceive_IT()
(+) Non Blocking mode functions with DMA are :
(++) HAL_SAI_Transmit_DMA()
(++) HAL_SAI_Receive_DMA()
- (++) HAL_SAI_TransmitReceive_DMA()
(+) A set of Transfer Complete Callbacks are provided in non Blocking mode:
(++) HAL_SAI_TxCpltCallback()
@@ -620,11 +614,11 @@
/**
* @brief Transmit an amount of data in blocking mode.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be sent
- * @param Timeout: Timeout duration
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t* pData, uint16_t Size, uint32_t Timeout)
@@ -720,11 +714,11 @@
/**
* @brief Receive an amount of data in blocking mode.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be received
- * @param Timeout: Timeout duration
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be received
+ * @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
@@ -818,10 +812,10 @@
/**
* @brief Transmit an amount of data in non-blocking mode with Interrupt.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be sent
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
@@ -880,10 +874,10 @@
/**
* @brief Receive an amount of data in non-blocking mode with Interrupt.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be received
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be received
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
@@ -940,7 +934,7 @@
/**
* @brief Pause the audio stream playing from the Media.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval HAL status
*/
@@ -960,7 +954,7 @@
/**
* @brief Resume the audio stream playing from the Media.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval HAL status
*/
@@ -987,7 +981,7 @@
/**
* @brief Stop the audio stream playing from the Media.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval HAL status
*/
@@ -1019,6 +1013,9 @@
/* Disable SAI peripheral */
SAI_Disable(hsai);
+ /* Flush the fifo */
+ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
+
hsai->State = HAL_SAI_STATE_READY;
/* Process Unlocked */
@@ -1029,7 +1026,7 @@
/**
* @brief Abort the current transfer and disable the SAI.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval HAL status
*/
@@ -1082,10 +1079,10 @@
/**
* @brief Transmit an amount of data in non-blocking mode with DMA.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be sent
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
@@ -1151,10 +1148,10 @@
/**
* @brief Receive an amount of data in non-blocking mode with DMA.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be received
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be received
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
@@ -1220,9 +1217,9 @@
/**
* @brief Enable the Tx mute mode.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
- * @param val: value sent during the mute @ref SAI_Block_Mute_Value
+ * @param val value sent during the mute @ref SAI_Block_Mute_Value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val)
@@ -1240,7 +1237,7 @@
/**
* @brief Disable the Tx mute mode.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval HAL status
*/
@@ -1256,10 +1253,10 @@
/**
* @brief Enable the Rx mute detection.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
- * @param callback: function called when the mute is detected.
- * @param counter: number a data before mute detection max 63.
+ * @param callback function called when the mute is detected.
+ * @param counter number a data before mute detection max 63.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter)
@@ -1270,7 +1267,7 @@
{
/* set the mute counter */
CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTECNT);
- SET_BIT(hsai->Instance->CR2, (uint32_t)((uint32_t)counter << SAI_xCR2_MUTECNT_OFFSET));
+ SET_BIT(hsai->Instance->CR2, (uint32_t)((uint32_t)counter << SAI_xCR2_MUTECNT_Pos));
hsai->mutecallback = callback;
/* enable the IT interrupt */
__HAL_SAI_ENABLE_IT(hsai, SAI_IT_MUTEDET);
@@ -1281,7 +1278,7 @@
/**
* @brief Disable the Rx mute detection.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval HAL status
*/
@@ -1300,7 +1297,7 @@
/**
* @brief Handle SAI interrupt request.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval None
*/
@@ -1483,7 +1480,7 @@
/**
* @brief Tx Transfer completed callback.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval None
*/
@@ -1499,7 +1496,7 @@
/**
* @brief Tx Transfer Half completed callback.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval None
*/
@@ -1515,7 +1512,7 @@
/**
* @brief Rx Transfer completed callback.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval None
*/
@@ -1531,7 +1528,7 @@
/**
* @brief Rx Transfer half completed callback.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval None
*/
@@ -1547,7 +1544,7 @@
/**
* @brief SAI error callback.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval None
*/
@@ -1583,7 +1580,7 @@
/**
* @brief Return the SAI handle state.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval HAL state
*/
@@ -1594,7 +1591,7 @@
/**
* @brief Return the SAI error code.
-* @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+* @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for the specified SAI Block.
* @retval SAI Error Code
*/
@@ -1618,12 +1615,12 @@
/**
* @brief Initialize the SAI I2S protocol according to the specified parameters
* in the SAI_InitTypeDef and create the associated handle.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
- * @param protocol: one of the supported protocol.
- * @param datasize: one of the supported datasize @ref SAI_Protocol_DataSize
+ * @param protocol one of the supported protocol.
+ * @param datasize one of the supported datasize @ref SAI_Protocol_DataSize
* the configuration information for SAI module.
- * @param nbslot: number of slot minimum value is 2 and max is 16.
+ * @param nbslot number of slot minimum value is 2 and max is 16.
* the value must be a multiple of 2.
* @retval HAL status
*/
@@ -1713,11 +1710,11 @@
/**
* @brief Initialize the SAI PCM protocol according to the specified parameters
* in the SAI_InitTypeDef and create the associated handle.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
- * @param protocol: one of the supported protocol
- * @param datasize: one of the supported datasize @ref SAI_Protocol_DataSize
- * @param nbslot: number of slot minimum value is 1 and the max is 16.
+ * @param protocol one of the supported protocol
+ * @param datasize one of the supported datasize @ref SAI_Protocol_DataSize
+ * @param nbslot number of slot minimum value is 1 and the max is 16.
* @retval HAL status
*/
static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
@@ -1783,7 +1780,7 @@
/**
* @brief Fill the fifo.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval None
*/
@@ -1812,9 +1809,9 @@
/**
* @brief Return the interrupt flag to set according the SAI setup.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
- * @param mode: SAI_MODE_DMA or SAI_MODE_IT
+ * @param mode SAI_MODE_DMA or SAI_MODE_IT
* @retval the list of the IT flag to enable
*/
static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode)
@@ -1846,7 +1843,7 @@
/**
* @brief Disable the SAI and wait for the disabling.
- * @param hsai : pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval None
*/
@@ -1875,7 +1872,7 @@
/**
* @brief Tx Handler for Transmit in Interrupt mode 8-Bit transfer.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval None
*/
@@ -1899,7 +1896,7 @@
/**
* @brief Tx Handler for Transmit in Interrupt mode for 16-Bit transfer.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval None
*/
@@ -1924,7 +1921,7 @@
/**
* @brief Tx Handler for Transmit in Interrupt mode for 32-Bit transfer.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval None
*/
@@ -1949,7 +1946,7 @@
/**
* @brief Rx Handler for Receive in Interrupt mode 8-Bit transfer.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval None
*/
@@ -1975,7 +1972,7 @@
/**
* @brief Rx Handler for Receive in Interrupt mode for 16-Bit transfer.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval None
*/
@@ -2002,7 +1999,7 @@
/**
* @brief Rx Handler for Receive in Interrupt mode for 32-Bit transfer.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval None
*/
@@ -2029,7 +2026,7 @@
/**
* @brief DMA SAI transmit process complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -2054,7 +2051,7 @@
/**
* @brief DMA SAI transmit process half complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -2067,7 +2064,7 @@
/**
* @brief DMA SAI receive process complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -2090,7 +2087,7 @@
/**
* @brief DMA SAI receive process half complete callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -2103,7 +2100,7 @@
/**
* @brief DMA SAI communication error callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -2134,7 +2131,7 @@
/**
* @brief DMA SAI Abort callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sai.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sai.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_sai.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of SAI HAL module. ****************************************************************************** * @attention @@ -568,14 +566,14 @@ */ /** @brief Reset SAI handle state - * @param __HANDLE__: specifies the SAI Handle. + * @param __HANDLE__ specifies the SAI Handle. * @retval NoneS */ #define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET) /** @brief Enable or disable the specified SAI interrupts. - * @param __HANDLE__: specifies the SAI Handle. - * @param __INTERRUPT__: specifies the interrupt source to enable or disable. + * @param __HANDLE__ specifies the SAI Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable or disable. * This parameter can be one of the following values: * @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable * @arg SAI_IT_MUTEDET: Mute detection interrupt enable @@ -590,9 +588,9 @@ #define __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__))) /** @brief Check if the specified SAI interrupt source is enabled or disabled. - * @param __HANDLE__: specifies the SAI Handle. + * @param __HANDLE__ specifies the SAI Handle. * This parameter can be SAI where x: 1, 2, or 3 to select the SAI peripheral. - * @param __INTERRUPT__: specifies the SAI interrupt source to check. + * @param __INTERRUPT__ specifies the SAI interrupt source to check. * This parameter can be one of the following values: * @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable * @arg SAI_IT_MUTEDET: Mute detection interrupt enable @@ -606,8 +604,8 @@ #define __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Check whether the specified SAI flag is set or not. - * @param __HANDLE__: specifies the SAI Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the SAI Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg SAI_FLAG_OVRUDR: Overrun underrun flag. * @arg SAI_FLAG_MUTEDET: Mute detection flag. @@ -621,8 +619,8 @@ #define __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) /** @brief Clear the specified SAI pending flag. - * @param __HANDLE__: specifies the SAI Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the SAI Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be any combination of the following values: * @arg SAI_FLAG_OVRUDR: Clear Overrun underrun * @arg SAI_FLAG_MUTEDET: Clear Mute detection @@ -636,13 +634,13 @@ #define __HAL_SAI_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->CLRFR = (__FLAG__)) /** @brief Enable SAI - * @param __HANDLE__: specifies the SAI Handle. + * @param __HANDLE__ specifies the SAI Handle. * @retval None */ #define __HAL_SAI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SAI_xCR1_SAIEN) /** @brief Disable SAI - * @param __HANDLE__: specifies the SAI Handle. + * @param __HANDLE__ specifies the SAI Handle. * @retval None */ #define __HAL_SAI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~SAI_xCR1_SAIEN)
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sai_ex.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sai_ex.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_sai_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief SAI Extension HAL module driver. * This file provides firmware functions to manage the following * functionalities of SAI extension peripheral: @@ -109,7 +107,7 @@ /** * @brief Configure SAI Block synchronization mode - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval SAI Clock Input */ @@ -170,7 +168,7 @@ } /** * @brief Get SAI Input Clock based on SAI source clock selection - * @param hsai: pointer to a SAI_HandleTypeDef structure that contains + * @param hsai pointer to a SAI_HandleTypeDef structure that contains * the configuration information for SAI module. * @retval SAI Clock Input */
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sai_ex.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sai_ex.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_sai_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of SAI Extension HAL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sd.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sd.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_sd.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief SD card HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Secure Digital (SD) peripheral:
@@ -303,7 +301,7 @@
/**
* @brief Initializes the SD according to the specified parameters in the
SD_HandleTypeDef and create the associated handle.
- * @param hsd: Pointer to the SD handle
+ * @param hsd Pointer to the SD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd)
@@ -350,7 +348,7 @@
/**
* @brief Initializes the SD Card.
- * @param hsd: Pointer to SD handle
+ * @param hsd Pointer to SD handle
* @note This function initializes the SD card. It could be used when a card
re-initialization is needed.
* @retval HAL status
@@ -407,7 +405,7 @@
/**
* @brief De-Initializes the SD card.
- * @param hsd: Pointer to SD handle
+ * @param hsd Pointer to SD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd)
@@ -438,7 +436,7 @@
/**
* @brief Initializes the SD MSP.
- * @param hsd: Pointer to SD handle
+ * @param hsd Pointer to SD handle
* @retval None
*/
__weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd)
@@ -453,7 +451,7 @@
/**
* @brief De-Initialize SD MSP.
- * @param hsd: Pointer to SD handle
+ * @param hsd Pointer to SD handle
* @retval None
*/
__weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd)
@@ -490,11 +488,11 @@
* is managed by polling mode.
* @note This API should be followed by a check on the card state through
* HAL_SD_GetCardState().
- * @param hsd: Pointer to SD handle
- * @param pData: pointer to the buffer that will contain the received data
- * @param BlockAdd: Block Address from where data is to be read
- * @param NumberOfBlocks: Number of SD blocks to read
- * @param Timeout: Specify timeout value
+ * @param hsd Pointer to SD handle
+ * @param pData pointer to the buffer that will contain the received data
+ * @param BlockAdd Block Address from where data is to be read
+ * @param NumberOfBlocks Number of SD blocks to read
+ * @param Timeout Specify timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
@@ -680,11 +678,11 @@
* transfer is managed by polling mode.
* @note This API should be followed by a check on the card state through
* HAL_SD_GetCardState().
- * @param hsd: Pointer to SD handle
- * @param pData: pointer to the buffer that will contain the data to transmit
- * @param BlockAdd: Block Address where data will be written
- * @param NumberOfBlocks: Number of SD blocks to write
- * @param Timeout: Specify timeout value
+ * @param hsd Pointer to SD handle
+ * @param pData pointer to the buffer that will contain the data to transmit
+ * @param BlockAdd Block Address where data will be written
+ * @param NumberOfBlocks Number of SD blocks to write
+ * @param Timeout Specify timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
@@ -857,10 +855,10 @@
* HAL_SD_GetCardState().
* @note You could also check the IT transfer process through the SD Rx
* interrupt event.
- * @param hsd: Pointer to SD handle
- * @param pData: Pointer to the buffer that will contain the received data
- * @param BlockAdd: Block Address from where data is to be read
- * @param NumberOfBlocks: Number of blocks to read.
+ * @param hsd Pointer to SD handle
+ * @param pData Pointer to the buffer that will contain the received data
+ * @param BlockAdd Block Address from where data is to be read
+ * @param NumberOfBlocks Number of blocks to read.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
@@ -962,10 +960,10 @@
* HAL_SD_GetCardState().
* @note You could also check the IT transfer process through the SD Tx
* interrupt event.
- * @param hsd: Pointer to SD handle
- * @param pData: Pointer to the buffer that will contain the data to transmit
- * @param BlockAdd: Block Address where data will be written
- * @param NumberOfBlocks: Number of blocks to write
+ * @param hsd Pointer to SD handle
+ * @param pData Pointer to the buffer that will contain the data to transmit
+ * @param BlockAdd Block Address where data will be written
+ * @param NumberOfBlocks Number of blocks to write
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
@@ -1068,10 +1066,10 @@
* HAL_SD_GetCardState().
* @note You could also check the DMA transfer process through the SD Rx
* interrupt event.
- * @param hsd: Pointer SD handle
- * @param pData: Pointer to the buffer that will contain the received data
- * @param BlockAdd: Block Address from where data is to be read
- * @param NumberOfBlocks: Number of blocks to read.
+ * @param hsd Pointer SD handle
+ * @param pData Pointer to the buffer that will contain the received data
+ * @param BlockAdd Block Address from where data is to be read
+ * @param NumberOfBlocks Number of blocks to read.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
@@ -1185,10 +1183,10 @@
* HAL_SD_GetCardState().
* @note You could also check the DMA transfer process through the SD Tx
* interrupt event.
- * @param hsd: Pointer to SD handle
- * @param pData: Pointer to the buffer that will contain the data to transmit
- * @param BlockAdd: Block Address where data will be written
- * @param NumberOfBlocks: Number of blocks to write
+ * @param hsd Pointer to SD handle
+ * @param pData Pointer to the buffer that will contain the data to transmit
+ * @param BlockAdd Block Address where data will be written
+ * @param NumberOfBlocks Number of blocks to write
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
@@ -1300,9 +1298,9 @@
* @brief Erases the specified memory area of the given SD card.
* @note This API should be followed by a check on the card state through
* HAL_SD_GetCardState().
- * @param hsd: Pointer to SD handle
- * @param BlockStartAdd: Start Block address
- * @param BlockEndAdd: End Block address
+ * @param hsd Pointer to SD handle
+ * @param BlockStartAdd Start Block address
+ * @param BlockEndAdd End Block address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd)
@@ -1402,7 +1400,7 @@
/**
* @brief This function handles SD card interrupt request.
- * @param hsd: Pointer to SD handle
+ * @param hsd Pointer to SD handle
* @retval None
*/
void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
@@ -1624,7 +1622,7 @@
/**
* @brief return the SD state
- * @param hsd: Pointer to sd handle
+ * @param hsd Pointer to sd handle
* @retval HAL state
*/
HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd)
@@ -1634,7 +1632,7 @@
/**
* @brief Return the SD error code
-* @param hsd : Pointer to a SD_HandleTypeDef structure that contains
+* @param hsd Pointer to a SD_HandleTypeDef structure that contains
* the configuration information.
* @retval SD Error Code
*/
@@ -1645,7 +1643,7 @@
/**
* @brief Tx Transfer completed callbacks
- * @param hsd: Pointer to SD handle
+ * @param hsd Pointer to SD handle
* @retval None
*/
__weak void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd)
@@ -1660,7 +1658,7 @@
/**
* @brief Rx Transfer completed callbacks
- * @param hsd: Pointer SD handle
+ * @param hsd Pointer SD handle
* @retval None
*/
__weak void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd)
@@ -1675,7 +1673,7 @@
/**
* @brief SD error callbacks
- * @param hsd: Pointer SD handle
+ * @param hsd Pointer SD handle
* @retval None
*/
__weak void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd)
@@ -1690,7 +1688,7 @@
/**
* @brief SD Abort callbacks
- * @param hsd: Pointer SD handle
+ * @param hsd Pointer SD handle
* @retval None
*/
__weak void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd)
@@ -1726,8 +1724,8 @@
/**
* @brief Returns information the information of the card which are stored on
* the CID register.
- * @param hsd: Pointer to SD handle
- * @param pCID: Pointer to a HAL_SD_CIDTypeDef structure that
+ * @param hsd Pointer to SD handle
+ * @param pCID Pointer to a HAL_SD_CIDTypeDef structure that
* contains all CID register parameters
* @retval HAL status
*/
@@ -1807,8 +1805,8 @@
/**
* @brief Returns information the information of the card which are stored on
* the CSD register.
- * @param hsd: Pointer to SD handle
- * @param pCSD: Pointer to a HAL_SD_CardCSDTypeDef structure that
+ * @param hsd Pointer to SD handle
+ * @param pCSD Pointer to a HAL_SD_CardCSDTypeDef structure that
* contains all CSD register parameters
* @retval HAL status
*/
@@ -1954,8 +1952,8 @@
/**
* @brief Gets the SD status info.
- * @param hsd: Pointer to SD handle
- * @param pStatus: Pointer to the HAL_SD_CardStatusTypeDef structure that
+ * @param hsd Pointer to SD handle
+ * @param pStatus Pointer to the HAL_SD_CardStatusTypeDef structure that
* will contain the SD card status information
* @retval HAL status
*/
@@ -2042,8 +2040,8 @@
/**
* @brief Gets the SD card info.
- * @param hsd: Pointer to SD handle
- * @param pCardInfo: Pointer to the HAL_SD_CardInfoTypeDef structure that
+ * @param hsd Pointer to SD handle
+ * @param pCardInfo Pointer to the HAL_SD_CardInfoTypeDef structure that
* will contain the SD card status information
* @retval HAL status
*/
@@ -2064,8 +2062,8 @@
/**
* @brief Enables wide bus operation for the requested card if supported by
* card.
- * @param hsd: Pointer to SD handle
- * @param WideMode: Specifies the SD card wide bus mode
+ * @param hsd Pointer to SD handle
+ * @param WideMode Specifies the SD card wide bus mode
* This parameter can be one of the following values:
* @arg SDIO_BUS_WIDE_8B: 8-bit data transfer
* @arg SDIO_BUS_WIDE_4B: 4-bit data transfer
@@ -2141,7 +2139,7 @@
/**
* @brief Gets the current sd card data state.
- * @param hsd: pointer to SD handle
+ * @param hsd pointer to SD handle
* @retval Card state
*/
HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd)
@@ -2163,7 +2161,7 @@
/**
* @brief Abort the current transfer and disable the SD.
- * @param hsd: pointer to a SD_HandleTypeDef structure that contains
+ * @param hsd pointer to a SD_HandleTypeDef structure that contains
* the configuration information for SD module.
* @retval HAL status
*/
@@ -2210,7 +2208,7 @@
/**
* @brief Abort the current transfer and disable the SD (IT mode).
- * @param hsd: pointer to a SD_HandleTypeDef structure that contains
+ * @param hsd pointer to a SD_HandleTypeDef structure that contains
* the configuration information for SD module.
* @retval HAL status
*/
@@ -2287,7 +2285,7 @@
/**
* @brief DMA SD transmit process complete callback
- * @param hdma: DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
@@ -2300,7 +2298,7 @@
/**
* @brief DMA SD receive process complete callback
- * @param hdma: DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
@@ -2333,7 +2331,7 @@
/**
* @brief DMA SD communication error callback
- * @param hdma: DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void SD_DMAError(DMA_HandleTypeDef *hdma)
@@ -2365,7 +2363,7 @@
/**
* @brief DMA SD Tx Abort callback
- * @param hdma: DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void SD_DMATxAbort(DMA_HandleTypeDef *hdma)
@@ -2402,7 +2400,7 @@
/**
* @brief DMA SD Rx Abort callback
- * @param hdma: DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void SD_DMARxAbort(DMA_HandleTypeDef *hdma)
@@ -2440,7 +2438,7 @@
/**
* @brief Initializes the sd card.
- * @param hsd: Pointer to SD handle
+ * @param hsd Pointer to SD handle
* @retval SD Card error state
*/
static uint32_t SD_InitCard(SD_HandleTypeDef *hsd)
@@ -2529,7 +2527,7 @@
* @brief Enquires cards about their operating voltage and configures clock
* controls and stores SD information that will be needed in future
* in the SD handle.
- * @param hsd: Pointer to SD handle
+ * @param hsd Pointer to SD handle
* @retval error state
*/
static uint32_t SD_PowerON(SD_HandleTypeDef *hsd)
@@ -2630,7 +2628,7 @@
/**
* @brief Turns the SDIO output signals off.
- * @param hsd: Pointer to SD handle
+ * @param hsd Pointer to SD handle
* @retval HAL status
*/
static HAL_StatusTypeDef SD_PowerOFF(SD_HandleTypeDef *hsd)
@@ -2643,8 +2641,8 @@
/**
* @brief Send Status info command.
- * @param hsd: pointer to SD handle
- * @param pSDstatus: Pointer to the buffer that will contain the SD card status
+ * @param hsd pointer to SD handle
+ * @param pSDstatus Pointer to the buffer that will contain the SD card status
* SD Status register)
* @retval error state
*/
@@ -2745,8 +2743,8 @@
/**
* @brief Returns the current card's status.
- * @param hsd: Pointer to SD handle
- * @param pCardStatus: pointer to the buffer that will contain the SD card
+ * @param hsd Pointer to SD handle
+ * @param pCardStatus pointer to the buffer that will contain the SD card
* status (Card Status register)
* @retval error state
*/
@@ -2774,7 +2772,7 @@
/**
* @brief Enables the SDIO wide bus mode.
- * @param hsd: pointer to SD handle
+ * @param hsd pointer to SD handle
* @retval error state
*/
static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd)
@@ -2821,7 +2819,7 @@
/**
* @brief Disables the SDIO wide bus mode.
- * @param hsd: Pointer to SD handle
+ * @param hsd Pointer to SD handle
* @retval error state
*/
static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd)
@@ -2869,8 +2867,8 @@
/**
* @brief Finds the SD card SCR register value.
- * @param hsd: Pointer to SD handle
- * @param pSCR: pointer to the buffer that will contain the SCR value
+ * @param hsd Pointer to SD handle
+ * @param pSCR pointer to the buffer that will contain the SCR value
* @retval error state
*/
static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
@@ -2960,7 +2958,7 @@
/**
* @brief Wrap up reading in non-blocking mode.
- * @param hsd: pointer to a SD_HandleTypeDef structure that contains
+ * @param hsd pointer to a SD_HandleTypeDef structure that contains
* the configuration information.
* @retval HAL status
*/
@@ -2984,7 +2982,7 @@
/**
* @brief Wrap up writing in non-blocking mode.
- * @param hsd: pointer to a SD_HandleTypeDef structure that contains
+ * @param hsd pointer to a SD_HandleTypeDef structure that contains
* the configuration information.
* @retval HAL status
*/
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sd.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sd.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_sd.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of SD HAL module. ****************************************************************************** * @attention @@ -389,8 +387,8 @@ /** * @brief Enable the SD device interrupt. - * @param __HANDLE__: SD Handle - * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled. + * @param __HANDLE__ SD Handle + * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled. * This parameter can be one or a combination of the following values: * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -420,8 +418,8 @@ /** * @brief Disable the SD device interrupt. - * @param __HANDLE__: SD Handle - * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled. + * @param __HANDLE__ SD Handle + * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled. * This parameter can be one or a combination of the following values: * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -451,8 +449,8 @@ /** * @brief Check whether the specified SD flag is set or not. - * @param __HANDLE__: SD Handle - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ SD Handle + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) @@ -482,8 +480,8 @@ /** * @brief Clear the SD's pending flags. - * @param __HANDLE__: SD Handle - * @param __FLAG__: specifies the flag to clear. + * @param __HANDLE__ SD Handle + * @param __FLAG__ specifies the flag to clear. * This parameter can be one or a combination of the following values: * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) @@ -502,8 +500,8 @@ /** * @brief Check whether the specified SD interrupt has occurred or not. - * @param __HANDLE__: SD Handle - * @param __INTERRUPT__: specifies the SDMMC interrupt source to check. + * @param __HANDLE__ SD Handle + * @param __INTERRUPT__ specifies the SDMMC interrupt source to check. * This parameter can be one of the following values: * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -533,8 +531,8 @@ /** * @brief Clear the SD's interrupt pending bits. - * @param __HANDLE__: SD Handle - * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * @param __HANDLE__ SD Handle + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. * This parameter can be one or a combination of the following values: * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sdram.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sdram.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_sdram.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief SDRAM HAL module driver.
* This file provides a generic firmware to drive SDRAM memories mounted
* as external device.
@@ -132,9 +130,9 @@
/**
* @brief Performs the SDRAM device initialization sequence.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
- * @param Timing: Pointer to SDRAM control timing structure
+ * @param Timing Pointer to SDRAM control timing structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
@@ -170,7 +168,7 @@
/**
* @brief Perform the SDRAM device initialization sequence.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
* @retval HAL status
*/
@@ -193,7 +191,7 @@
/**
* @brief SDRAM MSP Init.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
* @retval None
*/
@@ -208,7 +206,7 @@
/**
* @brief SDRAM MSP DeInit.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
* @retval None
*/
@@ -223,7 +221,7 @@
/**
* @brief This function handles SDRAM refresh error interrupt request.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
* @retval HAL status
*/
@@ -242,7 +240,7 @@
/**
* @brief SDRAM Refresh error callback.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
* @retval None
*/
@@ -257,7 +255,7 @@
/**
* @brief DMA transfer complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -272,7 +270,7 @@
/**
* @brief DMA transfer complete error callback.
- * @param hdma: DMA handle
+ * @param hdma DMA handle
* @retval None
*/
__weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
@@ -303,11 +301,11 @@
/**
* @brief Reads 8-bit data buffer from the SDRAM memory.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
- * @param pAddress: Pointer to read start address
- * @param pDstBuffer: Pointer to destination buffer
- * @param BufferSize: Size of the buffer to read from memory
+ * @param pAddress Pointer to read start address
+ * @param pDstBuffer Pointer to destination buffer
+ * @param BufferSize Size of the buffer to read from memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
@@ -343,11 +341,11 @@
/**
* @brief Writes 8-bit data buffer to SDRAM memory.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
- * @param pAddress: Pointer to write start address
- * @param pSrcBuffer: Pointer to source buffer to write
- * @param BufferSize: Size of the buffer to write to memory
+ * @param pAddress Pointer to write start address
+ * @param pSrcBuffer Pointer to source buffer to write
+ * @param BufferSize Size of the buffer to write to memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
@@ -386,11 +384,11 @@
/**
* @brief Reads 16-bit data buffer from the SDRAM memory.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
- * @param pAddress: Pointer to read start address
- * @param pDstBuffer: Pointer to destination buffer
- * @param BufferSize: Size of the buffer to read from memory
+ * @param pAddress Pointer to read start address
+ * @param pDstBuffer Pointer to destination buffer
+ * @param BufferSize Size of the buffer to read from memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
@@ -426,11 +424,11 @@
/**
* @brief Writes 16-bit data buffer to SDRAM memory.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
- * @param pAddress: Pointer to write start address
- * @param pSrcBuffer: Pointer to source buffer to write
- * @param BufferSize: Size of the buffer to write to memory
+ * @param pAddress Pointer to write start address
+ * @param pSrcBuffer Pointer to source buffer to write
+ * @param BufferSize Size of the buffer to write to memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
@@ -469,11 +467,11 @@
/**
* @brief Reads 32-bit data buffer from the SDRAM memory.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
- * @param pAddress: Pointer to read start address
- * @param pDstBuffer: Pointer to destination buffer
- * @param BufferSize: Size of the buffer to read from memory
+ * @param pAddress Pointer to read start address
+ * @param pDstBuffer Pointer to destination buffer
+ * @param BufferSize Size of the buffer to read from memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
@@ -509,11 +507,11 @@
/**
* @brief Writes 32-bit data buffer to SDRAM memory.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
- * @param pAddress: Pointer to write start address
- * @param pSrcBuffer: Pointer to source buffer to write
- * @param BufferSize: Size of the buffer to write to memory
+ * @param pAddress Pointer to write start address
+ * @param pSrcBuffer Pointer to source buffer to write
+ * @param BufferSize Size of the buffer to write to memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
@@ -552,11 +550,11 @@
/**
* @brief Reads a Words data from the SDRAM memory using DMA transfer.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
- * @param pAddress: Pointer to read start address
- * @param pDstBuffer: Pointer to destination buffer
- * @param BufferSize: Size of the buffer to read from memory
+ * @param pAddress Pointer to read start address
+ * @param pDstBuffer Pointer to destination buffer
+ * @param BufferSize Size of the buffer to read from memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
@@ -593,11 +591,11 @@
/**
* @brief Writes a Words data buffer to SDRAM memory using DMA transfer.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
- * @param pAddress: Pointer to write start address
- * @param pSrcBuffer: Pointer to source buffer to write
- * @param BufferSize: Size of the buffer to write to memory
+ * @param pAddress Pointer to write start address
+ * @param pSrcBuffer Pointer to source buffer to write
+ * @param BufferSize Size of the buffer to write to memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
@@ -652,7 +650,7 @@
/**
* @brief Enables dynamically SDRAM write protection.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
* @retval HAL status
*/
@@ -678,7 +676,7 @@
/**
* @brief Disables dynamically SDRAM write protection.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
* @retval HAL status
*/
@@ -704,10 +702,10 @@
/**
* @brief Sends Command to the SDRAM bank.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
- * @param Command: SDRAM command structure
- * @param Timeout: Timeout duration
+ * @param Command SDRAM command structure
+ * @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
@@ -739,9 +737,9 @@
/**
* @brief Programs the SDRAM Memory Refresh rate.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
- * @param RefreshRate: The SDRAM refresh rate value
+ * @param RefreshRate The SDRAM refresh rate value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
@@ -766,9 +764,9 @@
/**
* @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
- * @param AutoRefreshNumber: The SDRAM auto Refresh number
+ * @param AutoRefreshNumber The SDRAM auto Refresh number
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber)
@@ -793,7 +791,7 @@
/**
* @brief Returns the SDRAM memory current mode.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
* @retval The SDRAM memory mode.
*/
@@ -824,7 +822,7 @@
/**
* @brief Returns the SDRAM state.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
* @retval HAL state
*/
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sdram.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sdram.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_sdram.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of SDRAM HAL module. ****************************************************************************** * @attention @@ -103,7 +101,7 @@ */ /** @brief Reset SDRAM handle state - * @param __HANDLE__: specifies the SDRAM handle. + * @param __HANDLE__ specifies the SDRAM handle. * @retval None */ #define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET)
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_smartcard.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_smartcard.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_smartcard.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief SMARTCARD HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the SMARTCARD peripheral:
@@ -238,7 +236,7 @@
/**
* @brief Initializes the SmartCard mode according to the specified
* parameters in the SMARTCARD_InitTypeDef and create the associated handle .
- * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
* @retval HAL status
*/
@@ -304,7 +302,7 @@
/**
* @brief DeInitializes the USART SmartCard peripheral
- * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
* @retval HAL status
*/
@@ -339,7 +337,7 @@
/**
* @brief SMARTCARD MSP Init
- * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
* @retval None
*/
@@ -354,7 +352,7 @@
/**
* @brief SMARTCARD MSP DeInit
- * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
* @retval None
*/
@@ -425,11 +423,11 @@
/**
* @brief Send an amount of data in blocking mode
- * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
- * @param Timeout: Timeout duration
+ * @param pData pointer to data buffer
+ * @param Size amount of data to be sent
+ * @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_Transmit(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
@@ -488,11 +486,11 @@
/**
* @brief Receive an amount of data in blocking mode
- * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be received
- * @param Timeout: Timeout duration
+ * @param pData pointer to data buffer
+ * @param Size amount of data to be received
+ * @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_Receive(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size, uint32_t Timeout)
@@ -526,7 +524,9 @@
{
return HAL_TIMEOUT;
}
+/* MBED */
*pData = (uint8_t)(hsc->Instance->DR & (uint8_t)0xFF);
+/* MBED */
pData +=1U;
}
@@ -546,10 +546,10 @@
/**
* @brief Send an amount of data in non blocking mode
- * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
+ * @param pData pointer to data buffer
+ * @param Size amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_Transmit_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
@@ -594,10 +594,10 @@
/**
* @brief Receive an amount of data in non blocking mode
- * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be received
+ * @param pData pointer to data buffer
+ * @param Size amount of data to be received
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_Receive_IT(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
@@ -639,10 +639,10 @@
/**
* @brief Send an amount of data in non blocking mode
- * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
+ * @param pData pointer to data buffer
+ * @param Size amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMARTCARD_Transmit_DMA(SMARTCARD_HandleTypeDef *hsc, uint8_t *pData, uint16_t Size)
@@ -700,10 +700,10 @@
/**
* @brief Receive an amount of data in non blocking mode
- * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be received
+ * @param pData pointer to data buffer
+ * @param Size amount of data to be received
* @note When the SMARTCARD parity is enabled (PCE = 1) the data received contain the parity bit.s
* @retval HAL status
*/
@@ -1168,7 +1168,7 @@
/**
* @brief This function handles SMARTCARD interrupt request.
- * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
* @retval None
*/
@@ -1293,7 +1293,7 @@
/**
* @brief Tx Transfer completed callbacks
- * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
* @retval None
*/
@@ -1308,7 +1308,7 @@
/**
* @brief Rx Transfer completed callbacks
- * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
* @retval None
*/
@@ -1323,7 +1323,7 @@
/**
* @brief SMARTCARD error callbacks
- * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
* @retval None
*/
@@ -1402,7 +1402,7 @@
/**
* @brief return the SMARTCARD state
- * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
* @retval HAL state
*/
@@ -1417,7 +1417,7 @@
/**
* @brief Return the SMARTCARD error code
- * @param hsc : pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD.
* @retval SMARTCARD Error Code
*/
@@ -1432,7 +1432,7 @@
/**
* @brief DMA SMARTCARD transmit process complete callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -1452,7 +1452,7 @@
/**
* @brief DMA SMARTCARD receive process complete callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -1478,7 +1478,7 @@
/**
* @brief DMA SMARTCARD communication error callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -1509,11 +1509,11 @@
/**
* @brief This function handles SMARTCARD Communication Timeout.
- * @param hsc: SMARTCARD handle
- * @param Flag: specifies the SMARTCARD flag to check.
- * @param Status: The new Flag status (SET or RESET).
- * @param Timeout: Timeout duration
- * @param Tickstart: tick start value
+ * @param hsc SMARTCARD handle
+ * @param Flag specifies the SMARTCARD flag to check.
+ * @param Status The new Flag status (SET or RESET).
+ * @param Timeout Timeout duration
+ * @param Tickstart tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef SMARTCARD_WaitOnFlagUntilTimeout(SMARTCARD_HandleTypeDef *hsc, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
@@ -1545,7 +1545,7 @@
/**
* @brief End ongoing Tx transfer on SMARTCARD peripheral (following error detection or Transmit completion).
- * @param hsc: SMARTCARD handle.
+ * @param hsc SMARTCARD handle.
* @retval None
*/
static void SMARTCARD_EndTxTransfer(SMARTCARD_HandleTypeDef *hsc)
@@ -1560,7 +1560,7 @@
/**
* @brief End ongoing Rx transfer on SMARTCARD peripheral (following error detection or Reception completion).
- * @param hsc: SMARTCARD handle.
+ * @param hsc SMARTCARD handle.
* @retval None
*/
static void SMARTCARD_EndRxTransfer(SMARTCARD_HandleTypeDef *hsc)
@@ -1575,7 +1575,7 @@
/**
* @brief Send an amount of data in non blocking mode
- * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
* @retval HAL status
*/
@@ -1609,7 +1609,7 @@
/**
* @brief Wraps up transmission in non blocking mode.
- * @param hsmartcard: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @param hsmartcard pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for the specified SMARTCARD module.
* @retval HAL status
*/
@@ -1631,7 +1631,7 @@
/**
* @brief Receive an amount of data in non blocking mode
- * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
* @retval HAL status
*/
@@ -1806,7 +1806,7 @@
/**
* @brief Configure the SMARTCARD peripheral
- * @param hsc: pointer to a SMARTCARD_HandleTypeDef structure that contains
+ * @param hsc pointer to a SMARTCARD_HandleTypeDef structure that contains
* the configuration information for SMARTCARD module.
* @retval None
*/
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_smartcard.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_smartcard.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_smartcard.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief Header file of SMARTCARD HAL module.
******************************************************************************
* @attention
@@ -390,7 +388,7 @@
*/
/** @brief Reset SMARTCARD handle gstate & RxState
- * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
* @retval None
*/
#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) do{ \
@@ -399,13 +397,13 @@
} while(0U)
/** @brief Flushs the Smartcard DR register
- * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
*/
#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
/** @brief Checks whether the specified Smartcard flag is set or not.
- * @param __HANDLE__: specifies the SMARTCARD Handle.
- * @param __FLAG__: specifies the flag to check.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg SMARTCARD_FLAG_TXE: Transmit data register empty flag
* @arg SMARTCARD_FLAG_TC: Transmission Complete flag
@@ -420,8 +418,8 @@
#define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
/** @brief Clears the specified Smartcard pending flags.
- * @param __HANDLE__: specifies the SMARTCARD Handle.
- * @param __FLAG__: specifies the flag to check.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @param __FLAG__ specifies the flag to check.
* This parameter can be any combination of the following values:
* @arg SMARTCARD_FLAG_TC: Transmission Complete flag.
* @arg SMARTCARD_FLAG_RXNE: Receive data register not empty flag.
@@ -437,7 +435,7 @@
#define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
/** @brief Clear the SMARTCARD PE pending flag.
- * @param __HANDLE__: specifies the USART Handle.
+ * @param __HANDLE__ specifies the USART Handle.
* This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* SMARTCARD peripheral.
* @retval None
@@ -451,7 +449,7 @@
} while(0U)
/** @brief Clear the SMARTCARD FE pending flag.
- * @param __HANDLE__: specifies the USART Handle.
+ * @param __HANDLE__ specifies the USART Handle.
* This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* SMARTCARD peripheral.
* @retval None
@@ -459,7 +457,7 @@
#define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
/** @brief Clear the SMARTCARD NE pending flag.
- * @param __HANDLE__: specifies the USART Handle.
+ * @param __HANDLE__ specifies the USART Handle.
* This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* SMARTCARD peripheral.
* @retval None
@@ -467,7 +465,7 @@
#define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
/** @brief Clear the SMARTCARD ORE pending flag.
- * @param __HANDLE__: specifies the USART Handle.
+ * @param __HANDLE__ specifies the USART Handle.
* This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* SMARTCARD peripheral.
* @retval None
@@ -475,7 +473,7 @@
#define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
/** @brief Clear the SMARTCARD IDLE pending flag.
- * @param __HANDLE__: specifies the USART Handle.
+ * @param __HANDLE__ specifies the USART Handle.
* This parameter can be USARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* SMARTCARD peripheral.
* @retval None
@@ -483,8 +481,8 @@
#define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__)
/** @brief Enables or disables the specified SmartCard interrupts.
- * @param __HANDLE__: specifies the SMARTCARD Handle.
- * @param __INTERRUPT__: specifies the SMARTCARD interrupt source to check.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @param __INTERRUPT__ specifies the SMARTCARD interrupt source to check.
* This parameter can be one of the following values:
* @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
* @arg SMARTCARD_IT_TC: Transmission complete interrupt
@@ -499,8 +497,8 @@
((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & SMARTCARD_IT_MASK)))
/** @brief Checks whether the specified SmartCard interrupt has occurred or not.
- * @param __HANDLE__: specifies the SmartCard Handle.
- * @param __IT__: specifies the SMARTCARD interrupt source to check.
+ * @param __HANDLE__ specifies the SmartCard Handle.
+ * @param __IT__ specifies the SMARTCARD interrupt source to check.
* This parameter can be one of the following values:
* @arg SMARTCARD_IT_TXE: Transmit Data Register empty interrupt
* @arg SMARTCARD_IT_TC: Transmission complete interrupt
@@ -513,34 +511,34 @@
#define __HAL_SMARTCARD_GET_IT_SOURCE(__HANDLE__, __IT__) (((((__IT__) >> 28U) == 1U)? (__HANDLE__)->Instance->CR1: (__HANDLE__)->Instance->CR3) & (((uint32_t)(__IT__)) & SMARTCARD_IT_MASK))
/** @brief Macro to enable the SMARTCARD's one bit sample method
- * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
* @retval None
*/
#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
/** @brief Macro to disable the SMARTCARD's one bit sample method
- * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
* @retval None
*/
#define __HAL_SMARTCARD_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
/** @brief Enable the USART associated to the SMARTCARD Handle
- * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @retval None
*/
#define __HAL_SMARTCARD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
/** @brief Disable the USART associated to the SMARTCARD Handle
- * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
* SMARTCARD Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @retval None
*/
#define __HAL_SMARTCARD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
/** @brief Macros to enable or disable the SmartCard DMA request.
- * @param __HANDLE__: specifies the SmartCard Handle.
- * @param __REQUEST__: specifies the SmartCard DMA request.
+ * @param __HANDLE__ specifies the SmartCard Handle.
+ * @param __REQUEST__ specifies the SmartCard DMA request.
* This parameter can be one of the following values:
* @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request
* @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_spdifrx.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_spdifrx.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_spdifrx.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief This file provides firmware functions to manage the following * functionalities of the SPDIFRX audio interface: * + Initialization and Configuration @@ -197,7 +195,7 @@ /** * @brief Initializes the SPDIFRX according to the specified parameters * in the SPDIFRX_InitTypeDef and create the associated handle. - * @param hspdif: SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval HAL status */ HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif) @@ -268,7 +266,7 @@ /** * @brief DeInitializes the SPDIFRX peripheral - * @param hspdif: SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval HAL status */ HAL_StatusTypeDef HAL_SPDIFRX_DeInit(SPDIFRX_HandleTypeDef *hspdif) @@ -303,7 +301,7 @@ /** * @brief SPDIFRX MSP Init - * @param hspdif: SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval None */ __weak void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif) @@ -317,7 +315,7 @@ /** * @brief SPDIFRX MSP DeInit - * @param hspdif: SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval None */ __weak void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif) @@ -332,8 +330,8 @@ /** * @brief Sets the SPDIFRX dtat format according to the specified parameters * in the SPDIFRX_InitTypeDef. - * @param hspdif: SPDIFRX handle - * @param sDataFormat: SPDIFRX data format + * @param hspdif SPDIFRX handle + * @param sDataFormat SPDIFRX data format * @retval HAL status */ HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef sDataFormat) @@ -428,11 +426,11 @@ /** * @brief Receives an amount of data (Data Flow) in blocking mode. - * @param hspdif: pointer to SPDIFRX_HandleTypeDef structure that contains + * @param hspdif pointer to SPDIFRX_HandleTypeDef structure that contains * the configuration information for SPDIFRX module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received - * @param Timeout: Timeout duration + * @param pData Pointer to data buffer + * @param Size Amount of data to be received + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout) @@ -490,11 +488,11 @@ /** * @brief Receives an amount of data (Control Flow) in blocking mode. - * @param hspdif: pointer to a SPDIFRX_HandleTypeDef structure that contains + * @param hspdif pointer to a SPDIFRX_HandleTypeDef structure that contains * the configuration information for SPDIFRX module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received - * @param Timeout: Timeout duration + * @param pData Pointer to data buffer + * @param Size Amount of data to be received + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout) @@ -551,9 +549,9 @@ } /** * @brief Receive an amount of data (Data Flow) in non-blocking mode with Interrupt - * @param hspdif: SPDIFRX handle - * @param pData: a 32-bit pointer to the Receive data buffer. - * @param Size: number of data sample to be received . + * @param hspdif SPDIFRX handle + * @param pData a 32-bit pointer to the Receive data buffer. + * @param Size number of data sample to be received . * @retval HAL status */ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size) @@ -634,9 +632,9 @@ /** * @brief Receive an amount of data (Control Flow) with Interrupt - * @param hspdif: SPDIFRX handle - * @param pData: a 32-bit pointer to the Receive data buffer. - * @param Size: number of data sample (Control Flow) to be received : + * @param hspdif SPDIFRX handle + * @param pData a 32-bit pointer to the Receive data buffer. + * @param Size number of data sample (Control Flow) to be received : * @retval HAL status */ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size) @@ -717,9 +715,9 @@ /** * @brief Receive an amount of data (Data Flow) mode with DMA - * @param hspdif: SPDIFRX handle - * @param pData: a 32-bit pointer to the Receive data buffer. - * @param Size: number of data sample to be received : + * @param hspdif SPDIFRX handle + * @param pData a 32-bit pointer to the Receive data buffer. + * @param Size number of data sample to be received : * @retval HAL status */ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size) @@ -804,9 +802,9 @@ /** * @brief Receive an amount of data (Control Flow) with DMA - * @param hspdif: SPDIFRX handle - * @param pData: a 32-bit pointer to the Receive data buffer. - * @param Size: number of data (Control Flow) sample to be received : + * @param hspdif SPDIFRX handle + * @param pData a 32-bit pointer to the Receive data buffer. + * @param Size number of data (Control Flow) sample to be received : * @retval HAL status */ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size) @@ -891,7 +889,7 @@ /** * @brief stop the audio stream receive from the Media. - * @param hspdif: SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval None */ HAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif) @@ -920,7 +918,7 @@ /** * @brief This function handles SPDIFRX interrupt request. - * @param hspdif: SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval HAL status */ void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif) @@ -966,7 +964,7 @@ /** * @brief Rx Transfer (Data flow) half completed callbacks - * @param hspdif: SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval None */ __weak void HAL_SPDIFRX_RxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif) @@ -980,7 +978,7 @@ /** * @brief Rx Transfer (Data flow) completed callbacks - * @param hspdif: SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval None */ __weak void HAL_SPDIFRX_RxCpltCallback(SPDIFRX_HandleTypeDef *hspdif) @@ -994,7 +992,7 @@ /** * @brief Rx (Control flow) Transfer half completed callbacks - * @param hspdif: SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval None */ __weak void HAL_SPDIFRX_CxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif) @@ -1008,7 +1006,7 @@ /** * @brief Rx Transfer (Control flow) completed callbacks - * @param hspdif: SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval None */ __weak void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif) @@ -1022,7 +1020,7 @@ /** * @brief SPDIFRX error callbacks - * @param hspdif: SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval None */ __weak void HAL_SPDIFRX_ErrorCallback(SPDIFRX_HandleTypeDef *hspdif) @@ -1055,7 +1053,7 @@ /** * @brief Return the SPDIFRX state - * @param hspdif : SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval HAL state */ HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef *hspdif) @@ -1065,7 +1063,7 @@ /** * @brief Return the SPDIFRX error code - * @param hspdif : SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval SPDIFRX Error Code */ uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef *hspdif) @@ -1079,7 +1077,7 @@ /** * @brief DMA SPDIFRX receive process (Data flow) complete callback - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma) @@ -1096,7 +1094,7 @@ /** * @brief DMA SPDIFRX receive process (Data flow) half complete callback - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void SPDIFRX_DMARxHalfCplt(DMA_HandleTypeDef *hdma) @@ -1108,7 +1106,7 @@ /** * @brief DMA SPDIFRX receive process (Control flow) complete callback - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void SPDIFRX_DMACxCplt(DMA_HandleTypeDef *hdma) @@ -1125,7 +1123,7 @@ /** * @brief DMA SPDIFRX receive process (Control flow) half complete callback - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma) @@ -1137,7 +1135,7 @@ /** * @brief DMA SPDIFRX communication error callback - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void SPDIFRX_DMAError(DMA_HandleTypeDef *hdma) @@ -1157,7 +1155,7 @@ /** * @brief Receive an amount of data (Data Flow) with Interrupt - * @param hspdif: SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval None */ static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif) @@ -1182,7 +1180,7 @@ /** * @brief Receive an amount of data (Control Flow) with Interrupt - * @param hspdif: SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval None */ static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif) @@ -1207,10 +1205,10 @@ /** * @brief This function handles SPDIFRX Communication Timeout. - * @param hspdif: SPDIFRX handle - * @param Flag: Flag checked - * @param Status: Value of the flag expected - * @param Timeout: Duration of the timeout + * @param hspdif SPDIFRX handle + * @param Flag Flag checked + * @param Status Value of the flag expected + * @param Timeout Duration of the timeout * @retval HAL status */ static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout)
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_spdifrx.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_spdifrx.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_spdifrx.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of SPDIFRX HAL module. ****************************************************************************** * @attention @@ -342,33 +340,33 @@ */ /** @brief Reset SPDIFRX handle state - * @param __HANDLE__: SPDIFRX handle. + * @param __HANDLE__ SPDIFRX handle. * @retval None */ #define __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = (uint16_t)SPDIFRX_CR_SPDIFEN) /** @brief Disable the specified SPDIFRX peripheral (IDLE State). - * @param __HANDLE__: specifies the SPDIFRX Handle. + * @param __HANDLE__ specifies the SPDIFRX Handle. * @retval None */ #define __HAL_SPDIFRX_IDLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= SPDIFRX_STATE_IDLE) /** @brief Enable the specified SPDIFRX peripheral (SYNC State). - * @param __HANDLE__: specifies the SPDIFRX Handle. + * @param __HANDLE__ specifies the SPDIFRX Handle. * @retval None */ #define __HAL_SPDIFRX_SYNC(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_SYNC) /** @brief Enable the specified SPDIFRX peripheral (RCV State). - * @param __HANDLE__: specifies the SPDIFRX Handle. + * @param __HANDLE__ specifies the SPDIFRX Handle. * @retval None */ #define __HAL_SPDIFRX_RCV(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_RCV) /** @brief Enable or disable the specified SPDIFRX interrupts. - * @param __HANDLE__: specifies the SPDIFRX Handle. - * @param __INTERRUPT__: specifies the interrupt source to enable or disable. + * @param __HANDLE__ specifies the SPDIFRX Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable or disable. * This parameter can be one of the following values: * @arg SPDIFRX_IT_RXNE * @arg SPDIFRX_IT_CSRNE @@ -383,8 +381,8 @@ #define __HAL_SPDIFRX_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (uint16_t)(~(__INTERRUPT__))) /** @brief Checks if the specified SPDIFRX interrupt source is enabled or disabled. - * @param __HANDLE__: specifies the SPDIFRX Handle. - * @param __INTERRUPT__: specifies the SPDIFRX interrupt source to check. + * @param __HANDLE__ specifies the SPDIFRX Handle. + * @param __INTERRUPT__ specifies the SPDIFRX interrupt source to check. * This parameter can be one of the following values: * @arg SPDIFRX_IT_RXNE * @arg SPDIFRX_IT_CSRNE @@ -398,8 +396,8 @@ #define __HAL_SPDIFRX_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Checks whether the specified SPDIFRX flag is set or not. - * @param __HANDLE__: specifies the SPDIFRX Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the SPDIFRX Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg SPDIFRX_FLAG_RXNE * @arg SPDIFRX_FLAG_CSRNE @@ -415,8 +413,8 @@ #define __HAL_SPDIFRX_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) /** @brief Clears the specified SPDIFRX SR flag, in setting the proper IFCR register bit. - * @param __HANDLE__: specifies the USART Handle. - * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set + * @param __HANDLE__ specifies the USART Handle. + * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set * to clear the corresponding interrupt * This parameter can be one of the following values: * @arg SPDIFRX_FLAG_PERR
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_spi.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_spi.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_spi.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief SPI HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Serial Peripheral Interface (SPI) peripheral:
@@ -191,7 +189,9 @@
static void SPI_DMATxAbortCallback(DMA_HandleTypeDef *hdma);
static void SPI_DMARxAbortCallback(DMA_HandleTypeDef *hdma);
static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart);
+/* MBED */
static HAL_StatusTypeDef SPI_WaitTXEFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart);
+/* MBED */
static void SPI_TxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
static void SPI_TxISR_16BIT(struct __SPI_HandleTypeDef *hspi);
static void SPI_RxISR_8BIT(struct __SPI_HandleTypeDef *hspi);
@@ -257,7 +257,7 @@
/**
* @brief Initialize the SPI according to the specified parameters
* in the SPI_InitTypeDef and initialize the associated handle.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval HAL status
*/
@@ -339,7 +339,7 @@
/**
* @brief De Initialize the SPI peripheral.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval HAL status
*/
@@ -373,7 +373,7 @@
/**
* @brief Initialize the SPI MSP.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -388,7 +388,7 @@
/**
* @brief De-Initialize the SPI MSP.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -440,11 +440,11 @@
/**
* @brief Transmit an amount of data in blocking mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
- * @param Timeout: Timeout duration
+ * @param pData pointer to data buffer
+ * @param Size amount of data to be sent
+ * @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
@@ -569,7 +569,9 @@
}
/* Wait until TXE flag */
+/* MBED */
if(SPI_WaitTXEFlagStateUntilTimeout(hspi, Timeout, tickstart) != HAL_OK)
+/* MBED */
{
errorcode = HAL_TIMEOUT;
goto error;
@@ -610,11 +612,11 @@
/**
* @brief Receive an amount of data in blocking mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be received
- * @param Timeout: Timeout duration
+ * @param pData pointer to data buffer
+ * @param Size amount of data to be received
+ * @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
@@ -806,12 +808,12 @@
/**
* @brief Transmit and Receive an amount of data in blocking mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
- * @param pTxData: pointer to transmission data buffer
- * @param pRxData: pointer to reception data buffer
- * @param Size: amount of data to be sent and received
- * @param Timeout: Timeout duration
+ * @param pTxData pointer to transmission data buffer
+ * @param pRxData pointer to reception data buffer
+ * @param Size amount of data to be sent and received
+ * @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
@@ -1003,7 +1005,9 @@
#endif /* USE_SPI_CRC */
/* Wait until TXE flag */
+/* MBED */
if(SPI_WaitTXEFlagStateUntilTimeout(hspi, Timeout, tickstart) != HAL_OK)
+/* MBED */
{
errorcode = HAL_TIMEOUT;
goto error;
@@ -1031,10 +1035,10 @@
/**
* @brief Transmit an amount of data in non-blocking mode with Interrupt.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
+ * @param pData pointer to data buffer
+ * @param Size amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
@@ -1121,10 +1125,10 @@
/**
* @brief Receive an amount of data in non-blocking mode with Interrupt.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
+ * @param pData pointer to data buffer
+ * @param Size amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
@@ -1212,11 +1216,11 @@
/**
* @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
- * @param pTxData: pointer to transmission data buffer
- * @param pRxData: pointer to reception data buffer
- * @param Size: amount of data to be sent and received
+ * @param pTxData pointer to transmission data buffer
+ * @param pRxData pointer to reception data buffer
+ * @param Size amount of data to be sent and received
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
@@ -1299,10 +1303,10 @@
/**
* @brief Transmit an amount of data in non-blocking mode with DMA.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
+ * @param pData pointer to data buffer
+ * @param Size amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
@@ -1391,11 +1395,11 @@
/**
* @brief Receive an amount of data in non-blocking mode with DMA.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
- * @param pData: pointer to data buffer
+ * @param pData pointer to data buffer
* @note When the CRC feature is enabled the pData Length must be Size + 1.
- * @param Size: amount of data to be sent
+ * @param Size amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
@@ -1487,12 +1491,12 @@
/**
* @brief Transmit and Receive an amount of data in non-blocking mode with DMA.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
- * @param pTxData: pointer to transmission data buffer
- * @param pRxData: pointer to reception data buffer
+ * @param pTxData pointer to transmission data buffer
+ * @param pRxData pointer to reception data buffer
* @note When the CRC feature is enabled the pRxData Length must be Size + 1
- * @param Size: amount of data to be sent
+ * @param Size amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
@@ -1856,7 +1860,7 @@
/**
* @brief Pause the DMA Transfer.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for the specified SPI module.
* @retval HAL status
*/
@@ -1876,7 +1880,7 @@
/**
* @brief Resume the DMA Transfer.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for the specified SPI module.
* @retval HAL status
*/
@@ -1896,7 +1900,7 @@
/**
* @brief Stop the DMA Transfer.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for the specified SPI module.
* @retval HAL status
*/
@@ -1927,7 +1931,7 @@
/**
* @brief Handle SPI interrupt request.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for the specified SPI module.
* @retval None
*/
@@ -2023,7 +2027,7 @@
/**
* @brief Tx Transfer completed callback.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -2038,7 +2042,7 @@
/**
* @brief Rx Transfer completed callback.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -2053,7 +2057,7 @@
/**
* @brief Tx and Rx Transfer completed callback.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -2068,7 +2072,7 @@
/**
* @brief Tx Half Transfer completed callback.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -2083,7 +2087,7 @@
/**
* @brief Rx Half Transfer completed callback.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -2098,7 +2102,7 @@
/**
* @brief Tx and Rx Half Transfer callback.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -2113,7 +2117,7 @@
/**
* @brief SPI error callback.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -2165,7 +2169,7 @@
/**
* @brief Return the SPI handle state.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval SPI state
*/
@@ -2177,7 +2181,7 @@
/**
* @brief Return the SPI error code.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval SPI error code in bitmap format
*/
@@ -2202,7 +2206,7 @@
/**
* @brief DMA SPI transmit process complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -2246,7 +2250,7 @@
/**
* @brief DMA SPI receive process complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -2313,7 +2317,7 @@
/**
* @brief DMA SPI transmit receive process complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -2377,7 +2381,7 @@
/**
* @brief DMA SPI half transmit process complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -2390,7 +2394,7 @@
/**
* @brief DMA SPI half receive process complete callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -2403,7 +2407,7 @@
/**
* @brief DMA SPI half transmit receive process complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -2416,7 +2420,7 @@
/**
* @brief DMA SPI communication error callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -2551,7 +2555,7 @@
/**
* @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -2585,7 +2589,7 @@
#if (USE_SPI_CRC != 0U)
/**
* @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -2612,7 +2616,7 @@
/**
* @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -2645,7 +2649,7 @@
/**
* @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -2679,7 +2683,7 @@
#if (USE_SPI_CRC != 0U)
/**
* @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -2703,7 +2707,7 @@
/**
* @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -2739,7 +2743,7 @@
#if (USE_SPI_CRC != 0U)
/**
* @brief Manage the CRC 8-bit receive in Interrupt context.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -2759,7 +2763,7 @@
/**
* @brief Manage the receive 8-bit in Interrupt context.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -2792,7 +2796,7 @@
#if (USE_SPI_CRC != 0U)
/**
* @brief Manage the CRC 16-bit receive in Interrupt context.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -2815,7 +2819,7 @@
/**
* @brief Manage the 16-bit receive in Interrupt context.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -2848,7 +2852,7 @@
/**
* @brief Handle the data 8-bit transmit in Interrupt mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -2866,14 +2870,16 @@
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
#endif /* USE_SPI_CRC */
+/* MBED */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE));
+/* MBED */
SPI_CloseTx_ISR(hspi);
}
}
/**
* @brief Handle the data 16-bit transmit in Interrupt mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -2893,24 +2899,28 @@
SET_BIT(hspi->Instance->CR1, SPI_CR1_CRCNEXT);
}
#endif /* USE_SPI_CRC */
+/* MBED */
__HAL_SPI_DISABLE_IT(hspi, (SPI_IT_TXE));
+/* MBED */
SPI_CloseTx_ISR(hspi);
}
}
/**
* @brief Handle SPI Communication Timeout.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
- * @param Flag: SPI flag to check
- * @param State: flag state to check
- * @param Timeout: Timeout duration
- * @param Tickstart: tick start value
+ * @param Flag SPI flag to check
+ * @param State flag state to check
+ * @param Timeout Timeout duration
+ * @param Tickstart tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State, uint32_t Timeout, uint32_t Tickstart)
{
+/* MBED */
while((hspi->Instance->SR & Flag) != State)
+/* MBED */
{
if(Timeout != HAL_MAX_DELAY)
{
@@ -2948,6 +2958,7 @@
return HAL_OK;
}
+/* MBED */
/**
* @brief Handle SPI Communication Timeout.
* @param hspi: pointer to a SPI_HandleTypeDef structure that contains
@@ -2997,13 +3008,14 @@
return HAL_OK;
}
+/* MBED */
/**
* @brief Handle to check BSY flag before start a new transaction.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
- * @param Timeout: Timeout duration
- * @param Tickstart: tick start value
+ * @param Timeout Timeout duration
+ * @param Tickstart tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef SPI_CheckFlag_BSY(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
@@ -3019,7 +3031,7 @@
/**
* @brief Handle the end of the RXTX transaction.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -3093,7 +3105,7 @@
/**
* @brief Handle the end of the RX transaction.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -3142,7 +3154,7 @@
/**
* @brief Handle the end of the TX transaction.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -3197,7 +3209,7 @@
/**
* @brief Handle abort a Tx or Rx transaction.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -3232,7 +3244,7 @@
/**
* @brief Handle abort a Tx or Rx transaction.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_spi.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_spi.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_spi.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of SPI HAL module. ****************************************************************************** * @attention @@ -308,16 +306,16 @@ */ /** @brief Reset SPI handle state. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) /** @brief Enable or disable the specified SPI interrupts. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @param __INTERRUPT__: specifies the interrupt source to enable or disable. + * @param __INTERRUPT__ specifies the interrupt source to enable or disable. * This parameter can be one of the following values: * @arg SPI_IT_TXE: Tx buffer empty interrupt enable * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable @@ -328,9 +326,9 @@ #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__))) /** @brief Check whether the specified SPI interrupt source is enabled or not. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @param __INTERRUPT__: specifies the SPI interrupt source to check. + * @param __INTERRUPT__ specifies the SPI interrupt source to check. * This parameter can be one of the following values: * @arg SPI_IT_TXE: Tx buffer empty interrupt enable * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable @@ -340,9 +338,9 @@ #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Check whether the specified SPI flag is set or not. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @param __FLAG__: specifies the flag to check. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg SPI_FLAG_RXNE: Receive buffer not empty flag * @arg SPI_FLAG_TXE: Transmit buffer empty flag @@ -356,14 +354,14 @@ #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) /** @brief Clear the SPI CRCERR pending flag. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR)) /** @brief Clear the SPI MODF pending flag. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ @@ -376,7 +374,7 @@ } while(0U) /** @brief Clear the SPI OVR pending flag. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ @@ -389,7 +387,7 @@ } while(0U) /** @brief Clear the SPI FRE pending flag. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ @@ -401,14 +399,14 @@ }while(0U) /** @brief Enable the SPI peripheral. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE) /** @brief Disable the SPI peripheral. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ @@ -491,21 +489,21 @@ */ /** @brief Set the SPI transmit-only mode. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE) /** @brief Set the SPI receive-only mode. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE)) /** @brief Reset the CRC calculation of the SPI. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sram.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sram.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_sram.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief SRAM HAL module driver.
* This file provides a generic firmware to drive SRAM memories
* mounted as external device.
@@ -135,10 +133,10 @@
/**
* @brief Performs the SRAM device initialization sequence
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
- * @param Timing: Pointer to SRAM control timing structure
- * @param ExtTiming: Pointer to SRAM extended mode timing structure
+ * @param Timing Pointer to SRAM control timing structure
+ * @param ExtTiming Pointer to SRAM extended mode timing structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
@@ -174,7 +172,7 @@
/**
* @brief Performs the SRAM device De-initialization sequence.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @retval HAL status
*/
@@ -196,7 +194,7 @@
/**
* @brief SRAM MSP Init.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @retval None
*/
@@ -211,7 +209,7 @@
/**
* @brief SRAM MSP DeInit.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @retval None
*/
@@ -226,7 +224,7 @@
/**
* @brief DMA transfer complete callback.
- * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
+ * @param hdma pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @retval None
*/
@@ -241,7 +239,7 @@
/**
* @brief DMA transfer complete error callback.
- * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
+ * @param hdma pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @retval None
*/
@@ -274,11 +272,11 @@
/**
* @brief Reads 8-bit buffer from SRAM memory.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
- * @param pAddress: Pointer to read start address
- * @param pDstBuffer: Pointer to destination buffer
- * @param BufferSize: Size of the buffer to read from memory
+ * @param pAddress Pointer to read start address
+ * @param pDstBuffer Pointer to destination buffer
+ * @param BufferSize Size of the buffer to read from memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
@@ -310,11 +308,11 @@
/**
* @brief Writes 8-bit buffer to SRAM memory.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
- * @param pAddress: Pointer to write start address
- * @param pSrcBuffer: Pointer to source buffer to write
- * @param BufferSize: Size of the buffer to write to memory
+ * @param pAddress Pointer to write start address
+ * @param pSrcBuffer Pointer to source buffer to write
+ * @param BufferSize Size of the buffer to write to memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
@@ -352,11 +350,11 @@
/**
* @brief Reads 16-bit buffer from SRAM memory.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
- * @param pAddress: Pointer to read start address
- * @param pDstBuffer: Pointer to destination buffer
- * @param BufferSize: Size of the buffer to read from memory
+ * @param pAddress Pointer to read start address
+ * @param pDstBuffer Pointer to destination buffer
+ * @param BufferSize Size of the buffer to read from memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
@@ -388,11 +386,11 @@
/**
* @brief Writes 16-bit buffer to SRAM memory.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
- * @param pAddress: Pointer to write start address
- * @param pSrcBuffer: Pointer to source buffer to write
- * @param BufferSize: Size of the buffer to write to memory
+ * @param pAddress Pointer to write start address
+ * @param pSrcBuffer Pointer to source buffer to write
+ * @param BufferSize Size of the buffer to write to memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
@@ -430,11 +428,11 @@
/**
* @brief Reads 32-bit buffer from SRAM memory.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
- * @param pAddress: Pointer to read start address
- * @param pDstBuffer: Pointer to destination buffer
- * @param BufferSize: Size of the buffer to read from memory
+ * @param pAddress Pointer to read start address
+ * @param pDstBuffer Pointer to destination buffer
+ * @param BufferSize Size of the buffer to read from memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
@@ -464,11 +462,11 @@
/**
* @brief Writes 32-bit buffer to SRAM memory.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
- * @param pAddress: Pointer to write start address
- * @param pSrcBuffer: Pointer to source buffer to write
- * @param BufferSize: Size of the buffer to write to memory
+ * @param pAddress Pointer to write start address
+ * @param pSrcBuffer Pointer to source buffer to write
+ * @param BufferSize Size of the buffer to write to memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
@@ -504,11 +502,11 @@
/**
* @brief Reads a Words data from the SRAM memory using DMA transfer.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
- * @param pAddress: Pointer to read start address
- * @param pDstBuffer: Pointer to destination buffer
- * @param BufferSize: Size of the buffer to read from memory
+ * @param pAddress Pointer to read start address
+ * @param pDstBuffer Pointer to destination buffer
+ * @param BufferSize Size of the buffer to read from memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
@@ -537,11 +535,11 @@
/**
* @brief Writes a Words data buffer to SRAM memory using DMA transfer.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
- * @param pAddress: Pointer to write start address
- * @param pSrcBuffer: Pointer to source buffer to write
- * @param BufferSize: Size of the buffer to write to memory
+ * @param pAddress Pointer to write start address
+ * @param pSrcBuffer Pointer to source buffer to write
+ * @param BufferSize Size of the buffer to write to memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
@@ -595,7 +593,7 @@
/**
* @brief Enables dynamically SRAM write operation.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @retval HAL status
*/
@@ -618,7 +616,7 @@
/**
* @brief Disables dynamically SRAM write operation.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @retval HAL status
*/
@@ -663,7 +661,7 @@
/**
* @brief Returns the SRAM controller state
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @retval HAL state
*/
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sram.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_sram.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_sram.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief Header file of SRAM HAL module.
******************************************************************************
* @attention
@@ -116,7 +114,7 @@
* @{
*/
/** @brief Reset SRAM handle state
- * @param __HANDLE__: SRAM handle
+ * @param __HANDLE__ SRAM handle
* @retval None
*/
#define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_tim.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_tim.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_tim.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief TIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Timer (TIM) peripheral: @@ -201,7 +199,7 @@ /** * @brief Initializes the TIM Time base Unit according to the specified * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -240,7 +238,7 @@ /** * @brief DeInitializes the TIM Base peripheral - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -268,7 +266,7 @@ /** * @brief Initializes the TIM Base MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -283,7 +281,7 @@ /** * @brief DeInitializes TIM Base MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -298,7 +296,7 @@ /** * @brief Starts the TIM Base generation. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -322,7 +320,7 @@ /** * @brief Stops the TIM Base generation. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -346,7 +344,7 @@ /** * @brief Starts the TIM Base generation in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -367,7 +365,7 @@ /** * @brief Stops the TIM Base generation in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -387,10 +385,10 @@ /** * @brief Starts the TIM Base generation in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param pData: The source Buffer address. - * @param Length: The length of data to be transferred from memory to peripheral. + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to peripheral. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) @@ -434,7 +432,7 @@ /** * @brief Stops the TIM Base generation in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -483,7 +481,7 @@ /** * @brief Initializes the TIM Output Compare according to the specified * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -522,7 +520,7 @@ /** * @brief DeInitializes the TIM peripheral - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -550,7 +548,7 @@ /** * @brief Initializes the TIM Output Compare MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -565,7 +563,7 @@ /** * @brief DeInitializes TIM Output Compare MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -580,9 +578,9 @@ /** * @brief Starts the TIM Output Compare signal generation. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be enabled. + * @param Channel TIM Channel to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -613,9 +611,9 @@ /** * @brief Stops the TIM Output Compare signal generation. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be disabled. + * @param Channel TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -646,9 +644,9 @@ /** * @brief Starts the TIM Output Compare signal generation in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be enabled. + * @param Channel TIM Channel to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -713,9 +711,9 @@ /** * @brief Stops the TIM Output Compare signal generation in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be disabled. + * @param Channel TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -780,16 +778,16 @@ /** * @brief Starts the TIM Output Compare signal generation in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be enabled. + * @param Channel TIM Channel to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData: The source Buffer address. - * @param Length: The length of data to be transferred from memory to TIM peripheral + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) @@ -900,9 +898,9 @@ /** * @brief Stops the TIM Output Compare signal generation in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be disabled. + * @param Channel TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -995,7 +993,7 @@ /** * @brief Initializes the TIM PWM Time Base according to the specified * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -1034,7 +1032,7 @@ /** * @brief DeInitializes the TIM peripheral - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -1062,7 +1060,7 @@ /** * @brief Initializes the TIM PWM MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -1077,7 +1075,7 @@ /** * @brief DeInitializes TIM PWM MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -1092,9 +1090,9 @@ /** * @brief Starts the PWM signal generation. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be enabled. + * @param Channel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1125,9 +1123,9 @@ /** * @brief Stops the PWM signal generation. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be disabled. + * @param Channel TIM Channels to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1161,9 +1159,9 @@ /** * @brief Starts the PWM signal generation in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be enabled. + * @param Channel TIM Channel to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1228,9 +1226,9 @@ /** * @brief Stops the PWM signal generation in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be disabled. + * @param Channel TIM Channels to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1295,16 +1293,16 @@ /** * @brief Starts the TIM PWM signal generation in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be enabled. + * @param Channel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData: The source Buffer address. - * @param Length: The length of data to be transferred from memory to TIM peripheral + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) @@ -1415,9 +1413,9 @@ /** * @brief Stops the TIM PWM signal generation in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be disabled. + * @param Channel TIM Channels to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1510,7 +1508,7 @@ /** * @brief Initializes the TIM Input Capture Time base according to the specified * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -1549,7 +1547,7 @@ /** * @brief DeInitializes the TIM peripheral - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -1577,7 +1575,7 @@ /** * @brief Initializes the TIM INput Capture MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -1592,7 +1590,7 @@ /** * @brief DeInitializes TIM Input Capture MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -1607,9 +1605,9 @@ /** * @brief Starts the TIM Input Capture measurement. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be enabled. + * @param Channel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1634,9 +1632,9 @@ /** * @brief Stops the TIM Input Capture measurement. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be disabled. + * @param Channel TIM Channels to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1661,9 +1659,9 @@ /** * @brief Starts the TIM Input Capture measurement in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be enabled. + * @param Channel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1721,9 +1719,9 @@ /** * @brief Stops the TIM Input Capture measurement in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be disabled. + * @param Channel TIM Channels to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1782,16 +1780,16 @@ /** * @brief Starts the TIM Input Capture measurement on in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be enabled. + * @param Channel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData: The destination Buffer address. - * @param Length: The length of data to be transferred from TIM peripheral to memory. + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) @@ -1898,9 +1896,9 @@ /** * @brief Stops the TIM Input Capture measurement on in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be disabled. + * @param Channel TIM Channels to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1988,9 +1986,9 @@ /** * @brief Initializes the TIM One Pulse Time Base according to the specified * parameters in the TIM_HandleTypeDef and create the associated handle. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param OnePulseMode: Select the One pulse mode. + * @param OnePulseMode Select the One pulse mode. * This parameter can be one of the following values: * @arg TIM_OPMODE_SINGLE: Only one pulse will be generated. * @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated. @@ -2038,7 +2036,7 @@ /** * @brief DeInitializes the TIM One Pulse - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -2066,7 +2064,7 @@ /** * @brief Initializes the TIM One Pulse MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -2081,7 +2079,7 @@ /** * @brief DeInitializes TIM One Pulse MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -2096,9 +2094,9 @@ /** * @brief Starts the TIM One Pulse signal generation. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param OutputChannel : TIM Channels to be enabled. + * @param OutputChannel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2133,9 +2131,9 @@ /** * @brief Stops the TIM One Pulse signal generation. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param OutputChannel : TIM Channels to be disable. + * @param OutputChannel TIM Channels to be disable. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2170,9 +2168,9 @@ /** * @brief Starts the TIM One Pulse signal generation in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param OutputChannel : TIM Channels to be enabled. + * @param OutputChannel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2213,9 +2211,9 @@ /** * @brief Stops the TIM One Pulse signal generation in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param OutputChannel : TIM Channels to be enabled. + * @param OutputChannel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2279,9 +2277,9 @@ */ /** * @brief Initializes the TIM Encoder Interface and create the associated handle. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param sConfig: TIM Encoder Interface configuration structure + * @param sConfig TIM Encoder Interface configuration structure * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig) @@ -2369,7 +2367,7 @@ /** * @brief DeInitializes the TIM Encoder interface - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -2397,7 +2395,7 @@ /** * @brief Initializes the TIM Encoder Interface MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -2412,7 +2410,7 @@ /** * @brief DeInitializes TIM Encoder Interface MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -2427,9 +2425,9 @@ /** * @brief Starts the TIM Encoder Interface. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be enabled. + * @param Channel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2470,9 +2468,9 @@ /** * @brief Stops the TIM Encoder Interface. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be disabled. + * @param Channel TIM Channels to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2514,9 +2512,9 @@ /** * @brief Starts the TIM Encoder Interface in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be enabled. + * @param Channel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2563,9 +2561,9 @@ /** * @brief Stops the TIM Encoder Interface in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be disabled. + * @param Channel TIM Channels to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2615,16 +2613,16 @@ /** * @brief Starts the TIM Encoder Interface in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be enabled. + * @param Channel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected - * @param pData1: The destination Buffer address for IC1. - * @param pData2: The destination Buffer address for IC2. - * @param Length: The length of data to be transferred from TIM peripheral to memory. + * @param pData1 The destination Buffer address for IC1. + * @param pData2 The destination Buffer address for IC2. + * @param Length The length of data to be transferred from TIM peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length) @@ -2736,9 +2734,9 @@ /** * @brief Stops the TIM Encoder Interface in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be enabled. + * @param Channel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -2804,7 +2802,7 @@ */ /** * @brief This function handles TIM interrupts requests. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -2960,10 +2958,10 @@ /** * @brief Initializes the TIM Output Compare Channels according to the specified * parameters in the TIM_OC_InitTypeDef. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param sConfig: TIM Output Compare configuration structure - * @param Channel: TIM Channels to be enabled. + * @param sConfig TIM Output Compare configuration structure + * @param Channel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -3030,10 +3028,10 @@ /** * @brief Initializes the TIM Input Capture Channels according to the specified * parameters in the TIM_IC_InitTypeDef. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param sConfig: TIM Input Capture configuration structure - * @param Channel: TIM Channels to be enabled. + * @param sConfig TIM Input Capture configuration structure + * @param Channel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -3127,10 +3125,10 @@ /** * @brief Initializes the TIM PWM channels according to the specified * parameters in the TIM_OC_InitTypeDef. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param sConfig: TIM PWM configuration structure - * @param Channel: TIM Channels to be enabled. + * @param sConfig TIM PWM configuration structure + * @param Channel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -3226,14 +3224,14 @@ /** * @brief Initializes the TIM One Pulse Channels according to the specified * parameters in the TIM_OnePulse_InitTypeDef. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param sConfig: TIM One Pulse configuration structure - * @param OutputChannel: TIM Channels to be enabled. + * @param sConfig TIM One Pulse configuration structure + * @param OutputChannel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected - * @param InputChannel: TIM Channels to be enabled. + * @param InputChannel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -3339,9 +3337,9 @@ /** * @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write. + * @param BurstBaseAddress TIM Base address from when the DMA will starts the Data write. * This parameters can be on of the following values: * @arg TIM_DMABASE_CR1 * @arg TIM_DMABASE_CR2 @@ -3362,7 +3360,7 @@ * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR * @arg TIM_DMABASE_DCR - * @param BurstRequestSrc: TIM DMA Request sources. + * @param BurstRequestSrc TIM DMA Request sources. * This parameters can be on of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source @@ -3371,8 +3369,8 @@ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source * @arg TIM_DMA_COM: TIM Commutation DMA source * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer: The Buffer address. - * @param BurstLength: DMA Burst length. This parameter can be one value + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. * @retval HAL status */ @@ -3503,9 +3501,9 @@ /** * @brief Stops the TIM DMA Burst mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param BurstRequestSrc: TIM DMA Request sources to disable + * @param BurstRequestSrc TIM DMA Request sources to disable * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) @@ -3564,9 +3562,9 @@ /** * @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read. + * @param BurstBaseAddress TIM Base address from when the DMA will starts the Data read. * This parameters can be on of the following values: * @arg TIM_DMABASE_CR1 * @arg TIM_DMABASE_CR2 @@ -3587,7 +3585,7 @@ * @arg TIM_DMABASE_CCR4 * @arg TIM_DMABASE_BDTR * @arg TIM_DMABASE_DCR - * @param BurstRequestSrc: TIM DMA Request sources. + * @param BurstRequestSrc TIM DMA Request sources. * This parameters can be on of the following values: * @arg TIM_DMA_UPDATE: TIM update Interrupt source * @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source @@ -3596,8 +3594,8 @@ * @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source * @arg TIM_DMA_COM: TIM Commutation DMA source * @arg TIM_DMA_TRIGGER: TIM Trigger DMA source - * @param BurstBuffer: The Buffer address. - * @param BurstLength: DMA Burst length. This parameter can be one value + * @param BurstBuffer The Buffer address. + * @param BurstLength DMA Burst length. This parameter can be one value * between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS. * @retval HAL status */ @@ -3729,9 +3727,9 @@ /** * @brief Stop the DMA burst reading - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param BurstRequestSrc: TIM DMA Request sources to disable. + * @param BurstRequestSrc TIM DMA Request sources to disable. * @retval HAL status */ HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc) @@ -3790,9 +3788,9 @@ /** * @brief Generate a software event - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param EventSource: specifies the event source. + * @param EventSource specifies the event source. * This parameter can be one of the following values: * @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source * @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source @@ -3833,11 +3831,11 @@ /** * @brief Configures the OCRef clear feature - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that + * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that * contains the OCREF clear feature and parameters for the TIM peripheral. - * @param Channel: specifies the TIM Channel. + * @param Channel specifies the TIM Channel. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -3942,9 +3940,9 @@ /** * @brief Configures the clock source to be used - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that + * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that * contains the clock source information for the TIM peripheral. * @retval HAL status */ @@ -4099,9 +4097,9 @@ /** * @brief Selects the signal connected to the TI1 input: direct from CH1_input * or a XOR combination between CH1_input, CH2_input & CH3_input - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param TI1_Selection: Indicate whether or not channel 1 is connected to the + * @param TI1_Selection Indicate whether or not channel 1 is connected to the * output of a XOR gate. * This parameter can be one of the following values: * @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input @@ -4134,9 +4132,9 @@ /** * @brief Configures the TIM in Slave mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that * contains the selected trigger (internal trigger input, filtered * timer input or external trigger input) and the ) and the Slave * mode (Disable, Reset, Gated, Trigger, External clock mode 1). @@ -4170,8 +4168,8 @@ /** * @brief Configures the TIM in Slave mode in interrupt mode - * @param htim: TIM handle. - * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that + * @param htim TIM handle. + * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that * contains the selected trigger (internal trigger input, filtered * timer input or external trigger input) and the ) and the Slave * mode (Disable, Reset, Gated, Trigger, External clock mode 1). @@ -4206,9 +4204,9 @@ /** * @brief Read the captured value from Capture Compare unit - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channels to be enabled. + * @param Channel TIM Channels to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -4299,7 +4297,7 @@ /** * @brief Period elapsed callback in non blocking mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -4314,7 +4312,7 @@ /** * @brief Output Compare callback in non blocking mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -4329,7 +4327,7 @@ /** * @brief Input Capture callback in non blocking mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -4344,7 +4342,7 @@ /** * @brief PWM Pulse finished callback in non blocking mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -4359,7 +4357,7 @@ /** * @brief Hall Trigger detection callback in non blocking mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -4374,7 +4372,7 @@ /** * @brief Timer error callback in non blocking mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -4407,7 +4405,7 @@ /** * @brief Return the TIM Base state - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL state */ @@ -4418,7 +4416,7 @@ /** * @brief Return the TIM OC state - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL state */ @@ -4429,7 +4427,7 @@ /** * @brief Return the TIM PWM state - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL state */ @@ -4440,7 +4438,7 @@ /** * @brief Return the TIM Input Capture state - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL state */ @@ -4451,7 +4449,7 @@ /** * @brief Return the TIM One Pulse Mode state - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL state */ @@ -4462,7 +4460,7 @@ /** * @brief Return the TIM Encoder Mode state - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL state */ @@ -4476,8 +4474,8 @@ /** * @brief Time Base configuration - * @param TIMx: TIM peripheral - * @param Structure: pointer on TIM Time Base required parameters + * @param TIMx TIM peripheral + * @param Structure pointer on TIM Time Base required parameters * @retval None */ void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure) @@ -4522,17 +4520,17 @@ /** * @brief Configure the TI1 as Input. * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPolarity_Rising * @arg TIM_ICPolarity_Falling * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. + * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1. * @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2. * @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1 * (on channel2 path) is used as the input signal. Therefore CCMR1 must be @@ -4578,7 +4576,7 @@ /** * @brief Time Output Compare 2 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config: The output configuration structure + * @param OC_Config The output configuration structure * @retval None */ void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -4644,7 +4642,7 @@ /** * @brief TIM DMA Delay Pulse complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -4678,7 +4676,7 @@ /** * @brief TIM DMA error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -4693,7 +4691,7 @@ /** * @brief TIM DMA Capture complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -4728,13 +4726,13 @@ /** * @brief Enables or disables the TIM Capture Compare Channel x. * @param TIMx to select the TIM peripheral - * @param Channel: specifies the TIM Channel + * @param Channel specifies the TIM Channel * This parameter can be one of the following values: * @arg TIM_Channel_1: TIM Channel 1 * @arg TIM_Channel_2: TIM Channel 2 * @arg TIM_Channel_3: TIM Channel 3 * @arg TIM_Channel_4: TIM Channel 4 - * @param ChannelState: specifies the TIM Channel CCxE bit new state. + * @param ChannelState specifies the TIM Channel CCxE bit new state. * This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable. * @retval None */ @@ -4757,7 +4755,7 @@ /** * @brief TIM DMA Period Elapse complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -4772,7 +4770,7 @@ /** * @brief TIM DMA Trigger callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -4788,7 +4786,7 @@ /** * @brief Time Output Compare 1 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config: The output configuration structure + * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -4853,7 +4851,7 @@ /** * @brief Time Output Compare 3 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config: The output configuration structure + * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -4921,7 +4919,7 @@ /** * @brief Time Output Compare 4 configuration * @param TIMx to select the TIM peripheral - * @param OC_Config: The output configuration structure + * @param OC_Config The output configuration structure * @retval None */ static void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config) @@ -4977,9 +4975,9 @@ /** * @brief Time Output Compare 4 configuration - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param sSlaveConfig: The slave configuration structure + * @param sSlaveConfig The slave configuration structure * @retval None */ static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim, @@ -5110,12 +5108,12 @@ /** * @brief Configure the Polarity and Filter for TI1. * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPolarity_Rising * @arg TIM_ICPolarity_Falling * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICFilter: Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ @@ -5145,17 +5143,17 @@ /** * @brief Configure the TI2 as Input. * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPolarity_Rising * @arg TIM_ICPolarity_Falling * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. + * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2. * @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1. * @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2 * (on channel1 path) is used as the input signal. Therefore CCMR1 must be @@ -5193,12 +5191,12 @@ /** * @brief Configure the Polarity and Filter for TI2. * @param TIMx to select the TIM peripheral. - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPolarity_Rising * @arg TIM_ICPolarity_Falling * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICFilter: Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @retval None */ @@ -5228,17 +5226,17 @@ /** * @brief Configure the TI3 as Input. * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPolarity_Rising * @arg TIM_ICPolarity_Falling * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. + * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3. * @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4. * @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3 * (on channel4 path) is used as the input signal. Therefore CCMR2 must be @@ -5276,17 +5274,17 @@ /** * @brief Configure the TI4 as Input. * @param TIMx to select the TIM peripheral - * @param TIM_ICPolarity : The Input Polarity. + * @param TIM_ICPolarity The Input Polarity. * This parameter can be one of the following values: * @arg TIM_ICPolarity_Rising * @arg TIM_ICPolarity_Falling * @arg TIM_ICPolarity_BothEdge - * @param TIM_ICSelection: specifies the input to be used. + * @param TIM_ICSelection specifies the input to be used. * This parameter can be one of the following values: * @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4. * @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3. * @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC. - * @param TIM_ICFilter: Specifies the Input Capture Filter. + * @param TIM_ICFilter Specifies the Input Capture Filter. * This parameter must be a value between 0x00 and 0x0F. * @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4 * (on channel3 path) is used as the input signal. Therefore CCMR2 must be @@ -5324,7 +5322,7 @@ /** * @brief Selects the Input Trigger source * @param TIMx to select the TIM peripheral - * @param TIM_ITRx: The Input Trigger source. + * @param TIM_ITRx The Input Trigger source. * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal Trigger 0 * @arg TIM_TS_ITR1: Internal Trigger 1 @@ -5353,17 +5351,17 @@ /** * @brief Configures the TIMx External Trigger (ETR). * @param TIMx to select the TIM peripheral - * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler. + * @param TIM_ExtTRGPrescaler The external Trigger Prescaler. * This parameter can be one of the following values: * @arg TIM_ETRPRESCALER_DIV1 : ETRP Prescaler OFF. * @arg TIM_ETRPRESCALER_DIV2 : ETRP frequency divided by 2. * @arg TIM_ETRPRESCALER_DIV4 : ETRP frequency divided by 4. * @arg TIM_ETRPRESCALER_DIV8 : ETRP frequency divided by 8. - * @param TIM_ExtTRGPolarity: The external Trigger Polarity. + * @param TIM_ExtTRGPolarity The external Trigger Polarity. * This parameter can be one of the following values: * @arg TIM_ETRPOLARITY_INVERTED : active low or falling edge active. * @arg TIM_ETRPOLARITY_NONINVERTED : active high or rising edge active. - * @param ExtTRGFilter: External Trigger Filter. + * @param ExtTRGFilter External Trigger Filter. * This parameter must be a value between 0x00 and 0x0F * @retval None */
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_tim.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_tim.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_tim.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief Header file of TIM HAL module.
******************************************************************************
* @attention
@@ -853,21 +851,21 @@
* @{
*/
/** @brief Reset TIM handle state
- * @param __HANDLE__: TIM handle
+ * @param __HANDLE__ TIM handle
* @retval None
*/
#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
/**
* @brief Enable the TIM peripheral.
- * @param __HANDLE__: TIM handle
+ * @param __HANDLE__ TIM handle
* @retval None
*/
#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
/**
* @brief Enable the TIM main Output.
- * @param __HANDLE__: TIM handle
+ * @param __HANDLE__ TIM handle
* @retval None
*/
#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
@@ -875,7 +873,7 @@
/**
* @brief Disable the TIM peripheral.
- * @param __HANDLE__: TIM handle
+ * @param __HANDLE__ TIM handle
* @retval None
*/
#define __HAL_TIM_DISABLE(__HANDLE__) \
@@ -893,7 +891,7 @@
channels have been disabled */
/**
* @brief Disable the TIM main Output.
- * @param __HANDLE__: TIM handle
+ * @param __HANDLE__ TIM handle
* @retval None
*/
#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
@@ -909,15 +907,15 @@
/**
* @brief Disable the TIM main Output.
- * @param __HANDLE__: TIM handle
+ * @param __HANDLE__ TIM handle
* @retval None
* @note The Main Output Enable of a timer instance is disabled unconditionally
*/
#define __HAL_TIM_MOE_DISABLE_UNCONDITIONALLY(__HANDLE__) (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE)
/** @brief Enable the specified TIM interrupt.
- * @param __HANDLE__: specifies the TIM Handle.
- * @param __INTERRUPT__: specifies the TIM interrupt source to enable.
+ * @param __HANDLE__ specifies the TIM Handle.
+ * @param __INTERRUPT__ specifies the TIM interrupt source to enable.
* This parameter can be one of the following values:
* @arg TIM_IT_UPDATE: Update interrupt
* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
@@ -933,8 +931,8 @@
/** @brief Disable the specified TIM interrupt.
- * @param __HANDLE__: specifies the TIM Handle.
- * @param __INTERRUPT__: specifies the TIM interrupt source to disable.
+ * @param __HANDLE__ specifies the TIM Handle.
+ * @param __INTERRUPT__ specifies the TIM interrupt source to disable.
* This parameter can be one of the following values:
* @arg TIM_IT_UPDATE: Update interrupt
* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
@@ -949,8 +947,8 @@
#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
/** @brief Enable the specified DMA request.
- * @param __HANDLE__: specifies the TIM Handle.
- * @param __DMA__: specifies the TIM DMA request to enable.
+ * @param __HANDLE__ specifies the TIM Handle.
+ * @param __DMA__ specifies the TIM DMA request to enable.
* This parameter can be one of the following values:
* @arg TIM_DMA_UPDATE: Update DMA request
* @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
@@ -964,8 +962,8 @@
#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
/** @brief Disable the specified DMA request.
- * @param __HANDLE__: specifies the TIM Handle.
- * @param __DMA__: specifies the TIM DMA request to disable.
+ * @param __HANDLE__ specifies the TIM Handle.
+ * @param __DMA__ specifies the TIM DMA request to disable.
* This parameter can be one of the following values:
* @arg TIM_DMA_UPDATE: Update DMA request
* @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
@@ -979,8 +977,8 @@
#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
/** @brief Check whether the specified TIM interrupt flag is set or not.
- * @param __HANDLE__: specifies the TIM Handle.
- * @param __FLAG__: specifies the TIM interrupt flag to check.
+ * @param __HANDLE__ specifies the TIM Handle.
+ * @param __FLAG__ specifies the TIM interrupt flag to check.
* This parameter can be one of the following values:
* @arg TIM_FLAG_UPDATE: Update interrupt flag
* @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
@@ -1003,8 +1001,8 @@
#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
/** @brief Clear the specified TIM interrupt flag.
- * @param __HANDLE__: specifies the TIM Handle.
- * @param __FLAG__: specifies the TIM interrupt flag to clear.
+ * @param __HANDLE__ specifies the TIM Handle.
+ * @param __FLAG__ specifies the TIM interrupt flag to clear.
* This parameter can be one of the following values:
* @arg TIM_FLAG_UPDATE: Update interrupt flag
* @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
@@ -1028,8 +1026,8 @@
/**
* @brief Check whether the specified TIM interrupt source is enabled or not.
- * @param __HANDLE__: TIM handle
- * @param __INTERRUPT__: specifies the TIM interrupt source to check.
+ * @param __HANDLE__ TIM handle
+ * @param __INTERRUPT__ specifies the TIM interrupt source to check.
* This parameter can be one of the following values:
* @arg TIM_IT_UPDATE: Update interrupt
* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
@@ -1044,8 +1042,8 @@
#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Clear the TIM interrupt pending bits.
- * @param __HANDLE__: TIM handle
- * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
+ * @param __HANDLE__ TIM handle
+ * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
* This parameter can be one of the following values:
* @arg TIM_IT_UPDATE: Update interrupt
* @arg TIM_IT_CC1: Capture/Compare 1 interrupt
@@ -1061,7 +1059,7 @@
/**
* @brief Indicates whether or not the TIM Counter is used as downcounter.
- * @param __HANDLE__: TIM handle.
+ * @param __HANDLE__ TIM handle.
* @retval False (Counter used as upcounter) or True (Counter used as downcounter)
* @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder
mode.
@@ -1070,8 +1068,8 @@
/**
* @brief Set the TIM Prescaler on runtime.
- * @param __HANDLE__: TIM handle.
- * @param __PRESC__: specifies the Prescaler new value.
+ * @param __HANDLE__ TIM handle.
+ * @param __PRESC__ specifies the Prescaler new value.
* @retval None
*/
#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
@@ -1103,14 +1101,14 @@
/**
* @brief Sets the TIM Capture Compare Register value on runtime without
* calling another time ConfigChannel function.
- * @param __HANDLE__: TIM handle.
- * @param __CHANNEL__ : TIM Channels to be configured.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param __COMPARE__: specifies the Capture Compare register new value.
+ * @param __COMPARE__ specifies the Capture Compare register new value.
* @retval None
*/
#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
@@ -1118,8 +1116,8 @@
/**
* @brief Gets the TIM Capture Compare Register value on runtime.
- * @param __HANDLE__: TIM handle.
- * @param __CHANNEL__: TIM Channel associated with the capture compare register
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channel associated with the capture compare register
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: get capture/compare 1 register value
* @arg TIM_CHANNEL_2: get capture/compare 2 register value
@@ -1134,15 +1132,15 @@
/**
* @brief Sets the TIM Counter Register value on runtime.
- * @param __HANDLE__: TIM handle.
- * @param __COUNTER__: specifies the Counter register new value.
+ * @param __HANDLE__ TIM handle.
+ * @param __COUNTER__ specifies the Counter register new value.
* @retval None
*/
#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
/**
* @brief Gets the TIM Counter Register value on runtime.
- * @param __HANDLE__: TIM handle.
+ * @param __HANDLE__ TIM handle.
* @retval 16-bit or 32-bit value of the timer counter register (TIMx_CNT)
*/
#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
@@ -1150,8 +1148,8 @@
/**
* @brief Sets the TIM Autoreload Register value on runtime without calling
* another time any Init function.
- * @param __HANDLE__: TIM handle.
- * @param __AUTORELOAD__: specifies the Counter register new value.
+ * @param __HANDLE__ TIM handle.
+ * @param __AUTORELOAD__ specifies the Counter register new value.
* @retval None
*/
#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
@@ -1161,15 +1159,15 @@
} while(0U)
/**
* @brief Gets the TIM Autoreload Register value on runtime.
- * @param __HANDLE__: TIM handle.
+ * @param __HANDLE__ TIM handle.
* @retval 16-bit or 32-bit value of the timer auto-reload register(TIMx_ARR)
*/
#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
/**
* @brief Sets the TIM Clock Division value on runtime without calling another time any Init function.
- * @param __HANDLE__: TIM handle.
- * @param __CKD__: specifies the clock division value.
+ * @param __HANDLE__ TIM handle.
+ * @param __CKD__ specifies the clock division value.
* This parameter can be one of the following value:
* @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
* @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
@@ -1184,7 +1182,7 @@
} while(0U)
/**
* @brief Gets the TIM Clock Division value on runtime.
- * @param __HANDLE__: TIM handle.
+ * @param __HANDLE__ TIM handle.
* @retval The clock division can be one of the following values:
* @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
* @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
@@ -1195,14 +1193,14 @@
/**
* @brief Sets the TIM Input Capture prescaler on runtime without calling
* another time HAL_TIM_IC_ConfigChannel() function.
- * @param __HANDLE__: TIM handle.
- * @param __CHANNEL__ : TIM Channels to be configured.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param __ICPSC__: specifies the Input Capture4 prescaler new value.
+ * @param __ICPSC__ specifies the Input Capture4 prescaler new value.
* This parameter can be one of the following values:
* @arg TIM_ICPSC_DIV1: no prescaler
* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
@@ -1218,8 +1216,8 @@
/**
* @brief Get the TIM Input Capture prescaler on runtime.
- * @param __HANDLE__: TIM handle.
- * @param __CHANNEL__: TIM Channels to be configured.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: get input capture 1 prescaler value
* @arg TIM_CHANNEL_2: get input capture 2 prescaler value
@@ -1239,7 +1237,7 @@
/**
* @brief Set the Update Request Source (URS) bit of the TIMx_CR1 register
- * @param __HANDLE__: TIM handle.
+ * @param __HANDLE__ TIM handle.
* @note When the USR bit of the TIMx_CR1 register is set, only counter
* overflow/underflow generates an update interrupt or DMA request (if
* enabled)
@@ -1250,7 +1248,7 @@
/**
* @brief Reset the Update Request Source (URS) bit of the TIMx_CR1 register
- * @param __HANDLE__: TIM handle.
+ * @param __HANDLE__ TIM handle.
* @note When the USR bit of the TIMx_CR1 register is reset, any of the
* following events generate an update interrupt or DMA request (if
* enabled):
@@ -1264,14 +1262,14 @@
/**
* @brief Sets the TIM Capture x input polarity on runtime.
- * @param __HANDLE__: TIM handle.
- * @param __CHANNEL__: TIM Channels to be configured.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param __POLARITY__: Polarity for TIx source
+ * @param __POLARITY__ Polarity for TIx source
* @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
* @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
* @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_tim_ex.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_tim_ex.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_tim_ex.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief TIM HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Timer extension peripheral: @@ -151,9 +149,9 @@ */ /** * @brief Initializes the TIM Hall Sensor Interface and create the associated handle. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param sConfig: TIM Hall Sensor configuration structure + * @param sConfig TIM Hall Sensor configuration structure * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig) @@ -225,7 +223,7 @@ /** * @brief DeInitializes the TIM Hall Sensor interface - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -253,7 +251,7 @@ /** * @brief Initializes the TIM Hall Sensor MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -268,7 +266,7 @@ /** * @brief DeInitializes TIM Hall Sensor MSP. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -283,7 +281,7 @@ /** * @brief Starts the TIM Hall Sensor Interface. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -305,7 +303,7 @@ /** * @brief Stops the TIM Hall sensor Interface. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -327,7 +325,7 @@ /** * @brief Starts the TIM Hall Sensor Interface in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -352,7 +350,7 @@ /** * @brief Stops the TIM Hall Sensor Interface in interrupt mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -377,10 +375,10 @@ /** * @brief Starts the TIM Hall Sensor Interface in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param pData: The destination Buffer address. - * @param Length: The length of data to be transferred from TIM peripheral to memory. + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from TIM peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length) @@ -427,7 +425,7 @@ /** * @brief Stops the TIM Hall Sensor Interface in DMA mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL status */ @@ -477,14 +475,13 @@ /** * @brief Starts the TIM Output Compare signal generation on the complementary * output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be enabled. + * @param Channel TIM Channel to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -508,14 +505,13 @@ /** * @brief Stops the TIM Output Compare signal generation on the complementary * output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be disabled. + * @param Channel TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -539,14 +535,13 @@ /** * @brief Starts the TIM Output Compare signal generation in interrupt mode * on the complementary output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be enabled. + * @param Channel TIM Channel to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -607,14 +602,13 @@ /** * @brief Stops the TIM Output Compare signal generation in interrupt mode * on the complementary output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be disabled. + * @param Channel TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -678,16 +672,15 @@ /** * @brief Starts the TIM Output Compare signal generation in DMA mode * on the complementary output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be enabled. + * @param Channel TIM Channel to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData: The source Buffer address. - * @param Length: The length of data to be transferred from memory to TIM peripheral + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) @@ -796,14 +789,13 @@ /** * @brief Stops the TIM Output Compare signal generation in DMA mode * on the complementary output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be disabled. + * @param Channel TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -896,14 +888,13 @@ /** * @brief Starts the PWM signal generation on the complementary output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be enabled. + * @param Channel TIM Channel to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -926,14 +917,13 @@ /** * @brief Stops the PWM signal generation on the complementary output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be disabled. + * @param Channel TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -957,14 +947,13 @@ /** * @brief Starts the PWM signal generation in interrupt mode on the * complementary output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be disabled. + * @param Channel TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -1025,14 +1014,13 @@ /** * @brief Stops the PWM signal generation in interrupt mode on the * complementary output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be disabled. + * @param Channel TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel) @@ -1096,16 +1084,15 @@ /** * @brief Starts the TIM PWM signal generation in DMA mode on the * complementary output - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be enabled. + * @param Channel TIM Channel to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected - * @param pData: The source Buffer address. - * @param Length: The length of data to be transferred from memory to TIM peripheral + * @param pData The source Buffer address. + * @param Length The length of data to be transferred from memory to TIM peripheral * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length) @@ -1214,14 +1201,13 @@ /** * @brief Stops the TIM PWM signal generation in DMA mode on the complementary * output - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Channel: TIM Channel to be disabled. + * @param Channel TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected * @arg TIM_CHANNEL_3: TIM Channel 3 selected - * @arg TIM_CHANNEL_4: TIM Channel 4 selected * @retval HAL status */ HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel) @@ -1304,9 +1290,9 @@ /** * @brief Starts the TIM One Pulse signal generation on the complementary * output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param OutputChannel: TIM Channel to be enabled. + * @param OutputChannel TIM Channel to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1330,9 +1316,9 @@ /** * @brief Stops the TIM One Pulse signal generation on the complementary * output. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param OutputChannel: TIM Channel to be disabled. + * @param OutputChannel TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1360,9 +1346,9 @@ /** * @brief Starts the TIM One Pulse signal generation in interrupt mode on the * complementary channel. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param OutputChannel: TIM Channel to be enabled. + * @param OutputChannel TIM Channel to be enabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1392,9 +1378,9 @@ /** * @brief Stops the TIM One Pulse signal generation in interrupt mode on the * complementary channel. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param OutputChannel: TIM Channel to be disabled. + * @param OutputChannel TIM Channel to be disabled. * This parameter can be one of the following values: * @arg TIM_CHANNEL_1: TIM Channel 1 selected * @arg TIM_CHANNEL_2: TIM Channel 2 selected @@ -1454,16 +1440,16 @@ * configured in Hall sensor interface, this interface Timer will generate the * commutation at its TRGO output (connected to Timer used in this function) each time * the TI1 of the Interface Timer detect a commutation at its input TI1. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor. + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor. * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal trigger 0 selected * @arg TIM_TS_ITR1: Internal trigger 1 selected * @arg TIM_TS_ITR2: Internal trigger 2 selected * @arg TIM_TS_ITR3: Internal trigger 3 selected * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource: the Commutation Event source. + * @param CommutationSource the Commutation Event source. * This parameter can be one of the following values: * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit @@ -1504,16 +1490,16 @@ * configured in Hall sensor interface, this interface Timer will generate the * commutation at its TRGO output (connected to Timer used in this function) each time * the TI1 of the Interface Timer detect a commutation at its input TI1. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor. + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor. * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal trigger 0 selected * @arg TIM_TS_ITR1: Internal trigger 1 selected * @arg TIM_TS_ITR2: Internal trigger 2 selected * @arg TIM_TS_ITR3: Internal trigger 3 selected * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource: the Commutation Event source. + * @param CommutationSource the Commutation Event source. * This parameter can be one of the following values: * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit @@ -1558,16 +1544,16 @@ * commutation at its TRGO output (connected to Timer used in this function) each time * the TI1 of the Interface Timer detect a commutation at its input TI1. * @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor. + * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor. * This parameter can be one of the following values: * @arg TIM_TS_ITR0: Internal trigger 0 selected * @arg TIM_TS_ITR1: Internal trigger 1 selected * @arg TIM_TS_ITR2: Internal trigger 2 selected * @arg TIM_TS_ITR3: Internal trigger 3 selected * @arg TIM_TS_NONE: No trigger is needed - * @param CommutationSource: the Commutation Event source. + * @param CommutationSource the Commutation Event source. * This parameter can be one of the following values: * @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer * @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit @@ -1611,9 +1597,9 @@ /** * @brief Configures the TIM in master mode. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that + * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that * contains the selected trigger output (TRGO) and the Master/Slave * mode. * @retval HAL status @@ -1649,9 +1635,9 @@ /** * @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State * and the AOE(automatic output enable). - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param sBreakDeadTimeConfig: pointer to a TIM_ConfigBreakDeadConfig_TypeDef structure that + * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfig_TypeDef structure that * contains the BDTR Register configuration information for the TIM peripheral. * @retval HAL status */ @@ -1696,9 +1682,9 @@ /** * @brief Configures the TIM2, TIM5 and TIM11 Remapping input capabilities. - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. - * @param Remap: specifies the TIM input remapping source. + * @param Remap specifies the TIM input remapping source. * This parameter can be one of the following values: * @arg TIM_TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default) * @arg TIM_TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trigger output. @@ -1773,7 +1759,7 @@ /** * @brief Hall commutation changed callback in non blocking mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -1788,7 +1774,7 @@ /** * @brief Hall Break detection callback in non blocking mode - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval None */ @@ -1821,7 +1807,7 @@ /** * @brief Return the TIM Hall Sensor interface state - * @param htim: pointer to a TIM_HandleTypeDef structure that contains + * @param htim pointer to a TIM_HandleTypeDef structure that contains * the configuration information for TIM module. * @retval HAL state */ @@ -1836,7 +1822,7 @@ /** * @brief TIM DMA Commutation callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1855,12 +1841,12 @@ /** * @brief Enables or disables the TIM Capture Compare Channel xN. * @param TIMx to select the TIM peripheral - * @param Channel: specifies the TIM Channel + * @param Channel specifies the TIM Channel * This parameter can be one of the following values: * @arg TIM_Channel_1: TIM Channel 1 * @arg TIM_Channel_2: TIM Channel 2 * @arg TIM_Channel_3: TIM Channel 3 - * @param ChannelNState: specifies the TIM Channel CCxNE bit new state. + * @param ChannelNState specifies the TIM Channel CCxNE bit new state. * This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable. * @retval None */
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_tim_ex.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_tim_ex.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_tim_ex.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of TIM HAL Extension module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_uart.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_uart.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_uart.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief UART HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral:
@@ -239,7 +237,7 @@
/**
* @brief Initializes the UART mode according to the specified parameters in
* the UART_InitTypeDef and create the associated handle.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
@@ -301,7 +299,7 @@
/**
* @brief Initializes the half-duplex mode according to the specified
* parameters in the UART_InitTypeDef and create the associated handle.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
@@ -357,9 +355,9 @@
/**
* @brief Initializes the LIN mode according to the specified
* parameters in the UART_InitTypeDef and create the associated handle.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
- * @param BreakDetectLength: Specifies the LIN break detection length.
+ * @param BreakDetectLength Specifies the LIN break detection length.
* This parameter can be one of the following values:
* @arg UART_LINBREAKDETECTLENGTH_10B: 10-bit break detection
* @arg UART_LINBREAKDETECTLENGTH_11B: 11-bit break detection
@@ -422,10 +420,10 @@
/**
* @brief Initializes the Multi-Processor mode according to the specified
* parameters in the UART_InitTypeDef and create the associated handle.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
- * @param Address: USART address
- * @param WakeUpMethod: specifies the USART wake-up method.
+ * @param Address USART address
+ * @param WakeUpMethod specifies the USART wake-up method.
* This parameter can be one of the following values:
* @arg UART_WAKEUPMETHOD_IDLELINE: Wake-up by an idle line detection
* @arg UART_WAKEUPMETHOD_ADDRESSMARK: Wake-up by an address mark
@@ -490,7 +488,7 @@
/**
* @brief DeInitializes the UART peripheral.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
@@ -522,7 +520,7 @@
/**
* @brief UART MSP Init.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
@@ -537,7 +535,7 @@
/**
* @brief UART MSP DeInit.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
@@ -608,11 +606,11 @@
/**
* @brief Sends an amount of data in blocking mode.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be sent
- * @param Timeout: Timeout duration
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
@@ -690,11 +688,11 @@
/**
* @brief Receives an amount of data in blocking mode.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be received
- * @param Timeout: Timeout duration
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be received
+ * @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout)
@@ -779,10 +777,10 @@
/**
* @brief Sends an amount of data in non blocking mode.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be sent
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
@@ -821,10 +819,10 @@
/**
* @brief Receives an amount of data in non blocking mode
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be received
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be received
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
@@ -866,10 +864,10 @@
/**
* @brief Sends an amount of data in non blocking mode.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be sent
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size)
@@ -930,10 +928,10 @@
/**
* @brief Receives an amount of data in non blocking mode.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be received
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be received
* @note When the UART parity is enabled (PCE = 1) the data received contain the parity bit.
* @retval HAL status
*/
@@ -1000,7 +998,7 @@
/**
* @brief Pauses the DMA Transfer.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
@@ -1035,7 +1033,7 @@
/**
* @brief Resumes the DMA Transfer.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
@@ -1070,7 +1068,7 @@
/**
* @brief Stops the DMA Transfer.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
@@ -1518,7 +1516,7 @@
/**
* @brief This function handles UART interrupt request.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
@@ -1645,7 +1643,7 @@
/**
* @brief Tx Transfer completed callbacks.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
@@ -1660,7 +1658,7 @@
/**
* @brief Tx Half Transfer completed callbacks.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
@@ -1675,7 +1673,7 @@
/**
* @brief Rx Transfer completed callbacks.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
@@ -1690,7 +1688,7 @@
/**
* @brief Rx Half Transfer completed callbacks.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
@@ -1705,7 +1703,7 @@
/**
* @brief UART error callbacks.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
@@ -1785,7 +1783,7 @@
/**
* @brief Transmits break characters.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
@@ -1812,7 +1810,7 @@
/**
* @brief Enters the UART in mute mode.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
@@ -1839,7 +1837,7 @@
/**
* @brief Exits the UART mute mode: wake up software.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
@@ -1866,7 +1864,7 @@
/**
* @brief Enables the UART transmitter and disables the UART receiver.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
@@ -1901,7 +1899,7 @@
/**
* @brief Enables the UART receiver and disables the UART transmitter.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
@@ -1958,7 +1956,7 @@
/**
* @brief Returns the UART state.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL state
*/
@@ -1973,7 +1971,7 @@
/**
* @brief Return the UART error code
- * @param huart : pointer to a UART_HandleTypeDef structure that contains
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART.
* @retval UART Error Code
*/
@@ -1988,7 +1986,7 @@
/**
* @brief DMA UART transmit process complete callback.
- * @param hdma: DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
@@ -2016,7 +2014,7 @@
/**
* @brief DMA UART transmit process half complete callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -2029,7 +2027,7 @@
/**
* @brief DMA UART receive process complete callback.
- * @param hdma: DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
@@ -2056,7 +2054,7 @@
/**
* @brief DMA UART receive process half complete callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -2069,7 +2067,7 @@
/**
* @brief DMA UART communication error callback.
- * @param hdma: DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void UART_DMAError(DMA_HandleTypeDef *hdma)
@@ -2099,12 +2097,12 @@
/**
* @brief This function handles UART Communication Timeout.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
- * @param Flag: specifies the UART flag to check.
- * @param Status: The new Flag status (SET or RESET).
+ * @param Flag specifies the UART flag to check.
+ * @param Status The new Flag status (SET or RESET).
* @param Tickstart Tick start value
- * @param Timeout: Timeout duration
+ * @param Timeout Timeout duration
* @retval HAL status
*/
static HAL_StatusTypeDef UART_WaitOnFlagUntilTimeout(UART_HandleTypeDef *huart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
@@ -2137,7 +2135,7 @@
/**
* @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion).
- * @param huart: UART handle.
+ * @param huart UART handle.
* @retval None
*/
static void UART_EndTxTransfer(UART_HandleTypeDef *huart)
@@ -2151,7 +2149,7 @@
/**
* @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion).
- * @param huart: UART handle.
+ * @param huart UART handle.
* @retval None
*/
static void UART_EndRxTransfer(UART_HandleTypeDef *huart)
@@ -2299,7 +2297,7 @@
/**
* @brief Sends an amount of data in non blocking mode.
- * @param huart: Pointer to a UART_HandleTypeDef structure that contains
+ * @param huart Pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
@@ -2346,7 +2344,7 @@
/**
* @brief Wraps up transmission in non blocking mode.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
@@ -2365,7 +2363,7 @@
/**
* @brief Receives an amount of data in non blocking mode
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval HAL status
*/
@@ -2427,7 +2425,7 @@
/**
* @brief Configures the UART peripheral.
- * @param huart: pointer to a UART_HandleTypeDef structure that contains
+ * @param huart pointer to a UART_HandleTypeDef structure that contains
* the configuration information for the specified UART module.
* @retval None
*/
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_uart.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_uart.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_uart.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief Header file of UART HAL module.
******************************************************************************
* @attention
@@ -353,7 +351,7 @@
*/
/** @brief Reset UART handle gstate & RxState
- * @param __HANDLE__: specifies the UART Handle.
+ * @param __HANDLE__ specifies the UART Handle.
* This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* UART peripheral.
* @retval None
@@ -364,15 +362,15 @@
} while(0U)
/** @brief Flushes the UART DR register
- * @param __HANDLE__: specifies the UART Handle.
+ * @param __HANDLE__ specifies the UART Handle.
*/
#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) ((__HANDLE__)->Instance->DR)
/** @brief Checks whether the specified UART flag is set or not.
- * @param __HANDLE__: specifies the UART Handle.
+ * @param __HANDLE__ specifies the UART Handle.
* This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* UART peripheral.
- * @param __FLAG__: specifies the flag to check.
+ * @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5)
* @arg UART_FLAG_LBD: LIN Break detection flag
@@ -390,10 +388,10 @@
#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
/** @brief Clears the specified UART pending flag.
- * @param __HANDLE__: specifies the UART Handle.
+ * @param __HANDLE__ specifies the UART Handle.
* This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* UART peripheral.
- * @param __FLAG__: specifies the flag to check.
+ * @param __FLAG__ specifies the flag to check.
* This parameter can be any combination of the following values:
* @arg UART_FLAG_CTS: CTS Change flag (not available for UART4 and UART5).
* @arg UART_FLAG_LBD: LIN Break detection flag.
@@ -414,7 +412,7 @@
#define __HAL_UART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
/** @brief Clear the UART PE pending flag.
- * @param __HANDLE__: specifies the UART Handle.
+ * @param __HANDLE__ specifies the UART Handle.
* This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* UART peripheral.
* @retval None
@@ -428,7 +426,7 @@
} while(0U)
/** @brief Clear the UART FE pending flag.
- * @param __HANDLE__: specifies the UART Handle.
+ * @param __HANDLE__ specifies the UART Handle.
* This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* UART peripheral.
* @retval None
@@ -436,7 +434,7 @@
#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
/** @brief Clear the UART NE pending flag.
- * @param __HANDLE__: specifies the UART Handle.
+ * @param __HANDLE__ specifies the UART Handle.
* This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* UART peripheral.
* @retval None
@@ -444,7 +442,7 @@
#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
/** @brief Clear the UART ORE pending flag.
- * @param __HANDLE__: specifies the UART Handle.
+ * @param __HANDLE__ specifies the UART Handle.
* This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* UART peripheral.
* @retval None
@@ -452,7 +450,7 @@
#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
/** @brief Clear the UART IDLE pending flag.
- * @param __HANDLE__: specifies the UART Handle.
+ * @param __HANDLE__ specifies the UART Handle.
* This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* UART peripheral.
* @retval None
@@ -460,10 +458,10 @@
#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_PEFLAG(__HANDLE__)
/** @brief Enable the specified UART interrupt.
- * @param __HANDLE__: specifies the UART Handle.
+ * @param __HANDLE__ specifies the UART Handle.
* This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* UART peripheral.
- * @param __INTERRUPT__: specifies the UART interrupt source to enable.
+ * @param __INTERRUPT__ specifies the UART interrupt source to enable.
* This parameter can be one of the following values:
* @arg UART_IT_CTS: CTS change interrupt
* @arg UART_IT_LBD: LIN Break detection interrupt
@@ -480,10 +478,10 @@
(((__INTERRUPT__) >> 28U) == 2U)? ((__HANDLE__)->Instance->CR2 |= ((__INTERRUPT__) & UART_IT_MASK)): \
((__HANDLE__)->Instance->CR3 |= ((__INTERRUPT__) & UART_IT_MASK)))
/** @brief Disable the specified UART interrupt.
- * @param __HANDLE__: specifies the UART Handle.
+ * @param __HANDLE__ specifies the UART Handle.
* This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* UART peripheral.
- * @param __INTERRUPT__: specifies the UART interrupt source to disable.
+ * @param __INTERRUPT__ specifies the UART interrupt source to disable.
* This parameter can be one of the following values:
* @arg UART_IT_CTS: CTS change interrupt
* @arg UART_IT_LBD: LIN Break detection interrupt
@@ -500,10 +498,10 @@
((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & UART_IT_MASK)))
/** @brief Checks whether the specified UART interrupt has occurred or not.
- * @param __HANDLE__: specifies the UART Handle.
+ * @param __HANDLE__ specifies the UART Handle.
* This parameter can be UARTx where x: 1, 2, 3, 4, 5, 6, 7 or 8 to select the USART or
* UART peripheral.
- * @param __IT__: specifies the UART interrupt source to check.
+ * @param __IT__ specifies the UART interrupt source to check.
* This parameter can be one of the following values:
* @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
* @arg UART_IT_LBD: LIN Break detection interrupt
@@ -526,7 +524,7 @@
* - UART instance should have already been initialised (through call of HAL_UART_Init() )
* - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
* and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
- * @param __HANDLE__: specifies the UART Handle.
+ * @param __HANDLE__ specifies the UART Handle.
* The Handle Instance can be USART1, USART2 or LPUART.
* @retval None
*/
@@ -545,7 +543,7 @@
* - UART instance should have already been initialised (through call of HAL_UART_Init() )
* - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
* and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
- * @param __HANDLE__: specifies the UART Handle.
+ * @param __HANDLE__ specifies the UART Handle.
* The Handle Instance can be USART1, USART2 or LPUART.
* @retval None
*/
@@ -564,7 +562,7 @@
* - UART instance should have already been initialised (through call of HAL_UART_Init() )
* - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
* and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
- * @param __HANDLE__: specifies the UART Handle.
+ * @param __HANDLE__ specifies the UART Handle.
* The Handle Instance can be USART1, USART2 or LPUART.
* @retval None
*/
@@ -583,7 +581,7 @@
* - UART instance should have already been initialised (through call of HAL_UART_Init() )
* - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
* and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
- * @param __HANDLE__: specifies the UART Handle.
+ * @param __HANDLE__ specifies the UART Handle.
* The Handle Instance can be USART1, USART2 or LPUART.
* @retval None
*/
@@ -594,25 +592,25 @@
} while(0U)
/** @brief macros to enables the UART's one bit sample method
- * @param __HANDLE__: specifies the UART Handle.
+ * @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
/** @brief macros to disables the UART's one bit sample method
- * @param __HANDLE__: specifies the UART Handle.
+ * @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
/** @brief Enable UART
- * @param __HANDLE__: specifies the UART Handle.
+ * @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
/** @brief Disable UART
- * @param __HANDLE__: specifies the UART Handle.
+ * @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_usart.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_usart.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_usart.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief USART HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Universal Synchronous Asynchronous Receiver Transmitter (USART) peripheral:
@@ -221,7 +219,7 @@
/**
* @brief Initializes the USART mode according to the specified
* parameters in the USART_InitTypeDef and create the associated handle.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval HAL status
*/
@@ -267,7 +265,7 @@
/**
* @brief DeInitializes the USART peripheral.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval HAL status
*/
@@ -301,7 +299,7 @@
/**
* @brief USART MSP Init.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval None
*/
@@ -316,7 +314,7 @@
/**
* @brief USART MSP DeInit.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval None
*/
@@ -396,11 +394,11 @@
/**
* @brief Simplex Send an amount of data in blocking mode.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
- * @param pTxData: Pointer to data buffer
- * @param Size: Amount of data to be sent
- * @param Timeout: Timeout duration
+ * @param pTxData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
@@ -477,11 +475,11 @@
/**
* @brief Full-Duplex Receive an amount of data in blocking mode.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
- * @param pRxData: Pointer to data buffer
- * @param Size: Amount of data to be received
- * @param Timeout: Timeout duration
+ * @param pRxData Pointer to data buffer
+ * @param Size Amount of data to be received
+ * @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
@@ -582,12 +580,12 @@
/**
* @brief Full-Duplex Send receive an amount of data in full-duplex mode (blocking mode).
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
- * @param pTxData: Pointer to data transmitted buffer
- * @param pRxData: Pointer to data received buffer
- * @param Size: Amount of data to be sent
- * @param Timeout: Timeout duration
+ * @param pTxData Pointer to data transmitted buffer
+ * @param pRxData Pointer to data received buffer
+ * @param Size Amount of data to be sent
+ * @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
@@ -697,10 +695,10 @@
/**
* @brief Simplex Send an amount of data in non-blocking mode.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
- * @param pTxData: Pointer to data buffer
- * @param Size: Amount of data to be sent
+ * @param pTxData Pointer to data buffer
+ * @param Size Amount of data to be sent
* @retval HAL status
* @note The USART errors are not managed to avoid the overrun error.
*/
@@ -747,10 +745,10 @@
/**
* @brief Simplex Receive an amount of data in non-blocking mode.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
- * @param pRxData: Pointer to data buffer
- * @param Size: Amount of data to be received
+ * @param pRxData Pointer to data buffer
+ * @param Size Amount of data to be received
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
@@ -793,11 +791,11 @@
/**
* @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
- * @param pTxData: Pointer to data transmitted buffer
- * @param pRxData: Pointer to data received buffer
- * @param Size: Amount of data to be received
+ * @param pTxData Pointer to data transmitted buffer
+ * @param pRxData Pointer to data received buffer
+ * @param Size Amount of data to be received
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
@@ -846,10 +844,10 @@
/**
* @brief Simplex Send an amount of data in non-blocking mode.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
- * @param pTxData: Pointer to data buffer
- * @param Size: Amount of data to be sent
+ * @param pTxData Pointer to data buffer
+ * @param Size Amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
@@ -908,10 +906,10 @@
/**
* @brief Full-Duplex Receive an amount of data in non-blocking mode.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
- * @param pRxData: Pointer to data buffer
- * @param Size: Amount of data to be received
+ * @param pRxData Pointer to data buffer
+ * @param Size Amount of data to be received
* @retval HAL status
* @note The USART DMA transmit stream must be configured in order to generate the clock for the slave.
* @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
@@ -1000,11 +998,11 @@
/**
* @brief Full-Duplex Transmit Receive an amount of data in non-blocking mode.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
- * @param pTxData: Pointer to data transmitted buffer
- * @param pRxData: Pointer to data received buffer
- * @param Size: Amount of data to be received
+ * @param pTxData Pointer to data transmitted buffer
+ * @param pRxData Pointer to data received buffer
+ * @param Size Amount of data to be received
* @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
* @retval HAL status
*/
@@ -1091,7 +1089,7 @@
/**
* @brief Pauses the DMA Transfer.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval HAL status
*/
@@ -1111,7 +1109,7 @@
/**
* @brief Resumes the DMA Transfer.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval HAL status
*/
@@ -1131,7 +1129,7 @@
/**
* @brief Stops the DMA Transfer.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval HAL status
*/
@@ -1367,7 +1365,7 @@
/**
* @brief This function handles USART interrupt request.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval None
*/
@@ -1511,7 +1509,7 @@
/**
* @brief Tx Transfer completed callbacks.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval None
*/
@@ -1526,7 +1524,7 @@
/**
* @brief Tx Half Transfer completed callbacks.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval None
*/
@@ -1541,7 +1539,7 @@
/**
* @brief Rx Transfer completed callbacks.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval None
*/
@@ -1556,7 +1554,7 @@
/**
* @brief Rx Half Transfer completed callbacks.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval None
*/
@@ -1571,7 +1569,7 @@
/**
* @brief Tx/Rx Transfers completed callback for the non-blocking process.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval None
*/
@@ -1586,7 +1584,7 @@
/**
* @brief USART error callbacks.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval None
*/
@@ -1639,7 +1637,7 @@
/**
* @brief Returns the USART state.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval HAL state
*/
@@ -1650,7 +1648,7 @@
/**
* @brief Return the USART error code
- * @param husart : pointer to a USART_HandleTypeDef structure that contains
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART.
* @retval USART Error Code
*/
@@ -1665,7 +1663,7 @@
/**
* @brief DMA USART transmit process complete callback.
- * @param hdma: DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
@@ -1697,7 +1695,7 @@
/**
* @brief DMA USART transmit process half complete callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -1710,7 +1708,7 @@
/**
* @brief DMA USART receive process complete callback.
- * @param hdma: DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
@@ -1725,24 +1723,21 @@
CLEAR_BIT(husart->Instance->CR1, USART_CR1_PEIE);
CLEAR_BIT(husart->Instance->CR3, USART_CR3_EIE);
+ /* Disable the DMA transfer for the Transmit/receiver request by clearing the DMAT/DMAR bit
+ in the USART CR3 register */
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
+ CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
+
+ husart->State= HAL_USART_STATE_READY;
+
+ /* The USART state is HAL_USART_STATE_BUSY_RX */
if(husart->State == HAL_USART_STATE_BUSY_RX)
{
- /* Disable the DMA transfer for the Transmit/receiver requests by setting the DMAT/DMAR bit
- in the USART CR3 register */
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
-
- husart->State= HAL_USART_STATE_READY;
HAL_USART_RxCpltCallback(husart);
}
/* The USART state is HAL_USART_STATE_BUSY_TX_RX */
else
{
- /* Disable the DMA transfer for the Transmit/receiver requests by setting the DMAT/DMAR bit
- in the USART CR3 register */
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAR);
- CLEAR_BIT(husart->Instance->CR3, USART_CR3_DMAT);
-
- husart->State= HAL_USART_STATE_READY;
HAL_USART_TxRxCpltCallback(husart);
}
}
@@ -1763,7 +1758,7 @@
/**
* @brief DMA USART receive process half complete callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -1776,7 +1771,7 @@
/**
* @brief DMA USART communication error callback.
- * @param hdma: DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void USART_DMAError(DMA_HandleTypeDef *hdma)
@@ -1808,12 +1803,12 @@
/**
* @brief This function handles USART Communication Timeout.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
- * @param Flag: specifies the USART flag to check.
- * @param Status: The new Flag status (SET or RESET).
- * @param Tickstart: Tick start value.
- * @param Timeout: Timeout duration.
+ * @param Flag specifies the USART flag to check.
+ * @param Status The new Flag status (SET or RESET).
+ * @param Tickstart Tick start value.
+ * @param Timeout Timeout duration.
* @retval HAL status
*/
static HAL_StatusTypeDef USART_WaitOnFlagUntilTimeout(USART_HandleTypeDef *husart, uint32_t Flag, FlagStatus Status, uint32_t Tickstart, uint32_t Timeout)
@@ -1852,7 +1847,7 @@
/**
* @brief End ongoing Tx transfer on USART peripheral (following error detection or Transmit completion).
- * @param husart: USART handle.
+ * @param husart USART handle.
* @retval None
*/
static void USART_EndTxTransfer(USART_HandleTypeDef *husart)
@@ -1866,7 +1861,7 @@
/**
* @brief End ongoing Rx transfer on USART peripheral (following error detection or Reception completion).
- * @param husart: USART handle.
+ * @param husart USART handle.
* @retval None
*/
static void USART_EndRxTransfer(USART_HandleTypeDef *husart)
@@ -1970,7 +1965,7 @@
/**
* @brief Simplex Send an amount of data in non-blocking mode.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval HAL status
* @note The USART errors are not managed to avoid the overrun error.
@@ -2017,7 +2012,7 @@
/**
* @brief Wraps up transmission in non blocking mode.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval HAL status
*/
@@ -2038,7 +2033,7 @@
/**
* @brief Simplex Receive an amount of data in non-blocking mode.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval HAL status
*/
@@ -2110,7 +2105,7 @@
/**
* @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval HAL status
*/
@@ -2213,7 +2208,7 @@
/**
* @brief Configures the USART pferipheral.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval None
*/
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_usart.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_usart.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_hal_usart.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief Header file of USART HAL module.
******************************************************************************
* @attention
@@ -302,16 +300,16 @@
*/
/** @brief Reset USART handle state
- * @param __HANDLE__: specifies the USART Handle.
+ * @param __HANDLE__ specifies the USART Handle.
* This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
* @retval None
*/
#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
/** @brief Checks whether the specified Smartcard flag is set or not.
- * @param __HANDLE__: specifies the USART Handle.
+ * @param __HANDLE__ specifies the USART Handle.
* This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
- * @param __FLAG__: specifies the flag to check.
+ * @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg USART_FLAG_TXE: Transmit data register empty flag
* @arg USART_FLAG_TC: Transmission Complete flag
@@ -326,9 +324,9 @@
#define __HAL_USART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR & (__FLAG__)) == (__FLAG__))
/** @brief Clears the specified Smartcard pending flags.
- * @param __HANDLE__: specifies the USART Handle.
+ * @param __HANDLE__ specifies the USART Handle.
* This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
- * @param __FLAG__: specifies the flag to check.
+ * @param __FLAG__ specifies the flag to check.
* This parameter can be any combination of the following values:
* @arg USART_FLAG_TC: Transmission Complete flag.
* @arg USART_FLAG_RXNE: Receive data register not empty flag.
@@ -347,7 +345,7 @@
#define __HAL_USART_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
/** @brief Clear the USART PE pending flag.
- * @param __HANDLE__: specifies the USART Handle.
+ * @param __HANDLE__ specifies the USART Handle.
* This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
* @retval None
*/
@@ -360,37 +358,37 @@
} while(0U)
/** @brief Clear the USART FE pending flag.
- * @param __HANDLE__: specifies the USART Handle.
+ * @param __HANDLE__ specifies the USART Handle.
* This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
* @retval None
*/
#define __HAL_USART_CLEAR_FEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
/** @brief Clear the USART NE pending flag.
- * @param __HANDLE__: specifies the USART Handle.
+ * @param __HANDLE__ specifies the USART Handle.
* This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
* @retval None
*/
#define __HAL_USART_CLEAR_NEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
/** @brief Clear the UART ORE pending flag.
- * @param __HANDLE__: specifies the USART Handle.
+ * @param __HANDLE__ specifies the USART Handle.
* This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
* @retval None
*/
#define __HAL_USART_CLEAR_OREFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
/** @brief Clear the USART IDLE pending flag.
- * @param __HANDLE__: specifies the USART Handle.
+ * @param __HANDLE__ specifies the USART Handle.
* This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
* @retval None
*/
#define __HAL_USART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_USART_CLEAR_PEFLAG(__HANDLE__)
/** @brief Enables or disables the specified USART interrupts.
- * @param __HANDLE__: specifies the USART Handle.
+ * @param __HANDLE__ specifies the USART Handle.
* This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
- * @param __INTERRUPT__: specifies the USART interrupt source to check.
+ * @param __INTERRUPT__ specifies the USART interrupt source to check.
* This parameter can be one of the following values:
* @arg USART_IT_TXE: Transmit Data Register empty interrupt
* @arg USART_IT_TC: Transmission complete interrupt
@@ -409,9 +407,9 @@
((__HANDLE__)->Instance->CR3 &= ~ ((__INTERRUPT__) & USART_IT_MASK)))
/** @brief Checks whether the specified USART interrupt has occurred or not.
- * @param __HANDLE__: specifies the USART Handle.
+ * @param __HANDLE__ specifies the USART Handle.
* This parameter can be USARTx where x: 1, 2, 3 or 6 to select the USART peripheral.
- * @param __IT__: specifies the USART interrupt source to check.
+ * @param __IT__ specifies the USART interrupt source to check.
* This parameter can be one of the following values:
* @arg USART_IT_TXE: Transmit Data Register empty interrupt
* @arg USART_IT_TC: Transmission complete interrupt
@@ -425,26 +423,26 @@
(__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & (((uint32_t)(__IT__)) & USART_IT_MASK))
/** @brief Macro to enable the USART's one bit sample method
- * @param __HANDLE__: specifies the USART Handle.
+ * @param __HANDLE__ specifies the USART Handle.
* @retval None
*/
#define __HAL_USART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
/** @brief Macro to disable the USART's one bit sample method
- * @param __HANDLE__: specifies the USART Handle.
+ * @param __HANDLE__ specifies the USART Handle.
* @retval None
*/
#define __HAL_USART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT))
/** @brief Enable USART
- * @param __HANDLE__: specifies the USART Handle.
+ * @param __HANDLE__ specifies the USART Handle.
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @retval None
*/
#define __HAL_USART_ENABLE(__HANDLE__) ( (__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
/** @brief Disable USART
- * @param __HANDLE__: specifies the USART Handle.
+ * @param __HANDLE__ specifies the USART Handle.
* USART Handle selects the USARTx peripheral (USART availability and x value depending on device).
* @retval None
*/
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_wwdg.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_wwdg.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_wwdg.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief WWDG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Window Watchdog (WWDG) peripheral: @@ -280,7 +278,7 @@ /** * @brief WWDG Early Wakeup callback. - * @param hwwdg : pointer to a WWDG_HandleTypeDef structure that contains + * @param hwwdg pointer to a WWDG_HandleTypeDef structure that contains * the configuration information for the specified WWDG module. * @retval None */
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_wwdg.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_hal_wwdg.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_hal_wwdg.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of WWDG HAL module. ****************************************************************************** * @attention @@ -168,14 +166,14 @@ /** * @brief Enables the WWDG peripheral. - * @param __HANDLE__: WWDG handle + * @param __HANDLE__ WWDG handle * @retval None */ #define __HAL_WWDG_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, WWDG_CR_WDGA) /** * @brief Enables the WWDG early wakeup interrupt. - * @param __HANDLE__: WWDG handle + * @param __HANDLE__ WWDG handle * @param __INTERRUPT__ specifies the interrupt to enable. * This parameter can be one of the following values: * @arg WWDG_IT_EWI: Early wakeup interrupt @@ -196,8 +194,8 @@ /** @brief Clear the WWDG's interrupt pending bits * bits to clear the selected interrupt pending bits. - * @param __HANDLE__: WWDG handle - * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * @param __HANDLE__ WWDG handle + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. * This parameter can be one of the following values: * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag */ @@ -215,8 +213,8 @@ /** * @brief Clears the WWDG's pending flags. - * @param __HANDLE__: WWDG handle - * @param __FLAG__: specifies the flag to clear. + * @param __HANDLE__ WWDG handle + * @param __FLAG__ specifies the flag to clear. * This parameter can be one of the following values: * @arg WWDG_FLAG_EWIF: Early wakeup interrupt flag * @retval None @@ -224,8 +222,8 @@ #define __HAL_WWDG_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__)) /** @brief Checks if the specified WWDG interrupt source is enabled or disabled. - * @param __HANDLE__: WWDG Handle. - * @param __INTERRUPT__: specifies the WWDG interrupt source to check. + * @param __HANDLE__ WWDG Handle. + * @param __INTERRUPT__ specifies the WWDG interrupt source to check. * This parameter can be one of the following values: * @arg WWDG_IT_EWI: Early Wakeup Interrupt * @retval state of __INTERRUPT__ (TRUE or FALSE).
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_adc.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_adc.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_adc.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief ADC LL module driver ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_adc.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_adc.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_adc.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of ADC LL module. ****************************************************************************** * @attention @@ -297,7 +295,7 @@ * a register from a register basis from which an offset * is applied. * @param __REG__ Register basis from which the offset is applied. - * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers). + * @param __REG_OFFFSET__ Offset to be applied (unit number of registers). * @retval Pointer to register address */ #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ @@ -646,12 +644,12 @@ #define LL_ADC_CHANNEL_18 (ADC_CHANNEL_18_NUMBER | ADC_CHANNEL_18_SMP) /*!< ADC external channel (channel connected to GPIO pin) ADCx_IN18 */ #define LL_ADC_CHANNEL_VREFINT (LL_ADC_CHANNEL_17 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to VrefInt: Internal voltage reference. On STM32F4, ADC channel available only on ADC instance: ADC1. */ #define LL_ADC_CHANNEL_VBAT (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda. On STM32F4, ADC channel available only on ADC instance: ADC1. */ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F415xx) || defined(STM32F417xx) #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_16 | ADC_CHANNEL_ID_INTERNAL_CH) /*!< ADC internal channel connected to Temperature sensor. On STM32F4, ADC channel available only on ADC instance: ADC1. */ #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx */ -#if defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F411xE) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +#if defined(STM32F411xE) || defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) #define LL_ADC_CHANNEL_TEMPSENSOR (LL_ADC_CHANNEL_18 | ADC_CHANNEL_ID_INTERNAL_CH | ADC_CHANNEL_DIFFERENCIATION_TEMPSENSOR_VBAT) /*!< ADC internal channel connected to Temperature sensor. On STM32F4, ADC channel available only on ADC instance: ADC1. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */ -#endif /* STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F411xE || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ +#endif /* STM32F411xE || STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ /** * @} */ @@ -948,16 +946,16 @@ #define LL_ADC_AWD_CH_VBAT_REG ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group regular only */ #define LL_ADC_AWD_CH_VBAT_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda, converted by group injected only */ #define LL_ADC_AWD_CH_VBAT_REG_INJ ((LL_ADC_CHANNEL_VBAT & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Vbat/3: Vbat voltage through a divider ladder of factor 1/3 to have Vbat always below Vdda */ -#if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) || defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) +#if defined(STM32F401xC) || defined(STM32F401xE) || defined(STM32F405xx) || defined(STM32F407xx) || defined(STM32F410Tx) || defined(STM32F410Cx) || defined(STM32F410Rx) || defined(STM32F415xx) || defined(STM32F417xx) #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only */ #define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only */ #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected */ #endif /* STM32F405xx || STM32F415xx || STM32F407xx || STM32F417xx || STM32F401xC || STM32F401xE || STM32F410xx */ -#if defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F411xE) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) +#if defined(STM32F411xE) || defined(STM32F412Cx) || defined(STM32F412Rx) || defined(STM32F412Vx) || defined(STM32F412Zx) || defined(STM32F413xx) || defined(STM32F423xx) || defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx) #define LL_ADC_AWD_CH_TEMPSENSOR_REG ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group regular only. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */ #define LL_ADC_AWD_CH_TEMPSENSOR_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by group injected only. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */ #define LL_ADC_AWD_CH_TEMPSENSOR_REG_INJ ((LL_ADC_CHANNEL_TEMPSENSOR & ADC_CHANNEL_ID_MASK) | ADC_CR1_JAWDEN | ADC_CR1_AWDEN | ADC_CR1_AWDSGL) /*!< ADC analog watchdog monitoring of ADC internal channel connected to Temperature sensor, converted by either group regular or injected. This internal channel is shared between temperature sensor and Vbat, only 1 measurement path must be enabled. */ -#endif /* STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F411xE || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ +#endif /* STM32F411xE || STM32F412Cx || STM32F412Rx || STM32F412Vx || STM32F412Zx || STM32F413xx || STM32F423xx || STM32F427xx || STM32F437xx || STM32F429xx || STM32F439xx || STM32F446xx || STM32F469xx || STM32F479xx */ /** * @} */ @@ -1166,7 +1164,7 @@ * @note Example: * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4) * will return a data equivalent to "LL_ADC_CHANNEL_4". - * @param __DECIMAL_NB__: Value between Min_Data=0 and Max_Data=18 + * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 * @arg @ref LL_ADC_CHANNEL_1 @@ -1639,7 +1637,7 @@ * @note Analog reference voltage (Vref+) must be either known from * user board environment or can be calculated using ADC measurement * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). - * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) + * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit mV) * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) * (unit: digital value). * @param __ADC_RESOLUTION__ This parameter can be one of the following values: @@ -1686,13 +1684,13 @@ * @note ADC measurement data must correspond to a resolution of 12bits * (full scale digital value 4095). If not the case, the data must be * preliminarily rescaled to an equivalent resolution of 12 bits. - * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius). + * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data Temperature sensor slope typical value (unit uV/DegCelsius). * On STM32F4, refer to device datasheet parameter "Avg_Slope". - * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV). + * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit mV). * On STM32F4, refer to device datasheet parameter "V25". - * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV) - * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV) - * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). + * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit mV) + * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit mV) + * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit digital value). * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. * This parameter can be one of the following values: * @arg @ref LL_ADC_RESOLUTION_12B @@ -3496,7 +3494,7 @@ * @param AWDThresholdsHighLow This parameter can be one of the following values: * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH * @arg @ref LL_ADC_AWD_THRESHOLD_LOW - * @param AWDThresholdValue: Value between Min_Data=0x000 and Max_Data=0xFFF + * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF * @retval None */ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_bus.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_bus.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_bus.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of BUS LL module. @verbatim
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_cortex.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_cortex.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_cortex.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of CORTEX LL module. @verbatim ==============================================================================
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_crc.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_crc.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_crc.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief CRC LL module driver. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_crc.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_crc.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_crc.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of CRC LL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dac.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dac.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_dac.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief DAC LL module driver ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dac.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dac.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_dac.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of DAC LL module. ****************************************************************************** * @attention @@ -139,7 +137,7 @@ * a register from a register basis from which an offset * is applied. * @param __REG__ Register basis from which the offset is applied. - * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers). + * @param __REG_OFFFSET__ Offset to be applied (unit number of registers). * @retval Pointer to register address */ #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ @@ -493,7 +491,7 @@ * @note Analog reference voltage (Vref+) must be either known from * user board environment or can be calculated using ADC measurement * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). - * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) + * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit mV) * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel * (unit: mVolt). * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dma.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dma.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_dma.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief DMA LL module driver. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dma.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dma.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_ll_dma.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief Header file of DMA LL module.
******************************************************************************
* @attention
@@ -2097,7 +2095,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->LIFCR , DMA_LIFCR_CHTIF0);
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF0);
}
/**
@@ -2108,7 +2106,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->LIFCR , DMA_LIFCR_CHTIF1);
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF1);
}
/**
@@ -2119,7 +2117,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->LIFCR , DMA_LIFCR_CHTIF2);
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF2);
}
/**
@@ -2130,7 +2128,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->LIFCR , DMA_LIFCR_CHTIF3);
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF3);
}
/**
@@ -2141,7 +2139,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->HIFCR , DMA_HIFCR_CHTIF4);
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF4);
}
/**
@@ -2152,7 +2150,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->HIFCR , DMA_HIFCR_CHTIF5);
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF5);
}
/**
@@ -2163,7 +2161,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->HIFCR , DMA_HIFCR_CHTIF6);
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF6);
}
/**
@@ -2174,7 +2172,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->HIFCR , DMA_HIFCR_CHTIF7);
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF7);
}
/**
@@ -2185,7 +2183,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTCIF0);
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF0);
}
/**
@@ -2196,7 +2194,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTCIF1);
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF1);
}
/**
@@ -2207,7 +2205,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTCIF2);
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF2);
}
/**
@@ -2218,7 +2216,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTCIF3);
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF3);
}
/**
@@ -2229,7 +2227,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTCIF4);
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF4);
}
/**
@@ -2240,7 +2238,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTCIF5);
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF5);
}
/**
@@ -2251,7 +2249,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTCIF6);
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF6);
}
/**
@@ -2262,7 +2260,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTCIF7);
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF7);
}
/**
@@ -2273,7 +2271,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTEIF0);
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF0);
}
/**
@@ -2284,7 +2282,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTEIF1);
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF1);
}
/**
@@ -2295,7 +2293,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTEIF2);
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF2);
}
/**
@@ -2306,7 +2304,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTEIF3);
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF3);
}
/**
@@ -2317,7 +2315,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTEIF4);
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF4);
}
/**
@@ -2328,7 +2326,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTEIF5);
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF5);
}
/**
@@ -2339,7 +2337,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTEIF6);
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF6);
}
/**
@@ -2350,7 +2348,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTEIF7);
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF7);
}
/**
@@ -2361,7 +2359,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->LIFCR , DMA_LIFCR_CDMEIF0);
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF0);
}
/**
@@ -2372,7 +2370,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->LIFCR , DMA_LIFCR_CDMEIF1);
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF1);
}
/**
@@ -2383,7 +2381,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->LIFCR , DMA_LIFCR_CDMEIF2);
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF2);
}
/**
@@ -2394,7 +2392,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->LIFCR , DMA_LIFCR_CDMEIF3);
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF3);
}
/**
@@ -2405,7 +2403,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->HIFCR , DMA_HIFCR_CDMEIF4);
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF4);
}
/**
@@ -2416,7 +2414,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->HIFCR , DMA_HIFCR_CDMEIF5);
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF5);
}
/**
@@ -2427,7 +2425,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->HIFCR , DMA_HIFCR_CDMEIF6);
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF6);
}
/**
@@ -2438,7 +2436,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->HIFCR , DMA_HIFCR_CDMEIF7);
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF7);
}
/**
@@ -2449,7 +2447,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->LIFCR , DMA_LIFCR_CFEIF0);
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF0);
}
/**
@@ -2460,7 +2458,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->LIFCR , DMA_LIFCR_CFEIF1);
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF1);
}
/**
@@ -2471,7 +2469,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->LIFCR , DMA_LIFCR_CFEIF2);
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF2);
}
/**
@@ -2482,7 +2480,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->LIFCR , DMA_LIFCR_CFEIF3);
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF3);
}
/**
@@ -2493,7 +2491,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->HIFCR , DMA_HIFCR_CFEIF4);
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF4);
}
/**
@@ -2504,7 +2502,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->HIFCR , DMA_HIFCR_CFEIF5);
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF5);
}
/**
@@ -2515,7 +2513,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->HIFCR , DMA_HIFCR_CFEIF6);
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF6);
}
/**
@@ -2526,7 +2524,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->HIFCR , DMA_HIFCR_CFEIF7);
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF7);
}
/**
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dma2d.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dma2d.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_dma2d.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief DMA2D LL module driver. ****************************************************************************** * @attention @@ -164,7 +162,7 @@ * @note DMA2D transfers must be disabled to set initialization bits in configuration registers, * otherwise ERROR result is returned. * @param DMA2Dx DMA2D Instance - * @param DMA2D_InitStruct: pointer to a LL_DMA2D_InitTypeDef structure + * @param DMA2D_InitStruct pointer to a LL_DMA2D_InitTypeDef structure * that contains the configuration information for the specified DMA2D peripheral. * @retval An ErrorStatus enumeration value: * - SUCCESS: DMA2D registers are initialized according to DMA2D_InitStruct content @@ -226,7 +224,7 @@ /** * @brief Set each @ref LL_DMA2D_InitTypeDef field to default value. - * @param DMA2D_InitStruct: pointer to a @ref LL_DMA2D_InitTypeDef structure + * @param DMA2D_InitStruct pointer to a @ref LL_DMA2D_InitTypeDef structure * whose fields will be set to default values. * @retval None */ @@ -249,9 +247,9 @@ * @brief Configure the foreground or background according to the specified parameters * in the LL_DMA2D_LayerCfgTypeDef structure. * @param DMA2Dx DMA2D Instance - * @param DMA2D_LayerCfg: pointer to a LL_DMA2D_LayerCfgTypeDef structure that contains + * @param DMA2D_LayerCfg pointer to a LL_DMA2D_LayerCfgTypeDef structure that contains * the configuration information for the specified layer. - * @param LayerIdx: DMA2D Layer index. + * @param LayerIdx DMA2D Layer index. * This parameter can be one of the following values: * 0(background) / 1(foreground) * @retval None @@ -315,7 +313,7 @@ /** * @brief Set each @ref LL_DMA2D_LayerCfgTypeDef field to default value. - * @param DMA2D_LayerCfg: pointer to a @ref LL_DMA2D_LayerCfgTypeDef structure + * @param DMA2D_LayerCfg pointer to a @ref LL_DMA2D_LayerCfgTypeDef structure * whose fields will be set to default values. * @retval None */ @@ -339,7 +337,7 @@ * @brief Initialize DMA2D output color register according to the specified parameters * in DMA2D_ColorStruct. * @param DMA2Dx DMA2D Instance - * @param DMA2D_ColorStruct: pointer to a LL_DMA2D_ColorTypeDef structure that contains + * @param DMA2D_ColorStruct pointer to a LL_DMA2D_ColorTypeDef structure that contains * the color configuration information for the specified DMA2D peripheral. * @retval None */
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dma2d.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_dma2d.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_dma2d.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of DMA2D LL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_exti.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_exti.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_exti.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief EXTI LL module driver. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_exti.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_exti.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_exti.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of EXTI LL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fmc.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fmc.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_ll_fmc.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief FMC Low Layer HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -144,8 +142,8 @@
/**
* @brief Initialize the FMC_NORSRAM device according to the specified
* control parameters in the FMC_NORSRAM_InitTypeDef
- * @param Device: Pointer to NORSRAM device instance
- * @param Init: Pointer to NORSRAM Initialization structure
+ * @param Device Pointer to NORSRAM device instance
+ * @param Init Pointer to NORSRAM Initialization structure
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef* Init)
@@ -255,9 +253,9 @@
/**
* @brief DeInitialize the FMC_NORSRAM peripheral
- * @param Device: Pointer to NORSRAM device instance
- * @param ExDevice: Pointer to NORSRAM extended mode device instance
- * @param Bank: NORSRAM bank number
+ * @param Device Pointer to NORSRAM device instance
+ * @param ExDevice Pointer to NORSRAM extended mode device instance
+ * @param Bank NORSRAM bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
@@ -291,9 +289,9 @@
/**
* @brief Initialize the FMC_NORSRAM Timing according to the specified
* parameters in the FMC_NORSRAM_TimingTypeDef
- * @param Device: Pointer to NORSRAM device instance
- * @param Timing: Pointer to NORSRAM Timing structure
- * @param Bank: NORSRAM bank number
+ * @param Device Pointer to NORSRAM device instance
+ * @param Timing Pointer to NORSRAM Timing structure
+ * @param Bank NORSRAM bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
@@ -344,9 +342,9 @@
/**
* @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified
* parameters in the FMC_NORSRAM_TimingTypeDef
- * @param Device: Pointer to NORSRAM device instance
- * @param Timing: Pointer to NORSRAM Timing structure
- * @param Bank: NORSRAM bank number
+ * @param Device Pointer to NORSRAM device instance
+ * @param Timing Pointer to NORSRAM Timing structure
+ * @param Bank NORSRAM bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
@@ -410,8 +408,8 @@
*/
/**
* @brief Enables dynamically FMC_NORSRAM write operation.
- * @param Device: Pointer to NORSRAM device instance
- * @param Bank: NORSRAM bank number
+ * @param Device Pointer to NORSRAM device instance
+ * @param Bank NORSRAM bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
@@ -428,8 +426,8 @@
/**
* @brief Disables dynamically FMC_NORSRAM write operation.
- * @param Device: Pointer to NORSRAM device instance
- * @param Bank: NORSRAM bank number
+ * @param Device Pointer to NORSRAM device instance
+ * @param Bank NORSRAM bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
@@ -498,8 +496,8 @@
/**
* @brief Initializes the FMC_NAND device according to the specified
* control parameters in the FMC_NAND_HandleTypeDef
- * @param Device: Pointer to NAND device instance
- * @param Init: Pointer to NAND Initialization structure
+ * @param Device Pointer to NAND device instance
+ * @param Init Pointer to NAND Initialization structure
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
@@ -542,9 +540,9 @@
/**
* @brief Initializes the FMC_NAND Common space Timing according to the specified
* parameters in the FMC_NAND_PCC_TimingTypeDef
- * @param Device: Pointer to NAND device instance
- * @param Timing: Pointer to NAND timing structure
- * @param Bank: NAND bank number
+ * @param Device Pointer to NAND device instance
+ * @param Timing Pointer to NAND timing structure
+ * @param Bank NAND bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
@@ -583,9 +581,9 @@
/**
* @brief Initializes the FMC_NAND Attribute space Timing according to the specified
* parameters in the FMC_NAND_PCC_TimingTypeDef
- * @param Device: Pointer to NAND device instance
- * @param Timing: Pointer to NAND timing structure
- * @param Bank: NAND bank number
+ * @param Device Pointer to NAND device instance
+ * @param Timing Pointer to NAND timing structure
+ * @param Bank NAND bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
@@ -622,8 +620,8 @@
/**
* @brief DeInitializes the FMC_NAND device
- * @param Device: Pointer to NAND device instance
- * @param Bank: NAND bank number
+ * @param Device Pointer to NAND device instance
+ * @param Bank NAND bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
@@ -668,8 +666,8 @@
/**
* @brief Enables dynamically FMC_NAND ECC feature.
- * @param Device: Pointer to NAND device instance
- * @param Bank: NAND bank number
+ * @param Device Pointer to NAND device instance
+ * @param Bank NAND bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
@@ -687,8 +685,8 @@
/**
* @brief Disables dynamically FMC_NAND ECC feature.
- * @param Device: Pointer to NAND device instance
- * @param Bank: NAND bank number
+ * @param Device Pointer to NAND device instance
+ * @param Bank NAND bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
@@ -705,10 +703,10 @@
/**
* @brief Disables dynamically FMC_NAND ECC feature.
- * @param Device: Pointer to NAND device instance
- * @param ECCval: Pointer to ECC value
- * @param Bank: NAND bank number
- * @param Timeout: Timeout wait value
+ * @param Device Pointer to NAND device instance
+ * @param ECCval Pointer to ECC value
+ * @param Bank NAND bank number
+ * @param Timeout Timeout wait value
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
@@ -765,8 +763,8 @@
/**
* @brief Initializes the FMC_NAND device according to the specified
* control parameters in the FMC_NAND_HandleTypeDef
- * @param Device: Pointer to NAND device instance
- * @param Init: Pointer to NAND Initialization structure
+ * @param Device Pointer to NAND device instance
+ * @param Init Pointer to NAND Initialization structure
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
@@ -826,9 +824,9 @@
/**
* @brief Initializes the FMC_NAND Common space Timing according to the specified
* parameters in the FMC_NAND_PCC_TimingTypeDef
- * @param Device: Pointer to NAND device instance
- * @param Timing: Pointer to NAND timing structure
- * @param Bank: NAND bank number
+ * @param Device Pointer to NAND device instance
+ * @param Timing Pointer to NAND timing structure
+ * @param Bank NAND bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
@@ -882,9 +880,9 @@
/**
* @brief Initializes the FMC_NAND Attribute space Timing according to the specified
* parameters in the FMC_NAND_PCC_TimingTypeDef
- * @param Device: Pointer to NAND device instance
- * @param Timing: Pointer to NAND timing structure
- * @param Bank: NAND bank number
+ * @param Device Pointer to NAND device instance
+ * @param Timing Pointer to NAND timing structure
+ * @param Bank NAND bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
@@ -936,8 +934,8 @@
/**
* @brief DeInitializes the FMC_NAND device
- * @param Device: Pointer to NAND device instance
- * @param Bank: NAND bank number
+ * @param Device Pointer to NAND device instance
+ * @param Bank NAND bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
@@ -991,8 +989,8 @@
*/
/**
* @brief Enables dynamically FMC_NAND ECC feature.
- * @param Device: Pointer to NAND device instance
- * @param Bank: NAND bank number
+ * @param Device Pointer to NAND device instance
+ * @param Bank NAND bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
@@ -1016,8 +1014,8 @@
/**
* @brief Disables dynamically FMC_NAND ECC feature.
- * @param Device: Pointer to NAND device instance
- * @param Bank: NAND bank number
+ * @param Device Pointer to NAND device instance
+ * @param Bank NAND bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
@@ -1041,10 +1039,10 @@
/**
* @brief Disables dynamically FMC_NAND ECC feature.
- * @param Device: Pointer to NAND device instance
- * @param ECCval: Pointer to ECC value
- * @param Bank: NAND bank number
- * @param Timeout: Timeout wait value
+ * @param Device Pointer to NAND device instance
+ * @param ECCval Pointer to ECC value
+ * @param Bank NAND bank number
+ * @param Timeout Timeout wait value
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
@@ -1138,8 +1136,8 @@
/**
* @brief Initializes the FMC_PCCARD device according to the specified
* control parameters in the FMC_PCCARD_HandleTypeDef
- * @param Device: Pointer to PCCARD device instance
- * @param Init: Pointer to PCCARD Initialization structure
+ * @param Device Pointer to PCCARD device instance
+ * @param Init Pointer to PCCARD Initialization structure
* @retval HAL status
*/
HAL_StatusTypeDef FMC_PCCARD_Init(FMC_PCCARD_TypeDef *Device, FMC_PCCARD_InitTypeDef *Init)
@@ -1157,7 +1155,7 @@
/* Clear TAR, TCLR, PWAITEN and PWID bits */
tmpr &= ((uint32_t)~(FMC_PCR4_TAR | FMC_PCR4_TCLR | FMC_PCR4_PWAITEN | \
- FMC_PCR4_PWID));
+ FMC_PCR4_PWID | FMC_PCR4_PTYP));
/* Set FMC_PCCARD device control parameters */
tmpr |= (uint32_t)(Init->Waitfeature |\
@@ -1173,8 +1171,8 @@
/**
* @brief Initializes the FMC_PCCARD Common space Timing according to the specified
* parameters in the FMC_NAND_PCC_TimingTypeDef
- * @param Device: Pointer to PCCARD device instance
- * @param Timing: Pointer to PCCARD timing structure
+ * @param Device Pointer to PCCARD device instance
+ * @param Timing Pointer to PCCARD timing structure
* @retval HAL status
*/
HAL_StatusTypeDef FMC_PCCARD_CommonSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
@@ -1208,8 +1206,8 @@
/**
* @brief Initializes the FMC_PCCARD Attribute space Timing according to the specified
* parameters in the FMC_NAND_PCC_TimingTypeDef
- * @param Device: Pointer to PCCARD device instance
- * @param Timing: Pointer to PCCARD timing structure
+ * @param Device Pointer to PCCARD device instance
+ * @param Timing Pointer to PCCARD timing structure
* @retval HAL status
*/
HAL_StatusTypeDef FMC_PCCARD_AttributeSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
@@ -1243,8 +1241,8 @@
/**
* @brief Initializes the FMC_PCCARD IO space Timing according to the specified
* parameters in the FMC_NAND_PCC_TimingTypeDef
- * @param Device: Pointer to PCCARD device instance
- * @param Timing: Pointer to PCCARD timing structure
+ * @param Device Pointer to PCCARD device instance
+ * @param Timing Pointer to PCCARD timing structure
* @retval HAL status
*/
HAL_StatusTypeDef FMC_PCCARD_IOSpace_Timing_Init(FMC_PCCARD_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing)
@@ -1278,7 +1276,7 @@
/**
* @brief DeInitializes the FMC_PCCARD device
- * @param Device: Pointer to PCCARD device instance
+ * @param Device Pointer to PCCARD device instance
* @retval HAL status
*/
HAL_StatusTypeDef FMC_PCCARD_DeInit(FMC_PCCARD_TypeDef *Device)
@@ -1347,8 +1345,8 @@
/**
* @brief Initializes the FMC_SDRAM device according to the specified
* control parameters in the FMC_SDRAM_InitTypeDef
- * @param Device: Pointer to SDRAM device instance
- * @param Init: Pointer to SDRAM Initialization structure
+ * @param Device Pointer to SDRAM device instance
+ * @param Init Pointer to SDRAM Initialization structure
* @retval HAL status
*/
HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init)
@@ -1427,9 +1425,9 @@
/**
* @brief Initializes the FMC_SDRAM device timing according to the specified
* parameters in the FMC_SDRAM_TimingTypeDef
- * @param Device: Pointer to SDRAM device instance
- * @param Timing: Pointer to SDRAM Timing structure
- * @param Bank: SDRAM bank number
+ * @param Device Pointer to SDRAM device instance
+ * @param Timing Pointer to SDRAM Timing structure
+ * @param Bank SDRAM bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)
@@ -1498,7 +1496,7 @@
/**
* @brief DeInitializes the FMC_SDRAM peripheral
- * @param Device: Pointer to SDRAM device instance
+ * @param Device Pointer to SDRAM device instance
* @retval HAL status
*/
HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
@@ -1537,8 +1535,8 @@
*/
/**
* @brief Enables dynamically FMC_SDRAM write protection.
- * @param Device: Pointer to SDRAM device instance
- * @param Bank: SDRAM bank number
+ * @param Device Pointer to SDRAM device instance
+ * @param Bank SDRAM bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
@@ -1555,7 +1553,7 @@
/**
* @brief Disables dynamically FMC_SDRAM write protection.
- * @param hsdram: FMC_SDRAM handle
+ * @param hsdram FMC_SDRAM handle
* @retval HAL status
*/
HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
@@ -1572,10 +1570,10 @@
/**
* @brief Send Command to the FMC SDRAM bank
- * @param Device: Pointer to SDRAM device instance
- * @param Command: Pointer to SDRAM command structure
- * @param Timing: Pointer to SDRAM Timing structure
- * @param Timeout: Timeout wait value
+ * @param Device Pointer to SDRAM device instance
+ * @param Command Pointer to SDRAM command structure
+ * @param Timing Pointer to SDRAM Timing structure
+ * @param Timeout Timeout wait value
* @retval HAL state
*/
HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
@@ -1620,8 +1618,8 @@
/**
* @brief Program the SDRAM Memory Refresh rate.
- * @param Device: Pointer to SDRAM device instance
- * @param RefreshRate: The SDRAM refresh rate value.
+ * @param Device Pointer to SDRAM device instance
+ * @param RefreshRate The SDRAM refresh rate value.
* @retval HAL state
*/
HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)
@@ -1638,8 +1636,8 @@
/**
* @brief Set the Number of consecutive SDRAM Memory auto Refresh commands.
- * @param Device: Pointer to SDRAM device instance
- * @param AutoRefreshNumber: Specifies the auto Refresh number.
+ * @param Device Pointer to SDRAM device instance
+ * @param AutoRefreshNumber Specifies the auto Refresh number.
* @retval None
*/
HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber)
@@ -1656,8 +1654,8 @@
/**
* @brief Returns the indicated FMC SDRAM bank mode status.
- * @param Device: Pointer to SDRAM device instance
- * @param Bank: Defines the FMC SDRAM bank. This parameter can be
+ * @param Device Pointer to SDRAM device instance
+ * @param Bank Defines the FMC SDRAM bank. This parameter can be
* FMC_Bank1_SDRAM or FMC_Bank2_SDRAM.
* @retval The FMC SDRAM bank mode status, could be on of the following values:
* FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fmc.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fmc.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_ll_fmc.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief Header file of FMC HAL module.
******************************************************************************
* @attention
@@ -798,16 +796,16 @@
*/
/**
* @brief Enable the NORSRAM device access.
- * @param __INSTANCE__: FMC_NORSRAM Instance
- * @param __BANK__: FMC_NORSRAM Bank
+ * @param __INSTANCE__ FMC_NORSRAM Instance
+ * @param __BANK__ FMC_NORSRAM Bank
* @retval None
*/
#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCR1_MBKEN)
/**
* @brief Disable the NORSRAM device access.
- * @param __INSTANCE__: FMC_NORSRAM Instance
- * @param __BANK__: FMC_NORSRAM Bank
+ * @param __INSTANCE__ FMC_NORSRAM Instance
+ * @param __BANK__ FMC_NORSRAM Bank
* @retval None
*/
#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
@@ -822,24 +820,24 @@
#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
/**
* @brief Enable the NAND device access.
- * @param __INSTANCE__: FMC_NAND Instance
- * @param __BANK__: FMC_NAND Bank
+ * @param __INSTANCE__ FMC_NAND Instance
+ * @param __BANK__ FMC_NAND Bank
* @retval None
*/
#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN)
/**
* @brief Disable the NAND device access.
- * @param __INSTANCE__: FMC_NAND Instance
- * @param __BANK__: FMC_NAND Bank
+ * @param __INSTANCE__ FMC_NAND Instance
+ * @param __BANK__ FMC_NAND Bank
* @retval None
*/
#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN)
#else /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
/**
* @brief Enable the NAND device access.
- * @param __INSTANCE__: FMC_NAND Instance
- * @param __BANK__: FMC_NAND Bank
+ * @param __INSTANCE__ FMC_NAND Instance
+ * @param __BANK__ FMC_NAND Bank
* @retval None
*/
#define __FMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FMC_PCR2_PBKEN): \
@@ -847,8 +845,8 @@
/**
* @brief Disable the NAND device access.
- * @param __INSTANCE__: FMC_NAND Instance
- * @param __BANK__: FMC_NAND Bank
+ * @param __INSTANCE__ FMC_NAND Instance
+ * @param __BANK__ FMC_NAND Bank
* @retval None
*/
#define __FMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FMC_PCR2_PBKEN): \
@@ -865,14 +863,14 @@
*/
/**
* @brief Enable the PCCARD device access.
- * @param __INSTANCE__: FMC_PCCARD Instance
+ * @param __INSTANCE__ FMC_PCCARD Instance
* @retval None
*/
#define __FMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FMC_PCR4_PBKEN)
/**
* @brief Disable the PCCARD device access.
- * @param __INSTANCE__: FMC_PCCARD Instance
+ * @param __INSTANCE__ FMC_PCCARD Instance
* @retval None
*/
#define __FMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FMC_PCR4_PBKEN)
@@ -888,9 +886,9 @@
#if defined(STM32F446xx) || defined(STM32F469xx) || defined(STM32F479xx)
/**
* @brief Enable the NAND device interrupt.
- * @param __INSTANCE__: FMC_NAND instance
- * @param __BANK__: FMC_NAND Bank
- * @param __INTERRUPT__: FMC_NAND interrupt
+ * @param __INSTANCE__ FMC_NAND instance
+ * @param __BANK__ FMC_NAND Bank
+ * @param __INTERRUPT__ FMC_NAND interrupt
* This parameter can be any combination of the following values:
* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
* @arg FMC_IT_LEVEL: Interrupt level.
@@ -901,9 +899,9 @@
/**
* @brief Disable the NAND device interrupt.
- * @param __INSTANCE__: FMC_NAND Instance
- * @param __BANK__: FMC_NAND Bank
- * @param __INTERRUPT__: FMC_NAND interrupt
+ * @param __INSTANCE__ FMC_NAND Instance
+ * @param __BANK__ FMC_NAND Bank
+ * @param __INTERRUPT__ FMC_NAND interrupt
* This parameter can be any combination of the following values:
* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
* @arg FMC_IT_LEVEL: Interrupt level.
@@ -914,9 +912,9 @@
/**
* @brief Get flag status of the NAND device.
- * @param __INSTANCE__: FMC_NAND Instance
- * @param __BANK__: FMC_NAND Bank
- * @param __FLAG__: FMC_NAND flag
+ * @param __INSTANCE__ FMC_NAND Instance
+ * @param __BANK__ FMC_NAND Bank
+ * @param __FLAG__ FMC_NAND flag
* This parameter can be any combination of the following values:
* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
@@ -927,9 +925,9 @@
#define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))
/**
* @brief Clear flag status of the NAND device.
- * @param __INSTANCE__: FMC_NAND Instance
- * @param __BANK__: FMC_NAND Bank
- * @param __FLAG__: FMC_NAND flag
+ * @param __INSTANCE__ FMC_NAND Instance
+ * @param __BANK__ FMC_NAND Bank
+ * @param __FLAG__ FMC_NAND flag
* This parameter can be any combination of the following values:
* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
@@ -941,9 +939,9 @@
#else /* defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx) */
/**
* @brief Enable the NAND device interrupt.
- * @param __INSTANCE__: FMC_NAND instance
- * @param __BANK__: FMC_NAND Bank
- * @param __INTERRUPT__: FMC_NAND interrupt
+ * @param __INSTANCE__ FMC_NAND instance
+ * @param __BANK__ FMC_NAND Bank
+ * @param __INTERRUPT__ FMC_NAND interrupt
* This parameter can be any combination of the following values:
* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
* @arg FMC_IT_LEVEL: Interrupt level.
@@ -955,9 +953,9 @@
/**
* @brief Disable the NAND device interrupt.
- * @param __INSTANCE__: FMC_NAND Instance
- * @param __BANK__: FMC_NAND Bank
- * @param __INTERRUPT__: FMC_NAND interrupt
+ * @param __INSTANCE__ FMC_NAND Instance
+ * @param __BANK__ FMC_NAND Bank
+ * @param __INTERRUPT__ FMC_NAND interrupt
* This parameter can be any combination of the following values:
* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
* @arg FMC_IT_LEVEL: Interrupt level.
@@ -969,9 +967,9 @@
/**
* @brief Get flag status of the NAND device.
- * @param __INSTANCE__: FMC_NAND Instance
- * @param __BANK__: FMC_NAND Bank
- * @param __FLAG__: FMC_NAND flag
+ * @param __INSTANCE__ FMC_NAND Instance
+ * @param __BANK__ FMC_NAND Bank
+ * @param __FLAG__ FMC_NAND flag
* This parameter can be any combination of the following values:
* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
@@ -983,9 +981,9 @@
(((__INSTANCE__)->SR3 &(__FLAG__)) == (__FLAG__)))
/**
* @brief Clear flag status of the NAND device.
- * @param __INSTANCE__: FMC_NAND Instance
- * @param __BANK__: FMC_NAND Bank
- * @param __FLAG__: FMC_NAND flag
+ * @param __INSTANCE__ FMC_NAND Instance
+ * @param __BANK__ FMC_NAND Bank
+ * @param __FLAG__ FMC_NAND flag
* This parameter can be any combination of the following values:
* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
@@ -1000,8 +998,8 @@
#if defined(STM32F427xx) || defined(STM32F437xx) || defined(STM32F429xx) || defined(STM32F439xx)
/**
* @brief Enable the PCCARD device interrupt.
- * @param __INSTANCE__: FMC_PCCARD instance
- * @param __INTERRUPT__: FMC_PCCARD interrupt
+ * @param __INSTANCE__ FMC_PCCARD instance
+ * @param __INTERRUPT__ FMC_PCCARD interrupt
* This parameter can be any combination of the following values:
* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
* @arg FMC_IT_LEVEL: Interrupt level.
@@ -1012,8 +1010,8 @@
/**
* @brief Disable the PCCARD device interrupt.
- * @param __INSTANCE__: FMC_PCCARD instance
- * @param __INTERRUPT__: FMC_PCCARD interrupt
+ * @param __INSTANCE__ FMC_PCCARD instance
+ * @param __INTERRUPT__ FMC_PCCARD interrupt
* This parameter can be any combination of the following values:
* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
* @arg FMC_IT_LEVEL: Interrupt level.
@@ -1024,8 +1022,8 @@
/**
* @brief Get flag status of the PCCARD device.
- * @param __INSTANCE__: FMC_PCCARD instance
- * @param __FLAG__: FMC_PCCARD flag
+ * @param __INSTANCE__ FMC_PCCARD instance
+ * @param __FLAG__ FMC_PCCARD flag
* This parameter can be any combination of the following values:
* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
@@ -1037,8 +1035,8 @@
/**
* @brief Clear flag status of the PCCARD device.
- * @param __INSTANCE__: FMC_PCCARD instance
- * @param __FLAG__: FMC_PCCARD flag
+ * @param __INSTANCE__ FMC_PCCARD instance
+ * @param __FLAG__ FMC_PCCARD flag
* This parameter can be any combination of the following values:
* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
@@ -1051,8 +1049,8 @@
/**
* @brief Enable the SDRAM device interrupt.
- * @param __INSTANCE__: FMC_SDRAM instance
- * @param __INTERRUPT__: FMC_SDRAM interrupt
+ * @param __INSTANCE__ FMC_SDRAM instance
+ * @param __INTERRUPT__ FMC_SDRAM interrupt
* This parameter can be any combination of the following values:
* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
* @retval None
@@ -1061,8 +1059,8 @@
/**
* @brief Disable the SDRAM device interrupt.
- * @param __INSTANCE__: FMC_SDRAM instance
- * @param __INTERRUPT__: FMC_SDRAM interrupt
+ * @param __INSTANCE__ FMC_SDRAM instance
+ * @param __INTERRUPT__ FMC_SDRAM interrupt
* This parameter can be any combination of the following values:
* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
* @retval None
@@ -1071,8 +1069,8 @@
/**
* @brief Get flag status of the SDRAM device.
- * @param __INSTANCE__: FMC_SDRAM instance
- * @param __FLAG__: FMC_SDRAM flag
+ * @param __INSTANCE__ FMC_SDRAM instance
+ * @param __FLAG__ FMC_SDRAM flag
* This parameter can be any combination of the following values:
* @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.
* @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.
@@ -1083,8 +1081,8 @@
/**
* @brief Clear flag status of the SDRAM device.
- * @param __INSTANCE__: FMC_SDRAM instance
- * @param __FLAG__: FMC_SDRAM flag
+ * @param __INSTANCE__ FMC_SDRAM instance
+ * @param __FLAG__ FMC_SDRAM flag
* This parameter can be any combination of the following values:
* @arg FMC_SDRAM_FLAG_REFRESH_ERROR
* @retval None
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fsmc.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fsmc.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_ll_fsmc.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief FSMC Low Layer HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -140,8 +138,8 @@
/**
* @brief Initialize the FSMC_NORSRAM device according to the specified
* control parameters in the FSMC_NORSRAM_InitTypeDef
- * @param Device: Pointer to NORSRAM device instance
- * @param Init: Pointer to NORSRAM Initialization structure
+ * @param Device Pointer to NORSRAM device instance
+ * @param Init Pointer to NORSRAM Initialization structure
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_NORSRAM_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_InitTypeDef* Init)
@@ -248,9 +246,9 @@
/**
* @brief DeInitialize the FSMC_NORSRAM peripheral
- * @param Device: Pointer to NORSRAM device instance
- * @param ExDevice: Pointer to NORSRAM extended mode device instance
- * @param Bank: NORSRAM bank number
+ * @param Device Pointer to NORSRAM device instance
+ * @param ExDevice Pointer to NORSRAM extended mode device instance
+ * @param Bank NORSRAM bank number
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_NORSRAM_DeInit(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
@@ -285,9 +283,9 @@
/**
* @brief Initialize the FSMC_NORSRAM Timing according to the specified
* parameters in the FSMC_NORSRAM_TimingTypeDef
- * @param Device: Pointer to NORSRAM device instance
- * @param Timing: Pointer to NORSRAM Timing structure
- * @param Bank: NORSRAM bank number
+ * @param Device Pointer to NORSRAM device instance
+ * @param Timing Pointer to NORSRAM Timing structure
+ * @param Bank NORSRAM bank number
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_NORSRAM_Timing_Init(FSMC_NORSRAM_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
@@ -340,9 +338,9 @@
/**
* @brief Initialize the FSMC_NORSRAM Extended mode Timing according to the specified
* parameters in the FSMC_NORSRAM_TimingTypeDef
- * @param Device: Pointer to NORSRAM device instance
- * @param Timing: Pointer to NORSRAM Timing structure
- * @param Bank: NORSRAM bank number
+ * @param Device Pointer to NORSRAM device instance
+ * @param Timing Pointer to NORSRAM Timing structure
+ * @param Bank NORSRAM bank number
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_NORSRAM_Extended_Timing_Init(FSMC_NORSRAM_EXTENDED_TypeDef *Device, FSMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
@@ -407,8 +405,8 @@
/**
* @brief Enables dynamically FSMC_NORSRAM write operation.
- * @param Device: Pointer to NORSRAM device instance
- * @param Bank: NORSRAM bank number
+ * @param Device Pointer to NORSRAM device instance
+ * @param Bank NORSRAM bank number
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Enable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
@@ -425,8 +423,8 @@
/**
* @brief Disables dynamically FSMC_NORSRAM write operation.
- * @param Device: Pointer to NORSRAM device instance
- * @param Bank: NORSRAM bank number
+ * @param Device Pointer to NORSRAM device instance
+ * @param Bank NORSRAM bank number
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_NORSRAM_WriteOperation_Disable(FSMC_NORSRAM_TypeDef *Device, uint32_t Bank)
@@ -494,8 +492,8 @@
/**
* @brief Initializes the FSMC_NAND device according to the specified
* control parameters in the FSMC_NAND_HandleTypeDef
- * @param Device: Pointer to NAND device instance
- * @param Init: Pointer to NAND Initialization structure
+ * @param Device Pointer to NAND device instance
+ * @param Init Pointer to NAND Initialization structure
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_NAND_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_InitTypeDef *Init)
@@ -553,9 +551,9 @@
/**
* @brief Initializes the FSMC_NAND Common space Timing according to the specified
* parameters in the FSMC_NAND_PCC_TimingTypeDef
- * @param Device: Pointer to NAND device instance
- * @param Timing: Pointer to NAND timing structure
- * @param Bank: NAND bank number
+ * @param Device Pointer to NAND device instance
+ * @param Timing Pointer to NAND timing structure
+ * @param Bank NAND bank number
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_NAND_CommonSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
@@ -607,9 +605,9 @@
/**
* @brief Initializes the FSMC_NAND Attribute space Timing according to the specified
* parameters in the FSMC_NAND_PCC_TimingTypeDef
- * @param Device: Pointer to NAND device instance
- * @param Timing: Pointer to NAND timing structure
- * @param Bank: NAND bank number
+ * @param Device Pointer to NAND device instance
+ * @param Timing Pointer to NAND timing structure
+ * @param Bank NAND bank number
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_NAND_AttributeSpace_Timing_Init(FSMC_NAND_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
@@ -660,8 +658,8 @@
/**
* @brief DeInitializes the FSMC_NAND device
- * @param Device: Pointer to NAND device instance
- * @param Bank: NAND bank number
+ * @param Device Pointer to NAND device instance
+ * @param Bank NAND bank number
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_NAND_DeInit(FSMC_NAND_TypeDef *Device, uint32_t Bank)
@@ -711,8 +709,8 @@
/**
* @brief Enables dynamically FSMC_NAND ECC feature.
- * @param Device: Pointer to NAND device instance
- * @param Bank: NAND bank number
+ * @param Device Pointer to NAND device instance
+ * @param Bank NAND bank number
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_NAND_ECC_Enable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
@@ -732,8 +730,8 @@
/**
* @brief Disables dynamically FSMC_NAND ECC feature.
- * @param Device: Pointer to NAND device instance
- * @param Bank: NAND bank number
+ * @param Device Pointer to NAND device instance
+ * @param Bank NAND bank number
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_NAND_ECC_Disable(FSMC_NAND_TypeDef *Device, uint32_t Bank)
@@ -753,10 +751,10 @@
/**
* @brief Disables dynamically FSMC_NAND ECC feature.
- * @param Device: Pointer to NAND device instance
- * @param ECCval: Pointer to ECC value
- * @param Bank: NAND bank number
- * @param Timeout: Timeout wait value
+ * @param Device Pointer to NAND device instance
+ * @param ECCval Pointer to ECC value
+ * @param Bank NAND bank number
+ * @param Timeout Timeout wait value
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_NAND_GetECC(FSMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
@@ -849,8 +847,8 @@
/**
* @brief Initializes the FSMC_PCCARD device according to the specified
* control parameters in the FSMC_PCCARD_HandleTypeDef
- * @param Device: Pointer to PCCARD device instance
- * @param Init: Pointer to PCCARD Initialization structure
+ * @param Device Pointer to PCCARD device instance
+ * @param Init Pointer to PCCARD Initialization structure
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_PCCARD_Init(FSMC_PCCARD_TypeDef *Device, FSMC_PCCARD_InitTypeDef *Init)
@@ -867,7 +865,7 @@
/* Clear TAR, TCLR, PWAITEN and PWID bits */
tmpr &= ((uint32_t)~(FSMC_PCR4_TAR | FSMC_PCR4_TCLR | FSMC_PCR4_PWAITEN | \
- FSMC_PCR4_PWID));
+ FSMC_PCR4_PWID | FSMC_PCR4_PTYP));
/* Set FSMC_PCCARD device control parameters */
tmpr |= (uint32_t)(Init->Waitfeature |\
@@ -883,8 +881,8 @@
/**
* @brief Initializes the FSMC_PCCARD Common space Timing according to the specified
* parameters in the FSMC_NAND_PCC_TimingTypeDef
- * @param Device: Pointer to PCCARD device instance
- * @param Timing: Pointer to PCCARD timing structure
+ * @param Device Pointer to PCCARD device instance
+ * @param Timing Pointer to PCCARD timing structure
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_PCCARD_CommonSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
@@ -917,8 +915,8 @@
/**
* @brief Initializes the FSMC_PCCARD Attribute space Timing according to the specified
* parameters in the FSMC_NAND_PCC_TimingTypeDef
- * @param Device: Pointer to PCCARD device instance
- * @param Timing: Pointer to PCCARD timing structure
+ * @param Device Pointer to PCCARD device instance
+ * @param Timing Pointer to PCCARD timing structure
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_PCCARD_AttributeSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
@@ -951,8 +949,8 @@
/**
* @brief Initializes the FSMC_PCCARD IO space Timing according to the specified
* parameters in the FSMC_NAND_PCC_TimingTypeDef
- * @param Device: Pointer to PCCARD device instance
- * @param Timing: Pointer to PCCARD timing structure
+ * @param Device Pointer to PCCARD device instance
+ * @param Timing Pointer to PCCARD timing structure
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_PCCARD_IOSpace_Timing_Init(FSMC_PCCARD_TypeDef *Device, FSMC_NAND_PCC_TimingTypeDef *Timing)
@@ -985,7 +983,7 @@
/**
* @brief DeInitializes the FSMC_PCCARD device
- * @param Device: Pointer to PCCARD device instance
+ * @param Device Pointer to PCCARD device instance
* @retval HAL status
*/
HAL_StatusTypeDef FSMC_PCCARD_DeInit(FSMC_PCCARD_TypeDef *Device)
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fsmc.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_fsmc.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_fsmc.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of FSMC HAL module. ****************************************************************************** * @attention @@ -649,16 +647,16 @@ */ /** * @brief Enable the NORSRAM device access. - * @param __INSTANCE__: FSMC_NORSRAM Instance - * @param __BANK__: FSMC_NORSRAM Bank + * @param __INSTANCE__ FSMC_NORSRAM Instance + * @param __BANK__ FSMC_NORSRAM Bank * @retval none */ #define __FSMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FSMC_BCR1_MBKEN) /** * @brief Disable the NORSRAM device access. - * @param __INSTANCE__: FSMC_NORSRAM Instance - * @param __BANK__: FSMC_NORSRAM Bank + * @param __INSTANCE__ FSMC_NORSRAM Instance + * @param __BANK__ FSMC_NORSRAM Bank * @retval none */ #define __FSMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FSMC_BCR1_MBKEN) @@ -673,8 +671,8 @@ #if defined(STM32F405xx) || defined(STM32F415xx) || defined(STM32F407xx) || defined(STM32F417xx) /** * @brief Enable the NAND device access. - * @param __INSTANCE__: FSMC_NAND Instance - * @param __BANK__: FSMC_NAND Bank + * @param __INSTANCE__ FSMC_NAND Instance + * @param __BANK__ FSMC_NAND Bank * @retval none */ #define __FSMC_NAND_ENABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 |= FSMC_PCR2_PBKEN): \ @@ -682,8 +680,8 @@ /** * @brief Disable the NAND device access. - * @param __INSTANCE__: FSMC_NAND Instance - * @param __BANK__: FSMC_NAND Bank + * @param __INSTANCE__ FSMC_NAND Instance + * @param __BANK__ FSMC_NAND Bank * @retval none */ #define __FSMC_NAND_DISABLE(__INSTANCE__, __BANK__) (((__BANK__) == FSMC_NAND_BANK2)? ((__INSTANCE__)->PCR2 &= ~FSMC_PCR2_PBKEN): \ @@ -698,14 +696,14 @@ */ /** * @brief Enable the PCCARD device access. - * @param __INSTANCE__: FSMC_PCCARD Instance + * @param __INSTANCE__ FSMC_PCCARD Instance * @retval none */ #define __FSMC_PCCARD_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 |= FSMC_PCR4_PBKEN) /** * @brief Disable the PCCARD device access. - * @param __INSTANCE__: FSMC_PCCARD Instance + * @param __INSTANCE__ FSMC_PCCARD Instance * @retval none */ #define __FSMC_PCCARD_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR4 &= ~FSMC_PCR4_PBKEN) @@ -719,9 +717,9 @@ */ /** * @brief Enable the NAND device interrupt. - * @param __INSTANCE__: FSMC_NAND Instance - * @param __BANK__: FSMC_NAND Bank - * @param __INTERRUPT__: FSMC_NAND interrupt + * @param __INSTANCE__ FSMC_NAND Instance + * @param __BANK__ FSMC_NAND Bank + * @param __INTERRUPT__ FSMC_NAND interrupt * This parameter can be any combination of the following values: * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. * @arg FSMC_IT_LEVEL: Interrupt level. @@ -733,9 +731,9 @@ /** * @brief Disable the NAND device interrupt. - * @param __INSTANCE__: FSMC_NAND Instance - * @param __BANK__: FSMC_NAND Bank - * @param __INTERRUPT__: FSMC_NAND interrupt + * @param __INSTANCE__ FSMC_NAND Instance + * @param __BANK__ FSMC_NAND Bank + * @param __INTERRUPT__ FSMC_NAND interrupt * This parameter can be any combination of the following values: * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. * @arg FSMC_IT_LEVEL: Interrupt level. @@ -747,9 +745,9 @@ /** * @brief Get flag status of the NAND device. - * @param __INSTANCE__: FSMC_NAND Instance - * @param __BANK__ : FSMC_NAND Bank - * @param __FLAG__ : FSMC_NAND flag + * @param __INSTANCE__ FSMC_NAND Instance + * @param __BANK__ FSMC_NAND Bank + * @param __FLAG__ FSMC_NAND flag * This parameter can be any combination of the following values: * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. @@ -762,9 +760,9 @@ /** * @brief Clear flag status of the NAND device. - * @param __INSTANCE__: FSMC_NAND Instance - * @param __BANK__: FSMC_NAND Bank - * @param __FLAG__: FSMC_NAND flag + * @param __INSTANCE__ FSMC_NAND Instance + * @param __BANK__ FSMC_NAND Bank + * @param __FLAG__ FSMC_NAND flag * This parameter can be any combination of the following values: * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. @@ -777,8 +775,8 @@ /** * @brief Enable the PCCARD device interrupt. - * @param __INSTANCE__: FSMC_PCCARD Instance - * @param __INTERRUPT__: FSMC_PCCARD interrupt + * @param __INSTANCE__ FSMC_PCCARD Instance + * @param __INTERRUPT__ FSMC_PCCARD interrupt * This parameter can be any combination of the following values: * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. * @arg FSMC_IT_LEVEL: Interrupt level. @@ -789,8 +787,8 @@ /** * @brief Disable the PCCARD device interrupt. - * @param __INSTANCE__: FSMC_PCCARD Instance - * @param __INTERRUPT__: FSMC_PCCARD interrupt + * @param __INSTANCE__ FSMC_PCCARD Instance + * @param __INTERRUPT__ FSMC_PCCARD interrupt * This parameter can be any combination of the following values: * @arg FSMC_IT_RISING_EDGE: Interrupt rising edge. * @arg FSMC_IT_LEVEL: Interrupt level. @@ -801,8 +799,8 @@ /** * @brief Get flag status of the PCCARD device. - * @param __INSTANCE__: FSMC_PCCARD Instance - * @param __FLAG__: FSMC_PCCARD flag + * @param __INSTANCE__ FSMC_PCCARD Instance + * @param __FLAG__ FSMC_PCCARD flag * This parameter can be any combination of the following values: * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag. @@ -814,8 +812,8 @@ /** * @brief Clear flag status of the PCCARD device. - * @param __INSTANCE__: FSMC_PCCARD Instance - * @param __FLAG__: FSMC_PCCARD flag + * @param __INSTANCE__ FSMC_PCCARD Instance + * @param __FLAG__ FSMC_PCCARD flag * This parameter can be any combination of the following values: * @arg FSMC_FLAG_RISING_EDGE: Interrupt rising edge flag. * @arg FSMC_FLAG_LEVEL: Interrupt level edge flag.
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_gpio.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_gpio.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_gpio.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief GPIO LL module driver. ****************************************************************************** * @attention @@ -209,7 +207,7 @@ /** * @brief Initialize GPIO registers according to the specified parameters in GPIO_InitStruct. * @param GPIOx GPIO Port - * @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure + * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure * that contains the configuration information for the specified GPIO peripheral. * @retval An ErrorStatus enumeration value: * - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content @@ -286,7 +284,7 @@ /** * @brief Set each @ref LL_GPIO_InitTypeDef field to default value. - * @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure + * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure * whose fields will be set to default values. * @retval None */
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_gpio.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_gpio.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_gpio.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of GPIO LL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_i2c.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_i2c.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_ll_i2c.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief I2C LL module driver.
******************************************************************************
* @attention
@@ -69,9 +67,9 @@
((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE) || \
((__VALUE__) == LL_I2C_MODE_SMBUS_DEVICE_ARP))
-#define IS_I2C_CLOCK_SPEED(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= LL_I2C_MAX_SPEED_FAST))
+#define IS_LL_I2C_CLOCK_SPEED(__VALUE__) (((__VALUE__) > 0U) && ((__VALUE__) <= LL_I2C_MAX_SPEED_FAST))
-#define IS_I2C_DUTY_CYCLE(__VALUE__) (((__VALUE__) == LL_I2C_DUTYCYCLE_2) || \
+#define IS_LL_I2C_DUTY_CYCLE(__VALUE__) (((__VALUE__) == LL_I2C_DUTYCYCLE_2) || \
((__VALUE__) == LL_I2C_DUTYCYCLE_16_9))
#if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF)
@@ -169,8 +167,8 @@
/* Check the I2C parameters from I2C_InitStruct */
assert_param(IS_LL_I2C_PERIPHERAL_MODE(I2C_InitStruct->PeripheralMode));
- assert_param(IS_I2C_CLOCK_SPEED(I2C_InitStruct->ClockSpeed));
- assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->DutyCycle));
+ assert_param(IS_LL_I2C_CLOCK_SPEED(I2C_InitStruct->ClockSpeed));
+ assert_param(IS_LL_I2C_DUTY_CYCLE(I2C_InitStruct->DutyCycle));
#if defined(I2C_FLTR_ANOFF)&&defined(I2C_FLTR_DNF)
assert_param(IS_LL_I2C_ANALOG_FILTER(I2C_InitStruct->AnalogFilter));
assert_param(IS_LL_I2C_DIGITAL_FILTER(I2C_InitStruct->DigitalFilter));
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_i2c.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_i2c.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_i2c.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of I2C LL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_iwdg.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_iwdg.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_iwdg.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of IWDG LL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_lptim.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_lptim.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_lptim.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief LPTIM LL module driver. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_lptim.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_lptim.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_lptim.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of LPTIM LL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_pwr.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_pwr.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_pwr.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief PWR LL module driver. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_pwr.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_pwr.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_pwr.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of PWR LL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rcc.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rcc.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_ll_rcc.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief RCC LL module driver.
******************************************************************************
* @attention
@@ -208,6 +206,10 @@
/* Set HSION bit */
LL_RCC_HSI_Enable();
+ /* Wait for HSI READY bit */
+ while(LL_RCC_HSI_IsReady() != 1U)
+ {}
+
/* Reset CFGR register */
LL_RCC_WriteReg(CFGR, 0x00000000U);
@@ -232,6 +234,10 @@
/* Set HSITRIM bits to the reset value*/
LL_RCC_HSI_SetCalibTrimming(0x10U);
+ /* Wait for PLL READY bit to be reset */
+ while(LL_RCC_PLL_IsReady() != 0U)
+ {}
+
/* Reset PLLCFGR register */
LL_RCC_WriteReg(PLLCFGR, RCC_PLLCFGR_RST_VALUE);
@@ -245,11 +251,33 @@
LL_RCC_WriteReg(PLLSAICFGR, RCC_PLLSAICFGR_RST_VALUE);
#endif /* RCC_PLLSAI_SUPPORT */
- /* Reset HSEBYP bit */
- LL_RCC_HSE_DisableBypass();
+ /* Disable all interrupts */
+ CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE | RCC_CIR_LSERDYIE | RCC_CIR_HSIRDYIE | RCC_CIR_HSERDYIE | RCC_CIR_PLLRDYIE);
+
+#if defined(RCC_CIR_PLLI2SRDYIE)
+ CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
+#endif /* RCC_CIR_PLLI2SRDYIE */
+
+#if defined(RCC_CIR_PLLSAIRDYIE)
+ CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);
+#endif /* RCC_CIR_PLLSAIRDYIE */
+
+ /* Clear all interrupt flags */
+ SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_CSSC);
- /* Disable all interrupts */
- LL_RCC_WriteReg(CIR, 0x00000000U);
+#if defined(RCC_CIR_PLLI2SRDYC)
+ SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC);
+#endif /* RCC_CIR_PLLI2SRDYC */
+
+#if defined(RCC_CIR_PLLSAIRDYC)
+ SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC);
+#endif /* RCC_CIR_PLLSAIRDYC */
+
+ /* Clear LSION bit */
+ CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
+
+ /* Reset all CSR flags */
+ SET_BIT(RCC->CSR, RCC_CSR_RMVF);
return SUCCESS;
}
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rcc.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rcc.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_ll_rcc.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief Header file of RCC LL module.
******************************************************************************
* @attention
@@ -4854,6 +4852,31 @@
#endif /* RCC_PLLCFGR_PLLR */
/**
+ * @brief Configure PLL clock source
+ * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource
+ * @param PLLSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
+{
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource);
+}
+
+/**
+ * @brief Get the oscillator used as PLL clock source.
+ * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
+{
+ return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
+}
+
+/**
* @brief Get Main PLL multiplication factor for VCO
* @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN
* @retval Between 50/192(*) and 432
@@ -4968,18 +4991,6 @@
#endif /* RCC_DCKCFGR_PLLDIVR */
/**
- * @brief Get the oscillator used as PLL clock source.
- * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_PLLSOURCE_HSI
- * @arg @ref LL_RCC_PLLSOURCE_HSE
- */
-__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
-{
- return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
-}
-
-/**
* @brief Get Division factor for the main PLL and other PLL
* @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider
* @retval Returned value can be one of the following values:
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rng.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rng.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_rng.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief RNG LL module driver. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rng.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rng.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_rng.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of RNG LL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rtc.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rtc.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_rtc.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief RTC LL module driver. ****************************************************************************** * @attention @@ -381,7 +379,7 @@ * @param RTC_Format This parameter can be one of the following values: * @arg @ref LL_RTC_FORMAT_BIN * @arg @ref LL_RTC_FORMAT_BCD - * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains + * @param RTC_DateStruct pointer to a RTC_DateTypeDef structure that contains * the date configuration information for the RTC. * @retval An ErrorStatus enumeration value: * - SUCCESS: RTC Day register is configured
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rtc.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_rtc.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_rtc.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of RTC LL module. ****************************************************************************** * @attention @@ -2694,7 +2692,7 @@ * @brief Set timestamp Pin * @rmtoll TAFCR TSINSEL LL_RTC_TS_SetPin * @param RTCx RTC Instance - * @param TSPin: specifies the RTC TimeStamp Pin. + * @param TSPin specifies the RTC TimeStamp Pin. * This parameter can be one of the following values: * @arg LL_RTC_TimeStampPin_Default: RTC_AF1 is used as RTC TimeStamp. * @arg LL_RTC_TimeStampPin_Pos1: RTC_AF2 is selected as RTC TimeStamp. (*) @@ -2935,7 +2933,7 @@ * @brief Set Tamper Pin * @rmtoll TAFCR TAMP1INSEL LL_RTC_TAMPER_SetPin * @param RTCx RTC Instance - * @param TamperPin: specifies the RTC Tamper Pin. + * @param TamperPin specifies the RTC Tamper Pin. * This parameter can be one of the following values: * @arg LL_RTC_TamperPin_Default: RTC_AF1 is used as RTC Tamper. * @arg LL_RTC_TamperPin_Pos1: RTC_AF2 is selected as RTC Tamper. (*)
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_sdmmc.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_sdmmc.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_ll_sdmmc.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief SDMMC Low Layer HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -227,8 +225,8 @@
/**
* @brief Initializes the SDMMC according to the specified
* parameters in the SDMMC_InitTypeDef and create the associated handle.
- * @param SDIOx: Pointer to SDMMC register base
- * @param Init: SDMMC initialization structure
+ * @param SDIOx Pointer to SDMMC register base
+ * @param Init SDMMC initialization structure
* @retval HAL status
*/
HAL_StatusTypeDef SDIO_Init(SDIO_TypeDef *SDIOx, SDIO_InitTypeDef Init)
@@ -281,7 +279,7 @@
/**
* @brief Read data (word) from Rx FIFO in blocking mode (polling)
- * @param SDIOx: Pointer to SDMMC register base
+ * @param SDIOx Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDIO_ReadFIFO(SDIO_TypeDef *SDIOx)
@@ -292,8 +290,8 @@
/**
* @brief Write data (word) to Tx FIFO in blocking mode (polling)
- * @param SDIOx: Pointer to SDMMC register base
- * @param pWriteData: pointer to data to write
+ * @param SDIOx Pointer to SDMMC register base
+ * @param pWriteData pointer to data to write
* @retval HAL status
*/
HAL_StatusTypeDef SDIO_WriteFIFO(SDIO_TypeDef *SDIOx, uint32_t *pWriteData)
@@ -325,7 +323,7 @@
/**
* @brief Set SDMMC Power state to ON.
- * @param SDIOx: Pointer to SDMMC register base
+ * @param SDIOx Pointer to SDMMC register base
* @retval HAL status
*/
HAL_StatusTypeDef SDIO_PowerState_ON(SDIO_TypeDef *SDIOx)
@@ -338,7 +336,7 @@
/**
* @brief Set SDMMC Power state to OFF.
- * @param SDIOx: Pointer to SDMMC register base
+ * @param SDIOx Pointer to SDMMC register base
* @retval HAL status
*/
HAL_StatusTypeDef SDIO_PowerState_OFF(SDIO_TypeDef *SDIOx)
@@ -351,7 +349,7 @@
/**
* @brief Get SDMMC Power state.
- * @param SDIOx: Pointer to SDMMC register base
+ * @param SDIOx Pointer to SDMMC register base
* @retval Power status of the controller. The returned value can be one of the
* following values:
* - 0x00: Power OFF
@@ -366,8 +364,8 @@
/**
* @brief Configure the SDMMC command path according to the specified parameters in
* SDIO_CmdInitTypeDef structure and send the command
- * @param SDIOx: Pointer to SDMMC register base
- * @param Command: pointer to a SDIO_CmdInitTypeDef structure that contains
+ * @param SDIOx Pointer to SDMMC register base
+ * @param Command pointer to a SDIO_CmdInitTypeDef structure that contains
* the configuration information for the SDMMC command
* @retval HAL status
*/
@@ -398,7 +396,7 @@
/**
* @brief Return the command index of last command for which response received
- * @param SDIOx: Pointer to SDMMC register base
+ * @param SDIOx Pointer to SDMMC register base
* @retval Command index of the last command response received
*/
uint8_t SDIO_GetCommandResponse(SDIO_TypeDef *SDIOx)
@@ -409,8 +407,8 @@
/**
* @brief Return the response received from the card for the last command
- * @param SDIOx: Pointer to SDMMC register base
- * @param Response: Specifies the SDMMC response register.
+ * @param SDIOx Pointer to SDMMC register base
+ * @param Response Specifies the SDMMC response register.
* This parameter can be one of the following values:
* @arg SDIO_RESP1: Response Register 1
* @arg SDIO_RESP1: Response Register 2
@@ -434,8 +432,8 @@
/**
* @brief Configure the SDMMC data path according to the specified
* parameters in the SDIO_DataInitTypeDef.
- * @param SDIOx: Pointer to SDMMC register base
- * @param Data : pointer to a SDIO_DataInitTypeDef structure
+ * @param SDIOx Pointer to SDMMC register base
+ * @param Data pointer to a SDIO_DataInitTypeDef structure
* that contains the configuration information for the SDMMC data.
* @retval HAL status
*/
@@ -471,7 +469,7 @@
/**
* @brief Returns number of remaining data bytes to be transferred.
- * @param SDIOx: Pointer to SDMMC register base
+ * @param SDIOx Pointer to SDMMC register base
* @retval Number of remaining data bytes to be transferred
*/
uint32_t SDIO_GetDataCounter(SDIO_TypeDef *SDIOx)
@@ -481,7 +479,7 @@
/**
* @brief Get the FIFO data
- * @param SDIOx: Pointer to SDMMC register base
+ * @param SDIOx Pointer to SDMMC register base
* @retval Data received
*/
uint32_t SDIO_GetFIFOCount(SDIO_TypeDef *SDIOx)
@@ -491,8 +489,8 @@
/**
* @brief Sets one of the two options of inserting read wait interval.
- * @param SDIOx: Pointer to SDMMC register base
- * @param SDIO_ReadWaitMode: SDMMC Read Wait operation mode.
+ * @param SDIOx Pointer to SDMMC register base
+ * @param SDIO_ReadWaitMode SDMMC Read Wait operation mode.
* This parameter can be:
* @arg SDIO_READ_WAIT_MODE_CLK: Read Wait control by stopping SDMMCCLK
* @arg SDIO_READ_WAIT_MODE_DATA2: Read Wait control using SDMMC_DATA2
@@ -530,7 +528,7 @@
/**
* @brief Send the Data Block Lenght command and check the response
- * @param SDIOx: Pointer to SDMMC register base
+ * @param SDIOx Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdBlockLength(SDIO_TypeDef *SDIOx, uint32_t BlockSize)
@@ -554,7 +552,7 @@
/**
* @brief Send the Read Single Block command and check the response
- * @param SDIOx: Pointer to SDMMC register base
+ * @param SDIOx Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdReadSingleBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd)
@@ -578,7 +576,7 @@
/**
* @brief Send the Read Multi Block command and check the response
- * @param SDIOx: Pointer to SDIO register base
+ * @param SDIOx Pointer to SDIO register base
* @retval HAL status
*/
uint32_t SDMMC_CmdReadMultiBlock(SDIO_TypeDef *SDIOx, uint32_t ReadAdd)
@@ -602,7 +600,7 @@
/**
* @brief Send the Write Single Block command and check the response
- * @param SDIOx: Pointer to SDIO register base
+ * @param SDIOx Pointer to SDIO register base
* @retval HAL status
*/
uint32_t SDMMC_CmdWriteSingleBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd)
@@ -626,7 +624,7 @@
/**
* @brief Send the Write Multi Block command and check the response
- * @param SDIOx: Pointer to SDIO register base
+ * @param SDIOx Pointer to SDIO register base
* @retval HAL status
*/
uint32_t SDMMC_CmdWriteMultiBlock(SDIO_TypeDef *SDIOx, uint32_t WriteAdd)
@@ -650,7 +648,7 @@
/**
* @brief Send the Start Address Erase command for SD and check the response
- * @param SDIOx: Pointer to SDIO register base
+ * @param SDIOx Pointer to SDIO register base
* @retval HAL status
*/
uint32_t SDMMC_CmdSDEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd)
@@ -674,7 +672,7 @@
/**
* @brief Send the End Address Erase command for SD and check the response
- * @param SDIOx: Pointer to SDIO register base
+ * @param SDIOx Pointer to SDIO register base
* @retval HAL status
*/
uint32_t SDMMC_CmdSDEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd)
@@ -698,7 +696,7 @@
/**
* @brief Send the Start Address Erase command and check the response
- * @param SDIOx: Pointer to SDIO register base
+ * @param SDIOx Pointer to SDIO register base
* @retval HAL status
*/
uint32_t SDMMC_CmdEraseStartAdd(SDIO_TypeDef *SDIOx, uint32_t StartAdd)
@@ -722,7 +720,7 @@
/**
* @brief Send the End Address Erase command and check the response
- * @param SDIOx: Pointer to SDIO register base
+ * @param SDIOx Pointer to SDIO register base
* @retval HAL status
*/
uint32_t SDMMC_CmdEraseEndAdd(SDIO_TypeDef *SDIOx, uint32_t EndAdd)
@@ -746,7 +744,7 @@
/**
* @brief Send the Erase command and check the response
- * @param SDIOx: Pointer to SDIO register base
+ * @param SDIOx Pointer to SDIO register base
* @retval HAL status
*/
uint32_t SDMMC_CmdErase(SDIO_TypeDef *SDIOx)
@@ -770,7 +768,7 @@
/**
* @brief Send the Stop Transfer command and check the response.
- * @param SDIOx: Pointer to SDIO register base
+ * @param SDIOx Pointer to SDIO register base
* @retval HAL status
*/
uint32_t SDMMC_CmdStopTransfer(SDIO_TypeDef *SDIOx)
@@ -794,8 +792,8 @@
/**
* @brief Send the Select Deselect command and check the response.
- * @param SDIOx: Pointer to SDIO register base
- * @param addr: Address of the card to be selected
+ * @param SDIOx Pointer to SDIO register base
+ * @param addr Address of the card to be selected
* @retval HAL status
*/
uint32_t SDMMC_CmdSelDesel(SDIO_TypeDef *SDIOx, uint64_t Addr)
@@ -819,7 +817,7 @@
/**
* @brief Send the Go Idle State command and check the response.
- * @param SDIOx: Pointer to SDIO register base
+ * @param SDIOx Pointer to SDIO register base
* @retval HAL status
*/
uint32_t SDMMC_CmdGoIdleState(SDIO_TypeDef *SDIOx)
@@ -842,7 +840,7 @@
/**
* @brief Send the Operating Condition command and check the response.
- * @param SDIOx: Pointer to SDIO register base
+ * @param SDIOx Pointer to SDIO register base
* @retval HAL status
*/
uint32_t SDMMC_CmdOperCond(SDIO_TypeDef *SDIOx)
@@ -872,7 +870,7 @@
* @brief Send the Application command to verify that that the next command
* is an application specific com-mand rather than a standard command
* and check the response.
- * @param SDIOx: Pointer to SDIO register base
+ * @param SDIOx Pointer to SDIO register base
* @retval HAL status
*/
uint32_t SDMMC_CmdAppCommand(SDIO_TypeDef *SDIOx, uint32_t Argument)
@@ -899,7 +897,7 @@
/**
* @brief Send the command asking the accessed card to send its operating
* condition register (OCR)
- * @param SDIOx: Pointer to SDIO register base
+ * @param SDIOx Pointer to SDIO register base
* @retval HAL status
*/
uint32_t SDMMC_CmdAppOperCommand(SDIO_TypeDef *SDIOx, uint32_t SdType)
@@ -922,7 +920,7 @@
/**
* @brief Send the Bus Width command and check the response.
- * @param SDIOx: Pointer to SDIO register base
+ * @param SDIOx Pointer to SDIO register base
* @retval HAL status
*/
uint32_t SDMMC_CmdBusWidth(SDIO_TypeDef *SDIOx, uint32_t BusWidth)
@@ -945,7 +943,7 @@
/**
* @brief Send the Send SCR command and check the response.
- * @param SDIOx: Pointer to SDMMC register base
+ * @param SDIOx Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdSendSCR(SDIO_TypeDef *SDIOx)
@@ -969,7 +967,7 @@
/**
* @brief Send the Send CID command and check the response.
- * @param SDIOx: Pointer to SDIO register base
+ * @param SDIOx Pointer to SDIO register base
* @retval HAL status
*/
uint32_t SDMMC_CmdSendCID(SDIO_TypeDef *SDIOx)
@@ -993,7 +991,7 @@
/**
* @brief Send the Send CSD command and check the response.
- * @param SDIOx: Pointer to SDIO register base
+ * @param SDIOx Pointer to SDIO register base
* @retval HAL status
*/
uint32_t SDMMC_CmdSendCSD(SDIO_TypeDef *SDIOx, uint32_t Argument)
@@ -1017,7 +1015,7 @@
/**
* @brief Send the Send CSD command and check the response.
- * @param SDIOx: Pointer to SDIO register base
+ * @param SDIOx Pointer to SDIO register base
* @retval HAL status
*/
uint32_t SDMMC_CmdSetRelAdd(SDIO_TypeDef *SDIOx, uint16_t *pRCA)
@@ -1041,7 +1039,7 @@
/**
* @brief Send the Status command and check the response.
- * @param SDIOx: Pointer to SDIO register base
+ * @param SDIOx Pointer to SDIO register base
* @retval HAL status
*/
uint32_t SDMMC_CmdSendStatus(SDIO_TypeDef *SDIOx, uint32_t Argument)
@@ -1064,7 +1062,7 @@
/**
* @brief Send the Status register command and check the response.
- * @param SDIOx: Pointer to SDIO register base
+ * @param SDIOx Pointer to SDIO register base
* @retval HAL status
*/
uint32_t SDMMC_CmdStatusRegister(SDIO_TypeDef *SDIOx)
@@ -1088,8 +1086,8 @@
/**
* @brief Sends host capacity support information and activates the card's
* initialization process. Send SDMMC_CMD_SEND_OP_COND command
- * @param SDIOx: Pointer to SDIO register base
- * @parame Argument: Argument used for the command
+ * @param SDIOx Pointer to SDIO register base
+ * @parame Argument Argument used for the command
* @retval HAL status
*/
uint32_t SDMMC_CmdOpCondition(SDIO_TypeDef *SDIOx, uint32_t Argument)
@@ -1112,8 +1110,8 @@
/**
* @brief Checks switchable function and switch card function. SDMMC_CMD_HS_SWITCH comand
- * @param SDIOx: Pointer to SDIO register base
- * @parame Argument: Argument used for the command
+ * @param SDIOx Pointer to SDIO register base
+ * @parame Argument Argument used for the command
* @retval HAL status
*/
uint32_t SDMMC_CmdSwitch(SDIO_TypeDef *SDIOx, uint32_t Argument)
@@ -1145,7 +1143,7 @@
/**
* @brief Checks for error conditions for CMD0.
- * @param hsd: SD handle
+ * @param hsd SD handle
* @retval SD Card error state
*/
static uint32_t SDMMC_GetCmdError(SDIO_TypeDef *SDIOx)
@@ -1171,8 +1169,8 @@
/**
* @brief Checks for error conditions for R1 response.
- * @param hsd: SD handle
- * @param SD_CMD: The sent command index
+ * @param hsd SD handle
+ * @param SD_CMD The sent command index
* @retval SD Card error state
*/
static uint32_t SDMMC_GetCmdResp1(SDIO_TypeDef *SDIOx, uint8_t SD_CMD, uint32_t Timeout)
@@ -1301,7 +1299,7 @@
/**
* @brief Checks for error conditions for R2 (CID or CSD) response.
- * @param hsd: SD handle
+ * @param hsd SD handle
* @retval SD Card error state
*/
static uint32_t SDMMC_GetCmdResp2(SDIO_TypeDef *SDIOx)
@@ -1343,7 +1341,7 @@
/**
* @brief Checks for error conditions for R3 (OCR) response.
- * @param hsd: SD handle
+ * @param hsd SD handle
* @retval SD Card error state
*/
static uint32_t SDMMC_GetCmdResp3(SDIO_TypeDef *SDIOx)
@@ -1379,9 +1377,9 @@
/**
* @brief Checks for error conditions for R6 (RCA) response.
- * @param hsd: SD handle
- * @param SD_CMD: The sent command index
- * @param pRCA: Pointer to the variable that will contain the SD card relative
+ * @param hsd SD handle
+ * @param SD_CMD The sent command index
+ * @param pRCA Pointer to the variable that will contain the SD card relative
* address RCA
* @retval SD Card error state
*/
@@ -1449,7 +1447,7 @@
/**
* @brief Checks for error conditions for R7 response.
- * @param hsd: SD handle
+ * @param hsd SD handle
* @retval SD Card error state
*/
static uint32_t SDMMC_GetCmdResp7(SDIO_TypeDef *SDIOx)
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_sdmmc.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_sdmmc.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_sdmmc.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of SDMMC HAL module. ****************************************************************************** * @attention @@ -739,35 +737,35 @@ /** * @brief Enable the SDIO device. - * @param __INSTANCE__: SDIO Instance + * @param __INSTANCE__ SDIO Instance * @retval None */ #define __SDIO_ENABLE(__INSTANCE__) (*(__IO uint32_t *)CLKCR_CLKEN_BB = ENABLE) /** * @brief Disable the SDIO device. - * @param __INSTANCE__: SDIO Instance + * @param __INSTANCE__ SDIO Instance * @retval None */ #define __SDIO_DISABLE(__INSTANCE__) (*(__IO uint32_t *)CLKCR_CLKEN_BB = DISABLE) /** * @brief Enable the SDIO DMA transfer. - * @param __INSTANCE__: SDIO Instance + * @param __INSTANCE__ SDIO Instance * @retval None */ #define __SDIO_DMA_ENABLE(__INSTANCE__) (*(__IO uint32_t *)DCTRL_DMAEN_BB = ENABLE) /** * @brief Disable the SDIO DMA transfer. - * @param __INSTANCE__: SDIO Instance + * @param __INSTANCE__ SDIO Instance * @retval None */ #define __SDIO_DMA_DISABLE(__INSTANCE__) (*(__IO uint32_t *)DCTRL_DMAEN_BB = DISABLE) /** * @brief Enable the SDIO device interrupt. - * @param __INSTANCE__ : Pointer to SDIO register base - * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be enabled. + * @param __INSTANCE__ Pointer to SDIO register base + * @param __INTERRUPT__ specifies the SDIO interrupt sources to be enabled. * This parameter can be one or a combination of the following values: * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -797,8 +795,8 @@ /** * @brief Disable the SDIO device interrupt. - * @param __INSTANCE__ : Pointer to SDIO register base - * @param __INTERRUPT__ : specifies the SDIO interrupt sources to be disabled. + * @param __INSTANCE__ Pointer to SDIO register base + * @param __INTERRUPT__ specifies the SDIO interrupt sources to be disabled. * This parameter can be one or a combination of the following values: * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -828,8 +826,8 @@ /** * @brief Checks whether the specified SDIO flag is set or not. - * @param __INSTANCE__ : Pointer to SDIO register base - * @param __FLAG__: specifies the flag to check. + * @param __INSTANCE__ Pointer to SDIO register base + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) @@ -860,8 +858,8 @@ /** * @brief Clears the SDIO pending flags. - * @param __INSTANCE__ : Pointer to SDIO register base - * @param __FLAG__: specifies the flag to clear. + * @param __INSTANCE__ Pointer to SDIO register base + * @param __FLAG__ specifies the flag to clear. * This parameter can be one or a combination of the following values: * @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed) * @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) @@ -880,8 +878,8 @@ /** * @brief Checks whether the specified SDIO interrupt has occurred or not. - * @param __INSTANCE__ : Pointer to SDIO register base - * @param __INTERRUPT__: specifies the SDIO interrupt source to check. + * @param __INSTANCE__ Pointer to SDIO register base + * @param __INTERRUPT__ specifies the SDIO interrupt source to check. * This parameter can be one of the following values: * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -911,8 +909,8 @@ /** * @brief Clears the SDIO's interrupt pending bits. - * @param __INSTANCE__ : Pointer to SDIO register base - * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * @param __INSTANCE__ Pointer to SDIO register base + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. * This parameter can be one or a combination of the following values: * @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -930,56 +928,56 @@ /** * @brief Enable Start the SD I/O Read Wait operation. - * @param __INSTANCE__ : Pointer to SDIO register base + * @param __INSTANCE__ Pointer to SDIO register base * @retval None */ #define __SDIO_START_READWAIT_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTART_BB = ENABLE) /** * @brief Disable Start the SD I/O Read Wait operations. - * @param __INSTANCE__ : Pointer to SDIO register base + * @param __INSTANCE__ Pointer to SDIO register base * @retval None */ #define __SDIO_START_READWAIT_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTART_BB = DISABLE) /** * @brief Enable Start the SD I/O Read Wait operation. - * @param __INSTANCE__ : Pointer to SDIO register base + * @param __INSTANCE__ Pointer to SDIO register base * @retval None */ #define __SDIO_STOP_READWAIT_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTOP_BB = ENABLE) /** * @brief Disable Stop the SD I/O Read Wait operations. - * @param __INSTANCE__ : Pointer to SDIO register base + * @param __INSTANCE__ Pointer to SDIO register base * @retval None */ #define __SDIO_STOP_READWAIT_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_RWSTOP_BB = DISABLE) /** * @brief Enable the SD I/O Mode Operation. - * @param __INSTANCE__ : Pointer to SDIO register base + * @param __INSTANCE__ Pointer to SDIO register base * @retval None */ #define __SDIO_OPERATION_ENABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_SDIOEN_BB = ENABLE) /** * @brief Disable the SD I/O Mode Operation. - * @param __INSTANCE__ : Pointer to SDIO register base + * @param __INSTANCE__ Pointer to SDIO register base * @retval None */ #define __SDIO_OPERATION_DISABLE(__INSTANCE__) (*(__IO uint32_t *) DCTRL_SDIOEN_BB = DISABLE) /** * @brief Enable the SD I/O Suspend command sending. - * @param __INSTANCE__ : Pointer to SDIO register base + * @param __INSTANCE__ Pointer to SDIO register base * @retval None */ #define __SDIO_SUSPEND_CMD_ENABLE(__INSTANCE__) (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = ENABLE) /** * @brief Disable the SD I/O Suspend command sending. - * @param __INSTANCE__ : Pointer to SDIO register base + * @param __INSTANCE__ Pointer to SDIO register base * @retval None */ #define __SDIO_SUSPEND_CMD_DISABLE(__INSTANCE__) (*(__IO uint32_t *) CMD_SDIOSUSPEND_BB = DISABLE)
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_spi.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_spi.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_spi.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief SPI LL module driver. ****************************************************************************** * @attention @@ -536,7 +534,7 @@ * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S). * @param SPIx SPI Instance - * @param PrescalerLinear value: Min_Data=0x02 and Max_Data=0xFF. + * @param PrescalerLinear value Min_Data=0x02 and Max_Data=0xFF. * @param PrescalerParity This parameter can be one of the following values: * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_spi.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_spi.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_spi.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of SPI LL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_system.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_system.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_system.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of SYSTEM LL module. @verbatim ============================================================================== @@ -94,12 +92,14 @@ #define LL_SYSCFG_REMAP_FLASH (uint32_t)0x00000000 /*!< Main Flash memory mapped at 0x00000000 */ #define LL_SYSCFG_REMAP_SYSTEMFLASH SYSCFG_MEMRMP_MEM_MODE_0 /*!< System Flash memory mapped at 0x00000000 */ #if defined(FSMC_Bank1) -#define LL_SYSCFG_REMAP_FSMC SYSCFG_MEMRMP_MEM_MODE_1 /*!< FSMC(NOR/PSRAM 1 and 2) mapped at 0x00000000 */ +#define LL_SYSCFG_REMAP_FSMC SYSCFG_MEMRMP_MEM_MODE_1 /*!< FSMC(NOR/PSRAM 1 and 2) mapped at 0x00000000 */ #endif /* FSMC_Bank1 */ #if defined(FMC_Bank1) -#define LL_SYSCFG_REMAP_FMC SYSCFG_MEMRMP_MEM_MODE_1 /*!< FMC(NOR/PSRAM 1 and 2) mapped at 0x00000000 */ +#define LL_SYSCFG_REMAP_FMC SYSCFG_MEMRMP_MEM_MODE_1 /*!< FMC(NOR/PSRAM 1 and 2) mapped at 0x00000000 */ +#define LL_SYSCFG_REMAP_SDRAM SYSCFG_MEMRMP_MEM_MODE_2 /*!< FMC/SDRAM mapped at 0x00000000 */ #endif /* FMC_Bank1 */ #define LL_SYSCFG_REMAP_SRAM (SYSCFG_MEMRMP_MEM_MODE_1 | SYSCFG_MEMRMP_MEM_MODE_0) /*!< SRAM1 mapped at 0x00000000 */ + /** * @} */
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_tim.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_tim.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_tim.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief TIM LL module driver. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_tim.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_tim.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_ll_tim.h
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief Header file of TIM LL module.
******************************************************************************
* @attention
@@ -1099,7 +1097,7 @@
*/
__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
{
- SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
+ CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
}
/**
@@ -1110,18 +1108,18 @@
*/
__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
{
- CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
+ SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
}
/**
* @brief Indicates whether update event generation is enabled.
* @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
* @param TIMx Timer instance
- * @retval State of bit (1 or 0).
+ * @retval Inverted state of bit (0 or 1).
*/
__STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
{
- return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (TIM_CR1_UDIS));
+ return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == RESET);
}
/**
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_usart.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_usart.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_ll_usart.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief USART LL module driver.
******************************************************************************
* @attention
@@ -75,7 +73,13 @@
/* __BAUDRATE__ The maximum Baud Rate is derived from the maximum clock available
* divided by the smallest oversampling used on the USART (i.e. 8) */
-#define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 10000000U)
+#define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 12500000U)
+
+/* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */
+#define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
+
+/* __VALUE__ BRR content must be lower than or equal to 0xFFFF. */
+#define IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
#define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
|| ((__VALUE__) == LL_USART_DIRECTION_RX) \
@@ -254,7 +258,7 @@
* USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
* @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
* @param USARTx USART Instance
- * @param USART_InitStruct: pointer to a LL_USART_InitTypeDef structure
+ * @param USART_InitStruct pointer to a LL_USART_InitTypeDef structure
* that contains the configuration information for the specified USART peripheral.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: USART registers are initialized according to USART_InitStruct content
@@ -361,7 +365,7 @@
}
#endif /* UART9 */
#if defined(UART10)
- else if (USARTx == UART5)
+ else if (USARTx == UART10)
{
periphclk = rcc_clocks.PCLK1_Frequency;
}
@@ -383,6 +387,12 @@
periphclk,
USART_InitStruct->OverSampling,
USART_InitStruct->BaudRate);
+
+ /* Check BRR is greater than or equal to 16d */
+ assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR));
+
+ /* Check BRR is greater than or equal to 16d */
+ assert_param(IS_LL_USART_BRR_MAX(USARTx->BRR));
}
}
/* Endif (=> USART not in Disabled state => return ERROR) */
@@ -392,7 +402,7 @@
/**
* @brief Set each @ref LL_USART_InitTypeDef field to default value.
- * @param USART_InitStruct: pointer to a @ref LL_USART_InitTypeDef structure
+ * @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure
* whose fields will be set to default values.
* @retval None
*/
@@ -415,7 +425,7 @@
* @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
* USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
* @param USARTx USART Instance
- * @param USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure
+ * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
* that contains the Clock configuration information for the specified USART peripheral.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
@@ -476,7 +486,7 @@
/**
* @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
- * @param USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure
+ * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
* whose fields will be set to default values.
* @retval None
*/
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_usart.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_usart.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_usart.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of USART LL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_usb.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_usb.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f4xx_ll_usb.c
* @author MCD Application Team
- * @version V1.7.1
- * @date 14-April-2017
* @brief USB Low Layer HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -97,8 +95,8 @@
/**
* @brief Initializes the USB Core
- * @param USBx: USB Instance
- * @param cfg : pointer to a USB_OTG_CfgTypeDef structure that contains
+ * @param USBx USB Instance
+ * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
* the configuration information for the specified USBx peripheral.
* @retval HAL status
*/
@@ -145,7 +143,7 @@
/**
* @brief USB_EnableGlobalInt
* Enables the controller's Global Int in the AHB Config reg
- * @param USBx : Selected device
+ * @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
@@ -158,7 +156,7 @@
/**
* @brief USB_DisableGlobalInt
* Disable the controller's Global Int in the AHB Config reg
- * @param USBx : Selected device
+ * @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
@@ -169,8 +167,8 @@
/**
* @brief USB_SetCurrentMode : Set functional mode
- * @param USBx : Selected device
- * @param mode : current core mode
+ * @param USBx Selected device
+ * @param mode current core mode
* This parameter can be one of these values:
* @arg USB_OTG_DEVICE_MODE: Peripheral mode
* @arg USB_OTG_HOST_MODE: Host mode
@@ -197,8 +195,8 @@
/**
* @brief USB_DevInit : Initializes the USB_OTG controller registers
* for device mode
- * @param USBx : Selected device
- * @param cfg : pointer to a USB_OTG_CfgTypeDef structure that contains
+ * @param USBx Selected device
+ * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
* the configuration information for the specified USBx peripheral.
* @retval HAL status
*/
@@ -342,8 +340,8 @@
/**
* @brief USB_OTG_FlushTxFifo : Flush a Tx FIFO
- * @param USBx : Selected device
- * @param num : FIFO number
+ * @param USBx Selected device
+ * @param num FIFO number
* This parameter can be a value from 1 to 15
15 means Flush all Tx FIFOs
* @retval HAL status
@@ -369,7 +367,7 @@
/**
* @brief USB_FlushRxFifo : Flush Rx FIFO
- * @param USBx : Selected device
+ * @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
@@ -393,8 +391,8 @@
/**
* @brief USB_SetDevSpeed :Initializes the DevSpd field of DCFG register
* depending the PHY type and the enumeration speed of the device.
- * @param USBx : Selected device
- * @param speed : device speed
+ * @param USBx Selected device
+ * @param speed device speed
* This parameter can be one of these values:
* @arg USB_OTG_SPEED_HIGH: High speed mode
* @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode
@@ -410,7 +408,7 @@
/**
* @brief USB_GetDevSpeed :Return the Dev Speed
- * @param USBx : Selected device
+ * @param USBx Selected device
* @retval speed : device speed
* This parameter can be one of these values:
* @arg USB_OTG_SPEED_HIGH: High speed mode
@@ -440,8 +438,8 @@
/**
* @brief Activate and configure an endpoint
- * @param USBx : Selected device
- * @param ep: pointer to endpoint structure
+ * @param USBx Selected device
+ * @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
@@ -470,8 +468,8 @@
}
/**
* @brief Activate and configure a dedicated endpoint
- * @param USBx : Selected device
- * @param ep: pointer to endpoint structure
+ * @param USBx Selected device
+ * @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
@@ -513,8 +511,8 @@
}
/**
* @brief De-activate and de-initialize an endpoint
- * @param USBx : Selected device
- * @param ep: pointer to endpoint structure
+ * @param USBx Selected device
+ * @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
@@ -584,8 +582,8 @@
/**
* @brief De-activate and de-initialize a dedicated endpoint
- * @param USBx : Selected device
- * @param ep: pointer to endpoint structure
+ * @param USBx Selected device
+ * @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
@@ -656,9 +654,9 @@
/**
* @brief USB_EPStartXfer : setup and starts a transfer over an EP
- * @param USBx : Selected device
- * @param ep: pointer to endpoint structure
- * @param dma: USB dma enabled or disabled
+ * @param USBx Selected device
+ * @param ep pointer to endpoint structure
+ * @param dma USB dma enabled or disabled
* This parameter can be one of these values:
* 0 : DMA feature not used
* 1 : DMA feature used
@@ -708,7 +706,9 @@
/* Enable the Tx FIFO Empty Interrupt for this EP */
if (ep->xfer_len > 0U)
{
+/* MBED */
atomic_set_u32(&USBx_DEVICE->DIEPEMPMSK, 1U << ep->num);
+/* MBED */
}
}
}
@@ -778,9 +778,9 @@
/**
* @brief USB_EP0StartXfer : setup and starts a transfer over the EP 0
- * @param USBx : Selected device
- * @param ep: pointer to endpoint structure
- * @param dma: USB dma enabled or disabled
+ * @param USBx Selected device
+ * @param ep pointer to endpoint structure
+ * @param dma USB dma enabled or disabled
* This parameter can be one of these values:
* 0 : DMA feature not used
* 1 : DMA feature used
@@ -829,7 +829,9 @@
/* Enable the Tx FIFO Empty Interrupt for this EP */
if (ep->xfer_len > 0U)
{
+/* MBED */
atomic_set_u32(&USBx_DEVICE->DIEPEMPMSK, 1U << (ep->num));
+/* MBED */
}
}
}
@@ -866,11 +868,11 @@
/**
* @brief USB_WritePacket : Writes a packet into the Tx FIFO associated
* with the EP/channel
- * @param USBx : Selected device
- * @param src : pointer to source buffer
- * @param ch_ep_num : endpoint or host channel number
- * @param len : Number of bytes to write
- * @param dma: USB dma enabled or disabled
+ * @param USBx Selected device
+ * @param src pointer to source buffer
+ * @param ch_ep_num endpoint or host channel number
+ * @param len Number of bytes to write
+ * @param dma USB dma enabled or disabled
* This parameter can be one of these values:
* 0 : DMA feature not used
* 1 : DMA feature used
@@ -894,11 +896,11 @@
/**
* @brief USB_ReadPacket : read a packet from the Tx FIFO associated
* with the EP/channel
- * @param USBx : Selected device
- * @param src : source pointer
- * @param ch_ep_num : endpoint or host channel number
- * @param len : Number of bytes to read
- * @param dma: USB dma enabled or disabled
+ * @param USBx Selected device
+ * @param src source pointer
+ * @param ch_ep_num endpoint or host channel number
+ * @param len Number of bytes to read
+ * @param dma USB dma enabled or disabled
* This parameter can be one of these values:
* 0 : DMA feature not used
* 1 : DMA feature used
@@ -919,8 +921,8 @@
/**
* @brief USB_EPSetStall : set a stall condition over an EP
- * @param USBx : Selected device
- * @param ep: pointer to endpoint structure
+ * @param USBx Selected device
+ * @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep)
@@ -947,8 +949,8 @@
/**
* @brief USB_EPClearStall : Clear a stall condition over an EP
- * @param USBx : Selected device
- * @param ep: pointer to endpoint structure
+ * @param USBx Selected device
+ * @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
@@ -974,7 +976,7 @@
/**
* @brief USB_StopDevice : Stop the usb device mode
- * @param USBx : Selected device
+ * @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx)
@@ -1003,8 +1005,8 @@
/**
* @brief USB_SetDevAddress : Stop the usb device mode
- * @param USBx : Selected device
- * @param address : new device address to be assigned
+ * @param USBx Selected device
+ * @param address new device address to be assigned
* This parameter can be a value from 0 to 255
* @retval HAL status
*/
@@ -1018,7 +1020,7 @@
/**
* @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down
- * @param USBx : Selected device
+ * @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx)
@@ -1031,7 +1033,7 @@
/**
* @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down
- * @param USBx : Selected device
+ * @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx)
@@ -1044,7 +1046,7 @@
/**
* @brief USB_ReadInterrupts: return the global USB interrupt status
- * @param USBx : Selected device
+ * @param USBx Selected device
* @retval HAL status
*/
uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx)
@@ -1058,7 +1060,7 @@
/**
* @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status
- * @param USBx : Selected device
+ * @param USBx Selected device
* @retval HAL status
*/
uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx)
@@ -1071,7 +1073,7 @@
/**
* @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status
- * @param USBx : Selected device
+ * @param USBx Selected device
* @retval HAL status
*/
uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx)
@@ -1084,8 +1086,8 @@
/**
* @brief Returns Device OUT EP Interrupt register
- * @param USBx : Selected device
- * @param epnum : endpoint number
+ * @param USBx Selected device
+ * @param epnum endpoint number
* This parameter can be a value from 0 to 15
* @retval Device OUT EP Interrupt register
*/
@@ -1099,8 +1101,8 @@
/**
* @brief Returns Device IN EP Interrupt register
- * @param USBx : Selected device
- * @param epnum : endpoint number
+ * @param USBx Selected device
+ * @param epnum endpoint number
* This parameter can be a value from 0 to 15
* @retval Device IN EP Interrupt register
*/
@@ -1117,8 +1119,8 @@
/**
* @brief USB_ClearInterrupts: clear a USB interrupt
- * @param USBx : Selected device
- * @param interrupt : interrupt flag
+ * @param USBx Selected device
+ * @param interrupt interrupt flag
* @retval None
*/
void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)
@@ -1128,7 +1130,7 @@
/**
* @brief Returns USB core mode
- * @param USBx : Selected device
+ * @param USBx Selected device
* @retval return core mode : Host or Device
* This parameter can be one of these values:
* 0 : Host
@@ -1142,7 +1144,7 @@
/**
* @brief Activate EP0 for Setup transactions
- * @param USBx : Selected device
+ * @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx)
@@ -1162,12 +1164,12 @@
/**
* @brief Prepare the EP0 to start the first control setup
- * @param USBx : Selected device
- * @param dma: USB dma enabled or disabled
+ * @param USBx Selected device
+ * @param dma USB dma enabled or disabled
* This parameter can be one of these values:
* 0 : DMA feature not used
* 1 : DMA feature used
- * @param psetup : pointer to setup packet
+ * @param psetup pointer to setup packet
* @retval HAL status
*/
HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup)
@@ -1190,7 +1192,7 @@
/**
* @brief Reset the USB Core (needed after USB clock settings change)
- * @param USBx : Selected device
+ * @param USBx Selected device
* @retval HAL status
*/
static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
@@ -1227,8 +1229,8 @@
/**
* @brief USB_HostInit : Initializes the USB OTG controller registers
* for Host mode
- * @param USBx : Selected device
- * @param cfg : pointer to a USB_OTG_CfgTypeDef structure that contains
+ * @param USBx Selected device
+ * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
* the configuration information for the specified USBx peripheral.
* @retval HAL status
*/
@@ -1314,8 +1316,8 @@
/**
* @brief USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the
* HCFG register on the PHY type and set the right frame interval
- * @param USBx : Selected device
- * @param freq : clock frequency
+ * @param USBx Selected device
+ * @param freq clock frequency
* This parameter can be one of these values:
* HCFG_48_MHZ : Full Speed 48 MHz Clock
* HCFG_6_MHZ : Low Speed 6 MHz Clock
@@ -1339,7 +1341,7 @@
/**
* @brief USB_OTG_ResetPort : Reset Host Port
- * @param USBx : Selected device
+ * @param USBx Selected device
* @retval HAL status
* @note (1)The application must wait at least 10 ms
* before clearing the reset bit.
@@ -1361,7 +1363,7 @@
/**
* @brief USB_DriveVbus : activate or de-activate vbus
- * @param state : VBUS state
+ * @param state VBUS state
* This parameter can be one of these values:
* 0 : VBUS Active
* 1 : VBUS Inactive
@@ -1388,7 +1390,7 @@
/**
* @brief Return Host Core speed
- * @param USBx : Selected device
+ * @param USBx Selected device
* @retval speed : Host speed
* This parameter can be one of these values:
* @arg USB_OTG_SPEED_HIGH: High speed mode
@@ -1405,7 +1407,7 @@
/**
* @brief Return Host Current Frame number
- * @param USBx : Selected device
+ * @param USBx Selected device
* @retval current frame number
*/
uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx)
@@ -1415,25 +1417,25 @@
/**
* @brief Initialize a host channel
- * @param USBx : Selected device
- * @param ch_num : Channel number
+ * @param USBx Selected device
+ * @param ch_num Channel number
* This parameter can be a value from 1 to 15
- * @param epnum : Endpoint number
+ * @param epnum Endpoint number
* This parameter can be a value from 1 to 15
- * @param dev_address : Current device address
+ * @param dev_address Current device address
* This parameter can be a value from 0 to 255
- * @param speed : Current device speed
+ * @param speed Current device speed
* This parameter can be one of these values:
* @arg USB_OTG_SPEED_HIGH: High speed mode
* @arg USB_OTG_SPEED_FULL: Full speed mode
* @arg USB_OTG_SPEED_LOW: Low speed mode
- * @param ep_type : Endpoint Type
+ * @param ep_type Endpoint Type
* This parameter can be one of these values:
* @arg EP_TYPE_CTRL: Control type
* @arg EP_TYPE_ISOC: Isochronous type
* @arg EP_TYPE_BULK: Bulk type
* @arg EP_TYPE_INTR: Interrupt type
- * @param mps : Max Packet Size
+ * @param mps Max Packet Size
* This parameter can be a value from 0 to32K
* @retval HAL state
*/
@@ -1529,9 +1531,9 @@
/**
* @brief Start a transfer over a host channel
- * @param USBx : Selected device
- * @param hc : pointer to host channel structure
- * @param dma: USB dma enabled or disabled
+ * @param USBx Selected device
+ * @param hc pointer to host channel structure
+ * @param dma USB dma enabled or disabled
* This parameter can be one of these values:
* 0 : DMA feature not used
* 1 : DMA feature used
@@ -1642,7 +1644,9 @@
/* Write packet into the Tx FIFO. */
USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, hc->xfer_len, 0);
+/* MBED */
hc->xfer_count = hc->xfer_len;
+/* MBED */
}
}
@@ -1651,7 +1655,7 @@
/**
* @brief Read all host channel interrupts status
- * @param USBx : Selected device
+ * @param USBx Selected device
* @retval HAL state
*/
uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx)
@@ -1661,8 +1665,8 @@
/**
* @brief Halt a host channel
- * @param USBx : Selected device
- * @param hc_num : Host Channel number
+ * @param USBx Selected device
+ * @param hc_num Host Channel number
* This parameter can be a value from 1 to 15
* @retval HAL state
*/
@@ -1722,8 +1726,8 @@
/**
* @brief Initiate Do Ping protocol
- * @param USBx : Selected device
- * @param hc_num : Host Channel number
+ * @param USBx Selected device
+ * @param hc_num Host Channel number
* This parameter can be a value from 1 to 15
* @retval HAL state
*/
@@ -1746,7 +1750,7 @@
/**
* @brief Stop Host Core
- * @param USBx : Selected device
+ * @param USBx Selected device
* @retval HAL state
*/
HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_usb.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_usb.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_usb.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of USB Core HAL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_utils.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_utils.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_utils.c * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief UTILS LL module driver. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_utils.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_utils.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_utils.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of UTILS LL module. @verbatim ==============================================================================
--- a/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_wwdg.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/stm32f4xx_ll_wwdg.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f4xx_ll_wwdg.h * @author MCD Application Team - * @version V1.7.1 - * @date 14-April-2017 * @brief Header file of WWDG LL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F4/device/system_stm32f4xx.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F4/device/system_stm32f4xx.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file system_stm32f4xx.c * @author MCD Application Team - * @version V2.6.1 - * @date 14-February-2017 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File. * * This file provides two functions and one global variable to be called from
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F4/hal_init_pre.c Tue Mar 20 16:56:18 2018 +0000
@@ -0,0 +1,31 @@
+/*
+ * Copyright (c) 2015-2015, ARM Limited, All Rights Reserved
+ * SPDX-License-Identifier: Apache-2.0
+ *
+ * Licensed under the Apache License, Version 2.0 (the "License"); you may
+ * not use this file except in compliance with the License.
+ * You may obtain a copy of the License at
+ *
+ * http://www.apache.org/licenses/LICENSE-2.0
+ *
+ * Unless required by applicable law or agreed to in writing, software
+ * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
+ * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ * See the License for the specific language governing permissions and
+ * limitations under the License.
+ */
+#include "stm32f4xx_hal.h"
+
+HAL_StatusTypeDef HAL_InitPre(void);
+
+/* this function is needed to peform hardware initialization that must happen
+ * before the uVisor; the whole SystemInit function for the STM32F4 cannot be
+ * put here as it depends on some APIs that need uVisor to be enabled */
+HAL_StatusTypeDef HAL_InitPre(void)
+{
+ /* Set Interrupt Group Priority */
+ HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
+
+ /* Return function status */
+ return HAL_OK;
+}
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/system_clock.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_DISCO_F746NG/system_clock.c Tue Mar 20 16:56:18 2018 +0000
@@ -211,7 +211,7 @@
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
- RCC_OscInitStruct.HSICalibrationValue = 16;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8)
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/system_clock.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/TARGET_NUCLEO_F746ZG/system_clock.c Tue Mar 20 16:56:18 2018 +0000
@@ -212,7 +212,7 @@
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
- RCC_OscInitStruct.HSICalibrationValue = 16;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8)
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/stm32f746xx.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/stm32f746xx.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f746xx.h * @author MCD Application Team - * @version V1.2.0 - * @date 30-December-2016 * @brief CMSIS Cortex-M7 Device Peripheral Access Layer Header File. * * This file contains:
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/stm32f7xx.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/stm32f7xx.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,19 +2,17 @@
******************************************************************************
* @file stm32f7xx.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 30-December-2016
- * @brief CMSIS STM32F7xx Device Peripheral Access Layer Header File.
- *
+ * @brief CMSIS STM32F7xx Device Peripheral Access Layer Header File.
+ *
* The file is the unique include file that the application programmer
* is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select:
* - The STM32F7xx device used in the target application
- * - To use or not the peripherals drivers in application code(i.e.
+ * - To use or not the peripherals drivers in application code(i.e.
* code will be based on direct access to peripherals registers
* rather than drivers API), this option is controlled by
* "#define USE_HAL_DRIVER"
- *
+ *
******************************************************************************
* @attention
*
@@ -52,14 +50,14 @@
/** @addtogroup stm32f7xx
* @{
*/
-
+
#ifndef __STM32F7xx_H
#define __STM32F7xx_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
-
+
/** @addtogroup Library_configuration_section
* @{
*/
@@ -72,7 +70,7 @@
#endif /* STM32F7 */
/* Uncomment the line below according to the target STM32 device used in your
- application
+ application
*/
#if !defined (STM32F756xx) && !defined (STM32F746xx) && !defined (STM32F745xx) && !defined (STM32F767xx) && \
!defined (STM32F769xx) && !defined (STM32F777xx) && !defined (STM32F779xx) && !defined (STM32F722xx) && \
@@ -104,19 +102,19 @@
#if !defined (USE_HAL_DRIVER)
/**
* @brief Comment the line below if you will not use the peripherals drivers.
- In this case, these drivers will not be included and the application code will
- be based on direct access to peripherals registers
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
*/
#define USE_HAL_DRIVER
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS Device version number V1.2.0
+ * @brief CMSIS Device version number V1.2.2
*/
#define __STM32F7_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32F7_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
-#define __STM32F7_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
-#define __STM32F7_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
+#define __STM32F7_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
+#define __STM32F7_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F7_CMSIS_VERSION ((__STM32F7_CMSIS_VERSION_MAIN << 24)\
|(__STM32F7_CMSIS_VERSION_SUB1 << 16)\
|(__STM32F7_CMSIS_VERSION_SUB2 << 8 )\
@@ -135,7 +133,7 @@
#elif defined(STM32F732xx)
#include "stm32f732xx.h"
#elif defined(STM32F733xx)
- #include "stm32f733xx.h"
+ #include "stm32f733xx.h"
#elif defined(STM32F756xx)
#include "stm32f756xx.h"
#elif defined(STM32F746xx)
@@ -151,7 +149,7 @@
#elif defined(STM32F777xx)
#include "stm32f777xx.h"
#elif defined(STM32F779xx)
- #include "stm32f779xx.h"
+ #include "stm32f779xx.h"
#else
#error "Please select first the target STM32F7xx device used in your application (in stm32f7xx.h file)"
#endif
@@ -162,30 +160,30 @@
/** @addtogroup Exported_types
* @{
- */
-typedef enum
+ */
+typedef enum
{
- RESET = 0,
+ RESET = 0U,
SET = !RESET
} FlagStatus, ITStatus;
-typedef enum
+typedef enum
{
- DISABLE = 0,
+ DISABLE = 0U,
ENABLE = !DISABLE
} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
-typedef enum
+typedef enum
{
- ERROR = 0,
+ ERROR = 0U,
SUCCESS = !ERROR
} ErrorStatus;
/**
* @}
*/
-
+
/** @addtogroup Exported_macro
* @{
*/
@@ -203,14 +201,14 @@
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
-#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
/**
* @}
*/
#ifdef USE_HAL_DRIVER
- #include "stm32f7xx_hal.h"
+ #include "stm32f7xx_hal.h"
#endif /* USE_HAL_DRIVER */
#ifdef __cplusplus
@@ -223,7 +221,7 @@
* @}
*/
- /**
+/**
* @}
*/
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/system_stm32f7xx.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F746xG/device/system_stm32f7xx.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file system_stm32f7xx.h * @author MCD Application Team - * @version V1.2.0 - * @date 30-December-2016 * @brief CMSIS Cortex-M7 Device System Source File for STM32F7xx devices. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/system_clock.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/TARGET_NUCLEO_F756ZG/system_clock.c Tue Mar 20 16:56:18 2018 +0000
@@ -211,7 +211,7 @@
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSE;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
- RCC_OscInitStruct.HSICalibrationValue = 16;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 1 MHz (16 MHz / 16)
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/stm32f756xx.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/stm32f756xx.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f756xx.h * @author MCD Application Team - * @version V1.2.0 - * @date 30-December-2016 * @brief CMSIS Cortex-M7 Device Peripheral Access Layer Header File. * * This file contains:
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/stm32f7xx.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/stm32f7xx.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,19 +2,17 @@
******************************************************************************
* @file stm32f7xx.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 30-December-2016
- * @brief CMSIS STM32F7xx Device Peripheral Access Layer Header File.
- *
+ * @brief CMSIS STM32F7xx Device Peripheral Access Layer Header File.
+ *
* The file is the unique include file that the application programmer
* is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select:
* - The STM32F7xx device used in the target application
- * - To use or not the peripherals drivers in application code(i.e.
+ * - To use or not the peripherals drivers in application code(i.e.
* code will be based on direct access to peripherals registers
* rather than drivers API), this option is controlled by
* "#define USE_HAL_DRIVER"
- *
+ *
******************************************************************************
* @attention
*
@@ -52,14 +50,14 @@
/** @addtogroup stm32f7xx
* @{
*/
-
+
#ifndef __STM32F7xx_H
#define __STM32F7xx_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
-
+
/** @addtogroup Library_configuration_section
* @{
*/
@@ -72,7 +70,7 @@
#endif /* STM32F7 */
/* Uncomment the line below according to the target STM32 device used in your
- application
+ application
*/
#if !defined (STM32F756xx) && !defined (STM32F746xx) && !defined (STM32F745xx) && !defined (STM32F767xx) && \
!defined (STM32F769xx) && !defined (STM32F777xx) && !defined (STM32F779xx) && !defined (STM32F722xx) && \
@@ -104,19 +102,19 @@
#if !defined (USE_HAL_DRIVER)
/**
* @brief Comment the line below if you will not use the peripherals drivers.
- In this case, these drivers will not be included and the application code will
- be based on direct access to peripherals registers
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
*/
#define USE_HAL_DRIVER
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS Device version number V1.2.0
+ * @brief CMSIS Device version number V1.2.2
*/
#define __STM32F7_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32F7_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
-#define __STM32F7_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
-#define __STM32F7_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
+#define __STM32F7_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
+#define __STM32F7_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F7_CMSIS_VERSION ((__STM32F7_CMSIS_VERSION_MAIN << 24)\
|(__STM32F7_CMSIS_VERSION_SUB1 << 16)\
|(__STM32F7_CMSIS_VERSION_SUB2 << 8 )\
@@ -135,7 +133,7 @@
#elif defined(STM32F732xx)
#include "stm32f732xx.h"
#elif defined(STM32F733xx)
- #include "stm32f733xx.h"
+ #include "stm32f733xx.h"
#elif defined(STM32F756xx)
#include "stm32f756xx.h"
#elif defined(STM32F746xx)
@@ -151,7 +149,7 @@
#elif defined(STM32F777xx)
#include "stm32f777xx.h"
#elif defined(STM32F779xx)
- #include "stm32f779xx.h"
+ #include "stm32f779xx.h"
#else
#error "Please select first the target STM32F7xx device used in your application (in stm32f7xx.h file)"
#endif
@@ -162,30 +160,30 @@
/** @addtogroup Exported_types
* @{
- */
-typedef enum
+ */
+typedef enum
{
- RESET = 0,
+ RESET = 0U,
SET = !RESET
} FlagStatus, ITStatus;
-typedef enum
+typedef enum
{
- DISABLE = 0,
+ DISABLE = 0U,
ENABLE = !DISABLE
} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
-typedef enum
+typedef enum
{
- ERROR = 0,
+ ERROR = 0U,
SUCCESS = !ERROR
} ErrorStatus;
/**
* @}
*/
-
+
/** @addtogroup Exported_macro
* @{
*/
@@ -203,14 +201,14 @@
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
-#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
/**
* @}
*/
#ifdef USE_HAL_DRIVER
- #include "stm32f7xx_hal.h"
+ #include "stm32f7xx_hal.h"
#endif /* USE_HAL_DRIVER */
#ifdef __cplusplus
@@ -223,7 +221,7 @@
* @}
*/
- /**
+/**
* @}
*/
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/system_stm32f7xx.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F756xG/device/system_stm32f7xx.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file system_stm32f7xx.h * @author MCD Application Team - * @version V1.2.0 - * @date 30-December-2016 * @brief CMSIS Cortex-M7 Device System Source File for STM32F7xx devices. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/system_clock.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/TARGET_NUCLEO_F767ZI/system_clock.c Tue Mar 20 16:56:18 2018 +0000
@@ -213,7 +213,7 @@
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
- RCC_OscInitStruct.HSICalibrationValue = 16;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
RCC_OscInitStruct.PLL.PLLM = 8; // VCO input clock = 2 MHz (16 MHz / 8)
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/stm32f767xx.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/stm32f767xx.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f767xx.h * @author MCD Application Team - * @version V1.2.0 - * @date 30-December-2016 * @brief CMSIS Cortex-M7 Device Peripheral Access Layer Header File. * * This file contains:
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/stm32f7xx.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/stm32f7xx.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,19 +2,17 @@
******************************************************************************
* @file stm32f7xx.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 30-December-2016
- * @brief CMSIS STM32F7xx Device Peripheral Access Layer Header File.
- *
+ * @brief CMSIS STM32F7xx Device Peripheral Access Layer Header File.
+ *
* The file is the unique include file that the application programmer
* is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select:
* - The STM32F7xx device used in the target application
- * - To use or not the peripherals drivers in application code(i.e.
+ * - To use or not the peripherals drivers in application code(i.e.
* code will be based on direct access to peripherals registers
* rather than drivers API), this option is controlled by
* "#define USE_HAL_DRIVER"
- *
+ *
******************************************************************************
* @attention
*
@@ -52,14 +50,14 @@
/** @addtogroup stm32f7xx
* @{
*/
-
+
#ifndef __STM32F7xx_H
#define __STM32F7xx_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
-
+
/** @addtogroup Library_configuration_section
* @{
*/
@@ -72,7 +70,7 @@
#endif /* STM32F7 */
/* Uncomment the line below according to the target STM32 device used in your
- application
+ application
*/
#if !defined (STM32F756xx) && !defined (STM32F746xx) && !defined (STM32F745xx) && !defined (STM32F767xx) && \
!defined (STM32F769xx) && !defined (STM32F777xx) && !defined (STM32F779xx) && !defined (STM32F722xx) && \
@@ -104,19 +102,19 @@
#if !defined (USE_HAL_DRIVER)
/**
* @brief Comment the line below if you will not use the peripherals drivers.
- In this case, these drivers will not be included and the application code will
- be based on direct access to peripherals registers
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
*/
#define USE_HAL_DRIVER
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS Device version number V1.2.0
+ * @brief CMSIS Device version number V1.2.2
*/
#define __STM32F7_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32F7_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
-#define __STM32F7_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
-#define __STM32F7_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
+#define __STM32F7_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
+#define __STM32F7_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F7_CMSIS_VERSION ((__STM32F7_CMSIS_VERSION_MAIN << 24)\
|(__STM32F7_CMSIS_VERSION_SUB1 << 16)\
|(__STM32F7_CMSIS_VERSION_SUB2 << 8 )\
@@ -135,7 +133,7 @@
#elif defined(STM32F732xx)
#include "stm32f732xx.h"
#elif defined(STM32F733xx)
- #include "stm32f733xx.h"
+ #include "stm32f733xx.h"
#elif defined(STM32F756xx)
#include "stm32f756xx.h"
#elif defined(STM32F746xx)
@@ -151,7 +149,7 @@
#elif defined(STM32F777xx)
#include "stm32f777xx.h"
#elif defined(STM32F779xx)
- #include "stm32f779xx.h"
+ #include "stm32f779xx.h"
#else
#error "Please select first the target STM32F7xx device used in your application (in stm32f7xx.h file)"
#endif
@@ -162,30 +160,30 @@
/** @addtogroup Exported_types
* @{
- */
-typedef enum
+ */
+typedef enum
{
- RESET = 0,
+ RESET = 0U,
SET = !RESET
} FlagStatus, ITStatus;
-typedef enum
+typedef enum
{
- DISABLE = 0,
+ DISABLE = 0U,
ENABLE = !DISABLE
} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
-typedef enum
+typedef enum
{
- ERROR = 0,
+ ERROR = 0U,
SUCCESS = !ERROR
} ErrorStatus;
/**
* @}
*/
-
+
/** @addtogroup Exported_macro
* @{
*/
@@ -203,14 +201,14 @@
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
-#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
/**
* @}
*/
#ifdef USE_HAL_DRIVER
- #include "stm32f7xx_hal.h"
+ #include "stm32f7xx_hal.h"
#endif /* USE_HAL_DRIVER */
#ifdef __cplusplus
@@ -223,7 +221,7 @@
* @}
*/
- /**
+/**
* @}
*/
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/system_stm32f7xx.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F767xI/device/system_stm32f7xx.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file system_stm32f7xx.h * @author MCD Application Team - * @version V1.2.0 - * @date 30-December-2016 * @brief CMSIS Cortex-M7 Device System Source File for STM32F7xx devices. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/system_clock.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/TARGET_DISCO_F769NI/system_clock.c Tue Mar 20 16:56:18 2018 +0000
@@ -215,7 +215,7 @@
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
- RCC_OscInitStruct.HSICalibrationValue = 16;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSI;
RCC_OscInitStruct.PLL.PLLM = 16; // VCO input clock = 1 MHz (16 MHz / 16)
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/device/stm32f769xx.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/device/stm32f769xx.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f769xx.h * @author MCD Application Team - * @version V1.2.0 - * @date 30-December-2016 * @brief CMSIS Cortex-M7 Device Peripheral Access Layer Header File. * * This file contains:
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/device/stm32f7xx.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/device/stm32f7xx.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,19 +2,17 @@
******************************************************************************
* @file stm32f7xx.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 30-December-2016
- * @brief CMSIS STM32F7xx Device Peripheral Access Layer Header File.
- *
+ * @brief CMSIS STM32F7xx Device Peripheral Access Layer Header File.
+ *
* The file is the unique include file that the application programmer
* is using in the C source code, usually in main.c. This file contains:
* - Configuration section that allows to select:
* - The STM32F7xx device used in the target application
- * - To use or not the peripherals drivers in application code(i.e.
+ * - To use or not the peripherals drivers in application code(i.e.
* code will be based on direct access to peripherals registers
* rather than drivers API), this option is controlled by
* "#define USE_HAL_DRIVER"
- *
+ *
******************************************************************************
* @attention
*
@@ -52,14 +50,14 @@
/** @addtogroup stm32f7xx
* @{
*/
-
+
#ifndef __STM32F7xx_H
#define __STM32F7xx_H
#ifdef __cplusplus
extern "C" {
#endif /* __cplusplus */
-
+
/** @addtogroup Library_configuration_section
* @{
*/
@@ -72,7 +70,7 @@
#endif /* STM32F7 */
/* Uncomment the line below according to the target STM32 device used in your
- application
+ application
*/
#if !defined (STM32F756xx) && !defined (STM32F746xx) && !defined (STM32F745xx) && !defined (STM32F767xx) && \
!defined (STM32F769xx) && !defined (STM32F777xx) && !defined (STM32F779xx) && !defined (STM32F722xx) && \
@@ -104,19 +102,19 @@
#if !defined (USE_HAL_DRIVER)
/**
* @brief Comment the line below if you will not use the peripherals drivers.
- In this case, these drivers will not be included and the application code will
- be based on direct access to peripherals registers
+ In this case, these drivers will not be included and the application code will
+ be based on direct access to peripherals registers
*/
#define USE_HAL_DRIVER
#endif /* USE_HAL_DRIVER */
/**
- * @brief CMSIS Device version number V1.2.0
+ * @brief CMSIS Device version number V1.2.2
*/
#define __STM32F7_CMSIS_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32F7_CMSIS_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
-#define __STM32F7_CMSIS_VERSION_SUB2 (0x00) /*!< [15:8] sub2 version */
-#define __STM32F7_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
+#define __STM32F7_CMSIS_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
+#define __STM32F7_CMSIS_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F7_CMSIS_VERSION ((__STM32F7_CMSIS_VERSION_MAIN << 24)\
|(__STM32F7_CMSIS_VERSION_SUB1 << 16)\
|(__STM32F7_CMSIS_VERSION_SUB2 << 8 )\
@@ -135,7 +133,7 @@
#elif defined(STM32F732xx)
#include "stm32f732xx.h"
#elif defined(STM32F733xx)
- #include "stm32f733xx.h"
+ #include "stm32f733xx.h"
#elif defined(STM32F756xx)
#include "stm32f756xx.h"
#elif defined(STM32F746xx)
@@ -151,7 +149,7 @@
#elif defined(STM32F777xx)
#include "stm32f777xx.h"
#elif defined(STM32F779xx)
- #include "stm32f779xx.h"
+ #include "stm32f779xx.h"
#else
#error "Please select first the target STM32F7xx device used in your application (in stm32f7xx.h file)"
#endif
@@ -162,30 +160,30 @@
/** @addtogroup Exported_types
* @{
- */
-typedef enum
+ */
+typedef enum
{
- RESET = 0,
+ RESET = 0U,
SET = !RESET
} FlagStatus, ITStatus;
-typedef enum
+typedef enum
{
- DISABLE = 0,
+ DISABLE = 0U,
ENABLE = !DISABLE
} FunctionalState;
#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
-typedef enum
+typedef enum
{
- ERROR = 0,
+ ERROR = 0U,
SUCCESS = !ERROR
} ErrorStatus;
/**
* @}
*/
-
+
/** @addtogroup Exported_macro
* @{
*/
@@ -203,14 +201,14 @@
#define MODIFY_REG(REG, CLEARMASK, SETMASK) WRITE_REG((REG), (((READ_REG(REG)) & (~(CLEARMASK))) | (SETMASK)))
-#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
+#define POSITION_VAL(VAL) (__CLZ(__RBIT(VAL)))
/**
* @}
*/
#ifdef USE_HAL_DRIVER
- #include "stm32f7xx_hal.h"
+ #include "stm32f7xx_hal.h"
#endif /* USE_HAL_DRIVER */
#ifdef __cplusplus
@@ -223,7 +221,7 @@
* @}
*/
- /**
+/**
* @}
*/
--- a/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/device/system_stm32f7xx.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/TARGET_STM32F769xI/device/system_stm32f7xx.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file system_stm32f7xx.h * @author MCD Application Team - * @version V1.2.0 - * @date 30-December-2016 * @brief CMSIS Cortex-M7 Device System Source File for STM32F7xx devices. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/Release_Notes_stm32f7xx_hal.html Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/Release_Notes_stm32f7xx_hal.html Tue Mar 20 16:56:18 2018 +0000
@@ -670,12 +670,66 @@
</tr>
</tbody>
</table>
-<p class="MsoNormal"><span style="font-family: "Arial","sans-serif"; display: none;"><o:p> </o:p></span></p>
+<p class="MsoNormal"><span style="font-family: "Arial","sans-serif"; display: none;"><o:p> </o:p></span><span lang="fr"><font face="Arial">The hardware
+abstraction layer (HAL) provides low level drivers and the hardware
+interfacing methods to interact with upper layer (application,
+libraries and stacks). It includes a complete set of ready-to-use
+APIs, that are feature-oriented instead of IP-Oriented to simplify user
+application development.</font> </span></p>
<table class="MsoNormalTable" style="width: 675pt;" border="0" cellpadding="0" width="900">
<tbody>
<tr style="">
<td style="padding: 0in;" valign="top">
-<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">Update History</span></h2><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.2.2 / 14-April-2017</span></h3>
+<h2 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial;"><a name="History"></a><span style="font-size: 12pt; color: white;">Update History</span></h2><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 241px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.2.5 / 02-February-2018</span></h3>
+<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes</span></u></b></p><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">General updates to fix known defects and enhancements implementation</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add new macro to get variable aligned on 32-bytes, required for cache maintenance purpose</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update UNUSED() macro implementation to avoid GCC warning</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">The warning is detected when the UNUSED() macro is called from C++ file</span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL SAI </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL_SAI_DMAStop() and HAL_SAI_Abort() process to fix the lock/unlock audio issue </span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL PWR </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update
+HAL_PWR_EnterSLEEPMode() and HAL_PWR_EnterSTOPMode() APIs to ensure
+that all instructions finished before entering STOP mode. </span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL HCD </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add new callback to be used to handle usb device connection/disconnection</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_HCD_PortEnabled_Callback()</span></li></ul><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_HCD_PortDisabled_Callback()</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update to prevent reactivate host interrrupt channel<br></span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 241px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.2.4 / 22-December-2017</span></h3>
+<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes</span></u></b></p><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">General updates to fix known defects and enhancements implementation</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">The following changes done on the HAL drivers require an update on the application code based on older HAL versions</span></span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black; font-weight: bold;"><span style="font-size: 10pt; font-family: Verdana;">Rework of HAL CAN driver (compatibility break) </span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana;">A
+new HAL CAN driver has been redesigned with new APIs, to bypass
+limitations on CAN Tx/Rx FIFO management present with previous HAL CAN
+driver version.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana;">The
+new HAL CAN driver is the recommended version. It is located as usual
+in Drivers/STM32F7xx_HAL_Driver/Src and
+Drivers/STM32f7xx_HAL_Driver/Inc folders. It can be enabled through
+switch HAL_CAN_MODULE_ENABLED in stm32f7xx_hal_conf.h</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana;">The
+legacy HAL CAN driver is also present in the release in
+Drivers/STM32F7xx_HAL_Driver/Src/Legacy and
+Drivers/STM32F7xx_HAL_Driver/Inc/Legacy folders for software
+compatibility reasons. Its usage is not recommended as deprecated. It
+can however be enabled through switch HAL_CAN_LEGACY_MODULE_ENABLED in
+stm32f7xx_hal_conf.h</span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL driver to allow user to change systick period to 1ms , 10 ms or 100 ms :</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add the following API's : </span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_GetTickPrio() : Returns a tick priority.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_SetTickFreq() : Sets new tick </span><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">frequency.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">HAL_GetTickFreq() : Returns tick frequency.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Add HAL_TickFreqTypeDef enumeration for the different Tick Frequencies : 10 Hz , 100 Hz and 1KHz (default).</span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL CAN </span>update</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Fields of CAN_InitTypeDef structure are reworked:</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana;">SJW
+to SyncJumpWidth, BS1 to TimeSeg1, BS2 to TimeSeg2, TTCM to
+TimeTriggeredMode, ABOM to AutoBusOff, AWUM to AutoWakeUp, NART to
+AutoRetransmission (inversed), RFLM to ReceiveFifoLocked and TXFP to
+TransmitFifoPriority</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_CAN_Init() is split into both HAL_CAN_Init() and HAL_CAN_Start() API's</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_CAN_Transmit()
+is replaced by HAL_CAN_AddTxMessage() to place Tx Request, then
+HAL_CAN_GetTxMailboxesFreeLevel() for polling until completion.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_CAN_Transmit_IT()
+is replaced by HAL_CAN_ActivateNotification() to enable transmit IT, then
+HAL_CAN_</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">AddTxMessage</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">() for place Tx request.</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US"></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_CAN_Receive()
+is replaced by HAL_CAN_GetRxFifoFillLevel() for polling until
+reception, then HAL_CAN_GetRxMessage() <br>to get Rx message.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US"></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_CAN_Receive_IT()
+is replaced by HAL_CAN_</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">ActivateNotification</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">() </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">to enable receive IT, then
+HAL_CAN</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">_GetRxMessage()<br></span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US"> in the receivecallback to get Rx message</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_CAN_Slepp() is renamed as HAL_CAN_RequestSleep()</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_CAN_TxCpltCallback() is split into HAL_CAN_TxMailbox0CompleteCallback(), </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_CAN_TxMailbox1CompleteCallback() and </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_CAN_TxMailbox2CompleteCallback().</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_CAN_RxCpltCallback is split into HAL_CAN_RxFifo0MsgPendingCallback() and </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">HAL_CAN_RxFifo1MsgPendingCallback().</span></li></ul><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: 'Times New Roman',serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">More complete "How to use the new driver" is detailed in the driver header section itself.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL RCC </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">update</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;" lang="EN-US"><o:p></o:p></span></li><ul style="margin-top: 0cm;" type="square"><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add new LL macro </span><span style="font-size: 12pt; font-family: "Times New Roman",serif;" lang="EN-US"><o:p></o:p></span></li><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">LL_RCC_PLL_SetMainSource()
+ allowing to configure PLL clock source</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;" lang="EN-US"><o:p></o:p></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add new HAL macros</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;" lang="EN-US"><o:p></o:p></span></li><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">__HAL_RCC_GET_RTC_SOURCE()
+ allowing to get the RTC clock source<o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">__HAL_RCC_GET_RTC_HSE_PRESCALER()
+ allowing to get the HSE clock divider for RTC peripheral<o:p></o:p></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Ensure reset of CIR and CSR
+ registers when issuing HAL_RCC_DeInit()/LL_RCC_DeInit functions<o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update HAL_RCC_GetSysClockFreq()
+ to avoid risk of rounding error which may leads to a wrong returned
+ value.</span><span style="font-size: 7pt; font-family: "Times New Roman",serif;" lang="EN-US"> </span><span style="font-size: 12pt; font-family: "Times New Roman",serif;" lang="EN-US"><o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update HAL_RCC_DeInit()
+ and LL_RCC_DeInit() APIs to</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;" lang="EN-US"><o:p></o:p></span></li><ul style="margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Be able to return HAL/LL
+ status</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;" lang="EN-US"><o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add checks for HSI, PLL and
+ PLLI2S ready before modifying RCC CFGR registers</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;" lang="EN-US"><o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Clear all interrupt flags</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;" lang="EN-US"><o:p></o:p></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Initialize systick interrupt
+ period</span></li></ul></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL DMA </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span lang="fr"><font face="Courier New" size="2"></font></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add clean of callbacks in HAL_DMA_DeInit() API</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Fix wrong DMA_FLAG_FEIFO_4 and DMA_FLAGDMAEIFO_4 defines values </span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL I2C </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">update</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">Update Interface APIs headers to remove confusing message about device address</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;" lang="EN-US"><o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">Update </span><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">I2C_WaitOnRXNEFlagUntilTimeout() to resolve a race condition between STOPF and RXNE Flags</span><span style="font-size: 12pt; font-family: "Times New Roman",serif;" lang="EN-US"><o:p></o:p></span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: Verdana,sans-serif;" lang="EN-US">Update I2C_TransferConfig() to fix wrong bit management</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">LL USART<span> </span></span>update</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add assert macros to check USART BaudRate register</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL ETH </span></b><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Do{..} While(0) </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">insured </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">in </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">multi statement macros</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"> :</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">__HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">__HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER()</span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"> <br></span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US"></span></li></ul></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">HAL FLASH<span> </span></span>update</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_FLASH_Unlock() update to return state error when the FLASH is already unlocked</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">HAL GPIO<span> </span></span>update</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Add missing define of GPIO_PIN_2 in GPIOK_PIN_AVAILABLE list</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">HAL PCD<span> </span></span>update</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Do{..} While(0) insured in multi statement macros</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">LL UTILS<span> </span></span>update</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">stm32f7xx_</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">ll_utils.h : Update LL_GetPackageType command to return uint32_t instead of uint16_t</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">HAL TIM<span> </span></span>update</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">stm32f7xx_hal_tim_ex.c : Update HAL_TIMEx_ConfigBreakDeadTime API to avoid to block timer behavior when <br>remains in the state HAL_TIM_STATE_BUSY.</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US"> </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">stm32f7xx_hal_tim.h : </span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Fix __HAL_TIM_SET_PRESCALER() macro</span></li><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;" lang="EN-US">Fix typos in some exported macros description </span></li></ul></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">LL FMC<span> </span></span>update</span></li><ul style="margin-bottom: 0in;"><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">HAL_SDRAM_SendCommand() API: </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Remove the timeout</span><span style="font-family: Verdana,sans-serif; font-size: 10pt;"> check</span></li></ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;"><span style="font-weight: bold;">HAL NAND<span> </span></span>update</span></li><ul><li class="MsoNormal" style="margin: 4.5pt 0in; font-size: 12pt; font-family: "Times New Roman",serif; color: black;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Fix wrong check for NAND status</span></li></ul></ul>
+<h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.2.3 / 25-August-2017</span></h3>
+<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
+Changes</span></u></b></p><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">General updates
+to fix known defects and enhancements implementation</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Remove Date and Version from header files</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">Update HAL drivers to refer to the new CMSIS bit position defines instead of usage the </span><span style="font-family: Verdana,sans-serif; font-size: 10pt;">POSITION_VAL() macro</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL CAN </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add missing unlock in HAL_CAN_Receive_IT() process</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL DCMI </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL DCMI driver clean-up: remove non referenced callback APIs: HAL_DCMI_VsyncCallback() and HAL_DCMI_HsyncCallback()</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL DFSDM </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Fix cast issue on APIs that return signed integer value (uint32_t) </span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL DMA </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL DMA driver clean-up: remove non referenced callback APIs: HAL_DMA_CleanCallbacks()</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL FLASH </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">FLASH_Program_DoubleWord() API: Replace 64-bit accesses with 2 double words operations</span></li></ul></ul><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL Generic </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update assert_param() macro definition to be in line with stm32_ll_utils.c driver</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL GPIO </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">GPIOK_PIN_AVAILABLE() assert macro update to allow possibility to configure GPIO_PIN_2</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL LTDC </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Rename HAL_LTDC_LineEvenCallback() API to </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">HAL_LTDC_LineEven<span style="font-weight: bold;">t</span>Callback()</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL PCD </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update HAL_PCD_IRQHandler() API to fix transfer issues when </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">USB HS is used with DMA enabled</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL RCC </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update HAL_RCC_GetOscConfig() API to:</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">set PLLR in the RCC_OscInitStruct</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">check on null pointer<br></span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update HAL_RCC_ClockConfig() API to:</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">check on null pointer</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">optimize code size by updating the handling method of the SWS bits</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">update
+to use __HAL_FLASH_GET_LATENCY() flash macro instead of using
+direct register access to LATENCY bits in FLASH ACR register</span><span lang="fr">. </span></li></ul></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL SAI </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update HAL_SAI_DMAStop() API to flush fifo after disabling SAI</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL TIM </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;">Update HAL_TIMEx_ConfigBreakInput() API to support BKINP/BKIN2P polarity bits.<br></span></li></ul></ul><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">LL DMA </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update
+SET_BIT() access to LIFCR and HIFCR registers by WRITE_REG() to avoid
+read access that is not allowed when clearing DMA flags</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">LL I2C </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update LL_I2C_Init() API to avoid enabling own address1 when OwnAddress1 parameter value in the I2C_InitStruct is equal to 0.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">LL TIM </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update LL_TIM_EnableUpdateEvent() API to clear UDIS bit in CR1 register instead of setting it.</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update LL_TIM_DisableUpdateEvent() API </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">to set UDIS bit in CR1 register instead of clearing it.</span></li></ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">LL USB </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Update USB_EP0StartXfer() API to fix transfer issues when </span><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">USB HS is used with DMA enabled</span></li></ul></ul><h3 style="background: rgb(51, 102, 255) none repeat scroll 0% 50%; -moz-background-clip: initial; -moz-background-origin: initial; -moz-background-inline-policy: initial; margin-right: 500pt; width: 200px;"><span style="font-size: 10pt; font-family: Arial; color: white;">V1.2.2 / 14-April-2017</span></h3>
<p class="MsoNormal" style="margin: 4.5pt 0cm 4.5pt 18pt;"><b style=""><u><span style="font-size: 10pt; font-family: Verdana; color: black;">Main
Changes</span></u></b></p><ul style="margin-bottom: 0in; color: rgb(0, 0, 0); font-family: 'Times New Roman'; font-size: medium; font-style: normal; font-variant: normal; font-weight: normal; letter-spacing: normal; line-height: normal; text-align: start; text-indent: 0px; text-transform: none; white-space: normal; word-spacing: 0px; margin-top: 0cm;" type="square"><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: Verdana,sans-serif; font-size: 10pt;">General updates
to fix known defects and enhancements implementation</span></li><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-family: 'Verdana','sans-serif'; font-size: 10pt;"><span style="font-weight: bold;">HAL CAN </span>update</span></li><ul><li class="MsoNormal" style="color: black; margin-top: 4.5pt; margin-bottom: 4.5pt;"><span style="font-size: 10pt; font-family: "Verdana",sans-serif;" lang="EN-US">Add
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32_hal_legacy.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32_hal_legacy.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,9 +2,7 @@
******************************************************************************
* @file stm32_hal_legacy.h
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
- * @brief This file contains aliases definition for the STM32Cube HAL constants
+ * @brief This file contains aliases definition for the STM32Cube HAL constants
* macros and functions maintained for legacy purpose.
******************************************************************************
* @attention
@@ -60,7 +58,7 @@
/**
* @}
*/
-
+
/** @defgroup HAL_ADC_Aliased_Defines HAL ADC Aliased Defines maintained for legacy purpose
* @{
*/
@@ -92,10 +90,10 @@
#define ADC_CLOCKPRESCALER_PCLK_DIV4 ADC_CLOCK_SYNC_PCLK_DIV4
#define ADC_CLOCKPRESCALER_PCLK_DIV6 ADC_CLOCK_SYNC_PCLK_DIV6
#define ADC_CLOCKPRESCALER_PCLK_DIV8 ADC_CLOCK_SYNC_PCLK_DIV8
-#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
-#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
-#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
-#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
+#define ADC_EXTERNALTRIG0_T6_TRGO ADC_EXTERNALTRIGCONV_T6_TRGO
+#define ADC_EXTERNALTRIG1_T21_CC2 ADC_EXTERNALTRIGCONV_T21_CC2
+#define ADC_EXTERNALTRIG2_T2_TRGO ADC_EXTERNALTRIGCONV_T2_TRGO
+#define ADC_EXTERNALTRIG3_T2_CC4 ADC_EXTERNALTRIGCONV_T2_CC4
#define ADC_EXTERNALTRIG4_T22_TRGO ADC_EXTERNALTRIGCONV_T22_TRGO
#define ADC_EXTERNALTRIG7_EXT_IT11 ADC_EXTERNALTRIGCONV_EXT_IT11
#define ADC_CLOCK_ASYNC ADC_CLOCK_ASYNC_DIV1
@@ -111,21 +109,21 @@
#define HAL_ADC_STATE_EOC_INJ HAL_ADC_STATE_INJ_EOC
#define HAL_ADC_STATE_ERROR HAL_ADC_STATE_ERROR_INTERNAL
#define HAL_ADC_STATE_BUSY HAL_ADC_STATE_BUSY_INTERNAL
-#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1
+#define HAL_ADC_STATE_AWD HAL_ADC_STATE_AWD1
/**
* @}
*/
-
+
/** @defgroup HAL_CEC_Aliased_Defines HAL CEC Aliased Defines maintained for legacy purpose
* @{
- */
-
-#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
+ */
+
+#define __HAL_CEC_GET_IT __HAL_CEC_GET_FLAG
/**
* @}
- */
-
+ */
+
/** @defgroup HAL_COMP_Aliased_Defines HAL COMP Aliased Defines maintained for legacy purpose
* @{
*/
@@ -138,7 +136,9 @@
#define COMP_EXTI_LINE_COMP5_EVENT COMP_EXTI_LINE_COMP5
#define COMP_EXTI_LINE_COMP6_EVENT COMP_EXTI_LINE_COMP6
#define COMP_EXTI_LINE_COMP7_EVENT COMP_EXTI_LINE_COMP7
-#define COMP_LPTIMCONNECTION_ENABLED COMP_LPTIMCONNECTION_IN1_ENABLED /*!< COMPX output is connected to LPTIM input 1 */
+#if defined(STM32L0)
+#define COMP_LPTIMCONNECTION_ENABLED ((uint32_t)0x00000003U) /*!< COMPX output generic naming: connected to LPTIM input 1 for COMP1, LPTIM input 2 for COMP2 */
+#endif
#define COMP_OUTPUT_COMP6TIM2OCREFCLR COMP_OUTPUT_COMP6_TIM2OCREFCLR
#if defined(STM32F373xC) || defined(STM32F378xx)
#define COMP_OUTPUT_TIM3IC1 COMP_OUTPUT_COMP1_TIM3IC1
@@ -154,7 +154,7 @@
#define COMP_NONINVERTINGINPUT_IO4 COMP_INPUT_PLUS_IO4
#define COMP_NONINVERTINGINPUT_IO5 COMP_INPUT_PLUS_IO5
#define COMP_NONINVERTINGINPUT_IO6 COMP_INPUT_PLUS_IO6
-
+
#define COMP_INVERTINGINPUT_1_4VREFINT COMP_INPUT_MINUS_1_4VREFINT
#define COMP_INVERTINGINPUT_1_2VREFINT COMP_INPUT_MINUS_1_2VREFINT
#define COMP_INVERTINGINPUT_3_4VREFINT COMP_INPUT_MINUS_3_4VREFINT
@@ -226,7 +226,7 @@
/** @defgroup HAL_CRC_Aliased_Defines HAL CRC Aliased Defines maintained for legacy purpose
* @{
*/
-
+
#define CRC_OUTPUTDATA_INVERSION_DISABLED CRC_OUTPUTDATA_INVERSION_DISABLE
#define CRC_OUTPUTDATA_INVERSION_ENABLED CRC_OUTPUTDATA_INVERSION_ENABLE
@@ -255,28 +255,27 @@
/** @defgroup HAL_DMA_Aliased_Defines HAL DMA Aliased Defines maintained for legacy purpose
* @{
*/
-#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2
-#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4
-#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5
-#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4
-#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2
+#define HAL_REMAPDMA_ADC_DMA_CH2 DMA_REMAP_ADC_DMA_CH2
+#define HAL_REMAPDMA_USART1_TX_DMA_CH4 DMA_REMAP_USART1_TX_DMA_CH4
+#define HAL_REMAPDMA_USART1_RX_DMA_CH5 DMA_REMAP_USART1_RX_DMA_CH5
+#define HAL_REMAPDMA_TIM16_DMA_CH4 DMA_REMAP_TIM16_DMA_CH4
+#define HAL_REMAPDMA_TIM17_DMA_CH2 DMA_REMAP_TIM17_DMA_CH2
#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
#define HAL_REMAPDMA_TIM16_DMA_CH6 DMA_REMAP_TIM16_DMA_CH6
-#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
-#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
-#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
-#define HAL_REMAPDMA_USART3_DMA_CH32 DMA_REMAP_USART3_DMA_CH32
-#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
-#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
-#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
-#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6
-
-#define IS_HAL_REMAPDMA IS_DMA_REMAP
+#define HAL_REMAPDMA_TIM17_DMA_CH7 DMA_REMAP_TIM17_DMA_CH7
+#define HAL_REMAPDMA_SPI2_DMA_CH67 DMA_REMAP_SPI2_DMA_CH67
+#define HAL_REMAPDMA_USART2_DMA_CH67 DMA_REMAP_USART2_DMA_CH67
+#define HAL_REMAPDMA_I2C1_DMA_CH76 DMA_REMAP_I2C1_DMA_CH76
+#define HAL_REMAPDMA_TIM1_DMA_CH6 DMA_REMAP_TIM1_DMA_CH6
+#define HAL_REMAPDMA_TIM2_DMA_CH7 DMA_REMAP_TIM2_DMA_CH7
+#define HAL_REMAPDMA_TIM3_DMA_CH6 DMA_REMAP_TIM3_DMA_CH6
+
+#define IS_HAL_REMAPDMA IS_DMA_REMAP
#define __HAL_REMAPDMA_CHANNEL_ENABLE __HAL_DMA_REMAP_CHANNEL_ENABLE
#define __HAL_REMAPDMA_CHANNEL_DISABLE __HAL_DMA_REMAP_CHANNEL_DISABLE
-
-
-
+
+
+
/**
* @}
*/
@@ -284,7 +283,7 @@
/** @defgroup HAL_FLASH_Aliased_Defines HAL FLASH Aliased Defines maintained for legacy purpose
* @{
*/
-
+
#define TYPEPROGRAM_BYTE FLASH_TYPEPROGRAM_BYTE
#define TYPEPROGRAM_HALFWORD FLASH_TYPEPROGRAM_HALFWORD
#define TYPEPROGRAM_WORD FLASH_TYPEPROGRAM_WORD
@@ -360,11 +359,11 @@
/**
* @}
*/
-
+
/** @defgroup HAL_SYSCFG_Aliased_Defines HAL SYSCFG Aliased Defines maintained for legacy purpose
* @{
*/
-
+
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA9 I2C_FASTMODEPLUS_PA9
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PA10 I2C_FASTMODEPLUS_PA10
#define HAL_SYSCFG_FASTMODEPLUS_I2C_PB6 I2C_FASTMODEPLUS_PB6
@@ -377,12 +376,12 @@
/**
* @}
*/
-
+
/** @defgroup LL_FMC_Aliased_Defines LL FMC Aliased Defines maintained for compatibility purpose
* @{
*/
-#if defined(STM32L4) || defined(STM32F7)
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32H7) || defined(STM32G4)
#define FMC_NAND_PCC_WAIT_FEATURE_DISABLE FMC_NAND_WAIT_FEATURE_DISABLE
#define FMC_NAND_PCC_WAIT_FEATURE_ENABLE FMC_NAND_WAIT_FEATURE_ENABLE
#define FMC_NAND_PCC_MEM_BUS_WIDTH_8 FMC_NAND_MEM_BUS_WIDTH_8
@@ -400,7 +399,7 @@
/** @defgroup LL_FSMC_Aliased_Defines LL FSMC Aliased Defines maintained for legacy purpose
* @{
*/
-
+
#define FSMC_NORSRAM_TYPEDEF FSMC_NORSRAM_TypeDef
#define FSMC_NORSRAM_EXTENDED_TYPEDEF FSMC_NORSRAM_EXTENDED_TypeDef
/**
@@ -432,18 +431,18 @@
#define GPIO_AF1_LPTIM GPIO_AF1_LPTIM1
#define GPIO_AF2_LPTIM GPIO_AF2_LPTIM1
-#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7)
-#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
-#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
-#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
-#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
-#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 */
-
-#if defined(STM32L1)
- #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
- #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
- #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
- #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
+#if defined(STM32L0) || defined(STM32L4) || defined(STM32F4) || defined(STM32F2) || defined(STM32F7) || defined(STM32G4)
+#define GPIO_SPEED_LOW GPIO_SPEED_FREQ_LOW
+#define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_MEDIUM
+#define GPIO_SPEED_FAST GPIO_SPEED_FREQ_HIGH
+#define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
+#endif /* STM32L0 || STM32L4 || STM32F4 || STM32F2 || STM32F7 || STM32G4 */
+
+#if defined(STM32L1)
+ #define GPIO_SPEED_VERY_LOW GPIO_SPEED_FREQ_LOW
+ #define GPIO_SPEED_LOW GPIO_SPEED_FREQ_MEDIUM
+ #define GPIO_SPEED_MEDIUM GPIO_SPEED_FREQ_HIGH
+ #define GPIO_SPEED_HIGH GPIO_SPEED_FREQ_VERY_HIGH
#endif /* STM32L1 */
#if defined(STM32F0) || defined(STM32F3) || defined(STM32F1)
@@ -457,6 +456,78 @@
* @}
*/
+/** @defgroup HAL_JPEG_Aliased_Macros HAL JPEG Aliased Macros maintained for legacy purpose
+ * @{
+ */
+
+#if defined(STM32H7)
+ #define __HAL_RCC_JPEG_CLK_ENABLE __HAL_RCC_JPGDECEN_CLK_ENABLE
+ #define __HAL_RCC_JPEG_CLK_DISABLE __HAL_RCC_JPGDECEN_CLK_DISABLE
+ #define __HAL_RCC_JPEG_FORCE_RESET __HAL_RCC_JPGDECRST_FORCE_RESET
+ #define __HAL_RCC_JPEG_RELEASE_RESET __HAL_RCC_JPGDECRST_RELEASE_RESET
+ #define __HAL_RCC_JPEG_CLK_SLEEP_ENABLE __HAL_RCC_JPGDEC_CLK_SLEEP_ENABLE
+ #define __HAL_RCC_JPEG_CLK_SLEEP_DISABLE __HAL_RCC_JPGDEC_CLK_SLEEP_DISABLE
+
+ #define DMA_REQUEST_DAC1 DMA_REQUEST_DAC1_CH1
+ #define DMA_REQUEST_DAC2 DMA_REQUEST_DAC1_CH2
+
+ #define BDMA_REQUEST_LP_UART1_RX BDMA_REQUEST_LPUART1_RX
+ #define BDMA_REQUEST_LP_UART1_TX BDMA_REQUEST_LPUART1_TX
+
+ #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH0_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
+ #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH1_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
+ #define HAL_DMAMUX1_REQUEST_GEN_DMAMUX1_CH2_EVT HAL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
+ #define HAL_DMAMUX1_REQUEST_GEN_LPTIM1_OUT HAL_DMAMUX1_REQ_GEN_LPTIM1_OUT
+ #define HAL_DMAMUX1_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX1_REQ_GEN_LPTIM2_OUT
+ #define HAL_DMAMUX1_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX1_REQ_GEN_LPTIM3_OUT
+ #define HAL_DMAMUX1_REQUEST_GEN_EXTI0 HAL_DMAMUX1_REQ_GEN_EXTI0
+ #define HAL_DMAMUX1_REQUEST_GEN_TIM12_TRGO HAL_DMAMUX1_REQ_GEN_TIM12_TRGO
+
+ #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH0_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
+ #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH1_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
+ #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH2_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
+ #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH3_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
+ #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH4_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
+ #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH5_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
+ #define HAL_DMAMUX2_REQUEST_GEN_DMAMUX2_CH6_EVT HAL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
+ #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
+ #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_WKUP HAL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
+ #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
+ #define HAL_DMAMUX2_REQUEST_GEN_LPTIM2_OUT HAL_DMAMUX2_REQ_GEN_LPTIM2_OUT
+ #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
+ #define HAL_DMAMUX2_REQUEST_GEN_LPTIM3_OUT HAL_DMAMUX2_REQ_GEN_LPTIM3_OUT
+ #define HAL_DMAMUX2_REQUEST_GEN_LPTIM4_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM4_WKUP
+ #define HAL_DMAMUX2_REQUEST_GEN_LPTIM5_WKUP HAL_DMAMUX2_REQ_GEN_LPTIM5_WKUP
+ #define HAL_DMAMUX2_REQUEST_GEN_I2C4_WKUP HAL_DMAMUX2_REQ_GEN_I2C4_WKUP
+ #define HAL_DMAMUX2_REQUEST_GEN_SPI6_WKUP HAL_DMAMUX2_REQ_GEN_SPI6_WKUP
+ #define HAL_DMAMUX2_REQUEST_GEN_COMP1_OUT HAL_DMAMUX2_REQ_GEN_COMP1_OUT
+ #define HAL_DMAMUX2_REQUEST_GEN_COMP2_OUT HAL_DMAMUX2_REQ_GEN_COMP2_OUT
+ #define HAL_DMAMUX2_REQUEST_GEN_RTC_WKUP HAL_DMAMUX2_REQ_GEN_RTC_WKUP
+ #define HAL_DMAMUX2_REQUEST_GEN_EXTI0 HAL_DMAMUX2_REQ_GEN_EXTI0
+ #define HAL_DMAMUX2_REQUEST_GEN_EXTI2 HAL_DMAMUX2_REQ_GEN_EXTI2
+ #define HAL_DMAMUX2_REQUEST_GEN_I2C4_IT_EVT HAL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
+ #define HAL_DMAMUX2_REQUEST_GEN_SPI6_IT HAL_DMAMUX2_REQ_GEN_SPI6_IT
+ #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_TX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
+ #define HAL_DMAMUX2_REQUEST_GEN_LPUART1_RX_IT HAL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
+ #define HAL_DMAMUX2_REQUEST_GEN_ADC3_IT HAL_DMAMUX2_REQ_GEN_ADC3_IT
+ #define HAL_DMAMUX2_REQUEST_GEN_ADC3_AWD1_OUT HAL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT
+ #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH0_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
+ #define HAL_DMAMUX2_REQUEST_GEN_BDMA_CH1_IT HAL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
+
+ #define HAL_DMAMUX_REQUEST_GEN_NO_EVENT HAL_DMAMUX_REQ_GEN_NO_EVENT
+ #define HAL_DMAMUX_REQUEST_GEN_RISING HAL_DMAMUX_REQ_GEN_RISING
+ #define HAL_DMAMUX_REQUEST_GEN_FALLING HAL_DMAMUX_REQ_GEN_FALLING
+ #define HAL_DMAMUX_REQUEST_GEN_RISING_FALLING HAL_DMAMUX_REQ_GEN_RISING_FALLING
+
+
+#endif /* STM32H7 */
+
+
+/**
+ * @}
+ */
+
+
/** @defgroup HAL_HRTIM_Aliased_Macros HAL HRTIM Aliased Macros maintained for legacy purpose
* @{
*/
@@ -469,7 +540,7 @@
#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDOUT2_DEEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDOUT2_DEEV7
#define HRTIM_TIMDELAYEDPROTECTION_DELAYEDBOTH_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_DELAYEDBOTH_EEV7
#define HRTIM_TIMDELAYEDPROTECTION_BALANCED_EEV79 HRTIM_TIMER_A_B_C_DELAYEDPROTECTION_BALANCED_EEV7
-
+
#define __HAL_HRTIM_SetCounter __HAL_HRTIM_SETCOUNTER
#define __HAL_HRTIM_GetCounter __HAL_HRTIM_GETCOUNTER
#define __HAL_HRTIM_SetPeriod __HAL_HRTIM_SETPERIOD
@@ -542,7 +613,7 @@
#define LPTIM_TRIGSAMPLETIME_DIRECTTRANSISTION LPTIM_TRIGSAMPLETIME_DIRECTTRANSITION
#define LPTIM_TRIGSAMPLETIME_2TRANSISTIONS LPTIM_TRIGSAMPLETIME_2TRANSITIONS
#define LPTIM_TRIGSAMPLETIME_4TRANSISTIONS LPTIM_TRIGSAMPLETIME_4TRANSITIONS
-#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS
+#define LPTIM_TRIGSAMPLETIME_8TRANSISTIONS LPTIM_TRIGSAMPLETIME_8TRANSITIONS
/* The following 3 definition have also been present in a temporary version of lptim.h */
/* They need to be renamed also to the right name, just in case */
@@ -572,7 +643,7 @@
/**
* @}
*/
-
+
/** @defgroup HAL_NOR_Aliased_Defines HAL NOR Aliased Defines maintained for legacy purpose
* @{
*/
@@ -596,11 +667,11 @@
#define OPAMP_NONINVERTINGINPUT_VP1 OPAMP_NONINVERTINGINPUT_IO1
#define OPAMP_NONINVERTINGINPUT_VP2 OPAMP_NONINVERTINGINPUT_IO2
#define OPAMP_NONINVERTINGINPUT_VP3 OPAMP_NONINVERTINGINPUT_IO3
-
+
#define OPAMP_SEC_NONINVERTINGINPUT_VP0 OPAMP_SEC_NONINVERTINGINPUT_IO0
#define OPAMP_SEC_NONINVERTINGINPUT_VP1 OPAMP_SEC_NONINVERTINGINPUT_IO1
#define OPAMP_SEC_NONINVERTINGINPUT_VP2 OPAMP_SEC_NONINVERTINGINPUT_IO2
-#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
+#define OPAMP_SEC_NONINVERTINGINPUT_VP3 OPAMP_SEC_NONINVERTINGINPUT_IO3
#define OPAMP_INVERTINGINPUT_VM0 OPAMP_INVERTINGINPUT_IO0
#define OPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
@@ -609,14 +680,14 @@
#define IOPAMP_INVERTINGINPUT_VM1 OPAMP_INVERTINGINPUT_IO1
#define OPAMP_SEC_INVERTINGINPUT_VM0 OPAMP_SEC_INVERTINGINPUT_IO0
-#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
+#define OPAMP_SEC_INVERTINGINPUT_VM1 OPAMP_SEC_INVERTINGINPUT_IO1
#define OPAMP_INVERTINGINPUT_VINM OPAMP_SEC_INVERTINGINPUT_IO1
-
-#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
-#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
-#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
-
+
+#define OPAMP_PGACONNECT_NO OPAMP_PGA_CONNECT_INVERTINGINPUT_NO
+#define OPAMP_PGACONNECT_VM0 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO0
+#define OPAMP_PGACONNECT_VM1 OPAMP_PGA_CONNECT_INVERTINGINPUT_IO1
+
/**
* @}
*/
@@ -625,7 +696,7 @@
* @{
*/
#define I2S_STANDARD_PHILLIPS I2S_STANDARD_PHILIPS
-#if defined(STM32F7)
+#if defined(STM32F7)
#define I2S_CLOCK_SYSCLK I2S_CLOCK_PLL
#endif
/**
@@ -637,18 +708,18 @@
*/
/* Compact Flash-ATA registers description */
-#define CF_DATA ATA_DATA
-#define CF_SECTOR_COUNT ATA_SECTOR_COUNT
-#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
-#define CF_CYLINDER_LOW ATA_CYLINDER_LOW
-#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
-#define CF_CARD_HEAD ATA_CARD_HEAD
-#define CF_STATUS_CMD ATA_STATUS_CMD
+#define CF_DATA ATA_DATA
+#define CF_SECTOR_COUNT ATA_SECTOR_COUNT
+#define CF_SECTOR_NUMBER ATA_SECTOR_NUMBER
+#define CF_CYLINDER_LOW ATA_CYLINDER_LOW
+#define CF_CYLINDER_HIGH ATA_CYLINDER_HIGH
+#define CF_CARD_HEAD ATA_CARD_HEAD
+#define CF_STATUS_CMD ATA_STATUS_CMD
#define CF_STATUS_CMD_ALTERNATE ATA_STATUS_CMD_ALTERNATE
-#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
+#define CF_COMMON_DATA_AREA ATA_COMMON_DATA_AREA
/* Compact Flash-ATA commands */
-#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
+#define CF_READ_SECTOR_CMD ATA_READ_SECTOR_CMD
#define CF_WRITE_SECTOR_CMD ATA_WRITE_SECTOR_CMD
#define CF_ERASE_SECTOR_CMD ATA_ERASE_SECTOR_CMD
#define CF_IDENTIFY_CMD ATA_IDENTIFY_CMD
@@ -661,31 +732,27 @@
/**
* @}
*/
-
+
/** @defgroup HAL_RTC_Aliased_Defines HAL RTC Aliased Defines maintained for legacy purpose
* @{
*/
-
+
#define FORMAT_BIN RTC_FORMAT_BIN
#define FORMAT_BCD RTC_FORMAT_BCD
#define RTC_ALARMSUBSECONDMASK_None RTC_ALARMSUBSECONDMASK_NONE
-#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
#define RTC_TAMPERMASK_FLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
#define RTC_TAMPERMASK_FLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
-#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
-#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
+#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
+#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
#define RTC_TAMPERERASEBACKUP_ENABLED RTC_TAMPER_ERASE_BACKUP_ENABLE
-#define RTC_TAMPERERASEBACKUP_DISABLED RTC_TAMPER_ERASE_BACKUP_DISABLE
-#define RTC_MASKTAMPERFLAG_DISABLED RTC_TAMPERMASK_FLAG_DISABLE
-#define RTC_MASKTAMPERFLAG_ENABLED RTC_TAMPERMASK_FLAG_ENABLE
-#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
-#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
+#define RTC_TAMPER1_2_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
+#define RTC_TAMPER1_2_3_INTERRUPT RTC_ALL_TAMPER_INTERRUPT
#define RTC_TIMESTAMPPIN_PC13 RTC_TIMESTAMPPIN_DEFAULT
-#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
+#define RTC_TIMESTAMPPIN_PA0 RTC_TIMESTAMPPIN_POS1
#define RTC_TIMESTAMPPIN_PI8 RTC_TIMESTAMPPIN_POS1
#define RTC_TIMESTAMPPIN_PC1 RTC_TIMESTAMPPIN_POS2
@@ -693,15 +760,15 @@
#define RTC_OUTPUT_REMAP_PB14 RTC_OUTPUT_REMAP_POS1
#define RTC_OUTPUT_REMAP_PB2 RTC_OUTPUT_REMAP_POS1
-#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
-#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
+#define RTC_TAMPERPIN_PC13 RTC_TAMPERPIN_DEFAULT
+#define RTC_TAMPERPIN_PA0 RTC_TAMPERPIN_POS1
#define RTC_TAMPERPIN_PI8 RTC_TAMPERPIN_POS1
/**
* @}
*/
-
+
/** @defgroup HAL_SMARTCARD_Aliased_Defines HAL SMARTCARD Aliased Defines maintained for legacy purpose
* @{
*/
@@ -722,7 +789,7 @@
* @}
*/
-
+
/** @defgroup HAL_SMBUS_Aliased_Defines HAL SMBUS Aliased Defines maintained for legacy purpose
* @{
*/
@@ -740,7 +807,7 @@
/**
* @}
*/
-
+
/** @defgroup HAL_SPI_Aliased_Defines HAL SPI Aliased Defines maintained for legacy purpose
* @{
*/
@@ -756,13 +823,13 @@
/**
* @}
*/
-
+
/** @defgroup HAL_TIM_Aliased_Defines HAL TIM Aliased Defines maintained for legacy purpose
* @{
*/
#define CCER_CCxE_MASK TIM_CCER_CCxE_MASK
#define CCER_CCxNE_MASK TIM_CCER_CCxNE_MASK
-
+
#define TIM_DMABase_CR1 TIM_DMABASE_CR1
#define TIM_DMABase_CR2 TIM_DMABASE_CR2
#define TIM_DMABase_SMCR TIM_DMABASE_SMCR
@@ -863,7 +930,7 @@
* @}
*/
-
+
/** @defgroup HAL_USART_Aliased_Defines HAL USART Aliased Defines maintained for legacy purpose
* @{
*/
@@ -903,7 +970,7 @@
/**
* @}
*/
-
+
/** @defgroup HAL_ETH_Aliased_Defines HAL ETH Aliased Defines maintained for legacy purpose
* @{
*/
@@ -928,7 +995,7 @@
#define ETH_MMCRFCECR 0x00000194U
#define ETH_MMCRFAECR 0x00000198U
#define ETH_MMCRGUFCR 0x000001C4U
-
+
#define ETH_MAC_TXFIFO_FULL 0x02000000U /* Tx FIFO full */
#define ETH_MAC_TXFIFONOT_EMPTY 0x01000000U /* Tx FIFO not empty */
#define ETH_MAC_TXFIFO_WRITE_ACTIVE 0x00400000U /* Tx FIFO write active */
@@ -946,9 +1013,12 @@
#define ETH_MAC_RXFIFO_BELOW_THRESHOLD 0x00000100U /* Rx FIFO fill level: fill-level below flow-control de-activate threshold */
#define ETH_MAC_RXFIFO_ABOVE_THRESHOLD 0x00000200U /* Rx FIFO fill level: fill-level above flow-control activate threshold */
#define ETH_MAC_RXFIFO_FULL 0x00000300U /* Rx FIFO fill level: full */
+#if defined(STM32F1)
+#else
#define ETH_MAC_READCONTROLLER_IDLE 0x00000000U /* Rx FIFO read controller IDLE state */
#define ETH_MAC_READCONTROLLER_READING_DATA 0x00000020U /* Rx FIFO read controller Reading frame data */
#define ETH_MAC_READCONTROLLER_READING_STATUS 0x00000040U /* Rx FIFO read controller Reading frame status (or time-stamp) */
+#endif
#define ETH_MAC_READCONTROLLER_FLUSHING 0x00000060U /* Rx FIFO read controller Flushing the frame data and status */
#define ETH_MAC_RXFIFO_WRITE_ACTIVE 0x00000010U /* Rx FIFO write controller active */
#define ETH_MAC_SMALL_FIFO_NOTACTIVE 0x00000000U /* MAC small FIFO read / write controllers not active */
@@ -960,7 +1030,7 @@
/**
* @}
*/
-
+
/** @defgroup HAL_DCMI_Aliased_Defines HAL DCMI Aliased Defines maintained for legacy purpose
* @{
*/
@@ -975,39 +1045,39 @@
/**
* @}
- */
-
-#if defined(STM32L4xx) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\
+ */
+
+#if defined(STM32L4) || defined(STM32F7) || defined(STM32F427xx) || defined(STM32F437xx) ||\
defined(STM32F429xx) || defined(STM32F439xx) || defined(STM32F469xx) || defined(STM32F479xx)
/** @defgroup HAL_DMA2D_Aliased_Defines HAL DMA2D Aliased Defines maintained for legacy purpose
* @{
*/
#define DMA2D_ARGB8888 DMA2D_OUTPUT_ARGB8888
-#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888
-#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565
+#define DMA2D_RGB888 DMA2D_OUTPUT_RGB888
+#define DMA2D_RGB565 DMA2D_OUTPUT_RGB565
#define DMA2D_ARGB1555 DMA2D_OUTPUT_ARGB1555
#define DMA2D_ARGB4444 DMA2D_OUTPUT_ARGB4444
#define CM_ARGB8888 DMA2D_INPUT_ARGB8888
-#define CM_RGB888 DMA2D_INPUT_RGB888
-#define CM_RGB565 DMA2D_INPUT_RGB565
+#define CM_RGB888 DMA2D_INPUT_RGB888
+#define CM_RGB565 DMA2D_INPUT_RGB565
#define CM_ARGB1555 DMA2D_INPUT_ARGB1555
#define CM_ARGB4444 DMA2D_INPUT_ARGB4444
-#define CM_L8 DMA2D_INPUT_L8
-#define CM_AL44 DMA2D_INPUT_AL44
-#define CM_AL88 DMA2D_INPUT_AL88
-#define CM_L4 DMA2D_INPUT_L4
-#define CM_A8 DMA2D_INPUT_A8
-#define CM_A4 DMA2D_INPUT_A4
+#define CM_L8 DMA2D_INPUT_L8
+#define CM_AL44 DMA2D_INPUT_AL44
+#define CM_AL88 DMA2D_INPUT_AL88
+#define CM_L4 DMA2D_INPUT_L4
+#define CM_A8 DMA2D_INPUT_A8
+#define CM_A4 DMA2D_INPUT_A4
/**
* @}
- */
-#endif /* STM32L4xx || STM32F7*/
+ */
+#endif /* STM32L4 || STM32F7*/
/** @defgroup HAL_PPP_Aliased_Defines HAL PPP Aliased Defines maintained for legacy purpose
* @{
*/
-
+
/**
* @}
*/
@@ -1020,11 +1090,11 @@
#define HAL_CRYP_ComputationCpltCallback HAL_CRYPEx_ComputationCpltCallback
/**
* @}
- */
+ */
/** @defgroup HAL_HASH_Aliased_Functions HAL HASH Aliased Functions maintained for legacy purpose
* @{
- */
+ */
#define HAL_HASH_STATETypeDef HAL_HASH_StateTypeDef
#define HAL_HASHPhaseTypeDef HAL_HASH_PhaseTypeDef
#define HAL_HMAC_MD5_Finish HAL_HASH_MD5_Finish
@@ -1034,12 +1104,12 @@
/*HASH Algorithm Selection*/
-#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
+#define HASH_AlgoSelection_SHA1 HASH_ALGOSELECTION_SHA1
#define HASH_AlgoSelection_SHA224 HASH_ALGOSELECTION_SHA224
#define HASH_AlgoSelection_SHA256 HASH_ALGOSELECTION_SHA256
#define HASH_AlgoSelection_MD5 HASH_ALGOSELECTION_MD5
-#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
+#define HASH_AlgoMode_HASH HASH_ALGOMODE_HASH
#define HASH_AlgoMode_HMAC HASH_ALGOMODE_HMAC
#define HASH_HMACKeyType_ShortKey HASH_HMAC_KEYTYPE_SHORTKEY
@@ -1047,7 +1117,7 @@
/**
* @}
*/
-
+
/** @defgroup HAL_Aliased_Functions HAL Generic Aliased Functions maintained for legacy purpose
* @{
*/
@@ -1128,6 +1198,8 @@
#define CR_OFFSET_BB PWR_CR_OFFSET_BB
#define CSR_OFFSET_BB PWR_CSR_OFFSET_BB
+#define PMODE_BIT_NUMBER VOS_BIT_NUMBER
+#define CR_PMODE_BB CR_VOS_BB
#define DBP_BitNumber DBP_BIT_NUMBER
#define PVDE_BitNumber PVDE_BIT_NUMBER
@@ -1141,17 +1213,17 @@
#define BRE_BitNumber BRE_BIT_NUMBER
#define PWR_MODE_EVT PWR_PVD_MODE_NORMAL
-
+
/**
* @}
- */
-
+ */
+
/** @defgroup HAL_SMBUS_Aliased_Functions HAL SMBUS Aliased Functions maintained for legacy purpose
* @{
*/
#define HAL_SMBUS_Slave_Listen_IT HAL_SMBUS_EnableListen_IT
-#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
-#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
+#define HAL_SMBUS_SlaveAddrCallback HAL_SMBUS_AddrCallback
+#define HAL_SMBUS_SlaveListenCpltCallback HAL_SMBUS_ListenCpltCallback
/**
* @}
*/
@@ -1162,7 +1234,7 @@
#define HAL_SPI_FlushRxFifo HAL_SPIEx_FlushRxFifo
/**
* @}
- */
+ */
/** @defgroup HAL_TIM_Aliased_Functions HAL TIM Aliased Functions maintained for legacy purpose
* @{
@@ -1174,28 +1246,31 @@
/**
* @}
*/
-
+
/** @defgroup HAL_UART_Aliased_Functions HAL UART Aliased Functions maintained for legacy purpose
* @{
- */
+ */
#define HAL_UART_WakeupCallback HAL_UARTEx_WakeupCallback
/**
* @}
*/
-
+
/** @defgroup HAL_LTDC_Aliased_Functions HAL LTDC Aliased Functions maintained for legacy purpose
* @{
- */
+ */
#define HAL_LTDC_LineEvenCallback HAL_LTDC_LineEventCallback
+#define HAL_LTDC_Relaod HAL_LTDC_Reload
+#define HAL_LTDC_StructInitFromVideoConfig HAL_LTDCEx_StructInitFromVideoConfig
+#define HAL_LTDC_StructInitFromAdaptedCommandConfig HAL_LTDCEx_StructInitFromAdaptedCommandConfig
/**
* @}
- */
-
-
+ */
+
+
/** @defgroup HAL_PPP_Aliased_Functions HAL PPP Aliased Functions maintained for legacy purpose
* @{
*/
-
+
/**
* @}
*/
@@ -1210,8 +1285,8 @@
#define AES_FLAG_CCF CRYP_FLAG_CCF
/**
* @}
- */
-
+ */
+
/** @defgroup HAL_Aliased_Macros HAL Generic Aliased Macros maintained for legacy purpose
* @{
*/
@@ -1220,7 +1295,7 @@
#define __HAL_REMAPMEMORY_SYSTEMFLASH __HAL_SYSCFG_REMAPMEMORY_SYSTEMFLASH
#define __HAL_REMAPMEMORY_SRAM __HAL_SYSCFG_REMAPMEMORY_SRAM
#define __HAL_REMAPMEMORY_FMC __HAL_SYSCFG_REMAPMEMORY_FMC
-#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
+#define __HAL_REMAPMEMORY_FMC_SDRAM __HAL_SYSCFG_REMAPMEMORY_FMC_SDRAM
#define __HAL_REMAPMEMORY_FSMC __HAL_SYSCFG_REMAPMEMORY_FSMC
#define __HAL_REMAPMEMORY_QUADSPI __HAL_SYSCFG_REMAPMEMORY_QUADSPI
#define __HAL_FMC_BANK __HAL_SYSCFG_FMC_BANK
@@ -1228,6 +1303,7 @@
#define __HAL_CLEAR_FLAG __HAL_SYSCFG_CLEAR_FLAG
#define __HAL_VREFINT_OUT_ENABLE __HAL_SYSCFG_VREFINT_OUT_ENABLE
#define __HAL_VREFINT_OUT_DISABLE __HAL_SYSCFG_VREFINT_OUT_DISABLE
+#define __HAL_SYSCFG_SRAM2_WRP_ENABLE __HAL_SYSCFG_SRAM2_WRP_0_31_ENABLE
#define SYSCFG_FLAG_VREF_READY SYSCFG_FLAG_VREFINT_READY
#define SYSCFG_FLAG_RC48 RCC_FLAG_HSI48
@@ -1239,7 +1315,7 @@
* @}
*/
-
+
/** @defgroup HAL_ADC_Aliased_Macros HAL ADC Aliased Macros maintained for legacy purpose
* @{
*/
@@ -1309,7 +1385,6 @@
#define __HAL_ADC_CR1_SCANCONV ADC_CR1_SCANCONV
#define __HAL_ADC_CR2_EOCSelection ADC_CR2_EOCSelection
#define __HAL_ADC_CR2_DMAContReq ADC_CR2_DMAContReq
-#define __HAL_ADC_GET_RESOLUTION ADC_GET_RESOLUTION
#define __HAL_ADC_JSQR ADC_JSQR
#define __HAL_ADC_CHSELR_CHANNEL ADC_CHSELR_CHANNEL
@@ -1336,7 +1411,7 @@
/**
* @}
*/
-
+
/** @defgroup HAL_DBGMCU_Aliased_Macros HAL DBGMCU Aliased Macros maintained for legacy purpose
* @{
*/
@@ -1409,7 +1484,7 @@
#define COMP_START __HAL_COMP_ENABLE
#define COMP_STOP __HAL_COMP_DISABLE
#define COMP_LOCK __HAL_COMP_LOCK
-
+
#if defined(STM32F301x8) || defined(STM32F302x8) || defined(STM32F318xx) || defined(STM32F303x8) || defined(STM32F334x8) || defined(STM32F328xx)
#define __HAL_COMP_EXTI_RISING_IT_ENABLE(__EXTILINE__) (((__EXTILINE__) == COMP_EXTI_LINE_COMP2) ? __HAL_COMP_COMP2_EXTI_ENABLE_RISING_EDGE() : \
((__EXTILINE__) == COMP_EXTI_LINE_COMP4) ? __HAL_COMP_COMP4_EXTI_ENABLE_RISING_EDGE() : \
@@ -1596,7 +1671,7 @@
#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_WAVE_NONE) || \
((WAVE) == DAC_WAVE_NOISE)|| \
((WAVE) == DAC_WAVE_TRIANGLE))
-
+
/**
* @}
*/
@@ -1615,14 +1690,18 @@
/**
* @}
*/
-
+
/** @defgroup HAL_I2C_Aliased_Macros HAL I2C Aliased Macros maintained for legacy purpose
* @{
*/
-
+
#define __HAL_I2C_RESET_CR2 I2C_RESET_CR2
#define __HAL_I2C_GENERATE_START I2C_GENERATE_START
+#if defined(STM32F1)
+#define __HAL_I2C_FREQ_RANGE I2C_FREQRANGE
+#else
#define __HAL_I2C_FREQ_RANGE I2C_FREQ_RANGE
+#endif /* STM32F1 */
#define __HAL_I2C_RISE_TIME I2C_RISE_TIME
#define __HAL_I2C_SPEED_STANDARD I2C_SPEED_STANDARD
#define __HAL_I2C_SPEED_FAST I2C_SPEED_FAST
@@ -1638,11 +1717,11 @@
/**
* @}
*/
-
+
/** @defgroup HAL_I2S_Aliased_Macros HAL I2S Aliased Macros maintained for legacy purpose
* @{
*/
-
+
#define IS_I2S_INSTANCE IS_I2S_ALL_INSTANCE
#define IS_I2S_INSTANCE_EXT IS_I2S_ALL_INSTANCE_EXT
@@ -1653,7 +1732,7 @@
/** @defgroup HAL_IRDA_Aliased_Macros HAL IRDA Aliased Macros maintained for legacy purpose
* @{
*/
-
+
#define __IRDA_DISABLE __HAL_IRDA_DISABLE
#define __IRDA_ENABLE __HAL_IRDA_ENABLE
@@ -1662,7 +1741,7 @@
#define __IRDA_GETCLOCKSOURCE IRDA_GETCLOCKSOURCE
#define __IRDA_MASK_COMPUTATION IRDA_MASK_COMPUTATION
-#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
+#define IS_IRDA_ONEBIT_SAMPLE IS_IRDA_ONE_BIT_SAMPLE
/**
@@ -1691,8 +1770,8 @@
/**
* @}
*/
-
-
+
+
/** @defgroup HAL_OPAMP_Aliased_Macros HAL OPAMP Aliased Macros maintained for legacy purpose
* @{
*/
@@ -1757,7 +1836,7 @@
#if defined (STM32F4)
#define __HAL_PVD_EXTI_ENABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_ENABLE_IT()
#define __HAL_PVD_EXTI_DISABLE_IT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_DISABLE_IT()
-#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
+#define __HAL_PVD_EXTI_GET_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GET_FLAG()
#define __HAL_PVD_EXTI_CLEAR_FLAG(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_CLEAR_FLAG()
#define __HAL_PVD_EXTI_GENERATE_SWIT(PWR_EXTI_LINE_PVD) __HAL_PWR_PVD_EXTI_GENERATE_SWIT()
#else
@@ -1765,37 +1844,37 @@
#define __HAL_PVD_EXTI_DISABLE_IT __HAL_PWR_PVD_EXTI_DISABLE_IT
#define __HAL_PVD_EXTI_ENABLE_IT __HAL_PWR_PVD_EXTI_ENABLE_IT
#define __HAL_PVD_EXTI_GENERATE_SWIT __HAL_PWR_PVD_EXTI_GENERATE_SWIT
-#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
+#define __HAL_PVD_EXTI_GET_FLAG __HAL_PWR_PVD_EXTI_GET_FLAG
#endif /* STM32F4 */
-/**
+/**
* @}
- */
-
-
+ */
+
+
/** @defgroup HAL_RCC_Aliased HAL RCC Aliased maintained for legacy purpose
* @{
*/
-
+
#define RCC_StopWakeUpClock_MSI RCC_STOP_WAKEUPCLOCK_MSI
#define RCC_StopWakeUpClock_HSI RCC_STOP_WAKEUPCLOCK_HSI
#define HAL_RCC_CCSCallback HAL_RCC_CSSCallback
#define HAL_RC48_EnableBuffer_Cmd(cmd) (((cmd)==ENABLE) ? HAL_RCCEx_EnableHSI48_VREFINT() : HAL_RCCEx_DisableHSI48_VREFINT())
-#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
-#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
-#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
-#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
-#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
-#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
-#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
-#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
-#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
-#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
-#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
-#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
-#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
-#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
+#define __ADC_CLK_DISABLE __HAL_RCC_ADC_CLK_DISABLE
+#define __ADC_CLK_ENABLE __HAL_RCC_ADC_CLK_ENABLE
+#define __ADC_CLK_SLEEP_DISABLE __HAL_RCC_ADC_CLK_SLEEP_DISABLE
+#define __ADC_CLK_SLEEP_ENABLE __HAL_RCC_ADC_CLK_SLEEP_ENABLE
+#define __ADC_FORCE_RESET __HAL_RCC_ADC_FORCE_RESET
+#define __ADC_RELEASE_RESET __HAL_RCC_ADC_RELEASE_RESET
+#define __ADC1_CLK_DISABLE __HAL_RCC_ADC1_CLK_DISABLE
+#define __ADC1_CLK_ENABLE __HAL_RCC_ADC1_CLK_ENABLE
+#define __ADC1_FORCE_RESET __HAL_RCC_ADC1_FORCE_RESET
+#define __ADC1_RELEASE_RESET __HAL_RCC_ADC1_RELEASE_RESET
+#define __ADC1_CLK_SLEEP_ENABLE __HAL_RCC_ADC1_CLK_SLEEP_ENABLE
+#define __ADC1_CLK_SLEEP_DISABLE __HAL_RCC_ADC1_CLK_SLEEP_DISABLE
+#define __ADC2_CLK_DISABLE __HAL_RCC_ADC2_CLK_DISABLE
+#define __ADC2_CLK_ENABLE __HAL_RCC_ADC2_CLK_ENABLE
#define __ADC2_FORCE_RESET __HAL_RCC_ADC2_FORCE_RESET
#define __ADC2_RELEASE_RESET __HAL_RCC_ADC2_RELEASE_RESET
#define __ADC3_CLK_DISABLE __HAL_RCC_ADC3_CLK_DISABLE
@@ -1812,7 +1891,7 @@
#define __CRYP_CLK_SLEEP_DISABLE __HAL_RCC_CRYP_CLK_SLEEP_DISABLE
#define __CRYP_CLK_ENABLE __HAL_RCC_CRYP_CLK_ENABLE
#define __CRYP_CLK_DISABLE __HAL_RCC_CRYP_CLK_DISABLE
-#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
+#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
#define __CRYP_RELEASE_RESET __HAL_RCC_CRYP_RELEASE_RESET
#define __AFIO_CLK_DISABLE __HAL_RCC_AFIO_CLK_DISABLE
#define __AFIO_CLK_ENABLE __HAL_RCC_AFIO_CLK_ENABLE
@@ -2040,6 +2119,21 @@
#define __QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QSPI_CLK_SLEEP_ENABLE
#define __QSPI_FORCE_RESET __HAL_RCC_QSPI_FORCE_RESET
#define __QSPI_RELEASE_RESET __HAL_RCC_QSPI_RELEASE_RESET
+
+#if defined(STM32WB)
+#define __HAL_RCC_QSPI_CLK_DISABLE __HAL_RCC_QUADSPI_CLK_DISABLE
+#define __HAL_RCC_QSPI_CLK_ENABLE __HAL_RCC_QUADSPI_CLK_ENABLE
+#define __HAL_RCC_QSPI_CLK_SLEEP_DISABLE __HAL_RCC_QUADSPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_QSPI_CLK_SLEEP_ENABLE __HAL_RCC_QUADSPI_CLK_SLEEP_ENABLE
+#define __HAL_RCC_QSPI_FORCE_RESET __HAL_RCC_QUADSPI_FORCE_RESET
+#define __HAL_RCC_QSPI_RELEASE_RESET __HAL_RCC_QUADSPI_RELEASE_RESET
+#define __HAL_RCC_QSPI_IS_CLK_ENABLED __HAL_RCC_QUADSPI_IS_CLK_ENABLED
+#define __HAL_RCC_QSPI_IS_CLK_DISABLED __HAL_RCC_QUADSPI_IS_CLK_DISABLED
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_ENABLED
+#define __HAL_RCC_QSPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_QUADSPI_IS_CLK_SLEEP_DISABLED
+#define QSPI_IRQHandler QUADSPI_IRQHandler
+#endif /* __HAL_RCC_QUADSPI_CLK_ENABLE */
+
#define __RNG_CLK_DISABLE __HAL_RCC_RNG_CLK_DISABLE
#define __RNG_CLK_ENABLE __HAL_RCC_RNG_CLK_ENABLE
#define __RNG_CLK_SLEEP_DISABLE __HAL_RCC_RNG_CLK_SLEEP_DISABLE
@@ -2231,13 +2325,13 @@
#define __USART4_CLK_DISABLE __HAL_RCC_UART4_CLK_DISABLE
#define __USART4_CLK_ENABLE __HAL_RCC_UART4_CLK_ENABLE
#define __USART4_CLK_SLEEP_ENABLE __HAL_RCC_UART4_CLK_SLEEP_ENABLE
-#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
+#define __USART4_CLK_SLEEP_DISABLE __HAL_RCC_UART4_CLK_SLEEP_DISABLE
#define __USART4_FORCE_RESET __HAL_RCC_UART4_FORCE_RESET
#define __USART4_RELEASE_RESET __HAL_RCC_UART4_RELEASE_RESET
#define __USART5_CLK_DISABLE __HAL_RCC_UART5_CLK_DISABLE
#define __USART5_CLK_ENABLE __HAL_RCC_UART5_CLK_ENABLE
#define __USART5_CLK_SLEEP_ENABLE __HAL_RCC_UART5_CLK_SLEEP_ENABLE
-#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
+#define __USART5_CLK_SLEEP_DISABLE __HAL_RCC_UART5_CLK_SLEEP_DISABLE
#define __USART5_FORCE_RESET __HAL_RCC_UART5_FORCE_RESET
#define __USART5_RELEASE_RESET __HAL_RCC_UART5_RELEASE_RESET
#define __USART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
@@ -2290,111 +2384,111 @@
#define __USB_OTG_HS_CLK_DISABLE __HAL_RCC_USB_OTG_HS_CLK_DISABLE
#define __USB_OTG_HS_CLK_ENABLE __HAL_RCC_USB_OTG_HS_CLK_ENABLE
#define __USB_OTG_HS_ULPI_CLK_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE
-#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
+#define __USB_OTG_HS_ULPI_CLK_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE
#define __TIM9_CLK_SLEEP_ENABLE __HAL_RCC_TIM9_CLK_SLEEP_ENABLE
-#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
+#define __TIM9_CLK_SLEEP_DISABLE __HAL_RCC_TIM9_CLK_SLEEP_DISABLE
#define __TIM10_CLK_SLEEP_ENABLE __HAL_RCC_TIM10_CLK_SLEEP_ENABLE
-#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
+#define __TIM10_CLK_SLEEP_DISABLE __HAL_RCC_TIM10_CLK_SLEEP_DISABLE
#define __TIM11_CLK_SLEEP_ENABLE __HAL_RCC_TIM11_CLK_SLEEP_ENABLE
-#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
+#define __TIM11_CLK_SLEEP_DISABLE __HAL_RCC_TIM11_CLK_SLEEP_DISABLE
#define __ETHMACPTP_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_ENABLE
#define __ETHMACPTP_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACPTP_CLK_SLEEP_DISABLE
#define __ETHMACPTP_CLK_ENABLE __HAL_RCC_ETHMACPTP_CLK_ENABLE
-#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
+#define __ETHMACPTP_CLK_DISABLE __HAL_RCC_ETHMACPTP_CLK_DISABLE
#define __HASH_CLK_ENABLE __HAL_RCC_HASH_CLK_ENABLE
#define __HASH_FORCE_RESET __HAL_RCC_HASH_FORCE_RESET
#define __HASH_RELEASE_RESET __HAL_RCC_HASH_RELEASE_RESET
#define __HASH_CLK_SLEEP_ENABLE __HAL_RCC_HASH_CLK_SLEEP_ENABLE
#define __HASH_CLK_SLEEP_DISABLE __HAL_RCC_HASH_CLK_SLEEP_DISABLE
-#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
+#define __HASH_CLK_DISABLE __HAL_RCC_HASH_CLK_DISABLE
#define __SPI5_CLK_ENABLE __HAL_RCC_SPI5_CLK_ENABLE
#define __SPI5_CLK_DISABLE __HAL_RCC_SPI5_CLK_DISABLE
#define __SPI5_FORCE_RESET __HAL_RCC_SPI5_FORCE_RESET
#define __SPI5_RELEASE_RESET __HAL_RCC_SPI5_RELEASE_RESET
#define __SPI5_CLK_SLEEP_ENABLE __HAL_RCC_SPI5_CLK_SLEEP_ENABLE
-#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
+#define __SPI5_CLK_SLEEP_DISABLE __HAL_RCC_SPI5_CLK_SLEEP_DISABLE
#define __SPI6_CLK_ENABLE __HAL_RCC_SPI6_CLK_ENABLE
#define __SPI6_CLK_DISABLE __HAL_RCC_SPI6_CLK_DISABLE
#define __SPI6_FORCE_RESET __HAL_RCC_SPI6_FORCE_RESET
#define __SPI6_RELEASE_RESET __HAL_RCC_SPI6_RELEASE_RESET
#define __SPI6_CLK_SLEEP_ENABLE __HAL_RCC_SPI6_CLK_SLEEP_ENABLE
-#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
+#define __SPI6_CLK_SLEEP_DISABLE __HAL_RCC_SPI6_CLK_SLEEP_DISABLE
#define __LTDC_CLK_ENABLE __HAL_RCC_LTDC_CLK_ENABLE
#define __LTDC_CLK_DISABLE __HAL_RCC_LTDC_CLK_DISABLE
#define __LTDC_FORCE_RESET __HAL_RCC_LTDC_FORCE_RESET
#define __LTDC_RELEASE_RESET __HAL_RCC_LTDC_RELEASE_RESET
-#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
+#define __LTDC_CLK_SLEEP_ENABLE __HAL_RCC_LTDC_CLK_SLEEP_ENABLE
#define __ETHMAC_CLK_SLEEP_ENABLE __HAL_RCC_ETHMAC_CLK_SLEEP_ENABLE
-#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
+#define __ETHMAC_CLK_SLEEP_DISABLE __HAL_RCC_ETHMAC_CLK_SLEEP_DISABLE
#define __ETHMACTX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_ENABLE
-#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
+#define __ETHMACTX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACTX_CLK_SLEEP_DISABLE
#define __ETHMACRX_CLK_SLEEP_ENABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_ENABLE
-#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
+#define __ETHMACRX_CLK_SLEEP_DISABLE __HAL_RCC_ETHMACRX_CLK_SLEEP_DISABLE
#define __TIM12_CLK_SLEEP_ENABLE __HAL_RCC_TIM12_CLK_SLEEP_ENABLE
-#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
+#define __TIM12_CLK_SLEEP_DISABLE __HAL_RCC_TIM12_CLK_SLEEP_DISABLE
#define __TIM13_CLK_SLEEP_ENABLE __HAL_RCC_TIM13_CLK_SLEEP_ENABLE
-#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
+#define __TIM13_CLK_SLEEP_DISABLE __HAL_RCC_TIM13_CLK_SLEEP_DISABLE
#define __TIM14_CLK_SLEEP_ENABLE __HAL_RCC_TIM14_CLK_SLEEP_ENABLE
-#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
+#define __TIM14_CLK_SLEEP_DISABLE __HAL_RCC_TIM14_CLK_SLEEP_DISABLE
#define __BKPSRAM_CLK_ENABLE __HAL_RCC_BKPSRAM_CLK_ENABLE
#define __BKPSRAM_CLK_DISABLE __HAL_RCC_BKPSRAM_CLK_DISABLE
#define __BKPSRAM_CLK_SLEEP_ENABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_ENABLE
-#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
+#define __BKPSRAM_CLK_SLEEP_DISABLE __HAL_RCC_BKPSRAM_CLK_SLEEP_DISABLE
#define __CCMDATARAMEN_CLK_ENABLE __HAL_RCC_CCMDATARAMEN_CLK_ENABLE
-#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
+#define __CCMDATARAMEN_CLK_DISABLE __HAL_RCC_CCMDATARAMEN_CLK_DISABLE
#define __USART6_CLK_ENABLE __HAL_RCC_USART6_CLK_ENABLE
#define __USART6_CLK_DISABLE __HAL_RCC_USART6_CLK_DISABLE
#define __USART6_FORCE_RESET __HAL_RCC_USART6_FORCE_RESET
#define __USART6_RELEASE_RESET __HAL_RCC_USART6_RELEASE_RESET
#define __USART6_CLK_SLEEP_ENABLE __HAL_RCC_USART6_CLK_SLEEP_ENABLE
-#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
+#define __USART6_CLK_SLEEP_DISABLE __HAL_RCC_USART6_CLK_SLEEP_DISABLE
#define __SPI4_CLK_ENABLE __HAL_RCC_SPI4_CLK_ENABLE
#define __SPI4_CLK_DISABLE __HAL_RCC_SPI4_CLK_DISABLE
#define __SPI4_FORCE_RESET __HAL_RCC_SPI4_FORCE_RESET
#define __SPI4_RELEASE_RESET __HAL_RCC_SPI4_RELEASE_RESET
#define __SPI4_CLK_SLEEP_ENABLE __HAL_RCC_SPI4_CLK_SLEEP_ENABLE
-#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
+#define __SPI4_CLK_SLEEP_DISABLE __HAL_RCC_SPI4_CLK_SLEEP_DISABLE
#define __GPIOI_CLK_ENABLE __HAL_RCC_GPIOI_CLK_ENABLE
#define __GPIOI_CLK_DISABLE __HAL_RCC_GPIOI_CLK_DISABLE
#define __GPIOI_FORCE_RESET __HAL_RCC_GPIOI_FORCE_RESET
#define __GPIOI_RELEASE_RESET __HAL_RCC_GPIOI_RELEASE_RESET
#define __GPIOI_CLK_SLEEP_ENABLE __HAL_RCC_GPIOI_CLK_SLEEP_ENABLE
-#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
+#define __GPIOI_CLK_SLEEP_DISABLE __HAL_RCC_GPIOI_CLK_SLEEP_DISABLE
#define __GPIOJ_CLK_ENABLE __HAL_RCC_GPIOJ_CLK_ENABLE
#define __GPIOJ_CLK_DISABLE __HAL_RCC_GPIOJ_CLK_DISABLE
#define __GPIOJ_FORCE_RESET __HAL_RCC_GPIOJ_FORCE_RESET
#define __GPIOJ_RELEASE_RESET __HAL_RCC_GPIOJ_RELEASE_RESET
#define __GPIOJ_CLK_SLEEP_ENABLE __HAL_RCC_GPIOJ_CLK_SLEEP_ENABLE
-#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
+#define __GPIOJ_CLK_SLEEP_DISABLE __HAL_RCC_GPIOJ_CLK_SLEEP_DISABLE
#define __GPIOK_CLK_ENABLE __HAL_RCC_GPIOK_CLK_ENABLE
#define __GPIOK_CLK_DISABLE __HAL_RCC_GPIOK_CLK_DISABLE
#define __GPIOK_RELEASE_RESET __HAL_RCC_GPIOK_RELEASE_RESET
#define __GPIOK_CLK_SLEEP_ENABLE __HAL_RCC_GPIOK_CLK_SLEEP_ENABLE
-#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
+#define __GPIOK_CLK_SLEEP_DISABLE __HAL_RCC_GPIOK_CLK_SLEEP_DISABLE
#define __ETH_CLK_ENABLE __HAL_RCC_ETH_CLK_ENABLE
-#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
+#define __ETH_CLK_DISABLE __HAL_RCC_ETH_CLK_DISABLE
#define __DCMI_CLK_ENABLE __HAL_RCC_DCMI_CLK_ENABLE
#define __DCMI_CLK_DISABLE __HAL_RCC_DCMI_CLK_DISABLE
#define __DCMI_FORCE_RESET __HAL_RCC_DCMI_FORCE_RESET
#define __DCMI_RELEASE_RESET __HAL_RCC_DCMI_RELEASE_RESET
#define __DCMI_CLK_SLEEP_ENABLE __HAL_RCC_DCMI_CLK_SLEEP_ENABLE
-#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
+#define __DCMI_CLK_SLEEP_DISABLE __HAL_RCC_DCMI_CLK_SLEEP_DISABLE
#define __UART7_CLK_ENABLE __HAL_RCC_UART7_CLK_ENABLE
#define __UART7_CLK_DISABLE __HAL_RCC_UART7_CLK_DISABLE
#define __UART7_RELEASE_RESET __HAL_RCC_UART7_RELEASE_RESET
#define __UART7_FORCE_RESET __HAL_RCC_UART7_FORCE_RESET
#define __UART7_CLK_SLEEP_ENABLE __HAL_RCC_UART7_CLK_SLEEP_ENABLE
-#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
+#define __UART7_CLK_SLEEP_DISABLE __HAL_RCC_UART7_CLK_SLEEP_DISABLE
#define __UART8_CLK_ENABLE __HAL_RCC_UART8_CLK_ENABLE
#define __UART8_CLK_DISABLE __HAL_RCC_UART8_CLK_DISABLE
#define __UART8_FORCE_RESET __HAL_RCC_UART8_FORCE_RESET
#define __UART8_RELEASE_RESET __HAL_RCC_UART8_RELEASE_RESET
#define __UART8_CLK_SLEEP_ENABLE __HAL_RCC_UART8_CLK_SLEEP_ENABLE
-#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
+#define __UART8_CLK_SLEEP_DISABLE __HAL_RCC_UART8_CLK_SLEEP_DISABLE
#define __OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
#define __OTGHS_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE
#define __OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
-#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
+#define __OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
#define __OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
#define __OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
#define __HAL_RCC_OTGHS_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE
@@ -2402,29 +2496,28 @@
#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_ENABLED
#define __HAL_RCC_OTGHS_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_IS_CLK_SLEEP_DISABLED
#define __HAL_RCC_OTGHS_FORCE_RESET __HAL_RCC_USB_OTG_HS_FORCE_RESET
-#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
+#define __HAL_RCC_OTGHS_RELEASE_RESET __HAL_RCC_USB_OTG_HS_RELEASE_RESET
#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_ENABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE
-#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
+#define __HAL_RCC_OTGHSULPI_CLK_SLEEP_DISABLE __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE
#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_ENABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_ENABLED
-#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
-#define __CRYP_FORCE_RESET __HAL_RCC_CRYP_FORCE_RESET
-#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
+#define __HAL_RCC_OTGHSULPI_IS_CLK_SLEEP_DISABLED __HAL_RCC_USB_OTG_HS_ULPI_IS_CLK_SLEEP_DISABLED
+#define __SRAM3_CLK_SLEEP_ENABLE __HAL_RCC_SRAM3_CLK_SLEEP_ENABLE
#define __CAN2_CLK_SLEEP_ENABLE __HAL_RCC_CAN2_CLK_SLEEP_ENABLE
-#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
+#define __CAN2_CLK_SLEEP_DISABLE __HAL_RCC_CAN2_CLK_SLEEP_DISABLE
#define __DAC_CLK_SLEEP_ENABLE __HAL_RCC_DAC_CLK_SLEEP_ENABLE
-#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
+#define __DAC_CLK_SLEEP_DISABLE __HAL_RCC_DAC_CLK_SLEEP_DISABLE
#define __ADC2_CLK_SLEEP_ENABLE __HAL_RCC_ADC2_CLK_SLEEP_ENABLE
-#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
+#define __ADC2_CLK_SLEEP_DISABLE __HAL_RCC_ADC2_CLK_SLEEP_DISABLE
#define __ADC3_CLK_SLEEP_ENABLE __HAL_RCC_ADC3_CLK_SLEEP_ENABLE
-#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
+#define __ADC3_CLK_SLEEP_DISABLE __HAL_RCC_ADC3_CLK_SLEEP_DISABLE
#define __FSMC_FORCE_RESET __HAL_RCC_FSMC_FORCE_RESET
#define __FSMC_RELEASE_RESET __HAL_RCC_FSMC_RELEASE_RESET
#define __FSMC_CLK_SLEEP_ENABLE __HAL_RCC_FSMC_CLK_SLEEP_ENABLE
-#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
+#define __FSMC_CLK_SLEEP_DISABLE __HAL_RCC_FSMC_CLK_SLEEP_DISABLE
#define __SDIO_FORCE_RESET __HAL_RCC_SDIO_FORCE_RESET
#define __SDIO_RELEASE_RESET __HAL_RCC_SDIO_RELEASE_RESET
#define __SDIO_CLK_SLEEP_DISABLE __HAL_RCC_SDIO_CLK_SLEEP_DISABLE
-#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
+#define __SDIO_CLK_SLEEP_ENABLE __HAL_RCC_SDIO_CLK_SLEEP_ENABLE
#define __DMA2D_CLK_ENABLE __HAL_RCC_DMA2D_CLK_ENABLE
#define __DMA2D_CLK_DISABLE __HAL_RCC_DMA2D_CLK_DISABLE
#define __DMA2D_FORCE_RESET __HAL_RCC_DMA2D_FORCE_RESET
@@ -2440,8 +2533,6 @@
#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
#define __ADC34_CLK_ENABLE __HAL_RCC_ADC34_CLK_ENABLE
#define __ADC34_CLK_DISABLE __HAL_RCC_ADC34_CLK_DISABLE
-#define __ADC12_CLK_ENABLE __HAL_RCC_ADC12_CLK_ENABLE
-#define __ADC12_CLK_DISABLE __HAL_RCC_ADC12_CLK_DISABLE
#define __DAC2_CLK_ENABLE __HAL_RCC_DAC2_CLK_ENABLE
#define __DAC2_CLK_DISABLE __HAL_RCC_DAC2_CLK_DISABLE
#define __TIM18_CLK_ENABLE __HAL_RCC_TIM18_CLK_ENABLE
@@ -2463,8 +2554,6 @@
#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
#define __ADC34_FORCE_RESET __HAL_RCC_ADC34_FORCE_RESET
#define __ADC34_RELEASE_RESET __HAL_RCC_ADC34_RELEASE_RESET
-#define __ADC12_FORCE_RESET __HAL_RCC_ADC12_FORCE_RESET
-#define __ADC12_RELEASE_RESET __HAL_RCC_ADC12_RELEASE_RESET
#define __DAC2_FORCE_RESET __HAL_RCC_DAC2_FORCE_RESET
#define __DAC2_RELEASE_RESET __HAL_RCC_DAC2_RELEASE_RESET
#define __TIM18_FORCE_RESET __HAL_RCC_TIM18_FORCE_RESET
@@ -2628,7 +2717,7 @@
#define SdioClockSelection Sdmmc1ClockSelection
#define RCC_PERIPHCLK_SDIO RCC_PERIPHCLK_SDMMC1
#define __HAL_RCC_SDIO_CONFIG __HAL_RCC_SDMMC1_CONFIG
-#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE
+#define __HAL_RCC_GET_SDIO_SOURCE __HAL_RCC_GET_SDMMC1_SOURCE
#endif
#if defined(STM32F7)
@@ -2636,6 +2725,30 @@
#define RCC_SDIOCLKSOURCE_SYSCLK RCC_SDMMC1CLKSOURCE_SYSCLK
#endif
+#if defined(STM32H7)
+#define __HAL_RCC_USB_OTG_HS_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_FORCE_RESET() __HAL_RCC_USB1_OTG_HS_FORCE_RESET()
+#define __HAL_RCC_USB_OTG_HS_RELEASE_RESET() __HAL_RCC_USB1_OTG_HS_RELEASE_RESET()
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_HS_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_CLK_SLEEP_DISABLE()
+#define __HAL_RCC_USB_OTG_HS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB1_OTG_HS_ULPI_CLK_SLEEP_DISABLE()
+
+#define __HAL_RCC_USB_OTG_FS_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_FORCE_RESET() __HAL_RCC_USB2_OTG_FS_FORCE_RESET()
+#define __HAL_RCC_USB_OTG_FS_RELEASE_RESET() __HAL_RCC_USB2_OTG_FS_RELEASE_RESET()
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_ENABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_ENABLE()
+#define __HAL_RCC_USB_OTG_FS_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_CLK_SLEEP_DISABLE()
+#define __HAL_RCC_USB_OTG_FS_ULPI_CLK_SLEEP_DISABLE() __HAL_RCC_USB2_OTG_FS_ULPI_CLK_SLEEP_DISABLE()
+#endif
+
#define __HAL_RCC_I2SCLK __HAL_RCC_I2S_CONFIG
#define __HAL_RCC_I2SCLK_CONFIG __HAL_RCC_I2S_CONFIG
@@ -2689,7 +2802,12 @@
#define RCC_MCOSOURCE_PLLCLK_NODIV RCC_MCO1SOURCE_PLLCLK
#define RCC_MCOSOURCE_PLLCLK_DIV2 RCC_MCO1SOURCE_PLLCLK_DIV2
+#if defined(STM32L4)
+#define RCC_RTCCLKSOURCE_NO_CLK RCC_RTCCLKSOURCE_NONE
+#elif defined(STM32WB) || defined(STM32G0)
+#else
#define RCC_RTCCLKSOURCE_NONE RCC_RTCCLKSOURCE_NO_CLK
+#endif
#define RCC_USBCLK_PLLSAI1 RCC_USBCLKSOURCE_PLLSAI1
#define RCC_USBCLK_PLL RCC_USBCLKSOURCE_PLL
@@ -2789,6 +2907,15 @@
#define RCC_SWPMI1CLKSOURCE_PCLK RCC_SWPMI1CLKSOURCE_PCLK1
#define RCC_LPTIM1CLKSOURCE_PCLK RCC_LPTIM1CLKSOURCE_PCLK1
#define RCC_LPTIM2CLKSOURCE_PCLK RCC_LPTIM2CLKSOURCE_PCLK1
+
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM1AUDIOCLKSOURCE_I2S1
+#define RCC_DFSDM1AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM1AUDIOCLKSOURCE_I2S2
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB1 RCC_DFSDM2AUDIOCLKSOURCE_I2S1
+#define RCC_DFSDM2AUDIOCLKSOURCE_I2SAPB2 RCC_DFSDM2AUDIOCLKSOURCE_I2S2
+#define RCC_DFSDM1CLKSOURCE_APB2 RCC_DFSDM1CLKSOURCE_PCLK2
+#define RCC_DFSDM2CLKSOURCE_APB2 RCC_DFSDM2CLKSOURCE_PCLK2
+#define RCC_FMPI2C1CLKSOURCE_APB RCC_FMPI2C1CLKSOURCE_PCLK1
+
/**
* @}
*/
@@ -2796,17 +2923,19 @@
/** @defgroup HAL_RNG_Aliased_Macros HAL RNG Aliased Macros maintained for legacy purpose
* @{
*/
-#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
+#define HAL_RNG_ReadyCallback(__HANDLE__) HAL_RNG_ReadyDataCallback((__HANDLE__), uint32_t random32bit)
/**
* @}
*/
-
+
/** @defgroup HAL_RTC_Aliased_Macros HAL RTC Aliased Macros maintained for legacy purpose
* @{
*/
-
+#if defined (STM32G0)
+#else
#define __HAL_RTC_CLEAR_FLAG __HAL_RTC_EXTI_CLEAR_FLAG
+#endif
#define __HAL_RTC_DISABLE_IT __HAL_RTC_EXTI_DISABLE_IT
#define __HAL_RTC_ENABLE_IT __HAL_RTC_EXTI_ENABLE_IT
@@ -2842,7 +2971,7 @@
#define IS_ALARM_MASK IS_RTC_ALARM_MASK
#define IS_TAMPER IS_RTC_TAMPER
#define IS_TAMPER_ERASE_MODE IS_RTC_TAMPER_ERASE_MODE
-#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
+#define IS_TAMPER_FILTER IS_RTC_TAMPER_FILTER
#define IS_TAMPER_INTERRUPT IS_RTC_TAMPER_INTERRUPT
#define IS_TAMPER_MASKFLAG_STATE IS_RTC_TAMPER_MASKFLAG_STATE
#define IS_TAMPER_PRECHARGE_DURATION IS_RTC_TAMPER_PRECHARGE_DURATION
@@ -2867,26 +2996,26 @@
#define SD_OCR_CID_CSD_OVERWRIETE SD_OCR_CID_CSD_OVERWRITE
#define SD_CMD_SD_APP_STAUS SD_CMD_SD_APP_STATUS
-#if defined(STM32F4)
+#if defined(STM32F4) || defined(STM32F2)
#define SD_SDMMC_DISABLED SD_SDIO_DISABLED
-#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
-#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED
-#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION
-#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND
-#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT
-#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED
-#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE
-#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE
-#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE
-#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
-#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT
-#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT
-#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG
-#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG
-#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT
-#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT
-#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS
-#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT
+#define SD_SDMMC_FUNCTION_BUSY SD_SDIO_FUNCTION_BUSY
+#define SD_SDMMC_FUNCTION_FAILED SD_SDIO_FUNCTION_FAILED
+#define SD_SDMMC_UNKNOWN_FUNCTION SD_SDIO_UNKNOWN_FUNCTION
+#define SD_CMD_SDMMC_SEN_OP_COND SD_CMD_SDIO_SEN_OP_COND
+#define SD_CMD_SDMMC_RW_DIRECT SD_CMD_SDIO_RW_DIRECT
+#define SD_CMD_SDMMC_RW_EXTENDED SD_CMD_SDIO_RW_EXTENDED
+#define __HAL_SD_SDMMC_ENABLE __HAL_SD_SDIO_ENABLE
+#define __HAL_SD_SDMMC_DISABLE __HAL_SD_SDIO_DISABLE
+#define __HAL_SD_SDMMC_DMA_ENABLE __HAL_SD_SDIO_DMA_ENABLE
+#define __HAL_SD_SDMMC_DMA_DISABLE __HAL_SD_SDIO_DMA_DISABL
+#define __HAL_SD_SDMMC_ENABLE_IT __HAL_SD_SDIO_ENABLE_IT
+#define __HAL_SD_SDMMC_DISABLE_IT __HAL_SD_SDIO_DISABLE_IT
+#define __HAL_SD_SDMMC_GET_FLAG __HAL_SD_SDIO_GET_FLAG
+#define __HAL_SD_SDMMC_CLEAR_FLAG __HAL_SD_SDIO_CLEAR_FLAG
+#define __HAL_SD_SDMMC_GET_IT __HAL_SD_SDIO_GET_IT
+#define __HAL_SD_SDMMC_CLEAR_IT __HAL_SD_SDIO_CLEAR_IT
+#define SDMMC_STATIC_FLAGS SDIO_STATIC_FLAGS
+#define SDMMC_CMD0TIMEOUT SDIO_CMD0TIMEOUT
#define SD_SDMMC_SEND_IF_COND SD_SDIO_SEND_IF_COND
/* alias CMSIS */
#define SDMMC1_IRQn SDIO_IRQn
@@ -2895,8 +3024,8 @@
#if defined(STM32F7) || defined(STM32L4)
#define SD_SDIO_DISABLED SD_SDMMC_DISABLED
-#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY
-#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED
+#define SD_SDIO_FUNCTION_BUSY SD_SDMMC_FUNCTION_BUSY
+#define SD_SDIO_FUNCTION_FAILED SD_SDMMC_FUNCTION_FAILED
#define SD_SDIO_UNKNOWN_FUNCTION SD_SDMMC_UNKNOWN_FUNCTION
#define SD_CMD_SDIO_SEN_OP_COND SD_CMD_SDMMC_SEN_OP_COND
#define SD_CMD_SDIO_RW_DIRECT SD_CMD_SDMMC_RW_DIRECT
@@ -2919,13 +3048,23 @@
#define SDIO_IRQHandler SDMMC1_IRQHandler
#endif
-#if defined(STM32F7) || defined(STM32F4)
+#if defined(STM32F7) || defined(STM32F4) || defined(STM32F2)
#define HAL_SD_CardCIDTypedef HAL_SD_CardCIDTypeDef
#define HAL_SD_CardCSDTypedef HAL_SD_CardCSDTypeDef
#define HAL_SD_CardStatusTypedef HAL_SD_CardStatusTypeDef
#define HAL_SD_CardStateTypedef HAL_SD_CardStateTypeDef
#endif
+#if defined(STM32H7)
+#define HAL_MMCEx_Read_DMADoubleBuffer0CpltCallback HAL_MMCEx_Read_DMADoubleBuf0CpltCallback
+#define HAL_MMCEx_Read_DMADoubleBuffer1CpltCallback HAL_MMCEx_Read_DMADoubleBuf1CpltCallback
+#define HAL_MMCEx_Write_DMADoubleBuffer0CpltCallback HAL_MMCEx_Write_DMADoubleBuf0CpltCallback
+#define HAL_MMCEx_Write_DMADoubleBuffer1CpltCallback HAL_MMCEx_Write_DMADoubleBuf1CpltCallback
+#define HAL_SDEx_Read_DMADoubleBuffer0CpltCallback HAL_SDEx_Read_DMADoubleBuf0CpltCallback
+#define HAL_SDEx_Read_DMADoubleBuffer1CpltCallback HAL_SDEx_Read_DMADoubleBuf1CpltCallback
+#define HAL_SDEx_Write_DMADoubleBuffer0CpltCallback HAL_SDEx_Write_DMADoubleBuf0CpltCallback
+#define HAL_SDEx_Write_DMADoubleBuffer1CpltCallback HAL_SDEx_Write_DMADoubleBuf1CpltCallback
+#endif
/**
* @}
*/
@@ -2944,7 +3083,7 @@
#define __HAL_SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
#define __SMARTCARD_GETCLOCKSOURCE SMARTCARD_GETCLOCKSOURCE
-#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
+#define IS_SMARTCARD_ONEBIT_SAMPLING IS_SMARTCARD_ONE_BIT_SAMPLE
/**
* @}
@@ -2976,7 +3115,7 @@
/**
* @}
*/
-
+
/** @defgroup HAL_UART_Aliased_Macros HAL UART Aliased Macros maintained for legacy purpose
* @{
*/
@@ -2988,8 +3127,8 @@
#define IS_UART_WAKEUPMETHODE IS_UART_WAKEUPMETHOD
-#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
-#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
+#define IS_UART_ONEBIT_SAMPLE IS_UART_ONE_BIT_SAMPLE
+#define IS_UART_ONEBIT_SAMPLING IS_UART_ONE_BIT_SAMPLE
/**
* @}
@@ -3094,7 +3233,7 @@
/** @defgroup HAL_ETH_Aliased_Macros HAL ETH Aliased Macros maintained for legacy purpose
* @{
*/
-
+
#define __HAL_ETH_EXTI_ENABLE_IT __HAL_ETH_WAKEUP_EXTI_ENABLE_IT
#define __HAL_ETH_EXTI_DISABLE_IT __HAL_ETH_WAKEUP_EXTI_DISABLE_IT
#define __HAL_ETH_EXTI_GET_FLAG __HAL_ETH_WAKEUP_EXTI_GET_FLAG
@@ -3103,7 +3242,7 @@
#define __HAL_ETH_EXTI_SET_FALLING_EGDE_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER
#define __HAL_ETH_EXTI_SET_FALLINGRISING_TRIGGER __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER
-#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
+#define ETH_PROMISCIOUSMODE_ENABLE ETH_PROMISCUOUS_MODE_ENABLE
#define ETH_PROMISCIOUSMODE_DISABLE ETH_PROMISCUOUS_MODE_DISABLE
#define IS_ETH_PROMISCIOUS_MODE IS_ETH_PROMISCUOUS_MODE
/**
@@ -3114,6 +3253,10 @@
* @{
*/
#define __HAL_LTDC_LAYER LTDC_LAYER
+#if defined(STM32F7)
+#else
+#define __HAL_LTDC_RELOAD_CONFIG __HAL_LTDC_RELOAD_IMMEDIATE_CONFIG
+#endif
/**
* @}
*/
@@ -3139,11 +3282,22 @@
* @}
*/
+/** @defgroup HAL_SPDIFRX_Aliased_Macros HAL SPDIFRX Aliased Macros maintained for legacy purpose
+ * @{
+ */
+#if defined(STM32H7)
+#define HAL_SPDIFRX_ReceiveControlFlow HAL_SPDIFRX_ReceiveCtrlFlow
+#define HAL_SPDIFRX_ReceiveControlFlow_IT HAL_SPDIFRX_ReceiveCtrlFlow_IT
+#define HAL_SPDIFRX_ReceiveControlFlow_DMA HAL_SPDIFRX_ReceiveCtrlFlow_DMA
+#endif
+/**
+ * @}
+ */
/** @defgroup HAL_PPP_Aliased_Macros HAL PPP Aliased Macros maintained for legacy purpose
* @{
*/
-
+
/**
* @}
*/
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal.c
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief HAL module driver.
* This is the common part of the HAL initialization
*
@@ -68,11 +66,11 @@
* @{
*/
/**
- * @brief STM32F7xx HAL Driver version number V1.2.2
+ * @brief STM32F7xx HAL Driver version number V1.2.5
*/
#define __STM32F7xx_HAL_VERSION_MAIN (0x01) /*!< [31:24] main version */
#define __STM32F7xx_HAL_VERSION_SUB1 (0x02) /*!< [23:16] sub1 version */
-#define __STM32F7xx_HAL_VERSION_SUB2 (0x02) /*!< [15:8] sub2 version */
+#define __STM32F7xx_HAL_VERSION_SUB2 (0x05) /*!< [15:8] sub2 version */
#define __STM32F7xx_HAL_VERSION_RC (0x00) /*!< [7:0] release candidate */
#define __STM32F7xx_HAL_VERSION ((__STM32F7xx_HAL_VERSION_MAIN << 24)\
|(__STM32F7xx_HAL_VERSION_SUB1 << 16)\
@@ -90,6 +88,8 @@
* @{
*/
__IO uint32_t uwTick;
+uint32_t uwTickPrio = (1UL << __NVIC_PRIO_BITS); /* Invalid PRIO */
+HAL_TickFreqTypeDef uwTickFreq = HAL_TICK_FREQ_DEFAULT; /* 1KHz */
/**
* @}
*/
@@ -106,16 +106,16 @@
*
@verbatim
===============================================================================
- ##### Initialization and de-initialization functions #####
+ ##### Initialization and Configuration functions #####
===============================================================================
[..] This section provides functions allowing to:
(+) Initializes the Flash interface the NVIC allocation and initial clock
configuration. It initializes the systick also when timeout is needed
and the backup domain when enabled.
- (+) de-Initializes common part of the HAL
- (+) Configure The time base source to have 1ms time base with a dedicated
+ (+) De-Initializes common part of the HAL.
+ (+) Configure the time base source to have 1ms time base with a dedicated
Tick interrupt priority.
- (++) Systick timer is used by default as source of time base, but user
+ (++) SysTick timer is used by default as source of time base, but user
can eventually implement his proper time base source (a general purpose
timer for example or other time source), keeping in mind that Time base
duration should be kept 1ms since PPP_TIMEOUT_VALUEs are defined and
@@ -153,11 +153,16 @@
*/
HAL_StatusTypeDef HAL_Init(void)
{
- /* Configure Flash prefetch and Instruction cache through ART accelerator */
+ /* Configure Instruction cache through ART accelerator */
#if (ART_ACCLERATOR_ENABLE != 0)
__HAL_FLASH_ART_ENABLE();
#endif /* ART_ACCLERATOR_ENABLE */
+ /* Configure Flash prefetch */
+#if (PREFETCH_ENABLE != 0U)
+ __HAL_FLASH_PREFETCH_BUFFER_ENABLE();
+#endif /* PREFETCH_ENABLE */
+
/* Set Interrupt Group Priority */
HAL_NVIC_SetPriorityGrouping(NVIC_PRIORITYGROUP_4);
@@ -202,12 +207,12 @@
}
/**
- * @brief Initializes the MSP.
+ * @brief Initialize the MSP.
* @retval None
*/
__weak void HAL_MspInit(void)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_MspInit could be implemented in the user file
*/
}
@@ -218,7 +223,7 @@
*/
__weak void HAL_MspDeInit(void)
{
- /* NOTE : This function Should not be modified, when the callback is needed,
+ /* NOTE : This function should not be modified, when the callback is needed,
the HAL_MspDeInit could be implemented in the user file
*/
}
@@ -232,20 +237,31 @@
* @note In the default implementation, SysTick timer is the source of time base.
* It is used to generate interrupts at regular time intervals.
* Care must be taken if HAL_Delay() is called from a peripheral ISR process,
- * The the SysTick interrupt must have higher priority (numerically lower)
+ * The SysTick interrupt must have higher priority (numerically lower)
* than the peripheral interrupt. Otherwise the caller ISR process will be blocked.
* The function is declared as __weak to be overwritten in case of other
* implementation in user file.
- * @param TickPriority: Tick interrupt priority.
+ * @param TickPriority Tick interrupt priority.
* @retval HAL status
*/
__weak HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority)
{
- /*Configure the SysTick to have interrupt in 1ms time basis*/
- HAL_SYSTICK_Config(SystemCoreClock/1000);
+ /* Configure the SysTick to have interrupt in 1ms time basis*/
+ if (HAL_SYSTICK_Config(SystemCoreClock / (1000U / uwTickFreq)) > 0U)
+ {
+ return HAL_ERROR;
+ }
- /*Configure the SysTick IRQ priority */
- HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority ,0);
+ /* Configure the SysTick IRQ priority */
+ if (TickPriority < (1UL << __NVIC_PRIO_BITS))
+ {
+ HAL_NVIC_SetPriority(SysTick_IRQn, TickPriority, 0U);
+ uwTickPrio = TickPriority;
+ }
+ else
+ {
+ return HAL_ERROR;
+ }
/* Return function status */
return HAL_OK;
@@ -282,14 +298,14 @@
* @brief This function is called to increment a global variable "uwTick"
* used as application time base.
* @note In the default implementation, this variable is incremented each 1ms
- * in Systick ISR.
+ * in SysTick ISR.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
* @retval None
*/
__weak void HAL_IncTick(void)
{
- uwTick++;
+ uwTick += uwTickFreq;
}
/**
@@ -304,21 +320,66 @@
}
/**
- * @brief This function provides accurate delay (in milliseconds) based
+ * @brief This function returns a tick priority.
+ * @retval tick priority
+ */
+uint32_t HAL_GetTickPrio(void)
+{
+ return uwTickPrio;
+}
+
+/**
+ * @brief Set new tick Freq.
+ * @retval Status
+ */
+HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+ assert_param(IS_TICKFREQ(Freq));
+
+ if (uwTickFreq != Freq)
+ {
+ uwTickFreq = Freq;
+
+ /* Apply the new tick Freq */
+ status = HAL_InitTick(uwTickPrio);
+ }
+
+ return status;
+}
+
+/**
+ * @brief Return tick frequency.
+ * @retval tick period in Hz
+ */
+HAL_TickFreqTypeDef HAL_GetTickFreq(void)
+{
+ return uwTickFreq;
+}
+
+/**
+ * @brief This function provides minimum delay (in milliseconds) based
* on variable incremented.
* @note In the default implementation , SysTick timer is the source of time base.
* It is used to generate interrupts at regular time intervals where uwTick
* is incremented.
* @note This function is declared as __weak to be overwritten in case of other
* implementations in user file.
- * @param Delay: specifies the delay time length, in milliseconds.
+ * @param Delay specifies the delay time length, in milliseconds.
* @retval None
*/
-__weak void HAL_Delay(__IO uint32_t Delay)
+__weak void HAL_Delay(uint32_t Delay)
{
- uint32_t tickstart = 0;
- tickstart = HAL_GetTick();
- while((HAL_GetTick() - tickstart) < Delay)
+ uint32_t tickstart = HAL_GetTick();
+ uint32_t wait = Delay;
+
+ /* Add a freq to guarantee minimum wait */
+ if (wait < HAL_MAX_DELAY)
+ {
+ wait += (uint32_t)(uwTickFreq);
+ }
+
+ while ((HAL_GetTick() - tickstart) < wait)
{
}
}
@@ -383,6 +444,33 @@
}
/**
+ * @brief Returns first word of the unique device identifier (UID based on 96 bits)
+ * @retval Device identifier
+ */
+uint32_t HAL_GetUIDw0(void)
+{
+ return(READ_REG(*((uint32_t *)UID_BASE)));
+}
+
+/**
+ * @brief Returns second word of the unique device identifier (UID based on 96 bits)
+ * @retval Device identifier
+ */
+uint32_t HAL_GetUIDw1(void)
+{
+ return(READ_REG(*((uint32_t *)(UID_BASE + 4U))));
+}
+
+/**
+ * @brief Returns third word of the unique device identifier (UID based on 96 bits)
+ * @retval Device identifier
+ */
+uint32_t HAL_GetUIDw2(void)
+{
+ return(READ_REG(*((uint32_t *)(UID_BASE + 8U))));
+}
+
+/**
* @brief Enable the Debug Module during SLEEP mode
* @retval None
*/
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal.h
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief This file contains all the functions prototypes for the HAL
* module driver.
******************************************************************************
@@ -57,10 +55,25 @@
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
+
/** @defgroup HAL_Exported_Constants HAL Exported Constants
* @{
*/
+/** @defgroup HAL_TICK_FREQ Tick Frequency
+ * @{
+ */
+typedef enum
+{
+ HAL_TICK_FREQ_10HZ = 100U,
+ HAL_TICK_FREQ_100HZ = 10U,
+ HAL_TICK_FREQ_1KHZ = 1U,
+ HAL_TICK_FREQ_DEFAULT = HAL_TICK_FREQ_1KHZ
+} HAL_TickFreqTypeDef;
+/**
+ * @}
+ */
+
/** @defgroup SYSCFG_BootMode Boot Mode
* @{
*/
@@ -169,6 +182,15 @@
* @}
*/
+/** @defgroup HAL_Private_Macros HAL Private Macros
+ * @{
+ */
+#define IS_TICKFREQ(FREQ) (((FREQ) == HAL_TICK_FREQ_10HZ) || \
+ ((FREQ) == HAL_TICK_FREQ_100HZ) || \
+ ((FREQ) == HAL_TICK_FREQ_1KHZ))
+/**
+ * @}
+ */
/* Exported functions --------------------------------------------------------*/
/** @addtogroup HAL_Exported_Functions
* @{
@@ -176,12 +198,12 @@
/** @addtogroup HAL_Exported_Functions_Group1
* @{
*/
-/* Initialization and de-initialization functions ******************************/
+/* Initialization and Configuration functions ******************************/
HAL_StatusTypeDef HAL_Init(void);
HAL_StatusTypeDef HAL_DeInit(void);
void HAL_MspInit(void);
void HAL_MspDeInit(void);
-HAL_StatusTypeDef HAL_InitTick (uint32_t TickPriority);
+HAL_StatusTypeDef HAL_InitTick(uint32_t TickPriority);
/**
* @}
*/
@@ -191,13 +213,19 @@
*/
/* Peripheral Control functions ************************************************/
void HAL_IncTick(void);
-void HAL_Delay(__IO uint32_t Delay);
+void HAL_Delay(uint32_t Delay);
uint32_t HAL_GetTick(void);
+uint32_t HAL_GetTickPrio(void);
+HAL_StatusTypeDef HAL_SetTickFreq(HAL_TickFreqTypeDef Freq);
+HAL_TickFreqTypeDef HAL_GetTickFreq(void);
void HAL_SuspendTick(void);
void HAL_ResumeTick(void);
uint32_t HAL_GetHalVersion(void);
uint32_t HAL_GetREVID(void);
uint32_t HAL_GetDEVID(void);
+uint32_t HAL_GetUIDw0(void);
+uint32_t HAL_GetUIDw1(void);
+uint32_t HAL_GetUIDw2(void);
void HAL_DBGMCU_EnableDBGSleepMode(void);
void HAL_DBGMCU_DisableDBGSleepMode(void);
void HAL_DBGMCU_EnableDBGStopMode(void);
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_adc.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_adc.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_adc.c * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief This file provides firmware functions to manage the following * functionalities of the Analog to Digital Convertor (ADC) peripheral: * + Initialization and de-initialization functions @@ -252,7 +250,7 @@ * External trigger source and edge, DMA continuous request after the * last transfer and End of conversion selection). * - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval HAL status */ @@ -329,7 +327,7 @@ /** * @brief Deinitializes the ADCx peripheral registers to their default reset values. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval HAL status */ @@ -376,7 +374,7 @@ /** * @brief Initializes the ADC MSP. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ @@ -391,7 +389,7 @@ /** * @brief DeInitializes the ADC MSP. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ @@ -430,7 +428,7 @@ /** * @brief Enables ADC and starts conversion of the regular channels. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval HAL status */ @@ -530,7 +528,7 @@ * * @note Caution: This function will stop also injected channels. * - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * * @retval HAL status. @@ -573,9 +571,9 @@ * In this case, DMA resets the flag EOC and polling cannot be * performed on each conversion. Nevertheless, polling can still * be performed on the complete sequence. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param Timeout: Timeout value in millisecond. + * @param Timeout Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) @@ -654,13 +652,13 @@ /** * @brief Poll for conversion event - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param EventType: the ADC event type. + * @param EventType the ADC event type. * This parameter can be one of the following values: * @arg ADC_AWD_EVENT: ADC Analog watch Dog event. * @arg ADC_OVR_EVENT: ADC Overrun event. - * @param Timeout: Timeout value in millisecond. + * @param Timeout Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout) @@ -721,7 +719,7 @@ /** * @brief Enables the interrupt and starts ADC conversion of regular channels. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval HAL status. */ @@ -824,7 +822,7 @@ * * @note Caution: This function will stop also injected channels. * - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval HAL status. */ @@ -861,7 +859,7 @@ /** * @brief Handles ADC interrupt request - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ @@ -1004,10 +1002,10 @@ /** * @brief Enables ADC DMA request after last transfer (Single-ADC mode) and enables ADC peripheral - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param pData: The destination Buffer address. - * @param Length: The length of data to be transferred from ADC peripheral to memory. + * @param pData The destination Buffer address. + * @param Length The length of data to be transferred from ADC peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) @@ -1125,7 +1123,7 @@ /** * @brief Disables ADC DMA (Single-ADC mode) and disables ADC peripheral - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval HAL status */ @@ -1171,7 +1169,7 @@ /** * @brief Gets the converted value from data register of regular channel. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval Converted value */ @@ -1183,7 +1181,7 @@ /** * @brief Regular conversion complete callback in non blocking mode - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ @@ -1198,7 +1196,7 @@ /** * @brief Regular conversion half DMA transfer callback in non blocking mode - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ @@ -1213,7 +1211,7 @@ /** * @brief Analog watchdog callback in non blocking mode - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ @@ -1234,7 +1232,7 @@ * - If needed, restart a new ADC conversion using function * "HAL_ADC_Start_DMA()" * (this function is also clearing overrun flag) - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ @@ -1271,9 +1269,9 @@ /** * @brief Configures for the selected ADC regular channel its corresponding * rank in the sequencer and its sample time. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param sConfig: ADC configuration structure. + * @param sConfig ADC configuration structure. * @retval HAL status */ HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig) @@ -1384,9 +1382,9 @@ * Considering that registers write delay may happen due to * bus activity, this might cause an uncertainty on the * effective timing of the new programmed threshold values. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param AnalogWDGConfig : pointer to an ADC_AnalogWDGConfTypeDef structure + * @param AnalogWDGConfig pointer to an ADC_AnalogWDGConfTypeDef structure * that contains the configuration information of ADC analog watchdog. * @retval HAL status */ @@ -1468,7 +1466,7 @@ /** * @brief return the ADC state - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval HAL state */ @@ -1480,7 +1478,7 @@ /** * @brief Return the ADC error code - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval ADC Error Code */ @@ -1506,7 +1504,7 @@ /** * @brief Initializes the ADCx peripheral according to the specified parameters * in the ADC_InitStruct without initializing the ADC MSP. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ @@ -1587,7 +1585,7 @@ /** * @brief DMA transfer complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1640,7 +1638,7 @@ /** * @brief DMA half transfer complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1653,7 +1651,7 @@ /** * @brief DMA error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_adc.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_adc.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_adc.h * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief Header file of ADC HAL extension module. ****************************************************************************** * @attention @@ -492,60 +490,60 @@ */ /** @brief Reset ADC handle state - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval None */ #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET) /** * @brief Enable the ADC peripheral. - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval None */ #define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON) /** * @brief Disable the ADC peripheral. - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval None */ #define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON) /** * @brief Enable the ADC end of conversion interrupt. - * @param __HANDLE__: specifies the ADC Handle. - * @param __INTERRUPT__: ADC Interrupt. + * @param __HANDLE__ specifies the ADC Handle. + * @param __INTERRUPT__ ADC Interrupt. * @retval None */ #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__)) /** * @brief Disable the ADC end of conversion interrupt. - * @param __HANDLE__: specifies the ADC Handle. - * @param __INTERRUPT__: ADC interrupt. + * @param __HANDLE__ specifies the ADC Handle. + * @param __INTERRUPT__ ADC interrupt. * @retval None */ #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__)) /** @brief Check if the specified ADC interrupt source is enabled or disabled. - * @param __HANDLE__: specifies the ADC Handle. - * @param __INTERRUPT__: specifies the ADC interrupt source to check. + * @param __HANDLE__ specifies the ADC Handle. + * @param __INTERRUPT__ specifies the ADC interrupt source to check. * @retval The new state of __IT__ (TRUE or FALSE). */ #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) /** * @brief Clear the ADC's pending flags. - * @param __HANDLE__: specifies the ADC Handle. - * @param __FLAG__: ADC flag. + * @param __HANDLE__ specifies the ADC Handle. + * @param __FLAG__ ADC flag. * @retval None */ #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__)) /** * @brief Get the selected ADC's flag status. - * @param __HANDLE__: specifies the ADC Handle. - * @param __FLAG__: ADC flag. + * @param __HANDLE__ specifies the ADC Handle. + * @param __FLAG__ ADC flag. * @retval None */ #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) @@ -653,7 +651,7 @@ /** * @brief Verification of ADC state: enabled or disabled - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval SET (ADC enabled) or RESET (ADC disabled) */ #define ADC_IS_ENABLE(__HANDLE__) \ @@ -663,7 +661,7 @@ /** * @brief Test if conversion trigger of regular group is software start * or external trigger. - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval SET (software start) or RESET (external trigger) */ #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \ @@ -672,7 +670,7 @@ /** * @brief Test if conversion trigger of injected group is software start * or external trigger. - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval SET (software start) or RESET (external trigger) */ #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \ @@ -689,7 +687,7 @@ /** * @brief Clear ADC error code (set it to error code: "no error") - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval None */ #define ADC_CLEAR_ERRORCODE(__HANDLE__) \ @@ -797,89 +795,89 @@ /** * @brief Set ADC Regular channel sequence length. - * @param _NbrOfConversion_: Regular channel sequence length. + * @param _NbrOfConversion_ Regular channel sequence length. * @retval None */ #define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << 20) /** * @brief Set the ADC's sample time for channel numbers between 10 and 18. - * @param _SAMPLETIME_: Sample time parameter. - * @param _CHANNELNB_: Channel number. + * @param _SAMPLETIME_ Sample time parameter. + * @param _CHANNELNB_ Channel number. * @retval None */ #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10))) /** * @brief Set the ADC's sample time for channel numbers between 0 and 9. - * @param _SAMPLETIME_: Sample time parameter. - * @param _CHANNELNB_: Channel number. + * @param _SAMPLETIME_ Sample time parameter. + * @param _CHANNELNB_ Channel number. * @retval None */ #define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((uint32_t)((uint16_t)(_CHANNELNB_))))) /** * @brief Set the selected regular channel rank for rank between 1 and 6. - * @param _CHANNELNB_: Channel number. - * @param _RANKNB_: Rank number. + * @param _CHANNELNB_ Channel number. + * @param _RANKNB_ Rank number. * @retval None */ #define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 1))) /** * @brief Set the selected regular channel rank for rank between 7 and 12. - * @param _CHANNELNB_: Channel number. - * @param _RANKNB_: Rank number. + * @param _CHANNELNB_ Channel number. + * @param _RANKNB_ Rank number. * @retval None */ #define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 7))) /** * @brief Set the selected regular channel rank for rank between 13 and 16. - * @param _CHANNELNB_: Channel number. - * @param _RANKNB_: Rank number. + * @param _CHANNELNB_ Channel number. + * @param _RANKNB_ Rank number. * @retval None */ #define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 13))) /** * @brief Enable ADC continuous conversion mode. - * @param _CONTINUOUS_MODE_: Continuous mode. + * @param _CONTINUOUS_MODE_ Continuous mode. * @retval None */ #define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1) /** * @brief Configures the number of discontinuous conversions for the regular group channels. - * @param _NBR_DISCONTINUOUSCONV_: Number of discontinuous conversions. + * @param _NBR_DISCONTINUOUSCONV_ Number of discontinuous conversions. * @retval None */ -#define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1) << POSITION_VAL(ADC_CR1_DISCNUM)) +#define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1) << ADC_CR1_DISCNUM_Pos) /** * @brief Enable ADC scan mode. - * @param _SCANCONV_MODE_: Scan conversion mode. + * @param _SCANCONV_MODE_ Scan conversion mode. * @retval None */ #define ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8) /** * @brief Enable the ADC end of conversion selection. - * @param _EOCSelection_MODE_: End of conversion selection mode. + * @param _EOCSelection_MODE_ End of conversion selection mode. * @retval None */ #define ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10) /** * @brief Enable the ADC DMA continuous request. - * @param _DMAContReq_MODE_: DMA continuous request mode. + * @param _DMAContReq_MODE_ DMA continuous request mode. * @retval None */ #define ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9) /** * @brief Return resolution bits in CR1 register. - * @param __HANDLE__: ADC handle + * @param __HANDLE__ ADC handle * @retval None */ #define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES)
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_adc_ex.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_adc_ex.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_adc_ex.c * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief This file provides firmware functions to manage the following * functionalities of the ADC extension peripheral: * + Extended features functions @@ -170,7 +168,7 @@ /** * @brief Enables the selected ADC software start conversion of the injected channels. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval HAL status */ @@ -258,7 +256,7 @@ /** * @brief Enables the interrupt and starts ADC conversion of injected channels. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * * @retval HAL status. @@ -357,7 +355,7 @@ * @note If injected group mode auto-injection is enabled, * function HAL_ADC_Stop must be used. * @note In case of auto-injection mode, HAL_ADC_Stop must be used. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval None */ HAL_StatusTypeDef HAL_ADCEx_InjectedStop(ADC_HandleTypeDef* hadc) @@ -409,9 +407,9 @@ /** * @brief Poll for injected conversion complete - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param Timeout: Timeout value in millisecond. + * @param Timeout Timeout value in millisecond. * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_InjectedPollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout) @@ -478,7 +476,7 @@ * injected and regular groups, and disable the ADC. * @note If injected group mode auto-injection is enabled, * function HAL_ADC_Stop must be used. - * @param hadc: ADC handle + * @param hadc ADC handle * @retval None */ HAL_StatusTypeDef HAL_ADCEx_InjectedStop_IT(ADC_HandleTypeDef* hadc) @@ -533,9 +531,9 @@ /** * @brief Gets the converted value from data register of injected channel. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param InjectedRank: the ADC injected rank. + * @param InjectedRank the ADC injected rank. * This parameter can be one of the following values: * @arg ADC_INJECTED_RANK_1: Injected Channel1 selected * @arg ADC_INJECTED_RANK_2: Injected Channel2 selected @@ -588,10 +586,10 @@ * * @note Caution: This function must be used only with the ADC master. * - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param pData: Pointer to buffer in which transferred from ADC peripheral to memory will be stored. - * @param Length: The length of data to be transferred from ADC peripheral to memory. + * @param pData Pointer to buffer in which transferred from ADC peripheral to memory will be stored. + * @param Length The length of data to be transferred from ADC peripheral to memory. * @retval HAL status */ HAL_StatusTypeDef HAL_ADCEx_MultiModeStart_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length) @@ -703,7 +701,7 @@ /** * @brief Disables ADC DMA (multi-ADC mode) and disables ADC peripheral - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval HAL status */ @@ -750,7 +748,7 @@ /** * @brief Returns the last ADC1, ADC2 and ADC3 regular conversions results * data in the selected multi mode. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval The converted data value. */ @@ -762,7 +760,7 @@ /** * @brief Injected conversion complete callback in non blocking mode - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. * @retval None */ @@ -778,9 +776,9 @@ /** * @brief Configures for the selected ADC injected channel its corresponding * rank in the sequencer and its sample time. - * @param hadc: pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param sConfigInjected: ADC configuration structure for injected channel. + * @param sConfigInjected ADC configuration structure for injected channel. * @retval None */ HAL_StatusTypeDef HAL_ADCEx_InjectedConfigChannel(ADC_HandleTypeDef* hadc, ADC_InjectionConfTypeDef* sConfigInjected) @@ -933,9 +931,9 @@ /** * @brief Configures the ADC multi-mode - * @param hadc : pointer to a ADC_HandleTypeDef structure that contains + * @param hadc pointer to a ADC_HandleTypeDef structure that contains * the configuration information for the specified ADC. - * @param multimode : pointer to an ADC_MultiModeTypeDef structure that contains + * @param multimode pointer to an ADC_MultiModeTypeDef structure that contains * the configuration information for multimode. * @retval HAL status */ @@ -974,7 +972,7 @@ /** * @brief DMA transfer complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1027,7 +1025,7 @@ /** * @brief DMA half transfer complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1040,7 +1038,7 @@ /** * @brief DMA error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_adc_ex.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_adc_ex.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_adc.h * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief Header file of ADC HAL module. ****************************************************************************** * @attention @@ -339,9 +337,9 @@ /** * @brief Set the selected injected Channel rank. - * @param _CHANNELNB_: Channel number. - * @param _RANKNB_: Rank number. - * @param _JSQR_JL_: Sequence length. + * @param _CHANNELNB_ Channel number. + * @param _RANKNB_ Rank number. + * @param _JSQR_JL_ Sequence length. * @retval None */ #define ADC_JSQR(_CHANNELNB_, _RANKNB_,_JSQR_JL_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * (uint8_t)(((_RANKNB_) + 3) - (_JSQR_JL_))))
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_can.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_can.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,79 +2,131 @@
******************************************************************************
* @file stm32f7xx_hal_can.c
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief CAN HAL module driver.
- * This file provides firmware functions to manage the following
+ * This file provides firmware functions to manage the following
* functionalities of the Controller Area Network (CAN) peripheral:
- * + Initialization and de-initialization functions
- * + IO operation functions
- * + Peripheral Control functions
+ * + Initialization and de-initialization functions
+ * + Configuration functions
+ * + Control functions
+ * + Interrupts management
+ * + Callbacks functions
* + Peripheral State and Error functions
*
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
- [..]
- (#) Enable the CAN controller interface clock using
- __HAL_RCC_CAN1_CLK_ENABLE() for CAN1, __HAL_RCC_CAN2_CLK_ENABLE() for CAN2
- and __HAL_RCC_CAN3_CLK_ENABLE() for CAN3
- -@- In case you are using CAN2 only, you have to enable the CAN1 clock.
-
- (#) CAN pins configuration
- (++) Enable the clock for the CAN GPIOs using the following function:
- __HAL_RCC_GPIOx_CLK_ENABLE()
- (++) Connect and configure the involved CAN pins to AF9 using the
- following function HAL_GPIO_Init()
-
- (#) Initialize and configure the CAN using HAL_CAN_Init() function.
-
- (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function.
+ [..]
+ (#) Initialize the CAN low level resources by implementing the
+ HAL_CAN_MspInit():
+ (++) Enable the CAN interface clock using __HAL_RCC_CANx_CLK_ENABLE()
+ (++) Configure CAN pins
+ (+++) Enable the clock for the CAN GPIOs
+ (+++) Configure CAN pins as alternate function open-drain
+ (++) In case of using interrupts (e.g. HAL_CAN_ActivateNotification())
+ (+++) Configure the CAN interrupt priority using
+ HAL_NVIC_SetPriority()
+ (+++) Enable the CAN IRQ handler using HAL_NVIC_EnableIRQ()
+ (+++) In CAN IRQ handler, call HAL_CAN_IRQHandler()
+
+ (#) Initialize the CAN peripheral using HAL_CAN_Init() function. This
+ function resorts to HAL_CAN_MspInit() for low-level initialization.
+
+ (#) Configure the reception filters using the following configuration
+ functions:
+ (++) HAL_CAN_ConfigFilter()
+
+ (#) Start the CAN module using HAL_CAN_Start() function. At this level
+ the node is active on the bus: it receive messages, and can send
+ messages.
- (#) Or transmit the desired CAN frame using HAL_CAN_Transmit_IT() function.
-
- (#) Receive a CAN frame using HAL_CAN_Receive() function.
+ (#) To manage messages transmission, the following Tx control functions
+ can be used:
+ (++) HAL_CAN_AddTxMessage() to request transmission of a new
+ message.
+ (++) HAL_CAN_AbortTxRequest() to abort transmission of a pending
+ message.
+ (++) HAL_CAN_GetTxMailboxesFreeLevel() to get the number of free Tx
+ mailboxes.
+ (++) HAL_CAN_IsTxMessagePending() to check if a message is pending
+ in a Tx mailbox.
+ (++) HAL_CAN_GetTxTimestamp() to get the timestamp of Tx message
+ sent, if time triggered communication mode is enabled.
- (#) Or receive a CAN frame using HAL_CAN_Receive_IT() function.
+ (#) When a message is received into the CAN Rx FIFOs, it can be retrieved
+ using the HAL_CAN_GetRxMessage() function. The function
+ HAL_CAN_GetRxFifoFillLevel() allows to know how many Rx message are
+ stored in the Rx Fifo.
+
+ (#) Calling the HAL_CAN_Stop() function stops the CAN module.
+
+ (#) The deinitialization is achieved with HAL_CAN_DeInit() function.
+
+
+ *** Polling mode operation ***
+ ==============================
+ [..]
+ (#) Reception:
+ (++) Monitor reception of message using HAL_CAN_GetRxFifoFillLevel()
+ until at least one message is received.
+ (++) Then get the message using HAL_CAN_GetRxMessage().
- *** Polling mode IO operation ***
- =================================
- [..]
- (+) Start the CAN peripheral transmission and wait the end of this operation
- using HAL_CAN_Transmit(), at this stage user can specify the value of timeout
- according to his end application
- (+) Start the CAN peripheral reception and wait the end of this operation
- using HAL_CAN_Receive(), at this stage user can specify the value of timeout
- according to his end application
-
- *** Interrupt mode IO operation ***
- ===================================
- [..]
- (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT()
- (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT()
- (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine
- (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can
- add his own code by customization of function pointer HAL_CAN_TxCpltCallback
- (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can
- add his own code by customization of function pointer HAL_CAN_ErrorCallback
-
- *** CAN HAL driver macros list ***
- =============================================
- [..]
- Below the list of most used macros in CAN HAL driver.
-
- (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts
- (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts
- (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled
- (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags
- (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status
-
- [..]
- (@) You can refer to the CAN HAL driver header file for more useful macros
-
+ (#) Transmission:
+ (++) Monitor the Tx mailboxes availability until at least one Tx
+ mailbox is free, using HAL_CAN_GetTxMailboxesFreeLevel().
+ (++) Then request transmission of a message using
+ HAL_CAN_AddTxMessage().
+
+
+ *** Interrupt mode operation ***
+ ================================
+ [..]
+ (#) Notifications are activated using HAL_CAN_ActivateNotification()
+ function. Then, the process can be controlled through the
+ available user callbacks: HAL_CAN_xxxCallback(), using same APIs
+ HAL_CAN_GetRxMessage() and HAL_CAN_AddTxMessage().
+
+ (#) Notifications can be deactivated using
+ HAL_CAN_DeactivateNotification() function.
+
+ (#) Special care should be taken for CAN_IT_RX_FIFO0_MSG_PENDING and
+ CAN_IT_RX_FIFO1_MSG_PENDING notifications. These notifications trig
+ the callbacks HAL_CAN_RxFIFO0MsgPendingCallback() and
+ HAL_CAN_RxFIFO1MsgPendingCallback(). User has two possible options
+ here.
+ (++) Directly get the Rx message in the callback, using
+ HAL_CAN_GetRxMessage().
+ (++) Or deactivate the notification in the callback without
+ getting the Rx message. The Rx message can then be got later
+ using HAL_CAN_GetRxMessage(). Once the Rx message have been
+ read, the notification can be activated again.
+
+
+ *** Sleep mode ***
+ ==================
+ [..]
+ (#) The CAN peripheral can be put in sleep mode (low power), using
+ HAL_CAN_RequestSleep(). The sleep mode will be entered as soon as the
+ current CAN activity (transmission or reception of a CAN frame) will
+ be completed.
+
+ (#) A notification can be activated to be informed when the sleep mode
+ will be entered.
+
+ (#) It can be checked if the sleep mode is entered using
+ HAL_CAN_IsSleepActive().
+ Note that the CAN state (accessible from the API HAL_CAN_GetState())
+ is HAL_CAN_STATE_SLEEP_PENDING as soon as the sleep mode request is
+ submitted (the sleep mode is not yet entered), and become
+ HAL_CAN_STATE_SLEEP_ACTIVE when the sleep mode is effective.
+
+ (#) The wake-up from sleep mode can be trigged by two ways:
+ (++) Using HAL_CAN_WakeUp(). When returning from this function,
+ the sleep mode is exited (if return status is HAL_OK).
+ (++) When a start of Rx CAN frame is detected by the CAN peripheral,
+ if automatic wake up mode is enabled.
+
@endverbatim
-
******************************************************************************
* @attention
*
@@ -112,579 +164,622 @@
* @{
*/
+#if defined(CAN1)
+
/** @defgroup CAN CAN
* @brief CAN driver modules
* @{
- */
-
-#ifdef HAL_CAN_MODULE_ENABLED
+ */
+
+#ifdef HAL_CAN_MODULE_ENABLED
-
+#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
+ #error "The CAN driver cannot be used with its legacy, Please enable only one CAN module at once"
+#endif
+
/* Private typedef -----------------------------------------------------------*/
/* Private define ------------------------------------------------------------*/
-/** @addtogroup CAN_Private_Constants
+/** @defgroup CAN_Private_Constants CAN Private Constants
* @{
*/
-#define CAN_TIMEOUT_VALUE 10
+#define CAN_TIMEOUT_VALUE 10U
/**
* @}
*/
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
-/** @addtogroup CAN_Private_Functions
- * @{
- */
-static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber);
-static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan);
-/**
- * @}
- */
+/* Exported functions --------------------------------------------------------*/
-/* Exported functions --------------------------------------------------------*/
/** @defgroup CAN_Exported_Functions CAN Exported Functions
* @{
*/
-/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
+/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
*
-@verbatim
+@verbatim
==============================================================================
##### Initialization and de-initialization functions #####
==============================================================================
[..] This section provides functions allowing to:
- (+) Initialize and configure the CAN.
- (+) De-initialize the CAN.
-
+ (+) HAL_CAN_Init : Initialize and configure the CAN.
+ (+) HAL_CAN_DeInit : De-initialize the CAN.
+ (+) HAL_CAN_MspInit : Initialize the CAN MSP.
+ (+) HAL_CAN_MspDeInit : DeInitialize the CAN MSP.
+
@endverbatim
* @{
*/
-
+
/**
* @brief Initializes the CAN peripheral according to the specified
* parameters in the CAN_InitStruct.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
+HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan)
{
- uint32_t InitStatus = CAN_INITSTATUS_FAILED;
- uint32_t tickstart = 0;
-
+ uint32_t tickstart = 0U;
+
/* Check CAN handle */
- if(hcan == NULL)
+ if (hcan == NULL)
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
-
+
/* Check the parameters */
assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
- assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM));
- assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM));
- assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM));
- assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART));
- assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM));
- assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TimeTriggeredMode));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoBusOff));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoWakeUp));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AutoRetransmission));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ReceiveFifoLocked));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TransmitFifoPriority));
assert_param(IS_CAN_MODE(hcan->Init.Mode));
- assert_param(IS_CAN_SJW(hcan->Init.SJW));
- assert_param(IS_CAN_BS1(hcan->Init.BS1));
- assert_param(IS_CAN_BS2(hcan->Init.BS2));
+ assert_param(IS_CAN_SJW(hcan->Init.SyncJumpWidth));
+ assert_param(IS_CAN_BS1(hcan->Init.TimeSeg1));
+ assert_param(IS_CAN_BS2(hcan->Init.TimeSeg2));
assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));
-
- if(hcan->State == HAL_CAN_STATE_RESET)
+ if (hcan->State == HAL_CAN_STATE_RESET)
{
- /* Allocate lock resource and initialize it */
- hcan->Lock = HAL_UNLOCKED;
- /* Init the low level hardware */
+ /* Init the low level hardware: CLOCK, NVIC */
HAL_CAN_MspInit(hcan);
}
-
- /* Initialize the CAN state*/
- hcan->State = HAL_CAN_STATE_BUSY;
-
+
/* Exit from sleep mode */
- hcan->Instance->MCR &= (~(uint32_t)CAN_MCR_SLEEP);
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
- /* Request initialisation */
- hcan->Instance->MCR |= CAN_MCR_INRQ ;
-
/* Get tick */
tickstart = HAL_GetTick();
- /* Wait the acknowledge */
- while((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
+ /* Check Sleep mode leave acknowledge */
+ while ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET)
{
- if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE)
+ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
{
- hcan->State= HAL_CAN_STATE_TIMEOUT;
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
- return HAL_TIMEOUT;
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_ERROR;
+
+ return HAL_ERROR;
}
}
- /* Check acknowledge */
- if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
- {
- /* Set the time triggered communication mode */
- if (hcan->Init.TTCM == ENABLE)
- {
- hcan->Instance->MCR |= CAN_MCR_TTCM;
- }
- else
- {
- hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TTCM;
- }
-
- /* Set the automatic bus-off management */
- if (hcan->Init.ABOM == ENABLE)
- {
- hcan->Instance->MCR |= CAN_MCR_ABOM;
- }
- else
- {
- hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_ABOM;
- }
+ /* Request initialisation */
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
- /* Set the automatic wake-up mode */
- if (hcan->Init.AWUM == ENABLE)
- {
- hcan->Instance->MCR |= CAN_MCR_AWUM;
- }
- else
- {
- hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_AWUM;
- }
+ /* Get tick */
+ tickstart = HAL_GetTick();
- /* Set the no automatic retransmission */
- if (hcan->Init.NART == ENABLE)
- {
- hcan->Instance->MCR |= CAN_MCR_NART;
- }
- else
- {
- hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_NART;
- }
-
- /* Set the receive FIFO locked mode */
- if (hcan->Init.RFLM == ENABLE)
+ /* Wait initialisation acknowledge */
+ while ((hcan->Instance->MSR & CAN_MSR_INAK) == RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
{
- hcan->Instance->MCR |= CAN_MCR_RFLM;
- }
- else
- {
- hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_RFLM;
- }
-
- /* Set the transmit FIFO priority */
- if (hcan->Init.TXFP == ENABLE)
- {
- hcan->Instance->MCR |= CAN_MCR_TXFP;
- }
- else
- {
- hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TXFP;
- }
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
- /* Set the bit timing register */
- hcan->Instance->BTR = (uint32_t)((uint32_t)hcan->Init.Mode) | \
- ((uint32_t)hcan->Init.SJW) | \
- ((uint32_t)hcan->Init.BS1) | \
- ((uint32_t)hcan->Init.BS2) | \
- ((uint32_t)hcan->Init.Prescaler - 1);
-
- /* Request leave initialisation */
- hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ;
-
- /* Get tick */
- tickstart = HAL_GetTick();
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_ERROR;
- /* Wait the acknowledge */
- while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
- {
- if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE)
- {
- hcan->State= HAL_CAN_STATE_TIMEOUT;
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
- return HAL_TIMEOUT;
- }
- }
-
- /* Check acknowledged */
- if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
- {
- InitStatus = CAN_INITSTATUS_SUCCESS;
+ return HAL_ERROR;
}
}
-
- if(InitStatus == CAN_INITSTATUS_SUCCESS)
+
+ /* Set the time triggered communication mode */
+ if (hcan->Init.TimeTriggeredMode == ENABLE)
+ {
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
+ }
+ else
{
- /* Set CAN error code to none */
- hcan->ErrorCode = HAL_CAN_ERROR_NONE;
-
- /* Initialize the CAN state */
- hcan->State = HAL_CAN_STATE_READY;
-
- /* Return function status */
- return HAL_OK;
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TTCM);
+ }
+
+ /* Set the automatic bus-off management */
+ if (hcan->Init.AutoBusOff == ENABLE)
+ {
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
}
else
{
- /* Initialize the CAN state */
- hcan->State = HAL_CAN_STATE_ERROR;
-
- /* Return function status */
- return HAL_ERROR;
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_ABOM);
}
-}
-/**
- * @brief Configures the CAN reception filter according to the specified
- * parameters in the CAN_FilterInitStruct.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @param sFilterConfig: pointer to a CAN_FilterConfTypeDef structure that
- * contains the filter configuration information.
- * @retval None
- */
-HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig)
-{
- uint32_t filternbrbitpos = 0;
- CAN_TypeDef *can_ip;
-
- /* Check the parameters */
- assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber));
- assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));
- assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));
- assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));
- assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation));
- assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber));
-
- filternbrbitpos = ((uint32_t)1) << sFilterConfig->FilterNumber;
-#if defined (CAN3)
- /* Check the CAN instance */
- if(hcan->Instance == CAN3)
- {
- can_ip = CAN3;
+ /* Set the automatic wake-up mode */
+ if (hcan->Init.AutoWakeUp == ENABLE)
+ {
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
+ }
+ else
+ {
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_AWUM);
+ }
+
+ /* Set the automatic retransmission */
+ if (hcan->Init.AutoRetransmission == ENABLE)
+ {
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_NART);
}
else
{
- can_ip = CAN1;
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_NART);
}
-#else
- can_ip = CAN1;
-#endif
-
- /* Initialisation mode for the filter */
- can_ip->FMR |= (uint32_t)CAN_FMR_FINIT;
-
-#if defined (CAN2)
- /* Select the start slave bank */
- can_ip->FMR &= ~((uint32_t)CAN_FMR_CAN2SB);
- can_ip->FMR |= (uint32_t)(sFilterConfig->BankNumber << 8);
-#endif
-
- /* Filter Deactivation */
- can_ip->FA1R &= ~(uint32_t)filternbrbitpos;
- /* Filter Scale */
- if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
+ /* Set the receive FIFO locked mode */
+ if (hcan->Init.ReceiveFifoLocked == ENABLE)
{
- /* 16-bit scale for the filter */
- can_ip->FS1R &= ~(uint32_t)filternbrbitpos;
-
- /* First 16-bit identifier and First 16-bit mask */
- /* Or First 16-bit identifier and Second 16-bit identifier */
- can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
- ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16) |
- (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow);
-
- /* Second 16-bit identifier and Second 16-bit mask */
- /* Or Third 16-bit identifier and Fourth 16-bit identifier */
- can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
- ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) |
- (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh);
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
+ }
+ else
+ {
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_RFLM);
}
- if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
+ /* Set the transmit FIFO priority */
+ if (hcan->Init.TransmitFifoPriority == ENABLE)
{
- /* 32-bit scale for the filter */
- can_ip->FS1R |= filternbrbitpos;
-
- /* 32-bit identifier or First 32-bit identifier */
- can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
- ((0x0000FFFF & (uint32_t)sFilterConfig->FilterIdHigh) << 16) |
- (0x0000FFFF & (uint32_t)sFilterConfig->FilterIdLow);
-
- /* 32-bit mask or Second 32-bit identifier */
- can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
- ((0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16) |
- (0x0000FFFF & (uint32_t)sFilterConfig->FilterMaskIdLow);
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
+ }
+ else
+ {
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_TXFP);
}
- /* Filter Mode */
- if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
- {
- /*Id/Mask mode for the filter*/
- can_ip->FM1R &= ~(uint32_t)filternbrbitpos;
- }
- else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
- {
- /*Identifier list mode for the filter*/
- can_ip->FM1R |= (uint32_t)filternbrbitpos;
- }
+ /* Set the bit timing register */
+ WRITE_REG(hcan->Instance->BTR, (uint32_t)(hcan->Init.Mode |
+ hcan->Init.SyncJumpWidth |
+ hcan->Init.TimeSeg1 |
+ hcan->Init.TimeSeg2 |
+ (hcan->Init.Prescaler - 1U)));
- /* Filter FIFO assignment */
- if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
- {
- /* FIFO 0 assignation for the filter */
- can_ip->FFA1R &= ~(uint32_t)filternbrbitpos;
- }
+ /* Initialize the error code */
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;
- if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO1)
- {
- /* FIFO 1 assignation for the filter */
- can_ip->FFA1R |= (uint32_t)filternbrbitpos;
- }
-
- /* Filter activation */
- if (sFilterConfig->FilterActivation == ENABLE)
- {
- can_ip->FA1R |= filternbrbitpos;
- }
+ /* Initialize the CAN state */
+ hcan->State = HAL_CAN_STATE_READY;
- /* Leave the initialisation mode for the filter */
- can_ip->FMR &= ~((uint32_t)CAN_FMR_FINIT);
-
/* Return function status */
return HAL_OK;
}
/**
- * @brief Deinitializes the CANx peripheral registers to their default reset values.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
+ * @brief Deinitializes the CAN peripheral registers to their default
+ * reset values.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan)
+HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan)
{
/* Check CAN handle */
- if(hcan == NULL)
+ if (hcan == NULL)
{
- return HAL_ERROR;
+ return HAL_ERROR;
}
-
+
/* Check the parameters */
assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
-
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY;
-
- /* DeInit the low level hardware */
+
+ /* Stop the CAN module */
+ HAL_CAN_Stop(hcan);
+
+ /* DeInit the low level hardware: CLOCK, NVIC */
HAL_CAN_MspDeInit(hcan);
-
+
+ /* Reset the CAN peripheral */
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_RESET);
+
+ /* Reset the CAN ErrorCode */
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+
/* Change CAN state */
hcan->State = HAL_CAN_STATE_RESET;
- /* Release Lock */
- __HAL_UNLOCK(hcan);
-
/* Return function status */
return HAL_OK;
}
/**
* @brief Initializes the CAN MSP.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
* @retval None
*/
-__weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
+__weak void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcan);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_MspInit could be implemented in the user file
- */
+ */
}
/**
* @brief DeInitializes the CAN MSP.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
* @retval None
*/
-__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
+__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcan);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_MspDeInit could be implemented in the user file
- */
+ */
+}
+
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Exported_Functions_Group2 Configuration functions
+ * @brief Configuration functions.
+ *
+@verbatim
+ ==============================================================================
+ ##### Configuration functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) HAL_CAN_ConfigFilter : Configure the CAN reception filters
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Configures the CAN reception filter according to the specified
+ * parameters in the CAN_FilterInitStruct.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param sFilterConfig pointer to a CAN_FilterTypeDef structure that
+ * contains the filter configuration information.
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig)
+{
+ uint32_t filternbrbitpos = 0U;
+ CAN_TypeDef *can_ip = hcan->Instance;
+
+ if ((hcan->State == HAL_CAN_STATE_READY) ||
+ (hcan->State == HAL_CAN_STATE_LISTENING))
+ {
+ /* Check the parameters */
+ assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdHigh));
+ assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterIdLow));
+ assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdHigh));
+ assert_param(IS_CAN_FILTER_ID_HALFWORD(sFilterConfig->FilterMaskIdLow));
+ assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));
+ assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));
+ assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));
+ assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation));
+
+#if defined(CAN3)
+ /* Check the CAN instance */
+ if (hcan->Instance == CAN3)
+ {
+ /* CAN3 is single instance with 14 dedicated filters banks */
+
+ /* Check the parameters */
+ assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank));
+ }
+ else
+ {
+ /* CAN1 and CAN2 are dual instances with 28 common filters banks */
+ /* Select master instance to access the filter banks */
+ can_ip = CAN1;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->FilterBank));
+ assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->SlaveStartFilterBank));
+ }
+#elif defined(CAN2)
+ /* CAN1 and CAN2 are dual instances with 28 common filters banks */
+ /* Select master instance to access the filter banks */
+ can_ip = CAN1;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->FilterBank));
+ assert_param(IS_CAN_FILTER_BANK_DUAL(sFilterConfig->SlaveStartFilterBank));
+#else
+ /* CAN1 is single instance with 14 dedicated filters banks */
+
+ /* Check the parameters */
+ assert_param(IS_CAN_FILTER_BANK_SINGLE(sFilterConfig->FilterBank));
+#endif
+
+ /* Initialisation mode for the filter */
+ SET_BIT(can_ip->FMR, CAN_FMR_FINIT);
+
+#if defined(CAN3)
+ /* Check the CAN instance */
+ if (can_ip == CAN1)
+ {
+ /* Select the start filter number of CAN2 slave instance */
+ CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB);
+ SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos);
+ }
+
+#elif defined(CAN2)
+ /* Select the start filter number of CAN2 slave instance */
+ CLEAR_BIT(can_ip->FMR, CAN_FMR_CAN2SB);
+ SET_BIT(can_ip->FMR, sFilterConfig->SlaveStartFilterBank << CAN_FMR_CAN2SB_Pos);
+
+#endif
+ /* Convert filter number into bit position */
+ filternbrbitpos = (1U) << sFilterConfig->FilterBank;
+
+ /* Filter Deactivation */
+ CLEAR_BIT(can_ip->FA1R, filternbrbitpos);
+
+ /* Filter Scale */
+ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
+ {
+ /* 16-bit scale for the filter */
+ CLEAR_BIT(can_ip->FS1R, filternbrbitpos);
+
+ /* First 16-bit identifier and First 16-bit mask */
+ /* Or First 16-bit identifier and Second 16-bit identifier */
+ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
+
+ /* Second 16-bit identifier and Second 16-bit mask */
+ /* Or Third 16-bit identifier and Fourth 16-bit identifier */
+ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh);
+ }
+
+ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
+ {
+ /* 32-bit scale for the filter */
+ SET_BIT(can_ip->FS1R, filternbrbitpos);
+
+ /* 32-bit identifier or First 32-bit identifier */
+ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR1 =
+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
+
+ /* 32-bit mask or Second 32-bit identifier */
+ can_ip->sFilterRegister[sFilterConfig->FilterBank].FR2 =
+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow);
+ }
+
+ /* Filter Mode */
+ if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
+ {
+ /* Id/Mask mode for the filter*/
+ CLEAR_BIT(can_ip->FM1R, filternbrbitpos);
+ }
+ else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
+ {
+ /* Identifier list mode for the filter*/
+ SET_BIT(can_ip->FM1R, filternbrbitpos);
+ }
+
+ /* Filter FIFO assignment */
+ if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
+ {
+ /* FIFO 0 assignation for the filter */
+ CLEAR_BIT(can_ip->FFA1R, filternbrbitpos);
+ }
+ else
+ {
+ /* FIFO 1 assignation for the filter */
+ SET_BIT(can_ip->FFA1R, filternbrbitpos);
+ }
+
+ /* Filter activation */
+ if (sFilterConfig->FilterActivation == ENABLE)
+ {
+ SET_BIT(can_ip->FA1R, filternbrbitpos);
+ }
+
+ /* Leave the initialisation mode for the filter */
+ CLEAR_BIT(can_ip->FMR, CAN_FMR_FINIT);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
}
/**
* @}
*/
-/** @defgroup CAN_Exported_Functions_Group2 IO operation functions
- * @brief IO operation functions
+/** @defgroup CAN_Exported_Functions_Group3 Control functions
+ * @brief Control functions
*
-@verbatim
+@verbatim
==============================================================================
- ##### IO operation functions #####
+ ##### Control functions #####
==============================================================================
[..] This section provides functions allowing to:
- (+) Transmit a CAN frame message.
- (+) Receive a CAN frame message.
- (+) Enter CAN peripheral in sleep mode.
- (+) Wake up the CAN peripheral from sleep mode.
-
+ (+) HAL_CAN_Start : Start the CAN module
+ (+) HAL_CAN_Stop : Stop the CAN module
+ (+) HAL_CAN_RequestSleep : Request sleep mode entry.
+ (+) HAL_CAN_WakeUp : Wake up from sleep mode.
+ (+) HAL_CAN_IsSleepActive : Check is sleep mode is active.
+ (+) HAL_CAN_AddTxMessage : Add a message to the Tx mailboxes
+ and activate the corresponding
+ transmission request
+ (+) HAL_CAN_AbortTxRequest : Abort transmission request
+ (+) HAL_CAN_GetTxMailboxesFreeLevel : Return Tx mailboxes free level
+ (+) HAL_CAN_IsTxMessagePending : Check if a transmission request is
+ pending on the selected Tx mailbox
+ (+) HAL_CAN_GetRxMessage : Get a CAN frame from the Rx FIFO
+ (+) HAL_CAN_GetRxFifoFillLevel : Return Rx FIFO fill level
+
@endverbatim
* @{
*/
/**
- * @brief Initiates and transmits a CAN frame message.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @param Timeout: Specify Timeout value
+ * @brief Start the CAN module.
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
+HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan)
{
- uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
uint32_t tickstart = 0U;
- /* Check the parameters */
- assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
- assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
- assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
+ if (hcan->State == HAL_CAN_STATE_READY)
+ {
+ /* Change CAN peripheral state */
+ hcan->State = HAL_CAN_STATE_LISTENING;
- if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
- ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
- ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
- {
- /* Process locked */
- __HAL_LOCK(hcan);
-
- /* Change CAN state */
- switch(hcan->State)
- {
- case(HAL_CAN_STATE_BUSY_RX0):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
- break;
- case(HAL_CAN_STATE_BUSY_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
- break;
- default: /* HAL_CAN_STATE_READY */
- hcan->State = HAL_CAN_STATE_BUSY_TX;
- break;
- }
-
- /* Select one empty transmit mailbox */
- if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
- {
- transmitmailbox = CAN_TXMAILBOX_0;
- }
- else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
- {
- transmitmailbox = CAN_TXMAILBOX_1;
- }
- else
- {
- transmitmailbox = CAN_TXMAILBOX_2;
- }
+ /* Request leave initialisation */
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
- /* Set up the Id */
- hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
- if (hcan->pTxMsg->IDE == CAN_ID_STD)
- {
- assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
- hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21U) | \
- hcan->pTxMsg->RTR);
- }
- else
- {
- assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
- hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3U) | \
- hcan->pTxMsg->IDE | \
- hcan->pTxMsg->RTR);
- }
-
- /* Set up the DLC */
- hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
- hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U;
- hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
-
- /* Set up the data field */
- hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3U] << 24U) |
- ((uint32_t)hcan->pTxMsg->Data[2U] << 16U) |
- ((uint32_t)hcan->pTxMsg->Data[1U] << 8U) |
- ((uint32_t)hcan->pTxMsg->Data[0U]));
- hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7U] << 24U) |
- ((uint32_t)hcan->pTxMsg->Data[6U] << 16U) |
- ((uint32_t)hcan->pTxMsg->Data[5U] << 8U) |
- ((uint32_t)hcan->pTxMsg->Data[4U]));
- /* Request transmission */
- hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
-
/* Get tick */
tickstart = HAL_GetTick();
-
- /* Check End of transmission flag */
- while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox)))
+
+ /* Wait the acknowledge */
+ while ((hcan->Instance->MSR & CAN_MSR_INAK) != RESET)
{
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
{
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- hcan->State = HAL_CAN_STATE_TIMEOUT;
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
- __HAL_CAN_CANCEL_TRANSMIT(hcan, transmitmailbox);
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_ERROR;
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
- return HAL_TIMEOUT;
- }
+ return HAL_ERROR;
}
}
- /* Change CAN state */
- switch(hcan->State)
- {
- case(HAL_CAN_STATE_BUSY_TX_RX0):
- hcan->State = HAL_CAN_STATE_BUSY_RX0;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
- break;
- default: /* HAL_CAN_STATE_BUSY_TX */
- hcan->State = HAL_CAN_STATE_READY;
- break;
- }
+ /* Reset the CAN ErrorCode */
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
-
/* Return function status */
return HAL_OK;
}
else
{
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_ERROR;
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_READY;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Stop the CAN module and enable access to configuration registers.
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan)
+{
+ uint32_t tickstart = 0U;
+
+ if (hcan->State == HAL_CAN_STATE_LISTENING)
+ {
+ /* Request initialisation */
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_INRQ);
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait the acknowledge */
+ while ((hcan->Instance->MSR & CAN_MSR_INAK) == RESET)
+ {
+ /* Check for the Timeout */
+ if ((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_ERROR;
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Exit from sleep mode */
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
+
+ /* Change CAN peripheral state */
+ hcan->State = HAL_CAN_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_STARTED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Request the sleep mode (low power) entry.
+ * When returning from this function, Sleep mode will be entered
+ * as soon as the current CAN activity (transmission or reception
+ * of a CAN frame) has been completed.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan)
+{
+ if ((hcan->State == HAL_CAN_STATE_READY) ||
+ (hcan->State == HAL_CAN_STATE_LISTENING))
+ {
+ /* Request Sleep mode */
+ SET_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
/* Return function status */
return HAL_ERROR;
@@ -692,741 +787,1084 @@
}
/**
- * @brief Initiates and transmits a CAN frame message.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
+ * @brief Wake up from sleep mode.
+ * When returning with HAL_OK status from this function, Sleep mode
+ * is exited.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan)
+{
+ __IO uint32_t count = 0;
+ uint32_t timeout = 1000000U;
+
+ if ((hcan->State == HAL_CAN_STATE_READY) ||
+ (hcan->State == HAL_CAN_STATE_LISTENING))
+ {
+ /* Wake up request */
+ CLEAR_BIT(hcan->Instance->MCR, CAN_MCR_SLEEP);
+
+ /* Wait sleep mode is exited */
+ do
+ {
+ /* Check if timeout is reached */
+ if (++count > timeout)
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_TIMEOUT;
+
+ return HAL_ERROR;
+ }
+ }
+ while ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Check is sleep mode is active.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval Status
+ * - 0 : Sleep mode is not active.
+ * - 1 : Sleep mode is active.
+ */
+uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan)
+{
+ uint32_t status = 0U;
+
+ if ((hcan->State == HAL_CAN_STATE_READY) ||
+ (hcan->State == HAL_CAN_STATE_LISTENING))
+ {
+ /* Check Sleep mode */
+ if ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET)
+ {
+ status = 1U;
+ }
+ }
+
+ /* Return function status */
+ return status;
+}
+
+/**
+ * @brief Add a message to the first free Tx mailbox and activate the
+ * corresponding transmission request.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param pHeader pointer to a CAN_TxHeaderTypeDef structure.
+ * @param aData array containing the payload of the Tx frame.
+ * @param pTxMailbox pointer to a variable where the function will return
+ * the TxMailbox used to store the Tx message.
+ * This parameter can be a value of @arg CAN_Tx_Mailboxes.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
+HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox)
{
- uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
-
+ uint32_t transmitmailbox;
+
/* Check the parameters */
- assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
- assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
- assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
-
- if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
- ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
- ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
+ assert_param(IS_CAN_IDTYPE(pHeader->IDE));
+ assert_param(IS_CAN_RTR(pHeader->RTR));
+ assert_param(IS_CAN_DLC(pHeader->DLC));
+ if (pHeader->IDE == CAN_ID_STD)
+ {
+ assert_param(IS_CAN_STDID(pHeader->StdId));
+ }
+ else
{
- /* Process Locked */
- __HAL_LOCK(hcan);
+ assert_param(IS_CAN_EXTID(pHeader->ExtId));
+ }
+ assert_param(IS_FUNCTIONAL_STATE(pHeader->TransmitGlobalTime));
- /* Select one empty transmit mailbox */
- if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
+ if ((hcan->State == HAL_CAN_STATE_READY) ||
+ (hcan->State == HAL_CAN_STATE_LISTENING))
+ {
+ /* Check that all the Tx mailboxes are not full */
+ if (((hcan->Instance->TSR & CAN_TSR_TME0) != RESET) ||
+ ((hcan->Instance->TSR & CAN_TSR_TME1) != RESET) ||
+ ((hcan->Instance->TSR & CAN_TSR_TME2) != RESET))
{
- transmitmailbox = CAN_TXMAILBOX_0;
- }
- else if((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
- {
- transmitmailbox = CAN_TXMAILBOX_1;
- }
- else
- {
- transmitmailbox = CAN_TXMAILBOX_2;
- }
+ /* Select an empty transmit mailbox */
+ transmitmailbox = (hcan->Instance->TSR & CAN_TSR_CODE) >> CAN_TSR_CODE_Pos;
+
+ /* Store the Tx mailbox */
+ *pTxMailbox = 1U << transmitmailbox;
+
+ /* Set up the Id */
+ if (pHeader->IDE == CAN_ID_STD)
+ {
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->StdId << CAN_TI0R_STID_Pos) |
+ pHeader->RTR);
+ }
+ else
+ {
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR = ((pHeader->ExtId << CAN_TI0R_EXID_Pos) |
+ pHeader->IDE |
+ pHeader->RTR);
+ }
+
+ /* Set up the DLC */
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR = (pHeader->DLC);
- /* Set up the Id */
- hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
- if(hcan->pTxMsg->IDE == CAN_ID_STD)
- {
- assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
- hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21U) | \
- hcan->pTxMsg->RTR);
+ /* Set up the Transmit Global Time mode */
+ if (pHeader->TransmitGlobalTime == ENABLE)
+ {
+ SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TDTR, CAN_TDT0R_TGT);
+ }
+
+ /* Set up the data field */
+ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDHR,
+ ((uint32_t)aData[7] << CAN_TDH0R_DATA7_Pos) |
+ ((uint32_t)aData[6] << CAN_TDH0R_DATA6_Pos) |
+ ((uint32_t)aData[5] << CAN_TDH0R_DATA5_Pos) |
+ ((uint32_t)aData[4] << CAN_TDH0R_DATA4_Pos));
+ WRITE_REG(hcan->Instance->sTxMailBox[transmitmailbox].TDLR,
+ ((uint32_t)aData[3] << CAN_TDL0R_DATA3_Pos) |
+ ((uint32_t)aData[2] << CAN_TDL0R_DATA2_Pos) |
+ ((uint32_t)aData[1] << CAN_TDL0R_DATA1_Pos) |
+ ((uint32_t)aData[0] << CAN_TDL0R_DATA0_Pos));
+
+ /* Request transmission */
+ SET_BIT(hcan->Instance->sTxMailBox[transmitmailbox].TIR, CAN_TI0R_TXRQ);
+
+ /* Return function status */
+ return HAL_OK;
}
else
{
- assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
- hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3U) | \
- hcan->pTxMsg->IDE | \
- hcan->pTxMsg->RTR);
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
+
+ return HAL_ERROR;
}
-
- /* Set up the DLC */
- hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
- hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U;
- hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
+ }
+ else
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
- /* Set up the data field */
- hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3U] << 24U) |
- ((uint32_t)hcan->pTxMsg->Data[2U] << 16U) |
- ((uint32_t)hcan->pTxMsg->Data[1U] << 8U) |
- ((uint32_t)hcan->pTxMsg->Data[0U]));
- hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7U] << 24U) |
- ((uint32_t)hcan->pTxMsg->Data[6U] << 16U) |
- ((uint32_t)hcan->pTxMsg->Data[5U] << 8U) |
- ((uint32_t)hcan->pTxMsg->Data[4U]));
+/**
+ * @brief Abort transmission requests
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param TxMailboxes List of the Tx Mailboxes to abort.
+ * This parameter can be any combination of @arg CAN_Tx_Mailboxes.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes)
+{
+ /* Check function parameters */
+ assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes));
- /* Change CAN state */
- switch(hcan->State)
+ if ((hcan->State == HAL_CAN_STATE_READY) ||
+ (hcan->State == HAL_CAN_STATE_LISTENING))
+ {
+ /* Check Tx Mailbox 0 */
+ if ((TxMailboxes & CAN_TX_MAILBOX0) != RESET)
{
- case(HAL_CAN_STATE_BUSY_RX0):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
- break;
- case(HAL_CAN_STATE_BUSY_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
- break;
- default: /* HAL_CAN_STATE_READY */
- hcan->State = HAL_CAN_STATE_BUSY_TX;
- break;
+ /* Add cancellation request for Tx Mailbox 0 */
+ SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ0);
}
- /* Set CAN error code to none */
- hcan->ErrorCode = HAL_CAN_ERROR_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hcan);
-
- /* Request transmission */
- hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
+ /* Check Tx Mailbox 1 */
+ if ((TxMailboxes & CAN_TX_MAILBOX1) != RESET)
+ {
+ /* Add cancellation request for Tx Mailbox 1 */
+ SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ1);
+ }
- /* Enable Error warning, Error passive, Bus-off,
- Last error and Error Interrupts */
- __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
- CAN_IT_EPV |
- CAN_IT_BOF |
- CAN_IT_LEC |
- CAN_IT_ERR |
- CAN_IT_TME);
+ /* Check Tx Mailbox 2 */
+ if ((TxMailboxes & CAN_TX_MAILBOX2) != RESET)
+ {
+ /* Add cancellation request for Tx Mailbox 2 */
+ SET_BIT(hcan->Instance->TSR, CAN_TSR_ABRQ2);
+ }
+
+ /* Return function status */
+ return HAL_OK;
}
else
{
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_ERROR;
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
- /* Return function status */
return HAL_ERROR;
}
-
- return HAL_OK;
+}
+
+/**
+ * @brief Return Tx Mailboxes free level: number of free Tx Mailboxes.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval Number of free Tx Mailboxes.
+ */
+uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan)
+{
+ uint32_t freelevel = 0U;
+
+ if ((hcan->State == HAL_CAN_STATE_READY) ||
+ (hcan->State == HAL_CAN_STATE_LISTENING))
+ {
+ /* Check Tx Mailbox 0 status */
+ if ((hcan->Instance->TSR & CAN_TSR_TME0) != RESET)
+ {
+ freelevel++;
+ }
+
+ /* Check Tx Mailbox 1 status */
+ if ((hcan->Instance->TSR & CAN_TSR_TME1) != RESET)
+ {
+ freelevel++;
+ }
+
+ /* Check Tx Mailbox 2 status */
+ if ((hcan->Instance->TSR & CAN_TSR_TME2) != RESET)
+ {
+ freelevel++;
+ }
+ }
+
+ /* Return Tx Mailboxes free level */
+ return freelevel;
+}
+
+/**
+ * @brief Check if a transmission request is pending on the selected Tx
+ * Mailboxes.
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param TxMailboxes List of Tx Mailboxes to check.
+ * This parameter can be any combination of @arg CAN_Tx_Mailboxes.
+ * @retval Status
+ * - 0 : No pending transmission request on any selected Tx Mailboxes.
+ * - 1 : Pending transmission request on at least one of the selected
+ * Tx Mailbox.
+ */
+uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes)
+{
+ uint32_t status = 0U;
+
+ /* Check function parameters */
+ assert_param(IS_CAN_TX_MAILBOX_LIST(TxMailboxes));
+
+ if ((hcan->State == HAL_CAN_STATE_READY) ||
+ (hcan->State == HAL_CAN_STATE_LISTENING))
+ {
+ /* Check pending transmission request on the selected Tx Mailboxes */
+ if ((hcan->Instance->TSR & (TxMailboxes << CAN_TSR_TME0_Pos)) != (TxMailboxes << CAN_TSR_TME0_Pos))
+ {
+ status = 1U;
+ }
+ }
+
+ /* Return status */
+ return status;
+}
+
+/**
+ * @brief Return timestamp of Tx message sent, if time triggered communication
+ mode is enabled.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param TxMailbox Tx Mailbox where the timestamp of message sent will be
+ * read.
+ * This parameter can be one value of @arg CAN_Tx_Mailboxes.
+ * @retval Timestamp of message sent from Tx Mailbox.
+ */
+uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox)
+{
+ uint32_t timestamp = 0U;
+ uint32_t transmitmailbox;
+
+ /* Check function parameters */
+ assert_param(IS_CAN_TX_MAILBOX(TxMailbox));
+
+ if ((hcan->State == HAL_CAN_STATE_READY) ||
+ (hcan->State == HAL_CAN_STATE_LISTENING))
+ {
+ /* Select the Tx mailbox */
+ transmitmailbox = POSITION_VAL(TxMailbox);
+
+ /* Get timestamp */
+ timestamp = (hcan->Instance->sTxMailBox[transmitmailbox].TDTR & CAN_TDT0R_TIME) >> CAN_TDT0R_TIME_Pos;
+ }
+
+ /* Return the timestamp */
+ return timestamp;
}
/**
- * @brief Receives a correct CAN frame.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @param FIFONumber: FIFO Number value
- * @param Timeout: Specify Timeout value
+ * @brief Get an CAN frame from the Rx FIFO zone into the message RAM.
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param RxFifo Fifo number of the received message to be read.
+ * This parameter can be a value of @arg CAN_receive_FIFO_number.
+ * @param pHeader pointer to a CAN_RxHeaderTypeDef structure where the header
+ * of the Rx frame will be stored.
+ * @param aData array where the payload of the Rx frame will be stored.
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout)
+HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[])
{
- uint32_t tickstart = 0U;
- CanRxMsgTypeDef* pRxMsg = NULL;
-
- /* Check the parameters */
- assert_param(IS_CAN_FIFO(FIFONumber));
+ assert_param(IS_CAN_RX_FIFO(RxFifo));
- /* Check if CAN state is not busy for RX FIFO0 */
- if ((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \
- (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \
- (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
- (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
- {
- return HAL_BUSY;
- }
-
- /* Check if CAN state is not busy for RX FIFO1 */
- if ((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \
- (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \
- (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
- (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
- {
- return HAL_BUSY;
- }
-
- /* Process locked */
- __HAL_LOCK(hcan);
-
- /* Change CAN state */
- if (FIFONumber == CAN_FIFO0)
+ if ((hcan->State == HAL_CAN_STATE_READY) ||
+ (hcan->State == HAL_CAN_STATE_LISTENING))
{
- switch(hcan->State)
+ /* Check the Rx FIFO */
+ if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */
+ {
+ /* Check that the Rx FIFO 0 is not empty */
+ if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) == RESET)
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
+
+ return HAL_ERROR;
+ }
+ }
+ else if (RxFifo == CAN_RX_FIFO1) /* Rx element is assigned to Rx FIFO 1 */
+ {
+ /* Check that the Rx FIFO 1 is not empty */
+ if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) == RESET)
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_PARAM;
+
+ return HAL_ERROR;
+ }
+ }
+
+ /* Get the header */
+ pHeader->IDE = CAN_RI0R_IDE & hcan->Instance->sFIFOMailBox[RxFifo].RIR;
+ if (pHeader->IDE == CAN_ID_STD)
+ {
+ pHeader->StdId = (CAN_RI0R_STID & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_TI0R_STID_Pos;
+ }
+ else
{
- case(HAL_CAN_STATE_BUSY_TX):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
- break;
- case(HAL_CAN_STATE_BUSY_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
- break;
- default: /* HAL_CAN_STATE_READY */
- hcan->State = HAL_CAN_STATE_BUSY_RX0;
- break;
+ pHeader->ExtId = ((CAN_RI0R_EXID | CAN_RI0R_STID) & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_EXID_Pos;
}
+ pHeader->RTR = (CAN_RI0R_RTR & hcan->Instance->sFIFOMailBox[RxFifo].RIR) >> CAN_RI0R_RTR_Pos;
+ pHeader->DLC = (CAN_RDT0R_DLC & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_DLC_Pos;
+ pHeader->FilterMatchIndex = (CAN_RDT0R_FMI & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_FMI_Pos;
+ pHeader->Timestamp = (CAN_RDT0R_TIME & hcan->Instance->sFIFOMailBox[RxFifo].RDTR) >> CAN_RDT0R_TIME_Pos;
+
+ /* Get the data */
+ aData[0] = (CAN_RDL0R_DATA0 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA0_Pos;
+ aData[1] = (CAN_RDL0R_DATA1 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA1_Pos;
+ aData[2] = (CAN_RDL0R_DATA2 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA2_Pos;
+ aData[3] = (CAN_RDL0R_DATA3 & hcan->Instance->sFIFOMailBox[RxFifo].RDLR) >> CAN_RDL0R_DATA3_Pos;
+ aData[4] = (CAN_RDH0R_DATA4 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA4_Pos;
+ aData[5] = (CAN_RDH0R_DATA5 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA5_Pos;
+ aData[6] = (CAN_RDH0R_DATA6 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA6_Pos;
+ aData[7] = (CAN_RDH0R_DATA7 & hcan->Instance->sFIFOMailBox[RxFifo].RDHR) >> CAN_RDH0R_DATA7_Pos;
+
+ /* Release the FIFO */
+ if (RxFifo == CAN_RX_FIFO0) /* Rx element is assigned to Rx FIFO 0 */
+ {
+ /* Release RX FIFO 0 */
+ SET_BIT(hcan->Instance->RF0R, CAN_RF0R_RFOM0);
+ }
+ else if (RxFifo == CAN_RX_FIFO1) /* Rx element is assigned to Rx FIFO 1 */
+ {
+ /* Release RX FIFO 1 */
+ SET_BIT(hcan->Instance->RF1R, CAN_RF1R_RFOM1);
+ }
+
+ /* Return function status */
+ return HAL_OK;
}
- else /* FIFONumber == CAN_FIFO1 */
+ else
{
- switch(hcan->State)
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Return Rx FIFO fill level.
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param RxFifo Rx FIFO.
+ * This parameter can be a value of @arg CAN_receive_FIFO_number.
+ * @retval Number of messages available in Rx FIFO.
+ */
+uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo)
+{
+ uint32_t filllevel = 0U;
+
+ /* Check function parameters */
+ assert_param(IS_CAN_RX_FIFO(RxFifo));
+
+ if ((hcan->State == HAL_CAN_STATE_READY) ||
+ (hcan->State == HAL_CAN_STATE_LISTENING))
+ {
+ if (RxFifo == CAN_RX_FIFO0)
{
- case(HAL_CAN_STATE_BUSY_TX):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_RX0):
- hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX0):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
- break;
- default: /* HAL_CAN_STATE_READY */
- hcan->State = HAL_CAN_STATE_BUSY_RX1;
- break;
+ filllevel = hcan->Instance->RF0R & CAN_RF0R_FMP0;
+ }
+ else /* RxFifo == CAN_RX_FIFO1 */
+ {
+ filllevel = hcan->Instance->RF1R & CAN_RF1R_FMP1;
}
}
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Check pending message */
- while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0U)
+ /* Return Rx FIFO fill level */
+ return filllevel;
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Exported_Functions_Group4 Interrupts management
+ * @brief Interrupts management
+ *
+@verbatim
+ ==============================================================================
+ ##### Interrupts management #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) HAL_CAN_ActivateNotification : Enable interrupts
+ (+) HAL_CAN_DeactivateNotification : Disable interrupts
+ (+) HAL_CAN_IRQHandler : Handles CAN interrupt request
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enable interrupts.
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param ActiveITs indicates which interrupts will be enabled.
+ * This parameter can be any combination of @arg CAN_Interrupts.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs)
+{
+ /* Check function parameters */
+ assert_param(IS_CAN_IT(ActiveITs));
+
+ if ((hcan->State == HAL_CAN_STATE_READY) ||
+ (hcan->State == HAL_CAN_STATE_LISTENING))
+ {
+ /* Enable the selected interrupts */
+ __HAL_CAN_ENABLE_IT(hcan, ActiveITs);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Disable interrupts.
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param InactiveITs indicates which interrupts will be disabled.
+ * This parameter can be any combination of @arg CAN_Interrupts.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs)
+{
+ /* Check function parameters */
+ assert_param(IS_CAN_IT(InactiveITs));
+
+ if ((hcan->State == HAL_CAN_STATE_READY) ||
+ (hcan->State == HAL_CAN_STATE_LISTENING))
+ {
+ /* Disable the selected interrupts */
+ __HAL_CAN_DISABLE_IT(hcan, InactiveITs);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
{
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
+
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Handles CAN interrupt request
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan)
+{
+ uint32_t errorcode = HAL_CAN_ERROR_NONE;
+ uint32_t interrupts = READ_REG(hcan->Instance->IER);
+ uint32_t msrflags = READ_REG(hcan->Instance->MSR);
+ uint32_t tsrflags = READ_REG(hcan->Instance->TSR);
+ uint32_t rf0rflags = READ_REG(hcan->Instance->RF0R);
+ uint32_t rf1rflags = READ_REG(hcan->Instance->RF1R);
+ uint32_t esrflags = READ_REG(hcan->Instance->ESR);
+
+ /* Transmit Mailbox empty interrupt management *****************************/
+ if ((interrupts & CAN_IT_TX_MAILBOX_EMPTY) != RESET)
+ {
+ /* Transmit Mailbox 0 management *****************************************/
+ if ((tsrflags & CAN_TSR_RQCP0) != RESET)
{
- if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ /* Clear the Transmission Complete flag (and TXOK0,ALST0,TERR0 bits) */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP0);
+
+ if ((tsrflags & CAN_TSR_TXOK0) != RESET)
+ {
+ /* Transmission Mailbox 0 complete callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_TxMailbox0CompleteCallback(hcan);
+ }
+ else
{
- hcan->State = HAL_CAN_STATE_TIMEOUT;
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
- return HAL_TIMEOUT;
+ if ((tsrflags & CAN_TSR_ALST0) != RESET)
+ {
+ /* Update error code */
+ errorcode |= HAL_CAN_ERROR_TX_ALST0;
+ }
+ else if ((tsrflags & CAN_TSR_TERR0) != RESET)
+ {
+ /* Update error code */
+ errorcode |= HAL_CAN_ERROR_TX_TERR0;
+ }
+ else
+ {
+ /* Transmission Mailbox 0 abort callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_TxMailbox0AbortCallback(hcan);
+ }
+ }
+ }
+
+ /* Transmit Mailbox 1 management *****************************************/
+ if ((tsrflags & CAN_TSR_RQCP1) != RESET)
+ {
+ /* Clear the Transmission Complete flag (and TXOK1,ALST1,TERR1 bits) */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP1);
+
+ if ((tsrflags & CAN_TSR_TXOK1) != RESET)
+ {
+ /* Transmission Mailbox 1 complete callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_TxMailbox1CompleteCallback(hcan);
+ }
+ else
+ {
+ if ((tsrflags & CAN_TSR_ALST1) != RESET)
+ {
+ /* Update error code */
+ errorcode |= HAL_CAN_ERROR_TX_ALST1;
+ }
+ else if ((tsrflags & CAN_TSR_TERR1) != RESET)
+ {
+ /* Update error code */
+ errorcode |= HAL_CAN_ERROR_TX_TERR1;
+ }
+ else
+ {
+ /* Transmission Mailbox 1 abort callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_TxMailbox1AbortCallback(hcan);
+ }
+ }
+ }
+
+ /* Transmit Mailbox 2 management *****************************************/
+ if ((tsrflags & CAN_TSR_RQCP2) != RESET)
+ {
+ /* Clear the Transmission Complete flag (and TXOK2,ALST2,TERR2 bits) */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_RQCP2);
+
+ if ((tsrflags & CAN_TSR_TXOK2) != RESET)
+ {
+ /* Transmission Mailbox 2 complete callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_TxMailbox2CompleteCallback(hcan);
+ }
+ else
+ {
+ if ((tsrflags & CAN_TSR_ALST2) != RESET)
+ {
+ /* Update error code */
+ errorcode |= HAL_CAN_ERROR_TX_ALST2;
+ }
+ else if ((tsrflags & CAN_TSR_TERR2) != RESET)
+ {
+ /* Update error code */
+ errorcode |= HAL_CAN_ERROR_TX_TERR2;
+ }
+ else
+ {
+ /* Transmission Mailbox 2 abort callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_TxMailbox2AbortCallback(hcan);
+ }
}
}
}
- /* Set RxMsg pointer */
- if(FIFONumber == CAN_FIFO0)
+ /* Receive FIFO 0 overrun interrupt management *****************************/
+ if ((interrupts & CAN_IT_RX_FIFO0_OVERRUN) != RESET)
+ {
+ if ((rf0rflags & CAN_RF0R_FOVR0) != RESET)
+ {
+ /* Set CAN error code to Rx Fifo 0 overrun error */
+ errorcode |= HAL_CAN_ERROR_RX_FOV0;
+
+ /* Clear FIFO0 Overrun Flag */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0);
+ }
+ }
+
+ /* Receive FIFO 0 full interrupt management ********************************/
+ if ((interrupts & CAN_IT_RX_FIFO0_FULL) != RESET)
{
- pRxMsg = hcan->pRxMsg;
+ if ((rf0rflags & CAN_RF0R_FULL0) != RESET)
+ {
+ /* Clear FIFO 0 full Flag */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF0);
+
+ /* Receive FIFO 0 full Callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_RxFifo0FullCallback(hcan);
+ }
}
- else /* FIFONumber == CAN_FIFO1 */
+
+ /* Receive FIFO 0 message pending interrupt management *********************/
+ if ((interrupts & CAN_IT_RX_FIFO0_MSG_PENDING) != RESET)
{
- pRxMsg = hcan->pRx1Msg;
+ /* Check if message is still pending */
+ if ((hcan->Instance->RF0R & CAN_RF0R_FMP0) != RESET)
+ {
+ /* Receive FIFO 0 mesage pending Callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_RxFifo0MsgPendingCallback(hcan);
+ }
}
- /* Get the Id */
- pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
- if (pRxMsg->IDE == CAN_ID_STD)
- {
- pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
- }
- else
+ /* Receive FIFO 1 overrun interrupt management *****************************/
+ if ((interrupts & CAN_IT_RX_FIFO1_OVERRUN) != RESET)
{
- pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
- }
-
- pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
- /* Get the DLC */
- pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
- /* Get the FMI */
- pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
- /* Get the FIFONumber */
- pRxMsg->FIFONumber = FIFONumber;
- /* Get the data field */
- pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
- pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
- pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
- pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
- pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
- pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
- pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
- pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
+ if ((rf1rflags & CAN_RF1R_FOVR1) != RESET)
+ {
+ /* Set CAN error code to Rx Fifo 1 overrun error */
+ errorcode |= HAL_CAN_ERROR_RX_FOV1;
- /* Release the FIFO */
- if(FIFONumber == CAN_FIFO0)
- {
- /* Release FIFO0 */
- __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
- }
- else /* FIFONumber == CAN_FIFO1 */
- {
- /* Release FIFO1 */
- __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
+ /* Clear FIFO1 Overrun Flag */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1);
+ }
}
- /* Change CAN state */
- if (FIFONumber == CAN_FIFO0)
+ /* Receive FIFO 1 full interrupt management ********************************/
+ if ((interrupts & CAN_IT_RX_FIFO1_FULL) != RESET)
{
- switch(hcan->State)
+ if ((rf1rflags & CAN_RF1R_FULL1) != RESET)
{
- case(HAL_CAN_STATE_BUSY_TX_RX0):
- hcan->State = HAL_CAN_STATE_BUSY_TX;
- break;
- case(HAL_CAN_STATE_BUSY_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
- break;
- default: /* HAL_CAN_STATE_BUSY_RX0 */
- hcan->State = HAL_CAN_STATE_READY;
- break;
+ /* Clear FIFO 1 full Flag */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FF1);
+
+ /* Receive FIFO 1 full Callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_RxFifo1FullCallback(hcan);
}
}
- else /* FIFONumber == CAN_FIFO1 */
+
+ /* Receive FIFO 1 message pending interrupt management *********************/
+ if ((interrupts & CAN_IT_RX_FIFO1_MSG_PENDING) != RESET)
{
- switch(hcan->State)
+ /* Check if message is still pending */
+ if ((hcan->Instance->RF1R & CAN_RF1R_FMP1) != RESET)
{
- case(HAL_CAN_STATE_BUSY_TX_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX;
- break;
- case(HAL_CAN_STATE_BUSY_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_RX0;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
- break;
- default: /* HAL_CAN_STATE_BUSY_RX1 */
- hcan->State = HAL_CAN_STATE_READY;
- break;
+ /* Receive FIFO 1 mesage pending Callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_RxFifo1MsgPendingCallback(hcan);
+ }
+ }
+
+ /* Sleep interrupt management *********************************************/
+ if ((interrupts & CAN_IT_SLEEP_ACK) != RESET)
+ {
+ if ((msrflags & CAN_MSR_SLAKI) != RESET)
+ {
+ /* Clear Sleep interrupt Flag */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_SLAKI);
+
+ /* Sleep Callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_SleepCallback(hcan);
}
}
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
-
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Receives a correct CAN frame.
- * @param hcan: Pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @param FIFONumber: Specify the FIFO number
- * @retval HAL status
- */
-HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
-{
- /* Check the parameters */
- assert_param(IS_CAN_FIFO(FIFONumber));
-
- /* Check if CAN state is not busy for RX FIFO0 */
- if((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \
- (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \
- (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
- (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
+ /* WakeUp interrupt management *********************************************/
+ if ((interrupts & CAN_IT_WAKEUP) != RESET)
{
- return HAL_BUSY;
- }
-
- /* Check if CAN state is not busy for RX FIFO1 */
- if((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \
- (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \
- (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
- (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
- {
- return HAL_BUSY;
- }
+ if ((msrflags & CAN_MSR_WKUI) != RESET)
+ {
+ /* Clear WakeUp Flag */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_WKU);
- /* Process locked */
- __HAL_LOCK(hcan);
-
- /* Change CAN state */
- if(FIFONumber == CAN_FIFO0)
- {
- switch(hcan->State)
- {
- case(HAL_CAN_STATE_BUSY_TX):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
- break;
- case(HAL_CAN_STATE_BUSY_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
- break;
- default: /* HAL_CAN_STATE_READY */
- hcan->State = HAL_CAN_STATE_BUSY_RX0;
- break;
- }
- }
- else /* FIFONumber == CAN_FIFO1 */
- {
- switch(hcan->State)
- {
- case(HAL_CAN_STATE_BUSY_TX):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_RX0):
- hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX0):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
- break;
- default: /* HAL_CAN_STATE_READY */
- hcan->State = HAL_CAN_STATE_BUSY_RX1;
- break;
+ /* WakeUp Callback */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_WakeUpFromRxMsgCallback(hcan);
}
}
- /* Set CAN error code to none */
- hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+
+ /* Error interrupts management *********************************************/
+ if ((interrupts & CAN_IT_ERROR) != RESET)
+ {
+ if ((msrflags & CAN_MSR_ERRI) != RESET)
+ {
+ /* Check Error Warning Flag */
+ if (((interrupts & CAN_IT_ERROR_WARNING) != RESET) &&
+ ((esrflags & CAN_ESR_EWGF) != RESET))
+ {
+ /* Set CAN error code to Error Warning */
+ errorcode |= HAL_CAN_ERROR_EWG;
+
+ /* No need for clear of Error Warning Flag as read-only */
+ }
+
+ /* Check Error Passive Flag */
+ if (((interrupts & CAN_IT_ERROR_PASSIVE) != RESET) &&
+ ((esrflags & CAN_ESR_EPVF) != RESET))
+ {
+ /* Set CAN error code to Error Passive */
+ errorcode |= HAL_CAN_ERROR_EPV;
+
+ /* No need for clear of Error Passive Flag as read-only */
+ }
+
+ /* Check Bus-off Flag */
+ if (((interrupts & CAN_IT_BUSOFF) != RESET) &&
+ ((esrflags & CAN_ESR_BOFF) != RESET))
+ {
+ /* Set CAN error code to Bus-Off */
+ errorcode |= HAL_CAN_ERROR_BOF;
+
+ /* No need for clear of Error Bus-Off as read-only */
+ }
- /* Enable interrupts: */
- /* - Enable Error warning Interrupt */
- /* - Enable Error passive Interrupt */
- /* - Enable Bus-off Interrupt */
- /* - Enable Last error code Interrupt */
- /* - Enable Error Interrupt */
- /* - Enable Transmit mailbox empty Interrupt */
- __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
- CAN_IT_EPV |
- CAN_IT_BOF |
- CAN_IT_LEC |
- CAN_IT_ERR |
- CAN_IT_TME);
+ /* Check Last Error Code Flag */
+ if (((interrupts & CAN_IT_LAST_ERROR_CODE) != RESET) &&
+ ((esrflags & CAN_ESR_LEC) != RESET))
+ {
+ switch (esrflags & CAN_ESR_LEC)
+ {
+ case (CAN_ESR_LEC_0):
+ /* Set CAN error code to Stuff error */
+ errorcode |= HAL_CAN_ERROR_STF;
+ break;
+ case (CAN_ESR_LEC_1):
+ /* Set CAN error code to Form error */
+ errorcode |= HAL_CAN_ERROR_FOR;
+ break;
+ case (CAN_ESR_LEC_1 | CAN_ESR_LEC_0):
+ /* Set CAN error code to Acknowledgement error */
+ errorcode |= HAL_CAN_ERROR_ACK;
+ break;
+ case (CAN_ESR_LEC_2):
+ /* Set CAN error code to Bit recessive error */
+ errorcode |= HAL_CAN_ERROR_BR;
+ break;
+ case (CAN_ESR_LEC_2 | CAN_ESR_LEC_0):
+ /* Set CAN error code to Bit Dominant error */
+ errorcode |= HAL_CAN_ERROR_BD;
+ break;
+ case (CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
+ /* Set CAN error code to CRC error */
+ errorcode |= HAL_CAN_ERROR_CRC;
+ break;
+ default:
+ break;
+ }
- if(FIFONumber == CAN_FIFO0)
- {
- /* Enable FIFO 0 overrun and message pending Interrupt */
- __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0);
- }
- else
- {
- /* Enable FIFO 1 overrun and message pending Interrupt */
- __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1);
+ /* Clear Last error code Flag */
+ CLEAR_BIT(hcan->Instance->ESR, CAN_ESR_LEC);
+ }
+ }
+
+ /* Clear ERRI Flag */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_ERRI);
}
- /* Return function status */
- return HAL_OK;
-}
-
-/**
- * @brief Enters the Sleep (low power) mode.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @retval HAL status.
- */
-HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan)
-{
- uint32_t tickstart = 0;
-
- /* Process locked */
- __HAL_LOCK(hcan);
-
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY;
-
- /* Request Sleep mode */
- hcan->Instance->MCR = (((hcan->Instance->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
-
- /* Sleep mode status */
- if ((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)
+ /* Call the Error call Back in case of Errors */
+ if (errorcode != HAL_CAN_ERROR_NONE)
{
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
+ /* Update error code in handle */
+ hcan->ErrorCode |= errorcode;
- /* Return function status */
- return HAL_ERROR;
+ /* Call Error callback function */
+ /* Call weak (surcharged) callback */
+ HAL_CAN_ErrorCallback(hcan);
}
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* Wait the acknowledge */
- while((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)
- {
- if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
- {
- hcan->State = HAL_CAN_STATE_TIMEOUT;
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
- return HAL_TIMEOUT;
- }
- }
-
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
-
- /* Return function status */
- return HAL_OK;
}
/**
- * @brief Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral
- * is in the normal mode.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @retval HAL status.
+ * @}
*/
-HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan)
-{
- uint32_t tickstart = 0;
-
- /* Process locked */
- __HAL_LOCK(hcan);
-
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_BUSY;
-
- /* Wake up request */
- hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_SLEEP;
-
- /* Get tick */
- tickstart = HAL_GetTick();
- /* Sleep mode status */
- while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
- {
- if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
- {
- hcan->State= HAL_CAN_STATE_TIMEOUT;
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
- return HAL_TIMEOUT;
- }
- }
- if((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
- {
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
+/** @defgroup CAN_Exported_Functions_Group5 Callback functions
+ * @brief CAN Callback functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Callback functions #####
+ ==============================================================================
+ [..]
+ This subsection provides the following callback functions:
+ (+) HAL_CAN_TxMailbox0CompleteCallback
+ (+) HAL_CAN_TxMailbox1CompleteCallback
+ (+) HAL_CAN_TxMailbox2CompleteCallback
+ (+) HAL_CAN_TxMailbox0AbortCallback
+ (+) HAL_CAN_TxMailbox1AbortCallback
+ (+) HAL_CAN_TxMailbox2AbortCallback
+ (+) HAL_CAN_RxFifo0MsgPendingCallback
+ (+) HAL_CAN_RxFifo0FullCallback
+ (+) HAL_CAN_RxFifo1MsgPendingCallback
+ (+) HAL_CAN_RxFifo1FullCallback
+ (+) HAL_CAN_SleepCallback
+ (+) HAL_CAN_WakeUpFromRxMsgCallback
+ (+) HAL_CAN_ErrorCallback
- /* Return function status */
- return HAL_ERROR;
- }
-
- /* Change CAN state */
- hcan->State = HAL_CAN_STATE_READY;
-
- /* Process unlocked */
- __HAL_UNLOCK(hcan);
-
- /* Return function status */
- return HAL_OK;
-}
+@endverbatim
+ * @{
+ */
/**
- * @brief Handles CAN interrupt request
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * @brief Transmission Mailbox 0 complete callback.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
-void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
-{
- uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U;
- uint32_t errorcode = HAL_CAN_ERROR_NONE;
-
- /* Check Overrun flag for FIFO0 */
- tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV0);
- tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV0);
- if(tmp1 && tmp2)
- {
- /* Set CAN error code to FOV0 error */
- errorcode |= HAL_CAN_ERROR_FOV0;
-
- /* Clear FIFO0 Overrun Flag */
- __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0);
- }
- /* Check Overrun flag for FIFO1 */
- tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV1);
- tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV1);
-
- if(tmp1 && tmp2)
- {
- /* Set CAN error code to FOV1 error */
- errorcode |= HAL_CAN_ERROR_FOV1;
-
- /* Clear FIFO1 Overrun Flag */
- __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1);
- }
-
- /* Check End of transmission flag */
- if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME))
- {
- tmp1 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0);
- tmp2 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1);
- tmp3 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2);
- if(tmp1 || tmp2 || tmp3)
- {
- tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK0);
- tmp2 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK1);
- tmp3 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK2);
- /* Check Transmit success */
- if(tmp1 || tmp2 || tmp3)
- {
- /* Call transmit function */
- CAN_Transmit_IT(hcan);
- }
- else /* Transmit failure */
- {
- /* Set CAN error code to TXFAIL error */
- errorcode |= HAL_CAN_ERROR_TXFAIL;
- }
-
- /* Clear transmission status flags (RQCPx and TXOKx) */
- SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP0 | CAN_TSR_RQCP1 | CAN_TSR_RQCP2 | \
- CAN_FLAG_TXOK0 | CAN_FLAG_TXOK1 | CAN_FLAG_TXOK2);
- }
- }
-
- tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0);
- tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0);
- /* Check End of reception flag for FIFO0 */
- if((tmp1 != 0U) && tmp2)
- {
- /* Call receive function */
- CAN_Receive_IT(hcan, CAN_FIFO0);
- }
-
- tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1);
- tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1);
- /* Check End of reception flag for FIFO1 */
- if((tmp1 != 0U) && tmp2)
- {
- /* Call receive function */
- CAN_Receive_IT(hcan, CAN_FIFO1);
- }
-
- /* Set error code in handle */
- hcan->ErrorCode |= errorcode;
-
- tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG);
- tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG);
- tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
- /* Check Error Warning Flag */
- if(tmp1 && tmp2 && tmp3)
- {
- /* Set CAN error code to EWG error */
- hcan->ErrorCode |= HAL_CAN_ERROR_EWG;
- }
-
- tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV);
- tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV);
- tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
- /* Check Error Passive Flag */
- if(tmp1 && tmp2 && tmp3)
- {
- /* Set CAN error code to EPV error */
- hcan->ErrorCode |= HAL_CAN_ERROR_EPV;
- }
-
- tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF);
- tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF);
- tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
- /* Check Bus-Off Flag */
- if(tmp1 && tmp2 && tmp3)
- {
- /* Set CAN error code to BOF error */
- hcan->ErrorCode |= HAL_CAN_ERROR_BOF;
- }
-
- tmp1 = HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC);
- tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC);
- tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
- /* Check Last error code Flag */
- if((!tmp1) && tmp2 && tmp3)
- {
- tmp1 = (hcan->Instance->ESR) & CAN_ESR_LEC;
- switch(tmp1)
- {
- case(CAN_ESR_LEC_0):
- /* Set CAN error code to STF error */
- hcan->ErrorCode |= HAL_CAN_ERROR_STF;
- break;
- case(CAN_ESR_LEC_1):
- /* Set CAN error code to FOR error */
- hcan->ErrorCode |= HAL_CAN_ERROR_FOR;
- break;
- case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0):
- /* Set CAN error code to ACK error */
- hcan->ErrorCode |= HAL_CAN_ERROR_ACK;
- break;
- case(CAN_ESR_LEC_2):
- /* Set CAN error code to BR error */
- hcan->ErrorCode |= HAL_CAN_ERROR_BR;
- break;
- case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0):
- /* Set CAN error code to BD error */
- hcan->ErrorCode |= HAL_CAN_ERROR_BD;
- break;
- case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
- /* Set CAN error code to CRC error */
- hcan->ErrorCode |= HAL_CAN_ERROR_CRC;
- break;
- default:
- break;
- }
-
- /* Clear Last error code Flag */
- hcan->Instance->ESR &= ~(CAN_ESR_LEC);
- }
-
- /* Call the Error call Back in case of Errors */
- if(hcan->ErrorCode != HAL_CAN_ERROR_NONE)
- {
- /* Clear ERRI Flag */
- hcan->Instance->MSR = CAN_MSR_ERRI;
- /* Set the CAN state ready to be able to start again the process */
- hcan->State = HAL_CAN_STATE_READY;
-
- /* Disable interrupts: */
- /* - Disable Error warning Interrupt */
- /* - Disable Error passive Interrupt */
- /* - Disable Bus-off Interrupt */
- /* - Disable Last error code Interrupt */
- /* - Disable Error Interrupt */
- /* - Disable FIFO 0 message pending Interrupt */
- /* - Disable FIFO 0 Overrun Interrupt */
- /* - Disable FIFO 1 message pending Interrupt */
- /* - Disable FIFO 1 Overrun Interrupt */
- /* - Disable Transmit mailbox empty Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
- CAN_IT_EPV |
- CAN_IT_BOF |
- CAN_IT_LEC |
- CAN_IT_ERR |
- CAN_IT_FMP0|
- CAN_IT_FOV0|
- CAN_IT_FMP1|
- CAN_IT_FOV1|
- CAN_IT_TME);
-
- /* Call Error callback function */
- HAL_CAN_ErrorCallback(hcan);
- }
-}
-
-/**
- * @brief Transmission complete callback in non blocking mode
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @retval None
- */
-__weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan)
+__weak void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcan);
+
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_CAN_TxCpltCallback could be implemented in the user file
+ the HAL_CAN_TxMailbox0CompleteCallback could be implemented in the
+ user file
*/
}
/**
- * @brief Transmission complete callback in non blocking mode
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * @brief Transmission Mailbox 1 complete callback.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_TxMailbox1CompleteCallback could be implemented in the
+ user file
+ */
+}
+
+/**
+ * @brief Transmission Mailbox 2 complete callback.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_TxMailbox2CompleteCallback could be implemented in the
+ user file
+ */
+}
+
+/**
+ * @brief Transmission Mailbox 0 Cancellation callback.
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_TxMailbox0AbortCallback could be implemented in the
+ user file
+ */
+}
+
+/**
+ * @brief Transmission Mailbox 1 Cancellation callback.
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_TxMailbox1AbortCallback could be implemented in the
+ user file
+ */
+}
+
+/**
+ * @brief Transmission Mailbox 2 Cancellation callback.
+ * @param hcan pointer to an CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_TxMailbox2AbortCallback could be implemented in the
+ user file
+ */
+}
+
+/**
+ * @brief Rx FIFO 0 message pending callback.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
-__weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan)
+__weak void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_RxFifo0MsgPendingCallback could be implemented in the
+ user file
+ */
+}
+
+/**
+ * @brief Rx FIFO 0 full callback.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_RxFifo0FullCallback could be implemented in the user
+ file
+ */
+}
+
+/**
+ * @brief Rx FIFO 1 message pending callback.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcan);
+
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_CAN_RxCpltCallback could be implemented in the user file
+ the HAL_CAN_RxFifo1MsgPendingCallback could be implemented in the
+ user file
+ */
+}
+
+/**
+ * @brief Rx FIFO 1 full callback.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_RxFifo1FullCallback could be implemented in the user
+ file
+ */
+}
+
+/**
+ * @brief Sleep callback.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_SleepCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief WakeUp from Rx message callback.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_WakeUpFromRxMsgCallback could be implemented in the
+ user file
*/
}
/**
* @brief Error CAN callback.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval None
*/
@@ -1434,6 +1872,7 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hcan);
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_CAN_ErrorCallback could be implemented in the user file
*/
@@ -1443,225 +1882,95 @@
* @}
*/
-/** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
- * @brief CAN Peripheral State functions
+/** @defgroup CAN_Exported_Functions_Group6 Peripheral State and Error functions
+ * @brief CAN Peripheral State functions
*
-@verbatim
+@verbatim
==============================================================================
##### Peripheral State and Error functions #####
==============================================================================
[..]
This subsection provides functions allowing to :
- (+) Check the CAN state.
- (+) Check CAN Errors detected during interrupt process
-
+ (+) HAL_CAN_GetState() : Return the CAN state.
+ (+) HAL_CAN_GetError() : Return the CAN error codes if any.
+ (+) HAL_CAN_ResetError(): Reset the CAN error codes if any.
+
@endverbatim
* @{
*/
/**
- * @brief return the CAN state
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * @brief Return the CAN state.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval HAL state
*/
-HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan)
+HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan)
{
+ HAL_CAN_StateTypeDef state = hcan->State;
+
+ if ((hcan->State == HAL_CAN_STATE_READY) ||
+ (hcan->State == HAL_CAN_STATE_LISTENING))
+ {
+ /* Check sleep mode acknowledge flag */
+ if ((hcan->Instance->MSR & CAN_MSR_SLAK) != RESET)
+ {
+ /* Sleep mode is active */
+ state = HAL_CAN_STATE_SLEEP_ACTIVE;
+ }
+ /* Check sleep mode request flag */
+ else if ((hcan->Instance->MCR & CAN_MCR_SLEEP) != RESET)
+ {
+ /* Sleep mode request is pending */
+ state = HAL_CAN_STATE_SLEEP_PENDING;
+ }
+ }
+
/* Return CAN state */
- return hcan->State;
+ return state;
}
/**
- * @brief Return the CAN error code
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
+ * @brief Return the CAN error code.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
* the configuration information for the specified CAN.
* @retval CAN Error Code
*/
uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan)
{
+ /* Return CAN error code */
return hcan->ErrorCode;
}
/**
- * @}
- */
-
-/**
- * @brief Initiates and transmits a CAN frame message.
- * @param hcan: pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
+ * @brief Reset the CAN error code.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
* @retval HAL status
*/
-static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
+HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan)
{
- /* Disable Transmit mailbox empty Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME);
-
- if(hcan->State == HAL_CAN_STATE_BUSY_TX)
- {
- /* Disable Error warning, Error passive, Bus-off, Last error code
- and Error Interrupts */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
- CAN_IT_EPV |
- CAN_IT_BOF |
- CAN_IT_LEC |
- CAN_IT_ERR );
- }
-
- /* Change CAN state */
- switch(hcan->State)
- {
- case(HAL_CAN_STATE_BUSY_TX_RX0):
- hcan->State = HAL_CAN_STATE_BUSY_RX0;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
- break;
- default: /* HAL_CAN_STATE_BUSY_TX */
- hcan->State = HAL_CAN_STATE_READY;
- break;
- }
+ HAL_StatusTypeDef status = HAL_OK;
- /* Transmission complete callback */
- HAL_CAN_TxCpltCallback(hcan);
-
- return HAL_OK;
-}
-
-/**
- * @brief Receives a correct CAN frame.
- * @param hcan: Pointer to a CAN_HandleTypeDef structure that contains
- * the configuration information for the specified CAN.
- * @param FIFONumber: Specify the FIFO number
- * @retval HAL status
- * @retval None
- */
-static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
-{
- uint32_t tmp1 = 0U;
- CanRxMsgTypeDef* pRxMsg = NULL;
-
- /* Set RxMsg pointer */
- if(FIFONumber == CAN_FIFO0)
+ if ((hcan->State == HAL_CAN_STATE_READY) ||
+ (hcan->State == HAL_CAN_STATE_LISTENING))
{
- pRxMsg = hcan->pRxMsg;
- }
- else /* FIFONumber == CAN_FIFO1 */
- {
- pRxMsg = hcan->pRx1Msg;
- }
-
- /* Get the Id */
- pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
- if (pRxMsg->IDE == CAN_ID_STD)
- {
- pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
+ /* Reset CAN error code */
+ hcan->ErrorCode = 0U;
}
else
{
- pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
- }
-
- pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
- /* Get the DLC */
- pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
- /* Get the FIFONumber */
- pRxMsg->FIFONumber = FIFONumber;
- /* Get the FMI */
- pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
- /* Get the data field */
- pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
- pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
- pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
- pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
- pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
- pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
- pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
- pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
- /* Release the FIFO */
- /* Release FIFO0 */
- if (FIFONumber == CAN_FIFO0)
- {
- __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
+ /* Update error code */
+ hcan->ErrorCode |= HAL_CAN_ERROR_NOT_INITIALIZED;
- /* Disable FIFO 0 overrun and message pending Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0);
- }
- /* Release FIFO1 */
- else /* FIFONumber == CAN_FIFO1 */
- {
- __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
-
- /* Disable FIFO 1 overrun and message pending Interrupt */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1);
- }
-
- tmp1 = hcan->State;
- if((tmp1 == HAL_CAN_STATE_BUSY_RX0) || (tmp1 == HAL_CAN_STATE_BUSY_RX1))
- {
- /* Disable Error warning, Error passive, Bus-off, Last error code
- and Error Interrupts */
- __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
- CAN_IT_EPV |
- CAN_IT_BOF |
- CAN_IT_LEC |
- CAN_IT_ERR);
+ status = HAL_ERROR;
}
- /* Change CAN state */
- if (FIFONumber == CAN_FIFO0)
- {
- switch(hcan->State)
- {
- case(HAL_CAN_STATE_BUSY_TX_RX0):
- hcan->State = HAL_CAN_STATE_BUSY_TX;
- break;
- case(HAL_CAN_STATE_BUSY_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_RX1;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
- break;
- default: /* HAL_CAN_STATE_BUSY_RX0 */
- hcan->State = HAL_CAN_STATE_READY;
- break;
- }
- }
- else /* FIFONumber == CAN_FIFO1 */
- {
- switch(hcan->State)
- {
- case(HAL_CAN_STATE_BUSY_TX_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX;
- break;
- case(HAL_CAN_STATE_BUSY_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_RX0;
- break;
- case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
- hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
- break;
- default: /* HAL_CAN_STATE_BUSY_RX1 */
- hcan->State = HAL_CAN_STATE_READY;
- break;
- }
- }
-
- /* Receive complete callback */
- HAL_CAN_RxCpltCallback(hcan);
-
- /* Return function status */
- return HAL_OK;
+ /* Return the status */
+ return status;
}
/**
- * @}
- */
-
-#endif /* HAL_CAN_MODULE_ENABLED */
-/**
* @}
*/
@@ -1669,4 +1978,16 @@
* @}
*/
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+/**
+ * @}
+ */
+
+#endif /* CAN1 */
+
+/**
+ * @}
+ */
+
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_can.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_can.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_can.h
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief Header file of CAN HAL module.
******************************************************************************
* @attention
@@ -36,11 +34,11 @@
*/
/* Define to prevent recursive inclusion -------------------------------------*/
-#ifndef __STM32F7xx_HAL_CAN_H
-#define __STM32F7xx_HAL_CAN_H
+#ifndef STM32F7xx_HAL_CAN_H
+#define STM32F7xx_HAL_CAN_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -50,6 +48,7 @@
* @{
*/
+#if defined (CAN1)
/** @addtogroup CAN
* @{
*/
@@ -58,7 +57,6 @@
/** @defgroup CAN_Exported_Types CAN Exported Types
* @{
*/
-
/**
* @brief HAL State structures definition
*/
@@ -66,59 +64,53 @@
{
HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */
HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */
- HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */
- HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */
- HAL_CAN_STATE_BUSY_RX0 = 0x22U, /*!< CAN process is ongoing */
- HAL_CAN_STATE_BUSY_RX1 = 0x32U, /*!< CAN process is ongoing */
- HAL_CAN_STATE_BUSY_TX_RX0 = 0x42U, /*!< CAN process is ongoing */
- HAL_CAN_STATE_BUSY_TX_RX1 = 0x52U, /*!< CAN process is ongoing */
- HAL_CAN_STATE_BUSY_RX0_RX1 = 0x62U, /*!< CAN process is ongoing */
- HAL_CAN_STATE_BUSY_TX_RX0_RX1 = 0x72U, /*!< CAN process is ongoing */
- HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< CAN in Timeout state */
- HAL_CAN_STATE_ERROR = 0x04U /*!< CAN error state */
+ HAL_CAN_STATE_LISTENING = 0x02U, /*!< CAN receive process is ongoing */
+ HAL_CAN_STATE_SLEEP_PENDING = 0x03U, /*!< CAN sleep request is pending */
+ HAL_CAN_STATE_SLEEP_ACTIVE = 0x04U, /*!< CAN sleep mode is active */
+ HAL_CAN_STATE_ERROR = 0x05U /*!< CAN error state */
-}HAL_CAN_StateTypeDef;
+} HAL_CAN_StateTypeDef;
/**
* @brief CAN init structure definition
*/
typedef struct
{
- uint32_t Prescaler; /*!< Specifies the length of a time quantum.
- This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
+ uint32_t Prescaler; /*!< Specifies the length of a time quantum.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 1024. */
- uint32_t Mode; /*!< Specifies the CAN operating mode.
- This parameter can be a value of @ref CAN_operating_mode */
+ uint32_t Mode; /*!< Specifies the CAN operating mode.
+ This parameter can be a value of @ref CAN_operating_mode */
- uint32_t SJW; /*!< Specifies the maximum number of time quanta
- the CAN hardware is allowed to lengthen or
- shorten a bit to perform resynchronization.
- This parameter can be a value of @ref CAN_synchronisation_jump_width */
+ uint32_t SyncJumpWidth; /*!< Specifies the maximum number of time quanta the CAN hardware
+ is allowed to lengthen or shorten a bit to perform resynchronization.
+ This parameter can be a value of @ref CAN_synchronisation_jump_width */
- uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1.
- This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
+ uint32_t TimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1.
+ This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
- uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
- This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
+ uint32_t TimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2.
+ This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
- uint32_t TTCM; /*!< Enable or disable the time triggered communication mode.
- This parameter can be set to ENABLE or DISABLE. */
+ FunctionalState TimeTriggeredMode; /*!< Enable or disable the time triggered communication mode.
+ This parameter can be set to ENABLE or DISABLE. */
- uint32_t ABOM; /*!< Enable or disable the automatic bus-off management.
- This parameter can be set to ENABLE or DISABLE */
+ FunctionalState AutoBusOff; /*!< Enable or disable the automatic bus-off management.
+ This parameter can be set to ENABLE or DISABLE. */
- uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode.
- This parameter can be set to ENABLE or DISABLE */
+ FunctionalState AutoWakeUp; /*!< Enable or disable the automatic wake-up mode.
+ This parameter can be set to ENABLE or DISABLE. */
- uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode.
- This parameter can be set to ENABLE or DISABLE */
+ FunctionalState AutoRetransmission; /*!< Enable or disable the non-automatic retransmission mode.
+ This parameter can be set to ENABLE or DISABLE. */
- uint32_t RFLM; /*!< Enable or disable the receive FIFO Locked mode.
- This parameter can be set to ENABLE or DISABLE */
+ FunctionalState ReceiveFifoLocked; /*!< Enable or disable the Receive FIFO Locked mode.
+ This parameter can be set to ENABLE or DISABLE. */
- uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority.
- This parameter can be set to ENABLE or DISABLE */
-}CAN_InitTypeDef;
+ FunctionalState TransmitFifoPriority;/*!< Enable or disable the transmit FIFO priority.
+ This parameter can be set to ENABLE or DISABLE. */
+
+} CAN_InitTypeDef;
/**
* @brief CAN filter configuration structure definition
@@ -127,27 +119,30 @@
{
uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
configuration, first one for a 16-bit configuration).
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
configuration, second one for a 16-bit configuration).
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
according to the mode (MSBs for a 32-bit configuration,
first one for a 16-bit configuration).
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
according to the mode (LSBs for a 32-bit configuration,
second one for a 16-bit configuration).
- This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
- uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
+ uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1U) which will be assigned to the filter.
This parameter can be a value of @ref CAN_filter_FIFO */
- uint32_t FilterNumber; /*!< Specifies the filter which will be initialized.
- This parameter must be a number between Min_Data = 0 and Max_Data = 27 */
+ uint32_t FilterBank; /*!< Specifies the filter bank which will be initialized.
+ For single CAN instance(14 dedicated filter banks),
+ this parameter must be a number between Min_Data = 0 and Max_Data = 13.
+ For dual CAN instances(28 filter banks shared),
+ this parameter must be a number between Min_Data = 0 and Max_Data = 27. */
uint32_t FilterMode; /*!< Specifies the filter mode to be initialized.
This parameter can be a value of @ref CAN_filter_mode */
@@ -158,95 +153,94 @@
uint32_t FilterActivation; /*!< Enable or disable the filter.
This parameter can be set to ENABLE or DISABLE. */
- uint32_t BankNumber; /*!< Select the start slave bank filter.
- This parameter must be a number between Min_Data = 0 and Max_Data = 28 */
+ uint32_t SlaveStartFilterBank; /*!< Select the start filter bank for the slave CAN instance.
+ For single CAN instances, this parameter is meaningless.
+ For dual CAN instances, all filter banks with lower index are assigned to master
+ CAN instance, whereas all filter banks with greater index are assigned to slave
+ CAN instance.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 27. */
-}CAN_FilterConfTypeDef;
+} CAN_FilterTypeDef;
/**
- * @brief CAN Tx message structure definition
+ * @brief CAN Tx message header structure definition
*/
typedef struct
{
uint32_t StdId; /*!< Specifies the standard identifier.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
uint32_t ExtId; /*!< Specifies the extended identifier.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
- This parameter can be a value of @ref CAN_Identifier_Type */
+ This parameter can be a value of @ref CAN_identifier_type */
uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
This parameter can be a value of @ref CAN_remote_transmission_request */
uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
- This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
+ This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
- uint8_t Data[8]; /*!< Contains the data to be transmitted.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
+ FunctionalState TransmitGlobalTime; /*!< Specifies whether the timestamp counter value captured on start
+ of frame transmission, is sent in DATA6 and DATA7 replacing pData[6] and pData[7].
+ @note: Time Triggered Communication Mode must be enabled.
+ @note: DLC must be programmed as 8 bytes, in order these 2 bytes are sent.
+ This parameter can be set to ENABLE or DISABLE. */
-}CanTxMsgTypeDef;
+} CAN_TxHeaderTypeDef;
/**
- * @brief CAN Rx message structure definition
+ * @brief CAN Rx message header structure definition
*/
typedef struct
{
- uint32_t StdId; /*!< Specifies the standard identifier.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
+ uint32_t StdId; /*!< Specifies the standard identifier.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF. */
- uint32_t ExtId; /*!< Specifies the extended identifier.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
+ uint32_t ExtId; /*!< Specifies the extended identifier.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF. */
- uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received.
- This parameter can be a value of @ref CAN_Identifier_Type */
+ uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
+ This parameter can be a value of @ref CAN_identifier_type */
- uint32_t RTR; /*!< Specifies the type of frame for the received message.
- This parameter can be a value of @ref CAN_remote_transmission_request */
+ uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
+ This parameter can be a value of @ref CAN_remote_transmission_request */
- uint32_t DLC; /*!< Specifies the length of the frame that will be received.
- This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
-
- uint8_t Data[8]; /*!< Contains the data to be received.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
+ uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 8. */
- uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through.
- This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
+ uint32_t Timestamp; /*!< Specifies the timestamp counter value captured on start of frame reception.
+ @note: Time Triggered Communication Mode must be enabled.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0xFFFF. */
- uint32_t FIFONumber; /*!< Specifies the receive FIFO number.
- This parameter can be CAN_FIFO0 or CAN_FIFO1 */
+ uint32_t FilterMatchIndex; /*!< Specifies the index of matching acceptance filter element.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF. */
-}CanRxMsgTypeDef;
+} CAN_RxHeaderTypeDef;
/**
* @brief CAN handle Structure definition
*/
-typedef struct
+typedef struct __CAN_HandleTypeDef
{
- CAN_TypeDef *Instance; /*!< Register base address */
+ CAN_TypeDef *Instance; /*!< Register base address */
- CAN_InitTypeDef Init; /*!< CAN required parameters */
-
- CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */
-
- CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure for RX FIFO0 msg */
+ CAN_InitTypeDef Init; /*!< CAN required parameters */
- CanRxMsgTypeDef* pRx1Msg; /*!< Pointer to reception structure for RX FIFO1 msg */
-
- __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
+ __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
- HAL_LockTypeDef Lock; /*!< CAN locking object */
+ __IO uint32_t ErrorCode; /*!< CAN Error code.
+ This parameter can be a value of @ref CAN_Error_Code */
- __IO uint32_t ErrorCode; /*!< CAN Error code
- This parameter can be a value of @ref CAN_Error_Code */
-}CAN_HandleTypeDef;
+} CAN_HandleTypeDef;
/**
* @}
*/
/* Exported constants --------------------------------------------------------*/
+
/** @defgroup CAN_Exported_Constants CAN Exported Constants
* @{
*/
@@ -254,19 +248,30 @@
/** @defgroup CAN_Error_Code CAN Error Code
* @{
*/
-#define HAL_CAN_ERROR_NONE 0x00000000U /*!< No error */
-#define HAL_CAN_ERROR_EWG 0x00000001U /*!< EWG error */
-#define HAL_CAN_ERROR_EPV 0x00000002U /*!< EPV error */
-#define HAL_CAN_ERROR_BOF 0x00000004U /*!< BOF error */
-#define HAL_CAN_ERROR_STF 0x00000008U /*!< Stuff error */
-#define HAL_CAN_ERROR_FOR 0x00000010U /*!< Form error */
-#define HAL_CAN_ERROR_ACK 0x00000020U /*!< Acknowledgment error */
-#define HAL_CAN_ERROR_BR 0x00000040U /*!< Bit recessive */
-#define HAL_CAN_ERROR_BD 0x00000080U /*!< LEC dominant */
-#define HAL_CAN_ERROR_CRC 0x00000100U /*!< LEC transfer error */
-#define HAL_CAN_ERROR_FOV0 0x00000200U /*!< FIFO0 overrun error */
-#define HAL_CAN_ERROR_FOV1 0x00000400U /*!< FIFO1 overrun error */
-#define HAL_CAN_ERROR_TXFAIL 0x00000800U /*!< Transmit failure */
+#define HAL_CAN_ERROR_NONE (0x00000000U) /*!< No error */
+#define HAL_CAN_ERROR_EWG (0x00000001U) /*!< Protocol Error Warning */
+#define HAL_CAN_ERROR_EPV (0x00000002U) /*!< Error Passive */
+#define HAL_CAN_ERROR_BOF (0x00000004U) /*!< Bus-off error */
+#define HAL_CAN_ERROR_STF (0x00000008U) /*!< Stuff error */
+#define HAL_CAN_ERROR_FOR (0x00000010U) /*!< Form error */
+#define HAL_CAN_ERROR_ACK (0x00000020U) /*!< Acknowledgment error */
+#define HAL_CAN_ERROR_BR (0x00000040U) /*!< Bit recessive error */
+#define HAL_CAN_ERROR_BD (0x00000080U) /*!< Bit dominant error */
+#define HAL_CAN_ERROR_CRC (0x00000100U) /*!< CRC error */
+#define HAL_CAN_ERROR_RX_FOV0 (0x00000200U) /*!< Rx FIFO0 overrun error */
+#define HAL_CAN_ERROR_RX_FOV1 (0x00000400U) /*!< Rx FIFO1 overrun error */
+#define HAL_CAN_ERROR_TX_ALST0 (0x00000800U) /*!< TxMailbox 0 transmit failure due to arbitration lost */
+#define HAL_CAN_ERROR_TX_TERR0 (0x00001000U) /*!< TxMailbox 1 transmit failure due to tranmit error */
+#define HAL_CAN_ERROR_TX_ALST1 (0x00002000U) /*!< TxMailbox 0 transmit failure due to arbitration lost */
+#define HAL_CAN_ERROR_TX_TERR1 (0x00004000U) /*!< TxMailbox 1 transmit failure due to tranmit error */
+#define HAL_CAN_ERROR_TX_ALST2 (0x00008000U) /*!< TxMailbox 0 transmit failure due to arbitration lost */
+#define HAL_CAN_ERROR_TX_TERR2 (0x00010000U) /*!< TxMailbox 1 transmit failure due to tranmit error */
+#define HAL_CAN_ERROR_TIMEOUT (0x00020000U) /*!< Timeout error */
+#define HAL_CAN_ERROR_NOT_INITIALIZED (0x00040000U) /*!< Peripheral not initialized */
+#define HAL_CAN_ERROR_NOT_READY (0x00080000U) /*!< Peripheral not ready */
+#define HAL_CAN_ERROR_NOT_STARTED (0x00100000U) /*!< Peripheral not started */
+#define HAL_CAN_ERROR_PARAM (0x00200000U) /*!< Parameter error */
+
/**
* @}
*/
@@ -274,8 +279,8 @@
/** @defgroup CAN_InitStatus CAN InitStatus
* @{
*/
-#define CAN_INITSTATUS_FAILED ((uint8_t)0x00U) /*!< CAN initialization failed */
-#define CAN_INITSTATUS_SUCCESS ((uint8_t)0x01U) /*!< CAN initialization OK */
+#define CAN_INITSTATUS_FAILED (0x00000000U) /*!< CAN initialization failed */
+#define CAN_INITSTATUS_SUCCESS (0x00000001U) /*!< CAN initialization OK */
/**
* @}
*/
@@ -283,7 +288,7 @@
/** @defgroup CAN_operating_mode CAN Operating Mode
* @{
*/
-#define CAN_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */
+#define CAN_MODE_NORMAL (0x00000000U) /*!< Normal mode */
#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */
#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */
#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */
@@ -291,10 +296,11 @@
* @}
*/
-/** @defgroup CAN_synchronisation_jump_width CAN Synchronisation Jump Width
+
+/** @defgroup CAN_synchronisation_jump_width CAN Synchronization Jump Width
* @{
*/
-#define CAN_SJW_1TQ ((uint32_t)0x00000000U) /*!< 1 time quantum */
+#define CAN_SJW_1TQ (0x00000000U) /*!< 1 time quantum */
#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */
#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */
#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */
@@ -302,10 +308,10 @@
* @}
*/
-/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in bit segment 1
+/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in Bit Segment 1
* @{
*/
-#define CAN_BS1_1TQ ((uint32_t)0x00000000U) /*!< 1 time quantum */
+#define CAN_BS1_1TQ (0x00000000U) /*!< 1 time quantum */
#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */
#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */
#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */
@@ -325,10 +331,10 @@
* @}
*/
-/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in bit segment 2
+/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in Bit Segment 2
* @{
*/
-#define CAN_BS2_1TQ ((uint32_t)0x00000000U) /*!< 1 time quantum */
+#define CAN_BS2_1TQ (0x00000000U) /*!< 1 time quantum */
#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */
#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */
#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */
@@ -340,11 +346,11 @@
* @}
*/
-/** @defgroup CAN_filter_mode CAN Filter Mode
+/** @defgroup CAN_filter_mode CAN Filter Mode
* @{
*/
-#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00U) /*!< Identifier mask mode */
-#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01U) /*!< Identifier list mode */
+#define CAN_FILTERMODE_IDMASK (0x00000000U) /*!< Identifier mask mode */
+#define CAN_FILTERMODE_IDLIST (0x00000001U) /*!< Identifier list mode */
/**
* @}
*/
@@ -352,8 +358,8 @@
/** @defgroup CAN_filter_scale CAN Filter Scale
* @{
*/
-#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00U) /*!< Two 16-bit filters */
-#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01U) /*!< One 32-bit filter */
+#define CAN_FILTERSCALE_16BIT (0x00000000U) /*!< Two 16-bit filters */
+#define CAN_FILTERSCALE_32BIT (0x00000001U) /*!< One 32-bit filter */
/**
* @}
*/
@@ -361,17 +367,17 @@
/** @defgroup CAN_filter_FIFO CAN Filter FIFO
* @{
*/
-#define CAN_FILTER_FIFO0 ((uint8_t)0x00U) /*!< Filter FIFO 0 assignment for filter x */
-#define CAN_FILTER_FIFO1 ((uint8_t)0x01U) /*!< Filter FIFO 1 assignment for filter x */
+#define CAN_FILTER_FIFO0 (0x00000000U) /*!< Filter FIFO 0 assignment for filter x */
+#define CAN_FILTER_FIFO1 (0x00000001U) /*!< Filter FIFO 1 assignment for filter x */
/**
* @}
*/
-/** @defgroup CAN_Identifier_Type CAN Identifier Type
+/** @defgroup CAN_identifier_type CAN Identifier Type
* @{
*/
-#define CAN_ID_STD ((uint32_t)0x00000000U) /*!< Standard Id */
-#define CAN_ID_EXT ((uint32_t)0x00000004U) /*!< Extended Id */
+#define CAN_ID_STD (0x00000000U) /*!< Standard Id */
+#define CAN_ID_EXT (0x00000004U) /*!< Extended Id */
/**
* @}
*/
@@ -379,17 +385,27 @@
/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
* @{
*/
-#define CAN_RTR_DATA ((uint32_t)0x00000000U) /*!< Data frame */
-#define CAN_RTR_REMOTE ((uint32_t)0x00000002U) /*!< Remote frame */
+#define CAN_RTR_DATA (0x00000000U) /*!< Data frame */
+#define CAN_RTR_REMOTE (0x00000002U) /*!< Remote frame */
/**
* @}
*/
-/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number Constants
+/** @defgroup CAN_receive_FIFO_number CAN Receive FIFO Number
* @{
*/
-#define CAN_FIFO0 ((uint8_t)0x00U) /*!< CAN FIFO 0 used to receive */
-#define CAN_FIFO1 ((uint8_t)0x01U) /*!< CAN FIFO 1 used to receive */
+#define CAN_RX_FIFO0 (0x00000000U) /*!< CAN receive FIFO 0 */
+#define CAN_RX_FIFO1 (0x00000001U) /*!< CAN receive FIFO 1 */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Tx_Mailboxes CAN Tx Mailboxes
+ * @{
+ */
+#define CAN_TX_MAILBOX0 (0x00000001U) /*!< Tx Mailbox 0 */
+#define CAN_TX_MAILBOX1 (0x00000002U) /*!< Tx Mailbox 1 */
+#define CAN_TX_MAILBOX2 (0x00000004U) /*!< Tx Mailbox 2 */
/**
* @}
*/
@@ -397,80 +413,72 @@
/** @defgroup CAN_flags CAN Flags
* @{
*/
-/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
- and CAN_ClearFlag() functions. */
-/* If the flag is 0x1XXXXXXX, it means that it can only be used with
- CAN_GetFlagStatus() function. */
-
/* Transmit Flags */
-#define CAN_FLAG_RQCP0 ((uint32_t)0x00000500U) /*!< Request MailBox0 flag */
-#define CAN_FLAG_RQCP1 ((uint32_t)0x00000508U) /*!< Request MailBox1 flag */
-#define CAN_FLAG_RQCP2 ((uint32_t)0x00000510U) /*!< Request MailBox2 flag */
-#define CAN_FLAG_TXOK0 ((uint32_t)0x00000501U) /*!< Transmission OK MailBox0 flag */
-#define CAN_FLAG_TXOK1 ((uint32_t)0x00000509U) /*!< Transmission OK MailBox1 flag */
-#define CAN_FLAG_TXOK2 ((uint32_t)0x00000511U) /*!< Transmission OK MailBox2 flag */
-#define CAN_FLAG_TME0 ((uint32_t)0x0000051AU) /*!< Transmit mailbox 0 empty flag */
-#define CAN_FLAG_TME1 ((uint32_t)0x0000051BU) /*!< Transmit mailbox 0 empty flag */
-#define CAN_FLAG_TME2 ((uint32_t)0x0000051CU) /*!< Transmit mailbox 0 empty flag */
+#define CAN_FLAG_RQCP0 (0x00000500U) /*!< Request complete MailBox 0 flag */
+#define CAN_FLAG_TXOK0 (0x00000501U) /*!< Transmission OK MailBox 0 flag */
+#define CAN_FLAG_ALST0 (0x00000502U) /*!< Arbitration Lost MailBox 0 flag */
+#define CAN_FLAG_TERR0 (0x00000503U) /*!< Transmission error MailBox 0 flag */
+#define CAN_FLAG_RQCP1 (0x00000508U) /*!< Request complete MailBox1 flag */
+#define CAN_FLAG_TXOK1 (0x00000509U) /*!< Transmission OK MailBox 1 flag */
+#define CAN_FLAG_ALST1 (0x0000050AU) /*!< Arbitration Lost MailBox 1 flag */
+#define CAN_FLAG_TERR1 (0x0000050BU) /*!< Transmission error MailBox 1 flag */
+#define CAN_FLAG_RQCP2 (0x00000510U) /*!< Request complete MailBox2 flag */
+#define CAN_FLAG_TXOK2 (0x00000511U) /*!< Transmission OK MailBox 2 flag */
+#define CAN_FLAG_ALST2 (0x00000512U) /*!< Arbitration Lost MailBox 2 flag */
+#define CAN_FLAG_TERR2 (0x00000513U) /*!< Transmission error MailBox 2 flag */
+#define CAN_FLAG_TME0 (0x0000051AU) /*!< Transmit mailbox 0 empty flag */
+#define CAN_FLAG_TME1 (0x0000051BU) /*!< Transmit mailbox 1 empty flag */
+#define CAN_FLAG_TME2 (0x0000051CU) /*!< Transmit mailbox 2 empty flag */
+#define CAN_FLAG_LOW0 (0x0000051DU) /*!< Lowest priority mailbox 0 flag */
+#define CAN_FLAG_LOW1 (0x0000051EU) /*!< Lowest priority mailbox 1 flag */
+#define CAN_FLAG_LOW2 (0x0000051FU) /*!< Lowest priority mailbox 2 flag */
/* Receive Flags */
-#define CAN_FLAG_FF0 ((uint32_t)0x00000203U) /*!< FIFO 0 Full flag */
-#define CAN_FLAG_FOV0 ((uint32_t)0x00000204U) /*!< FIFO 0 Overrun flag */
-
-#define CAN_FLAG_FF1 ((uint32_t)0x00000403U) /*!< FIFO 1 Full flag */
-#define CAN_FLAG_FOV1 ((uint32_t)0x00000404U) /*!< FIFO 1 Overrun flag */
+#define CAN_FLAG_FF0 (0x00000203U) /*!< RX FIFO 0 Full flag */
+#define CAN_FLAG_FOV0 (0x00000204U) /*!< RX FIFO 0 Overrun flag */
+#define CAN_FLAG_FF1 (0x00000403U) /*!< RX FIFO 1 Full flag */
+#define CAN_FLAG_FOV1 (0x00000404U) /*!< RX FIFO 1 Overrun flag */
/* Operating Mode Flags */
-#define CAN_FLAG_INAK ((uint32_t)0x00000100U) /*!< Initialization acknowledge flag */
-#define CAN_FLAG_SLAK ((uint32_t)0x00000101U) /*!< Sleep acknowledge flag */
-#define CAN_FLAG_ERRI ((uint32_t)0x00000102U) /*!< Error flag */
-#define CAN_FLAG_WKU ((uint32_t)0x00000103U) /*!< Wake up flag */
-#define CAN_FLAG_SLAKI ((uint32_t)0x00000104U) /*!< Sleep acknowledge flag */
-
-/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
- In this case the SLAK bit can be polled.*/
+#define CAN_FLAG_INAK (0x00000100U) /*!< Initialization acknowledge flag */
+#define CAN_FLAG_SLAK (0x00000101U) /*!< Sleep acknowledge flag */
+#define CAN_FLAG_ERRI (0x00000102U) /*!< Error flag */
+#define CAN_FLAG_WKU (0x00000103U) /*!< Wake up interrupt flag */
+#define CAN_FLAG_SLAKI (0x00000104U) /*!< Sleep acknowledge interrupt flag */
/* Error Flags */
-#define CAN_FLAG_EWG ((uint32_t)0x00000300U) /*!< Error warning flag */
-#define CAN_FLAG_EPV ((uint32_t)0x00000301U) /*!< Error passive flag */
-#define CAN_FLAG_BOF ((uint32_t)0x00000302U) /*!< Bus-Off flag */
+#define CAN_FLAG_EWG (0x00000300U) /*!< Error warning flag */
+#define CAN_FLAG_EPV (0x00000301U) /*!< Error passive flag */
+#define CAN_FLAG_BOF (0x00000302U) /*!< Bus-Off flag */
/**
* @}
*/
+
/** @defgroup CAN_Interrupts CAN Interrupts
* @{
*/
-#define CAN_IT_TME ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */
+/* Transmit Interrupt */
+#define CAN_IT_TX_MAILBOX_EMPTY ((uint32_t)CAN_IER_TMEIE) /*!< Transmit mailbox empty interrupt */
/* Receive Interrupts */
-#define CAN_IT_FMP0 ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */
-#define CAN_IT_FF0 ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */
-#define CAN_IT_FOV0 ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */
-#define CAN_IT_FMP1 ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */
-#define CAN_IT_FF1 ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */
-#define CAN_IT_FOV1 ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */
+#define CAN_IT_RX_FIFO0_MSG_PENDING ((uint32_t)CAN_IER_FMPIE0) /*!< FIFO 0 message pending interrupt */
+#define CAN_IT_RX_FIFO0_FULL ((uint32_t)CAN_IER_FFIE0) /*!< FIFO 0 full interrupt */
+#define CAN_IT_RX_FIFO0_OVERRUN ((uint32_t)CAN_IER_FOVIE0) /*!< FIFO 0 overrun interrupt */
+#define CAN_IT_RX_FIFO1_MSG_PENDING ((uint32_t)CAN_IER_FMPIE1) /*!< FIFO 1 message pending interrupt */
+#define CAN_IT_RX_FIFO1_FULL ((uint32_t)CAN_IER_FFIE1) /*!< FIFO 1 full interrupt */
+#define CAN_IT_RX_FIFO1_OVERRUN ((uint32_t)CAN_IER_FOVIE1) /*!< FIFO 1 overrun interrupt */
/* Operating Mode Interrupts */
-#define CAN_IT_WKU ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */
-#define CAN_IT_SLK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */
+#define CAN_IT_WAKEUP ((uint32_t)CAN_IER_WKUIE) /*!< Wake-up interrupt */
+#define CAN_IT_SLEEP_ACK ((uint32_t)CAN_IER_SLKIE) /*!< Sleep acknowledge interrupt */
/* Error Interrupts */
-#define CAN_IT_EWG ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */
-#define CAN_IT_EPV ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */
-#define CAN_IT_BOF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */
-#define CAN_IT_LEC ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
-#define CAN_IT_ERR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */
-/**
- * @}
- */
-
-/** @defgroup CAN_Mailboxes_Definition CAN Mailboxes Definition
- * @{
- */
-#define CAN_TXMAILBOX_0 ((uint8_t)0x00U)
-#define CAN_TXMAILBOX_1 ((uint8_t)0x01U)
-#define CAN_TXMAILBOX_2 ((uint8_t)0x02U)
+#define CAN_IT_ERROR_WARNING ((uint32_t)CAN_IER_EWGIE) /*!< Error warning interrupt */
+#define CAN_IT_ERROR_PASSIVE ((uint32_t)CAN_IER_EPVIE) /*!< Error passive interrupt */
+#define CAN_IT_BUSOFF ((uint32_t)CAN_IER_BOFIE) /*!< Bus-off interrupt */
+#define CAN_IT_LAST_ERROR_CODE ((uint32_t)CAN_IER_LECIE) /*!< Last error code interrupt */
+#define CAN_IT_ERROR ((uint32_t)CAN_IER_ERRIE) /*!< Error Interrupt */
/**
* @}
*/
@@ -479,213 +487,198 @@
* @}
*/
-/* Exported macro ------------------------------------------------------------*/
+/* Exported macros -----------------------------------------------------------*/
/** @defgroup CAN_Exported_Macros CAN Exported Macros
* @{
*/
-/** @brief Reset CAN handle state
- * @param __HANDLE__: specifies the CAN Handle.
+/** @brief Reset CAN handle state
+ * @param __HANDLE__ CAN handle.
* @retval None
*/
#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
/**
* @brief Enable the specified CAN interrupts.
- * @param __HANDLE__: CAN handle
- * @param __INTERRUPT__: CAN Interrupt
+ * @param __HANDLE__ CAN handle.
+ * @param __INTERRUPT__ CAN Interrupt sources to enable.
+ * This parameter can be any combination of @arg CAN_Interrupts
* @retval None
*/
#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
/**
* @brief Disable the specified CAN interrupts.
- * @param __HANDLE__: CAN handle
- * @param __INTERRUPT__: CAN Interrupt
+ * @param __HANDLE__ CAN handle.
+ * @param __INTERRUPT__ CAN Interrupt sources to disable.
+ * This parameter can be any combination of @arg CAN_Interrupts
* @retval None
*/
#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
-/**
- * @brief Return the number of pending received messages.
- * @param __HANDLE__: CAN handle
- * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
- * @retval The number of pending message.
+/** @brief Check if the specified CAN interrupt source is enabled or disabled.
+ * @param __HANDLE__ specifies the CAN Handle.
+ * @param __INTERRUPT__ specifies the CAN interrupt source to check.
+ * This parameter can be a value of @arg CAN_Interrupts
+ * @retval The state of __IT__ (TRUE or FALSE).
*/
-#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
-((uint8_t)((__HANDLE__)->Instance->RF0R&(uint32_t)0x03)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&(uint32_t)0x03)))
+#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) & (__INTERRUPT__))
/** @brief Check whether the specified CAN flag is set or not.
- * @param __HANDLE__: CAN Handle
- * @param __FLAG__: specifies the flag to check.
- * This parameter can be one of the following values:
- * @arg CAN_TSR_RQCP0: Request MailBox0 Flag
- * @arg CAN_TSR_RQCP1: Request MailBox1 Flag
- * @arg CAN_TSR_RQCP2: Request MailBox2 Flag
- * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
- * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
- * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
- * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
- * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
- * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
- * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
- * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
- * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
- * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
- * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
- * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
- * @arg CAN_FLAG_WKU: Wake up Flag
- * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
- * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
- * @arg CAN_FLAG_EWG: Error Warning Flag
- * @arg CAN_FLAG_EPV: Error Passive Flag
- * @arg CAN_FLAG_BOF: Bus-Off Flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
+ * @param __HANDLE__ specifies the CAN Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of @arg CAN_flags
+ * @retval The state of __FLAG__ (TRUE or FALSE).
*/
#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
-((((__FLAG__) >> 8) == 5)? ((((__HANDLE__)->Instance->TSR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8) == 2)? ((((__HANDLE__)->Instance->RF0R) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8) == 4)? ((((__HANDLE__)->Instance->RF1R) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8) == 1)? ((((__HANDLE__)->Instance->MSR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))): \
- ((((__HANDLE__)->Instance->ESR) & (1 << ((__FLAG__) & CAN_FLAG_MASK))) == (1 << ((__FLAG__) & CAN_FLAG_MASK))))
+ ((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 3U)? ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)
/** @brief Clear the specified CAN pending flag.
- * @param __HANDLE__: CAN Handle.
- * @param __FLAG__: specifies the flag to check.
+ * @param __HANDLE__ specifies the CAN Handle.
+ * @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
- * @arg CAN_TSR_RQCP0: Request MailBox0 Flag
- * @arg CAN_TSR_RQCP1: Request MailBox1 Flag
- * @arg CAN_TSR_RQCP2: Request MailBox2 Flag
- * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
- * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
- * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
- * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
- * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
- * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
- * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
- * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
- * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
- * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
- * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
- * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
- * @arg CAN_FLAG_WKU: Wake up Flag
- * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
- * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
- * @retval The new state of __FLAG__ (TRUE or FALSE).
+ * @arg CAN_FLAG_RQCP0: Request complete MailBox 0 Flag
+ * @arg CAN_FLAG_TXOK0: Transmission OK MailBox 0 Flag
+ * @arg CAN_FLAG_ALST0: Arbitration Lost MailBox 0 Flag
+ * @arg CAN_FLAG_TERR0: Transmission error MailBox 0 Flag
+ * @arg CAN_FLAG_RQCP1: Request complete MailBox 1 Flag
+ * @arg CAN_FLAG_TXOK1: Transmission OK MailBox 1 Flag
+ * @arg CAN_FLAG_ALST1: Arbitration Lost MailBox 1 Flag
+ * @arg CAN_FLAG_TERR1: Transmission error MailBox 1 Flag
+ * @arg CAN_FLAG_RQCP2: Request complete MailBox 2 Flag
+ * @arg CAN_FLAG_TXOK2: Transmission OK MailBox 2 Flag
+ * @arg CAN_FLAG_ALST2: Arbitration Lost MailBox 2 Flag
+ * @arg CAN_FLAG_TERR2: Transmission error MailBox 2 Flag
+ * @arg CAN_FLAG_FF0: RX FIFO 0 Full Flag
+ * @arg CAN_FLAG_FOV0: RX FIFO 0 Overrun Flag
+ * @arg CAN_FLAG_FF1: RX FIFO 1 Full Flag
+ * @arg CAN_FLAG_FOV1: RX FIFO 1 Overrun Flag
+ * @arg CAN_FLAG_WKUI: Wake up Interrupt Flag
+ * @arg CAN_FLAG_SLAKI: Sleep acknowledge Interrupt Flag
+ * @retval None
*/
#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
-((((__FLAG__) >> 8) == 5)? (((__HANDLE__)->Instance->TSR) = ((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8) == 2)? (((__HANDLE__)->Instance->RF0R) = ((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__FLAG__) >> 8) == 4)? (((__HANDLE__)->Instance->RF1R) = ((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))): \
- (((__HANDLE__)->Instance->MSR) = ((uint32_t)1 << ((__FLAG__) & CAN_FLAG_MASK))))
-
-/** @brief Check if the specified CAN interrupt source is enabled or disabled.
- * @param __HANDLE__: CAN Handle
- * @param __INTERRUPT__: specifies the CAN interrupt source to check.
- * This parameter can be one of the following values:
- * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
- * @arg CAN_IT_FMP0: FIFO0 message pending interrupt enable
- * @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable
- * @retval The new state of __IT__ (TRUE or FALSE).
- */
-#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+ ((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 1U)? (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): 0U)
/**
- * @brief Check the transmission status of a CAN Frame.
- * @param __HANDLE__: CAN Handle
- * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
- * @retval The new status of transmission (TRUE or FALSE).
- */
-#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\
-(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\
- ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\
- ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)))
-
-/**
- * @brief Release the specified receive FIFO.
- * @param __HANDLE__: CAN handle
- * @param __FIFONUMBER__: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
- * @retval None
- */
-#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
-((__HANDLE__)->Instance->RF0R = CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R = CAN_RF1R_RFOM1))
-
-/**
- * @brief Cancel a transmit request.
- * @param __HANDLE__: CAN Handle
- * @param __TRANSMITMAILBOX__: the number of the mailbox that is used for transmission.
- * @retval None
- */
-#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
-(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ0) :\
- ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ1) :\
- ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ2))
-
-/**
- * @brief Enable or disable the DBG Freeze for CAN.
- * @param __HANDLE__: CAN Handle
- * @param __NEWSTATE__: new state of the CAN peripheral.
- * This parameter can be: ENABLE (CAN reception/transmission is frozen
- * during debug. Reception FIFOs can still be accessed/controlled normally)
- * or DISABLE (CAN is working during debug).
- * @retval None
- */
-#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
-((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))
-
-/**
- * @}
- */
+ * @}
+ */
/* Exported functions --------------------------------------------------------*/
-/** @addtogroup CAN_Exported_Functions
+/** @addtogroup CAN_Exported_Functions CAN Exported Functions
* @{
*/
-/** @addtogroup CAN_Exported_Functions_Group1
- * @{
- */
-/* Initialization/de-initialization functions ***********************************/
-HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);
-HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);
-HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);
-void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
-void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
+/** @addtogroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ * @{
+ */
+
+/* Initialization and de-initialization functions *****************************/
+HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef *hcan);
+void HAL_CAN_MspInit(CAN_HandleTypeDef *hcan);
+void HAL_CAN_MspDeInit(CAN_HandleTypeDef *hcan);
+
/**
- * @}
- */
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group2 Configuration functions
+ * @brief Configuration functions
+ * @{
+ */
+
+/* Configuration functions ****************************************************/
+HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef *hcan, CAN_FilterTypeDef *sFilterConfig);
-/** @addtogroup CAN_Exported_Functions_Group2
- * @{
- */
-/* I/O operation functions ******************************************************/
-HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);
-HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout);
-HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);
-HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group3 Control functions
+ * @brief Control functions
+ * @{
+ */
+
+/* Control functions **********************************************************/
+HAL_StatusTypeDef HAL_CAN_Start(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_Stop(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_RequestSleep(CAN_HandleTypeDef *hcan);
HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
-void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);
-void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);
-void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
-void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
-/**
- * @}
- */
-
-/** @addtogroup CAN_Exported_Functions_Group3
- * @{
- */
-/* Peripheral State functions ***************************************************/
-uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
-HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
-/**
- * @}
- */
+uint32_t HAL_CAN_IsSleepActive(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_AddTxMessage(CAN_HandleTypeDef *hcan, CAN_TxHeaderTypeDef *pHeader, uint8_t aData[], uint32_t *pTxMailbox);
+HAL_StatusTypeDef HAL_CAN_AbortTxRequest(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes);
+uint32_t HAL_CAN_GetTxMailboxesFreeLevel(CAN_HandleTypeDef *hcan);
+uint32_t HAL_CAN_IsTxMessagePending(CAN_HandleTypeDef *hcan, uint32_t TxMailboxes);
+uint32_t HAL_CAN_GetTxTimestamp(CAN_HandleTypeDef *hcan, uint32_t TxMailbox);
+HAL_StatusTypeDef HAL_CAN_GetRxMessage(CAN_HandleTypeDef *hcan, uint32_t RxFifo, CAN_RxHeaderTypeDef *pHeader, uint8_t aData[]);
+uint32_t HAL_CAN_GetRxFifoFillLevel(CAN_HandleTypeDef *hcan, uint32_t RxFifo);
/**
- * @}
- */
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group4 Interrupts management
+ * @brief Interrupts management
+ * @{
+ */
+/* Interrupts management ******************************************************/
+HAL_StatusTypeDef HAL_CAN_ActivateNotification(CAN_HandleTypeDef *hcan, uint32_t ActiveITs);
+HAL_StatusTypeDef HAL_CAN_DeactivateNotification(CAN_HandleTypeDef *hcan, uint32_t InactiveITs);
+void HAL_CAN_IRQHandler(CAN_HandleTypeDef *hcan);
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group5 Callback functions
+ * @brief Callback functions
+ * @{
+ */
+/* Callbacks functions ********************************************************/
+
+void HAL_CAN_TxMailbox0CompleteCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_TxMailbox1CompleteCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_TxMailbox2CompleteCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_TxMailbox0AbortCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_TxMailbox1AbortCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_TxMailbox2AbortCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_RxFifo0MsgPendingCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_RxFifo0FullCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_RxFifo1MsgPendingCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_RxFifo1FullCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_SleepCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_WakeUpFromRxMsgCallback(CAN_HandleTypeDef *hcan);
+void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
+
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group6 Peripheral State and Error functions
+ * @brief CAN Peripheral State functions
+ * @{
+ */
+/* Peripheral State and Error functions ***************************************/
+HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef *hcan);
+uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_ResetError(CAN_HandleTypeDef *hcan);
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
/* Private types -------------------------------------------------------------*/
/** @defgroup CAN_Private_Types CAN Private Types
@@ -703,66 +696,80 @@
/**
* @}
- */
+ */
/* Private constants ---------------------------------------------------------*/
/** @defgroup CAN_Private_Constants CAN Private Constants
* @{
*/
-#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04U) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
-#define CAN_FLAG_MASK ((uint32_t)0x000000FFU)
+#define CAN_FLAG_MASK (0x000000FFU)
/**
* @}
*/
-/* Private macros ------------------------------------------------------------*/
+/* Private Macros -----------------------------------------------------------*/
/** @defgroup CAN_Private_Macros CAN Private Macros
* @{
*/
+
#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
((MODE) == CAN_MODE_LOOPBACK)|| \
((MODE) == CAN_MODE_SILENT) || \
((MODE) == CAN_MODE_SILENT_LOOPBACK))
-#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
+#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ) || \
((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
-#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
-#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
-#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
-#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
+#define IS_CAN_BS1(BS1) (((BS1) == CAN_BS1_1TQ) || ((BS1) == CAN_BS1_2TQ) || \
+ ((BS1) == CAN_BS1_3TQ) || ((BS1) == CAN_BS1_4TQ) || \
+ ((BS1) == CAN_BS1_5TQ) || ((BS1) == CAN_BS1_6TQ) || \
+ ((BS1) == CAN_BS1_7TQ) || ((BS1) == CAN_BS1_8TQ) || \
+ ((BS1) == CAN_BS1_9TQ) || ((BS1) == CAN_BS1_10TQ)|| \
+ ((BS1) == CAN_BS1_11TQ)|| ((BS1) == CAN_BS1_12TQ)|| \
+ ((BS1) == CAN_BS1_13TQ)|| ((BS1) == CAN_BS1_14TQ)|| \
+ ((BS1) == CAN_BS1_15TQ)|| ((BS1) == CAN_BS1_16TQ))
+#define IS_CAN_BS2(BS2) (((BS2) == CAN_BS2_1TQ) || ((BS2) == CAN_BS2_2TQ) || \
+ ((BS2) == CAN_BS2_3TQ) || ((BS2) == CAN_BS2_4TQ) || \
+ ((BS2) == CAN_BS2_5TQ) || ((BS2) == CAN_BS2_6TQ) || \
+ ((BS2) == CAN_BS2_7TQ) || ((BS2) == CAN_BS2_8TQ))
+#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U))
+#define IS_CAN_FILTER_ID_HALFWORD(HALFWORD) ((HALFWORD) <= 0xFFFFU)
+#define IS_CAN_FILTER_BANK_DUAL(BANK) ((BANK) <= 27U)
+#define IS_CAN_FILTER_BANK_SINGLE(BANK) ((BANK) <= 13U)
#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
((MODE) == CAN_FILTERMODE_IDLIST))
#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
((SCALE) == CAN_FILTERSCALE_32BIT))
#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
((FIFO) == CAN_FILTER_FIFO1))
-#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28)
-
-#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
-#define IS_CAN_STDID(STDID) ((STDID) <= ((uint32_t)0x7FF))
-#define IS_CAN_EXTID(EXTID) ((EXTID) <= ((uint32_t)0x1FFFFFFF))
-#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
-
+#define IS_CAN_TX_MAILBOX(TRANSMITMAILBOX) (((TRANSMITMAILBOX) == CAN_TX_MAILBOX0 ) || \
+ ((TRANSMITMAILBOX) == CAN_TX_MAILBOX1 ) || \
+ ((TRANSMITMAILBOX) == CAN_TX_MAILBOX2 ))
+#define IS_CAN_TX_MAILBOX_LIST(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= (CAN_TX_MAILBOX0 | CAN_TX_MAILBOX1 | CAN_TX_MAILBOX2))
+#define IS_CAN_STDID(STDID) ((STDID) <= 0x7FFU)
+#define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU)
+#define IS_CAN_DLC(DLC) ((DLC) <= 8U)
#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
((IDTYPE) == CAN_ID_EXT))
#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
-#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
+#define IS_CAN_RX_FIFO(FIFO) (((FIFO) == CAN_RX_FIFO0) || ((FIFO) == CAN_RX_FIFO1))
+#define IS_CAN_IT(IT) ((IT) <= (CAN_IT_TX_MAILBOX_EMPTY | CAN_IT_RX_FIFO0_MSG_PENDING | \
+ CAN_IT_RX_FIFO0_FULL | CAN_IT_RX_FIFO0_OVERRUN | \
+ CAN_IT_RX_FIFO1_MSG_PENDING | CAN_IT_RX_FIFO1_FULL | \
+ CAN_IT_RX_FIFO1_OVERRUN | CAN_IT_WAKEUP | \
+ CAN_IT_SLEEP_ACK | CAN_IT_ERROR_WARNING | \
+ CAN_IT_ERROR_PASSIVE | CAN_IT_BUSOFF | \
+ CAN_IT_LAST_ERROR_CODE | CAN_IT_ERROR))
+
+/**
+ * @}
+ */
+/* End of private macros -----------------------------------------------------*/
/**
* @}
*/
-/* Private functions ---------------------------------------------------------*/
-/** @defgroup CAN_Private_Functions CAN Private Functions
- * @{
- */
-/**
- * @}
- */
-/**
- * @}
- */
-
+#endif /* CAN1 */
/**
* @}
*/
@@ -771,7 +778,7 @@
}
#endif
-#endif /* __STM32F7xx_CAN_H */
+#endif /* STM32F7xx_HAL_CAN_H */
/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_can_legacy.c Tue Mar 20 16:56:18 2018 +0000
@@ -0,0 +1,1688 @@
+/**
+ ******************************************************************************
+ * @file stm32f7xx_hal_can.c
+ * @author MCD Application Team
+ * @brief CAN HAL module driver.
+ * This file provides firmware functions to manage the following
+ * functionalities of the Controller Area Network (CAN) peripheral:
+ * + Initialization and de-initialization functions
+ * + IO operation functions
+ * + Peripheral Control functions
+ * + Peripheral State and Error functions
+ *
+ @verbatim
+ ==============================================================================
+ ##### User NOTE #####
+ ==============================================================================
+ [..]
+ (#) This HAL CAN driver is deprecated, it contains some CAN Tx/Rx FIFO management limitations.
+ Another HAL CAN driver version has been designed with new API's, to fix these limitations.
+
+ ==============================================================================
+ ##### How to use this driver #####
+ ==============================================================================
+ [..]
+ (#) Enable the CAN controller interface clock using
+ __HAL_RCC_CAN1_CLK_ENABLE() for CAN1, __HAL_RCC_CAN2_CLK_ENABLE() for CAN2
+ and __HAL_RCC_CAN3_CLK_ENABLE() for CAN3
+ -@- In case you are using CAN2 only, you have to enable the CAN1 clock.
+
+ (#) CAN pins configuration
+ (++) Enable the clock for the CAN GPIOs using the following function:
+ __HAL_RCC_GPIOx_CLK_ENABLE()
+ (++) Connect and configure the involved CAN pins to AF9 using the
+ following function HAL_GPIO_Init()
+
+ (#) Initialize and configure the CAN using HAL_CAN_Init() function.
+
+ (#) Transmit the desired CAN frame using HAL_CAN_Transmit() function.
+
+ (#) Or transmit the desired CAN frame using HAL_CAN_Transmit_IT() function.
+
+ (#) Receive a CAN frame using HAL_CAN_Receive() function.
+
+ (#) Or receive a CAN frame using HAL_CAN_Receive_IT() function.
+
+ *** Polling mode IO operation ***
+ =================================
+ [..]
+ (+) Start the CAN peripheral transmission and wait the end of this operation
+ using HAL_CAN_Transmit(), at this stage user can specify the value of timeout
+ according to his end application
+ (+) Start the CAN peripheral reception and wait the end of this operation
+ using HAL_CAN_Receive(), at this stage user can specify the value of timeout
+ according to his end application
+
+ *** Interrupt mode IO operation ***
+ ===================================
+ [..]
+ (+) Start the CAN peripheral transmission using HAL_CAN_Transmit_IT()
+ (+) Start the CAN peripheral reception using HAL_CAN_Receive_IT()
+ (+) Use HAL_CAN_IRQHandler() called under the used CAN Interrupt subroutine
+ (+) At CAN end of transmission HAL_CAN_TxCpltCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_CAN_TxCpltCallback
+ (+) In case of CAN Error, HAL_CAN_ErrorCallback() function is executed and user can
+ add his own code by customization of function pointer HAL_CAN_ErrorCallback
+
+ *** CAN HAL driver macros list ***
+ =============================================
+ [..]
+ Below the list of most used macros in CAN HAL driver.
+
+ (+) __HAL_CAN_ENABLE_IT: Enable the specified CAN interrupts
+ (+) __HAL_CAN_DISABLE_IT: Disable the specified CAN interrupts
+ (+) __HAL_CAN_GET_IT_SOURCE: Check if the specified CAN interrupt source is enabled or disabled
+ (+) __HAL_CAN_CLEAR_FLAG: Clear the CAN's pending flags
+ (+) __HAL_CAN_GET_FLAG: Get the selected CAN's flag status
+
+ [..]
+ (@) You can refer to the CAN Legacy HAL driver header file for more useful macros
+
+ @endverbatim
+
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal.h"
+
+/** @addtogroup STM32F7xx_HAL_Driver
+ * @{
+ */
+
+/** @defgroup CAN CAN
+ * @brief CAN driver modules
+ * @{
+ */
+
+#ifdef HAL_CAN_LEGACY_MODULE_ENABLED
+#ifdef HAL_CAN_MODULE_ENABLED
+/* Select HAL CAN module in stm32f7xx_hal_conf.h file:
+ (#) HAL_CAN_MODULE_ENABLED for new HAL CAN driver fixing FIFO limitations
+ (#) HAL_CAN_LEGACY_MODULE_ENABLED for legacy HAL CAN driver */
+#error 'The HAL CAN driver cannot be used with its legacy, Please ensure to enable only one HAL CAN module at once in stm32f7xx_hal_conf.h file'
+#endif /* HAL_CAN_MODULE_ENABLED */
+
+#warning 'Legacy HAL CAN driver is enabled! It can be used with known limitations, refer to the release notes. However it is recommended to use rather the new HAL CAN driver'
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/** @addtogroup CAN_Private_Constants
+ * @{
+ */
+#define CAN_TIMEOUT_VALUE 10U
+/**
+ * @}
+ */
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/** @addtogroup CAN_Private_Functions
+ * @{
+ */
+static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber);
+static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan);
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @defgroup CAN_Exported_Functions CAN Exported Functions
+ * @{
+ */
+
+/** @defgroup CAN_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Initialization and de-initialization functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Initialize and configure the CAN.
+ (+) De-initialize the CAN.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initializes the CAN peripheral according to the specified
+ * parameters in the CAN_InitStruct.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan)
+{
+ uint32_t InitStatus = CAN_INITSTATUS_FAILED;
+ uint32_t tickstart = 0U;
+
+ /* Check CAN handle */
+ if(hcan == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TTCM));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.ABOM));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.AWUM));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.NART));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.RFLM));
+ assert_param(IS_FUNCTIONAL_STATE(hcan->Init.TXFP));
+ assert_param(IS_CAN_MODE(hcan->Init.Mode));
+ assert_param(IS_CAN_SJW(hcan->Init.SJW));
+ assert_param(IS_CAN_BS1(hcan->Init.BS1));
+ assert_param(IS_CAN_BS2(hcan->Init.BS2));
+ assert_param(IS_CAN_PRESCALER(hcan->Init.Prescaler));
+
+
+ if(hcan->State == HAL_CAN_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ hcan->Lock = HAL_UNLOCKED;
+ /* Init the low level hardware */
+ HAL_CAN_MspInit(hcan);
+ }
+
+ /* Initialize the CAN state*/
+ hcan->State = HAL_CAN_STATE_BUSY;
+
+ /* Exit from sleep mode */
+ hcan->Instance->MCR &= (~(uint32_t)CAN_MCR_SLEEP);
+
+ /* Request initialisation */
+ hcan->Instance->MCR |= CAN_MCR_INRQ ;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait the acknowledge */
+ while((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
+ {
+ if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE)
+ {
+ hcan->State= HAL_CAN_STATE_TIMEOUT;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Check acknowledge */
+ if ((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
+ {
+ /* Set the time triggered communication mode */
+ if (hcan->Init.TTCM == ENABLE)
+ {
+ hcan->Instance->MCR |= CAN_MCR_TTCM;
+ }
+ else
+ {
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TTCM;
+ }
+
+ /* Set the automatic bus-off management */
+ if (hcan->Init.ABOM == ENABLE)
+ {
+ hcan->Instance->MCR |= CAN_MCR_ABOM;
+ }
+ else
+ {
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_ABOM;
+ }
+
+ /* Set the automatic wake-up mode */
+ if (hcan->Init.AWUM == ENABLE)
+ {
+ hcan->Instance->MCR |= CAN_MCR_AWUM;
+ }
+ else
+ {
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_AWUM;
+ }
+
+ /* Set the no automatic retransmission */
+ if (hcan->Init.NART == ENABLE)
+ {
+ hcan->Instance->MCR |= CAN_MCR_NART;
+ }
+ else
+ {
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_NART;
+ }
+
+ /* Set the receive FIFO locked mode */
+ if (hcan->Init.RFLM == ENABLE)
+ {
+ hcan->Instance->MCR |= CAN_MCR_RFLM;
+ }
+ else
+ {
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_RFLM;
+ }
+
+ /* Set the transmit FIFO priority */
+ if (hcan->Init.TXFP == ENABLE)
+ {
+ hcan->Instance->MCR |= CAN_MCR_TXFP;
+ }
+ else
+ {
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_TXFP;
+ }
+
+ /* Set the bit timing register */
+ hcan->Instance->BTR = (uint32_t)((uint32_t)hcan->Init.Mode) | \
+ ((uint32_t)hcan->Init.SJW) | \
+ ((uint32_t)hcan->Init.BS1) | \
+ ((uint32_t)hcan->Init.BS2) | \
+ ((uint32_t)hcan->Init.Prescaler - 1U);
+
+ /* Request leave initialisation */
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_INRQ;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait the acknowledge */
+ while((hcan->Instance->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
+ {
+ if((HAL_GetTick() - tickstart ) > CAN_TIMEOUT_VALUE)
+ {
+ hcan->State= HAL_CAN_STATE_TIMEOUT;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Check acknowledged */
+ if ((hcan->Instance->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
+ {
+ InitStatus = CAN_INITSTATUS_SUCCESS;
+ }
+ }
+
+ if(InitStatus == CAN_INITSTATUS_SUCCESS)
+ {
+ /* Set CAN error code to none */
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+
+ /* Initialize the CAN state */
+ hcan->State = HAL_CAN_STATE_READY;
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Initialize the CAN state */
+ hcan->State = HAL_CAN_STATE_ERROR;
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Configures the CAN reception filter according to the specified
+ * parameters in the CAN_FilterInitStruct.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param sFilterConfig pointer to a CAN_FilterConfTypeDef structure that
+ * contains the filter configuration information.
+ * @retval None
+ */
+HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig)
+{
+ uint32_t filternbrbitpos = 0U;
+ CAN_TypeDef *can_ip;
+
+#if !defined(CAN3)
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+#endif /* CAN3 */
+
+ /* Check the parameters */
+ assert_param(IS_CAN_FILTER_NUMBER(sFilterConfig->FilterNumber));
+ assert_param(IS_CAN_FILTER_MODE(sFilterConfig->FilterMode));
+ assert_param(IS_CAN_FILTER_SCALE(sFilterConfig->FilterScale));
+ assert_param(IS_CAN_FILTER_FIFO(sFilterConfig->FilterFIFOAssignment));
+ assert_param(IS_FUNCTIONAL_STATE(sFilterConfig->FilterActivation));
+ assert_param(IS_CAN_BANKNUMBER(sFilterConfig->BankNumber));
+
+ filternbrbitpos = 1U << sFilterConfig->FilterNumber;
+#if defined (CAN3)
+ /* Check the CAN instance */
+ if(hcan->Instance == CAN3)
+ {
+ can_ip = CAN3;
+ }
+ else
+ {
+ can_ip = CAN1;
+ }
+#else
+ can_ip = CAN1;
+#endif
+
+ /* Initialisation mode for the filter */
+ can_ip->FMR |= (uint32_t)CAN_FMR_FINIT;
+
+#if defined (CAN2)
+ /* Select the start slave bank */
+ can_ip->FMR &= ~((uint32_t)CAN_FMR_CAN2SB);
+ can_ip->FMR |= (uint32_t)(sFilterConfig->BankNumber << 8U);
+#endif
+
+ /* Filter Deactivation */
+ can_ip->FA1R &= ~(uint32_t)filternbrbitpos;
+
+ /* Filter Scale */
+ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_16BIT)
+ {
+ /* 16-bit scale for the filter */
+ can_ip->FS1R &= ~(uint32_t)filternbrbitpos;
+
+ /* First 16-bit identifier and First 16-bit mask */
+ /* Or First 16-bit identifier and Second 16-bit identifier */
+ can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow) << 16U) |
+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
+
+ /* Second 16-bit identifier and Second 16-bit mask */
+ /* Or Third 16-bit identifier and Fourth 16-bit identifier */
+ can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh);
+ }
+
+ if (sFilterConfig->FilterScale == CAN_FILTERSCALE_32BIT)
+ {
+ /* 32-bit scale for the filter */
+ can_ip->FS1R |= filternbrbitpos;
+
+ /* 32-bit identifier or First 32-bit identifier */
+ can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR1 =
+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdHigh) << 16U) |
+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterIdLow);
+ /* 32-bit mask or Second 32-bit identifier */
+ can_ip->sFilterRegister[sFilterConfig->FilterNumber].FR2 =
+ ((0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdHigh) << 16U) |
+ (0x0000FFFFU & (uint32_t)sFilterConfig->FilterMaskIdLow);
+ }
+
+ /* Filter Mode */
+ if (sFilterConfig->FilterMode == CAN_FILTERMODE_IDMASK)
+ {
+ /*Id/Mask mode for the filter*/
+ can_ip->FM1R &= ~(uint32_t)filternbrbitpos;
+ }
+ else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
+ {
+ /*Identifier list mode for the filter*/
+ can_ip->FM1R |= (uint32_t)filternbrbitpos;
+ }
+
+ /* Filter FIFO assignment */
+ if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO0)
+ {
+ /* FIFO 0 assignation for the filter */
+ can_ip->FFA1R &= ~(uint32_t)filternbrbitpos;
+ }
+
+ if (sFilterConfig->FilterFIFOAssignment == CAN_FILTER_FIFO1)
+ {
+ /* FIFO 1 assignation for the filter */
+ can_ip->FFA1R |= (uint32_t)filternbrbitpos;
+ }
+
+ /* Filter activation */
+ if (sFilterConfig->FilterActivation == ENABLE)
+ {
+ can_ip->FA1R |= filternbrbitpos;
+ }
+
+ /* Leave the initialisation mode for the filter */
+ can_ip->FMR &= ~((uint32_t)CAN_FMR_FINIT);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Deinitializes the CANx peripheral registers to their default reset values.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan)
+{
+ /* Check CAN handle */
+ if(hcan == NULL)
+ {
+ return HAL_ERROR;
+ }
+
+ /* Check the parameters */
+ assert_param(IS_CAN_ALL_INSTANCE(hcan->Instance));
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY;
+
+ /* DeInit the low level hardware */
+ HAL_CAN_MspDeInit(hcan);
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_RESET;
+
+ /* Release Lock */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Initializes the CAN MSP.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_MspInit could be implemented in the user file
+ */
+}
+
+/**
+ * @brief DeInitializes the CAN MSP.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_MspDeInit could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Exported_Functions_Group2 IO operation functions
+ * @brief IO operation functions
+ *
+@verbatim
+ ==============================================================================
+ ##### IO operation functions #####
+ ==============================================================================
+ [..] This section provides functions allowing to:
+ (+) Transmit a CAN frame message.
+ (+) Receive a CAN frame message.
+ (+) Enter CAN peripheral in sleep mode.
+ (+) Wake up the CAN peripheral from sleep mode.
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Initiates and transmits a CAN frame message.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param Timeout Specify Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef* hcan, uint32_t Timeout)
+{
+ uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
+ uint32_t tickstart = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
+ assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
+ assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
+
+ if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
+ ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
+ ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
+ {
+ /* Process locked */
+ __HAL_LOCK(hcan);
+
+ /* Change CAN state */
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_READY */
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ break;
+ }
+
+ /* Select one empty transmit mailbox */
+ if ((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
+ {
+ transmitmailbox = CAN_TXMAILBOX_0;
+ }
+ else if ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
+ {
+ transmitmailbox = CAN_TXMAILBOX_1;
+ }
+ else
+ {
+ transmitmailbox = CAN_TXMAILBOX_2;
+ }
+
+ /* Set up the Id */
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
+ if (hcan->pTxMsg->IDE == CAN_ID_STD)
+ {
+ assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21U) | \
+ hcan->pTxMsg->RTR);
+ }
+ else
+ {
+ assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3U) | \
+ hcan->pTxMsg->IDE | \
+ hcan->pTxMsg->RTR);
+ }
+
+ /* Set up the DLC */
+ hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= (uint32_t)0xFFFFFFF0U;
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
+
+ /* Set up the data field */
+ hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3U] << 24U) |
+ ((uint32_t)hcan->pTxMsg->Data[2U] << 16U) |
+ ((uint32_t)hcan->pTxMsg->Data[1U] << 8U) |
+ ((uint32_t)hcan->pTxMsg->Data[0U]));
+ hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7U] << 24U) |
+ ((uint32_t)hcan->pTxMsg->Data[6U] << 16U) |
+ ((uint32_t)hcan->pTxMsg->Data[5U] << 8U) |
+ ((uint32_t)hcan->pTxMsg->Data[4U]));
+ /* Request transmission */
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Check End of transmission flag */
+ while(!(__HAL_CAN_TRANSMIT_STATUS(hcan, transmitmailbox)))
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ hcan->State = HAL_CAN_STATE_TIMEOUT;
+ __HAL_CAN_CANCEL_TRANSMIT(hcan, transmitmailbox);
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Change CAN state */
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_BUSY_TX */
+ hcan->State = HAL_CAN_STATE_READY;
+ break;
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_ERROR;
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+}
+
+/**
+ * @brief Initiates and transmits a CAN frame message.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
+{
+ uint32_t transmitmailbox = CAN_TXSTATUS_NOMAILBOX;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_IDTYPE(hcan->pTxMsg->IDE));
+ assert_param(IS_CAN_RTR(hcan->pTxMsg->RTR));
+ assert_param(IS_CAN_DLC(hcan->pTxMsg->DLC));
+
+ if(((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0) || \
+ ((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1) || \
+ ((hcan->Instance->TSR&CAN_TSR_TME2) == CAN_TSR_TME2))
+ {
+ /* Process Locked */
+ __HAL_LOCK(hcan);
+
+ /* Select one empty transmit mailbox */
+ if((hcan->Instance->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
+ {
+ transmitmailbox = CAN_TXMAILBOX_0;
+ }
+ else if((hcan->Instance->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
+ {
+ transmitmailbox = CAN_TXMAILBOX_1;
+ }
+ else
+ {
+ transmitmailbox = CAN_TXMAILBOX_2;
+ }
+
+ /* Set up the Id */
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR &= CAN_TI0R_TXRQ;
+ if(hcan->pTxMsg->IDE == CAN_ID_STD)
+ {
+ assert_param(IS_CAN_STDID(hcan->pTxMsg->StdId));
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->StdId << 21U) | \
+ hcan->pTxMsg->RTR);
+ }
+ else
+ {
+ assert_param(IS_CAN_EXTID(hcan->pTxMsg->ExtId));
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= ((hcan->pTxMsg->ExtId << 3U) | \
+ hcan->pTxMsg->IDE | \
+ hcan->pTxMsg->RTR);
+ }
+
+ /* Set up the DLC */
+ hcan->pTxMsg->DLC &= (uint8_t)0x0000000F;
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR &= 0xFFFFFFF0U;
+ hcan->Instance->sTxMailBox[transmitmailbox].TDTR |= hcan->pTxMsg->DLC;
+
+ /* Set up the data field */
+ hcan->Instance->sTxMailBox[transmitmailbox].TDLR = (((uint32_t)hcan->pTxMsg->Data[3U] << 24U) |
+ ((uint32_t)hcan->pTxMsg->Data[2U] << 16U) |
+ ((uint32_t)hcan->pTxMsg->Data[1U] << 8U) |
+ ((uint32_t)hcan->pTxMsg->Data[0U]));
+ hcan->Instance->sTxMailBox[transmitmailbox].TDHR = (((uint32_t)hcan->pTxMsg->Data[7U] << 24U) |
+ ((uint32_t)hcan->pTxMsg->Data[6U] << 16U) |
+ ((uint32_t)hcan->pTxMsg->Data[5U] << 8U) |
+ ((uint32_t)hcan->pTxMsg->Data[4U]));
+
+ /* Change CAN state */
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_READY */
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ break;
+ }
+
+ /* Set CAN error code to none */
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Request transmission */
+ hcan->Instance->sTxMailBox[transmitmailbox].TIR |= CAN_TI0R_TXRQ;
+
+ /* Enable Error warning, Error passive, Bus-off,
+ Last error and Error Interrupts */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
+ CAN_IT_EPV |
+ CAN_IT_BOF |
+ CAN_IT_LEC |
+ CAN_IT_ERR |
+ CAN_IT_TME);
+ }
+ else
+ {
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_ERROR;
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Receives a correct CAN frame.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param FIFONumber FIFO Number value
+ * @param Timeout Specify Timeout value
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef* hcan, uint8_t FIFONumber, uint32_t Timeout)
+{
+ uint32_t tickstart = 0U;
+ CanRxMsgTypeDef* pRxMsg = NULL;
+
+ /* Check the parameters */
+ assert_param(IS_CAN_FIFO(FIFONumber));
+
+ /* Check if CAN state is not busy for RX FIFO0 */
+ if ((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
+ {
+ return HAL_BUSY;
+ }
+
+ /* Check if CAN state is not busy for RX FIFO1 */
+ if ((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hcan);
+
+ /* Change CAN state */
+ if (FIFONumber == CAN_FIFO0)
+ {
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_READY */
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
+ break;
+ }
+ }
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_READY */
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
+ break;
+ }
+ }
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Check pending message */
+ while(__HAL_CAN_MSG_PENDING(hcan, FIFONumber) == 0U)
+ {
+ /* Check for the Timeout */
+ if(Timeout != HAL_MAX_DELAY)
+ {
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
+ {
+ hcan->State = HAL_CAN_STATE_TIMEOUT;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+ return HAL_TIMEOUT;
+ }
+ }
+ }
+
+ /* Set RxMsg pointer */
+ if(FIFONumber == CAN_FIFO0)
+ {
+ pRxMsg = hcan->pRxMsg;
+ }
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ pRxMsg = hcan->pRx1Msg;
+ }
+
+ /* Get the Id */
+ pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+ if (pRxMsg->IDE == CAN_ID_STD)
+ {
+ pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
+ }
+ else
+ {
+ pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
+ }
+
+ pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+ /* Get the DLC */
+ pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
+ /* Get the FMI */
+ pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
+ /* Get the FIFONumber */
+ pRxMsg->FIFONumber = FIFONumber;
+ /* Get the data field */
+ pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
+ pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
+ pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
+ pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
+ pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
+ pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
+ pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
+ pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
+
+ /* Release the FIFO */
+ if(FIFONumber == CAN_FIFO0)
+ {
+ /* Release FIFO0 */
+ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
+ }
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ /* Release FIFO1 */
+ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
+ }
+
+ /* Change CAN state */
+ if (FIFONumber == CAN_FIFO0)
+ {
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+ break;
+ default: /* HAL_CAN_STATE_BUSY_RX0 */
+ hcan->State = HAL_CAN_STATE_READY;
+ break;
+ }
+ }
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+ break;
+ default: /* HAL_CAN_STATE_BUSY_RX1 */
+ hcan->State = HAL_CAN_STATE_READY;
+ break;
+ }
+ }
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Receives a correct CAN frame.
+ * @param hcan Pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param FIFONumber Specify the FIFO number
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
+{
+ /* Check the parameters */
+ assert_param(IS_CAN_FIFO(FIFONumber));
+
+ /* Check if CAN state is not busy for RX FIFO0 */
+ if((FIFONumber == CAN_FIFO0) && ((hcan->State == HAL_CAN_STATE_BUSY_RX0) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
+ {
+ return HAL_BUSY;
+ }
+
+ /* Check if CAN state is not busy for RX FIFO1 */
+ if((FIFONumber == CAN_FIFO1) && ((hcan->State == HAL_CAN_STATE_BUSY_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_RX0_RX1) || \
+ (hcan->State == HAL_CAN_STATE_BUSY_TX_RX0_RX1)))
+ {
+ return HAL_BUSY;
+ }
+
+ /* Process locked */
+ __HAL_LOCK(hcan);
+
+ /* Change CAN state */
+ if(FIFONumber == CAN_FIFO0)
+ {
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_READY */
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
+ break;
+ }
+ }
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_READY */
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
+ break;
+ }
+ }
+ /* Set CAN error code to none */
+ hcan->ErrorCode = HAL_CAN_ERROR_NONE;
+
+ /* Enable interrupts: */
+ /* - Enable Error warning Interrupt */
+ /* - Enable Error passive Interrupt */
+ /* - Enable Bus-off Interrupt */
+ /* - Enable Last error code Interrupt */
+ /* - Enable Error Interrupt */
+ /* - Enable Transmit mailbox empty Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_EWG |
+ CAN_IT_EPV |
+ CAN_IT_BOF |
+ CAN_IT_LEC |
+ CAN_IT_ERR |
+ CAN_IT_TME);
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ if(FIFONumber == CAN_FIFO0)
+ {
+ /* Enable FIFO 0 overrun and message pending Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0);
+ }
+ else
+ {
+ /* Enable FIFO 1 overrun and message pending Interrupt */
+ __HAL_CAN_ENABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1);
+ }
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Enters the Sleep (low power) mode.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef* hcan)
+{
+ uint32_t tickstart = 0U;
+
+ /* Process locked */
+ __HAL_LOCK(hcan);
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY;
+
+ /* Request Sleep mode */
+ hcan->Instance->MCR = (((hcan->Instance->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
+
+ /* Sleep mode status */
+ if ((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Wait the acknowledge */
+ while((hcan->Instance->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) != CAN_MSR_SLAK)
+ {
+ if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
+ {
+ hcan->State = HAL_CAN_STATE_TIMEOUT;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Wakes up the CAN peripheral from sleep mode, after that the CAN peripheral
+ * is in the normal mode.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status.
+ */
+HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef* hcan)
+{
+ uint32_t tickstart = 0U;
+
+ /* Process locked */
+ __HAL_LOCK(hcan);
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_BUSY;
+
+ /* Wake up request */
+ hcan->Instance->MCR &= ~(uint32_t)CAN_MCR_SLEEP;
+
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
+ /* Sleep mode status */
+ while((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
+ {
+ if((HAL_GetTick() - tickstart) > CAN_TIMEOUT_VALUE)
+ {
+ hcan->State= HAL_CAN_STATE_TIMEOUT;
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+ return HAL_TIMEOUT;
+ }
+ }
+ if((hcan->Instance->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)
+ {
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_ERROR;
+ }
+
+ /* Change CAN state */
+ hcan->State = HAL_CAN_STATE_READY;
+
+ /* Process unlocked */
+ __HAL_UNLOCK(hcan);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @brief Handles CAN interrupt request
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan)
+{
+ uint32_t tmp1 = 0U, tmp2 = 0U, tmp3 = 0U;
+ uint32_t errorcode = HAL_CAN_ERROR_NONE;
+
+ /* Check Overrun flag for FIFO0 */
+ tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV0);
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV0);
+ if(tmp1 && tmp2)
+ {
+ /* Set CAN error code to FOV0 error */
+ errorcode |= HAL_CAN_ERROR_FOV0;
+
+ /* Clear FIFO0 Overrun Flag */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV0);
+ }
+ /* Check Overrun flag for FIFO1 */
+ tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_FOV1);
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FOV1);
+
+ if(tmp1 && tmp2)
+ {
+ /* Set CAN error code to FOV1 error */
+ errorcode |= HAL_CAN_ERROR_FOV1;
+
+ /* Clear FIFO1 Overrun Flag */
+ __HAL_CAN_CLEAR_FLAG(hcan, CAN_FLAG_FOV1);
+ }
+
+ /* Check End of transmission flag */
+ if(__HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_TME))
+ {
+ tmp1 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_0);
+ tmp2 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_1);
+ tmp3 = __HAL_CAN_TRANSMIT_STATUS(hcan, CAN_TXMAILBOX_2);
+ if(tmp1 || tmp2 || tmp3)
+ {
+ tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK0);
+ tmp2 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK1);
+ tmp3 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_TXOK2);
+ /* Check Transmit success */
+ if(tmp1 || tmp2 || tmp3)
+ {
+ /* Call transmit function */
+ CAN_Transmit_IT(hcan);
+ }
+ else /* Transmit failure */
+ {
+ /* Set CAN error code to TXFAIL error */
+ errorcode |= HAL_CAN_ERROR_TXFAIL;
+ }
+
+ /* Clear transmission status flags (RQCPx and TXOKx) */
+ SET_BIT(hcan->Instance->TSR, CAN_TSR_RQCP0 | CAN_TSR_RQCP1 | CAN_TSR_RQCP2 | \
+ CAN_FLAG_TXOK0 | CAN_FLAG_TXOK1 | CAN_FLAG_TXOK2);
+ }
+ }
+
+ tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO0);
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP0);
+ /* Check End of reception flag for FIFO0 */
+ if((tmp1 != 0U) && tmp2)
+ {
+ /* Call receive function */
+ CAN_Receive_IT(hcan, CAN_FIFO0);
+ }
+
+ tmp1 = __HAL_CAN_MSG_PENDING(hcan, CAN_FIFO1);
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_FMP1);
+ /* Check End of reception flag for FIFO1 */
+ if((tmp1 != 0U) && tmp2)
+ {
+ /* Call receive function */
+ CAN_Receive_IT(hcan, CAN_FIFO1);
+ }
+
+ /* Set error code in handle */
+ hcan->ErrorCode |= errorcode;
+
+ tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EWG);
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EWG);
+ tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
+ /* Check Error Warning Flag */
+ if(tmp1 && tmp2 && tmp3)
+ {
+ /* Set CAN error code to EWG error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_EWG;
+ }
+
+ tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_EPV);
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_EPV);
+ tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
+ /* Check Error Passive Flag */
+ if(tmp1 && tmp2 && tmp3)
+ {
+ /* Set CAN error code to EPV error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_EPV;
+ }
+
+ tmp1 = __HAL_CAN_GET_FLAG(hcan, CAN_FLAG_BOF);
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_BOF);
+ tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
+ /* Check Bus-Off Flag */
+ if(tmp1 && tmp2 && tmp3)
+ {
+ /* Set CAN error code to BOF error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_BOF;
+ }
+
+ tmp1 = HAL_IS_BIT_CLR(hcan->Instance->ESR, CAN_ESR_LEC);
+ tmp2 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_LEC);
+ tmp3 = __HAL_CAN_GET_IT_SOURCE(hcan, CAN_IT_ERR);
+ /* Check Last error code Flag */
+ if((!tmp1) && tmp2 && tmp3)
+ {
+ tmp1 = (hcan->Instance->ESR) & CAN_ESR_LEC;
+ switch(tmp1)
+ {
+ case(CAN_ESR_LEC_0):
+ /* Set CAN error code to STF error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_STF;
+ break;
+ case(CAN_ESR_LEC_1):
+ /* Set CAN error code to FOR error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_FOR;
+ break;
+ case(CAN_ESR_LEC_1 | CAN_ESR_LEC_0):
+ /* Set CAN error code to ACK error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_ACK;
+ break;
+ case(CAN_ESR_LEC_2):
+ /* Set CAN error code to BR error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_BR;
+ break;
+ case(CAN_ESR_LEC_2 | CAN_ESR_LEC_0):
+ /* Set CAN error code to BD error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_BD;
+ break;
+ case(CAN_ESR_LEC_2 | CAN_ESR_LEC_1):
+ /* Set CAN error code to CRC error */
+ hcan->ErrorCode |= HAL_CAN_ERROR_CRC;
+ break;
+ default:
+ break;
+ }
+
+ /* Clear Last error code Flag */
+ hcan->Instance->ESR &= ~(CAN_ESR_LEC);
+ }
+
+ /* Call the Error call Back in case of Errors */
+ if(hcan->ErrorCode != HAL_CAN_ERROR_NONE)
+ {
+ /* Clear ERRI Flag */
+ hcan->Instance->MSR = CAN_MSR_ERRI;
+ /* Set the CAN state ready to be able to start again the process */
+ hcan->State = HAL_CAN_STATE_READY;
+
+ /* Disable interrupts: */
+ /* - Disable Error warning Interrupt */
+ /* - Disable Error passive Interrupt */
+ /* - Disable Bus-off Interrupt */
+ /* - Disable Last error code Interrupt */
+ /* - Disable Error Interrupt */
+ /* - Disable FIFO 0 message pending Interrupt */
+ /* - Disable FIFO 0 Overrun Interrupt */
+ /* - Disable FIFO 1 message pending Interrupt */
+ /* - Disable FIFO 1 Overrun Interrupt */
+ /* - Disable Transmit mailbox empty Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
+ CAN_IT_EPV |
+ CAN_IT_BOF |
+ CAN_IT_LEC |
+ CAN_IT_ERR |
+ CAN_IT_FMP0|
+ CAN_IT_FOV0|
+ CAN_IT_FMP1|
+ CAN_IT_FOV1|
+ CAN_IT_TME);
+
+ /* Call Error callback function */
+ HAL_CAN_ErrorCallback(hcan);
+ }
+}
+
+/**
+ * @brief Transmission complete callback in non blocking mode
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_TxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Transmission complete callback in non blocking mode
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_RxCpltCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Error CAN callback.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval None
+ */
+__weak void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hcan);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_CAN_ErrorCallback could be implemented in the user file
+ */
+}
+
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Exported_Functions_Group3 Peripheral State and Error functions
+ * @brief CAN Peripheral State functions
+ *
+@verbatim
+ ==============================================================================
+ ##### Peripheral State and Error functions #####
+ ==============================================================================
+ [..]
+ This subsection provides functions allowing to :
+ (+) Check the CAN state.
+ (+) Check CAN Errors detected during interrupt process
+
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief return the CAN state
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL state
+ */
+HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan)
+{
+ /* Return CAN state */
+ return hcan->State;
+}
+
+/**
+ * @brief Return the CAN error code
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval CAN Error Code
+ */
+uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan)
+{
+ return hcan->ErrorCode;
+}
+
+/**
+ * @}
+ */
+/**
+ * @brief Initiates and transmits a CAN frame message.
+ * @param hcan pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @retval HAL status
+ */
+static HAL_StatusTypeDef CAN_Transmit_IT(CAN_HandleTypeDef* hcan)
+{
+ /* Disable Transmit mailbox empty Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_TME);
+
+ if(hcan->State == HAL_CAN_STATE_BUSY_TX)
+ {
+ /* Disable Error warning, Error passive, Bus-off, Last error code
+ and Error Interrupts */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
+ CAN_IT_EPV |
+ CAN_IT_BOF |
+ CAN_IT_LEC |
+ CAN_IT_ERR );
+ }
+
+ /* Change CAN state */
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0_RX1;
+ break;
+ default: /* HAL_CAN_STATE_BUSY_TX */
+ hcan->State = HAL_CAN_STATE_READY;
+ break;
+ }
+
+ /* Transmission complete callback */
+ HAL_CAN_TxCpltCallback(hcan);
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Receives a correct CAN frame.
+ * @param hcan Pointer to a CAN_HandleTypeDef structure that contains
+ * the configuration information for the specified CAN.
+ * @param FIFONumber Specify the FIFO number
+ * @retval HAL status
+ * @retval None
+ */
+static HAL_StatusTypeDef CAN_Receive_IT(CAN_HandleTypeDef* hcan, uint8_t FIFONumber)
+{
+ uint32_t tmp1 = 0U;
+ CanRxMsgTypeDef* pRxMsg = NULL;
+
+ /* Set RxMsg pointer */
+ if(FIFONumber == CAN_FIFO0)
+ {
+ pRxMsg = hcan->pRxMsg;
+ }
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ pRxMsg = hcan->pRx1Msg;
+ }
+
+ /* Get the Id */
+ pRxMsg->IDE = (uint8_t)0x04 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+ if (pRxMsg->IDE == CAN_ID_STD)
+ {
+ pRxMsg->StdId = 0x000007FFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 21U);
+ }
+ else
+ {
+ pRxMsg->ExtId = 0x1FFFFFFFU & (hcan->Instance->sFIFOMailBox[FIFONumber].RIR >> 3U);
+ }
+
+ pRxMsg->RTR = (uint8_t)0x02 & hcan->Instance->sFIFOMailBox[FIFONumber].RIR;
+ /* Get the DLC */
+ pRxMsg->DLC = (uint8_t)0x0F & hcan->Instance->sFIFOMailBox[FIFONumber].RDTR;
+ /* Get the FIFONumber */
+ pRxMsg->FIFONumber = FIFONumber;
+ /* Get the FMI */
+ pRxMsg->FMI = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDTR >> 8U);
+ /* Get the data field */
+ pRxMsg->Data[0] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDLR;
+ pRxMsg->Data[1] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 8U);
+ pRxMsg->Data[2] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 16U);
+ pRxMsg->Data[3] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDLR >> 24U);
+ pRxMsg->Data[4] = (uint8_t)0xFF & hcan->Instance->sFIFOMailBox[FIFONumber].RDHR;
+ pRxMsg->Data[5] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 8U);
+ pRxMsg->Data[6] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 16U);
+ pRxMsg->Data[7] = (uint8_t)0xFF & (hcan->Instance->sFIFOMailBox[FIFONumber].RDHR >> 24U);
+ /* Release the FIFO */
+ /* Release FIFO0 */
+ if (FIFONumber == CAN_FIFO0)
+ {
+ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO0);
+
+ /* Disable FIFO 0 overrun and message pending Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV0 | CAN_IT_FMP0);
+ }
+ /* Release FIFO1 */
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ __HAL_CAN_FIFO_RELEASE(hcan, CAN_FIFO1);
+
+ /* Disable FIFO 1 overrun and message pending Interrupt */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_FOV1 | CAN_IT_FMP1);
+ }
+
+ tmp1 = hcan->State;
+ if((tmp1 == HAL_CAN_STATE_BUSY_RX0) || (tmp1 == HAL_CAN_STATE_BUSY_RX1))
+ {
+ /* Disable Error warning, Error passive, Bus-off, Last error code
+ and Error Interrupts */
+ __HAL_CAN_DISABLE_IT(hcan, CAN_IT_EWG |
+ CAN_IT_EPV |
+ CAN_IT_BOF |
+ CAN_IT_LEC |
+ CAN_IT_ERR);
+ }
+
+ /* Change CAN state */
+ if (FIFONumber == CAN_FIFO0)
+ {
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX_RX0):
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX1;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX1;
+ break;
+ default: /* HAL_CAN_STATE_BUSY_RX0 */
+ hcan->State = HAL_CAN_STATE_READY;
+ break;
+ }
+ }
+ else /* FIFONumber == CAN_FIFO1 */
+ {
+ switch(hcan->State)
+ {
+ case(HAL_CAN_STATE_BUSY_TX_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX;
+ break;
+ case(HAL_CAN_STATE_BUSY_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_RX0;
+ break;
+ case(HAL_CAN_STATE_BUSY_TX_RX0_RX1):
+ hcan->State = HAL_CAN_STATE_BUSY_TX_RX0;
+ break;
+ default: /* HAL_CAN_STATE_BUSY_RX1 */
+ hcan->State = HAL_CAN_STATE_READY;
+ break;
+ }
+ }
+
+ /* Receive complete callback */
+ HAL_CAN_RxCpltCallback(hcan);
+
+ /* Return function status */
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
+#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_can_legacy.h Tue Mar 20 16:56:18 2018 +0000
@@ -0,0 +1,777 @@
+/**
+ ******************************************************************************
+ * @file stm32f7xx_hal_can_legacy.h
+ * @author MCD Application Team
+ * @brief Header file of CAN HAL module.
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F7xx_HAL_CAN_LEGACY_H
+#define __STM32F7xx_HAL_CAN_LEGACY_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f7xx_hal_def.h"
+
+/** @addtogroup STM32F7xx_HAL_Driver
+ * @{
+ */
+
+/** @addtogroup CAN
+ * @{
+ */
+
+/* Exported types ------------------------------------------------------------*/
+/** @defgroup CAN_Exported_Types CAN Exported Types
+ * @{
+ */
+
+/**
+ * @brief HAL State structures definition
+ */
+typedef enum
+{
+ HAL_CAN_STATE_RESET = 0x00U, /*!< CAN not yet initialized or disabled */
+ HAL_CAN_STATE_READY = 0x01U, /*!< CAN initialized and ready for use */
+ HAL_CAN_STATE_BUSY = 0x02U, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_TX = 0x12U, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_RX0 = 0x22U, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_RX1 = 0x32U, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_TX_RX0 = 0x42U, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_TX_RX1 = 0x52U, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_RX0_RX1 = 0x62U, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_BUSY_TX_RX0_RX1 = 0x72U, /*!< CAN process is ongoing */
+ HAL_CAN_STATE_TIMEOUT = 0x03U, /*!< CAN in Timeout state */
+ HAL_CAN_STATE_ERROR = 0x04U /*!< CAN error state */
+
+}HAL_CAN_StateTypeDef;
+
+/**
+ * @brief CAN init structure definition
+ */
+typedef struct
+{
+ uint32_t Prescaler; /*!< Specifies the length of a time quantum.
+ This parameter must be a number between Min_Data = 1 and Max_Data = 1024 */
+
+ uint32_t Mode; /*!< Specifies the CAN operating mode.
+ This parameter can be a value of @ref CAN_operating_mode */
+
+ uint32_t SJW; /*!< Specifies the maximum number of time quanta
+ the CAN hardware is allowed to lengthen or
+ shorten a bit to perform resynchronization.
+ This parameter can be a value of @ref CAN_synchronisation_jump_width */
+
+ uint32_t BS1; /*!< Specifies the number of time quanta in Bit Segment 1.
+ This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_1 */
+
+ uint32_t BS2; /*!< Specifies the number of time quanta in Bit Segment 2.
+ This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
+
+ uint32_t TTCM; /*!< Enable or disable the time triggered communication mode.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ uint32_t ABOM; /*!< Enable or disable the automatic bus-off management.
+ This parameter can be set to ENABLE or DISABLE */
+
+ uint32_t AWUM; /*!< Enable or disable the automatic wake-up mode.
+ This parameter can be set to ENABLE or DISABLE */
+
+ uint32_t NART; /*!< Enable or disable the non-automatic retransmission mode.
+ This parameter can be set to ENABLE or DISABLE */
+
+ uint32_t RFLM; /*!< Enable or disable the receive FIFO Locked mode.
+ This parameter can be set to ENABLE or DISABLE */
+
+ uint32_t TXFP; /*!< Enable or disable the transmit FIFO priority.
+ This parameter can be set to ENABLE or DISABLE */
+}CAN_InitTypeDef;
+
+/**
+ * @brief CAN filter configuration structure definition
+ */
+typedef struct
+{
+ uint32_t FilterIdHigh; /*!< Specifies the filter identification number (MSBs for a 32-bit
+ configuration, first one for a 16-bit configuration).
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+ uint32_t FilterIdLow; /*!< Specifies the filter identification number (LSBs for a 32-bit
+ configuration, second one for a 16-bit configuration).
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+ uint32_t FilterMaskIdHigh; /*!< Specifies the filter mask number or identification number,
+ according to the mode (MSBs for a 32-bit configuration,
+ first one for a 16-bit configuration).
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+ uint32_t FilterMaskIdLow; /*!< Specifies the filter mask number or identification number,
+ according to the mode (LSBs for a 32-bit configuration,
+ second one for a 16-bit configuration).
+ This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
+
+ uint32_t FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
+ This parameter can be a value of @ref CAN_filter_FIFO */
+
+ uint32_t FilterNumber; /*!< Specifies the filter which will be initialized.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 27 */
+
+ uint32_t FilterMode; /*!< Specifies the filter mode to be initialized.
+ This parameter can be a value of @ref CAN_filter_mode */
+
+ uint32_t FilterScale; /*!< Specifies the filter scale.
+ This parameter can be a value of @ref CAN_filter_scale */
+
+ uint32_t FilterActivation; /*!< Enable or disable the filter.
+ This parameter can be set to ENABLE or DISABLE. */
+
+ uint32_t BankNumber; /*!< Select the start slave bank filter.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 28 */
+
+}CAN_FilterConfTypeDef;
+
+/**
+ * @brief CAN Tx message structure definition
+ */
+typedef struct
+{
+ uint32_t StdId; /*!< Specifies the standard identifier.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
+
+ uint32_t ExtId; /*!< Specifies the extended identifier.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
+
+ uint32_t IDE; /*!< Specifies the type of identifier for the message that will be transmitted.
+ This parameter can be a value of @ref CAN_Identifier_Type */
+
+ uint32_t RTR; /*!< Specifies the type of frame for the message that will be transmitted.
+ This parameter can be a value of @ref CAN_remote_transmission_request */
+
+ uint32_t DLC; /*!< Specifies the length of the frame that will be transmitted.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
+
+ uint8_t Data[8]; /*!< Contains the data to be transmitted.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
+
+}CanTxMsgTypeDef;
+
+/**
+ * @brief CAN Rx message structure definition
+ */
+typedef struct
+{
+ uint32_t StdId; /*!< Specifies the standard identifier.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x7FF */
+
+ uint32_t ExtId; /*!< Specifies the extended identifier.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0x1FFFFFFF */
+
+ uint32_t IDE; /*!< Specifies the type of identifier for the message that will be received.
+ This parameter can be a value of @ref CAN_Identifier_Type */
+
+ uint32_t RTR; /*!< Specifies the type of frame for the received message.
+ This parameter can be a value of @ref CAN_remote_transmission_request */
+
+ uint32_t DLC; /*!< Specifies the length of the frame that will be received.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 8 */
+
+ uint8_t Data[8]; /*!< Contains the data to be received.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
+
+ uint32_t FMI; /*!< Specifies the index of the filter the message stored in the mailbox passes through.
+ This parameter must be a number between Min_Data = 0 and Max_Data = 0xFF */
+
+ uint32_t FIFONumber; /*!< Specifies the receive FIFO number.
+ This parameter can be CAN_FIFO0 or CAN_FIFO1 */
+
+}CanRxMsgTypeDef;
+
+/**
+ * @brief CAN handle Structure definition
+ */
+typedef struct
+{
+ CAN_TypeDef *Instance; /*!< Register base address */
+
+ CAN_InitTypeDef Init; /*!< CAN required parameters */
+
+ CanTxMsgTypeDef* pTxMsg; /*!< Pointer to transmit structure */
+
+ CanRxMsgTypeDef* pRxMsg; /*!< Pointer to reception structure for RX FIFO0 msg */
+
+ CanRxMsgTypeDef* pRx1Msg; /*!< Pointer to reception structure for RX FIFO1 msg */
+
+ __IO HAL_CAN_StateTypeDef State; /*!< CAN communication state */
+
+ HAL_LockTypeDef Lock; /*!< CAN locking object */
+
+ __IO uint32_t ErrorCode; /*!< CAN Error code
+ This parameter can be a value of @ref CAN_Error_Code */
+}CAN_HandleTypeDef;
+
+/**
+ * @}
+ */
+
+/* Exported constants --------------------------------------------------------*/
+/** @defgroup CAN_Exported_Constants CAN Exported Constants
+ * @{
+ */
+
+/** @defgroup CAN_Error_Code CAN Error Code
+ * @{
+ */
+#define HAL_CAN_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_CAN_ERROR_EWG 0x00000001U /*!< EWG error */
+#define HAL_CAN_ERROR_EPV 0x00000002U /*!< EPV error */
+#define HAL_CAN_ERROR_BOF 0x00000004U /*!< BOF error */
+#define HAL_CAN_ERROR_STF 0x00000008U /*!< Stuff error */
+#define HAL_CAN_ERROR_FOR 0x00000010U /*!< Form error */
+#define HAL_CAN_ERROR_ACK 0x00000020U /*!< Acknowledgment error */
+#define HAL_CAN_ERROR_BR 0x00000040U /*!< Bit recessive */
+#define HAL_CAN_ERROR_BD 0x00000080U /*!< LEC dominant */
+#define HAL_CAN_ERROR_CRC 0x00000100U /*!< LEC transfer error */
+#define HAL_CAN_ERROR_FOV0 0x00000200U /*!< FIFO0 overrun error */
+#define HAL_CAN_ERROR_FOV1 0x00000400U /*!< FIFO1 overrun error */
+#define HAL_CAN_ERROR_TXFAIL 0x00000800U /*!< Transmit failure */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_InitStatus CAN InitStatus
+ * @{
+ */
+#define CAN_INITSTATUS_FAILED ((uint8_t)0x00) /*!< CAN initialization failed */
+#define CAN_INITSTATUS_SUCCESS ((uint8_t)0x01) /*!< CAN initialization OK */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_operating_mode CAN Operating Mode
+ * @{
+ */
+#define CAN_MODE_NORMAL 0x00000000U /*!< Normal mode */
+#define CAN_MODE_LOOPBACK ((uint32_t)CAN_BTR_LBKM) /*!< Loopback mode */
+#define CAN_MODE_SILENT ((uint32_t)CAN_BTR_SILM) /*!< Silent mode */
+#define CAN_MODE_SILENT_LOOPBACK ((uint32_t)(CAN_BTR_LBKM | CAN_BTR_SILM)) /*!< Loopback combined with silent mode */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_synchronisation_jump_width CAN Synchronisation Jump Width
+ * @{
+ */
+#define CAN_SJW_1TQ 0x00000000U /*!< 1 time quantum */
+#define CAN_SJW_2TQ ((uint32_t)CAN_BTR_SJW_0) /*!< 2 time quantum */
+#define CAN_SJW_3TQ ((uint32_t)CAN_BTR_SJW_1) /*!< 3 time quantum */
+#define CAN_SJW_4TQ ((uint32_t)CAN_BTR_SJW) /*!< 4 time quantum */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_1 CAN Time Quantum in bit segment 1
+ * @{
+ */
+#define CAN_BS1_1TQ 0x00000000U /*!< 1 time quantum */
+#define CAN_BS1_2TQ ((uint32_t)CAN_BTR_TS1_0) /*!< 2 time quantum */
+#define CAN_BS1_3TQ ((uint32_t)CAN_BTR_TS1_1) /*!< 3 time quantum */
+#define CAN_BS1_4TQ ((uint32_t)(CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 4 time quantum */
+#define CAN_BS1_5TQ ((uint32_t)CAN_BTR_TS1_2) /*!< 5 time quantum */
+#define CAN_BS1_6TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 6 time quantum */
+#define CAN_BS1_7TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 7 time quantum */
+#define CAN_BS1_8TQ ((uint32_t)(CAN_BTR_TS1_2 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 8 time quantum */
+#define CAN_BS1_9TQ ((uint32_t)CAN_BTR_TS1_3) /*!< 9 time quantum */
+#define CAN_BS1_10TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_0)) /*!< 10 time quantum */
+#define CAN_BS1_11TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1)) /*!< 11 time quantum */
+#define CAN_BS1_12TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_1 | CAN_BTR_TS1_0)) /*!< 12 time quantum */
+#define CAN_BS1_13TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2)) /*!< 13 time quantum */
+#define CAN_BS1_14TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_0)) /*!< 14 time quantum */
+#define CAN_BS1_15TQ ((uint32_t)(CAN_BTR_TS1_3 | CAN_BTR_TS1_2 | CAN_BTR_TS1_1)) /*!< 15 time quantum */
+#define CAN_BS1_16TQ ((uint32_t)CAN_BTR_TS1) /*!< 16 time quantum */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_2 CAN Time Quantum in bit segment 2
+ * @{
+ */
+#define CAN_BS2_1TQ 0x00000000U /*!< 1 time quantum */
+#define CAN_BS2_2TQ ((uint32_t)CAN_BTR_TS2_0) /*!< 2 time quantum */
+#define CAN_BS2_3TQ ((uint32_t)CAN_BTR_TS2_1) /*!< 3 time quantum */
+#define CAN_BS2_4TQ ((uint32_t)(CAN_BTR_TS2_1 | CAN_BTR_TS2_0)) /*!< 4 time quantum */
+#define CAN_BS2_5TQ ((uint32_t)CAN_BTR_TS2_2) /*!< 5 time quantum */
+#define CAN_BS2_6TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_0)) /*!< 6 time quantum */
+#define CAN_BS2_7TQ ((uint32_t)(CAN_BTR_TS2_2 | CAN_BTR_TS2_1)) /*!< 7 time quantum */
+#define CAN_BS2_8TQ ((uint32_t)CAN_BTR_TS2) /*!< 8 time quantum */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_mode CAN Filter Mode
+ * @{
+ */
+#define CAN_FILTERMODE_IDMASK ((uint8_t)0x00) /*!< Identifier mask mode */
+#define CAN_FILTERMODE_IDLIST ((uint8_t)0x01) /*!< Identifier list mode */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_scale CAN Filter Scale
+ * @{
+ */
+#define CAN_FILTERSCALE_16BIT ((uint8_t)0x00) /*!< Two 16-bit filters */
+#define CAN_FILTERSCALE_32BIT ((uint8_t)0x01) /*!< One 32-bit filter */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_filter_FIFO CAN Filter FIFO
+ * @{
+ */
+#define CAN_FILTER_FIFO0 ((uint8_t)0x00) /*!< Filter FIFO 0 assignment for filter x */
+#define CAN_FILTER_FIFO1 ((uint8_t)0x01) /*!< Filter FIFO 1 assignment for filter x */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Identifier_Type CAN Identifier Type
+ * @{
+ */
+#define CAN_ID_STD 0x00000000U /*!< Standard Id */
+#define CAN_ID_EXT 0x00000004U /*!< Extended Id */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_remote_transmission_request CAN Remote Transmission Request
+ * @{
+ */
+#define CAN_RTR_DATA 0x00000000U /*!< Data frame */
+#define CAN_RTR_REMOTE 0x00000002U /*!< Remote frame */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_receive_FIFO_number_constants CAN Receive FIFO Number Constants
+ * @{
+ */
+#define CAN_FIFO0 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
+#define CAN_FIFO1 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_flags CAN Flags
+ * @{
+ */
+/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
+ and CAN_ClearFlag() functions. */
+/* If the flag is 0x1XXXXXXX, it means that it can only be used with
+ CAN_GetFlagStatus() function. */
+
+/* Transmit Flags */
+#define CAN_FLAG_RQCP0 0x00000500U /*!< Request MailBox0 flag */
+#define CAN_FLAG_RQCP1 0x00000508U /*!< Request MailBox1 flag */
+#define CAN_FLAG_RQCP2 0x00000510U /*!< Request MailBox2 flag */
+#define CAN_FLAG_TXOK0 0x00000501U /*!< Transmission OK MailBox0 flag */
+#define CAN_FLAG_TXOK1 0x00000509U /*!< Transmission OK MailBox1 flag */
+#define CAN_FLAG_TXOK2 0x00000511U /*!< Transmission OK MailBox2 flag */
+#define CAN_FLAG_TME0 0x0000051AU /*!< Transmit mailbox 0 empty flag */
+#define CAN_FLAG_TME1 0x0000051BU /*!< Transmit mailbox 0 empty flag */
+#define CAN_FLAG_TME2 0x0000051CU /*!< Transmit mailbox 0 empty flag */
+
+/* Receive Flags */
+#define CAN_FLAG_FF0 0x00000203U /*!< FIFO 0 Full flag */
+#define CAN_FLAG_FOV0 0x00000204U /*!< FIFO 0 Overrun flag */
+
+#define CAN_FLAG_FF1 0x00000403U /*!< FIFO 1 Full flag */
+#define CAN_FLAG_FOV1 0x00000404U /*!< FIFO 1 Overrun flag */
+
+/* Operating Mode Flags */
+#define CAN_FLAG_INAK 0x00000100U /*!< Initialization acknowledge flag */
+#define CAN_FLAG_SLAK 0x00000101U /*!< Sleep acknowledge flag */
+#define CAN_FLAG_ERRI 0x00000102U /*!< Error flag */
+#define CAN_FLAG_WKU 0x00000103U /*!< Wake up flag */
+#define CAN_FLAG_SLAKI 0x00000104U /*!< Sleep acknowledge flag */
+
+/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible.
+ In this case the SLAK bit can be polled.*/
+
+/* Error Flags */
+#define CAN_FLAG_EWG 0x00000300U /*!< Error warning flag */
+#define CAN_FLAG_EPV 0x00000301U /*!< Error passive flag */
+#define CAN_FLAG_BOF 0x00000302U /*!< Bus-Off flag */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Interrupts CAN Interrupts
+ * @{
+ */
+#define CAN_IT_TME CAN_IER_TMEIE /*!< Transmit mailbox empty interrupt */
+
+/* Receive Interrupts */
+#define CAN_IT_FMP0 CAN_IER_FMPIE0 /*!< FIFO 0 message pending interrupt */
+#define CAN_IT_FF0 CAN_IER_FFIE0 /*!< FIFO 0 full interrupt */
+#define CAN_IT_FOV0 CAN_IER_FOVIE0 /*!< FIFO 0 overrun interrupt */
+#define CAN_IT_FMP1 CAN_IER_FMPIE1 /*!< FIFO 1 message pending interrupt */
+#define CAN_IT_FF1 CAN_IER_FFIE1 /*!< FIFO 1 full interrupt */
+#define CAN_IT_FOV1 CAN_IER_FOVIE1 /*!< FIFO 1 overrun interrupt */
+
+/* Operating Mode Interrupts */
+#define CAN_IT_WKU CAN_IER_WKUIE /*!< Wake-up interrupt */
+#define CAN_IT_SLK CAN_IER_SLKIE /*!< Sleep acknowledge interrupt */
+
+/* Error Interrupts */
+#define CAN_IT_EWG CAN_IER_EWGIE /*!< Error warning interrupt */
+#define CAN_IT_EPV CAN_IER_EPVIE /*!< Error passive interrupt */
+#define CAN_IT_BOF CAN_IER_BOFIE /*!< Bus-off interrupt */
+#define CAN_IT_LEC CAN_IER_LECIE /*!< Last error code interrupt */
+#define CAN_IT_ERR CAN_IER_ERRIE /*!< Error Interrupt */
+/**
+ * @}
+ */
+
+/** @defgroup CAN_Mailboxes_Definition CAN Mailboxes Definition
+ * @{
+ */
+#define CAN_TXMAILBOX_0 ((uint8_t)0x00)
+#define CAN_TXMAILBOX_1 ((uint8_t)0x01)
+#define CAN_TXMAILBOX_2 ((uint8_t)0x02)
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Exported macro ------------------------------------------------------------*/
+/** @defgroup CAN_Exported_Macros CAN Exported Macros
+ * @{
+ */
+
+/** @brief Reset CAN handle state
+ * @param __HANDLE__ specifies the CAN Handle.
+ * @retval None
+ */
+#define __HAL_CAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CAN_STATE_RESET)
+
+/**
+ * @brief Enable the specified CAN interrupts.
+ * @param __HANDLE__ CAN handle
+ * @param __INTERRUPT__ CAN Interrupt
+ * @retval None
+ */
+#define __HAL_CAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) |= (__INTERRUPT__))
+
+/**
+ * @brief Disable the specified CAN interrupts.
+ * @param __HANDLE__ CAN handle
+ * @param __INTERRUPT__ CAN Interrupt
+ * @retval None
+ */
+#define __HAL_CAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IER) &= ~(__INTERRUPT__))
+
+/**
+ * @brief Return the number of pending received messages.
+ * @param __HANDLE__ CAN handle
+ * @param __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+ * @retval The number of pending message.
+ */
+#define __HAL_CAN_MSG_PENDING(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
+((uint8_t)((__HANDLE__)->Instance->RF0R&0x03U)) : ((uint8_t)((__HANDLE__)->Instance->RF1R&0x03U)))
+
+/** @brief Check whether the specified CAN flag is set or not.
+ * @param __HANDLE__ CAN Handle
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg CAN_TSR_RQCP0: Request MailBox0 Flag
+ * @arg CAN_TSR_RQCP1: Request MailBox1 Flag
+ * @arg CAN_TSR_RQCP2: Request MailBox2 Flag
+ * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
+ * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
+ * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
+ * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
+ * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
+ * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
+ * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
+ * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
+ * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
+ * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
+ * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
+ * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
+ * @arg CAN_FLAG_WKU: Wake up Flag
+ * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
+ * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
+ * @arg CAN_FLAG_EWG: Error Warning Flag
+ * @arg CAN_FLAG_EPV: Error Passive Flag
+ * @arg CAN_FLAG_BOF: Bus-Off Flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_CAN_GET_FLAG(__HANDLE__, __FLAG__) \
+((((__FLAG__) >> 8U) == 5U)? ((((__HANDLE__)->Instance->TSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 2U)? ((((__HANDLE__)->Instance->RF0R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 4U)? ((((__HANDLE__)->Instance->RF1R) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 1U)? ((((__HANDLE__)->Instance->MSR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ ((((__HANDLE__)->Instance->ESR) & (1U << ((__FLAG__) & CAN_FLAG_MASK))) == (1U << ((__FLAG__) & CAN_FLAG_MASK))))
+
+/** @brief Clear the specified CAN pending flag.
+ * @param __HANDLE__ CAN Handle.
+ * @param __FLAG__ specifies the flag to check.
+ * This parameter can be one of the following values:
+ * @arg CAN_TSR_RQCP0: Request MailBox0 Flag
+ * @arg CAN_TSR_RQCP1: Request MailBox1 Flag
+ * @arg CAN_TSR_RQCP2: Request MailBox2 Flag
+ * @arg CAN_FLAG_TXOK0: Transmission OK MailBox0 Flag
+ * @arg CAN_FLAG_TXOK1: Transmission OK MailBox1 Flag
+ * @arg CAN_FLAG_TXOK2: Transmission OK MailBox2 Flag
+ * @arg CAN_FLAG_TME0: Transmit mailbox 0 empty Flag
+ * @arg CAN_FLAG_TME1: Transmit mailbox 1 empty Flag
+ * @arg CAN_FLAG_TME2: Transmit mailbox 2 empty Flag
+ * @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag
+ * @arg CAN_FLAG_FF0: FIFO 0 Full Flag
+ * @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag
+ * @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag
+ * @arg CAN_FLAG_FF1: FIFO 1 Full Flag
+ * @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag
+ * @arg CAN_FLAG_WKU: Wake up Flag
+ * @arg CAN_FLAG_SLAK: Sleep acknowledge Flag
+ * @arg CAN_FLAG_SLAKI: Sleep acknowledge Flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
+#define __HAL_CAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
+((((__FLAG__) >> 8U) == 5U)? (((__HANDLE__)->Instance->TSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 2U)? (((__HANDLE__)->Instance->RF0R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__FLAG__) >> 8U) == 4U)? (((__HANDLE__)->Instance->RF1R) = (1U << ((__FLAG__) & CAN_FLAG_MASK))): \
+ (((__HANDLE__)->Instance->MSR) = (1U << ((__FLAG__) & CAN_FLAG_MASK))))
+
+/** @brief Check if the specified CAN interrupt source is enabled or disabled.
+ * @param __HANDLE__ CAN Handle
+ * @param __INTERRUPT__ specifies the CAN interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg CAN_IT_TME: Transmit mailbox empty interrupt enable
+ * @arg CAN_IT_FMP0: FIFO0 message pending interrupt enable
+ * @arg CAN_IT_FMP1: FIFO1 message pending interrupt enable
+ * @retval The new state of __IT__ (TRUE or FALSE).
+ */
+#define __HAL_CAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/**
+ * @brief Check the transmission status of a CAN Frame.
+ * @param __HANDLE__ CAN Handle
+ * @param __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission.
+ * @retval The new status of transmission (TRUE or FALSE).
+ */
+#define __HAL_CAN_TRANSMIT_STATUS(__HANDLE__, __TRANSMITMAILBOX__)\
+(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) == (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0)) :\
+ ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) == (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1)) :\
+ ((((__HANDLE__)->Instance->TSR) & (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)) == (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2)))
+
+/**
+ * @brief Release the specified receive FIFO.
+ * @param __HANDLE__ CAN handle
+ * @param __FIFONUMBER__ Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+ * @retval None
+ */
+#define __HAL_CAN_FIFO_RELEASE(__HANDLE__, __FIFONUMBER__) (((__FIFONUMBER__) == CAN_FIFO0)? \
+((__HANDLE__)->Instance->RF0R = CAN_RF0R_RFOM0) : ((__HANDLE__)->Instance->RF1R = CAN_RF1R_RFOM1))
+
+/**
+ * @brief Cancel a transmit request.
+ * @param __HANDLE__ CAN Handle
+ * @param __TRANSMITMAILBOX__ the number of the mailbox that is used for transmission.
+ * @retval None
+ */
+#define __HAL_CAN_CANCEL_TRANSMIT(__HANDLE__, __TRANSMITMAILBOX__)\
+(((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_0)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ0) :\
+ ((__TRANSMITMAILBOX__) == CAN_TXMAILBOX_1)? ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ1) :\
+ ((__HANDLE__)->Instance->TSR = CAN_TSR_ABRQ2))
+
+/**
+ * @brief Enable or disable the DBG Freeze for CAN.
+ * @param __HANDLE__ CAN Handle
+ * @param __NEWSTATE__ new state of the CAN peripheral.
+ * This parameter can be: ENABLE (CAN reception/transmission is frozen
+ * during debug. Reception FIFOs can still be accessed/controlled normally)
+ * or DISABLE (CAN is working during debug).
+ * @retval None
+ */
+#define __HAL_CAN_DBG_FREEZE(__HANDLE__, __NEWSTATE__) (((__NEWSTATE__) == ENABLE)? \
+((__HANDLE__)->Instance->MCR |= CAN_MCR_DBF) : ((__HANDLE__)->Instance->MCR &= ~CAN_MCR_DBF))
+
+/**
+ * @}
+ */
+
+/* Exported functions --------------------------------------------------------*/
+/** @addtogroup CAN_Exported_Functions
+ * @{
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group1
+ * @{
+ */
+/* Initialization/de-initialization functions ***********************************/
+HAL_StatusTypeDef HAL_CAN_Init(CAN_HandleTypeDef* hcan);
+HAL_StatusTypeDef HAL_CAN_ConfigFilter(CAN_HandleTypeDef* hcan, CAN_FilterConfTypeDef* sFilterConfig);
+HAL_StatusTypeDef HAL_CAN_DeInit(CAN_HandleTypeDef* hcan);
+void HAL_CAN_MspInit(CAN_HandleTypeDef* hcan);
+void HAL_CAN_MspDeInit(CAN_HandleTypeDef* hcan);
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group2
+ * @{
+ */
+/* I/O operation functions ******************************************************/
+HAL_StatusTypeDef HAL_CAN_Transmit(CAN_HandleTypeDef *hcan, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CAN_Transmit_IT(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_Receive(CAN_HandleTypeDef *hcan, uint8_t FIFONumber, uint32_t Timeout);
+HAL_StatusTypeDef HAL_CAN_Receive_IT(CAN_HandleTypeDef *hcan, uint8_t FIFONumber);
+HAL_StatusTypeDef HAL_CAN_Sleep(CAN_HandleTypeDef *hcan);
+HAL_StatusTypeDef HAL_CAN_WakeUp(CAN_HandleTypeDef *hcan);
+void HAL_CAN_IRQHandler(CAN_HandleTypeDef* hcan);
+void HAL_CAN_TxCpltCallback(CAN_HandleTypeDef* hcan);
+void HAL_CAN_RxCpltCallback(CAN_HandleTypeDef* hcan);
+void HAL_CAN_ErrorCallback(CAN_HandleTypeDef *hcan);
+/**
+ * @}
+ */
+
+/** @addtogroup CAN_Exported_Functions_Group3
+ * @{
+ */
+/* Peripheral State functions ***************************************************/
+uint32_t HAL_CAN_GetError(CAN_HandleTypeDef *hcan);
+HAL_CAN_StateTypeDef HAL_CAN_GetState(CAN_HandleTypeDef* hcan);
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+/* Private types -------------------------------------------------------------*/
+/** @defgroup CAN_Private_Types CAN Private Types
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private variables ---------------------------------------------------------*/
+/** @defgroup CAN_Private_Variables CAN Private Variables
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup CAN_Private_Constants CAN Private Constants
+ * @{
+ */
+#define CAN_TXSTATUS_NOMAILBOX ((uint8_t)0x04) /*!< CAN cell did not provide CAN_TxStatus_NoMailBox */
+#define CAN_FLAG_MASK 0x000000FFU
+/**
+ * @}
+ */
+
+/* Private macros ------------------------------------------------------------*/
+/** @defgroup CAN_Private_Macros CAN Private Macros
+ * @{
+ */
+#define IS_CAN_MODE(MODE) (((MODE) == CAN_MODE_NORMAL) || \
+ ((MODE) == CAN_MODE_LOOPBACK)|| \
+ ((MODE) == CAN_MODE_SILENT) || \
+ ((MODE) == CAN_MODE_SILENT_LOOPBACK))
+#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1TQ) || ((SJW) == CAN_SJW_2TQ)|| \
+ ((SJW) == CAN_SJW_3TQ) || ((SJW) == CAN_SJW_4TQ))
+#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16TQ)
+#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8TQ)
+#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 1024U))
+#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27U)
+#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FILTERMODE_IDMASK) || \
+ ((MODE) == CAN_FILTERMODE_IDLIST))
+#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FILTERSCALE_16BIT) || \
+ ((SCALE) == CAN_FILTERSCALE_32BIT))
+#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FILTER_FIFO0) || \
+ ((FIFO) == CAN_FILTER_FIFO1))
+#define IS_CAN_BANKNUMBER(BANKNUMBER) ((BANKNUMBER) <= 28U)
+
+#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
+#define IS_CAN_STDID(STDID) ((STDID) <= 0x7FFU)
+#define IS_CAN_EXTID(EXTID) ((EXTID) <= 0x1FFFFFFFU)
+#define IS_CAN_DLC(DLC) ((DLC) <= ((uint8_t)0x08))
+
+#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_ID_STD) || \
+ ((IDTYPE) == CAN_ID_EXT))
+#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_DATA) || ((RTR) == CAN_RTR_REMOTE))
+#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
+
+/**
+ * @}
+ */
+
+/* Private functions ---------------------------------------------------------*/
+/** @defgroup CAN_Private_Functions CAN Private Functions
+ * @{
+ */
+
+/**
+ * @}
+ */
+
+
+/**
+ * @}
+ */
+
+/**
+ * @}
+ */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F7xx_HAL_CAN_LEGACY_H */
+
+
+/************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cec.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cec.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_cec.c * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief CEC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the High Definition Multimedia Interface @@ -142,7 +140,7 @@ /** * @brief Initializes the CEC mode according to the specified * parameters in the CEC_InitTypeDef and creates the associated handle . - * @param hcec: CEC handle + * @param hcec CEC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CEC_Init(CEC_HandleTypeDef *hcec) @@ -212,7 +210,7 @@ /** * @brief DeInitializes the CEC peripheral - * @param hcec: CEC handle + * @param hcec CEC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CEC_DeInit(CEC_HandleTypeDef *hcec) @@ -266,8 +264,8 @@ /** * @brief Initializes the Own Address of the CEC device - * @param hcec: CEC handle - * @param CEC_OwnAddress: The CEC own address. + * @param hcec CEC handle + * @param CEC_OwnAddress The CEC own address. * @retval HAL status */ HAL_StatusTypeDef HAL_CEC_SetDeviceAddress(CEC_HandleTypeDef *hcec, uint16_t CEC_OwnAddress) @@ -313,7 +311,7 @@ /** * @brief CEC MSP Init - * @param hcec: CEC handle + * @param hcec CEC handle * @retval None */ __weak void HAL_CEC_MspInit(CEC_HandleTypeDef *hcec) @@ -327,7 +325,7 @@ /** * @brief CEC MSP DeInit - * @param hcec: CEC handle + * @param hcec CEC handle * @retval None */ __weak void HAL_CEC_MspDeInit(CEC_HandleTypeDef *hcec) @@ -379,11 +377,11 @@ /** * @brief Send data in interrupt mode - * @param hcec: CEC handle - * @param InitiatorAddress: Initiator address - * @param DestinationAddress: destination logical address - * @param pData: pointer to input byte data buffer - * @param Size: amount of data to be sent in bytes (without counting the header). + * @param hcec CEC handle + * @param InitiatorAddress Initiator address + * @param DestinationAddress destination logical address + * @param pData pointer to input byte data buffer + * @param Size amount of data to be sent in bytes (without counting the header). * 0 means only the header is sent (ping operation). * Maximum TX size is 15 bytes (1 opcode and up to 14 operands). * @retval HAL status @@ -438,7 +436,7 @@ /** * @brief Get size of the received frame. - * @param hcec: CEC handle + * @param hcec CEC handle * @retval Frame size */ uint32_t HAL_CEC_GetLastReceivedFrameSize(CEC_HandleTypeDef *hcec) @@ -448,8 +446,8 @@ /** * @brief Change Rx Buffer. - * @param hcec: CEC handle - * @param Rxbuffer: Rx Buffer + * @param hcec CEC handle + * @param Rxbuffer Rx Buffer * @note This function can be called only inside the HAL_CEC_RxCpltCallback() * @retval Frame size */ @@ -460,7 +458,7 @@ /** * @brief This function handles CEC interrupt requests. - * @param hcec: CEC handle + * @param hcec CEC handle * @retval None */ void HAL_CEC_IRQHandler(CEC_HandleTypeDef *hcec) @@ -565,7 +563,7 @@ /** * @brief Tx Transfer completed callback - * @param hcec: CEC handle + * @param hcec CEC handle * @retval None */ __weak void HAL_CEC_TxCpltCallback(CEC_HandleTypeDef *hcec) @@ -579,8 +577,8 @@ /** * @brief Rx Transfer completed callback - * @param hcec: CEC handle - * @param RxFrameSize: Size of frame + * @param hcec CEC handle + * @param RxFrameSize Size of frame * @retval None */ __weak void HAL_CEC_RxCpltCallback(CEC_HandleTypeDef *hcec, uint32_t RxFrameSize) @@ -595,7 +593,7 @@ /** * @brief CEC error callbacks - * @param hcec: CEC handle + * @param hcec CEC handle * @retval None */ __weak void HAL_CEC_ErrorCallback(CEC_HandleTypeDef *hcec) @@ -626,7 +624,7 @@ */ /** * @brief return the CEC state - * @param hcec: pointer to a CEC_HandleTypeDef structure that contains + * @param hcec pointer to a CEC_HandleTypeDef structure that contains * the configuration information for the specified CEC module. * @retval HAL state */ @@ -641,7 +639,7 @@ /** * @brief Return the CEC error code -* @param hcec : pointer to a CEC_HandleTypeDef structure that contains +* @param hcec pointer to a CEC_HandleTypeDef structure that contains * the configuration information for the specified CEC. * @retval CEC Error Code */
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cec.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cec.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_cec.h
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief Header file of CEC HAL module.
******************************************************************************
* @attention
@@ -429,7 +427,7 @@
*/
/** @brief Reset CEC handle gstate & RxState
- * @param __HANDLE__: CEC handle.
+ * @param __HANDLE__ CEC handle.
* @retval None
*/
#define __HAL_CEC_RESET_HANDLE_STATE(__HANDLE__) do{ \
@@ -438,8 +436,8 @@
} while(0)
/** @brief Checks whether or not the specified CEC interrupt flag is set.
- * @param __HANDLE__: specifies the CEC Handle.
- * @param __FLAG__: specifies the flag to check.
+ * @param __HANDLE__ specifies the CEC Handle.
+ * @param __FLAG__ specifies the flag to check.
* @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
* @arg CEC_FLAG_TXERR: Tx Error.
* @arg CEC_FLAG_TXUDR: Tx-Buffer Underrun.
@@ -458,8 +456,8 @@
#define __HAL_CEC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
/** @brief Clears the interrupt or status flag when raised (write at 1)
- * @param __HANDLE__: specifies the CEC Handle.
- * @param __FLAG__: specifies the interrupt/status flag to clear.
+ * @param __HANDLE__ specifies the CEC Handle.
+ * @param __FLAG__ specifies the interrupt/status flag to clear.
* This parameter can be one of the following values:
* @arg CEC_FLAG_TXACKE: Tx Missing acknowledge Error
* @arg CEC_FLAG_TXERR: Tx Error.
@@ -479,8 +477,8 @@
#define __HAL_CEC_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR |= (__FLAG__))
/** @brief Enables the specified CEC interrupt.
- * @param __HANDLE__: specifies the CEC Handle.
- * @param __INTERRUPT__: specifies the CEC interrupt to enable.
+ * @param __HANDLE__ specifies the CEC Handle.
+ * @param __INTERRUPT__ specifies the CEC interrupt to enable.
* This parameter can be one of the following values:
* @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
* @arg CEC_IT_TXERR: Tx Error IT Enable
@@ -500,8 +498,8 @@
#define __HAL_CEC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER |= (__INTERRUPT__))
/** @brief Disables the specified CEC interrupt.
- * @param __HANDLE__: specifies the CEC Handle.
- * @param __INTERRUPT__: specifies the CEC interrupt to disable.
+ * @param __HANDLE__ specifies the CEC Handle.
+ * @param __INTERRUPT__ specifies the CEC interrupt to disable.
* This parameter can be one of the following values:
* @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
* @arg CEC_IT_TXERR: Tx Error IT Enable
@@ -521,8 +519,8 @@
#define __HAL_CEC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER &= (~(__INTERRUPT__)))
/** @brief Checks whether or not the specified CEC interrupt is enabled.
- * @param __HANDLE__: specifies the CEC Handle.
- * @param __INTERRUPT__: specifies the CEC interrupt to check.
+ * @param __HANDLE__ specifies the CEC Handle.
+ * @param __INTERRUPT__ specifies the CEC interrupt to check.
* This parameter can be one of the following values:
* @arg CEC_IT_TXACKE: Tx Missing acknowledge Error IT Enable
* @arg CEC_IT_TXERR: Tx Error IT Enable
@@ -542,52 +540,52 @@
#define __HAL_CEC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IER & (__INTERRUPT__))
/** @brief Enables the CEC device
- * @param __HANDLE__: specifies the CEC Handle.
+ * @param __HANDLE__ specifies the CEC Handle.
* @retval none
*/
#define __HAL_CEC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_CECEN)
/** @brief Disables the CEC device
- * @param __HANDLE__: specifies the CEC Handle.
+ * @param __HANDLE__ specifies the CEC Handle.
* @retval none
*/
#define __HAL_CEC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~CEC_CR_CECEN)
/** @brief Set Transmission Start flag
- * @param __HANDLE__: specifies the CEC Handle.
+ * @param __HANDLE__ specifies the CEC Handle.
* @retval none
*/
#define __HAL_CEC_FIRST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXSOM)
/** @brief Set Transmission End flag
- * @param __HANDLE__: specifies the CEC Handle.
+ * @param __HANDLE__ specifies the CEC Handle.
* @retval none
* If the CEC message consists of only one byte, TXEOM must be set before of TXSOM.
*/
#define __HAL_CEC_LAST_BYTE_TX_SET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CEC_CR_TXEOM)
/** @brief Get Transmission Start flag
- * @param __HANDLE__: specifies the CEC Handle.
+ * @param __HANDLE__ specifies the CEC Handle.
* @retval FlagStatus
*/
#define __HAL_CEC_GET_TRANSMISSION_START_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXSOM)
/** @brief Get Transmission End flag
- * @param __HANDLE__: specifies the CEC Handle.
+ * @param __HANDLE__ specifies the CEC Handle.
* @retval FlagStatus
*/
#define __HAL_CEC_GET_TRANSMISSION_END_FLAG(__HANDLE__) ((__HANDLE__)->Instance->CR & CEC_CR_TXEOM)
/** @brief Clear OAR register
- * @param __HANDLE__: specifies the CEC Handle.
+ * @param __HANDLE__ specifies the CEC Handle.
* @retval none
*/
#define __HAL_CEC_CLEAR_OAR(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CFGR, CEC_CFGR_OAR)
/** @brief Set OAR register (without resetting previously set address in case of multi-address mode)
* To reset OAR, __HAL_CEC_CLEAR_OAR() needs to be called beforehand
- * @param __HANDLE__: specifies the CEC Handle.
- * @param __ADDRESS__: Own Address value (CEC logical address is identified by bit position)
+ * @param __HANDLE__ specifies the CEC Handle.
+ * @param __ADDRESS__ Own Address value (CEC logical address is identified by bit position)
* @retval none
*/
#define __HAL_CEC_SET_OAR(__HANDLE__,__ADDRESS__) SET_BIT((__HANDLE__)->Instance->CFGR, (__ADDRESS__)<< CEC_CFGR_OAR_LSB_POS)
@@ -702,21 +700,21 @@
* The message size is the payload size: without counting the header,
* it varies from 0 byte (ping operation, one header only, no payload) to
* 15 bytes (1 opcode and up to 14 operands following the header).
- * @param __SIZE__: CEC message size.
+ * @param __SIZE__ CEC message size.
* @retval Test result (TRUE or FALSE).
*/
#define IS_CEC_MSGSIZE(__SIZE__) ((__SIZE__) <= 0x10)
/** @brief Check CEC device Own Address Register (OAR) setting.
* OAR address is written in a 15-bit field within CEC_CFGR register.
- * @param __ADDRESS__: CEC own address.
+ * @param __ADDRESS__ CEC own address.
* @retval Test result (TRUE or FALSE).
*/
#define IS_CEC_OWN_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0x7FFF)
/** @brief Check CEC initiator or destination logical address setting.
* Initiator and destination addresses are coded over 4 bits.
- * @param __ADDRESS__: CEC initiator or logical address.
+ * @param __ADDRESS__ CEC initiator or logical address.
* @retval Test result (TRUE or FALSE).
*/
#define IS_CEC_ADDRESS(__ADDRESS__) ((__ADDRESS__) <= 0xF)
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_conf.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_conf.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_conf.h * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief HAL configuration file. ****************************************************************************** * @attention @@ -52,7 +50,9 @@ */ #define HAL_MODULE_ENABLED #define HAL_ADC_MODULE_ENABLED -#define HAL_CAN_MODULE_ENABLED +// MBED: use the legacy module for now +//#define HAL_CAN_MODULE_ENABLED +#define HAL_CAN_LEGACY_MODULE_ENABLED #define HAL_CEC_MODULE_ENABLED #define HAL_CRC_MODULE_ENABLED #define HAL_CRYP_MODULE_ENABLED @@ -164,8 +164,8 @@ #define VDD_VALUE 3300U /*!< Value of VDD in mv */ #define TICK_INT_PRIORITY 0x0FU /*!< tick interrupt priority */ #define USE_RTOS 0U -#define PREFETCH_ENABLE 1U -#define ART_ACCLERATOR_ENABLE 1U /* To enable instruction cache and prefetch */ +#define PREFETCH_ENABLE 1U /* To enable prefetch */ +#define ART_ACCLERATOR_ENABLE 1U /* To enable ART Accelerator */ /* ########################## Assert Selection ############################## */ /** @@ -278,6 +278,10 @@ #include "stm32f7xx_hal_can.h" #endif /* HAL_CAN_MODULE_ENABLED */ +#ifdef HAL_CAN_LEGACY_MODULE_ENABLED + #include "stm32f7xx_hal_can_legacy.h" +#endif /* HAL_CAN_LEGACY_MODULE_ENABLED */ + #ifdef HAL_CEC_MODULE_ENABLED #include "stm32f7xx_hal_cec.h" #endif /* HAL_CEC_MODULE_ENABLED */ @@ -442,8 +446,19 @@ #ifdef USE_FULL_ASSERT /* ALL MBED targets use same stm32_assert.h */ #include "stm32_assert.h" +/** + * @brief The assert_param macro is used for function's parameters check. + * @param expr If expr is false, it calls assert_failed function + * which reports the name of the source file and the source + * line number of the call that failed. + * If expr is true, it returns no value. + * @retval None + */ +//#define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__)) +/* Exported functions ------------------------------------------------------- */ +//void assert_failed(uint8_t* file, uint32_t line); #else - #define assert_param(expr) ((void)0) + #define assert_param(expr) ((void)0U) #endif /* USE_FULL_ASSERT */
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cortex.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cortex.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_cortex.c * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief CORTEX HAL module driver. * This file provides firmware functions to manage the following * functionalities of the CORTEX: @@ -142,7 +140,7 @@ /** * @brief Sets the priority grouping field (preemption priority and subpriority) * using the required unlock sequence. - * @param PriorityGroup: The priority grouping bits length. + * @param PriorityGroup The priority grouping bits length. * This parameter can be one of the following values: * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority * 4 bits for subpriority @@ -169,13 +167,13 @@ /** * @brief Sets the priority of an interrupt. - * @param IRQn: External interrupt number. + * @param IRQn External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h)) - * @param PreemptPriority: The preemption priority for the IRQn channel. + * @param PreemptPriority The preemption priority for the IRQn channel. * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority - * @param SubPriority: the subpriority level for the IRQ channel. + * @param SubPriority the subpriority level for the IRQ channel. * This parameter can be a value between 0 and 15 * A lower priority value indicates a higher priority. * @retval None @@ -240,7 +238,7 @@ /** * @brief Initializes the System Timer and its interrupt, and starts the System Tick Timer. * Counter is in free running mode to generate periodic interrupts. - * @param TicksNumb: Specifies the ticks Number of ticks between two interrupts. + * @param TicksNumb Specifies the ticks Number of ticks between two interrupts. * @retval status: - 0 Function succeeded. * - 1 Function failed. */ @@ -287,7 +285,7 @@ /** * @brief Enables the MPU - * @param MPU_Control: Specifies the control mode of the MPU during hard fault, + * @param MPU_Control Specifies the control mode of the MPU during hard fault, * NMI, FAULTMASK and privileged access to the default memory * This parameter can be one of the following values: * @arg MPU_HFNMI_PRIVDEF_NONE @@ -311,7 +309,7 @@ /** * @brief Initializes and configures the Region and the memory to be protected. - * @param MPU_Init: Pointer to a MPU_Region_InitTypeDef structure that contains + * @param MPU_Init Pointer to a MPU_Region_InitTypeDef structure that contains * the initialization and configuration information. * @retval None */ @@ -367,10 +365,10 @@ /** * @brief Gets the priority of an interrupt. - * @param IRQn: External interrupt number. + * @param IRQn External interrupt number. * This parameter can be an enumerator of IRQn_Type enumeration * (For the complete STM32 Devices IRQ Channels list, please refer to the appropriate CMSIS device file (stm32f7xxxx.h)) - * @param PriorityGroup: the priority grouping bits length. + * @param PriorityGroup the priority grouping bits length. * This parameter can be one of the following values: * @arg NVIC_PRIORITYGROUP_0: 0 bits for preemption priority * 4 bits for subpriority @@ -382,8 +380,8 @@ * 1 bits for subpriority * @arg NVIC_PRIORITYGROUP_4: 4 bits for preemption priority * 0 bits for subpriority - * @param pPreemptPriority: Pointer on the Preemptive priority value (starting from 0). - * @param pSubPriority: Pointer on the Subpriority value (starting from 0). + * @param pPreemptPriority Pointer on the Preemptive priority value (starting from 0). + * @param pSubPriority Pointer on the Subpriority value (starting from 0). * @retval None */ void HAL_NVIC_GetPriority(IRQn_Type IRQn, uint32_t PriorityGroup, uint32_t *pPreemptPriority, uint32_t *pSubPriority) @@ -463,7 +461,7 @@ /** * @brief Configures the SysTick clock source. - * @param CLKSource: specifies the SysTick clock source. + * @param CLKSource specifies the SysTick clock source. * This parameter can be one of the following values: * @arg SYSTICK_CLKSOURCE_HCLK_DIV8: AHB clock divided by 8 selected as SysTick clock source. * @arg SYSTICK_CLKSOURCE_HCLK: AHB clock selected as SysTick clock source.
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cortex.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cortex.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_cortex.h * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief Header file of CORTEX HAL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_crc.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_crc.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_crc.c * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief CRC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Cyclic Redundancy Check (CRC) peripheral: @@ -112,7 +110,7 @@ /** * @brief Initialize the CRC according to the specified * parameters in the CRC_InitTypeDef and create the associated handle. - * @param hcrc: CRC handle + * @param hcrc CRC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CRC_Init(CRC_HandleTypeDef *hcrc) @@ -189,7 +187,7 @@ /** * @brief DeInitialize the CRC peripheral. - * @param hcrc: CRC handle + * @param hcrc CRC handle * @retval HAL status */ HAL_StatusTypeDef HAL_CRC_DeInit(CRC_HandleTypeDef *hcrc) @@ -233,7 +231,7 @@ /** * @brief Initialize the CRC MSP. - * @param hcrc: CRC handle + * @param hcrc CRC handle * @retval None */ __weak void HAL_CRC_MspInit(CRC_HandleTypeDef *hcrc) @@ -248,7 +246,7 @@ /** * @brief DeInitialize the CRC MSP. - * @param hcrc: CRC handle + * @param hcrc CRC handle * @retval None */ __weak void HAL_CRC_MspDeInit(CRC_HandleTypeDef *hcrc) @@ -288,10 +286,10 @@ /** * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer * starting with the previously computed CRC as initialization value. - * @param hcrc: CRC handle - * @param pBuffer: pointer to the input data buffer, exact input data format is + * @param hcrc CRC handle + * @param pBuffer pointer to the input data buffer, exact input data format is * provided by hcrc->InputDataFormat. - * @param BufferLength: input data buffer length (number of bytes if pBuffer + * @param BufferLength input data buffer length (number of bytes if pBuffer * type is * uint8_t, number of half-words if pBuffer type is * uint16_t, * number of words if pBuffer type is * uint32_t). * @note By default, the API expects a uint32_t pointer as input buffer parameter. @@ -346,10 +344,10 @@ /** * @brief Compute the 7, 8, 16 or 32-bit CRC value of an 8, 16 or 32-bit data buffer * starting with hcrc->Instance->INIT as initialization value. - * @param hcrc: CRC handle - * @param pBuffer: pointer to the input data buffer, exact input data format is + * @param hcrc CRC handle + * @param pBuffer pointer to the input data buffer, exact input data format is * provided by hcrc->InputDataFormat. - * @param BufferLength: input data buffer length (number of bytes if pBuffer + * @param BufferLength input data buffer length (number of bytes if pBuffer * type is * uint8_t, number of half-words if pBuffer type is * uint16_t, * number of words if pBuffer type is * uint32_t). * @note By default, the API expects a uint32_t pointer as input buffer parameter. @@ -410,9 +408,9 @@ /** * @brief Enter 8-bit input data to the CRC calculator. * Specific data handling to optimize processing time. - * @param hcrc: CRC handle - * @param pBuffer: pointer to the input data buffer - * @param BufferLength: input data buffer length + * @param hcrc CRC handle + * @param pBuffer pointer to the input data buffer + * @param BufferLength input data buffer length * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ static uint32_t CRC_Handle_8(CRC_HandleTypeDef *hcrc, uint8_t pBuffer[], uint32_t BufferLength) @@ -451,9 +449,9 @@ /** * @brief Enter 16-bit input data to the CRC calculator. * Specific data handling to optimize processing time. - * @param hcrc: CRC handle - * @param pBuffer: pointer to the input data buffer - * @param BufferLength: input data buffer length + * @param hcrc CRC handle + * @param pBuffer pointer to the input data buffer + * @param BufferLength input data buffer length * @retval uint32_t CRC (returned value LSBs for CRC shorter than 32 bits) */ static uint32_t CRC_Handle_16(CRC_HandleTypeDef *hcrc, uint16_t pBuffer[], uint32_t BufferLength) @@ -497,7 +495,7 @@ /** * @brief Return the CRC state. - * @param hcrc: CRC handle + * @param hcrc CRC handle * @retval HAL state */ HAL_CRC_StateTypeDef HAL_CRC_GetState(CRC_HandleTypeDef *hcrc)
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_crc.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_crc.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_crc.h * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief Header file of CRC HAL module. ****************************************************************************** * @attention @@ -243,37 +241,37 @@ */ /** @brief Reset CRC handle state - * @param __HANDLE__: CRC handle. + * @param __HANDLE__ CRC handle. * @retval None */ #define __HAL_CRC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRC_STATE_RESET) /** * @brief Reset CRC Data Register. - * @param __HANDLE__: CRC handle + * @param __HANDLE__ CRC handle * @retval None. */ #define __HAL_CRC_DR_RESET(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_RESET) /** * @brief Set CRC INIT non-default value - * @param __HANDLE__ : CRC handle - * @param __INIT__ : 32-bit initial value + * @param __HANDLE__ CRC handle + * @param __INIT__ 32-bit initial value * @retval None. */ #define __HAL_CRC_INITIALCRCVALUE_CONFIG(__HANDLE__, __INIT__) ((__HANDLE__)->Instance->INIT = (__INIT__)) /** * @brief Stores a 8-bit data in the Independent Data(ID) register. - * @param __HANDLE__: CRC handle - * @param __VALUE__: 8-bit value to be stored in the ID register + * @param __HANDLE__ CRC handle + * @param __VALUE__ 8-bit value to be stored in the ID register * @retval None */ #define __HAL_CRC_SET_IDR(__HANDLE__, __VALUE__) (WRITE_REG((__HANDLE__)->Instance->IDR, CRC_IDR_IDR, (__VALUE__))) /** * @brief Returns the 8-bit data stored in the Independent Data(ID) register. - * @param __HANDLE__: CRC handle + * @param __HANDLE__ CRC handle * @retval 8-bit value of the ID register */ #define __HAL_CRC_GET_IDR(__HANDLE__) (((__HANDLE__)->Instance->IDR) & CRC_IDR_IDR)
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_crc_ex.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_crc_ex.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_crc_ex.c * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief Extended CRC HAL module driver. * * This file provides firmware functions to manage the following @@ -93,12 +91,12 @@ /** * @brief Initializes the CRC polynomial if different from default one. - * @param hcrc: CRC handle - * @param Pol: CRC generating polynomial (7, 8, 16 or 32-bit long) + * @param hcrc CRC handle + * @param Pol CRC generating polynomial (7, 8, 16 or 32-bit long) * This parameter is written in normal representation, e.g. * for a polynomial of degree 7, X^7 + X^6 + X^5 + X^2 + 1 is written 0x65 * for a polynomial of degree 16, X^16 + X^12 + X^5 + 1 is written 0x1021 - * @param PolyLength: CRC polynomial length + * @param PolyLength CRC polynomial length * This parameter can be one of the following values: * @arg CRC_POLYLENGTH_7B: 7-bit long CRC (generating polynomial of degree 7) * @arg CRC_POLYLENGTH_8B: 8-bit long CRC (generating polynomial of degree 8) @@ -163,8 +161,8 @@ /** * @brief Set the Reverse Input data mode. - * @param hcrc: CRC handle - * @param InputReverseMode: Input Data inversion mode + * @param hcrc CRC handle + * @param InputReverseMode Input Data inversion mode * This parameter can be one of the following values: * @arg CRC_INPUTDATA_INVERSION_NONE: no change in bit order (default value) * @arg CRC_INPUTDATA_INVERSION_BYTE: Byte-wise bit reversal @@ -191,8 +189,8 @@ /** * @brief Set the Reverse Output data mode. - * @param hcrc: CRC handle - * @param OutputReverseMode: Output Data inversion mode + * @param hcrc CRC handle + * @param OutputReverseMode Output Data inversion mode * This parameter can be one of the following values: * @arg CRC_OUTPUTDATA_INVERSION_DISABLE: no CRC inversion (default value) * @arg CRC_OUTPUTDATA_INVERSION_ENABLE: bit-level inversion (e.g for a 8-bit CRC: 0xB5 becomes 0xAD)
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_crc_ex.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_crc_ex.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_crc_ex.h
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief Header file of CRC HAL extension module.
******************************************************************************
* @attention
@@ -101,22 +99,22 @@
/**
* @brief Set CRC output reversal
- * @param __HANDLE__ : CRC handle
+ * @param __HANDLE__ CRC handle
* @retval None.
*/
#define __HAL_CRC_OUTPUTREVERSAL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRC_CR_REV_OUT)
/**
* @brief Unset CRC output reversal
- * @param __HANDLE__ : CRC handle
+ * @param __HANDLE__ CRC handle
* @retval None.
*/
#define __HAL_CRC_OUTPUTREVERSAL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(CRC_CR_REV_OUT))
/**
* @brief Set CRC non-default polynomial
- * @param __HANDLE__ : CRC handle
- * @param __POLYNOMIAL__: 7, 8, 16 or 32-bit polynomial
+ * @param __HANDLE__ CRC handle
+ * @param __POLYNOMIAL__ 7, 8, 16 or 32-bit polynomial
* @retval None.
*/
#define __HAL_CRC_POLYNOMIAL_CONFIG(__HANDLE__, __POLYNOMIAL__) ((__HANDLE__)->Instance->POL = (__POLYNOMIAL__))
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cryp.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cryp.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_cryp.c * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief CRYP HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Cryptography (CRYP) peripheral: @@ -151,7 +149,7 @@ /** * @brief DMA CRYP Input Data process complete callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma) @@ -168,7 +166,7 @@ /** * @brief DMA CRYP Output Data process complete callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) @@ -191,7 +189,7 @@ /** * @brief DMA CRYP communication error callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void CRYP_DMAError(DMA_HandleTypeDef *hdma) @@ -203,10 +201,10 @@ /** * @brief Writes the Key in Key registers. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param Key: Pointer to Key buffer - * @param KeySize: Size of Key + * @param Key Pointer to Key buffer + * @param KeySize Size of Key * @retval None */ static void CRYP_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize) @@ -262,10 +260,10 @@ /** * @brief Writes the InitVector/InitCounter in IV registers. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param InitVector: Pointer to InitVector/InitCounter buffer - * @param IVSize: Size of the InitVector/InitCounter + * @param InitVector Pointer to InitVector/InitCounter buffer + * @param IVSize Size of the InitVector/InitCounter * @retval None */ static void CRYP_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector, uint32_t IVSize) @@ -301,12 +299,12 @@ /** * @brief Process Data: Writes Input data in polling mode and read the output data - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param Input: Pointer to the Input buffer - * @param Ilength: Length of the Input buffer, must be a multiple of 16. - * @param Output: Pointer to the returned buffer - * @param Timeout: Timeout value + * @param Input Pointer to the Input buffer + * @param Ilength Length of the Input buffer, must be a multiple of 16. + * @param Output Pointer to the returned buffer + * @param Timeout Timeout value * @retval None */ static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout) @@ -365,12 +363,12 @@ /** * @brief Process Data: Write Input data in polling mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param Input: Pointer to the Input buffer - * @param Ilength: Length of the Input buffer, must be a multiple of 8 - * @param Output: Pointer to the returned buffer - * @param Timeout: Specify Timeout value + * @param Input Pointer to the Input buffer + * @param Ilength Length of the Input buffer, must be a multiple of 8 + * @param Output Pointer to the returned buffer + * @param Timeout Specify Timeout value * @retval None */ static HAL_StatusTypeDef CRYP_ProcessData2Words(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout) @@ -421,11 +419,11 @@ /** * @brief Set the DMA configuration and start the DMA transfer - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param inputaddr: address of the Input buffer - * @param Size: Size of the Input buffer, must be a multiple of 16. - * @param outputaddr: address of the Output buffer + * @param inputaddr address of the Input buffer + * @param Size Size of the Input buffer, must be a multiple of 16. + * @param outputaddr address of the Output buffer * @retval None */ static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr) @@ -459,9 +457,9 @@ /** * @brief Sets the CRYP peripheral in DES ECB mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param Direction: Encryption or decryption + * @param Direction Encryption or decryption * @retval None */ static void CRYP_SetDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction) @@ -486,9 +484,9 @@ /** * @brief Sets the CRYP peripheral in DES CBC mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param Direction: Encryption or decryption + * @param Direction Encryption or decryption * @retval None */ static void CRYP_SetDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction) @@ -516,9 +514,9 @@ /** * @brief Sets the CRYP peripheral in TDES ECB mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param Direction: Encryption or decryption + * @param Direction Encryption or decryption * @retval None */ static void CRYP_SetTDESECBMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction) @@ -542,9 +540,9 @@ /** * @brief Sets the CRYP peripheral in TDES CBC mode - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param Direction: Encryption or decryption + * @param Direction Encryption or decryption * @retval None */ static void CRYP_SetTDESCBCMode(CRYP_HandleTypeDef *hcryp, uint32_t Direction) @@ -599,7 +597,7 @@ /** * @brief Initializes the CRYP according to the specified * parameters in the CRYP_InitTypeDef and creates the associated handle. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval HAL status */ @@ -645,7 +643,7 @@ /** * @brief DeInitializes the CRYP peripheral. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval HAL status */ @@ -685,7 +683,7 @@ /** * @brief Initializes the CRYP MSP. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -701,7 +699,7 @@ /** * @brief DeInitializes CRYP MSP. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -741,12 +739,12 @@ /** * @brief Initializes the CRYP peripheral in AES ECB encryption mode * then encrypt pPlainData. The cypher data are available in pCypherData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) @@ -795,12 +793,12 @@ /** * @brief Initializes the CRYP peripheral in AES CBC encryption mode * then encrypt pPlainData. The cypher data are available in pCypherData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) @@ -852,12 +850,12 @@ /** * @brief Initializes the CRYP peripheral in AES CTR encryption mode * then encrypt pPlainData. The cypher data are available in pCypherData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) @@ -911,12 +909,12 @@ /** * @brief Initializes the CRYP peripheral in AES ECB decryption mode * then decrypted pCypherData. The cypher data are available in pPlainData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer - * @param Timeout: Specify Timeout value + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16. + * @param pPlainData Pointer to the plaintext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) @@ -999,12 +997,12 @@ /** * @brief Initializes the CRYP peripheral in AES ECB decryption mode * then decrypted pCypherData. The cypher data are available in pPlainData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer - * @param Timeout: Specify Timeout value + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16. + * @param pPlainData Pointer to the plaintext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) @@ -1088,12 +1086,12 @@ /** * @brief Initializes the CRYP peripheral in AES CTR decryption mode * then decrypted pCypherData. The cypher data are available in pPlainData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer - * @param Timeout: Specify Timeout value + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16. + * @param pPlainData Pointer to the plaintext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) @@ -1144,11 +1142,11 @@ /** * @brief Initializes the CRYP peripheral in AES ECB encryption mode using Interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -1245,11 +1243,11 @@ /** * @brief Initializes the CRYP peripheral in AES CBC encryption mode using Interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -1348,11 +1346,11 @@ /** * @brief Initializes the CRYP peripheral in AES CTR encryption mode using Interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -1452,11 +1450,11 @@ /** * @brief Initializes the CRYP peripheral in AES ECB decryption mode using Interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16. + * @param pPlainData Pointer to the plaintext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -1581,11 +1579,11 @@ /** * @brief Initializes the CRYP peripheral in AES CBC decryption mode using IT. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 + * @param pPlainData Pointer to the plaintext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -1718,11 +1716,11 @@ /** * @brief Initializes the CRYP peripheral in AES CTR decryption mode using Interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 + * @param pPlainData Pointer to the plaintext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -1823,11 +1821,11 @@ /** * @brief Initializes the CRYP peripheral in AES ECB encryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -1878,11 +1876,11 @@ /** * @brief Initializes the CRYP peripheral in AES CBC encryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -1936,11 +1934,11 @@ /** * @brief Initializes the CRYP peripheral in AES CTR encryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCTR_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -1995,11 +1993,11 @@ /** * @brief Initializes the CRYP peripheral in AES ECB decryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes + * @param pPlainData Pointer to the plaintext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -2079,11 +2077,11 @@ /** * @brief Initializes the CRYP peripheral in AES CBC encryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 bytes - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 bytes + * @param pPlainData Pointer to the plaintext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -2166,11 +2164,11 @@ /** * @brief Initializes the CRYP peripheral in AES CTR decryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 + * @param pPlainData Pointer to the plaintext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_AESCTR_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -2249,12 +2247,12 @@ /** * @brief Initializes the CRYP peripheral in DES ECB encryption mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) @@ -2289,12 +2287,12 @@ /** * @brief Initializes the CRYP peripheral in DES ECB decryption mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pPlainData: Pointer to the plaintext buffer - * @param Timeout: Specify Timeout value + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pPlainData Pointer to the plaintext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) @@ -2329,12 +2327,12 @@ /** * @brief Initializes the CRYP peripheral in DES CBC encryption mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) @@ -2369,12 +2367,12 @@ /** * @brief Initializes the CRYP peripheral in DES ECB decryption mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pPlainData: Pointer to the plaintext buffer - * @param Timeout: Specify Timeout value + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pPlainData Pointer to the plaintext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) @@ -2409,11 +2407,11 @@ /** * @brief Initializes the CRYP peripheral in DES ECB encryption mode using IT. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -2494,11 +2492,11 @@ /** * @brief Initializes the CRYP peripheral in DES CBC encryption mode using interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -2580,11 +2578,11 @@ /** * @brief Initializes the CRYP peripheral in DES ECB decryption mode using IT. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -2665,11 +2663,11 @@ /** * @brief Initializes the CRYP peripheral in DES ECB decryption mode using interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -2750,11 +2748,11 @@ /** * @brief Initializes the CRYP peripheral in DES ECB encryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_DESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -2793,11 +2791,11 @@ /** * @brief Initializes the CRYP peripheral in DES CBC encryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_DESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -2836,11 +2834,11 @@ /** * @brief Initializes the CRYP peripheral in DES ECB decryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_DESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -2879,11 +2877,11 @@ /** * @brief Initializes the CRYP peripheral in DES ECB decryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_DESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -2946,12 +2944,12 @@ /** * @brief Initializes the CRYP peripheral in TDES ECB encryption mode * then encrypt pPlainData. The cypher data are available in pCypherData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) @@ -2987,12 +2985,12 @@ /** * @brief Initializes the CRYP peripheral in TDES ECB decryption mode * then decrypted pCypherData. The cypher data are available in pPlainData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) @@ -3028,12 +3026,12 @@ /** * @brief Initializes the CRYP peripheral in TDES CBC encryption mode * then encrypt pPlainData. The cypher data are available in pCypherData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) @@ -3069,12 +3067,12 @@ /** * @brief Initializes the CRYP peripheral in TDES CBC decryption mode * then decrypted pCypherData. The cypher data are available in pPlainData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pPlainData: Pointer to the plaintext buffer - * @param Timeout: Specify Timeout value + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pPlainData Pointer to the plaintext buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) @@ -3109,11 +3107,11 @@ /** * @brief Initializes the CRYP peripheral in TDES ECB encryption mode using interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -3194,11 +3192,11 @@ /** * @brief Initializes the CRYP peripheral in TDES CBC encryption mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -3278,11 +3276,11 @@ /** * @brief Initializes the CRYP peripheral in TDES ECB decryption mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -3362,11 +3360,11 @@ /** * @brief Initializes the CRYP peripheral in TDES CBC decryption mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pPlainData Pointer to the plaintext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -3446,11 +3444,11 @@ /** * @brief Initializes the CRYP peripheral in TDES ECB encryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_TDESECB_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -3489,11 +3487,11 @@ /** * @brief Initializes the CRYP peripheral in TDES CBC encryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -3532,11 +3530,11 @@ /** * @brief Initializes the CRYP peripheral in TDES ECB decryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_TDESECB_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -3575,11 +3573,11 @@ /** * @brief Initializes the CRYP peripheral in TDES CBC decryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 8 - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 8 + * @param pPlainData Pointer to the plaintext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYP_TDESCBC_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -3638,7 +3636,7 @@ /** * @brief Input FIFO transfer completed callbacks. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -3654,7 +3652,7 @@ /** * @brief Output FIFO transfer completed callbacks. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -3670,7 +3668,7 @@ /** * @brief CRYP error callbacks. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -3703,7 +3701,7 @@ /** * @brief This function handles CRYP interrupt request. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -3792,7 +3790,7 @@ /** * @brief Returns the CRYP state. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval HAL state */ @@ -4104,7 +4102,7 @@ /** * @brief DeInitialize the CRYP peripheral. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval HAL status */ @@ -4144,7 +4142,7 @@ /** * @brief Initialize the CRYP MSP. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -4160,7 +4158,7 @@ /** * @brief DeInitialize CRYP MSP. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -4200,12 +4198,12 @@ /** * @brief Encrypt pPlainData in AES ECB encryption mode. The cypher data are available in pCypherData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Specify Timeout value * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). * @retval HAL status @@ -4231,12 +4229,12 @@ /** * @brief Encrypt pPlainData in AES CBC encryption mode with key derivation. The cypher data are available in pCypherData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Specify Timeout value * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). * @retval HAL status @@ -4262,12 +4260,12 @@ /** * @brief Encrypt pPlainData in AES CTR encryption mode. The cypher data are available in pCypherData - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Specify Timeout value + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Specify Timeout value * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). * @retval HAL status @@ -4293,12 +4291,12 @@ /** * @brief Decrypt pCypherData in AES ECB decryption mode with key derivation, * the decyphered data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer - * @param Timeout: Specify Timeout value + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pPlainData Pointer to the plaintext buffer + * @param Timeout Specify Timeout value * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). * @retval HAL status @@ -4324,12 +4322,12 @@ /** * @brief Decrypt pCypherData in AES ECB decryption mode with key derivation, * the decyphered data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer - * @param Timeout: Specify Timeout value + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pPlainData Pointer to the plaintext buffer + * @param Timeout Specify Timeout value * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). * @retval HAL status @@ -4355,12 +4353,12 @@ /** * @brief Decrypt pCypherData in AES CTR decryption mode, * the decyphered data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer - * @param Timeout: Specify Timeout value + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pPlainData Pointer to the plaintext buffer + * @param Timeout Specify Timeout value * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES() API instead (usage recommended). * @retval HAL status @@ -4386,11 +4384,11 @@ /** * @brief Encrypt pPlainData in AES ECB encryption mode using Interrupt, * the cypher data are available in pCypherData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). * @retval HAL status @@ -4416,11 +4414,11 @@ /** * @brief Encrypt pPlainData in AES CBC encryption mode using Interrupt, * the cypher data are available in pCypherData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). * @retval HAL status @@ -4447,11 +4445,11 @@ /** * @brief Encrypt pPlainData in AES CTR encryption mode using Interrupt, * the cypher data are available in pCypherData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). * @retval HAL status @@ -4477,11 +4475,11 @@ /** * @brief Decrypt pCypherData in AES ECB decryption mode using Interrupt, * the decyphered data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer. + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pPlainData Pointer to the plaintext buffer. * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). * @retval HAL status @@ -4507,11 +4505,11 @@ /** * @brief Decrypt pCypherData in AES CBC decryption mode using Interrupt, * the decyphered data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pPlainData Pointer to the plaintext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). * @retval HAL status @@ -4537,11 +4535,11 @@ /** * @brief Decrypt pCypherData in AES CTR decryption mode using Interrupt, * the decyphered data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pPlainData Pointer to the plaintext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_IT() API instead (usage recommended). * @retval HAL status @@ -4567,11 +4565,11 @@ /** * @brief Encrypt pPlainData in AES ECB encryption mode using DMA, * the cypher data are available in pCypherData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended). * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. @@ -4600,11 +4598,11 @@ /** * @brief Encrypt pPlainData in AES CBC encryption mode using DMA, * the cypher data are available in pCypherData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended). * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. @@ -4631,11 +4629,11 @@ /** * @brief Encrypt pPlainData in AES CTR encryption mode using DMA, * the cypher data are available in pCypherData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pCypherData: Pointer to the cyphertext buffer. + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pCypherData Pointer to the cyphertext buffer. * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended). * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. @@ -4662,11 +4660,11 @@ /** * @brief Decrypt pCypherData in AES ECB decryption mode using DMA, * the decyphered data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pPlainData Pointer to the plaintext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended). * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. @@ -4693,11 +4691,11 @@ /** * @brief Decrypt pCypherData in AES CBC decryption mode using DMA, * the decyphered data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pPlainData Pointer to the plaintext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended). * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. @@ -4724,11 +4722,11 @@ /** * @brief Decrypt pCypherData in AES CTR decryption mode using DMA, * the decyphered data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer in bytes, must be a multiple of 16. - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer in bytes, must be a multiple of 16. + * @param pPlainData Pointer to the plaintext buffer * @note This API is provided only to maintain compatibility with legacy software. Users should directly * resort to generic HAL_CRYPEx_AES_DMA() API instead (usage recommended). * @note pPlainData and pCypherData buffers must be 32-bit aligned to ensure a correct DMA transfer to and from the IP. @@ -4775,7 +4773,7 @@ /** * @brief CRYP error callback. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -4791,7 +4789,7 @@ /** * @brief Input DMA transfer complete callback. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -4807,7 +4805,7 @@ /** * @brief Output DMA transfer complete callback. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -4840,7 +4838,7 @@ /** * @brief Handle AES interrupt request. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -4925,7 +4923,7 @@ /** * @brief Return the CRYP handle state. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval HAL state */ @@ -4937,7 +4935,7 @@ /** * @brief Return the CRYP peripheral error. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @note The returned error is a bit-map combination of possible errors * @retval Error bit-map @@ -4962,7 +4960,7 @@ /** * @brief Write the Key in KeyRx registers. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -5003,7 +5001,7 @@ /** * @brief Write the InitVector/InitCounter in IVRx registers. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -5046,7 +5044,7 @@ * @brief Handle CRYP block input/output data handling under interruption. * @note The function is called under interruption only, once * interruptions have been enabled by HAL_CRYPEx_AES_IT(). - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. * @retval HAL status */
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cryp.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cryp.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_cryp.h
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief Header file of CRYP HAL module.
******************************************************************************
* @attention
@@ -258,14 +256,14 @@
*/
/** @brief Reset CRYP handle state
- * @param __HANDLE__: specifies the CRYP handle.
+ * @param __HANDLE__ specifies the CRYP handle.
* @retval None
*/
#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRYP_STATE_RESET)
/**
* @brief Enable/Disable the CRYP peripheral.
- * @param __HANDLE__: specifies the CRYP handle.
+ * @param __HANDLE__ specifies the CRYP handle.
* @retval None
*/
#define __HAL_CRYP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_CRYPEN)
@@ -273,22 +271,22 @@
/**
* @brief Flush the data FIFO.
- * @param __HANDLE__: specifies the CRYP handle.
+ * @param __HANDLE__ specifies the CRYP handle.
* @retval None
*/
#define __HAL_CRYP_FIFO_FLUSH(__HANDLE__) ((__HANDLE__)->Instance->CR |= CRYP_CR_FFLUSH)
/**
* @brief Set the algorithm mode: AES-ECB, AES-CBC, AES-CTR, DES-ECB, DES-CBC.
- * @param __HANDLE__: specifies the CRYP handle.
- * @param MODE: The algorithm mode.
+ * @param __HANDLE__ specifies the CRYP handle.
+ * @param MODE The algorithm mode.
* @retval None
*/
#define __HAL_CRYP_SET_MODE(__HANDLE__, MODE) ((__HANDLE__)->Instance->CR |= (uint32_t)(MODE))
/** @brief Check whether the specified CRYP flag is set or not.
- * @param __HANDLE__: specifies the CRYP handle.
- * @param __FLAG__: specifies the flag to check.
+ * @param __HANDLE__ specifies the CRYP handle.
+ * @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg CRYP_FLAG_BUSY: The CRYP core is currently processing a block of data
* or a key preparation (for AES decryption).
@@ -305,8 +303,8 @@
((((__HANDLE__)->Instance->RISR) & ((__FLAG__) & CRYP_FLAG_MASK)) == ((__FLAG__) & CRYP_FLAG_MASK)))
/** @brief Check whether the specified CRYP interrupt is set or not.
- * @param __HANDLE__: specifies the CRYP handle.
- * @param __INTERRUPT__: specifies the interrupt to check.
+ * @param __HANDLE__ specifies the CRYP handle.
+ * @param __INTERRUPT__ specifies the interrupt to check.
* This parameter can be one of the following values:
* @arg CRYP_IT_INRIS: Input FIFO service raw interrupt is pending
* @arg CRYP_IT_OUTRIS: Output FIFO service raw interrupt is pending
@@ -316,16 +314,16 @@
/**
* @brief Enable the CRYP interrupt.
- * @param __HANDLE__: specifies the CRYP handle.
- * @param __INTERRUPT__: CRYP Interrupt.
+ * @param __HANDLE__ specifies the CRYP handle.
+ * @param __INTERRUPT__ CRYP Interrupt.
* @retval None
*/
#define __HAL_CRYP_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) |= (__INTERRUPT__))
/**
* @brief Disable the CRYP interrupt.
- * @param __HANDLE__: specifies the CRYP handle.
- * @param __INTERRUPT__: CRYP interrupt.
+ * @param __HANDLE__ specifies the CRYP handle.
+ * @param __INTERRUPT__ CRYP interrupt.
* @retval None
*/
#define __HAL_CRYP_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->IMSCR) &= ~(__INTERRUPT__))
@@ -827,7 +825,7 @@
*/
/** @brief Reset CRYP handle state.
- * @param __HANDLE__: specifies the CRYP handle.
+ * @param __HANDLE__ specifies the CRYP handle.
* @retval None
*/
#define __HAL_CRYP_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_CRYP_STATE_RESET)
@@ -846,7 +844,7 @@
/**
* @brief Set the algorithm operating mode.
- * @param __OPERATING_MODE__: specifies the operating mode
+ * @param __OPERATING_MODE__ specifies the operating mode
* This parameter can be one of the following values:
* @arg @ref CRYP_ALGOMODE_ENCRYPT encryption
* @arg @ref CRYP_ALGOMODE_KEYDERIVATION key derivation
@@ -859,7 +857,7 @@
/**
* @brief Set the algorithm chaining mode.
- * @param __CHAINING_MODE__: specifies the chaining mode
+ * @param __CHAINING_MODE__ specifies the chaining mode
* This parameter can be one of the following values:
* @arg @ref CRYP_CHAINMODE_AES_ECB Electronic CodeBook
* @arg @ref CRYP_CHAINMODE_AES_CBC Cipher Block Chaining
@@ -873,7 +871,7 @@
/** @brief Check whether the specified CRYP status flag is set or not.
- * @param __FLAG__: specifies the flag to check.
+ * @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg @ref CRYP_FLAG_BUSY GCM process suspension forbidden
* @arg @ref CRYP_IT_WRERR Write Error
@@ -885,7 +883,7 @@
/** @brief Clear the CRYP pending status flag.
- * @param __FLAG__: specifies the flag to clear.
+ * @param __FLAG__ specifies the flag to clear.
* This parameter can be one of the following values:
* @arg @ref CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear
* @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear
@@ -896,7 +894,7 @@
/** @brief Check whether the specified CRYP interrupt source is enabled or not.
- * @param __INTERRUPT__: CRYP interrupt source to check
+ * @param __INTERRUPT__ CRYP interrupt source to check
* This parameter can be one of the following values:
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
@@ -906,7 +904,7 @@
/** @brief Check whether the specified CRYP interrupt is set or not.
- * @param __INTERRUPT__: specifies the interrupt to check.
+ * @param __INTERRUPT__ specifies the interrupt to check.
* This parameter can be one of the following values:
* @arg @ref CRYP_IT_WRERR Write Error
* @arg @ref CRYP_IT_RDERR Read Error
@@ -918,7 +916,7 @@
/** @brief Clear the CRYP pending interrupt.
- * @param __INTERRUPT__: specifies the IT to clear.
+ * @param __INTERRUPT__ specifies the IT to clear.
* This parameter can be one of the following values:
* @arg @ref CRYP_ERR_CLEAR Read (RDERR) or Write Error (WRERR) Flag Clear
* @arg @ref CRYP_CCF_CLEAR Computation Complete Flag (CCF) Clear
@@ -929,7 +927,7 @@
/**
* @brief Enable the CRYP interrupt.
- * @param __INTERRUPT__: CRYP Interrupt.
+ * @param __INTERRUPT__ CRYP Interrupt.
* This parameter can be one of the following values:
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
@@ -940,7 +938,7 @@
/**
* @brief Disable the CRYP interrupt.
- * @param __INTERRUPT__: CRYP Interrupt.
+ * @param __INTERRUPT__ CRYP Interrupt.
* This parameter can be one of the following values:
* @arg @ref CRYP_IT_ERRIE Error interrupt (used for RDERR and WRERR)
* @arg @ref CRYP_IT_CCFIE Computation Complete interrupt
@@ -959,7 +957,7 @@
/**
* @brief Verify the key size length.
- * @param __KEYSIZE__: Ciphering/deciphering algorithm key size.
+ * @param __KEYSIZE__ Ciphering/deciphering algorithm key size.
* @retval SET (__KEYSIZE__ is a valid value) or RESET (__KEYSIZE__ is invalid)
*/
#define IS_CRYP_KEYSIZE(__KEYSIZE__) (((__KEYSIZE__) == CRYP_KEYSIZE_128B) || \
@@ -967,7 +965,7 @@
/**
* @brief Verify the input data type.
- * @param __DATATYPE__: Ciphering/deciphering algorithm input data type.
+ * @param __DATATYPE__ Ciphering/deciphering algorithm input data type.
* @retval SET (__DATATYPE__ is valid) or RESET (__DATATYPE__ is invalid)
*/
#define IS_CRYP_DATATYPE(__DATATYPE__) (((__DATATYPE__) == CRYP_DATATYPE_32B) || \
@@ -977,7 +975,7 @@
/**
* @brief Verify the CRYP AES IP running mode.
- * @param __MODE__: CRYP AES IP running mode.
+ * @param __MODE__ CRYP AES IP running mode.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
*/
#define IS_CRYP_AES(__MODE__) (((__MODE__) == CRYP_AES_DISABLE) || \
@@ -985,7 +983,7 @@
/**
* @brief Verify the selected CRYP algorithm.
- * @param __ALGOMODE__: Selected CRYP algorithm (ciphering, deciphering, key derivation or a combination of the latter).
+ * @param __ALGOMODE__ Selected CRYP algorithm (ciphering, deciphering, key derivation or a combination of the latter).
* @retval SET (__ALGOMODE__ is valid) or RESET (__ALGOMODE__ is invalid)
*/
#define IS_CRYP_ALGOMODE(__ALGOMODE__) (((__ALGOMODE__) == CRYP_ALGOMODE_ENCRYPT) || \
@@ -996,7 +994,7 @@
/**
* @brief Verify the selected CRYP chaining algorithm.
- * @param __CHAINMODE__: Selected CRYP chaining algorithm.
+ * @param __CHAINMODE__ Selected CRYP chaining algorithm.
* @retval SET (__CHAINMODE__ is valid) or RESET (__CHAINMODE__ is invalid)
*/
#if defined(AES_CR_NPBLB)
@@ -1015,7 +1013,7 @@
/**
* @brief Verify the deciphering key write option.
- * @param __WRITE__: deciphering key write option.
+ * @param __WRITE__ deciphering key write option.
* @retval SET (__WRITE__ is valid) or RESET (__WRITE__ is invalid)
*/
#define IS_CRYP_WRITE(__WRITE__) (((__WRITE__) == CRYP_KEY_WRITE_ENABLE) || \
@@ -1023,7 +1021,7 @@
/**
* @brief Verify the CRYP input data DMA mode.
- * @param __MODE__: CRYP input data DMA mode.
+ * @param __MODE__ CRYP input data DMA mode.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
*/
#define IS_CRYP_DMAIN(__MODE__) (((__MODE__) == CRYP_DMAIN_DISABLE) || \
@@ -1031,7 +1029,7 @@
/**
* @brief Verify the CRYP output data DMA mode.
- * @param __MODE__: CRYP output data DMA mode.
+ * @param __MODE__ CRYP output data DMA mode.
* @retval SET (__MODE__ is valid) or RESET (__MODE__ is invalid)
*/
#define IS_CRYP_DMAOUT(__MODE__) (((__MODE__) == CRYP_DMAOUT_DISABLE) || \
@@ -1039,7 +1037,7 @@
/**
* @brief Verify the CRYP AES ciphering/deciphering/authentication algorithm phase.
- * @param __PHASE__: CRYP AES ciphering/deciphering/authentication algorithm phase.
+ * @param __PHASE__ CRYP AES ciphering/deciphering/authentication algorithm phase.
* @retval SET (__PHASE__ is valid) or RESET (__PHASE__ is invalid)
*/
#define IS_CRYP_GCMCMAC_PHASE(__PHASE__) (((__PHASE__) == CRYP_GCM_INIT_PHASE) || \
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cryp_ex.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cryp_ex.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_cryp_ex.c * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief Extended CRYP HAL module driver * This file provides firmware functions to manage the following * functionalities of CRYP extension peripheral: @@ -147,7 +145,7 @@ /** * @brief DMA CRYP Input Data process complete callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void CRYPEx_GCMCCM_DMAInCplt(DMA_HandleTypeDef *hdma) @@ -164,7 +162,7 @@ /** * @brief DMA CRYP Output Data process complete callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void CRYPEx_GCMCCM_DMAOutCplt(DMA_HandleTypeDef *hdma) @@ -187,7 +185,7 @@ /** * @brief DMA CRYP communication error callback. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void CRYPEx_GCMCCM_DMAError(DMA_HandleTypeDef *hdma) @@ -199,10 +197,10 @@ /** * @brief Writes the Key in Key registers. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param Key: Pointer to Key buffer - * @param KeySize: Size of Key + * @param Key Pointer to Key buffer + * @param KeySize Size of Key * @retval None */ static void CRYPEx_GCMCCM_SetKey(CRYP_HandleTypeDef *hcryp, uint8_t *Key, uint32_t KeySize) @@ -258,9 +256,9 @@ /** * @brief Writes the InitVector/InitCounter in IV registers. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param InitVector: Pointer to InitVector/InitCounter buffer + * @param InitVector Pointer to InitVector/InitCounter buffer * @retval None */ static void CRYPEx_GCMCCM_SetInitVector(CRYP_HandleTypeDef *hcryp, uint8_t *InitVector) @@ -278,12 +276,12 @@ /** * @brief Process Data: Writes Input data in polling mode and read the Output data. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param Input: Pointer to the Input buffer. - * @param Ilength: Length of the Input buffer, must be a multiple of 16 - * @param Output: Pointer to the returned buffer - * @param Timeout: Timeout value + * @param Input Pointer to the Input buffer. + * @param Ilength Length of the Input buffer, must be a multiple of 16 + * @param Output Pointer to the returned buffer + * @param Timeout Timeout value * @retval None */ static HAL_StatusTypeDef CRYPEx_GCMCCM_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t *Input, uint16_t Ilength, uint8_t *Output, uint32_t Timeout) @@ -341,11 +339,11 @@ /** * @brief Sets the header phase - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param Input: Pointer to the Input buffer. - * @param Ilength: Length of the Input buffer, must be a multiple of 16 - * @param Timeout: Timeout value + * @param Input Pointer to the Input buffer. + * @param Ilength Length of the Input buffer, must be a multiple of 16 + * @param Timeout Timeout value * @retval None */ static HAL_StatusTypeDef CRYPEx_GCMCCM_SetHeaderPhase(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint32_t Timeout) @@ -424,11 +422,11 @@ /** * @brief Sets the DMA configuration and start the DMA transfer. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param inputaddr: Address of the Input buffer - * @param Size: Size of the Input buffer, must be a multiple of 16 - * @param outputaddr: Address of the Output buffer + * @param inputaddr Address of the Input buffer + * @param Size Size of the Input buffer, must be a multiple of 16 + * @param outputaddr Address of the Output buffer * @retval None */ static void CRYPEx_GCMCCM_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr) @@ -492,12 +490,12 @@ /** * @brief Initializes the CRYP peripheral in AES CCM encryption mode then * encrypt pPlainData. The cypher data are available in pCypherData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Timeout duration + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) @@ -748,12 +746,12 @@ /** * @brief Initializes the CRYP peripheral in AES GCM encryption mode then * encrypt pPlainData. The cypher data are available in pCypherData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Timeout duration + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData, uint32_t Timeout) @@ -846,12 +844,12 @@ /** * @brief Initializes the CRYP peripheral in AES GCM decryption mode then * decrypted pCypherData. The cypher data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the cyphertext buffer, must be a multiple of 16 - * @param pPlainData: Pointer to the plaintext buffer - * @param Timeout: Timeout duration + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the cyphertext buffer, must be a multiple of 16 + * @param pPlainData Pointer to the plaintext buffer + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) @@ -939,11 +937,11 @@ /** * @brief Computes the authentication TAG. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param Size: Total length of the plain/cyphertext buffer - * @param AuthTag: Pointer to the authentication buffer - * @param Timeout: Timeout duration + * @param Size Total length of the plain/cyphertext buffer + * @param AuthTag Pointer to the authentication buffer + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Finish(CRYP_HandleTypeDef *hcryp, uint32_t Size, uint8_t *AuthTag, uint32_t Timeout) @@ -1048,10 +1046,10 @@ /** * @brief Computes the authentication TAG for AES CCM mode. * @note This API is called after HAL_AES_CCM_Encrypt()/HAL_AES_CCM_Decrypt() - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param AuthTag: Pointer to the authentication buffer - * @param Timeout: Timeout duration + * @param AuthTag Pointer to the authentication buffer + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Finish(CRYP_HandleTypeDef *hcryp, uint8_t *AuthTag, uint32_t Timeout) @@ -1140,12 +1138,12 @@ /** * @brief Initializes the CRYP peripheral in AES CCM decryption mode then * decrypted pCypherData. The cypher data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pCypherData: Pointer to the cyphertext buffer - * @param Timeout: Timeout duration + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 + * @param pCypherData Pointer to the cyphertext buffer + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData, uint32_t Timeout) @@ -1392,11 +1390,11 @@ /** * @brief Initializes the CRYP peripheral in AES GCM encryption mode using IT. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -1543,11 +1541,11 @@ /** * @brief Initializes the CRYP peripheral in AES CCM encryption mode using interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -1842,11 +1840,11 @@ /** * @brief Initializes the CRYP peripheral in AES GCM decryption mode using IT. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the cyphertext buffer, must be a multiple of 16 - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the cyphertext buffer, must be a multiple of 16 + * @param pPlainData Pointer to the plaintext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -1990,11 +1988,11 @@ /** * @brief Initializes the CRYP peripheral in AES CCM decryption mode using interrupt * then decrypted pCypherData. The cypher data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 + * @param pPlainData Pointer to the plaintext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_IT(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -2280,11 +2278,11 @@ /** * @brief Initializes the CRYP peripheral in AES GCM encryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -2377,11 +2375,11 @@ /** * @brief Initializes the CRYP peripheral in AES CCM encryption mode using interrupt. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pPlainData: Pointer to the plaintext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pCypherData: Pointer to the cyphertext buffer + * @param pPlainData Pointer to the plaintext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 + * @param pCypherData Pointer to the cyphertext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Encrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pPlainData, uint16_t Size, uint8_t *pCypherData) @@ -2631,11 +2629,11 @@ /** * @brief Initializes the CRYP peripheral in AES GCM decryption mode using DMA. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer. - * @param Size: Length of the cyphertext buffer, must be a multiple of 16 - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer. + * @param Size Length of the cyphertext buffer, must be a multiple of 16 + * @param pPlainData Pointer to the plaintext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESGCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -2721,11 +2719,11 @@ /** * @brief Initializes the CRYP peripheral in AES CCM decryption mode using DMA * then decrypted pCypherData. The cypher data are available in pPlainData. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pCypherData: Pointer to the cyphertext buffer - * @param Size: Length of the plaintext buffer, must be a multiple of 16 - * @param pPlainData: Pointer to the plaintext buffer + * @param pCypherData Pointer to the cyphertext buffer + * @param Size Length of the plaintext buffer, must be a multiple of 16 + * @param pPlainData Pointer to the plaintext buffer * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AESCCM_Decrypt_DMA(CRYP_HandleTypeDef *hcryp, uint8_t *pCypherData, uint16_t Size, uint8_t *pPlainData) @@ -2992,7 +2990,7 @@ /** * @brief This function handles CRYPEx interrupt request. - * @param hcryp: pointer to a CRYPEx_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYPEx_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -3099,7 +3097,7 @@ /** * @brief Computation completed callbacks. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval None */ @@ -3148,17 +3146,17 @@ * @brief Carry out in polling mode the ciphering or deciphering operation according to * hcryp->Init structure fields, all operating modes (encryption, key derivation and/or decryption) and * chaining modes ECB, CBC and CTR are managed by this function in polling mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pInputData: Pointer to the plain text in case of encryption or cipher text in case of decryption + * @param pInputData Pointer to the plain text in case of encryption or cipher text in case of decryption * or key derivation+decryption. * Parameter is meaningless in case of key derivation. - * @param Size: Length of the input data buffer in bytes, must be a multiple of 16. + * @param Size Length of the input data buffer in bytes, must be a multiple of 16. * Parameter is meaningless in case of key derivation. - * @param pOutputData: Pointer to the cipher text in case of encryption or plain text in case of + * @param pOutputData Pointer to the cipher text in case of encryption or plain text in case of * decryption/key derivation+decryption, or pointer to the derivative keys in * case of key derivation only. - * @param Timeout: Specify Timeout value + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_CRYPEx_AES(CRYP_HandleTypeDef *hcryp, uint8_t *pInputData, uint16_t Size, uint8_t *pOutputData, uint32_t Timeout) @@ -3229,14 +3227,14 @@ * @brief Carry out in interrupt mode the ciphering or deciphering operation according to * hcryp->Init structure fields, all operating modes (encryption, key derivation and/or decryption) and * chaining modes ECB, CBC and CTR are managed by this function in interrupt mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pInputData: Pointer to the plain text in case of encryption or cipher text in case of decryption + * @param pInputData Pointer to the plain text in case of encryption or cipher text in case of decryption * or key derivation+decryption. * Parameter is meaningless in case of key derivation. - * @param Size: Length of the input data buffer in bytes, must be a multiple of 16. + * @param Size Length of the input data buffer in bytes, must be a multiple of 16. * Parameter is meaningless in case of key derivation. - * @param pOutputData: Pointer to the cipher text in case of encryption or plain text in case of + * @param pOutputData Pointer to the cipher text in case of encryption or plain text in case of * decryption/key derivation+decryption, or pointer to the derivative keys in * case of key derivation only. * @retval HAL status @@ -3324,12 +3322,12 @@ /** * @brief Carry out in DMA mode the ciphering or deciphering operation according to * hcryp->Init structure fields. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pInputData: Pointer to the plain text in case of encryption or cipher text in case of decryption + * @param pInputData Pointer to the plain text in case of encryption or cipher text in case of decryption * or key derivation+decryption. - * @param Size: Length of the input data buffer in bytes, must be a multiple of 16. - * @param pOutputData: Pointer to the cipher text in case of encryption or plain text in case of + * @param Size Length of the input data buffer in bytes, must be a multiple of 16. + * @param pOutputData Pointer to the cipher text in case of encryption or plain text in case of * decryption/key derivation+decryption. * @note Chaining modes ECB, CBC and CTR are managed by this function in DMA mode. * @note Supported operating modes are encryption, decryption and key derivation with decryption. @@ -3395,24 +3393,24 @@ /** * @brief Carry out in polling mode the authentication tag generation as well as the ciphering or deciphering * operation according to hcryp->Init structure fields. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pInputData: + * @param pInputData * - pointer to payload data in GCM payload phase, * - pointer to B0 block in CMAC header phase, * - pointer to C block in CMAC final phase. * - Parameter is meaningless in case of GCM/GMAC init, header and final phases. - * @param Size: + * @param Size * - length of the input payload data buffer in bytes, * - length of B0 block (in bytes) in CMAC header phase, * - length of C block (in bytes) in CMAC final phase. * - Parameter is meaningless in case of GCM/GMAC init and header phases. - * @param pOutputData: + * @param pOutputData * - pointer to plain or cipher text in GCM payload phase, * - pointer to authentication tag in GCM/GMAC and CMAC final phases. * - Parameter is meaningless in case of GCM/GMAC init and header phases * and in case of CMAC header phase. - * @param Timeout: Specify Timeout value + * @param Timeout Specify Timeout value * @note Supported operating modes are encryption and decryption, supported chaining modes are GCM, GMAC, CMAC and CCM when the latter is applicable. * @note Phases are singly processed according to hcryp->Init.GCMCMACPhase so that steps in these specific chaining modes * can be skipped by the user if so required. @@ -3880,19 +3878,19 @@ /** * @brief Carry out in interrupt mode the authentication tag generation as well as the ciphering or deciphering * operation according to hcryp->Init structure fields. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pInputData: + * @param pInputData * - pointer to payload data in GCM payload phase, * - pointer to B0 block in CMAC header phase, * - pointer to C block in CMAC final phase. * Parameter is meaningless in case of GCM/GMAC init, header and final phases. - * @param Size: + * @param Size * - length of the input payload data buffer in bytes, * - length of B0 block (in bytes) in CMAC header phase, * - length of C block (in bytes) in CMAC final phase. * - Parameter is meaningless in case of GCM/GMAC init and header phases. - * @param pOutputData: + * @param pOutputData * - pointer to plain or cipher text in GCM payload phase, * - pointer to authentication tag in GCM/GMAC and CMAC final phases. * - Parameter is meaningless in case of GCM/GMAC init and header phases @@ -4296,19 +4294,19 @@ /** * @brief Carry out in DMA mode the authentication tag generation as well as the ciphering or deciphering * operation according to hcryp->Init structure fields. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module - * @param pInputData: + * @param pInputData * - pointer to payload data in GCM payload phase, * - pointer to B0 block in CMAC header phase, * - pointer to C block in CMAC final phase. * - Parameter is meaningless in case of GCM/GMAC init, header and final phases. - * @param Size: + * @param Size * - length of the input payload data buffer in bytes, * - length of B block (in bytes) in CMAC header phase, * - length of C block (in bytes) in CMAC final phase. * - Parameter is meaningless in case of GCM/GMAC init and header phases. - * @param pOutputData: + * @param pOutputData * - pointer to plain or cipher text in GCM payload phase, * - pointer to authentication tag in GCM/GMAC and CMAC final phases. * - Parameter is meaningless in case of GCM/GMAC init and header phases @@ -4723,9 +4721,9 @@ /** * @brief In case of message processing suspension, read the Initialization Vector. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param Output: Pointer to the buffer containing the saved Initialization Vector. + * @param Output Pointer to the buffer containing the saved Initialization Vector. * @note This value has to be stored for reuse by writing the AES_IVRx registers * as soon as the interrupted processing has to be resumed. * Applicable to all chaining modes. @@ -4748,9 +4746,9 @@ /** * @brief In case of message processing resumption, rewrite the Initialization * Vector in the AES_IVRx registers. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param Input: Pointer to the buffer containing the saved Initialization Vector to + * @param Input Pointer to the buffer containing the saved Initialization Vector to * write back in the CRYP hardware block. * @note Applicable to all chaining modes. * @note AES must be disabled when reading or resetting the IV values. @@ -4772,9 +4770,9 @@ /** * @brief In case of message GCM/GMAC or CMAC processing suspension, read the Suspend Registers. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param Output: Pointer to the buffer containing the saved Suspend Registers. + * @param Output Pointer to the buffer containing the saved Suspend Registers. * @note These values have to be stored for reuse by writing back the AES_SUSPxR registers * as soon as the interrupted processing has to be resumed. * @retval None @@ -4820,9 +4818,9 @@ /** * @brief In case of message GCM/GMAC or CMAC processing resumption, rewrite the Suspend * Registers in the AES_SUSPxR registers. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param Input: Pointer to the buffer containing the saved suspend registers to + * @param Input Pointer to the buffer containing the saved suspend registers to * write back in the CRYP hardware block. * @retval None */ @@ -4850,10 +4848,10 @@ /** * @brief In case of message GCM/GMAC or CMAC processing suspension, read the Key Registers. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param Output: Pointer to the buffer containing the saved Key Registers. - * @param KeySize: Indicates the key size (128 or 256 bits). + * @param Output Pointer to the buffer containing the saved Key Registers. + * @param KeySize Indicates the key size (128 or 256 bits). * @note These values have to be stored for reuse by writing back the AES_KEYRx registers * as soon as the interrupted processing has to be resumed. * @retval None @@ -4886,11 +4884,11 @@ /** * @brief In case of message GCM/GMAC or CMAC processing resumption, rewrite the Key * Registers in the AES_KEYRx registers. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param Input: Pointer to the buffer containing the saved key registers to + * @param Input Pointer to the buffer containing the saved key registers to * write back in the CRYP hardware block. - * @param KeySize: Indicates the key size (128 or 256 bits) + * @param KeySize Indicates the key size (128 or 256 bits) * @retval None */ void HAL_CRYPEx_Write_KeyRegisters(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint32_t KeySize) @@ -4921,9 +4919,9 @@ /** * @brief In case of message GCM/GMAC or CMAC processing suspension, read the Control Register. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param Output: Pointer to the buffer containing the saved Control Register. + * @param Output Pointer to the buffer containing the saved Control Register. * @note This values has to be stored for reuse by writing back the AES_CR register * as soon as the interrupted processing has to be resumed. * @retval None @@ -4936,9 +4934,9 @@ /** * @brief In case of message GCM/GMAC or CMAC processing resumption, rewrite the Control * Registers in the AES_CR register. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param Input: Pointer to the buffer containing the saved Control Register to + * @param Input Pointer to the buffer containing the saved Control Register to * write back in the CRYP hardware block. * @retval None */ @@ -4952,7 +4950,7 @@ /** * @brief Request CRYP processing suspension when in polling or interruption mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. * @note Set the handle field SuspendRequest to the appropriate value so that * the on-going CRYP processing is suspended as soon as the required @@ -4986,7 +4984,7 @@ * in the case of header phase where no output data DMA * transfer is on-going (only input data transfer is enabled * in such a case). - * @param hdma: DMA handle. + * @param hdma DMA handle. * @retval None */ static void CRYP_GCMCMAC_DMAInCplt(DMA_HandleTypeDef *hdma) @@ -5027,7 +5025,7 @@ * @brief DMA CRYP Output Data process complete callback * for GCM, GMAC or CMAC chainging modes. * @note This callback is called only in the payload phase. - * @param hdma: DMA handle. + * @param hdma DMA handle. * @retval None */ static void CRYP_GCMCMAC_DMAOutCplt(DMA_HandleTypeDef *hdma) @@ -5063,7 +5061,7 @@ /** * @brief DMA CRYP communication error callback * for GCM, GMAC or CMAC chainging modes. - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void CRYP_GCMCMAC_DMAError(DMA_HandleTypeDef *hdma) @@ -5084,7 +5082,7 @@ * for GCM, GMAC or CMAC chaining modes. * @note The function is called under interruption only, once * interruptions have been enabled by HAL_CRYPEx_AES_Auth_IT(). - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module * @retval HAL status */ @@ -5544,11 +5542,11 @@ /** * @brief Set the DMA configuration and start the DMA transfer * for GCM, GMAC or CMAC chainging modes. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param inputaddr: Address of the Input buffer. - * @param Size: Size of the Input buffer un bytes, must be a multiple of 16. - * @param outputaddr: Address of the Output buffer, null pointer when no output DMA stream + * @param inputaddr Address of the Input buffer. + * @param Size Size of the Input buffer un bytes, must be a multiple of 16. + * @param outputaddr Address of the Output buffer, null pointer when no output DMA stream * has to be configured. * @retval None */ @@ -5592,12 +5590,12 @@ /** * @brief Write/read input/output data in polling mode. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param Input: Pointer to the Input buffer. - * @param Ilength: Length of the Input buffer in bytes, must be a multiple of 16. - * @param Output: Pointer to the returned buffer. - * @param Timeout: Specify Timeout value. + * @param Input Pointer to the Input buffer. + * @param Ilength Length of the Input buffer in bytes, must be a multiple of 16. + * @param Output Pointer to the returned buffer. + * @param Timeout Specify Timeout value. * @retval HAL status */ static HAL_StatusTypeDef CRYP_ProcessData(CRYP_HandleTypeDef *hcryp, uint8_t* Input, uint16_t Ilength, uint8_t* Output, uint32_t Timeout) @@ -5673,10 +5671,10 @@ /** * @brief Read derivative key in polling mode when CRYP hardware block is set * in key derivation operating mode (mode 2). - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param Output: Pointer to the returned buffer. - * @param Timeout: Specify Timeout value. + * @param Output Pointer to the returned buffer. + * @param Timeout Specify Timeout value. * @retval HAL status */ static HAL_StatusTypeDef CRYP_ReadKey(CRYP_HandleTypeDef *hcryp, uint8_t* Output, uint32_t Timeout) @@ -5721,11 +5719,11 @@ /** * @brief Set the DMA configuration and start the DMA transfer. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param inputaddr: Address of the Input buffer. - * @param Size: Size of the Input buffer in bytes, must be a multiple of 16. - * @param outputaddr: Address of the Output buffer. + * @param inputaddr Address of the Input buffer. + * @param Size Size of the Input buffer in bytes, must be a multiple of 16. + * @param outputaddr Address of the Output buffer. * @retval None */ static void CRYP_SetDMAConfig(CRYP_HandleTypeDef *hcryp, uint32_t inputaddr, uint16_t Size, uint32_t outputaddr) @@ -5756,9 +5754,9 @@ /** * @brief Handle CRYP hardware block Timeout when waiting for CCF flag to be raised. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param Timeout: Timeout duration. + * @param Timeout Timeout duration. * @retval HAL status */ static HAL_StatusTypeDef CRYP_WaitOnCCFlag(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) @@ -5784,9 +5782,9 @@ /** * @brief Wait for Busy Flag to be reset during a GCM payload encryption process suspension. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param Timeout: Timeout duration. + * @param Timeout Timeout duration. * @retval HAL status */ static HAL_StatusTypeDef CRYP_WaitOnBusyFlagReset(CRYP_HandleTypeDef *hcryp, uint32_t Timeout) @@ -5813,7 +5811,7 @@ /** * @brief DMA CRYP Input Data process complete callback. - * @param hdma: DMA handle. + * @param hdma DMA handle. * @retval None */ static void CRYP_DMAInCplt(DMA_HandleTypeDef *hdma) @@ -5829,7 +5827,7 @@ /** * @brief DMA CRYP Output Data process complete callback. - * @param hdma: DMA handle. + * @param hdma DMA handle. * @retval None */ static void CRYP_DMAOutCplt(DMA_HandleTypeDef *hdma) @@ -5854,7 +5852,7 @@ /** * @brief DMA CRYP communication error callback. - * @param hdma: DMA handle. + * @param hdma DMA handle. * @retval None */ static void CRYP_DMAError(DMA_HandleTypeDef *hdma) @@ -5870,10 +5868,10 @@ /** * @brief Last header or payload block padding when size is not a multiple of 128 bits. - * @param hcryp: pointer to a CRYP_HandleTypeDef structure that contains + * @param hcryp pointer to a CRYP_HandleTypeDef structure that contains * the configuration information for CRYP module. - * @param difflength: size remainder after having fed all complete 128-bit blocks. - * @param polling: specifies whether or not polling on CCF must be done after having + * @param difflength size remainder after having fed all complete 128-bit blocks. + * @param polling specifies whether or not polling on CCF must be done after having * entered a complete block. * @retval None */
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cryp_ex.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_cryp_ex.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_cryp_ex.h
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief Header file of CRYP HAL Extension module.
******************************************************************************
* @attention
@@ -98,8 +96,8 @@
/**
* @brief Set the phase: Init, header, payload, final.
* This is relevant only for GCM and CCM modes.
- * @param __HANDLE__: specifies the CRYP handle.
- * @param __PHASE__: The phase.
+ * @param __HANDLE__ specifies the CRYP handle.
+ * @param __PHASE__ The phase.
* @retval None
*/
#define __HAL_CRYP_SET_PHASE(__HANDLE__, __PHASE__) do{(__HANDLE__)->Instance->CR &= (uint32_t)(~CRYP_CR_GCM_CCMPH);\
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dac.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dac.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_dac.c * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief DAC HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Digital to Analog Converter (DAC) peripheral: @@ -223,7 +221,7 @@ /** * @brief Initializes the DAC peripheral according to the specified parameters * in the DAC_InitStruct. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval HAL status */ @@ -260,7 +258,7 @@ /** * @brief Deinitializes the DAC peripheral registers to their default reset values. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval HAL status */ @@ -296,7 +294,7 @@ /** * @brief Initializes the DAC MSP. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -312,7 +310,7 @@ /** * @brief DeInitializes the DAC MSP. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -350,9 +348,9 @@ /** * @brief Enables DAC and starts conversion of channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected @@ -409,9 +407,9 @@ /** * @brief Disables DAC and stop conversion of channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected @@ -434,15 +432,15 @@ /** * @brief Enables DAC and starts conversion of channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @param pData: The Source memory Buffer address. - * @param Length: The length of data to be transferred from memory to DAC peripheral - * @param Alignment: Specifies the data alignment for DAC channel. + * @param pData The Source memory Buffer address. + * @param Length The length of data to be transferred from memory to DAC peripheral + * @param Alignment Specifies the data alignment for DAC channel. * This parameter can be one of the following values: * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected @@ -560,9 +558,9 @@ /** * @brief Disables DAC and stop conversion of channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected @@ -610,9 +608,9 @@ /** * @brief Returns the last data output value of the selected DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected @@ -636,7 +634,7 @@ /** * @brief Handles DAC interrupt request - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -682,7 +680,7 @@ /** * @brief Conversion complete callback in non blocking mode for Channel1 - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -698,7 +696,7 @@ /** * @brief Conversion half DMA transfer callback in non blocking mode for Channel1 - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -714,7 +712,7 @@ /** * @brief Error DAC callback for Channel1. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -730,7 +728,7 @@ /** * @brief DMA underrun DAC callback for channel1. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -765,10 +763,10 @@ /** * @brief Configures the selected DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param sConfig: DAC configuration structure. - * @param Channel: The selected DAC channel. + * @param sConfig DAC configuration structure. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected @@ -816,18 +814,18 @@ /** * @brief Set the specified data holding register value for DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @param Alignment: Specifies the data alignment. + * @param Alignment Specifies the data alignment. * This parameter can be one of the following values: * @arg DAC_ALIGN_8B_R: 8bit right data alignment selected * @arg DAC_ALIGN_12B_L: 12bit left data alignment selected * @arg DAC_ALIGN_12B_R: 12bit right data alignment selected - * @param Data: Data to be loaded in the selected data holding register. + * @param Data Data to be loaded in the selected data holding register. * @retval HAL status */ HAL_StatusTypeDef HAL_DAC_SetValue(DAC_HandleTypeDef* hdac, uint32_t Channel, uint32_t Alignment, uint32_t Data) @@ -878,7 +876,7 @@ /** * @brief return the DAC state - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval HAL state */ @@ -891,7 +889,7 @@ /** * @brief Return the DAC error code - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval DAC Error Code */ @@ -906,7 +904,7 @@ /** * @brief DMA conversion complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -921,7 +919,7 @@ /** * @brief DMA half transfer complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -934,7 +932,7 @@ /** * @brief DMA error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dac.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dac.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_dac.h
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief Header file of DAC HAL module.
******************************************************************************
* @attention
@@ -196,22 +194,22 @@
*/
/** @brief Reset DAC handle state
- * @param __HANDLE__: specifies the DAC handle.
+ * @param __HANDLE__ specifies the DAC handle.
* @retval None
*/
#define __HAL_DAC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DAC_STATE_RESET)
/** @brief Enable the DAC channel
- * @param __HANDLE__: specifies the DAC handle.
- * @param __DAC_CHANNEL__: specifies the DAC channel
+ * @param __HANDLE__ specifies the DAC handle.
+ * @param __DAC_CHANNEL__ specifies the DAC channel
* @retval None
*/
#define __HAL_DAC_ENABLE(__HANDLE__, __DAC_CHANNEL__) \
((__HANDLE__)->Instance->CR |= (DAC_CR_EN1 << (__DAC_CHANNEL__)))
/** @brief Disable the DAC channel
- * @param __HANDLE__: specifies the DAC handle
- * @param __DAC_CHANNEL__: specifies the DAC channel.
+ * @param __HANDLE__ specifies the DAC handle
+ * @param __DAC_CHANNEL__ specifies the DAC channel.
* @retval None
*/
#define __HAL_DAC_DISABLE(__HANDLE__, __DAC_CHANNEL__) \
@@ -219,22 +217,22 @@
/** @brief Enable the DAC interrupt
- * @param __HANDLE__: specifies the DAC handle
- * @param __INTERRUPT__: specifies the DAC interrupt.
+ * @param __HANDLE__ specifies the DAC handle
+ * @param __INTERRUPT__ specifies the DAC interrupt.
* @retval None
*/
#define __HAL_DAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) |= (__INTERRUPT__))
/** @brief Disable the DAC interrupt
- * @param __HANDLE__: specifies the DAC handle
- * @param __INTERRUPT__: specifies the DAC interrupt.
+ * @param __HANDLE__ specifies the DAC handle
+ * @param __INTERRUPT__ specifies the DAC interrupt.
* @retval None
*/
#define __HAL_DAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR) &= ~(__INTERRUPT__))
/** @brief Checks if the specified DAC interrupt source is enabled or disabled.
- * @param __HANDLE__: DAC handle
- * @param __INTERRUPT__: DAC interrupt source to check
+ * @param __HANDLE__ DAC handle
+ * @param __INTERRUPT__ DAC interrupt source to check
* This parameter can be any combination of the following values:
* @arg DAC_IT_DMAUDR1: DAC channel 1 DMA underrun interrupt
* @arg DAC_IT_DMAUDR2: DAC channel 2 DMA underrun interrupt
@@ -243,8 +241,8 @@
#define __HAL_DAC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR & (__INTERRUPT__)) == (__INTERRUPT__))
/** @brief Get the selected DAC's flag status.
- * @param __HANDLE__: specifies the DAC handle.
- * @param __FLAG__: specifies the flag to clear.
+ * @param __HANDLE__ specifies the DAC handle.
+ * @param __FLAG__ specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag
* @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag
@@ -253,8 +251,8 @@
#define __HAL_DAC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
/** @brief Clear the DAC's flag.
- * @param __HANDLE__: specifies the DAC handle.
- * @param __FLAG__: specifies the flag to clear.
+ * @param __HANDLE__ specifies the DAC handle.
+ * @param __FLAG__ specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg DAC_FLAG_DMAUDR1: DMA underrun 1 flag
* @arg DAC_FLAG_DMAUDR2: DMA underrun 2 flag
@@ -362,19 +360,19 @@
((TRIGGER) == DAC_TRIGGER_SOFTWARE))
/** @brief Set DHR12R1 alignment
- * @param __ALIGNMENT__: specifies the DAC alignment
+ * @param __ALIGNMENT__ specifies the DAC alignment
* @retval None
*/
#define DAC_DHR12R1_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000008U) + (__ALIGNMENT__))
/** @brief Set DHR12R2 alignment
- * @param __ALIGNMENT__: specifies the DAC alignment
+ * @param __ALIGNMENT__ specifies the DAC alignment
* @retval None
*/
#define DAC_DHR12R2_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000014U) + (__ALIGNMENT__))
/** @brief Set DHR12RD alignment
- * @param __ALIGNMENT__: specifies the DAC alignment
+ * @param __ALIGNMENT__ specifies the DAC alignment
* @retval None
*/
#define DAC_DHR12RD_ALIGNMENT(__ALIGNMENT__) (((uint32_t)0x00000020U) + (__ALIGNMENT__))
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dac_ex.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dac_ex.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_dac_ex.c * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief Extended DAC HAL module driver. * This file provides firmware functions to manage the following * functionalities of DAC extension peripheral: @@ -99,7 +97,7 @@ /** * @brief Returns the last data output value of the selected DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval The selected DAC channel data output value. */ @@ -117,13 +115,13 @@ /** * @brief Enables or disables the selected DAC channel wave generation. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @param Amplitude: Select max triangle amplitude. + * @param Amplitude Select max triangle amplitude. * This parameter can be one of the following values: * @arg DAC_TRIANGLEAMPLITUDE_1: Select max triangle amplitude of 1 * @arg DAC_TRIANGLEAMPLITUDE_3: Select max triangle amplitude of 3 @@ -166,13 +164,13 @@ /** * @brief Enables or disables the selected DAC channel wave generation. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Channel: The selected DAC channel. + * @param Channel The selected DAC channel. * This parameter can be one of the following values: * @arg DAC_CHANNEL_1: DAC Channel1 selected * @arg DAC_CHANNEL_2: DAC Channel2 selected - * @param Amplitude: Unmask DAC channel LFSR for noise wave generation. + * @param Amplitude Unmask DAC channel LFSR for noise wave generation. * This parameter can be one of the following values: * @arg DAC_LFSRUNMASK_BIT0: Unmask DAC channel LFSR bit0 for noise wave generation * @arg DAC_LFSRUNMASK_BITS1_0: Unmask DAC channel LFSR bit[1:0] for noise wave generation @@ -215,15 +213,15 @@ /** * @brief Set the specified data holding register value for dual DAC channel. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. - * @param Alignment: Specifies the data alignment for dual channel DAC. + * @param Alignment Specifies the data alignment for dual channel DAC. * This parameter can be one of the following values: * DAC_ALIGN_8B_R: 8bit right data alignment selected * DAC_ALIGN_12B_L: 12bit left data alignment selected * DAC_ALIGN_12B_R: 12bit right data alignment selected - * @param Data1: Data for DAC Channel2 to be loaded in the selected data holding register. - * @param Data2: Data for DAC Channel1 to be loaded in the selected data holding register. + * @param Data1 Data for DAC Channel2 to be loaded in the selected data holding register. + * @param Data2 Data for DAC Channel1 to be loaded in the selected data holding register. * @note In dual mode, a unique register access is required to write in both * DAC channels at the same time. * @retval HAL status @@ -263,7 +261,7 @@ /** * @brief Conversion complete callback in non blocking mode for Channel2 - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -279,7 +277,7 @@ /** * @brief Conversion half DMA transfer callback in non blocking mode for Channel2 - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -295,7 +293,7 @@ /** * @brief Error DAC callback for Channel2. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -311,7 +309,7 @@ /** * @brief DMA underrun DAC callback for channel2. - * @param hdac: pointer to a DAC_HandleTypeDef structure that contains + * @param hdac pointer to a DAC_HandleTypeDef structure that contains * the configuration information for the specified DAC. * @retval None */ @@ -327,7 +325,7 @@ /** * @brief DMA conversion complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -342,7 +340,7 @@ /** * @brief DMA half transfer complete callback. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -355,7 +353,7 @@ /** * @brief DMA error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dac_ex.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dac_ex.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_dac.h * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief Header file of DAC HAL Extension module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dcmi.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dcmi.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_dcmi.c
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief DCMI HAL module driver
* This file provides firmware functions to manage the following
* functionalities of the Digital Camera Interface (DCMI) peripheral:
@@ -108,13 +106,6 @@
/* Private define ------------------------------------------------------------*/
#define HAL_TIMEOUT_DCMI_STOP ((uint32_t)1000) /* Set timeout to 1s */
-#define DCMI_POSITION_CWSIZE_VLINE (uint32_t)POSITION_VAL(DCMI_CWSIZE_VLINE) /*!< Required left shift to set crop window vertical line count */
-#define DCMI_POSITION_CWSTRT_VST (uint32_t)POSITION_VAL(DCMI_CWSTRT_VST) /*!< Required left shift to set crop window vertical start line count */
-
-#define DCMI_POSITION_ESCR_LSC (uint32_t)POSITION_VAL(DCMI_ESCR_LSC) /*!< Required left shift to set line start delimiter */
-#define DCMI_POSITION_ESCR_LEC (uint32_t)POSITION_VAL(DCMI_ESCR_LEC) /*!< Required left shift to set line end delimiter */
-#define DCMI_POSITION_ESCR_FEC (uint32_t)POSITION_VAL(DCMI_ESCR_FEC) /*!< Required left shift to set frame end delimiter */
-
/* Private macro -------------------------------------------------------------*/
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
@@ -145,7 +136,7 @@
/**
* @brief Initializes the DCMI according to the specified
* parameters in the DCMI_InitTypeDef and create the associated handle.
- * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @retval HAL status
*/
@@ -196,9 +187,9 @@
if(hdcmi->Init.SynchroMode == DCMI_SYNCHRO_EMBEDDED)
{
hdcmi->Instance->ESCR = (((uint32_t)hdcmi->Init.SyncroCode.FrameStartCode) |\
- ((uint32_t)hdcmi->Init.SyncroCode.LineStartCode << DCMI_POSITION_ESCR_LSC)|\
- ((uint32_t)hdcmi->Init.SyncroCode.LineEndCode << DCMI_POSITION_ESCR_LEC) |\
- ((uint32_t)hdcmi->Init.SyncroCode.FrameEndCode << DCMI_POSITION_ESCR_FEC));
+ ((uint32_t)hdcmi->Init.SyncroCode.LineStartCode << DCMI_ESCR_LSC_Pos)|\
+ ((uint32_t)hdcmi->Init.SyncroCode.LineEndCode << DCMI_ESCR_LEC_Pos) |\
+ ((uint32_t)hdcmi->Init.SyncroCode.FrameEndCode << DCMI_ESCR_FEC_Pos));
}
@@ -217,7 +208,7 @@
/**
* @brief Deinitializes the DCMI peripheral registers to their default reset
* values.
- * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @retval HAL status
*/
@@ -241,7 +232,7 @@
/**
* @brief Initializes the DCMI MSP.
- * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @retval None
*/
@@ -257,7 +248,7 @@
/**
* @brief DeInitializes the DCMI MSP.
- * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @retval None
*/
@@ -293,11 +284,11 @@
/**
* @brief Enables DCMI DMA request and enables DCMI capture
- * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
- * @param DCMI_Mode: DCMI capture mode snapshot or continuous grab.
- * @param pData: The destination memory Buffer address (LCD Frame buffer).
- * @param Length: The length of capture to be transferred.
+ * @param DCMI_Mode DCMI capture mode snapshot or continuous grab.
+ * @param pData The destination memory Buffer address (LCD Frame buffer).
+ * @param Length The length of capture to be transferred.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_Start_DMA(DCMI_HandleTypeDef* hdcmi, uint32_t DCMI_Mode, uint32_t pData, uint32_t Length)
@@ -379,7 +370,7 @@
/**
* @brief Disable DCMI DMA request and Disable DCMI capture
- * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @retval HAL status
*/
@@ -432,7 +423,7 @@
/**
* @brief Suspend DCMI capture
- * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @retval HAL status
*/
@@ -478,7 +469,7 @@
/**
* @brief Resume DCMI capture
- * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @retval HAL status
*/
@@ -504,7 +495,7 @@
/**
* @brief Handles DCMI interrupt request.
- * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for the DCMI.
* @retval None
*/
@@ -589,7 +580,7 @@
/**
* @brief Error DCMI callback.
- * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @retval None
*/
@@ -605,7 +596,7 @@
/**
* @brief Line Event callback.
- * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @retval None
*/
@@ -618,7 +609,7 @@
/**
* @brief VSYNC Event callback.
- * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @retval None
*/
@@ -634,7 +625,7 @@
/**
* @brief Frame Event callback.
- * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @retval None
*/
@@ -670,12 +661,12 @@
/**
* @brief Configure the DCMI CROP coordinate.
- * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
- * @param YSize: DCMI Line number
- * @param XSize: DCMI Pixel per line
- * @param X0: DCMI window X offset
- * @param Y0: DCMI window Y offset
+ * @param YSize DCMI Line number
+ * @param XSize DCMI Pixel per line
+ * @param X0 DCMI window X offset
+ * @param Y0 DCMI window Y offset
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DCMI_ConfigCrop(DCMI_HandleTypeDef *hdcmi, uint32_t X0, uint32_t Y0, uint32_t XSize, uint32_t YSize)
@@ -693,8 +684,8 @@
assert_param(IS_DCMI_WINDOW_COORDINATE(YSize));
/* Configure CROP */
- hdcmi->Instance->CWSIZER = (XSize | (YSize << DCMI_POSITION_CWSIZE_VLINE));
- hdcmi->Instance->CWSTRTR = (X0 | (Y0 << DCMI_POSITION_CWSTRT_VST));
+ hdcmi->Instance->CWSIZER = (XSize | (YSize << DCMI_CWSIZE_VLINE_Pos));
+ hdcmi->Instance->CWSTRTR = (X0 | (Y0 << DCMI_CWSTRT_VST_Pos));
/* Initialize the DCMI state*/
hdcmi->State = HAL_DCMI_STATE_READY;
@@ -707,7 +698,7 @@
/**
* @brief Disable the Crop feature.
- * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @retval HAL status
*/
@@ -733,7 +724,7 @@
/**
* @brief Enable the Crop feature.
- * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @retval HAL status
*/
@@ -779,7 +770,7 @@
/**
* @brief Return the DCMI state
- * @param hdcmi: pointer to a DCMI_HandleTypeDef structure that contains
+ * @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @retval HAL state
*/
@@ -790,7 +781,7 @@
/**
* @brief Return the DCMI error code
-* @param hdcmi : pointer to a DCMI_HandleTypeDef structure that contains
+* @param hdcmi pointer to a DCMI_HandleTypeDef structure that contains
* the configuration information for DCMI.
* @retval DCMI Error Code
*/
@@ -808,7 +799,7 @@
*/
/**
* @brief DMA conversion complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -865,7 +856,7 @@
/**
* @brief DMA error callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dcmi.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dcmi.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_dcmi.h * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief Header file of DCMI HAL module. ****************************************************************************** * @attention @@ -372,21 +370,21 @@ */ /** @brief Reset DCMI handle state - * @param __HANDLE__: specifies the DCMI handle. + * @param __HANDLE__ specifies the DCMI handle. * @retval None */ #define __HAL_DCMI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DCMI_STATE_RESET) /** * @brief Enable the DCMI. - * @param __HANDLE__: DCMI handle + * @param __HANDLE__ DCMI handle * @retval None */ #define __HAL_DCMI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DCMI_CR_ENABLE) /** * @brief Disable the DCMI. - * @param __HANDLE__: DCMI handle + * @param __HANDLE__ DCMI handle * @retval None */ #define __HAL_DCMI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(DCMI_CR_ENABLE)) @@ -394,8 +392,8 @@ /* Interrupt & Flag management */ /** * @brief Get the DCMI pending flag. - * @param __HANDLE__: DCMI handle - * @param __FLAG__: Get the specified flag. + * @param __HANDLE__ DCMI handle + * @param __FLAG__ Get the specified flag. * This parameter can be one of the following values (no combination allowed) * @arg DCMI_FLAG_HSYNC: HSYNC pin state (active line / synchronization between lines) * @arg DCMI_FLAG_VSYNC: VSYNC pin state (active frame / synchronization between frames) @@ -418,8 +416,8 @@ /** * @brief Clear the DCMI pending flags. - * @param __HANDLE__: DCMI handle - * @param __FLAG__: specifies the flag to clear. + * @param __HANDLE__ DCMI handle + * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: * @arg DCMI_FLAG_FRAMERI: Frame capture complete flag mask * @arg DCMI_FLAG_OVFRI: Overflow flag mask @@ -432,8 +430,8 @@ /** * @brief Enable the specified DCMI interrupts. - * @param __HANDLE__: DCMI handle - * @param __INTERRUPT__: specifies the DCMI interrupt sources to be enabled. + * @param __HANDLE__ DCMI handle + * @param __INTERRUPT__ specifies the DCMI interrupt sources to be enabled. * This parameter can be any combination of the following values: * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask * @arg DCMI_IT_OVF: Overflow interrupt mask @@ -446,8 +444,8 @@ /** * @brief Disable the specified DCMI interrupts. - * @param __HANDLE__: DCMI handle - * @param __INTERRUPT__: specifies the DCMI interrupt sources to be enabled. + * @param __HANDLE__ DCMI handle + * @param __INTERRUPT__ specifies the DCMI interrupt sources to be enabled. * This parameter can be any combination of the following values: * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask * @arg DCMI_IT_OVF: Overflow interrupt mask @@ -460,8 +458,8 @@ /** * @brief Check whether the specified DCMI interrupt has occurred or not. - * @param __HANDLE__: DCMI handle - * @param __INTERRUPT__: specifies the DCMI interrupt source to check. + * @param __HANDLE__ DCMI handle + * @param __INTERRUPT__ specifies the DCMI interrupt source to check. * This parameter can be one of the following values: * @arg DCMI_IT_FRAME: Frame capture complete interrupt mask * @arg DCMI_IT_OVF: Overflow interrupt mask @@ -505,8 +503,6 @@ void HAL_DCMI_LineEventCallback(DCMI_HandleTypeDef *hdcmi); void HAL_DCMI_FrameEventCallback(DCMI_HandleTypeDef *hdcmi); void HAL_DCMI_VsyncEventCallback(DCMI_HandleTypeDef *hdcmi); -void HAL_DCMI_VsyncCallback(DCMI_HandleTypeDef *hdcmi); -void HAL_DCMI_HsyncCallback(DCMI_HandleTypeDef *hdcmi); void HAL_DCMI_IRQHandler(DCMI_HandleTypeDef *hdcmi); /** * @}
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dcmi_ex.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dcmi_ex.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_dcmi_ex.c * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief Empty file; This file is no longer used to handle the Black&White * feature. Its content is now moved to common files * (stm32f7xx_hal_dcmi.c/.h) as there's no device's dependency within F7
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dcmi_ex.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dcmi_ex.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_dcmi_ex.h * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief Header file of DCMI Extension HAL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_def.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_def.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_def.h
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief This file contains HAL common defines, enumeration, macros and
* structures definitions.
******************************************************************************
@@ -48,6 +46,7 @@
#include "stm32f7xx.h"
#include "stm32_hal_legacy.h"
#include <stdio.h>
+
/* Exported types ------------------------------------------------------------*/
/**
@@ -66,11 +65,14 @@
*/
typedef enum
{
- HAL_UNLOCKED = 0x00,
- HAL_LOCKED = 0x01
+ HAL_UNLOCKED = 0x00U,
+ HAL_LOCKED = 0x01U
} HAL_LockTypeDef;
/* Exported macro ------------------------------------------------------------*/
+
+#define UNUSED(X) (void)X /* To avoid gcc/g++ warnings */
+
#define HAL_MAX_DELAY 0xFFFFFFFFU
#define HAL_IS_BIT_SET(REG, BIT) (((REG) & (BIT)) != RESET)
@@ -82,10 +84,8 @@
(__DMA_HANDLE__).Parent = (__HANDLE__); \
} while(0)
-#define UNUSED(x) ((void)(x))
-
/** @brief Reset the Handle's State field.
- * @param __HANDLE__: specifies the Peripheral Handle.
+ * @param __HANDLE__ specifies the Peripheral Handle.
* @note This macro can be used for the following purpose:
* - When the Handle is declared as local variable; before passing it as parameter
* to HAL_PPP_Init() for the first time, it is mandatory to use this macro
@@ -101,7 +101,7 @@
*/
#define __HAL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = 0U)
-#if (USE_RTOS == 1)
+#if (USE_RTOS == 1U)
/* Reserved for future use */
#error "USE_RTOS should be 0 in the current HAL release"
#else
@@ -115,12 +115,12 @@
{ \
(__HANDLE__)->Lock = HAL_LOCKED; \
} \
- }while (0)
+ }while (0U)
#define __HAL_UNLOCK(__HANDLE__) \
do{ \
(__HANDLE__)->Lock = HAL_UNLOCKED; \
- }while (0)
+ }while (0U)
#endif /* USE_RTOS */
#if defined (__CC_ARM)
#pragma diag_suppress 3731
@@ -156,7 +156,7 @@
/* Macro to get variable aligned on 4-bytes, for __ICCARM__ the directive "#pragma data_alignment=4" must be used instead */
-#if defined (__GNUC__) /* GNU Compiler */
+#if defined ( __GNUC__ ) && !defined (__CC_ARM) /* GNU Compiler */
#ifndef __ALIGN_END
#define __ALIGN_END __attribute__ ((aligned (4)))
#endif /* __ALIGN_END */
@@ -169,15 +169,23 @@
#endif /* __ALIGN_END */
#ifndef __ALIGN_BEGIN
#if defined (__CC_ARM) /* ARM Compiler */
- #define __ALIGN_BEGIN __align(4)
+ #define __ALIGN_BEGIN __align(4)
#elif defined (__ICCARM__) /* IAR Compiler */
#define __ALIGN_BEGIN
#endif /* __CC_ARM */
#endif /* __ALIGN_BEGIN */
#endif /* __GNUC__ */
+/* Macro to get variable aligned on 32-bytes,needed for cache maintenance purpose */
+#if defined (__GNUC__) /* GNU Compiler */
+ #define ALIGN_32BYTES(buf) buf __attribute__ ((aligned (32)))
+#elif defined (__ICCARM__) /* IAR Compiler */
+ #define ALIGN_32BYTES(buf) _Pragma("data_alignment=32") buf
+#elif defined (__CC_ARM) /* ARM Compiler */
+ #define ALIGN_32BYTES(buf) __align(32) buf
+#endif
-/**
+/**
* @brief __RAM_FUNC definition
*/
#if defined ( __CC_ARM )
@@ -190,14 +198,14 @@
Available memory areas are declared in the 'Target' tab of the 'Options for Target'
dialog.
*/
-#define __RAM_FUNC HAL_StatusTypeDef
+#define __RAM_FUNC
#elif defined ( __ICCARM__ )
/* ICCARM Compiler
---------------
RAM functions are defined using a specific toolchain keyword "__ramfunc".
*/
-#define __RAM_FUNC __ramfunc HAL_StatusTypeDef
+#define __RAM_FUNC __ramfunc
#elif defined ( __GNUC__ )
/* GNU Compiler
@@ -205,7 +213,7 @@
RAM functions are defined using a specific toolchain attribute
"__attribute__((section(".RamFunc")))".
*/
-#define __RAM_FUNC HAL_StatusTypeDef __attribute__((section(".RamFunc")))
+#define __RAM_FUNC __attribute__((section(".RamFunc")))
#endif
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dfsdm.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dfsdm.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_dfsdm.c
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief This file provides firmware functions to manage the following
* functionalities of the Digital Filter for Sigma-Delta Modulators
* (DFSDM) peripherals:
@@ -206,27 +204,9 @@
/** @defgroup DFSDM_Private_Define DFSDM Private Define
* @{
*/
-#define DFSDM_CHCFGR1_CLK_DIV_OFFSET POSITION_VAL(DFSDM_CHCFGR1_CKOUTDIV)
-#define DFSDM_CHAWSCDR_BKSCD_OFFSET POSITION_VAL(DFSDM_CHAWSCDR_BKSCD)
-#define DFSDM_CHAWSCDR_FOSR_OFFSET POSITION_VAL(DFSDM_CHAWSCDR_AWFOSR)
-#define DFSDM_CHCFGR2_OFFSET_OFFSET POSITION_VAL(DFSDM_CHCFGR2_OFFSET)
-#define DFSDM_CHCFGR2_DTRBS_OFFSET POSITION_VAL(DFSDM_CHCFGR2_DTRBS)
-#define DFSDM_FLTFCR_FOSR_OFFSET POSITION_VAL(DFSDM_FLTFCR_FOSR)
+
#define DFSDM_FLTCR1_MSB_RCH_OFFSET 8
-#define DFSDM_FLTCR2_EXCH_OFFSET POSITION_VAL(DFSDM_FLTCR2_EXCH)
-#define DFSDM_FLTCR2_AWDCH_OFFSET POSITION_VAL(DFSDM_FLTCR2_AWDCH)
-#define DFSDM_FLTISR_CKABF_OFFSET POSITION_VAL(DFSDM_FLTISR_CKABF)
-#define DFSDM_FLTISR_SCDF_OFFSET POSITION_VAL(DFSDM_FLTISR_SCDF)
-#define DFSDM_FLTICR_CLRCKABF_OFFSET POSITION_VAL(DFSDM_FLTICR_CLRCKABF)
-#define DFSDM_FLTICR_CLRSCDF_OFFSET POSITION_VAL(DFSDM_FLTICR_CLRSCSDF)
-#define DFSDM_FLTRDATAR_DATA_OFFSET POSITION_VAL(DFSDM_FLTRDATAR_RDATA)
-#define DFSDM_FLTJDATAR_DATA_OFFSET POSITION_VAL(DFSDM_FLTJDATAR_JDATA)
-#define DFSDM_FLTAWHTR_THRESHOLD_OFFSET POSITION_VAL(DFSDM_FLTAWHTR_AWHT)
-#define DFSDM_FLTAWLTR_THRESHOLD_OFFSET POSITION_VAL(DFSDM_FLTAWLTR_AWLT)
-#define DFSDM_FLTEXMAX_DATA_OFFSET POSITION_VAL(DFSDM_FLTEXMAX_EXMAX)
-#define DFSDM_FLTEXMIN_DATA_OFFSET POSITION_VAL(DFSDM_FLTEXMIN_EXMIN)
-#define DFSDM_FLTCNVTIMR_DATA_OFFSET POSITION_VAL(DFSDM_FLTCNVTIMR_CNVCNT)
-#define DFSDM_FLTAWSR_HIGH_OFFSET POSITION_VAL(DFSDM_FLTAWSR_AWHTF)
+
#define DFSDM_MSB_MASK 0xFFFF0000U
#define DFSDM_LSB_MASK 0x0000FFFFU
#define DFSDM_CKAB_TIMEOUT 5000U
@@ -287,7 +267,7 @@
/**
* @brief Initialize the DFSDM channel according to the specified parameters
* in the DFSDM_ChannelInitTypeDef structure and initialize the associated handle.
- * @param hdfsdm_channel : DFSDM channel handle.
+ * @param hdfsdm_channel DFSDM channel handle.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DFSDM_ChannelInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
@@ -338,7 +318,7 @@
assert_param(IS_DFSDM_CHANNEL_OUTPUT_CLOCK_DIVIDER(hdfsdm_channel->Init.OutputClock.Divider));
/* Set the output clock divider */
DFSDM1_Channel0->CHCFGR1 |= (uint32_t) ((hdfsdm_channel->Init.OutputClock.Divider - 1) <<
- DFSDM_CHCFGR1_CLK_DIV_OFFSET);
+ DFSDM_CHCFGR1_CKOUTDIV_Pos);
}
/* enable the DFSDM global interface */
@@ -360,12 +340,12 @@
/* Set analog watchdog parameters */
hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_AWFORD | DFSDM_CHAWSCDR_AWFOSR);
hdfsdm_channel->Instance->CHAWSCDR |= (hdfsdm_channel->Init.Awd.FilterOrder |
- ((hdfsdm_channel->Init.Awd.Oversampling - 1) << DFSDM_CHAWSCDR_FOSR_OFFSET));
+ ((hdfsdm_channel->Init.Awd.Oversampling - 1) << DFSDM_CHAWSCDR_AWFOSR_Pos));
/* Set channel offset and right bit shift */
hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET | DFSDM_CHCFGR2_DTRBS);
- hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_OFFSET) |
- (hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_OFFSET));
+ hdfsdm_channel->Instance->CHCFGR2 |= (((uint32_t) hdfsdm_channel->Init.Offset << DFSDM_CHCFGR2_OFFSET_Pos) |
+ (hdfsdm_channel->Init.RightBitShift << DFSDM_CHCFGR2_DTRBS_Pos));
/* Enable DFSDM channel */
hdfsdm_channel->Instance->CHCFGR1 |= DFSDM_CHCFGR1_CHEN;
@@ -381,7 +361,7 @@
/**
* @brief De-initialize the DFSDM channel.
- * @param hdfsdm_channel : DFSDM channel handle.
+ * @param hdfsdm_channel DFSDM channel handle.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DFSDM_ChannelDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
@@ -427,7 +407,7 @@
/**
* @brief Initialize the DFSDM channel MSP.
- * @param hdfsdm_channel : DFSDM channel handle.
+ * @param hdfsdm_channel DFSDM channel handle.
* @retval None
*/
__weak void HAL_DFSDM_ChannelMspInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
@@ -442,7 +422,7 @@
/**
* @brief De-initialize the DFSDM channel MSP.
- * @param hdfsdm_channel : DFSDM channel handle.
+ * @param hdfsdm_channel DFSDM channel handle.
* @retval None
*/
__weak void HAL_DFSDM_ChannelMspDeInit(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
@@ -481,7 +461,7 @@
* @note If clock is not available on this channel during 5 seconds,
* clock absence detection will not be activated and function
* will return HAL_TIMEOUT error.
- * @param hdfsdm_channel : DFSDM channel handle.
+ * @param hdfsdm_channel DFSDM channel handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
@@ -508,9 +488,9 @@
tickstart = HAL_GetTick();
/* Clear clock absence flag */
- while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1) != 0)
+ while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1) != 0)
{
- DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
+ DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
/* Check the Timeout */
if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT)
@@ -533,8 +513,8 @@
/**
* @brief This function allows to poll for the clock absence detection.
- * @param hdfsdm_channel : DFSDM channel handle.
- * @param Timeout : Timeout value in milliseconds.
+ * @param hdfsdm_channel DFSDM channel handle.
+ * @param Timeout Timeout value in milliseconds.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_ChannelPollForCkab(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
@@ -561,7 +541,7 @@
tickstart = HAL_GetTick();
/* Wait clock absence detection */
- while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1) == 0)
+ while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1) == 0)
{
/* Check the Timeout */
if(Timeout != HAL_MAX_DELAY)
@@ -575,7 +555,7 @@
}
/* Clear clock absence detection flag */
- DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
+ DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
/* Return function status */
return HAL_OK;
@@ -584,7 +564,7 @@
/**
* @brief This function allows to stop clock absence detection in polling mode.
- * @param hdfsdm_channel : DFSDM channel handle.
+ * @param hdfsdm_channel DFSDM channel handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
@@ -608,7 +588,7 @@
/* Clear clock absence flag */
channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
- DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
+ DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
}
/* Return function status */
return status;
@@ -620,7 +600,7 @@
* @note If clock is not available on this channel during 5 seconds,
* clock absence detection will not be activated and function
* will return HAL_TIMEOUT error.
- * @param hdfsdm_channel : DFSDM channel handle.
+ * @param hdfsdm_channel DFSDM channel handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStart_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
@@ -647,9 +627,9 @@
tickstart = HAL_GetTick();
/* Clear clock absence flag */
- while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_OFFSET + channel)) & 1) != 0)
+ while((((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_CKABF) >> (DFSDM_FLTISR_CKABF_Pos + channel)) & 1) != 0)
{
- DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
+ DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
/* Check the Timeout */
if((HAL_GetTick()-tickstart) > DFSDM_CKAB_TIMEOUT)
@@ -675,7 +655,7 @@
/**
* @brief Clock absence detection callback.
- * @param hdfsdm_channel : DFSDM channel handle.
+ * @param hdfsdm_channel DFSDM channel handle.
* @retval None
*/
__weak void HAL_DFSDM_ChannelCkabCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
@@ -691,7 +671,7 @@
/**
* @brief This function allows to stop clock absence detection in interrupt mode.
* @note Interrupt will be disabled for all channels
- * @param hdfsdm_channel : DFSDM channel handle.
+ * @param hdfsdm_channel DFSDM channel handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_ChannelCkabStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
@@ -715,7 +695,7 @@
/* Clear clock absence flag */
channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
- DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
+ DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
/* Disable clock absence detection interrupt */
DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_CKABIE);
@@ -727,10 +707,10 @@
/**
* @brief This function allows to start short circuit detection in polling mode.
* @note Same mode has to be used for all channels
- * @param hdfsdm_channel : DFSDM channel handle.
- * @param Threshold : Short circuit detector threshold.
+ * @param hdfsdm_channel DFSDM channel handle.
+ * @param Threshold Short circuit detector threshold.
* This parameter must be a number between Min_Data = 0 and Max_Data = 255.
- * @param BreakSignal : Break signals assigned to short circuit event.
+ * @param BreakSignal Break signals assigned to short circuit event.
* This parameter can be a values combination of @ref DFSDM_BreakSignals.
* @retval HAL status
*/
@@ -755,7 +735,7 @@
{
/* Configure threshold and break signals */
hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT);
- hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_OFFSET) | \
+ hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_Pos) | \
Threshold);
/* Start short circuit detection */
@@ -767,8 +747,8 @@
/**
* @brief This function allows to poll for the short circuit detection.
- * @param hdfsdm_channel : DFSDM channel handle.
- * @param Timeout : Timeout value in milliseconds.
+ * @param hdfsdm_channel DFSDM channel handle.
+ * @param Timeout Timeout value in milliseconds.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_ChannelPollForScd(DFSDM_Channel_HandleTypeDef *hdfsdm_channel,
@@ -795,7 +775,7 @@
tickstart = HAL_GetTick();
/* Wait short circuit detection */
- while(((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_SCDF) >> (DFSDM_FLTISR_SCDF_OFFSET + channel)) == 0)
+ while(((DFSDM1_Filter0->FLTISR & DFSDM_FLTISR_SCDF) >> (DFSDM_FLTISR_SCDF_Pos + channel)) == 0)
{
/* Check the Timeout */
if(Timeout != HAL_MAX_DELAY)
@@ -809,7 +789,7 @@
}
/* Clear short circuit detection flag */
- DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel));
+ DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCSDF_Pos + channel));
/* Return function status */
return HAL_OK;
@@ -818,7 +798,7 @@
/**
* @brief This function allows to stop short circuit detection in polling mode.
- * @param hdfsdm_channel : DFSDM channel handle.
+ * @param hdfsdm_channel DFSDM channel handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
@@ -842,7 +822,7 @@
/* Clear short circuit detection flag */
channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
- DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel));
+ DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCSDF_Pos + channel));
}
/* Return function status */
return status;
@@ -851,10 +831,10 @@
/**
* @brief This function allows to start short circuit detection in interrupt mode.
* @note Same mode has to be used for all channels
- * @param hdfsdm_channel : DFSDM channel handle.
- * @param Threshold : Short circuit detector threshold.
+ * @param hdfsdm_channel DFSDM channel handle.
+ * @param Threshold Short circuit detector threshold.
* This parameter must be a number between Min_Data = 0 and Max_Data = 255.
- * @param BreakSignal : Break signals assigned to short circuit event.
+ * @param BreakSignal Break signals assigned to short circuit event.
* This parameter can be a values combination of @ref DFSDM_BreakSignals.
* @retval HAL status
*/
@@ -882,7 +862,7 @@
/* Configure threshold and break signals */
hdfsdm_channel->Instance->CHAWSCDR &= ~(DFSDM_CHAWSCDR_BKSCD | DFSDM_CHAWSCDR_SCDT);
- hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_OFFSET) | \
+ hdfsdm_channel->Instance->CHAWSCDR |= ((BreakSignal << DFSDM_CHAWSCDR_BKSCD_Pos) | \
Threshold);
/* Start short circuit detection */
@@ -894,7 +874,7 @@
/**
* @brief Short circuit detection callback.
- * @param hdfsdm_channel : DFSDM channel handle.
+ * @param hdfsdm_channel DFSDM channel handle.
* @retval None
*/
__weak void HAL_DFSDM_ChannelScdCallback(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
@@ -910,7 +890,7 @@
/**
* @brief This function allows to stop short circuit detection in interrupt mode.
* @note Interrupt will be disabled for all channels
- * @param hdfsdm_channel : DFSDM channel handle.
+ * @param hdfsdm_channel DFSDM channel handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_ChannelScdStop_IT(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
@@ -934,7 +914,7 @@
/* Clear short circuit detection flag */
channel = DFSDM_GetChannelFromInstance(hdfsdm_channel->Instance);
- DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel));
+ DFSDM1_Filter0->FLTICR = (1 << (DFSDM_FLTICR_CLRSCSDF_Pos + channel));
/* Disable short circuit detection interrupt */
DFSDM1_Filter0->FLTCR2 &= ~(DFSDM_FLTCR2_SCDIE);
@@ -945,7 +925,7 @@
/**
* @brief This function allows to get channel analog watchdog value.
- * @param hdfsdm_channel : DFSDM channel handle.
+ * @param hdfsdm_channel DFSDM channel handle.
* @retval Channel analog watchdog value.
*/
int16_t HAL_DFSDM_ChannelGetAwdValue(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
@@ -955,8 +935,8 @@
/**
* @brief This function allows to modify channel offset value.
- * @param hdfsdm_channel : DFSDM channel handle.
- * @param Offset : DFSDM channel offset.
+ * @param hdfsdm_channel DFSDM channel handle.
+ * @param Offset DFSDM channel offset.
* This parameter must be a number between Min_Data = -8388608 and Max_Data = 8388607.
* @retval HAL status.
*/
@@ -979,7 +959,7 @@
{
/* Modify channel offset */
hdfsdm_channel->Instance->CHCFGR2 &= ~(DFSDM_CHCFGR2_OFFSET);
- hdfsdm_channel->Instance->CHCFGR2 |= ((uint32_t) Offset << DFSDM_CHCFGR2_OFFSET_OFFSET);
+ hdfsdm_channel->Instance->CHCFGR2 |= ((uint32_t) Offset << DFSDM_CHCFGR2_OFFSET_Pos);
}
/* Return function status */
return status;
@@ -1004,7 +984,7 @@
/**
* @brief This function allows to get the current DFSDM channel handle state.
- * @param hdfsdm_channel : DFSDM channel handle.
+ * @param hdfsdm_channel DFSDM channel handle.
* @retval DFSDM channel state.
*/
HAL_DFSDM_Channel_StateTypeDef HAL_DFSDM_ChannelGetState(DFSDM_Channel_HandleTypeDef *hdfsdm_channel)
@@ -1034,7 +1014,7 @@
/**
* @brief Initialize the DFSDM filter according to the specified parameters
* in the DFSDM_FilterInitTypeDef structure and initialize the associated handle.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DFSDM_FilterInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@@ -1124,7 +1104,7 @@
/* Set filter parameters */
hdfsdm_filter->Instance->FLTFCR &= ~(DFSDM_FLTFCR_FORD | DFSDM_FLTFCR_FOSR | DFSDM_FLTFCR_IOSR);
hdfsdm_filter->Instance->FLTFCR |= (hdfsdm_filter->Init.FilterParam.SincOrder |
- ((hdfsdm_filter->Init.FilterParam.Oversampling - 1) << DFSDM_FLTFCR_FOSR_OFFSET) |
+ ((hdfsdm_filter->Init.FilterParam.Oversampling - 1) << DFSDM_FLTFCR_FOSR_Pos) |
(hdfsdm_filter->Init.FilterParam.IntOversampling - 1));
/* Store regular and injected triggers and injected scan mode*/
@@ -1144,7 +1124,7 @@
/**
* @brief De-initializes the DFSDM filter.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval HAL status.
*/
HAL_StatusTypeDef HAL_DFSDM_FilterDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@@ -1172,7 +1152,7 @@
/**
* @brief Initializes the DFSDM filter MSP.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval None
*/
__weak void HAL_DFSDM_FilterMspInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@@ -1187,7 +1167,7 @@
/**
* @brief De-initializes the DFSDM filter MSP.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval None
*/
__weak void HAL_DFSDM_FilterMspDeInit(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@@ -1221,10 +1201,10 @@
/**
* @brief This function allows to select channel and to enable/disable
* continuous mode for regular conversion.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @param Channel : Channel for regular conversion.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @param Channel Channel for regular conversion.
* This parameter can be a value of @ref DFSDM_Channel_Selection.
- * @param ContinuousMode : Enable/disable continuous mode for regular conversion.
+ * @param ContinuousMode Enable/disable continuous mode for regular conversion.
* This parameter can be a value of @ref DFSDM_ContinuousMode.
* @retval HAL status
*/
@@ -1268,8 +1248,8 @@
/**
* @brief This function allows to select channels for injected conversion.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @param Channel : Channels for injected conversion.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @param Channel Channels for injected conversion.
* This parameter can be a values combination of @ref DFSDM_Channel_Selection.
* @retval HAL status
*/
@@ -1340,7 +1320,7 @@
* @brief This function allows to start regular conversion in polling mode.
* @note This function should be called only when DFSDM filter instance is
* in idle state or if injected conversion is ongoing.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@@ -1368,8 +1348,8 @@
/**
* @brief This function allows to poll for the end of regular conversion.
* @note This function should be called only if regular conversion is ongoing.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @param Timeout : Timeout value in milliseconds.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @param Timeout Timeout value in milliseconds.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterPollForRegConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
@@ -1430,7 +1410,7 @@
/**
* @brief This function allows to stop regular conversion in polling mode.
* @note This function should be called only if regular conversion is ongoing.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@@ -1460,7 +1440,7 @@
* @brief This function allows to start regular conversion in interrupt mode.
* @note This function should be called only when DFSDM filter instance is
* in idle state or if injected conversion is ongoing.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@@ -1491,7 +1471,7 @@
/**
* @brief This function allows to stop regular conversion in interrupt mode.
* @note This function should be called only if regular conversion is ongoing.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@@ -1527,9 +1507,9 @@
* Please note that data on buffer will contain signed regular conversion
* value on 24 most significant bits and corresponding channel on 3 least
* significant bits.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @param pData : The destination buffer address.
- * @param Length : The length of data to be transferred from DFSDM filter to memory.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @param pData The destination buffer address.
+ * @param Length The length of data to be transferred from DFSDM filter to memory.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
@@ -1604,9 +1584,9 @@
* in idle state or if injected conversion is ongoing.
* Please note that data on buffer will contain signed 16 most significant
* bits of regular conversion.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @param pData : The destination buffer address.
- * @param Length : The length of data to be transferred from DFSDM filter to memory.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @param pData The destination buffer address.
+ * @param Length The length of data to be transferred from DFSDM filter to memory.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterRegularMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
@@ -1677,7 +1657,7 @@
/**
* @brief This function allows to stop regular conversion in DMA mode.
* @note This function should be called only if regular conversion is ongoing.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterRegularStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@@ -1715,8 +1695,8 @@
/**
* @brief This function allows to get regular conversion value.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @param Channel : Corresponding channel of regular conversion.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @param Channel Corresponding channel of regular conversion.
* @retval Regular conversion value
*/
int32_t HAL_DFSDM_FilterGetRegularValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
@@ -1734,7 +1714,7 @@
/* Extract channel and regular conversion value */
*Channel = (reg & DFSDM_FLTRDATAR_RDATACH);
- value = ((reg & DFSDM_FLTRDATAR_RDATA) >> DFSDM_FLTRDATAR_DATA_OFFSET);
+ value = ((int32_t)(reg & DFSDM_FLTRDATAR_RDATA) >> DFSDM_FLTRDATAR_RDATA_Pos);
/* return regular conversion value */
return value;
@@ -1744,7 +1724,7 @@
* @brief This function allows to start injected conversion in polling mode.
* @note This function should be called only when DFSDM filter instance is
* in idle state or if regular conversion is ongoing.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@@ -1772,8 +1752,8 @@
/**
* @brief This function allows to poll for the end of injected conversion.
* @note This function should be called only if injected conversion is ongoing.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @param Timeout : Timeout value in milliseconds.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @param Timeout Timeout value in milliseconds.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterPollForInjConversion(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
@@ -1844,7 +1824,7 @@
/**
* @brief This function allows to stop injected conversion in polling mode.
* @note This function should be called only if injected conversion is ongoing.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@@ -1874,7 +1854,7 @@
* @brief This function allows to start injected conversion in interrupt mode.
* @note This function should be called only when DFSDM filter instance is
* in idle state or if regular conversion is ongoing.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@@ -1905,7 +1885,7 @@
/**
* @brief This function allows to stop injected conversion in interrupt mode.
* @note This function should be called only if injected conversion is ongoing.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@@ -1941,9 +1921,9 @@
* Please note that data on buffer will contain signed injected conversion
* value on 24 most significant bits and corresponding channel on 3 least
* significant bits.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @param pData : The destination buffer address.
- * @param Length : The length of data to be transferred from DFSDM filter to memory.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @param pData The destination buffer address.
+ * @param Length The length of data to be transferred from DFSDM filter to memory.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
@@ -2016,9 +1996,9 @@
* in idle state or if regular conversion is ongoing.
* Please note that data on buffer will contain signed 16 most significant
* bits of injected conversion.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @param pData : The destination buffer address.
- * @param Length : The length of data to be transferred from DFSDM filter to memory.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @param pData The destination buffer address.
+ * @param Length The length of data to be transferred from DFSDM filter to memory.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedMsbStart_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
@@ -2087,7 +2067,7 @@
/**
* @brief This function allows to stop injected conversion in DMA mode.
* @note This function should be called only if injected conversion is ongoing.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterInjectedStop_DMA(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@@ -2125,8 +2105,8 @@
/**
* @brief This function allows to get injected conversion value.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @param Channel : Corresponding channel of injected conversion.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @param Channel Corresponding channel of injected conversion.
* @retval Injected conversion value
*/
int32_t HAL_DFSDM_FilterGetInjectedValue(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
@@ -2144,7 +2124,7 @@
/* Extract channel and injected conversion value */
*Channel = (reg & DFSDM_FLTJDATAR_JDATACH);
- value = ((reg & DFSDM_FLTJDATAR_JDATA) >> DFSDM_FLTJDATAR_DATA_OFFSET);
+ value = ((int32_t)(reg & DFSDM_FLTJDATAR_JDATA) >> DFSDM_FLTJDATAR_JDATA_Pos);
/* return regular conversion value */
return value;
@@ -2152,8 +2132,8 @@
/**
* @brief This function allows to start filter analog watchdog in interrupt mode.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @param awdParam : DFSDM filter analog watchdog parameters.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @param awdParam DFSDM filter analog watchdog parameters.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterAwdStart_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
@@ -2185,15 +2165,15 @@
/* Set thresholds and break signals */
hdfsdm_filter->Instance->FLTAWHTR &= ~(DFSDM_FLTAWHTR_AWHT | DFSDM_FLTAWHTR_BKAWH);
- hdfsdm_filter->Instance->FLTAWHTR |= (((uint32_t) awdParam->HighThreshold << DFSDM_FLTAWHTR_THRESHOLD_OFFSET) | \
+ hdfsdm_filter->Instance->FLTAWHTR |= (((uint32_t) awdParam->HighThreshold << DFSDM_FLTAWHTR_AWHT_Pos) | \
awdParam->HighBreakSignal);
hdfsdm_filter->Instance->FLTAWLTR &= ~(DFSDM_FLTAWLTR_AWLT | DFSDM_FLTAWLTR_BKAWL);
- hdfsdm_filter->Instance->FLTAWLTR |= (((uint32_t) awdParam->LowThreshold << DFSDM_FLTAWLTR_THRESHOLD_OFFSET) | \
+ hdfsdm_filter->Instance->FLTAWLTR |= (((uint32_t) awdParam->LowThreshold << DFSDM_FLTAWLTR_AWLT_Pos) | \
awdParam->LowBreakSignal);
/* Set channels and interrupt for analog watchdog */
hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_AWDCH);
- hdfsdm_filter->Instance->FLTCR2 |= (((awdParam->Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_AWDCH_OFFSET) | \
+ hdfsdm_filter->Instance->FLTCR2 |= (((awdParam->Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_AWDCH_Pos) | \
DFSDM_FLTCR2_AWDIE);
}
/* Return function status */
@@ -2202,7 +2182,7 @@
/**
* @brief This function allows to stop filter analog watchdog in interrupt mode.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterAwdStop_IT(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@@ -2240,8 +2220,8 @@
/**
* @brief This function allows to start extreme detector feature.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @param Channel : Channels where extreme detector is enabled.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @param Channel Channels where extreme detector is enabled.
* This parameter can be a values combination of @ref DFSDM_Channel_Selection.
* @retval HAL status
*/
@@ -2265,7 +2245,7 @@
{
/* Set channels for extreme detector */
hdfsdm_filter->Instance->FLTCR2 &= ~(DFSDM_FLTCR2_EXCH);
- hdfsdm_filter->Instance->FLTCR2 |= ((Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_EXCH_OFFSET);
+ hdfsdm_filter->Instance->FLTCR2 |= ((Channel & DFSDM_LSB_MASK) << DFSDM_FLTCR2_EXCH_Pos);
}
/* Return function status */
return status;
@@ -2273,7 +2253,7 @@
/**
* @brief This function allows to stop extreme detector feature.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DFSDM_FilterExdStop(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@@ -2309,8 +2289,8 @@
/**
* @brief This function allows to get extreme detector maximum value.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @param Channel : Corresponding channel.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @param Channel Corresponding channel.
* @retval Extreme detector maximum value
* This value is between Min_Data = -8388608 and Max_Data = 8388607.
*/
@@ -2329,7 +2309,7 @@
/* Extract channel and extreme detector maximum value */
*Channel = (reg & DFSDM_FLTEXMAX_EXMAXCH);
- value = ((reg & DFSDM_FLTEXMAX_EXMAX) >> DFSDM_FLTEXMAX_DATA_OFFSET);
+ value = ((int32_t)(reg & DFSDM_FLTEXMAX_EXMAX) >> DFSDM_FLTEXMAX_EXMAX_Pos);
/* return extreme detector maximum value */
return value;
@@ -2337,8 +2317,8 @@
/**
* @brief This function allows to get extreme detector minimum value.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @param Channel : Corresponding channel.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @param Channel Corresponding channel.
* @retval Extreme detector minimum value
* This value is between Min_Data = -8388608 and Max_Data = 8388607.
*/
@@ -2357,7 +2337,7 @@
/* Extract channel and extreme detector minimum value */
*Channel = (reg & DFSDM_FLTEXMIN_EXMINCH);
- value = ((reg & DFSDM_FLTEXMIN_EXMIN) >> DFSDM_FLTEXMIN_DATA_OFFSET);
+ value = ((int32_t)(reg & DFSDM_FLTEXMIN_EXMIN) >> DFSDM_FLTEXMIN_EXMIN_Pos);
/* return extreme detector minimum value */
return value;
@@ -2365,7 +2345,7 @@
/**
* @brief This function allows to get conversion time value.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval Conversion time value
* @note To get time in second, this value has to be divided by DFSDM clock frequency.
*/
@@ -2381,7 +2361,7 @@
reg = hdfsdm_filter->Instance->FLTCNVTIMR;
/* Extract conversion time value */
- value = ((reg & DFSDM_FLTCNVTIMR_CNVCNT) >> DFSDM_FLTCNVTIMR_DATA_OFFSET);
+ value = ((reg & DFSDM_FLTCNVTIMR_CNVCNT) >> DFSDM_FLTCNVTIMR_CNVCNT_Pos);
/* return extreme detector minimum value */
return value;
@@ -2389,7 +2369,7 @@
/**
* @brief This function handles the DFSDM interrupts.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval None
*/
void HAL_DFSDM_IRQHandler(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@@ -2478,7 +2458,7 @@
threshold = ((reg & DFSDM_FLTAWSR_AWLTF) != 0) ? DFSDM_AWD_LOW_THRESHOLD : DFSDM_AWD_HIGH_THRESHOLD;
if(threshold == DFSDM_AWD_HIGH_THRESHOLD)
{
- reg = reg >> DFSDM_FLTAWSR_HIGH_OFFSET;
+ reg = reg >> DFSDM_FLTAWSR_AWHTF_Pos;
}
while((reg & 1) == 0)
{
@@ -2487,7 +2467,7 @@
}
/* Clear analog watchdog flag */
hdfsdm_filter->Instance->FLTAWCFR = (threshold == DFSDM_AWD_HIGH_THRESHOLD) ? \
- (1 << (DFSDM_FLTAWSR_HIGH_OFFSET + channel)) : \
+ (1 << (DFSDM_FLTAWSR_AWHTF_Pos + channel)) : \
(1 << channel);
/* Call analog watchdog callback */
@@ -2501,7 +2481,7 @@
uint32_t reg = 0;
uint32_t channel = 0;
- reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) >> DFSDM_FLTISR_CKABF_OFFSET);
+ reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_CKABF) >> DFSDM_FLTISR_CKABF_Pos);
while(channel < DFSDM1_CHANNEL_NUMBER)
{
@@ -2512,7 +2492,7 @@
if((a_dfsdm1ChannelHandle[channel]->Instance->CHCFGR1 & DFSDM_CHCFGR1_CKABEN) != 0)
{
/* Clear clock absence flag */
- hdfsdm_filter->Instance->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_OFFSET + channel));
+ hdfsdm_filter->Instance->FLTICR = (1 << (DFSDM_FLTICR_CLRCKABF_Pos + channel));
/* Call clock absence callback */
HAL_DFSDM_ChannelCkabCallback(a_dfsdm1ChannelHandle[channel]);
@@ -2531,7 +2511,7 @@
uint32_t channel = 0;
/* Get channel */
- reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) >> DFSDM_FLTISR_SCDF_OFFSET);
+ reg = ((hdfsdm_filter->Instance->FLTISR & DFSDM_FLTISR_SCDF) >> DFSDM_FLTISR_SCDF_Pos);
while((reg & 1) == 0)
{
channel++;
@@ -2539,7 +2519,7 @@
}
/* Clear short circuit detection flag */
- hdfsdm_filter->Instance->FLTICR = (1 << (DFSDM_FLTICR_CLRSCDF_OFFSET + channel));
+ hdfsdm_filter->Instance->FLTICR = (1 << (DFSDM_FLTICR_CLRSCSDF_Pos + channel));
/* Call short circuit detection callback */
HAL_DFSDM_ChannelScdCallback(a_dfsdm1ChannelHandle[channel]);
@@ -2550,7 +2530,7 @@
* @brief Regular conversion complete callback.
* @note In interrupt mode, user has to read conversion value in this function
* using HAL_DFSDM_FilterGetRegularValue.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval None
*/
__weak void HAL_DFSDM_FilterRegConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@@ -2565,7 +2545,7 @@
/**
* @brief Half regular conversion complete callback.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval None
*/
__weak void HAL_DFSDM_FilterRegConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@@ -2582,7 +2562,7 @@
* @brief Injected conversion complete callback.
* @note In interrupt mode, user has to read conversion value in this function
* using HAL_DFSDM_FilterGetInjectedValue.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval None
*/
__weak void HAL_DFSDM_FilterInjConvCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@@ -2597,7 +2577,7 @@
/**
* @brief Half injected conversion complete callback.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval None
*/
__weak void HAL_DFSDM_FilterInjConvHalfCpltCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@@ -2612,9 +2592,9 @@
/**
* @brief Filter analog watchdog callback.
- * @param hdfsdm_filter : DFSDM filter handle.
- * @param Channel : Corresponding channel.
- * @param Threshold : Low or high threshold has been reached.
+ * @param hdfsdm_filter DFSDM filter handle.
+ * @param Channel Corresponding channel.
+ * @param Threshold Low or high threshold has been reached.
* @retval None
*/
__weak void HAL_DFSDM_FilterAwdCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter,
@@ -2632,7 +2612,7 @@
/**
* @brief Error callback.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval None
*/
__weak void HAL_DFSDM_FilterErrorCallback(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@@ -2665,7 +2645,7 @@
/**
* @brief This function allows to get the current DFSDM filter handle state.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval DFSDM filter state.
*/
HAL_DFSDM_Filter_StateTypeDef HAL_DFSDM_FilterGetState(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@@ -2676,7 +2656,7 @@
/**
* @brief This function allows to get the current DFSDM filter error.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval DFSDM filter error code.
*/
uint32_t HAL_DFSDM_FilterGetError(DFSDM_Filter_HandleTypeDef *hdfsdm_filter)
@@ -2700,7 +2680,7 @@
/**
* @brief DMA half transfer complete callback for regular conversion.
- * @param hdma : DMA handle.
+ * @param hdma DMA handle.
* @retval None
*/
static void DFSDM_DMARegularHalfConvCplt(DMA_HandleTypeDef *hdma)
@@ -2714,7 +2694,7 @@
/**
* @brief DMA transfer complete callback for regular conversion.
- * @param hdma : DMA handle.
+ * @param hdma DMA handle.
* @retval None
*/
static void DFSDM_DMARegularConvCplt(DMA_HandleTypeDef *hdma)
@@ -2728,7 +2708,7 @@
/**
* @brief DMA half transfer complete callback for injected conversion.
- * @param hdma : DMA handle.
+ * @param hdma DMA handle.
* @retval None
*/
static void DFSDM_DMAInjectedHalfConvCplt(DMA_HandleTypeDef *hdma)
@@ -2742,7 +2722,7 @@
/**
* @brief DMA transfer complete callback for injected conversion.
- * @param hdma : DMA handle.
+ * @param hdma DMA handle.
* @retval None
*/
static void DFSDM_DMAInjectedConvCplt(DMA_HandleTypeDef *hdma)
@@ -2756,7 +2736,7 @@
/**
* @brief DMA error callback.
- * @param hdma : DMA handle.
+ * @param hdma DMA handle.
* @retval None
*/
static void DFSDM_DMAError(DMA_HandleTypeDef *hdma)
@@ -2773,7 +2753,7 @@
/**
* @brief This function allows to get the number of injected channels.
- * @param Channels : bitfield of injected channels.
+ * @param Channels bitfield of injected channels.
* @retval Number of injected channels.
*/
static uint32_t DFSDM_GetInjChannelsNbr(uint32_t Channels)
@@ -2796,7 +2776,7 @@
/**
* @brief This function allows to get the channel number from channel instance.
- * @param Instance : DFSDM channel instance.
+ * @param Instance DFSDM channel instance.
* @retval Channel number.
*/
static uint32_t DFSDM_GetChannelFromInstance(DFSDM_Channel_TypeDef* Instance)
@@ -2842,7 +2822,7 @@
/**
* @brief This function allows to really start regular conversion.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval None
*/
static void DFSDM_RegConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
@@ -2883,7 +2863,7 @@
/**
* @brief This function allows to really stop regular conversion.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval None
*/
static void DFSDM_RegConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
@@ -2919,7 +2899,7 @@
/**
* @brief This function allows to really start injected conversion.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval None
*/
static void DFSDM_InjConvStart(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
@@ -2963,7 +2943,7 @@
/**
* @brief This function allows to really stop injected conversion.
- * @param hdfsdm_filter : DFSDM filter handle.
+ * @param hdfsdm_filter DFSDM filter handle.
* @retval None
*/
static void DFSDM_InjConvStop(DFSDM_Filter_HandleTypeDef* hdfsdm_filter)
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dfsdm.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dfsdm.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_dfsdm.h * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief Header file of DFSDM HAL module. ****************************************************************************** * @attention @@ -462,13 +460,13 @@ */ /** @brief Reset DFSDM channel handle state. - * @param __HANDLE__: DFSDM channel handle. + * @param __HANDLE__ DFSDM channel handle. * @retval None */ #define __HAL_DFSDM_CHANNEL_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_CHANNEL_STATE_RESET) /** @brief Reset DFSDM filter handle state. - * @param __HANDLE__: DFSDM filter handle. + * @param __HANDLE__ DFSDM filter handle. * @retval None */ #define __HAL_DFSDM_FILTER_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DFSDM_FILTER_STATE_RESET)
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_dma.c
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief DMA HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -43,7 +41,8 @@
===================================
[..]
(+) Configure the DMA interrupt priority using HAL_NVIC_SetPriority()
- (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
+ (+) Enable the DMA IRQ handler using HAL_NVIC_EnableIRQ()
+ (+) Select Callbacks functions using HAL_DMA_RegisterCallback()
(+) Use HAL_DMA_Start_IT() to start DMA transfer after the configuration of
Source address and destination address and the Length of data to be transferred. In this
case the DMA interrupt is configured
@@ -182,7 +181,7 @@
/**
* @brief Initialize the DMA according to the specified
* parameters in the DMA_InitTypeDef and create the associated handle.
- * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma Pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval HAL status
*/
@@ -321,7 +320,7 @@
/**
* @brief DeInitializes the DMA peripheral
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval HAL status
*/
@@ -371,11 +370,19 @@
/* Clear all interrupt flags at correct offset within the register */
regs->IFCR = 0x3FU << hdma->StreamIndex;
+
+ /* Clean all callbacks */
+ hdma->XferCpltCallback = NULL;
+ hdma->XferHalfCpltCallback = NULL;
+ hdma->XferM1CpltCallback = NULL;
+ hdma->XferM1HalfCpltCallback = NULL;
+ hdma->XferErrorCallback = NULL;
+ hdma->XferAbortCallback = NULL;
- /* Initialize the error code */
+ /* Reset the error code */
hdma->ErrorCode = HAL_DMA_ERROR_NONE;
- /* Initialize the DMA state */
+ /* Reset the DMA state */
hdma->State = HAL_DMA_STATE_RESET;
/* Release Lock */
@@ -408,11 +415,11 @@
/**
* @brief Starts the DMA Transfer.
- * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
- * @param SrcAddress: The source memory Buffer address
- * @param DstAddress: The destination memory Buffer address
- * @param DataLength: The length of data to be transferred from source to destination
+ * @param SrcAddress The source memory Buffer address
+ * @param DstAddress The destination memory Buffer address
+ * @param DataLength The length of data to be transferred from source to destination
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Start(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
@@ -452,11 +459,11 @@
/**
* @brief Start the DMA Transfer with interrupt enabled.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
- * @param SrcAddress: The source memory Buffer address
- * @param DstAddress: The destination memory Buffer address
- * @param DataLength: The length of data to be transferred from source to destination
+ * @param SrcAddress The source memory Buffer address
+ * @param DstAddress The destination memory Buffer address
+ * @param DataLength The length of data to be transferred from source to destination
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_Start_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
@@ -512,7 +519,7 @@
/**
* @brief Aborts the DMA Transfer.
- * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
*
* @note After disabling a DMA Stream, a check for wait until the DMA Stream is
@@ -585,7 +592,7 @@
/**
* @brief Aborts the DMA Transfer in Interrupt mode.
- * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval HAL status
*/
@@ -610,13 +617,13 @@
/**
* @brief Polling for transfer complete.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
- * @param CompleteLevel: Specifies the DMA level complete.
+ * @param CompleteLevel Specifies the DMA level complete.
* @note The polling mode is kept in this version for legacy. it is recommanded to use the IT model instead.
* This model could be used for debug purpose.
* @note The HAL_DMA_PollForTransfer API cannot be used in circular and double buffering mode (automatic circular mode).
- * @param Timeout: Timeout duration.
+ * @param Timeout Timeout duration.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout)
@@ -742,7 +749,7 @@
}
else
{
- /* Clear the half transfer and transfer complete flags */
+ /* Clear the half transfer flag */
regs->IFCR = (DMA_FLAG_HTIF0_4) << hdma->StreamIndex;
}
@@ -751,7 +758,7 @@
/**
* @brief Handles DMA interrupt request.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval None
*/
@@ -968,11 +975,11 @@
/**
* @brief Register callbacks
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
- * @param CallbackID: User Callback identifer
+ * @param CallbackID User Callback identifer
* a DMA_HandleTypeDef structure as parameter.
- * @param pCallback: pointer to private callbacsk function which has pointer to
+ * @param pCallback pointer to private callbacsk function which has pointer to
* a DMA_HandleTypeDef structure as parameter.
* @retval HAL status
*/
@@ -1030,9 +1037,9 @@
/**
* @brief UnRegister callbacks
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
- * @param CallbackID: User Callback identifer
+ * @param CallbackID User Callback identifer
* a HAL_DMA_CallbackIDTypeDef ENUM as parameter.
* @retval HAL status
*/
@@ -1117,7 +1124,7 @@
/**
* @brief Returns the DMA state.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval HAL state
*/
@@ -1128,7 +1135,7 @@
/**
* @brief Return the DMA error code
- * @param hdma : pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval DMA Error Code
*/
@@ -1151,11 +1158,11 @@
/**
* @brief Sets the DMA Transfer parameter.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
- * @param SrcAddress: The source memory Buffer address
- * @param DstAddress: The destination memory Buffer address
- * @param DataLength: The length of data to be transferred from source to destination
+ * @param SrcAddress The source memory Buffer address
+ * @param DstAddress The destination memory Buffer address
+ * @param DataLength The length of data to be transferred from source to destination
* @retval HAL status
*/
static void DMA_SetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
@@ -1166,7 +1173,7 @@
/* Configure DMA Stream data length */
hdma->Instance->NDTR = DataLength;
- /* Peripheral to Memory */
+ /* Memory to Peripheral */
if((hdma->Init.Direction) == DMA_MEMORY_TO_PERIPH)
{
/* Configure DMA Stream destination address */
@@ -1175,7 +1182,7 @@
/* Configure DMA Stream source address */
hdma->Instance->M0AR = SrcAddress;
}
- /* Memory to Peripheral */
+ /* Peripheral to Memory */
else
{
/* Configure DMA Stream source address */
@@ -1188,7 +1195,7 @@
/**
* @brief Returns the DMA Stream base address depending on stream number
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval Stream base address
*/
@@ -1216,7 +1223,7 @@
/**
* @brief Check compatibility between FIFO threshold level and size of the memory burst
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA Stream.
* @retval HAL status
*/
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_dma.h
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief Header file of DMA HAL module.
******************************************************************************
* @attention
@@ -201,14 +199,14 @@
* @brief DMA Error Code
* @{
*/
-#define HAL_DMA_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
-#define HAL_DMA_ERROR_TE ((uint32_t)0x00000001U) /*!< Transfer error */
-#define HAL_DMA_ERROR_FE ((uint32_t)0x00000002U) /*!< FIFO error */
-#define HAL_DMA_ERROR_DME ((uint32_t)0x00000004U) /*!< Direct Mode error */
-#define HAL_DMA_ERROR_TIMEOUT ((uint32_t)0x00000020U) /*!< Timeout error */
-#define HAL_DMA_ERROR_PARAM ((uint32_t)0x00000040U) /*!< Parameter error */
-#define HAL_DMA_ERROR_NO_XFER ((uint32_t)0x00000080U) /*!< Abort requested with no Xfer ongoing */
-#define HAL_DMA_ERROR_NOT_SUPPORTED ((uint32_t)0x00000100U) /*!< Not supported mode */
+#define HAL_DMA_ERROR_NONE 0x00000000U /*!< No error */
+#define HAL_DMA_ERROR_TE 0x00000001U /*!< Transfer error */
+#define HAL_DMA_ERROR_FE 0x00000002U /*!< FIFO error */
+#define HAL_DMA_ERROR_DME 0x00000004U /*!< Direct Mode error */
+#define HAL_DMA_ERROR_TIMEOUT 0x00000020U /*!< Timeout error */
+#define HAL_DMA_ERROR_PARAM 0x00000040U /*!< Parameter error */
+#define HAL_DMA_ERROR_NO_XFER 0x00000080U /*!< Abort requested with no Xfer ongoing */
+#define HAL_DMA_ERROR_NOT_SUPPORTED 0x00000100U /*!< Not supported mode */
/**
* @}
*/
@@ -217,9 +215,9 @@
* @brief DMA data transfer direction
* @{
*/
-#define DMA_PERIPH_TO_MEMORY ((uint32_t)0x00000000U) /*!< Peripheral to memory direction */
-#define DMA_MEMORY_TO_PERIPH ((uint32_t)DMA_SxCR_DIR_0) /*!< Memory to peripheral direction */
-#define DMA_MEMORY_TO_MEMORY ((uint32_t)DMA_SxCR_DIR_1) /*!< Memory to memory direction */
+#define DMA_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
+#define DMA_MEMORY_TO_PERIPH DMA_SxCR_DIR_0 /*!< Memory to peripheral direction */
+#define DMA_MEMORY_TO_MEMORY DMA_SxCR_DIR_1 /*!< Memory to memory direction */
/**
* @}
*/
@@ -228,8 +226,8 @@
* @brief DMA peripheral incremented mode
* @{
*/
-#define DMA_PINC_ENABLE ((uint32_t)DMA_SxCR_PINC) /*!< Peripheral increment mode enable */
-#define DMA_PINC_DISABLE ((uint32_t)0x00000000U) /*!< Peripheral increment mode disable */
+#define DMA_PINC_ENABLE DMA_SxCR_PINC /*!< Peripheral increment mode enable */
+#define DMA_PINC_DISABLE 0x00000000U /*!< Peripheral increment mode disable */
/**
* @}
*/
@@ -238,8 +236,8 @@
* @brief DMA memory incremented mode
* @{
*/
-#define DMA_MINC_ENABLE ((uint32_t)DMA_SxCR_MINC) /*!< Memory increment mode enable */
-#define DMA_MINC_DISABLE ((uint32_t)0x00000000U) /*!< Memory increment mode disable */
+#define DMA_MINC_ENABLE DMA_SxCR_MINC /*!< Memory increment mode enable */
+#define DMA_MINC_DISABLE 0x00000000U /*!< Memory increment mode disable */
/**
* @}
*/
@@ -248,9 +246,9 @@
* @brief DMA peripheral data size
* @{
*/
-#define DMA_PDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Peripheral data alignment: Byte */
-#define DMA_PDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_PSIZE_0) /*!< Peripheral data alignment: HalfWord */
-#define DMA_PDATAALIGN_WORD ((uint32_t)DMA_SxCR_PSIZE_1) /*!< Peripheral data alignment: Word */
+#define DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment: Byte */
+#define DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /*!< Peripheral data alignment: HalfWord */
+#define DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1 /*!< Peripheral data alignment: Word */
/**
* @}
*/
@@ -259,9 +257,9 @@
* @brief DMA memory data size
* @{
*/
-#define DMA_MDATAALIGN_BYTE ((uint32_t)0x00000000U) /*!< Memory data alignment: Byte */
-#define DMA_MDATAALIGN_HALFWORD ((uint32_t)DMA_SxCR_MSIZE_0) /*!< Memory data alignment: HalfWord */
-#define DMA_MDATAALIGN_WORD ((uint32_t)DMA_SxCR_MSIZE_1) /*!< Memory data alignment: Word */
+#define DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment: Byte */
+#define DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0 /*!< Memory data alignment: HalfWord */
+#define DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1 /*!< Memory data alignment: Word */
/**
* @}
*/
@@ -270,9 +268,9 @@
* @brief DMA mode
* @{
*/
-#define DMA_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */
-#define DMA_CIRCULAR ((uint32_t)DMA_SxCR_CIRC) /*!< Circular mode */
-#define DMA_PFCTRL ((uint32_t)DMA_SxCR_PFCTRL) /*!< Peripheral flow control mode */
+#define DMA_NORMAL 0x00000000U /*!< Normal mode */
+#define DMA_CIRCULAR DMA_SxCR_CIRC /*!< Circular mode */
+#define DMA_PFCTRL DMA_SxCR_PFCTRL /*!< Peripheral flow control mode */
/**
* @}
*/
@@ -281,10 +279,10 @@
* @brief DMA priority levels
* @{
*/
-#define DMA_PRIORITY_LOW ((uint32_t)0x00000000U) /*!< Priority level: Low */
-#define DMA_PRIORITY_MEDIUM ((uint32_t)DMA_SxCR_PL_0) /*!< Priority level: Medium */
-#define DMA_PRIORITY_HIGH ((uint32_t)DMA_SxCR_PL_1) /*!< Priority level: High */
-#define DMA_PRIORITY_VERY_HIGH ((uint32_t)DMA_SxCR_PL) /*!< Priority level: Very High */
+#define DMA_PRIORITY_LOW 0x00000000U /*!< Priority level: Low */
+#define DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0 /*!< Priority level: Medium */
+#define DMA_PRIORITY_HIGH DMA_SxCR_PL_1 /*!< Priority level: High */
+#define DMA_PRIORITY_VERY_HIGH DMA_SxCR_PL /*!< Priority level: Very High */
/**
* @}
*/
@@ -293,8 +291,8 @@
* @brief DMA FIFO direct mode
* @{
*/
-#define DMA_FIFOMODE_DISABLE ((uint32_t)0x00000000U) /*!< FIFO mode disable */
-#define DMA_FIFOMODE_ENABLE ((uint32_t)DMA_SxFCR_DMDIS) /*!< FIFO mode enable */
+#define DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable */
+#define DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /*!< FIFO mode enable */
/**
* @}
*/
@@ -303,10 +301,10 @@
* @brief DMA FIFO level
* @{
*/
-#define DMA_FIFO_THRESHOLD_1QUARTERFULL ((uint32_t)0x00000000U) /*!< FIFO threshold 1 quart full configuration */
-#define DMA_FIFO_THRESHOLD_HALFFULL ((uint32_t)DMA_SxFCR_FTH_0) /*!< FIFO threshold half full configuration */
-#define DMA_FIFO_THRESHOLD_3QUARTERSFULL ((uint32_t)DMA_SxFCR_FTH_1) /*!< FIFO threshold 3 quarts full configuration */
-#define DMA_FIFO_THRESHOLD_FULL ((uint32_t)DMA_SxFCR_FTH) /*!< FIFO threshold full configuration */
+#define DMA_FIFO_THRESHOLD_1QUARTERFULL 0x00000000U /*!< FIFO threshold 1 quart full configuration */
+#define DMA_FIFO_THRESHOLD_HALFFULL DMA_SxFCR_FTH_0 /*!< FIFO threshold half full configuration */
+#define DMA_FIFO_THRESHOLD_3QUARTERSFULL DMA_SxFCR_FTH_1 /*!< FIFO threshold 3 quarts full configuration */
+#define DMA_FIFO_THRESHOLD_FULL DMA_SxFCR_FTH /*!< FIFO threshold full configuration */
/**
* @}
*/
@@ -315,10 +313,10 @@
* @brief DMA memory burst
* @{
*/
-#define DMA_MBURST_SINGLE ((uint32_t)0x00000000U)
-#define DMA_MBURST_INC4 ((uint32_t)DMA_SxCR_MBURST_0)
-#define DMA_MBURST_INC8 ((uint32_t)DMA_SxCR_MBURST_1)
-#define DMA_MBURST_INC16 ((uint32_t)DMA_SxCR_MBURST)
+#define DMA_MBURST_SINGLE 0x00000000U
+#define DMA_MBURST_INC4 DMA_SxCR_MBURST_0
+#define DMA_MBURST_INC8 DMA_SxCR_MBURST_1
+#define DMA_MBURST_INC16 DMA_SxCR_MBURST
/**
* @}
*/
@@ -327,10 +325,10 @@
* @brief DMA peripheral burst
* @{
*/
-#define DMA_PBURST_SINGLE ((uint32_t)0x00000000U)
-#define DMA_PBURST_INC4 ((uint32_t)DMA_SxCR_PBURST_0)
-#define DMA_PBURST_INC8 ((uint32_t)DMA_SxCR_PBURST_1)
-#define DMA_PBURST_INC16 ((uint32_t)DMA_SxCR_PBURST)
+#define DMA_PBURST_SINGLE 0x00000000U
+#define DMA_PBURST_INC4 DMA_SxCR_PBURST_0
+#define DMA_PBURST_INC8 DMA_SxCR_PBURST_1
+#define DMA_PBURST_INC16 DMA_SxCR_PBURST
/**
* @}
*/
@@ -339,11 +337,11 @@
* @brief DMA interrupts definition
* @{
*/
-#define DMA_IT_TC ((uint32_t)DMA_SxCR_TCIE)
-#define DMA_IT_HT ((uint32_t)DMA_SxCR_HTIE)
-#define DMA_IT_TE ((uint32_t)DMA_SxCR_TEIE)
-#define DMA_IT_DME ((uint32_t)DMA_SxCR_DMEIE)
-#define DMA_IT_FE ((uint32_t)0x00000080U)
+#define DMA_IT_TC DMA_SxCR_TCIE
+#define DMA_IT_HT DMA_SxCR_HTIE
+#define DMA_IT_TE DMA_SxCR_TEIE
+#define DMA_IT_DME DMA_SxCR_DMEIE
+#define DMA_IT_FE 0x00000080U
/**
* @}
*/
@@ -352,26 +350,26 @@
* @brief DMA flag definitions
* @{
*/
-#define DMA_FLAG_FEIF0_4 ((uint32_t)0x00800001U)
-#define DMA_FLAG_DMEIF0_4 ((uint32_t)0x00800004U)
-#define DMA_FLAG_TEIF0_4 ((uint32_t)0x00000008U)
-#define DMA_FLAG_HTIF0_4 ((uint32_t)0x00000010U)
-#define DMA_FLAG_TCIF0_4 ((uint32_t)0x00000020U)
-#define DMA_FLAG_FEIF1_5 ((uint32_t)0x00000040U)
-#define DMA_FLAG_DMEIF1_5 ((uint32_t)0x00000100U)
-#define DMA_FLAG_TEIF1_5 ((uint32_t)0x00000200U)
-#define DMA_FLAG_HTIF1_5 ((uint32_t)0x00000400U)
-#define DMA_FLAG_TCIF1_5 ((uint32_t)0x00000800U)
-#define DMA_FLAG_FEIF2_6 ((uint32_t)0x00010000U)
-#define DMA_FLAG_DMEIF2_6 ((uint32_t)0x00040000U)
-#define DMA_FLAG_TEIF2_6 ((uint32_t)0x00080000U)
-#define DMA_FLAG_HTIF2_6 ((uint32_t)0x00100000U)
-#define DMA_FLAG_TCIF2_6 ((uint32_t)0x00200000U)
-#define DMA_FLAG_FEIF3_7 ((uint32_t)0x00400000U)
-#define DMA_FLAG_DMEIF3_7 ((uint32_t)0x01000000U)
-#define DMA_FLAG_TEIF3_7 ((uint32_t)0x02000000U)
-#define DMA_FLAG_HTIF3_7 ((uint32_t)0x04000000U)
-#define DMA_FLAG_TCIF3_7 ((uint32_t)0x08000000U)
+#define DMA_FLAG_FEIF0_4 0x00000001U
+#define DMA_FLAG_DMEIF0_4 0x00000004U
+#define DMA_FLAG_TEIF0_4 0x00000008U
+#define DMA_FLAG_HTIF0_4 0x00000010U
+#define DMA_FLAG_TCIF0_4 0x00000020U
+#define DMA_FLAG_FEIF1_5 0x00000040U
+#define DMA_FLAG_DMEIF1_5 0x00000100U
+#define DMA_FLAG_TEIF1_5 0x00000200U
+#define DMA_FLAG_HTIF1_5 0x00000400U
+#define DMA_FLAG_TCIF1_5 0x00000800U
+#define DMA_FLAG_FEIF2_6 0x00010000U
+#define DMA_FLAG_DMEIF2_6 0x00040000U
+#define DMA_FLAG_TEIF2_6 0x00080000U
+#define DMA_FLAG_HTIF2_6 0x00100000U
+#define DMA_FLAG_TCIF2_6 0x00200000U
+#define DMA_FLAG_FEIF3_7 0x00400000U
+#define DMA_FLAG_DMEIF3_7 0x01000000U
+#define DMA_FLAG_TEIF3_7 0x02000000U
+#define DMA_FLAG_HTIF3_7 0x04000000U
+#define DMA_FLAG_TCIF3_7 0x08000000U
/**
* @}
*/
@@ -383,14 +381,14 @@
/* Exported macro ------------------------------------------------------------*/
/** @brief Reset DMA handle state
- * @param __HANDLE__: specifies the DMA handle.
+ * @param __HANDLE__ specifies the DMA handle.
* @retval None
*/
#define __HAL_DMA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA_STATE_RESET)
/**
* @brief Return the current DMA Stream FIFO filled level.
- * @param __HANDLE__: DMA handle
+ * @param __HANDLE__ DMA handle
* @retval The FIFO filling state.
* - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full
* and not empty.
@@ -404,14 +402,14 @@
/**
* @brief Enable the specified DMA Stream.
- * @param __HANDLE__: DMA handle
+ * @param __HANDLE__ DMA handle
* @retval None
*/
#define __HAL_DMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA_SxCR_EN)
/**
* @brief Disable the specified DMA Stream.
- * @param __HANDLE__: DMA handle
+ * @param __HANDLE__ DMA handle
* @retval None
*/
#define __HAL_DMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DMA_SxCR_EN)
@@ -420,7 +418,7 @@
/**
* @brief Return the current DMA Stream transfer complete flag.
- * @param __HANDLE__: DMA handle
+ * @param __HANDLE__ DMA handle
* @retval The specified transfer complete flag index.
*/
#define __HAL_DMA_GET_TC_FLAG_INDEX(__HANDLE__) \
@@ -440,7 +438,7 @@
/**
* @brief Return the current DMA Stream half transfer complete flag.
- * @param __HANDLE__: DMA handle
+ * @param __HANDLE__ DMA handle
* @retval The specified half transfer complete flag index.
*/
#define __HAL_DMA_GET_HT_FLAG_INDEX(__HANDLE__)\
@@ -460,7 +458,7 @@
/**
* @brief Return the current DMA Stream transfer error flag.
- * @param __HANDLE__: DMA handle
+ * @param __HANDLE__ DMA handle
* @retval The specified transfer error flag index.
*/
#define __HAL_DMA_GET_TE_FLAG_INDEX(__HANDLE__)\
@@ -480,7 +478,7 @@
/**
* @brief Return the current DMA Stream FIFO error flag.
- * @param __HANDLE__: DMA handle
+ * @param __HANDLE__ DMA handle
* @retval The specified FIFO error flag index.
*/
#define __HAL_DMA_GET_FE_FLAG_INDEX(__HANDLE__)\
@@ -500,7 +498,7 @@
/**
* @brief Return the current DMA Stream direct mode error flag.
- * @param __HANDLE__: DMA handle
+ * @param __HANDLE__ DMA handle
* @retval The specified direct mode error flag index.
*/
#define __HAL_DMA_GET_DME_FLAG_INDEX(__HANDLE__)\
@@ -520,8 +518,8 @@
/**
* @brief Get the DMA Stream pending flags.
- * @param __HANDLE__: DMA handle
- * @param __FLAG__: Get the specified flag.
+ * @param __HANDLE__ DMA handle
+ * @param __FLAG__ Get the specified flag.
* This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCIFx: Transfer complete flag.
* @arg DMA_FLAG_HTIFx: Half transfer complete flag.
@@ -538,8 +536,8 @@
/**
* @brief Clear the DMA Stream pending flags.
- * @param __HANDLE__: DMA handle
- * @param __FLAG__: specifies the flag to clear.
+ * @param __HANDLE__ DMA handle
+ * @param __FLAG__ specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg DMA_FLAG_TCIFx: Transfer complete flag.
* @arg DMA_FLAG_HTIFx: Half transfer complete flag.
@@ -556,8 +554,8 @@
/**
* @brief Enable the specified DMA Stream interrupts.
- * @param __HANDLE__: DMA handle
- * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
+ * @param __HANDLE__ DMA handle
+ * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
* This parameter can be one of the following values:
* @arg DMA_IT_TC: Transfer complete interrupt mask.
* @arg DMA_IT_HT: Half transfer complete interrupt mask.
@@ -571,8 +569,8 @@
/**
* @brief Disable the specified DMA Stream interrupts.
- * @param __HANDLE__: DMA handle
- * @param __INTERRUPT__: specifies the DMA interrupt sources to be enabled or disabled.
+ * @param __HANDLE__ DMA handle
+ * @param __INTERRUPT__ specifies the DMA interrupt sources to be enabled or disabled.
* This parameter can be one of the following values:
* @arg DMA_IT_TC: Transfer complete interrupt mask.
* @arg DMA_IT_HT: Half transfer complete interrupt mask.
@@ -586,8 +584,8 @@
/**
* @brief Check whether the specified DMA Stream interrupt is enabled or not.
- * @param __HANDLE__: DMA handle
- * @param __INTERRUPT__: specifies the DMA interrupt source to check.
+ * @param __HANDLE__ DMA handle
+ * @param __INTERRUPT__ specifies the DMA interrupt source to check.
* This parameter can be one of the following values:
* @arg DMA_IT_TC: Transfer complete interrupt mask.
* @arg DMA_IT_HT: Half transfer complete interrupt mask.
@@ -602,8 +600,8 @@
/**
* @brief Writes the number of data units to be transferred on the DMA Stream.
- * @param __HANDLE__: DMA handle
- * @param __COUNTER__: Number of data units to be transferred (from 0 to 65535)
+ * @param __HANDLE__ DMA handle
+ * @param __COUNTER__ Number of data units to be transferred (from 0 to 65535)
* Number of data items depends only on the Peripheral data format.
*
* @note If Peripheral data format is Bytes: number of data units is equal
@@ -621,7 +619,7 @@
/**
* @brief Returns the number of remaining data units in the current DMAy Streamx transfer.
- * @param __HANDLE__: DMA handle
+ * @param __HANDLE__ DMA handle
*
* @retval The number of remaining data units in the current DMA Stream transfer.
*/
@@ -658,7 +656,6 @@
HAL_StatusTypeDef HAL_DMA_Abort_IT(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_PollForTransfer(DMA_HandleTypeDef *hdma, HAL_DMA_LevelCompleteTypeDef CompleteLevel, uint32_t Timeout);
void HAL_DMA_IRQHandler(DMA_HandleTypeDef *hdma);
-HAL_StatusTypeDef HAL_DMA_CleanCallbacks(DMA_HandleTypeDef *hdma);
HAL_StatusTypeDef HAL_DMA_RegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID, void (* pCallback)(DMA_HandleTypeDef *_hdma));
HAL_StatusTypeDef HAL_DMA_UnRegisterCallback(DMA_HandleTypeDef *hdma, HAL_DMA_CallbackIDTypeDef CallbackID);
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma2d.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma2d.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_dma2d.c
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief DMA2D HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the DMA2D peripheral:
@@ -155,36 +153,6 @@
* @}
*/
-/** @defgroup DMA2D_Shifts DMA2D Shifts
- * @{
- */
-#define DMA2D_POSITION_FGPFCCR_CS (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CS) /*!< Required left shift to set foreground CLUT size */
-#define DMA2D_POSITION_BGPFCCR_CS (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_CS) /*!< Required left shift to set background CLUT size */
-
-#define DMA2D_POSITION_FGPFCCR_CCM (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CCM) /*!< Required left shift to set foreground CLUT color mode */
-#define DMA2D_POSITION_BGPFCCR_CCM (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_CCM) /*!< Required left shift to set background CLUT color mode */
-
-#define DMA2D_POSITION_OPFCCR_AI (uint32_t)POSITION_VAL(DMA2D_OPFCCR_AI) /*!< Required left shift to set output alpha inversion */
-#define DMA2D_POSITION_FGPFCCR_AI (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_AI) /*!< Required left shift to set foreground alpha inversion */
-#define DMA2D_POSITION_BGPFCCR_AI (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_AI) /*!< Required left shift to set background alpha inversion */
-
-#define DMA2D_POSITION_OPFCCR_RBS (uint32_t)POSITION_VAL(DMA2D_OPFCCR_RBS) /*!< Required left shift to set output Red/Blue swap */
-#define DMA2D_POSITION_FGPFCCR_RBS (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_RBS) /*!< Required left shift to set foreground Red/Blue swap */
-#define DMA2D_POSITION_BGPFCCR_RBS (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_RBS) /*!< Required left shift to set background Red/Blue swap */
-
-#define DMA2D_POSITION_AMTCR_DT (uint32_t)POSITION_VAL(DMA2D_AMTCR_DT) /*!< Required left shift to set deadtime value */
-
-#define DMA2D_POSITION_FGPFCCR_AM (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_AM) /*!< Required left shift to set foreground alpha mode */
-#define DMA2D_POSITION_BGPFCCR_AM (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_AM) /*!< Required left shift to set background alpha mode */
-
-#define DMA2D_POSITION_FGPFCCR_ALPHA (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_ALPHA) /*!< Required left shift to set foreground alpha value */
-#define DMA2D_POSITION_BGPFCCR_ALPHA (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_ALPHA) /*!< Required left shift to set background alpha value */
-
-#define DMA2D_POSITION_NLR_PL (uint32_t)POSITION_VAL(DMA2D_NLR_PL) /*!< Required left shift to set pixels per lines value */
-/**
- * @}
- */
-
/**
* @}
*/
@@ -225,7 +193,7 @@
/**
* @brief Initialize the DMA2D according to the specified
* parameters in the DMA2D_InitTypeDef and create the associated handle.
- * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @retval HAL status
*/
@@ -265,11 +233,11 @@
#if defined (DMA2D_OPFCCR_AI)
/* DMA2D OPFCCR AI fields setting (Output Alpha Inversion)*/
- MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_AI, (hdma2d->Init.AlphaInverted << DMA2D_POSITION_OPFCCR_AI));
+ MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_AI, (hdma2d->Init.AlphaInverted << DMA2D_OPFCCR_AI_Pos));
#endif /* DMA2D_OPFCCR_AI */
#if defined (DMA2D_OPFCCR_RBS)
- MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_RBS,(hdma2d->Init.RedBlueSwap << DMA2D_POSITION_OPFCCR_RBS));
+ MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_RBS,(hdma2d->Init.RedBlueSwap << DMA2D_OPFCCR_RBS_Pos));
#endif /* DMA2D_OPFCCR_RBS */
@@ -285,7 +253,7 @@
/**
* @brief Deinitializes the DMA2D peripheral registers to their default reset
* values.
- * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @retval None
*/
@@ -364,7 +332,7 @@
/**
* @brief Initializes the DMA2D MSP.
- * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @retval None
*/
@@ -380,7 +348,7 @@
/**
* @brief DeInitializes the DMA2D MSP.
- * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @retval None
*/
@@ -436,15 +404,15 @@
/**
* @brief Start the DMA2D Transfer.
- * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
- * @param pdata: Configure the source memory Buffer address if
+ * @param pdata Configure the source memory Buffer address if
* Memory-to-Memory or Memory-to-Memory with pixel format
* conversion mode is selected, or configure
* the color value if Register-to-Memory mode is selected.
- * @param DstAddress: The destination memory Buffer address.
- * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line).
- * @param Height: The height of data to be transferred from source to destination (expressed in number of lines).
+ * @param DstAddress The destination memory Buffer address.
+ * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line).
+ * @param Height The height of data to be transferred from source to destination (expressed in number of lines).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
@@ -470,15 +438,15 @@
/**
* @brief Start the DMA2D Transfer with interrupt enabled.
- * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
- * @param pdata: Configure the source memory Buffer address if
+ * @param pdata Configure the source memory Buffer address if
* the Memory-to-Memory or Memory-to-Memory with pixel format
* conversion mode is selected, or configure
* the color value if Register-to-Memory mode is selected.
- * @param DstAddress: The destination memory Buffer address.
- * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line).
- * @param Height: The height of data to be transferred from source to destination (expressed in number of lines).
+ * @param DstAddress The destination memory Buffer address.
+ * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line).
+ * @param Height The height of data to be transferred from source to destination (expressed in number of lines).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
@@ -507,13 +475,13 @@
/**
* @brief Start the multi-source DMA2D Transfer.
- * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
- * @param SrcAddress1: The source memory Buffer address for the foreground layer.
- * @param SrcAddress2: The source memory Buffer address for the background layer.
- * @param DstAddress: The destination memory Buffer address.
- * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line).
- * @param Height: The height of data to be transferred from source to destination (expressed in number of lines).
+ * @param SrcAddress1 The source memory Buffer address for the foreground layer.
+ * @param SrcAddress2 The source memory Buffer address for the background layer.
+ * @param DstAddress The destination memory Buffer address.
+ * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line).
+ * @param Height The height of data to be transferred from source to destination (expressed in number of lines).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
@@ -542,13 +510,13 @@
/**
* @brief Start the multi-source DMA2D Transfer with interrupt enabled.
- * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
- * @param SrcAddress1: The source memory Buffer address for the foreground layer.
- * @param SrcAddress2: The source memory Buffer address for the background layer.
- * @param DstAddress: The destination memory Buffer address.
- * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line).
- * @param Height: The height of data to be transferred from source to destination (expressed in number of lines).
+ * @param SrcAddress1 The source memory Buffer address for the foreground layer.
+ * @param SrcAddress2 The source memory Buffer address for the background layer.
+ * @param DstAddress The destination memory Buffer address.
+ * @param Width The width of data to be transferred from source to destination (expressed in number of pixels per line).
+ * @param Height The height of data to be transferred from source to destination (expressed in number of lines).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
@@ -580,7 +548,7 @@
/**
* @brief Abort the DMA2D Transfer.
- * @param hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @retval HAL status
*/
@@ -629,7 +597,7 @@
/**
* @brief Suspend the DMA2D Transfer.
- * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @retval HAL status
*/
@@ -679,7 +647,7 @@
/**
* @brief Resume the DMA2D Transfer.
- * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @retval HAL status
*/
@@ -704,9 +672,9 @@
/**
* @brief Enable the DMA2D CLUT Transfer.
- * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
- * @param LayerIdx: DMA2D Layer index.
+ * @param LayerIdx DMA2D Layer index.
* This parameter can be one of the following values:
* 0(background) / 1(foreground)
* @retval HAL status
@@ -739,14 +707,14 @@
/**
* @brief Start DMA2D CLUT Loading.
- * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
- * @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
+ * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
* the configuration information for the color look up table.
- * @param LayerIdx: DMA2D Layer index.
+ * @param LayerIdx DMA2D Layer index.
* This parameter can be one of the following values:
* 0(background) / 1(foreground)
- * @note Invoking this API is similar to calling HAL_DMA2D_ConfigCLUT() then HAL_DMA2D_EnableCLUT().
+ * @note Invoking this API is similar to calling HAL_DMA2D_ConfigCLUT() then HAL_DMA2D_EnableCLUT().
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
@@ -770,7 +738,7 @@
/* Write background CLUT size and CLUT color mode */
MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
- ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));
+ ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
/* Enable the CLUT loading for the background */
SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
@@ -783,7 +751,7 @@
/* Write foreground CLUT size and CLUT color mode */
MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
- ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));
+ ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
/* Enable the CLUT loading for the foreground */
SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
@@ -794,11 +762,11 @@
/**
* @brief Start DMA2D CLUT Loading with interrupt enabled.
- * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
- * @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
+ * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
* the configuration information for the color look up table.
- * @param LayerIdx: DMA2D Layer index.
+ * @param LayerIdx DMA2D Layer index.
* This parameter can be one of the following values:
* 0(background) / 1(foreground)
* @retval HAL status
@@ -824,7 +792,7 @@
/* Write background CLUT size and CLUT color mode */
MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
- ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));
+ ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
/* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
__HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
@@ -840,7 +808,7 @@
/* Write foreground CLUT size and CLUT color mode */
MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
- ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));
+ ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
/* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
__HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
@@ -854,9 +822,9 @@
/**
* @brief Abort the DMA2D CLUT loading.
- * @param hdma2d : Pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
- * @param LayerIdx: DMA2D Layer index.
+ * @param LayerIdx DMA2D Layer index.
* This parameter can be one of the following values:
* 0(background) / 1(foreground)
* @retval HAL status
@@ -911,9 +879,9 @@
/**
* @brief Suspend the DMA2D CLUT loading.
- * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
- * @param LayerIdx: DMA2D Layer index.
+ * @param LayerIdx DMA2D Layer index.
* This parameter can be one of the following values:
* 0(background) / 1(foreground)
* @retval HAL status
@@ -968,9 +936,9 @@
/**
* @brief Resume the DMA2D CLUT loading.
- * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
- * @param LayerIdx: DMA2D Layer index.
+ * @param LayerIdx DMA2D Layer index.
* This parameter can be one of the following values:
* 0(background) / 1(foreground)
* @retval HAL status
@@ -1009,9 +977,9 @@
/**
* @brief Polling for transfer complete or CLUT loading.
- * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
- * @param Timeout: Timeout duration
+ * @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
@@ -1136,7 +1104,7 @@
}
/**
* @brief Handle DMA2D interrupt request.
- * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @retval HAL status
*/
@@ -1297,7 +1265,7 @@
/**
* @brief Transfer watermark callback.
- * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @retval None
*/
@@ -1313,7 +1281,7 @@
/**
* @brief CLUT Transfer Complete callback.
- * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @retval None
*/
@@ -1353,9 +1321,9 @@
/**
* @brief Configure the DMA2D Layer according to the specified
* parameters in the DMA2D_InitTypeDef and create the associated handle.
- * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
- * @param LayerIdx: DMA2D Layer index.
+ * @param LayerIdx DMA2D Layer index.
* This parameter can be one of the following values:
* 0(background) / 1(foreground)
* @retval HAL status
@@ -1387,16 +1355,16 @@
/* DMA2D BGPFCR register configuration -----------------------------------*/
/* Prepare the value to be written to the BGPFCCR register */
- regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_POSITION_BGPFCCR_AM);
+ regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_BGPFCCR_AM_Pos);
regMask = DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA;
#if defined (DMA2D_FGPFCCR_AI) && defined (DMA2D_BGPFCCR_AI)
- regValue |= (pLayerCfg->AlphaInverted << DMA2D_POSITION_BGPFCCR_AI);
+ regValue |= (pLayerCfg->AlphaInverted << DMA2D_BGPFCCR_AI_Pos);
regMask |= DMA2D_BGPFCCR_AI;
#endif /* (DMA2D_FGPFCCR_AI) && (DMA2D_BGPFCCR_AI) */
#if defined (DMA2D_FGPFCCR_RBS) && defined (DMA2D_BGPFCCR_RBS)
- regValue |= (pLayerCfg->RedBlueSwap << DMA2D_POSITION_BGPFCCR_RBS);
+ regValue |= (pLayerCfg->RedBlueSwap << DMA2D_BGPFCCR_RBS_Pos);
regMask |= DMA2D_BGPFCCR_RBS;
#endif
@@ -1406,7 +1374,7 @@
}
else
{
- regValue |= (pLayerCfg->InputAlpha << DMA2D_POSITION_BGPFCCR_ALPHA);
+ regValue |= (pLayerCfg->InputAlpha << DMA2D_BGPFCCR_ALPHA_Pos);
}
/* Configure the background DMA2D layer */
@@ -1450,11 +1418,11 @@
/**
* @brief Configure the DMA2D CLUT Transfer.
- * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
- * @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
+ * @param CLUTCfg Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
* the configuration information for the color look up table.
- * @param LayerIdx: DMA2D Layer index.
+ * @param LayerIdx DMA2D Layer index.
* This parameter can be one of the following values:
* 0(background) / 1(foreground)
* @retval HAL status
@@ -1480,7 +1448,7 @@
/* Write background CLUT size and CLUT color mode */
MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
- ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));
+ ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_BGPFCCR_CCM_Pos)));
}
/* Configure the CLUT of the foreground DMA2D layer */
else
@@ -1490,7 +1458,7 @@
/* Write foreground CLUT size and CLUT color mode */
MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
- ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));
+ ((CLUTCfg.Size << DMA2D_BGPFCCR_CS_Pos) | (CLUTCfg.CLUTColorMode << DMA2D_FGPFCCR_CCM_Pos)));
}
/* Set the DMA2D state to Ready*/
@@ -1505,9 +1473,9 @@
/**
* @brief Configure the line watermark.
- * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
- * @param Line: Line Watermark configuration (maximum 16-bit long value expected).
+ * @param Line Line Watermark configuration (maximum 16-bit long value expected).
* @note HAL_DMA2D_ProgramLineEvent() API enables the transfer watermark interrupt.
* @note The transfer watermark interrupt is disabled once it has occurred.
* @retval HAL status
@@ -1548,7 +1516,7 @@
/**
* @brief Enable DMA2D dead time feature.
- * @param hdma2d: DMA2D handle.
+ * @param hdma2d DMA2D handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d)
@@ -1571,7 +1539,7 @@
/**
* @brief Disable DMA2D dead time feature.
- * @param hdma2d: DMA2D handle.
+ * @param hdma2d DMA2D handle.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d)
@@ -1596,8 +1564,8 @@
* @brief Configure dead time.
* @note The dead time value represents the guaranteed minimum number of cycles between
* two consecutive transactions on the AHB bus.
- * @param hdma2d: DMA2D handle.
- * @param DeadTime: dead time value.
+ * @param hdma2d DMA2D handle.
+ * @param DeadTime dead time value.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime)
@@ -1608,7 +1576,7 @@
hdma2d->State = HAL_DMA2D_STATE_BUSY;
/* Set DMA2D_AMTCR DT field */
- MODIFY_REG(hdma2d->Instance->AMTCR, DMA2D_AMTCR_DT, (((uint32_t) DeadTime) << DMA2D_POSITION_AMTCR_DT));
+ MODIFY_REG(hdma2d->Instance->AMTCR, DMA2D_AMTCR_DT, (((uint32_t) DeadTime) << DMA2D_AMTCR_DT_Pos));
hdma2d->State = HAL_DMA2D_STATE_READY;
@@ -1641,7 +1609,7 @@
/**
* @brief Return the DMA2D state
- * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the DMA2D.
* @retval HAL state
*/
@@ -1652,7 +1620,7 @@
/**
* @brief Return the DMA2D error code
- * @param hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for DMA2D.
* @retval DMA2D Error Code
*/
@@ -1676,12 +1644,12 @@
/**
* @brief Set the DMA2D transfer parameters.
- * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
+ * @param hdma2d Pointer to a DMA2D_HandleTypeDef structure that contains
* the configuration information for the specified DMA2D.
- * @param pdata: The source memory Buffer address
- * @param DstAddress: The destination memory Buffer address
- * @param Width: The width of data to be transferred from source to destination.
- * @param Height: The height of data to be transferred from source to destination.
+ * @param pdata The source memory Buffer address
+ * @param DstAddress The destination memory Buffer address
+ * @param Width The width of data to be transferred from source to destination.
+ * @param Height The height of data to be transferred from source to destination.
* @retval HAL status
*/
static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
@@ -1693,7 +1661,7 @@
uint32_t tmp4 = 0;
/* Configure DMA2D data size */
- MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL|DMA2D_NLR_PL), (Height| (Width << DMA2D_POSITION_NLR_PL)));
+ MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL|DMA2D_NLR_PL), (Height| (Width << DMA2D_NLR_PL_Pos)));
/* Configure DMA2D destination address */
WRITE_REG(hdma2d->Instance->OMAR, DstAddress);
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma2d.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma2d.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_dma2d.h * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief Header file of DMA2D HAL module. ****************************************************************************** * @attention @@ -343,14 +341,14 @@ */ /** @brief Reset DMA2D handle state - * @param __HANDLE__: specifies the DMA2D handle. + * @param __HANDLE__ specifies the DMA2D handle. * @retval None */ #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET) /** * @brief Enable the DMA2D. - * @param __HANDLE__: DMA2D handle + * @param __HANDLE__ DMA2D handle * @retval None. */ #define __HAL_DMA2D_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DMA2D_CR_START) @@ -359,8 +357,8 @@ /* Interrupt & Flag management */ /** * @brief Get the DMA2D pending flags. - * @param __HANDLE__: DMA2D handle - * @param __FLAG__: flag to check. + * @param __HANDLE__ DMA2D handle + * @param __FLAG__ flag to check. * This parameter can be any combination of the following values: * @arg DMA2D_FLAG_CE: Configuration error flag * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag @@ -374,8 +372,8 @@ /** * @brief Clear the DMA2D pending flags. - * @param __HANDLE__: DMA2D handle - * @param __FLAG__: specifies the flag to clear. + * @param __HANDLE__ DMA2D handle + * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: * @arg DMA2D_FLAG_CE: Configuration error flag * @arg DMA2D_FLAG_CTC: CLUT transfer complete flag @@ -389,8 +387,8 @@ /** * @brief Enable the specified DMA2D interrupts. - * @param __HANDLE__: DMA2D handle - * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be enabled. + * @param __HANDLE__ DMA2D handle + * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be enabled. * This parameter can be any combination of the following values: * @arg DMA2D_IT_CE: Configuration error interrupt mask * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask @@ -404,8 +402,8 @@ /** * @brief Disable the specified DMA2D interrupts. - * @param __HANDLE__: DMA2D handle - * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be disabled. + * @param __HANDLE__ DMA2D handle + * @param __INTERRUPT__ specifies the DMA2D interrupt sources to be disabled. * This parameter can be any combination of the following values: * @arg DMA2D_IT_CE: Configuration error interrupt mask * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask @@ -419,8 +417,8 @@ /** * @brief Check whether the specified DMA2D interrupt source is enabled or not. - * @param __HANDLE__: DMA2D handle - * @param __INTERRUPT__: specifies the DMA2D interrupt source to check. + * @param __HANDLE__ DMA2D handle + * @param __INTERRUPT__ specifies the DMA2D interrupt source to check. * This parameter can be one of the following values: * @arg DMA2D_IT_CE: Configuration error interrupt mask * @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma_ex.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma_ex.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_dma_ex.c * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief DMA Extension HAL module driver * This file provides firmware functions to manage the following * functionalities of the DMA Extension peripheral: @@ -110,12 +108,12 @@ /** * @brief Starts the multi_buffer DMA Transfer. - * @param hdma : pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer - * @param DataLength: The length of data to be transferred from source to destination + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param SecondMemAddress The second memory Buffer address in case of multi buffer Transfer + * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength) @@ -164,12 +162,12 @@ /** * @brief Starts the multi_buffer DMA Transfer with interrupt enabled. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param SecondMemAddress: The second memory Buffer address in case of multi buffer Transfer - * @param DataLength: The length of data to be transferred from source to destination + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param SecondMemAddress The second memory Buffer address in case of multi buffer Transfer + * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ HAL_StatusTypeDef HAL_DMAEx_MultiBufferStart_IT(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t SecondMemAddress, uint32_t DataLength) @@ -238,10 +236,10 @@ /** * @brief Change the memory0 or memory1 address on the fly. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. - * @param Address: The new address - * @param memory: the memory to be changed, This parameter can be one of + * @param Address The new address + * @param memory the memory to be changed, This parameter can be one of * the following values: * MEMORY0 / * MEMORY1 @@ -280,11 +278,11 @@ /** * @brief Set the DMA Transfer parameter. - * @param hdma: pointer to a DMA_HandleTypeDef structure that contains + * @param hdma pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA Stream. - * @param SrcAddress: The source memory Buffer address - * @param DstAddress: The destination memory Buffer address - * @param DataLength: The length of data to be transferred from source to destination + * @param SrcAddress The source memory Buffer address + * @param DstAddress The destination memory Buffer address + * @param DataLength The length of data to be transferred from source to destination * @retval HAL status */ static void DMA_MultiBufferSetConfig(DMA_HandleTypeDef *hdma, uint32_t SrcAddress, uint32_t DstAddress, uint32_t DataLength)
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma_ex.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dma_ex.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_dma_ex.h
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief Header file of DMA HAL extension module.
******************************************************************************
* @attention
@@ -85,25 +83,25 @@
* @brief DMAEx channel selection
* @{
*/
-#define DMA_CHANNEL_0 ((uint32_t)0x00000000U) /*!< DMA Channel 0 */
-#define DMA_CHANNEL_1 ((uint32_t)0x02000000U) /*!< DMA Channel 1 */
-#define DMA_CHANNEL_2 ((uint32_t)0x04000000U) /*!< DMA Channel 2 */
-#define DMA_CHANNEL_3 ((uint32_t)0x06000000U) /*!< DMA Channel 3 */
-#define DMA_CHANNEL_4 ((uint32_t)0x08000000U) /*!< DMA Channel 4 */
-#define DMA_CHANNEL_5 ((uint32_t)0x0A000000U) /*!< DMA Channel 5 */
-#define DMA_CHANNEL_6 ((uint32_t)0x0C000000U) /*!< DMA Channel 6 */
-#define DMA_CHANNEL_7 ((uint32_t)0x0E000000U) /*!< DMA Channel 7 */
+#define DMA_CHANNEL_0 0x00000000U /*!< DMA Channel 0 */
+#define DMA_CHANNEL_1 0x02000000U /*!< DMA Channel 1 */
+#define DMA_CHANNEL_2 0x04000000U /*!< DMA Channel 2 */
+#define DMA_CHANNEL_3 0x06000000U /*!< DMA Channel 3 */
+#define DMA_CHANNEL_4 0x08000000U /*!< DMA Channel 4 */
+#define DMA_CHANNEL_5 0x0A000000U /*!< DMA Channel 5 */
+#define DMA_CHANNEL_6 0x0C000000U /*!< DMA Channel 6 */
+#define DMA_CHANNEL_7 0x0E000000U /*!< DMA Channel 7 */
#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) ||\
defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) ||\
defined (STM32F779xx)
-#define DMA_CHANNEL_8 ((uint32_t)0x10000000U) /*!< DMA Channel 8 */
-#define DMA_CHANNEL_9 ((uint32_t)0x12000000U) /*!< DMA Channel 9 */
-#define DMA_CHANNEL_10 ((uint32_t)0x14000000U) /*!< DMA Channel 10*/
-#define DMA_CHANNEL_11 ((uint32_t)0x16000000U) /*!< DMA Channel 11*/
-#define DMA_CHANNEL_12 ((uint32_t)0x18000000U) /*!< DMA Channel 12*/
-#define DMA_CHANNEL_13 ((uint32_t)0x1A000000U) /*!< DMA Channel 13*/
-#define DMA_CHANNEL_14 ((uint32_t)0x1C000000U) /*!< DMA Channel 14*/
-#define DMA_CHANNEL_15 ((uint32_t)0x1E000000U) /*!< DMA Channel 15*/
+#define DMA_CHANNEL_8 0x10000000U /*!< DMA Channel 8 */
+#define DMA_CHANNEL_9 0x12000000U /*!< DMA Channel 9 */
+#define DMA_CHANNEL_10 0x14000000U /*!< DMA Channel 10*/
+#define DMA_CHANNEL_11 0x16000000U /*!< DMA Channel 11*/
+#define DMA_CHANNEL_12 0x18000000U /*!< DMA Channel 12*/
+#define DMA_CHANNEL_13 0x1A000000U /*!< DMA Channel 13*/
+#define DMA_CHANNEL_14 0x1C000000U /*!< DMA Channel 14*/
+#define DMA_CHANNEL_15 0x1E000000U /*!< DMA Channel 15*/
#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx || STM32F765xx || STM32F767xx ||
STM32F769xx || STM32F777xx || STM32F779xx */
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dsi.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dsi.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_dsi.c * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief DSI HAL module driver. * This file provides firmware functions to manage the following * functionalities of the DSI peripheral: @@ -88,16 +86,16 @@ /* Private functions ---------------------------------------------------------*/ /** * @brief Generic DSI packet header configuration - * @param DSIx: Pointer to DSI register base - * @param ChannelID: Virtual channel ID of the header packet - * @param DataType: Packet data type of the header packet + * @param DSIx Pointer to DSI register base + * @param ChannelID Virtual channel ID of the header packet + * @param DataType Packet data type of the header packet * This parameter can be any value of : * @ref DSI_SHORT_WRITE_PKT_Data_Type * or @ref DSI_LONG_WRITE_PKT_Data_Type * or @ref DSI_SHORT_READ_PKT_Data_Type * or DSI_MAX_RETURN_PKT_SIZE - * @param Data0: Word count LSB - * @param Data1: Word count MSB + * @param Data0 Word count LSB + * @param Data1 Word count MSB * @retval None */ static void DSI_ConfigPacketHeader(DSI_TypeDef *DSIx, @@ -133,9 +131,9 @@ /** * @brief Initializes the DSI according to the specified * parameters in the DSI_InitTypeDef and create the associated handle. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param PLLInit: pointer to a DSI_PLLInitTypeDef structure that contains + * @param PLLInit pointer to a DSI_PLLInitTypeDef structure that contains * the PLL Clock structure definition for the DSI. * @retval HAL status */ @@ -253,7 +251,7 @@ /** * @brief De-initializes the DSI peripheral registers to their default reset * values. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL status */ @@ -300,7 +298,7 @@ /** * @brief Return the DSI error code - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval DSI Error Code */ @@ -312,9 +310,9 @@ /** * @brief Enable the error monitor flags - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param ActiveErrors: indicates which error interrupts will be enabled. + * @param ActiveErrors indicates which error interrupts will be enabled. * This parameter can be any combination of @ref DSI_Error_Data_Type. * @retval HAL status */ @@ -397,7 +395,7 @@ /** * @brief Initializes the DSI MSP. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval None */ @@ -413,7 +411,7 @@ /** * @brief De-initializes the DSI MSP. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval None */ @@ -446,7 +444,7 @@ */ /** * @brief Handles DSI interrupt request. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL status */ @@ -549,7 +547,7 @@ /** * @brief Tearing Effect DSI callback. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval None */ @@ -565,7 +563,7 @@ /** * @brief End of Refresh DSI callback. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval None */ @@ -581,7 +579,7 @@ /** * @brief Operation Error DSI callback. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval None */ @@ -613,9 +611,9 @@ /** * @brief Configure the Generic interface read-back Virtual Channel ID. - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param VirtualChannelID: Virtual channel ID + * @param VirtualChannelID Virtual channel ID * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_SetGenericVCID(DSI_HandleTypeDef *hdsi, uint32_t VirtualChannelID) @@ -635,9 +633,9 @@ /** * @brief Select video mode and configure the corresponding parameters - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param VidCfg: pointer to a DSI_VidCfgTypeDef structure that contains + * @param VidCfg pointer to a DSI_VidCfgTypeDef structure that contains * the DSI video mode configuration parameters * @retval HAL status */ @@ -785,9 +783,9 @@ /** * @brief Select adapted command mode and configure the corresponding parameters - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param CmdCfg: pointer to a DSI_CmdCfgTypeDef structure that contains + * @param CmdCfg pointer to a DSI_CmdCfgTypeDef structure that contains * the DSI command mode configuration parameters * @retval HAL status */ @@ -855,9 +853,9 @@ /** * @brief Configure command transmission mode: High-speed or Low-power * and enable/disable acknowledge request after packet transmission - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param LPCmd: pointer to a DSI_LPCmdTypeDef structure that contains + * @param LPCmd pointer to a DSI_LPCmdTypeDef structure that contains * the DSI command transmission mode configuration parameters * @retval HAL status */ @@ -918,9 +916,9 @@ /** * @brief Configure the flow control parameters - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param FlowControl: flow control feature(s) to be enabled. + * @param FlowControl flow control feature(s) to be enabled. * This parameter can be any combination of @ref DSI_FlowControl. * @retval HAL status */ @@ -944,9 +942,9 @@ /** * @brief Configure the DSI PHY timer parameters - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param PhyTimers: DSI_PHY_TimerTypeDef structure that contains + * @param PhyTimers DSI_PHY_TimerTypeDef structure that contains * the DSI PHY timing parameters * @retval HAL status */ @@ -988,9 +986,9 @@ /** * @brief Configure the DSI HOST timeout parameters - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param HostTimeouts: DSI_HOST_TimeoutTypeDef structure that contains + * @param HostTimeouts DSI_HOST_TimeoutTypeDef structure that contains * the DSI host timeout parameters * @retval HAL status */ @@ -1043,7 +1041,7 @@ /** * @brief Start the DSI module - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL status */ @@ -1066,7 +1064,7 @@ /** * @brief Stop the DSI module - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL status */ @@ -1089,7 +1087,7 @@ /** * @brief Refresh the display in command mode - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL status */ @@ -1109,9 +1107,9 @@ /** * @brief Controls the display color mode in Video mode - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param ColorMode: Color mode (full or 8-colors). + * @param ColorMode Color mode (full or 8-colors). * This parameter can be any value of @ref DSI_Color_Mode * @retval HAL status */ @@ -1135,9 +1133,9 @@ /** * @brief Control the display shutdown in Video mode - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param Shutdown: Shut-down (Display-ON or Display-OFF). + * @param Shutdown Shut-down (Display-ON or Display-OFF). * This parameter can be any value of @ref DSI_ShutDown * @retval HAL status */ @@ -1161,15 +1159,15 @@ /** * @brief DCS or Generic short write command - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param ChannelID: Virtual channel ID. - * @param Mode: DSI short packet data type. + * @param ChannelID Virtual channel ID. + * @param Mode DSI short packet data type. * This parameter can be any value of @ref DSI_SHORT_WRITE_PKT_Data_Type. - * @param Param1: DSC command or first generic parameter. + * @param Param1 DSC command or first generic parameter. * This parameter can be any value of @ref DSI_DCS_Command or a * generic command code. - * @param Param2: DSC parameter or second generic parameter. + * @param Param2 DSC parameter or second generic parameter. * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_ShortWrite(DSI_HandleTypeDef *hdsi, @@ -1217,16 +1215,16 @@ /** * @brief DCS or Generic long write command - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param ChannelID: Virtual channel ID. - * @param Mode: DSI long packet data type. + * @param ChannelID Virtual channel ID. + * @param Mode DSI long packet data type. * This parameter can be any value of @ref DSI_LONG_WRITE_PKT_Data_Type. - * @param NbParams: Number of parameters. - * @param Param1: DSC command or first generic parameter. + * @param NbParams Number of parameters. + * @param Param1 DSC command or first generic parameter. * This parameter can be any value of @ref DSI_DCS_Command or a * generic command code - * @param ParametersTable: Pointer to parameter values table. + * @param ParametersTable Pointer to parameter values table. * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_LongWrite(DSI_HandleTypeDef *hdsi, @@ -1297,15 +1295,15 @@ /** * @brief Read command (DCS or generic) - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param ChannelNbr: Virtual channel ID - * @param Array: pointer to a buffer to store the payload of a read back operation. - * @param Size: Data size to be read (in byte). - * @param Mode: DSI read packet data type. + * @param ChannelNbr Virtual channel ID + * @param Array pointer to a buffer to store the payload of a read back operation. + * @param Size Data size to be read (in byte). + * @param Mode DSI read packet data type. * This parameter can be any value of @ref DSI_SHORT_READ_PKT_Data_Type. - * @param DCSCmd: DCS get/read command. - * @param ParametersTable: Pointer to parameter values table. + * @param DCSCmd DCS get/read command. + * @param ParametersTable Pointer to parameter values table. * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_Read(DSI_HandleTypeDef *hdsi, @@ -1418,7 +1416,7 @@ /** * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL running * (only data lanes are in ULPM) - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL status */ @@ -1474,7 +1472,7 @@ /** * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL running * (only data lanes are in ULPM) - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL status */ @@ -1533,7 +1531,7 @@ /** * @brief Enter the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off * (both data and clock lanes are in ULPM) - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL status */ @@ -1598,7 +1596,7 @@ /** * @brief Exit the ULPM (Ultra Low Power Mode) with the D-PHY PLL turned off * (both data and clock lanes are in ULPM) - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL status */ @@ -1681,13 +1679,13 @@ /** * @brief Start test pattern generation - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param Mode: Pattern generator mode + * @param Mode Pattern generator mode * This parameter can be one of the following values: * 0 : Color bars (horizontal or vertical) * 1 : BER pattern (vertical only) - * @param Orientation: Pattern generator orientation + * @param Orientation Pattern generator orientation * This parameter can be one of the following values: * 0 : Vertical color bars * 1 : Horizontal color bars @@ -1713,7 +1711,7 @@ /** * @brief Stop test pattern generation - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL status */ @@ -1733,13 +1731,13 @@ /** * @brief Set Slew-Rate And Delay Tuning - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param CommDelay: Communication delay to be adjusted. + * @param CommDelay Communication delay to be adjusted. * This parameter can be any value of @ref DSI_Communication_Delay - * @param Lane: select between clock or data lanes. + * @param Lane select between clock or data lanes. * This parameter can be any value of @ref DSI_Lane_Group - * @param Value: Custom value of the slew-rate or delay + * @param Value Custom value of the slew-rate or delay * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_SetSlewRateAndDelayTuning(DSI_HandleTypeDef *hdsi, uint32_t CommDelay, uint32_t Lane, uint32_t Value) @@ -1807,9 +1805,9 @@ /** * @brief Low-Power Reception Filter Tuning - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param Frequency: cutoff frequency of low-pass filter at the input of LPRX + * @param Frequency cutoff frequency of low-pass filter at the input of LPRX * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_SetLowPowerRXFilter(DSI_HandleTypeDef *hdsi, uint32_t Frequency) @@ -1830,9 +1828,9 @@ /** * @brief Activate an additional current path on all lanes to meet the SDDTx parameter * defined in the MIPI D-PHY specification - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param State: ENABLE or DISABLE + * @param State ENABLE or DISABLE * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_SetSDD(DSI_HandleTypeDef *hdsi, FunctionalState State) @@ -1855,13 +1853,13 @@ /** * @brief Custom lane pins configuration - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param CustomLane: Function to be applyed on selected lane. + * @param CustomLane Function to be applyed on selected lane. * This parameter can be any value of @ref DSI_CustomLane - * @param Lane: select between clock or data lane 0 or data lane 1. + * @param Lane select between clock or data lane 0 or data lane 1. * This parameter can be any value of @ref DSI_Lane_Select - * @param State: ENABLE or DISABLE + * @param State ENABLE or DISABLE * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_SetLanePinsConfiguration(DSI_HandleTypeDef *hdsi, uint32_t CustomLane, uint32_t Lane, FunctionalState State) @@ -1928,12 +1926,12 @@ /** * @brief Set custom timing for the PHY - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param Timing: PHY timing to be adjusted. + * @param Timing PHY timing to be adjusted. * This parameter can be any value of @ref DSI_PHY_Timing - * @param State: ENABLE or DISABLE - * @param Value: Custom value of the timing + * @param State ENABLE or DISABLE + * @param Value Custom value of the timing * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_SetPHYTimings(DSI_HandleTypeDef *hdsi, uint32_t Timing, FunctionalState State, uint32_t Value) @@ -2076,11 +2074,11 @@ /** * @brief Force the Clock/Data Lane in TX Stop Mode - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param Lane: select between clock or data lanes. + * @param Lane select between clock or data lanes. * This parameter can be any value of @ref DSI_Lane_Group - * @param State: ENABLE or DISABLE + * @param State ENABLE or DISABLE * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_ForceTXStopMode(DSI_HandleTypeDef *hdsi, uint32_t Lane, FunctionalState State) @@ -2113,9 +2111,9 @@ /** * @brief Forces LP Receiver in Low-Power Mode - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param State: ENABLE or DISABLE + * @param State ENABLE or DISABLE * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_ForceRXLowPower(DSI_HandleTypeDef *hdsi, FunctionalState State) @@ -2138,9 +2136,9 @@ /** * @brief Force Data Lanes in RX Mode after a BTA - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param State: ENABLE or DISABLE + * @param State ENABLE or DISABLE * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_ForceDataLanesInRX(DSI_HandleTypeDef *hdsi, FunctionalState State) @@ -2163,9 +2161,9 @@ /** * @brief Enable a pull-down on the lanes to prevent from floating states when unused - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param State: ENABLE or DISABLE + * @param State ENABLE or DISABLE * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_SetPullDown(DSI_HandleTypeDef *hdsi, FunctionalState State) @@ -2188,9 +2186,9 @@ /** * @brief Switch off the contention detection on data lanes - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. - * @param State: ENABLE or DISABLE + * @param State ENABLE or DISABLE * @retval HAL status */ HAL_StatusTypeDef HAL_DSI_SetContentionDetectionOff(DSI_HandleTypeDef *hdsi, FunctionalState State) @@ -2233,7 +2231,7 @@ /** * @brief Return the DSI state - * @param hdsi: pointer to a DSI_HandleTypeDef structure that contains + * @param hdsi pointer to a DSI_HandleTypeDef structure that contains * the configuration information for the DSI. * @retval HAL state */
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dsi.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_dsi.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_dsi.h * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief Header file of DSI HAL module. ****************************************************************************** * @attention @@ -889,64 +887,64 @@ /* Exported macros -----------------------------------------------------------*/ /** * @brief Enables the DSI host. - * @param __HANDLE__: DSI handle + * @param __HANDLE__ DSI handle * @retval None. */ #define __HAL_DSI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= DSI_CR_EN) /** * @brief Disables the DSI host. - * @param __HANDLE__: DSI handle + * @param __HANDLE__ DSI handle * @retval None. */ #define __HAL_DSI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~DSI_CR_EN) /** * @brief Enables the DSI wrapper. - * @param __HANDLE__: DSI handle + * @param __HANDLE__ DSI handle * @retval None. */ #define __HAL_DSI_WRAPPER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->WCR |= DSI_WCR_DSIEN) /** * @brief Disable the DSI wrapper. - * @param __HANDLE__: DSI handle + * @param __HANDLE__ DSI handle * @retval None. */ #define __HAL_DSI_WRAPPER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->WCR &= ~DSI_WCR_DSIEN) /** * @brief Enables the DSI PLL. - * @param __HANDLE__: DSI handle + * @param __HANDLE__ DSI handle * @retval None. */ #define __HAL_DSI_PLL_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR |= DSI_WRPCR_PLLEN) /** * @brief Disables the DSI PLL. - * @param __HANDLE__: DSI handle + * @param __HANDLE__ DSI handle * @retval None. */ #define __HAL_DSI_PLL_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR &= ~DSI_WRPCR_PLLEN) /** * @brief Enables the DSI regulator. - * @param __HANDLE__: DSI handle + * @param __HANDLE__ DSI handle * @retval None. */ #define __HAL_DSI_REG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR |= DSI_WRPCR_REGEN) /** * @brief Disables the DSI regulator. - * @param __HANDLE__: DSI handle + * @param __HANDLE__ DSI handle * @retval None. */ #define __HAL_DSI_REG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->WRPCR &= ~DSI_WRPCR_REGEN) /** * @brief Get the DSI pending flags. - * @param __HANDLE__: DSI handle. - * @param __FLAG__: Get the specified flag. + * @param __HANDLE__ DSI handle. + * @param __FLAG__ Get the specified flag. * This parameter can be any combination of the following values: * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag @@ -962,8 +960,8 @@ /** * @brief Clears the DSI pending flags. - * @param __HANDLE__: DSI handle. - * @param __FLAG__: specifies the flag to clear. + * @param __HANDLE__ DSI handle. + * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: * @arg DSI_FLAG_TE : Tearing Effect Interrupt Flag * @arg DSI_FLAG_ER : End of Refresh Interrupt Flag @@ -976,8 +974,8 @@ /** * @brief Enables the specified DSI interrupts. - * @param __HANDLE__: DSI handle. - * @param __INTERRUPT__: specifies the DSI interrupt sources to be enabled. + * @param __HANDLE__ DSI handle. + * @param __INTERRUPT__ specifies the DSI interrupt sources to be enabled. * This parameter can be any combination of the following values: * @arg DSI_IT_TE : Tearing Effect Interrupt * @arg DSI_IT_ER : End of Refresh Interrupt @@ -990,8 +988,8 @@ /** * @brief Disables the specified DSI interrupts. - * @param __HANDLE__: DSI handle - * @param __INTERRUPT__: specifies the DSI interrupt sources to be disabled. + * @param __HANDLE__ DSI handle + * @param __INTERRUPT__ specifies the DSI interrupt sources to be disabled. * This parameter can be any combination of the following values: * @arg DSI_IT_TE : Tearing Effect Interrupt * @arg DSI_IT_ER : End of Refresh Interrupt @@ -1004,8 +1002,8 @@ /** * @brief Checks whether the specified DSI interrupt has occurred or not. - * @param __HANDLE__: DSI handle - * @param __INTERRUPT__: specifies the DSI interrupt source to check. + * @param __HANDLE__ DSI handle + * @param __INTERRUPT__ specifies the DSI interrupt source to check. * This parameter can be one of the following values: * @arg DSI_IT_TE : Tearing Effect Interrupt * @arg DSI_IT_ER : End of Refresh Interrupt
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_eth.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_eth.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_eth.c
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief ETH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Ethernet (ETH) peripheral:
@@ -167,7 +165,7 @@
/**
* @brief Initializes the Ethernet MAC and DMA according to default
* parameters.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval HAL status
*/
@@ -440,7 +438,7 @@
/**
* @brief De-Initializes the ETH peripheral.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval HAL status
*/
@@ -464,11 +462,11 @@
/**
* @brief Initializes the DMA Tx descriptors in chain mode.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
- * @param DMATxDescTab: Pointer to the first Tx desc list
- * @param TxBuff: Pointer to the first TxBuffer list
- * @param TxBuffCount: Number of the used Tx desc in the list
+ * @param DMATxDescTab Pointer to the first Tx desc list
+ * @param TxBuff Pointer to the first TxBuffer list
+ * @param TxBuffCount Number of the used Tx desc in the list
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t *TxBuff, uint32_t TxBuffCount)
@@ -531,11 +529,11 @@
/**
* @brief Initializes the DMA Rx descriptors in chain mode.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
- * @param DMARxDescTab: Pointer to the first Rx desc list
- * @param RxBuff: Pointer to the first RxBuffer list
- * @param RxBuffCount: Number of the used Rx desc in the list
+ * @param DMARxDescTab Pointer to the first Rx desc list
+ * @param RxBuff Pointer to the first RxBuffer list
+ * @param RxBuffCount Number of the used Rx desc in the list
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount)
@@ -601,7 +599,7 @@
/**
* @brief Initializes the ETH MSP.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
@@ -617,7 +615,7 @@
/**
* @brief DeInitializes ETH MSP.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
@@ -660,9 +658,9 @@
/**
* @brief Sends an Ethernet frame.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
- * @param FrameLength: Amount of data to be sent
+ * @param FrameLength Amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength)
@@ -717,8 +715,11 @@
heth->TxDesc->Status |=ETH_DMATXDESC_FS|ETH_DMATXDESC_LS;
/* Set frame size */
heth->TxDesc->ControlBufferSize = (FrameLength & ETH_DMATXDESC_TBS1);
- /* Ensure rest of descriptor is written to RAM before the OWN bit */
+
+ // MBED: added
+ // Ensure rest of descriptor is written to RAM before the OWN bit
__DMB();
+
/* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
/* Point to next descriptor */
@@ -748,16 +749,19 @@
heth->TxDesc->ControlBufferSize = (size & ETH_DMATXDESC_TBS1);
}
- /* Ensure rest of descriptor is written to RAM before the OWN bit */
+ // MBED: added
+ // Ensure rest of descriptor is written to RAM before the OWN bit
__DMB();
+
/* Set Own bit of the Tx descriptor Status: gives the buffer back to ETHERNET DMA */
heth->TxDesc->Status |= ETH_DMATXDESC_OWN;
/* point to next descriptor */
heth->TxDesc = (ETH_DMADescTypeDef *)(heth->TxDesc->Buffer2NextDescAddr);
}
}
-
- /* Ensure all descriptors are written to RAM before checking transmitter status */
+
+ // MBED: added
+ // Ensure all descriptors are written to RAM before checking transmitter status
__DMB();
/* When Tx Buffer unavailable flag is set: clear it and resume transmission */
@@ -781,7 +785,7 @@
/**
* @brief Checks for received frames.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval HAL status
*/
@@ -861,7 +865,7 @@
/**
* @brief Gets the Received frame in interrupt mode.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval HAL status
*/
@@ -946,7 +950,7 @@
/**
* @brief This function handles ETH interrupt request.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval HAL status
*/
@@ -1006,7 +1010,7 @@
/**
* @brief Tx Transfer completed callbacks.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
@@ -1022,7 +1026,7 @@
/**
* @brief Rx Transfer completed callbacks.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
@@ -1038,7 +1042,7 @@
/**
* @brief Ethernet transfer error callbacks
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
@@ -1054,14 +1058,14 @@
/**
* @brief Reads a PHY register
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
- * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
+ * @param PHYReg PHY register address, is the index of one of the 32 PHY register.
* This parameter can be one of the following values:
* PHY_BCR: Transceiver Basic Control Register,
* PHY_BSR: Transceiver Basic Status Register.
* More PHY register could be read depending on the used PHY
- * @param RegValue: PHY register value
+ * @param RegValue PHY register value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue)
@@ -1127,13 +1131,13 @@
/**
* @brief Writes to a PHY register.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
- * @param PHYReg: PHY register address, is the index of one of the 32 PHY register.
+ * @param PHYReg PHY register address, is the index of one of the 32 PHY register.
* This parameter can be one of the following values:
* PHY_BCR: Transceiver Control Register.
* More PHY register could be written depending on the used PHY
- * @param RegValue: the value to write
+ * @param RegValue the value to write
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue)
@@ -1224,7 +1228,7 @@
/**
* @brief Enables Ethernet MAC and DMA reception/transmission
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval HAL status
*/
@@ -1263,7 +1267,7 @@
/**
* @brief Stop Ethernet MAC and DMA reception/transmission
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval HAL status
*/
@@ -1302,9 +1306,9 @@
/**
* @brief Set ETH MAC Configuration.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
- * @param macconf: MAC Configuration structure
+ * @param macconf MAC Configuration structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf)
@@ -1469,9 +1473,9 @@
/**
* @brief Sets ETH DMA Configuration.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
- * @param dmaconf: DMA Configuration structure
+ * @param dmaconf DMA Configuration structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf)
@@ -1577,7 +1581,7 @@
/**
* @brief Return the ETH HAL state
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval HAL state
*/
@@ -1601,9 +1605,9 @@
/**
* @brief Configures Ethernet MAC and DMA with default parameters.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
- * @param err: Ethernet Init error
+ * @param err Ethernet Init error
* @retval HAL status
*/
static void ETH_MACDMAConfig(ETH_HandleTypeDef *heth, uint32_t err)
@@ -1858,15 +1862,15 @@
/**
* @brief Configures the selected MAC address.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
- * @param MacAddr: The MAC address to configure
+ * @param MacAddr The MAC address to configure
* This parameter can be one of the following values:
* @arg ETH_MAC_Address0: MAC Address0
* @arg ETH_MAC_Address1: MAC Address1
* @arg ETH_MAC_Address2: MAC Address2
* @arg ETH_MAC_Address3: MAC Address3
- * @param Addr: Pointer to MAC address buffer data (6 bytes)
+ * @param Addr Pointer to MAC address buffer data (6 bytes)
* @retval HAL status
*/
static void ETH_MACAddressConfig(ETH_HandleTypeDef *heth, uint32_t MacAddr, uint8_t *Addr)
@@ -1889,7 +1893,7 @@
/**
* @brief Enables the MAC transmission.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
@@ -1909,7 +1913,7 @@
/**
* @brief Disables the MAC transmission.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
@@ -1929,7 +1933,7 @@
/**
* @brief Enables the MAC reception.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
@@ -1949,7 +1953,7 @@
/**
* @brief Disables the MAC reception.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
@@ -1969,7 +1973,7 @@
/**
* @brief Enables the DMA transmission.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
@@ -1981,7 +1985,7 @@
/**
* @brief Disables the DMA transmission.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
@@ -1993,7 +1997,7 @@
/**
* @brief Enables the DMA reception.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
@@ -2005,7 +2009,7 @@
/**
* @brief Disables the DMA reception.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
@@ -2017,7 +2021,7 @@
/**
* @brief Clears the ETHERNET transmit FIFO.
- * @param heth: pointer to a ETH_HandleTypeDef structure that contains
+ * @param heth pointer to a ETH_HandleTypeDef structure that contains
* the configuration information for ETHERNET module
* @retval None
*/
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_eth.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_eth.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_eth.h
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief Header file of ETH HAL module.
******************************************************************************
* @attention
@@ -1593,80 +1591,80 @@
*/
/** @brief Reset ETH handle state
- * @param __HANDLE__: specifies the ETH handle.
+ * @param __HANDLE__ specifies the ETH handle.
* @retval None
*/
#define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
/**
* @brief Checks whether the specified Ethernet DMA Tx Desc flag is set or not.
- * @param __HANDLE__: ETH Handle
- * @param __FLAG__: specifies the flag of TDES0 to check.
+ * @param __HANDLE__ ETH Handle
+ * @param __FLAG__ specifies the flag of TDES0 to check.
* @retval the ETH_DMATxDescFlag (SET or RESET).
*/
#define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
/**
* @brief Checks whether the specified Ethernet DMA Rx Desc flag is set or not.
- * @param __HANDLE__: ETH Handle
- * @param __FLAG__: specifies the flag of RDES0 to check.
+ * @param __HANDLE__ ETH Handle
+ * @param __FLAG__ specifies the flag of RDES0 to check.
* @retval the ETH_DMATxDescFlag (SET or RESET).
*/
#define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
/**
* @brief Enables the specified DMA Rx Desc receive interrupt.
- * @param __HANDLE__: ETH Handle
+ * @param __HANDLE__ ETH Handle
* @retval None
*/
#define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
/**
* @brief Disables the specified DMA Rx Desc receive interrupt.
- * @param __HANDLE__: ETH Handle
+ * @param __HANDLE__ ETH Handle
* @retval None
*/
#define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC)
/**
* @brief Set the specified DMA Rx Desc Own bit.
- * @param __HANDLE__: ETH Handle
+ * @param __HANDLE__ ETH Handle
* @retval None
*/
#define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN)
/**
* @brief Returns the specified Ethernet DMA Tx Desc collision count.
- * @param __HANDLE__: ETH Handle
+ * @param __HANDLE__ ETH Handle
* @retval The Transmit descriptor collision counter value.
*/
#define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
/**
* @brief Set the specified DMA Tx Desc Own bit.
- * @param __HANDLE__: ETH Handle
+ * @param __HANDLE__ ETH Handle
* @retval None
*/
#define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN)
/**
* @brief Enables the specified DMA Tx Desc Transmit interrupt.
- * @param __HANDLE__: ETH Handle
+ * @param __HANDLE__ ETH Handle
* @retval None
*/
#define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC)
/**
* @brief Disables the specified DMA Tx Desc Transmit interrupt.
- * @param __HANDLE__: ETH Handle
+ * @param __HANDLE__ ETH Handle
* @retval None
*/
#define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
/**
* @brief Selects the specified Ethernet DMA Tx Desc Checksum Insertion.
- * @param __HANDLE__: ETH Handle
- * @param __CHECKSUM__: specifies is the DMA Tx desc checksum insertion.
+ * @param __HANDLE__ ETH Handle
+ * @param __CHECKSUM__ specifies is the DMA Tx desc checksum insertion.
* This parameter can be one of the following values:
* @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass
* @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum
@@ -1678,36 +1676,36 @@
/**
* @brief Enables the DMA Tx Desc CRC.
- * @param __HANDLE__: ETH Handle
+ * @param __HANDLE__ ETH Handle
* @retval None
*/
#define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
/**
* @brief Disables the DMA Tx Desc CRC.
- * @param __HANDLE__: ETH Handle
+ * @param __HANDLE__ ETH Handle
* @retval None
*/
#define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC)
/**
* @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes.
- * @param __HANDLE__: ETH Handle
+ * @param __HANDLE__ ETH Handle
* @retval None
*/
#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
/**
* @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes.
- * @param __HANDLE__: ETH Handle
+ * @param __HANDLE__ ETH Handle
* @retval None
*/
#define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP)
/**
* @brief Enables the specified Ethernet MAC interrupts.
- * @param __HANDLE__ : ETH Handle
- * @param __INTERRUPT__: specifies the Ethernet MAC interrupt sources to be
+ * @param __HANDLE__ ETH Handle
+ * @param __INTERRUPT__ specifies the Ethernet MAC interrupt sources to be
* enabled or disabled.
* This parameter can be any combination of the following values:
* @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
@@ -1718,8 +1716,8 @@
/**
* @brief Disables the specified Ethernet MAC interrupts.
- * @param __HANDLE__ : ETH Handle
- * @param __INTERRUPT__: specifies the Ethernet MAC interrupt sources to be
+ * @param __HANDLE__ ETH Handle
+ * @param __INTERRUPT__ specifies the Ethernet MAC interrupt sources to be
* enabled or disabled.
* This parameter can be any combination of the following values:
* @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
@@ -1730,36 +1728,36 @@
/**
* @brief Initiate a Pause Control Frame (Full-duplex only).
- * @param __HANDLE__: ETH Handle
+ * @param __HANDLE__ ETH Handle
* @retval None
*/
#define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
/**
* @brief Checks whether the Ethernet flow control busy bit is set or not.
- * @param __HANDLE__: ETH Handle
+ * @param __HANDLE__ ETH Handle
* @retval The new state of flow control busy status bit (SET or RESET).
*/
#define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
/**
* @brief Enables the MAC Back Pressure operation activation (Half-duplex only).
- * @param __HANDLE__: ETH Handle
+ * @param __HANDLE__ ETH Handle
* @retval None
*/
#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
/**
* @brief Disables the MAC BackPressure operation activation (Half-duplex only).
- * @param __HANDLE__: ETH Handle
+ * @param __HANDLE__ ETH Handle
* @retval None
*/
#define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
/**
* @brief Checks whether the specified Ethernet MAC flag is set or not.
- * @param __HANDLE__: ETH Handle
- * @param __FLAG__: specifies the flag to check.
+ * @param __HANDLE__ ETH Handle
+ * @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
* @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
@@ -1772,8 +1770,8 @@
/**
* @brief Enables the specified Ethernet DMA interrupts.
- * @param __HANDLE__ : ETH Handle
- * @param __INTERRUPT__: specifies the Ethernet DMA interrupt sources to be
+ * @param __HANDLE__ ETH Handle
+ * @param __INTERRUPT__ specifies the Ethernet DMA interrupt sources to be
* enabled @ref ETH_DMA_Interrupts
* @retval None
*/
@@ -1781,8 +1779,8 @@
/**
* @brief Disables the specified Ethernet DMA interrupts.
- * @param __HANDLE__ : ETH Handle
- * @param __INTERRUPT__: specifies the Ethernet DMA interrupt sources to be
+ * @param __HANDLE__ ETH Handle
+ * @param __INTERRUPT__ specifies the Ethernet DMA interrupt sources to be
* disabled. @ref ETH_DMA_Interrupts
* @retval None
*/
@@ -1790,32 +1788,32 @@
/**
* @brief Clears the Ethernet DMA IT pending bit.
- * @param __HANDLE__ : ETH Handle
- * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
+ * @param __HANDLE__ ETH Handle
+ * @param __INTERRUPT__ specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
* @retval None
*/
#define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
/**
* @brief Checks whether the specified Ethernet DMA flag is set or not.
-* @param __HANDLE__: ETH Handle
- * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Flags
+* @param __HANDLE__ ETH Handle
+ * @param __FLAG__ specifies the flag to check. @ref ETH_DMA_Flags
* @retval The new state of ETH_DMA_FLAG (SET or RESET).
*/
#define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
/**
* @brief Checks whether the specified Ethernet DMA flag is set or not.
- * @param __HANDLE__: ETH Handle
- * @param __FLAG__: specifies the flag to clear. @ref ETH_DMA_Flags
+ * @param __HANDLE__ ETH Handle
+ * @param __FLAG__ specifies the flag to clear. @ref ETH_DMA_Flags
* @retval The new state of ETH_DMA_FLAG (SET or RESET).
*/
#define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__))
/**
* @brief Checks whether the specified Ethernet DMA overflow flag is set or not.
- * @param __HANDLE__: ETH Handle
- * @param __OVERFLOW__: specifies the DMA overflow flag to check.
+ * @param __HANDLE__ ETH Handle
+ * @param __OVERFLOW__ specifies the DMA overflow flag to check.
* This parameter can be one of the following values:
* @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter
* @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter
@@ -1825,8 +1823,8 @@
/**
* @brief Set the DMA Receive status watchdog timer register value
- * @param __HANDLE__: ETH Handle
- * @param __VALUE__: DMA Receive status watchdog timer register value
+ * @param __HANDLE__ ETH Handle
+ * @param __VALUE__ DMA Receive status watchdog timer register value
* @retval None
*/
#define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
@@ -1834,7 +1832,7 @@
/**
* @brief Enables any unicast packet filtered by the MAC address
* recognition to be a wake-up frame.
- * @param __HANDLE__: ETH Handle.
+ * @param __HANDLE__ ETH Handle.
* @retval None
*/
#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU)
@@ -1842,57 +1840,57 @@
/**
* @brief Disables any unicast packet filtered by the MAC address
* recognition to be a wake-up frame.
- * @param __HANDLE__: ETH Handle.
+ * @param __HANDLE__ ETH Handle.
* @retval None
*/
#define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
/**
* @brief Enables the MAC Wake-Up Frame Detection.
- * @param __HANDLE__: ETH Handle.
+ * @param __HANDLE__ ETH Handle.
* @retval None
*/
#define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE)
/**
* @brief Disables the MAC Wake-Up Frame Detection.
- * @param __HANDLE__: ETH Handle.
+ * @param __HANDLE__ ETH Handle.
* @retval None
*/
#define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
/**
* @brief Enables the MAC Magic Packet Detection.
- * @param __HANDLE__: ETH Handle.
+ * @param __HANDLE__ ETH Handle.
* @retval None
*/
#define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE)
/**
* @brief Disables the MAC Magic Packet Detection.
- * @param __HANDLE__: ETH Handle.
+ * @param __HANDLE__ ETH Handle.
* @retval None
*/
#define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
/**
* @brief Enables the MAC Power Down.
- * @param __HANDLE__: ETH Handle
+ * @param __HANDLE__ ETH Handle
* @retval None
*/
#define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD)
/**
* @brief Disables the MAC Power Down.
- * @param __HANDLE__: ETH Handle
+ * @param __HANDLE__ ETH Handle
* @retval None
*/
#define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
/**
* @brief Checks whether the specified Ethernet PMT flag is set or not.
- * @param __HANDLE__: ETH Handle.
- * @param __FLAG__: specifies the flag to check.
+ * @param __HANDLE__ ETH Handle.
+ * @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset
* @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received
@@ -1903,14 +1901,14 @@
/**
* @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
- * @param __HANDLE__: ETH Handle.
+ * @param __HANDLE__ ETH Handle.
* @retval None
*/
#define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP))
/**
* @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)
- * @param __HANDLE__: ETH Handle.
+ * @param __HANDLE__ ETH Handle.
* @retval None
*/
#define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
@@ -1918,57 +1916,57 @@
/**
* @brief Enables the MMC Counter Freeze.
- * @param __HANDLE__: ETH Handle.
+ * @param __HANDLE__ ETH Handle.
* @retval None
*/
#define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF)
/**
* @brief Disables the MMC Counter Freeze.
- * @param __HANDLE__: ETH Handle.
+ * @param __HANDLE__ ETH Handle.
* @retval None
*/
#define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
/**
* @brief Enables the MMC Reset On Read.
- * @param __HANDLE__: ETH Handle.
+ * @param __HANDLE__ ETH Handle.
* @retval None
*/
#define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR)
/**
* @brief Disables the MMC Reset On Read.
- * @param __HANDLE__: ETH Handle.
+ * @param __HANDLE__ ETH Handle.
* @retval None
*/
#define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
/**
* @brief Enables the MMC Counter Stop Rollover.
- * @param __HANDLE__: ETH Handle.
+ * @param __HANDLE__ ETH Handle.
* @retval None
*/
#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
/**
* @brief Disables the MMC Counter Stop Rollover.
- * @param __HANDLE__: ETH Handle.
+ * @param __HANDLE__ ETH Handle.
* @retval None
*/
#define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR)
/**
* @brief Resets the MMC Counters.
- * @param __HANDLE__: ETH Handle.
+ * @param __HANDLE__ ETH Handle.
* @retval None
*/
#define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR)
/**
* @brief Enables the specified Ethernet MMC Rx interrupts.
- * @param __HANDLE__: ETH Handle.
- * @param __INTERRUPT__: specifies the Ethernet MMC interrupt sources to be enabled or disabled.
+ * @param __HANDLE__ ETH Handle.
+ * @param __INTERRUPT__ specifies the Ethernet MMC interrupt sources to be enabled or disabled.
* This parameter can be one of the following values:
* @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
* @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
@@ -1978,8 +1976,8 @@
#define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF)
/**
* @brief Disables the specified Ethernet MMC Rx interrupts.
- * @param __HANDLE__: ETH Handle.
- * @param __INTERRUPT__: specifies the Ethernet MMC interrupt sources to be enabled or disabled.
+ * @param __HANDLE__ ETH Handle.
+ * @param __INTERRUPT__ specifies the Ethernet MMC interrupt sources to be enabled or disabled.
* This parameter can be one of the following values:
* @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
* @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
@@ -1989,8 +1987,8 @@
#define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFF)
/**
* @brief Enables the specified Ethernet MMC Tx interrupts.
- * @param __HANDLE__: ETH Handle.
- * @param __INTERRUPT__: specifies the Ethernet MMC interrupt sources to be enabled or disabled.
+ * @param __HANDLE__ ETH Handle.
+ * @param __INTERRUPT__ specifies the Ethernet MMC interrupt sources to be enabled or disabled.
* This parameter can be one of the following values:
* @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
* @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
@@ -2001,8 +1999,8 @@
/**
* @brief Disables the specified Ethernet MMC Tx interrupts.
- * @param __HANDLE__: ETH Handle.
- * @param __INTERRUPT__: specifies the Ethernet MMC interrupt sources to be enabled or disabled.
+ * @param __HANDLE__ ETH Handle.
+ * @param __INTERRUPT__ specifies the Ethernet MMC interrupt sources to be enabled or disabled.
* This parameter can be one of the following values:
* @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
* @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
@@ -2075,15 +2073,17 @@
* @brief Enables rising/falling edge trigger to the ETH External interrupt line.
* @retval None
*/
-#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\
- EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP
+#define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\
+ EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP;\
+ }while(0)
/**
* @brief Disables rising/falling edge trigger to the ETH External interrupt line.
* @retval None
*/
-#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
- EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
+#define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() do{EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
+ EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
+ }while(0)
/**
* @brief Generate a Software interrupt on selected EXTI line.
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_flash.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_flash.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_flash.c
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief FLASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the internal FLASH memory:
@@ -172,10 +170,10 @@
/**
* @brief Program byte, halfword, word or double word at a specified address
- * @param TypeProgram: Indicate the way to program at a specified address.
+ * @param TypeProgram Indicate the way to program at a specified address.
* This parameter can be a value of @ref FLASH_Type_Program
- * @param Address: specifies the address to be programmed.
- * @param Data: specifies the data to be programmed
+ * @param Address specifies the address to be programmed.
+ * @param Data specifies the data to be programmed
*
* @retval HAL_StatusTypeDef HAL Status
*/
@@ -241,10 +239,10 @@
/**
* @brief Program byte, halfword, word or double word at a specified address with interrupt enabled.
- * @param TypeProgram: Indicate the way to program at a specified address.
+ * @param TypeProgram Indicate the way to program at a specified address.
* This parameter can be a value of @ref FLASH_Type_Program
- * @param Address: specifies the address to be programmed.
- * @param Data: specifies the data to be programmed
+ * @param Address specifies the address to be programmed.
+ * @param Data specifies the data to be programmed
*
* @retval HAL Status
*/
@@ -438,7 +436,7 @@
/**
* @brief FLASH end of operation interrupt callback
- * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure
+ * @param ReturnValue The value saved in this parameter depends on the ongoing procedure
* - Sectors Erase: Sector which has been erased (if 0xFFFFFFFF, it means that
* all the selected sectors have been erased)
* - Program : Address which was selected for data program
@@ -456,7 +454,7 @@
/**
* @brief FLASH operation error interrupt callback
- * @param ReturnValue: The value saved in this parameter depends on the ongoing procedure
+ * @param ReturnValue The value saved in this parameter depends on the ongoing procedure
* - Sectors Erase: Sector which has been erased (if 0xFFFFFFFF, it means that
* all the selected sectors have been erased)
* - Program : Address which was selected for data program
@@ -497,18 +495,22 @@
*/
HAL_StatusTypeDef HAL_FLASH_Unlock(void)
{
- if((FLASH->CR & FLASH_CR_LOCK) != RESET)
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
{
/* Authorize the FLASH Registers access */
- FLASH->KEYR = FLASH_KEY1;
- FLASH->KEYR = FLASH_KEY2;
+ WRITE_REG(FLASH->KEYR, FLASH_KEY1);
+ WRITE_REG(FLASH->KEYR, FLASH_KEY2);
+
+ /* Verify Flash is unlocked */
+ if(READ_BIT(FLASH->CR, FLASH_CR_LOCK) != RESET)
+ {
+ status = HAL_ERROR;
+ }
}
- else
- {
- return HAL_ERROR;
- }
-
- return HAL_OK;
+
+ return status;
}
/**
@@ -606,7 +608,7 @@
/**
* @brief Wait for a FLASH operation to complete.
- * @param Timeout: maximum flash operationtimeout
+ * @param Timeout maximum flash operationtimeout
* @retval HAL Status
*/
HAL_StatusTypeDef FLASH_WaitForLastOperation(uint32_t Timeout)
@@ -660,8 +662,8 @@
* @note If an erase and a program operations are requested simultaneously,
* the erase operation is performed before the program one.
*
- * @param Address: specifies the address to be programmed.
- * @param Data: specifies the data to be programmed.
+ * @param Address specifies the address to be programmed.
+ * @param Data specifies the data to be programmed.
* @retval None
*/
static void FLASH_Program_DoubleWord(uint32_t Address, uint64_t Data)
@@ -673,9 +675,11 @@
FLASH->CR &= CR_PSIZE_MASK;
FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD;
FLASH->CR |= FLASH_CR_PG;
-
- *(__IO uint64_t*)Address = Data;
-
+
+ /* Program the double-word */
+ *(__IO uint32_t*)Address = (uint32_t)Data;
+ *(__IO uint32_t*)(Address+4) = (uint32_t)(Data >> 32);
+
/* Data synchronous Barrier (DSB) Just after the write operation
This will force the CPU to respect the sequence of instruction (no optimization).*/
__DSB();
@@ -690,8 +694,8 @@
* @note If an erase and a program operations are requested simultaneously,
* the erase operation is performed before the program one.
*
- * @param Address: specifies the address to be programmed.
- * @param Data: specifies the data to be programmed.
+ * @param Address specifies the address to be programmed.
+ * @param Data specifies the data to be programmed.
* @retval None
*/
static void FLASH_Program_Word(uint32_t Address, uint32_t Data)
@@ -719,8 +723,8 @@
* @note If an erase and a program operations are requested simultaneously,
* the erase operation is performed before the program one.
*
- * @param Address: specifies the address to be programmed.
- * @param Data: specifies the data to be programmed.
+ * @param Address specifies the address to be programmed.
+ * @param Data specifies the data to be programmed.
* @retval None
*/
static void FLASH_Program_HalfWord(uint32_t Address, uint16_t Data)
@@ -749,8 +753,8 @@
* @note If an erase and a program operations are requested simultaneously,
* the erase operation is performed before the program one.
*
- * @param Address: specifies the address to be programmed.
- * @param Data: specifies the data to be programmed.
+ * @param Address specifies the address to be programmed.
+ * @param Data specifies the data to be programmed.
* @retval None
*/
static void FLASH_Program_Byte(uint32_t Address, uint8_t Data)
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_flash.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_flash.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_flash.h * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief Header file of FLASH HAL module. ****************************************************************************** * @attention @@ -209,7 +207,7 @@ */ /** * @brief Set the FLASH Latency. - * @param __LATENCY__: FLASH Latency + * @param __LATENCY__ FLASH Latency * The value of this parameter depend on device used within the same series * @retval none */ @@ -258,7 +256,7 @@ /** * @brief Enable the specified FLASH interrupt. - * @param __INTERRUPT__ : FLASH interrupt + * @param __INTERRUPT__ FLASH interrupt * This parameter can be any combination of the following values: * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt * @arg FLASH_IT_ERR: Error Interrupt @@ -268,7 +266,7 @@ /** * @brief Disable the specified FLASH interrupt. - * @param __INTERRUPT__ : FLASH interrupt + * @param __INTERRUPT__ FLASH interrupt * This parameter can be any combination of the following values: * @arg FLASH_IT_EOP: End of FLASH Operation Interrupt * @arg FLASH_IT_ERR: Error Interrupt @@ -278,7 +276,7 @@ /** * @brief Get the specified FLASH flag status. - * @param __FLAG__: specifies the FLASH flag to check. + * @param __FLAG__ specifies the FLASH flag to check. * This parameter can be one of the following values: * @arg FLASH_FLAG_EOP : FLASH End of Operation flag * @arg FLASH_FLAG_OPERR : FLASH operation Error flag @@ -293,7 +291,7 @@ /** * @brief Clear the specified FLASH flag. - * @param __FLAG__: specifies the FLASH flags to clear. + * @param __FLAG__ specifies the FLASH flags to clear. * This parameter can be any combination of the following values: * @arg FLASH_FLAG_EOP : FLASH End of Operation flag * @arg FLASH_FLAG_OPERR : FLASH operation Error flag
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_flash_ex.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_flash_ex.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_flash_ex.c * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief Extended FLASH HAL module driver. * This file provides firmware functions to manage the following * functionalities of the FLASH extension peripheral: @@ -164,10 +162,10 @@ */ /** * @brief Perform a mass erase or erase the specified FLASH memory sectors - * @param[in] pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that + * @param[in] pEraseInit pointer to an FLASH_EraseInitTypeDef structure that * contains the configuration information for the erasing. * - * @param[out] SectorError: pointer to variable that + * @param[out] SectorError pointer to variable that * contains the configuration information on faulty sector in case of error * (0xFFFFFFFF means that all the sectors have been correctly erased) * @@ -241,7 +239,7 @@ /** * @brief Perform a mass erase or erase the specified FLASH memory sectors with interrupt enabled - * @param pEraseInit: pointer to an FLASH_EraseInitTypeDef structure that + * @param pEraseInit pointer to an FLASH_EraseInitTypeDef structure that * contains the configuration information for the erasing. * * @retval HAL Status @@ -297,7 +295,7 @@ /** * @brief Program option bytes - * @param pOBInit: pointer to an FLASH_OBInitStruct structure that + * @param pOBInit pointer to an FLASH_OBInitStruct structure that * contains the configuration information for the programming. * * @retval HAL Status @@ -396,7 +394,7 @@ /** * @brief Get the Option byte configuration - * @param pOBInit: pointer to an FLASH_OBInitStruct structure that + * @param pOBInit pointer to an FLASH_OBInitStruct structure that * contains the configuration information for the programming. * * @retval None @@ -439,7 +437,7 @@ #if defined (FLASH_OPTCR_nDBANK) /** * @brief Full erase of FLASH memory sectors - * @param VoltageRange: The device voltage range which defines the erase parallelism. + * @param VoltageRange The device voltage range which defines the erase parallelism. * This parameter can be one of the following values: * @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, * the operation will be done by byte (8-bit) @@ -449,7 +447,7 @@ * the operation will be done by word (32-bit) * @arg VOLTAGE_RANGE_4: when the device voltage range is 2.7V to 3.6V + External Vpp, * the operation will be done by double word (64-bit) - * @param Banks: Banks to be erased + * @param Banks Banks to be erased * This parameter can be one of the following values: * @arg FLASH_BANK_1: Bank1 to be erased * @arg FLASH_BANK_2: Bank2 to be erased @@ -488,9 +486,9 @@ /** * @brief Erase the specified FLASH memory sector - * @param Sector: FLASH sector to erase + * @param Sector FLASH sector to erase * The value of this parameter depend on device used within the same series - * @param VoltageRange: The device voltage range which defines the erase parallelism. + * @param VoltageRange The device voltage range which defines the erase parallelism. * This parameter can be one of the following values: * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, * the operation will be done by byte (8-bit) @@ -538,7 +536,7 @@ FLASH->CR &= CR_PSIZE_MASK; FLASH->CR |= tmp_psize; CLEAR_BIT(FLASH->CR, FLASH_CR_SNB); - FLASH->CR |= FLASH_CR_SER | (Sector << POSITION_VAL(FLASH_CR_SNB)); + FLASH->CR |= FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos); FLASH->CR |= FLASH_CR_STRT; /* Data synchronous Barrier (DSB) Just after the write operation @@ -558,35 +556,35 @@ /** * @brief Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. - * @param Wwdg: Selects the IWDG mode + * @param Wwdg Selects the IWDG mode * This parameter can be one of the following values: * @arg OB_WWDG_SW: Software WWDG selected * @arg OB_WWDG_HW: Hardware WWDG selected - * @param Iwdg: Selects the WWDG mode + * @param Iwdg Selects the WWDG mode * This parameter can be one of the following values: * @arg OB_IWDG_SW: Software IWDG selected * @arg OB_IWDG_HW: Hardware IWDG selected - * @param Stop: Reset event when entering STOP mode. + * @param Stop Reset event when entering STOP mode. * This parameter can be one of the following values: * @arg OB_STOP_NO_RST: No reset generated when entering in STOP * @arg OB_STOP_RST: Reset generated when entering in STOP - * @param Stdby: Reset event when entering Standby mode. + * @param Stdby Reset event when entering Standby mode. * This parameter can be one of the following values: * @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY * @arg OB_STDBY_RST: Reset generated when entering in STANDBY - * @param Iwdgstop: Independent watchdog counter freeze in Stop mode. + * @param Iwdgstop Independent watchdog counter freeze in Stop mode. * This parameter can be one of the following values: * @arg OB_IWDG_STOP_FREEZE: Freeze IWDG counter in STOP * @arg OB_IWDG_STOP_ACTIVE: IWDG counter active in STOP - * @param Iwdgstdby: Independent watchdog counter freeze in standby mode. + * @param Iwdgstdby Independent watchdog counter freeze in standby mode. * This parameter can be one of the following values: * @arg OB_IWDG_STDBY_FREEZE: Freeze IWDG counter in STANDBY * @arg OB_IWDG_STDBY_ACTIVE: IWDG counter active in STANDBY - * @param NDBank: Flash Single Bank mode enabled. + * @param NDBank Flash Single Bank mode enabled. * This parameter can be one of the following values: * @arg OB_NDBANK_SINGLE_BANK: enable 256 bits mode (Flash is a single bank) * @arg OB_NDBANK_DUAL_BANK: disable 256 bits mode (Flash is a dual bank in 128 bits mode) - * @param NDBoot: Flash Dual boot mode disable. + * @param NDBoot Flash Dual boot mode disable. * This parameter can be one of the following values: * @arg OB_DUAL_BOOT_DISABLE: Disable Dual Boot * @arg OB_DUAL_BOOT_ENABLE: Enable Dual Boot @@ -643,7 +641,7 @@ /** * @brief Full erase of FLASH memory sectors - * @param VoltageRange: The device voltage range which defines the erase parallelism. + * @param VoltageRange The device voltage range which defines the erase parallelism. * This parameter can be one of the following values: * @arg VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, * the operation will be done by byte (8-bit) @@ -672,9 +670,9 @@ /** * @brief Erase the specified FLASH memory sector - * @param Sector: FLASH sector to erase + * @param Sector FLASH sector to erase * The value of this parameter depend on device used within the same series - * @param VoltageRange: The device voltage range which defines the erase parallelism. + * @param VoltageRange The device voltage range which defines the erase parallelism. * This parameter can be one of the following values: * @arg FLASH_VOLTAGE_RANGE_1: when the device voltage range is 1.8V to 2.1V, * the operation will be done by byte (8-bit) @@ -716,7 +714,7 @@ FLASH->CR &= CR_PSIZE_MASK; FLASH->CR |= tmp_psize; FLASH->CR &= SECTOR_MASK; - FLASH->CR |= FLASH_CR_SER | (Sector << POSITION_VAL(FLASH_CR_SNB)); + FLASH->CR |= FLASH_CR_SER | (Sector << FLASH_CR_SNB_Pos); FLASH->CR |= FLASH_CR_STRT; /* Data synchronous Barrier (DSB) Just after the write operation @@ -736,27 +734,27 @@ /** * @brief Program the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY. - * @param Wwdg: Selects the IWDG mode + * @param Wwdg Selects the IWDG mode * This parameter can be one of the following values: * @arg OB_WWDG_SW: Software WWDG selected * @arg OB_WWDG_HW: Hardware WWDG selected - * @param Iwdg: Selects the WWDG mode + * @param Iwdg Selects the WWDG mode * This parameter can be one of the following values: * @arg OB_IWDG_SW: Software IWDG selected * @arg OB_IWDG_HW: Hardware IWDG selected - * @param Stop: Reset event when entering STOP mode. + * @param Stop Reset event when entering STOP mode. * This parameter can be one of the following values: * @arg OB_STOP_NO_RST: No reset generated when entering in STOP * @arg OB_STOP_RST: Reset generated when entering in STOP - * @param Stdby: Reset event when entering Standby mode. + * @param Stdby Reset event when entering Standby mode. * This parameter can be one of the following values: * @arg OB_STDBY_NO_RST: No reset generated when entering in STANDBY * @arg OB_STDBY_RST: Reset generated when entering in STANDBY - * @param Iwdgstop: Independent watchdog counter freeze in Stop mode. + * @param Iwdgstop Independent watchdog counter freeze in Stop mode. * This parameter can be one of the following values: * @arg OB_IWDG_STOP_FREEZE: Freeze IWDG counter in STOP * @arg OB_IWDG_STOP_ACTIVE: IWDG counter active in STOP - * @param Iwdgstdby: Independent watchdog counter freeze in standby mode. + * @param Iwdgstdby Independent watchdog counter freeze in standby mode. * This parameter can be one of the following values: * @arg OB_IWDG_STDBY_FREEZE: Freeze IWDG counter in STANDBY * @arg OB_IWDG_STDBY_ACTIVE: IWDG counter active in STANDBY @@ -814,7 +812,7 @@ * it is not possible to program or erase the flash sector i if CortexM7 * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 * - * @param WRPSector: specifies the sector(s) to be write protected. + * @param WRPSector specifies the sector(s) to be write protected. * This parameter can be one of the following values: * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7 (for STM32F74xxx/STM32F75xxx devices) * or a value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_11 (in Single Bank mode for STM32F76xxx/STM32F77xxx devices) @@ -849,7 +847,7 @@ * it is not possible to program or erase the flash sector i if CortexM4 * debug features are connected or boot code is executed in RAM, even if nWRPi = 1 * - * @param WRPSector: specifies the sector(s) to be write protected. + * @param WRPSector specifies the sector(s) to be write protected. * This parameter can be one of the following values: * @arg WRPSector: A value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_7 (for STM32F74xxx/STM32F75xxx devices) * or a value between OB_WRP_SECTOR_0 and OB_WRP_SECTOR_11 (in Single Bank mode for STM32F76xxx/STM32F77xxx devices) @@ -880,7 +878,7 @@ /** * @brief Set the read protection level. - * @param Level: specifies the read protection level. + * @param Level specifies the read protection level. * This parameter can be one of the following values: * @arg OB_RDP_LEVEL_0: No protection * @arg OB_RDP_LEVEL_1: Read protection of the memory @@ -910,7 +908,7 @@ /** * @brief Set the BOR Level. - * @param Level: specifies the Option Bytes BOR Reset Level. + * @param Level specifies the Option Bytes BOR Reset Level. * This parameter can be one of the following values: * @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V * @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V @@ -933,11 +931,11 @@ /** * @brief Configure Boot base address. * - * @param BootOption : specifies Boot base address depending from Boot pin = 0 or pin = 1 + * @param BootOption specifies Boot base address depending from Boot pin = 0 or pin = 1 * This parameter can be one of the following values: * @arg OPTIONBYTE_BOOTADDR_0 : Boot address based when Boot pin = 0 * @arg OPTIONBYTE_BOOTADDR_1 : Boot address based when Boot pin = 1 - * @param Address: specifies Boot base address + * @param Address specifies Boot base address * This parameter can be one of the following values: * @arg OB_BOOTADDR_ITCM_RAM : Boot from ITCM RAM (0x00000000) * @arg OB_BOOTADDR_SYSTEM : Boot from System memory bootloader (0x00100000) @@ -1019,7 +1017,7 @@ /** * @brief Configure Boot base address. * - * @param BootOption : specifies Boot base address depending from Boot pin = 0 or pin = 1 + * @param BootOption specifies Boot base address depending from Boot pin = 0 or pin = 1 * This parameter can be one of the following values: * @arg OPTIONBYTE_BOOTADDR_0 : Boot address based when Boot pin = 0 * @arg OPTIONBYTE_BOOTADDR_1 : Boot address based when Boot pin = 1 @@ -1053,7 +1051,7 @@ #if defined (FLASH_OPTCR2_PCROP) /** * @brief Set the PCROP protection for sectors. - * @param PCROPSector: specifies the sector(s) to be PCROP protected. + * @param PCROPSector specifies the sector(s) to be PCROP protected. * This parameter can be one of the following values: * @arg OB_PCROP_SECTOR_x: A value between OB_PCROP_SECTOR_0 and OB_PCROP_SECTOR_7 * @arg OB_PCROP_SECTOR_ALL @@ -1080,7 +1078,7 @@ /** * @brief Set the PCROP_RDP value - * @param Pcrop_Rdp: specifies the PCROP_RDP bit value. + * @param Pcrop_Rdp specifies the PCROP_RDP bit value. * * @retval HAL Status */
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_flash_ex.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_flash_ex.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_flash_ex.h * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief Header file of FLASH HAL Extension module. ****************************************************************************** * @attention @@ -480,7 +478,7 @@ /** * @brief Calculate the FLASH Boot Base Adress (BOOT_ADD0 or BOOT_ADD1) * @note Returned value BOOT_ADDx[15:0] corresponds to boot address [29:14]. - * @param __ADDRESS__: FLASH Boot Address (in the range 0x0000 0000 to 0x2004 FFFF with a granularity of 16KB) + * @param __ADDRESS__ FLASH Boot Address (in the range 0x0000 0000 to 0x2004 FFFF with a granularity of 16KB) * @retval The FLASH Boot Base Adress */ #define __HAL_FLASH_CALC_BOOT_BASE_ADR(__ADDRESS__) ((__ADDRESS__) >> 14)
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_gpio.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_gpio.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_gpio.c * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief GPIO HAL module driver. * This file provides firmware functions to manage the following * functionalities of the General Purpose Input/Output (GPIO) peripheral: @@ -179,8 +177,8 @@ /** * @brief Initializes the GPIOx peripheral according to the specified parameters in the GPIO_Init. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral. - * @param GPIO_Init: pointer to a GPIO_InitTypeDef structure that contains + * @param GPIOx where x can be (A..K) to select the GPIO peripheral. + * @param GPIO_Init pointer to a GPIO_InitTypeDef structure that contains * the configuration information for the specified GPIO peripheral. * @retval None */ @@ -304,8 +302,8 @@ /** * @brief De-initializes the GPIOx peripheral registers to their default reset values. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to be written. + * @param GPIOx where x can be (A..K) to select the GPIO peripheral. + * @param GPIO_Pin specifies the port bit to be written. * This parameter can be one of GPIO_PIN_x where x can be (0..15). * @retval None */ @@ -384,8 +382,8 @@ /** * @brief Reads the specified input port pin. - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to read. + * @param GPIOx where x can be (A..K) to select the GPIO peripheral. + * @param GPIO_Pin specifies the port bit to read. * This parameter can be GPIO_PIN_x where x can be (0..15). * @retval The input port pin value. */ @@ -414,10 +412,10 @@ * accesses. In this way, there is no risk of an IRQ occurring between * the read and the modify access. * - * @param GPIOx: where x can be (A..K) to select the GPIO peripheral. - * @param GPIO_Pin: specifies the port bit to be written. + * @param GPIOx where x can be (A..K) to select the GPIO peripheral. + * @param GPIO_Pin specifies the port bit to be written. * This parameter can be one of GPIO_PIN_x where x can be (0..15). - * @param PinState: specifies the value to be written to the selected bit. + * @param PinState specifies the value to be written to the selected bit. * This parameter can be one of the GPIO_PinState enum values: * @arg GPIO_PIN_RESET: to clear the port pin * @arg GPIO_PIN_SET: to set the port pin @@ -441,8 +439,8 @@ /** * @brief Toggles the specified GPIO pins. - * @param GPIOx: Where x can be (A..I) to select the GPIO peripheral. - * @param GPIO_Pin: Specifies the pins to be toggled. + * @param GPIOx Where x can be (A..I) to select the GPIO peripheral. + * @param GPIO_Pin Specifies the pins to be toggled. * @retval None */ void HAL_GPIO_TogglePin(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin) @@ -459,8 +457,8 @@ * GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH. * @note The configuration of the locked GPIO pins can no longer be modified * until the next reset. - * @param GPIOx: where x can be (A..F) to select the GPIO peripheral for STM32F7 family - * @param GPIO_Pin: specifies the port bit to be locked. + * @param GPIOx where x can be (A..F) to select the GPIO peripheral for STM32F7 family + * @param GPIO_Pin specifies the port bit to be locked. * This parameter can be any combination of GPIO_PIN_x where x can be (0..15). * @retval None */ @@ -494,7 +492,7 @@ /** * @brief This function handles EXTI interrupt request. - * @param GPIO_Pin: Specifies the pins connected EXTI line + * @param GPIO_Pin Specifies the pins connected EXTI line * @retval None */ void HAL_GPIO_EXTI_IRQHandler(uint16_t GPIO_Pin) @@ -509,7 +507,7 @@ /** * @brief EXTI line detection callbacks. - * @param GPIO_Pin: Specifies the pins connected EXTI line + * @param GPIO_Pin Specifies the pins connected EXTI line * @retval None */ __weak void HAL_GPIO_EXTI_Callback(uint16_t GPIO_Pin)
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_gpio.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_gpio.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_gpio.h * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief Header file of GPIO HAL module. ****************************************************************************** * @attention @@ -187,7 +185,7 @@ /** * @brief Checks whether the specified EXTI line flag is set or not. - * @param __EXTI_LINE__: specifies the EXTI line flag to check. + * @param __EXTI_LINE__ specifies the EXTI line flag to check. * This parameter can be GPIO_PIN_x where x can be(0..15) * @retval The new state of __EXTI_LINE__ (SET or RESET). */ @@ -195,7 +193,7 @@ /** * @brief Clears the EXTI's line pending flags. - * @param __EXTI_LINE__: specifies the EXTI lines flags to clear. + * @param __EXTI_LINE__ specifies the EXTI lines flags to clear. * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) * @retval None */ @@ -203,7 +201,7 @@ /** * @brief Checks whether the specified EXTI line is asserted or not. - * @param __EXTI_LINE__: specifies the EXTI line to check. + * @param __EXTI_LINE__ specifies the EXTI line to check. * This parameter can be GPIO_PIN_x where x can be(0..15) * @retval The new state of __EXTI_LINE__ (SET or RESET). */ @@ -211,7 +209,7 @@ /** * @brief Clears the EXTI's line pending bits. - * @param __EXTI_LINE__: specifies the EXTI lines to clear. + * @param __EXTI_LINE__ specifies the EXTI lines to clear. * This parameter can be any combination of GPIO_PIN_x where x can be (0..15) * @retval None */ @@ -219,7 +217,7 @@ /** * @brief Generates a Software interrupt on selected EXTI line. - * @param __EXTI_LINE__: specifies the EXTI line to check. + * @param __EXTI_LINE__ specifies the EXTI line to check. * This parameter can be GPIO_PIN_x where x can be(0..15) * @retval None */
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_gpio_ex.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_gpio_ex.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_gpio_ex.h
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief Header file of GPIO HAL Extension module.
******************************************************************************
* @attention
@@ -397,7 +395,7 @@
#define GPIOI_PIN_AVAILABLE GPIO_PIN_All
#define GPIOJ_PIN_AVAILABLE GPIO_PIN_All
#define GPIOH_PIN_AVAILABLE GPIO_PIN_All
-#define GPIOK_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_3 | GPIO_PIN_4 | \
+#define GPIOK_PIN_AVAILABLE (GPIO_PIN_0 | GPIO_PIN_1 | GPIO_PIN_2 | GPIO_PIN_3 | GPIO_PIN_4 | \
GPIO_PIN_5 | GPIO_PIN_6 | GPIO_PIN_7)
/**
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hash.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hash.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_hash.c
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief HASH HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the HASH peripheral:
@@ -133,7 +131,7 @@
/**
* @brief DMA HASH Input Data complete callback.
- * @param hdma: DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void HASH_DMAXferCplt(DMA_HandleTypeDef *hdma)
@@ -205,7 +203,7 @@
/**
* @brief DMA HASH communication error callback.
- * @param hdma: DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void HASH_DMAError(DMA_HandleTypeDef *hdma)
@@ -217,8 +215,8 @@
/**
* @brief Writes the input buffer in data register.
- * @param pInBuffer: Pointer to input buffer
- * @param Size: The size of input buffer
+ * @param pInBuffer Pointer to input buffer
+ * @param Size The size of input buffer
* @retval None
*/
static void HASH_WriteData(uint8_t *pInBuffer, uint32_t Size)
@@ -235,8 +233,8 @@
/**
* @brief Provides the message digest result.
- * @param pMsgDigest: Pointer to the message digest
- * @param Size: The size of the message digest in bytes
+ * @param pMsgDigest Pointer to the message digest
+ * @param Size The size of the message digest in bytes
* @retval None
*/
static void HASH_GetDigest(uint8_t *pMsgDigest, uint8_t Size)
@@ -337,7 +335,7 @@
/**
* @brief Initializes the HASH according to the specified parameters in the
HASH_HandleTypeDef and creates the associated handle.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @retval HAL status
*/
@@ -384,7 +382,7 @@
/**
* @brief DeInitializes the HASH peripheral.
* @note This API must be called before starting a new processing.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @retval HAL status
*/
@@ -422,7 +420,7 @@
/**
* @brief Initializes the HASH MSP.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @retval None
*/
@@ -438,7 +436,7 @@
/**
* @brief DeInitializes HASH MSP.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @retval None
*/
@@ -454,7 +452,7 @@
/**
* @brief Input data transfer complete callback.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @retval None
*/
@@ -470,7 +468,7 @@
/**
* @brief Data transfer Error callback.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @retval None
*/
@@ -487,7 +485,7 @@
/**
* @brief Digest computation complete callback. It is used only with interrupt.
* @note This callback is not relevant with DMA.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @retval None
*/
@@ -524,15 +522,15 @@
/**
* @brief Initializes the HASH peripheral in MD5 mode then processes pInBuffer.
The digest is available in pOutBuffer.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
* If the Size is multiple of 64 bytes, appending the input buffer is possible.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware
* and appending the input buffer is no more possible.
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes.
- * @param Timeout: Timeout value
+ * @param pOutBuffer Pointer to the computed digest. Its size must be 16 bytes.
+ * @param Timeout Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
@@ -601,10 +599,10 @@
/**
* @brief Initializes the HASH peripheral in MD5 mode then writes the pInBuffer.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
* If the Size is multiple of 64 bytes, appending the input buffer is possible.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware
* and appending the input buffer is no more possible.
@@ -648,13 +646,13 @@
/**
* @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
The digest is available in pOutBuffer.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
- * @param Timeout: Timeout value
+ * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.
+ * @param Timeout Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
@@ -723,10 +721,10 @@
/**
* @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
* @note Input buffer size in bytes must be a multiple of 4 otherwise the digest computation is corrupted.
* @retval HAL status
@@ -792,12 +790,12 @@
/**
* @brief Initializes the HASH peripheral in MD5 mode then processes pInBuffer.
* The digest is available in pOutBuffer.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes.
+ * @param pOutBuffer Pointer to the computed digest. Its size must be 16 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_MD5_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
@@ -954,12 +952,12 @@
/**
* @brief Initializes the HASH peripheral in SHA1 mode then processes pInBuffer.
* The digest is available in pOutBuffer.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
+ * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_SHA1_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
@@ -1114,7 +1112,7 @@
/**
* @brief This function handles HASH interrupt request.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @retval None
*/
@@ -1158,10 +1156,10 @@
/**
* @brief Initializes the HASH peripheral in MD5 mode then enables DMA to
control data transfer. Use HAL_HASH_MD5_Finish() to get the digest.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
* @retval HAL status
*/
@@ -1209,10 +1207,10 @@
/**
* @brief Returns the computed digest in MD5 mode
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 16 bytes.
- * @param Timeout: Timeout value
+ * @param pOutBuffer Pointer to the computed digest. Its size must be 16 bytes.
+ * @param Timeout Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_MD5_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
@@ -1262,10 +1260,10 @@
/**
* @brief Initializes the HASH peripheral in SHA1 mode then enables DMA to
control data transfer. Use HAL_HASH_SHA1_Finish() to get the digest.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
* @retval HAL status
*/
@@ -1314,10 +1312,10 @@
/**
* @brief Returns the computed digest in SHA1 mode.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
- * @param Timeout: Timeout value
+ * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.
+ * @param Timeout Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASH_SHA1_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
@@ -1387,13 +1385,13 @@
/**
* @brief Initializes the HASH peripheral in HMAC MD5 mode
* then processes pInBuffer. The digest is available in pOutBuffer
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
- * @param Timeout: Timeout value
+ * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.
+ * @param Timeout Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMAC_MD5_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
@@ -1532,13 +1530,13 @@
/**
* @brief Initializes the HASH peripheral in HMAC SHA1 mode
* then processes pInBuffer. The digest is available in pOutBuffer.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
- * @param Timeout: Timeout value
+ * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.
+ * @param Timeout Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMAC_SHA1_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
@@ -1696,10 +1694,10 @@
/**
* @brief Initializes the HASH peripheral in HMAC MD5 mode
* then enables DMA to control data transfer.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
* @retval HAL status
*/
@@ -1763,10 +1761,10 @@
/**
* @brief Initializes the HASH peripheral in HMAC SHA1 mode
* then enables DMA to control data transfer.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
* @retval HAL status
*/
@@ -1847,7 +1845,7 @@
/**
* @brief return the HASH state
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @retval HAL state
*/
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hash.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hash.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_hash.h
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief Header file of HASH HAL module.
******************************************************************************
* @attention
@@ -225,13 +223,13 @@
*/
/** @brief Reset HASH handle state
- * @param __HANDLE__: specifies the HASH handle.
+ * @param __HANDLE__ specifies the HASH handle.
* @retval None
*/
#define __HAL_HASH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_HASH_STATE_RESET)
/** @brief Check whether the specified HASH flag is set or not.
- * @param __FLAG__: specifies the flag to check.
+ * @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg HASH_FLAG_DINIS: A new block can be entered into the input buffer.
* @arg HASH_FLAG_DCIS: Digest calculation complete
@@ -264,7 +262,7 @@
/**
* @brief Set the number of valid bits in last word written in Data register
- * @param SIZE: size in byte of last data written in Data register.
+ * @param SIZE size in byte of last data written in Data register.
* @retval None
*/
#define __HAL_HASH_SET_NBVALIDBITS(SIZE) do{HASH->STR &= ~(HASH_STR_NBW);\
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hash_ex.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hash_ex.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_hash_ex.c
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief HASH HAL Extension module driver.
* This file provides firmware functions to manage the following
* functionalities of HASH peripheral:
@@ -131,8 +129,8 @@
/**
* @brief Writes the input buffer in data register.
- * @param pInBuffer: Pointer to input buffer
- * @param Size: The size of input buffer
+ * @param pInBuffer Pointer to input buffer
+ * @param Size The size of input buffer
* @retval None
*/
static void HASHEx_WriteData(uint8_t *pInBuffer, uint32_t Size)
@@ -149,8 +147,8 @@
/**
* @brief Provides the message digest result.
- * @param pMsgDigest: Pointer to the message digest
- * @param Size: The size of the message digest in bytes
+ * @param pMsgDigest Pointer to the message digest
+ * @param Size The size of the message digest in bytes
* @retval None
*/
static void HASHEx_GetDigest(uint8_t *pMsgDigest, uint8_t Size)
@@ -222,7 +220,7 @@
/**
* @brief DMA HASH Input Data complete callback.
- * @param hdma: DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void HASHEx_DMAXferCplt(DMA_HandleTypeDef *hdma)
@@ -294,7 +292,7 @@
/**
* @brief DMA HASH communication error callback.
- * @param hdma: DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void HASHEx_DMAError(DMA_HandleTypeDef *hdma)
@@ -332,13 +330,13 @@
/**
* @brief Initializes the HASH peripheral in SHA224 mode
* then processes pInBuffer. The digest is available in pOutBuffer
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 28 bytes.
- * @param Timeout: Specify Timeout value
+ * @param pOutBuffer Pointer to the computed digest. Its size must be 28 bytes.
+ * @param Timeout Specify Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
@@ -408,13 +406,13 @@
/**
* @brief Initializes the HASH peripheral in SHA256 mode then processes pInBuffer.
The digest is available in pOutBuffer.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 32 bytes.
- * @param Timeout: Specify Timeout value
+ * @param pOutBuffer Pointer to the computed digest. Its size must be 32 bytes.
+ * @param Timeout Specify Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
@@ -485,10 +483,10 @@
/**
* @brief Initializes the HASH peripheral in SHA224 mode
* then processes pInBuffer. The digest is available in pOutBuffer
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
* @retval HAL status
*/
@@ -531,10 +529,10 @@
/**
* @brief Initializes the HASH peripheral in SHA256 mode then processes pInBuffer.
The digest is available in pOutBuffer.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
* @retval HAL status
*/
@@ -597,13 +595,13 @@
/**
* @brief Initializes the HASH peripheral in HMAC SHA224 mode
* then processes pInBuffer. The digest is available in pOutBuffer.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
- * @param Timeout: Timeout value
+ * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.
+ * @param Timeout Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA224_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
@@ -741,13 +739,13 @@
/**
* @brief Initializes the HASH peripheral in HMAC SHA256 mode
* then processes pInBuffer. The digest is available in pOutBuffer
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
- * @param Timeout: Timeout value
+ * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.
+ * @param Timeout Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HMACEx_SHA256_Start(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer, uint32_t Timeout)
@@ -908,12 +906,12 @@
/**
* @brief Initializes the HASH peripheral in SHA224 mode then processes pInBuffer.
* The digest is available in pOutBuffer.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
+ * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
@@ -1056,12 +1054,12 @@
/**
* @brief Initializes the HASH peripheral in SHA256 mode then processes pInBuffer.
* The digest is available in pOutBuffer.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 20 bytes.
+ * @param pOutBuffer Pointer to the computed digest. Its size must be 20 bytes.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Start_IT(HASH_HandleTypeDef *hhash, uint8_t *pInBuffer, uint32_t Size, uint8_t* pOutBuffer)
@@ -1207,7 +1205,7 @@
/**
* @brief This function handles HASH interrupt request.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
* @retval None
*/
@@ -1253,10 +1251,10 @@
/**
* @brief Initializes the HASH peripheral in SHA224 mode then enables DMA to
control data transfer. Use HAL_HASH_SHA224_Finish() to get the digest.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
* @retval HAL status
*/
@@ -1304,10 +1302,10 @@
/**
* @brief Returns the computed digest in SHA224
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 28 bytes.
- * @param Timeout: Timeout value
+ * @param pOutBuffer Pointer to the computed digest. Its size must be 28 bytes.
+ * @param Timeout Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA224_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
@@ -1357,10 +1355,10 @@
/**
* @brief Initializes the HASH peripheral in SHA256 mode then enables DMA to
control data transfer. Use HAL_HASH_SHA256_Finish() to get the digest.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
* @retval HAL status
*/
@@ -1408,10 +1406,10 @@
/**
* @brief Returns the computed digest in SHA256.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pOutBuffer: Pointer to the computed digest. Its size must be 32 bytes.
- * @param Timeout: Timeout value
+ * @param pOutBuffer Pointer to the computed digest. Its size must be 32 bytes.
+ * @param Timeout Timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HASHEx_SHA256_Finish(HASH_HandleTypeDef *hhash, uint8_t* pOutBuffer, uint32_t Timeout)
@@ -1481,10 +1479,10 @@
/**
* @brief Initializes the HASH peripheral in HMAC SHA224 mode
* then enables DMA to control data transfer.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
* @retval HAL status
*/
@@ -1548,10 +1546,10 @@
/**
* @brief Initializes the HASH peripheral in HMAC SHA256 mode
* then enables DMA to control data transfer.
- * @param hhash: pointer to a HASH_HandleTypeDef structure that contains
+ * @param hhash pointer to a HASH_HandleTypeDef structure that contains
* the configuration information for HASH module
- * @param pInBuffer: Pointer to the input buffer (buffer to be hashed).
- * @param Size: Length of the input buffer in bytes.
+ * @param pInBuffer Pointer to the input buffer (buffer to be hashed).
+ * @param Size Length of the input buffer in bytes.
* If the Size is not multiple of 64 bytes, the padding is managed by hardware.
* @retval HAL status
*/
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hash_ex.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hash_ex.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_hash_ex.h * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief Header file of HASH HAL Extension module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hcd.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hcd.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,16 +2,14 @@
******************************************************************************
* @file stm32f7xx_hal_hcd.c
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief HCD HAL module driver.
- * This file provides firmware functions to manage the following
+ * This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
* + Initialization and de-initialization functions
* + IO operation functions
- * + Peripheral Control functions
+ * + Peripheral Control functions
* + Peripheral State functions
- *
+ *
@verbatim
==============================================================================
##### How to use this driver #####
@@ -19,21 +17,21 @@
[..]
(#)Declare a HCD_HandleTypeDef handle structure, for example:
HCD_HandleTypeDef hhcd;
-
+
(#)Fill parameters of Init structure in HCD handle
-
- (#)Call HAL_HCD_Init() API to initialize the HCD peripheral (Core, Host core, ...)
+
+ (#)Call HAL_HCD_Init() API to initialize the HCD peripheral (Core, Host core, ...)
(#)Initialize the HCD low level resources through the HAL_HCD_MspInit() API:
(##) Enable the HCD/USB Low Level interface clock using the following macros
(+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
(+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode)
(+++) __HAL_RCC_USB_OTG_HS_ULPI_CLK_ENABLE(); (For High Speed Mode)
-
+
(##) Initialize the related GPIO clocks
(##) Configure HCD pin-out
(##) Configure HCD NVIC interrupt
-
+
(#)Associate the Upper USB Host stack to the HAL HCD Driver:
(##) hhcd.pData = phost;
@@ -69,7 +67,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
- */
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
@@ -78,7 +76,7 @@
* @{
*/
-/** @defgroup HCD HCD
+/** @defgroup HCD HCD
* @brief HCD HAL module driver
* @{
*/
@@ -94,7 +92,7 @@
* @{
*/
static void HCD_HC_IN_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum);
-static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum);
+static void HCD_HC_OUT_IRQHandler(HCD_HandleTypeDef *hhcd, uint8_t chnum);
static void HCD_RXQLVL_IRQHandler(HCD_HandleTypeDef *hhcd);
static void HCD_Port_IRQHandler(HCD_HandleTypeDef *hhcd);
/**
@@ -106,82 +104,82 @@
* @{
*/
-/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
+/** @defgroup HCD_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
*
-@verbatim
+@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..] This section provides functions allowing to:
-
+
@endverbatim
* @{
*/
/**
* @brief Initialize the host driver.
- * @param hhcd: HCD handle
+ * @param hhcd HCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd)
-{
+{
/* Check the HCD handle allocation */
if(hhcd == NULL)
{
return HAL_ERROR;
}
-
+
/* Check the parameters */
assert_param(IS_HCD_ALL_INSTANCE(hhcd->Instance));
hhcd->State = HAL_HCD_STATE_BUSY;
-
+
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_HCD_MspInit(hhcd);
/* Disable the Interrupts */
__HAL_HCD_DISABLE(hhcd);
-
+
/*Init the Core (common init.) */
USB_CoreInit(hhcd->Instance, hhcd->Init);
-
+
/* Force Host Mode*/
USB_SetCurrentMode(hhcd->Instance , USB_OTG_HOST_MODE);
-
+
/* Init Host */
USB_HostInit(hhcd->Instance, hhcd->Init);
-
+
hhcd->State= HAL_HCD_STATE_READY;
-
+
return HAL_OK;
}
/**
* @brief Initialize a host channel.
- * @param hhcd: HCD handle
- * @param ch_num: Channel number.
+ * @param hhcd HCD handle
+ * @param ch_num Channel number.
* This parameter can be a value from 1 to 15
- * @param epnum: Endpoint number.
+ * @param epnum Endpoint number.
* This parameter can be a value from 1 to 15
- * @param dev_address : Current device address
+ * @param dev_address Current device address
* This parameter can be a value from 0 to 255
- * @param speed: Current device speed.
+ * @param speed Current device speed.
* This parameter can be one of these values:
* HCD_SPEED_HIGH: High speed mode,
* HCD_SPEED_FULL: Full speed mode,
* HCD_SPEED_LOW: Low speed mode
- * @param ep_type: Endpoint Type.
+ * @param ep_type Endpoint Type.
* This parameter can be one of these values:
* EP_TYPE_CTRL: Control type,
* EP_TYPE_ISOC: Isochronous type,
* EP_TYPE_BULK: Bulk type,
* EP_TYPE_INTR: Interrupt type
- * @param mps: Max Packet Size.
+ * @param mps Max Packet Size.
* This parameter can be a value from 0 to32K
* @retval HAL status
*/
-HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
+HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
uint8_t ch_num,
uint8_t epnum,
uint8_t dev_address,
@@ -190,9 +188,9 @@
uint16_t mps)
{
HAL_StatusTypeDef status = HAL_OK;
-
- __HAL_LOCK(hhcd);
-
+
+ __HAL_LOCK(hhcd);
+ hhcd->hc[ch_num].do_ping = 0;
hhcd->hc[ch_num].dev_addr = dev_address;
hhcd->hc[ch_num].max_packet = mps;
hhcd->hc[ch_num].ch_num = ch_num;
@@ -200,43 +198,44 @@
hhcd->hc[ch_num].ep_num = epnum & 0x7F;
hhcd->hc[ch_num].ep_is_in = ((epnum & 0x80) == 0x80);
hhcd->hc[ch_num].speed = speed;
- /* reset to 0 */
+
+ // MBED: added
hhcd->hc[ch_num].toggle_out = 0;
hhcd->hc[ch_num].toggle_in = 0;
- status = USB_HC_Init(hhcd->Instance,
+ status = USB_HC_Init(hhcd->Instance,
ch_num,
epnum,
dev_address,
speed,
ep_type,
mps);
- __HAL_UNLOCK(hhcd);
-
+ __HAL_UNLOCK(hhcd);
+
return status;
}
/**
* @brief Halt a host channel.
- * @param hhcd: HCD handle
- * @param ch_num: Channel number.
+ * @param hhcd HCD handle
+ * @param ch_num Channel number.
* This parameter can be a value from 1 to 15
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_HC_Halt(HCD_HandleTypeDef *hhcd, uint8_t ch_num)
{
HAL_StatusTypeDef status = HAL_OK;
-
- __HAL_LOCK(hhcd);
- USB_HC_Halt(hhcd->Instance, ch_num);
+
+ __HAL_LOCK(hhcd);
+ USB_HC_Halt(hhcd->Instance, ch_num);
__HAL_UNLOCK(hhcd);
-
+
return status;
}
/**
* @brief DeInitialize the host driver.
- * @param hhcd: HCD handle
+ * @param hhcd HCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_DeInit(HCD_HandleTypeDef *hhcd)
@@ -246,29 +245,29 @@
{
return HAL_ERROR;
}
-
+
hhcd->State = HAL_HCD_STATE_BUSY;
-
+
/* DeInit the low level hardware */
HAL_HCD_MspDeInit(hhcd);
-
+
__HAL_HCD_DISABLE(hhcd);
-
- hhcd->State = HAL_HCD_STATE_RESET;
-
+
+ hhcd->State = HAL_HCD_STATE_RESET;
+
return HAL_OK;
}
/**
* @brief Initialize the HCD MSP.
- * @param hhcd: HCD handle
+ * @param hhcd HCD handle
* @retval None
*/
__weak void HAL_HCD_MspInit(HCD_HandleTypeDef *hhcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hhcd);
-
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_HCD_MspInit could be implemented in the user file
*/
@@ -276,14 +275,14 @@
/**
* @brief DeInitialize the HCD MSP.
- * @param hhcd: HCD handle
+ * @param hhcd HCD handle
* @retval None
*/
__weak void HAL_HCD_MspDeInit(HCD_HandleTypeDef *hhcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hhcd);
-
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_HCD_MspDeInit could be implemented in the user file
*/
@@ -300,46 +299,47 @@
===============================================================================
##### IO operation functions #####
===============================================================================
- [..] This subsection provides a set of functions allowing to manage the USB Host Data
+ [..] This subsection provides a set of functions allowing to manage the USB Host Data
Transfer
-
+
@endverbatim
* @{
*/
-
-/**
- * @brief Submit a new URB for processing.
- * @param hhcd: HCD handle
- * @param ch_num: Channel number.
+
+/**
+ * @brief Submit a new URB for processing.
+ * @param hhcd HCD handle
+ * @param ch_num Channel number.
* This parameter can be a value from 1 to 15
- * @param direction: Channel number.
+ * @param direction Channel number.
* This parameter can be one of these values:
* 0 : Output / 1 : Input
- * @param ep_type: Endpoint Type.
+ * @param ep_type Endpoint Type.
* This parameter can be one of these values:
* EP_TYPE_CTRL: Control type/
* EP_TYPE_ISOC: Isochronous type/
* EP_TYPE_BULK: Bulk type/
* EP_TYPE_INTR: Interrupt type/
- * @param token: Endpoint Type.
+ * @param token Endpoint Type.
* This parameter can be one of these values:
* 0: HC_PID_SETUP / 1: HC_PID_DATA1
- * @param pbuff: pointer to URB data
- * @param length: Length of URB data
- * @param do_ping: activate do ping protocol (for high speed only).
+ * @param pbuff pointer to URB data
+ * @param length Length of URB data
+ * @param do_ping activate do ping protocol (for high speed only).
* This parameter can be one of these values:
- * 0 : do ping inactive / 1 : do ping active
+ * 0 : do ping inactive / 1 : do ping active
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
- uint8_t ch_num,
+ uint8_t ch_num,
uint8_t direction ,
- uint8_t ep_type,
- uint8_t token,
- uint8_t* pbuff,
+ uint8_t ep_type,
+ uint8_t token,
+ uint8_t* pbuff,
uint16_t length,
- uint8_t do_ping)
+ uint8_t do_ping)
{
+ // MBED: added
if ((hhcd->hc[ch_num].ep_is_in != direction)) {
if ((hhcd->hc[ch_num].ep_type == EP_TYPE_CTRL)){
/* reconfigure the endpoint !!! from tx -> rx, and rx ->tx */
@@ -359,6 +359,7 @@
if (direction == 1) hhcd->hc[ch_num].toggle_in=1;
}
}
+
hhcd->hc[ch_num].ep_type = ep_type;
if(token == 0)
@@ -384,17 +385,14 @@
/* Set the Data Toggle bit as per the Flag */
if ( hhcd->hc[ch_num].toggle_out == 0)
{ /* Put the PID 0 */
- hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
}
else
{ /* Put the PID 1 */
- hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ;
- }
- if(hhcd->hc[ch_num].urb_state != URB_NOTREADY)
- {
- hhcd->hc[ch_num].do_ping = do_ping;
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
}
}
+ // MBED: added
else if ((token == 1) && (direction == 1))
{
if( hhcd->hc[ch_num].toggle_in == 0)
@@ -415,15 +413,11 @@
/* Set the Data Toggle bit as per the Flag */
if ( hhcd->hc[ch_num].toggle_out == 0)
{ /* Put the PID 0 */
- hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
}
else
{ /* Put the PID 1 */
- hhcd->hc[ch_num].data_pid = HC_PID_DATA1 ;
- }
- if(hhcd->hc[ch_num].urb_state != URB_NOTREADY)
- {
- hhcd->hc[ch_num].do_ping = do_ping;
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA1;
}
}
else
@@ -445,7 +439,7 @@
/* Set the Data Toggle bit as per the Flag */
if ( hhcd->hc[ch_num].toggle_out == 0)
{ /* Put the PID 0 */
- hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
+ hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
}
else
{ /* Put the PID 1 */
@@ -464,47 +458,47 @@
}
}
break;
-
- case EP_TYPE_ISOC:
+
+ case EP_TYPE_ISOC:
hhcd->hc[ch_num].data_pid = HC_PID_DATA0;
- break;
+ break;
}
-
+
hhcd->hc[ch_num].xfer_buff = pbuff;
hhcd->hc[ch_num].xfer_len = length;
- hhcd->hc[ch_num].urb_state = URB_IDLE;
+ hhcd->hc[ch_num].urb_state = URB_IDLE;
hhcd->hc[ch_num].xfer_count = 0 ;
hhcd->hc[ch_num].ch_num = ch_num;
hhcd->hc[ch_num].state = HC_IDLE;
-
+
return USB_HC_StartXfer(hhcd->Instance, &(hhcd->hc[ch_num]), hhcd->Init.dma_enable);
}
/**
* @brief Handle HCD interrupt request.
- * @param hhcd: HCD handle
+ * @param hhcd HCD handle
* @retval None
*/
void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd)
{
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
uint32_t i = 0 , interrupt = 0;
-
+
/* ensure that we are in device mode */
if (USB_GetMode(hhcd->Instance) == USB_OTG_MODE_HOST)
{
/* avoid spurious interrupt */
- if(__HAL_HCD_IS_INVALID_INTERRUPT(hhcd))
+ if(__HAL_HCD_IS_INVALID_INTERRUPT(hhcd))
{
return;
}
-
+
if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
{
/* incorrect mode, acknowledge the interrupt */
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
}
-
+
if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_IISOIXFR))
{
/* incorrect mode, acknowledge the interrupt */
@@ -515,41 +509,41 @@
{
/* incorrect mode, acknowledge the interrupt */
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_PTXFE);
- }
-
+ }
+
if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_MMIS))
{
/* incorrect mode, acknowledge the interrupt */
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_MMIS);
- }
-
+ }
+
/* Handle Host Disconnect Interrupts */
if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT))
{
-
+
/* Cleanup HPRT */
USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
-
+
/* Handle Host Port Interrupts */
HAL_HCD_Disconnect_Callback(hhcd);
USB_InitFSLSPClkSel(hhcd->Instance ,HCFG_48_MHZ );
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_DISCINT);
}
-
+
/* Handle Host Port Interrupts */
if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HPRTINT))
{
HCD_Port_IRQHandler (hhcd);
}
-
+
/* Handle Host SOF Interrupts */
if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_SOF))
{
HAL_HCD_SOF_Callback(hhcd);
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_SOF);
}
-
+
/* Handle Host channel Interrupts */
if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_HCINT))
{
@@ -569,15 +563,15 @@
}
}
__HAL_HCD_CLEAR_FLAG(hhcd, USB_OTG_GINTSTS_HCINT);
- }
-
+ }
+
/* Handle Rx Queue Level Interrupts */
if(__HAL_HCD_GET_FLAG(hhcd, USB_OTG_GINTSTS_RXFLVL))
{
USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
-
+
HCD_RXQLVL_IRQHandler (hhcd);
-
+
USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_RXFLVL);
}
}
@@ -585,14 +579,14 @@
/**
* @brief SOF callback.
- * @param hhcd: HCD handle
+ * @param hhcd HCD handle
* @retval None
*/
__weak void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hhcd);
-
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_HCD_SOF_Callback could be implemented in the user file
*/
@@ -600,14 +594,14 @@
/**
* @brief Connection Event callback.
- * @param hhcd: HCD handle
+ * @param hhcd HCD handle
* @retval None
*/
__weak void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hhcd);
-
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_HCD_Connect_Callback could be implemented in the user file
*/
@@ -615,39 +609,67 @@
/**
* @brief Disconnection Event callback.
- * @param hhcd: HCD handle
+ * @param hhcd HCD handle
* @retval None
*/
__weak void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hhcd);
-
+
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_HCD_Disconnect_Callback could be implemented in the user file
+ */
+}
+
+/**
+ * @brief Port Enabled Event callback.
+ * @param hhcd: HCD handle
+ * @retval None
+ */
+__weak void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhcd);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_HCD_Disconnect_Callback could be implemented in the user file
*/
-}
+}
+
+/**
+ * @brief Port Disabled Event callback.
+ * @param hhcd: HCD handle
+ * @retval None
+ */
+__weak void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd)
+{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(hhcd);
+ /* NOTE : This function Should not be modified, when the callback is needed,
+ the HAL_HCD_Disconnect_Callback could be implemented in the user file
+ */
+}
/**
* @brief Notify URB state change callback.
- * @param hhcd: HCD handle
- * @param chnum: Channel number.
+ * @param hhcd HCD handle
+ * @param chnum Channel number.
* This parameter can be a value from 1 to 15
* @param urb_state:
* This parameter can be one of these values:
* URB_IDLE/
* URB_DONE/
* URB_NOTREADY/
- * URB_NYET/
- * URB_ERROR/
- * URB_STALL/
+ * URB_NYET/
+ * URB_ERROR/
+ * URB_STALL/
* @retval None
*/
__weak void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd, uint8_t chnum, HCD_URBStateTypeDef urb_state)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hhcd);
-
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_HCD_HC_NotifyURBChange_Callback could be implemented in the user file
*/
@@ -657,15 +679,15 @@
* @}
*/
-/** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions
- * @brief Management functions
+/** @defgroup HCD_Exported_Functions_Group3 Peripheral Control functions
+ * @brief Management functions
*
-@verbatim
+@verbatim
===============================================================================
##### Peripheral Control functions #####
- ===============================================================================
+ ===============================================================================
[..]
- This subsection provides a set of functions allowing to control the HCD data
+ This subsection provides a set of functions allowing to control the HCD data
transfers.
@endverbatim
@@ -674,35 +696,35 @@
/**
* @brief Start the host driver.
- * @param hhcd: HCD handle
+ * @param hhcd HCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_Start(HCD_HandleTypeDef *hhcd)
-{
- __HAL_LOCK(hhcd);
+{
+ __HAL_LOCK(hhcd);
__HAL_HCD_ENABLE(hhcd);
- USB_DriveVbus(hhcd->Instance, 1);
- __HAL_UNLOCK(hhcd);
+ USB_DriveVbus(hhcd->Instance, 1);
+ __HAL_UNLOCK(hhcd);
return HAL_OK;
}
/**
* @brief Stop the host driver.
- * @param hhcd: HCD handle
+ * @param hhcd HCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_Stop(HCD_HandleTypeDef *hhcd)
-{
- __HAL_LOCK(hhcd);
+{
+ __HAL_LOCK(hhcd);
USB_StopHost(hhcd->Instance);
- __HAL_UNLOCK(hhcd);
+ __HAL_UNLOCK(hhcd);
return HAL_OK;
}
/**
* @brief Reset the host port.
- * @param hhcd: HCD handle
+ * @param hhcd HCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_HCD_ResetPort(HCD_HandleTypeDef *hhcd)
@@ -714,15 +736,15 @@
* @}
*/
-/** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions
- * @brief Peripheral State functions
+/** @defgroup HCD_Exported_Functions_Group4 Peripheral State functions
+ * @brief Peripheral State functions
*
-@verbatim
+@verbatim
===============================================================================
##### Peripheral State functions #####
- ===============================================================================
+ ===============================================================================
[..]
- This subsection permits to get in run-time the status of the peripheral
+ This subsection permits to get in run-time the status of the peripheral
and the data flow.
@endverbatim
@@ -731,7 +753,7 @@
/**
* @brief Return the HCD handle state.
- * @param hhcd: HCD handle
+ * @param hhcd HCD handle
* @retval HAL state
*/
HCD_StateTypeDef HAL_HCD_GetState(HCD_HandleTypeDef *hhcd)
@@ -741,16 +763,16 @@
/**
* @brief Return URB state for a channel.
- * @param hhcd: HCD handle
- * @param chnum: Channel number.
+ * @param hhcd HCD handle
+ * @param chnum Channel number.
* This parameter can be a value from 1 to 15
* @retval URB state.
* This parameter can be one of these values:
* URB_IDLE/
* URB_DONE/
* URB_NOTREADY/
- * URB_NYET/
- * URB_ERROR/
+ * URB_NYET/
+ * URB_ERROR/
* URB_STALL
*/
HCD_URBStateTypeDef HAL_HCD_HC_GetURBState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
@@ -761,32 +783,32 @@
/**
* @brief Return the last host transfer size.
- * @param hhcd: HCD handle
- * @param chnum: Channel number.
+ * @param hhcd HCD handle
+ * @param chnum Channel number.
* This parameter can be a value from 1 to 15
* @retval last transfer size in byte
*/
uint32_t HAL_HCD_HC_GetXferCount(HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
- return hhcd->hc[chnum].xfer_count;
+ return hhcd->hc[chnum].xfer_count;
}
-
+
/**
* @brief Return the Host Channel state.
- * @param hhcd: HCD handle
- * @param chnum: Channel number.
+ * @param hhcd HCD handle
+ * @param chnum Channel number.
* This parameter can be a value from 1 to 15
* @retval Host channel state
* This parameter can be one of these values:
* HC_IDLE/
* HC_XFRC/
* HC_HALTED/
- * HC_NYET/
- * HC_NAK/
- * HC_STALL/
- * HC_XACTERR/
- * HC_BBLERR/
- * HC_DATATGLERR
+ * HC_NYET/
+ * HC_NAK/
+ * HC_STALL/
+ * HC_XACTERR/
+ * HC_BBLERR/
+ * HC_DATATGLERR
*/
HCD_HCStateTypeDef HAL_HCD_HC_GetState(HCD_HandleTypeDef *hhcd, uint8_t chnum)
{
@@ -795,7 +817,7 @@
/**
* @brief Return the current Host frame number.
- * @param hhcd: HCD handle
+ * @param hhcd HCD handle
* @retval Current Host frame number
*/
uint32_t HAL_HCD_GetCurrentFrame(HCD_HandleTypeDef *hhcd)
@@ -805,7 +827,7 @@
/**
* @brief Return the Host enumeration speed.
- * @param hhcd: HCD handle
+ * @param hhcd HCD handle
* @retval Enumeration speed
*/
uint32_t HAL_HCD_GetCurrentSpeed(HCD_HandleTypeDef *hhcd)
@@ -826,8 +848,8 @@
*/
/**
* @brief Handle Host Channel IN interrupt requests.
- * @param hhcd: HCD handle
- * @param chnum: Channel number.
+ * @param hhcd HCD handle
+ * @param chnum Channel number.
* This parameter can be a value from 1 to 15
* @retval none
*/
@@ -835,92 +857,92 @@
{
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
uint32_t tmpreg = 0;
-
+
if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_AHBERR)
{
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR);
__HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- }
+ }
else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_ACK)
{
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);
}
-
- else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_STALL)
+
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_STALL)
{
__HAL_HCD_UNMASK_HALT_HC_INT(chnum);
hhcd->hc[chnum].state = HC_STALL;
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL);
- USB_HC_Halt(hhcd->Instance, chnum);
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL);
+ USB_HC_Halt(hhcd->Instance, chnum);
}
else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_DTERR)
{
__HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- USB_HC_Halt(hhcd->Instance, chnum);
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
+ USB_HC_Halt(hhcd->Instance, chnum);
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
hhcd->hc[chnum].state = HC_DATATGLERR;
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR);
- }
-
+ }
+
if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_FRMOR)
{
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- USB_HC_Halt(hhcd->Instance, chnum);
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+ USB_HC_Halt(hhcd->Instance, chnum);
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR);
}
-
+
else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_XFRC)
{
-
+
if (hhcd->Init.dma_enable)
{
hhcd->hc[chnum].xfer_count = hhcd->hc[chnum].xfer_len - \
(USBx_HC(chnum)->HCTSIZ & USB_OTG_HCTSIZ_XFRSIZ);
}
-
+
hhcd->hc[chnum].state = HC_XFRC;
hhcd->hc[chnum].ErrCnt = 0;
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC);
-
-
+
+
if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)||
(hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
{
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- USB_HC_Halt(hhcd->Instance, chnum);
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+ USB_HC_Halt(hhcd->Instance, chnum);
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
-
+
}
else if(hhcd->hc[chnum].ep_type == EP_TYPE_INTR)
{
USBx_HC(chnum)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM;
- hhcd->hc[chnum].urb_state = URB_DONE;
+ hhcd->hc[chnum].urb_state = URB_DONE;
HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
}
hhcd->hc[chnum].toggle_in ^= 1;
-
+
}
else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_CHH)
{
- int reactivate = 0;
- __HAL_HCD_MASK_HALT_HC_INT(chnum);
-
+ int reactivate = 0; // MBED: added
+ __HAL_HCD_MASK_HALT_HC_INT(chnum);
+
if(hhcd->hc[chnum].state == HC_XFRC)
{
- hhcd->hc[chnum].urb_state = URB_DONE;
+ hhcd->hc[chnum].urb_state = URB_DONE;
}
-
- else if (hhcd->hc[chnum].state == HC_STALL)
+
+ else if (hhcd->hc[chnum].state == HC_STALL)
{
hhcd->hc[chnum].urb_state = URB_STALL;
- }
-
+ }
+
else if((hhcd->hc[chnum].state == HC_XACTERR) ||
(hhcd->hc[chnum].state == HC_DATATGLERR))
{
if(hhcd->hc[chnum].ErrCnt++ > 3)
- {
+ {
hhcd->hc[chnum].ErrCnt = 0;
hhcd->hc[chnum].urb_state = URB_ERROR;
}
@@ -932,50 +954,63 @@
/* re-activate the channel */
tmpreg = USBx_HC(chnum)->HCCHAR;
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+ // MBED: changed
if ( hhcd->hc[chnum].urb_state != URB_ERROR) {
tmpreg |= USB_OTG_HCCHAR_CHENA;
reactivate = 1;
}
USBx_HC(chnum)->HCCHAR = tmpreg;
}
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
- if (hhcd->hc[chnum].state == 0) reactivate = 1;
- if (reactivate == 0 )HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
- }
-
- else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_TXERR)
- {
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- hhcd->hc[chnum].ErrCnt++;
- hhcd->hc[chnum].state = HC_XACTERR;
- USB_HC_Halt(hhcd->Instance, chnum);
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);
- }
- else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_NAK)
- {
- if(hhcd->hc[chnum].ep_type == EP_TYPE_INTR)
+ else if (hhcd->hc[chnum].state == HC_NAK)
{
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- USB_HC_Halt(hhcd->Instance, chnum);
- }
- else if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)||
- (hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
- {
- /* re-activate the channel */
+ hhcd->hc[chnum].urb_state = URB_NOTREADY;
+ /* re-activate the channel */
tmpreg = USBx_HC(chnum)->HCCHAR;
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
tmpreg |= USB_OTG_HCCHAR_CHENA;
USBx_HC(chnum)->HCCHAR = tmpreg;
}
- hhcd->hc[chnum].state = HC_NAK;
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
+ // MBED: changed
+ if (hhcd->hc[chnum].state == 0) reactivate = 1;
+ if (reactivate == 0 )HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
+ }
+
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_TXERR)
+ {
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+ hhcd->hc[chnum].ErrCnt++;
+ hhcd->hc[chnum].state = HC_XACTERR;
+ USB_HC_Halt(hhcd->Instance, chnum);
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);
+ }
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_NAK)
+ {
+ if(hhcd->hc[chnum].ep_type == EP_TYPE_INTR)
+ {
+ hhcd->hc[chnum].ErrCnt = 0;
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+ USB_HC_Halt(hhcd->Instance, chnum);
+ }
+ else if ((hhcd->hc[chnum].ep_type == EP_TYPE_CTRL)||
+ (hhcd->hc[chnum].ep_type == EP_TYPE_BULK))
+ {
+ hhcd->hc[chnum].ErrCnt = 0;
+ if (!hhcd->Init.dma_enable)
+ {
+ hhcd->hc[chnum].state = HC_NAK;
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+ USB_HC_Halt(hhcd->Instance, chnum);
+ }
+ }
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
}
}
/**
* @brief Handle Host Channel OUT interrupt requests.
- * @param hhcd: HCD handle
- * @param chnum: Channel number.
+ * @param hhcd HCD handle
+ * @param chnum Channel number.
* This parameter can be a value from 1 to 15
* @retval none
*/
@@ -983,120 +1018,126 @@
{
USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
uint32_t tmpreg = 0;
-
+
if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_AHBERR)
{
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_AHBERR);
__HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- }
+ }
else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_ACK)
{
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_ACK);
-
if( hhcd->hc[chnum].do_ping == 1)
{
- hhcd->hc[chnum].state = HC_NYET;
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- USB_HC_Halt(hhcd->Instance, chnum);
+ hhcd->hc[chnum].do_ping = 0;
hhcd->hc[chnum].urb_state = URB_NOTREADY;
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+ USB_HC_Halt(hhcd->Instance, chnum);
}
}
-
+
else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_NYET)
{
hhcd->hc[chnum].state = HC_NYET;
- hhcd->hc[chnum].ErrCnt= 0;
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- USB_HC_Halt(hhcd->Instance, chnum);
+ hhcd->hc[chnum].do_ping = 1;
+ hhcd->hc[chnum].ErrCnt= 0;
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+ USB_HC_Halt(hhcd->Instance, chnum);
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NYET);
-
- }
-
+ }
+
else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_FRMOR)
{
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- USB_HC_Halt(hhcd->Instance, chnum);
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+ USB_HC_Halt(hhcd->Instance, chnum);
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_FRMOR);
}
-
+
else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_XFRC)
{
- hhcd->hc[chnum].ErrCnt = 0;
+ hhcd->hc[chnum].ErrCnt = 0;
__HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- USB_HC_Halt(hhcd->Instance, chnum);
+ USB_HC_Halt(hhcd->Instance, chnum);
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_XFRC);
hhcd->hc[chnum].state = HC_XFRC;
- }
+ }
- else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_STALL)
+ else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_STALL)
{
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL);
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_STALL);
__HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- USB_HC_Halt(hhcd->Instance, chnum);
- hhcd->hc[chnum].state = HC_STALL;
+ USB_HC_Halt(hhcd->Instance, chnum);
+ hhcd->hc[chnum].state = HC_STALL;
}
else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_NAK)
- {
- hhcd->hc[chnum].ErrCnt = 0;
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- USB_HC_Halt(hhcd->Instance, chnum);
+ {
+ hhcd->hc[chnum].ErrCnt = 0;
hhcd->hc[chnum].state = HC_NAK;
+
+ if ( hhcd->hc[chnum].do_ping == 0)
+ {
+ if (hhcd->hc[chnum].speed == HCD_SPEED_HIGH)
+ {
+ hhcd->hc[chnum].do_ping = 1;
+ }
+ }
+
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+ USB_HC_Halt(hhcd->Instance, chnum);
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
}
else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_TXERR)
{
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- USB_HC_Halt(hhcd->Instance, chnum);
- hhcd->hc[chnum].state = HC_XACTERR;
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+ USB_HC_Halt(hhcd->Instance, chnum);
+ hhcd->hc[chnum].state = HC_XACTERR;
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_TXERR);
}
-
+
else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_DTERR)
{
- __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
- USB_HC_Halt(hhcd->Instance, chnum);
+ __HAL_HCD_UNMASK_HALT_HC_INT(chnum);
+ USB_HC_Halt(hhcd->Instance, chnum);
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_NAK);
- __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR);
+ __HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_DTERR);
hhcd->hc[chnum].state = HC_DATATGLERR;
}
-
-
+
else if ((USBx_HC(chnum)->HCINT) & USB_OTG_HCINT_CHH)
{
- __HAL_HCD_MASK_HALT_HC_INT(chnum);
-
+ __HAL_HCD_MASK_HALT_HC_INT(chnum);
+
if(hhcd->hc[chnum].state == HC_XFRC)
{
hhcd->hc[chnum].urb_state = URB_DONE;
if (hhcd->hc[chnum].ep_type == EP_TYPE_BULK)
{
- hhcd->hc[chnum].toggle_out ^= 1;
- }
+ hhcd->hc[chnum].toggle_out ^= 1;
+ }
}
- else if (hhcd->hc[chnum].state == HC_NAK)
+ else if (hhcd->hc[chnum].state == HC_NAK)
+ {
+ hhcd->hc[chnum].urb_state = URB_NOTREADY;
+ }
+
+ else if (hhcd->hc[chnum].state == HC_NYET)
{
hhcd->hc[chnum].urb_state = URB_NOTREADY;
- }
-
- else if (hhcd->hc[chnum].state == HC_NYET)
- {
- hhcd->hc[chnum].urb_state = URB_NOTREADY;
- hhcd->hc[chnum].do_ping = 0;
- }
-
- else if (hhcd->hc[chnum].state == HC_STALL)
+ }
+
+ else if (hhcd->hc[chnum].state == HC_STALL)
{
hhcd->hc[chnum].urb_state = URB_STALL;
- }
-
+ }
+
else if((hhcd->hc[chnum].state == HC_XACTERR) ||
(hhcd->hc[chnum].state == HC_DATATGLERR))
{
if(hhcd->hc[chnum].ErrCnt++ > 3)
- {
+ {
hhcd->hc[chnum].ErrCnt = 0;
hhcd->hc[chnum].urb_state = URB_ERROR;
}
@@ -1104,51 +1145,51 @@
{
hhcd->hc[chnum].urb_state = URB_NOTREADY;
}
-
+
/* re-activate the channel */
tmpreg = USBx_HC(chnum)->HCCHAR;
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
tmpreg |= USB_OTG_HCCHAR_CHENA;
- USBx_HC(chnum)->HCCHAR = tmpreg;
+ USBx_HC(chnum)->HCCHAR = tmpreg;
}
-
+
__HAL_HCD_CLEAR_HC_INT(chnum, USB_OTG_HCINT_CHH);
- HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
+ HAL_HCD_HC_NotifyURBChange_Callback(hhcd, chnum, hhcd->hc[chnum].urb_state);
}
-}
+}
/**
* @brief Handle Rx Queue Level interrupt requests.
- * @param hhcd: HCD handle
+ * @param hhcd HCD handle
* @retval none
*/
static void HCD_RXQLVL_IRQHandler (HCD_HandleTypeDef *hhcd)
{
- USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
- uint8_t channelnum =0;
+ USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+ uint8_t channelnum =0;
uint32_t pktsts;
- uint32_t pktcnt;
+ uint32_t pktcnt;
uint32_t temp = 0;
uint32_t tmpreg = 0;
-
+
temp = hhcd->Instance->GRXSTSP ;
- channelnum = temp & USB_OTG_GRXSTSP_EPNUM;
+ channelnum = temp & USB_OTG_GRXSTSP_EPNUM;
pktsts = (temp & USB_OTG_GRXSTSP_PKTSTS) >> 17;
pktcnt = (temp & USB_OTG_GRXSTSP_BCNT) >> 4;
-
+
switch (pktsts)
{
case GRXSTS_PKTSTS_IN:
/* Read the data into the host buffer. */
if ((pktcnt > 0) && (hhcd->hc[channelnum].xfer_buff != (void *)0))
- {
-
+ {
+
USB_ReadPacket(hhcd->Instance, hhcd->hc[channelnum].xfer_buff, pktcnt);
-
+
/*manage multiple Xfer */
- hhcd->hc[channelnum].xfer_buff += pktcnt;
+ hhcd->hc[channelnum].xfer_buff += pktcnt;
hhcd->hc[channelnum].xfer_count += pktcnt;
-
+
if((USBx_HC(channelnum)->HCTSIZ & USB_OTG_HCTSIZ_PKTCNT) > 0)
{
/* re-activate the channel when more packets are expected */
@@ -1172,40 +1213,40 @@
/**
* @brief Handle Host Port interrupt requests.
- * @param hhcd: HCD handle
+ * @param hhcd HCD handle
* @retval None
*/
static void HCD_Port_IRQHandler (HCD_HandleTypeDef *hhcd)
{
- USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
+ USB_OTG_GlobalTypeDef *USBx = hhcd->Instance;
__IO uint32_t hprt0, hprt0_dup;
-
+
/* Handle Host Port Interrupts */
hprt0 = USBx_HPRT0;
hprt0_dup = USBx_HPRT0;
-
+
hprt0_dup &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
-
+
/* Check whether Port Connect detected */
if((hprt0 & USB_OTG_HPRT_PCDET) == USB_OTG_HPRT_PCDET)
- {
+ {
if((hprt0 & USB_OTG_HPRT_PCSTS) == USB_OTG_HPRT_PCSTS)
{
USB_MASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT);
HAL_HCD_Connect_Callback(hhcd);
}
hprt0_dup |= USB_OTG_HPRT_PCDET;
-
+
}
-
+
/* Check whether Port Enable Changed */
if((hprt0 & USB_OTG_HPRT_PENCHNG) == USB_OTG_HPRT_PENCHNG)
{
hprt0_dup |= USB_OTG_HPRT_PENCHNG;
-
+
if((hprt0 & USB_OTG_HPRT_PENA) == USB_OTG_HPRT_PENA)
- {
+ {
if(hhcd->Init.phy_itface == USB_OTG_EMBEDDED_PHY)
{
if ((hprt0 & USB_OTG_HPRT_PSPD) == (HPRT0_PRTSPD_LOW_SPEED << 17))
@@ -1224,19 +1265,22 @@
USBx_HOST->HFIR = (uint32_t)60000;
}
}
+
+ HAL_HCD_PortEnabled_Callback(hhcd);
HAL_HCD_Connect_Callback(hhcd);
-
+
}
else
{
+ HAL_HCD_PortDisabled_Callback(hhcd);
/* Cleanup HPRT */
USBx_HPRT0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |\
USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG );
-
- USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT);
- }
+
+ USB_UNMASK_INTERRUPT(hhcd->Instance, USB_OTG_GINTSTS_DISCINT);
+ }
}
-
+
/* Check For an overcurrent */
if((hprt0 & USB_OTG_HPRT_POCCHNG) == USB_OTG_HPRT_POCCHNG)
{
@@ -1254,7 +1298,7 @@
/**
* @}
*/
-
+
#endif /* HAL_HCD_MODULE_ENABLED */
/**
* @}
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hcd.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_hcd.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_hcd.h
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief Header file of HCD HAL module.
******************************************************************************
* @attention
@@ -33,7 +31,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
- */
+ */
/* Define to prevent recursive inclusion -------------------------------------*/
#ifndef __STM32F7xx_HAL_HCD_H
@@ -45,7 +43,7 @@
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_ll_usb.h"
-
+
/** @addtogroup STM32F7xx_HAL_Driver
* @{
*/
@@ -53,17 +51,17 @@
/** @defgroup HCD HCD
* @brief HCD HAL module driver
* @{
- */
+ */
/* Exported types ------------------------------------------------------------*/
/** @defgroup HCD_Exported_Types HCD Exported Types
* @{
- */
+ */
-/** @defgroup HCD_Exported_Types_Group1 HCD State Structure definition
+/** @defgroup HCD_Exported_Types_Group1 HCD State Structure definition
* @{
*/
-typedef enum
+typedef enum
{
HAL_HCD_STATE_RESET = 0x00U,
HAL_HCD_STATE_READY = 0x01U,
@@ -74,19 +72,19 @@
typedef USB_OTG_GlobalTypeDef HCD_TypeDef;
typedef USB_OTG_CfgTypeDef HCD_InitTypeDef;
-typedef USB_OTG_HCTypeDef HCD_HCTypeDef ;
+typedef USB_OTG_HCTypeDef HCD_HCTypeDef ;
typedef USB_OTG_URBStateTypeDef HCD_URBStateTypeDef ;
typedef USB_OTG_HCStateTypeDef HCD_HCStateTypeDef ;
/**
* @}
*/
-/** @defgroup HCD_Exported_Types_Group2 HCD Handle Structure definition
+/** @defgroup HCD_Exported_Types_Group2 HCD Handle Structure definition
* @{
- */
+ */
typedef struct
{
- HCD_TypeDef *Instance; /*!< Register base address */
+ HCD_TypeDef *Instance; /*!< Register base address */
HCD_InitTypeDef Init; /*!< HCD required parameters */
HCD_HCTypeDef hc[15]; /*!< Host channels parameters */
HAL_LockTypeDef Lock; /*!< HCD peripheral status */
@@ -99,8 +97,8 @@
/**
* @}
- */
-
+ */
+
/* Exported constants --------------------------------------------------------*/
/** @defgroup HCD_Exported_Constants HCD Exported Constants
* @{
@@ -110,12 +108,12 @@
* @{
*/
#define HCD_SPEED_HIGH 0U
-#define HCD_SPEED_LOW 2U
+#define HCD_SPEED_LOW 2U
#define HCD_SPEED_FULL 3U
/**
* @}
*/
-
+
/** @defgroup HCD_PHY_Module HCD PHY Module
* @{
*/
@@ -124,11 +122,11 @@
/**
* @}
*/
-
+
/**
* @}
- */
-
+ */
+
/* Exported macro ------------------------------------------------------------*/
/** @defgroup HCD_Exported_Macros HCD Exported Macros
* @brief macros to handle interrupts and specific clock configurations
@@ -139,13 +137,13 @@
#define __HAL_HCD_GET_FLAG(__HANDLE__, __INTERRUPT__) ((USB_ReadInterrupts((__HANDLE__)->Instance) & (__INTERRUPT__)) == (__INTERRUPT__))
#define __HAL_HCD_CLEAR_FLAG(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->GINTSTS) = (__INTERRUPT__))
-#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
+#define __HAL_HCD_IS_INVALID_INTERRUPT(__HANDLE__) (USB_ReadInterrupts((__HANDLE__)->Instance) == 0U)
-#define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__) (USBx_HC(chnum)->HCINT = (__INTERRUPT__))
-#define __HAL_HCD_MASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM)
-#define __HAL_HCD_UNMASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM)
-#define __HAL_HCD_MASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM)
-#define __HAL_HCD_UNMASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM)
+#define __HAL_HCD_CLEAR_HC_INT(chnum, __INTERRUPT__) (USBx_HC(chnum)->HCINT = (__INTERRUPT__))
+#define __HAL_HCD_MASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_CHHM)
+#define __HAL_HCD_UNMASK_HALT_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_CHHM)
+#define __HAL_HCD_MASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK &= ~USB_OTG_HCINTMSK_ACKM)
+#define __HAL_HCD_UNMASK_ACK_HC_INT(chnum) (USBx_HC(chnum)->HCINTMSK |= USB_OTG_HCINTMSK_ACKM)
/**
* @}
*/
@@ -160,7 +158,7 @@
*/
HAL_StatusTypeDef HAL_HCD_Init(HCD_HandleTypeDef *hhcd);
HAL_StatusTypeDef HAL_HCD_DeInit (HCD_HandleTypeDef *hhcd);
-HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
+HAL_StatusTypeDef HAL_HCD_HC_Init(HCD_HandleTypeDef *hhcd,
uint8_t ch_num,
uint8_t epnum,
uint8_t dev_address,
@@ -180,21 +178,23 @@
* @{
*/
HAL_StatusTypeDef HAL_HCD_HC_SubmitRequest(HCD_HandleTypeDef *hhcd,
- uint8_t pipe,
+ uint8_t pipe,
uint8_t direction ,
- uint8_t ep_type,
- uint8_t token,
- uint8_t* pbuff,
+ uint8_t ep_type,
+ uint8_t token,
+ uint8_t* pbuff,
uint16_t length,
uint8_t do_ping);
/* Non-Blocking mode: Interrupt */
-void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_IRQHandler(HCD_HandleTypeDef *hhcd);
void HAL_HCD_SOF_Callback(HCD_HandleTypeDef *hhcd);
void HAL_HCD_Connect_Callback(HCD_HandleTypeDef *hhcd);
void HAL_HCD_Disconnect_Callback(HCD_HandleTypeDef *hhcd);
-void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,
- uint8_t chnum,
+void HAL_HCD_PortEnabled_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_PortDisabled_Callback(HCD_HandleTypeDef *hhcd);
+void HAL_HCD_HC_NotifyURBChange_Callback(HCD_HandleTypeDef *hhcd,
+ uint8_t chnum,
HCD_URBStateTypeDef urb_state);
/**
* @}
@@ -270,7 +270,7 @@
/**
* @}
- */
+ */
#ifdef __cplusplus
}
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2c.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2c.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_i2c.c
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief I2C HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Inter Integrated Circuit (I2C) peripheral:
@@ -107,6 +105,12 @@
(++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
and with new data to transfer if the direction change or manage only the new data to transfer
if no direction change and with a final stop condition in both cases
+ (++) I2C_LAST_FRAME_NO_STOP: Sequential usage (Master only), this option allow to manage a restart condition after several call of the same master sequential
+ interface several times (link with option I2C_FIRST_AND_NEXT_FRAME).
+ Usage can, transfer several bytes one by one using HAL_I2C_Master_Sequential_Transmit_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME)
+ or HAL_I2C_Master_Sequential_Receive_IT(option I2C_FIRST_AND_NEXT_FRAME then I2C_NEXT_FRAME).
+ Then usage of this option I2C_LAST_FRAME_NO_STOP at the last Transmit or Receive sequence permit to call the oposite interface Receive or Transmit
+ without stopping the communication and so generate a restart condition.
(+) Differents sequential I2C interfaces are listed below:
(++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT()
@@ -238,7 +242,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
- */
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
@@ -303,8 +307,8 @@
/* Private macro -------------------------------------------------------------*/
#define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) ((((__HANDLE__)->State) == HAL_I2C_STATE_BUSY_TX) ? \
- ((uint32_t)((__HANDLE__)->hdmatx->Instance->NDTR)) : \
- ((uint32_t)((__HANDLE__)->hdmarx->Instance->NDTR)))
+ ((uint32_t)(((DMA_Stream_TypeDef *)(__HANDLE__)->hdmatx->Instance)->NDTR)) : \
+ ((uint32_t)(((DMA_Stream_TypeDef *)(__HANDLE__)->hdmarx->Instance)->NDTR)))
/* Private variables ---------------------------------------------------------*/
/* Private function prototypes -----------------------------------------------*/
@@ -366,7 +370,7 @@
*/
/** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
+ * @brief Initialization and Configuration functions
*
@verbatim
===============================================================================
@@ -406,7 +410,7 @@
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
{
/* Check the I2C handle allocation */
- if(hi2c == NULL)
+ if (hi2c == NULL)
{
return HAL_ERROR;
}
@@ -421,7 +425,7 @@
assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
- if(hi2c->State == HAL_I2C_STATE_RESET)
+ if (hi2c->State == HAL_I2C_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hi2c->Lock = HAL_UNLOCKED;
@@ -444,7 +448,7 @@
hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
/* Configure I2Cx: Own Address1 and ack own address1 mode */
- if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
+ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
{
hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
}
@@ -455,7 +459,7 @@
/*---------------------------- I2Cx CR2 Configuration ----------------------*/
/* Configure I2Cx: Addressing Master mode */
- if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
{
hi2c->Instance->CR2 = (I2C_CR2_ADD10);
}
@@ -493,7 +497,7 @@
HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
{
/* Check the I2C handle allocation */
- if(hi2c == NULL)
+ if (hi2c == NULL)
{
return HAL_ERROR;
}
@@ -557,7 +561,7 @@
*/
/** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
- * @brief Data transfers functions
+ * @brief Data transfers functions
*
@verbatim
===============================================================================
@@ -569,7 +573,7 @@
(#) There are two modes of transfer:
(++) Blocking mode : The communication is performed in the polling mode.
- The status of all data processing is returned by the same function
+ The status of all data processing is returned by the same function
after finishing transfer.
(++) No-Blocking mode : The communication is performed using Interrupts
or DMA. These functions return the status of the transfer startup.
@@ -619,8 +623,8 @@
* @brief Transmits in master mode an amount of data in blocking mode.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * @param DevAddress Target device address which contain device 7 or 10 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param Timeout Timeout duration
@@ -630,7 +634,7 @@
{
uint32_t tickstart = 0U;
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
@@ -638,7 +642,7 @@
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -646,7 +650,7 @@
hi2c->State = HAL_I2C_STATE_BUSY_TX;
hi2c->Mode = HAL_I2C_MODE_MASTER;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
-
+
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
@@ -654,7 +658,7 @@
/* Send Slave Address */
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
@@ -665,12 +669,12 @@
I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
}
- while(hi2c->XferCount > 0U)
+ while (hi2c->XferCount > 0U)
{
/* Wait until TXIS flag is set */
- if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
return HAL_ERROR;
}
@@ -684,15 +688,15 @@
hi2c->XferCount--;
hi2c->XferSize--;
- if((hi2c->XferSize == 0U) && (hi2c->XferCount!=0U))
+ if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
{
/* Wait until TCR flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
@@ -707,9 +711,9 @@
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is set */
- if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
return HAL_ERROR;
}
@@ -743,8 +747,8 @@
* @brief Receives in master mode an amount of data in blocking mode.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * @param DevAddress Target device address which contain device 7 or 10 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param Timeout Timeout duration
@@ -754,7 +758,7 @@
{
uint32_t tickstart = 0U;
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
@@ -762,7 +766,7 @@
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -778,7 +782,7 @@
/* Send Slave Address */
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
@@ -789,12 +793,12 @@
I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
}
- while(hi2c->XferCount > 0U)
+ while (hi2c->XferCount > 0U)
{
/* Wait until RXNE flag is set */
- if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
return HAL_ERROR;
}
@@ -809,15 +813,15 @@
hi2c->XferSize--;
hi2c->XferCount--;
- if((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
+ if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
{
/* Wait until TCR flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
@@ -832,9 +836,9 @@
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is set */
- if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
return HAL_ERROR;
}
@@ -865,7 +869,7 @@
}
/**
- * @brief Transmits in slave mode an amount of data in blocking mode.
+ * @brief Transmits in slave mode an amount of data in blocking mode.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param pData Pointer to data buffer
@@ -877,9 +881,9 @@
{
uint32_t tickstart = 0U;
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -902,7 +906,7 @@
hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
/* Wait until ADDR flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
@@ -910,13 +914,13 @@
}
/* Clear ADDR flag */
- __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
/* If 10bit addressing mode is selected */
- if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
{
/* Wait until ADDR flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
@@ -924,26 +928,26 @@
}
/* Clear ADDR flag */
- __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
}
/* Wait until DIR flag is set Transmitter mode */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
return HAL_TIMEOUT;
}
- while(hi2c->XferCount > 0U)
+ while (hi2c->XferCount > 0U)
{
/* Wait until TXIS flag is set */
- if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
return HAL_ERROR;
}
@@ -959,12 +963,12 @@
}
/* Wait until STOP flag is set */
- if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
/* Normal use case for Transmitter mode */
/* A NACK is generated to confirm the end of transfer */
@@ -977,10 +981,10 @@
}
/* Clear STOP flag */
- __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);
-
- /* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Wait until BUSY flag is reset */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
@@ -1017,9 +1021,9 @@
{
uint32_t tickstart = 0U;
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -1042,7 +1046,7 @@
hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
/* Wait until ADDR flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
@@ -1050,33 +1054,33 @@
}
/* Clear ADDR flag */
- __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
/* Wait until DIR flag is reset Receiver mode */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
return HAL_TIMEOUT;
}
- while(hi2c->XferCount > 0U)
+ while (hi2c->XferCount > 0U)
{
/* Wait until RXNE flag is set */
- if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
/* Store Last receive data if any */
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
{
/* Read data from RXDR */
(*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
hi2c->XferCount--;
}
- if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
{
return HAL_TIMEOUT;
}
@@ -1092,12 +1096,12 @@
}
/* Wait until STOP flag is set */
- if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
return HAL_ERROR;
}
@@ -1108,10 +1112,10 @@
}
/* Clear STOP flag */
- __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Wait until BUSY flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
{
/* Disable Address Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
@@ -1139,8 +1143,8 @@
* @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * @param DevAddress Target device address which contain device 7 or 10 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @retval HAL status
@@ -1149,9 +1153,9 @@
{
uint32_t xfermode = 0U;
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
{
return HAL_BUSY;
}
@@ -1168,8 +1172,8 @@
hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferISR = I2C_Master_ISR_IT;
-
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = I2C_RELOAD_MODE;
@@ -1185,7 +1189,7 @@
I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
/* Process Unlocked */
- __HAL_UNLOCK(hi2c);
+ __HAL_UNLOCK(hi2c);
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
@@ -1208,8 +1212,8 @@
* @brief Receive in master mode an amount of data in non-blocking mode with Interrupt
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * @param DevAddress Target device address which contain device 7 or 10 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @retval HAL status
@@ -1218,9 +1222,9 @@
{
uint32_t xfermode = 0U;
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
{
return HAL_BUSY;
}
@@ -1237,8 +1241,8 @@
hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferISR = I2C_Master_ISR_IT;
-
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = I2C_RELOAD_MODE;
@@ -1252,7 +1256,7 @@
/* Send Slave Address */
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
-
+
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -1283,7 +1287,7 @@
*/
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
{
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
@@ -1323,7 +1327,7 @@
}
/**
- * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt
+ * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @param pData Pointer to data buffer
@@ -1332,7 +1336,7 @@
*/
HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
{
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
@@ -1375,8 +1379,8 @@
* @brief Transmit in master mode an amount of data in non-blocking mode with DMA
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * @param DevAddress Target device address which contain device 7 or 10 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @retval HAL status
@@ -1385,9 +1389,9 @@
{
uint32_t xfermode = 0U;
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
{
return HAL_BUSY;
}
@@ -1404,8 +1408,8 @@
hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferISR = I2C_Master_ISR_DMA;
-
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = I2C_RELOAD_MODE;
@@ -1416,7 +1420,7 @@
xfermode = I2C_AUTOEND_MODE;
}
- if(hi2c->XferSize > 0U)
+ if (hi2c->XferSize > 0U)
{
/* Set the I2C DMA transfer complete callback */
hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
@@ -1428,7 +1432,7 @@
hi2c->hdmatx->XferHalfCpltCallback = NULL;
hi2c->hdmatx->XferAbortCallback = NULL;
- /* Enable the DMA channel */
+ /* Enable the DMA stream */
HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
/* Send Slave Address */
@@ -1454,7 +1458,7 @@
{
/* Update Transfer ISR function pointer */
hi2c->XferISR = I2C_Master_ISR_IT;
-
+
/* Send Slave Address */
/* Set NBYTES to write and generate START condition */
I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
@@ -1483,8 +1487,8 @@
* @brief Receive in master mode an amount of data in non-blocking mode with DMA
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * @param DevAddress Target device address which contain device 7 or 10 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @retval HAL status
@@ -1493,9 +1497,9 @@
{
uint32_t xfermode = 0U;
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
{
return HAL_BUSY;
}
@@ -1512,8 +1516,8 @@
hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferISR = I2C_Master_ISR_DMA;
-
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = I2C_RELOAD_MODE;
@@ -1524,7 +1528,7 @@
xfermode = I2C_AUTOEND_MODE;
}
- if(hi2c->XferSize > 0U)
+ if (hi2c->XferSize > 0U)
{
/* Set the I2C DMA transfer complete callback */
hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
@@ -1536,12 +1540,12 @@
hi2c->hdmarx->XferHalfCpltCallback = NULL;
hi2c->hdmarx->XferAbortCallback = NULL;
- /* Enable the DMA channel */
+ /* Enable the DMA stream */
HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
/* Send Slave Address */
/* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
/* Update XferCount value */
hi2c->XferCount -= hi2c->XferSize;
@@ -1562,7 +1566,7 @@
{
/* Update Transfer ISR function pointer */
hi2c->XferISR = I2C_Master_ISR_IT;
-
+
/* Send Slave Address */
/* Set NBYTES to read and generate START condition */
I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
@@ -1596,12 +1600,12 @@
*/
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
{
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
- }
+ }
/* Process Locked */
__HAL_LOCK(hi2c);
@@ -1626,7 +1630,7 @@
hi2c->hdmatx->XferHalfCpltCallback = NULL;
hi2c->hdmatx->XferAbortCallback = NULL;
- /* Enable the DMA channel */
+ /* Enable the DMA stream */
HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
/* Enable Address Acknowledge */
@@ -1642,7 +1646,7 @@
I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
/* Enable DMA Request */
- hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
+ hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
return HAL_OK;
}
@@ -1662,9 +1666,9 @@
*/
HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
{
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -1692,7 +1696,7 @@
hi2c->hdmarx->XferHalfCpltCallback = NULL;
hi2c->hdmarx->XferAbortCallback = NULL;
- /* Enable the DMA channel */
+ /* Enable the DMA stream */
HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
/* Enable Address Acknowledge */
@@ -1721,8 +1725,8 @@
* @brief Write an amount of data in blocking mode to a specific memory address
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * @param DevAddress Target device address which contain device 7 or 10 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
* @param pData Pointer to data buffer
@@ -1737,9 +1741,9 @@
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -1750,7 +1754,7 @@
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -1765,9 +1769,9 @@
hi2c->XferISR = NULL;
/* Send Slave Address and Memory Address */
- if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
+ if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -1782,7 +1786,7 @@
}
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
@@ -1796,9 +1800,9 @@
do
{
/* Wait until TXIS flag is set */
- if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
return HAL_ERROR;
}
@@ -1813,15 +1817,15 @@
hi2c->XferCount--;
hi2c->XferSize--;
- if((hi2c->XferSize == 0U) && (hi2c->XferCount!=0U))
+ if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
{
/* Wait until TCR flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
@@ -1833,13 +1837,14 @@
}
}
- }while(hi2c->XferCount > 0U);
+ }
+ while (hi2c->XferCount > 0U);
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
- /* Wait until STOPF flag is reset */
- if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ /* Wait until STOPF flag is reset */
+ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
return HAL_ERROR;
}
@@ -1873,8 +1878,8 @@
* @brief Read an amount of data in blocking mode from a specific memory address
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * @param DevAddress Target device address which contain device 7 or 10 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
* @param pData Pointer to data buffer
@@ -1889,9 +1894,9 @@
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -1902,7 +1907,7 @@
/* Init tickstart for timeout management*/
tickstart = HAL_GetTick();
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -1917,9 +1922,9 @@
hi2c->XferISR = NULL;
/* Send Slave Address and Memory Address */
- if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
+ if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -1935,7 +1940,7 @@
/* Send Slave Address */
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
@@ -1949,7 +1954,7 @@
do
{
/* Wait until RXNE flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -1959,15 +1964,15 @@
hi2c->XferSize--;
hi2c->XferCount--;
- if((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
+ if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
{
/* Wait until TCR flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
@@ -1978,13 +1983,14 @@
I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
}
}
- }while(hi2c->XferCount > 0U);
+ }
+ while (hi2c->XferCount > 0U);
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
- /* Wait until STOPF flag is reset */
- if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
+ /* Wait until STOPF flag is reset */
+ if (I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
return HAL_ERROR;
}
@@ -2017,8 +2023,8 @@
* @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * @param DevAddress Target device address which contain device 7 or 10 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
* @param pData Pointer to data buffer
@@ -2033,14 +2039,14 @@
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
-
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
{
return HAL_BUSY;
}
@@ -2060,8 +2066,8 @@
hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferISR = I2C_Master_ISR_IT;
-
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = I2C_RELOAD_MODE;
@@ -2073,9 +2079,9 @@
}
/* Send Slave Address and Memory Address */
- if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+ if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -2090,12 +2096,12 @@
}
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
/* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- /* Note : The I2C interrupts must be enabled after unlocking current process
+ __HAL_UNLOCK(hi2c);
+
+ /* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
@@ -2116,8 +2122,8 @@
* @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * @param DevAddress Target device address which contain device 7 or 10 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
* @param pData Pointer to data buffer
@@ -2132,14 +2138,14 @@
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
-
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
{
return HAL_BUSY;
}
@@ -2159,8 +2165,8 @@
hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferISR = I2C_Master_ISR_IT;
-
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = I2C_RELOAD_MODE;
@@ -2172,9 +2178,9 @@
}
/* Send Slave Address and Memory Address */
- if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+ if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -2189,7 +2195,7 @@
}
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -2214,8 +2220,8 @@
* @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * @param DevAddress Target device address which contain device 7 or 10 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
* @param pData Pointer to data buffer
@@ -2230,14 +2236,14 @@
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
{
return HAL_BUSY;
}
@@ -2257,8 +2263,8 @@
hi2c->XferCount = Size;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferISR = I2C_Master_ISR_DMA;
-
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = I2C_RELOAD_MODE;
@@ -2270,9 +2276,9 @@
}
/* Send Slave Address and Memory Address */
- if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+ if (I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -2296,7 +2302,7 @@
hi2c->hdmatx->XferHalfCpltCallback = NULL;
hi2c->hdmatx->XferAbortCallback = NULL;
- /* Enable the DMA channel */
+ /* Enable the DMA stream */
HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
/* Send Slave Address */
@@ -2330,8 +2336,8 @@
* @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * @param DevAddress Target device address which contain device 7 or 10 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
* @param pData Pointer to data buffer
@@ -2346,14 +2352,14 @@
/* Check the parameters */
assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
- if((pData == NULL) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
{
return HAL_BUSY;
}
@@ -2374,7 +2380,7 @@
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->XferISR = I2C_Master_ISR_DMA;
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = I2C_RELOAD_MODE;
@@ -2386,9 +2392,9 @@
}
/* Send Slave Address and Memory Address */
- if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
+ if (I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -2412,11 +2418,11 @@
hi2c->hdmarx->XferHalfCpltCallback = NULL;
hi2c->hdmarx->XferAbortCallback = NULL;
- /* Enable the DMA channel */
+ /* Enable the DMA stream */
HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
/* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
- I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
/* Update XferCount value */
hi2c->XferCount -= hi2c->XferSize;
@@ -2446,8 +2452,8 @@
* @note This function is used with Memory devices
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * @param DevAddress Target device address which contain device 7 or 10 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param Trials Number of trials
* @param Timeout Timeout duration
* @retval HAL status
@@ -2458,9 +2464,9 @@
__IO uint32_t I2C_Trials = 0U;
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
{
return HAL_BUSY;
}
@@ -2474,16 +2480,16 @@
do
{
/* Generate Start */
- hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode,DevAddress);
+ hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode, DevAddress);
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is set or a NACK flag is set*/
tickstart = HAL_GetTick();
- while((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT))
+ while ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT))
{
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+ if (Timeout != HAL_MAX_DELAY)
+ {
+ if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
{
/* Device is ready */
hi2c->State = HAL_I2C_STATE_READY;
@@ -2491,14 +2497,14 @@
__HAL_UNLOCK(hi2c);
return HAL_TIMEOUT;
}
- }
+ }
}
/* Check if the NACKF flag has not been set */
if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
{
- /* Wait until STOPF flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
+ /* Wait until STOPF flag is reset */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -2517,7 +2523,7 @@
else
{
/* Wait until STOPF flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -2535,8 +2541,8 @@
/* Generate Stop */
hi2c->Instance->CR2 |= I2C_CR2_STOP;
- /* Wait until STOPF flag is reset */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
+ /* Wait until STOPF flag is reset */
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -2544,7 +2550,8 @@
/* Clear STOP Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
}
- }while(I2C_Trials < Trials);
+ }
+ while (I2C_Trials < Trials);
hi2c->State = HAL_I2C_STATE_READY;
@@ -2564,8 +2571,8 @@
* @note This interface allow to manage repeated start condition when a direction change during transfer
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * @param DevAddress Target device address which contain device 7 or 10 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
@@ -2579,7 +2586,7 @@
/* Check the parameters */
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
@@ -2591,11 +2598,11 @@
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
- hi2c->XferOptions = (XferOptions & (~I2C_RELOAD_MODE));
+ hi2c->XferOptions = (XferOptions & (~I2C_RELOAD_MODE)); // MBED: changed
hi2c->XferISR = I2C_Master_ISR_IT;
-
+
/* If size > MAX_NBYTE_SIZE, use reload mode */
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = I2C_RELOAD_MODE;
@@ -2606,12 +2613,20 @@
xfermode = hi2c->XferOptions;
}
+ // MBED: removed
+ /* If transfer direction not change, do not generate Restart Condition */
+ /* Mean Previous state is same as current state */
+ //if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
+ //{
+ // xferrequest = I2C_NO_STARTSTOP;
+ //}
+
/* Send Slave Address and set NBYTES to write */
I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest);
-
+
/* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
+ __HAL_UNLOCK(hi2c);
+
/* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
@@ -2630,8 +2645,8 @@
* @note This interface allow to manage repeated start condition when a direction change during transfer
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * @param DevAddress Target device address which contain device 7 or 10 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
@@ -2645,7 +2660,7 @@
/* Check the parameters */
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
@@ -2657,11 +2672,11 @@
/* Prepare transfer parameters */
hi2c->pBuffPtr = pData;
hi2c->XferCount = Size;
- hi2c->XferOptions = (XferOptions & (~I2C_RELOAD_MODE));
+ hi2c->XferOptions = (XferOptions & (~I2C_RELOAD_MODE)); // MBED: changed
hi2c->XferISR = I2C_Master_ISR_IT;
/* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = I2C_RELOAD_MODE;
@@ -2670,11 +2685,18 @@
{
hi2c->XferSize = hi2c->XferCount;
xfermode = hi2c->XferOptions;
-
}
+ // MBED: removed
+ /* If transfer direction not change, do not generate Restart Condition */
+ /* Mean Previous state is same as current state */
+ //if (hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
+ //{
+ // xferrequest = I2C_NO_STARTSTOP;
+ //}
+
/* Send Slave Address and set NBYTES to read */
- I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, xferrequest);
+ I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -2707,9 +2729,9 @@
/* Check the parameters */
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
- if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
+ if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
{
- if((pData == NULL) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -2719,10 +2741,10 @@
/* Process Locked */
__HAL_LOCK(hi2c);
-
+
/* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
/* and then toggle the HAL slave RX state to TX state */
- if(hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+ if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
{
/* Disable associated Interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
@@ -2742,11 +2764,11 @@
hi2c->XferOptions = XferOptions;
hi2c->XferISR = I2C_Slave_ISR_IT;
- if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
+ if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
{
/* Clear ADDR flag after prepare the transfer parameters */
/* This action will generate an acknowledge to the Master */
- __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
}
/* Process Unlocked */
@@ -2781,9 +2803,9 @@
/* Check the parameters */
assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
- if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
+ if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
{
- if((pData == NULL) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -2793,15 +2815,15 @@
/* Process Locked */
__HAL_LOCK(hi2c);
-
+
/* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
/* and then toggle the HAL slave TX state to RX state */
- if(hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+ if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
{
/* Disable associated Interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
}
-
+
hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
hi2c->Mode = HAL_I2C_MODE_SLAVE;
hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
@@ -2816,11 +2838,11 @@
hi2c->XferOptions = XferOptions;
hi2c->XferISR = I2C_Slave_ISR_IT;
- if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
+ if (I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
{
/* Clear ADDR flag after prepare the transfer parameters */
/* This action will generate an acknowledge to the Master */
- __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
}
/* Process Unlocked */
@@ -2848,7 +2870,7 @@
*/
HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
{
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
hi2c->State = HAL_I2C_STATE_LISTEN;
hi2c->XferISR = I2C_Slave_ISR_IT;
@@ -2876,7 +2898,7 @@
uint32_t tmp;
/* Disable Address listen mode only if a transfer is not ongoing */
- if(hi2c->State == HAL_I2C_STATE_LISTEN)
+ if (hi2c->State == HAL_I2C_STATE_LISTEN)
{
tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
@@ -2899,13 +2921,13 @@
* @brief Abort a master I2C IT or DMA process communication with Interrupt.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * @param DevAddress Target device address which contain device 7 or 10 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @retval HAL status
*/
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
{
- if(hi2c->Mode == HAL_I2C_MODE_MASTER)
+ if (hi2c->Mode == HAL_I2C_MODE_MASTER)
{
/* Process Locked */
__HAL_LOCK(hi2c);
@@ -2924,7 +2946,7 @@
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
- /* Note : The I2C interrupts must be enabled after unlocking current process
+ /* Note : The I2C interrupts must be enabled after unlocking current process
to avoid the risk of I2C interrupt handle execution before current
process unlock */
I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
@@ -2945,7 +2967,7 @@
/** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
* @{
- */
+ */
/**
* @brief This function handles I2C event interrupt request.
@@ -2960,7 +2982,7 @@
uint32_t itsources = READ_REG(hi2c->Instance->CR1);
/* I2C events treatment -------------------------------------*/
- if(hi2c->XferISR != NULL)
+ if (hi2c->XferISR != NULL)
{
hi2c->XferISR(hi2c, itflags, itsources);
}
@@ -2978,7 +3000,7 @@
uint32_t itsources = READ_REG(hi2c->Instance->CR1);
/* I2C Bus error interrupt occurred ------------------------------------*/
- if(((itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
+ if (((itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
@@ -2987,7 +3009,7 @@
}
/* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
- if(((itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
+ if (((itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
@@ -2996,7 +3018,7 @@
}
/* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
- if(((itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
+ if (((itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
@@ -3005,7 +3027,7 @@
}
/* Call the Error Callback in case of Error detected */
- if((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE)
+ if ((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE)
{
I2C_ITError(hi2c, hi2c->ErrorCode);
}
@@ -3078,8 +3100,8 @@
* @brief Slave Address Match callback.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param TransferDirection: Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION
- * @param AddrMatchCode: Address Match Code
+ * @param TransferDirection Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION
+ * @param AddrMatchCode Address Match Code
* @retval None
*/
__weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
@@ -3217,7 +3239,7 @@
}
/**
-* @brief Return the I2C error code.
+ * @brief Return the I2C error code.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
* @retval I2C Error Code
@@ -3229,7 +3251,7 @@
/**
* @}
- */
+ */
/**
* @}
@@ -3247,14 +3269,14 @@
* @param ITSources Interrupt sources enabled.
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
+static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
{
uint16_t devaddress = 0U;
/* Process Locked */
__HAL_LOCK(hi2c);
- if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
+ if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
@@ -3267,27 +3289,27 @@
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
}
- else if(((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET))
+ else if (((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET))
{
/* Read data from RXDR */
(*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
hi2c->XferSize--;
hi2c->XferCount--;
}
- else if(((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET))
+ else if (((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET))
{
/* Write data to TXDR */
hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
hi2c->XferSize--;
hi2c->XferCount--;
}
- else if(((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
+ else if (((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
{
- if((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
+ if ((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
{
devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
-
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
+
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
@@ -3295,7 +3317,7 @@
else
{
hi2c->XferSize = hi2c->XferCount;
- if(hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+ if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
{
I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP);
}
@@ -3308,7 +3330,7 @@
else
{
/* Call TxCpltCallback() if no stop mode is set */
- if(I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+ if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
{
/* Call I2C Master Sequential complete process */
I2C_ITMasterSequentialCplt(hi2c);
@@ -3321,14 +3343,14 @@
}
}
}
- else if(((ITFlags & I2C_FLAG_TC) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
+ else if (((ITFlags & I2C_FLAG_TC) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
{
- if(hi2c->XferCount == 0U)
+ if (hi2c->XferCount == 0U)
{
- if(I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
+ if (I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
{
/* Generate a stop condition in case of no transfer option */
- if(hi2c->XferOptions == I2C_NO_OPTION_FRAME)
+ if (hi2c->XferOptions == I2C_NO_OPTION_FRAME)
{
/* Generate Stop */
hi2c->Instance->CR2 |= I2C_CR2_STOP;
@@ -3348,7 +3370,7 @@
}
}
- if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
+ if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
{
/* Call I2C Master complete process */
I2C_ITMasterCplt(hi2c, ITFlags);
@@ -3368,26 +3390,26 @@
* @param ITSources Interrupt sources enabled.
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
+static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
{
/* Process locked */
__HAL_LOCK(hi2c);
-
- if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
+
+ if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
{
/* Check that I2C transfer finished */
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
/* Mean XferCount == 0*/
/* So clear Flag NACKF only */
- if(hi2c->XferCount == 0U)
+ if (hi2c->XferCount == 0U)
{
- if(((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \
- (hi2c->State == HAL_I2C_STATE_LISTEN))
+ if (((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \
+ (hi2c->State == HAL_I2C_STATE_LISTEN))
{
/* Call I2C Listen complete process */
I2C_ITListenCplt(hi2c, ITFlags);
}
- else if((hi2c->XferOptions != I2C_NO_OPTION_FRAME) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN))
+ else if ((hi2c->XferOptions != I2C_NO_OPTION_FRAME) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN))
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
@@ -3415,9 +3437,9 @@
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
}
}
- else if(((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET))
+ else if (((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET))
{
- if(hi2c->XferCount > 0U)
+ if (hi2c->XferCount > 0U)
{
/* Read data from RXDR */
(*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
@@ -3425,24 +3447,24 @@
hi2c->XferCount--;
}
- if((hi2c->XferCount == 0U) && \
- (hi2c->XferOptions != I2C_NO_OPTION_FRAME))
+ if ((hi2c->XferCount == 0U) && \
+ (hi2c->XferOptions != I2C_NO_OPTION_FRAME))
{
/* Call I2C Slave Sequential complete process */
I2C_ITSlaveSequentialCplt(hi2c);
- }
+ }
}
- else if(((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET))
+ else if (((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET))
{
I2C_ITAddrCplt(hi2c, ITFlags);
}
- else if(((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET))
+ else if (((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET))
{
/* Write data to TXDR only if XferCount not reach "0" */
/* A TXIS flag can be set, during STOP treatment */
/* Check if all Datas have already been sent */
/* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
- if(hi2c->XferCount > 0U)
+ if (hi2c->XferCount > 0U)
{
/* Write data to TXDR */
hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
@@ -3451,7 +3473,7 @@
}
else
{
- if((hi2c->XferOptions == I2C_NEXT_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME))
+ if ((hi2c->XferOptions == I2C_NEXT_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME))
{
/* Last Byte is Transmitted */
/* Call I2C Slave Sequential complete process */
@@ -3461,7 +3483,7 @@
}
/* Check if STOPF is set */
- if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
+ if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
{
/* Call I2C Slave complete process */
I2C_ITSlaveCplt(hi2c, ITFlags);
@@ -3481,7 +3503,7 @@
* @param ITSources Interrupt sources enabled.
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
+static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
{
uint16_t devaddress = 0U;
uint32_t xfermode = 0U;
@@ -3489,14 +3511,14 @@
/* Process Locked */
__HAL_LOCK(hi2c);
- if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
+ if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
/* Set corresponding Error Code */
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
-
+
/* No need to generate STOP, it is automatically done */
/* But enable STOP interrupt, to treat it */
/* Error callback will be send during stop flag treatment */
@@ -3505,18 +3527,18 @@
/* Flush TX register */
I2C_Flush_TXDR(hi2c);
}
- else if(((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
+ else if (((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
{
/* Disable TC interrupt */
__HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
-
- if(hi2c->XferCount != 0U)
+
+ if (hi2c->XferCount != 0U)
{
/* Recover Slave address */
devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
-
+
/* Prepare the new XferSize to transfer */
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
xfermode = I2C_RELOAD_MODE;
@@ -3534,7 +3556,7 @@
hi2c->XferCount -= hi2c->XferSize;
/* Enable DMA Request */
- if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
{
hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
}
@@ -3550,7 +3572,7 @@
I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
}
}
- else if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
+ else if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
{
/* Call I2C Master complete process */
I2C_ITMasterCplt(hi2c, ITFlags);
@@ -3570,18 +3592,18 @@
* @param ITSources Interrupt sources enabled.
* @retval HAL status
*/
-static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
+static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
{
/* Process locked */
__HAL_LOCK(hi2c);
-
- if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
+
+ if (((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
{
/* Check that I2C transfer finished */
/* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
/* Mean XferCount == 0 */
/* So clear Flag NACKF only */
- if(I2C_GET_DMA_REMAIN_DATA(hi2c) == 0U)
+ if (I2C_GET_DMA_REMAIN_DATA(hi2c) == 0U)
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
@@ -3591,17 +3613,17 @@
/* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
-
+
/* Set ErrorCode corresponding to a Non-Acknowledge */
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
}
}
- else if(((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET))
+ else if (((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET))
{
/* Clear ADDR flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
}
- else if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
+ else if (((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
{
/* Call I2C Slave complete process */
I2C_ITSlaveCplt(hi2c, ITFlags);
@@ -3617,8 +3639,8 @@
* @brief Master sends target device address followed by internal memory address for write request.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * @param DevAddress Target device address which contain device 7 or 10 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
* @param Timeout Timeout duration
@@ -3627,12 +3649,12 @@
*/
static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
{
- I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
+ I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
/* Wait until TXIS flag is set */
- if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
return HAL_ERROR;
}
@@ -3643,7 +3665,7 @@
}
/* If Memory address size is 8Bit */
- if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
+ if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
{
/* Send Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
@@ -3655,9 +3677,9 @@
hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
/* Wait until TXIS flag is set */
- if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
return HAL_ERROR;
}
@@ -3666,26 +3688,26 @@
return HAL_TIMEOUT;
}
}
-
+
/* Send LSB of Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
}
/* Wait until TCR flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
-return HAL_OK;
+ return HAL_OK;
}
/**
* @brief Master sends target device address followed by internal memory address for read request.
* @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
* the configuration information for the specified I2C.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * @param DevAddress Target device address which contain device 7 or 10 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param MemAddress Internal memory address
* @param MemAddSize Size of internal memory address
* @param Timeout Timeout duration
@@ -3694,12 +3716,12 @@
*/
static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
{
- I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
+ I2C_TransferConfig(hi2c, DevAddress, MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
/* Wait until TXIS flag is set */
- if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
return HAL_ERROR;
}
@@ -3710,7 +3732,7 @@
}
/* If Memory address size is 8Bit */
- if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
+ if (MemAddSize == I2C_MEMADD_SIZE_8BIT)
{
/* Send Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
@@ -3722,9 +3744,9 @@
hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
/* Wait until TXIS flag is set */
- if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
+ if (I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
{
- if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
+ if (hi2c->ErrorCode == HAL_I2C_ERROR_AF)
{
return HAL_ERROR;
}
@@ -3733,17 +3755,17 @@
return HAL_TIMEOUT;
}
}
-
+
/* Send LSB of Memory Address */
hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
}
/* Wait until TC flag is set */
- if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
+ if (I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
{
return HAL_TIMEOUT;
}
-
+
return HAL_OK;
}
@@ -3764,7 +3786,7 @@
UNUSED(ITFlags);
/* In case of Listen state, need to inform upper layer of address match code event */
- if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
+ if ((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
{
transferdirection = I2C_GET_DIR(hi2c);
slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c);
@@ -3772,19 +3794,19 @@
ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c);
/* If 10bits addressing mode is selected */
- if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
+ if (hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
{
- if((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK))
+ if ((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK))
{
slaveaddrcode = ownadd1code;
hi2c->AddrEventCount++;
- if(hi2c->AddrEventCount == 2U)
+ if (hi2c->AddrEventCount == 2U)
{
/* Reset Address Event counter */
hi2c->AddrEventCount = 0U;
/* Clear ADDR flag */
- __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -3886,7 +3908,7 @@
/* Reset I2C handle mode */
hi2c->Mode = HAL_I2C_MODE_NONE;
- if(hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
+ if (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
{
/* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
hi2c->State = HAL_I2C_STATE_LISTEN;
@@ -3902,7 +3924,7 @@
HAL_I2C_SlaveTxCpltCallback(hi2c);
}
- else if(hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
+ else if (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
{
/* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */
hi2c->State = HAL_I2C_STATE_LISTEN;
@@ -3938,7 +3960,7 @@
hi2c->XferISR = NULL;
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
- if((ITFlags & I2C_FLAG_AF) != RESET)
+ if ((ITFlags & I2C_FLAG_AF) != RESET)
{
/* Clear NACK Flag */
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
@@ -3951,16 +3973,16 @@
I2C_Flush_TXDR(hi2c);
/* Disable Interrupts */
- I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT| I2C_XFER_RX_IT);
+ I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_RX_IT);
/* Call the corresponding callback to inform upper layer of End of Transfer */
- if((hi2c->ErrorCode != HAL_I2C_ERROR_NONE) || (hi2c->State == HAL_I2C_STATE_ABORT))
+ if ((hi2c->ErrorCode != HAL_I2C_ERROR_NONE) || (hi2c->State == HAL_I2C_STATE_ABORT))
{
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c, hi2c->ErrorCode);
}
/* hi2c->State == HAL_I2C_STATE_BUSY_TX */
- else if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
+ else if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
{
hi2c->State = HAL_I2C_STATE_READY;
@@ -3986,7 +4008,7 @@
}
}
/* hi2c->State == HAL_I2C_STATE_BUSY_RX */
- else if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
{
hi2c->State = HAL_I2C_STATE_READY;
@@ -4023,7 +4045,7 @@
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
/* Clear ADDR flag */
- __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
/* Disable all interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
@@ -4038,26 +4060,26 @@
I2C_Flush_TXDR(hi2c);
/* If a DMA is ongoing, Update handle size context */
- if(((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) ||
- ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN))
+ if (((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) ||
+ ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN))
{
hi2c->XferCount = I2C_GET_DMA_REMAIN_DATA(hi2c);
}
/* All data are not transferred, so set error code accordingly */
- if(hi2c->XferCount != 0U)
+ if (hi2c->XferCount != 0U)
{
/* Set ErrorCode corresponding to a Non-Acknowledge */
hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
}
/* Store Last receive data if any */
- if(((ITFlags & I2C_FLAG_RXNE) != RESET))
+ if (((ITFlags & I2C_FLAG_RXNE) != RESET))
{
/* Read data from RXDR */
(*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
- if((hi2c->XferSize > 0U))
+ if ((hi2c->XferSize > 0U))
{
hi2c->XferSize--;
hi2c->XferCount--;
@@ -4071,19 +4093,19 @@
hi2c->Mode = HAL_I2C_MODE_NONE;
hi2c->XferISR = NULL;
- if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
+ if (hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
{
/* Call the corresponding callback to inform upper layer of End of Transfer */
I2C_ITError(hi2c, hi2c->ErrorCode);
/* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
- if(hi2c->State == HAL_I2C_STATE_LISTEN)
+ if (hi2c->State == HAL_I2C_STATE_LISTEN)
{
/* Call I2C Listen complete process */
I2C_ITListenCplt(hi2c, ITFlags);
}
}
- else if(hi2c->XferOptions != I2C_NO_OPTION_FRAME)
+ else if (hi2c->XferOptions != I2C_NO_OPTION_FRAME)
{
hi2c->XferOptions = I2C_NO_OPTION_FRAME;
hi2c->State = HAL_I2C_STATE_READY;
@@ -4095,7 +4117,7 @@
HAL_I2C_ListenCpltCallback(hi2c);
}
/* Call the corresponding callback to inform upper layer of End of Transfer */
- else if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
+ else if (hi2c->State == HAL_I2C_STATE_BUSY_RX)
{
hi2c->State = HAL_I2C_STATE_READY;
@@ -4133,12 +4155,12 @@
hi2c->XferISR = NULL;
/* Store Last receive data if any */
- if(((ITFlags & I2C_FLAG_RXNE) != RESET))
+ if (((ITFlags & I2C_FLAG_RXNE) != RESET))
{
/* Read data from RXDR */
(*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
- if((hi2c->XferSize > 0U))
+ if ((hi2c->XferSize > 0U))
{
hi2c->XferSize--;
hi2c->XferCount--;
@@ -4178,9 +4200,9 @@
hi2c->ErrorCode |= ErrorCode;
/* Disable Interrupts */
- if((hi2c->State == HAL_I2C_STATE_LISTEN) ||
- (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
- (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN))
+ if ((hi2c->State == HAL_I2C_STATE_LISTEN) ||
+ (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
+ (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN))
{
/* Disable all interrupts, except interrupts related to LISTEN state */
I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
@@ -4194,10 +4216,10 @@
{
/* Disable all interrupts */
I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
-
+
/* If state is an abort treatment on goind, don't change state */
/* This change will be do later */
- if(hi2c->State != HAL_I2C_STATE_ABORT)
+ if (hi2c->State != HAL_I2C_STATE_ABORT)
{
/* Set HAL_I2C_STATE_READY */
hi2c->State = HAL_I2C_STATE_READY;
@@ -4207,7 +4229,7 @@
}
/* Abort DMA TX transfer if any */
- if((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
+ if ((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
{
hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
@@ -4219,14 +4241,14 @@
__HAL_UNLOCK(hi2c);
/* Abort DMA TX */
- if(HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
{
/* Call Directly XferAbortCallback function in case of error */
hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
}
}
/* Abort DMA RX transfer if any */
- else if((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
+ else if ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
{
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
@@ -4238,16 +4260,16 @@
__HAL_UNLOCK(hi2c);
/* Abort DMA RX */
- if(HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
+ if (HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
{
/* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
}
}
- else if(hi2c->State == HAL_I2C_STATE_ABORT)
+ else if (hi2c->State == HAL_I2C_STATE_ABORT)
{
hi2c->State = HAL_I2C_STATE_READY;
-
+
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -4273,13 +4295,13 @@
{
/* If a pending TXIS flag is set */
/* Write a dummy data in TXDR to clear it */
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
{
- hi2c->Instance->TXDR = 0x00U;
+ hi2c->Instance->TXDR = 0x00U;
}
/* Flush TX register if not empty */
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
{
__HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
}
@@ -4292,13 +4314,13 @@
*/
static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
{
- I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Disable DMA Request */
hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
/* If last transfer, enable STOP interrupt */
- if(hi2c->XferCount == 0U)
+ if (hi2c->XferCount == 0U)
{
/* Enable STOP interrupt */
I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
@@ -4310,7 +4332,7 @@
hi2c->pBuffPtr += hi2c->XferSize;
/* Set the XferSize to transfer */
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
}
@@ -4319,7 +4341,7 @@
hi2c->XferSize = hi2c->XferCount;
}
- /* Enable the DMA channel */
+ /* Enable the DMA stream */
HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
/* Enable TC interrupts */
@@ -4349,13 +4371,13 @@
*/
static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
{
- I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Disable DMA Request */
hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
/* If last transfer, enable STOP interrupt */
- if(hi2c->XferCount == 0U)
+ if (hi2c->XferCount == 0U)
{
/* Enable STOP interrupt */
I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
@@ -4367,7 +4389,7 @@
hi2c->pBuffPtr += hi2c->XferSize;
/* Set the XferSize to transfer */
- if(hi2c->XferCount > MAX_NBYTE_SIZE)
+ if (hi2c->XferCount > MAX_NBYTE_SIZE)
{
hi2c->XferSize = MAX_NBYTE_SIZE;
}
@@ -4376,7 +4398,7 @@
hi2c->XferSize = hi2c->XferCount;
}
- /* Enable the DMA channel */
+ /* Enable the DMA stream */
HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
/* Enable TC interrupts */
@@ -4406,7 +4428,7 @@
*/
static void I2C_DMAError(DMA_HandleTypeDef *hdma)
{
- I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Disable Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
@@ -4418,12 +4440,12 @@
/**
* @brief DMA I2C communication abort callback
* (To be called at end of DMA Abort procedure).
- * @param hdma: DMA handle.
+ * @param hdma DMA handle.
* @retval None
*/
static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
{
- I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
+ I2C_HandleTypeDef *hi2c = (I2C_HandleTypeDef *)((DMA_HandleTypeDef *)hdma)->Parent;
/* Disable Acknowledge */
hi2c->Instance->CR2 |= I2C_CR2_NACK;
@@ -4433,10 +4455,10 @@
hi2c->hdmarx->XferAbortCallback = NULL;
/* Check if come from abort from user */
- if(hi2c->State == HAL_I2C_STATE_ABORT)
+ if (hi2c->State == HAL_I2C_STATE_ABORT)
{
hi2c->State = HAL_I2C_STATE_READY;
-
+
/* Call the corresponding callback to inform upper layer of End of Transfer */
HAL_I2C_AbortCpltCallback(hi2c);
}
@@ -4459,14 +4481,14 @@
*/
static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
{
- while(__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
+ while (__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
{
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
+ if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
{
- hi2c->State= HAL_I2C_STATE_READY;
+ hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
@@ -4488,21 +4510,21 @@
*/
static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
- while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
+ while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
{
/* Check if a NACK is detected */
- if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
+ if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
{
return HAL_ERROR;
}
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout))
+ if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- hi2c->State= HAL_I2C_STATE_READY;
+ hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
@@ -4525,19 +4547,19 @@
*/
static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
- while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
+ while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
{
/* Check if a NACK is detected */
- if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
+ if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
{
return HAL_ERROR;
}
/* Check for the Timeout */
- if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout))
+ if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- hi2c->State= HAL_I2C_STATE_READY;
+ hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
@@ -4559,38 +4581,49 @@
*/
static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
- while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
+ while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
{
/* Check if a NACK is detected */
- if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
+ if (I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
{
return HAL_ERROR;
}
/* Check if a STOPF is detected */
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
{
- /* Clear STOP Flag */
- __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
-
- /* Clear Configuration Register 2 */
- I2C_RESET_CR2(hi2c);
-
- hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
- hi2c->State= HAL_I2C_STATE_READY;
- hi2c->Mode = HAL_I2C_MODE_NONE;
-
- /* Process Unlocked */
- __HAL_UNLOCK(hi2c);
-
- return HAL_ERROR;
+ /* Check if an RXNE is pending */
+ /* Store Last receive data if any */
+ if ((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET) && (hi2c->XferSize > 0U))
+ {
+ /* Return HAL_OK */
+ /* The Reading of data from RXDR will be done in caller function */
+ return HAL_OK;
+ }
+ else
+ {
+ /* Clear STOP Flag */
+ __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
+
+ /* Clear Configuration Register 2 */
+ I2C_RESET_CR2(hi2c);
+
+ hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
+ hi2c->State = HAL_I2C_STATE_READY;
+ hi2c->Mode = HAL_I2C_MODE_NONE;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hi2c);
+
+ return HAL_ERROR;
+ }
}
/* Check for the Timeout */
- if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout))
+ if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
{
hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
- hi2c->State= HAL_I2C_STATE_READY;
+ hi2c->State = HAL_I2C_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hi2c);
@@ -4611,18 +4644,18 @@
*/
static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
{
- if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
+ if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
{
/* Wait until STOP Flag is reset */
/* AutoEnd should be initiate after AF */
- while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
+ while (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
{
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout))
+ if ((Timeout == 0U) || ((HAL_GetTick() - Tickstart) > Timeout))
{
- hi2c->State= HAL_I2C_STATE_READY;
+ hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
@@ -4645,7 +4678,7 @@
I2C_RESET_CR2(hi2c);
hi2c->ErrorCode = HAL_I2C_ERROR_AF;
- hi2c->State= HAL_I2C_STATE_READY;
+ hi2c->State = HAL_I2C_STATE_READY;
hi2c->Mode = HAL_I2C_MODE_NONE;
/* Process Unlocked */
@@ -4677,25 +4710,14 @@
*/
static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
{
- uint32_t tmpreg = 0U;
-
/* Check the parameters */
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_TRANSFER_MODE(Mode));
assert_param(IS_TRANSFER_REQUEST(Request));
- /* Get the CR2 register value */
- tmpreg = hi2c->Instance->CR2;
-
- /* clear tmpreg specific bits */
- tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP));
-
- /* update tmpreg */
- tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16 ) & I2C_CR2_NBYTES) | \
- (uint32_t)Mode | (uint32_t)Request);
-
/* update CR2 register */
- hi2c->Instance->CR2 = tmpreg;
+ MODIFY_REG(hi2c->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP)), \
+ (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));
}
/**
@@ -4709,28 +4731,28 @@
{
uint32_t tmpisr = 0U;
- if((hi2c->XferISR == I2C_Master_ISR_DMA) || \
- (hi2c->XferISR == I2C_Slave_ISR_DMA))
+ if ((hi2c->XferISR == I2C_Master_ISR_DMA) || \
+ (hi2c->XferISR == I2C_Slave_ISR_DMA))
{
- if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+ if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
{
/* Enable ERR, STOP, NACK and ADDR interrupts */
tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
}
- if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
+ if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
{
/* Enable ERR and NACK interrupts */
tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
}
- if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
+ if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
{
/* Enable STOP interrupts */
tmpisr |= I2C_IT_STOPI;
}
-
- if((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
+
+ if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
{
/* Enable TC interrupts */
tmpisr |= I2C_IT_TCI;
@@ -4738,31 +4760,31 @@
}
else
{
- if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+ if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
{
/* Enable ERR, STOP, NACK, and ADDR interrupts */
tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
}
- if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
+ if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
{
/* Enable ERR, TC, STOP, NACK and RXI interrupts */
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
}
- if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
+ if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
{
/* Enable ERR, TC, STOP, NACK and TXI interrupts */
tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
}
- if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
+ if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
{
/* Enable STOP interrupts */
tmpisr |= I2C_IT_STOPI;
}
}
-
+
/* Enable interrupts only at the end */
/* to avoid the risk of I2C interrupt handle execution before */
/* all interrupts requested done */
@@ -4782,49 +4804,49 @@
{
uint32_t tmpisr = 0U;
- if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
+ if ((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
{
/* Disable TC and TXI interrupts */
tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
- if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN)
+ if ((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN)
{
/* Disable NACK and STOP interrupts */
tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
}
}
- if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
+ if ((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
{
/* Disable TC and RXI interrupts */
tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
- if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN)
+ if ((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN)
{
/* Disable NACK and STOP interrupts */
tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
}
}
- if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
+ if ((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
{
/* Disable ADDR, NACK and STOP interrupts */
tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
}
- if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
+ if ((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
{
/* Enable ERR and NACK interrupts */
tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
}
- if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
+ if ((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
{
/* Enable STOP interrupts */
tmpisr |= I2C_IT_STOPI;
}
-
- if((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
+
+ if ((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
{
/* Enable TC interrupts */
tmpisr |= I2C_IT_TCI;
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2c.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2c.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_i2c.h
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief Header file of I2C HAL module.
******************************************************************************
* @attention
@@ -40,11 +38,11 @@
#define __STM32F7xx_HAL_I2C_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
-#include "stm32f7xx_hal_def.h"
+#include "stm32f7xx_hal_def.h"
/** @addtogroup STM32F7xx_HAL_Driver
* @{
@@ -52,7 +50,7 @@
/** @addtogroup I2C
* @{
- */
+ */
/* Exported types ------------------------------------------------------------*/
/** @defgroup I2C_Exported_Types I2C Exported Types
@@ -60,13 +58,13 @@
*/
/** @defgroup I2C_Configuration_Structure_definition I2C Configuration Structure definition
- * @brief I2C Configuration Structure definition
+ * @brief I2C Configuration Structure definition
* @{
*/
typedef struct
{
uint32_t Timing; /*!< Specifies the I2C_TIMINGR_register value.
- This parameter calculated by referring to I2C initialization
+ This parameter calculated by referring to I2C initialization
section in Reference manual */
uint32_t OwnAddress1; /*!< Specifies the first device own address.
@@ -90,9 +88,9 @@
uint32_t NoStretchMode; /*!< Specifies if nostretch mode is selected.
This parameter can be a value of @ref I2C_NOSTRETCH_MODE */
-}I2C_InitTypeDef;
+} I2C_InitTypeDef;
-/**
+/**
* @}
*/
@@ -122,7 +120,7 @@
* 0 : Ready (no Tx operation ongoing)\n
* 1 : Busy (Tx operation ongoing)
* @{
- */
+ */
typedef enum
{
HAL_I2C_STATE_RESET = 0x00U, /*!< Peripheral is not yet Initialized */
@@ -139,7 +137,7 @@
HAL_I2C_STATE_TIMEOUT = 0xA0U, /*!< Timeout state */
HAL_I2C_STATE_ERROR = 0xE0U /*!< Error */
-}HAL_I2C_StateTypeDef;
+} HAL_I2C_StateTypeDef;
/**
* @}
@@ -170,9 +168,9 @@
HAL_I2C_MODE_SLAVE = 0x20U, /*!< I2C communication is in Slave Mode */
HAL_I2C_MODE_MEM = 0x40U /*!< I2C communication is in Memory Mode */
-}HAL_I2C_ModeTypeDef;
+} HAL_I2C_ModeTypeDef;
-/**
+/**
* @}
*/
@@ -213,7 +211,7 @@
__IO uint32_t PreviousState; /*!< I2C communication Previous state */
- HAL_StatusTypeDef (*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */
+ HAL_StatusTypeDef(*XferISR)(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources); /*!< I2C transfer IRQ handler function pointer */
DMA_HandleTypeDef *hdmatx; /*!< I2C Tx DMA handle parameters */
@@ -228,7 +226,7 @@
__IO uint32_t ErrorCode; /*!< I2C Error code */
__IO uint32_t AddrEventCount; /*!< I2C Address Event counter */
-}I2C_HandleTypeDef;
+} I2C_HandleTypeDef;
/**
* @}
*/
@@ -250,6 +248,7 @@
#define I2C_NEXT_FRAME ((uint32_t)(I2C_RELOAD_MODE | I2C_SOFTEND_MODE))
#define I2C_FIRST_AND_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
#define I2C_LAST_FRAME ((uint32_t)I2C_AUTOEND_MODE)
+#define I2C_LAST_FRAME_NO_STOP ((uint32_t)I2C_SOFTEND_MODE)
/**
* @}
*/
@@ -313,7 +312,7 @@
/**
* @}
*/
-
+
/** @defgroup I2C_XFERDIRECTION I2C Transfer Direction Master Point of View
* @{
*/
@@ -337,9 +336,9 @@
* @{
*/
#define I2C_NO_STARTSTOP (0x00000000U)
-#define I2C_GENERATE_STOP I2C_CR2_STOP
-#define I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
-#define I2C_GENERATE_START_WRITE I2C_CR2_START
+#define I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
+#define I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
+#define I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
/**
* @}
*/
@@ -431,7 +430,7 @@
* @retval None
*/
#define __HAL_I2C_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
-
+
/** @brief Check whether the specified I2C interrupt source is enabled or not.
* @param __HANDLE__ specifies the I2C Handle.
* @param __INTERRUPT__ specifies the I2C interrupt source to check.
@@ -506,7 +505,7 @@
#define __HAL_I2C_DISABLE(__HANDLE__) (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
/** @brief Generate a Non-Acknowledge I2C peripheral in Slave mode.
- * @param __HANDLE__: specifies the I2C Handle.
+ * @param __HANDLE__ specifies the I2C Handle.
* @retval None
*/
#define __HAL_I2C_GENERATE_NACK(__HANDLE__) (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
@@ -527,7 +526,7 @@
*/
/* Initialization and de-initialization functions******************************/
HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c);
-HAL_StatusTypeDef HAL_I2C_DeInit (I2C_HandleTypeDef *hi2c);
+HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c);
void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c);
/**
@@ -538,7 +537,7 @@
* @{
*/
/* IO operation functions ****************************************************/
- /******* Blocking mode: Polling */
+/******* Blocking mode: Polling */
HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout);
@@ -547,7 +546,7 @@
HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout);
HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
- /******* Non-Blocking mode: Interrupt */
+/******* Non-Blocking mode: Interrupt */
HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
@@ -563,7 +562,7 @@
HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c);
HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress);
- /******* Non-Blocking mode: DMA */
+/******* Non-Blocking mode: DMA */
HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size);
HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size);
@@ -604,11 +603,11 @@
/**
* @}
- */
+ */
/**
* @}
- */
+ */
/* Private constants ---------------------------------------------------------*/
/** @defgroup I2C_Private_Constants I2C Private Constants
@@ -617,7 +616,7 @@
/**
* @}
- */
+ */
/* Private macros ------------------------------------------------------------*/
/** @defgroup I2C_Private_Macro I2C Private Macros
@@ -661,7 +660,8 @@
((REQUEST) == I2C_FIRST_AND_NEXT_FRAME) || \
((REQUEST) == I2C_NEXT_FRAME) || \
((REQUEST) == I2C_FIRST_AND_LAST_FRAME) || \
- ((REQUEST) == I2C_LAST_FRAME))
+ ((REQUEST) == I2C_LAST_FRAME) || \
+ ((REQUEST) == I2C_LAST_FRAME_NO_STOP))
#define I2C_RESET_CR2(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
@@ -681,7 +681,7 @@
(uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
/**
* @}
- */
+ */
/* Private Functions ---------------------------------------------------------*/
/** @defgroup I2C_Private_Functions I2C Private Functions
@@ -690,15 +690,15 @@
/* Private functions are defined in stm32f7xx_hal_i2c.c file */
/**
* @}
- */
+ */
/**
* @}
- */
+ */
/**
* @}
- */
+ */
#ifdef __cplusplus
}
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2c_ex.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2c_ex.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,10 +2,8 @@
******************************************************************************
* @file stm32f7xx_hal_i2c_ex.c
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief I2C Extended HAL module driver.
- * This file provides firmware functions to manage the following
+ * This file provides firmware functions to manage the following
* functionalities of I2C Extended peripheral:
* + Extended features functions
*
@@ -93,7 +91,7 @@
##### Extended features functions #####
===============================================================================
[..] This section provides functions allowing to:
- (+) Configure Noise Filters
+ (+) Configure Noise Filters
(+) Configure Fast Mode Plus
@endverbatim
@@ -113,7 +111,7 @@
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_ANALOG_FILTER(AnalogFilter));
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
@@ -159,7 +157,7 @@
assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
assert_param(IS_I2C_DIGITAL_FILTER(DigitalFilter));
- if(hi2c->State == HAL_I2C_STATE_READY)
+ if (hi2c->State == HAL_I2C_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hi2c);
@@ -196,7 +194,7 @@
}
}
-#if defined(SYSCFG_PMC_I2C1_FMP)
+#if (defined(SYSCFG_PMC_I2C_PB6_FMP) || defined(SYSCFG_PMC_I2C_PB7_FMP)) || (defined(SYSCFG_PMC_I2C_PB8_FMP) || defined(SYSCFG_PMC_I2C_PB9_FMP)) || (defined(SYSCFG_PMC_I2C1_FMP)) || (defined(SYSCFG_PMC_I2C2_FMP)) || defined(SYSCFG_PMC_I2C3_FMP) || defined(SYSCFG_PMC_I2C4_FMP)
/**
* @brief Enable the I2C fast mode plus driving capability.
* @param ConfigFastModePlus Selects the pin.
@@ -254,7 +252,8 @@
/* Disable fast mode plus driving capability for selected pin */
CLEAR_BIT(SYSCFG->PMC, (uint32_t)ConfigFastModePlus);
}
-#endif /* SYSCFG_PMC_I2C1_FMP */
+
+#endif
/**
* @}
*/
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2c_ex.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2c_ex.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_i2c_ex.h
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief Header file of I2C HAL Extended module.
******************************************************************************
* @attention
@@ -40,7 +38,7 @@
#define __STM32F7xx_HAL_I2C_EX_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -52,7 +50,7 @@
/** @addtogroup I2CEx
* @{
- */
+ */
/* Exported types ------------------------------------------------------------*/
/* Exported constants --------------------------------------------------------*/
@@ -114,7 +112,7 @@
/**
* @}
- */
+ */
/* Exported macro ------------------------------------------------------------*/
/* Exported functions --------------------------------------------------------*/
@@ -131,10 +129,10 @@
/* Peripheral Control functions ************************************************/
HAL_StatusTypeDef HAL_I2CEx_ConfigAnalogFilter(I2C_HandleTypeDef *hi2c, uint32_t AnalogFilter);
HAL_StatusTypeDef HAL_I2CEx_ConfigDigitalFilter(I2C_HandleTypeDef *hi2c, uint32_t DigitalFilter);
-#if defined(SYSCFG_PMC_I2C1_FMP)
+#if (defined(SYSCFG_PMC_I2C_PB6_FMP) || defined(SYSCFG_PMC_I2C_PB7_FMP)) || (defined(SYSCFG_PMC_I2C_PB8_FMP) || defined(SYSCFG_PMC_I2C_PB9_FMP)) || (defined(SYSCFG_PMC_I2C1_FMP)) || (defined(SYSCFG_PMC_I2C2_FMP)) || defined(SYSCFG_PMC_I2C3_FMP) || defined(SYSCFG_PMC_I2C4_FMP)
void HAL_I2CEx_EnableFastModePlus(uint32_t ConfigFastModePlus);
void HAL_I2CEx_DisableFastModePlus(uint32_t ConfigFastModePlus);
-#endif /* SYSCFG_PMC_I2C1_FMP */
+#endif
/* Private constants ---------------------------------------------------------*/
/** @defgroup I2CEx_Private_Constants I2C Extended Private Constants
@@ -154,7 +152,7 @@
#define IS_I2C_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
-#if defined(SYSCFG_PMC_I2C1_FMP) && defined(SYSCFG_PMC_I2C2_FMP) && defined(SYSCFG_PMC_I2C3_FMP) && defined(SYSCFG_PMC_I2C4_FMP)
+#if defined(SYSCFG_PMC_I2C1_FMP) && defined(SYSCFG_PMC_I2C2_FMP) && defined(SYSCFG_PMC_I2C3_FMP) && defined(SYSCFG_PMC_I2C4_FMP)
#define IS_I2C_FASTMODEPLUS(__CONFIG__) ((((__CONFIG__) & I2C_FASTMODEPLUS_PB6) == I2C_FASTMODEPLUS_PB6) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_PB7) == I2C_FASTMODEPLUS_PB7) || \
(((__CONFIG__) & I2C_FASTMODEPLUS_PB8) == I2C_FASTMODEPLUS_PB8) || \
@@ -187,7 +185,7 @@
#endif /* SYSCFG_PMC_I2C1_FMP && SYSCFG_PMC_I2C2_FMP && SYSCFG_PMC_I2C3_FMP && SYSCFG_PMC_I2C4_FMP */
/**
* @}
- */
+ */
/* Private Functions ---------------------------------------------------------*/
/** @defgroup I2CEx_Private_Functions I2C Extended Private Functions
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2s.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2s.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_i2s.c
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief I2S HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Integrated Interchip Sound (I2S) peripheral:
@@ -209,7 +207,7 @@
/**
* @brief Initializes the I2S according to the specified parameters
* in the I2S_InitTypeDef and create the associated handle.
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval HAL status
*/
@@ -342,7 +340,7 @@
/**
* @brief DeInitializes the I2S peripheral
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval HAL status
*/
@@ -373,7 +371,7 @@
/**
* @brief I2S MSP Init
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval None
*/
@@ -389,7 +387,7 @@
/**
* @brief I2S MSP DeInit
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval None
*/
@@ -451,15 +449,15 @@
/**
* @brief Transmit an amount of data in blocking mode
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
- * @param pData: a 16-bit pointer to data buffer.
- * @param Size: number of data sample to be sent:
+ * @param pData a 16-bit pointer to data buffer.
+ * @param Size number of data sample to be sent:
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
* configuration phase, the Size parameter means the number of 16-bit data length
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
* the Size parameter means the number of 16-bit data length.
- * @param Timeout: Timeout duration
+ * @param Timeout Timeout duration
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
* between Master and Slave(example: audio streaming).
* @retval HAL status
@@ -556,15 +554,15 @@
/**
* @brief Receive an amount of data in blocking mode
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
- * @param pData: a 16-bit pointer to data buffer.
- * @param Size: number of data sample to be sent:
+ * @param pData a 16-bit pointer to data buffer.
+ * @param Size number of data sample to be sent:
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
* configuration phase, the Size parameter means the number of 16-bit data length
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
* the Size parameter means the number of 16-bit data length.
- * @param Timeout: Timeout duration
+ * @param Timeout Timeout duration
* @note The I2S is kept enabled at the end of transaction to avoid the clock de-synchronization
* between Master and Slave(example: audio streaming).
* @note In I2S Master Receiver mode, just after enabling the peripheral the clock will be generate
@@ -659,10 +657,10 @@
/**
* @brief Transmit an amount of data in non-blocking mode with Interrupt
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
- * @param pData: a 16-bit pointer to data buffer.
- * @param Size: number of data sample to be sent:
+ * @param pData a 16-bit pointer to data buffer.
+ * @param Size number of data sample to be sent:
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
* configuration phase, the Size parameter means the number of 16-bit data length
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
@@ -722,10 +720,10 @@
/**
* @brief Receive an amount of data in non-blocking mode with Interrupt
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
- * @param pData: a 16-bit pointer to the Receive data buffer.
- * @param Size: number of data sample to be sent:
+ * @param pData a 16-bit pointer to the Receive data buffer.
+ * @param Size number of data sample to be sent:
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
* configuration phase, the Size parameter means the number of 16-bit data length
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
@@ -786,10 +784,10 @@
/**
* @brief Transmit an amount of data in non-blocking mode with DMA
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
- * @param pData: a 16-bit pointer to the Transmit data buffer.
- * @param Size: number of data sample to be sent:
+ * @param pData a 16-bit pointer to the Transmit data buffer.
+ * @param Size number of data sample to be sent:
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
* configuration phase, the Size parameter means the number of 16-bit data length
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
@@ -864,10 +862,10 @@
/**
* @brief Receive an amount of data in non-blocking mode with DMA
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
- * @param pData: a 16-bit pointer to the Receive data buffer.
- * @param Size: number of data sample to be sent:
+ * @param pData a 16-bit pointer to the Receive data buffer.
+ * @param Size number of data sample to be sent:
* @note When a 16-bit data frame or a 16-bit data frame extended is selected during the I2S
* configuration phase, the Size parameter means the number of 16-bit data length
* in the transaction and when a 24-bit data frame or a 32-bit data frame is selected
@@ -949,7 +947,7 @@
/**
* @brief Pauses the audio stream playing from the Media.
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval HAL status
*/
@@ -990,7 +988,7 @@
/**
* @brief Resumes the audio stream playing from the Media.
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval HAL status
*/
@@ -1025,7 +1023,7 @@
/**
* @brief Stops the audio stream playing from the Media.
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval HAL status
*/
@@ -1066,7 +1064,7 @@
/**
* @brief This function handles I2S interrupt request.
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval HAL status
*/
@@ -1133,11 +1131,11 @@
*/
/**
* @brief This function handles I2S Communication Timeout.
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
- * @param Flag: Flag checked
- * @param State: Value of the flag expected
- * @param Timeout: Duration of the timeout
+ * @param Flag Flag checked
+ * @param State Value of the flag expected
+ * @param Timeout Duration of the timeout
* @retval HAL status
*/
static HAL_StatusTypeDef I2S_WaitFlagStateUntilTimeout(I2S_HandleTypeDef *hi2s, uint32_t Flag,
@@ -1202,7 +1200,7 @@
*/
/**
* @brief Tx Transfer Half completed callbacks
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval None
*/
@@ -1218,7 +1216,7 @@
/**
* @brief Tx Transfer completed callbacks
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval None
*/
@@ -1234,7 +1232,7 @@
/**
* @brief Rx Transfer half completed callbacks
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval None
*/
@@ -1250,7 +1248,7 @@
/**
* @brief Rx Transfer completed callbacks
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval None
*/
@@ -1266,7 +1264,7 @@
/**
* @brief I2S error callbacks
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval None
*/
@@ -1301,7 +1299,7 @@
/**
* @brief Return the I2S state
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval HAL state
*/
@@ -1312,7 +1310,7 @@
/**
* @brief Return the I2S error code
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval I2S Error Code
*/
@@ -1330,7 +1328,7 @@
/**
* @brief Get I2S Input Clock based on I2S source clock selection
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module.
* @retval I2S Clock Input
*/
@@ -1389,7 +1387,7 @@
*/
/**
* @brief DMA I2S transmit process complete callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -1421,7 +1419,7 @@
/**
* @brief DMA I2S transmit process half complete callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -1434,7 +1432,7 @@
/**
* @brief DMA I2S receive process complete callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -1465,7 +1463,7 @@
/**
* @brief DMA I2S receive process half complete callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -1478,7 +1476,7 @@
/**
* @brief DMA I2S communication error callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -1500,7 +1498,7 @@
/**
* @brief Transmit an amount of data in non-blocking mode with Interrupt
- * @param hi2s: pointer to a I2S_HandleTypeDef structure that contains
+ * @param hi2s pointer to a I2S_HandleTypeDef structure that contains
* the configuration information for I2S module
* @retval None
*/
@@ -1522,7 +1520,7 @@
/**
* @brief Receive an amount of data in non-blocking mode with Interrupt
- * @param hi2s: I2S handle
+ * @param hi2s I2S handle
* @retval None
*/
static void I2S_Receive_IT(I2S_HandleTypeDef *hi2s)
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2s.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_i2s.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_i2s.h
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief Header file of I2S HAL module.
******************************************************************************
* @attention
@@ -277,21 +275,21 @@
*/
/** @brief Reset I2S handle state
- * @param __HANDLE__: specifies the I2S handle.
+ * @param __HANDLE__ specifies the I2S handle.
* @retval None
*/
#define __HAL_I2S_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_I2S_STATE_RESET)
/** @brief Enable or disable the specified SPI peripheral (in I2S mode).
- * @param __HANDLE__: specifies the I2S Handle.
+ * @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2S_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR |= SPI_I2SCFGR_I2SE)
#define __HAL_I2S_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->I2SCFGR &= ~SPI_I2SCFGR_I2SE)
/** @brief Enable or disable the specified I2S interrupts.
- * @param __HANDLE__: specifies the I2S Handle.
- * @param __INTERRUPT__: specifies the interrupt source to enable or disable.
+ * @param __HANDLE__ specifies the I2S Handle.
+ * @param __INTERRUPT__ specifies the interrupt source to enable or disable.
* This parameter can be one of the following values:
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
@@ -302,9 +300,9 @@
#define __HAL_I2S_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= ~(__INTERRUPT__))
/** @brief Checks if the specified I2S interrupt source is enabled or disabled.
- * @param __HANDLE__: specifies the I2S Handle.
+ * @param __HANDLE__ specifies the I2S Handle.
* This parameter can be I2S where x: 1, 2, or 3 to select the I2S peripheral.
- * @param __INTERRUPT__: specifies the I2S interrupt source to check.
+ * @param __INTERRUPT__ specifies the I2S interrupt source to check.
* This parameter can be one of the following values:
* @arg I2S_IT_TXE: Tx buffer empty interrupt enable
* @arg I2S_IT_RXNE: RX buffer not empty interrupt enable
@@ -314,8 +312,8 @@
#define __HAL_I2S_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
/** @brief Checks whether the specified I2S flag is set or not.
- * @param __HANDLE__: specifies the I2S Handle.
- * @param __FLAG__: specifies the flag to check.
+ * @param __HANDLE__ specifies the I2S Handle.
+ * @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg I2S_FLAG_RXNE: Receive buffer not empty flag
* @arg I2S_FLAG_TXE: Transmit buffer empty flag
@@ -329,7 +327,7 @@
#define __HAL_I2S_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
/** @brief Clears the I2S OVR pending flag.
- * @param __HANDLE__: specifies the I2S Handle.
+ * @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2S_CLEAR_OVRFLAG(__HANDLE__) \
@@ -341,7 +339,7 @@
} while(0)
/** @brief Clears the I2S UDR pending flag.
- * @param __HANDLE__: specifies the I2S Handle.
+ * @param __HANDLE__ specifies the I2S Handle.
* @retval None
*/
#define __HAL_I2S_CLEAR_UDRFLAG(__HANDLE__) \
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_irda.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_irda.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_irda.c * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief IRDA HAL module driver. * This file provides firmware functions to manage the following * functionalities of the IrDA (Infrared Data Association) Peripheral @@ -229,7 +227,7 @@ /** * @brief Initialize the IRDA mode according to the specified * parameters in the IRDA_InitTypeDef and initialize the associated handle. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval HAL status */ @@ -282,7 +280,7 @@ /** * @brief DeInitialize the IRDA peripheral. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval HAL status */ @@ -316,7 +314,7 @@ /** * @brief Initialize the IRDA MSP. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval None */ @@ -332,7 +330,7 @@ /** * @brief DeInitialize the IRDA MSP. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval None */ @@ -1530,7 +1528,7 @@ /** * @brief Rx Half Transfer complete callback. - * @param hirda: Pointer to a IRDA_HandleTypeDef structure that contains + * @param hirda Pointer to a IRDA_HandleTypeDef structure that contains * the configuration information for the specified IRDA module. * @retval None */ @@ -1885,7 +1883,7 @@ /** * @brief DMA IRDA receive process complete callback. - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */ @@ -1915,7 +1913,7 @@ /** * @brief DMA IRDA receive process half complete callback. - * @param hdma: Pointer to a DMA_HandleTypeDef structure that contains + * @param hdma Pointer to a DMA_HandleTypeDef structure that contains * the configuration information for the specified DMA module. * @retval None */
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_irda.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_irda.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_irda.h
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief Header file of IRDA HAL module.
******************************************************************************
* @attention
@@ -396,14 +394,14 @@
*/
/** @brief Reset IRDA handle state
- * @param __HANDLE__: specifies the IRDA Handle.
+ * @param __HANDLE__ specifies the IRDA Handle.
* The Handle Instance which can be USART1 or USART2.
* @retval None
*/
#define __HAL_IRDA_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_IRDA_STATE_RESET)
/** @brief Flush the IRDA DR register.
- * @param __HANDLE__: specifies the IRDA Handle.
+ * @param __HANDLE__ specifies the IRDA Handle.
* @retval None
*/
#define __HAL_IRDA_FLUSH_DRREGISTER(__HANDLE__) \
@@ -413,8 +411,8 @@
} while(0)
/** @brief Clear the specified IRDA pending flag.
- * @param __HANDLE__: specifies the IRDA Handle.
- * @param __FLAG__: specifies the flag to check.
+ * @param __HANDLE__ specifies the IRDA Handle.
+ * @param __FLAG__ specifies the flag to check.
* This parameter can be any combination of the following values:
* @arg @ref IRDA_CLEAR_PEF
* @arg @ref IRDA_CLEAR_FEF
@@ -426,41 +424,41 @@
#define __HAL_IRDA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
/** @brief Clear the IRDA PE pending flag.
- * @param __HANDLE__: specifies the IRDA Handle.
+ * @param __HANDLE__ specifies the IRDA Handle.
* @retval None
*/
#define __HAL_IRDA_CLEAR_PEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_PEF)
/** @brief Clear the IRDA FE pending flag.
- * @param __HANDLE__: specifies the IRDA Handle.
+ * @param __HANDLE__ specifies the IRDA Handle.
* @retval None
*/
#define __HAL_IRDA_CLEAR_FEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_FEF)
/** @brief Clear the IRDA NE pending flag.
- * @param __HANDLE__: specifies the IRDA Handle.
+ * @param __HANDLE__ specifies the IRDA Handle.
* @retval None
*/
#define __HAL_IRDA_CLEAR_NEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_NEF)
/** @brief Clear the IRDA ORE pending flag.
- * @param __HANDLE__: specifies the IRDA Handle.
+ * @param __HANDLE__ specifies the IRDA Handle.
* @retval None
*/
#define __HAL_IRDA_CLEAR_OREFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_OREF)
/** @brief Clear the IRDA IDLE pending flag.
- * @param __HANDLE__: specifies the IRDA Handle.
+ * @param __HANDLE__ specifies the IRDA Handle.
* @retval None
*/
#define __HAL_IRDA_CLEAR_IDLEFLAG(__HANDLE__) __HAL_IRDA_CLEAR_FLAG((__HANDLE__), IRDA_CLEAR_IDLEF)
/** @brief Check whether the specified IRDA flag is set or not.
- * @param __HANDLE__: specifies the IRDA Handle.
+ * @param __HANDLE__ specifies the IRDA Handle.
* The Handle Instance which can be USART1 or USART2.
* UART peripheral
- * @param __FLAG__: specifies the flag to check.
+ * @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg IRDA_FLAG_REACK: Receive enable acknowledge flag
* @arg IRDA_FLAG_TEACK: Transmit enable acknowledge flag
@@ -480,10 +478,10 @@
#define __HAL_IRDA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
/** @brief Enable the specified IRDA interrupt.
- * @param __HANDLE__: specifies the IRDA Handle.
+ * @param __HANDLE__ specifies the IRDA Handle.
* The Handle Instance which can be USART1 or USART2.
* UART peripheral
- * @param __INTERRUPT__: specifies the IRDA interrupt source to enable.
+ * @param __INTERRUPT__ specifies the IRDA interrupt source to enable.
* This parameter can be one of the following values:
* @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
* @arg IRDA_IT_TC: Transmission complete interrupt
@@ -498,9 +496,9 @@
((__HANDLE__)->Instance->CR3 |= (1 << ((__INTERRUPT__) & IRDA_IT_MASK))))
/** @brief Disable the specified IRDA interrupt.
- * @param __HANDLE__: specifies the IRDA Handle.
+ * @param __HANDLE__ specifies the IRDA Handle.
* The Handle Instance which can be USART1 or USART2.
- * @param __INTERRUPT__: specifies the IRDA interrupt source to disable.
+ * @param __INTERRUPT__ specifies the IRDA interrupt source to disable.
* This parameter can be one of the following values:
* @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
* @arg IRDA_IT_TC: Transmission complete interrupt
@@ -515,9 +513,9 @@
((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1 << ((__INTERRUPT__) & IRDA_IT_MASK))))
/** @brief Check whether the specified IRDA interrupt has occurred or not.
- * @param __HANDLE__: specifies the IRDA Handle.
+ * @param __HANDLE__ specifies the IRDA Handle.
* The Handle Instance which can be USART1 or USART2.
- * @param __IT__: specifies the IRDA interrupt source to check.
+ * @param __IT__ specifies the IRDA interrupt source to check.
* This parameter can be one of the following values:
* @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
* @arg IRDA_IT_TC: Transmission complete interrupt
@@ -532,9 +530,9 @@
#define __HAL_IRDA_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
/** @brief Check whether the specified IRDA interrupt source is enabled.
- * @param __HANDLE__: specifies the IRDA Handle.
+ * @param __HANDLE__ specifies the IRDA Handle.
* The Handle Instance which can be USART1 or USART2.
- * @param __IT__: specifies the IRDA interrupt source to check.
+ * @param __IT__ specifies the IRDA interrupt source to check.
* This parameter can be one of the following values:
* @arg IRDA_IT_TXE: Transmit Data Register empty interrupt
* @arg IRDA_IT_TC: Transmission complete interrupt
@@ -550,9 +548,9 @@
(__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & IRDA_IT_MASK)))
/** @brief Clear the specified IRDA ISR flag, in setting the proper ICR register flag.
- * @param __HANDLE__: specifies the IRDA Handle.
+ * @param __HANDLE__ specifies the IRDA Handle.
* The Handle Instance which can be USART1 or USART2.
- * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
+ * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
* to clear the corresponding interrupt
* This parameter can be one of the following values:
* @arg IRDA_CLEAR_PEF: Parity Error Clear Flag
@@ -565,9 +563,9 @@
#define __HAL_IRDA_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR |= (uint32_t)(__IT_CLEAR__))
/** @brief Set a specific IRDA request flag.
- * @param __HANDLE__: specifies the IRDA Handle.
+ * @param __HANDLE__ specifies the IRDA Handle.
* The Handle Instance which can be USART1 or USART2.
- * @param __REQ__: specifies the request flag to set
+ * @param __REQ__ specifies the request flag to set
* This parameter can be one of the following values:
* @arg IRDA_AUTOBAUD_REQUEST: Auto-Baud Rate Request
* @arg IRDA_RXDATA_FLUSH_REQUEST: Receive Data flush Request
@@ -578,14 +576,14 @@
#define __HAL_IRDA_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
/** @brief Enable UART/USART associated to IRDA Handle
- * @param __HANDLE__: specifies the IRDA Handle.
+ * @param __HANDLE__ specifies the IRDA Handle.
* The Handle Instance which can be USART1 or USART2.
* @retval None
*/
#define __HAL_IRDA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
/** @brief Disable UART/USART associated to IRDA Handle
- * @param __HANDLE__: specifies the IRDA Handle.
+ * @param __HANDLE__ specifies the IRDA Handle.
* The Handle Instance which can be USART1 or USART2.
* @retval None
*/
@@ -690,13 +688,13 @@
*/
/** @brief Ensure that IRDA Baud rate is less or equal to maximum value
- * @param __BAUDRATE__: specifies the IRDA Baudrate set by the user.
+ * @param __BAUDRATE__ specifies the IRDA Baudrate set by the user.
* @retval True or False
*/
#define IS_IRDA_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) < 115201)
/** @brief Ensure that IRDA prescaler value is strictly larger than 0
- * @param __PRESCALER__: specifies the IRDA prescaler value set by the user.
+ * @param __PRESCALER__ specifies the IRDA prescaler value set by the user.
* @retval True or False
*/
#define IS_IRDA_PRESCALER(__PRESCALER__) ((__PRESCALER__) > 0)
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_irda_ex.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_irda_ex.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_irda_ex.h
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief Header file of IRDA HAL Extension module.
******************************************************************************
* @attention
@@ -83,8 +81,8 @@
* @{
*/
/** @brief Reports the IRDA clock source.
- * @param __HANDLE__: specifies the IRDA Handle
- * @param __CLOCKSOURCE__ : output variable
+ * @param __HANDLE__ specifies the IRDA Handle
+ * @param __CLOCKSOURCE__ output variable
* @retval IRDA clocking source, written in __CLOCKSOURCE__.
*/
#define IRDA_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
@@ -173,7 +171,7 @@
/** @brief Reports the mask to apply to retrieve the received data
* according to the word length and to the parity bits activation.
- * @param __HANDLE__: specifies the IRDA Handle
+ * @param __HANDLE__ specifies the IRDA Handle
* @retval mask to apply to USART RDR register value.
*/
#define IRDA_MASK_COMPUTATION(__HANDLE__) \
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_iwdg.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_iwdg.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_iwdg.c * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief IWDG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Independent Watchdog (IWDG) peripheral:
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_iwdg.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_iwdg.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_iwdg.h * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief Header file of IWDG HAL module. ****************************************************************************** * @attention @@ -128,7 +126,7 @@ /** * @brief Enable the IWDG peripheral. - * @param __HANDLE__: IWDG handle + * @param __HANDLE__ IWDG handle * @retval None */ #define __HAL_IWDG_START(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_ENABLE) @@ -136,7 +134,7 @@ /** * @brief Reload IWDG counter with value defined in the reload register * (write access to IWDG_PR, IWDG_RLR & IWDG_WINR registers disabled). - * @param __HANDLE__: IWDG handle + * @param __HANDLE__ IWDG handle * @retval None */ #define __HAL_IWDG_RELOAD_COUNTER(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_RELOAD) @@ -196,21 +194,21 @@ /** * @brief Enable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers. - * @param __HANDLE__: IWDG handle + * @param __HANDLE__ IWDG handle * @retval None */ #define IWDG_ENABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_ENABLE) /** * @brief Disable write access to IWDG_PR, IWDG_RLR and IWDG_WINR registers. - * @param __HANDLE__: IWDG handle + * @param __HANDLE__ IWDG handle * @retval None */ #define IWDG_DISABLE_WRITE_ACCESS(__HANDLE__) WRITE_REG((__HANDLE__)->Instance->KR, IWDG_KEY_WRITE_ACCESS_DISABLE) /** * @brief Check IWDG prescaler value. - * @param __PRESCALER__: IWDG prescaler value + * @param __PRESCALER__ IWDG prescaler value * @retval None */ #define IS_IWDG_PRESCALER(__PRESCALER__) (((__PRESCALER__) == IWDG_PRESCALER_4) || \ @@ -223,14 +221,14 @@ /** * @brief Check IWDG reload value. - * @param __RELOAD__: IWDG reload value + * @param __RELOAD__ IWDG reload value * @retval None */ #define IS_IWDG_RELOAD(__RELOAD__) ((__RELOAD__) <= IWDG_RLR_RL) /** * @brief Check IWDG window value. - * @param __WINDOW__: IWDG window value + * @param __WINDOW__ IWDG window value * @retval None */ #define IS_IWDG_WINDOW(__WINDOW__) ((__WINDOW__) <= IWDG_WINR_WIN)
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_jpeg.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_jpeg.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_jpeg.c * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief JPEG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the JPEG encoder/decoder peripheral: @@ -469,7 +467,7 @@ /** * @brief Initializes the JPEG according to the specified * parameters in the JPEG_InitTypeDef and creates the associated handle. - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module * @retval HAL status */ @@ -554,7 +552,7 @@ /** * @brief DeInitializes the JPEG peripheral. - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module * @retval HAL status */ @@ -594,7 +592,7 @@ /** * @brief Initializes the JPEG MSP. - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module * @retval None */ @@ -610,7 +608,7 @@ /** * @brief DeInitializes JPEG MSP. - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module * @retval None */ @@ -648,9 +646,9 @@ /** * @brief Set the JPEG encoding configuration. - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module - * @param pConf: pointer to a JPEG_ConfTypeDef structure that contains + * @param pConf pointer to a JPEG_ConfTypeDef structure that contains * the encoding configuration * @retval HAL status */ @@ -829,9 +827,9 @@ /** * @brief Extract the image configuration from the JPEG header during the decoding - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module - * @param pInfo: pointer to a JPEG_ConfTypeDef structure that contains + * @param pInfo pointer to a JPEG_ConfTypeDef structure that contains * The JPEG decoded header informations * @retval HAL status */ @@ -898,7 +896,7 @@ /** * @brief Enable JPEG Header parsing for decoding - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for the JPEG. * @retval HAL status */ @@ -934,7 +932,7 @@ /** * @brief Disable JPEG Header parsing for decoding - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for the JPEG. * @retval HAL status */ @@ -970,15 +968,15 @@ /** * @brief Modify the default Quantization tables used for JPEG encoding. - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module - * @param QTable0 : pointer to uint8_t , define the user quantification table for color component 1. + * @param QTable0 pointer to uint8_t , define the user quantification table for color component 1. * If NULL assume no need to update the table and no error return - * @param QTable1 : pointer to uint8_t , define the user quantification table for color component 2. + * @param QTable1 pointer to uint8_t , define the user quantification table for color component 2. * If NULL assume no need to update the table and no error return. - * @param QTable2 : pointer to uint8_t , define the user quantification table for color component 3, + * @param QTable2 pointer to uint8_t , define the user quantification table for color component 3, * If NULL assume no need to update the table and no error return. - * @param QTable3 : pointer to uint8_t , define the user quantification table for color component 4. + * @param QTable3 pointer to uint8_t , define the user quantification table for color component 4. * If NULL assume no need to update the table and no error return. * * @retval HAL status @@ -1050,13 +1048,13 @@ /** * @brief Starts JPEG encoding with polling processing - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module - * @param pDataInMCU: Pointer to the Input buffer - * @param InDataLength: size in bytes Input buffer - * @param pDataOut: Pointer to the jpeg output data buffer - * @param OutDataLength: size in bytes of the Output buffer - * @param Timeout: Specify Timeout value + * @param pDataInMCU Pointer to the Input buffer + * @param InDataLength size in bytes Input buffer + * @param pDataOut Pointer to the jpeg output data buffer + * @param OutDataLength size in bytes of the Output buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_JPEG_Encode(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength, uint32_t Timeout) @@ -1156,13 +1154,13 @@ /** * @brief Starts JPEG decoding with polling processing - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module - * @param pDataIn: Pointer to the input data buffer - * @param InDataLength: size in bytes Input buffer - * @param pDataOutMCU: Pointer to the Output data buffer - * @param OutDataLength: size in bytes of the Output buffer - * @param Timeout: Specify Timeout value + * @param pDataIn Pointer to the input data buffer + * @param InDataLength size in bytes Input buffer + * @param pDataOutMCU Pointer to the Output data buffer + * @param OutDataLength size in bytes of the Output buffer + * @param Timeout Specify Timeout value * @retval HAL status */ HAL_StatusTypeDef HAL_JPEG_Decode(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,uint32_t InDataLength ,uint8_t *pDataOutMCU ,uint32_t OutDataLength, uint32_t Timeout) @@ -1254,12 +1252,12 @@ /** * @brief Starts JPEG encoding with interrupt processing - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module - * @param pDataInMCU: Pointer to the Input buffer - * @param InDataLength: size in bytes Input buffer - * @param pDataOut: Pointer to the jpeg output data buffer - * @param OutDataLength: size in bytes of the Output buffer + * @param pDataInMCU Pointer to the Input buffer + * @param InDataLength size in bytes Input buffer + * @param pDataOut Pointer to the jpeg output data buffer + * @param OutDataLength size in bytes of the Output buffer * @retval HAL status */ HAL_StatusTypeDef HAL_JPEG_Encode_IT(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength) @@ -1328,12 +1326,12 @@ /** * @brief Starts JPEG decoding with interrupt processing - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module - * @param pDataIn: Pointer to the input data buffer - * @param InDataLength: size in bytes Input buffer - * @param pDataOutMCU: Pointer to the Output data buffer - * @param OutDataLength: size in bytes of the Output buffer + * @param pDataIn Pointer to the input data buffer + * @param InDataLength size in bytes Input buffer + * @param pDataOutMCU Pointer to the Output data buffer + * @param OutDataLength size in bytes of the Output buffer * @retval HAL status */ HAL_StatusTypeDef HAL_JPEG_Decode_IT(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,uint32_t InDataLength ,uint8_t *pDataOutMCU ,uint32_t OutDataLength) @@ -1392,12 +1390,12 @@ /** * @brief Starts JPEG encoding with DMA processing - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module - * @param pDataInMCU: Pointer to the Input buffer - * @param InDataLength: size in bytes Input buffer - * @param pDataOut: Pointer to the jpeg output data buffer - * @param OutDataLength: size in bytes of the Output buffer + * @param pDataInMCU Pointer to the Input buffer + * @param InDataLength size in bytes Input buffer + * @param pDataOut Pointer to the jpeg output data buffer + * @param OutDataLength size in bytes of the Output buffer * @retval HAL status */ HAL_StatusTypeDef HAL_JPEG_Encode_DMA(JPEG_HandleTypeDef *hjpeg, uint8_t *pDataInMCU, uint32_t InDataLength, uint8_t *pDataOut, uint32_t OutDataLength) @@ -1465,12 +1463,12 @@ /** * @brief Starts JPEG decoding with DMA processing - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module - * @param pDataIn: Pointer to the input data buffer - * @param InDataLength: size in bytes Input buffer - * @param pDataOutMCU: Pointer to the Output data buffer - * @param OutDataLength: size in bytes of the Output buffer + * @param pDataIn Pointer to the input data buffer + * @param InDataLength size in bytes Input buffer + * @param pDataOutMCU Pointer to the Output data buffer + * @param OutDataLength size in bytes of the Output buffer * @retval HAL status */ HAL_StatusTypeDef HAL_JPEG_Decode_DMA(JPEG_HandleTypeDef *hjpeg ,uint8_t *pDataIn ,uint32_t InDataLength ,uint8_t *pDataOutMCU ,uint32_t OutDataLength) @@ -1528,9 +1526,9 @@ /** * @brief Pause the JPEG Input/Output processing - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module - * @param XferSelection: This parameter can be one of the following values : + * @param XferSelection This parameter can be one of the following values : * JPEG_PAUSE_RESUME_INPUT : Pause Input processing * JPEG_PAUSE_RESUME_OUTPUT: Pause Output processing * JPEG_PAUSE_RESUME_INPUT_OUTPUT: Pause Input and Output processing @@ -1580,9 +1578,9 @@ /** * @brief Resume the JPEG Input/Output processing - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module - * @param XferSelection: This parameter can be one of the following values : + * @param XferSelection This parameter can be one of the following values : * JPEG_PAUSE_RESUME_INPUT : Resume Input processing * JPEG_PAUSE_RESUME_OUTPUT: Resume Output processing * JPEG_PAUSE_RESUME_INPUT_OUTPUT: Resume Input and Output processing @@ -1661,10 +1659,10 @@ /** * @brief Config Encoding/Decoding Input Buffer. - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module. - * @param pNewInputBuffer: Pointer to the new input data buffer - * @param InDataLength: Size in bytes of the new Input data buffer + * @param pNewInputBuffer Pointer to the new input data buffer + * @param InDataLength Size in bytes of the new Input data buffer * @retval HAL status */ void HAL_JPEG_ConfigInputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewInputBuffer, uint32_t InDataLength) @@ -1675,10 +1673,10 @@ /** * @brief Config Encoding/Decoding Output Buffer. - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module. - * @param pNewOutputBuffer: Pointer to the new output data buffer - * @param OutDataLength: Size in bytes of the new Output data buffer + * @param pNewOutputBuffer Pointer to the new output data buffer + * @param OutDataLength Size in bytes of the new Output data buffer * @retval HAL status */ void HAL_JPEG_ConfigOutputBuffer(JPEG_HandleTypeDef *hjpeg, uint8_t *pNewOutputBuffer, uint32_t OutDataLength) @@ -1689,7 +1687,7 @@ /** * @brief Aborts the JPEG Encoding/Decoding. - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module * @retval HAL status */ @@ -1790,9 +1788,9 @@ /** * @brief Decoding JPEG Info ready callback. - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module - * @param pInfo: pointer to a JPEG_ConfTypeDef structure that contains + * @param pInfo pointer to a JPEG_ConfTypeDef structure that contains * The JPEG decoded header informations * @retval None */ @@ -1809,7 +1807,7 @@ /** * @brief Encoding complete callback. - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module * @retval None */ @@ -1825,7 +1823,7 @@ /** * @brief Decoding complete callback. - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module * @retval None */ @@ -1841,7 +1839,7 @@ /** * @brief JPEG error callback. - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module * @retval None */ @@ -1857,9 +1855,9 @@ /** * @brief Get New Data chunk callback. - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module - * @param NbDecodedData: Number of consummed data in the previous chunk in bytes + * @param NbDecodedData Number of consummed data in the previous chunk in bytes * @retval None */ __weak void HAL_JPEG_GetDataCallback(JPEG_HandleTypeDef *hjpeg, uint32_t NbDecodedData) @@ -1875,10 +1873,10 @@ /** * @brief Decoded/Encoded Data ready callback. - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module - * @param pDataOut: pointer to the output data buffer - * @param OutDataLength: number in bytes of data available in the specified output buffer + * @param pDataOut pointer to the output data buffer + * @param OutDataLength number in bytes of data available in the specified output buffer * @retval None */ __weak void HAL_JPEG_DataReadyCallback (JPEG_HandleTypeDef *hjpeg, uint8_t *pDataOut, uint32_t OutDataLength) @@ -1914,7 +1912,7 @@ /** * @brief This function handles JPEG interrupt request. - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module * @retval None */ @@ -1964,7 +1962,7 @@ /** * @brief Returns the JPEG state. - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module * @retval JPEG state */ @@ -1975,7 +1973,7 @@ /** * @brief Return the JPEG error code -* @param hjpeg : pointer to a JPEG_HandleTypeDef structure that contains +* @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for the specified JPEG. * @retval JPEG Error Code */ @@ -1999,10 +1997,10 @@ /** * @brief Generates Huffman sizes/Codes Table from Bits/vals Table - * @param Bits: pointer to bits table - * @param Huffsize: pointer to sizes table - * @param Huffcode: pointer to codes table - * @param LastK: pointer to last Coeff (table dimmension) + * @param Bits pointer to bits table + * @param Huffsize pointer to sizes table + * @param Huffcode pointer to codes table + * @param LastK pointer to last Coeff (table dimmension) * @retval HAL status */ static HAL_StatusTypeDef JPEG_Bits_To_SizeCodes(uint8_t *Bits, uint8_t *Huffsize, uint32_t *Huffcode, uint32_t *LastK) @@ -2053,8 +2051,8 @@ /** * @brief Transform a Bits/Vals AC Huffman table to sizes/Codes huffman Table * that can programmed to the JPEG encoder registers - * @param AC_BitsValsTable: pointer to AC huffman bits/vals table - * @param AC_SizeCodesTable: pointer to AC huffman Sizes/Codes table + * @param AC_BitsValsTable pointer to AC huffman bits/vals table + * @param AC_SizeCodesTable pointer to AC huffman Sizes/Codes table * @retval HAL status */ static HAL_StatusTypeDef JPEG_ACHuff_BitsVals_To_SizeCodes(JPEG_ACHuffTableTypeDef *AC_BitsValsTable, JPEG_AC_HuffCodeTableTypeDef *AC_SizeCodesTable) @@ -2111,8 +2109,8 @@ /** * @brief Transform a Bits/Vals DC Huffman table to sizes/Codes huffman Table * that can programmed to the JPEG encoder registers - * @param DC_BitsValsTable: pointer to DC huffman bits/vals table - * @param DC_SizeCodesTable: pointer to DC huffman Sizes/Codes table + * @param DC_BitsValsTable pointer to DC huffman bits/vals table + * @param DC_SizeCodesTable pointer to DC huffman Sizes/Codes table * @retval HAL status */ static HAL_StatusTypeDef JPEG_DCHuff_BitsVals_To_SizeCodes(JPEG_DCHuffTableTypeDef *DC_BitsValsTable, JPEG_DC_HuffCodeTableTypeDef *DC_SizeCodesTable) @@ -2153,10 +2151,10 @@ /** * @brief Set the JPEG register with an DC huffman table at the given DC table address - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module - * @param HuffTableDC: pointer to DC huffman table - * @param DCTableAddress: Encoder DC huffman table address it could be HUFFENC_DC0 or HUFFENC_DC1. + * @param HuffTableDC pointer to DC huffman table + * @param DCTableAddress Encoder DC huffman table address it could be HUFFENC_DC0 or HUFFENC_DC1. * @retval HAL status */ static HAL_StatusTypeDef JPEG_Set_HuffDC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_DCHuffTableTypeDef *HuffTableDC, uint32_t *DCTableAddress) @@ -2210,10 +2208,10 @@ /** * @brief Set the JPEG register with an AC huffman table at the given AC table address - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module - * @param HuffTableAC: pointer to AC huffman table - * @param ACTableAddress: Encoder AC huffman table address it could be HUFFENC_AC0 or HUFFENC_AC1. + * @param HuffTableAC pointer to AC huffman table + * @param ACTableAddress Encoder AC huffman table address it could be HUFFENC_AC0 or HUFFENC_AC1. * @retval HAL status */ static HAL_StatusTypeDef JPEG_Set_HuffAC_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC, uint32_t *ACTableAddress) @@ -2282,12 +2280,12 @@ /** * @brief Configure the JPEG encoder register huffman tables to used during * the encdoing operation - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module - * @param HuffTableAC0: AC0 huffman table - * @param HuffTableDC0: DC0 huffman table - * @param HuffTableAC1: AC1 huffman table - * @param HuffTableDC1: DC1 huffman table + * @param HuffTableAC0 AC0 huffman table + * @param HuffTableDC0 DC0 huffman table + * @param HuffTableAC1 AC1 huffman table + * @param HuffTableDC1 DC1 huffman table * @retval None */ static HAL_StatusTypeDef JPEG_Set_HuffEnc_Mem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC0, JPEG_DCHuffTableTypeDef *HuffTableDC0 , JPEG_ACHuffTableTypeDef *HuffTableAC1, JPEG_DCHuffTableTypeDef *HuffTableDC1) @@ -2338,12 +2336,12 @@ /** * @brief Configure the JPEG register huffman tables to be included in the JPEG * file header (used for encoding only) - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module - * @param HuffTableAC0: AC0 huffman table - * @param HuffTableDC0: DC0 huffman table - * @param HuffTableAC1: AC1 huffman table - * @param HuffTableDC1: DC1 huffman table + * @param HuffTableAC0 AC0 huffman table + * @param HuffTableDC0 DC0 huffman table + * @param HuffTableAC1 AC1 huffman table + * @param HuffTableDC1 DC1 huffman table * @retval None */ static void JPEG_Set_Huff_DHTMem(JPEG_HandleTypeDef *hjpeg, JPEG_ACHuffTableTypeDef *HuffTableAC0, JPEG_DCHuffTableTypeDef *HuffTableDC0 , JPEG_ACHuffTableTypeDef *HuffTableAC1, JPEG_DCHuffTableTypeDef *HuffTableDC1) @@ -2534,10 +2532,10 @@ /** * @brief Configure the JPEG registers with a given quantization table - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module - * @param QTable: pointer to an array of 64 bytes giving the quantization table - * @param QTableAddress: destination quantization address in the JPEG peripheral + * @param QTable pointer to an array of 64 bytes giving the quantization table + * @param QTableAddress destination quantization address in the JPEG peripheral * it could be QMEM0, QMEM1, QMEM2 or QMEM3 * @retval None */ @@ -2603,7 +2601,7 @@ /** * @brief Configure the JPEG registers for YCbCr color space - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module * @retval None */ @@ -2664,7 +2662,7 @@ /** * @brief Configure the JPEG registers for GrayScale color space - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module * @retval None */ @@ -2684,7 +2682,7 @@ /** * @brief Configure the JPEG registers for CMYK color space - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module * @retval None */ @@ -2743,7 +2741,7 @@ /** * @brief Init the JPEG encoding/decoding process in case of Polling or Interrupt and DMA - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module * @retval None */ @@ -2797,7 +2795,7 @@ /** * @brief JPEG encoding/decoding process in case of Polling or Interrupt - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module * @retval JPEG_PROCESS_DONE if the process has ends else JPEG_PROCESS_ONGOING */ @@ -2914,9 +2912,9 @@ * @brief Store some output data from the JPEG peripheral to the output buffer. * This function is used when the JPEG peripheral has new data to output * in case of Polling or Interrupt process - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module - * @param nbOutputWords: Number of output words (of 32 bits) ready from the JPEG peripheral + * @param nbOutputWords Number of output words (of 32 bits) ready from the JPEG peripheral * @retval None */ static void JPEG_StoreOutputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbOutputWords) @@ -2984,9 +2982,9 @@ * @brief Read some input Data from the input buffer. * This function is used when the JPEG peripheral needs new data * in case of Polling or Interrupt process - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module - * @param nbRequestWords: Number of input words (of 32 bits) that the JPE peripheral request + * @param nbRequestWords Number of input words (of 32 bits) that the JPE peripheral request * @retval None */ static void JPEG_ReadInputData(JPEG_HandleTypeDef *hjpeg, uint32_t nbRequestWords) @@ -3053,7 +3051,7 @@ /** * @brief Start the JPEG DMA process (encoding/decoding) - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module * @retval JPEG_PROCESS_DONE if process ends else JPEG_PROCESS_ONGOING */ @@ -3101,7 +3099,7 @@ /** * @brief Continue the current JPEG DMA process (encoding/decoding) - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module * @retval JPEG_PROCESS_DONE if process ends else JPEG_PROCESS_ONGOING */ @@ -3165,7 +3163,7 @@ /** * @brief Finalize the current JPEG DMA process (encoding/decoding) - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module * @retval JPEG_PROCESS_DONE */ @@ -3219,7 +3217,7 @@ /** * @brief Poll residual output data when DMA process (encoding/decoding) - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module * @retval None. */ @@ -3277,7 +3275,7 @@ /** * @brief DMA input transfer complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure. + * @param hdma pointer to a DMA_HandleTypeDef structure. * @retval None */ static void JPEG_DMAInCpltCallback(DMA_HandleTypeDef *hdma) @@ -3322,7 +3320,7 @@ /** * @brief DMA output transfer complete callback - * @param hdma: pointer to a DMA_HandleTypeDef structure. + * @param hdma pointer to a DMA_HandleTypeDef structure. * @retval None */ static void JPEG_DMAOutCpltCallback(DMA_HandleTypeDef *hdma) @@ -3357,7 +3355,7 @@ /** * @brief DMA Transfer error callback - * @param hdma: pointer to a DMA_HandleTypeDef structure. + * @param hdma pointer to a DMA_HandleTypeDef structure. * @retval None */ static void JPEG_DMAErrorCallback(DMA_HandleTypeDef *hdma) @@ -3384,7 +3382,7 @@ /** * @brief DMA output Abort callback - * @param hdma: pointer to a DMA_HandleTypeDef structure. + * @param hdma pointer to a DMA_HandleTypeDef structure. * @retval None */ static void JPEG_DMAOutAbortCallback(DMA_HandleTypeDef *hdma) @@ -3399,7 +3397,7 @@ /** * @brief Calculate the decoded image quality (from 1 to 100) - * @param hjpeg: pointer to a JPEG_HandleTypeDef structure that contains + * @param hjpeg pointer to a JPEG_HandleTypeDef structure that contains * the configuration information for JPEG module * @retval JPEG image quality from 1 to 100. */
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_jpeg.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_jpeg.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_jpeg.h * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief Header file of JPEG HAL module. ****************************************************************************** * @attention @@ -276,7 +274,7 @@ */ /** @brief Reset JPEG handle state - * @param __HANDLE__: specifies the JPEG handle. + * @param __HANDLE__ specifies the JPEG handle. * @retval None */ #define __HAL_JPEG_RESET_HANDLE_STATE(__HANDLE__) ( (__HANDLE__)->State = HAL_JPEG_STATE_RESET) @@ -284,14 +282,14 @@ /** * @brief Enable the JPEG peripheral. - * @param __HANDLE__: specifies the JPEG handle. + * @param __HANDLE__ specifies the JPEG handle. * @retval None */ #define __HAL_JPEG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= JPEG_CR_JCEN) /** * @brief Disable the JPEG peripheral. - * @param __HANDLE__: specifies the JPEG handle. + * @param __HANDLE__ specifies the JPEG handle. * @retval None */ #define __HAL_JPEG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~JPEG_CR_JCEN) @@ -299,8 +297,8 @@ /** * @brief Check the specified JPEG status flag. - * @param __HANDLE__: specifies the JPEG handle. - * @param __FLAG__ : specifies the flag to check + * @param __HANDLE__ specifies the JPEG handle. + * @param __FLAG__ specifies the flag to check * This parameter can be one of the following values: * @arg JPEG_FLAG_IFTF : The input FIFO is not full and is bellow its threshold flag * @arg JPEG_FLAG_IFNFF : The input FIFO Not Full Flag, a data can be written @@ -319,8 +317,8 @@ /** * @brief Clear the specified JPEG status flag. - * @param __HANDLE__: specifies the JPEG handle. - * @param __FLAG__ : specifies the flag to clear + * @param __HANDLE__ specifies the JPEG handle. + * @param __FLAG__ specifies the flag to clear * This parameter can be one of the following values: * @arg JPEG_FLAG_EOCF : JPEG Codec core has finished the encoding or the decoding process * and than last data has been sent to the output FIFO @@ -333,8 +331,8 @@ /** * @brief Enable Interrupt. - * @param __HANDLE__: specifies the JPEG handle. - * @param __INTERRUPT__ : specifies the interrupt to enable + * @param __HANDLE__ specifies the JPEG handle. + * @param __INTERRUPT__ specifies the interrupt to enable * This parameter can be one of the following values: * @arg JPEG_IT_IFT : Input FIFO Threshold Interrupt * @arg JPEG_IT_IFNF : Input FIFO Not Full Interrupt @@ -349,8 +347,8 @@ /** * @brief Disable Interrupt. - * @param __HANDLE__: specifies the JPEG handle. - * @param __INTERRUPT__ : specifies the interrupt to disable + * @param __HANDLE__ specifies the JPEG handle. + * @param __INTERRUPT__ specifies the interrupt to disable * This parameter can be one of the following values: * @arg JPEG_IT_IFT : Input FIFO Threshold Interrupt * @arg JPEG_IT_IFNF : Input FIFO Not Full Interrupt @@ -368,8 +366,8 @@ /** * @brief Get Interrupt state. - * @param __HANDLE__: specifies the JPEG handle. - * @param __INTERRUPT__ : specifies the interrupt to check + * @param __HANDLE__ specifies the JPEG handle. + * @param __INTERRUPT__ specifies the interrupt to check * This parameter can be one of the following values: * @arg JPEG_IT_IFT : Input FIFO Threshold Interrupt * @arg JPEG_IT_IFNF : Input FIFO Not Full Interrupt
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_lptim.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_lptim.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_lptim.c
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief LPTIM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Low Power Timer (LPTIM) peripheral:
@@ -89,6 +87,53 @@
(#) Call HAL_LPTIM_DeInit() to deinitialize the LPTIM peripheral.
+ *** Callback registration ***
+ =============================================
+
+ The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ Use Function @ref HAL_LPTIM_RegisterCallback() to register a callback.
+ @ref HAL_LPTIM_RegisterCallback() takes as parameters the HAL peripheral handle,
+ the Callback ID and a pointer to the user callback function.
+
+ Use function @ref HAL_LPTIM_UnRegisterCallback() to reset a callback to the default
+ weak function.
+ @ref HAL_LPTIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+
+ These functions allow to register/unregister following callbacks:
+ (+) MspInitCallback : LPTIM Msp Init Callback.
+ (+) MspDeInitCallback : LPTIM Msp DeInit Callback.
+ (+) CompareMatchCallback : LPTIM Compare Match Init Callback.
+ (+) AutoReloadMatchCallback : LPTIM Auto Reload Match Callback.
+ (+) TriggerCallback : LPTIM Trigger Callback.
+ (+) CompareWriteCallback : LPTIM Compare Write Callback.
+ (+) AutoReloadWriteCallback : LPTIM Auto Reload Write Callback.
+ (+) DirectionUpCallback : LPTIM Direction Up Callback.
+ (+) DirectionDownCallback : LPTIM Direction Down Callback.
+
+ By default, after the @ref HAL_LPTIM_Init and when the state is HAL_LPTIM_STATE_RESET
+ all interrupt callbacks are set to the corresponding weak functions:
+ examples @ref HAL_LPTIM_CompareMatchCallback(), @ref HAL_LPTIM_AutoReloadMatchCallback().
+
+ Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
+ functionalities in the @ref HAL_LPTIM_Init/@ref HAL_LPTIM_DeInit only when these
+ callbacks are null (not registered beforehand). If not, MspInit or MspDeInit are not null,
+ the @ref HAL_LPTIM_Init/@ref HAL_LPTIM_DeInit keep and use the user MspInit/MspDeInit
+ callbacks (registered beforehand)
+
+ Callbacks can be registered/unregistered in HAL_LPTIM_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_LPTIM_STATE_READY or HAL_LPTIM_STATE_RESET state, thus registered (user)
+ MspInit/DeInit callbacks can be used during the @ref HAL_LPTIM_Init/@ref HAL_LPTIM_DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks using
+ @ref HAL_LPTIM_RegisterCallback() before calling DeInit or Init function.
+
+ When The compilation define USE_HAL_LPTIM_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
+
@endverbatim
******************************************************************************
* @attention
@@ -222,7 +267,7 @@
/**
* @brief Initializes the LPTIM according to the specified parameters in the
* LPTIM_InitTypeDef and creates the associated handle.
- * @param hlptim: LPTIM handle
+ * @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_Init(LPTIM_HandleTypeDef *hlptim)
@@ -254,15 +299,33 @@
assert_param(IS_LPTIM_OUTPUT_POLARITY(hlptim->Init.OutputPolarity));
assert_param(IS_LPTIM_UPDATE_MODE(hlptim->Init.UpdateMode));
assert_param(IS_LPTIM_COUNTER_SOURCE(hlptim->Init.CounterSource));
-
+
if(hlptim->State == HAL_LPTIM_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hlptim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+ /* Reset the LPTIM callback to the legacy weak callbacks */
+ hlptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback;
+ hlptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback;
+ hlptim->TriggerCallback = HAL_LPTIM_TriggerCallback;
+ hlptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback;
+ hlptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback;
+ hlptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback;
+ hlptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback;
+
+ if(hlptim->MspInitCallback == NULL)
+ {
+ hlptim->MspInitCallback = HAL_LPTIM_MspInit;
+ }
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ hlptim->MspInitCallback(hlptim);
+#else
/* Init the low level hardware */
HAL_LPTIM_MspInit(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
}
-
/* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_BUSY;
@@ -315,7 +378,7 @@
/**
* @brief DeInitializes the LPTIM peripheral.
- * @param hlptim: LPTIM handle
+ * @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_DeInit(LPTIM_HandleTypeDef *hlptim)
@@ -331,10 +394,19 @@
/* Disable the LPTIM Peripheral Clock */
__HAL_LPTIM_DISABLE(hlptim);
-
+
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+ if(hlptim->MspDeInitCallback == NULL)
+ {
+ hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ hlptim->MspDeInitCallback(hlptim);
+#else
/* DeInit the low level hardware: CLOCK, NVIC.*/
HAL_LPTIM_MspDeInit(hlptim);
-
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+
/* Change the LPTIM state */
hlptim->State = HAL_LPTIM_STATE_RESET;
@@ -347,7 +419,7 @@
/**
* @brief Initializes the LPTIM MSP.
- * @param hlptim: LPTIM handle
+ * @param hlptim LPTIM handle
* @retval None
*/
__weak void HAL_LPTIM_MspInit(LPTIM_HandleTypeDef *hlptim)
@@ -362,7 +434,7 @@
/**
* @brief DeInitializes LPTIM MSP.
- * @param hlptim: LPTIM handle
+ * @param hlptim LPTIM handle
* @retval None
*/
__weak void HAL_LPTIM_MspDeInit(LPTIM_HandleTypeDef *hlptim)
@@ -407,10 +479,10 @@
/**
* @brief Starts the LPTIM PWM generation.
- * @param hlptim : LPTIM handle
- * @param Period : Specifies the Autoreload value.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
* This parameter must be a value between 0x0000 and 0xFFFF.
- * @param Pulse : Specifies the compare value.
+ * @param Pulse Specifies the compare value.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
*/
@@ -448,7 +520,7 @@
/**
* @brief Stops the LPTIM PWM generation.
- * @param hlptim : LPTIM handle
+ * @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_PWM_Stop(LPTIM_HandleTypeDef *hlptim)
@@ -471,10 +543,10 @@
/**
* @brief Starts the LPTIM PWM generation in interrupt mode.
- * @param hlptim : LPTIM handle
- * @param Period : Specifies the Autoreload value.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
* This parameter must be a value between 0x0000 and 0xFFFF
- * @param Pulse : Specifies the compare value.
+ * @param Pulse Specifies the compare value.
* This parameter must be a value between 0x0000 and 0xFFFF
* @retval HAL status
*/
@@ -531,7 +603,7 @@
/**
* @brief Stops the LPTIM PWM generation in interrupt mode.
- * @param hlptim : LPTIM handle
+ * @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_PWM_Stop_IT(LPTIM_HandleTypeDef *hlptim)
@@ -573,10 +645,10 @@
/**
* @brief Starts the LPTIM One pulse generation.
- * @param hlptim : LPTIM handle
- * @param Period : Specifies the Autoreload value.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
* This parameter must be a value between 0x0000 and 0xFFFF.
- * @param Pulse : Specifies the compare value.
+ * @param Pulse Specifies the compare value.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
*/
@@ -614,7 +686,7 @@
/**
* @brief Stops the LPTIM One pulse generation.
- * @param hlptim : LPTIM handle
+ * @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop(LPTIM_HandleTypeDef *hlptim)
@@ -637,10 +709,10 @@
/**
* @brief Starts the LPTIM One pulse generation in interrupt mode.
- * @param hlptim : LPTIM handle
- * @param Period : Specifies the Autoreload value.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
* This parameter must be a value between 0x0000 and 0xFFFF.
- * @param Pulse : Specifies the compare value.
+ * @param Pulse Specifies the compare value.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
*/
@@ -697,7 +769,7 @@
/**
* @brief Stops the LPTIM One pulse generation in interrupt mode.
- * @param hlptim : LPTIM handle
+ * @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_OnePulse_Stop_IT(LPTIM_HandleTypeDef *hlptim)
@@ -739,10 +811,10 @@
/**
* @brief Starts the LPTIM in Set once mode.
- * @param hlptim : LPTIM handle
- * @param Period : Specifies the Autoreload value.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
* This parameter must be a value between 0x0000 and 0xFFFF.
- * @param Pulse : Specifies the compare value.
+ * @param Pulse Specifies the compare value.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
*/
@@ -780,7 +852,7 @@
/**
* @brief Stops the LPTIM Set once mode.
- * @param hlptim : LPTIM handle
+ * @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop(LPTIM_HandleTypeDef *hlptim)
@@ -803,10 +875,10 @@
/**
* @brief Starts the LPTIM Set once mode in interrupt mode.
- * @param hlptim : LPTIM handle
- * @param Period : Specifies the Autoreload value.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
* This parameter must be a value between 0x0000 and 0xFFFF.
- * @param Pulse : Specifies the compare value.
+ * @param Pulse Specifies the compare value.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
*/
@@ -863,7 +935,7 @@
/**
* @brief Stops the LPTIM Set once mode in interrupt mode.
- * @param hlptim : LPTIM handle
+ * @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_SetOnce_Stop_IT(LPTIM_HandleTypeDef *hlptim)
@@ -905,8 +977,8 @@
/**
* @brief Starts the Encoder interface.
- * @param hlptim : LPTIM handle
- * @param Period : Specifies the Autoreload value.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
*/
@@ -957,7 +1029,7 @@
/**
* @brief Stops the Encoder interface.
- * @param hlptim : LPTIM handle
+ * @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop(LPTIM_HandleTypeDef *hlptim)
@@ -983,8 +1055,8 @@
/**
* @brief Starts the Encoder interface in interrupt mode.
- * @param hlptim : LPTIM handle
- * @param Period : Specifies the Autoreload value.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
*/
@@ -1042,7 +1114,7 @@
/**
* @brief Stops the Encoder interface in interrupt mode.
- * @param hlptim : LPTIM handle
+ * @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_Encoder_Stop_IT(LPTIM_HandleTypeDef *hlptim)
@@ -1076,10 +1148,10 @@
* @brief Starts the Timeout function. The first trigger event will start the
* timer, any successive trigger event will reset the counter and
* the timer restarts.
- * @param hlptim : LPTIM handle
- * @param Period : Specifies the Autoreload value.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
* This parameter must be a value between 0x0000 and 0xFFFF.
- * @param Timeout : Specifies the TimeOut value to rest the counter.
+ * @param Timeout Specifies the TimeOut value to rest the counter.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
*/
@@ -1117,7 +1189,7 @@
/**
* @brief Stops the Timeout function.
- * @param hlptim : LPTIM handle
+ * @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop(LPTIM_HandleTypeDef *hlptim)
@@ -1145,10 +1217,10 @@
* @brief Starts the Timeout function in interrupt mode. The first trigger
* event will start the timer, any successive trigger event will reset
* the counter and the timer restarts.
- * @param hlptim : LPTIM handle
- * @param Period : Specifies the Autoreload value.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
* This parameter must be a value between 0x0000 and 0xFFFF.
- * @param Timeout : Specifies the TimeOut value to rest the counter.
+ * @param Timeout Specifies the TimeOut value to rest the counter.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
*/
@@ -1195,7 +1267,7 @@
/**
* @brief Stops the Timeout function in interrupt mode.
- * @param hlptim : LPTIM handle
+ * @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_TimeOut_Stop_IT(LPTIM_HandleTypeDef *hlptim)
@@ -1230,8 +1302,8 @@
/**
* @brief Starts the Counter mode.
- * @param hlptim : LPTIM handle
- * @param Period : Specifies the Autoreload value.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
*/
@@ -1271,7 +1343,7 @@
/**
* @brief Stops the Counter mode.
- * @param hlptim : LPTIM handle
+ * @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_Counter_Stop(LPTIM_HandleTypeDef *hlptim)
@@ -1294,8 +1366,8 @@
/**
* @brief Starts the Counter mode in interrupt mode.
- * @param hlptim : LPTIM handle
- * @param Period : Specifies the Autoreload value.
+ * @param hlptim LPTIM handle
+ * @param Period Specifies the Autoreload value.
* This parameter must be a value between 0x0000 and 0xFFFF.
* @retval HAL status
*/
@@ -1347,7 +1419,7 @@
/**
* @brief Stops the Counter mode in interrupt mode.
- * @param hlptim : LPTIM handle
+ * @param hlptim LPTIM handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LPTIM_Counter_Stop_IT(LPTIM_HandleTypeDef *hlptim)
@@ -1401,7 +1473,7 @@
/**
* @brief This function returns the current counter value.
- * @param hlptim: LPTIM handle
+ * @param hlptim LPTIM handle
* @retval Counter value.
*/
uint32_t HAL_LPTIM_ReadCounter(LPTIM_HandleTypeDef *hlptim)
@@ -1414,7 +1486,7 @@
/**
* @brief This function return the current Autoreload (Period) value.
- * @param hlptim: LPTIM handle
+ * @param hlptim LPTIM handle
* @retval Autoreload value.
*/
uint32_t HAL_LPTIM_ReadAutoReload(LPTIM_HandleTypeDef *hlptim)
@@ -1427,7 +1499,7 @@
/**
* @brief This function return the current Compare (Pulse) value.
- * @param hlptim: LPTIM handle
+ * @param hlptim LPTIM handle
* @retval Compare value.
*/
uint32_t HAL_LPTIM_ReadCompare(LPTIM_HandleTypeDef *hlptim)
@@ -1459,7 +1531,7 @@
/**
* @brief This function handles LPTIM interrupt request.
- * @param hlptim: LPTIM handle
+ * @param hlptim LPTIM handle
* @retval None
*/
void HAL_LPTIM_IRQHandler(LPTIM_HandleTypeDef *hlptim)
@@ -1472,7 +1544,11 @@
/* Clear Compare match flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPM);
/* Compare match Callback */
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+ hlptim->CompareMatchCallback(hlptim);
+#else
HAL_LPTIM_CompareMatchCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
}
}
@@ -1484,7 +1560,11 @@
/* Clear Autoreload match flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARRM);
/* Autoreload match Callback */
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+ hlptim->AutoReloadMatchCallback(hlptim);
+#else
HAL_LPTIM_AutoReloadMatchCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
}
}
@@ -1496,7 +1576,11 @@
/* Clear Trigger detected flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_EXTTRIG);
/* Trigger detected callback */
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+ hlptim->TriggerCallback(hlptim);
+#else
HAL_LPTIM_TriggerCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
}
}
@@ -1508,7 +1592,11 @@
/* Clear Compare write flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_CMPOK);
/* Compare write Callback */
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+ hlptim->CompareWriteCallback(hlptim);
+#else
HAL_LPTIM_CompareWriteCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
}
}
@@ -1520,7 +1608,11 @@
/* Clear Autoreload write flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_ARROK);
/* Autoreload write Callback */
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+ hlptim->AutoReloadWriteCallback(hlptim);
+#else
HAL_LPTIM_AutoReloadWriteCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
}
}
@@ -1532,7 +1624,11 @@
/* Clear Direction counter changed from Down to Up flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_UP);
/* Direction counter changed from Down to Up Callback */
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+ hlptim->DirectionUpCallback(hlptim);
+#else
HAL_LPTIM_DirectionUpCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
}
}
@@ -1544,7 +1640,11 @@
/* Clear Direction counter changed from Up to Down flag */
__HAL_LPTIM_CLEAR_FLAG(hlptim, LPTIM_FLAG_DOWN);
/* Direction counter changed from Up to Down Callback */
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+ hlptim->DirectionDownCallback(hlptim);
+#else
HAL_LPTIM_DirectionDownCallback(hlptim);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
}
}
@@ -1553,7 +1653,7 @@
/**
* @brief Compare match callback in non blocking mode
- * @param hlptim : LPTIM handle
+ * @param hlptim LPTIM handle
* @retval None
*/
__weak void HAL_LPTIM_CompareMatchCallback(LPTIM_HandleTypeDef *hlptim)
@@ -1568,7 +1668,7 @@
/**
* @brief Autoreload match callback in non blocking mode
- * @param hlptim : LPTIM handle
+ * @param hlptim LPTIM handle
* @retval None
*/
__weak void HAL_LPTIM_AutoReloadMatchCallback(LPTIM_HandleTypeDef *hlptim)
@@ -1583,7 +1683,7 @@
/**
* @brief Trigger detected callback in non blocking mode
- * @param hlptim : LPTIM handle
+ * @param hlptim LPTIM handle
* @retval None
*/
__weak void HAL_LPTIM_TriggerCallback(LPTIM_HandleTypeDef *hlptim)
@@ -1598,7 +1698,7 @@
/**
* @brief Compare write callback in non blocking mode
- * @param hlptim : LPTIM handle
+ * @param hlptim LPTIM handle
* @retval None
*/
__weak void HAL_LPTIM_CompareWriteCallback(LPTIM_HandleTypeDef *hlptim)
@@ -1613,7 +1713,7 @@
/**
* @brief Autoreload write callback in non blocking mode
- * @param hlptim : LPTIM handle
+ * @param hlptim LPTIM handle
* @retval None
*/
__weak void HAL_LPTIM_AutoReloadWriteCallback(LPTIM_HandleTypeDef *hlptim)
@@ -1628,7 +1728,7 @@
/**
* @brief Direction counter changed from Down to Up callback in non blocking mode
- * @param hlptim : LPTIM handle
+ * @param hlptim LPTIM handle
* @retval None
*/
__weak void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim)
@@ -1643,7 +1743,7 @@
/**
* @brief Direction counter changed from Up to Down callback in non blocking mode
- * @param hlptim : LPTIM handle
+ * @param hlptim LPTIM handle
* @retval None
*/
__weak void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim)
@@ -1656,6 +1756,212 @@
*/
}
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register user LPTIM callback to be used instead of the weak predefined callback
+ * @param hlptim lptim handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_LPTIM_MSPINIT_CB_ID MspInit Callback ID
+ * @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID MspDeInit Callback ID
+ * @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID Compare Match Callback ID
+ * @arg @ref HAL_LPTIM_AUTO_RELOAD_MATCH_CB_ID Auto Reload Match Callback ID
+ * @arg @ref HAL_LPTIM_TRIGGER_CB_ID Trigger Callback ID
+ * @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID Compare Write Callback ID
+ * @arg @ref HAL_LPTIM_AUTO_RELOAD_WRITE_CB_ID Auto Reload Write Callback ID
+ * @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID Direction UP Callback ID
+ * @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID Direction Down Callback ID
+ * @param pCallback pointer to the callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if(pCallback == NULL)
+ {
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(hlptim);
+
+ if(hlptim->State == HAL_LPTIM_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_LPTIM_MSPINIT_CB_ID :
+ hlptim->MspInitCallback = pCallback;
+ break;
+
+ case HAL_LPTIM_MSPDEINIT_CB_ID :
+ hlptim->MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_LPTIM_COMPARE_MATCH_CB_ID :
+ hlptim->CompareMatchCallback = pCallback;
+ break;
+
+ case HAL_LPTIM_AUTO_RELOAD_MATCH_CB_ID :
+ hlptim->AutoReloadMatchCallback = pCallback;
+ break;
+
+ case HAL_LPTIM_TRIGGER_CB_ID :
+ hlptim->TriggerCallback = pCallback;
+ break;
+
+ case HAL_LPTIM_COMPARE_WRITE_CB_ID :
+ hlptim->CompareWriteCallback = pCallback;
+ break;
+
+ case HAL_LPTIM_AUTO_RELOAD_WRITE_CB_ID :
+ hlptim->AutoReloadWriteCallback = pCallback;
+ break;
+
+ case HAL_LPTIM_DIRECTION_UP_CB_ID :
+ hlptim->DirectionUpCallback = pCallback;
+ break;
+
+ case HAL_LPTIM_DIRECTION_DOWN_CB_ID :
+ hlptim->DirectionDownCallback = pCallback;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(hlptim->State == HAL_LPTIM_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_LPTIM_MSPINIT_CB_ID :
+ hlptim->MspInitCallback = pCallback;
+ break;
+
+ case HAL_LPTIM_MSPDEINIT_CB_ID :
+ hlptim->MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hlptim);
+
+ return status;
+}
+
+/**
+ * @brief UnRegister user LPTIM callback
+ * LPTIM callback is redirected to the weak predefined callback
+ * @param hlptim lptim handle
+ * @param CallbackID ID of the callback to be unregistered
++ * This parameter can be one of the following values:
++ * @arg @ref HAL_LPTIM_MSPINIT_CB_ID MspInit Callback ID
++ * @arg @ref HAL_LPTIM_MSPDEINIT_CB_ID MspDeInit Callback ID
++ * @arg @ref HAL_LPTIM_COMPARE_MATCH_CB_ID Compare Match Callback ID
++ * @arg @ref HAL_LPTIM_AUTO_RELOAD_MATCH_CB_ID Auto Reload Match Callback ID
++ * @arg @ref HAL_LPTIM_TRIGGER_CB_ID Trigger Callback ID
++ * @arg @ref HAL_LPTIM_COMPARE_WRITE_CB_ID Compare Write Callback ID
++ * @arg @ref HAL_LPTIM_AUTO_RELOAD_WRITE_CB_ID Auto Reload Write Callback ID
++ * @arg @ref HAL_LPTIM_DIRECTION_UP_CB_ID Direction UP Callback ID
++ * @arg @ref HAL_LPTIM_DIRECTION_DOWN_CB_ID Direction Down Callback ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(hlptim);
+
+ if(hlptim->State == HAL_LPTIM_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_LPTIM_MSPINIT_CB_ID :
+ hlptim->MspInitCallback = HAL_LPTIM_MspInit; /* Legacy weak MspInit Callback */
+ break;
+
+ case HAL_LPTIM_MSPDEINIT_CB_ID :
+ hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; /* Legacy weak MspDeInit Callback */
+ break;
+
+ case HAL_LPTIM_COMPARE_MATCH_CB_ID :
+ hlptim->CompareMatchCallback = HAL_LPTIM_CompareMatchCallback; /* Legacy weak Compare Match Callback */
+ break;
+
+ case HAL_LPTIM_AUTO_RELOAD_MATCH_CB_ID :
+ hlptim->AutoReloadMatchCallback = HAL_LPTIM_AutoReloadMatchCallback; /* Legacy weak Auto Reload Match Callback */
+ break;
+
+ case HAL_LPTIM_TRIGGER_CB_ID :
+ hlptim->TriggerCallback = HAL_LPTIM_TriggerCallback; /* Legacy weak Trigger Callback */
+ break;
+
+ case HAL_LPTIM_COMPARE_WRITE_CB_ID :
+ hlptim->CompareWriteCallback = HAL_LPTIM_CompareWriteCallback; /* Legacy weak Compare Write Callback */
+ break;
+
+ case HAL_LPTIM_AUTO_RELOAD_WRITE_CB_ID :
+ hlptim->AutoReloadWriteCallback = HAL_LPTIM_AutoReloadWriteCallback; /* Legacy weak Auto Reload Write Callback */
+ break;
+
+ case HAL_LPTIM_DIRECTION_UP_CB_ID :
+ hlptim->DirectionUpCallback = HAL_LPTIM_DirectionUpCallback; /* Legacy weak Direction Up Callback */
+ break;
+
+ case HAL_LPTIM_DIRECTION_DOWN_CB_ID :
+ hlptim->DirectionDownCallback = HAL_LPTIM_DirectionDownCallback; /* Legacy weak Direction Down Callback */
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(hlptim->State == HAL_LPTIM_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_LPTIM_MSPINIT_CB_ID :
+ hlptim->MspInitCallback = HAL_LPTIM_MspInit; /* Legacy weak MspInit Callback */
+ break;
+
+ case HAL_LPTIM_MSPDEINIT_CB_ID :
+ hlptim->MspDeInitCallback = HAL_LPTIM_MspDeInit; /* Legacy weak MspDeInit Callback */
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(hlptim);
+
+ return status;
+}
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -1676,7 +1982,7 @@
/**
* @brief Returns the LPTIM state.
- * @param hlptim: LPTIM handle
+ * @param hlptim LPTIM handle
* @retval HAL state
*/
HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim)
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_lptim.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_lptim.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_lptim.h
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief Header file of LPTIM HAL module.
******************************************************************************
* @attention
@@ -155,20 +153,54 @@
/**
* @brief LPTIM handle Structure definition
*/
-typedef struct
+typedef struct __LPTIM_HandleTypeDef
{
- LPTIM_TypeDef *Instance; /*!< Register base address */
-
- LPTIM_InitTypeDef Init; /*!< LPTIM required parameters */
-
- HAL_StatusTypeDef Status; /*!< LPTIM peripheral status */
-
- HAL_LockTypeDef Lock; /*!< LPTIM locking object */
-
- __IO HAL_LPTIM_StateTypeDef State; /*!< LPTIM peripheral state */
-
+ LPTIM_TypeDef *Instance; /*!< Register base address */
+ LPTIM_InitTypeDef Init; /*!< LPTIM required parameters */
+ HAL_StatusTypeDef Status; /*!< LPTIM peripheral status */
+ HAL_LockTypeDef Lock; /*!< LPTIM locking object */
+ __IO HAL_LPTIM_StateTypeDef State; /*!< LPTIM peripheral state */
+
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+ void (* MspInitCallback) (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Msp Init Callback */
+ void (* MspDeInitCallback) (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Msp DeInit Callback */
+
+ void (* CompareMatchCallback) (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Compare Match Callback */
+ void (* AutoReloadMatchCallback) (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Auto Reload Match Callback */
+ void (* TriggerCallback) (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Trigger Callback */
+ void (* CompareWriteCallback) (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Compare Write Callback */
+ void (* AutoReloadWriteCallback) (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Auto Reload Write Callback */
+ void (* DirectionUpCallback) (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Direction Up Callback */
+ void (* DirectionDownCallback) (struct __LPTIM_HandleTypeDef *hlptim); /*!< LPTIM Direction Down Callback */
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+
}LPTIM_HandleTypeDef;
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL LPTIM Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_LPTIM_MSPINIT_CB_ID = 0x00U, /*!< LPTIM MspInit Callback ID */
+ HAL_LPTIM_MSPDEINIT_CB_ID = 0x01U, /*!< LPTIM MspDeInit Callback ID */
+
+ HAL_LPTIM_COMPARE_MATCH_CB_ID = 0x02U, /*!< LPTIM Compare Match Callback ID */
+ HAL_LPTIM_AUTO_RELOAD_MATCH_CB_ID = 0x03U, /*!< LPTIM Auto Reload Match Callback ID */
+ HAL_LPTIM_TRIGGER_CB_ID = 0x04U, /*!< LPTIM Trigger Callback ID */
+ HAL_LPTIM_COMPARE_WRITE_CB_ID = 0x05U, /*!< LPTIM Compare Write Callback ID */
+ HAL_LPTIM_AUTO_RELOAD_WRITE_CB_ID = 0x06U, /*!< LPTIM Auto Reload Write Callback ID */
+ HAL_LPTIM_DIRECTION_UP_CB_ID = 0x07U, /*!< LPTIM Direction Up Callback ID */
+ HAL_LPTIM_DIRECTION_DOWN_CB_ID = 0x08U, /*!< LPTIM Direction Down Callback ID */
+}HAL_LPTIM_CallbackIDTypeDef;
+
+/**
+ * @brief HAL LPTIM Callback pointer definition
+ */
+typedef void (*pLPTIM_CallbackTypeDef)(LPTIM_HandleTypeDef * hlptim); /*!< pointer to the LPTIM callback function */
+
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -329,14 +361,14 @@
*/
/** @brief Reset LPTIM handle state
- * @param __HANDLE__: LPTIM handle
+ * @param __HANDLE__ LPTIM handle
* @retval None
*/
#define __HAL_LPTIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LPTIM_STATE_RESET)
/**
* @brief Enable/Disable the LPTIM peripheral.
- * @param __HANDLE__: LPTIM handle
+ * @param __HANDLE__ LPTIM handle
* @retval None
*/
#define __HAL_LPTIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (LPTIM_CR_ENABLE))
@@ -344,7 +376,7 @@
/**
* @brief Starts the LPTIM peripheral in Continuous or in single mode.
- * @param __HANDLE__: DMA handle
+ * @param __HANDLE__ DMA handle
* @retval None
*/
#define __HAL_LPTIM_START_CONTINUOUS(__HANDLE__) ((__HANDLE__)->Instance->CR |= LPTIM_CR_CNTSTRT)
@@ -353,24 +385,24 @@
/**
* @brief Writes the passed parameter in the Autoreload register.
- * @param __HANDLE__: LPTIM handle
- * @param __VALUE__ : Autoreload value
+ * @param __HANDLE__ LPTIM handle
+ * @param __VALUE__ Autoreload value
* @retval None
*/
#define __HAL_LPTIM_AUTORELOAD_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->ARR = (__VALUE__))
/**
* @brief Writes the passed parameter in the Compare register.
- * @param __HANDLE__: LPTIM handle
- * @param __VALUE__ : Compare value
+ * @param __HANDLE__ LPTIM handle
+ * @param __VALUE__ Compare value
* @retval None
*/
#define __HAL_LPTIM_COMPARE_SET(__HANDLE__ , __VALUE__) ((__HANDLE__)->Instance->CMP = (__VALUE__))
/**
* @brief Checks whether the specified LPTIM flag is set or not.
- * @param __HANDLE__: LPTIM handle
- * @param __FLAG__ : LPTIM flag to check
+ * @param __HANDLE__ LPTIM handle
+ * @param __FLAG__ LPTIM flag to check
* This parameter can be a value of:
* @arg LPTIM_FLAG_DOWN : Counter direction change up Flag.
* @arg LPTIM_FLAG_UP : Counter direction change down to up Flag.
@@ -385,8 +417,8 @@
/**
* @brief Clears the specified LPTIM flag.
- * @param __HANDLE__: LPTIM handle.
- * @param __FLAG__ : LPTIM flag to clear.
+ * @param __HANDLE__ LPTIM handle.
+ * @param __FLAG__ LPTIM flag to clear.
* This parameter can be a value of:
* @arg LPTIM_FLAG_DOWN : Counter direction change up Flag.
* @arg LPTIM_FLAG_UP : Counter direction change down to up Flag.
@@ -401,8 +433,8 @@
/**
* @brief Enable the specified LPTIM interrupt.
- * @param __HANDLE__ : LPTIM handle.
- * @param __INTERRUPT__ : LPTIM interrupt to set.
+ * @param __HANDLE__ LPTIM handle.
+ * @param __INTERRUPT__ LPTIM interrupt to set.
* This parameter can be a value of:
* @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
* @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
@@ -417,8 +449,8 @@
/**
* @brief Disable the specified LPTIM interrupt.
- * @param __HANDLE__ : LPTIM handle.
- * @param __INTERRUPT__ : LPTIM interrupt to set.
+ * @param __HANDLE__ LPTIM handle.
+ * @param __INTERRUPT__ LPTIM interrupt to set.
* This parameter can be a value of:
* @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
* @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
@@ -433,8 +465,8 @@
/**
* @brief Checks whether the specified LPTIM interrupt is set or not.
- * @param __HANDLE__ : LPTIM handle.
- * @param __INTERRUPT__ : LPTIM interrupt to check.
+ * @param __HANDLE__ LPTIM handle.
+ * @param __INTERRUPT__ LPTIM interrupt to check.
* This parameter can be a value of:
* @arg LPTIM_IT_DOWN : Counter direction change up Interrupt.
* @arg LPTIM_IT_UP : Counter direction change down to up Interrupt.
@@ -614,6 +646,12 @@
void HAL_LPTIM_DirectionUpCallback(LPTIM_HandleTypeDef *hlptim);
void HAL_LPTIM_DirectionDownCallback(LPTIM_HandleTypeDef *hlptim);
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_LPTIM_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_LPTIM_RegisterCallback(LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID, pLPTIM_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_LPTIM_UnRegisterCallback(LPTIM_HandleTypeDef *hlptim, HAL_LPTIM_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_LPTIM_REGISTER_CALLBACKS */
+
/* Peripheral State functions ************************************************/
HAL_LPTIM_StateTypeDef HAL_LPTIM_GetState(LPTIM_HandleTypeDef *hlptim);
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_ltdc.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_ltdc.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_ltdc.c
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief LTDC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the LTDC peripheral:
@@ -154,7 +152,7 @@
/**
* @brief Initializes the LTDC according to the specified
* parameters in the LTDC_InitTypeDef and create the associated handle.
- * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval HAL status
*/
@@ -246,7 +244,7 @@
/**
* @brief Deinitializes the LTDC peripheral registers to their default reset
* values.
- * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval None
*/
@@ -270,7 +268,7 @@
/**
* @brief Initializes the LTDC MSP.
- * @param hltdc : pointer to a LTDC_HandleTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval None
*/
@@ -286,7 +284,7 @@
/**
* @brief DeInitializes the LTDC MSP.
- * @param hltdc : pointer to a LTDC_HandleTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval None
*/
@@ -319,7 +317,7 @@
*/
/**
* @brief Handles LTDC interrupt request.
- * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval HAL status
*/
@@ -391,7 +389,7 @@
__HAL_UNLOCK(hltdc);
/* Line interrupt Callback */
- HAL_LTDC_LineEvenCallback(hltdc);
+ HAL_LTDC_LineEventCallback(hltdc);
}
}
/* Register reload Interrupt management ***************************************/
@@ -419,7 +417,7 @@
/**
* @brief Error LTDC callback.
- * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval None
*/
@@ -435,23 +433,23 @@
/**
* @brief Line Event callback.
- * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval None
*/
-__weak void HAL_LTDC_LineEvenCallback(LTDC_HandleTypeDef *hltdc)
+__weak void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hltdc);
/* NOTE : This function Should not be modified, when the callback is needed,
- the HAL_LTDC_LineEvenCallback could be implemented in the user file
+ the HAL_LTDC_LineEventCallback could be implemented in the user file
*/
}
/**
* @brief Reload Event callback.
- * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval None
*/
@@ -496,11 +494,11 @@
/**
* @brief Configure the LTDC Layer according to the specified
* parameters in the LTDC_InitTypeDef and create the associated handle.
- * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
- * @param pLayerCfg: pointer to a LTDC_LayerCfgTypeDef structure that contains
+ * @param pLayerCfg pointer to a LTDC_LayerCfgTypeDef structure that contains
* the configuration information for the Layer.
- * @param LayerIdx: LTDC Layer index.
+ * @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
* 0 or 1
* @retval HAL status
@@ -546,10 +544,10 @@
/**
* @brief Configure the color keying.
- * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
- * @param RGBValue: the color key value
- * @param LayerIdx: LTDC Layer index.
+ * @param RGBValue the color key value
+ * @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
* 0 or 1
* @retval HAL status
@@ -583,11 +581,11 @@
/**
* @brief Load the color lookup table.
- * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
- * @param pCLUT: pointer to the color lookup table address.
- * @param CLUTSize: the color lookup table size.
- * @param LayerIdx: LTDC Layer index.
+ * @param pCLUT pointer to the color lookup table address.
+ * @param CLUTSize the color lookup table size.
+ * @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
* 0 or 1
* @retval HAL status
@@ -635,9 +633,9 @@
/**
* @brief Enable the color keying.
- * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
- * @param LayerIdx: LTDC Layer index.
+ * @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
* 0 or 1
* @retval HAL status
@@ -670,9 +668,9 @@
/**
* @brief Disable the color keying.
- * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
- * @param LayerIdx: LTDC Layer index.
+ * @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
* 0 or 1
* @retval HAL status
@@ -705,9 +703,9 @@
/**
* @brief Enable the color lookup table.
- * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
- * @param LayerIdx: LTDC Layer index.
+ * @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
* 0 or 1
* @retval HAL status
@@ -741,9 +739,9 @@
/**
* @brief Disable the color lookup table.
- * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
- * @param LayerIdx: LTDC Layer index.
+ * @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
* 0 or 1
* @retval HAL status
@@ -777,7 +775,7 @@
/**
* @brief Enables Dither.
- * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval HAL status
*/
@@ -804,7 +802,7 @@
/**
* @brief Disables Dither.
- * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval HAL status
*/
@@ -831,11 +829,11 @@
/**
* @brief Set the LTDC window size.
- * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
- * @param XSize: LTDC Pixel per line
- * @param YSize: LTDC Line number
- * @param LayerIdx: LTDC Layer index.
+ * @param XSize LTDC Pixel per line
+ * @param YSize LTDC Line number
+ * @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
* 0 or 1
* @retval HAL status
@@ -893,11 +891,11 @@
/**
* @brief Set the LTDC window position.
- * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
- * @param X0: LTDC window X offset
- * @param Y0: LTDC window Y offset
- * @param LayerIdx: LTDC Layer index.
+ * @param X0 LTDC window X offset
+ * @param Y0 LTDC window Y offset
+ * @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
* 0 or 1
* @retval HAL status
@@ -947,10 +945,10 @@
/**
* @brief Reconfigure the pixel format.
- * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
- * @param Pixelformat: new pixel format value.
- * @param LayerIdx: LTDC Layer index.
+ * @param Pixelformat new pixel format value.
+ * @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
* 0 or 1.
* @retval HAL status
@@ -992,10 +990,10 @@
/**
* @brief Reconfigure the layer alpha value.
- * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
- * @param Alpha: new alpha value.
- * @param LayerIdx: LTDC Layer index.
+ * @param Alpha new alpha value.
+ * @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
* 0 or 1
* @retval HAL status
@@ -1036,10 +1034,10 @@
}
/**
* @brief Reconfigure the frame buffer Address.
- * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
- * @param Address: new address value.
- * @param LayerIdx: LTDC Layer index.
+ * @param Address new address value.
+ * @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
* 0 or 1.
* @retval HAL status
@@ -1085,10 +1083,10 @@
* will be in that case 800 pixels and not 320 pixels as initially configured by previous call to HAL_LTDC_ConfigLayer().
* Note : this function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch
* configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above).
- * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
- * @param LinePitchInPixels: New line pitch in pixels to configure for LTDC layer 'LayerIdx'.
- * @param LayerIdx: LTDC layer index concerned by the modification of line pitch.
+ * @param LinePitchInPixels New line pitch in pixels to configure for LTDC layer 'LayerIdx'.
+ * @param LayerIdx LTDC layer index concerned by the modification of line pitch.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_SetPitch(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx)
@@ -1154,9 +1152,9 @@
/**
* @brief Define the position of the line interrupt.
- * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
- * @param Line: Line Interrupt Position.
+ * @param Line Line Interrupt Position.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_ProgramLineEvent(LTDC_HandleTypeDef *hltdc, uint32_t Line)
@@ -1187,9 +1185,9 @@
/**
* @brief LTDC configuration reload.
- * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
- * @param ReloadType: This parameter can be one of the following values :
+ * @param ReloadType This parameter can be one of the following values :
* LTDC_RELOAD_IMMEDIATE : Immediate Reload
* LTDC_RELOAD_VERTICAL_BLANKING : Reload in the next Vertical Blanking
* @retval HAL status
@@ -1223,11 +1221,11 @@
* @brief Configure the LTDC Layer according to the specified without reloading
* parameters in the LTDC_InitTypeDef and create the associated handle.
* Variant of the function HAL_LTDC_ConfigLayer without immediate reload
- * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
- * @param pLayerCfg: pointer to a LTDC_LayerCfgTypeDef structure that contains
+ * @param pLayerCfg pointer to a LTDC_LayerCfgTypeDef structure that contains
* the configuration information for the Layer.
- * @param LayerIdx: LTDC Layer index.
+ * @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
* 0 or 1
* @retval HAL status
@@ -1273,11 +1271,11 @@
/**
* @brief Set the LTDC window size without reloading.
* Variant of the function HAL_LTDC_SetWindowSize without immediate reload
- * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
- * @param XSize: LTDC Pixel per line
- * @param YSize: LTDC Line number
- * @param LayerIdx: LTDC Layer index.
+ * @param XSize LTDC Pixel per line
+ * @param YSize LTDC Line number
+ * @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
* 0 or 1
* @retval HAL status
@@ -1335,11 +1333,11 @@
/**
* @brief Set the LTDC window position without reloading.
* Variant of the function HAL_LTDC_SetWindowPosition without immediate reload
- * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
- * @param X0: LTDC window X offset
- * @param Y0: LTDC window Y offset
- * @param LayerIdx: LTDC Layer index.
+ * @param X0 LTDC window X offset
+ * @param Y0 LTDC window Y offset
+ * @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
* 0 or 1
* @retval HAL status
@@ -1389,10 +1387,10 @@
/**
* @brief Reconfigure the pixel format without reloading.
* Variant of the function HAL_LTDC_SetPixelFormat without immediate reload
- * @param hltdc: pointer to a LTDC_HandleTypeDfef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDfef structure that contains
* the configuration information for the LTDC.
- * @param Pixelformat: new pixel format value.
- * @param LayerIdx: LTDC Layer index.
+ * @param Pixelformat new pixel format value.
+ * @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
* 0 or 1.
* @retval HAL status
@@ -1434,10 +1432,10 @@
/**
* @brief Reconfigure the layer alpha value without reloading.
* Variant of the function HAL_LTDC_SetAlpha without immediate reload
- * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
- * @param Alpha: new alpha value.
- * @param LayerIdx: LTDC Layer index.
+ * @param Alpha new alpha value.
+ * @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
* 0 or 1
* @retval HAL status
@@ -1479,10 +1477,10 @@
/**
* @brief Reconfigure the frame buffer Address without reloading.
* Variant of the function HAL_LTDC_SetAddress without immediate reload
- * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
- * @param Address: new address value.
- * @param LayerIdx: LTDC Layer index.
+ * @param Address new address value.
+ * @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
* 0 or 1.
* @retval HAL status
@@ -1528,10 +1526,10 @@
* Note : this function should be called only after a previous call to HAL_LTDC_ConfigLayer() to modify the default pitch
* configured by HAL_LTDC_ConfigLayer() when required (refer to example described just above).
* Variant of the function HAL_LTDC_SetPitch without immediate reload
- * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
- * @param LinePitchInPixels: New line pitch in pixels to configure for LTDC layer 'LayerIdx'.
- * @param LayerIdx: LTDC layer index concerned by the modification of line pitch.
+ * @param LinePitchInPixels New line pitch in pixels to configure for LTDC layer 'LayerIdx'.
+ * @param LayerIdx LTDC layer index concerned by the modification of line pitch.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_LTDC_SetPitch_NoReload(LTDC_HandleTypeDef *hltdc, uint32_t LinePitchInPixels, uint32_t LayerIdx)
@@ -1595,10 +1593,10 @@
/**
* @brief Configure the color keying without reloading.
* Variant of the function HAL_LTDC_ConfigColorKeying without immediate reload
- * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
- * @param RGBValue: the color key value
- * @param LayerIdx: LTDC Layer index.
+ * @param RGBValue the color key value
+ * @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
* 0 or 1
* @retval HAL status
@@ -1632,9 +1630,9 @@
/**
* @brief Enable the color keying without reloading.
* Variant of the function HAL_LTDC_EnableColorKeying without immediate reload
- * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
- * @param LayerIdx: LTDC Layer index.
+ * @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
* 0 or 1
* @retval HAL status
@@ -1667,9 +1665,9 @@
/**
* @brief Disable the color keying without reloading.
* Variant of the function HAL_LTDC_DisableColorKeying without immediate reload
- * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
- * @param LayerIdx: LTDC Layer index.
+ * @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
* 0 or 1
* @retval HAL status
@@ -1702,9 +1700,9 @@
/**
* @brief Enable the color lookup table without reloading.
* Variant of the function HAL_LTDC_EnableCLUT without immediate reload
- * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
- * @param LayerIdx: LTDC Layer index.
+ * @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
* 0 or 1
* @retval HAL status
@@ -1738,9 +1736,9 @@
/**
* @brief Disable the color lookup table without reloading.
* Variant of the function HAL_LTDC_DisableCLUT without immediate reload
- * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
- * @param LayerIdx: LTDC Layer index.
+ * @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values:
* 0 or 1
* @retval HAL status
@@ -1793,7 +1791,7 @@
/**
* @brief Return the LTDC state
- * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains
+ * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval HAL state
*/
@@ -1804,7 +1802,7 @@
/**
* @brief Return the LTDC error code
-* @param hltdc : pointer to a LTDC_HandleTypeDef structure that contains
+* @param hltdc pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
* @retval LTDC Error Code
*/
@@ -1819,10 +1817,10 @@
/**
* @brief Configures the LTDC peripheral
- * @param hltdc : Pointer to a LTDC_HandleTypeDef structure that contains
+ * @param hltdc Pointer to a LTDC_HandleTypeDef structure that contains
* the configuration information for the LTDC.
- * @param pLayerCfg: Pointer LTDC Layer Configuration structure
- * @param LayerIdx: LTDC Layer index.
+ * @param pLayerCfg Pointer LTDC Layer Configuration structure
+ * @param LayerIdx LTDC Layer index.
* This parameter can be one of the following values: 0 or 1
* @retval None
*/
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_ltdc.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_ltdc.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_ltdc.h * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief Header file of LTDC HAL module. ****************************************************************************** * @attention @@ -365,29 +363,29 @@ */ /** @brief Reset LTDC handle state - * @param __HANDLE__: specifies the LTDC handle. + * @param __HANDLE__ specifies the LTDC handle. * @retval None */ #define __HAL_LTDC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_LTDC_STATE_RESET) /** * @brief Enable the LTDC. - * @param __HANDLE__: LTDC handle + * @param __HANDLE__ LTDC handle * @retval None. */ #define __HAL_LTDC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR |= LTDC_GCR_LTDCEN) /** * @brief Disable the LTDC. - * @param __HANDLE__: LTDC handle + * @param __HANDLE__ LTDC handle * @retval None. */ #define __HAL_LTDC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->GCR &= ~(LTDC_GCR_LTDCEN)) /** * @brief Enable the LTDC Layer. - * @param __HANDLE__: LTDC handle - * @param __LAYER__: Specify the layer to be enabled + * @param __HANDLE__ LTDC handle + * @param __LAYER__ Specify the layer to be enabled * This parameter can be 0 or 1 * @retval None. */ @@ -395,8 +393,8 @@ /** * @brief Disable the LTDC Layer. - * @param __HANDLE__: LTDC handle - * @param __LAYER__: Specify the layer to be disabled + * @param __HANDLE__ LTDC handle + * @param __LAYER__ Specify the layer to be disabled * This parameter can be 0 or 1 * @retval None. */ @@ -404,7 +402,7 @@ /** * @brief Reload Layer Configuration. - * @param __HANDLE__: LTDC handle + * @param __HANDLE__ LTDC handle * @retval None. */ #define __HAL_LTDC_RELOAD_CONFIG(__HANDLE__) ((__HANDLE__)->Instance->SRCR |= LTDC_SRCR_IMR) @@ -412,8 +410,8 @@ /* Interrupt & Flag management */ /** * @brief Get the LTDC pending flags. - * @param __HANDLE__: LTDC handle - * @param __FLAG__: Get the specified flag. + * @param __HANDLE__ LTDC handle + * @param __FLAG__ Get the specified flag. * This parameter can be any combination of the following values: * @arg LTDC_FLAG_LI: Line Interrupt flag * @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag @@ -425,8 +423,8 @@ /** * @brief Clears the LTDC pending flags. - * @param __HANDLE__: LTDC handle - * @param __FLAG__: specifies the flag to clear. + * @param __HANDLE__ LTDC handle + * @param __FLAG__ specifies the flag to clear. * This parameter can be any combination of the following values: * @arg LTDC_FLAG_LI: Line Interrupt flag * @arg LTDC_FLAG_FU: FIFO Underrun Interrupt flag @@ -438,8 +436,8 @@ /** * @brief Enables the specified LTDC interrupts. - * @param __HANDLE__: LTDC handle - * @param __INTERRUPT__: specifies the LTDC interrupt sources to be enabled. + * @param __HANDLE__ LTDC handle + * @param __INTERRUPT__ specifies the LTDC interrupt sources to be enabled. * This parameter can be any combination of the following values: * @arg LTDC_IT_LI: Line Interrupt flag * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag @@ -451,8 +449,8 @@ /** * @brief Disables the specified LTDC interrupts. - * @param __HANDLE__: LTDC handle - * @param __INTERRUPT__: specifies the LTDC interrupt sources to be disabled. + * @param __HANDLE__ LTDC handle + * @param __INTERRUPT__ specifies the LTDC interrupt sources to be disabled. * This parameter can be any combination of the following values: * @arg LTDC_IT_LI: Line Interrupt flag * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag @@ -464,8 +462,8 @@ /** * @brief Checks whether the specified LTDC interrupt has occurred or not. - * @param __HANDLE__: LTDC handle - * @param __INTERRUPT__: specifies the LTDC interrupt source to check. + * @param __HANDLE__ LTDC handle + * @param __INTERRUPT__ specifies the LTDC interrupt source to check. * This parameter can be one of the following values: * @arg LTDC_IT_LI: Line Interrupt flag * @arg LTDC_IT_FU: FIFO Underrun Interrupt flag @@ -496,7 +494,7 @@ void HAL_LTDC_MspInit(LTDC_HandleTypeDef* hltdc); void HAL_LTDC_MspDeInit(LTDC_HandleTypeDef* hltdc); void HAL_LTDC_ErrorCallback(LTDC_HandleTypeDef *hltdc); -void HAL_LTDC_LineEvenCallback(LTDC_HandleTypeDef *hltdc); +void HAL_LTDC_LineEventCallback(LTDC_HandleTypeDef *hltdc); void HAL_LTDC_ReloadEventCallback(LTDC_HandleTypeDef *hltdc); /** * @}
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_ltdc_ex.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_ltdc_ex.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_ltdc_ex.c * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief LTDC Extension HAL module driver. ****************************************************************************** * @attention @@ -75,9 +73,9 @@ #if defined (STM32F769xx) || defined (STM32F779xx) /** * @brief Retrieve common parameters from DSI Video mode configuration structure - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. - * @param VidCfg: pointer to a DSI_VidCfgTypeDef structure that contains + * @param VidCfg pointer to a DSI_VidCfgTypeDef structure that contains * the DSI video mode configuration parameters * @note The implementation of this function is taking into account the LTDC * polarities inversion as described in the current LTDC specification @@ -111,9 +109,9 @@ /** * @brief Retrieve common parameters from DSI Adapted command mode configuration structure - * @param hltdc: pointer to a LTDC_HandleTypeDef structure that contains + * @param hltdc pointer to a LTDC_HandleTypeDef structure that contains * the configuration information for the LTDC. - * @param CmdCfg: pointer to a DSI_CmdCfgTypeDef structure that contains + * @param CmdCfg pointer to a DSI_CmdCfgTypeDef structure that contains * the DSI command mode configuration parameters * @note The implementation of this function is taking into account the LTDC * polarities inversion as described in the current LTDC specification
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_ltdc_ex.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_ltdc_ex.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_ltdc_ex.h * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief Header file of LTDC HAL Extension module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_mdios.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_mdios.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_mdios.c
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief MDIOS HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the MDIOS Peripheral.
@@ -145,7 +143,7 @@
/**
* @brief Initializes the MDIOS according to the specified parameters in
* the MDIOS_InitTypeDef and creates the associated handle .
- * @param hmdios: pointer to a MDIOS_HandleTypeDef structure that contains
+ * @param hmdios pointer to a MDIOS_HandleTypeDef structure that contains
* the configuration information for MDIOS module
* @retval HAL status
*/
@@ -203,7 +201,7 @@
/**
* @brief DeInitializes the MDIOS peripheral.
- * @param hmdios: MDIOS handle
+ * @param hmdios MDIOS handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MDIOS_DeInit(MDIOS_HandleTypeDef *hmdios)
@@ -238,7 +236,7 @@
/**
* @brief MDIOS MSP Init
- * @param hmdios: mdios handle
+ * @param hmdios mdios handle
* @retval None
*/
__weak void HAL_MDIOS_MspInit(MDIOS_HandleTypeDef *hmdios)
@@ -253,7 +251,7 @@
/**
* @brief MDIOS MSP DeInit
- * @param hmdios: mdios handle
+ * @param hmdios mdios handle
* @retval None
*/
__weak void HAL_MDIOS_MspDeInit(MDIOS_HandleTypeDef *hmdios)
@@ -304,9 +302,9 @@
/**
* @brief Writes to an MDIOS output register
- * @param hmdios: mdios handle
- * @param RegNum: MDIOS input register number
- * @param Data: Data to write
+ * @param hmdios mdios handle
+ * @param RegNum MDIOS input register number
+ * @param Data Data to write
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MDIOS_WriteReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t Data)
@@ -333,9 +331,9 @@
/**
* @brief Reads an MDIOS input register
- * @param hmdios: mdios handle
- * @param RegNum: MDIOS input register number
- * @param pData: pointer to Data
+ * @param hmdios mdios handle
+ * @param RegNum MDIOS input register number
+ * @param pData pointer to Data
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MDIOS_ReadReg(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum, uint16_t *pData)
@@ -362,7 +360,7 @@
/**
* @brief Gets Written registers by MDIO master
- * @param hmdios: mdios handle
+ * @param hmdios mdios handle
* @retval bit map of written registers addresses
*/
uint32_t HAL_MDIOS_GetWrittenRegAddress(MDIOS_HandleTypeDef *hmdios)
@@ -372,7 +370,7 @@
/**
* @brief Gets Read registers by MDIO master
- * @param hmdios: mdios handle
+ * @param hmdios mdios handle
* @retval bit map of read registers addresses
*/
uint32_t HAL_MDIOS_GetReadRegAddress(MDIOS_HandleTypeDef *hmdios)
@@ -382,8 +380,8 @@
/**
* @brief Clears Write registers flag
- * @param hmdios: mdios handle
- * @param RegNum: registers addresses to be cleared
+ * @param hmdios mdios handle
+ * @param RegNum registers addresses to be cleared
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MDIOS_ClearWriteRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum)
@@ -405,8 +403,8 @@
/**
* @brief Clears Read register flag
- * @param hmdios: mdios handle
- * @param RegNum: registers addresses to be cleared
+ * @param hmdios mdios handle
+ * @param RegNum registers addresses to be cleared
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MDIOS_ClearReadRegAddress(MDIOS_HandleTypeDef *hmdios, uint32_t RegNum)
@@ -428,7 +426,7 @@
/**
* @brief Enables Events for MDIOS peripheral
- * @param hmdios: mdios handle
+ * @param hmdios mdios handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MDIOS_EnableEvents(MDIOS_HandleTypeDef *hmdios)
@@ -447,7 +445,7 @@
/**
* @brief This function handles MDIOS interrupt request.
- * @param hmdios: MDIOS handle
+ * @param hmdios MDIOS handle
* @retval None
*/
void HAL_MDIOS_IRQHandler(MDIOS_HandleTypeDef *hmdios)
@@ -507,7 +505,7 @@
/**
* @brief Write Complete Callback
- * @param hmdios: mdios handle
+ * @param hmdios mdios handle
* @retval None
*/
__weak void HAL_MDIOS_WriteCpltCallback(MDIOS_HandleTypeDef *hmdios)
@@ -522,7 +520,7 @@
/**
* @brief Read Complete Callback
- * @param hmdios: mdios handle
+ * @param hmdios mdios handle
* @retval None
*/
__weak void HAL_MDIOS_ReadCpltCallback(MDIOS_HandleTypeDef *hmdios)
@@ -537,7 +535,7 @@
/**
* @brief Error Callback
- * @param hmdios: mdios handle
+ * @param hmdios mdios handle
* @retval None
*/
__weak void HAL_MDIOS_ErrorCallback(MDIOS_HandleTypeDef *hmdios)
@@ -552,7 +550,7 @@
/**
* @brief MDIOS WAKEUP interrupt callback
- * @param hmdios: mdios handle
+ * @param hmdios mdios handle
* @retval None
*/
__weak void HAL_MDIOS_WakeUpCallback(MDIOS_HandleTypeDef *hmdios)
@@ -587,7 +585,7 @@
/**
* @brief Gets MDIOS error flags
- * @param hmdios: mdios handle
+ * @param hmdios mdios handle
* @retval bit map of occured errors
*/
uint32_t HAL_MDIOS_GetError(MDIOS_HandleTypeDef *hmdios)
@@ -598,7 +596,7 @@
/**
* @brief Return the MDIOS HAL state
- * @param hmdios: mdios handle
+ * @param hmdios mdios handle
* @retval MDIOS state
*/
HAL_MDIOS_StateTypeDef HAL_MDIOS_GetState(MDIOS_HandleTypeDef *hmdios)
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_mdios.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_mdios.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_mdios.h * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief Header file of MDIOS HAL module. ****************************************************************************** * @attention @@ -246,14 +244,14 @@ */ /** @brief Reset MDIOS handle state - * @param __HANDLE__: MDIOS handle. + * @param __HANDLE__ MDIOS handle. * @retval None */ #define __HAL_MDIOS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_MDIOS_STATE_RESET) /** * @brief Enable/Disable the MDIOS peripheral. - * @param __HANDLE__: specifies the MDIOS handle. + * @param __HANDLE__ specifies the MDIOS handle. * @retval None */ #define __HAL_MDIOS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= MDIOS_CR_EN) @@ -262,8 +260,8 @@ /** * @brief Enable the MDIOS device interrupt. - * @param __HANDLE__: specifies the MDIOS handle. - * @param __INTERRUPT__ : specifies the MDIOS interrupt sources to be enabled. + * @param __HANDLE__ specifies the MDIOS handle. + * @param __INTERRUPT__ specifies the MDIOS interrupt sources to be enabled. * This parameter can be one or a combination of the following values: * @arg MDIOS_IT_WRITE: Register write interrupt * @arg MDIOS_IT_READ: Register read interrupt @@ -274,8 +272,8 @@ /** * @brief Disable the MDIOS device interrupt. - * @param __HANDLE__: specifies the MDIOS handle. - * @param __INTERRUPT__ : specifies the MDIOS interrupt sources to be disabled. + * @param __HANDLE__ specifies the MDIOS handle. + * @param __INTERRUPT__ specifies the MDIOS interrupt sources to be disabled. * This parameter can be one or a combination of the following values: * @arg MDIOS_IT_WRITE: Register write interrupt * @arg MDIOS_IT_READ: Register read interrupt @@ -285,22 +283,22 @@ #define __HAL_MDIOS_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__)) /** @brief Set MDIOS slave get write register flag - * @param __HANDLE__: specifies the MDIOS handle. - * @param __FLAG__: specifies the write register flag + * @param __HANDLE__ specifies the MDIOS handle. + * @param __FLAG__ specifies the write register flag * @retval The state of write flag */ #define __HAL_MDIOS_GET_WRITE_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->WRFR & (__FLAG__)) /** @brief MDIOS slave get read register flag - * @param __HANDLE__: specifies the MDIOS handle. - * @param __FLAG__: specifies the read register flag + * @param __HANDLE__ specifies the MDIOS handle. + * @param __FLAG__ specifies the read register flag * @retval The state of read flag */ #define __HAL_MDIOS_GET_READ_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->RDFR & (__FLAG__)) /** @brief MDIOS slave get interrupt - * @param __HANDLE__: specifies the MDIOS handle. - * @param __FLAG__ : specifies the Error flag. + * @param __HANDLE__ specifies the MDIOS handle. + * @param __FLAG__ specifies the Error flag. * This parameter can be one or a combination of the following values: * @arg MDIOS_TURNARROUND_ERROR_FLAG: Register write interrupt * @arg MDIOS_START_ERROR_FLAG: Register read interrupt @@ -310,8 +308,8 @@ #define __HAL_MDIOS_GET_ERROR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR & (__FLAG__)) /** @brief MDIOS slave clear interrupt - * @param __HANDLE__: specifies the MDIOS handle. - * @param __FLAG__ : specifies the Error flag. + * @param __HANDLE__ specifies the MDIOS handle. + * @param __FLAG__ specifies the Error flag. * This parameter can be one or a combination of the following values: * @arg MDIOS_TURNARROUND_ERROR_FLAG: Register write interrupt * @arg MDIOS_START_ERROR_FLAG: Register read interrupt @@ -322,8 +320,8 @@ /** * @brief Checks whether the specified MDIOS interrupt is set or not. - * @param __HANDLE__: specifies the MDIOS handle. - * @param __INTERRUPT__ : specifies the MDIOS interrupt sources + * @param __HANDLE__ specifies the MDIOS handle. + * @param __INTERRUPT__ specifies the MDIOS interrupt sources * This parameter can be one or a combination of the following values: * @arg MDIOS_IT_WRITE: Register write interrupt * @arg MDIOS_IT_READ: Register read interrupt
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_mmc.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_mmc.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_mmc.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 30-December-2016
* @brief MMC card HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Secure Digital (MMC) peripheral:
@@ -192,7 +190,7 @@
******************************************************************************
* @attention
*
- * <h2><center>© COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
+ * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
*
* Redistribution and use in source and binary forms, with or without modification,
* are permitted provided that the following conditions are met:
@@ -288,7 +286,7 @@
/**
* @brief Initializes the MMC according to the specified parameters in the
MMC_HandleTypeDef and create the associated handle.
- * @param hmmc: Pointer to the MMC handle
+ * @param hmmc Pointer to the MMC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_Init(MMC_HandleTypeDef *hmmc)
@@ -335,7 +333,7 @@
/**
* @brief Initializes the MMC Card.
- * @param hmmc: Pointer to MMC handle
+ * @param hmmc Pointer to MMC handle
* @note This function initializes the MMC card. It could be used when a card
re-initialization is needed.
* @retval HAL status
@@ -365,6 +363,10 @@
/* Enable MMC Clock */
__HAL_MMC_ENABLE(hmmc);
+ /* Required power up waiting time before starting the SD initialization sequence */
+ // MBED: removed
+ //HAL_Delay(2);
+
/* Identify card operating voltage */
errorstate = MMC_PowerON(hmmc);
if(errorstate != HAL_MMC_ERROR_NONE)
@@ -388,7 +390,7 @@
/**
* @brief De-Initializes the MMC card.
- * @param hmmc: Pointer to MMC handle
+ * @param hmmc Pointer to MMC handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_DeInit(MMC_HandleTypeDef *hmmc)
@@ -419,7 +421,7 @@
/**
* @brief Initializes the MMC MSP.
- * @param hmmc: Pointer to MMC handle
+ * @param hmmc Pointer to MMC handle
* @retval None
*/
__weak void HAL_MMC_MspInit(MMC_HandleTypeDef *hmmc)
@@ -434,7 +436,7 @@
/**
* @brief De-Initialize MMC MSP.
- * @param hmmc: Pointer to MMC handle
+ * @param hmmc Pointer to MMC handle
* @retval None
*/
__weak void HAL_MMC_MspDeInit(MMC_HandleTypeDef *hmmc)
@@ -471,11 +473,11 @@
* is managed by polling mode.
* @note This API should be followed by a check on the card state through
* HAL_MMC_GetCardState().
- * @param hmmc: Pointer to MMC handle
- * @param pData: pointer to the buffer that will contain the received data
- * @param BlockAdd: Block Address from where data is to be read
- * @param NumberOfBlocks: Number of MMC blocks to read
- * @param Timeout: Specify timeout value
+ * @param hmmc Pointer to MMC handle
+ * @param pData pointer to the buffer that will contain the received data
+ * @param BlockAdd Block Address from where data is to be read
+ * @param NumberOfBlocks Number of MMC blocks to read
+ * @param Timeout Specify timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_ReadBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
@@ -655,11 +657,11 @@
* transfer is managed by polling mode.
* @note This API should be followed by a check on the card state through
* HAL_MMC_GetCardState().
- * @param hmmc: Pointer to MMC handle
- * @param pData: pointer to the buffer that will contain the data to transmit
- * @param BlockAdd: Block Address where data will be written
- * @param NumberOfBlocks: Number of MMC blocks to write
- * @param Timeout: Specify timeout value
+ * @param hmmc Pointer to MMC handle
+ * @param pData pointer to the buffer that will contain the data to transmit
+ * @param BlockAdd Block Address where data will be written
+ * @param NumberOfBlocks Number of MMC blocks to write
+ * @param Timeout Specify timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_WriteBlocks(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
@@ -826,10 +828,10 @@
* HAL_MMC_GetCardState().
* @note You could also check the IT transfer process through the MMC Rx
* interrupt event.
- * @param hmmc: Pointer to MMC handle
- * @param pData: Pointer to the buffer that will contain the received data
- * @param BlockAdd: Block Address from where data is to be read
- * @param NumberOfBlocks: Number of blocks to read.
+ * @param hmmc Pointer to MMC handle
+ * @param pData Pointer to the buffer that will contain the received data
+ * @param BlockAdd Block Address from where data is to be read
+ * @param NumberOfBlocks Number of blocks to read.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_ReadBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
@@ -928,10 +930,10 @@
* HAL_MMC_GetCardState().
* @note You could also check the IT transfer process through the MMC Tx
* interrupt event.
- * @param hmmc: Pointer to MMC handle
- * @param pData: Pointer to the buffer that will contain the data to transmit
- * @param BlockAdd: Block Address where data will be written
- * @param NumberOfBlocks: Number of blocks to write
+ * @param hmmc Pointer to MMC handle
+ * @param pData Pointer to the buffer that will contain the data to transmit
+ * @param BlockAdd Block Address where data will be written
+ * @param NumberOfBlocks Number of blocks to write
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_WriteBlocks_IT(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
@@ -1031,10 +1033,10 @@
* HAL_MMC_GetCardState().
* @note You could also check the DMA transfer process through the MMC Rx
* interrupt event.
- * @param hmmc: Pointer MMC handle
- * @param pData: Pointer to the buffer that will contain the received data
- * @param BlockAdd: Block Address from where data is to be read
- * @param NumberOfBlocks: Number of blocks to read.
+ * @param hmmc Pointer MMC handle
+ * @param pData Pointer to the buffer that will contain the received data
+ * @param BlockAdd Block Address from where data is to be read
+ * @param NumberOfBlocks Number of blocks to read.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_ReadBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
@@ -1145,10 +1147,10 @@
* HAL_MMC_GetCardState().
* @note You could also check the DMA transfer process through the MMC Tx
* interrupt event.
- * @param hmmc: Pointer to MMC handle
- * @param pData: Pointer to the buffer that will contain the data to transmit
- * @param BlockAdd: Block Address where data will be written
- * @param NumberOfBlocks: Number of blocks to write
+ * @param hmmc Pointer to MMC handle
+ * @param pData Pointer to the buffer that will contain the data to transmit
+ * @param BlockAdd Block Address where data will be written
+ * @param NumberOfBlocks Number of blocks to write
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_WriteBlocks_DMA(MMC_HandleTypeDef *hmmc, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
@@ -1257,9 +1259,9 @@
* @brief Erases the specified memory area of the given MMC card.
* @note This API should be followed by a check on the card state through
* HAL_MMC_GetCardState().
- * @param hmmc: Pointer to MMC handle
- * @param BlockStartAdd: Start Block address
- * @param BlockEndAdd: End Block address
+ * @param hmmc Pointer to MMC handle
+ * @param BlockStartAdd Start Block address
+ * @param BlockEndAdd End Block address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_MMC_Erase(MMC_HandleTypeDef *hmmc, uint32_t BlockStartAdd, uint32_t BlockEndAdd)
@@ -1355,7 +1357,7 @@
/**
* @brief This function handles MMC card interrupt request.
- * @param hmmc: Pointer to MMC handle
+ * @param hmmc Pointer to MMC handle
* @retval None
*/
void HAL_MMC_IRQHandler(MMC_HandleTypeDef *hmmc)
@@ -1501,7 +1503,7 @@
/**
* @brief return the MMC state
- * @param hmmc: Pointer to mmc handle
+ * @param hmmc Pointer to mmc handle
* @retval HAL state
*/
HAL_MMC_StateTypeDef HAL_MMC_GetState(MMC_HandleTypeDef *hmmc)
@@ -1511,7 +1513,7 @@
/**
* @brief Return the MMC error code
-* @param hmmc : Pointer to a MMC_HandleTypeDef structure that contains
+* @param hmmc Pointer to a MMC_HandleTypeDef structure that contains
* the configuration information.
* @retval MMC Error Code
*/
@@ -1522,7 +1524,7 @@
/**
* @brief Tx Transfer completed callbacks
- * @param hmmc: Pointer to MMC handle
+ * @param hmmc Pointer to MMC handle
* @retval None
*/
__weak void HAL_MMC_TxCpltCallback(MMC_HandleTypeDef *hmmc)
@@ -1537,7 +1539,7 @@
/**
* @brief Rx Transfer completed callbacks
- * @param hmmc: Pointer MMC handle
+ * @param hmmc Pointer MMC handle
* @retval None
*/
__weak void HAL_MMC_RxCpltCallback(MMC_HandleTypeDef *hmmc)
@@ -1552,7 +1554,7 @@
/**
* @brief MMC error callbacks
- * @param hmmc: Pointer MMC handle
+ * @param hmmc Pointer MMC handle
* @retval None
*/
__weak void HAL_MMC_ErrorCallback(MMC_HandleTypeDef *hmmc)
@@ -1567,7 +1569,7 @@
/**
* @brief MMC Abort callbacks
- * @param hmmc: Pointer MMC handle
+ * @param hmmc Pointer MMC handle
* @retval None
*/
__weak void HAL_MMC_AbortCallback(MMC_HandleTypeDef *hmmc)
@@ -1603,8 +1605,8 @@
/**
* @brief Returns information the information of the card which are stored on
* the CID register.
- * @param hmmc: Pointer to MMC handle
- * @param pCID: Pointer to a HAL_MMC_CIDTypedef structure that
+ * @param hmmc Pointer to MMC handle
+ * @param pCID Pointer to a HAL_MMC_CIDTypedef structure that
* contains all CID register parameters
* @retval HAL status
*/
@@ -1684,8 +1686,8 @@
/**
* @brief Returns information the information of the card which are stored on
* the CSD register.
- * @param hmmc: Pointer to MMC handle
- * @param pCSD: Pointer to a HAL_MMC_CardInfoTypeDef structure that
+ * @param hmmc Pointer to MMC handle
+ * @param pCSD Pointer to a HAL_MMC_CardInfoTypeDef structure that
* contains all CSD register parameters
* @retval HAL status
*/
@@ -1798,8 +1800,8 @@
/**
* @brief Gets the MMC card info.
- * @param hmmc: Pointer to MMC handle
- * @param pCardInfo: Pointer to the HAL_MMC_CardInfoTypeDef structure that
+ * @param hmmc Pointer to MMC handle
+ * @param pCardInfo Pointer to the HAL_MMC_CardInfoTypeDef structure that
* will contain the MMC card status information
* @retval HAL status
*/
@@ -1819,8 +1821,8 @@
/**
* @brief Enables wide bus operation for the requested card if supported by
* card.
- * @param hmmc: Pointer to MMC handle
- * @param WideMode: Specifies the MMC card wide bus mode
+ * @param hmmc Pointer to MMC handle
+ * @param WideMode Specifies the MMC card wide bus mode
* This parameter can be one of the following values:
* @arg SDMMC_BUS_WIDE_8B: 8-bit data transfer
* @arg SDMMC_BUS_WIDE_4B: 4-bit data transfer
@@ -1954,7 +1956,7 @@
/**
* @brief Gets the current mmc card data state.
- * @param hmmc: pointer to MMC handle
+ * @param hmmc pointer to MMC handle
* @retval Card state
*/
HAL_MMC_CardStateTypeDef HAL_MMC_GetCardState(MMC_HandleTypeDef *hmmc)
@@ -1976,7 +1978,7 @@
/**
* @brief Abort the current transfer and disable the MMC.
- * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains
+ * @param hmmc pointer to a MMC_HandleTypeDef structure that contains
* the configuration information for MMC module.
* @retval HAL status
*/
@@ -2023,7 +2025,7 @@
/**
* @brief Abort the current transfer and disable the MMC (IT mode).
- * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains
+ * @param hmmc pointer to a MMC_HandleTypeDef structure that contains
* the configuration information for MMC module.
* @retval HAL status
*/
@@ -2100,7 +2102,7 @@
/**
* @brief DMA MMC transmit process complete callback
- * @param hdma: DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void MMC_DMATransmitCplt(DMA_HandleTypeDef *hdma)
@@ -2113,7 +2115,7 @@
/**
* @brief DMA MMC receive process complete callback
- * @param hdma: DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void MMC_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
@@ -2146,7 +2148,7 @@
/**
* @brief DMA MMC communication error callback
- * @param hdma: DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void MMC_DMAError(DMA_HandleTypeDef *hdma)
@@ -2154,6 +2156,7 @@
MMC_HandleTypeDef* hmmc = (MMC_HandleTypeDef* )(hdma->Parent);
HAL_MMC_CardStateTypeDef CardState;
+ // MBED: changed
if((hmmc->hdmarx->ErrorCode == HAL_DMA_ERROR_TE) || (hmmc->hdmatx->ErrorCode == HAL_DMA_ERROR_TE))
{
/* Clear All flags */
@@ -2178,7 +2181,7 @@
/**
* @brief DMA MMC Tx Abort callback
- * @param hdma: DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void MMC_DMATxAbort(DMA_HandleTypeDef *hdma)
@@ -2215,7 +2218,7 @@
/**
* @brief DMA MMC Rx Abort callback
- * @param hdma: DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void MMC_DMARxAbort(DMA_HandleTypeDef *hdma)
@@ -2253,7 +2256,7 @@
/**
* @brief Initializes the mmc card.
- * @param hmmc: Pointer to MMC handle
+ * @param hmmc Pointer to MMC handle
* @retval MMC Card error state
*/
static uint32_t MMC_InitCard(MMC_HandleTypeDef *hmmc)
@@ -2334,7 +2337,7 @@
* @brief Enquires cards about their operating voltage and configures clock
* controls and stores MMC information that will be needed in future
* in the MMC handle.
- * @param hmmc: Pointer to MMC handle
+ * @param hmmc Pointer to MMC handle
* @retval error state
*/
static uint32_t MMC_PowerON(MMC_HandleTypeDef *hmmc)
@@ -2388,7 +2391,7 @@
/**
* @brief Turns the SDMMC output signals off.
- * @param hmmc: Pointer to MMC handle
+ * @param hmmc Pointer to MMC handle
* @retval HAL status
*/
static HAL_StatusTypeDef MMC_PowerOFF(MMC_HandleTypeDef *hmmc)
@@ -2401,8 +2404,8 @@
/**
* @brief Returns the current card's status.
- * @param hmmc: Pointer to MMC handle
- * @param pCardStatus: pointer to the buffer that will contain the MMC card
+ * @param hmmc Pointer to MMC handle
+ * @param pCardStatus pointer to the buffer that will contain the MMC card
* status (Card Status register)
* @retval error state
*/
@@ -2430,7 +2433,7 @@
/**
* @brief Wrap up reading in non-blocking mode.
- * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains
+ * @param hmmc pointer to a MMC_HandleTypeDef structure that contains
* the configuration information.
* @retval HAL status
*/
@@ -2454,7 +2457,7 @@
/**
* @brief Wrap up writing in non-blocking mode.
- * @param hmmc: pointer to a MMC_HandleTypeDef structure that contains
+ * @param hmmc pointer to a MMC_HandleTypeDef structure that contains
* the configuration information.
* @retval HAL status
*/
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_mmc.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_mmc.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_mmc.h * @author MCD Application Team - * @version V1.2.0 - * @date 30-December-2016 * @brief Header file of MMC HAL module. ****************************************************************************** * @attention @@ -364,8 +362,8 @@ /** * @brief Enable the MMC device interrupt. - * @param __HANDLE__: MMC Handle - * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled. + * @param __HANDLE__ MMC Handle + * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled. * This parameter can be one or a combination of the following values: * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -395,8 +393,8 @@ /** * @brief Disable the MMC device interrupt. - * @param __HANDLE__: MMC Handle - * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled. + * @param __HANDLE__ MMC Handle + * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled. * This parameter can be one or a combination of the following values: * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -426,8 +424,8 @@ /** * @brief Check whether the specified MMC flag is set or not. - * @param __HANDLE__: MMC Handle - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ MMC Handle + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) @@ -457,8 +455,8 @@ /** * @brief Clear the MMC's pending flags. - * @param __HANDLE__: MMC Handle - * @param __FLAG__: specifies the flag to clear. + * @param __HANDLE__ MMC Handle + * @param __FLAG__ specifies the flag to clear. * This parameter can be one or a combination of the following values: * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) @@ -477,8 +475,8 @@ /** * @brief Check whether the specified MMC interrupt has occurred or not. - * @param __HANDLE__: MMC Handle - * @param __INTERRUPT__: specifies the SDMMC interrupt source to check. + * @param __HANDLE__ MMC Handle + * @param __INTERRUPT__ specifies the SDMMC interrupt source to check. * This parameter can be one of the following values: * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -508,8 +506,8 @@ /** * @brief Clear the MMC's interrupt pending bits. - * @param __HANDLE__: MMC Handle - * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * @param __HANDLE__ MMC Handle + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. * This parameter can be one or a combination of the following values: * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_nand.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_nand.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_nand.c
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief NAND HAL module driver.
* This file provides a generic firmware to drive NAND memories mounted
* as external device.
@@ -128,10 +126,10 @@
/**
* @brief Perform NAND memory Initialization sequence
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
- * @param ComSpace_Timing: pointer to Common space timing structure
- * @param AttSpace_Timing: pointer to Attribute space timing structure
+ * @param ComSpace_Timing pointer to Common space timing structure
+ * @param AttSpace_Timing pointer to Attribute space timing structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing)
@@ -170,7 +168,7 @@
/**
* @brief Perform NAND memory De-Initialization sequence
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval HAL status
*/
@@ -193,7 +191,7 @@
/**
* @brief NAND MSP Init
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval None
*/
@@ -209,7 +207,7 @@
/**
* @brief NAND MSP DeInit
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval None
*/
@@ -226,7 +224,7 @@
/**
* @brief This function handles NAND device interrupt request.
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval HAL status
*/
@@ -276,7 +274,7 @@
/**
* @brief NAND interrupt feature callback
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval None
*/
@@ -311,9 +309,9 @@
/**
* @brief Read the NAND memory electronic signature
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
- * @param pNAND_ID: NAND ID structure
+ * @param pNAND_ID NAND ID structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID)
@@ -377,7 +375,7 @@
/**
* @brief NAND memory reset
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval HAL status
*/
@@ -415,9 +413,9 @@
/**
* @brief Configure the device: Enter the physical parameters of the device
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
- * @param pDeviceConfig : pointer to NAND_DeviceConfigTypeDef structure
+ * @param pDeviceConfig pointer to NAND_DeviceConfigTypeDef structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig)
@@ -436,11 +434,11 @@
/**
* @brief Read Page(s) from NAND memory block (8-bits addressing)
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
- * @param pAddress : pointer to NAND address structure
- * @param pBuffer : pointer to destination read buffer
- * @param NumPageToRead : number of pages to read from block
+ * @param pAddress pointer to NAND address structure
+ * @param pBuffer pointer to destination read buffer
+ * @param NumPageToRead number of pages to read from block
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead)
@@ -580,11 +578,11 @@
/**
* @brief Read Page(s) from NAND memory block (16-bits addressing)
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
- * @param pAddress : pointer to NAND address structure
- * @param pBuffer : pointer to destination read buffer. pBuffer should be 16bits aligned
- * @param NumPageToRead : number of pages to read from block
+ * @param pAddress pointer to NAND address structure
+ * @param pBuffer pointer to destination read buffer. pBuffer should be 16bits aligned
+ * @param NumPageToRead number of pages to read from block
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead)
@@ -722,11 +720,11 @@
/**
* @brief Write Page(s) to NAND memory block (8-bits addressing)
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
- * @param pAddress : pointer to NAND address structure
- * @param pBuffer : pointer to source buffer to write
- * @param NumPageToWrite : number of pages to write to block
+ * @param pAddress pointer to NAND address structure
+ * @param pBuffer pointer to source buffer to write
+ * @param NumPageToWrite number of pages to write to block
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite)
@@ -827,12 +825,12 @@
*(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
__DSB();
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
/* Read status until NAND is ready */
while(HAL_NAND_Read_Status(hnand) != NAND_READY)
- {
- /* Get tick */
- tickstart = HAL_GetTick();
-
+ {
if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
{
return HAL_TIMEOUT;
@@ -860,11 +858,11 @@
/**
* @brief Write Page(s) to NAND memory block (16-bits addressing)
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
- * @param pAddress : pointer to NAND address structure
- * @param pBuffer : pointer to source buffer to write. pBuffer should be 16bits aligned
- * @param NumPageToWrite : number of pages to write to block
+ * @param pAddress pointer to NAND address structure
+ * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned
+ * @param NumPageToWrite number of pages to write to block
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite)
@@ -965,12 +963,12 @@
*(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
__DSB();
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
/* Read status until NAND is ready */
while(HAL_NAND_Read_Status(hnand) != NAND_READY)
- {
- /* Get tick */
- tickstart = HAL_GetTick();
-
+ {
if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
{
return HAL_TIMEOUT;
@@ -998,11 +996,11 @@
/**
* @brief Read Spare area(s) from NAND memory (8-bits addressing)
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
- * @param pAddress : pointer to NAND address structure
- * @param pBuffer: pointer to source buffer to write
- * @param NumSpareAreaToRead: Number of spare area to read
+ * @param pAddress pointer to NAND address structure
+ * @param pBuffer pointer to source buffer to write
+ * @param NumSpareAreaToRead Number of spare area to read
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead)
@@ -1147,11 +1145,11 @@
/**
* @brief Read Spare area(s) from NAND memory (16-bits addressing)
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
- * @param pAddress : pointer to NAND address structure
- * @param pBuffer: pointer to source buffer to write. pBuffer should be 16bits aligned.
- * @param NumSpareAreaToRead: Number of spare area to read
+ * @param pAddress pointer to NAND address structure
+ * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned.
+ * @param NumSpareAreaToRead Number of spare area to read
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead)
@@ -1296,11 +1294,11 @@
/**
* @brief Write Spare area(s) to NAND memory (8-bits addressing)
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
- * @param pAddress : pointer to NAND address structure
- * @param pBuffer : pointer to source buffer to write
- * @param NumSpareAreaTowrite : number of spare areas to write to block
+ * @param pAddress pointer to NAND address structure
+ * @param pBuffer pointer to source buffer to write
+ * @param NumSpareAreaTowrite number of spare areas to write to block
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite)
@@ -1410,12 +1408,12 @@
*(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
__DSB();
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
/* Read status until NAND is ready */
while(HAL_NAND_Read_Status(hnand) != NAND_READY)
- {
- /* Get tick */
- tickstart = HAL_GetTick();
-
+ {
if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
{
return HAL_TIMEOUT;
@@ -1443,11 +1441,11 @@
/**
* @brief Write Spare area(s) to NAND memory (16-bits addressing)
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
- * @param pAddress : pointer to NAND address structure
- * @param pBuffer : pointer to source buffer to write. pBuffer should be 16bits aligned.
- * @param NumSpareAreaTowrite : number of spare areas to write to block
+ * @param pAddress pointer to NAND address structure
+ * @param pBuffer pointer to source buffer to write. pBuffer should be 16bits aligned.
+ * @param NumSpareAreaTowrite number of spare areas to write to block
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite)
@@ -1557,12 +1555,12 @@
*(__IO uint8_t *)((uint32_t)(deviceAddress | CMD_AREA)) = NAND_CMD_WRITE_TRUE1;
__DSB();
+ /* Get tick */
+ tickstart = HAL_GetTick();
+
/* Read status until NAND is ready */
while(HAL_NAND_Read_Status(hnand) != NAND_READY)
- {
- /* Get tick */
- tickstart = HAL_GetTick();
-
+ {
if((HAL_GetTick() - tickstart ) > NAND_WRITE_TIMEOUT)
{
return HAL_TIMEOUT;
@@ -1590,9 +1588,9 @@
/**
* @brief NAND memory Block erase
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
- * @param pAddress : pointer to NAND address structure
+ * @param pAddress pointer to NAND address structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress)
@@ -1638,9 +1636,9 @@
/**
* @brief Increment the NAND memory address
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
- * @param pAddress: pointer to NAND address structure
+ * @param pAddress pointer to NAND address structure
* @retval The new status of the increment address operation. It can be:
* - NAND_VALID_ADDRESS: When the new address is valid address
* - NAND_INVALID_ADDRESS: When the new address is invalid address
@@ -1694,7 +1692,7 @@
/**
* @brief Enables dynamically NAND ECC feature.
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval HAL status
*/
@@ -1720,7 +1718,7 @@
/**
* @brief Disables dynamically FMC_NAND ECC feature.
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval HAL status
*/
@@ -1746,10 +1744,10 @@
/**
* @brief Disables dynamically NAND ECC feature.
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
- * @param ECCval: pointer to ECC value
- * @param Timeout: maximum timeout to wait
+ * @param ECCval pointer to ECC value
+ * @param Timeout maximum timeout to wait
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout)
@@ -1796,7 +1794,7 @@
/**
* @brief return the NAND state
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval HAL state
*/
@@ -1807,7 +1805,7 @@
/**
* @brief NAND memory read status
- * @param hnand: pointer to a NAND_HandleTypeDef structure that contains
+ * @param hnand pointer to a NAND_HandleTypeDef structure that contains
* the configuration information for NAND module.
* @retval NAND status
*/
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_nand.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_nand.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_nand.h * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief Header file of NAND HAL module. ****************************************************************************** * @attention @@ -154,7 +152,7 @@ */ /** @brief Reset NAND handle state - * @param __HANDLE__: specifies the NAND handle. + * @param __HANDLE__ specifies the NAND handle. * @retval None */ #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET) @@ -285,8 +283,8 @@ /** * @brief NAND memory address computation. - * @param __ADDRESS__: NAND memory address. - * @param __HANDLE__ : NAND handle. + * @param __ADDRESS__ NAND memory address. + * @param __HANDLE__ NAND handle. * @retval NAND Raw address value */ #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \ @@ -296,7 +294,7 @@ /** * @brief NAND memory address cycling. - * @param __ADDRESS__: NAND memory address. + * @param __ADDRESS__ NAND memory address. * @retval NAND address cycling value. */ #define ADDR_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st addressing cycle */ @@ -306,7 +304,7 @@ /** * @brief NAND memory Columns cycling. - * @param __ADDRESS__: NAND memory address. + * @param __ADDRESS__ NAND memory address. * @retval NAND Column address cycling value. */ #define COLUMN_1ST_CYCLE(__ADDRESS__) (uint8_t)(__ADDRESS__) /* 1st Column addressing cycle */
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_nor.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_nor.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_nor.c
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief NOR HAL module driver.
* This file provides a generic firmware to drive NOR memories mounted
* as external device.
@@ -170,10 +168,10 @@
/**
* @brief Perform the NOR memory Initialization sequence
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
- * @param Timing: pointer to NOR control timing structure
- * @param ExtTiming: pointer to NOR extended mode timing structure
+ * @param Timing pointer to NOR control timing structure
+ * @param ExtTiming pointer to NOR extended mode timing structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_Init(NOR_HandleTypeDef *hnor, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
@@ -222,7 +220,7 @@
/**
* @brief Perform NOR memory De-Initialization sequence
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @retval HAL status
*/
@@ -245,7 +243,7 @@
/**
* @brief NOR MSP Init
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @retval None
*/
@@ -261,7 +259,7 @@
/**
* @brief NOR MSP DeInit
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @retval None
*/
@@ -277,9 +275,9 @@
/**
* @brief NOR MSP Wait for Ready/Busy signal
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
- * @param Timeout: Maximum timeout value
+ * @param Timeout Maximum timeout value
* @retval None
*/
__weak void HAL_NOR_MspWait(NOR_HandleTypeDef *hnor, uint32_t Timeout)
@@ -313,9 +311,9 @@
/**
* @brief Read NOR flash IDs
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
- * @param pNOR_ID : pointer to NOR ID structure
+ * @param pNOR_ID pointer to NOR ID structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_Read_ID(NOR_HandleTypeDef *hnor, NOR_IDTypeDef *pNOR_ID)
@@ -374,7 +372,7 @@
/**
* @brief Returns the NOR memory to Read mode.
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @retval HAL status
*/
@@ -422,10 +420,10 @@
/**
* @brief Read data from NOR memory
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
- * @param pAddress: pointer to Device address
- * @param pData : pointer to read data
+ * @param pAddress pointer to Device address
+ * @param pData pointer to read data
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_Read(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
@@ -481,10 +479,10 @@
/**
* @brief Program data to NOR memory
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
- * @param pAddress: Device address
- * @param pData : pointer to the data to write
+ * @param pAddress Device address
+ * @param pData pointer to the data to write
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_Program(NOR_HandleTypeDef *hnor, uint32_t *pAddress, uint16_t *pData)
@@ -540,11 +538,11 @@
/**
* @brief Reads a half-word buffer from the NOR memory.
- * @param hnor: pointer to the NOR handle
- * @param uwAddress: NOR memory internal address to read from.
- * @param pData: pointer to the buffer that receives the data read from the
+ * @param hnor pointer to the NOR handle
+ * @param uwAddress NOR memory internal address to read from.
+ * @param pData pointer to the buffer that receives the data read from the
* NOR memory.
- * @param uwBufferSize : number of Half word to read.
+ * @param uwBufferSize number of Half word to read.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_ReadBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
@@ -606,10 +604,10 @@
/**
* @brief Writes a half-word buffer to the NOR memory. This function must be used
only with S29GL128P NOR memory.
- * @param hnor: pointer to the NOR handle
- * @param uwAddress: NOR memory internal start write address
- * @param pData: pointer to source data buffer.
- * @param uwBufferSize: Size of the buffer to write
+ * @param hnor pointer to the NOR handle
+ * @param uwAddress NOR memory internal start write address
+ * @param pData pointer to source data buffer.
+ * @param uwBufferSize Size of the buffer to write
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_ProgramBuffer(NOR_HandleTypeDef *hnor, uint32_t uwAddress, uint16_t *pData, uint32_t uwBufferSize)
@@ -686,10 +684,10 @@
/**
* @brief Erase the specified block of the NOR memory
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
- * @param BlockAddress : Block to erase address
- * @param Address: Device address
+ * @param BlockAddress Block to erase address
+ * @param Address Device address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_Erase_Block(NOR_HandleTypeDef *hnor, uint32_t BlockAddress, uint32_t Address)
@@ -746,9 +744,9 @@
/**
* @brief Erase the entire NOR chip.
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
- * @param Address : Device address
+ * @param Address Device address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_Erase_Chip(NOR_HandleTypeDef *hnor, uint32_t Address)
@@ -804,9 +802,9 @@
/**
* @brief Read NOR flash CFI IDs
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
- * @param pNOR_CFI : pointer to NOR CFI IDs structure
+ * @param pNOR_CFI pointer to NOR CFI IDs structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_NOR_Read_CFI(NOR_HandleTypeDef *hnor, NOR_CFITypeDef *pNOR_CFI)
@@ -882,7 +880,7 @@
/**
* @brief Enables dynamically NOR write operation.
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @retval HAL status
*/
@@ -905,7 +903,7 @@
/**
* @brief Disables dynamically NOR write operation.
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @retval HAL status
*/
@@ -950,7 +948,7 @@
/**
* @brief return the NOR controller state
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
* @retval NOR controller state
*/
@@ -961,10 +959,10 @@
/**
* @brief Returns the NOR operation status.
- * @param hnor: pointer to a NOR_HandleTypeDef structure that contains
+ * @param hnor pointer to a NOR_HandleTypeDef structure that contains
* the configuration information for NOR module.
- * @param Address: Device address
- * @param Timeout: NOR programming Timeout
+ * @param Address Device address
+ * @param Timeout NOR programming Timeout
* @retval NOR_Status: The returned value can be: HAL_NOR_STATUS_SUCCESS, HAL_NOR_STATUS_ERROR
* or HAL_NOR_STATUS_TIMEOUT
*/
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_nor.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_nor.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_nor.h
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief Header file of NOR HAL module.
******************************************************************************
* @attention
@@ -144,7 +142,7 @@
* @{
*/
/** @brief Reset NOR handle state
- * @param __HANDLE__: specifies the NOR handle.
+ * @param __HANDLE__ specifies the NOR handle.
* @retval None
*/
#define __HAL_NOR_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NOR_STATE_RESET)
@@ -257,9 +255,9 @@
*/
/**
* @brief NOR memory address shifting.
- * @param __NOR_ADDRESS: NOR base address
- * @param __NOR_MEMORY_WIDTH_: NOR memory width
- * @param __ADDRESS__: NOR memory address
+ * @param __NOR_ADDRESS NOR base address
+ * @param __NOR_MEMORY_WIDTH_ NOR memory width
+ * @param __ADDRESS__ NOR memory address
* @retval NOR shifted address value
*/
#define NOR_ADDR_SHIFT(__NOR_ADDRESS, __NOR_MEMORY_WIDTH_, __ADDRESS__) \
@@ -269,8 +267,8 @@
/**
* @brief NOR memory write data to specified address.
- * @param __ADDRESS__: NOR memory address
- * @param __DATA__: Data to write
+ * @param __ADDRESS__ NOR memory address
+ * @param __DATA__ Data to write
* @retval None
*/
#define NOR_WRITE(__ADDRESS__, __DATA__) do{ \
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pcd.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pcd.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,16 +2,14 @@
******************************************************************************
* @file stm32f7xx_hal_pcd.c
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief PCD HAL module driver.
- * This file provides firmware functions to manage the following
+ * This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
* + Initialization and de-initialization functions
* + IO operation functions
- * + Peripheral Control functions
+ * + Peripheral Control functions
* + Peripheral State functions
- *
+ *
@verbatim
==============================================================================
##### How to use this driver #####
@@ -21,20 +19,20 @@
(#) Declare a PCD_HandleTypeDef handle structure, for example:
PCD_HandleTypeDef hpcd;
-
+
(#) Fill parameters of Init structure in HCD handle
-
- (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...)
+
+ (#) Call HAL_PCD_Init() API to initialize the PCD peripheral (Core, Device core, ...)
(#) Initialize the PCD low level resources through the HAL_PCD_MspInit() API:
- (##) Enable the PCD/USB Low Level interface clock using
+ (##) Enable the PCD/USB Low Level interface clock using
(+++) __HAL_RCC_USB_OTG_FS_CLK_ENABLE();
(+++) __HAL_RCC_USB_OTG_HS_CLK_ENABLE(); (For High Speed Mode)
-
+
(##) Initialize the related GPIO clocks
(##) Configure PCD pin-out
(##) Configure PCD NVIC interrupt
-
+
(#)Associate the Upper USB device stack to the HAL PCD Driver:
(##) hpcd.pData = pdev;
@@ -70,7 +68,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
- */
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
@@ -92,7 +90,7 @@
/* Private macros ------------------------------------------------------------*/
/** @defgroup PCD_Private_Macros PCD Private Macros
* @{
- */
+ */
#define PCD_MIN(a, b) (((a) < (b)) ? (a) : (b))
#define PCD_MAX(a, b) (((a) > (b)) ? (a) : (b))
/**
@@ -113,15 +111,15 @@
* @{
*/
-/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
+/** @defgroup PCD_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
*
-@verbatim
+@verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..] This section provides functions allowing to:
-
+
@endverbatim
* @{
*/
@@ -129,22 +127,23 @@
/**
* @brief Initializes the PCD according to the specified
* parameters in the PCD_InitTypeDef and create the associated handle.
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_Init(PCD_HandleTypeDef *hpcd)
-{
+{
uint32_t i = 0;
-
+
/* Check the PCD handle allocation */
if(hpcd == NULL)
{
return HAL_ERROR;
}
-
+
/* Check the parameters */
assert_param(IS_PCD_ALL_INSTANCE(hpcd->Instance));
+ // MBED: added
if(hpcd->State == HAL_PCD_STATE_RESET)
{
/* Allocate lock resource and initialize it */
@@ -156,19 +155,19 @@
}
hpcd->State = HAL_PCD_STATE_BUSY;
-
+
/* Init the low level hardware : GPIO, CLOCK, NVIC... */
HAL_PCD_MspInit(hpcd);
/* Disable the Interrupts */
__HAL_PCD_DISABLE(hpcd);
-
+
/*Init the Core (common init.) */
USB_CoreInit(hpcd->Instance, hpcd->Init);
-
+
/* Force Device Mode*/
USB_SetCurrentMode(hpcd->Instance , USB_OTG_DEVICE_MODE);
-
+
/* Init endpoints structures */
for (i = 0; i < 15 ; i++)
{
@@ -182,7 +181,7 @@
hpcd->IN_ep[i].xfer_buff = 0;
hpcd->IN_ep[i].xfer_len = 0;
}
-
+
for (i = 0; i < 15 ; i++)
{
hpcd->OUT_ep[i].is_in = 0;
@@ -193,34 +192,35 @@
hpcd->OUT_ep[i].maxpacket = 0;
hpcd->OUT_ep[i].xfer_buff = 0;
hpcd->OUT_ep[i].xfer_len = 0;
-
+
hpcd->Instance->DIEPTXF[i] = 0;
}
+
/* Init Device */
USB_DevInit(hpcd->Instance, hpcd->Init);
-
+
hpcd->State= HAL_PCD_STATE_READY;
-
+
/* Activate LPM */
if (hpcd->Init.lpm_enable ==1)
{
HAL_PCDEx_ActivateLPM(hpcd);
}
-#if defined (USB_OTG_GCCFG_BCDEN)
+#if defined (USB_OTG_GCCFG_BCDEN)
/* Activate Battery charging */
if (hpcd->Init.battery_charging_enable ==1)
{
HAL_PCDEx_ActivateBCD(hpcd);
}
-#endif /* USB_OTG_GCCFG_BCDEN */
-
- USB_DevDisconnect (hpcd->Instance);
+#endif /* USB_OTG_GCCFG_BCDEN */
+
+ USB_DevDisconnect (hpcd->Instance);
return HAL_OK;
}
/**
- * @brief DeInitializes the PCD peripheral.
- * @param hpcd: PCD handle
+ * @brief DeInitializes the PCD peripheral.
+ * @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_DeInit(PCD_HandleTypeDef *hpcd)
@@ -232,28 +232,28 @@
}
hpcd->State = HAL_PCD_STATE_BUSY;
-
+
/* Stop Device */
HAL_PCD_Stop(hpcd);
-
+
/* DeInit the low level hardware */
HAL_PCD_MspDeInit(hpcd);
-
- hpcd->State = HAL_PCD_STATE_RESET;
-
+
+ hpcd->State = HAL_PCD_STATE_RESET;
+
return HAL_OK;
}
/**
* @brief Initializes the PCD MSP.
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval None
*/
__weak void HAL_PCD_MspInit(PCD_HandleTypeDef *hpcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
-
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCD_MspInit could be implemented in the user file
*/
@@ -261,14 +261,14 @@
/**
* @brief DeInitializes PCD MSP.
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval None
*/
__weak void HAL_PCD_MspDeInit(PCD_HandleTypeDef *hpcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
-
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCD_MspDeInit could be implemented in the user file
*/
@@ -279,52 +279,52 @@
*/
/** @defgroup PCD_Exported_Functions_Group2 Input and Output operation functions
- * @brief Data transfers functions
+ * @brief Data transfers functions
*
-@verbatim
+@verbatim
===============================================================================
##### IO operation functions #####
- ===============================================================================
+ ===============================================================================
[..]
- This subsection provides a set of functions allowing to manage the PCD data
+ This subsection provides a set of functions allowing to manage the PCD data
transfers.
@endverbatim
* @{
*/
-
+
/**
* @brief Start The USB OTG Device.
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_Start(PCD_HandleTypeDef *hpcd)
-{
- __HAL_LOCK(hpcd);
- USB_DevConnect (hpcd->Instance);
+{
+ __HAL_LOCK(hpcd);
+ USB_DevConnect (hpcd->Instance);
__HAL_PCD_ENABLE(hpcd);
- __HAL_UNLOCK(hpcd);
+ __HAL_UNLOCK(hpcd);
return HAL_OK;
}
/**
* @brief Stop The USB OTG Device.
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_Stop(PCD_HandleTypeDef *hpcd)
-{
- __HAL_LOCK(hpcd);
+{
+ __HAL_LOCK(hpcd);
__HAL_PCD_DISABLE(hpcd);
USB_StopDevice(hpcd->Instance);
USB_DevDisconnect (hpcd->Instance);
- __HAL_UNLOCK(hpcd);
+ __HAL_UNLOCK(hpcd);
return HAL_OK;
}
/**
* @brief Handle PCD interrupt request.
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval HAL status
*/
void HAL_PCD_IRQHandler(PCD_HandleTypeDef *hpcd)
@@ -334,45 +334,54 @@
uint32_t fifoemptymsk = 0, temp = 0;
USB_OTG_EPTypeDef *ep = NULL;
uint32_t hclk = 200000000;
-
+
/* ensure that we are in device mode */
if (USB_GetMode(hpcd->Instance) == USB_OTG_MODE_DEVICE)
{
/* avoid spurious interrupt */
- if(__HAL_PCD_IS_INVALID_INTERRUPT(hpcd))
+ if(__HAL_PCD_IS_INVALID_INTERRUPT(hpcd))
{
return;
}
-
+
if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_MMIS))
{
/* incorrect mode, acknowledge the interrupt */
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_MMIS);
}
-
+
if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OEPINT))
{
epnum = 0;
-
+
/* Read in the device interrupt bits */
ep_intr = USB_ReadDevAllOutEpInterrupt(hpcd->Instance);
-
+
while ( ep_intr )
{
if (ep_intr & 0x1)
{
epint = USB_ReadDevOutEPInterrupt(hpcd->Instance, epnum);
-
+
if(( epint & USB_OTG_DOEPINT_XFRC) == USB_OTG_DOEPINT_XFRC)
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_XFRC);
-
+
+ /* setup/out transaction management for Core ID >= 310A */
+ if (hpcd->Init.dma_enable == 1)
+ {
+ if (USBx_OUTEP(0)->DOEPINT & (1 << 15))
+ {
+ CLEAR_OUT_EP_INTR(epnum, (1 << 15));
+ }
+ }
+
if(hpcd->Init.dma_enable == 1)
{
- hpcd->OUT_ep[epnum].xfer_count = hpcd->OUT_ep[epnum].maxpacket- (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ);
- hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket;
+ hpcd->OUT_ep[epnum].xfer_count = hpcd->OUT_ep[epnum].maxpacket- (USBx_OUTEP(epnum)->DOEPTSIZ & USB_OTG_DOEPTSIZ_XFRSIZ);
+ hpcd->OUT_ep[epnum].xfer_buff += hpcd->OUT_ep[epnum].maxpacket;
}
-
+
HAL_PCD_DataOutStageCallback(hpcd, epnum);
if(hpcd->Init.dma_enable == 1)
{
@@ -380,17 +389,26 @@
{
/* this is ZLP, so prepare EP0 for next setup */
USB_EP0_OutStart(hpcd->Instance, 1, (uint8_t *)hpcd->Setup);
- }
+ }
}
}
-
+
if(( epint & USB_OTG_DOEPINT_STUP) == USB_OTG_DOEPINT_STUP)
{
+ /* setup/out transaction management for Core ID >= 310A */
+ if (hpcd->Init.dma_enable == 1)
+ {
+ if (USBx_OUTEP(0)->DOEPINT & (1 << 15))
+ {
+ CLEAR_OUT_EP_INTR(epnum, (1 << 15));
+ }
+ }
+
/* Inform the upper layer that a setup packet is available */
HAL_PCD_SetupStageCallback(hpcd);
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_STUP);
}
-
+
if(( epint & USB_OTG_DOEPINT_OTEPDIS) == USB_OTG_DOEPINT_OTEPDIS)
{
CLEAR_OUT_EP_INTR(epnum, USB_OTG_DOEPINT_OTEPDIS);
@@ -405,14 +423,14 @@
ep_intr >>= 1;
}
}
-
+
if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IEPINT))
{
/* Read in the device interrupt bits */
ep_intr = USB_ReadDevAllInEpInterrupt(hpcd->Instance);
-
+
epnum = 0;
-
+
while ( ep_intr )
{
if (ep_intr & 0x1) /* In ITR */
@@ -422,15 +440,15 @@
if(( epint & USB_OTG_DIEPINT_XFRC) == USB_OTG_DIEPINT_XFRC)
{
fifoemptymsk = 0x1 << epnum;
- atomic_clr_u32(&USBx_DEVICE->DIEPEMPMSK, fifoemptymsk);
-
+ atomic_clr_u32(&USBx_DEVICE->DIEPEMPMSK, fifoemptymsk); // MBED: changed
+
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_XFRC);
-
+
if (hpcd->Init.dma_enable == 1)
{
- hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket;
+ hpcd->IN_ep[epnum].xfer_buff += hpcd->IN_ep[epnum].maxpacket;
}
-
+
HAL_PCD_DataInStageCallback(hpcd, epnum);
if (hpcd->Init.dma_enable == 1)
@@ -441,7 +459,7 @@
/* prepare to rx more setup packets */
USB_EP0_OutStart(hpcd->Instance, 1, (uint8_t *)hpcd->Setup);
}
- }
+ }
}
if(( epint & USB_OTG_DIEPINT_TOC) == USB_OTG_DIEPINT_TOC)
{
@@ -458,7 +476,7 @@
if(( epint & USB_OTG_DIEPINT_EPDISD) == USB_OTG_DIEPINT_EPDISD)
{
CLEAR_IN_EP_INTR(epnum, USB_OTG_DIEPINT_EPDISD);
- }
+ }
if(( epint & USB_OTG_DIEPINT_TXFE) == USB_OTG_DIEPINT_TXFE)
{
PCD_WriteEmptyTxFifo(hpcd , epnum);
@@ -468,13 +486,13 @@
ep_intr >>= 1;
}
}
-
+
/* Handle Resume Interrupt */
if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT))
{
/* Clear the Remote Wake-up Signaling */
USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
-
+
if(hpcd->LPM_State == LPM_L1)
{
hpcd->LPM_State = LPM_L0;
@@ -486,22 +504,22 @@
}
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_WKUINT);
}
-
+
/* Handle Suspend Interrupt */
if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP))
{
if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
{
-
+
HAL_PCD_SuspendCallback(hpcd);
}
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBSUSP);
}
-
- /* Handle LPM Interrupt */
+
+ /* Handle LPM Interrupt */
if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT))
{
- __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT);
+ __HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_LPMINT);
if( hpcd->LPM_State == LPM_L0)
{
hpcd->LPM_State = LPM_L1;
@@ -513,47 +531,49 @@
HAL_PCD_SuspendCallback(hpcd);
}
}
-
+
/* Handle Reset Interrupt */
if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_USBRST))
{
- USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
+ USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_RWUSIG;
USB_FlushTxFifo(hpcd->Instance, 0x10);
-
+
for (i = 0; i < hpcd->Init.dev_endpoints ; i++)
{
USBx_INEP(i)->DIEPINT = 0xFF;
+ USBx_INEP(i)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
USBx_OUTEP(i)->DOEPINT = 0xFF;
+ USBx_OUTEP(i)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
}
USBx_DEVICE->DAINT = 0xFFFFFFFF;
USBx_DEVICE->DAINTMSK |= 0x10001;
-
+
if(hpcd->Init.use_dedicated_ep1)
{
- USBx_DEVICE->DOUTEP1MSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM);
- USBx_DEVICE->DINEP1MSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM);
+ USBx_DEVICE->DOUTEP1MSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM);
+ USBx_DEVICE->DINEP1MSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM);
}
else
{
USBx_DEVICE->DOEPMSK |= (USB_OTG_DOEPMSK_STUPM | USB_OTG_DOEPMSK_XFRCM | USB_OTG_DOEPMSK_EPDM | USB_OTG_DOEPMSK_OTEPSPRM);
USBx_DEVICE->DIEPMSK |= (USB_OTG_DIEPMSK_TOM | USB_OTG_DIEPMSK_XFRCM | USB_OTG_DIEPMSK_EPDM);
}
-
+
/* Set Default Address to 0 */
USBx_DEVICE->DCFG &= ~USB_OTG_DCFG_DAD;
-
+
/* setup EP0 to receive SETUP packets */
USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
-
+
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_USBRST);
}
-
+
/* Handle Enumeration done Interrupt */
if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE))
{
USB_ActivateSetup(hpcd->Instance);
hpcd->Instance->GUSBCFG &= ~USB_OTG_GUSBCFG_TRDT;
-
+
if ( USB_GetDevSpeed(hpcd->Instance) == USB_OTG_SPEED_HIGH)
{
hpcd->Init.speed = USB_OTG_SPEED_HIGH;
@@ -563,89 +583,89 @@
else
{
hpcd->Init.speed = USB_OTG_SPEED_FULL;
- hpcd->Init.ep0_mps = USB_OTG_FS_MAX_PACKET_SIZE ;
-
- /* The USBTRD is configured according to the tables below, depending on AHB frequency
- used by application. In the low AHB frequency range it is used to stretch enough the USB response
- time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access
+ hpcd->Init.ep0_mps = USB_OTG_FS_MAX_PACKET_SIZE ;
+
+ /* The USBTRD is configured according to the tables below, depending on AHB frequency
+ used by application. In the low AHB frequency range it is used to stretch enough the USB response
+ time to IN tokens, the USB turnaround time, so to compensate for the longer AHB read access
latency to the Data FIFO */
-
+
/* Get hclk frequency value */
hclk = HAL_RCC_GetHCLKFreq();
-
+
if((hclk >= 14200000)&&(hclk < 15000000))
{
/* hclk Clock Range between 14.2-15 MHz */
hpcd->Instance->GUSBCFG |= (uint32_t)((0xF << 10) & USB_OTG_GUSBCFG_TRDT);
}
-
+
else if((hclk >= 15000000)&&(hclk < 16000000))
{
/* hclk Clock Range between 15-16 MHz */
hpcd->Instance->GUSBCFG |= (uint32_t)((0xE << 10) & USB_OTG_GUSBCFG_TRDT);
}
-
+
else if((hclk >= 16000000)&&(hclk < 17200000))
{
/* hclk Clock Range between 16-17.2 MHz */
hpcd->Instance->GUSBCFG |= (uint32_t)((0xD << 10) & USB_OTG_GUSBCFG_TRDT);
}
-
+
else if((hclk >= 17200000)&&(hclk < 18500000))
{
/* hclk Clock Range between 17.2-18.5 MHz */
hpcd->Instance->GUSBCFG |= (uint32_t)((0xC << 10) & USB_OTG_GUSBCFG_TRDT);
}
-
+
else if((hclk >= 18500000)&&(hclk < 20000000))
{
/* hclk Clock Range between 18.5-20 MHz */
hpcd->Instance->GUSBCFG |= (uint32_t)((0xB << 10) & USB_OTG_GUSBCFG_TRDT);
}
-
+
else if((hclk >= 20000000)&&(hclk < 21800000))
{
/* hclk Clock Range between 20-21.8 MHz */
hpcd->Instance->GUSBCFG |= (uint32_t)((0xA << 10) & USB_OTG_GUSBCFG_TRDT);
}
-
+
else if((hclk >= 21800000)&&(hclk < 24000000))
{
/* hclk Clock Range between 21.8-24 MHz */
hpcd->Instance->GUSBCFG |= (uint32_t)((0x9 << 10) & USB_OTG_GUSBCFG_TRDT);
}
-
+
else if((hclk >= 24000000)&&(hclk < 27700000))
{
/* hclk Clock Range between 24-27.7 MHz */
hpcd->Instance->GUSBCFG |= (uint32_t)((0x8 << 10) & USB_OTG_GUSBCFG_TRDT);
}
-
+
else if((hclk >= 27700000)&&(hclk < 32000000))
{
/* hclk Clock Range between 27.7-32 MHz */
hpcd->Instance->GUSBCFG |= (uint32_t)((0x7 << 10) & USB_OTG_GUSBCFG_TRDT);
}
-
+
else /* if(hclk >= 32000000) */
{
/* hclk Clock Range between 32-200 MHz */
hpcd->Instance->GUSBCFG |= (uint32_t)((0x6 << 10) & USB_OTG_GUSBCFG_TRDT);
- }
+ }
}
-
+
HAL_PCD_ResetCallback(hpcd);
-
+
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_ENUMDNE);
}
-
+
/* Handle RxQLevel Interrupt */
if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_RXFLVL))
{
USB_MASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
temp = USBx->GRXSTSP;
ep = &hpcd->OUT_ep[temp & USB_OTG_GRXSTSP_EPNUM];
-
+
if(((temp & USB_OTG_GRXSTSP_PKTSTS) >> 17) == STS_DATA_UPDT)
{
if((temp & USB_OTG_GRXSTSP_BCNT) != 0)
@@ -662,40 +682,40 @@
}
USB_UNMASK_INTERRUPT(hpcd->Instance, USB_OTG_GINTSTS_RXFLVL);
}
-
+
/* Handle SOF Interrupt */
if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SOF))
{
HAL_PCD_SOFCallback(hpcd);
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SOF);
}
-
+
/* Handle Incomplete ISO IN Interrupt */
if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR))
{
HAL_PCD_ISOINIncompleteCallback(hpcd, epnum);
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_IISOIXFR);
- }
-
+ }
+
/* Handle Incomplete ISO OUT Interrupt */
if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT))
{
HAL_PCD_ISOOUTIncompleteCallback(hpcd, epnum);
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_PXFR_INCOMPISOOUT);
- }
-
+ }
+
/* Handle Connection event Interrupt */
if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT))
{
HAL_PCD_ConnectCallback(hpcd);
__HAL_PCD_CLEAR_FLAG(hpcd, USB_OTG_GINTSTS_SRQINT);
- }
-
+ }
+
/* Handle Disconnection event Interrupt */
if(__HAL_PCD_GET_FLAG(hpcd, USB_OTG_GINTSTS_OTGINT))
{
temp = hpcd->Instance->GOTGINT;
-
+
if((temp & USB_OTG_GOTGINT_SEDET) == USB_OTG_GOTGINT_SEDET)
{
HAL_PCD_DisconnectCallback(hpcd);
@@ -707,185 +727,185 @@
/**
* @brief Data OUT stage callback.
- * @param hpcd: PCD handle
- * @param epnum: endpoint number
+ * @param hpcd PCD handle
+ * @param epnum endpoint number
* @retval None
*/
__weak void HAL_PCD_DataOutStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
- UNUSED(epnum);
+ UNUSED(epnum);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCD_DataOutStageCallback could be implemented in the user file
- */
+ */
}
/**
* @brief Data IN stage callback.
- * @param hpcd: PCD handle
- * @param epnum: endpoint number
+ * @param hpcd PCD handle
+ * @param epnum endpoint number
* @retval None
*/
__weak void HAL_PCD_DataInStageCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
- UNUSED(epnum);
+ UNUSED(epnum);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCD_DataInStageCallback could be implemented in the user file
- */
+ */
}
/**
* @brief Setup stage callback.
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval None
*/
__weak void HAL_PCD_SetupStageCallback(PCD_HandleTypeDef *hpcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
-
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCD_SetupStageCallback could be implemented in the user file
- */
+ */
}
/**
* @brief USB Start Of Frame callback.
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval None
*/
__weak void HAL_PCD_SOFCallback(PCD_HandleTypeDef *hpcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
-
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCD_SOFCallback could be implemented in the user file
- */
+ */
}
/**
* @brief USB Reset callback.
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval None
*/
__weak void HAL_PCD_ResetCallback(PCD_HandleTypeDef *hpcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
-
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCD_ResetCallback could be implemented in the user file
- */
+ */
}
/**
* @brief Suspend event callback.
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval None
*/
__weak void HAL_PCD_SuspendCallback(PCD_HandleTypeDef *hpcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
-
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCD_SuspendCallback could be implemented in the user file
- */
+ */
}
/**
* @brief Resume event callback.
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval None
*/
__weak void HAL_PCD_ResumeCallback(PCD_HandleTypeDef *hpcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
-
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCD_ResumeCallback could be implemented in the user file
- */
+ */
}
/**
* @brief Incomplete ISO OUT callback.
- * @param hpcd: PCD handle
- * @param epnum: endpoint number
+ * @param hpcd PCD handle
+ * @param epnum endpoint number
* @retval None
*/
__weak void HAL_PCD_ISOOUTIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
- UNUSED(epnum);
+ UNUSED(epnum);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCD_ISOOUTIncompleteCallback could be implemented in the user file
- */
+ */
}
/**
* @brief Incomplete ISO IN callback.
- * @param hpcd: PCD handle
- * @param epnum: endpoint number
+ * @param hpcd PCD handle
+ * @param epnum endpoint number
* @retval None
*/
__weak void HAL_PCD_ISOINIncompleteCallback(PCD_HandleTypeDef *hpcd, uint8_t epnum)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
- UNUSED(epnum);
+ UNUSED(epnum);
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCD_ISOINIncompleteCallback could be implemented in the user file
- */
+ */
}
/**
* @brief Connection event callback.
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval None
*/
__weak void HAL_PCD_ConnectCallback(PCD_HandleTypeDef *hpcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
-
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCD_ConnectCallback could be implemented in the user file
- */
+ */
}
/**
* @brief Disconnection event callback.
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval None
*/
__weak void HAL_PCD_DisconnectCallback(PCD_HandleTypeDef *hpcd)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hpcd);
-
+
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_PCD_DisconnectCallback could be implemented in the user file
- */
+ */
}
/**
* @}
*/
-
+
/** @defgroup PCD_Exported_Functions_Group3 Peripheral Control functions
- * @brief management functions
+ * @brief management functions
*
-@verbatim
+@verbatim
===============================================================================
##### Peripheral Control functions #####
- ===============================================================================
+ ===============================================================================
[..]
- This subsection provides a set of functions allowing to control the PCD data
+ This subsection provides a set of functions allowing to control the PCD data
transfers.
@endverbatim
@@ -894,56 +914,56 @@
/**
* @brief Connect the USB device.
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_DevConnect(PCD_HandleTypeDef *hpcd)
{
- __HAL_LOCK(hpcd);
+ __HAL_LOCK(hpcd);
USB_DevConnect(hpcd->Instance);
- __HAL_UNLOCK(hpcd);
+ __HAL_UNLOCK(hpcd);
return HAL_OK;
}
/**
* @brief Disconnect the USB device.
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_DevDisconnect(PCD_HandleTypeDef *hpcd)
{
- __HAL_LOCK(hpcd);
+ __HAL_LOCK(hpcd);
USB_DevDisconnect(hpcd->Instance);
- __HAL_UNLOCK(hpcd);
+ __HAL_UNLOCK(hpcd);
return HAL_OK;
}
/**
- * @brief Set the USB Device address.
- * @param hpcd: PCD handle
- * @param address: new device address
+ * @brief Set the USB Device address.
+ * @param hpcd PCD handle
+ * @param address new device address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_SetAddress(PCD_HandleTypeDef *hpcd, uint8_t address)
{
- __HAL_LOCK(hpcd);
+ __HAL_LOCK(hpcd);
USB_SetDevAddress(hpcd->Instance, address);
- __HAL_UNLOCK(hpcd);
+ __HAL_UNLOCK(hpcd);
return HAL_OK;
}
/**
* @brief Open and configure an endpoint.
- * @param hpcd: PCD handle
- * @param ep_addr: endpoint address
- * @param ep_mps: endpoint max packet size
- * @param ep_type: endpoint type
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
+ * @param ep_mps endpoint max packet size
+ * @param ep_type endpoint type
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Open(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint16_t ep_mps, uint8_t ep_type)
{
HAL_StatusTypeDef ret = HAL_OK;
USB_OTG_EPTypeDef *ep;
-
+
if ((ep_addr & 0x80) == 0x80)
{
ep = &hpcd->IN_ep[ep_addr & 0x7F];
@@ -953,7 +973,7 @@
ep = &hpcd->OUT_ep[ep_addr & 0x7F];
}
ep->num = ep_addr & 0x7F;
-
+
ep->is_in = (0x80 & ep_addr) != 0;
ep->maxpacket = ep_mps;
ep->type = ep_type;
@@ -967,24 +987,24 @@
{
ep->data_pid_start = 0;
}
-
- __HAL_LOCK(hpcd);
+
+ __HAL_LOCK(hpcd);
USB_ActivateEndpoint(hpcd->Instance , ep);
- __HAL_UNLOCK(hpcd);
+ __HAL_UNLOCK(hpcd);
return ret;
}
/**
* @brief Deactivate an endpoint.
- * @param hpcd: PCD handle
- * @param ep_addr: endpoint address
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Close(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
-{
+{
USB_OTG_EPTypeDef *ep;
-
+
if ((ep_addr & 0x80) == 0x80)
{
ep = &hpcd->IN_ep[ep_addr & 0x7F];
@@ -994,22 +1014,22 @@
ep = &hpcd->OUT_ep[ep_addr & 0x7F];
}
ep->num = ep_addr & 0x7F;
-
+
ep->is_in = (0x80 & ep_addr) != 0;
-
- __HAL_LOCK(hpcd);
+
+ __HAL_LOCK(hpcd);
USB_DeactivateEndpoint(hpcd->Instance , ep);
- __HAL_UNLOCK(hpcd);
+ __HAL_UNLOCK(hpcd);
return HAL_OK;
}
/**
- * @brief Receive an amount of data.
- * @param hpcd: PCD handle
- * @param ep_addr: endpoint address
- * @param pBuf: pointer to the reception buffer
- * @param len: amount of data to be received
+ * @brief Receive an amount of data.
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
+ * @param pBuf pointer to the reception buffer
+ * @param len amount of data to be received
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Receive(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
@@ -1019,7 +1039,7 @@
ep = &hpcd->OUT_ep[ep_addr & 0x7F];
/*setup and start the Xfer */
- ep->xfer_buff = pBuf;
+ ep->xfer_buff = pBuf;
ep->xfer_len = len;
ep->xfer_count = 0;
ep->is_in = 0;
@@ -1027,28 +1047,29 @@
if (hpcd->Init.dma_enable == 1)
{
- ep->dma_addr = (uint32_t)pBuf;
+ ep->dma_addr = (uint32_t)pBuf;
}
-
- __HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]);
-
- if ((ep_addr & 0x7F) == 0 )
+
+ __HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]); // MBED:added
+
+ if ((ep_addr & 0x7F) == 0)
{
- USB_EP0StartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
+ USB_EP0StartXfer(hpcd->Instance, ep, hpcd->Init.dma_enable);
}
else
{
- USB_EPStartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
+ USB_EPStartXfer(hpcd->Instance, ep, hpcd->Init.dma_enable);
}
- __HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7F]);
-
+
+ __HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7F]); // MBED: added
+
return HAL_OK;
}
/**
* @brief Get Received Data Size.
- * @param hpcd: PCD handle
- * @param ep_addr: endpoint address
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
* @retval Data Size
*/
uint16_t HAL_PCD_EP_GetRxCount(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
@@ -1056,57 +1077,62 @@
return hpcd->OUT_ep[ep_addr & 0xF].xfer_count;
}
/**
- * @brief Send an amount of data.
- * @param hpcd: PCD handle
- * @param ep_addr: endpoint address
- * @param pBuf: pointer to the transmission buffer
- * @param len: amount of data to be sent
+ * @brief Send an amount of data.
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
+ * @param pBuf pointer to the transmission buffer
+ * @param len amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Transmit(PCD_HandleTypeDef *hpcd, uint8_t ep_addr, uint8_t *pBuf, uint32_t len)
{
USB_OTG_EPTypeDef *ep;
-
+
ep = &hpcd->IN_ep[ep_addr & 0x7F];
-
+
/*setup and start the Xfer */
- ep->xfer_buff = pBuf;
+ ep->xfer_buff = pBuf;
ep->xfer_len = len;
ep->xfer_count = 0;
ep->is_in = 1;
ep->num = ep_addr & 0x7F;
-
+
if (hpcd->Init.dma_enable == 1)
{
- ep->dma_addr = (uint32_t)pBuf;
+ ep->dma_addr = (uint32_t)pBuf;
}
-
- __HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]);
-
- if ((ep_addr & 0x7F) == 0 )
+
+ __HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]); // MBED: added
+
+ if ((ep_addr & 0x7F) == 0)
{
- USB_EP0StartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
+ USB_EP0StartXfer(hpcd->Instance, ep, hpcd->Init.dma_enable);
}
else
{
- USB_EPStartXfer(hpcd->Instance , ep, hpcd->Init.dma_enable);
+ USB_EPStartXfer(hpcd->Instance, ep, hpcd->Init.dma_enable);
}
-
- __HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7F]);
+
+ __HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7F]); // MBED: added
return HAL_OK;
}
/**
* @brief Set a STALL condition over an endpoint.
- * @param hpcd: PCD handle
- * @param ep_addr: endpoint address
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_SetStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
USB_OTG_EPTypeDef *ep;
-
+
+ if ((ep_addr & 0x0F) > hpcd->Init.dev_endpoints)
+ {
+ return HAL_ERROR;
+ }
+
if ((0x80 & ep_addr) == 0x80)
{
ep = &hpcd->IN_ep[ep_addr & 0x7F];
@@ -1115,33 +1141,40 @@
{
ep = &hpcd->OUT_ep[ep_addr];
}
-
+
ep->is_stall = 1;
ep->num = ep_addr & 0x7F;
ep->is_in = ((ep_addr & 0x80) == 0x80);
-
-
- __HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]);
+
+
+ __HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]); // MBED: changed
+
USB_EPSetStall(hpcd->Instance , ep);
if((ep_addr & 0x7F) == 0)
{
USB_EP0_OutStart(hpcd->Instance, hpcd->Init.dma_enable, (uint8_t *)hpcd->Setup);
}
- __HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7F]);
-
+
+ __HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7F]); // MBED: changed
+
return HAL_OK;
}
/**
* @brief Clear a STALL condition over in an endpoint.
- * @param hpcd: PCD handle
- * @param ep_addr: endpoint address
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_ClrStall(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
USB_OTG_EPTypeDef *ep;
-
+
+ if ((ep_addr & 0x0F) > hpcd->Init.dev_endpoints)
+ {
+ return HAL_ERROR;
+ }
+
if ((0x80 & ep_addr) == 0x80)
{
ep = &hpcd->IN_ep[ep_addr & 0x7F];
@@ -1150,28 +1183,28 @@
{
ep = &hpcd->OUT_ep[ep_addr];
}
-
+
ep->is_stall = 0;
ep->num = ep_addr & 0x7F;
ep->is_in = ((ep_addr & 0x80) == 0x80);
-
- __HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]);
+
+ __HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]); // MBED: changed
USB_EPClearStall(hpcd->Instance , ep);
- __HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7F]);
-
+ __HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7F]); // MBED: changed
+
return HAL_OK;
}
/**
* @brief Flush an endpoint.
- * @param hpcd: PCD handle
- * @param ep_addr: endpoint address
+ * @param hpcd PCD handle
+ * @param ep_addr endpoint address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_EP_Flush(PCD_HandleTypeDef *hpcd, uint8_t ep_addr)
{
- __HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]);
-
+ __HAL_LOCK(&hpcd->EPLock[ep_addr & 0x7F]); // MBED: changed
+
if ((ep_addr & 0x80) == 0x80)
{
USB_FlushTxFifo(hpcd->Instance, ep_addr & 0x7F);
@@ -1180,55 +1213,55 @@
{
USB_FlushRxFifo(hpcd->Instance);
}
-
- __HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7F]);
-
+
+ __HAL_UNLOCK(&hpcd->EPLock[ep_addr & 0x7F]); // MBED: change
+
return HAL_OK;
}
/**
* @brief Activate remote wakeup signalling.
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_ActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
{
- USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
-
+ USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+
if((USBx_DEVICE->DSTS & USB_OTG_DSTS_SUSPSTS) == USB_OTG_DSTS_SUSPSTS)
{
/* Activate Remote wakeup signaling */
USBx_DEVICE->DCTL |= USB_OTG_DCTL_RWUSIG;
}
- return HAL_OK;
+ return HAL_OK;
}
/**
* @brief De-activate remote wakeup signalling.
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_PCD_DeActivateRemoteWakeup(PCD_HandleTypeDef *hpcd)
{
- USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
-
+ USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+
/* De-activate Remote wakeup signaling */
USBx_DEVICE->DCTL &= ~(USB_OTG_DCTL_RWUSIG);
- return HAL_OK;
+ return HAL_OK;
}
/**
* @}
*/
-
-/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions
- * @brief Peripheral State functions
+
+/** @defgroup PCD_Exported_Functions_Group4 Peripheral State functions
+ * @brief Peripheral State functions
*
-@verbatim
+@verbatim
===============================================================================
##### Peripheral State functions #####
- ===============================================================================
+ ===============================================================================
[..]
- This subsection permits to get in run-time the status of the peripheral
+ This subsection permits to get in run-time the status of the peripheral
and the data flow.
@endverbatim
@@ -1237,7 +1270,7 @@
/**
* @brief Return the PCD handle state.
- * @param hpcd: PCD handle
+ * @param hpcd PCD handle
* @retval HAL state
*/
PCD_StateTypeDef HAL_PCD_GetState(PCD_HandleTypeDef *hpcd)
@@ -1259,13 +1292,13 @@
/**
* @brief Check FIFO for the next packet to be loaded.
- * @param hpcd: PCD handle
- * @param epnum : endpoint number
+ * @param hpcd PCD handle
+ * @param epnum endpoint number
* @retval HAL status
*/
static HAL_StatusTypeDef PCD_WriteEmptyTxFifo(PCD_HandleTypeDef *hpcd, uint32_t epnum)
{
- USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
+ USB_OTG_GlobalTypeDef *USBx = hpcd->Instance;
USB_OTG_EPTypeDef *ep;
int32_t len = 0;
uint32_t len32b;
@@ -1273,42 +1306,42 @@
ep = &hpcd->IN_ep[epnum];
len = ep->xfer_len - ep->xfer_count;
-
+
if (len > ep->maxpacket)
{
len = ep->maxpacket;
}
-
-
+
+
len32b = (len + 3) / 4;
-
+
while ( (USBx_INEP(epnum)->DTXFSTS & USB_OTG_DTXFSTS_INEPTFSAV) > len32b &&
ep->xfer_count < ep->xfer_len &&
ep->xfer_len != 0)
{
/* Write the FIFO */
len = ep->xfer_len - ep->xfer_count;
-
+
if (len > ep->maxpacket)
{
len = ep->maxpacket;
}
len32b = (len + 3) / 4;
-
- USB_WritePacket(USBx, ep->xfer_buff, epnum, len, hpcd->Init.dma_enable);
-
+
+ USB_WritePacket(USBx, ep->xfer_buff, epnum, len, hpcd->Init.dma_enable);
+
ep->xfer_buff += len;
ep->xfer_count += len;
}
-
+
if(len <= 0)
{
fifoemptymsk = 0x1 << epnum;
- atomic_clr_u32(&USBx_DEVICE->DIEPEMPMSK, fifoemptymsk);
-
+ atomic_clr_u32(&USBx_DEVICE->DIEPEMPMSK, fifoemptymsk); // MBED: changed
+
}
-
- return HAL_OK;
+
+ return HAL_OK;
}
/**
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pcd.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pcd.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_pcd.h
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief Header file of PCD HAL module.
******************************************************************************
* @attention
@@ -196,16 +194,18 @@
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_HS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (USB_OTG_HS_WAKEUP_EXTI_LINE)
-#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
- EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE
+#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_EDGE() do{EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
+ EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE;\
+ }while(0)
-#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (USB_OTG_HS_WAKEUP_EXTI_LINE);\
- EXTI->RTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE)
-
-#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() EXTI->RTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
- EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE;)\
- EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE;\
- EXTI->FTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE
+#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() do{EXTI->FTSR |= (USB_OTG_HS_WAKEUP_EXTI_LINE);\
+ EXTI->RTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
+ }while(0)
+#define __HAL_USB_OTG_HS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() do{EXTI->RTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
+ EXTI->FTSR &= ~(USB_OTG_HS_WAKEUP_EXTI_LINE);\
+ EXTI->RTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE;\
+ EXTI->FTSR |= USB_OTG_HS_WAKEUP_EXTI_LINE;\
+ }while(0)
#define __HAL_USB_OTG_HS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE)
@@ -214,18 +214,21 @@
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (USB_OTG_FS_WAKEUP_EXTI_LINE)
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = USB_OTG_FS_WAKEUP_EXTI_LINE
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
- EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE
-
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_EDGE() do{EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
+ EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
+ }while(0)
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() EXTI->FTSR |= (USB_OTG_FS_WAKEUP_EXTI_LINE);\
- EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE)
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_FALLING_EDGE() do{EXTI->FTSR |= (USB_OTG_FS_WAKEUP_EXTI_LINE);\
+ EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
+ }while(0)
-#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
- EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
- EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
- EXTI->FTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE
-
+#define __HAL_USB_OTG_FS_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE() do{EXTI->RTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
+ EXTI->FTSR &= ~(USB_OTG_FS_WAKEUP_EXTI_LINE);\
+ EXTI->RTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
+ EXTI->FTSR |= USB_OTG_FS_WAKEUP_EXTI_LINE;\
+ }while(0)
+
+
#define __HAL_USB_OTG_FS_WAKEUP_EXTI_GENERATE_SWIT() (EXTI->SWIER |= USB_OTG_FS_WAKEUP_EXTI_LINE)
/**
* @}
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pcd_ex.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pcd_ex.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_pcd_ex.c * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief PCD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the USB Peripheral Controller: @@ -79,9 +77,9 @@ /** * @brief Set Tx FIFO - * @param hpcd: PCD handle - * @param fifo: The number of Tx fifo - * @param size: Fifo size + * @param hpcd PCD handle + * @param fifo The number of Tx fifo + * @param size Fifo size * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_SetTxFiFo(PCD_HandleTypeDef *hpcd, uint8_t fifo, uint16_t size) @@ -122,8 +120,8 @@ /** * @brief Set Rx FIFO - * @param hpcd: PCD handle - * @param size: Size of Rx fifo + * @param hpcd PCD handle + * @param size Size of Rx fifo * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_SetRxFiFo(PCD_HandleTypeDef *hpcd, uint16_t size) @@ -135,7 +133,7 @@ /** * @brief Activate LPM Feature - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_ActivateLPM(PCD_HandleTypeDef *hpcd) @@ -152,7 +150,7 @@ /** * @brief DeActivate LPM feature. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_DeActivateLPM(PCD_HandleTypeDef *hpcd) @@ -169,7 +167,7 @@ #if defined (USB_OTG_GCCFG_BCDEN) /** * @brief Handle BatteryCharging Process. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ void HAL_PCDEx_BCD_VBUSDetect(PCD_HandleTypeDef *hpcd) @@ -240,7 +238,7 @@ /** * @brief Activate BatteryCharging feature. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_ActivateBCD(PCD_HandleTypeDef *hpcd) @@ -255,7 +253,7 @@ /** * @brief Deactivate BatteryCharging feature. - * @param hpcd: PCD handle + * @param hpcd PCD handle * @retval HAL status */ HAL_StatusTypeDef HAL_PCDEx_DeActivateBCD(PCD_HandleTypeDef *hpcd) @@ -269,8 +267,8 @@ /** * @brief Send BatteryCharging message to user layer callback. - * @param hpcd: PCD handle - * @param msg: LPM message + * @param hpcd PCD handle + * @param msg LPM message * @retval HAL status */ __weak void HAL_PCDEx_BCD_Callback(PCD_HandleTypeDef *hpcd, PCD_BCD_MsgTypeDef msg) @@ -287,8 +285,8 @@ #endif /* USB_OTG_GCCFG_BCDEN */ /** * @brief Send LPM message to user layer callback. - * @param hpcd: PCD handle - * @param msg: LPM message + * @param hpcd PCD handle + * @param msg LPM message * @retval HAL status */ __weak void HAL_PCDEx_LPM_Callback(PCD_HandleTypeDef *hpcd, PCD_LPM_MsgTypeDef msg)
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pcd_ex.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pcd_ex.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_pcd_ex.h * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief Header file of PCD HAL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pwr.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pwr.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_pwr.c
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief PWR HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Power Controller (PWR) peripheral:
@@ -268,7 +266,7 @@
/**
* @brief Configures the voltage threshold detected by the Power Voltage Detector(PVD).
- * @param sConfigPVD: pointer to an PWR_PVDTypeDef structure that contains the configuration
+ * @param sConfigPVD pointer to an PWR_PVDTypeDef structure that contains the configuration
* information for the PVD.
* @note Refer to the electrical characteristics of your device datasheet for
* more details about the voltage threshold corresponding to each
@@ -336,7 +334,7 @@
/**
* @brief Enable the WakeUp PINx functionality.
- * @param WakeUpPinPolarity: Specifies which Wake-Up pin to enable.
+ * @param WakeUpPinPolarity Specifies which Wake-Up pin to enable.
* This parameter can be one of the following legacy values, which sets the default polarity:
* detection on high level (rising edge):
* @arg PWR_WAKEUP_PIN1, PWR_WAKEUP_PIN2, PWR_WAKEUP_PIN3, PWR_WAKEUP_PIN4, PWR_WAKEUP_PIN5, PWR_WAKEUP_PIN6
@@ -365,7 +363,7 @@
/**
* @brief Disables the WakeUp PINx functionality.
- * @param WakeUpPinx: Specifies the Power Wake-Up pin to disable.
+ * @param WakeUpPinx Specifies the Power Wake-Up pin to disable.
* This parameter can be one of the following values:
* @arg PWR_WAKEUP_PIN1
* @arg PWR_WAKEUP_PIN2
@@ -390,13 +388,13 @@
* @note In Sleep mode, the systick is stopped to avoid exit from this mode with
* systick interrupt when used as time base for Timeout
*
- * @param Regulator: Specifies the regulator state in SLEEP mode.
+ * @param Regulator Specifies the regulator state in SLEEP mode.
* This parameter can be one of the following values:
* @arg PWR_MAINREGULATOR_ON: SLEEP mode with regulator ON
* @arg PWR_LOWPOWERREGULATOR_ON: SLEEP mode with low power regulator ON
* @note This parameter is not used for the STM32F7 family and is kept as parameter
* just to maintain compatibility with the lower power families.
- * @param SLEEPEntry: Specifies if SLEEP mode in entered with WFI or WFE instruction.
+ * @param SLEEPEntry Specifies if SLEEP mode in entered with WFI or WFE instruction.
* This parameter can be one of the following values:
* @arg PWR_SLEEPENTRY_WFI: enter SLEEP mode with WFI instruction
* @arg PWR_SLEEPENTRY_WFE: enter SLEEP mode with WFE instruction
@@ -411,6 +409,10 @@
/* Clear SLEEPDEEP bit of Cortex System Control Register */
CLEAR_BIT(SCB->SCR, ((uint32_t)SCB_SCR_SLEEPDEEP_Msk));
+ /* Ensure that all instructions done before entering SLEEP mode */
+ __DSB();
+ __ISB();
+
/* Select SLEEP mode entry -------------------------------------------------*/
if(SLEEPEntry == PWR_SLEEPENTRY_WFI)
{
@@ -435,11 +437,11 @@
* startup delay is incurred when waking up from Stop mode.
* By keeping the internal regulator ON during Stop mode, the consumption
* is higher although the startup time is reduced.
- * @param Regulator: Specifies the regulator state in Stop mode.
+ * @param Regulator Specifies the regulator state in Stop mode.
* This parameter can be one of the following values:
* @arg PWR_MAINREGULATOR_ON: Stop mode with regulator ON
* @arg PWR_LOWPOWERREGULATOR_ON: Stop mode with low power regulator ON
- * @param STOPEntry: Specifies if Stop mode in entered with WFI or WFE instruction.
+ * @param STOPEntry Specifies if Stop mode in entered with WFI or WFE instruction.
* This parameter can be one of the following values:
* @arg PWR_STOPENTRY_WFI: Enter Stop mode with WFI instruction
* @arg PWR_STOPENTRY_WFE: Enter Stop mode with WFE instruction
@@ -448,25 +450,29 @@
void HAL_PWR_EnterSTOPMode(uint32_t Regulator, uint8_t STOPEntry)
{
uint32_t tmpreg = 0;
-
+
/* Check the parameters */
assert_param(IS_PWR_REGULATOR(Regulator));
assert_param(IS_PWR_STOP_ENTRY(STOPEntry));
-
+
/* Select the regulator state in Stop mode ---------------------------------*/
tmpreg = PWR->CR1;
/* Clear PDDS and LPDS bits */
tmpreg &= (uint32_t)~(PWR_CR1_PDDS | PWR_CR1_LPDS);
-
+
/* Set LPDS, MRLVDS and LPLVDS bits according to Regulator value */
tmpreg |= Regulator;
-
+
/* Store the new value */
PWR->CR1 = tmpreg;
-
+
/* Set SLEEPDEEP bit of Cortex System Control Register */
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
-
+
+ /* Ensure that all instructions done before entering STOP mode */
+ __DSB();
+ __ISB();
+
/* Select Stop mode entry --------------------------------------------------*/
if(STOPEntry == PWR_STOPENTRY_WFI)
{
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pwr.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pwr.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_pwr.h * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief Header file of PWR HAL module. ****************************************************************************** * @attention @@ -171,7 +169,7 @@ */ /** @brief macros configure the main internal regulator output voltage. - * @param __REGULATOR__: specifies the regulator output voltage to achieve + * @param __REGULATOR__ specifies the regulator output voltage to achieve * a tradeoff between performance and power consumption when the device does * not operate at the maximum frequency (refer to the datasheets for more details). * This parameter can be one of the following values: @@ -189,7 +187,7 @@ } while(0) /** @brief Check PWR flag is set or not. - * @param __FLAG__: specifies the flag to check. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event * was received on the internal wakeup line in standby mode (RTC alarm (Alarm A or Alarm B), @@ -210,7 +208,7 @@ #define __HAL_PWR_GET_FLAG(__FLAG__) ((PWR->CSR1 & (__FLAG__)) == (__FLAG__)) /** @brief Clear the PWR's pending flags. - * @param __FLAG__: specifies the flag to clear. + * @param __FLAG__ specifies the flag to clear. * This parameter can be one of the following values: * @arg PWR_FLAG_SB: StandBy flag */
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pwr_ex.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pwr_ex.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_pwr_ex.c * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief Extended PWR HAL module driver. * This file provides firmware functions to manage the following * functionalities of PWR extension peripheral: @@ -382,13 +380,13 @@ * By keeping the internal regulator ON during Stop mode, the consumption * is higher although the startup time is reduced. * - * @param Regulator: specifies the regulator state in STOP mode. + * @param Regulator specifies the regulator state in STOP mode. * This parameter can be one of the following values: * @arg PWR_MAINREGULATOR_UNDERDRIVE_ON: Main Regulator in under-drive mode * and Flash memory in power-down when the device is in Stop under-drive mode * @arg PWR_LOWPOWERREGULATOR_UNDERDRIVE_ON: Low Power Regulator in under-drive mode * and Flash memory in power-down when the device is in Stop under-drive mode - * @param STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction. + * @param STOPEntry specifies if STOP mode in entered with WFI or WFE instruction. * This parameter can be one of the following values: * @arg PWR_SLEEPENTRY_WFI: enter STOP mode with WFI instruction * @arg PWR_SLEEPENTRY_WFE: enter STOP mode with WFE instruction @@ -467,7 +465,7 @@ /** * @brief Configures the main internal regulator output voltage. - * @param VoltageScaling: specifies the regulator output voltage to achieve + * @param VoltageScaling specifies the regulator output voltage to achieve * a tradeoff between performance and power consumption. * This parameter can be one of the following values: * @arg PWR_REGULATOR_VOLTAGE_SCALE1: Regulator voltage output range 1 mode,
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pwr_ex.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_pwr_ex.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_pwr_ex.h * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief Header file of PWR HAL Extension module. ****************************************************************************** * @attention @@ -149,7 +147,7 @@ #define __HAL_PWR_UNDERDRIVE_DISABLE() (PWR->CR1 &= (uint32_t)(~PWR_CR1_UDEN)) /** @brief Check PWR flag is set or not. - * @param __FLAG__: specifies the flag to check. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg PWR_FLAG_ODRDY: This flag indicates that the Over-drive mode * is ready @@ -166,7 +164,7 @@ #define __HAL_PWR_CLEAR_ODRUDR_FLAG() (PWR->CSR1 |= PWR_FLAG_UDRDY) /** @brief Check Wake Up flag is set or not. - * @param __WUFLAG__: specifies the Wake Up flag to check. + * @param __WUFLAG__ specifies the Wake Up flag to check. * This parameter can be one of the following values: * @arg PWR_WAKEUP_PIN_FLAG1: Wakeup Pin Flag for PA0 * @arg PWR_WAKEUP_PIN_FLAG2: Wakeup Pin Flag for PA2 @@ -178,7 +176,7 @@ #define __HAL_PWR_GET_WAKEUP_FLAG(__WUFLAG__) (PWR->CSR2 & (__WUFLAG__)) /** @brief Clear the WakeUp pins flags. - * @param __WUFLAG__: specifies the Wake Up pin flag to clear. + * @param __WUFLAG__ specifies the Wake Up pin flag to clear. * This parameter can be one of the following values: * @arg PWR_WAKEUP_PIN_FLAG1: Wakeup Pin Flag for PA0 * @arg PWR_WAKEUP_PIN_FLAG2: Wakeup Pin Flag for PA2
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_qspi.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_qspi.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_qspi.c
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief QSPI HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the QuadSPI interface (QSPI).
@@ -245,7 +243,7 @@
/**
* @brief Initializes the QSPI mode according to the specified parameters
* in the QSPI_InitTypeDef and creates the associated handle.
- * @param hqspi: qspi handle
+ * @param hqspi qspi handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
@@ -324,7 +322,7 @@
/**
* @brief DeInitializes the QSPI peripheral
- * @param hqspi: qspi handle
+ * @param hqspi qspi handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
@@ -358,7 +356,7 @@
/**
* @brief QSPI MSP Init
- * @param hqspi: QSPI handle
+ * @param hqspi QSPI handle
* @retval None
*/
__weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
@@ -373,7 +371,7 @@
/**
* @brief QSPI MSP DeInit
- * @param hqspi: QSPI handle
+ * @param hqspi QSPI handle
* @retval None
*/
__weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
@@ -412,7 +410,7 @@
/**
* @brief This function handles QSPI interrupt request.
- * @param hqspi: QSPI handle
+ * @param hqspi QSPI handle
* @retval None.
*/
void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
@@ -636,9 +634,9 @@
/**
* @brief Sets the command configuration.
- * @param hqspi: QSPI handle
- * @param cmd : structure that contains the command configuration information
- * @param Timeout : Time out duration
+ * @param hqspi QSPI handle
+ * @param cmd structure that contains the command configuration information
+ * @param Timeout Time out duration
* @note This function is used only in Indirect Read or Write Modes
* @retval HAL status
*/
@@ -727,8 +725,8 @@
/**
* @brief Sets the command configuration in interrupt mode.
- * @param hqspi: QSPI handle
- * @param cmd : structure that contains the command configuration information
+ * @param hqspi QSPI handle
+ * @param cmd structure that contains the command configuration information
* @note This function is used only in Indirect Read or Write Modes
* @retval HAL status
*/
@@ -826,9 +824,9 @@
/**
* @brief Transmit an amount of data in blocking mode.
- * @param hqspi: QSPI handle
- * @param pData: pointer to data buffer
- * @param Timeout : Time out duration
+ * @param hqspi QSPI handle
+ * @param pData pointer to data buffer
+ * @param Timeout Time out duration
* @note This function is used only in Indirect Write Mode
* @retval HAL status
*/
@@ -912,9 +910,9 @@
/**
* @brief Receive an amount of data in blocking mode
- * @param hqspi: QSPI handle
- * @param pData: pointer to data buffer
- * @param Timeout : Time out duration
+ * @param hqspi QSPI handle
+ * @param pData pointer to data buffer
+ * @param Timeout Time out duration
* @note This function is used only in Indirect Read Mode
* @retval HAL status
*/
@@ -1000,8 +998,8 @@
/**
* @brief Send an amount of data in interrupt mode
- * @param hqspi: QSPI handle
- * @param pData: pointer to data buffer
+ * @param hqspi QSPI handle
+ * @param pData pointer to data buffer
* @note This function is used only in Indirect Write Mode
* @retval HAL status
*/
@@ -1060,8 +1058,8 @@
/**
* @brief Receive an amount of data in no-blocking mode with Interrupt
- * @param hqspi: QSPI handle
- * @param pData: pointer to data buffer
+ * @param hqspi QSPI handle
+ * @param pData pointer to data buffer
* @note This function is used only in Indirect Read Mode
* @retval HAL status
*/
@@ -1124,8 +1122,8 @@
/**
* @brief Sends an amount of data in non blocking mode with DMA.
- * @param hqspi: QSPI handle
- * @param pData: pointer to data buffer
+ * @param hqspi QSPI handle
+ * @param pData pointer to data buffer
* @note This function is used only in Indirect Write Mode
* @note If DMA peripheral access is configured as halfword, the number
* of data and the fifo threshold should be aligned on halfword
@@ -1258,8 +1256,8 @@
/**
* @brief Receives an amount of data in non blocking mode with DMA.
- * @param hqspi: QSPI handle
- * @param pData: pointer to data buffer.
+ * @param hqspi QSPI handle
+ * @param pData pointer to data buffer.
* @note This function is used only in Indirect Read Mode
* @note If DMA peripheral access is configured as halfword, the number
* of data and the fifo threshold should be aligned on halfword
@@ -1394,10 +1392,10 @@
/**
* @brief Configure the QSPI Automatic Polling Mode in blocking mode.
- * @param hqspi: QSPI handle
- * @param cmd: structure that contains the command configuration information.
- * @param cfg: structure that contains the polling configuration information.
- * @param Timeout : Time out duration
+ * @param hqspi QSPI handle
+ * @param cmd structure that contains the command configuration information.
+ * @param cfg structure that contains the polling configuration information.
+ * @param Timeout Time out duration
* @note This function is used only in Automatic Polling Mode
* @retval HAL status
*/
@@ -1495,9 +1493,9 @@
/**
* @brief Configure the QSPI Automatic Polling Mode in non-blocking mode.
- * @param hqspi: QSPI handle
- * @param cmd: structure that contains the command configuration information.
- * @param cfg: structure that contains the polling configuration information.
+ * @param hqspi QSPI handle
+ * @param cmd structure that contains the command configuration information.
+ * @param cfg structure that contains the polling configuration information.
* @note This function is used only in Automatic Polling Mode
* @retval HAL status
*/
@@ -1599,9 +1597,9 @@
/**
* @brief Configure the Memory Mapped mode.
- * @param hqspi: QSPI handle
- * @param cmd: structure that contains the command configuration information.
- * @param cfg: structure that contains the memory mapped configuration information.
+ * @param hqspi QSPI handle
+ * @param cmd structure that contains the command configuration information.
+ * @param cfg structure that contains the memory mapped configuration information.
* @note This function is used only in Memory mapped Mode
* @retval HAL status
*/
@@ -1688,7 +1686,7 @@
/**
* @brief Transfer Error callbacks
- * @param hqspi: QSPI handle
+ * @param hqspi QSPI handle
* @retval None
*/
__weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
@@ -1703,7 +1701,7 @@
/**
* @brief Abort completed callback.
- * @param hqspi: QSPI handle
+ * @param hqspi QSPI handle
* @retval None
*/
__weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi)
@@ -1718,7 +1716,7 @@
/**
* @brief Command completed callback.
- * @param hqspi: QSPI handle
+ * @param hqspi QSPI handle
* @retval None
*/
__weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
@@ -1733,7 +1731,7 @@
/**
* @brief Rx Transfer completed callbacks.
- * @param hqspi: QSPI handle
+ * @param hqspi QSPI handle
* @retval None
*/
__weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
@@ -1748,7 +1746,7 @@
/**
* @brief Tx Transfer completed callbacks.
- * @param hqspi: QSPI handle
+ * @param hqspi QSPI handle
* @retval None
*/
__weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
@@ -1763,7 +1761,7 @@
/**
* @brief Rx Half Transfer completed callbacks.
- * @param hqspi: QSPI handle
+ * @param hqspi QSPI handle
* @retval None
*/
__weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
@@ -1778,7 +1776,7 @@
/**
* @brief Tx Half Transfer completed callbacks.
- * @param hqspi: QSPI handle
+ * @param hqspi QSPI handle
* @retval None
*/
__weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
@@ -1793,7 +1791,7 @@
/**
* @brief FIFO Threshold callbacks
- * @param hqspi: QSPI handle
+ * @param hqspi QSPI handle
* @retval None
*/
__weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
@@ -1808,7 +1806,7 @@
/**
* @brief Status Match callbacks
- * @param hqspi: QSPI handle
+ * @param hqspi QSPI handle
* @retval None
*/
__weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
@@ -1823,7 +1821,7 @@
/**
* @brief Timeout callbacks
- * @param hqspi: QSPI handle
+ * @param hqspi QSPI handle
* @retval None
*/
__weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
@@ -1859,7 +1857,7 @@
/**
* @brief Return the QSPI handle state.
- * @param hqspi: QSPI handle
+ * @param hqspi QSPI handle
* @retval HAL state
*/
HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
@@ -1870,7 +1868,7 @@
/**
* @brief Return the QSPI error code
-* @param hqspi: QSPI handle
+* @param hqspi QSPI handle
* @retval QSPI Error Code
*/
uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
@@ -1880,7 +1878,7 @@
/**
* @brief Abort the current transmission
-* @param hqspi: QSPI handle
+* @param hqspi QSPI handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
@@ -1933,7 +1931,7 @@
/**
* @brief Abort the current transmission (non-blocking function)
-* @param hqspi: QSPI handle
+* @param hqspi QSPI handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)
@@ -1978,8 +1976,8 @@
}
/** @brief Set QSPI timeout
- * @param hqspi: QSPI handle.
- * @param Timeout: Timeout for the QSPI memory access.
+ * @param hqspi QSPI handle.
+ * @param Timeout Timeout for the QSPI memory access.
* @retval None
*/
void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
@@ -1988,8 +1986,8 @@
}
/** @brief Set QSPI Fifo threshold.
- * @param hqspi: QSPI handle.
- * @param Threshold: Threshold of the Fifo (value between 1 and 16).
+ * @param hqspi QSPI handle.
+ * @param Threshold Threshold of the Fifo (value between 1 and 16).
* @retval HAL status
*/
HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold)
@@ -2006,7 +2004,7 @@
/* Configure QSPI FIFO Threshold */
MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
- ((hqspi->Init.FifoThreshold - 1) << POSITION_VAL(QUADSPI_CR_FTHRES)));
+ ((hqspi->Init.FifoThreshold - 1) << QUADSPI_CR_FTHRES_Pos));
}
else
{
@@ -2021,12 +2019,12 @@
}
/** @brief Get QSPI Fifo threshold.
- * @param hqspi: QSPI handle.
+ * @param hqspi QSPI handle.
* @retval Fifo threshold (value between 1 and 16)
*/
uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi)
{
- return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> POSITION_VAL(QUADSPI_CR_FTHRES)) + 1);
+ return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> QUADSPI_CR_FTHRES_Pos) + 1);
}
/**
@@ -2037,7 +2035,7 @@
/**
* @brief DMA QSPI receive process complete callback.
- * @param hdma: DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma)
@@ -2051,7 +2049,7 @@
/**
* @brief DMA QSPI transmit process complete callback.
- * @param hdma: DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma)
@@ -2065,7 +2063,7 @@
/**
* @brief DMA QSPI receive process half complete callback
- * @param hdma : DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
@@ -2077,7 +2075,7 @@
/**
* @brief DMA QSPI transmit process half complete callback
- * @param hdma : DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
@@ -2089,7 +2087,7 @@
/**
* @brief DMA QSPI communication error callback.
- * @param hdma: DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void QSPI_DMAError(DMA_HandleTypeDef *hdma)
@@ -2113,7 +2111,7 @@
/**
* @brief DMA QSPI abort complete callback.
- * @param hdma: DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma)
@@ -2148,11 +2146,11 @@
/**
* @brief Wait for a flag state until timeout.
- * @param hqspi: QSPI handle
- * @param Flag: Flag checked
- * @param State: Value of the flag expected
- * @param tickstart: Start tick value
- * @param Timeout: Duration of the time out
+ * @param hqspi QSPI handle
+ * @param Flag Flag checked
+ * @param State Value of the flag expected
+ * @param tickstart Start tick value
+ * @param Timeout Duration of the time out
* @retval HAL status
*/
static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
@@ -2178,9 +2176,9 @@
/**
* @brief Configure the communication registers.
- * @param hqspi: QSPI handle
- * @param cmd: structure that contains the command configuration information
- * @param FunctionalMode: functional mode to configured
+ * @param hqspi QSPI handle
+ * @param cmd structure that contains the command configuration information
+ * @param FunctionalMode functional mode to configured
* This parameter can be one of the following values:
* @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode
* @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_qspi.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_qspi.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_qspi.h * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief Header file of QSPI HAL module. ****************************************************************************** * @attention @@ -431,26 +429,26 @@ */ /** @brief Reset QSPI handle state - * @param __HANDLE__: QSPI handle. + * @param __HANDLE__ QSPI handle. * @retval None */ #define __HAL_QSPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_QSPI_STATE_RESET) /** @brief Enable QSPI - * @param __HANDLE__: specifies the QSPI Handle. + * @param __HANDLE__ specifies the QSPI Handle. * @retval None */ #define __HAL_QSPI_ENABLE(__HANDLE__) SET_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) /** @brief Disable QSPI - * @param __HANDLE__: specifies the QSPI Handle. + * @param __HANDLE__ specifies the QSPI Handle. * @retval None */ #define __HAL_QSPI_DISABLE(__HANDLE__) CLEAR_BIT((__HANDLE__)->Instance->CR, QUADSPI_CR_EN) /** @brief Enables the specified QSPI interrupt. - * @param __HANDLE__: specifies the QSPI Handle. - * @param __INTERRUPT__: specifies the QSPI interrupt source to enable. + * @param __HANDLE__ specifies the QSPI Handle. + * @param __INTERRUPT__ specifies the QSPI interrupt source to enable. * This parameter can be one of the following values: * @arg QSPI_IT_TO: QSPI Time out interrupt * @arg QSPI_IT_SM: QSPI Status match interrupt @@ -463,8 +461,8 @@ /** @brief Disables the specified QSPI interrupt. - * @param __HANDLE__: specifies the QSPI Handle. - * @param __INTERRUPT__: specifies the QSPI interrupt source to disable. + * @param __HANDLE__ specifies the QSPI Handle. + * @param __INTERRUPT__ specifies the QSPI interrupt source to disable. * This parameter can be one of the following values: * @arg QSPI_IT_TO: QSPI Timeout interrupt * @arg QSPI_IT_SM: QSPI Status match interrupt @@ -476,8 +474,8 @@ #define __HAL_QSPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) CLEAR_BIT((__HANDLE__)->Instance->CR, (__INTERRUPT__)) /** @brief Checks whether the specified QSPI interrupt source is enabled. - * @param __HANDLE__: specifies the QSPI Handle. - * @param __INTERRUPT__: specifies the QSPI interrupt source to check. + * @param __HANDLE__ specifies the QSPI Handle. + * @param __INTERRUPT__ specifies the QSPI interrupt source to check. * This parameter can be one of the following values: * @arg QSPI_IT_TO: QSPI Time out interrupt * @arg QSPI_IT_SM: QSPI Status match interrupt @@ -490,8 +488,8 @@ /** * @brief Get the selected QSPI's flag status. - * @param __HANDLE__: specifies the QSPI Handle. - * @param __FLAG__: specifies the QSPI flag to check. + * @param __HANDLE__ specifies the QSPI Handle. + * @param __FLAG__ specifies the QSPI flag to check. * This parameter can be one of the following values: * @arg QSPI_FLAG_BUSY: QSPI Busy flag * @arg QSPI_FLAG_TO: QSPI Time out flag @@ -504,8 +502,8 @@ #define __HAL_QSPI_GET_FLAG(__HANDLE__, __FLAG__) (READ_BIT((__HANDLE__)->Instance->SR, (__FLAG__)) != 0) /** @brief Clears the specified QSPI's flag status. - * @param __HANDLE__: specifies the QSPI Handle. - * @param __FLAG__: specifies the QSPI clear register flag that needs to be set + * @param __HANDLE__ specifies the QSPI Handle. + * @param __FLAG__ specifies the QSPI clear register flag that needs to be set * This parameter can be one of the following values: * @arg QSPI_FLAG_TO: QSPI Time out flag * @arg QSPI_FLAG_SM: QSPI Status match flag
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rcc.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rcc.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,21 +2,19 @@
******************************************************************************
* @file stm32f7xx_hal_rcc.c
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief RCC HAL module driver.
- * This file provides firmware functions to manage the following
+ * This file provides firmware functions to manage the following
* functionalities of the Reset and Clock Control (RCC) peripheral:
* + Initialization and de-initialization functions
* + Peripheral Control functions
- *
- @verbatim
+ *
+ @verbatim
==============================================================================
##### RCC specific features #####
==============================================================================
- [..]
- After reset the device is running from Internal High Speed oscillator
- (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
+ [..]
+ After reset the device is running from Internal High Speed oscillator
+ (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache
and I-Cache are disabled, and all peripherals are off except internal
SRAM, Flash and JTAG.
(+) There is no prescaler on High speed (AHB) and Low speed (APB) busses;
@@ -24,12 +22,12 @@
(+) The clock for all peripherals is switched off, except the SRAM and FLASH.
(+) All GPIOs are in input floating state, except the JTAG pins which
are assigned to be used for debug purpose.
-
- [..]
- Once the device started from reset, the user application has to:
+
+ [..]
+ Once the device started from reset, the user application has to:
(+) Configure the clock source to be used to drive the System clock
(if the application needs higher frequency/performance)
- (+) Configure the System clock frequency and Flash settings
+ (+) Configure the System clock frequency and Flash settings
(+) Configure the AHB and APB busses prescalers
(+) Enable the clock for the peripheral(s) to be used
(+) Configure the clock source(s) for peripherals which clocks are not
@@ -37,17 +35,17 @@
##### RCC Limitations #####
==============================================================================
- [..]
- A delay between an RCC peripheral clock enable and the effective peripheral
- enabling should be taken into account in order to manage the peripheral read/write
+ [..]
+ A delay between an RCC peripheral clock enable and the effective peripheral
+ enabling should be taken into account in order to manage the peripheral read/write
from/to registers.
(+) This delay depends on the peripheral mapping.
- (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
+ (+) If peripheral is mapped on AHB: the delay is 2 AHB clock cycle
after the clock enable bit is set on the hardware register
- (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
+ (+) If peripheral is mapped on APB: the delay is 2 APB clock cycle
after the clock enable bit is set on the hardware register
- [..]
+ [..]
Implemented Workaround:
(+) For AHB & APB peripherals, a dummy read to the peripheral register has been
inserted in each __HAL_RCC_PPP_CLK_ENABLE() macro.
@@ -81,7 +79,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
- */
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
@@ -131,16 +129,16 @@
* @{
*/
-/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
- * @brief Initialization and Configuration functions
+/** @defgroup RCC_Exported_Functions_Group1 Initialization and de-initialization functions
+ * @brief Initialization and Configuration functions
*
- @verbatim
+ @verbatim
===============================================================================
##### Initialization and de-initialization functions #####
===============================================================================
[..]
This section provides functions allowing to configure the internal/external oscillators
- (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1
+ (HSE, HSI, LSE, LSI, PLL, CSS and MCO) and the System buses clocks (SYSCLK, AHB, APB1
and APB2).
[..] Internal/external clock and PLL configuration
@@ -153,7 +151,7 @@
(#) HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
through the PLL as System clock source. Can be used also as RTC clock source.
- (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
+ (#) LSE (low-speed external), 32 KHz oscillator used as RTC clock source.
(#) PLL (clocked by HSI or HSE), featuring two different output clocks:
(++) The first output is used to generate the high speed system clock (up to 216 MHz)
@@ -161,10 +159,10 @@
the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
(#) CSS (Clock security system), once enable using the function HAL_RCC_EnableCSS()
- and if a HSE clock failure occurs(HSE used directly or through PLL as System
+ and if a HSE clock failure occurs(HSE used directly or through PLL as System
clock source), the System clock is automatically switched to HSI and an interrupt
- is generated if enabled. The interrupt is linked to the Cortex-M7 NMI
- (Non-Maskable Interrupt) exception vector.
+ is generated if enabled. The interrupt is linked to the Cortex-M7 NMI
+ (Non-Maskable Interrupt) exception vector.
(#) MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
clock (through a configurable prescaler) on PA8 pin.
@@ -172,26 +170,26 @@
(#) MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
clock (through a configurable prescaler) on PC9 pin.
- [..] System, AHB and APB busses clocks configuration
+ [..] System, AHB and APB busses clocks configuration
(#) Several clock sources can be used to drive the System clock (SYSCLK): HSI,
HSE and PLL.
- The AHB clock (HCLK) is derived from System clock through configurable
- prescaler and used to clock the CPU, memory and peripherals mapped
- on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
- from AHB clock through configurable prescalers and used to clock
- the peripherals mapped on these busses. You can use
- "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
+ The AHB clock (HCLK) is derived from System clock through configurable
+ prescaler and used to clock the CPU, memory and peripherals mapped
+ on AHB bus (DMA, GPIO...). APB1 (PCLK1) and APB2 (PCLK2) clocks are derived
+ from AHB clock through configurable prescalers and used to clock
+ the peripherals mapped on these busses. You can use
+ "HAL_RCC_GetSysClockFreq()" function to retrieve the frequencies of these clocks.
-@- All the peripheral clocks are derived from the System clock (SYSCLK) except:
(+@) I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or
- from an external clock mapped on the I2S_CKIN pin.
+ from an external clock mapped on the I2S_CKIN pin.
You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.
(+@) SAI: the SAI clock can be derived either from a specific PLL (PLLI2S) or (PLLSAI) or
- from an external clock mapped on the I2S_CKIN pin.
- You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.
+ from an external clock mapped on the I2S_CKIN pin.
+ You have to use __HAL_RCC_PLLI2S_CONFIG() macro to configure this clock.
(+@) RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
divided by 2 to 31. You have to use __HAL_RCC_RTC_CONFIG() and __HAL_RCC_RTC_ENABLE()
- macros to configure this clock.
+ macros to configure this clock.
(+@) USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz
to work correctly, while the SDIO require a frequency equal or lower than
to 48. This clock is derived of the main PLL through PLLQ divider.
@@ -204,48 +202,151 @@
* @brief Resets the RCC clock configuration to the default reset state.
* @note The default reset state of the clock configuration is given below:
* - HSI ON and used as system clock source
- * - HSE, PLL and PLLI2S OFF
+ * - HSE, PLL, PLLI2S and PLLSAI OFF
* - AHB, APB1 and APB2 prescaler set to 1.
* - CSS, MCO1 and MCO2 OFF
* - All interrupts disabled
* @note This function doesn't modify the configuration of the
- * - Peripheral clocks
- * - LSI, LSE and RTC clocks
+ * - Peripheral clocks
+ * - LSI, LSE and RTC clocks
* @retval None
*/
-void HAL_RCC_DeInit(void)
+HAL_StatusTypeDef HAL_RCC_DeInit(void)
{
- /* Set HSION bit */
- SET_BIT(RCC->CR, RCC_CR_HSION | RCC_CR_HSITRIM_4);
-
+ uint32_t tickstart;
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Set HSION bit to the reset value */
+ SET_BIT(RCC->CR, RCC_CR_HSION);
+
+ /* Wait till HSI is ready */
+ while (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > HSI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Set HSITRIM[4:0] bits to the reset value */
+ SET_BIT(RCC->CR, RCC_CR_HSITRIM_4);
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
/* Reset CFGR register */
CLEAR_REG(RCC->CFGR);
-
- /* Reset HSEON, CSSON, PLLON, PLLI2S */
- CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_CSSON | RCC_CR_PLLON| RCC_CR_PLLI2SON);
-
- /* Reset PLLCFGR register */
- CLEAR_REG(RCC->PLLCFGR);
- SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2 | ((uint32_t)0x20000000U));
-
- /* Reset PLLI2SCFGR register */
- CLEAR_REG(RCC->PLLI2SCFGR);
- SET_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SR_1);
-
- /* Reset HSEBYP bit */
- CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
-
+
+ /* Wait till clock switch is ready */
+ while (READ_BIT(RCC->CFGR, RCC_CFGR_SWS) != RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Clear HSEON, HSEBYP and CSSON bits */
+ CLEAR_BIT(RCC->CR, RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_CSSON);
+
+ /* Wait till HSE is disabled */
+ while (READ_BIT(RCC->CR, RCC_CR_HSERDY) != RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > HSE_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Clear PLLON bit */
+ CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
+
+ /* Wait till PLL is disabled */
+ while (READ_BIT(RCC->CR, RCC_CR_PLLRDY) != RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > PLL_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Reset PLLI2SON bit */
+ CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON);
+
+ /* Wait till PLLI2S is disabled */
+ while (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Get Start Tick */
+ tickstart = HAL_GetTick();
+
+ /* Reset PLLSAI bit */
+ CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION);
+
+ /* Wait till PLLSAI is disabled */
+ while (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) != RESET)
+ {
+ if ((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
+ {
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Once PLL, PLLI2S and PLLSAI are OFF, reset PLLCFGR register to default value */
+ RCC->PLLCFGR = RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLN_6 | RCC_PLLCFGR_PLLN_7 | RCC_PLLCFGR_PLLQ_2 | 0x20000000U;
+
+ /* Reset PLLI2SCFGR register to default value */
+ RCC->PLLI2SCFGR = RCC_PLLI2SCFGR_PLLI2SN_6 | RCC_PLLI2SCFGR_PLLI2SN_7 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SR_1;
+
+ /* Reset PLLSAICFGR register to default value */
+ RCC->PLLSAICFGR = RCC_PLLSAICFGR_PLLSAIN_6 | RCC_PLLSAICFGR_PLLSAIN_7 | RCC_PLLSAICFGR_PLLSAIQ_2 | 0x20000000U;
+
/* Disable all interrupts */
- CLEAR_REG(RCC->CIR);
-
+ CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE | RCC_CIR_LSERDYIE | RCC_CIR_HSIRDYIE | RCC_CIR_HSERDYIE | RCC_CIR_PLLRDYIE | RCC_CIR_PLLI2SRDYIE | RCC_CIR_PLLSAIRDYIE);
+
+ /* Clear all interrupt flags */
+ SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_PLLI2SRDYC | RCC_CIR_PLLSAIRDYC | RCC_CIR_CSSC);
+
+ /* Clear LSION bit */
+ CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
+
+ /* Reset all CSR flags */
+ SET_BIT(RCC->CSR, RCC_CSR_RMVF);
+
/* Update the SystemCoreClock global variable */
SystemCoreClock = HSI_VALUE;
+
+ /* Adapt Systick interrupt period */
+ if(HAL_InitTick(TICK_INT_PRIORITY) != HAL_OK)
+ {
+ return HAL_ERROR;
+ }
+ else
+ {
+ return HAL_OK;
+ }
}
/**
* @brief Initializes the RCC Oscillators according to the specified parameters in the
* RCC_OscInitTypeDef.
- * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
+ * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
* contains the configuration information for the RCC Oscillators.
* @note The PLL is not disabled when used as system clock.
* @note Transitions LSE Bypass to LSE On and LSE On to LSE Bypass are not
@@ -258,22 +359,28 @@
*/
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart;
FlagStatus pwrclkchanged = RESET;
-
+
+ /* Check Null pointer */
+ if(RCC_OscInitStruct == NULL)
+ {
+ return HAL_ERROR;
+ }
+
/* Check the parameters */
assert_param(IS_RCC_OSCILLATORTYPE(RCC_OscInitStruct->OscillatorType));
-
- /*------------------------------- HSE Configuration ------------------------*/
+
+ /*------------------------------- HSE Configuration ------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSE) == RCC_OSCILLATORTYPE_HSE)
{
/* Check the parameters */
assert_param(IS_RCC_HSE(RCC_OscInitStruct->HSEState));
/* When the HSE is used as system clock or clock source for PLL, It can not be disabled */
- if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
+ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSE)
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSE)))
{
- if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
+ if((__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET) && (RCC_OscInitStruct->HSEState == RCC_HSE_OFF))
{
return HAL_ERROR;
}
@@ -282,14 +389,14 @@
{
/* Set the new HSE configuration ---------------------------------------*/
__HAL_RCC_HSE_CONFIG(RCC_OscInitStruct->HSEState);
-
+
/* Check the HSE State */
if(RCC_OscInitStruct->HSEState != RCC_HSE_OFF)
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
-
- /* Wait till HSE is ready */
+
+ /* Wait till HSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > HSE_TIMEOUT_VALUE)
@@ -302,7 +409,7 @@
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
-
+
/* Wait till HSE is bypassed or disabled */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) != RESET)
{
@@ -314,15 +421,15 @@
}
}
}
- /*----------------------------- HSI Configuration --------------------------*/
+ /*----------------------------- HSI Configuration --------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_HSI) == RCC_OSCILLATORTYPE_HSI)
{
/* Check the parameters */
assert_param(IS_RCC_HSI(RCC_OscInitStruct->HSIState));
assert_param(IS_RCC_CALIBRATION_VALUE(RCC_OscInitStruct->HSICalibrationValue));
-
- /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
- if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
+
+ /* Check if HSI is used as system clock or as PLL source when PLL is selected as system clock */
+ if((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_HSI)
|| ((__HAL_RCC_GET_SYSCLK_SOURCE() == RCC_SYSCLKSOURCE_STATUS_PLLCLK) && ((RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) == RCC_PLLCFGR_PLLSRC_HSI)))
{
/* When HSI is used as system clock it will not disabled */
@@ -348,7 +455,7 @@
/* Get Start Tick*/
tickstart = HAL_GetTick();
- /* Wait till HSI is ready */
+ /* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
@@ -356,7 +463,7 @@
return HAL_TIMEOUT;
}
}
-
+
/* Adjusts the Internal High Speed oscillator (HSI) calibration value.*/
__HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(RCC_OscInitStruct->HSICalibrationValue);
}
@@ -367,15 +474,15 @@
/* Get Start Tick*/
tickstart = HAL_GetTick();
-
- /* Wait till HSI is ready */
+
+ /* Wait till HSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > HSI_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
- }
+ }
+ }
}
}
}
@@ -390,10 +497,10 @@
{
/* Enable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_ENABLE();
-
+
/* Get Start Tick*/
tickstart = HAL_GetTick();
-
+
/* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) == RESET)
{
@@ -407,11 +514,11 @@
{
/* Disable the Internal Low Speed oscillator (LSI). */
__HAL_RCC_LSI_DISABLE();
-
+
/* Get Start Tick*/
tickstart = HAL_GetTick();
-
- /* Wait till LSI is ready */
+
+ /* Wait till LSI is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSIRDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > LSI_TIMEOUT_VALUE)
@@ -421,12 +528,12 @@
}
}
}
- /*------------------------------ LSE Configuration -------------------------*/
+ /*------------------------------ LSE Configuration -------------------------*/
if(((RCC_OscInitStruct->OscillatorType) & RCC_OSCILLATORTYPE_LSE) == RCC_OSCILLATORTYPE_LSE)
{
/* Check the parameters */
assert_param(IS_RCC_LSE(RCC_OscInitStruct->LSEState));
-
+
/* Update LSE configuration in Backup Domain control register */
/* Requires to enable write access to Backup Domain of necessary */
if(__HAL_RCC_PWR_IS_CLK_DISABLED())
@@ -435,15 +542,15 @@
__HAL_RCC_PWR_CLK_ENABLE();
pwrclkchanged = SET;
}
-
+
if(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
- {
+ {
/* Enable write access to Backup domain */
PWR->CR1 |= PWR_CR1_DBP;
-
+
/* Wait for Backup domain Write protection disable */
tickstart = HAL_GetTick();
-
+
while(HAL_IS_BIT_CLR(PWR->CR1, PWR_CR1_DBP))
{
if((HAL_GetTick() - tickstart ) > RCC_DBP_TIMEOUT_VALUE)
@@ -452,7 +559,7 @@
}
}
}
-
+
/* Set the new LSE configuration -----------------------------------------*/
__HAL_RCC_LSE_CONFIG(RCC_OscInitStruct->LSEState);
/* Check the LSE State */
@@ -460,31 +567,31 @@
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
-
- /* Wait till LSE is ready */
+
+ /* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
+ }
}
}
else
{
/* Get Start Tick*/
tickstart = HAL_GetTick();
-
- /* Wait till LSE is ready */
+
+ /* Wait till LSE is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > RCC_LSE_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
+ }
}
}
-
+
/* Restore clock configuration if changed */
if(pwrclkchanged == SET)
{
@@ -498,7 +605,7 @@
{
/* Check if the PLL is used as system clock or not */
if(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
- {
+ {
if((RCC_OscInitStruct->PLL.PLLState) == RCC_PLL_ON)
{
/* Check the parameters */
@@ -510,14 +617,14 @@
#if defined (RCC_PLLCFGR_PLLR)
assert_param(IS_RCC_PLLR_VALUE(RCC_OscInitStruct->PLL.PLLR));
#endif
-
+
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
-
+
/* Get Start Tick*/
tickstart = HAL_GetTick();
-
- /* Wait till PLL is ready */
+
+ /* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
@@ -525,7 +632,7 @@
return HAL_TIMEOUT;
}
}
-
+
/* Configure the main PLL clock source, multiplication and division factors. */
#if defined (RCC_PLLCFGR_PLLR)
__HAL_RCC_PLL_CONFIG(RCC_OscInitStruct->PLL.PLLSource,
@@ -547,25 +654,25 @@
/* Get Start Tick*/
tickstart = HAL_GetTick();
-
- /* Wait till PLL is ready */
+
+ /* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
{
return HAL_TIMEOUT;
- }
+ }
}
}
else
{
/* Disable the main PLL. */
__HAL_RCC_PLL_DISABLE();
-
+
/* Get Start Tick*/
tickstart = HAL_GetTick();
-
- /* Wait till PLL is ready */
+
+ /* Wait till PLL is ready */
while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) != RESET)
{
if((HAL_GetTick() - tickstart ) > PLL_TIMEOUT_VALUE)
@@ -582,26 +689,26 @@
}
return HAL_OK;
}
-
+
/**
- * @brief Initializes the CPU, AHB and APB busses clocks according to the specified
+ * @brief Initializes the CPU, AHB and APB busses clocks according to the specified
* parameters in the RCC_ClkInitStruct.
- * @param RCC_ClkInitStruct: pointer to an RCC_OscInitTypeDef structure that
+ * @param RCC_ClkInitStruct pointer to an RCC_OscInitTypeDef structure that
* contains the configuration information for the RCC peripheral.
- * @param FLatency: FLASH Latency, this parameter depend on device selected
- *
- * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
+ * @param FLatency FLASH Latency, this parameter depend on device selected
+ *
+ * @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency
* and updated by HAL_RCC_GetHCLKFreq() function called within this function
*
* @note The HSI is used (enabled by hardware) as system clock source after
* startup from Reset, wake-up from STOP and STANDBY mode, or in case
* of failure of the HSE used directly or indirectly as system clock
* (if the Clock Security System CSS is enabled).
- *
+ *
* @note A switch from one clock source to another occurs only if the target
- * clock source is ready (clock stable after startup delay or PLL locked).
+ * clock source is ready (clock stable after startup delay or PLL locked).
* If a clock source which is not yet ready is selected, the switch will
- * occur when the clock source will be ready.
+ * occur when the clock source will be ready.
* You can use HAL_RCC_GetClockConfig() function to know which clock is
* currently used as system clock source.
* @note Depending on the device voltage range, the software has to set correctly
@@ -613,44 +720,63 @@
{
uint32_t tickstart = 0;
+ /* Check Null pointer */
+ if(RCC_ClkInitStruct == NULL)
+ {
+ return HAL_ERROR;
+ }
+
/* Check the parameters */
assert_param(IS_RCC_CLOCKTYPE(RCC_ClkInitStruct->ClockType));
assert_param(IS_FLASH_LATENCY(FLatency));
- /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
- must be correctly programmed according to the frequency of the CPU clock
- (HCLK) and the supply voltage of the device. */
-
+ /* To correctly read data from FLASH memory, the number of wait states (LATENCY)
+ must be correctly programmed according to the frequency of the CPU clock
+ (HCLK) and the supply voltage of the device. */
+
/* Increasing the CPU frequency */
- if(FLatency > (FLASH->ACR & FLASH_ACR_LATENCY))
- {
+ if(FLatency > __HAL_FLASH_GET_LATENCY())
+ {
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
-
+
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
- if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
+ if(__HAL_FLASH_GET_LATENCY() != FLatency)
{
return HAL_ERROR;
}
}
-
+
/*-------------------------- HCLK Configuration --------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_HCLK) == RCC_CLOCKTYPE_HCLK)
{
+ /* Set the highest APBx dividers in order to ensure that we do not go through
+ a non-spec phase whatever we decrease or increase HCLK. */
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
+ {
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_HCLK_DIV16);
+ }
+
+ if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
+ {
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, (RCC_HCLK_DIV16 << 3));
+ }
+
+ /* Set the new HCLK clock divider */
assert_param(IS_RCC_HCLK(RCC_ClkInitStruct->AHBCLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
}
-
- /*------------------------- SYSCLK Configuration ---------------------------*/
+
+ /*------------------------- SYSCLK Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_SYSCLK) == RCC_CLOCKTYPE_SYSCLK)
- {
+ {
assert_param(IS_RCC_SYSCLKSOURCE(RCC_ClkInitStruct->SYSCLKSource));
-
+
/* HSE is selected as System Clock Source */
if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
{
- /* Check the HSE ready flag */
+ /* Check the HSE ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSERDY) == RESET)
{
return HAL_ERROR;
@@ -659,7 +785,7 @@
/* PLL is selected as System Clock Source */
else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
{
- /* Check the PLL ready flag */
+ /* Check the PLL ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLRDY) == RESET)
{
return HAL_ERROR;
@@ -668,71 +794,49 @@
/* HSI is selected as System Clock Source */
else
{
- /* Check the HSI ready flag */
+ /* Check the HSI ready flag */
if(__HAL_RCC_GET_FLAG(RCC_FLAG_HSIRDY) == RESET)
{
return HAL_ERROR;
}
}
-
+
__HAL_RCC_SYSCLK_CONFIG(RCC_ClkInitStruct->SYSCLKSource);
+
/* Get Start Tick*/
tickstart = HAL_GetTick();
-
- if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_HSE)
+
+ while (__HAL_RCC_GET_SYSCLK_SOURCE() != (RCC_ClkInitStruct->SYSCLKSource << RCC_CFGR_SWS_Pos))
{
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSE)
- {
- if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else if(RCC_ClkInitStruct->SYSCLKSource == RCC_SYSCLKSOURCE_PLLCLK)
- {
- while (__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_PLLCLK)
+ if ((HAL_GetTick() - tickstart) > CLOCKSWITCH_TIMEOUT_VALUE)
{
- if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
- }
- }
- else
- {
- while(__HAL_RCC_GET_SYSCLK_SOURCE() != RCC_SYSCLKSOURCE_STATUS_HSI)
- {
- if((HAL_GetTick() - tickstart ) > CLOCKSWITCH_TIMEOUT_VALUE)
- {
- return HAL_TIMEOUT;
- }
+ return HAL_TIMEOUT;
}
}
}
-
+
/* Decreasing the number of wait states because of lower CPU frequency */
- if(FLatency < (FLASH->ACR & FLASH_ACR_LATENCY))
+ if(FLatency < __HAL_FLASH_GET_LATENCY())
{
/* Program the new number of wait states to the LATENCY bits in the FLASH_ACR register */
__HAL_FLASH_SET_LATENCY(FLatency);
-
+
/* Check that the new number of wait states is taken into account to access the Flash
memory by reading the FLASH_ACR register */
- if((FLASH->ACR & FLASH_ACR_LATENCY) != FLatency)
+ if(__HAL_FLASH_GET_LATENCY() != FLatency)
{
return HAL_ERROR;
}
}
- /*-------------------------- PCLK1 Configuration ---------------------------*/
+ /*-------------------------- PCLK1 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK1) == RCC_CLOCKTYPE_PCLK1)
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB1CLKDivider));
MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, RCC_ClkInitStruct->APB1CLKDivider);
}
-
- /*-------------------------- PCLK2 Configuration ---------------------------*/
+
+ /*-------------------------- PCLK2 Configuration ---------------------------*/
if(((RCC_ClkInitStruct->ClockType) & RCC_CLOCKTYPE_PCLK2) == RCC_CLOCKTYPE_PCLK2)
{
assert_param(IS_RCC_PCLK(RCC_ClkInitStruct->APB2CLKDivider));
@@ -740,11 +844,11 @@
}
/* Update the SystemCoreClock global variable */
- SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> POSITION_VAL(RCC_CFGR_HPRE)];
-
+ SystemCoreClock = HAL_RCC_GetSysClockFreq() >> AHBPrescTable[(RCC->CFGR & RCC_CFGR_HPRE)>> RCC_CFGR_HPRE_Pos];
+
/* Configure the source of time base considering new system clocks settings*/
HAL_InitTick (TICK_INT_PRIORITY);
-
+
return HAL_OK;
}
@@ -752,17 +856,17 @@
* @}
*/
-/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
- * @brief RCC clocks control functions
+/** @defgroup RCC_Exported_Functions_Group2 Peripheral Control functions
+ * @brief RCC clocks control functions
*
- @verbatim
+ @verbatim
===============================================================================
##### Peripheral Control functions #####
- ===============================================================================
+ ===============================================================================
[..]
- This subsection provides a set of functions allowing to control the RCC Clocks
+ This subsection provides a set of functions allowing to control the RCC Clocks
frequencies.
-
+
@endverbatim
* @{
*/
@@ -770,11 +874,11 @@
/**
* @brief Selects the clock source to output on MCO1 pin(PA8) or on MCO2 pin(PC9).
* @note PA8/PC9 should be configured in alternate function mode.
- * @param RCC_MCOx: specifies the output direction for the clock source.
+ * @param RCC_MCOx specifies the output direction for the clock source.
* This parameter can be one of the following values:
* @arg RCC_MCO1: Clock source to output on MCO1 pin(PA8).
* @arg RCC_MCO2: Clock source to output on MCO2 pin(PC9).
- * @param RCC_MCOSource: specifies the clock source to output.
+ * @param RCC_MCOSource specifies the clock source to output.
* This parameter can be one of the following values:
* @arg RCC_MCO1SOURCE_HSI: HSI clock selected as MCO1 source
* @arg RCC_MCO1SOURCE_LSE: LSE clock selected as MCO1 source
@@ -784,7 +888,7 @@
* @arg RCC_MCO2SOURCE_PLLI2SCLK: PLLI2S clock selected as MCO2 source
* @arg RCC_MCO2SOURCE_HSE: HSE clock selected as MCO2 source
* @arg RCC_MCO2SOURCE_PLLCLK: main PLL clock selected as MCO2 source
- * @param RCC_MCODiv: specifies the MCOx prescaler.
+ * @param RCC_MCODiv specifies the MCOx prescaler.
* This parameter can be one of the following values:
* @arg RCC_MCODIV_1: no division applied to MCOx clock
* @arg RCC_MCODIV_2: division by 2 applied to MCOx clock
@@ -803,28 +907,28 @@
if(RCC_MCOx == RCC_MCO1)
{
assert_param(IS_RCC_MCO1SOURCE(RCC_MCOSource));
-
+
/* MCO1 Clock Enable */
MCO1_CLK_ENABLE();
-
- /* Configure the MCO1 pin in alternate function mode */
+
+ /* Configure the MCO1 pin in alternate function mode */
GPIO_InitStruct.Pin = MCO1_PIN;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
GPIO_InitStruct.Speed = GPIO_SPEED_HIGH;
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
HAL_GPIO_Init(MCO1_GPIO_PORT, &GPIO_InitStruct);
-
+
/* Mask MCO1 and MCO1PRE[2:0] bits then Select MCO1 clock source and prescaler */
MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO1 | RCC_CFGR_MCO1PRE), (RCC_MCOSource | RCC_MCODiv));
}
else
{
assert_param(IS_RCC_MCO2SOURCE(RCC_MCOSource));
-
+
/* MCO2 Clock Enable */
MCO2_CLK_ENABLE();
-
+
/* Configure the MCO2 pin in alternate function mode */
GPIO_InitStruct.Pin = MCO2_PIN;
GPIO_InitStruct.Mode = GPIO_MODE_AF_PP;
@@ -832,7 +936,7 @@
GPIO_InitStruct.Pull = GPIO_NOPULL;
GPIO_InitStruct.Alternate = GPIO_AF0_MCO;
HAL_GPIO_Init(MCO2_GPIO_PORT, &GPIO_InitStruct);
-
+
/* Mask MCO2 and MCO2PRE[2:0] bits then Select MCO2 clock source and prescaler */
MODIFY_REG(RCC->CFGR, (RCC_CFGR_MCO2 | RCC_CFGR_MCO2PRE), (RCC_MCOSource | (RCC_MCODiv << 3)));
}
@@ -843,8 +947,8 @@
* @note If a failure is detected on the HSE oscillator clock, this oscillator
* is automatically disabled and an interrupt is generated to inform the
* software about the failure (Clock Security System Interrupt, CSSI),
- * allowing the MCU to perform rescue operations. The CSSI is linked to
- * the Cortex-M7 NMI (Non-Maskable Interrupt) exception vector.
+ * allowing the MCU to perform rescue operations. The CSSI is linked to
+ * the Cortex-M7 NMI (Non-Maskable Interrupt) exception vector.
* @retval None
*/
void HAL_RCC_EnableCSS(void)
@@ -863,14 +967,14 @@
/**
* @brief Returns the SYSCLK frequency
- *
- * @note The system frequency computed by this function is not the real
- * frequency in the chip. It is calculated based on the predefined
+ *
+ * @note The system frequency computed by this function is not the real
+ * frequency in the chip. It is calculated based on the predefined
* constant and the selected clock source:
* @note If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
* @note If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
- * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
- * or HSI_VALUE(*) multiplied/divided by the PLL factors.
+ * @note If SYSCLK source is PLL, function returns values based on HSE_VALUE(**)
+ * or HSI_VALUE(*) multiplied/divided by the PLL factors.
* @note (*) HSI_VALUE is a constant defined in stm32f7xx_hal_conf.h file (default value
* 16 MHz) but the real value may vary depending on the variations
* in voltage and temperature.
@@ -878,17 +982,17 @@
* 25 MHz), user has to ensure that HSE_VALUE is same as the real
* frequency of the crystal used. Otherwise, this function may
* have wrong result.
- *
+ *
* @note The result of this function could be not correct when using fractional
* value for HSE crystal.
- *
- * @note This function can be used by the user application to compute the
+ *
+ * @note This function can be used by the user application to compute the
* baudrate for the communication peripherals or configure other parameters.
- *
+ *
* @note Each time SYSCLK changes, this function must be called to update the
* right SYSCLK value. Otherwise, any configuration based on this function will be incorrect.
- *
- *
+ *
+ *
* @retval SYSCLK frequency
*/
uint32_t HAL_RCC_GetSysClockFreq(void)
@@ -917,15 +1021,15 @@
if (__HAL_RCC_GET_PLL_OSCSOURCE() != RCC_PLLCFGR_PLLSRC_HSI)
{
/* HSE used as PLL clock source */
- pllvco = ((HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
+ pllvco = (uint32_t) ((((uint64_t) HSE_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
}
else
{
/* HSI used as PLL clock source */
- pllvco = ((HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN)));
+ pllvco = (uint32_t) ((((uint64_t) HSI_VALUE * ((uint64_t) ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos)))) / (uint64_t)pllm);
}
- pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> POSITION_VAL(RCC_PLLCFGR_PLLP)) + 1 ) *2);
-
+ pllp = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >> RCC_PLLCFGR_PLLP_Pos) + 1 ) *2);
+
sysclockfreq = pllvco/pllp;
break;
}
@@ -939,9 +1043,9 @@
}
/**
- * @brief Returns the HCLK frequency
+ * @brief Returns the HCLK frequency
* @note Each time HCLK changes, this function must be called to update the
- * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
+ * right HCLK value. Otherwise, any configuration based on this function will be incorrect.
* @note The SystemCoreClock CMSIS variable is used to store System Clock Frequency.
* @retval HCLK frequency
*/
@@ -951,19 +1055,19 @@
}
/**
- * @brief Returns the PCLK1 frequency
+ * @brief Returns the PCLK1 frequency
* @note Each time PCLK1 changes, this function must be called to update the
* right PCLK1 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK1 frequency
*/
uint32_t HAL_RCC_GetPCLK1Freq(void)
-{
+{
/* Get HCLK source and Compute PCLK1 frequency ---------------------------*/
- return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> POSITION_VAL(RCC_CFGR_PPRE1)]);
+ return (HAL_RCC_GetHCLKFreq() >> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE1)>> RCC_CFGR_PPRE1_Pos]);
}
/**
- * @brief Returns the PCLK2 frequency
+ * @brief Returns the PCLK2 frequency
* @note Each time PCLK2 changes, this function must be called to update the
* right PCLK2 value. Otherwise, any configuration based on this function will be incorrect.
* @retval PCLK2 frequency
@@ -971,13 +1075,13 @@
uint32_t HAL_RCC_GetPCLK2Freq(void)
{
/* Get HCLK source and Compute PCLK2 frequency ---------------------------*/
- return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> POSITION_VAL(RCC_CFGR_PPRE2)]);
-}
+ return (HAL_RCC_GetHCLKFreq()>> APBPrescTable[(RCC->CFGR & RCC_CFGR_PPRE2)>> RCC_CFGR_PPRE2_Pos]);
+}
/**
- * @brief Configures the RCC_OscInitStruct according to the internal
+ * @brief Configures the RCC_OscInitStruct according to the internal
* RCC configuration registers.
- * @param RCC_OscInitStruct: pointer to an RCC_OscInitTypeDef structure that
+ * @param RCC_OscInitStruct pointer to an RCC_OscInitTypeDef structure that
* will be configured.
* @retval None
*/
@@ -985,7 +1089,7 @@
{
/* Set all possible values for the Oscillator type parameter ---------------*/
RCC_OscInitStruct->OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_LSI;
-
+
/* Get the HSE configuration -----------------------------------------------*/
if((RCC->CR &RCC_CR_HSEBYP) == RCC_CR_HSEBYP)
{
@@ -999,7 +1103,7 @@
{
RCC_OscInitStruct->HSEState = RCC_HSE_OFF;
}
-
+
/* Get the HSI configuration -----------------------------------------------*/
if((RCC->CR &RCC_CR_HSION) == RCC_CR_HSION)
{
@@ -1009,9 +1113,9 @@
{
RCC_OscInitStruct->HSIState = RCC_HSI_OFF;
}
-
- RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> POSITION_VAL(RCC_CR_HSITRIM));
-
+
+ RCC_OscInitStruct->HSICalibrationValue = (uint32_t)((RCC->CR &RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
+
/* Get the LSE configuration -----------------------------------------------*/
if((RCC->BDCR &RCC_BDCR_LSEBYP) == RCC_BDCR_LSEBYP)
{
@@ -1025,7 +1129,7 @@
{
RCC_OscInitStruct->LSEState = RCC_LSE_OFF;
}
-
+
/* Get the LSI configuration -----------------------------------------------*/
if((RCC->CSR &RCC_CSR_LSION) == RCC_CSR_LSION)
{
@@ -1035,7 +1139,7 @@
{
RCC_OscInitStruct->LSIState = RCC_LSI_OFF;
}
-
+
/* Get the PLL configuration -----------------------------------------------*/
if((RCC->CR &RCC_CR_PLLON) == RCC_CR_PLLON)
{
@@ -1047,38 +1151,41 @@
}
RCC_OscInitStruct->PLL.PLLSource = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC);
RCC_OscInitStruct->PLL.PLLM = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);
- RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> POSITION_VAL(RCC_PLLCFGR_PLLN));
- RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1) >> POSITION_VAL(RCC_PLLCFGR_PLLP));
- RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> POSITION_VAL(RCC_PLLCFGR_PLLQ));
+ RCC_OscInitStruct->PLL.PLLN = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
+ RCC_OscInitStruct->PLL.PLLP = (uint32_t)((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) + RCC_PLLCFGR_PLLP_0) << 1) >> RCC_PLLCFGR_PLLP_Pos);
+ RCC_OscInitStruct->PLL.PLLQ = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLQ) >> RCC_PLLCFGR_PLLQ_Pos);
+#if defined (RCC_PLLCFGR_PLLR)
+ RCC_OscInitStruct->PLL.PLLR = (uint32_t)((RCC->PLLCFGR & RCC_PLLCFGR_PLLR) >> POSITION_VAL(RCC_PLLCFGR_PLLR));
+#endif
}
/**
- * @brief Configures the RCC_ClkInitStruct according to the internal
+ * @brief Configures the RCC_ClkInitStruct according to the internal
* RCC configuration registers.
- * @param RCC_ClkInitStruct: pointer to an RCC_ClkInitTypeDef structure that
+ * @param RCC_ClkInitStruct pointer to an RCC_ClkInitTypeDef structure that
* will be configured.
- * @param pFLatency: Pointer on the Flash Latency.
+ * @param pFLatency Pointer on the Flash Latency.
* @retval None
*/
void HAL_RCC_GetClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t *pFLatency)
{
/* Set all possible values for the Clock type parameter --------------------*/
RCC_ClkInitStruct->ClockType = RCC_CLOCKTYPE_SYSCLK | RCC_CLOCKTYPE_HCLK | RCC_CLOCKTYPE_PCLK1 | RCC_CLOCKTYPE_PCLK2;
-
- /* Get the SYSCLK configuration --------------------------------------------*/
+
+ /* Get the SYSCLK configuration --------------------------------------------*/
RCC_ClkInitStruct->SYSCLKSource = (uint32_t)(RCC->CFGR & RCC_CFGR_SW);
-
- /* Get the HCLK configuration ----------------------------------------------*/
- RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
-
- /* Get the APB1 configuration ----------------------------------------------*/
- RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
-
- /* Get the APB2 configuration ----------------------------------------------*/
+
+ /* Get the HCLK configuration ----------------------------------------------*/
+ RCC_ClkInitStruct->AHBCLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_HPRE);
+
+ /* Get the APB1 configuration ----------------------------------------------*/
+ RCC_ClkInitStruct->APB1CLKDivider = (uint32_t)(RCC->CFGR & RCC_CFGR_PPRE1);
+
+ /* Get the APB2 configuration ----------------------------------------------*/
RCC_ClkInitStruct->APB2CLKDivider = (uint32_t)((RCC->CFGR & RCC_CFGR_PPRE2) >> 3);
-
- /* Get the Flash Wait State (Latency) configuration ------------------------*/
- *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
+
+ /* Get the Flash Wait State (Latency) configuration ------------------------*/
+ *pFLatency = (uint32_t)(FLASH->ACR & FLASH_ACR_LATENCY);
}
/**
@@ -1107,7 +1214,7 @@
{
/* NOTE : This function Should not be modified, when the callback is needed,
the HAL_RCC_CSSCallback could be implemented in the user file
- */
+ */
}
/**
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rcc.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rcc.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_rcc.h
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief Header file of RCC HAL module.
******************************************************************************
* @attention
@@ -267,8 +265,10 @@
/** @defgroup RCC_RTC_Clock_Source RCC RTC Clock Source
* @{
*/
+#define RCC_RTCCLKSOURCE_NO_CLK ((uint32_t)0x00000000U)
#define RCC_RTCCLKSOURCE_LSE ((uint32_t)0x00000100U)
#define RCC_RTCCLKSOURCE_LSI ((uint32_t)0x00000200U)
+#define RCC_RTCCLKSOURCE_HSE_DIVX ((uint32_t)0x00000300U)
#define RCC_RTCCLKSOURCE_HSE_DIV2 ((uint32_t)0x00020300U)
#define RCC_RTCCLKSOURCE_HSE_DIV3 ((uint32_t)0x00030300U)
#define RCC_RTCCLKSOURCE_HSE_DIV4 ((uint32_t)0x00040300U)
@@ -694,11 +694,11 @@
/** @brief Macro to adjust the Internal High Speed oscillator (HSI) calibration value.
* @note The calibration is used to compensate for the variations in voltage
* and temperature that influence the frequency of the internal HSI RC.
- * @param __HSICALIBRATIONVALUE__: specifies the calibration trimming value.
+ * @param __HSICALIBRATIONVALUE__ specifies the calibration trimming value.
* (default is RCC_HSICALIBRATION_DEFAULT).
*/
#define __HAL_RCC_HSI_CALIBRATIONVALUE_ADJUST(__HSICALIBRATIONVALUE__) (MODIFY_REG(RCC->CR,\
- RCC_CR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << POSITION_VAL(RCC_CR_HSITRIM)))
+ RCC_CR_HSITRIM, (uint32_t)(__HSICALIBRATIONVALUE__) << RCC_CR_HSITRIM_Pos))
/**
* @}
*/
@@ -739,7 +739,7 @@
* @note This function reset the CSSON bit, so if the clock security system(CSS)
* was previously enabled you have to enable it again after calling this
* function.
- * @param __STATE__: specifies the new state of the HSE.
+ * @param __STATE__ specifies the new state of the HSE.
* This parameter can be one of the following values:
* @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
* 6 HSE oscillator clock cycles.
@@ -787,7 +787,7 @@
* @note After enabling the LSE (RCC_LSE_ON or RCC_LSE_BYPASS), the application
* software should wait on LSERDY flag to be set indicating that LSE clock
* is stable and can be used to clock the RTC.
- * @param __STATE__: specifies the new state of the LSE.
+ * @param __STATE__ specifies the new state of the LSE.
* This parameter can be one of the following values:
* @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
* 6 LSE oscillator clock cycles.
@@ -838,12 +838,13 @@
* @note Once the RTC clock is configured it can't be changed unless the
* Backup domain is reset using __HAL_RCC_BackupReset_RELEASE() macro, or by
* a Power On Reset (POR).
- * @param __RTCCLKSource__: specifies the RTC clock source.
+ * @param __RTCCLKSource__ specifies the RTC clock source.
* This parameter can be one of the following values:
- * @arg RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
- * @arg RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
- * @arg RCC_RTCCLKSOURCE_HSE_DIVx: HSE clock divided by x selected
- * as RTC clock, where x:[2,31]
+ @arg @ref RCC_RTCCLKSOURCE_NO_CLK: No clock selected as RTC clock.
+ * @arg @ref RCC_RTCCLKSOURCE_LSE: LSE selected as RTC clock.
+ * @arg @ref RCC_RTCCLKSOURCE_LSI: LSI selected as RTC clock.
+ * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected
+ * as RTC clock, where x:[2,31]
* @note If the LSE or LSI is used as RTC clock source, the RTC continues to
* work in STOP and STANDBY modes, and can be used as wakeup source.
* However, when the HSE clock is used as RTC clock source, the RTC
@@ -852,11 +853,28 @@
* RTC clock source).
*/
#define __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__) (((__RTCCLKSource__) & RCC_BDCR_RTCSEL) == RCC_BDCR_RTCSEL) ? \
- MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
+ MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, ((__RTCCLKSource__) & 0xFFFFCFF)) : CLEAR_BIT(RCC->CFGR, RCC_CFGR_RTCPRE)
#define __HAL_RCC_RTC_CONFIG(__RTCCLKSource__) do { __HAL_RCC_RTC_CLKPRESCALER(__RTCCLKSource__); \
RCC->BDCR |= ((__RTCCLKSource__) & 0x00000FFF); \
- } while (0)
+ } while (0)
+
+/** @brief Macro to get the RTC clock source.
+ * @retval The clock source can be one of the following values:
+ * @arg @ref RCC_RTCCLKSOURCE_NO_CLK No clock selected as RTC clock
+ * @arg @ref RCC_RTCCLKSOURCE_LSE LSE selected as RTC clock
+ * @arg @ref RCC_RTCCLKSOURCE_LSI LSI selected as RTC clock
+ * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX HSE divided by X selected as RTC clock (X can be retrieved thanks to @ref __HAL_RCC_GET_RTC_HSE_PRESCALER()
+ */
+#define __HAL_RCC_GET_RTC_SOURCE() (READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL))
+
+/**
+ * @brief Get the RTC and HSE clock divider (RTCPRE).
+ * @retval Returned value can be one of the following values:
+ * @arg @ref RCC_RTCCLKSOURCE_HSE_DIVX: HSE clock divided by x selected
+ * as RTC clock, where x:[2,31]
+ */
+#define __HAL_RCC_GET_RTC_HSE_PRESCALER() (READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE) | RCC_BDCR_RTCSEL)
/** @brief Macros to force or release the Backup domain reset.
* @note This function resets the RTC peripheral (including the backup registers)
@@ -885,7 +903,7 @@
/** @brief Macro to configure the PLL clock source.
* @note This function must be used only when the main PLL is disabled.
- * @param __PLLSOURCE__: specifies the PLL entry clock source.
+ * @param __PLLSOURCE__ specifies the PLL entry clock source.
* This parameter can be one of the following values:
* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
@@ -895,7 +913,7 @@
/** @brief Macro to configure the PLL multiplication factor.
* @note This function must be used only when the main PLL is disabled.
- * @param __PLLM__: specifies the division factor for PLL VCO input clock
+ * @param __PLLM__ specifies the division factor for PLL VCO input clock
* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
* @note You have to set the PLLM parameter correctly to ensure that the VCO input
* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
@@ -913,7 +931,7 @@
/** @brief Macro to configure the I2S clock source (I2SCLK).
* @note This function must be called before enabling the I2S APB clock.
- * @param __SOURCE__: specifies the I2S clock source.
+ * @param __SOURCE__ specifies the I2S clock source.
* This parameter can be one of the following values:
* @arg RCC_I2SCLKSOURCE_PLLI2S: PLLI2S clock used as I2S clock source.
* @arg RCC_I2SCLKSOURCE_EXT: External clock mapped on the I2S_CKIN pin
@@ -937,7 +955,7 @@
*/
/**
* @brief Macro to configure the system clock source.
- * @param __RCC_SYSCLKSOURCE__: specifies the system clock source.
+ * @param __RCC_SYSCLKSOURCE__ specifies the system clock source.
* This parameter can be one of the following values:
* - RCC_SYSCLKSOURCE_HSI: HSI oscillator is used as system clock source.
* - RCC_SYSCLKSOURCE_HSE: HSE oscillator is used as system clock source.
@@ -951,8 +969,8 @@
* - RCC_SYSCLKSOURCE_STATUS_HSI: HSI used as system clock.
* - RCC_SYSCLKSOURCE_STATUS_HSE: HSE used as system clock.
* - RCC_SYSCLKSOURCE_STATUS_PLLCLK: PLL used as system clock.
- */
-#define __HAL_RCC_GET_SYSCLK_SOURCE() ((uint32_t)(RCC->CFGR & RCC_CFGR_SWS))
+ */
+#define __HAL_RCC_GET_SYSCLK_SOURCE() (RCC->CFGR & RCC_CFGR_SWS)
/**
* @brief Macro to configures the External Low Speed oscillator (LSE) drive capability.
@@ -960,7 +978,7 @@
* this domain after reset, you have to enable write access using
* HAL_PWR_EnableBkUpAccess() function before to configure the LSE
* (to be done once after reset).
- * @param __RCC_LSEDRIVE__: specifies the new state of the LSE drive capability.
+ * @param __RCC_LSEDRIVE__ specifies the new state of the LSE drive capability.
* This parameter can be one of the following values:
* @arg RCC_LSEDRIVE_LOW: LSE oscillator low drive capability.
* @arg RCC_LSEDRIVE_MEDIUMLOW: LSE oscillator medium low drive capability.
@@ -1034,7 +1052,7 @@
/** @brief Enable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to enable
* the selected interrupts).
- * @param __INTERRUPT__: specifies the RCC interrupt sources to be enabled.
+ * @param __INTERRUPT__ specifies the RCC interrupt sources to be enabled.
* This parameter can be any combination of the following values:
* @arg RCC_IT_LSIRDY: LSI ready interrupt.
* @arg RCC_IT_LSERDY: LSE ready interrupt.
@@ -1047,7 +1065,7 @@
/** @brief Disable RCC interrupt (Perform Byte access to RCC_CIR[14:8] bits to disable
* the selected interrupts).
- * @param __INTERRUPT__: specifies the RCC interrupt sources to be disabled.
+ * @param __INTERRUPT__ specifies the RCC interrupt sources to be disabled.
* This parameter can be any combination of the following values:
* @arg RCC_IT_LSIRDY: LSI ready interrupt.
* @arg RCC_IT_LSERDY: LSE ready interrupt.
@@ -1060,7 +1078,7 @@
/** @brief Clear the RCC's interrupt pending bits (Perform Byte access to RCC_CIR[23:16]
* bits to clear the selected interrupt pending bits.
- * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
+ * @param __INTERRUPT__ specifies the interrupt pending bit to clear.
* This parameter can be any combination of the following values:
* @arg RCC_IT_LSIRDY: LSI ready interrupt.
* @arg RCC_IT_LSERDY: LSE ready interrupt.
@@ -1073,7 +1091,7 @@
#define __HAL_RCC_CLEAR_IT(__INTERRUPT__) (*(__IO uint8_t *) RCC_CIR_BYTE2_ADDRESS = (__INTERRUPT__))
/** @brief Check the RCC's interrupt has occurred or not.
- * @param __INTERRUPT__: specifies the RCC interrupt source to check.
+ * @param __INTERRUPT__ specifies the RCC interrupt source to check.
* This parameter can be one of the following values:
* @arg RCC_IT_LSIRDY: LSI ready interrupt.
* @arg RCC_IT_LSERDY: LSE ready interrupt.
@@ -1092,7 +1110,7 @@
#define __HAL_RCC_CLEAR_RESET_FLAGS() (RCC->CSR |= RCC_CSR_RMVF)
/** @brief Check RCC flag is set or not.
- * @param __FLAG__: specifies the flag to check.
+ * @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready.
* @arg RCC_FLAG_HSERDY: HSE oscillator clock ready.
@@ -1132,7 +1150,7 @@
* @{
*/
/* Initialization and de-initialization functions ******************************/
-void HAL_RCC_DeInit(void);
+HAL_StatusTypeDef HAL_RCC_DeInit(void);
HAL_StatusTypeDef HAL_RCC_OscConfig(RCC_OscInitTypeDef *RCC_OscInitStruct);
HAL_StatusTypeDef HAL_RCC_ClockConfig(RCC_ClkInitTypeDef *RCC_ClkInitStruct, uint32_t FLatency);
/**
@@ -1173,10 +1191,12 @@
* @{
*/
#define HSE_TIMEOUT_VALUE HSE_STARTUP_TIMEOUT
-#define HSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
-#define LSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
-#define PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
-#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
+#define HSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
+#define LSI_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
+#define PLL_TIMEOUT_VALUE ((uint32_t)2) /* 2 ms */
+#define CLOCKSWITCH_TIMEOUT_VALUE ((uint32_t)5000) /* 5 s */
+#define PLLI2S_TIMEOUT_VALUE 100U /* Timeout value fixed to 100 ms */
+#define PLLSAI_TIMEOUT_VALUE 100U /* Timeout value fixed to 100 ms */
/** @defgroup RCC_BitAddress_Alias RCC BitAddress Alias
* @brief RCC registers bit address alias
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rcc_ex.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rcc_ex.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_rcc_ex.c
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief Extension RCC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities RCC extension peripheral:
@@ -58,10 +56,6 @@
/** @defgroup RCCEx_Private_Defines RCCEx Private Defines
* @{
*/
-
-#define PLLI2S_TIMEOUT_VALUE 100 /* Timeout value fixed to 100 ms */
-#define PLLSAI_TIMEOUT_VALUE 100 /* Timeout value fixed to 100 ms */
-
/**
* @}
*/
@@ -114,7 +108,7 @@
/**
* @brief Initializes the RCC extended peripherals clocks according to the specified
* parameters in the RCC_PeriphCLKInitTypeDef.
- * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
+ * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
* contains the configuration information for the Extended Peripherals
* clocks(I2S, SAI, LTDC, RTC, TIM, UARTs, USARTs, LTPIM, SDMMC...).
*
@@ -503,8 +497,8 @@
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
/* Read PLLI2SP and PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
- tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP));
- tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
+ tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos);
+ tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
@@ -521,8 +515,8 @@
assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
/* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */
- tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP));
- tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
+ tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos);
+ tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
@@ -540,8 +534,8 @@
assert_param(IS_RCC_PLLI2SP_VALUE(PeriphClkInit->PLLI2S.PLLI2SP));
/* Read PLLI2SR value from PLLI2SCFGR register (this value is not needed for SPDIF-RX configuration) */
- tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
- tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
+ tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
+ tmpreg1 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
/* SPDIFCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SP */
@@ -612,8 +606,8 @@
assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
/* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
- tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP));
- tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
+ tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
+ tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
@@ -630,8 +624,8 @@
/* check for Parameters */
assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
/* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */
- tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
- tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
+ tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
+ tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
/* Configure the PLLSAI division factors */
/* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */
@@ -647,8 +641,8 @@
assert_param(IS_RCC_PLLSAI_DIVR_VALUE(PeriphClkInit->PLLSAIDivR));
/* Read PLLSAIP and PLLSAIQ value from PLLSAICFGR register (these value are not needed for LTDC configuration) */
- tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
- tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP));
+ tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
+ tmpreg1 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
@@ -682,7 +676,7 @@
/**
* @brief Get the RCC_PeriphCLKInitTypeDef according to the internal
* RCC configuration registers.
- * @param PeriphClkInit: pointer to the configured RCC_PeriphCLKInitTypeDef structure
+ * @param PeriphClkInit pointer to the configured RCC_PeriphCLKInitTypeDef structure
* @retval None
*/
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
@@ -718,21 +712,21 @@
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
/* Get the PLLI2S Clock configuration -----------------------------------------------*/
- PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
- PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP));
- PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
- PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
+ PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
+ PeriphClkInit->PLLI2S.PLLI2SP = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SP) >> RCC_PLLI2SCFGR_PLLI2SP_Pos);
+ PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
+ PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
/* Get the PLLSAI Clock configuration -----------------------------------------------*/
- PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN));
- PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP));
- PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
- PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR));
+ PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos);
+ PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
+ PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
+ PeriphClkInit->PLLSAI.PLLSAIR = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIR) >> RCC_PLLSAICFGR_PLLSAIR_Pos);
/* Get the PLLSAI/PLLI2S division factors -------------------------------------------*/
- PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR1_PLLI2SDIVQ));
- PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR1_PLLSAIDIVQ));
- PeriphClkInit->PLLSAIDivR = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVR) >> POSITION_VAL(RCC_DCKCFGR1_PLLSAIDIVR));
+ PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) >> RCC_DCKCFGR1_PLLI2SDIVQ_Pos);
+ PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> RCC_DCKCFGR1_PLLSAIDIVQ_Pos);
+ PeriphClkInit->PLLSAIDivR = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVR) >> RCC_DCKCFGR1_PLLSAIDIVR_Pos);
/* Get the SAI1 clock configuration ----------------------------------------------*/
PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
@@ -822,7 +816,7 @@
/**
* @brief Initializes the RCC extended peripherals clocks according to the specified
* parameters in the RCC_PeriphCLKInitTypeDef.
- * @param PeriphClkInit: pointer to an RCC_PeriphCLKInitTypeDef structure that
+ * @param PeriphClkInit pointer to an RCC_PeriphCLKInitTypeDef structure that
* contains the configuration information for the Extended Peripherals
* clocks(I2S, SAI, RTC, TIM, UARTs, USARTs, LTPIM, SDMMC...).
*
@@ -1154,7 +1148,7 @@
assert_param(IS_RCC_PLLI2SR_VALUE(PeriphClkInit->PLLI2S.PLLI2SR));
/* Read PLLI2SQ value from PLLI2SCFGR register (this value is not needed for I2S configuration) */
- tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
+ tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) x (PLLI2SN/PLLM) */
/* I2SCLK = f(PLLI2S clock output) = f(VCO clock) / PLLI2SR */
@@ -1171,7 +1165,7 @@
assert_param(IS_RCC_PLLI2S_DIVQ_VALUE(PeriphClkInit->PLLI2SDivQ));
/* Read PLLI2SP and PLLI2SR values from PLLI2SCFGR register (this value is not needed for SAI configuration) */
- tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
+ tmpreg0 = ((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
/* Configure the PLLI2S division factors */
/* PLLI2S_VCO Input = PLL_SOURCE/PLLM */
/* PLLI2S_VCO Output = PLLI2S_VCO Input * PLLI2SN */
@@ -1244,7 +1238,7 @@
assert_param(IS_RCC_PLLSAI_DIVQ_VALUE(PeriphClkInit->PLLSAIDivQ));
/* Read PLLSAIP value from PLLSAICFGR register (this value is not needed for SAI configuration) */
- tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP));
+ tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
/* PLLSAI_VCO Input = PLL_SOURCE/PLLM */
/* PLLSAI_VCO Output = PLLSAI_VCO Input * PLLSAIN */
/* SAI_CLK(first level) = PLLSAI_VCO Output/PLLSAIQ */
@@ -1261,7 +1255,7 @@
/* check for Parameters */
assert_param(IS_RCC_PLLSAIP_VALUE(PeriphClkInit->PLLSAI.PLLSAIP));
/* Read PLLSAIQ and PLLSAIR value from PLLSAICFGR register (this value is not needed for CK48 configuration) */
- tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
+ tmpreg0 = ((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
/* Configure the PLLSAI division factors */
/* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) x (PLLI2SN/PLLM) */
@@ -1291,7 +1285,7 @@
/**
* @brief Get the RCC_PeriphCLKInitTypeDef according to the internal
* RCC configuration registers.
- * @param PeriphClkInit: pointer to the configured RCC_PeriphCLKInitTypeDef structure
+ * @param PeriphClkInit pointer to the configured RCC_PeriphCLKInitTypeDef structure
* @retval None
*/
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit)
@@ -1311,18 +1305,18 @@
RCC_PERIPHCLK_CLK48 | RCC_PERIPHCLK_SDMMC2;
/* Get the PLLI2S Clock configuration -----------------------------------------------*/
- PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN));
- PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ));
- PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR));
+ PeriphClkInit->PLLI2S.PLLI2SN = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
+ PeriphClkInit->PLLI2S.PLLI2SQ = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SQ) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos);
+ PeriphClkInit->PLLI2S.PLLI2SR = (uint32_t)((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> RCC_PLLI2SCFGR_PLLI2SR_Pos);
/* Get the PLLSAI Clock configuration -----------------------------------------------*/
- PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN));
- PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP));
- PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ));
+ PeriphClkInit->PLLSAI.PLLSAIN = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos);
+ PeriphClkInit->PLLSAI.PLLSAIP = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIP) >> RCC_PLLSAICFGR_PLLSAIP_Pos);
+ PeriphClkInit->PLLSAI.PLLSAIQ = (uint32_t)((RCC->PLLSAICFGR & RCC_PLLSAICFGR_PLLSAIQ) >> RCC_PLLSAICFGR_PLLSAIQ_Pos);
/* Get the PLLSAI/PLLI2S division factors -------------------------------------------*/
- PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) >> POSITION_VAL(RCC_DCKCFGR1_PLLI2SDIVQ));
- PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> POSITION_VAL(RCC_DCKCFGR1_PLLSAIDIVQ));
+ PeriphClkInit->PLLI2SDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLI2SDIVQ) >> RCC_DCKCFGR1_PLLI2SDIVQ_Pos);
+ PeriphClkInit->PLLSAIDivQ = (uint32_t)((RCC->DCKCFGR1 & RCC_DCKCFGR1_PLLSAIDIVQ) >> RCC_DCKCFGR1_PLLSAIDIVQ_Pos);
/* Get the SAI1 clock configuration ----------------------------------------------*/
PeriphClkInit->Sai1ClockSelection = __HAL_RCC_GET_SAI1_SOURCE();
@@ -1397,7 +1391,7 @@
/**
* @brief Return the peripheral clock frequency for a given peripheral(SAI..)
* @note Return 0 if peripheral clock identifier not managed by this API
- * @param PeriphClk: Peripheral clock identifier
+ * @param PeriphClk Peripheral clock identifier
* This parameter can be one of the following values:
* @arg RCC_PERIPHCLK_SAI1: SAI1 peripheral clock
* @arg RCC_PERIPHCLK_SAI2: SAI2 peripheral clock
@@ -1586,6 +1580,201 @@
* @}
*/
+/** @defgroup RCCEx_Exported_Functions_Group2 Extended Clock management functions
+ * @brief Extended Clock management functions
+ *
+@verbatim
+ ===============================================================================
+ ##### Extended clock management functions #####
+ ===============================================================================
+ [..]
+ This subsection provides a set of functions allowing to control the
+ activation or deactivation of PLLI2S, PLLSAI.
+@endverbatim
+ * @{
+ */
+
+/**
+ * @brief Enable PLLI2S.
+ * @param PLLI2SInit pointer to an RCC_PLLI2SInitTypeDef structure that
+ * contains the configuration information for the PLLI2S
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit)
+{
+ uint32_t tickstart;
+
+ /* Check for parameters */
+ assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SInit->PLLI2SN));
+ assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SInit->PLLI2SR));
+ assert_param(IS_RCC_PLLI2SQ_VALUE(PLLI2SInit->PLLI2SQ));
+#if defined(RCC_PLLI2SCFGR_PLLI2SP)
+ assert_param(IS_RCC_PLLI2SP_VALUE(PLLI2SInit->PLLI2SP));
+#endif /* RCC_PLLI2SCFGR_PLLI2SP */
+
+ /* Disable the PLLI2S */
+ __HAL_RCC_PLLI2S_DISABLE();
+
+ /* Wait till PLLI2S is disabled */
+ tickstart = HAL_GetTick();
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+ {
+ /* return in case of Timeout detected */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Configure the PLLI2S division factors */
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx)
+ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * PLLI2SN */
+ /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */
+ /* I2SRCLK = PLLI2S_VCO / PLLI2SR */
+ __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR);
+#else
+ /* PLLI2S_VCO = f(VCO clock) = f(PLLI2S clock input) * PLLI2SN */
+ /* I2SPCLK = PLLI2S_VCO / PLLI2SP */
+ /* I2SQCLK = PLLI2S_VCO / PLLI2SQ */
+ /* I2SRCLK = PLLI2S_VCO / PLLI2SR */
+ __HAL_RCC_PLLI2S_CONFIG(PLLI2SInit->PLLI2SN, PLLI2SInit->PLLI2SP, PLLI2SInit->PLLI2SQ, PLLI2SInit->PLLI2SR);
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx */
+
+ /* Enable the PLLI2S */
+ __HAL_RCC_PLLI2S_ENABLE();
+
+ /* Wait till PLLI2S is ready */
+ tickstart = HAL_GetTick();
+ while(__HAL_RCC_GET_FLAG(RCC_FLAG_PLLI2SRDY) == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLLI2S_TIMEOUT_VALUE)
+ {
+ /* return in case of Timeout detected */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable PLLI2S.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void)
+{
+ uint32_t tickstart;
+
+ /* Disable the PLLI2S */
+ __HAL_RCC_PLLI2S_DISABLE();
+
+ /* Wait till PLLI2S is disabled */
+ tickstart = HAL_GetTick();
+ while(READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) != RESET)
+ {
+ if((HAL_GetTick() - tickstart) > PLLI2S_TIMEOUT_VALUE)
+ {
+ /* return in case of Timeout detected */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Enable PLLSAI.
+ * @param PLLSAIInit pointer to an RCC_PLLSAIInitTypeDef structure that
+ * contains the configuration information for the PLLSAI
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit)
+{
+ uint32_t tickstart;
+
+ /* Check for parameters */
+ assert_param(IS_RCC_PLLSAIN_VALUE(PLLSAIInit->PLLSAIN));
+ assert_param(IS_RCC_PLLSAIQ_VALUE(PLLSAIInit->PLLSAIQ));
+ assert_param(IS_RCC_PLLSAIP_VALUE(PLLSAIInit->PLLSAIP));
+#if defined(RCC_PLLSAICFGR_PLLSAIR)
+ assert_param(IS_RCC_PLLSAIR_VALUE(PLLSAIInit->PLLSAIR));
+#endif /* RCC_PLLSAICFGR_PLLSAIR */
+
+ /* Disable the PLLSAI */
+ __HAL_RCC_PLLSAI_DISABLE();
+
+ /* Wait till PLLSAI is disabled */
+ tickstart = HAL_GetTick();
+ while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
+ {
+ /* return in case of Timeout detected */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ /* Configure the PLLSAI division factors */
+#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx)
+ /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * PLLSAIN */
+ /* SAIPCLK = PLLSAI_VCO / PLLSAIP */
+ /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */
+ __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIP, PLLSAIInit->PLLSAIQ);
+#else
+ /* PLLSAI_VCO = f(VCO clock) = f(PLLSAI clock input) * PLLSAIN */
+ /* SAIPCLK = PLLSAI_VCO / PLLSAIP */
+ /* SAIQCLK = PLLSAI_VCO / PLLSAIQ */
+ /* SAIRCLK = PLLSAI_VCO / PLLSAIR */
+ __HAL_RCC_PLLSAI_CONFIG(PLLSAIInit->PLLSAIN, PLLSAIInit->PLLSAIP, \
+ PLLSAIInit->PLLSAIQ, PLLSAIInit->PLLSAIR);
+#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx */
+
+ /* Enable the PLLSAI */
+ __HAL_RCC_PLLSAI_ENABLE();
+
+ /* Wait till PLLSAI is ready */
+ tickstart = HAL_GetTick();
+ while(__HAL_RCC_PLLSAI_GET_FLAG() == RESET)
+ {
+ if((HAL_GetTick() - tickstart ) > PLLSAI_TIMEOUT_VALUE)
+ {
+ /* return in case of Timeout detected */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @brief Disable PLLSAI.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void)
+{
+ uint32_t tickstart;
+
+ /* Disable the PLLSAI */
+ __HAL_RCC_PLLSAI_DISABLE();
+
+ /* Wait till PLLSAI is disabled */
+ tickstart = HAL_GetTick();
+ while(__HAL_RCC_PLLSAI_GET_FLAG() != RESET)
+ {
+ if((HAL_GetTick() - tickstart) > PLLSAI_TIMEOUT_VALUE)
+ {
+ /* return in case of Timeout detected */
+ return HAL_TIMEOUT;
+ }
+ }
+
+ return HAL_OK;
+}
+
+/**
+ * @}
+ */
+
/**
* @}
*/
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rcc_ex.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rcc_ex.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_rcc_ex.h
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief Header file of RCC HAL Extension module.
******************************************************************************
* @attention
@@ -2511,61 +2509,61 @@
#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
* @note This function must be used only when the main PLL is disabled.
- * @param __RCC_PLLSource__: specifies the PLL entry clock source.
+ * @param __RCC_PLLSource__ specifies the PLL entry clock source.
* This parameter can be one of the following values:
* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
* @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
- * @param __PLLM__: specifies the division factor for PLL VCO input clock
+ * @param __PLLM__ specifies the division factor for PLL VCO input clock
* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
* @note You have to set the PLLM parameter correctly to ensure that the VCO input
* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
* of 2 MHz to limit PLL jitter.
- * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
+ * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock
* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
* @note You have to set the PLLN parameter correctly to ensure that the VCO
* output frequency is between 100 and 432 MHz.
- * @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
+ * @param __PLLP__ specifies the division factor for main system clock (SYSCLK)
* This parameter must be a number in the range {2, 4, 6, or 8}.
* @note You have to set the PLLP parameter correctly to not exceed 216 MHz on
* the System clock frequency.
- * @param __PLLQ__: specifies the division factor for OTG FS, SDMMC and RNG clocks
+ * @param __PLLQ__ specifies the division factor for OTG FS, SDMMC and RNG clocks
* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
* @note If the USB OTG FS is used in your application, you have to set the
* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
* the SDMMC and RNG need a frequency lower than or equal to 48 MHz to work
* correctly.
- * @param __PLLR__: specifies the division factor for DSI clock
+ * @param __PLLR__ specifies the division factor for DSI clock
* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
*/
#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__,__PLLR__) \
(RCC->PLLCFGR = ((__RCC_PLLSource__) | (__PLLM__) | \
- ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
- ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \
- ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ)) | \
- ((__PLLR__) << POSITION_VAL(RCC_PLLCFGR_PLLR))))
+ ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \
+ ((((__PLLP__) >> 1) -1) << RCC_PLLCFGR_PLLP_Pos) | \
+ ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos) | \
+ ((__PLLR__) << RCC_PLLCFGR_PLLR_Pos)))
#else
/** @brief Macro to configure the main PLL clock source, multiplication and division factors.
* @note This function must be used only when the main PLL is disabled.
- * @param __RCC_PLLSource__: specifies the PLL entry clock source.
+ * @param __RCC_PLLSource__ specifies the PLL entry clock source.
* This parameter can be one of the following values:
* @arg RCC_PLLSOURCE_HSI: HSI oscillator clock selected as PLL clock entry
* @arg RCC_PLLSOURCE_HSE: HSE oscillator clock selected as PLL clock entry
* @note This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.
- * @param __PLLM__: specifies the division factor for PLL VCO input clock
+ * @param __PLLM__ specifies the division factor for PLL VCO input clock
* This parameter must be a number between Min_Data = 2 and Max_Data = 63.
* @note You have to set the PLLM parameter correctly to ensure that the VCO input
* frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
* of 2 MHz to limit PLL jitter.
- * @param __PLLN__: specifies the multiplication factor for PLL VCO output clock
+ * @param __PLLN__ specifies the multiplication factor for PLL VCO output clock
* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
* @note You have to set the PLLN parameter correctly to ensure that the VCO
* output frequency is between 100 and 432 MHz.
- * @param __PLLP__: specifies the division factor for main system clock (SYSCLK)
+ * @param __PLLP__ specifies the division factor for main system clock (SYSCLK)
* This parameter must be a number in the range {2, 4, 6, or 8}.
* @note You have to set the PLLP parameter correctly to not exceed 216 MHz on
* the System clock frequency.
- * @param __PLLQ__: specifies the division factor for OTG FS, SDMMC and RNG clocks
+ * @param __PLLQ__ specifies the division factor for OTG FS, SDMMC and RNG clocks
* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
* @note If the USB OTG FS is used in your application, you have to set the
* PLLQ parameter correctly to have 48 MHz clock for the USB. However,
@@ -2574,14 +2572,14 @@
*/
#define __HAL_RCC_PLL_CONFIG(__RCC_PLLSource__, __PLLM__, __PLLN__, __PLLP__, __PLLQ__) \
(RCC->PLLCFGR = (0x20000000 | (__RCC_PLLSource__) | (__PLLM__)| \
- ((__PLLN__) << POSITION_VAL(RCC_PLLCFGR_PLLN)) | \
- ((((__PLLP__) >> 1) -1) << POSITION_VAL(RCC_PLLCFGR_PLLP)) | \
- ((__PLLQ__) << POSITION_VAL(RCC_PLLCFGR_PLLQ))))
+ ((__PLLN__) << RCC_PLLCFGR_PLLN_Pos) | \
+ ((((__PLLP__) >> 1) -1) << RCC_PLLCFGR_PLLP_Pos) | \
+ ((__PLLQ__) << RCC_PLLCFGR_PLLQ_Pos)))
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
/*---------------------------------------------------------------------------------------------*/
/** @brief Macro to configure the Timers clocks prescalers
- * @param __PRESC__ : specifies the Timers clocks prescalers selection
+ * @param __PRESC__ specifies the Timers clocks prescalers selection
* This parameter can be one of the following values:
* @arg RCC_TIMPRES_DESACTIVATED: The Timers kernels clocks prescaler is
* equal to HPRE if PPREx is corresponding to division by 1 or 2,
@@ -2607,88 +2605,88 @@
* @note This function must be used only when the PLLSAI is disabled.
* @note PLLSAI clock source is common with the main PLL (configured in
* RCC_PLLConfig function )
- * @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
+ * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock.
* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
- * @param __PLLSAIP__: specifies the division factor for USB, RNG, SDMMC clocks
- * This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider.
- * @param __PLLSAIQ__: specifies the division factor for SAI clock
+ * @param __PLLSAIP__ specifies the division factor for USB, RNG, SDMMC clocks
+ * This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider.
+ * @param __PLLSAIQ__ specifies the division factor for SAI clock
* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
*/
#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__) \
- (RCC->PLLSAICFGR = ((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) |\
- ((__PLLSAIP__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) |\
- ((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)))
+ (RCC->PLLSAICFGR = ((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) |\
+ ((__PLLSAIP__) << RCC_PLLSAICFGR_PLLSAIP_Pos) |\
+ ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos))
/** @brief Macro to configure the PLLI2S clock multiplication and division factors.
* @note This macro must be used only when the PLLI2S is disabled.
* @note PLLI2S clock source is common with the main PLL (configured in
* HAL_RCC_ClockConfig() API)
- * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
+ * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock.
* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
- * @param __PLLI2SQ__: specifies the division factor for SAI clock.
+ * @param __PLLI2SQ__ specifies the division factor for SAI clock.
* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
- * @param __PLLI2SR__: specifies the division factor for I2S clock
+ * @param __PLLI2SR__ specifies the division factor for I2S clock
* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
* on the I2S clock frequency.
*/
#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SQ__, __PLLI2SR__) \
- (RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\
- ((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)) |\
- ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)))
-#else
+ (RCC->PLLI2SCFGR = ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\
+ ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) |\
+ ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))
+#else
/** @brief Macro to configure the PLLSAI clock multiplication and division factors.
* @note This function must be used only when the PLLSAI is disabled.
* @note PLLSAI clock source is common with the main PLL (configured in
* RCC_PLLConfig function )
- * @param __PLLSAIN__: specifies the multiplication factor for PLLSAI VCO output clock.
+ * @param __PLLSAIN__ specifies the multiplication factor for PLLSAI VCO output clock.
* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
* @note You have to set the PLLSAIN parameter correctly to ensure that the VCO
* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
- * @param __PLLSAIP__: specifies the division factor for USB, RNG, SDMMC clocks
+ * @param __PLLSAIP__ specifies the division factor for USB, RNG, SDMMC clocks
* This parameter can be a value of @ref RCCEx_PLLSAIP_Clock_Divider.
- * @param __PLLSAIQ__: specifies the division factor for SAI clock
+ * @param __PLLSAIQ__ specifies the division factor for SAI clock
* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
- * @param __PLLSAIR__: specifies the division factor for LTDC clock
+ * @param __PLLSAIR__ specifies the division factor for LTDC clock
* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
*/
#define __HAL_RCC_PLLSAI_CONFIG(__PLLSAIN__, __PLLSAIP__, __PLLSAIQ__, __PLLSAIR__) \
- (RCC->PLLSAICFGR = ((__PLLSAIN__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIN)) |\
- ((__PLLSAIP__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIP)) |\
- ((__PLLSAIQ__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIQ)) |\
- ((__PLLSAIR__) << POSITION_VAL(RCC_PLLSAICFGR_PLLSAIR)))
+ (RCC->PLLSAICFGR = ((__PLLSAIN__) << RCC_PLLSAICFGR_PLLSAIN_Pos) |\
+ ((__PLLSAIP__) << RCC_PLLSAICFGR_PLLSAIP_Pos) |\
+ ((__PLLSAIQ__) << RCC_PLLSAICFGR_PLLSAIQ_Pos) |\
+ ((__PLLSAIR__) << RCC_PLLSAICFGR_PLLSAIR_Pos))
/** @brief Macro to configure the PLLI2S clock multiplication and division factors.
* @note This macro must be used only when the PLLI2S is disabled.
* @note PLLI2S clock source is common with the main PLL (configured in
* HAL_RCC_ClockConfig() API)
- * @param __PLLI2SN__: specifies the multiplication factor for PLLI2S VCO output clock.
+ * @param __PLLI2SN__ specifies the multiplication factor for PLLI2S VCO output clock.
* This parameter must be a number between Min_Data = 50 and Max_Data = 432.
* @note You have to set the PLLI2SN parameter correctly to ensure that the VCO
* output frequency is between Min_Data = 100 and Max_Data = 432 MHz.
- * @param __PLLI2SP__: specifies the division factor for SPDDIF-RX clock.
+ * @param __PLLI2SP__ specifies the division factor for SPDDIF-RX clock.
* This parameter can be a value of @ref RCCEx_PLLI2SP_Clock_Divider.
- * @param __PLLI2SQ__: specifies the division factor for SAI clock.
+ * @param __PLLI2SQ__ specifies the division factor for SAI clock.
* This parameter must be a number between Min_Data = 2 and Max_Data = 15.
- * @param __PLLI2SR__: specifies the division factor for I2S clock
+ * @param __PLLI2SR__ specifies the division factor for I2S clock
* This parameter must be a number between Min_Data = 2 and Max_Data = 7.
* @note You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
* on the I2S clock frequency.
*/
#define __HAL_RCC_PLLI2S_CONFIG(__PLLI2SN__, __PLLI2SP__, __PLLI2SQ__, __PLLI2SR__) \
- (RCC->PLLI2SCFGR = ((__PLLI2SN__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SN)) |\
- ((__PLLI2SP__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SP)) |\
- ((__PLLI2SQ__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SQ)) |\
- ((__PLLI2SR__) << POSITION_VAL(RCC_PLLI2SCFGR_PLLI2SR)))
+ (RCC->PLLI2SCFGR = ((__PLLI2SN__) << RCC_PLLI2SCFGR_PLLI2SN_Pos) |\
+ ((__PLLI2SP__) << RCC_PLLI2SCFGR_PLLI2SP_Pos) |\
+ ((__PLLI2SQ__) << RCC_PLLI2SCFGR_PLLI2SQ_Pos) |\
+ ((__PLLI2SR__) << RCC_PLLI2SCFGR_PLLI2SR_Pos))
#endif /* STM32F722xx || STM32F723xx || STM32F732xx || STM32F733xx */
/** @brief Macro to configure the SAI clock Divider coming from PLLI2S.
* @note This function must be called before enabling the PLLI2S.
- * @param __PLLI2SDivQ__: specifies the PLLI2S division factor for SAI1 clock .
+ * @param __PLLI2SDivQ__ specifies the PLLI2S division factor for SAI1 clock .
* This parameter must be a number between 1 and 32.
* SAI1 clock frequency = f(PLLI2SQ) / __PLLI2SDivQ__
*/
@@ -2696,7 +2694,7 @@
/** @brief Macro to configure the SAI clock Divider coming from PLLSAI.
* @note This function must be called before enabling the PLLSAI.
- * @param __PLLSAIDivQ__: specifies the PLLSAI division factor for SAI1 clock .
+ * @param __PLLSAIDivQ__ specifies the PLLSAI division factor for SAI1 clock .
* This parameter must be a number between Min_Data = 1 and Max_Data = 32.
* SAI1 clock frequency = f(PLLSAIQ) / __PLLSAIDivQ__
*/
@@ -2706,7 +2704,7 @@
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
/** @brief Macro to configure the LTDC clock Divider coming from PLLSAI.
* @note This function must be called before enabling the PLLSAI.
- * @param __PLLSAIDivR__: specifies the PLLSAI division factor for LTDC clock .
+ * @param __PLLSAIDivR__ specifies the PLLSAI division factor for LTDC clock .
* This parameter can be a value of @ref RCCEx_PLLSAI_DIVR.
* LTDC clock frequency = f(PLLSAIR) / __PLLSAIDivR__
*/
@@ -2717,7 +2715,7 @@
/** @brief Macro to configure SAI1 clock source selection.
* @note This function must be called before enabling PLLSAI, PLLI2S and
* the SAI clock.
- * @param __SOURCE__: specifies the SAI1 clock source.
+ * @param __SOURCE__ specifies the SAI1 clock source.
* This parameter can be one of the following values:
* @arg RCC_SAI1CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
* as SAI1 clock.
@@ -2750,7 +2748,7 @@
/** @brief Macro to configure SAI2 clock source selection.
* @note This function must be called before enabling PLLSAI, PLLI2S and
* the SAI clock.
- * @param __SOURCE__: specifies the SAI2 clock source.
+ * @param __SOURCE__ specifies the SAI2 clock source.
* This parameter can be one of the following values:
* @arg RCC_SAI2CLKSOURCE_PLLI2S: PLLI2S_Q clock divided by PLLI2SDIVQ used
* as SAI2 clock.
@@ -2812,7 +2810,7 @@
/** @brief Macro to configure the I2C1 clock (I2C1CLK).
*
- * @param __I2C1_CLKSOURCE__: specifies the I2C1 clock source.
+ * @param __I2C1_CLKSOURCE__ specifies the I2C1 clock source.
* This parameter can be one of the following values:
* @arg RCC_I2C1CLKSOURCE_PCLK1: PCLK1 selected as I2C1 clock
* @arg RCC_I2C1CLKSOURCE_HSI: HSI selected as I2C1 clock
@@ -2831,7 +2829,7 @@
/** @brief Macro to configure the I2C2 clock (I2C2CLK).
*
- * @param __I2C2_CLKSOURCE__: specifies the I2C2 clock source.
+ * @param __I2C2_CLKSOURCE__ specifies the I2C2 clock source.
* This parameter can be one of the following values:
* @arg RCC_I2C2CLKSOURCE_PCLK1: PCLK1 selected as I2C2 clock
* @arg RCC_I2C2CLKSOURCE_HSI: HSI selected as I2C2 clock
@@ -2850,7 +2848,7 @@
/** @brief Macro to configure the I2C3 clock (I2C3CLK).
*
- * @param __I2C3_CLKSOURCE__: specifies the I2C3 clock source.
+ * @param __I2C3_CLKSOURCE__ specifies the I2C3 clock source.
* This parameter can be one of the following values:
* @arg RCC_I2C3CLKSOURCE_PCLK1: PCLK1 selected as I2C3 clock
* @arg RCC_I2C3CLKSOURCE_HSI: HSI selected as I2C3 clock
@@ -2869,7 +2867,7 @@
/** @brief Macro to configure the I2C4 clock (I2C4CLK).
*
- * @param __I2C4_CLKSOURCE__: specifies the I2C4 clock source.
+ * @param __I2C4_CLKSOURCE__ specifies the I2C4 clock source.
* This parameter can be one of the following values:
* @arg RCC_I2C4CLKSOURCE_PCLK1: PCLK1 selected as I2C4 clock
* @arg RCC_I2C4CLKSOURCE_HSI: HSI selected as I2C4 clock
@@ -2888,7 +2886,7 @@
/** @brief Macro to configure the USART1 clock (USART1CLK).
*
- * @param __USART1_CLKSOURCE__: specifies the USART1 clock source.
+ * @param __USART1_CLKSOURCE__ specifies the USART1 clock source.
* This parameter can be one of the following values:
* @arg RCC_USART1CLKSOURCE_PCLK2: PCLK2 selected as USART1 clock
* @arg RCC_USART1CLKSOURCE_HSI: HSI selected as USART1 clock
@@ -2909,7 +2907,7 @@
/** @brief Macro to configure the USART2 clock (USART2CLK).
*
- * @param __USART2_CLKSOURCE__: specifies the USART2 clock source.
+ * @param __USART2_CLKSOURCE__ specifies the USART2 clock source.
* This parameter can be one of the following values:
* @arg RCC_USART2CLKSOURCE_PCLK1: PCLK1 selected as USART2 clock
* @arg RCC_USART2CLKSOURCE_HSI: HSI selected as USART2 clock
@@ -2930,7 +2928,7 @@
/** @brief Macro to configure the USART3 clock (USART3CLK).
*
- * @param __USART3_CLKSOURCE__: specifies the USART3 clock source.
+ * @param __USART3_CLKSOURCE__ specifies the USART3 clock source.
* This parameter can be one of the following values:
* @arg RCC_USART3CLKSOURCE_PCLK1: PCLK1 selected as USART3 clock
* @arg RCC_USART3CLKSOURCE_HSI: HSI selected as USART3 clock
@@ -2951,7 +2949,7 @@
/** @brief Macro to configure the UART4 clock (UART4CLK).
*
- * @param __UART4_CLKSOURCE__: specifies the UART4 clock source.
+ * @param __UART4_CLKSOURCE__ specifies the UART4 clock source.
* This parameter can be one of the following values:
* @arg RCC_UART4CLKSOURCE_PCLK1: PCLK1 selected as UART4 clock
* @arg RCC_UART4CLKSOURCE_HSI: HSI selected as UART4 clock
@@ -2972,7 +2970,7 @@
/** @brief Macro to configure the UART5 clock (UART5CLK).
*
- * @param __UART5_CLKSOURCE__: specifies the UART5 clock source.
+ * @param __UART5_CLKSOURCE__ specifies the UART5 clock source.
* This parameter can be one of the following values:
* @arg RCC_UART5CLKSOURCE_PCLK1: PCLK1 selected as UART5 clock
* @arg RCC_UART5CLKSOURCE_HSI: HSI selected as UART5 clock
@@ -2993,7 +2991,7 @@
/** @brief Macro to configure the USART6 clock (USART6CLK).
*
- * @param __USART6_CLKSOURCE__: specifies the USART6 clock source.
+ * @param __USART6_CLKSOURCE__ specifies the USART6 clock source.
* This parameter can be one of the following values:
* @arg RCC_USART6CLKSOURCE_PCLK1: PCLK1 selected as USART6 clock
* @arg RCC_USART6CLKSOURCE_HSI: HSI selected as USART6 clock
@@ -3014,7 +3012,7 @@
/** @brief Macro to configure the UART7 clock (UART7CLK).
*
- * @param __UART7_CLKSOURCE__: specifies the UART7 clock source.
+ * @param __UART7_CLKSOURCE__ specifies the UART7 clock source.
* This parameter can be one of the following values:
* @arg RCC_UART7CLKSOURCE_PCLK1: PCLK1 selected as UART7 clock
* @arg RCC_UART7CLKSOURCE_HSI: HSI selected as UART7 clock
@@ -3035,7 +3033,7 @@
/** @brief Macro to configure the UART8 clock (UART8CLK).
*
- * @param __UART8_CLKSOURCE__: specifies the UART8 clock source.
+ * @param __UART8_CLKSOURCE__ specifies the UART8 clock source.
* This parameter can be one of the following values:
* @arg RCC_UART8CLKSOURCE_PCLK1: PCLK1 selected as UART8 clock
* @arg RCC_UART8CLKSOURCE_HSI: HSI selected as UART8 clock
@@ -3056,7 +3054,7 @@
/** @brief Macro to configure the LPTIM1 clock (LPTIM1CLK).
*
- * @param __LPTIM1_CLKSOURCE__: specifies the LPTIM1 clock source.
+ * @param __LPTIM1_CLKSOURCE__ specifies the LPTIM1 clock source.
* This parameter can be one of the following values:
* @arg RCC_LPTIM1CLKSOURCE_PCLK1: PCLK selected as LPTIM1 clock
* @arg RCC_LPTIM1CLKSOURCE_HSI: HSI selected as LPTIM1 clock
@@ -3077,7 +3075,7 @@
/** @brief Macro to configure the CEC clock (CECCLK).
*
- * @param __CEC_CLKSOURCE__: specifies the CEC clock source.
+ * @param __CEC_CLKSOURCE__ specifies the CEC clock source.
* This parameter can be one of the following values:
* @arg RCC_CECCLKSOURCE_LSE: LSE selected as CEC clock
* @arg RCC_CECCLKSOURCE_HSI: HSI divided by 488 selected as CEC clock
@@ -3094,7 +3092,7 @@
/** @brief Macro to configure the CLK48 source (CLK48CLK).
*
- * @param __CLK48_SOURCE__: specifies the CLK48 clock source.
+ * @param __CLK48_SOURCE__ specifies the CLK48 clock source.
* This parameter can be one of the following values:
* @arg RCC_CLK48SOURCE_PLL: PLL selected as CLK48 source
* @arg RCC_CLK48SOURCE_PLLSAIP: PLLSAIP selected as CLK48 source
@@ -3111,7 +3109,7 @@
/** @brief Macro to configure the SDMMC1 clock (SDMMC1CLK).
*
- * @param __SDMMC1_CLKSOURCE__: specifies the SDMMC1 clock source.
+ * @param __SDMMC1_CLKSOURCE__ specifies the SDMMC1 clock source.
* This parameter can be one of the following values:
* @arg RCC_SDMMC1CLKSOURCE_CLK48: CLK48 selected as SDMMC clock
* @arg RCC_SDMMC1CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC clock
@@ -3129,7 +3127,7 @@
#if defined (STM32F722xx) || defined (STM32F723xx) || defined (STM32F732xx) || defined (STM32F733xx) || defined (STM32F765xx) ||\
defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
/** @brief Macro to configure the SDMMC2 clock (SDMMC2CLK).
- * @param __SDMMC2_CLKSOURCE__: specifies the SDMMC2 clock source.
+ * @param __SDMMC2_CLKSOURCE__ specifies the SDMMC2 clock source.
* This parameter can be one of the following values:
* @arg RCC_SDMMC2CLKSOURCE_CLK48: CLK48 selected as SDMMC2 clock
* @arg RCC_SDMMC2CLKSOURCE_SYSCLK: SYSCLK selected as SDMMC2 clock
@@ -3147,7 +3145,7 @@
#if defined (STM32F765xx) || defined (STM32F767xx) || defined (STM32F769xx) || defined (STM32F777xx) || defined (STM32F779xx)
/** @brief Macro to configure the DFSDM1 clock
- * @param __DFSDM1_CLKSOURCE__: specifies the DFSDM1 clock source.
+ * @param __DFSDM1_CLKSOURCE__ specifies the DFSDM1 clock source.
* This parameter can be one of the following values:
* @arg RCC_DFSDM1CLKSOURCE_PCLK2: PCLK2 Clock selected as DFSDM clock
* @arg RCC_DFSDMCLKSOURCE_SYSCLK: System Clock selected as DFSDM clock
@@ -3163,7 +3161,7 @@
#define __HAL_RCC_GET_DFSDM1_SOURCE() ((uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL)))
/** @brief Macro to configure the DFSDM1 Audio clock
- * @param __DFSDM1AUDIO_CLKSOURCE__: specifies the DFSDM1 Audio clock source.
+ * @param __DFSDM1AUDIO_CLKSOURCE__ specifies the DFSDM1 Audio clock source.
* This parameter can be one of the following values:
* @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI1: SAI1 Clock selected as DFSDM1 Audio clock
* @arg RCC_DFSDM1AUDIOCLKSOURCE_SAI2: SAI2 Clock selected as DFSDM1 Audio clock
@@ -3181,7 +3179,7 @@
#if defined (STM32F769xx) || defined (STM32F779xx)
/** @brief Macro to configure the DSI clock.
- * @param __DSI_CLKSOURCE__: specifies the DSI clock source.
+ * @param __DSI_CLKSOURCE__ specifies the DSI clock source.
* This parameter can be one of the following values:
* @arg RCC_DSICLKSOURCE_PLLR: PLLR output used as DSI clock.
* @arg RCC_DSICLKSOURCE_DSIPHY: DSI-PHY output used as DSI clock.
@@ -3206,7 +3204,10 @@
HAL_StatusTypeDef HAL_RCCEx_PeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
void HAL_RCCEx_GetPeriphCLKConfig(RCC_PeriphCLKInitTypeDef *PeriphClkInit);
uint32_t HAL_RCCEx_GetPeriphCLKFreq(uint32_t PeriphClk);
-
+HAL_StatusTypeDef HAL_RCCEx_EnablePLLI2S(RCC_PLLI2SInitTypeDef *PLLI2SInit);
+HAL_StatusTypeDef HAL_RCCEx_DisablePLLI2S(void);
+HAL_StatusTypeDef HAL_RCCEx_EnablePLLSAI(RCC_PLLSAIInitTypeDef *PLLSAIInit);
+HAL_StatusTypeDef HAL_RCCEx_DisablePLLSAI(void);
/**
* @}
*/
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rng.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rng.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_rng.c
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief RNG HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Random Number Generator (RNG) peripheral:
@@ -76,7 +74,7 @@
/** @addtogroup RNG_Private_Constants
* @{
*/
-#define RNG_TIMEOUT_VALUE 2
+#define RNG_TIMEOUT_VALUE 2U
/**
* @}
*/
@@ -109,7 +107,7 @@
/**
* @brief Initializes the RNG peripheral and creates the associated handle.
- * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval HAL status
*/
@@ -120,14 +118,11 @@
{
return HAL_ERROR;
}
-
- __HAL_LOCK(hrng);
-
+
if(hrng->State == HAL_RNG_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hrng->Lock = HAL_UNLOCKED;
-
/* Init the low level hardware */
HAL_RNG_MspInit(hrng);
}
@@ -140,16 +135,14 @@
/* Initialize the RNG state */
hrng->State = HAL_RNG_STATE_READY;
-
- __HAL_UNLOCK(hrng);
-
+
/* Return function status */
return HAL_OK;
}
/**
* @brief DeInitializes the RNG peripheral.
- * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval HAL status
*/
@@ -181,7 +174,7 @@
/**
* @brief Initializes the RNG MSP.
- * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval None
*/
@@ -189,7 +182,6 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hrng);
-
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_RNG_MspInit must be implemented in the user file.
*/
@@ -197,7 +189,7 @@
/**
* @brief DeInitializes the RNG MSP.
- * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval None
*/
@@ -205,7 +197,6 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hrng);
-
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_RNG_MspDeInit must be implemented in the user file.
*/
@@ -235,15 +226,15 @@
* @brief Generates a 32-bit random number.
* @note Each time the random number data is read the RNG_FLAG_DRDY flag
* is automatically cleared.
- * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
- * @param random32bit: pointer to generated random number variable if successful.
+ * @param random32bit pointer to generated random number variable if successful.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RNG_GenerateRandomNumber(RNG_HandleTypeDef *hrng, uint32_t *random32bit)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart = 0U;
HAL_StatusTypeDef status = HAL_OK;
/* Process Locked */
@@ -291,7 +282,7 @@
/**
* @brief Generates a 32-bit random number in interrupt mode.
- * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval HAL status
*/
@@ -341,7 +332,7 @@
* the RNG peripheral to reinitialize and restart the RNG.
* @note User-written HAL_RNG_ErrorCallback() API is called once whether SEIS
* or CEIS are set.
- * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval None
@@ -384,7 +375,7 @@
/**
* @brief Returns generated random number in polling mode (Obsolete)
* Use HAL_RNG_GenerateRandomNumber() API instead.
- * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval Random value
*/
@@ -396,20 +387,20 @@
}
else
{
- return 0;
+ return 0U;
}
}
/**
* @brief Returns a 32-bit random number with interrupt enabled (Obsolete),
* Use HAL_RNG_GenerateRandomNumber_IT() API instead.
- * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval 32-bit random number
*/
uint32_t HAL_RNG_GetRandomNumber_IT(RNG_HandleTypeDef *hrng)
{
- uint32_t random32bit = 0;
+ uint32_t random32bit = 0U;
/* Process locked */
__HAL_LOCK(hrng);
@@ -429,7 +420,7 @@
/**
* @brief Read latest generated random number.
- * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval random value
*/
@@ -440,16 +431,16 @@
/**
* @brief Data Ready callback in non-blocking mode.
- * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
- * @param random32bit: generated random number.
+ * @param random32bit generated random number.
* @retval None
*/
__weak void HAL_RNG_ReadyDataCallback(RNG_HandleTypeDef *hrng, uint32_t random32bit)
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hrng);
-
+ UNUSED(random32bit);
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_RNG_ReadyDataCallback must be implemented in the user file.
*/
@@ -457,7 +448,7 @@
/**
* @brief RNG error callbacks.
- * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval None
*/
@@ -465,7 +456,6 @@
{
/* Prevent unused argument(s) compilation warning */
UNUSED(hrng);
-
/* NOTE : This function should not be modified. When the callback is needed,
function HAL_RNG_ErrorCallback must be implemented in the user file.
*/
@@ -492,7 +482,7 @@
/**
* @brief Returns the RNG state.
- * @param hrng: pointer to a RNG_HandleTypeDef structure that contains
+ * @param hrng pointer to a RNG_HandleTypeDef structure that contains
* the configuration information for RNG.
* @retval HAL state
*/
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rng.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rng.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_rng.h
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief Header file of RNG HAL module.
******************************************************************************
* @attention
@@ -139,29 +137,29 @@
*/
/** @brief Reset RNG handle state
- * @param __HANDLE__: RNG Handle
+ * @param __HANDLE__ RNG Handle
* @retval None
*/
#define __HAL_RNG_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RNG_STATE_RESET)
/**
* @brief Enables the RNG peripheral.
- * @param __HANDLE__: RNG Handle
+ * @param __HANDLE__ RNG Handle
* @retval None
*/
#define __HAL_RNG_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_RNGEN)
/**
* @brief Disables the RNG peripheral.
- * @param __HANDLE__: RNG Handle
+ * @param __HANDLE__ RNG Handle
* @retval None
*/
#define __HAL_RNG_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_RNGEN)
/**
* @brief Check the selected RNG flag status.
- * @param __HANDLE__: RNG Handle
- * @param __FLAG__: RNG flag
+ * @param __HANDLE__ RNG Handle
+ * @param __FLAG__ RNG flag
* This parameter can be one of the following values:
* @arg RNG_FLAG_DRDY: Data ready
* @arg RNG_FLAG_CECS: Clock error current status
@@ -172,8 +170,8 @@
/**
* @brief Clears the selected RNG flag status.
- * @param __HANDLE__: RNG handle
- * @param __FLAG__: RNG flag to clear
+ * @param __HANDLE__ RNG handle
+ * @param __FLAG__ RNG flag to clear
* @note WARNING: This is a dummy macro for HAL code alignment,
* flags RNG_FLAG_DRDY, RNG_FLAG_CECS and RNG_FLAG_SECS are read-only.
* @retval None
@@ -184,22 +182,22 @@
/**
* @brief Enables the RNG interrupts.
- * @param __HANDLE__: RNG Handle
+ * @param __HANDLE__ RNG Handle
* @retval None
*/
#define __HAL_RNG_ENABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR |= RNG_CR_IE)
/**
* @brief Disables the RNG interrupts.
- * @param __HANDLE__: RNG Handle
+ * @param __HANDLE__ RNG Handle
* @retval None
*/
#define __HAL_RNG_DISABLE_IT(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~RNG_CR_IE)
/**
* @brief Checks whether the specified RNG interrupt has occurred or not.
- * @param __HANDLE__: RNG Handle
- * @param __INTERRUPT__: specifies the RNG interrupt status flag to check.
+ * @param __HANDLE__ RNG Handle
+ * @param __INTERRUPT__ specifies the RNG interrupt status flag to check.
* This parameter can be one of the following values:
* @arg RNG_IT_DRDY: Data ready interrupt
* @arg RNG_IT_CEI: Clock error interrupt
@@ -210,8 +208,8 @@
/**
* @brief Clear the RNG interrupt status flags.
- * @param __HANDLE__: RNG Handle
- * @param __INTERRUPT__: specifies the RNG interrupt status flag to clear.
+ * @param __HANDLE__ RNG Handle
+ * @param __INTERRUPT__ specifies the RNG interrupt status flag to clear.
* This parameter can be one of the following values:
* @arg RNG_IT_CEI: Clock error interrupt
* @arg RNG_IT_SEI: Seed error interrupt
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rtc.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rtc.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_rtc.c
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief RTC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Real Time Clock (RTC) peripheral:
@@ -197,7 +195,7 @@
/**
* @brief Initializes the RTC peripheral
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval HAL status
*/
@@ -272,7 +270,7 @@
/**
* @brief DeInitializes the RTC peripheral
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @note This function doesn't reset the RTC Backup Data registers.
* @retval HAL status
@@ -378,7 +376,7 @@
/**
* @brief Initializes the RTC MSP.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval None
*/
@@ -394,7 +392,7 @@
/**
* @brief DeInitializes the RTC MSP.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval None
*/
@@ -428,10 +426,10 @@
/**
* @brief Sets RTC current time.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
- * @param sTime: Pointer to Time structure
- * @param Format: Specifies the format of the entered parameters.
+ * @param sTime Pointer to Time structure
+ * @param Format Specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg FORMAT_BIN: Binary data format
* @arg FORMAT_BCD: BCD data format
@@ -553,12 +551,12 @@
/**
* @brief Gets RTC current time.
- * @param hrtc: RTC handle
- * @param sTime: Pointer to Time structure with Hours, Minutes and Seconds fields returned
+ * @param hrtc RTC handle
+ * @param sTime Pointer to Time structure with Hours, Minutes and Seconds fields returned
* with input format (BIN or BCD), also SubSeconds field returning the
* RTC_SSR register content and SecondFraction field the Synchronous pre-scaler
* factor to be used for second fraction ratio computation.
- * @param Format: Specifies the format of the entered parameters.
+ * @param Format Specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg RTC_FORMAT_BIN: Binary data format
* @arg RTC_FORMAT_BCD: BCD data format
@@ -608,10 +606,10 @@
/**
* @brief Sets RTC current date.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
- * @param sDate: Pointer to date structure
- * @param Format: specifies the format of the entered parameters.
+ * @param sDate Pointer to date structure
+ * @param Format specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg RTC_FORMAT_BIN: Binary data format
* @arg RTC_FORMAT_BCD: BCD data format
@@ -650,10 +648,8 @@
else
{
assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(sDate->Year)));
- datetmpreg = RTC_Bcd2ToByte(sDate->Month);
- assert_param(IS_RTC_MONTH(datetmpreg));
- datetmpreg = RTC_Bcd2ToByte(sDate->Date);
- assert_param(IS_RTC_DATE(datetmpreg));
+ assert_param(IS_RTC_MONTH(sDate->Month));
+ assert_param(IS_RTC_DATE(sDate->Date));
datetmpreg = ((((uint32_t)sDate->Year) << 16) | \
(((uint32_t)sDate->Month) << 8) | \
@@ -717,10 +713,10 @@
/**
* @brief Gets RTC current date.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
- * @param sDate: Pointer to Date structure
- * @param Format: Specifies the format of the entered parameters.
+ * @param sDate Pointer to Date structure
+ * @param Format Specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg RTC_FORMAT_BIN: Binary data format
* @arg RTC_FORMAT_BCD: BCD data format
@@ -775,10 +771,10 @@
*/
/**
* @brief Sets the specified RTC Alarm.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
- * @param sAlarm: Pointer to Alarm structure
- * @param Format: Specifies the format of the entered parameters.
+ * @param sAlarm Pointer to Alarm structure
+ * @param Format Specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg FORMAT_BIN: Binary data format
* @arg FORMAT_BCD: BCD data format
@@ -961,10 +957,10 @@
/**
* @brief Sets the specified RTC Alarm with Interrupt
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
- * @param sAlarm: Pointer to Alarm structure
- * @param Format: Specifies the format of the entered parameters.
+ * @param sAlarm Pointer to Alarm structure
+ * @param Format Specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg FORMAT_BIN: Binary data format
* @arg FORMAT_BCD: BCD data format
@@ -975,8 +971,8 @@
*/
HAL_StatusTypeDef HAL_RTC_SetAlarm_IT(RTC_HandleTypeDef *hrtc, RTC_AlarmTypeDef *sAlarm, uint32_t Format)
{
- uint32_t tickstart = 0;
- uint32_t tmpreg = 0, subsecondtmpreg = 0;
+ uint32_t tmpreg = 0U, subsecondtmpreg = 0U;
+ __IO uint32_t count = RTC_TIMEOUT_VALUE * (SystemCoreClock / 32U / 1000U) ;
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
@@ -1000,7 +996,7 @@
}
else
{
- sAlarm->AlarmTime.TimeFormat = 0x00;
+ sAlarm->AlarmTime.TimeFormat = 0x00U;
assert_param(IS_RTC_HOUR24(sAlarm->AlarmTime.Hours));
}
assert_param(IS_RTC_MINUTES(sAlarm->AlarmTime.Minutes));
@@ -1014,11 +1010,11 @@
{
assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(sAlarm->AlarmDateWeekDay));
}
- tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16) | \
- ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8) | \
+ tmpreg = (((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Hours) << 16U) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Minutes) << 8U) | \
((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmTime.Seconds)) | \
- ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
- ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24) | \
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
+ ((uint32_t)RTC_ByteToBcd2(sAlarm->AlarmDateWeekDay) << 24U) | \
((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
((uint32_t)sAlarm->AlarmMask));
}
@@ -1032,7 +1028,7 @@
}
else
{
- sAlarm->AlarmTime.TimeFormat = 0x00;
+ sAlarm->AlarmTime.TimeFormat = 0x00U;
assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(sAlarm->AlarmTime.Hours)));
}
@@ -1049,11 +1045,11 @@
tmpreg = RTC_Bcd2ToByte(sAlarm->AlarmDateWeekDay);
assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));
}
- tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16) | \
- ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8) | \
+ tmpreg = (((uint32_t)(sAlarm->AlarmTime.Hours) << 16U) | \
+ ((uint32_t)(sAlarm->AlarmTime.Minutes) << 8U) | \
((uint32_t) sAlarm->AlarmTime.Seconds) | \
- ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16) | \
- ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24) | \
+ ((uint32_t)(sAlarm->AlarmTime.TimeFormat) << 16U) | \
+ ((uint32_t)(sAlarm->AlarmDateWeekDay) << 24U) | \
((uint32_t)sAlarm->AlarmDateWeekDaySel) | \
((uint32_t)sAlarm->AlarmMask));
}
@@ -1072,26 +1068,24 @@
/* Clear flag alarm A */
__HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRAF);
- /* Get tick */
- tickstart = HAL_GetTick();
-
/* Wait till RTC ALRAWF flag is set and if Time out is reached exit */
- while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET)
+ do
{
- if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+ if (count-- == 0U)
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
- /* Process Unlocked */
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
__HAL_UNLOCK(hrtc);
-
+
return HAL_TIMEOUT;
- }
- }
-
+ }
+ }
+ while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRAWF) == RESET);
+
hrtc->Instance->ALRMAR = (uint32_t)tmpreg;
/* Configure the Alarm A Sub Second register */
hrtc->Instance->ALRMASSR = subsecondtmpreg;
@@ -1108,26 +1102,24 @@
/* Clear flag alarm B */
__HAL_RTC_ALARM_CLEAR_FLAG(hrtc, RTC_FLAG_ALRBF);
- /* Get tick */
- tickstart = HAL_GetTick();
-
/* Wait till RTC ALRBWF flag is set and if Time out is reached exit */
- while(__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET)
+ do
{
- if((HAL_GetTick() - tickstart ) > RTC_TIMEOUT_VALUE)
+ if (count-- == 0U)
{
/* Enable the write protection for RTC registers */
__HAL_RTC_WRITEPROTECTION_ENABLE(hrtc);
-
- hrtc->State = HAL_RTC_STATE_TIMEOUT;
-
- /* Process Unlocked */
+
+ hrtc->State = HAL_RTC_STATE_TIMEOUT;
+
+ /* Process Unlocked */
__HAL_UNLOCK(hrtc);
-
+
return HAL_TIMEOUT;
- }
- }
-
+ }
+ }
+ while (__HAL_RTC_ALARM_GET_FLAG(hrtc, RTC_FLAG_ALRBWF) == RESET);
+
hrtc->Instance->ALRMBR = (uint32_t)tmpreg;
/* Configure the Alarm B Sub Second register */
hrtc->Instance->ALRMBSSR = subsecondtmpreg;
@@ -1155,9 +1147,9 @@
/**
* @brief Deactive the specified RTC Alarm
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
- * @param Alarm: Specifies the Alarm.
+ * @param Alarm Specifies the Alarm.
* This parameter can be one of the following values:
* @arg RTC_ALARM_A: AlarmA
* @arg RTC_ALARM_B: AlarmB
@@ -1247,14 +1239,14 @@
/**
* @brief Gets the RTC Alarm value and masks.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
- * @param sAlarm: Pointer to Date structure
- * @param Alarm: Specifies the Alarm.
+ * @param sAlarm Pointer to Date structure
+ * @param Alarm Specifies the Alarm.
* This parameter can be one of the following values:
* @arg RTC_ALARM_A: AlarmA
* @arg RTC_ALARM_B: AlarmB
- * @param Format: Specifies the format of the entered parameters.
+ * @param Format Specifies the format of the entered parameters.
* This parameter can be one of the following values:
* @arg RTC_FORMAT_BIN: Binary data format
* @arg RTC_FORMAT_BCD: BCD data format
@@ -1307,7 +1299,7 @@
/**
* @brief This function handles Alarm interrupt request.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval None
*/
@@ -1348,7 +1340,7 @@
/**
* @brief Alarm A callback.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval None
*/
@@ -1364,9 +1356,9 @@
/**
* @brief This function handles AlarmA Polling request.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
- * @param Timeout: Timeout duration
+ * @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTC_PollForAlarmAEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
@@ -1427,7 +1419,7 @@
* The software must then wait until it is set again before reading
* the calendar, which means that the calendar registers have been
* correctly copied into the RTC_TR and RTC_DR shadow registers.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval HAL status
*/
@@ -1473,7 +1465,7 @@
*/
/**
* @brief Returns the RTC state.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval HAL state
*/
@@ -1490,7 +1482,7 @@
* @brief Enters the RTC Initialization mode.
* @note The RTC Initialization mode is write protected, use the
* __HAL_RTC_WRITEPROTECTION_DISABLE() before calling this function.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval HAL status
*/
@@ -1523,7 +1515,7 @@
/**
* @brief Converts a 2 digit decimal to BCD format.
- * @param Value: Byte to be converted
+ * @param Value Byte to be converted
* @retval Converted byte
*/
uint8_t RTC_ByteToBcd2(uint8_t Value)
@@ -1541,7 +1533,7 @@
/**
* @brief Converts from 2 digit BCD to Binary.
- * @param Value: BCD value to be converted
+ * @param Value BCD value to be converted
* @retval Converted word
*/
uint8_t RTC_Bcd2ToByte(uint8_t Value)
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rtc.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rtc.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_rtc.h
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief Header file of RTC HAL module.
******************************************************************************
* @attention
@@ -418,14 +416,14 @@
*/
/** @brief Reset RTC handle state
- * @param __HANDLE__: specifies the RTC handle.
+ * @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_RTC_STATE_RESET)
/**
* @brief Disable the write protection for RTC registers.
- * @param __HANDLE__: specifies the RTC handle.
+ * @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_WRITEPROTECTION_DISABLE(__HANDLE__) \
@@ -436,7 +434,7 @@
/**
* @brief Enable the write protection for RTC registers.
- * @param __HANDLE__: specifies the RTC handle.
+ * @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_WRITEPROTECTION_ENABLE(__HANDLE__) \
@@ -446,36 +444,36 @@
/**
* @brief Enable the RTC ALARMA peripheral.
- * @param __HANDLE__: specifies the RTC handle.
+ * @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_ALARMA_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRAE))
/**
* @brief Disable the RTC ALARMA peripheral.
- * @param __HANDLE__: specifies the RTC handle.
+ * @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_ALARMA_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRAE))
/**
* @brief Enable the RTC ALARMB peripheral.
- * @param __HANDLE__: specifies the RTC handle.
+ * @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_ALARMB_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ALRBE))
/**
* @brief Disable the RTC ALARMB peripheral.
- * @param __HANDLE__: specifies the RTC handle.
+ * @param __HANDLE__ specifies the RTC handle.
* @retval None
*/
#define __HAL_RTC_ALARMB_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ALRBE))
/**
* @brief Enable the RTC Alarm interrupt.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg RTC_IT_ALRA: Alarm A interrupt
* @arg RTC_IT_ALRB: Alarm B interrupt
@@ -485,8 +483,8 @@
/**
* @brief Disable the RTC Alarm interrupt.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to be enabled or disabled.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to be enabled or disabled.
* This parameter can be any combination of the following values:
* @arg RTC_IT_ALRA: Alarm A interrupt
* @arg RTC_IT_ALRB: Alarm B interrupt
@@ -496,8 +494,8 @@
/**
* @brief Check whether the specified RTC Alarm interrupt has occurred or not.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC Alarm interrupt to check.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC Alarm interrupt to check.
* This parameter can be:
* @arg RTC_IT_ALRA: Alarm A interrupt
* @arg RTC_IT_ALRB: Alarm B interrupt
@@ -507,8 +505,8 @@
/**
* @brief Get the selected RTC Alarm's flag status.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC Alarm Flag to check.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __FLAG__ specifies the RTC Alarm Flag to check.
* This parameter can be:
* @arg RTC_FLAG_ALRAF
* @arg RTC_FLAG_ALRBF
@@ -520,8 +518,8 @@
/**
* @brief Clear the RTC Alarm's pending flags.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __FLAG__: specifies the RTC Alarm Flag sources to be enabled or disabled.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __FLAG__ specifies the RTC Alarm Flag sources to be enabled or disabled.
* This parameter can be:
* @arg RTC_FLAG_ALRAF
* @arg RTC_FLAG_ALRBF
@@ -531,8 +529,8 @@
/**
* @brief Check whether the specified RTC Alarm interrupt has been enabled or not.
- * @param __HANDLE__: specifies the RTC handle.
- * @param __INTERRUPT__: specifies the RTC Alarm interrupt sources to check.
+ * @param __HANDLE__ specifies the RTC handle.
+ * @param __INTERRUPT__ specifies the RTC Alarm interrupt sources to check.
* This parameter can be:
* @arg RTC_IT_ALRA: Alarm A interrupt
* @arg RTC_IT_ALRB: Alarm B interrupt
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rtc_ex.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rtc_ex.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_rtc_ex.c
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief RTC HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Real Time Clock (RTC) Extension peripheral:
@@ -140,16 +138,16 @@
/**
* @brief Sets TimeStamp.
* @note This API must be called before enabling the TimeStamp feature.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
- * @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is
+ * @param TimeStampEdge Specifies the pin edge on which the TimeStamp is
* activated.
* This parameter can be one of the following values:
* @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
* rising edge of the related pin.
* @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
* falling edge of the related pin.
- * @param RTC_TimeStampPin: specifies the RTC TimeStamp Pin.
+ * @param RTC_TimeStampPin specifies the RTC TimeStamp Pin.
* This parameter can be one of the following values:
* @arg RTC_TIMESTAMPPIN_PC13: PC13 is selected as RTC TimeStamp Pin.
* @arg RTC_TIMESTAMPPIN_PI8: PI8 is selected as RTC TimeStamp Pin.
@@ -199,17 +197,17 @@
/**
* @brief Sets TimeStamp with Interrupt.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @note This API must be called before enabling the TimeStamp feature.
- * @param TimeStampEdge: Specifies the pin edge on which the TimeStamp is
+ * @param TimeStampEdge Specifies the pin edge on which the TimeStamp is
* activated.
* This parameter can be one of the following values:
* @arg RTC_TIMESTAMPEDGE_RISING: the Time stamp event occurs on the
* rising edge of the related pin.
* @arg RTC_TIMESTAMPEDGE_FALLING: the Time stamp event occurs on the
* falling edge of the related pin.
- * @param RTC_TimeStampPin: Specifies the RTC TimeStamp Pin.
+ * @param RTC_TimeStampPin Specifies the RTC TimeStamp Pin.
* This parameter can be one of the following values:
* @arg RTC_TIMESTAMPPIN_PC13: PC13 is selected as RTC TimeStamp Pin.
* @arg RTC_TIMESTAMPPIN_PI8: PI8 is selected as RTC TimeStamp Pin.
@@ -269,13 +267,13 @@
/**
* @brief Deactivates TimeStamp.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_DeactivateTimeStamp(RTC_HandleTypeDef *hrtc)
{
- uint32_t tmpreg = 0;
+ uint32_t tmpreg = 0U;
/* Process Locked */
__HAL_LOCK(hrtc);
@@ -308,7 +306,7 @@
/**
* @brief Sets Internal TimeStamp.
* @note This API must be called before enabling the internal TimeStamp feature.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval HAL status
*/
@@ -339,7 +337,7 @@
/**
* @brief Deactivates internal TimeStamp.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval HAL status
*/
@@ -369,11 +367,11 @@
/**
* @brief Gets the RTC TimeStamp value.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
- * @param sTimeStamp: Pointer to Time structure
- * @param sTimeStampDate: Pointer to Date structure
- * @param Format: specifies the format of the entered parameters.
+ * @param sTimeStamp Pointer to Time structure
+ * @param sTimeStampDate Pointer to Date structure
+ * @param Format specifies the format of the entered parameters.
* This parameter can be one of the following values:
* FORMAT_BIN: Binary data format
* FORMAT_BCD: BCD data format
@@ -381,7 +379,7 @@
*/
HAL_StatusTypeDef HAL_RTCEx_GetTimeStamp(RTC_HandleTypeDef *hrtc, RTC_TimeTypeDef* sTimeStamp, RTC_DateTypeDef* sTimeStampDate, uint32_t Format)
{
- uint32_t tmptime = 0, tmpdate = 0;
+ uint32_t tmptime = 0U, tmpdate = 0U;
/* Check the parameters */
assert_param(IS_RTC_FORMAT(Format));
@@ -391,17 +389,17 @@
tmpdate = (uint32_t)(hrtc->Instance->TSDR & RTC_DR_RESERVED_MASK);
/* Fill the Time structure fields with the read parameters */
- sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16);
- sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8);
+ sTimeStamp->Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16U);
+ sTimeStamp->Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8U);
sTimeStamp->Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU));
- sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16);
+ sTimeStamp->TimeFormat = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16U);
sTimeStamp->SubSeconds = (uint32_t) hrtc->Instance->TSSSR;
/* Fill the Date structure fields with the read parameters */
- sTimeStampDate->Year = 0;
- sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8);
+ sTimeStampDate->Year = 0U;
+ sTimeStampDate->Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8U);
sTimeStampDate->Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));
- sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13);
+ sTimeStampDate->WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13U);
/* Check the input parameters format */
if(Format == RTC_FORMAT_BIN)
@@ -426,14 +424,14 @@
/**
* @brief Sets Tamper
* @note By calling this API we disable the tamper interrupt for all tampers.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
- * @param sTamper: Pointer to Tamper Structure.
+ * @param sTamper Pointer to Tamper Structure.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_SetTamper(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
{
- uint32_t tmpreg = 0;
+ uint32_t tmpreg = 0U;
/* Check the parameters */
assert_param(IS_RTC_TAMPER(sTamper->Tamper));
@@ -453,21 +451,21 @@
if(sTamper->Trigger != RTC_TAMPERTRIGGER_RISINGEDGE)
{
- sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1);
+ sTamper->Trigger = (uint32_t)(sTamper->Tamper << 1U);
}
if(sTamper->NoErase != RTC_TAMPER_ERASE_BACKUP_ENABLE)
{
sTamper->NoErase = 0;
- if((sTamper->Tamper & RTC_TAMPER_1) != 0)
+ if((sTamper->Tamper & RTC_TAMPER_1) != 0U)
{
sTamper->NoErase |= RTC_TAMPCR_TAMP1NOERASE;
}
- if((sTamper->Tamper & RTC_TAMPER_2) != 0)
+ if((sTamper->Tamper & RTC_TAMPER_2) != 0U)
{
sTamper->NoErase |= RTC_TAMPCR_TAMP2NOERASE;
}
- if((sTamper->Tamper & RTC_TAMPER_3) != 0)
+ if((sTamper->Tamper & RTC_TAMPER_3) != 0U)
{
sTamper->NoErase |= RTC_TAMPCR_TAMP3NOERASE;
}
@@ -476,15 +474,15 @@
if(sTamper->MaskFlag != RTC_TAMPERMASK_FLAG_DISABLE)
{
sTamper->MaskFlag = 0;
- if((sTamper->Tamper & RTC_TAMPER_1) != 0)
+ if((sTamper->Tamper & RTC_TAMPER_1) != 0U)
{
sTamper->MaskFlag |= RTC_TAMPCR_TAMP1MF;
}
- if((sTamper->Tamper & RTC_TAMPER_2) != 0)
+ if((sTamper->Tamper & RTC_TAMPER_2) != 0U)
{
sTamper->MaskFlag |= RTC_TAMPCR_TAMP2MF;
}
- if((sTamper->Tamper & RTC_TAMPER_3) != 0)
+ if((sTamper->Tamper & RTC_TAMPER_3) != 0U)
{
sTamper->MaskFlag |= RTC_TAMPCR_TAMP3MF;
}
@@ -514,9 +512,9 @@
/**
* @brief Sets Tamper with interrupt.
* @note By calling this API we force the tamper interrupt for all tampers.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
- * @param sTamper: Pointer to RTC Tamper.
+ * @param sTamper Pointer to RTC Tamper.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_SetTamper_IT(RTC_HandleTypeDef *hrtc, RTC_TamperTypeDef* sTamper)
@@ -624,9 +622,9 @@
/**
* @brief Deactivates Tamper.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
- * @param Tamper: Selected tamper pin.
+ * @param Tamper Selected tamper pin.
* This parameter can be RTC_Tamper_1 and/or RTC_TAMPER_2.
* @retval HAL status
*/
@@ -668,7 +666,7 @@
/**
* @brief This function handles TimeStamp interrupt request.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval None
*/
@@ -741,7 +739,7 @@
/**
* @brief TimeStamp callback.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval None
*/
@@ -757,7 +755,7 @@
/**
* @brief Tamper 1 callback.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval None
*/
@@ -773,7 +771,7 @@
/**
* @brief Tamper 2 callback.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval None
*/
@@ -789,7 +787,7 @@
/**
* @brief Tamper 3 callback.
- * @param hrtc: RTC handle
+ * @param hrtc RTC handle
* @retval None
*/
__weak void HAL_RTCEx_Tamper3EventCallback(RTC_HandleTypeDef *hrtc)
@@ -804,9 +802,9 @@
/**
* @brief This function handles TimeStamp polling request.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
- * @param Timeout: Timeout duration
+ * @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_PollForTimeStampEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
@@ -847,14 +845,14 @@
/**
* @brief This function handles Tamper1 Polling.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
- * @param Timeout: Timeout duration
+ * @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_PollForTamper1Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart = 0U;
/* Get tick */
tickstart = HAL_GetTick();
@@ -864,7 +862,7 @@
{
if(Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
+ if((Timeout == 0U)||((HAL_GetTick() - tickstart ) > Timeout))
{
hrtc->State = HAL_RTC_STATE_TIMEOUT;
return HAL_TIMEOUT;
@@ -883,9 +881,9 @@
/**
* @brief This function handles Tamper2 Polling.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
- * @param Timeout: Timeout duration
+ * @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_PollForTamper2Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
@@ -919,8 +917,8 @@
/**
* @brief This function handles Tamper3 Polling.
- * @param hrtc: RTC handle
- * @param Timeout: Timeout duration
+ * @param hrtc RTC handle
+ * @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_PollForTamper3Event(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
@@ -969,10 +967,10 @@
/**
* @brief Sets wake up timer.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
- * @param WakeUpCounter: Wake up counter
- * @param WakeUpClock: Wake up clock
+ * @param WakeUpCounter Wake up counter
+ * @param WakeUpClock Wake up clock
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
@@ -1042,15 +1040,15 @@
/**
* @brief Sets wake up timer with interrupt
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
- * @param WakeUpCounter: Wake up counter
- * @param WakeUpClock: Wake up clock
+ * @param WakeUpCounter Wake up counter
+ * @param WakeUpClock Wake up clock
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_SetWakeUpTimer_IT(RTC_HandleTypeDef *hrtc, uint32_t WakeUpCounter, uint32_t WakeUpClock)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart = 0; // MBED: changed
/* Check the parameters */
assert_param(IS_RTC_WAKEUP_CLOCK(WakeUpClock));
@@ -1144,13 +1142,13 @@
/**
* @brief Deactivates wake up timer counter.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval HAL status
*/
uint32_t HAL_RTCEx_DeactivateWakeUpTimer(RTC_HandleTypeDef *hrtc)
{
- uint32_t tickstart = 0;
+ uint32_t tickstart = 0U;
/* Process Locked */
__HAL_LOCK(hrtc);
@@ -1199,7 +1197,7 @@
/**
* @brief Gets wake up timer counter.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval Counter value
*/
@@ -1211,7 +1209,7 @@
/**
* @brief This function handles Wake Up Timer interrupt request.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval None
*/
@@ -1239,7 +1237,7 @@
/**
* @brief Wake Up Timer callback.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval None
*/
@@ -1255,9 +1253,9 @@
/**
* @brief This function handles Wake Up Timer Polling.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
- * @param Timeout: Timeout duration
+ * @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_PollForWakeUpTimerEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
@@ -1322,12 +1320,12 @@
/**
* @brief Writes a data in a specified RTC Backup data register.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
- * @param BackupRegister: RTC Backup data Register number.
+ * @param BackupRegister RTC Backup data Register number.
* This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
* specify the register.
- * @param Data: Data to be written in the specified RTC Backup data register.
+ * @param Data Data to be written in the specified RTC Backup data register.
* @retval None
*/
void HAL_RTCEx_BKUPWrite(RTC_HandleTypeDef *hrtc, uint32_t BackupRegister, uint32_t Data)
@@ -1346,9 +1344,9 @@
/**
* @brief Reads data from the specified RTC Backup data Register.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
- * @param BackupRegister: RTC Backup data Register number.
+ * @param BackupRegister RTC Backup data Register number.
* This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to
* specify the register.
* @retval Read value
@@ -1369,18 +1367,18 @@
/**
* @brief Sets the Smooth calibration parameters.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
- * @param SmoothCalibPeriod: Select the Smooth Calibration Period.
+ * @param SmoothCalibPeriod Select the Smooth Calibration Period.
* This parameter can be can be one of the following values :
* @arg RTC_SMOOTHCALIB_PERIOD_32SEC: The smooth calibration period is 32s.
* @arg RTC_SMOOTHCALIB_PERIOD_16SEC: The smooth calibration period is 16s.
* @arg RTC_SMOOTHCALIB_PERIOD_8SEC: The smooth calibration period is 8s.
- * @param SmoothCalibPlusPulses: Select to Set or reset the CALP bit.
+ * @param SmoothCalibPlusPulses Select to Set or reset the CALP bit.
* This parameter can be one of the following values:
* @arg RTC_SMOOTHCALIB_PLUSPULSES_SET: Add one RTCCLK pulses every 2*11 pulses.
* @arg RTC_SMOOTHCALIB_PLUSPULSES_RESET: No RTCCLK pulses are added.
- * @param SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits.
+ * @param SmouthCalibMinusPulsesValue Select the value of CALM[80] bits.
* This parameter can be one any value from 0 to 0x000001FF.
* @note To deactivate the smooth calibration, the field SmoothCalibPlusPulses
* must be equal to SMOOTHCALIB_PLUSPULSES_RESET and the field
@@ -1447,13 +1445,13 @@
/**
* @brief Configures the Synchronization Shift Control Settings.
* @note When REFCKON is set, firmware must not write to Shift control register.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
- * @param ShiftAdd1S: Select to add or not 1 second to the time calendar.
+ * @param ShiftAdd1S Select to add or not 1 second to the time calendar.
* This parameter can be one of the following values :
* @arg RTC_SHIFTADD1S_SET: Add one second to the clock calendar.
* @arg RTC_SHIFTADD1S_RESET: No effect.
- * @param ShiftSubFS: Select the number of Second Fractions to substitute.
+ * @param ShiftSubFS Select the number of Second Fractions to substitute.
* This parameter can be one any value from 0 to 0x7FFF.
* @retval HAL status
*/
@@ -1544,9 +1542,9 @@
/**
* @brief Configures the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
- * @param CalibOutput: Select the Calibration output Selection .
+ * @param CalibOutput Select the Calibration output Selection .
* This parameter can be one of the following values:
* @arg RTC_CALIBOUTPUT_512HZ: A signal has a regular waveform at 512Hz.
* @arg RTC_CALIBOUTPUT_1HZ: A signal has a regular waveform at 1Hz.
@@ -1587,7 +1585,7 @@
/**
* @brief Deactivates the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval HAL status
*/
@@ -1617,7 +1615,7 @@
/**
* @brief Enables the RTC reference clock detection.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval HAL status
*/
@@ -1667,7 +1665,7 @@
/**
* @brief Disable the RTC reference clock detection.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval HAL status
*/
@@ -1717,7 +1715,7 @@
/**
* @brief Enables the Bypass Shadow feature.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @note When the Bypass Shadow is enabled the calendar value are taken
* directly from the Calendar counter.
@@ -1750,7 +1748,7 @@
/**
* @brief Disables the Bypass Shadow feature.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @note When the Bypass Shadow is enabled the calendar value are taken
* directly from the Calendar counter.
@@ -1802,7 +1800,7 @@
/**
* @brief Alarm B callback.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
* @retval None
*/
@@ -1818,9 +1816,9 @@
/**
* @brief This function handles AlarmB Polling request.
- * @param hrtc: pointer to a RTC_HandleTypeDef structure that contains
+ * @param hrtc pointer to a RTC_HandleTypeDef structure that contains
* the configuration information for RTC.
- * @param Timeout: Timeout duration
+ * @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_RTCEx_PollForAlarmBEvent(RTC_HandleTypeDef *hrtc, uint32_t Timeout)
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rtc_ex.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_rtc_ex.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_rtc_ex.h * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief Header file of RTC HAL Extension module. ****************************************************************************** * @attention @@ -360,22 +358,22 @@ /** * @brief Enable the RTC WakeUp Timer peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_WAKEUPTIMER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_WUTE)) /** * @brief Disable the RTC WakeUp Timer peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_WAKEUPTIMER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_WUTE)) /** * @brief Enable the RTC WakeUpTimer interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled. * This parameter can be: * @arg RTC_IT_WUT: WakeUpTimer interrupt * @retval None @@ -384,8 +382,8 @@ /** * @brief Disable the RTC WakeUpTimer interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to be enabled or disabled. * This parameter can be: * @arg RTC_IT_WUT: WakeUpTimer interrupt * @retval None @@ -394,8 +392,8 @@ /** * @brief Check whether the specified RTC WakeUpTimer interrupt has occurred or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC WakeUpTimer interrupt sources to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC WakeUpTimer interrupt sources to check. * This parameter can be: * @arg RTC_IT_WUT: WakeUpTimer interrupt * @retval None @@ -404,8 +402,8 @@ /** * @brief Check whether the specified RTC Wake Up timer interrupt has been enabled or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Wake Up timer interrupt sources to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Wake Up timer interrupt sources to check. * This parameter can be: * @arg RTC_IT_WUT: WakeUpTimer interrupt * @retval None @@ -414,8 +412,8 @@ /** * @brief Get the selected RTC WakeUpTimer's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC WakeUpTimer Flag is pending or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC WakeUpTimer Flag is pending or not. * This parameter can be: * @arg RTC_FLAG_WUTF * @arg RTC_FLAG_WUTWF @@ -425,8 +423,8 @@ /** * @brief Clear the RTC Wake Up timer's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC WakeUpTimer Flag to clear. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC WakeUpTimer Flag to clear. * This parameter can be: * @arg RTC_FLAG_WUTF * @retval None @@ -435,50 +433,50 @@ /** * @brief Enable the RTC Tamper1 input detection. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_TAMPER1_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP1E)) /** * @brief Disable the RTC Tamper1 input detection. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_TAMPER1_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP1E)) /** * @brief Enable the RTC Tamper2 input detection. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_TAMPER2_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP2E)) /** * @brief Disable the RTC Tamper2 input detection. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_TAMPER2_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP2E)) /** * @brief Enable the RTC Tamper3 input detection. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_TAMPER3_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR |= (RTC_TAMPCR_TAMP3E)) /** * @brief Disable the RTC Tamper3 input detection. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_TAMPER3_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->TAMPCR &= ~(RTC_TAMPCR_TAMP3E)) /** * @brief Check whether the specified RTC Tamper interrupt has occurred or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Tamper interrupt to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Tamper interrupt to check. * This parameter can be: * @arg RTC_IT_TAMP: All tampers interrupts * @arg RTC_IT_TAMP1: Tamper1 interrupt @@ -492,8 +490,8 @@ /** * @brief Check whether the specified RTC Tamper interrupt has been enabled or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Tamper interrupt source to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Tamper interrupt source to check. * This parameter can be: * @arg RTC_IT_TAMP: All tampers interrupts * @arg RTC_IT_TAMP1: Tamper1 interrupt @@ -505,8 +503,8 @@ /** * @brief Get the selected RTC Tamper's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Tamper Flag is pending or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Tamper Flag is pending or not. * This parameter can be: * @arg RTC_FLAG_TAMP1F: Tamper1 flag * @arg RTC_FLAG_TAMP2F: Tamper2 flag @@ -517,8 +515,8 @@ /** * @brief Clear the RTC Tamper's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Tamper Flag sources to clear. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Tamper Flag sources to clear. * This parameter can be: * @arg RTC_FLAG_TAMP1F: Tamper1 flag * @arg RTC_FLAG_TAMP2F: Tamper2 flag @@ -529,22 +527,22 @@ /** * @brief Enable the RTC TimeStamp peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_TSE)) /** * @brief Disable the RTC TimeStamp peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_TSE)) /** * @brief Enable the RTC TimeStamp interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt sources to be enabled or disabled. * This parameter can be: * @arg RTC_IT_TS: TimeStamp interrupt * @retval None @@ -553,8 +551,8 @@ /** * @brief Disable the RTC TimeStamp interrupt. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to be enabled or disabled. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt sources to be enabled or disabled. * This parameter can be: * @arg RTC_IT_TS: TimeStamp interrupt * @retval None @@ -563,8 +561,8 @@ /** * @brief Check whether the specified RTC TimeStamp interrupt has occurred or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC TimeStamp interrupt sources to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC TimeStamp interrupt sources to check. * This parameter can be: * @arg RTC_IT_TS: TimeStamp interrupt * @retval None @@ -573,8 +571,8 @@ /** * @brief Check whether the specified RTC Time Stamp interrupt has been enabled or not. - * @param __HANDLE__: specifies the RTC handle. - * @param __INTERRUPT__: specifies the RTC Time Stamp interrupt source to check. + * @param __HANDLE__ specifies the RTC handle. + * @param __INTERRUPT__ specifies the RTC Time Stamp interrupt source to check. * This parameter can be: * @arg RTC_IT_TS: TimeStamp interrupt * @retval None @@ -583,8 +581,8 @@ /** * @brief Get the selected RTC TimeStamp's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC TimeStamp Flag is pending or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC TimeStamp Flag is pending or not. * This parameter can be: * @arg RTC_FLAG_TSF * @arg RTC_FLAG_TSOVF @@ -594,8 +592,8 @@ /** * @brief Clear the RTC Time Stamp's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Alarm Flag sources to clear. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Alarm Flag sources to clear. * This parameter can be: * @arg RTC_FLAG_TSF * @arg RTC_FLAG_TSOVF @@ -605,22 +603,22 @@ /** * @brief Enable the RTC internal TimeStamp peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_INTERNAL_TIMESTAMP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_ITSE)) /** * @brief Disable the RTC internal TimeStamp peripheral. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_INTERNAL_TIMESTAMP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_ITSE)) /** * @brief Get the selected RTC Internal Time Stamp's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Internal Time Stamp Flag is pending or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Internal Time Stamp Flag is pending or not. * This parameter can be: * @arg RTC_FLAG_ITSF * @retval None @@ -629,8 +627,8 @@ /** * @brief Clear the RTC Internal Time Stamp's pending flags. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC Internal Time Stamp Flag source to clear. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC Internal Time Stamp Flag source to clear. * This parameter can be: * @arg RTC_FLAG_ITSF * @retval None @@ -639,36 +637,36 @@ /** * @brief Enable the RTC calibration output. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_CALIBRATION_OUTPUT_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_COE)) /** * @brief Disable the calibration output. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_CALIBRATION_OUTPUT_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_COE)) /** * @brief Enable the clock reference detection. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_CLOCKREF_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR |= (RTC_CR_REFCKON)) /** * @brief Disable the clock reference detection. - * @param __HANDLE__: specifies the RTC handle. + * @param __HANDLE__ specifies the RTC handle. * @retval None */ #define __HAL_RTC_CLOCKREF_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= ~(RTC_CR_REFCKON)) /** * @brief Get the selected RTC shift operation's flag status. - * @param __HANDLE__: specifies the RTC handle. - * @param __FLAG__: specifies the RTC shift operation Flag is pending or not. + * @param __HANDLE__ specifies the RTC handle. + * @param __FLAG__ specifies the RTC shift operation Flag is pending or not. * This parameter can be: * @arg RTC_FLAG_SHPF * @retval None
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sai.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sai.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_sai.c
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief SAI HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Serial Audio Interface (SAI) peripheral:
@@ -197,7 +195,6 @@
*/
#define SAI_FIFO_SIZE 8
#define SAI_DEFAULT_TIMEOUT 4 /* 4ms */
-#define SAI_xCR2_MUTECNT_OFFSET POSITION_VAL(SAI_xCR2_MUTECNT)
/**
* @}
*/
@@ -273,12 +270,12 @@
* @brief Initialize the structure FrameInit, SlotInit and the low part of
* Init according to the specified parameters and call the function
* HAL_SAI_Init to initialize the SAI block.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
- * @param protocol: one of the supported protocol @ref SAI_Protocol
- * @param datasize: one of the supported datasize @ref SAI_Protocol_DataSize
+ * @param protocol one of the supported protocol @ref SAI_Protocol
+ * @param datasize one of the supported datasize @ref SAI_Protocol_DataSize
* the configuration information for SAI module.
- * @param nbslot: Number of slot.
+ * @param nbslot Number of slot.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SAI_InitProtocol(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
@@ -316,7 +313,7 @@
/**
* @brief Initialize the SAI according to the specified parameters.
* in the SAI_InitTypeDef structure and initialize the associated handle.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval HAL status
*/
@@ -518,7 +515,7 @@
/**
* @brief DeInitialize the SAI peripheral.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval HAL status
*/
@@ -559,7 +556,7 @@
/**
* @brief Initialize the SAI MSP.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval None
*/
@@ -575,7 +572,7 @@
/**
* @brief DeInitialize the SAI MSP.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval None
*/
@@ -617,17 +614,14 @@
(+) Blocking mode functions are :
(++) HAL_SAI_Transmit()
(++) HAL_SAI_Receive()
- (++) HAL_SAI_TransmitReceive()
(+) Non Blocking mode functions with Interrupt are :
(++) HAL_SAI_Transmit_IT()
(++) HAL_SAI_Receive_IT()
- (++) HAL_SAI_TransmitReceive_IT()
(+) Non Blocking mode functions with DMA are :
(++) HAL_SAI_Transmit_DMA()
(++) HAL_SAI_Receive_DMA()
- (++) HAL_SAI_TransmitReceive_DMA()
(+) A set of Transfer Complete Callbacks are provided in non Blocking mode:
(++) HAL_SAI_TxCpltCallback()
@@ -640,11 +634,11 @@
/**
* @brief Transmit an amount of data in blocking mode.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be sent
- * @param Timeout: Timeout duration
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
+ * @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SAI_Transmit(SAI_HandleTypeDef *hsai, uint8_t* pData, uint16_t Size, uint32_t Timeout)
@@ -740,11 +734,11 @@
/**
* @brief Receive an amount of data in blocking mode.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be received
- * @param Timeout: Timeout duration
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be received
+ * @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SAI_Receive(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size, uint32_t Timeout)
@@ -838,10 +832,10 @@
/**
* @brief Transmit an amount of data in non-blocking mode with Interrupt.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be sent
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SAI_Transmit_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
@@ -900,10 +894,10 @@
/**
* @brief Receive an amount of data in non-blocking mode with Interrupt.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be received
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be received
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SAI_Receive_IT(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
@@ -960,7 +954,7 @@
/**
* @brief Pause the audio stream playing from the Media.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval HAL status
*/
@@ -980,7 +974,7 @@
/**
* @brief Resume the audio stream playing from the Media.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval HAL status
*/
@@ -1007,54 +1001,73 @@
/**
* @brief Stop the audio stream playing from the Media.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SAI_DMAStop(SAI_HandleTypeDef *hsai)
{
+ HAL_StatusTypeDef status = HAL_OK;
+
/* Process Locked */
__HAL_LOCK(hsai);
/* Disable the SAI DMA request */
hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
- /* Abort the SAI DMA Streams */
- if(hsai->hdmatx != NULL)
+ /* Abort the SAI Tx DMA Stream */
+ if((hsai->hdmatx != NULL) && (hsai->State == HAL_SAI_STATE_BUSY_TX))
{
if(HAL_DMA_Abort(hsai->hdmatx) != HAL_OK)
{
- return HAL_ERROR;
+ /* If the DMA Tx errorCode is different from DMA No Transfer then return Error */
+ if(hsai->hdmatx->ErrorCode != HAL_DMA_ERROR_NO_XFER)
+ {
+ status = HAL_ERROR;
+ hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
+ }
}
}
- if(hsai->hdmarx != NULL)
+ /* Abort the SAI Rx DMA Stream */
+ if((hsai->hdmarx != NULL) && (hsai->State == HAL_SAI_STATE_BUSY_RX))
{
if(HAL_DMA_Abort(hsai->hdmarx) != HAL_OK)
{
- return HAL_ERROR;
+ /* If the DMA Rx errorCode is different from DMA No Transfer then return Error */
+ if(hsai->hdmarx->ErrorCode != HAL_DMA_ERROR_NO_XFER)
+ {
+ status = HAL_ERROR;
+ hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
+ }
}
}
-
+
/* Disable SAI peripheral */
SAI_Disable(hsai);
+ /* Flush the fifo */
+ SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
+
+ /* Set hsai state to ready */
hsai->State = HAL_SAI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hsai);
- return HAL_OK;
+ return status;
}
/**
* @brief Abort the current transfer and disable the SAI.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SAI_Abort(SAI_HandleTypeDef *hsai)
{
+ HAL_StatusTypeDef status = HAL_OK;
+
/* Process Locked */
__HAL_LOCK(hsai);
@@ -1063,21 +1076,32 @@
{
/* Disable the SAI DMA request */
hsai->Instance->CR1 &= ~SAI_xCR1_DMAEN;
-
- /* Abort the SAI DMA Streams */
- if(hsai->hdmatx != NULL)
+
+ /* Abort the SAI Tx DMA Stream */
+ if((hsai->hdmatx != NULL) && (hsai->State == HAL_SAI_STATE_BUSY_TX))
{
if(HAL_DMA_Abort(hsai->hdmatx) != HAL_OK)
{
- return HAL_ERROR;
+ /* If the DMA Tx errorCode is different from DMA No Transfer then return Error */
+ if(hsai->hdmatx->ErrorCode != HAL_DMA_ERROR_NO_XFER)
+ {
+ status = HAL_ERROR;
+ hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
+ }
}
}
- if(hsai->hdmarx != NULL)
+ /* Abort the SAI Rx DMA Stream */
+ if((hsai->hdmarx != NULL) && (hsai->State == HAL_SAI_STATE_BUSY_RX))
{
if(HAL_DMA_Abort(hsai->hdmarx) != HAL_OK)
{
- return HAL_ERROR;
+ /* If the DMA Rx errorCode is different from DMA No Transfer then return Error */
+ if(hsai->hdmarx->ErrorCode != HAL_DMA_ERROR_NO_XFER)
+ {
+ status = HAL_ERROR;
+ hsai->ErrorCode |= HAL_SAI_ERROR_DMA;
+ }
}
}
}
@@ -1091,20 +1115,21 @@
/* Flush the fifo */
SET_BIT(hsai->Instance->CR2, SAI_xCR2_FFLUSH);
+ /* Set hsai state to ready */
hsai->State = HAL_SAI_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hsai);
- return HAL_OK;
+ return status;
}
/**
* @brief Transmit an amount of data in non-blocking mode with DMA.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be sent
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SAI_Transmit_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
@@ -1170,10 +1195,10 @@
/**
* @brief Receive an amount of data in non-blocking mode with DMA.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
- * @param pData: Pointer to data buffer
- * @param Size: Amount of data to be received
+ * @param pData Pointer to data buffer
+ * @param Size Amount of data to be received
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SAI_Receive_DMA(SAI_HandleTypeDef *hsai, uint8_t *pData, uint16_t Size)
@@ -1240,9 +1265,9 @@
/**
* @brief Enable the Tx mute mode.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
- * @param val: value sent during the mute @ref SAI_Block_Mute_Value
+ * @param val value sent during the mute @ref SAI_Block_Mute_Value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SAI_EnableTxMuteMode(SAI_HandleTypeDef *hsai, uint16_t val)
@@ -1260,7 +1285,7 @@
/**
* @brief Disable the Tx mute mode.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval HAL status
*/
@@ -1276,10 +1301,10 @@
/**
* @brief Enable the Rx mute detection.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
- * @param callback: function called when the mute is detected.
- * @param counter: number a data before mute detection max 63.
+ * @param callback function called when the mute is detected.
+ * @param counter number a data before mute detection max 63.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SAI_EnableRxMuteMode(SAI_HandleTypeDef *hsai, SAIcallback callback, uint16_t counter)
@@ -1290,7 +1315,7 @@
{
/* set the mute counter */
CLEAR_BIT(hsai->Instance->CR2, SAI_xCR2_MUTECNT);
- SET_BIT(hsai->Instance->CR2, (uint32_t)((uint32_t)counter << SAI_xCR2_MUTECNT_OFFSET));
+ SET_BIT(hsai->Instance->CR2, (uint32_t)((uint32_t)counter << SAI_xCR2_MUTECNT_Pos));
hsai->mutecallback = callback;
/* enable the IT interrupt */
__HAL_SAI_ENABLE_IT(hsai, SAI_IT_MUTEDET);
@@ -1301,7 +1326,7 @@
/**
* @brief Disable the Rx mute detection.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval HAL status
*/
@@ -1320,7 +1345,7 @@
/**
* @brief Handle SAI interrupt request.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval None
*/
@@ -1486,7 +1511,7 @@
/**
* @brief Tx Transfer completed callback.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval None
*/
@@ -1502,7 +1527,7 @@
/**
* @brief Tx Transfer Half completed callback.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval None
*/
@@ -1518,7 +1543,7 @@
/**
* @brief Rx Transfer completed callback.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval None
*/
@@ -1534,7 +1559,7 @@
/**
* @brief Rx Transfer half completed callback.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval None
*/
@@ -1550,7 +1575,7 @@
/**
* @brief SAI error callback.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval None
*/
@@ -1586,7 +1611,7 @@
/**
* @brief Return the SAI handle state.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval HAL state
*/
@@ -1597,7 +1622,7 @@
/**
* @brief Return the SAI error code.
-* @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+* @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for the specified SAI Block.
* @retval SAI Error Code
*/
@@ -1621,12 +1646,12 @@
/**
* @brief Initialize the SAI I2S protocol according to the specified parameters
* in the SAI_InitTypeDef and create the associated handle.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
- * @param protocol: one of the supported protocol.
- * @param datasize: one of the supported datasize @ref SAI_Protocol_DataSize
+ * @param protocol one of the supported protocol.
+ * @param datasize one of the supported datasize @ref SAI_Protocol_DataSize
* the configuration information for SAI module.
- * @param nbslot: number of slot minimum value is 2 and max is 16.
+ * @param nbslot number of slot minimum value is 2 and max is 16.
* the value must be a multiple of 2.
* @retval HAL status
*/
@@ -1716,11 +1741,11 @@
/**
* @brief Initialize the SAI PCM protocol according to the specified parameters
* in the SAI_InitTypeDef and create the associated handle.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
- * @param protocol: one of the supported protocol
- * @param datasize: one of the supported datasize @ref SAI_Protocol_DataSize
- * @param nbslot: number of slot minimum value is 1 and the max is 16.
+ * @param protocol one of the supported protocol
+ * @param datasize one of the supported datasize @ref SAI_Protocol_DataSize
+ * @param nbslot number of slot minimum value is 1 and the max is 16.
* @retval HAL status
*/
static HAL_StatusTypeDef SAI_InitPCM(SAI_HandleTypeDef *hsai, uint32_t protocol, uint32_t datasize, uint32_t nbslot)
@@ -1786,7 +1811,7 @@
/**
* @brief Fill the fifo.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval None
*/
@@ -1815,9 +1840,9 @@
/**
* @brief Return the interrupt flag to set according the SAI setup.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
- * @param mode: SAI_MODE_DMA or SAI_MODE_IT
+ * @param mode SAI_MODE_DMA or SAI_MODE_IT
* @retval the list of the IT flag to enable
*/
static uint32_t SAI_InterruptFlag(SAI_HandleTypeDef *hsai, uint32_t mode)
@@ -1849,7 +1874,7 @@
/**
* @brief Disable the SAI and wait for the disabling.
- * @param hsai : pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval None
*/
@@ -1878,7 +1903,7 @@
/**
* @brief Tx Handler for Transmit in Interrupt mode 8-Bit transfer.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval None
*/
@@ -1902,7 +1927,7 @@
/**
* @brief Tx Handler for Transmit in Interrupt mode for 16-Bit transfer.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval None
*/
@@ -1927,7 +1952,7 @@
/**
* @brief Tx Handler for Transmit in Interrupt mode for 32-Bit transfer.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval None
*/
@@ -1952,7 +1977,7 @@
/**
* @brief Rx Handler for Receive in Interrupt mode 8-Bit transfer.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval None
*/
@@ -1978,7 +2003,7 @@
/**
* @brief Rx Handler for Receive in Interrupt mode for 16-Bit transfer.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval None
*/
@@ -2004,7 +2029,7 @@
}
/**
* @brief Rx Handler for Receive in Interrupt mode for 32-Bit transfer.
- * @param hsai: pointer to a SAI_HandleTypeDef structure that contains
+ * @param hsai pointer to a SAI_HandleTypeDef structure that contains
* the configuration information for SAI module.
* @retval None
*/
@@ -2031,7 +2056,7 @@
/**
* @brief DMA SAI transmit process complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -2056,7 +2081,7 @@
/**
* @brief DMA SAI transmit process half complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -2069,7 +2094,7 @@
/**
* @brief DMA SAI receive process complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -2092,7 +2117,7 @@
/**
* @brief DMA SAI receive process half complete callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -2104,7 +2129,7 @@
}
/**
* @brief DMA SAI communication error callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -2135,7 +2160,7 @@
/**
* @brief DMA SAI Abort callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sai.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sai.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_sai.h * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief Header file of SAI HAL module. ****************************************************************************** * @attention @@ -565,14 +563,14 @@ */ /** @brief Reset SAI handle state. - * @param __HANDLE__: specifies the SAI Handle. + * @param __HANDLE__ specifies the SAI Handle. * @retval None */ #define __HAL_SAI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SAI_STATE_RESET) /** @brief Enable or disable the specified SAI interrupts. - * @param __HANDLE__: specifies the SAI Handle. - * @param __INTERRUPT__: specifies the interrupt source to enable or disable. + * @param __HANDLE__ specifies the SAI Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable or disable. * This parameter can be one of the following values: * @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable * @arg SAI_IT_MUTEDET: Mute detection interrupt enable @@ -587,8 +585,8 @@ #define __HAL_SAI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (~(__INTERRUPT__))) /** @brief Check whether the specified SAI interrupt source is enabled or not. - * @param __HANDLE__: specifies the SAI Handle. - * @param __INTERRUPT__: specifies the SAI interrupt source to check. + * @param __HANDLE__ specifies the SAI Handle. + * @param __INTERRUPT__ specifies the SAI interrupt source to check. * This parameter can be one of the following values: * @arg SAI_IT_OVRUDR: Overrun underrun interrupt enable * @arg SAI_IT_MUTEDET: Mute detection interrupt enable @@ -602,8 +600,8 @@ #define __HAL_SAI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Check whether the specified SAI flag is set or not. - * @param __HANDLE__: specifies the SAI Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the SAI Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg SAI_FLAG_OVRUDR: Overrun underrun flag. * @arg SAI_FLAG_MUTEDET: Mute detection flag. @@ -617,8 +615,8 @@ #define __HAL_SAI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) /** @brief Clear the specified SAI pending flag. - * @param __HANDLE__: specifies the SAI Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the SAI Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be any combination of the following values: * @arg SAI_FLAG_OVRUDR: Clear Overrun underrun * @arg SAI_FLAG_MUTEDET: Clear Mute detection
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sai_ex.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sai_ex.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_sai_ex.c * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief Empty file; This file is no longer used to set synchronization and * to get SAI block frequency. Its content is now moved to common files * (stm32f7xx_hal_sai.c/.h) as there's no device's dependency within F7
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sai_ex.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sai_ex.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_sai_ex.h * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief Header file of SAI Extension HAL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sd.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sd.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_sd.c
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief SD card HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Secure Digital (SD) peripheral:
@@ -297,7 +295,7 @@
/**
* @brief Initializes the SD according to the specified parameters in the
SD_HandleTypeDef and create the associated handle.
- * @param hsd: Pointer to the SD handle
+ * @param hsd Pointer to the SD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_Init(SD_HandleTypeDef *hsd)
@@ -344,7 +342,7 @@
/**
* @brief Initializes the SD Card.
- * @param hsd: Pointer to SD handle
+ * @param hsd Pointer to SD handle
* @note This function initializes the SD card. It could be used when a card
re-initialization is needed.
* @retval HAL status
@@ -400,7 +398,7 @@
/**
* @brief De-Initializes the SD card.
- * @param hsd: Pointer to SD handle
+ * @param hsd Pointer to SD handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_DeInit(SD_HandleTypeDef *hsd)
@@ -431,7 +429,7 @@
/**
* @brief Initializes the SD MSP.
- * @param hsd: Pointer to SD handle
+ * @param hsd Pointer to SD handle
* @retval None
*/
__weak void HAL_SD_MspInit(SD_HandleTypeDef *hsd)
@@ -446,7 +444,7 @@
/**
* @brief De-Initialize SD MSP.
- * @param hsd: Pointer to SD handle
+ * @param hsd Pointer to SD handle
* @retval None
*/
__weak void HAL_SD_MspDeInit(SD_HandleTypeDef *hsd)
@@ -483,11 +481,11 @@
* is managed by polling mode.
* @note This API should be followed by a check on the card state through
* HAL_SD_GetCardState().
- * @param hsd: Pointer to SD handle
- * @param pData: pointer to the buffer that will contain the received data
- * @param BlockAdd: Block Address from where data is to be read
- * @param NumberOfBlocks: Number of SD blocks to read
- * @param Timeout: Specify timeout value
+ * @param hsd Pointer to SD handle
+ * @param pData pointer to the buffer that will contain the received data
+ * @param BlockAdd Block Address from where data is to be read
+ * @param NumberOfBlocks Number of SD blocks to read
+ * @param Timeout Specify timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_ReadBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
@@ -669,11 +667,11 @@
* transfer is managed by polling mode.
* @note This API should be followed by a check on the card state through
* HAL_SD_GetCardState().
- * @param hsd: Pointer to SD handle
- * @param pData: pointer to the buffer that will contain the data to transmit
- * @param BlockAdd: Block Address where data will be written
- * @param NumberOfBlocks: Number of SD blocks to write
- * @param Timeout: Specify timeout value
+ * @param hsd Pointer to SD handle
+ * @param pData pointer to the buffer that will contain the data to transmit
+ * @param BlockAdd Block Address where data will be written
+ * @param NumberOfBlocks Number of SD blocks to write
+ * @param Timeout Specify timeout value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_WriteBlocks(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks, uint32_t Timeout)
@@ -842,10 +840,10 @@
* HAL_SD_GetCardState().
* @note You could also check the IT transfer process through the SD Rx
* interrupt event.
- * @param hsd: Pointer to SD handle
- * @param pData: Pointer to the buffer that will contain the received data
- * @param BlockAdd: Block Address from where data is to be read
- * @param NumberOfBlocks: Number of blocks to read.
+ * @param hsd Pointer to SD handle
+ * @param pData Pointer to the buffer that will contain the received data
+ * @param BlockAdd Block Address from where data is to be read
+ * @param NumberOfBlocks Number of blocks to read.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_ReadBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
@@ -943,10 +941,10 @@
* HAL_SD_GetCardState().
* @note You could also check the IT transfer process through the SD Tx
* interrupt event.
- * @param hsd: Pointer to SD handle
- * @param pData: Pointer to the buffer that will contain the data to transmit
- * @param BlockAdd: Block Address where data will be written
- * @param NumberOfBlocks: Number of blocks to write
+ * @param hsd Pointer to SD handle
+ * @param pData Pointer to the buffer that will contain the data to transmit
+ * @param BlockAdd Block Address where data will be written
+ * @param NumberOfBlocks Number of blocks to write
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_WriteBlocks_IT(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
@@ -1045,10 +1043,10 @@
* HAL_SD_GetCardState().
* @note You could also check the DMA transfer process through the SD Rx
* interrupt event.
- * @param hsd: Pointer SD handle
- * @param pData: Pointer to the buffer that will contain the received data
- * @param BlockAdd: Block Address from where data is to be read
- * @param NumberOfBlocks: Number of blocks to read.
+ * @param hsd Pointer SD handle
+ * @param pData Pointer to the buffer that will contain the received data
+ * @param BlockAdd Block Address from where data is to be read
+ * @param NumberOfBlocks Number of blocks to read.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_ReadBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
@@ -1158,10 +1156,10 @@
* HAL_SD_GetCardState().
* @note You could also check the DMA transfer process through the SD Tx
* interrupt event.
- * @param hsd: Pointer to SD handle
- * @param pData: Pointer to the buffer that will contain the data to transmit
- * @param BlockAdd: Block Address where data will be written
- * @param NumberOfBlocks: Number of blocks to write
+ * @param hsd Pointer to SD handle
+ * @param pData Pointer to the buffer that will contain the data to transmit
+ * @param BlockAdd Block Address where data will be written
+ * @param NumberOfBlocks Number of blocks to write
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_WriteBlocks_DMA(SD_HandleTypeDef *hsd, uint8_t *pData, uint32_t BlockAdd, uint32_t NumberOfBlocks)
@@ -1269,9 +1267,9 @@
* @brief Erases the specified memory area of the given SD card.
* @note This API should be followed by a check on the card state through
* HAL_SD_GetCardState().
- * @param hsd: Pointer to SD handle
- * @param BlockStartAdd: Start Block address
- * @param BlockEndAdd: End Block address
+ * @param hsd Pointer to SD handle
+ * @param BlockStartAdd Start Block address
+ * @param BlockEndAdd End Block address
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SD_Erase(SD_HandleTypeDef *hsd, uint32_t BlockStartAdd, uint32_t BlockEndAdd)
@@ -1371,7 +1369,7 @@
/**
* @brief This function handles SD card interrupt request.
- * @param hsd: Pointer to SD handle
+ * @param hsd Pointer to SD handle
* @retval None
*/
void HAL_SD_IRQHandler(SD_HandleTypeDef *hsd)
@@ -1517,7 +1515,7 @@
/**
* @brief return the SD state
- * @param hsd: Pointer to sd handle
+ * @param hsd Pointer to sd handle
* @retval HAL state
*/
HAL_SD_StateTypeDef HAL_SD_GetState(SD_HandleTypeDef *hsd)
@@ -1527,7 +1525,7 @@
/**
* @brief Return the SD error code
-* @param hsd : Pointer to a SD_HandleTypeDef structure that contains
+* @param hsd Pointer to a SD_HandleTypeDef structure that contains
* the configuration information.
* @retval SD Error Code
*/
@@ -1538,7 +1536,7 @@
/**
* @brief Tx Transfer completed callbacks
- * @param hsd: Pointer to SD handle
+ * @param hsd Pointer to SD handle
* @retval None
*/
__weak void HAL_SD_TxCpltCallback(SD_HandleTypeDef *hsd)
@@ -1553,7 +1551,7 @@
/**
* @brief Rx Transfer completed callbacks
- * @param hsd: Pointer SD handle
+ * @param hsd Pointer SD handle
* @retval None
*/
__weak void HAL_SD_RxCpltCallback(SD_HandleTypeDef *hsd)
@@ -1568,7 +1566,7 @@
/**
* @brief SD error callbacks
- * @param hsd: Pointer SD handle
+ * @param hsd Pointer SD handle
* @retval None
*/
__weak void HAL_SD_ErrorCallback(SD_HandleTypeDef *hsd)
@@ -1583,7 +1581,7 @@
/**
* @brief SD Abort callbacks
- * @param hsd: Pointer SD handle
+ * @param hsd Pointer SD handle
* @retval None
*/
__weak void HAL_SD_AbortCallback(SD_HandleTypeDef *hsd)
@@ -1619,8 +1617,8 @@
/**
* @brief Returns information the information of the card which are stored on
* the CID register.
- * @param hsd: Pointer to SD handle
- * @param pCID: Pointer to a HAL_SD_CardCIDTypeDef structure that
+ * @param hsd Pointer to SD handle
+ * @param pCID Pointer to a HAL_SD_CardCIDTypeDef structure that
* contains all CID register parameters
* @retval HAL status
*/
@@ -1700,8 +1698,8 @@
/**
* @brief Returns information the information of the card which are stored on
* the CSD register.
- * @param hsd: Pointer to SD handle
- * @param pCSD: Pointer to a HAL_SD_CardCSDTypeDef structure that
+ * @param hsd Pointer to SD handle
+ * @param pCSD Pointer to a HAL_SD_CardCSDTypeDef structure that
* contains all CSD register parameters
* @retval HAL status
*/
@@ -1847,8 +1845,8 @@
/**
* @brief Gets the SD status info.
- * @param hsd: Pointer to SD handle
- * @param pStatus: Pointer to the HAL_SD_CardStatusTypeDef structure that
+ * @param hsd Pointer to SD handle
+ * @param pStatus Pointer to the HAL_SD_CardStatusTypeDef structure that
* will contain the SD card status information
* @retval HAL status
*/
@@ -1935,8 +1933,8 @@
/**
* @brief Gets the SD card info.
- * @param hsd: Pointer to SD handle
- * @param pCardInfo: Pointer to the HAL_SD_CardInfoTypeDef structure that
+ * @param hsd Pointer to SD handle
+ * @param pCardInfo Pointer to the HAL_SD_CardInfoTypeDef structure that
* will contain the SD card status information
* @retval HAL status
*/
@@ -1957,8 +1955,8 @@
/**
* @brief Enables wide bus operation for the requested card if supported by
* card.
- * @param hsd: Pointer to SD handle
- * @param WideMode: Specifies the SD card wide bus mode
+ * @param hsd Pointer to SD handle
+ * @param WideMode Specifies the SD card wide bus mode
* This parameter can be one of the following values:
* @arg SDMMC_BUS_WIDE_8B: 8-bit data transfer
* @arg SDMMC_BUS_WIDE_4B: 4-bit data transfer
@@ -2034,7 +2032,7 @@
/**
* @brief Gets the current sd card data state.
- * @param hsd: pointer to SD handle
+ * @param hsd pointer to SD handle
* @retval Card state
*/
HAL_SD_CardStateTypeDef HAL_SD_GetCardState(SD_HandleTypeDef *hsd)
@@ -2056,7 +2054,7 @@
/**
* @brief Abort the current transfer and disable the SD.
- * @param hsd: pointer to a SD_HandleTypeDef structure that contains
+ * @param hsd pointer to a SD_HandleTypeDef structure that contains
* the configuration information for SD module.
* @retval HAL status
*/
@@ -2103,7 +2101,7 @@
/**
* @brief Abort the current transfer and disable the SD (IT mode).
- * @param hsd: pointer to a SD_HandleTypeDef structure that contains
+ * @param hsd pointer to a SD_HandleTypeDef structure that contains
* the configuration information for SD module.
* @retval HAL status
*/
@@ -2180,7 +2178,7 @@
/**
* @brief DMA SD transmit process complete callback
- * @param hdma: DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void SD_DMATransmitCplt(DMA_HandleTypeDef *hdma)
@@ -2193,7 +2191,7 @@
/**
* @brief DMA SD receive process complete callback
- * @param hdma: DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void SD_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
@@ -2226,7 +2224,7 @@
/**
* @brief DMA SD communication error callback
-* @param hdma: DMA handle
+* @param hdma DMA handle
* @retval None
*/
static void SD_DMAError(DMA_HandleTypeDef *hdma)
@@ -2261,7 +2259,7 @@
/**
* @brief DMA SD Tx Abort callback
- * @param hdma: DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void SD_DMATxAbort(DMA_HandleTypeDef *hdma)
@@ -2298,7 +2296,7 @@
/**
* @brief DMA SD Rx Abort callback
- * @param hdma: DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void SD_DMARxAbort(DMA_HandleTypeDef *hdma)
@@ -2336,7 +2334,7 @@
/**
* @brief Initializes the sd card.
- * @param hsd: Pointer to SD handle
+ * @param hsd Pointer to SD handle
* @retval SD Card error state
*/
static uint32_t SD_InitCard(SD_HandleTypeDef *hsd)
@@ -2425,7 +2423,7 @@
* @brief Enquires cards about their operating voltage and configures clock
* controls and stores SD information that will be needed in future
* in the SD handle.
- * @param hsd: Pointer to SD handle
+ * @param hsd Pointer to SD handle
* @retval error state
*/
static uint32_t SD_PowerON(SD_HandleTypeDef *hsd)
@@ -2526,7 +2524,7 @@
/**
* @brief Turns the SDMMC output signals off.
- * @param hsd: Pointer to SD handle
+ * @param hsd Pointer to SD handle
* @retval HAL status
*/
static HAL_StatusTypeDef SD_PowerOFF(SD_HandleTypeDef *hsd)
@@ -2539,8 +2537,8 @@
/**
* @brief Send Status info command.
- * @param hsd: pointer to SD handle
- * @param pSDstatus: Pointer to the buffer that will contain the SD card status
+ * @param hsd pointer to SD handle
+ * @param pSDstatus Pointer to the buffer that will contain the SD card status
* SD Status register)
* @retval error state
*/
@@ -2641,8 +2639,8 @@
/**
* @brief Returns the current card's status.
- * @param hsd: Pointer to SD handle
- * @param pCardStatus: pointer to the buffer that will contain the SD card
+ * @param hsd Pointer to SD handle
+ * @param pCardStatus pointer to the buffer that will contain the SD card
* status (Card Status register)
* @retval error state
*/
@@ -2670,7 +2668,7 @@
/**
* @brief Enables the SDMMC wide bus mode.
- * @param hsd: pointer to SD handle
+ * @param hsd pointer to SD handle
* @retval error state
*/
static uint32_t SD_WideBus_Enable(SD_HandleTypeDef *hsd)
@@ -2717,7 +2715,7 @@
/**
* @brief Disables the SDMMC wide bus mode.
- * @param hsd: Pointer to SD handle
+ * @param hsd Pointer to SD handle
* @retval error state
*/
static uint32_t SD_WideBus_Disable(SD_HandleTypeDef *hsd)
@@ -2765,8 +2763,8 @@
/**
* @brief Finds the SD card SCR register value.
- * @param hsd: Pointer to SD handle
- * @param pSCR: pointer to the buffer that will contain the SCR value
+ * @param hsd Pointer to SD handle
+ * @param pSCR pointer to the buffer that will contain the SCR value
* @retval error state
*/
static uint32_t SD_FindSCR(SD_HandleTypeDef *hsd, uint32_t *pSCR)
@@ -2856,7 +2854,7 @@
/**
* @brief Wrap up reading in non-blocking mode.
- * @param hsd: pointer to a SD_HandleTypeDef structure that contains
+ * @param hsd pointer to a SD_HandleTypeDef structure that contains
* the configuration information.
* @retval HAL status
*/
@@ -2880,7 +2878,7 @@
/**
* @brief Wrap up writing in non-blocking mode.
- * @param hsd: pointer to a SD_HandleTypeDef structure that contains
+ * @param hsd pointer to a SD_HandleTypeDef structure that contains
* the configuration information.
* @retval HAL status
*/
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sd.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sd.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_sd.h * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief Header file of SD HAL module. ****************************************************************************** * @attention @@ -383,8 +381,8 @@ /** * @brief Enable the SD device interrupt. - * @param __HANDLE__: SD Handle - * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be enabled. + * @param __HANDLE__ SD Handle + * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled. * This parameter can be one or a combination of the following values: * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -414,8 +412,8 @@ /** * @brief Disable the SD device interrupt. - * @param __HANDLE__: SD Handle - * @param __INTERRUPT__: specifies the SDMMC interrupt sources to be disabled. + * @param __HANDLE__ SD Handle + * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled. * This parameter can be one or a combination of the following values: * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -445,8 +443,8 @@ /** * @brief Check whether the specified SD flag is set or not. - * @param __HANDLE__: SD Handle - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ SD Handle + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) @@ -476,8 +474,8 @@ /** * @brief Clear the SD's pending flags. - * @param __HANDLE__: SD Handle - * @param __FLAG__: specifies the flag to clear. + * @param __HANDLE__ SD Handle + * @param __FLAG__ specifies the flag to clear. * This parameter can be one or a combination of the following values: * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) @@ -496,8 +494,8 @@ /** * @brief Check whether the specified SD interrupt has occurred or not. - * @param __HANDLE__: SD Handle - * @param __INTERRUPT__: specifies the SDMMC interrupt source to check. + * @param __HANDLE__ SD Handle + * @param __INTERRUPT__ specifies the SDMMC interrupt source to check. * This parameter can be one of the following values: * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -527,8 +525,8 @@ /** * @brief Clear the SD's interrupt pending bits. - * @param __HANDLE__: SD Handle - * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * @param __HANDLE__ SD Handle + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. * This parameter can be one or a combination of the following values: * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sdram.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sdram.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_sdram.c
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief SDRAM HAL module driver.
* This file provides a generic firmware to drive SDRAM memories mounted
* as external device.
@@ -130,9 +128,9 @@
/**
* @brief Performs the SDRAM device initialization sequence.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
- * @param Timing: Pointer to SDRAM control timing structure
+ * @param Timing Pointer to SDRAM control timing structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_Init(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_TimingTypeDef *Timing)
@@ -168,7 +166,7 @@
/**
* @brief Perform the SDRAM device initialization sequence.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
* @retval HAL status
*/
@@ -191,7 +189,7 @@
/**
* @brief SDRAM MSP Init.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
* @retval None
*/
@@ -207,7 +205,7 @@
/**
* @brief SDRAM MSP DeInit.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
* @retval None
*/
@@ -223,7 +221,7 @@
/**
* @brief This function handles SDRAM refresh error interrupt request.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
* @retval HAL status
*/
@@ -242,7 +240,7 @@
/**
* @brief SDRAM Refresh error callback.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
* @retval None
*/
@@ -258,7 +256,7 @@
/**
* @brief DMA transfer complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -274,7 +272,7 @@
/**
* @brief DMA transfer complete error callback.
- * @param hdma: DMA handle
+ * @param hdma DMA handle
* @retval None
*/
__weak void HAL_SDRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
@@ -307,11 +305,11 @@
/**
* @brief Reads 8-bit data buffer from the SDRAM memory.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
- * @param pAddress: Pointer to read start address
- * @param pDstBuffer: Pointer to destination buffer
- * @param BufferSize: Size of the buffer to read from memory
+ * @param pAddress Pointer to read start address
+ * @param pDstBuffer Pointer to destination buffer
+ * @param BufferSize Size of the buffer to read from memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_Read_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
@@ -348,11 +346,11 @@
/**
* @brief Writes 8-bit data buffer to SDRAM memory.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
- * @param pAddress: Pointer to write start address
- * @param pSrcBuffer: Pointer to source buffer to write
- * @param BufferSize: Size of the buffer to write to memory
+ * @param pAddress Pointer to write start address
+ * @param pSrcBuffer Pointer to source buffer to write
+ * @param BufferSize Size of the buffer to write to memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_Write_8b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
@@ -392,11 +390,11 @@
/**
* @brief Reads 16-bit data buffer from the SDRAM memory.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
- * @param pAddress: Pointer to read start address
- * @param pDstBuffer: Pointer to destination buffer
- * @param BufferSize: Size of the buffer to read from memory
+ * @param pAddress Pointer to read start address
+ * @param pDstBuffer Pointer to destination buffer
+ * @param BufferSize Size of the buffer to read from memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_Read_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
@@ -432,11 +430,11 @@
/**
* @brief Writes 16-bit data buffer to SDRAM memory.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
- * @param pAddress: Pointer to write start address
- * @param pSrcBuffer: Pointer to source buffer to write
- * @param BufferSize: Size of the buffer to write to memory
+ * @param pAddress Pointer to write start address
+ * @param pSrcBuffer Pointer to source buffer to write
+ * @param BufferSize Size of the buffer to write to memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_Write_16b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
@@ -475,11 +473,11 @@
/**
* @brief Reads 32-bit data buffer from the SDRAM memory.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
- * @param pAddress: Pointer to read start address
- * @param pDstBuffer: Pointer to destination buffer
- * @param BufferSize: Size of the buffer to read from memory
+ * @param pAddress Pointer to read start address
+ * @param pDstBuffer Pointer to destination buffer
+ * @param BufferSize Size of the buffer to read from memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_Read_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
@@ -515,11 +513,11 @@
/**
* @brief Writes 32-bit data buffer to SDRAM memory.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
- * @param pAddress: Pointer to write start address
- * @param pSrcBuffer: Pointer to source buffer to write
- * @param BufferSize: Size of the buffer to write to memory
+ * @param pAddress Pointer to write start address
+ * @param pSrcBuffer Pointer to source buffer to write
+ * @param BufferSize Size of the buffer to write to memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_Write_32b(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
@@ -558,11 +556,11 @@
/**
* @brief Reads a Words data from the SDRAM memory using DMA transfer.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
- * @param pAddress: Pointer to read start address
- * @param pDstBuffer: Pointer to destination buffer
- * @param BufferSize: Size of the buffer to read from memory
+ * @param pAddress Pointer to read start address
+ * @param pDstBuffer Pointer to destination buffer
+ * @param BufferSize Size of the buffer to read from memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_Read_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
@@ -599,11 +597,11 @@
/**
* @brief Writes a Words data buffer to SDRAM memory using DMA transfer.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
- * @param pAddress: Pointer to write start address
- * @param pSrcBuffer: Pointer to source buffer to write
- * @param BufferSize: Size of the buffer to write to memory
+ * @param pAddress Pointer to write start address
+ * @param pSrcBuffer Pointer to source buffer to write
+ * @param BufferSize Size of the buffer to write to memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_Write_DMA(SDRAM_HandleTypeDef *hsdram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
@@ -659,7 +657,7 @@
/**
* @brief Enables dynamically SDRAM write protection.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
* @retval HAL status
*/
@@ -685,7 +683,7 @@
/**
* @brief Disables dynamically SDRAM write protection.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
* @retval HAL status
*/
@@ -711,10 +709,10 @@
/**
* @brief Sends Command to the SDRAM bank.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
- * @param Command: SDRAM command structure
- * @param Timeout: Timeout duration
+ * @param Command SDRAM command structure
+ * @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_SendCommand(SDRAM_HandleTypeDef *hsdram, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
@@ -746,9 +744,9 @@
/**
* @brief Programs the SDRAM Memory Refresh rate.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
- * @param RefreshRate: The SDRAM refresh rate value
+ * @param RefreshRate The SDRAM refresh rate value
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_ProgramRefreshRate(SDRAM_HandleTypeDef *hsdram, uint32_t RefreshRate)
@@ -773,9 +771,9 @@
/**
* @brief Sets the Number of consecutive SDRAM Memory auto Refresh commands.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
- * @param AutoRefreshNumber: The SDRAM auto Refresh number
+ * @param AutoRefreshNumber The SDRAM auto Refresh number
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SDRAM_SetAutoRefreshNumber(SDRAM_HandleTypeDef *hsdram, uint32_t AutoRefreshNumber)
@@ -800,7 +798,7 @@
/**
* @brief Returns the SDRAM memory current mode.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
* @retval The SDRAM memory mode.
*/
@@ -831,7 +829,7 @@
/**
* @brief Returns the SDRAM state.
- * @param hsdram: pointer to a SDRAM_HandleTypeDef structure that contains
+ * @param hsdram pointer to a SDRAM_HandleTypeDef structure that contains
* the configuration information for SDRAM module.
* @retval HAL state
*/
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sdram.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sdram.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_sdram.h * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief Header file of SDRAM HAL module. ****************************************************************************** * @attention @@ -102,7 +100,7 @@ */ /** @brief Reset SDRAM handle state - * @param __HANDLE__: specifies the SDRAM handle. + * @param __HANDLE__ specifies the SDRAM handle. * @retval None */ #define __HAL_SDRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SDRAM_STATE_RESET)
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_smartcard.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_smartcard.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_smartcard.c * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief SMARTCARD HAL module driver. * This file provides firmware functions to manage the following * functionalities of the SMARTCARD peripheral: @@ -1295,7 +1293,7 @@ /** * @brief Handle SMARTCARD interrupt requests. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * @retval None */ @@ -1659,7 +1657,7 @@ /** * @brief Configure the SMARTCARD associated USART peripheral. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * @retval None */ @@ -1757,7 +1755,7 @@ /** * @brief Configure the SMARTCARD associated USART peripheral advanced features. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * @retval None */ @@ -1819,7 +1817,7 @@ /** * @brief Check the SMARTCARD Idle State. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * @retval HAL status */ @@ -2148,7 +2146,7 @@ /** * @brief Send an amount of data in non-blocking mode. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * Function called under interruption only, once * interruptions have been enabled by HAL_SMARTCARD_Transmit_IT() @@ -2221,7 +2219,7 @@ /** * @brief Receive an amount of data in non-blocking mode. - * @param hsmartcard: Pointer to a SMARTCARD_HandleTypeDef structure that contains + * @param hsmartcard Pointer to a SMARTCARD_HandleTypeDef structure that contains * the configuration information for the specified SMARTCARD module. * Function called under interruption only, once * interruptions have been enabled by HAL_SMARTCARD_Receive_IT().
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_smartcard.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_smartcard.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_smartcard.h
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief Header file of SMARTCARD HAL module.
******************************************************************************
* @attention
@@ -589,23 +587,23 @@
*/
/** @brief Reset SMARTCARD handle state
- * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
* The Handle Instance which can be USART1 or USART2
* @retval None
*/
#define __HAL_SMARTCARD_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMARTCARD_STATE_RESET)
/** @brief Flush the Smartcard DR register
- * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
* The Handle Instance which can be USART1 or USART2.
* @retval None
*/
#define __HAL_SMARTCARD_FLUSH_DRREGISTER(__HANDLE__) (__HAL_SMARTCARD_SEND_REQ((__HANDLE__), SMARTCARD_RXDATA_FLUSH_REQUEST))
/** @brief Checks whether the specified Smartcard flag is set or not.
- * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
* The Handle Instance which can be USART1 or USART2.
- * @param __FLAG__: specifies the flag to check.
+ * @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg SMARTCARD_FLAG_REACK: Receive enable acknowledge flag
* @arg SMARTCARD_FLAG_TEACK: Transmit enable acknowledge flag
@@ -624,8 +622,8 @@
#define __HAL_SMARTCARD_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
/** @brief Clear the specified SMARTCARD pending flag.
- * @param __HANDLE__: specifies the SMARTCARD Handle.
- * @param __FLAG__: specifies the flag to check.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
+ * @param __FLAG__ specifies the flag to check.
* This parameter can be any combination of the following values:
* @arg @ref SMARTCARD_CLEAR_PEF Parity error clear flag
* @arg @ref SMARTCARD_CLEAR_FEF Framing error clear flag
@@ -643,40 +641,40 @@
#define __HAL_SMARTCARD_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
/** @brief Clear the SMARTCARD PE pending flag.
- * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
* @retval None
*/
#define __HAL_SMARTCARD_CLEAR_PEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_PEF)
/** @brief Clear the SMARTCARD FE pending flag.
- * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
* @retval None
*/
#define __HAL_SMARTCARD_CLEAR_FEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_FEF)
/** @brief Clear the SMARTCARD NE pending flag.
- * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
* @retval None
*/
#define __HAL_SMARTCARD_CLEAR_NEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_NEF)
/** @brief Clear the SMARTCARD ORE pending flag.
- * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
* @retval None
*/
#define __HAL_SMARTCARD_CLEAR_OREFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_OREF)
/** @brief Clear the SMARTCARD IDLE pending flag.
- * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
* @retval None
*/
#define __HAL_SMARTCARD_CLEAR_IDLEFLAG(__HANDLE__) __HAL_SMARTCARD_CLEAR_FLAG((__HANDLE__), SMARTCARD_CLEAR_IDLEF)
/** @brief Enables the specified SmartCard interrupt.
- * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
* The Handle Instance which can be USART1 or USART2.
- * @param __INTERRUPT__: specifies the SMARTCARD interrupt to enable.
+ * @param __INTERRUPT__ specifies the SMARTCARD interrupt to enable.
* This parameter can be one of the following values:
* @arg SMARTCARD_IT_EOBF: End Of Block interrupt
* @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt
@@ -691,9 +689,9 @@
((((uint8_t)(__INTERRUPT__)) >> 5U) == 2U)? ((__HANDLE__)->Instance->CR2 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))): \
((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
/** @brief Disables the specified SmartCard interrupt.
- * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
* The Handle Instance which can be USART1 or USART2.
- * @param __INTERRUPT__: specifies the SMARTCARD interrupt to enable.
+ * @param __INTERRUPT__ specifies the SMARTCARD interrupt to enable.
* This parameter can be one of the following values:
* @arg SMARTCARD_IT_EOBF: End Of Block interrupt
* @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt
@@ -709,9 +707,9 @@
((__HANDLE__)->Instance->CR3 &= ~ ((uint32_t)1U << ((__INTERRUPT__) & SMARTCARD_IT_MASK))))
/** @brief Checks whether the specified SmartCard interrupt has occurred or not.
- * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
* The Handle Instance which can be USART1 or USART2.
- * @param __IT__: specifies the SMARTCARD interrupt to check.
+ * @param __IT__ specifies the SMARTCARD interrupt to check.
* This parameter can be one of the following values:
* @arg SMARTCARD_IT_EOBF: End Of Block interrupt
* @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt
@@ -727,9 +725,9 @@
#define __HAL_SMARTCARD_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1U << ((__IT__)>> 0x08U)))
/** @brief Checks whether the specified SmartCard interrupt interrupt source is enabled.
- * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
* The Handle Instance which can be USART1 or USART2.
- * @param __IT__: specifies the SMARTCARD interrupt source to check.
+ * @param __IT__ specifies the SMARTCARD interrupt source to check.
* This parameter can be one of the following values:
* @arg SMARTCARD_IT_EOBF: End Of Block interrupt
* @arg SMARTCARD_IT_RTOF: Receive TimeOut interrupt
@@ -748,9 +746,9 @@
/** @brief Clears the specified SMARTCARD ISR flag, in setting the proper ICR register flag.
- * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
* The Handle Instance which can be USART1 or USART2.
- * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
+ * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
* to clear the corresponding interrupt
* This parameter can be one of the following values:
* @arg USART_CLEAR_PEF: Parity Error Clear Flag
@@ -765,9 +763,9 @@
#define __HAL_SMARTCARD_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
/** @brief Set a specific SMARTCARD request flag.
- * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
* The Handle Instance which can be USART1 or USART2.
- * @param __REQ__: specifies the request flag to set
+ * @param __REQ__ specifies the request flag to set
* This parameter can be one of the following values:
* @arg SMARTCARD_RXDATA_FLUSH_REQUEST: Receive Data flush Request
* @arg SMARTCARD_TXDATA_FLUSH_REQUEST: Transmit data flush Request
@@ -777,23 +775,23 @@
#define __HAL_SMARTCARD_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__))
/** @brief Enable the USART associated to the SMARTCARD Handle
- * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
* The Handle Instance which can be USART1 or USART2.
* @retval None
*/
#define __HAL_SMARTCARD_ENABLE(__HANDLE__) ( (__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
/** @brief Disable the USART associated to the SMARTCARD Handle
- * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
* The Handle Instance which can be USART1 or USART2.
* @retval None
*/
#define __HAL_SMARTCARD_DISABLE(__HANDLE__) ( (__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
/** @brief Macros to enable or disable the SmartCard DMA request.
- * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
* The Handle Instance which can be USART1 or USART2.
- * @param __REQUEST__: specifies the SmartCard DMA request.
+ * @param __REQUEST__ specifies the SmartCard DMA request.
* This parameter can be one of the following values:
* @arg SMARTCARD_DMAREQ_TX: SmartCard DMA transmit request
* @arg SMARTCARD_DMAREQ_RX: SmartCard DMA receive request
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_smartcard_ex.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_smartcard_ex.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_smartcard_ex.c * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief SMARTCARD HAL module driver. * * This file provides extended firmware functions to manage the following @@ -96,8 +94,8 @@ /** * @brief Update on the fly the SMARTCARD block length in RTOR register - * @param hsc: SMARTCARD handle - * @param BlockLength: SMARTCARD block length (8-bit long at most) + * @param hsc SMARTCARD handle + * @param BlockLength SMARTCARD block length (8-bit long at most) * @retval None */ void HAL_SMARTCARDEx_BlockLength_Config(SMARTCARD_HandleTypeDef *hsc, uint8_t BlockLength) @@ -107,8 +105,8 @@ /** * @brief Update on the fly the receiver timeout value in RTOR register - * @param hsc: SMARTCARD handle - * @param TimeOutValue: receiver timeout value in number of baud blocks. The timeout + * @param hsc SMARTCARD handle + * @param TimeOutValue receiver timeout value in number of baud blocks. The timeout * value must be less or equal to 0x0FFFFFFFF. * @retval None */ @@ -120,7 +118,7 @@ /** * @brief Enable the SMARTCARD receiver timeout feature - * @param hsc: SMARTCARD handle + * @param hsc SMARTCARD handle * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARDEx_EnableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsc) @@ -143,7 +141,7 @@ /** * @brief Disable the SMARTCARD receiver timeout feature - * @param hsc: SMARTCARD handle + * @param hsc SMARTCARD handle * @retval HAL status */ HAL_StatusTypeDef HAL_SMARTCARDEx_DisableReceiverTimeOut(SMARTCARD_HandleTypeDef *hsc)
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_smartcard_ex.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_smartcard_ex.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_smartcard_ex.h
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief Header file of SMARTCARD HAL module.
******************************************************************************
* @attention
@@ -136,8 +134,8 @@
/* Exported macro ------------------------------------------------------------*/
/** @brief Reports the SMARTCARD clock source.
- * @param __HANDLE__: specifies the USART Handle
- * @param __CLOCKSOURCE__ : output variable
+ * @param __HANDLE__ specifies the USART Handle
+ * @param __CLOCKSOURCE__ output variable
* @retval the USART clocking source, written in __CLOCKSOURCE__.
*/
#define SMARTCARD_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
@@ -225,7 +223,7 @@
} while(0)
/** @brief Set the Transmission Completion flag
- * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
* @note If TCBGT (Transmission Complete Before Guard Time) flag is not available or if
* AdvancedInit.TxCompletionIndication is not already filled, the latter is forced
* to SMARTCARD_TC (transmission completion indication when guard time has elapsed).
@@ -251,7 +249,7 @@
#endif
/** @brief Return the transmission completion flag.
- * @param __HANDLE__: specifies the SMARTCARD Handle.
+ * @param __HANDLE__ specifies the SMARTCARD Handle.
* @note Based on AdvancedInit.TxCompletionIndication setting, return TC or TCBGT flag.
* When TCBGT flag (Transmission Complete Before Guard Time) is not available, TC flag is
* reported.
@@ -266,7 +264,7 @@
/**
* @brief Ensure that SMARTCARD frame transmission completion used flag is valid.
- * @param __TXCOMPLETE__: SMARTCARD frame transmission completion used flag.
+ * @param __TXCOMPLETE__ SMARTCARD frame transmission completion used flag.
* @retval SET (__TXCOMPLETE__ is valid) or RESET (__TXCOMPLETE__ is invalid)
*/
#if defined(USART_TCBGT_SUPPORT)
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_smbus.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_smbus.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_smbus.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 30-December-2016
* @brief SMBUS HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the System Management Bus (SMBus) peripheral,
@@ -172,6 +170,8 @@
static void SMBUS_ConvertOtherXferOptions(SMBUS_HandleTypeDef *hsmbus);
+static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus);
+
static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
/**
* @}
@@ -215,6 +215,9 @@
(+) Call the function HAL_SMBUS_DeInit() to restore the default configuration
of the selected SMBUSx peripheral.
+ (+) Enable/Disable Analog/Digital filters with HAL_SMBUS_ConfigAnalogFilter() and
+ HAL_SMBUS_ConfigDigitalFilter().
+
@endverbatim
* @{
*/
@@ -229,7 +232,7 @@
HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus)
{
/* Check the SMBUS handle allocation */
- if(hsmbus == NULL)
+ if (hsmbus == NULL)
{
return HAL_ERROR;
}
@@ -247,7 +250,7 @@
assert_param(IS_SMBUS_PEC(hsmbus->Init.PacketErrorCheckMode));
assert_param(IS_SMBUS_PERIPHERAL_MODE(hsmbus->Init.PeripheralMode));
- if(hsmbus->State == HAL_SMBUS_STATE_RESET)
+ if (hsmbus->State == HAL_SMBUS_STATE_RESET)
{
/* Allocate lock resource and initialize it */
hsmbus->Lock = HAL_UNLOCKED;
@@ -275,9 +278,9 @@
/* Configure SMBUSx: Own Address1 and ack own address1 mode */
hsmbus->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
- if(hsmbus->Init.OwnAddress1 != 0U)
+ if (hsmbus->Init.OwnAddress1 != 0U)
{
- if(hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT)
+ if (hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_7BIT)
{
hsmbus->Instance->OAR1 = (I2C_OAR1_OA1EN | hsmbus->Init.OwnAddress1);
}
@@ -289,7 +292,7 @@
/*---------------------------- SMBUSx CR2 Configuration ------------------------*/
/* Configure SMBUSx: Addressing Master mode */
- if(hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_10BIT)
+ if (hsmbus->Init.AddressingMode == SMBUS_ADDRESSINGMODE_10BIT)
{
hsmbus->Instance->CR2 = (I2C_CR2_ADD10);
}
@@ -306,8 +309,8 @@
hsmbus->Instance->CR1 = (hsmbus->Init.GeneralCallMode | hsmbus->Init.NoStretchMode | hsmbus->Init.PacketErrorCheckMode | hsmbus->Init.PeripheralMode | hsmbus->Init.AnalogFilter);
/* Enable Slave Byte Control only in case of Packet Error Check is enabled and SMBUS Peripheral is set in Slave mode */
- if( (hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE)
- && ( (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP) ) )
+ if ((hsmbus->Init.PacketErrorCheckMode == SMBUS_PEC_ENABLE)
+ && ((hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE) || (hsmbus->Init.PeripheralMode == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP)))
{
hsmbus->Instance->CR1 |= I2C_CR1_SBC;
}
@@ -331,7 +334,7 @@
HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus)
{
/* Check the SMBUS handle allocation */
- if(hsmbus == NULL)
+ if (hsmbus == NULL)
{
return HAL_ERROR;
}
@@ -351,7 +354,7 @@
hsmbus->PreviousState = HAL_SMBUS_STATE_RESET;
hsmbus->State = HAL_SMBUS_STATE_RESET;
- /* Release Lock */
+ /* Release Lock */
__HAL_UNLOCK(hsmbus);
return HAL_OK;
@@ -390,6 +393,104 @@
}
/**
+ * @brief Configure Analog noise filter.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param AnalogFilter This parameter can be one of the following values:
+ * @arg @ref SMBUS_ANALOGFILTER_ENABLE
+ * @arg @ref SMBUS_ANALOGFILTER_DISABLE
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter)
+{
+ /* Check the parameters */
+ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
+ assert_param(IS_SMBUS_ANALOG_FILTER(AnalogFilter));
+
+ if (hsmbus->State == HAL_SMBUS_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+ /* Disable the selected SMBUS peripheral */
+ __HAL_SMBUS_DISABLE(hsmbus);
+
+ /* Reset ANOFF bit */
+ hsmbus->Instance->CR1 &= ~(I2C_CR1_ANFOFF);
+
+ /* Set analog filter bit*/
+ hsmbus->Instance->CR1 |= AnalogFilter;
+
+ __HAL_SMBUS_ENABLE(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
+ * @brief Configure Digital noise filter.
+ * @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
+ * the configuration information for the specified SMBUS.
+ * @param DigitalFilter Coefficient of digital noise filter between Min_Data=0x00 and Max_Data=0x0F.
+ * @retval HAL status
+ */
+HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter)
+{
+ uint32_t tmpreg = 0U;
+
+ /* Check the parameters */
+ assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
+ assert_param(IS_SMBUS_DIGITAL_FILTER(DigitalFilter));
+
+ if (hsmbus->State == HAL_SMBUS_STATE_READY)
+ {
+ /* Process Locked */
+ __HAL_LOCK(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_BUSY;
+
+ /* Disable the selected SMBUS peripheral */
+ __HAL_SMBUS_DISABLE(hsmbus);
+
+ /* Get the old register value */
+ tmpreg = hsmbus->Instance->CR1;
+
+ /* Reset I2C DNF bits [11:8] */
+ tmpreg &= ~(I2C_CR1_DNF);
+
+ /* Set I2Cx DNF coefficient */
+ tmpreg |= DigitalFilter << I2C_CR1_DNF_Pos;
+
+ /* Store the new register value */
+ hsmbus->Instance->CR1 = tmpreg;
+
+ __HAL_SMBUS_ENABLE(hsmbus);
+
+ hsmbus->State = HAL_SMBUS_STATE_READY;
+
+ /* Process Unlocked */
+ __HAL_UNLOCK(hsmbus);
+
+ return HAL_OK;
+ }
+ else
+ {
+ return HAL_BUSY;
+ }
+}
+
+/**
* @}
*/
@@ -418,7 +519,7 @@
(++) HAL_SMBUS_Master_Receive_IT()
(++) HAL_SMBUS_Slave_Transmit_IT()
(++) HAL_SMBUS_Slave_Receive_IT()
- (++) HAL_SMBUS_EnableListen_IT()
+ (++) HAL_SMBUS_EnableListen_IT() or alias HAL_SMBUS_EnableListen_IT()
(++) HAL_SMBUS_DisableListen_IT()
(++) HAL_SMBUS_EnableAlert_IT()
(++) HAL_SMBUS_DisableAlert_IT()
@@ -440,8 +541,8 @@
* @brief Transmit in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
* @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * @param DevAddress Target device address which contain device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
@@ -452,7 +553,7 @@
/* Check the parameters */
assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
- if(hsmbus->State == HAL_SMBUS_STATE_READY)
+ if (hsmbus->State == HAL_SMBUS_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hsmbus);
@@ -466,12 +567,12 @@
/* In case of Quick command, remove autoend mode */
/* Manage the stop generation by software */
- if(hsmbus->pBuffPtr == NULL)
+ if (hsmbus->pBuffPtr == NULL)
{
hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
}
- if(Size > MAX_NBYTE_SIZE)
+ if (Size > MAX_NBYTE_SIZE)
{
hsmbus->XferSize = MAX_NBYTE_SIZE;
}
@@ -482,17 +583,17 @@
/* Send Slave Address */
/* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
- if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) )
+ if ((hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount))
{
- SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE);
+ SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_WRITE);
}
else
{
/* If transfer direction not change, do not generate Restart Condition */
/* Mean Previous state is same as current state */
- if((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0))
+ if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0))
{
- SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
}
/* Else transfer direction change, so generate Restart with new transfer direction */
else
@@ -501,12 +602,12 @@
SMBUS_ConvertOtherXferOptions(hsmbus);
/* Handle Transfer */
- SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE);
+ SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_WRITE);
}
/* If PEC mode is enable, size to transmit manage by SW part should be Size-1 byte, corresponding to PEC byte */
/* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
- if(SMBUS_GET_PEC_MODE(hsmbus) != RESET)
+ if (SMBUS_GET_PEC_MODE(hsmbus) != RESET)
{
hsmbus->XferSize--;
hsmbus->XferCount--;
@@ -533,8 +634,8 @@
* @brief Receive in master/host SMBUS mode an amount of data in non-blocking mode with Interrupt.
* @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * @param DevAddress Target device address which contain device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param pData Pointer to data buffer
* @param Size Amount of data to be sent
* @param XferOptions Options of Transfer, value of @ref SMBUS_XferOptions_definition
@@ -545,7 +646,7 @@
/* Check the parameters */
assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
- if(hsmbus->State == HAL_SMBUS_STATE_READY)
+ if (hsmbus->State == HAL_SMBUS_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hsmbus);
@@ -560,12 +661,12 @@
/* In case of Quick command, remove autoend mode */
/* Manage the stop generation by software */
- if(hsmbus->pBuffPtr == NULL)
+ if (hsmbus->pBuffPtr == NULL)
{
hsmbus->XferOptions &= ~SMBUS_AUTOEND_MODE;
}
- if(Size > MAX_NBYTE_SIZE)
+ if (Size > MAX_NBYTE_SIZE)
{
hsmbus->XferSize = MAX_NBYTE_SIZE;
}
@@ -576,17 +677,17 @@
/* Send Slave Address */
/* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
- if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) )
+ if ((hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount))
{
- SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ);
+ SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_GENERATE_START_READ);
}
else
{
/* If transfer direction not change, do not generate Restart Condition */
/* Mean Previous state is same as current state */
- if((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0))
+ if ((hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX) && (IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(hsmbus->XferOptions) == 0))
{
- SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
}
/* Else transfer direction change, so generate Restart with new transfer direction */
else
@@ -595,7 +696,7 @@
SMBUS_ConvertOtherXferOptions(hsmbus);
/* Handle Transfer */
- SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ);
+ SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_GENERATE_START_READ);
}
}
@@ -620,24 +721,24 @@
* @note This abort can be called only if state is ready
* @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * @param DevAddress Target device address which contain device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress)
{
- if(hsmbus->State == HAL_SMBUS_STATE_READY)
+ if (hsmbus->State == HAL_SMBUS_STATE_READY)
{
/* Process Locked */
__HAL_LOCK(hsmbus);
/* Keep the same state as previous */
/* to perform as well the call of the corresponding end of transfer callback */
- if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+ if (hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_TX)
{
hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_TX;
}
- else if(hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+ else if (hsmbus->PreviousState == HAL_SMBUS_STATE_MASTER_BUSY_RX)
{
hsmbus->State = HAL_SMBUS_STATE_MASTER_BUSY_RX;
}
@@ -659,11 +760,11 @@
/* Note : The SMBUS interrupts must be enabled after unlocking current process
to avoid the risk of SMBUS interrupt handle execution before current
process unlock */
- if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+ if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
{
SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_TX);
}
- else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+ else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
{
SMBUS_Enable_IRQ(hsmbus, SMBUS_IT_RX);
}
@@ -690,9 +791,9 @@
/* Check the parameters */
assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
- if(hsmbus->State == HAL_SMBUS_STATE_LISTEN)
+ if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
{
- if((pData == NULL) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -720,7 +821,7 @@
/* Convert OTHER_xxx XferOptions if any */
SMBUS_ConvertOtherXferOptions(hsmbus);
- if(Size > MAX_NBYTE_SIZE)
+ if (Size > MAX_NBYTE_SIZE)
{
hsmbus->XferSize = MAX_NBYTE_SIZE;
}
@@ -730,18 +831,18 @@
}
/* Set NBYTES to write and reload if size > MAX_NBYTE_SIZE and generate RESTART */
- if( (hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount) )
+ if ((hsmbus->XferSize == MAX_NBYTE_SIZE) && (hsmbus->XferSize < hsmbus->XferCount))
{
- SMBUS_TransferConfig(hsmbus, 0U,hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE), SMBUS_NO_STARTSTOP);
}
else
{
/* Set NBYTE to transmit */
- SMBUS_TransferConfig(hsmbus, 0U,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
/* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
/* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
- if(SMBUS_GET_PEC_MODE(hsmbus) != RESET)
+ if (SMBUS_GET_PEC_MODE(hsmbus) != RESET)
{
hsmbus->XferSize--;
hsmbus->XferCount--;
@@ -750,7 +851,7 @@
/* Clear ADDR flag after prepare the transfer parameters */
/* This action will generate an acknowledge to the HOST */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR);
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR);
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
@@ -783,9 +884,9 @@
/* Check the parameters */
assert_param(IS_SMBUS_TRANSFER_OPTIONS_REQUEST(XferOptions));
- if(hsmbus->State == HAL_SMBUS_STATE_LISTEN)
+ if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
{
- if((pData == NULL) || (Size == 0U))
+ if ((pData == NULL) || (Size == 0U))
{
return HAL_ERROR;
}
@@ -819,7 +920,7 @@
/* no need to set RELOAD bit mode, a ACK will be automatically generated in that case */
/* else need to set RELOAD bit mode to generate an automatic ACK at each byte Received */
/* This RELOAD bit will be reset for last BYTE to be receive in SMBUS_Slave_ISR */
- if((hsmbus->XferSize == 1U) || ((hsmbus->XferSize == 2U) && (SMBUS_GET_PEC_MODE(hsmbus) != RESET)))
+ if ((hsmbus->XferSize == 1U) || ((hsmbus->XferSize == 2U) && (SMBUS_GET_PEC_MODE(hsmbus) != RESET)))
{
SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
}
@@ -830,7 +931,7 @@
/* Clear ADDR flag after prepare the transfer parameters */
/* This action will generate an acknowledge to the HOST */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR);
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR);
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
@@ -874,7 +975,7 @@
HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus)
{
/* Disable Address listen mode only if a transfer is not ongoing */
- if(hsmbus->State == HAL_SMBUS_STATE_LISTEN)
+ if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
{
hsmbus->State = HAL_SMBUS_STATE_READY;
@@ -929,8 +1030,8 @@
* @brief Check if target device is ready for communication.
* @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
- * @param DevAddress Target device address: The device 7 bits address value
- * in datasheet must be shift at right before call interface
+ * @param DevAddress Target device address which contain device 7 bits address value
+ * in datasheet must be shifted to the left before calling the interface
* @param Trials Number of trials
* @param Timeout Timeout duration
* @retval HAL status
@@ -941,9 +1042,9 @@
__IO uint32_t SMBUS_Trials = 0U;
- if(hsmbus->State == HAL_SMBUS_STATE_READY)
+ if (hsmbus->State == HAL_SMBUS_STATE_READY)
{
- if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BUSY) != RESET)
+ if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BUSY) != RESET)
{
return HAL_BUSY;
}
@@ -957,16 +1058,16 @@
do
{
/* Generate Start */
- hsmbus->Instance->CR2 = SMBUS_GENERATE_START(hsmbus->Init.AddressingMode,DevAddress);
+ hsmbus->Instance->CR2 = SMBUS_GENERATE_START(hsmbus->Init.AddressingMode, DevAddress);
/* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
/* Wait until STOPF flag is set or a NACK flag is set*/
tickstart = HAL_GetTick();
- while((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) == RESET) && (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET) && (hsmbus->State != HAL_SMBUS_STATE_TIMEOUT))
+ while ((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) == RESET) && (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET) && (hsmbus->State != HAL_SMBUS_STATE_TIMEOUT))
{
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+ if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
{
/* Device is ready */
hsmbus->State = HAL_SMBUS_STATE_READY;
@@ -982,7 +1083,7 @@
if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) == RESET)
{
/* Wait until STOPF flag is reset */
- if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
+ if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -1001,7 +1102,7 @@
else
{
/* Wait until STOPF flag is reset */
- if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
+ if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -1020,7 +1121,7 @@
hsmbus->Instance->CR2 |= I2C_CR2_STOP;
/* Wait until STOPF flag is reset */
- if(SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
+ if (SMBUS_WaitOnFlagUntilTimeout(hsmbus, SMBUS_FLAG_STOPF, RESET, Timeout) != HAL_OK)
{
return HAL_TIMEOUT;
}
@@ -1028,7 +1129,8 @@
/* Clear STOP Flag */
__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
}
- }while(SMBUS_Trials < Trials);
+ }
+ while (SMBUS_Trials < Trials);
hsmbus->State = HAL_SMBUS_STATE_READY;
@@ -1065,7 +1167,7 @@
tmpisrvalue = SMBUS_GET_ISR_REG(hsmbus);
/* SMBUS in mode Transmitter ---------------------------------------------------*/
- if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI| SMBUS_IT_STOPI| SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET))
+ if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TXIS) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)) != RESET))
{
/* Slave mode selected */
if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
@@ -1073,14 +1175,14 @@
SMBUS_Slave_ISR(hsmbus);
}
/* Master mode selected */
- else if((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_TX) == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+ else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_TX) == HAL_SMBUS_STATE_MASTER_BUSY_TX)
{
SMBUS_Master_ISR(hsmbus);
}
}
/* SMBUS in mode Receiver ----------------------------------------------------*/
- if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI| SMBUS_IT_STOPI| SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET))
+ if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_RXNE) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TCR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_TC) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET)) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, (SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI)) != RESET))
{
/* Slave mode selected */
if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
@@ -1088,15 +1190,15 @@
SMBUS_Slave_ISR(hsmbus);
}
/* Master mode selected */
- else if((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_RX) == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+ else if ((hsmbus->State & HAL_SMBUS_STATE_MASTER_BUSY_RX) == HAL_SMBUS_STATE_MASTER_BUSY_RX)
{
SMBUS_Master_ISR(hsmbus);
}
}
- /* SMBUS in mode Listener Only --------------------------------------------------*/
+ /* SMBUS in mode Listener Only --------------------------------------------------*/
if (((SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_ADDR) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_STOPF) != RESET) || (SMBUS_CHECK_FLAG(tmpisrvalue, SMBUS_FLAG_AF) != RESET))
- && ((__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ADDRI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_STOPI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_NACKI) != RESET)))
+ && ((__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ADDRI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_STOPI) != RESET) || (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_NACKI) != RESET)))
{
if (hsmbus->State == HAL_SMBUS_STATE_LISTEN)
{
@@ -1113,79 +1215,7 @@
*/
void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus)
{
- /* SMBUS Bus error interrupt occurred ------------------------------------*/
- if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_BERR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
- {
- hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR;
-
- /* Clear BERR flag */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_BERR);
- }
-
- /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/
- if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_OVR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
- {
- hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR;
-
- /* Clear OVR flag */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_OVR);
- }
-
- /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/
- if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ARLO) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
- {
- hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO;
-
- /* Clear ARLO flag */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ARLO);
- }
-
- /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/
- if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
- {
- hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT;
-
- /* Clear TIMEOUT flag */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT);
- }
-
- /* SMBUS Alert error interrupt occurred -----------------------------------------------*/
- if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ALERT) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
- {
- hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT;
-
- /* Clear ALERT flag */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
- }
-
- /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/
- if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_PECERR) != RESET) && (__HAL_SMBUS_GET_IT_SOURCE(hsmbus, SMBUS_IT_ERRI) != RESET))
- {
- hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR;
-
- /* Clear PEC error flag */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR);
- }
-
- /* Call the Error Callback in case of Error detected */
- if((hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE)&&(hsmbus->ErrorCode != HAL_SMBUS_ERROR_ACKF))
- {
- /* Do not Reset the HAL state in case of ALERT error */
- if((hsmbus->ErrorCode & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT)
- {
- if(((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
- || ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX))
- {
- /* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX */
- /* keep HAL_SMBUS_STATE_LISTEN if set */
- hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
- hsmbus->State = HAL_SMBUS_STATE_LISTEN;
- }
- }
-
- /* Call the Error callback to prevent upper layer */
- HAL_SMBUS_ErrorCallback(hsmbus);
- }
+ SMBUS_ITErrorHandler(hsmbus);
}
/**
@@ -1255,8 +1285,8 @@
* @brief Slave Address Match callback.
* @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
* the configuration information for the specified SMBUS.
- * @param TransferDirection: Master request Transfer Direction (Write/Read)
- * @param AddrMatchCode: Address Match Code
+ * @param TransferDirection Master request Transfer Direction (Write/Read)
+ * @param AddrMatchCode Address Match Code
* @retval None
*/
__weak void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode)
@@ -1371,7 +1401,7 @@
/* Process Locked */
__HAL_LOCK(hsmbus);
- if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET)
+ if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET)
{
/* Clear NACK Flag */
__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
@@ -1383,13 +1413,16 @@
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
- /* Call the Error callback to prevent upper layer */
+ /* Call the Error callback to inform upper layer */
HAL_SMBUS_ErrorCallback(hsmbus);
}
- else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET)
+ else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET)
{
+ /* Check and treat errors if errors occurs during STOP process */
+ SMBUS_ITErrorHandler(hsmbus);
+
/* Call the corresponding callback to inform upper layer of End of Transfer */
- if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+ if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
{
/* Disable Interrupt */
SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
@@ -1415,15 +1448,15 @@
HAL_SMBUS_MasterTxCpltCallback(hsmbus);
}
- else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+ else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
{
/* Store Last receive data if any */
- if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
+ if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
{
/* Read data from RXDR */
(*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
- if((hsmbus->XferSize > 0U))
+ if ((hsmbus->XferSize > 0U))
{
hsmbus->XferSize--;
hsmbus->XferCount--;
@@ -1448,27 +1481,27 @@
HAL_SMBUS_MasterRxCpltCallback(hsmbus);
}
}
- else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
+ else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
{
/* Read data from RXDR */
(*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
hsmbus->XferSize--;
hsmbus->XferCount--;
}
- else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
+ else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
{
/* Write data to TXDR */
hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++);
hsmbus->XferSize--;
hsmbus->XferCount--;
}
- else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET)
+ else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET)
{
- if((hsmbus->XferSize == 0U)&&(hsmbus->XferCount != 0U))
+ if ((hsmbus->XferSize == 0U) && (hsmbus->XferCount != 0U))
{
DevAddress = (hsmbus->Instance->CR2 & I2C_CR2_SADD);
- if(hsmbus->XferCount > MAX_NBYTE_SIZE)
+ if (hsmbus->XferCount > MAX_NBYTE_SIZE)
{
SMBUS_TransferConfig(hsmbus, DevAddress, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
hsmbus->XferSize = MAX_NBYTE_SIZE;
@@ -1476,23 +1509,23 @@
else
{
hsmbus->XferSize = hsmbus->XferCount;
- SMBUS_TransferConfig(hsmbus,DevAddress,hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, DevAddress, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
/* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
/* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
- if(SMBUS_GET_PEC_MODE(hsmbus) != RESET)
+ if (SMBUS_GET_PEC_MODE(hsmbus) != RESET)
{
hsmbus->XferSize--;
hsmbus->XferCount--;
}
}
}
- else if((hsmbus->XferSize == 0U)&&(hsmbus->XferCount == 0U))
+ else if ((hsmbus->XferSize == 0U) && (hsmbus->XferCount == 0U))
{
/* Call TxCpltCallback() if no stop mode is set */
- if(SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
+ if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
{
/* Call the corresponding callback to inform upper layer of End of Transfer */
- if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+ if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
{
/* Disable Interrupt */
SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
@@ -1504,7 +1537,7 @@
HAL_SMBUS_MasterTxCpltCallback(hsmbus);
}
- else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+ else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
{
SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
hsmbus->PreviousState = hsmbus->State;
@@ -1518,24 +1551,24 @@
}
}
}
- else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TC) != RESET)
+ else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TC) != RESET)
{
- if(hsmbus->XferCount == 0U)
+ if (hsmbus->XferCount == 0U)
{
/* Specific use case for Quick command */
- if(hsmbus->pBuffPtr == NULL)
+ if (hsmbus->pBuffPtr == NULL)
{
/* Generate a Stop command */
hsmbus->Instance->CR2 |= I2C_CR2_STOP;
}
/* Call TxCpltCallback() if no stop mode is set */
- else if(SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
+ else if (SMBUS_GET_STOP_MODE(hsmbus) != SMBUS_AUTOEND_MODE)
{
/* No Generate Stop, to permit restart mode */
/* The stop will be done at the end of transfer, when SMBUS_AUTOEND_MODE enable */
/* Call the corresponding callback to inform upper layer of End of Transfer */
- if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
+ if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_TX)
{
/* Disable Interrupt */
SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_TX);
@@ -1547,7 +1580,7 @@
HAL_SMBUS_MasterTxCpltCallback(hsmbus);
}
- else if(hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
+ else if (hsmbus->State == HAL_SMBUS_STATE_MASTER_BUSY_RX)
{
SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
hsmbus->PreviousState = hsmbus->State;
@@ -1581,13 +1614,13 @@
/* Process Locked */
__HAL_LOCK(hsmbus);
- if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET)
+ if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_AF) != RESET)
{
/* Check that SMBUS transfer finished */
/* if yes, normal usecase, a NACK is sent by the HOST when Transfer is finished */
/* Mean XferCount == 0*/
/* So clear Flag NACKF only */
- if(hsmbus->XferCount == 0U)
+ if (hsmbus->XferCount == 0U)
{
/* Clear NACK Flag */
__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_AF);
@@ -1616,11 +1649,11 @@
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
- /* Call the Error callback to prevent upper layer */
+ /* Call the Error callback to inform upper layer */
HAL_SMBUS_ErrorCallback(hsmbus);
}
}
- else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ADDR) != RESET)
+ else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_ADDR) != RESET)
{
TransferDirection = SMBUS_GET_DIR(hsmbus);
SlaveAddrCode = SMBUS_GET_ADDR_MATCH(hsmbus);
@@ -1635,24 +1668,24 @@
/* Call Slave Addr callback */
HAL_SMBUS_AddrCallback(hsmbus, TransferDirection, SlaveAddrCode);
}
- else if((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) || (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET))
+ else if ((__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET) || (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TCR) != RESET))
{
- if( (hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
+ if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX)
{
/* Read data from RXDR */
(*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
hsmbus->XferSize--;
hsmbus->XferCount--;
- if(hsmbus->XferCount == 1U)
+ if (hsmbus->XferCount == 1U)
{
/* Receive last Byte, can be PEC byte in case of PEC BYTE enabled */
/* or only the last Byte of Transfer */
/* So reset the RELOAD bit mode */
hsmbus->XferOptions &= ~SMBUS_RELOAD_MODE;
- SMBUS_TransferConfig(hsmbus, 0U ,1U , hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
+ SMBUS_TransferConfig(hsmbus, 0U, 1U, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
}
- else if(hsmbus->XferCount == 0U)
+ else if (hsmbus->XferCount == 0U)
{
/* Last Byte is received, disable Interrupt */
SMBUS_Disable_IRQ(hsmbus, SMBUS_IT_RX);
@@ -1676,11 +1709,11 @@
hsmbus->Instance->CR2 &= ~I2C_CR2_NACK;
}
}
- else if( (hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
+ else if ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
{
- if((hsmbus->XferSize == 0U)&&(hsmbus->XferCount != 0U))
+ if ((hsmbus->XferSize == 0U) && (hsmbus->XferCount != 0U))
{
- if(hsmbus->XferCount > MAX_NBYTE_SIZE)
+ if (hsmbus->XferCount > MAX_NBYTE_SIZE)
{
SMBUS_TransferConfig(hsmbus, 0U, MAX_NBYTE_SIZE, (SMBUS_RELOAD_MODE | (hsmbus->XferOptions & SMBUS_SENDPEC_MODE)), SMBUS_NO_STARTSTOP);
hsmbus->XferSize = MAX_NBYTE_SIZE;
@@ -1691,7 +1724,7 @@
SMBUS_TransferConfig(hsmbus, 0U, hsmbus->XferSize, hsmbus->XferOptions, SMBUS_NO_STARTSTOP);
/* If PEC mode is enable, size to transmit should be Size-1 byte, corresponding to PEC byte */
/* PEC byte is automatically sent by HW block, no need to manage it in Transmit process */
- if(SMBUS_GET_PEC_MODE(hsmbus) != RESET)
+ if (SMBUS_GET_PEC_MODE(hsmbus) != RESET)
{
hsmbus->XferSize--;
hsmbus->XferCount--;
@@ -1700,13 +1733,13 @@
}
}
}
- else if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
+ else if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_TXIS) != RESET)
{
/* Write data to TXDR only if XferCount not reach "0" */
/* A TXIS flag can be set, during STOP treatment */
/* Check if all Data have already been sent */
/* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
- if(hsmbus->XferCount > 0U)
+ if (hsmbus->XferCount > 0U)
{
/* Write data to TXDR */
hsmbus->Instance->TXDR = (*hsmbus->pBuffPtr++);
@@ -1714,7 +1747,7 @@
hsmbus->XferSize--;
}
- if(hsmbus->XferCount == 0U)
+ if (hsmbus->XferCount == 0U)
{
/* Last Byte is Transmitted */
/* Remove HAL_SMBUS_STATE_SLAVE_BUSY_TX, keep only HAL_SMBUS_STATE_LISTEN */
@@ -1731,17 +1764,17 @@
}
/* Check if STOPF is set */
- if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET)
+ if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_STOPF) != RESET)
{
- if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
+ if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) == HAL_SMBUS_STATE_LISTEN)
{
/* Store Last receive data if any */
- if(__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
+ if (__HAL_SMBUS_GET_FLAG(hsmbus, SMBUS_FLAG_RXNE) != RESET)
{
/* Read data from RXDR */
(*hsmbus->pBuffPtr++) = hsmbus->Instance->RXDR;
- if((hsmbus->XferSize > 0U))
+ if ((hsmbus->XferSize > 0U))
{
hsmbus->XferSize--;
hsmbus->XferCount--;
@@ -1763,8 +1796,8 @@
/* Clear STOP Flag */
__HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_STOPF);
- /* Clear ADDR flag */
- __HAL_SMBUS_CLEAR_FLAG(hsmbus,SMBUS_FLAG_ADDR);
+ /* Clear ADDR flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ADDR);
hsmbus->XferOptions = 0U;
hsmbus->PreviousState = hsmbus->State;
@@ -1773,7 +1806,7 @@
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
- /* Call the Listen Complete callback, to prevent upper layer of the end of Listen usecase */
+ /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
HAL_SMBUS_ListenCpltCallback(hsmbus);
}
}
@@ -1794,25 +1827,25 @@
{
uint32_t tmpisr = 0U;
- if((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT)
+ if ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT)
{
/* Enable ERR interrupt */
tmpisr |= SMBUS_IT_ERRI;
}
- if((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
+ if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
{
/* Enable ADDR, STOP interrupt */
tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_ERRI;
}
- if((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
+ if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
{
/* Enable ERR, TC, STOP, NACK, RXI interrupt */
tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI;
}
- if((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
+ if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
{
/* Enable ERR, TC, STOP, NACK, TXI interrupt */
tmpisr |= SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_RXI;
@@ -1836,56 +1869,56 @@
{
uint32_t tmpisr = 0U;
- if( ((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) && (hsmbus->State == HAL_SMBUS_STATE_READY) )
+ if (((InterruptRequest & SMBUS_IT_ALERT) == SMBUS_IT_ALERT) && (hsmbus->State == HAL_SMBUS_STATE_READY))
{
/* Disable ERR interrupt */
tmpisr |= SMBUS_IT_ERRI;
}
- if((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
+ if ((InterruptRequest & SMBUS_IT_TX) == SMBUS_IT_TX)
{
/* Disable TC, STOP, NACK, TXI interrupt */
tmpisr |= SMBUS_IT_TCI | SMBUS_IT_TXI;
- if((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
- && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
+ if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
+ && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
{
/* Disable ERR interrupt */
tmpisr |= SMBUS_IT_ERRI;
}
- if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
+ if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
{
/* Disable STOPI, NACKI */
tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
}
}
- if((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
+ if ((InterruptRequest & SMBUS_IT_RX) == SMBUS_IT_RX)
{
/* Disable TC, STOP, NACK, RXI interrupt */
tmpisr |= SMBUS_IT_TCI | SMBUS_IT_RXI;
- if((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
- && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
+ if ((SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
+ && ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN))
{
/* Disable ERR interrupt */
tmpisr |= SMBUS_IT_ERRI;
}
- if((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
+ if ((hsmbus->State & HAL_SMBUS_STATE_LISTEN) != HAL_SMBUS_STATE_LISTEN)
{
/* Disable STOPI, NACKI */
tmpisr |= SMBUS_IT_STOPI | SMBUS_IT_NACKI;
}
}
- if((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
+ if ((InterruptRequest & SMBUS_IT_ADDR) == SMBUS_IT_ADDR)
{
/* Enable ADDR, STOP interrupt */
tmpisr |= SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI;
- if(SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
+ if (SMBUS_GET_ALERT_ENABLED(hsmbus) == RESET)
{
/* Disable ERR interrupt */
tmpisr |= SMBUS_IT_ERRI;
@@ -1899,6 +1932,92 @@
return HAL_OK;
}
+
+/**
+ * @brief SMBUS interrupts error handler.
+ * @param hsmbus SMBUS handle.
+ * @retval None
+ */
+static void SMBUS_ITErrorHandler(SMBUS_HandleTypeDef *hsmbus)
+{
+ uint32_t itflags = READ_REG(hsmbus->Instance->ISR);
+ uint32_t itsources = READ_REG(hsmbus->Instance->CR1);
+
+ /* SMBUS Bus error interrupt occurred ------------------------------------*/
+ if (((itflags & SMBUS_FLAG_BERR) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
+ {
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BERR;
+
+ /* Clear BERR flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_BERR);
+ }
+
+ /* SMBUS Over-Run/Under-Run interrupt occurred ----------------------------------------*/
+ if (((itflags & SMBUS_FLAG_OVR) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
+ {
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_OVR;
+
+ /* Clear OVR flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_OVR);
+ }
+
+ /* SMBUS Arbitration Loss error interrupt occurred ------------------------------------*/
+ if (((itflags & SMBUS_FLAG_ARLO) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
+ {
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ARLO;
+
+ /* Clear ARLO flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ARLO);
+ }
+
+ /* SMBUS Timeout error interrupt occurred ---------------------------------------------*/
+ if (((itflags & SMBUS_FLAG_TIMEOUT) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
+ {
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_BUSTIMEOUT;
+
+ /* Clear TIMEOUT flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_TIMEOUT);
+ }
+
+ /* SMBUS Alert error interrupt occurred -----------------------------------------------*/
+ if (((itflags & SMBUS_FLAG_ALERT) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
+ {
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_ALERT;
+
+ /* Clear ALERT flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_ALERT);
+ }
+
+ /* SMBUS Packet Error Check error interrupt occurred ----------------------------------*/
+ if (((itflags & SMBUS_FLAG_PECERR) != RESET) && ((itsources & SMBUS_IT_ERRI) != RESET))
+ {
+ hsmbus->ErrorCode |= HAL_SMBUS_ERROR_PECERR;
+
+ /* Clear PEC error flag */
+ __HAL_SMBUS_CLEAR_FLAG(hsmbus, SMBUS_FLAG_PECERR);
+ }
+
+ /* Call the Error Callback in case of Error detected */
+ if ((hsmbus->ErrorCode != HAL_SMBUS_ERROR_NONE) && (hsmbus->ErrorCode != HAL_SMBUS_ERROR_ACKF))
+ {
+ /* Do not Reset the HAL state in case of ALERT error */
+ if ((hsmbus->ErrorCode & HAL_SMBUS_ERROR_ALERT) != HAL_SMBUS_ERROR_ALERT)
+ {
+ if (((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_TX) == HAL_SMBUS_STATE_SLAVE_BUSY_TX)
+ || ((hsmbus->State & HAL_SMBUS_STATE_SLAVE_BUSY_RX) == HAL_SMBUS_STATE_SLAVE_BUSY_RX))
+ {
+ /* Reset only HAL_SMBUS_STATE_SLAVE_BUSY_XX */
+ /* keep HAL_SMBUS_STATE_LISTEN if set */
+ hsmbus->PreviousState = HAL_SMBUS_STATE_READY;
+ hsmbus->State = HAL_SMBUS_STATE_LISTEN;
+ }
+ }
+
+ /* Call the Error callback to inform upper layer */
+ HAL_SMBUS_ErrorCallback(hsmbus);
+ }
+}
+
/**
* @brief Handle SMBUS Communication Timeout.
* @param hsmbus Pointer to a SMBUS_HandleTypeDef structure that contains
@@ -1913,17 +2032,17 @@
uint32_t tickstart = HAL_GetTick();
/* Wait until flag is set */
- if(Status == RESET)
+ if (Status == RESET)
{
- while(__HAL_SMBUS_GET_FLAG(hsmbus, Flag) == RESET)
+ while (__HAL_SMBUS_GET_FLAG(hsmbus, Flag) == RESET)
{
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+ if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
{
hsmbus->PreviousState = hsmbus->State;
- hsmbus->State= HAL_SMBUS_STATE_READY;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
@@ -1935,15 +2054,15 @@
}
else
{
- while(__HAL_SMBUS_GET_FLAG(hsmbus, Flag) != RESET)
+ while (__HAL_SMBUS_GET_FLAG(hsmbus, Flag) != RESET)
{
/* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
+ if (Timeout != HAL_MAX_DELAY)
{
- if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
+ if ((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
{
hsmbus->PreviousState = hsmbus->State;
- hsmbus->State= HAL_SMBUS_STATE_READY;
+ hsmbus->State = HAL_SMBUS_STATE_READY;
/* Process Unlocked */
__HAL_UNLOCK(hsmbus);
@@ -1978,25 +2097,14 @@
*/
static void SMBUS_TransferConfig(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
{
- uint32_t tmpreg = 0U;
-
/* Check the parameters */
assert_param(IS_SMBUS_ALL_INSTANCE(hsmbus->Instance));
assert_param(IS_SMBUS_TRANSFER_MODE(Mode));
assert_param(IS_SMBUS_TRANSFER_REQUEST(Request));
- /* Get the CR2 register value */
- tmpreg = hsmbus->Instance->CR2;
-
- /* clear tmpreg specific bits */
- tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE));
-
- /* update tmpreg */
- tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16U ) & I2C_CR2_NBYTES) | \
- (uint32_t)Mode | (uint32_t)Request);
-
/* update CR2 register */
- hsmbus->Instance->CR2 = tmpreg;
+ MODIFY_REG(hsmbus->Instance->CR2, ((I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_PECBYTE)), \
+ (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << I2C_CR2_NBYTES_Pos) & I2C_CR2_NBYTES) | (uint32_t)Mode | (uint32_t)Request));
}
/**
@@ -2009,14 +2117,14 @@
/* if user set XferOptions to SMBUS_OTHER_FRAME_NO_PEC */
/* it request implicitly to generate a restart condition */
/* set XferOptions to SMBUS_FIRST_FRAME */
- if(hsmbus->XferOptions == SMBUS_OTHER_FRAME_NO_PEC)
+ if (hsmbus->XferOptions == SMBUS_OTHER_FRAME_NO_PEC)
{
hsmbus->XferOptions = SMBUS_FIRST_FRAME;
}
/* else if user set XferOptions to SMBUS_OTHER_FRAME_WITH_PEC */
/* it request implicitly to generate a restart condition */
/* set XferOptions to SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE */
- else if(hsmbus->XferOptions == SMBUS_OTHER_FRAME_WITH_PEC)
+ else if (hsmbus->XferOptions == SMBUS_OTHER_FRAME_WITH_PEC)
{
hsmbus->XferOptions = SMBUS_FIRST_FRAME | SMBUS_SENDPEC_MODE;
}
@@ -2024,7 +2132,7 @@
/* it request implicitly to generate a restart condition */
/* then generate a stop condition at the end of transfer */
/* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_NO_PEC */
- else if(hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC)
+ else if (hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC)
{
hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_NO_PEC;
}
@@ -2032,7 +2140,7 @@
/* it request implicitly to generate a restart condition */
/* then generate a stop condition at the end of transfer */
/* set XferOptions to SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC */
- else if(hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)
+ else if (hsmbus->XferOptions == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC)
{
hsmbus->XferOptions = SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC;
}
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_smbus.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_smbus.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_smbus.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 30-December-2016
* @brief Header file of SMBUS HAL module.
******************************************************************************
* @attention
@@ -40,7 +38,7 @@
#define __STM32F7xx_HAL_SMBUS_H
#ifdef __cplusplus
- extern "C" {
+extern "C" {
#endif
/* Includes ------------------------------------------------------------------*/
@@ -99,7 +97,7 @@
This parameter can be a value of @ref SMBUS_peripheral_mode */
uint32_t SMBusTimeout; /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value.
- (Enable bits and different timeout values)
+ (Enable bits and different timeout values)
This parameter calculated by referring to SMBUS initialization
section in Reference manual */
} SMBUS_InitTypeDef;
@@ -168,7 +166,7 @@
__IO uint32_t ErrorCode; /*!< SMBUS Error code */
-}SMBUS_HandleTypeDef;
+} SMBUS_HandleTypeDef;
/**
* @}
*/
@@ -281,9 +279,9 @@
*/
#define SMBUS_NO_STARTSTOP (0x00000000U)
-#define SMBUS_GENERATE_STOP I2C_CR2_STOP
-#define SMBUS_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
-#define SMBUS_GENERATE_START_WRITE I2C_CR2_START
+#define SMBUS_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP)
+#define SMBUS_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN)
+#define SMBUS_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START)
/**
* @}
*/
@@ -429,17 +427,17 @@
* @param __HANDLE__ specifies the SMBUS Handle.
* @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
- * @arg @ref SMBUS_FLAG_TXE Transmit data register empty
+ * @arg @ref SMBUS_FLAG_TXE Transmit data register empty
* @arg @ref SMBUS_FLAG_TXIS Transmit interrupt status
* @arg @ref SMBUS_FLAG_RXNE Receive data register not empty
* @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode)
- * @arg @ref SMBUS_FLAG_AF NACK received flag
+ * @arg @ref SMBUS_FLAG_AF NACK received flag
* @arg @ref SMBUS_FLAG_STOPF STOP detection flag
- * @arg @ref SMBUS_FLAG_TC Transfer complete (master mode)
- * @arg @ref SMBUS_FLAG_TCR Transfer complete reload
+ * @arg @ref SMBUS_FLAG_TC Transfer complete (master mode)
+ * @arg @ref SMBUS_FLAG_TCR Transfer complete reload
* @arg @ref SMBUS_FLAG_BERR Bus error
* @arg @ref SMBUS_FLAG_ARLO Arbitration lost
- * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun
+ * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun
* @arg @ref SMBUS_FLAG_PECERR PEC error in reception
* @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
* @arg @ref SMBUS_FLAG_ALERT SMBus alert
@@ -456,11 +454,11 @@
* @param __FLAG__ specifies the flag to clear.
* This parameter can be any combination of the following values:
* @arg @ref SMBUS_FLAG_ADDR Address matched (slave mode)
- * @arg @ref SMBUS_FLAG_AF NACK received flag
+ * @arg @ref SMBUS_FLAG_AF NACK received flag
* @arg @ref SMBUS_FLAG_STOPF STOP detection flag
* @arg @ref SMBUS_FLAG_BERR Bus error
* @arg @ref SMBUS_FLAG_ARLO Arbitration lost
- * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun
+ * @arg @ref SMBUS_FLAG_OVR Overrun/Underrun
* @arg @ref SMBUS_FLAG_PECERR PEC error in reception
* @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
* @arg @ref SMBUS_FLAG_ALERT SMBus alert
@@ -502,6 +500,8 @@
#define IS_SMBUS_ANALOG_FILTER(FILTER) (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \
((FILTER) == SMBUS_ANALOGFILTER_DISABLE))
+#define IS_SMBUS_DIGITAL_FILTER(FILTER) ((FILTER) <= 0x0000000FU)
+
#define IS_SMBUS_ADDRESSING_MODE(MODE) (((MODE) == SMBUS_ADDRESSINGMODE_7BIT) || \
((MODE) == SMBUS_ADDRESSINGMODE_10BIT))
@@ -592,9 +592,11 @@
/* Initialization and de-initialization functions **********************************/
HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);
-HAL_StatusTypeDef HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus);
+HAL_StatusTypeDef HAL_SMBUS_DeInit(SMBUS_HandleTypeDef *hsmbus);
void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus);
void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus);
+HAL_StatusTypeDef HAL_SMBUS_ConfigAnalogFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t AnalogFilter);
+HAL_StatusTypeDef HAL_SMBUS_ConfigDigitalFilter(SMBUS_HandleTypeDef *hsmbus, uint32_t DigitalFilter);
/**
* @}
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_spdifrx.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_spdifrx.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_spdifrx.c * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief This file provides firmware functions to manage the following * functionalities of the SPDIFRX audio interface: * + Initialization and Configuration @@ -194,7 +192,7 @@ /** * @brief Initializes the SPDIFRX according to the specified parameters * in the SPDIFRX_InitTypeDef and create the associated handle. - * @param hspdif: SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval HAL status */ HAL_StatusTypeDef HAL_SPDIFRX_Init(SPDIFRX_HandleTypeDef *hspdif) @@ -264,7 +262,7 @@ /** * @brief DeInitializes the SPDIFRX peripheral - * @param hspdif: SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval HAL status */ HAL_StatusTypeDef HAL_SPDIFRX_DeInit(SPDIFRX_HandleTypeDef *hspdif) @@ -299,7 +297,7 @@ /** * @brief SPDIFRX MSP Init - * @param hspdif: SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval None */ __weak void HAL_SPDIFRX_MspInit(SPDIFRX_HandleTypeDef *hspdif) @@ -314,7 +312,7 @@ /** * @brief SPDIFRX MSP DeInit - * @param hspdif: SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval None */ __weak void HAL_SPDIFRX_MspDeInit(SPDIFRX_HandleTypeDef *hspdif) @@ -330,8 +328,8 @@ /** * @brief Sets the SPDIFRX dtat format according to the specified parameters * in the SPDIFRX_InitTypeDef. - * @param hspdif: SPDIFRX handle - * @param sDataFormat: SPDIFRX data format + * @param hspdif SPDIFRX handle + * @param sDataFormat SPDIFRX data format * @retval HAL status */ HAL_StatusTypeDef HAL_SPDIFRX_SetDataFormat(SPDIFRX_HandleTypeDef *hspdif, SPDIFRX_SetDataFormatTypeDef sDataFormat) @@ -427,11 +425,11 @@ /** * @brief Receives an amount of data (Data Flow) in blocking mode. - * @param hspdif: pointer to SPDIFRX_HandleTypeDef structure that contains + * @param hspdif pointer to SPDIFRX_HandleTypeDef structure that contains * the configuration information for SPDIFRX module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received - * @param Timeout: Timeout duration + * @param pData Pointer to data buffer + * @param Size Amount of data to be received + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout) @@ -497,11 +495,11 @@ /** * @brief Receives an amount of data (Control Flow) in blocking mode. - * @param hspdif: pointer to a SPDIFRX_HandleTypeDef structure that contains + * @param hspdif pointer to a SPDIFRX_HandleTypeDef structure that contains * the configuration information for SPDIFRX module. - * @param pData: Pointer to data buffer - * @param Size: Amount of data to be received - * @param Timeout: Timeout duration + * @param pData Pointer to data buffer + * @param Size Amount of data to be received + * @param Timeout Timeout duration * @retval HAL status */ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size, uint32_t Timeout) @@ -567,9 +565,9 @@ /** * @brief Receive an amount of data (Data Flow) in non-blocking mode with Interrupt - * @param hspdif: SPDIFRX handle - * @param pData: a 32-bit pointer to the Receive data buffer. - * @param Size: number of data sample to be received . + * @param hspdif SPDIFRX handle + * @param pData a 32-bit pointer to the Receive data buffer. + * @param Size number of data sample to be received . * @retval HAL status */ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size) @@ -636,9 +634,9 @@ /** * @brief Receive an amount of data (Control Flow) with Interrupt - * @param hspdif: SPDIFRX handle - * @param pData: a 32-bit pointer to the Receive data buffer. - * @param Size: number of data sample (Control Flow) to be received : + * @param hspdif SPDIFRX handle + * @param pData a 32-bit pointer to the Receive data buffer. + * @param Size number of data sample (Control Flow) to be received : * @retval HAL status */ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size) @@ -705,9 +703,9 @@ /** * @brief Receive an amount of data (Data Flow) mode with DMA - * @param hspdif: SPDIFRX handle - * @param pData: a 32-bit pointer to the Receive data buffer. - * @param Size: number of data sample to be received : + * @param hspdif SPDIFRX handle + * @param pData a 32-bit pointer to the Receive data buffer. + * @param Size number of data sample to be received : * @retval HAL status */ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveDataFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size) @@ -777,9 +775,9 @@ /** * @brief Receive an amount of data (Control Flow) with DMA - * @param hspdif: SPDIFRX handle - * @param pData: a 32-bit pointer to the Receive data buffer. - * @param Size: number of data (Control Flow) sample to be received : + * @param hspdif SPDIFRX handle + * @param pData a 32-bit pointer to the Receive data buffer. + * @param Size number of data (Control Flow) sample to be received : * @retval HAL status */ HAL_StatusTypeDef HAL_SPDIFRX_ReceiveControlFlow_DMA(SPDIFRX_HandleTypeDef *hspdif, uint32_t *pData, uint16_t Size) @@ -849,7 +847,7 @@ /** * @brief stop the audio stream receive from the Media. - * @param hspdif: SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval None */ HAL_StatusTypeDef HAL_SPDIFRX_DMAStop(SPDIFRX_HandleTypeDef *hspdif) @@ -878,7 +876,7 @@ /** * @brief This function handles SPDIFRX interrupt request. - * @param hspdif: SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval HAL status */ void HAL_SPDIFRX_IRQHandler(SPDIFRX_HandleTypeDef *hspdif) @@ -924,7 +922,7 @@ /** * @brief Rx Transfer (Data flow) half completed callbacks - * @param hspdif: SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval None */ __weak void HAL_SPDIFRX_RxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif) @@ -939,7 +937,7 @@ /** * @brief Rx Transfer (Data flow) completed callbacks - * @param hspdif: SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval None */ __weak void HAL_SPDIFRX_RxCpltCallback(SPDIFRX_HandleTypeDef *hspdif) @@ -954,7 +952,7 @@ /** * @brief Rx (Control flow) Transfer half completed callbacks - * @param hspdif: SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval None */ __weak void HAL_SPDIFRX_CxHalfCpltCallback(SPDIFRX_HandleTypeDef *hspdif) @@ -969,7 +967,7 @@ /** * @brief Rx Transfer (Control flow) completed callbacks - * @param hspdif: SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval None */ __weak void HAL_SPDIFRX_CxCpltCallback(SPDIFRX_HandleTypeDef *hspdif) @@ -984,7 +982,7 @@ /** * @brief SPDIFRX error callbacks - * @param hspdif: SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval None */ __weak void HAL_SPDIFRX_ErrorCallback(SPDIFRX_HandleTypeDef *hspdif) @@ -1018,7 +1016,7 @@ /** * @brief Return the SPDIFRX state - * @param hspdif : SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval HAL state */ HAL_SPDIFRX_StateTypeDef HAL_SPDIFRX_GetState(SPDIFRX_HandleTypeDef *hspdif) @@ -1028,7 +1026,7 @@ /** * @brief Return the SPDIFRX error code - * @param hspdif : SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval SPDIFRX Error Code */ uint32_t HAL_SPDIFRX_GetError(SPDIFRX_HandleTypeDef *hspdif) @@ -1042,7 +1040,7 @@ /** * @brief DMA SPDIFRX receive process (Data flow) complete callback - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void SPDIFRX_DMARxCplt(DMA_HandleTypeDef *hdma) @@ -1061,7 +1059,7 @@ /** * @brief DMA SPDIFRX receive process (Data flow) half complete callback - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void SPDIFRX_DMARxHalfCplt(DMA_HandleTypeDef *hdma) @@ -1074,7 +1072,7 @@ /** * @brief DMA SPDIFRX receive process (Control flow) complete callback - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void SPDIFRX_DMACxCplt(DMA_HandleTypeDef *hdma) @@ -1091,7 +1089,7 @@ /** * @brief DMA SPDIFRX receive process (Control flow) half complete callback - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void SPDIFRX_DMACxHalfCplt(DMA_HandleTypeDef *hdma) @@ -1103,7 +1101,7 @@ /** * @brief DMA SPDIFRX communication error callback - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void SPDIFRX_DMAError(DMA_HandleTypeDef *hdma) @@ -1123,7 +1121,7 @@ /** * @brief Receive an amount of data (Data Flow) with Interrupt - * @param hspdif: SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval None */ static void SPDIFRX_ReceiveDataFlow_IT(SPDIFRX_HandleTypeDef *hspdif) @@ -1148,7 +1146,7 @@ /** * @brief Receive an amount of data (Control Flow) with Interrupt - * @param hspdif: SPDIFRX handle + * @param hspdif SPDIFRX handle * @retval None */ static void SPDIFRX_ReceiveControlFlow_IT(SPDIFRX_HandleTypeDef *hspdif) @@ -1173,11 +1171,11 @@ /** * @brief This function handles SPDIFRX Communication Timeout. - * @param hspdif: SPDIFRX handle - * @param Flag: Flag checked - * @param Status: Value of the flag expected - * @param Timeout: Duration of the timeout - * @param tickstart: Tick start value + * @param hspdif SPDIFRX handle + * @param Flag Flag checked + * @param Status Value of the flag expected + * @param Timeout Duration of the timeout + * @param tickstart Tick start value * @retval HAL status */ static HAL_StatusTypeDef SPDIFRX_WaitOnFlagUntilTimeout(SPDIFRX_HandleTypeDef *hspdif, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t tickstart)
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_spdifrx.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_spdifrx.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_spdifrx.h * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief Header file of SPDIFRX HAL module. ****************************************************************************** * @attention @@ -345,34 +343,34 @@ */ /** @brief Reset SPDIFRX handle state - * @param __HANDLE__: SPDIFRX handle. + * @param __HANDLE__ SPDIFRX handle. * @retval None */ #define __HAL_SPDIFRX_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = (uint16_t)SPDIFRX_CR_SPDIFEN) /** @brief Disable the specified SPDIFRX peripheral (IDLE State). - * @param __HANDLE__: specifies the SPDIFRX Handle. + * @param __HANDLE__ specifies the SPDIFRX Handle. * @retval None */ #define __HAL_SPDIFRX_IDLE(__HANDLE__) ((__HANDLE__)->Instance->CR &= SPDIFRX_STATE_IDLE) /** @brief Enable the specified SPDIFRX peripheral (SYNC State). - * @param __HANDLE__: specifies the SPDIFRX Handle. + * @param __HANDLE__ specifies the SPDIFRX Handle. * @retval None */ #define __HAL_SPDIFRX_SYNC(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_SYNC) /** @brief Enable the specified SPDIFRX peripheral (RCV State). - * @param __HANDLE__: specifies the SPDIFRX Handle. + * @param __HANDLE__ specifies the SPDIFRX Handle. * @retval None */ #define __HAL_SPDIFRX_RCV(__HANDLE__) ((__HANDLE__)->Instance->CR |= SPDIFRX_STATE_RCV) /** @brief Enable or disable the specified SPDIFRX interrupts. - * @param __HANDLE__: specifies the SPDIFRX Handle. - * @param __INTERRUPT__: specifies the interrupt source to enable or disable. + * @param __HANDLE__ specifies the SPDIFRX Handle. + * @param __INTERRUPT__ specifies the interrupt source to enable or disable. * This parameter can be one of the following values: * @arg SPDIFRX_IT_RXNE * @arg SPDIFRX_IT_CSRNE @@ -387,8 +385,8 @@ #define __HAL_SPDIFRX_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->IMR &= (uint16_t)(~(__INTERRUPT__))) /** @brief Checks if the specified SPDIFRX interrupt source is enabled or disabled. - * @param __HANDLE__: specifies the SPDIFRX Handle. - * @param __INTERRUPT__: specifies the SPDIFRX interrupt source to check. + * @param __HANDLE__ specifies the SPDIFRX Handle. + * @param __INTERRUPT__ specifies the SPDIFRX interrupt source to check. * This parameter can be one of the following values: * @arg SPDIFRX_IT_RXNE * @arg SPDIFRX_IT_CSRNE @@ -402,8 +400,8 @@ #define __HAL_SPDIFRX_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->IMR & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Checks whether the specified SPDIFRX flag is set or not. - * @param __HANDLE__: specifies the SPDIFRX Handle. - * @param __FLAG__: specifies the flag to check. + * @param __HANDLE__ specifies the SPDIFRX Handle. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg SPDIFRX_FLAG_RXNE * @arg SPDIFRX_FLAG_CSRNE @@ -419,8 +417,8 @@ #define __HAL_SPDIFRX_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) /** @brief Clears the specified SPDIFRX SR flag, in setting the proper IFCR register bit. - * @param __HANDLE__: specifies the USART Handle. - * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set + * @param __HANDLE__ specifies the USART Handle. + * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set * to clear the corresponding interrupt * This parameter can be one of the following values: * @arg SPDIFRX_FLAG_PERR
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_spi.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_spi.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_spi.c
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief SPI HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Serial Peripheral Interface (SPI) peripheral:
@@ -258,7 +256,7 @@
/**
* @brief Initialize the SPI according to the specified parameters
* in the SPI_InitTypeDef and initialize the associated handle.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval HAL status
*/
@@ -383,7 +381,7 @@
/**
* @brief De-Initialize the SPI peripheral.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval HAL status
*/
@@ -417,7 +415,7 @@
/**
* @brief Initialize the SPI MSP.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -433,7 +431,7 @@
/**
* @brief De-Initialize the SPI MSP.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -486,11 +484,11 @@
/**
* @brief Transmit an amount of data in blocking mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
- * @param Timeout: Timeout duration
+ * @param pData pointer to data buffer
+ * @param Size amount of data to be sent
+ * @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
@@ -644,11 +642,11 @@
/**
* @brief Receive an amount of data in blocking mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be received
- * @param Timeout: Timeout duration
+ * @param pData pointer to data buffer
+ * @param Size amount of data to be received
+ * @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout)
@@ -874,12 +872,12 @@
/**
* @brief Transmit and Receive an amount of data in blocking mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
- * @param pTxData: pointer to transmission data buffer
- * @param pRxData: pointer to reception data buffer
- * @param Size: amount of data to be sent and received
- * @param Timeout: Timeout duration
+ * @param pTxData pointer to transmission data buffer
+ * @param pRxData pointer to reception data buffer
+ * @param Size amount of data to be sent and received
+ * @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
@@ -1158,10 +1156,10 @@
/**
* @brief Transmit an amount of data in non-blocking mode with Interrupt.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
+ * @param pData pointer to data buffer
+ * @param Size amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
@@ -1241,10 +1239,10 @@
/**
* @brief Receive an amount of data in non-blocking mode with Interrupt.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
+ * @param pData pointer to data buffer
+ * @param Size amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
@@ -1345,11 +1343,11 @@
/**
* @brief Transmit and Receive an amount of data in non-blocking mode with Interrupt.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
- * @param pTxData: pointer to transmission data buffer
- * @param pRxData: pointer to reception data buffer
- * @param Size: amount of data to be sent and received
+ * @param pTxData pointer to transmission data buffer
+ * @param pRxData pointer to reception data buffer
+ * @param Size amount of data to be sent and received
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
@@ -1453,10 +1451,10 @@
/**
* @brief Transmit an amount of data in non-blocking mode with DMA.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
- * @param pData: pointer to data buffer
- * @param Size: amount of data to be sent
+ * @param pData pointer to data buffer
+ * @param Size amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
@@ -1562,11 +1560,11 @@
/**
* @brief Receive an amount of data in non-blocking mode with DMA.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
- * @param pData: pointer to data buffer
+ * @param pData pointer to data buffer
* @note When the CRC feature is enabled the pData Length must be Size + 1.
- * @param Size: amount of data to be sent
+ * @param Size amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size)
@@ -1678,12 +1676,12 @@
/**
* @brief Transmit and Receive an amount of data in non-blocking mode with DMA.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
- * @param pTxData: pointer to transmission data buffer
- * @param pRxData: pointer to reception data buffer
+ * @param pTxData pointer to transmission data buffer
+ * @param pRxData pointer to reception data buffer
* @note When the CRC feature is enabled the pRxData Length must be Size + 1
- * @param Size: amount of data to be sent
+ * @param Size amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
@@ -2163,7 +2161,7 @@
/**
* @brief Pause the DMA Transfer.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for the specified SPI module.
* @retval HAL status
*/
@@ -2183,7 +2181,7 @@
/**
* @brief Resume the DMA Transfer.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for the specified SPI module.
* @retval HAL status
*/
@@ -2203,7 +2201,7 @@
/**
* @brief Stop the DMA Transfer.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for the specified SPI module.
* @retval HAL status
*/
@@ -2234,7 +2232,7 @@
/**
* @brief Handle SPI interrupt request.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for the specified SPI module.
* @retval None
*/
@@ -2330,7 +2328,7 @@
/**
* @brief Tx Transfer completed callback.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -2346,7 +2344,7 @@
/**
* @brief Rx Transfer completed callback.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -2362,7 +2360,7 @@
/**
* @brief Tx and Rx Transfer completed callback.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -2378,7 +2376,7 @@
/**
* @brief Tx Half Transfer completed callback.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -2394,7 +2392,7 @@
/**
* @brief Rx Half Transfer completed callback.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -2410,7 +2408,7 @@
/**
* @brief Tx and Rx Half Transfer callback.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -2426,7 +2424,7 @@
/**
* @brief SPI error callback.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -2479,7 +2477,7 @@
/**
* @brief Return the SPI handle state.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval SPI state
*/
@@ -2491,7 +2489,7 @@
/**
* @brief Return the SPI error code.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval SPI error code in bitmap format
*/
@@ -2516,7 +2514,7 @@
/**
* @brief DMA SPI transmit process complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -2563,7 +2561,7 @@
/**
* @brief DMA SPI receive process complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -2654,7 +2652,7 @@
/**
* @brief DMA SPI transmit receive process complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -2739,7 +2737,7 @@
/**
* @brief DMA SPI half transmit process complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -2752,7 +2750,7 @@
/**
* @brief DMA SPI half receive process complete callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -2765,7 +2763,7 @@
/**
* @brief DMA SPI half transmit receive process complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -2778,7 +2776,7 @@
/**
* @brief DMA SPI communication error callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -2936,7 +2934,7 @@
/**
* @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -2986,7 +2984,7 @@
#if (USE_SPI_CRC != 0U)
/**
* @brief Rx 8-bit handler for Transmit and Receive in Interrupt mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -3018,7 +3016,7 @@
/**
* @brief Tx 8-bit handler for Transmit and Receive in Interrupt mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -3064,7 +3062,7 @@
/**
* @brief Rx 16-bit handler for Transmit and Receive in Interrupt mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -3098,7 +3096,7 @@
#if (USE_SPI_CRC != 0U)
/**
* @brief Manage the CRC 16-bit receive for Transmit and Receive in Interrupt mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -3122,7 +3120,7 @@
/**
* @brief Tx 16-bit handler for Transmit and Receive in Interrupt mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -3160,7 +3158,7 @@
#if (USE_SPI_CRC != 0U)
/**
* @brief Manage the CRC 8-bit receive in Interrupt context.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -3185,7 +3183,7 @@
/**
* @brief Manage the receive 8-bit in Interrupt context.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -3218,7 +3216,7 @@
#if (USE_SPI_CRC != 0U)
/**
* @brief Manage the CRC 16-bit receive in Interrupt context.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -3241,7 +3239,7 @@
/**
* @brief Manage the 16-bit receive in Interrupt context.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -3274,7 +3272,7 @@
/**
* @brief Handle the data 8-bit transmit in Interrupt mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -3298,7 +3296,7 @@
/**
* @brief Handle the data 16-bit transmit in Interrupt mode.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -3324,12 +3322,12 @@
/**
* @brief Handle SPI Communication Timeout.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
- * @param Flag: SPI flag to check
- * @param State: flag state to check
- * @param Timeout: Timeout duration
- * @param Tickstart: tick start value
+ * @param Flag SPI flag to check
+ * @param State flag state to check
+ * @param Timeout Timeout duration
+ * @param Tickstart tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef SPI_WaitFlagStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Flag, uint32_t State,
@@ -3376,12 +3374,12 @@
/**
* @brief Handle SPI FIFO Communication Timeout.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
- * @param Fifo: Fifo to check
- * @param State: Fifo state to check
- * @param Timeout: Timeout duration
- * @param Tickstart: tick start value
+ * @param Fifo Fifo to check
+ * @param State Fifo state to check
+ * @param Timeout Timeout duration
+ * @param Tickstart tick start value
* @retval HAL status
*/
static HAL_StatusTypeDef SPI_WaitFifoStateUntilTimeout(SPI_HandleTypeDef *hspi, uint32_t Fifo, uint32_t State,
@@ -3437,10 +3435,10 @@
/**
* @brief Handle the check of the RX transaction complete.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
- * @param Timeout: Timeout duration
- * @param Tickstart: tick start value
+ * @param Timeout Timeout duration
+ * @param Tickstart tick start value
* @retval None.
*/
static HAL_StatusTypeDef SPI_EndRxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
@@ -3474,9 +3472,9 @@
/**
* @brief Handle the check of the RXTX or TX transaction complete.
- * @param hspi: SPI handle
- * @param Timeout: Timeout duration
- * @param Tickstart: tick start value
+ * @param hspi SPI handle
+ * @param Timeout Timeout duration
+ * @param Tickstart tick start value
*/
static HAL_StatusTypeDef SPI_EndRxTxTransaction(SPI_HandleTypeDef *hspi, uint32_t Timeout, uint32_t Tickstart)
{
@@ -3503,7 +3501,7 @@
/**
* @brief Handle the end of the RXTX transaction.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -3560,7 +3558,7 @@
/**
* @brief Handle the end of the RX transaction.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -3602,7 +3600,7 @@
/**
* @brief Handle the end of the TX transaction.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -3641,7 +3639,7 @@
/**
* @brief Handle abort a Rx transaction.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
@@ -3683,7 +3681,7 @@
/**
* @brief Handle abort a Tx or Rx/Tx transaction.
- * @param hspi: pointer to a SPI_HandleTypeDef structure that contains
+ * @param hspi pointer to a SPI_HandleTypeDef structure that contains
* the configuration information for SPI module.
* @retval None
*/
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_spi.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_spi.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_spi.h * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief Header file of SPI HAL module. ****************************************************************************** * @attention @@ -395,16 +393,16 @@ */ /** @brief Reset SPI handle state. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET) /** @brief Enable or disable the specified SPI interrupts. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @param __INTERRUPT__: specifies the interrupt source to enable or disable. + * @param __INTERRUPT__ specifies the interrupt source to enable or disable. * This parameter can be one of the following values: * @arg SPI_IT_TXE: Tx buffer empty interrupt enable * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable @@ -415,9 +413,9 @@ #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__))) /** @brief Check whether the specified SPI interrupt source is enabled or not. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @param __INTERRUPT__: specifies the SPI interrupt source to check. + * @param __INTERRUPT__ specifies the SPI interrupt source to check. * This parameter can be one of the following values: * @arg SPI_IT_TXE: Tx buffer empty interrupt enable * @arg SPI_IT_RXNE: RX buffer not empty interrupt enable @@ -427,9 +425,9 @@ #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET) /** @brief Check whether the specified SPI flag is set or not. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. - * @param __FLAG__: specifies the flag to check. + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg SPI_FLAG_RXNE: Receive buffer not empty flag * @arg SPI_FLAG_TXE: Transmit buffer empty flag @@ -445,14 +443,14 @@ #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__)) /** @brief Clear the SPI CRCERR pending flag. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR)) /** @brief Clear the SPI MODF pending flag. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ @@ -465,7 +463,7 @@ } while(0) /** @brief Clear the SPI OVR pending flag. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ @@ -478,7 +476,7 @@ } while(0) /** @brief Clear the SPI FRE pending flag. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ @@ -490,14 +488,14 @@ }while(0) /** @brief Enable the SPI peripheral. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_SPE) /** @brief Disable the SPI peripheral. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ @@ -513,21 +511,21 @@ */ /** @brief Set the SPI transmit-only mode. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE) /** @brief Set the SPI receive-only mode. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */ #define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE)) /** @brief Reset the CRC calculation of the SPI. - * @param __HANDLE__: specifies the SPI Handle. + * @param __HANDLE__ specifies the SPI Handle. * This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral. * @retval None */
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sram.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sram.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_sram.c
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief SRAM HAL module driver.
* This file provides a generic firmware to drive SRAM memories
* mounted as external device.
@@ -130,10 +128,10 @@
/**
* @brief Performs the SRAM device initialization sequence
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
- * @param Timing: Pointer to SRAM control timing structure
- * @param ExtTiming: Pointer to SRAM extended mode timing structure
+ * @param Timing Pointer to SRAM control timing structure
+ * @param ExtTiming Pointer to SRAM extended mode timing structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
@@ -169,7 +167,7 @@
/**
* @brief Performs the SRAM device De-initialization sequence.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @retval HAL status
*/
@@ -191,7 +189,7 @@
/**
* @brief SRAM MSP Init.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @retval None
*/
@@ -207,7 +205,7 @@
/**
* @brief SRAM MSP DeInit.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @retval None
*/
@@ -223,7 +221,7 @@
/**
* @brief DMA transfer complete callback.
- * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
+ * @param hdma pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @retval None
*/
@@ -239,7 +237,7 @@
/**
* @brief DMA transfer complete error callback.
- * @param hdma: pointer to a SRAM_HandleTypeDef structure that contains
+ * @param hdma pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @retval None
*/
@@ -273,11 +271,11 @@
/**
* @brief Reads 8-bit buffer from SRAM memory.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
- * @param pAddress: Pointer to read start address
- * @param pDstBuffer: Pointer to destination buffer
- * @param BufferSize: Size of the buffer to read from memory
+ * @param pAddress Pointer to read start address
+ * @param pDstBuffer Pointer to destination buffer
+ * @param BufferSize Size of the buffer to read from memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
@@ -309,11 +307,11 @@
/**
* @brief Writes 8-bit buffer to SRAM memory.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
- * @param pAddress: Pointer to write start address
- * @param pSrcBuffer: Pointer to source buffer to write
- * @param BufferSize: Size of the buffer to write to memory
+ * @param pAddress Pointer to write start address
+ * @param pSrcBuffer Pointer to source buffer to write
+ * @param BufferSize Size of the buffer to write to memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
@@ -351,11 +349,11 @@
/**
* @brief Reads 16-bit buffer from SRAM memory.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
- * @param pAddress: Pointer to read start address
- * @param pDstBuffer: Pointer to destination buffer
- * @param BufferSize: Size of the buffer to read from memory
+ * @param pAddress Pointer to read start address
+ * @param pDstBuffer Pointer to destination buffer
+ * @param BufferSize Size of the buffer to read from memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
@@ -387,11 +385,11 @@
/**
* @brief Writes 16-bit buffer to SRAM memory.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
- * @param pAddress: Pointer to write start address
- * @param pSrcBuffer: Pointer to source buffer to write
- * @param BufferSize: Size of the buffer to write to memory
+ * @param pAddress Pointer to write start address
+ * @param pSrcBuffer Pointer to source buffer to write
+ * @param BufferSize Size of the buffer to write to memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
@@ -429,11 +427,11 @@
/**
* @brief Reads 32-bit buffer from SRAM memory.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
- * @param pAddress: Pointer to read start address
- * @param pDstBuffer: Pointer to destination buffer
- * @param BufferSize: Size of the buffer to read from memory
+ * @param pAddress Pointer to read start address
+ * @param pDstBuffer Pointer to destination buffer
+ * @param BufferSize Size of the buffer to read from memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
@@ -463,11 +461,11 @@
/**
* @brief Writes 32-bit buffer to SRAM memory.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
- * @param pAddress: Pointer to write start address
- * @param pSrcBuffer: Pointer to source buffer to write
- * @param BufferSize: Size of the buffer to write to memory
+ * @param pAddress Pointer to write start address
+ * @param pSrcBuffer Pointer to source buffer to write
+ * @param BufferSize Size of the buffer to write to memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
@@ -503,11 +501,11 @@
/**
* @brief Reads a Words data from the SRAM memory using DMA transfer.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
- * @param pAddress: Pointer to read start address
- * @param pDstBuffer: Pointer to destination buffer
- * @param BufferSize: Size of the buffer to read from memory
+ * @param pAddress Pointer to read start address
+ * @param pDstBuffer Pointer to destination buffer
+ * @param BufferSize Size of the buffer to read from memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
@@ -536,11 +534,11 @@
/**
* @brief Writes a Words data buffer to SRAM memory using DMA transfer.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
- * @param pAddress: Pointer to write start address
- * @param pSrcBuffer: Pointer to source buffer to write
- * @param BufferSize: Size of the buffer to write to memory
+ * @param pAddress Pointer to write start address
+ * @param pSrcBuffer Pointer to source buffer to write
+ * @param BufferSize Size of the buffer to write to memory
* @retval HAL status
*/
HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
@@ -594,7 +592,7 @@
/**
* @brief Enables dynamically SRAM write operation.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @retval HAL status
*/
@@ -617,7 +615,7 @@
/**
* @brief Disables dynamically SRAM write operation.
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @retval HAL status
*/
@@ -662,7 +660,7 @@
/**
* @brief Returns the SRAM controller state
- * @param hsram: pointer to a SRAM_HandleTypeDef structure that contains
+ * @param hsram pointer to a SRAM_HandleTypeDef structure that contains
* the configuration information for SRAM module.
* @retval HAL state
*/
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sram.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_sram.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_sram.h * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief Header file of SRAM HAL module. ****************************************************************************** * @attention @@ -102,7 +100,7 @@ */ /** @brief Reset SRAM handle state - * @param __HANDLE__: SRAM handle + * @param __HANDLE__ SRAM handle * @retval None */ #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_tim.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_tim.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_tim.c
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief TIM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Timer (TIM) peripheral:
@@ -94,6 +92,63 @@
HAL_TIM_DMABurst_WriteStart()
HAL_TIM_DMABurst_ReadStart()
+ *** Callback registration ***
+ =============================================
+
+ The compilation define USE_HAL_TIM_REGISTER_CALLBACKS when set to 1
+ allows the user to configure dynamically the driver callbacks.
+
+ Use Function @ref HAL_TIM_RegisterCallback() to register a callback.
+ @ref HAL_TIM_RegisterCallback() takes as parameters the HAL peripheral handle,
+ the Callback ID and a pointer to the user callback function.
+
+ Use function @ref HAL_TIM_UnRegisterCallback() to reset a callback to the default
+ weak function.
+ @ref HAL_TIM_UnRegisterCallback takes as parameters the HAL peripheral handle,
+ and the Callback ID.
+
+ These functions allow to register/unregister following callbacks:
+ (+) Base_MspInitCallback : TIM Base Msp Init Callback.
+ (+) Base_MspDeInitCallback : TIM Base Msp DeInit Callback.
+ (+) IC_MspInitCallback : TIM IC Msp Init Callback.
+ (+) IC_MspDeInitCallback : TIM IC Msp DeInit Callback.
+ (+) OC_MspInitCallback : TIM OC Msp Init Callback.
+ (+) OC_MspDeInitCallback : TIM OC Msp DeInit Callback.
+ (+) PWM_MspInitCallback : TIM PWM Msp Init Callback.
+ (+) PWM_MspDeInitCallback : TIM PWM Msp DeInit Callback.
+ (+) OnePulse_MspInitCallback : TIM One Pulse Msp Init Callback.
+ (+) OnePulse_MspDeInitCallback : TIM One Pulse Msp DeInit Callback.
+ (+) Encoder_MspInitCallback : TIM Encoder Msp Init Callback.
+ (+) Encoder_MspDeInitCallback : TIM Encoder Msp DeInit Callback.
+ (+) PeriodElapsedCallback : TIM Period Elapsed Callback.
+ (+) TriggerCallback : TIM Trigger Callback.
+ (+) IC_CaptureCallback : TIM Input Capture Callback.
+ (+) OC_DelayElapsedCallback : TIM Output Compare Delay Elapsed Callback.
+ (+) PWM_PulseFinishedCallback : TIM PWM Pulse Finished Callback.
+ (+) ErrorCallback : TIM Error Callback.
+ (+) CommutationCallback : TIM Commutation Callback.
+ (+) BreakCallback : TIM Break Callback.
+
+ By default, after the Init and when the state is HAL_TIM_STATE_RESET
+ all interrupt callbacks are set to the corresponding weak functions:
+ examples @ref HAL_TIM_TriggerCallback(), @ref HAL_TIM_ErrorCallback().
+
+ Exception done for MspInit and MspDeInit functions that are reset to the legacy weak
+ functionalities in the Init/DeInit only when these callbacks are null
+ (not registered beforehand). If not, MspInit or MspDeInit are not null, the Init/DeInit
+ keep and use the user MspInit/MspDeInit callbacks (registered beforehand)
+
+ Callbacks can be registered/unregistered in HAL_TIM_STATE_READY state only.
+ Exception done MspInit/MspDeInit that can be registered/unregistered
+ in HAL_TIM_STATE_READY or HAL_TIM_STATE_RESET state,
+ thus registered (user) MspInit/DeInit callbacks can be used during the Init/DeInit.
+ In that case first register the MspInit/MspDeInit user callbacks
+ using @ref HAL_TIM_RegisterCallback() before calling DeInit or Init function.
+
+ When The compilation define USE_HAL_TIM_REGISTER_CALLBACKS is set to 0 or
+ not defined, the callback registration feature is not available and all callbacks
+ are set to the corresponding weak functions.
+
@endverbatim
******************************************************************************
* @attention
@@ -161,6 +216,7 @@
static void TIM_DMATriggerCplt(DMA_HandleTypeDef *hdma);
static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
TIM_SlaveConfigTypeDef * sSlaveConfig);
+
/**
* @}
*/
@@ -194,7 +250,7 @@
/**
* @brief Initializes the TIM Time base Unit according to the specified
* parameters in the TIM_HandleTypeDef and create the associated handle.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @retval HAL status
*/
@@ -205,21 +261,33 @@
{
return HAL_ERROR;
}
-
+
/* Check the parameters */
assert_param(IS_TIM_INSTANCE(htim->Instance));
assert_param(IS_TIM_COUNTER_MODE(htim->Init.CounterMode));
assert_param(IS_TIM_CLOCKDIVISION_DIV(htim->Init.ClockDivision));
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
-
+
if(htim->State == HAL_TIM_STATE_RESET)
- {
+ {
/* Allocate lock resource and initialize it */
htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ /* Reset interrupt callbacks to legacy week callbacks */
+ TIM_ResetCallback(htim);
+
+ if(htim->Base_MspInitCallback == NULL)
+ {
+ htim->Base_MspInitCallback = HAL_TIM_Base_MspInit;
+ }
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ htim->Base_MspInitCallback(htim);
+#else
/* Init the low level hardware : GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
-
/* Set the TIM state */
htim->State= HAL_TIM_STATE_BUSY;
@@ -234,7 +302,7 @@
/**
* @brief DeInitializes the TIM Base peripheral
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @retval HAL status
*/
@@ -247,9 +315,18 @@
/* Disable the TIM Peripheral Clock */
__HAL_TIM_DISABLE(htim);
-
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ if(htim->Base_MspDeInitCallback == NULL)
+ {
+ htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ htim->Base_MspDeInitCallback(htim);
+#else
/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
HAL_TIM_Base_MspDeInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
/* Change TIM state */
htim->State = HAL_TIM_STATE_RESET;
@@ -262,7 +339,7 @@
/**
* @brief Initializes the TIM Base MSP.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @retval None
*/
@@ -278,7 +355,7 @@
/**
* @brief DeInitializes TIM Base MSP.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @retval None
*/
@@ -294,7 +371,7 @@
/**
* @brief Starts the TIM Base generation.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @retval HAL status
*/
@@ -318,7 +395,7 @@
/**
* @brief Stops the TIM Base generation.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @retval HAL status
*/
@@ -342,7 +419,7 @@
/**
* @brief Starts the TIM Base generation in interrupt mode.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @retval HAL status
*/
@@ -363,7 +440,7 @@
/**
* @brief Stops the TIM Base generation in interrupt mode.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @retval HAL status
*/
@@ -383,10 +460,10 @@
/**
* @brief Starts the TIM Base generation in DMA mode.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param pData: The source Buffer address.
- * @param Length: The length of data to be transferred from memory to peripheral.
+ * @param pData The source Buffer address.
+ * @param Length The length of data to be transferred from memory to peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
@@ -430,7 +507,7 @@
/**
* @brief Stops the TIM Base generation in DMA mode.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @retval HAL status
*/
@@ -480,7 +557,7 @@
/**
* @brief Initializes the TIM Output Compare according to the specified
* parameters in the TIM_HandleTypeDef and create the associated handle.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @retval HAL status
*/
@@ -499,13 +576,25 @@
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if(htim->State == HAL_TIM_STATE_RESET)
- {
+ {
/* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
+ htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ /* Reset interrupt callbacks to legacy week callbacks */
+ TIM_ResetCallback(htim);
+
+ if(htim->OC_MspInitCallback == NULL)
+ {
+ htim->OC_MspInitCallback = HAL_TIM_OC_MspDeInit;
+ }
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ htim->OC_MspInitCallback(htim);
+#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_OC_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
-
/* Set the TIM state */
htim->State= HAL_TIM_STATE_BUSY;
@@ -520,7 +609,7 @@
/**
* @brief DeInitializes the TIM peripheral
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @retval HAL status
*/
@@ -533,10 +622,19 @@
/* Disable the TIM Peripheral Clock */
__HAL_TIM_DISABLE(htim);
-
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ if(htim->OC_MspDeInitCallback == NULL)
+ {
+ htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ htim->OC_MspDeInitCallback(htim);
+#else
/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
HAL_TIM_OC_MspDeInit(htim);
-
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
/* Change TIM state */
htim->State = HAL_TIM_STATE_RESET;
@@ -548,7 +646,7 @@
/**
* @brief Initializes the TIM Output Compare MSP.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @retval None
*/
@@ -564,7 +662,7 @@
/**
* @brief DeInitializes TIM Output Compare MSP.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @retval None
*/
@@ -580,9 +678,9 @@
/**
* @brief Starts the TIM Output Compare signal generation.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param Channel: TIM Channel to be enabled.
+ * @param Channel TIM Channel to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -613,9 +711,9 @@
/**
* @brief Stops the TIM Output Compare signal generation.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param Channel: TIM Channel to be disabled.
+ * @param Channel TIM Channel to be disabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -646,9 +744,9 @@
/**
* @brief Starts the TIM Output Compare signal generation in interrupt mode.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param Channel: TIM Channel to be enabled.
+ * @param Channel TIM Channel to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -713,9 +811,9 @@
/**
* @brief Stops the TIM Output Compare signal generation in interrupt mode.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param Channel: TIM Channel to be disabled.
+ * @param Channel TIM Channel to be disabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -780,16 +878,16 @@
/**
* @brief Starts the TIM Output Compare signal generation in DMA mode.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param Channel: TIM Channel to be enabled.
+ * @param Channel TIM Channel to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param pData: The source Buffer address.
- * @param Length: The length of data to be transferred from memory to TIM peripheral
+ * @param pData The source Buffer address.
+ * @param Length The length of data to be transferred from memory to TIM peripheral
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
@@ -900,9 +998,9 @@
/**
* @brief Stops the TIM Output Compare signal generation in DMA mode.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param Channel: TIM Channel to be disabled.
+ * @param Channel TIM Channel to be disabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -996,7 +1094,7 @@
/**
* @brief Initializes the TIM PWM Time Base according to the specified
* parameters in the TIM_HandleTypeDef and create the associated handle.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @retval HAL status
*/
@@ -1017,11 +1115,23 @@
if(htim->State == HAL_TIM_STATE_RESET)
{
/* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
+ htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ /* Reset interrupt callbacks to legacy week callbacks */
+ TIM_ResetCallback(htim);
+
+ if(htim->PWM_MspInitCallback == NULL)
+ {
+ htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit;
+ }
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ htim->PWM_MspInitCallback(htim);
+#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_PWM_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
-
/* Set the TIM state */
htim->State= HAL_TIM_STATE_BUSY;
@@ -1036,7 +1146,7 @@
/**
* @brief DeInitializes the TIM peripheral
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @retval HAL status
*/
@@ -1049,10 +1159,19 @@
/* Disable the TIM Peripheral Clock */
__HAL_TIM_DISABLE(htim);
-
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ if(htim->PWM_MspDeInitCallback == NULL)
+ {
+ htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ htim->PWM_MspDeInitCallback(htim);
+#else
/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
HAL_TIM_PWM_MspDeInit(htim);
-
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
/* Change TIM state */
htim->State = HAL_TIM_STATE_RESET;
@@ -1064,7 +1183,7 @@
/**
* @brief Initializes the TIM PWM MSP.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @retval None
*/
@@ -1080,7 +1199,7 @@
/**
* @brief DeInitializes TIM PWM MSP.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @retval None
*/
@@ -1096,9 +1215,9 @@
/**
* @brief Starts the PWM signal generation.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param Channel: TIM Channels to be enabled.
+ * @param Channel TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1129,9 +1248,9 @@
/**
* @brief Stops the PWM signal generation.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param Channel: TIM Channels to be disabled.
+ * @param Channel TIM Channels to be disabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1165,9 +1284,9 @@
/**
* @brief Starts the PWM signal generation in interrupt mode.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param Channel: TIM Channel to be enabled.
+ * @param Channel TIM Channel to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1232,9 +1351,9 @@
/**
* @brief Stops the PWM signal generation in interrupt mode.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param Channel: TIM Channels to be disabled.
+ * @param Channel TIM Channels to be disabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1299,16 +1418,16 @@
/**
* @brief Starts the TIM PWM signal generation in DMA mode.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param Channel: TIM Channels to be enabled.
+ * @param Channel TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param pData: The source Buffer address.
- * @param Length: The length of data to be transferred from memory to TIM peripheral
+ * @param pData The source Buffer address.
+ * @param Length The length of data to be transferred from memory to TIM peripheral
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
@@ -1419,9 +1538,9 @@
/**
* @brief Stops the TIM PWM signal generation in DMA mode.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param Channel: TIM Channels to be disabled.
+ * @param Channel TIM Channels to be disabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1515,7 +1634,7 @@
/**
* @brief Initializes the TIM Input Capture Time base according to the specified
* parameters in the TIM_HandleTypeDef and create the associated handle.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @retval HAL status
*/
@@ -1534,13 +1653,26 @@
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if(htim->State == HAL_TIM_STATE_RESET)
- {
+ {
/* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
+ htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ /* Reset interrupt callbacks to legacy week callbacks */
+ TIM_ResetCallback(htim);
+
+ if(htim->IC_MspInitCallback == NULL)
+ {
+ htim->IC_MspInitCallback = HAL_TIM_IC_MspInit;
+ }
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ htim->IC_MspInitCallback(htim);
+#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_IC_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
-
+
/* Set the TIM state */
htim->State= HAL_TIM_STATE_BUSY;
@@ -1555,7 +1687,7 @@
/**
* @brief DeInitializes the TIM peripheral
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @retval HAL status
*/
@@ -1568,10 +1700,19 @@
/* Disable the TIM Peripheral Clock */
__HAL_TIM_DISABLE(htim);
-
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ if(htim->IC_MspDeInitCallback == NULL)
+ {
+ htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ htim->IC_MspDeInitCallback(htim);
+#else
/* DeInit the low level hardware: GPIO, CLOCK, NVIC and DMA */
HAL_TIM_IC_MspDeInit(htim);
-
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
/* Change TIM state */
htim->State = HAL_TIM_STATE_RESET;
@@ -1583,7 +1724,7 @@
/**
* @brief Initializes the TIM INput Capture MSP.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @retval None
*/
@@ -1599,7 +1740,7 @@
/**
* @brief DeInitializes TIM Input Capture MSP.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @retval None
*/
@@ -1615,9 +1756,9 @@
/**
* @brief Starts the TIM Input Capture measurement.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param Channel: TIM Channels to be enabled.
+ * @param Channel TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1642,9 +1783,9 @@
/**
* @brief Stops the TIM Input Capture measurement.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param Channel: TIM Channels to be disabled.
+ * @param Channel TIM Channels to be disabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1669,9 +1810,9 @@
/**
* @brief Starts the TIM Input Capture measurement in interrupt mode.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param Channel: TIM Channels to be enabled.
+ * @param Channel TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1729,9 +1870,9 @@
/**
* @brief Stops the TIM Input Capture measurement in interrupt mode.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param Channel: TIM Channels to be disabled.
+ * @param Channel TIM Channels to be disabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1790,16 +1931,16 @@
/**
* @brief Starts the TIM Input Capture measurement on in DMA mode.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param Channel: TIM Channels to be enabled.
+ * @param Channel TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param pData: The destination Buffer address.
- * @param Length: The length of data to be transferred from TIM peripheral to memory.
+ * @param pData The destination Buffer address.
+ * @param Length The length of data to be transferred from TIM peripheral to memory.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
@@ -1906,9 +2047,9 @@
/**
* @brief Stops the TIM Input Capture measurement on in DMA mode.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param Channel: TIM Channels to be disabled.
+ * @param Channel TIM Channels to be disabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1996,9 +2137,9 @@
/**
* @brief Initializes the TIM One Pulse Time Base according to the specified
* parameters in the TIM_HandleTypeDef and create the associated handle.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param OnePulseMode: Select the One pulse mode.
+ * @param OnePulseMode Select the One pulse mode.
* This parameter can be one of the following values:
* @arg TIM_OPMODE_SINGLE: Only one pulse will be generated.
* @arg TIM_OPMODE_REPETITIVE: Repetitive pulses will be generated.
@@ -2020,13 +2161,26 @@
assert_param(IS_TIM_AUTORELOAD_PRELOAD(htim->Init.AutoReloadPreload));
if(htim->State == HAL_TIM_STATE_RESET)
- {
+ {
/* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
+ htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ /* Reset interrupt callbacks to legacy week callbacks */
+ TIM_ResetCallback(htim);
+
+ if(htim->OnePulse_MspDeInitCallback == NULL)
+ {
+ htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspInit;
+ }
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ htim->OnePulse_MspDeInitCallback(htim);
+#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_OnePulse_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
-
+
/* Set the TIM state */
htim->State= HAL_TIM_STATE_BUSY;
@@ -2047,7 +2201,7 @@
/**
* @brief DeInitializes the TIM One Pulse
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @retval HAL status
*/
@@ -2060,10 +2214,19 @@
/* Disable the TIM Peripheral Clock */
__HAL_TIM_DISABLE(htim);
-
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ if(htim->OnePulse_MspDeInitCallback == NULL)
+ {
+ htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ htim->OnePulse_MspDeInitCallback(htim);
+#else
/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
HAL_TIM_OnePulse_MspDeInit(htim);
-
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
/* Change TIM state */
htim->State = HAL_TIM_STATE_RESET;
@@ -2075,7 +2238,7 @@
/**
* @brief Initializes the TIM One Pulse MSP.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @retval None
*/
@@ -2091,7 +2254,7 @@
/**
* @brief DeInitializes TIM One Pulse MSP.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @retval None
*/
@@ -2107,9 +2270,9 @@
/**
* @brief Starts the TIM One Pulse signal generation.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param OutputChannel : TIM Channels to be enabled.
+ * @param OutputChannel TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2117,6 +2280,9 @@
*/
HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(OutputChannel);
+
/* Enable the Capture compare and the Input Capture channels
(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
@@ -2141,9 +2307,9 @@
/**
* @brief Stops the TIM One Pulse signal generation.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param OutputChannel : TIM Channels to be disable.
+ * @param OutputChannel TIM Channels to be disable.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2151,6 +2317,9 @@
*/
HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(OutputChannel);
+
/* Disable the Capture compare and the Input Capture channels
(in the OPM Mode the two possible channels that can be used are TIM_CHANNEL_1 and TIM_CHANNEL_2)
if TIM_CHANNEL_1 is used as output, the TIM_CHANNEL_2 will be used as input and
@@ -2175,9 +2344,9 @@
/**
* @brief Starts the TIM One Pulse signal generation in interrupt mode.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param OutputChannel : TIM Channels to be enabled.
+ * @param OutputChannel TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2193,7 +2362,10 @@
No need to enable the counter, it's enabled automatically by hardware
(the counter starts in response to a stimulus and generate a pulse */
-
+
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(OutputChannel);
+
/* Enable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_ENABLE_IT(htim, TIM_IT_CC1);
@@ -2215,9 +2387,9 @@
/**
* @brief Stops the TIM One Pulse signal generation in interrupt mode.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param OutputChannel : TIM Channels to be enabled.
+ * @param OutputChannel TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2225,6 +2397,9 @@
*/
HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel)
{
+ /* Prevent unused argument(s) compilation warning */
+ UNUSED(OutputChannel);
+
/* Disable the TIM Capture/Compare 1 interrupt */
__HAL_TIM_DISABLE_IT(htim, TIM_IT_CC1);
@@ -2279,9 +2454,9 @@
*/
/**
* @brief Initializes the TIM Encoder Interface and create the associated handle.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param sConfig: TIM Encoder Interface configuration structure
+ * @param sConfig TIM Encoder Interface configuration structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig)
@@ -2312,13 +2487,26 @@
assert_param(IS_TIM_IC_FILTER(sConfig->IC2Filter));
if(htim->State == HAL_TIM_STATE_RESET)
- {
+ {
/* Allocate lock resource and initialize it */
- htim->Lock = HAL_UNLOCKED;
+ htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ /* Reset interrupt callbacks to legacy week callbacks */
+ TIM_ResetCallback(htim);
+
+ if(htim->Encoder_MspInitCallback == NULL)
+ {
+ htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit;
+ }
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ htim->Encoder_MspInitCallback(htim);
+#else
/* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
HAL_TIM_Encoder_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
-
+
/* Set the TIM state */
htim->State= HAL_TIM_STATE_BUSY;
@@ -2372,7 +2560,7 @@
/**
* @brief DeInitializes the TIM Encoder interface
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @retval HAL status
*/
@@ -2385,10 +2573,19 @@
/* Disable the TIM Peripheral Clock */
__HAL_TIM_DISABLE(htim);
-
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ if(htim->Encoder_MspDeInitCallback == NULL)
+ {
+ htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ htim->Encoder_MspDeInitCallback(htim);
+#else
/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
HAL_TIM_Encoder_MspDeInit(htim);
-
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
/* Change TIM state */
htim->State = HAL_TIM_STATE_RESET;
@@ -2400,7 +2597,7 @@
/**
* @brief Initializes the TIM Encoder Interface MSP.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @retval None
*/
@@ -2416,7 +2613,7 @@
/**
* @brief DeInitializes TIM Encoder Interface MSP.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @retval None
*/
@@ -2432,9 +2629,9 @@
/**
* @brief Starts the TIM Encoder Interface.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param Channel: TIM Channels to be enabled.
+ * @param Channel TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2475,9 +2672,9 @@
/**
* @brief Stops the TIM Encoder Interface.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param Channel: TIM Channels to be disabled.
+ * @param Channel TIM Channels to be disabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2519,9 +2716,9 @@
/**
* @brief Starts the TIM Encoder Interface in interrupt mode.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param Channel: TIM Channels to be enabled.
+ * @param Channel TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2568,9 +2765,9 @@
/**
* @brief Stops the TIM Encoder Interface in interrupt mode.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param Channel: TIM Channels to be disabled.
+ * @param Channel TIM Channels to be disabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2620,16 +2817,16 @@
/**
* @brief Starts the TIM Encoder Interface in DMA mode.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param Channel: TIM Channels to be enabled.
+ * @param Channel TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_ALL: TIM Channel 1 and TIM Channel 2 are selected
- * @param pData1: The destination Buffer address for IC1.
- * @param pData2: The destination Buffer address for IC2.
- * @param Length: The length of data to be transferred from TIM peripheral to memory.
+ * @param pData1 The destination Buffer address for IC1.
+ * @param pData2 The destination Buffer address for IC2.
+ * @param Length The length of data to be transferred from TIM peripheral to memory.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length)
@@ -2741,9 +2938,9 @@
/**
* @brief Stops the TIM Encoder Interface in DMA mode.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param Channel: TIM Channels to be enabled.
+ * @param Channel TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2809,7 +3006,7 @@
*/
/**
* @brief This function handles TIM interrupts requests.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @retval None
*/
@@ -2827,13 +3024,22 @@
/* Input capture event */
if((htim->Instance->CCMR1 & TIM_CCMR1_CC1S) != 0x00)
{
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->IC_CaptureCallback(htim);
+#else
HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Output compare event */
else
{
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->OC_DelayElapsedCallback(htim);
+ htim->PWM_PulseFinishedCallback(htim);
+#else
HAL_TIM_OC_DelayElapsedCallback(htim);
HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}
@@ -2848,14 +3054,23 @@
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_2;
/* Input capture event */
if((htim->Instance->CCMR1 & TIM_CCMR1_CC2S) != 0x00)
- {
+ {
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->IC_CaptureCallback(htim);
+#else
HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Output compare event */
else
{
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->OC_DelayElapsedCallback(htim);
+ htim->PWM_PulseFinishedCallback(htim);
+#else
HAL_TIM_OC_DelayElapsedCallback(htim);
HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}
@@ -2870,13 +3085,22 @@
/* Input capture event */
if((htim->Instance->CCMR2 & TIM_CCMR2_CC3S) != 0x00)
{
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->IC_CaptureCallback(htim);
+#else
HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Output compare event */
else
{
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->OC_DelayElapsedCallback(htim);
+ htim->PWM_PulseFinishedCallback(htim);
+#else
HAL_TIM_OC_DelayElapsedCallback(htim);
- HAL_TIM_PWM_PulseFinishedCallback(htim);
+ HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}
@@ -2891,13 +3115,22 @@
/* Input capture event */
if((htim->Instance->CCMR2 & TIM_CCMR2_CC4S) != 0x00)
{
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->IC_CaptureCallback(htim);
+#else
HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/* Output compare event */
else
{
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->OC_DelayElapsedCallback(htim);
+ htim->PWM_PulseFinishedCallback(htim);
+#else
HAL_TIM_OC_DelayElapsedCallback(htim);
HAL_TIM_PWM_PulseFinishedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}
@@ -2908,7 +3141,11 @@
if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_UPDATE) !=RESET)
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_UPDATE);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->PeriodElapsedCallback(htim);
+#else
HAL_TIM_PeriodElapsedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM Break input event */
@@ -2917,7 +3154,12 @@
if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->BreakCallback(htim);
+#else
HAL_TIMEx_BreakCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
}
}
@@ -2927,7 +3169,11 @@
if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_BREAK) !=RESET)
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_BREAK);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->BreakCallback(htim);
+#else
HAL_TIMEx_BreakCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
@@ -2937,7 +3183,11 @@
if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_TRIGGER) !=RESET)
{
__HAL_TIM_CLEAR_IT(htim, TIM_IT_TRIGGER);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->TriggerCallback(htim);
+#else
HAL_TIM_TriggerCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
/* TIM commutation event */
@@ -2946,7 +3196,11 @@
if(__HAL_TIM_GET_IT_SOURCE(htim, TIM_IT_COM) !=RESET)
{
__HAL_TIM_CLEAR_IT(htim, TIM_FLAG_COM);
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->CommutationCallback(htim);
+#else
HAL_TIMEx_CommutationCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
}
}
@@ -2977,10 +3231,10 @@
/**
* @brief Initializes the TIM Output Compare Channels according to the specified
* parameters in the TIM_OC_InitTypeDef.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param sConfig: TIM Output Compare configuration structure
- * @param Channel: TIM Channels to be enabled.
+ * @param sConfig TIM Output Compare configuration structure
+ * @param Channel TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -3047,10 +3301,10 @@
/**
* @brief Initializes the TIM Input Capture Channels according to the specified
* parameters in the TIM_IC_InitTypeDef.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param sConfig: TIM Input Capture configuration structure
- * @param Channel: TIM Channels to be enabled.
+ * @param sConfig TIM Input Capture configuration structure
+ * @param Channel TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -3144,10 +3398,10 @@
/**
* @brief Initializes the TIM PWM channels according to the specified
* parameters in the TIM_OC_InitTypeDef.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param sConfig: TIM PWM configuration structure
- * @param Channel: TIM Channels to be enabled.
+ * @param sConfig TIM PWM configuration structure
+ * @param Channel TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -3243,14 +3497,14 @@
/**
* @brief Initializes the TIM One Pulse Channels according to the specified
* parameters in the TIM_OnePulse_InitTypeDef.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param sConfig: TIM One Pulse configuration structure
- * @param OutputChannel: TIM Channels to be enabled.
+ * @param sConfig TIM One Pulse configuration structure
+ * @param OutputChannel TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
- * @param InputChannel: TIM Channels to be enabled.
+ * @param InputChannel TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -3356,9 +3610,9 @@
/**
* @brief Configure the DMA Burst to transfer Data from the memory to the TIM peripheral
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data write.
+ * @param BurstBaseAddress TIM Base address from when the DMA will starts the Data write.
* This parameters can be on of the following values:
* @arg TIM_DMABASE_CR1
* @arg TIM_DMABASE_CR2
@@ -3379,7 +3633,7 @@
* @arg TIM_DMABASE_CCR4
* @arg TIM_DMABASE_BDTR
* @arg TIM_DMABASE_DCR
- * @param BurstRequestSrc: TIM DMA Request sources.
+ * @param BurstRequestSrc TIM DMA Request sources.
* This parameters can be on of the following values:
* @arg TIM_DMA_UPDATE: TIM update Interrupt source
* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
@@ -3388,8 +3642,8 @@
* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
* @arg TIM_DMA_COM: TIM Commutation DMA source
* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
- * @param BurstBuffer: The Buffer address.
- * @param BurstLength: DMA Burst length. This parameter can be one value
+ * @param BurstBuffer The Buffer address.
+ * @param BurstLength DMA Burst length. This parameter can be one value
* between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
* @retval HAL status
*/
@@ -3520,9 +3774,9 @@
/**
* @brief Stops the TIM DMA Burst mode
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param BurstRequestSrc: TIM DMA Request sources to disable
+ * @param BurstRequestSrc TIM DMA Request sources to disable
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
@@ -3581,9 +3835,9 @@
/**
* @brief Configure the DMA Burst to transfer Data from the TIM peripheral to the memory
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param BurstBaseAddress: TIM Base address from when the DMA will starts the Data read.
+ * @param BurstBaseAddress TIM Base address from when the DMA will starts the Data read.
* This parameters can be on of the following values:
* @arg TIM_DMABASE_CR1
* @arg TIM_DMABASE_CR2
@@ -3604,7 +3858,7 @@
* @arg TIM_DMABASE_CCR4
* @arg TIM_DMABASE_BDTR
* @arg TIM_DMABASE_DCR
- * @param BurstRequestSrc: TIM DMA Request sources.
+ * @param BurstRequestSrc TIM DMA Request sources.
* This parameters can be on of the following values:
* @arg TIM_DMA_UPDATE: TIM update Interrupt source
* @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
@@ -3613,8 +3867,8 @@
* @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
* @arg TIM_DMA_COM: TIM Commutation DMA source
* @arg TIM_DMA_TRIGGER: TIM Trigger DMA source
- * @param BurstBuffer: The Buffer address.
- * @param BurstLength: DMA Burst length. This parameter can be one value
+ * @param BurstBuffer The Buffer address.
+ * @param BurstLength DMA Burst length. This parameter can be one value
* between TIM_DMABURSTLENGTH_1TRANSFER and TIM_DMABURSTLENGTH_18TRANSFERS.
* @retval HAL status
*/
@@ -3746,9 +4000,9 @@
/**
* @brief Stop the DMA burst reading
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param BurstRequestSrc: TIM DMA Request sources to disable.
+ * @param BurstRequestSrc TIM DMA Request sources to disable.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc)
@@ -3807,9 +4061,9 @@
/**
* @brief Generate a software event
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param EventSource: specifies the event source.
+ * @param EventSource specifies the event source.
* This parameter can be one of the following values:
* @arg TIM_EVENTSOURCE_UPDATE: Timer update Event source
* @arg TIM_EVENTSOURCE_CC1: Timer Capture Compare 1 Event source
@@ -3851,11 +4105,11 @@
/**
* @brief Configures the OCRef clear feature
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
+ * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
* contains the OCREF clear feature and parameters for the TIM peripheral.
- * @param Channel: specifies the TIM Channel.
+ * @param Channel specifies the TIM Channel.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -3961,9 +4215,9 @@
/**
* @brief Configures the clock source to be used
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param sClockSourceConfig: pointer to a TIM_ClockConfigTypeDef structure that
+ * @param sClockSourceConfig pointer to a TIM_ClockConfigTypeDef structure that
* contains the clock source information for the TIM peripheral.
* @retval HAL status
*/
@@ -4113,9 +4367,9 @@
/**
* @brief Selects the signal connected to the TI1 input: direct from CH1_input
* or a XOR combination between CH1_input, CH2_input & CH3_input
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param TI1_Selection: Indicate whether or not channel 1 is connected to the
+ * @param TI1_Selection Indicate whether or not channel 1 is connected to the
* output of a XOR gate.
* This parameter can be one of the following values:
* @arg TIM_TI1SELECTION_CH1: The TIMx_CH1 pin is connected to TI1 input
@@ -4148,9 +4402,9 @@
/**
* @brief Configures the TIM in Slave mode
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
+ * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
* contains the selected trigger (internal trigger input, filtered
* timer input or external trigger input) and the ) and the Slave
* mode (Disable, Reset, Gated, Trigger, External clock mode 1).
@@ -4296,8 +4550,8 @@
/**
* @brief Configures the TIM in Slave mode in interrupt mode
- * @param htim: TIM handle.
- * @param sSlaveConfig: pointer to a TIM_SlaveConfigTypeDef structure that
+ * @param htim TIM handle.
+ * @param sSlaveConfig pointer to a TIM_SlaveConfigTypeDef structure that
* contains the selected trigger (internal trigger input, filtered
* timer input or external trigger input) and the ) and the Slave
* mode (Disable, Reset, Gated, Trigger, External clock mode 1).
@@ -4332,9 +4586,9 @@
/**
* @brief Read the captured value from Capture Compare unit
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param Channel: TIM Channels to be enabled.
+ * @param Channel TIM Channels to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -4419,6 +4673,8 @@
(+) Timer Input capture callback
(+) Timer Trigger callback
(+) Timer Error callback
+ (+) Timer_RegisterCallback
+ (+) Timer_UnRegisterCallback
@endverbatim
* @{
@@ -4426,7 +4682,7 @@
/**
* @brief Period elapsed callback in non blocking mode
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @retval None
*/
@@ -4442,7 +4698,7 @@
}
/**
* @brief Output Compare callback in non blocking mode
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @retval None
*/
@@ -4457,7 +4713,7 @@
}
/**
* @brief Input Capture callback in non blocking mode
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @retval None
*/
@@ -4473,7 +4729,7 @@
/**
* @brief PWM Pulse finished callback in non blocking mode
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @retval None
*/
@@ -4489,7 +4745,7 @@
/**
* @brief Hall Trigger detection callback in non blocking mode
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @retval None
*/
@@ -4505,7 +4761,7 @@
/**
* @brief Timer error callback in non blocking mode
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @retval None
*/
@@ -4519,6 +4775,438 @@
*/
}
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Register a User TIM callback to be used instead of the weak predefined callback
+ * @param htim tim handle
+ * @param CallbackID ID of the callback to be registered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
+ * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
+ * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
+ * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
+ * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
+ * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
+ * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
+ * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
+ * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
+ * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
+ * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
+ * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
+ * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
+ * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
+ * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
+ * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
+ * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
+ * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
+ * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
+ * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
+ * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
+ * @param pCallback pointer to the callback function
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ if(pCallback == NULL)
+ {
+ return HAL_ERROR;
+ }
+ /* Process locked */
+ __HAL_LOCK(htim);
+
+ if(htim->State == HAL_TIM_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_TIM_BASE_MSPINIT_CB_ID :
+ htim->Base_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+ htim->Base_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_IC_MSPINIT_CB_ID :
+ htim->IC_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_IC_MSPDEINIT_CB_ID :
+ htim->IC_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_OC_MSPINIT_CB_ID :
+ htim->OC_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_OC_MSPDEINIT_CB_ID :
+ htim->OC_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_PWM_MSPINIT_CB_ID :
+ htim->PWM_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+ htim->PWM_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+ htim->OnePulse_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+ htim->OnePulse_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+ htim->Encoder_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+ htim->Encoder_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+ htim->HallSensor_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+ htim->HallSensor_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_PERIOD_ELAPSED_CB_ID :
+ htim->PeriodElapsedCallback = pCallback;
+ break;
+
+ case HAL_TIM_TRIGGER_CB_ID :
+ htim->TriggerCallback = pCallback;
+ break;
+
+ case HAL_TIM_IC_CAPTURE_CB_ID :
+ htim->IC_CaptureCallback = pCallback;
+ break;
+
+ case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
+ htim->OC_DelayElapsedCallback = pCallback;
+ break;
+
+ case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
+ htim->PWM_PulseFinishedCallback = pCallback;
+ break;
+
+ case HAL_TIM_ERROR_CB_ID :
+ htim->ErrorCallback = pCallback;
+ break;
+
+ case HAL_TIM_COMMUTATION_CB_ID :
+ htim->CommutationCallback = pCallback;
+ break;
+
+ case HAL_TIM_BREAK_CB_ID :
+ htim->BreakCallback = pCallback;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(htim->State == HAL_TIM_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_TIM_BASE_MSPINIT_CB_ID :
+ htim->Base_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+ htim->Base_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_IC_MSPINIT_CB_ID :
+ htim->IC_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_IC_MSPDEINIT_CB_ID :
+ htim->IC_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_OC_MSPINIT_CB_ID :
+ htim->OC_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_OC_MSPDEINIT_CB_ID :
+ htim->OC_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_PWM_MSPINIT_CB_ID :
+ htim->PWM_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+ htim->PWM_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+ htim->OnePulse_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+ htim->OnePulse_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+ htim->Encoder_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+ htim->Encoder_MspDeInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+ htim->HallSensor_MspInitCallback = pCallback;
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+ htim->HallSensor_MspDeInitCallback = pCallback;
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return status;
+}
+
+/**
+ * @brief Unregister a TIM callback
+ * TIM callback is redirected to the weak predefined callback
+ * @param htim tim handle
+ * @param CallbackID ID of the callback to be unregistered
+ * This parameter can be one of the following values:
+ * @arg @ref HAL_TIM_BASE_MSPINIT_CB_ID Base MspInit Callback ID
+ * @arg @ref HAL_TIM_BASE_MSPDEINIT_CB_ID Base MspDeInit Callback ID
+ * @arg @ref HAL_TIM_IC_MSPINIT_CB_ID IC MspInit Callback ID
+ * @arg @ref HAL_TIM_IC_MSPDEINIT_CB_ID IC MspDeInit Callback ID
+ * @arg @ref HAL_TIM_OC_MSPINIT_CB_ID OC MspInit Callback ID
+ * @arg @ref HAL_TIM_OC_MSPDEINIT_CB_ID OC MspDeInit Callback ID
+ * @arg @ref HAL_TIM_PWM_MSPINIT_CB_ID PWM MspInit Callback ID
+ * @arg @ref HAL_TIM_PWM_MSPDEINIT_CB_ID PWM MspDeInit Callback ID
+ * @arg @ref HAL_TIM_ONE_PULSE_MSPINIT_CB_ID One Pulse MspInit Callback ID
+ * @arg @ref HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID One Pulse MspDeInit Callback ID
+ * @arg @ref HAL_TIM_ENCODER_MSPINIT_CB_ID Encoder MspInit Callback ID
+ * @arg @ref HAL_TIM_ENCODER_MSPDEINIT_CB_ID Encoder MspDeInit Callback ID
+ * @arg @ref HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID Hall Sensor MspInit Callback ID
+ * @arg @ref HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID Hall Sensor MspDeInit Callback ID
+ * @arg @ref HAL_TIM_PERIOD_ELAPSED_CB_ID Period Elapsed Callback ID
+ * @arg @ref HAL_TIM_TRIGGER_CB_ID Trigger Callback ID
+ * @arg @ref HAL_TIM_IC_CAPTURE_CB_ID Input Capture Callback ID
+ * @arg @ref HAL_TIM_OC_DELAY_ELAPSED_CB_ID Output Compare Delay Elapsed Callback ID
+ * @arg @ref HAL_TIM_PWM_PULSE_FINISHED_CB_ID PWM Pulse Finished Callback ID
+ * @arg @ref HAL_TIM_ERROR_CB_ID Error Callback ID
+ * @arg @ref HAL_TIM_COMMUTATION_CB_ID Commutation Callback ID
+ * @arg @ref HAL_TIM_BREAK_CB_ID Break Callback ID
+ * @retval status
+ */
+HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID)
+{
+ HAL_StatusTypeDef status = HAL_OK;
+
+ /* Process locked */
+ __HAL_LOCK(htim);
+
+ if(htim->State == HAL_TIM_STATE_READY)
+ {
+ switch (CallbackID)
+ {
+ case HAL_TIM_BASE_MSPINIT_CB_ID :
+ htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */
+ break;
+
+ case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+ htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */
+ break;
+
+ case HAL_TIM_IC_MSPINIT_CB_ID :
+ htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */
+ break;
+
+ case HAL_TIM_IC_MSPDEINIT_CB_ID :
+ htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */
+ break;
+
+ case HAL_TIM_OC_MSPINIT_CB_ID :
+ htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */
+ break;
+
+ case HAL_TIM_OC_MSPDEINIT_CB_ID :
+ htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */
+ break;
+
+ case HAL_TIM_PWM_MSPINIT_CB_ID :
+ htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */
+ break;
+
+ case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+ htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+ htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+ htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */
+ break;
+
+ case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+ htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */
+ break;
+
+ case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+ htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+ htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+ htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */
+ break;
+
+ case HAL_TIM_PERIOD_ELAPSED_CB_ID :
+ htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak Period Elapsed Callback */
+ break;
+
+ case HAL_TIM_TRIGGER_CB_ID :
+ htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak Trigger Callback */
+ break;
+
+ case HAL_TIM_IC_CAPTURE_CB_ID :
+ htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC Capture Callback */
+ break;
+
+ case HAL_TIM_OC_DELAY_ELAPSED_CB_ID :
+ htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC Delay Elapsed Callback */
+ break;
+
+ case HAL_TIM_PWM_PULSE_FINISHED_CB_ID :
+ htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM Pulse Finished Callback */
+ break;
+
+ case HAL_TIM_ERROR_CB_ID :
+ htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak Error Callback */
+ break;
+
+ case HAL_TIM_COMMUTATION_CB_ID :
+ htim->CommutationCallback = HAL_TIMEx_CommutationCallback; /* Legacy weak Commutation Callback */
+ break;
+
+ case HAL_TIM_BREAK_CB_ID :
+ htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak Break Callback */
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else if(htim->State == HAL_TIM_STATE_RESET)
+ {
+ switch (CallbackID)
+ {
+ case HAL_TIM_BASE_MSPINIT_CB_ID :
+ htim->Base_MspInitCallback = HAL_TIM_Base_MspInit; /* Legacy weak Base MspInit Callback */
+ break;
+
+ case HAL_TIM_BASE_MSPDEINIT_CB_ID :
+ htim->Base_MspDeInitCallback = HAL_TIM_Base_MspDeInit; /* Legacy weak Base Msp DeInit Callback */
+ break;
+
+ case HAL_TIM_IC_MSPINIT_CB_ID :
+ htim->IC_MspInitCallback = HAL_TIM_IC_MspInit; /* Legacy weak IC Msp Init Callback */
+ break;
+
+ case HAL_TIM_IC_MSPDEINIT_CB_ID :
+ htim->IC_MspDeInitCallback = HAL_TIM_IC_MspDeInit; /* Legacy weak IC Msp DeInit Callback */
+ break;
+
+ case HAL_TIM_OC_MSPINIT_CB_ID :
+ htim->OC_MspInitCallback = HAL_TIM_OC_MspInit; /* Legacy weak OC Msp Init Callback */
+ break;
+
+ case HAL_TIM_OC_MSPDEINIT_CB_ID :
+ htim->OC_MspDeInitCallback = HAL_TIM_OC_MspDeInit; /* Legacy weak OC Msp DeInit Callback */
+ break;
+
+ case HAL_TIM_PWM_MSPINIT_CB_ID :
+ htim->PWM_MspInitCallback = HAL_TIM_PWM_MspInit; /* Legacy weak PWM Msp Init Callback */
+ break;
+
+ case HAL_TIM_PWM_MSPDEINIT_CB_ID :
+ htim->PWM_MspDeInitCallback = HAL_TIM_PWM_MspDeInit; /* Legacy weak PWM Msp DeInit Callback */
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPINIT_CB_ID :
+ htim->OnePulse_MspInitCallback = HAL_TIM_OnePulse_MspInit; /* Legacy weak One Pulse Msp Init Callback */
+ break;
+
+ case HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID :
+ htim->OnePulse_MspDeInitCallback = HAL_TIM_OnePulse_MspDeInit; /* Legacy weak One Pulse Msp DeInit Callback */
+ break;
+
+ case HAL_TIM_ENCODER_MSPINIT_CB_ID :
+ htim->Encoder_MspInitCallback = HAL_TIM_Encoder_MspInit; /* Legacy weak Encoder Msp Init Callback */
+ break;
+
+ case HAL_TIM_ENCODER_MSPDEINIT_CB_ID :
+ htim->Encoder_MspDeInitCallback = HAL_TIM_Encoder_MspDeInit; /* Legacy weak Encoder Msp DeInit Callback */
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID :
+ htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit; /* Legacy weak Hall Sensor Msp Init Callback */
+ break;
+
+ case HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID :
+ htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit; /* Legacy weak Hall Sensor Msp DeInit Callback */
+ break;
+
+ default :
+ /* Return error status */
+ status = HAL_ERROR;
+ break;
+ }
+ }
+ else
+ {
+ /* Return error status */
+ status = HAL_ERROR;
+ }
+
+ /* Release Lock */
+ __HAL_UNLOCK(htim);
+
+ return status;
+}
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -4540,7 +5228,7 @@
/**
* @brief Return the TIM Base state
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @retval HAL state
*/
@@ -4551,7 +5239,7 @@
/**
* @brief Return the TIM OC state
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @retval HAL state
*/
@@ -4562,7 +5250,7 @@
/**
* @brief Return the TIM PWM state
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @retval HAL state
*/
@@ -4573,7 +5261,7 @@
/**
* @brief Return the TIM Input Capture state
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @retval HAL state
*/
@@ -4584,7 +5272,7 @@
/**
* @brief Return the TIM One Pulse Mode state
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @retval HAL state
*/
@@ -4595,7 +5283,7 @@
/**
* @brief Return the TIM Encoder Mode state
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @retval HAL state
*/
@@ -4610,7 +5298,7 @@
/**
* @brief TIM DMA error callback
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -4619,13 +5307,16 @@
TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
htim->State= HAL_TIM_STATE_READY;
-
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->ErrorCallback(htim);
+#else
HAL_TIM_ErrorCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/**
* @brief TIM DMA Delay Pulse complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -4652,13 +5343,16 @@
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
}
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->PWM_PulseFinishedCallback(htim);
+#else
HAL_TIM_PWM_PulseFinishedCallback(htim);
-
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}
/**
* @brief TIM DMA Capture complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -4684,31 +5378,36 @@
{
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_4;
}
-
- HAL_TIM_IC_CaptureCallback(htim);
-
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->IC_CaptureCallback(htim);
+#else
+ HAL_TIM_IC_CaptureCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
htim->Channel = HAL_TIM_ACTIVE_CHANNEL_CLEARED;
}
/**
* @brief TIM DMA Period Elapse complete callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
static void TIM_DMAPeriodElapsedCplt(DMA_HandleTypeDef *hdma)
{
TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
-
+
htim->State= HAL_TIM_STATE_READY;
-
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->PeriodElapsedCallback(htim);
+#else
HAL_TIM_PeriodElapsedCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/**
* @brief TIM DMA Trigger callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -4717,14 +5416,17 @@
TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
htim->State= HAL_TIM_STATE_READY;
-
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->TriggerCallback(htim);
+#else
HAL_TIM_TriggerCallback(htim);
+ #endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/**
* @brief Time Base configuration
- * @param TIMx: TIM peripheral
- * @param Structure: pointer on TIM Time Base required parameters
+ * @param TIMx TIM peripheral
+ * @param Structure pointer on TIM Time Base required parameters
* @retval None
*/
void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure)
@@ -4772,7 +5474,7 @@
/**
* @brief Time Output Compare 1 configuration
* @param TIMx to select the TIM peripheral
- * @param OC_Config: The output configuration structure
+ * @param OC_Config The output configuration structure
* @retval None
*/
void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
@@ -4837,7 +5539,7 @@
/**
* @brief Time Output Compare 2 configuration
* @param TIMx to select the TIM peripheral
- * @param OC_Config: The output configuration structure
+ * @param OC_Config The output configuration structure
* @retval None
*/
void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
@@ -4904,7 +5606,7 @@
/**
* @brief Time Output Compare 3 configuration
* @param TIMx to select the TIM peripheral
- * @param OC_Config: The output configuration structure
+ * @param OC_Config The output configuration structure
* @retval None
*/
void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
@@ -4970,7 +5672,7 @@
/**
* @brief Time Output Compare 4 configuration
* @param TIMx to select the TIM peripheral
- * @param OC_Config: The output configuration structure
+ * @param OC_Config The output configuration structure
* @retval None
*/
void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
@@ -5026,9 +5728,9 @@
/**
* @brief Time Output Compare 4 configuration
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param sSlaveConfig: The slave configuration structure
+ * @param sSlaveConfig The slave configuration structure
* @retval None
*/
static void TIM_SlaveTimer_SetConfig(TIM_HandleTypeDef *htim,
@@ -5159,17 +5861,17 @@
/**
* @brief Configure the TI1 as Input.
* @param TIMx to select the TIM peripheral.
- * @param TIM_ICPolarity : The Input Polarity.
+ * @param TIM_ICPolarity The Input Polarity.
* This parameter can be one of the following values:
* @arg TIM_ICPolarity_Rising
* @arg TIM_ICPolarity_Falling
* @arg TIM_ICPolarity_BothEdge
- * @param TIM_ICSelection: specifies the input to be used.
+ * @param TIM_ICSelection specifies the input to be used.
* This parameter can be one of the following values:
* @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
* @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
* @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
+ * @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI2FP1
@@ -5214,12 +5916,12 @@
/**
* @brief Configure the Polarity and Filter for TI1.
* @param TIMx to select the TIM peripheral.
- * @param TIM_ICPolarity : The Input Polarity.
+ * @param TIM_ICPolarity The Input Polarity.
* This parameter can be one of the following values:
* @arg TIM_ICPolarity_Rising
* @arg TIM_ICPolarity_Falling
* @arg TIM_ICPolarity_BothEdge
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
+ * @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
@@ -5249,17 +5951,17 @@
/**
* @brief Configure the TI2 as Input.
* @param TIMx to select the TIM peripheral
- * @param TIM_ICPolarity : The Input Polarity.
+ * @param TIM_ICPolarity The Input Polarity.
* This parameter can be one of the following values:
* @arg TIM_ICPolarity_Rising
* @arg TIM_ICPolarity_Falling
* @arg TIM_ICPolarity_BothEdge
- * @param TIM_ICSelection: specifies the input to be used.
+ * @param TIM_ICSelection specifies the input to be used.
* This parameter can be one of the following values:
* @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
* @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
* @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
+ * @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI1FP2
@@ -5297,12 +5999,12 @@
/**
* @brief Configure the Polarity and Filter for TI2.
* @param TIMx to select the TIM peripheral.
- * @param TIM_ICPolarity : The Input Polarity.
+ * @param TIM_ICPolarity The Input Polarity.
* This parameter can be one of the following values:
* @arg TIM_ICPolarity_Rising
* @arg TIM_ICPolarity_Falling
* @arg TIM_ICPolarity_BothEdge
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
+ * @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
*/
@@ -5332,17 +6034,17 @@
/**
* @brief Configure the TI3 as Input.
* @param TIMx to select the TIM peripheral
- * @param TIM_ICPolarity : The Input Polarity.
+ * @param TIM_ICPolarity The Input Polarity.
* This parameter can be one of the following values:
* @arg TIM_ICPolarity_Rising
* @arg TIM_ICPolarity_Falling
* @arg TIM_ICPolarity_BothEdge
- * @param TIM_ICSelection: specifies the input to be used.
+ * @param TIM_ICSelection specifies the input to be used.
* This parameter can be one of the following values:
* @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
* @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
* @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
+ * @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI3FP4
@@ -5380,17 +6082,17 @@
/**
* @brief Configure the TI4 as Input.
* @param TIMx to select the TIM peripheral
- * @param TIM_ICPolarity : The Input Polarity.
+ * @param TIM_ICPolarity The Input Polarity.
* This parameter can be one of the following values:
* @arg TIM_ICPolarity_Rising
* @arg TIM_ICPolarity_Falling
* @arg TIM_ICPolarity_BothEdge
- * @param TIM_ICSelection: specifies the input to be used.
+ * @param TIM_ICSelection specifies the input to be used.
* This parameter can be one of the following values:
* @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
* @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
* @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
- * @param TIM_ICFilter: Specifies the Input Capture Filter.
+ * @param TIM_ICFilter Specifies the Input Capture Filter.
* This parameter must be a value between 0x00 and 0x0F.
* @retval None
* @note TIM_ICFilter and TIM_ICPolarity are not used in INDIRECT mode as TI4FP3
@@ -5428,7 +6130,7 @@
/**
* @brief Selects the Input Trigger source
* @param TIMx to select the TIM peripheral
- * @param TIM_ITRx: The Input Trigger source.
+ * @param TIM_ITRx The Input Trigger source.
* This parameter can be one of the following values:
* @arg TIM_TS_ITR0: Internal Trigger 0
* @arg TIM_TS_ITR1: Internal Trigger 1
@@ -5457,17 +6159,17 @@
/**
* @brief Configures the TIMx External Trigger (ETR).
* @param TIMx to select the TIM peripheral
- * @param TIM_ExtTRGPrescaler: The external Trigger Prescaler.
+ * @param TIM_ExtTRGPrescaler The external Trigger Prescaler.
* This parameter can be one of the following values:
* @arg TIM_ExtTRGPSC_DIV1: ETRP Prescaler OFF.
* @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
* @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
* @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
- * @param TIM_ExtTRGPolarity: The external Trigger Polarity.
+ * @param TIM_ExtTRGPolarity The external Trigger Polarity.
* This parameter can be one of the following values:
* @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
* @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
- * @param ExtTRGFilter: External Trigger Filter.
+ * @param ExtTRGFilter External Trigger Filter.
* This parameter must be a value between 0x00 and 0x0F
* @retval None
*/
@@ -5491,13 +6193,13 @@
/**
* @brief Enables or disables the TIM Capture Compare Channel x.
* @param TIMx to select the TIM peripheral
- * @param Channel: specifies the TIM Channel
+ * @param Channel specifies the TIM Channel
* This parameter can be one of the following values:
* @arg TIM_Channel_1: TIM Channel 1
* @arg TIM_Channel_2: TIM Channel 2
* @arg TIM_Channel_3: TIM Channel 3
* @arg TIM_Channel_4: TIM Channel 4
- * @param ChannelState: specifies the TIM Channel CCxE bit new state.
+ * @param ChannelState specifies the TIM Channel CCxE bit new state.
* This parameter can be: TIM_CCx_ENABLE or TIM_CCx_Disable.
* @retval None
*/
@@ -5518,7 +6220,26 @@
TIMx->CCER |= (uint32_t)(ChannelState << Channel);
}
-
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+/**
+ * @brief Reset interrupt callbacks to the legacy week callbacks.
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
+ * the configuration information for TIM module.
+ * @retval None
+ */
+void TIM_ResetCallback(TIM_HandleTypeDef *htim)
+{
+ /* Reset the TIM callback to the legacy weak callbacks */
+ htim->PeriodElapsedCallback = HAL_TIM_PeriodElapsedCallback; /* Legacy weak PeriodElapsedCallback */
+ htim->TriggerCallback = HAL_TIM_TriggerCallback; /* Legacy weak TriggerCallback */
+ htim->IC_CaptureCallback = HAL_TIM_IC_CaptureCallback; /* Legacy weak IC_CaptureCallback */
+ htim->OC_DelayElapsedCallback = HAL_TIM_OC_DelayElapsedCallback; /* Legacy weak OC_DelayElapsedCallback */
+ htim->PWM_PulseFinishedCallback = HAL_TIM_PWM_PulseFinishedCallback; /* Legacy weak PWM_PulseFinishedCallback */
+ htim->ErrorCallback = HAL_TIM_ErrorCallback; /* Legacy weak ErrorCallback */
+ htim->CommutationCallback = HAL_TIMEx_CommutationCallback; /* Legacy weak CommutationCallback */
+ htim->BreakCallback = HAL_TIMEx_BreakCallback; /* Legacy weak BreakCallback */
+}
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
/**
* @}
*/
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_tim.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_tim.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_tim.h
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief Header file of TIM HAL module.
******************************************************************************
* @attention
@@ -290,7 +288,7 @@
/**
* @brief TIM Time Base Handle Structure definition
*/
-typedef struct
+typedef struct __TIM_HandleTypeDef
{
TIM_TypeDef *Instance; /*!< Register base address */
TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
@@ -299,7 +297,74 @@
This array is accessed by a @ref DMA_Handle_index */
HAL_LockTypeDef Lock; /*!< Locking object */
__IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ void (* Base_MspInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp Init Callback */
+ void (* Base_MspDeInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Base Msp DeInit Callback */
+ void (* IC_MspInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp Init Callback */
+ void (* IC_MspDeInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM IC Msp DeInit Callback */
+ void (* OC_MspInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp Init Callback */
+ void (* OC_MspDeInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM OC Msp DeInit Callback */
+ void (* PWM_MspInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp Init Callback */
+ void (* PWM_MspDeInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Msp DeInit Callback */
+ void (* OnePulse_MspInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp Init Callback */
+ void (* OnePulse_MspDeInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM One Pulse Msp DeInit Callback */
+ void (* Encoder_MspInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp Init Callback */
+ void (* Encoder_MspDeInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Encoder Msp DeInit Callback */
+ void (* HallSensor_MspInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp Init Callback */
+ void (* HallSensor_MspDeInitCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Hall Sensor Msp DeInit Callback */
+
+ void (* PeriodElapsedCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Period Elapsed Callback */
+ void (* TriggerCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Trigger Callback */
+ void (* IC_CaptureCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Input Capture Callback */
+ void (* OC_DelayElapsedCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Output Compare Delay Elapsed Callback */
+ void (* PWM_PulseFinishedCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM PWM Pulse Finished Callback */
+ void (* ErrorCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Error Callback */
+ void (* CommutationCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Commutation Callback */
+ void (* BreakCallback) (struct __TIM_HandleTypeDef *htim); /*!< TIM Break Callback */
+
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
}TIM_HandleTypeDef;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+/**
+ * @brief HAL TIM Callback ID enumeration definition
+ */
+typedef enum
+{
+ HAL_TIM_BASE_MSPINIT_CB_ID = 0x00U, /*!< TIM Base MspInit Callback ID */
+ HAL_TIM_BASE_MSPDEINIT_CB_ID = 0x01U, /*!< TIM Base MspDeInit Callback ID */
+ HAL_TIM_IC_MSPINIT_CB_ID = 0x02U, /*!< TIM IC MspInit Callback ID */
+ HAL_TIM_IC_MSPDEINIT_CB_ID = 0x03U, /*!< TIM IC MspDeInit Callback ID */
+ HAL_TIM_OC_MSPINIT_CB_ID = 0x04U, /*!< TIM OC MspInit Callback ID */
+ HAL_TIM_OC_MSPDEINIT_CB_ID = 0x05U, /*!< TIM OC MspDeInit Callback ID */
+ HAL_TIM_PWM_MSPINIT_CB_ID = 0x06U, /*!< TIM PWM MspInit Callback ID */
+ HAL_TIM_PWM_MSPDEINIT_CB_ID = 0x07U, /*!< TIM PWM MspDeInit Callback ID */
+ HAL_TIM_ONE_PULSE_MSPINIT_CB_ID = 0x08U, /*!< TIM One Pulse MspInit Callback ID */
+ HAL_TIM_ONE_PULSE_MSPDEINIT_CB_ID = 0x09U, /*!< TIM One Pulse MspDeInit Callback ID */
+ HAL_TIM_ENCODER_MSPINIT_CB_ID = 0x0AU, /*!< TIM Encoder MspInit Callback ID */
+ HAL_TIM_ENCODER_MSPDEINIT_CB_ID = 0x0BU, /*!< TIM Encoder MspDeInit Callback ID */
+ HAL_TIM_HALL_SENSOR_MSPINIT_CB_ID = 0x0CU, /*!< TIM Encoder MspDeInit Callback ID */
+ HAL_TIM_HALL_SENSOR_MSPDEINIT_CB_ID = 0x0DU, /*!< TIM Encoder MspDeInit Callback ID */
+
+ HAL_TIM_PERIOD_ELAPSED_CB_ID = 0x0EU, /*!< TIM Period Elapsed Callback ID */
+ HAL_TIM_TRIGGER_CB_ID = 0x0FU, /*!< TIM Trigger Callback ID */
+ HAL_TIM_IC_CAPTURE_CB_ID = 0x10U, /*!< TIM Input Capture Callback ID */
+ HAL_TIM_OC_DELAY_ELAPSED_CB_ID = 0x11U, /*!< TIM Output Compare Delay Elapsed Callback ID */
+ HAL_TIM_PWM_PULSE_FINISHED_CB_ID = 0x12U, /*!< TIM PWM Pulse Finished Callback ID */
+ HAL_TIM_ERROR_CB_ID = 0x13U, /*!< TIM Error Callback ID */
+ HAL_TIM_COMMUTATION_CB_ID = 0x14U, /*!< TIM Commutation Callback ID */
+ HAL_TIM_BREAK_CB_ID = 0x15U /*!< TIM Break Callback ID */
+
+}HAL_TIM_CallbackIDTypeDef;
+
+/**
+ * @brief HAL TIM Callback pointer definition
+ */
+typedef void (*pTIM_CallbackTypeDef)(TIM_HandleTypeDef * htim); /*!< pointer to the TIM callback function */
+
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
/**
* @}
*/
@@ -837,41 +902,35 @@
* @{
*/
/** @brief Reset TIM handle state
- * @param __HANDLE__: TIM handle
+ * @param __HANDLE__ TIM handle
* @retval None
*/
#define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
/**
* @brief Enable the TIM peripheral.
- * @param __HANDLE__: TIM handle
+ * @param __HANDLE__ TIM handle
* @retval None
*/
#define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
/**
* @brief Enable the TIM update source request.
- * @param __HANDLE__: TIM handle
+ * @param __HANDLE__ TIM handle
* @retval None
*/
#define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_URS))
/**
* @brief Enable the TIM main Output.
- * @param __HANDLE__: TIM handle
+ * @param __HANDLE__ TIM handle
* @retval None
*/
#define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
-
-/* The counter of a timer instance is disabled only if all the CCx and CCxN
- channels have been disabled */
-#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
-#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
-
/**
* @brief Disable the TIM peripheral.
- * @param __HANDLE__: TIM handle
+ * @param __HANDLE__ TIM handle
* @retval None
*/
#define __HAL_TIM_DISABLE(__HANDLE__) \
@@ -887,18 +946,16 @@
/**
* @brief Disable the TIM update source request.
- * @param __HANDLE__: TIM handle
+ * @param __HANDLE__ TIM handle
* @retval None
- */
+ */
#define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
-
-/* The Main Output of a timer instance is disabled only if all the CCx and CCxN
- channels have been disabled */
/**
* @brief Disable the TIM main Output.
- * @param __HANDLE__: TIM handle
+ * @param __HANDLE__ TIM handle
* @retval None
+ * @note The Main Output Enable of a timer instance is disabled only if all the CCx and CCxN channels have been disabled
*/
#define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
do { \
@@ -911,64 +968,181 @@
} \
} while(0)
+/** @brief Enable the specified TIM interrupt.
+ * @param __HANDLE__: specifies the TIM Handle.
+ * @param __INTERRUPT__: specifies the TIM interrupt source to enable.
+ * This parameter can be one of the following values:
+ * @arg TIM_IT_UPDATE: Update interrupt
+ * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
+ * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
+ * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
+ * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
+ * @arg TIM_IT_COM: Commutation interrupt
+ * @arg TIM_IT_TRIGGER: Trigger interrupt
+ * @arg TIM_IT_BREAK: Break interrupt
+ * @retval None
+ */
#define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
-#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
+
+/** @brief Disable the specified TIM interrupt.
+ * @param __HANDLE__: specifies the TIM Handle.
+ * @param __INTERRUPT__: specifies the TIM interrupt source to disable.
+ * This parameter can be one of the following values:
+ * @arg TIM_IT_UPDATE: Update interrupt
+ * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
+ * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
+ * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
+ * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
+ * @arg TIM_IT_COM: Commutation interrupt
+ * @arg TIM_IT_TRIGGER: Trigger interrupt
+ * @arg TIM_IT_BREAK: Break interrupt
+ * @retval None
+ */
#define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
+
+/** @brief Enable the specified DMA request.
+ * @param __HANDLE__: specifies the TIM Handle.
+ * @param __DMA__: specifies the TIM DMA request to enable.
+ * This parameter can be one of the following values:
+ * @arg TIM_DMA_UPDATE: Update DMA request
+ * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
+ * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
+ * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
+ * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
+ * @arg TIM_DMA_COM: Commutation DMA request
+ * @arg TIM_DMA_TRIGGER: Trigger DMA request
+ * @retval None
+ */
+#define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
+
+/** @brief Disable the specified DMA request.
+ * @param __HANDLE__: specifies the TIM Handle.
+ * @param __DMA__: specifies the TIM DMA request to disable.
+ * This parameter can be one of the following values:
+ * @arg TIM_DMA_UPDATE: Update DMA request
+ * @arg TIM_DMA_CC1: Capture/Compare 1 DMA request
+ * @arg TIM_DMA_CC2: Capture/Compare 2 DMA request
+ * @arg TIM_DMA_CC3: Capture/Compare 3 DMA request
+ * @arg TIM_DMA_CC4: Capture/Compare 4 DMA request
+ * @arg TIM_DMA_COM: Commutation DMA request
+ * @arg TIM_DMA_TRIGGER: Trigger DMA request
+ * @retval None
+ */
#define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
+
+/** @brief Check whether the specified TIM interrupt flag is set or not.
+ * @param __HANDLE__: specifies the TIM Handle.
+ * @param __FLAG__: specifies the TIM interrupt flag to check.
+ * This parameter can be one of the following values:
+ * @arg TIM_FLAG_UPDATE: Update interrupt flag
+ * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
+ * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
+ * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
+ * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
+ * @arg TIM_FLAG_COM: Commutation interrupt flag
+ * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
+ * @arg TIM_FLAG_BREAK: Break interrupt flag
+ * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
+ * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
+ * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
+ * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
+ * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
#define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
+
+/** @brief Clear the specified TIM interrupt flag.
+ * @param __HANDLE__: specifies the TIM Handle.
+ * @param __FLAG__: specifies the TIM interrupt flag to clear.
+ * This parameter can be one of the following values:
+ * @arg TIM_FLAG_UPDATE: Update interrupt flag
+ * @arg TIM_FLAG_CC1: Capture/Compare 1 interrupt flag
+ * @arg TIM_FLAG_CC2: Capture/Compare 2 interrupt flag
+ * @arg TIM_FLAG_CC3: Capture/Compare 3 interrupt flag
+ * @arg TIM_FLAG_CC4: Capture/Compare 4 interrupt flag
+ * @arg TIM_FLAG_COM: Commutation interrupt flag
+ * @arg TIM_FLAG_TRIGGER: Trigger interrupt flag
+ * @arg TIM_FLAG_BREAK: Break interrupt flag
+ * @arg TIM_FLAG_BREAK2: Break 2 interrupt flag
+ * @arg TIM_FLAG_CC1OF: Capture/Compare 1 overcapture flag
+ * @arg TIM_FLAG_CC2OF: Capture/Compare 2 overcapture flag
+ * @arg TIM_FLAG_CC3OF: Capture/Compare 3 overcapture flag
+ * @arg TIM_FLAG_CC4OF: Capture/Compare 4 overcapture flag
+ * @retval The new state of __FLAG__ (TRUE or FALSE).
+ */
#define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
+/**
+ * @brief Check whether the specified TIM interrupt source is enabled or not.
+ * @param __HANDLE__: TIM handle
+ * @param __INTERRUPT__: specifies the TIM interrupt source to check.
+ * This parameter can be one of the following values:
+ * @arg TIM_IT_UPDATE: Update interrupt
+ * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
+ * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
+ * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
+ * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
+ * @arg TIM_IT_COM: Commutation interrupt
+ * @arg TIM_IT_TRIGGER: Trigger interrupt
+ * @arg TIM_IT_BREAK: Break interrupt
+ * @retval The state of TIM_IT (SET or RESET).
+ */
#define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
+
+/** @brief Clear the TIM interrupt pending bits.
+ * @param __HANDLE__: TIM handle
+ * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
+ * This parameter can be one of the following values:
+ * @arg TIM_IT_UPDATE: Update interrupt
+ * @arg TIM_IT_CC1: Capture/Compare 1 interrupt
+ * @arg TIM_IT_CC2: Capture/Compare 2 interrupt
+ * @arg TIM_IT_CC3: Capture/Compare 3 interrupt
+ * @arg TIM_IT_CC4: Capture/Compare 4 interrupt
+ * @arg TIM_IT_COM: Commutation interrupt
+ * @arg TIM_IT_TRIGGER: Trigger interrupt
+ * @arg TIM_IT_BREAK: Break interrupt
+ * @retval None
+ */
#define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
+/**
+ * @brief Indicates whether or not the TIM Counter is used as downcounter.
+ * @param __HANDLE__: TIM handle.
+ * @retval False (Counter used as upcounter) or True (Counter used as downcounter)
+ * @note This macro is particularly useful to get the counting mode when the timer operates in Center-aligned mode or Encoder
+mode.
+ */
#define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
-#define __HAL_TIM_SET_PRESCALER (__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
-
-#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
- ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8)))
-
-#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
- ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
-#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\
- ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12) & TIM_CCER_CC4P)))
+/**
+ * @brief Set the TIM Prescaler on runtime.
+ * @param __HANDLE__: TIM handle.
+ * @param __PRESC__: specifies the Prescaler new value.
+ * @retval None
+ */
+#define __HAL_TIM_SET_PRESCALER(__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
-#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
-(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
- ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
- ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
- ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
-
/**
- * @brief Sets the TIM Counter Register value on runtime.
- * @param __HANDLE__: TIM handle.
- * @param __COUNTER__: specifies the Counter register new value.
+ * @brief Set the TIM Counter Register value on runtime.
+ * @param __HANDLE__ TIM handle.
+ * @param __COUNTER__ specifies the Counter register new value.
* @retval None
*/
#define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
/**
- * @brief Gets the TIM Counter Register value on runtime.
- * @param __HANDLE__: TIM handle.
- * @retval None
+ * @brief Get the TIM Counter Register value on runtime.
+ * @param __HANDLE__ TIM handle.
+ * @retval 16-bit or 32-bit value of the timer counter register
*/
#define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
/**
- * @brief Sets the TIM Autoreload Register value on runtime without calling
+ * @brief Set the TIM Autoreload Register value on runtime without calling
* another time any Init function.
- * @param __HANDLE__: TIM handle.
- * @param __AUTORELOAD__: specifies the Counter register new value.
- * @retval None
+ * @param __HANDLE__ TIM handle.
+ * @param __AUTORELOAD__ specifies the Counter register new value.
+ * @retval 16-bit or 32-bit value of the timer auto-reload
*/
#define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
do{ \
@@ -976,17 +1150,17 @@
(__HANDLE__)->Init.Period = (__AUTORELOAD__); \
} while(0)
/**
- * @brief Gets the TIM Autoreload Register value on runtime
- * @param __HANDLE__: TIM handle.
+ * @brief Get the TIM Autoreload Register value on runtime
+ * @param __HANDLE__ TIM handle.
* @retval None
*/
#define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
/**
- * @brief Sets the TIM Clock Division value on runtime without calling
+ * @brief Set the TIM Clock Division value on runtime without calling
* another time any Init function.
- * @param __HANDLE__: TIM handle.
- * @param __CKD__: specifies the clock division value.
+ * @param __HANDLE__ TIM handle.
+ * @param __CKD__ specifies the clock division value.
* This parameter can be one of the following value:
* @arg TIM_CLOCKDIVISION_DIV1
* @arg TIM_CLOCKDIVISION_DIV2
@@ -1000,23 +1174,26 @@
(__HANDLE__)->Init.ClockDivision = (__CKD__); \
} while(0)
/**
- * @brief Gets the TIM Clock Division value on runtime
- * @param __HANDLE__: TIM handle.
- * @retval None
+ * @brief Get the TIM Clock Division value on runtime
+ * @param __HANDLE__ TIM handle.
+ * @retval The clock division can be one of the following values:
+ * @arg TIM_CLOCKDIVISION_DIV1: tDTS=tCK_INT
+ * @arg TIM_CLOCKDIVISION_DIV2: tDTS=2*tCK_INT
+ * @arg TIM_CLOCKDIVISION_DIV4: tDTS=4*tCK_INT
*/
#define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
/**
- * @brief Sets the TIM Input Capture prescaler on runtime without calling
+ * @brief Set the TIM Input Capture prescaler on runtime without calling
* another time HAL_TIM_IC_ConfigChannel() function.
- * @param __HANDLE__: TIM handle.
- * @param __CHANNEL__ : TIM Channels to be configured.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param __ICPSC__: specifies the Input Capture4 prescaler new value.
+ * @param __ICPSC__ specifies the Input Capture4 prescaler new value.
* This parameter can be one of the following values:
* @arg TIM_ICPSC_DIV1: no prescaler
* @arg TIM_ICPSC_DIV2: capture is done once every 2 events
@@ -1031,15 +1208,19 @@
} while(0)
/**
- * @brief Gets the TIM Input Capture prescaler on runtime
- * @param __HANDLE__: TIM handle.
- * @param __CHANNEL__ : TIM Channels to be configured.
+ * @brief Get the TIM Input Capture prescaler on runtime
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: get input capture 1 prescaler value
* @arg TIM_CHANNEL_2: get input capture 2 prescaler value
* @arg TIM_CHANNEL_3: get input capture 3 prescaler value
* @arg TIM_CHANNEL_4: get input capture 4 prescaler value
- * @retval None
+ * @retval The input capture prescaler can be one of the following values:
+ * @arg TIM_ICPSC_DIV1: no prescaler
+ * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+ * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+ * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
*/
#define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
@@ -1048,15 +1229,15 @@
(((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
/**
- * @brief Sets the TIM Capture x input polarity on runtime.
- * @param __HANDLE__: TIM handle.
- * @param __CHANNEL__: TIM Channels to be configured.
+ * @brief Set the TIM Capture x input polarity on runtime.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param __POLARITY__: Polarity for TIx source
+ * @param __POLARITY__ Polarity for TIx source
* @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
* @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
* @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
@@ -1072,6 +1253,7 @@
/**
* @}
*/
+/* End of exported macros ----------------------------------------------------*/
/* Include TIM HAL Extension module */
#include "stm32f7xx_hal_tim_ex.h"
@@ -1133,6 +1315,7 @@
HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
+
/* Blocking mode: Polling */
HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
@@ -1258,6 +1441,12 @@
void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
+/* Callbacks Register/UnRegister functions ***********************************/
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+HAL_StatusTypeDef HAL_TIM_RegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID, pTIM_CallbackTypeDef pCallback);
+HAL_StatusTypeDef HAL_TIM_UnRegisterCallback(TIM_HandleTypeDef *htim, HAL_TIM_CallbackIDTypeDef CallbackID);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
/**
* @}
*/
@@ -1280,7 +1469,20 @@
/**
* @}
*/
-
+
+/* Private constants ---------------------------------------------------------*/
+/** @defgroup TIM_Private_Constants TIM Private Constants
+ * @{
+ */
+/* The counter of a timer instance is disabled only if all the CCx and CCxN
+ channels have been disabled */
+#define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
+#define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
+/**
+ * @}
+ */
+/* End of private constants --------------------------------------------------*/
+
/* Private macros ------------------------------------------------------------*/
/** @defgroup TIM_Private_Macros TIM Private Macros
* @{
@@ -1516,15 +1718,50 @@
((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
+/**
+ * @}
+ */
+/** @defgroup TIM_ICPRESCALER TIM Private macros to SET/RESET TIM Input capture value
+ * @{
+ */
+#define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
+ ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8)))
+
+#define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
+ ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
+/**
+ * @}
+ */
+
+/** @defgroup TIM_CAPTUREPOLARITY TIM Private macros to SET/RESET TIM capture polarity value
+ * @{
+ */
+#define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\
+ ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12) & TIM_CCER_CC4P)))
+
+#define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
+(((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
+ ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
+ ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
+/**
+ * @}
+ */
/**
* @}
*/
-
-/**
- * @}
- */
+/* End of private macros -----------------------------------------------------*/
/* Private functions ---------------------------------------------------------*/
/** @defgroup TIM_Private_Functions TIM Private Functions
@@ -1542,10 +1779,16 @@
void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma);
void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+void TIM_ResetCallback(TIM_HandleTypeDef *htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
/**
* @}
*/
-
+/* End of private functions --------------------------------------------------*/
+
/**
* @}
*/
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_tim_ex.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_tim_ex.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_tim_ex.c
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief TIM HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Timer extension peripheral:
@@ -158,9 +156,9 @@
*/
/**
* @brief Initializes the TIM Hall Sensor Interface and create the associated handle.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param sConfig: TIM Hall Sensor configuration structure
+ * @param sConfig TIM Hall Sensor configuration structure
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Init(TIM_HandleTypeDef *htim, TIM_HallSensor_InitTypeDef* sConfig)
@@ -181,12 +179,30 @@
assert_param(IS_TIM_IC_PRESCALER(sConfig->IC1Prescaler));
assert_param(IS_TIM_IC_FILTER(sConfig->IC1Filter));
+ if(htim->State == HAL_TIM_STATE_RESET)
+ {
+ /* Allocate lock resource and initialize it */
+ htim->Lock = HAL_UNLOCKED;
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ /* Reset interrupt callbacks to legacy week callbacks */
+ TIM_ResetCallback(htim);
+
+ if(htim->HallSensor_MspInitCallback == NULL)
+ {
+ htim->HallSensor_MspInitCallback = HAL_TIMEx_HallSensor_MspInit;
+ }
+ /* Init the low level hardware : GPIO, CLOCK, NVIC */
+ htim->HallSensor_MspInitCallback(htim);
+#else
+ /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
+ HAL_TIMEx_HallSensor_MspInit(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+ }
+
/* Set the TIM state */
htim->State= HAL_TIM_STATE_BUSY;
-
- /* Init the low level hardware : GPIO, CLOCK, NVIC and DMA */
- HAL_TIMEx_HallSensor_MspInit(htim);
-
+
/* Configure the Time base in the Encoder Mode */
TIM_Base_SetConfig(htim->Instance, &htim->Init);
@@ -233,7 +249,7 @@
/**
* @brief DeInitializes the TIM Hall Sensor interface
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @retval HAL status
*/
@@ -246,10 +262,19 @@
/* Disable the TIM Peripheral Clock */
__HAL_TIM_DISABLE(htim);
-
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ if(htim->HallSensor_MspDeInitCallback == NULL)
+ {
+ htim->HallSensor_MspDeInitCallback = HAL_TIMEx_HallSensor_MspDeInit;
+ }
+ /* DeInit the low level hardware */
+ htim->HallSensor_MspDeInitCallback(htim);
+#else
/* DeInit the low level hardware: GPIO, CLOCK, NVIC */
HAL_TIMEx_HallSensor_MspDeInit(htim);
-
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
+
/* Change TIM state */
htim->State = HAL_TIM_STATE_RESET;
@@ -261,7 +286,7 @@
/**
* @brief Initializes the TIM Hall Sensor MSP.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @retval None
*/
@@ -277,7 +302,7 @@
/**
* @brief DeInitializes TIM Hall Sensor MSP.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @retval None
*/
@@ -293,7 +318,7 @@
/**
* @brief Starts the TIM Hall Sensor Interface.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @retval HAL status
*/
@@ -315,7 +340,7 @@
/**
* @brief Stops the TIM Hall sensor Interface.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @retval HAL status
*/
@@ -337,7 +362,7 @@
/**
* @brief Starts the TIM Hall Sensor Interface in interrupt mode.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @retval HAL status
*/
@@ -362,7 +387,7 @@
/**
* @brief Stops the TIM Hall Sensor Interface in interrupt mode.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @retval HAL status
*/
@@ -387,10 +412,10 @@
/**
* @brief Starts the TIM Hall Sensor Interface in DMA mode.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param pData: The destination Buffer address.
- * @param Length: The length of data to be transferred from TIM peripheral to memory.
+ * @param pData The destination Buffer address.
+ * @param Length The length of data to be transferred from TIM peripheral to memory.
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_HallSensor_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length)
@@ -437,7 +462,7 @@
/**
* @brief Stops the TIM Hall Sensor Interface in DMA mode.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @retval HAL status
*/
@@ -488,14 +513,13 @@
/**
* @brief Starts the TIM Output Compare signal generation on the complementary
* output.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param Channel: TIM Channel to be enabled.
+ * @param Channel TIM Channel to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
@@ -519,14 +543,13 @@
/**
* @brief Stops the TIM Output Compare signal generation on the complementary
* output.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param Channel: TIM Channel to be disabled.
+ * @param Channel TIM Channel to be disabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
@@ -550,14 +573,13 @@
/**
* @brief Starts the TIM Output Compare signal generation in interrupt mode
* on the complementary output.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param Channel: TIM Channel to be enabled.
+ * @param Channel TIM Channel to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
@@ -618,14 +640,13 @@
/**
* @brief Stops the TIM Output Compare signal generation in interrupt mode
* on the complementary output.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param Channel: TIM Channel to be disabled.
+ * @param Channel TIM Channel to be disabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
@@ -692,16 +713,15 @@
/**
* @brief Starts the TIM Output Compare signal generation in DMA mode
* on the complementary output.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param Channel: TIM Channel to be enabled.
+ * @param Channel TIM Channel to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param pData: The source Buffer address.
- * @param Length: The length of data to be transferred from memory to TIM peripheral
+ * @param pData The source Buffer address.
+ * @param Length The length of data to be transferred from memory to TIM peripheral
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
@@ -810,14 +830,13 @@
/**
* @brief Stops the TIM Output Compare signal generation in DMA mode
* on the complementary output.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param Channel: TIM Channel to be disabled.
+ * @param Channel TIM Channel to be disabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_OCN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
@@ -911,14 +930,13 @@
/**
* @brief Starts the PWM signal generation on the complementary output.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param Channel: TIM Channel to be enabled.
+ * @param Channel TIM Channel to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start(TIM_HandleTypeDef *htim, uint32_t Channel)
@@ -941,14 +959,13 @@
/**
* @brief Stops the PWM signal generation on the complementary output.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param Channel: TIM Channel to be disabled.
+ * @param Channel TIM Channel to be disabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop(TIM_HandleTypeDef *htim, uint32_t Channel)
@@ -972,14 +989,13 @@
/**
* @brief Starts the PWM signal generation in interrupt mode on the
* complementary output.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param Channel: TIM Channel to be disabled.
+ * @param Channel TIM Channel to be disabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel)
@@ -1040,14 +1056,13 @@
/**
* @brief Stops the PWM signal generation in interrupt mode on the
* complementary output.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param Channel: TIM Channel to be disabled.
+ * @param Channel TIM Channel to be disabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_IT (TIM_HandleTypeDef *htim, uint32_t Channel)
@@ -1114,16 +1129,15 @@
/**
* @brief Starts the TIM PWM signal generation in DMA mode on the
* complementary output
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param Channel: TIM Channel to be enabled.
+ * @param Channel TIM Channel to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
- * @param pData: The source Buffer address.
- * @param Length: The length of data to be transferred from memory to TIM peripheral
+ * @param pData The source Buffer address.
+ * @param Length The length of data to be transferred from memory to TIM peripheral
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length)
@@ -1232,14 +1246,13 @@
/**
* @brief Stops the TIM PWM signal generation in DMA mode on the complementary
* output
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param Channel: TIM Channel to be disabled.
+ * @param Channel TIM Channel to be disabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
* @arg TIM_CHANNEL_3: TIM Channel 3 selected
- * @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_PWMN_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel)
@@ -1322,9 +1335,9 @@
/**
* @brief Starts the TIM One Pulse signal generation on the complemetary
* output.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param OutputChannel: TIM Channel to be enabled.
+ * @param OutputChannel TIM Channel to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1348,9 +1361,9 @@
/**
* @brief Stops the TIM One Pulse signal generation on the complementary
* output.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param OutputChannel: TIM Channel to be disabled.
+ * @param OutputChannel TIM Channel to be disabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1378,9 +1391,9 @@
/**
* @brief Starts the TIM One Pulse signal generation in interrupt mode on the
* complementary channel.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param OutputChannel: TIM Channel to be enabled.
+ * @param OutputChannel TIM Channel to be enabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1410,9 +1423,9 @@
/**
* @brief Stops the TIM One Pulse signal generation in interrupt mode on the
* complementary channel.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param OutputChannel: TIM Channel to be disabled.
+ * @param OutputChannel TIM Channel to be disabled.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -1473,16 +1486,16 @@
* configured in Hall sensor interface, this interface Timer will generate the
* commutation at its TRGO output (connected to Timer used in this function) each time
* the TI1 of the Interface Timer detect a commutation at its input TI1.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
+ * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
* This parameter can be one of the following values:
* @arg TIM_TS_ITR0: Internal trigger 0 selected
* @arg TIM_TS_ITR1: Internal trigger 1 selected
* @arg TIM_TS_ITR2: Internal trigger 2 selected
* @arg TIM_TS_ITR3: Internal trigger 3 selected
* @arg TIM_TS_NONE: No trigger is needed
- * @param CommutationSource: the Commutation Event source.
+ * @param CommutationSource the Commutation Event source.
* This parameter can be one of the following values:
* @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
@@ -1523,16 +1536,16 @@
* configured in Hall sensor interface, this interface Timer will generate the
* commutation at its TRGO output (connected to Timer used in this function) each time
* the TI1 of the Interface Timer detect a commutation at its input TI1.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
+ * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
* This parameter can be one of the following values:
* @arg TIM_TS_ITR0: Internal trigger 0 selected
* @arg TIM_TS_ITR1: Internal trigger 1 selected
* @arg TIM_TS_ITR2: Internal trigger 2 selected
* @arg TIM_TS_ITR3: Internal trigger 3 selected
* @arg TIM_TS_NONE: No trigger is needed
- * @param CommutationSource: the Commutation Event source.
+ * @param CommutationSource the Commutation Event source.
* This parameter can be one of the following values:
* @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
@@ -1577,16 +1590,16 @@
* commutation at its TRGO output (connected to Timer used in this function) each time
* the TI1 of the Interface Timer detect a commutation at its input TI1.
* @note: The user should configure the DMA in his own software, in This function only the COMDE bit is set
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param InputTrigger: the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
+ * @param InputTrigger the Internal trigger corresponding to the Timer Interfacing with the Hall sensor.
* This parameter can be one of the following values:
* @arg TIM_TS_ITR0: Internal trigger 0 selected
* @arg TIM_TS_ITR1: Internal trigger 1 selected
* @arg TIM_TS_ITR2: Internal trigger 2 selected
* @arg TIM_TS_ITR3: Internal trigger 3 selected
* @arg TIM_TS_NONE: No trigger is needed
- * @param CommutationSource: the Commutation Event source.
+ * @param CommutationSource the Commutation Event source.
* This parameter can be one of the following values:
* @arg TIM_COMMUTATION_TRGI: Commutation source is the TRGI of the Interface Timer
* @arg TIM_COMMUTATION_SOFTWARE: Commutation source is set by software using the COMG bit
@@ -1630,9 +1643,9 @@
/**
* @brief Configures the TIM in master mode.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param sMasterConfig: pointer to a TIM_MasterConfigTypeDef structure that
+ * @param sMasterConfig pointer to a TIM_MasterConfigTypeDef structure that
* contains the selected trigger output (TRGO) and the Master/Slave
* mode.
* @retval HAL status
@@ -1692,9 +1705,9 @@
/**
* @brief Configures the Break feature, dead time, Lock level, OSSI/OSSR State
* and the AOE(automatic output enable).
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param sBreakDeadTimeConfig: pointer to a TIM_ConfigBreakDeadConfig_TypeDef structure that
+ * @param sBreakDeadTimeConfig pointer to a TIM_ConfigBreakDeadConfig_TypeDef structure that
* contains the BDTR Register configuration information for the TIM peripheral.
* @retval HAL status
*/
@@ -1719,8 +1732,6 @@
/* Check input state */
__HAL_LOCK(htim);
-
- htim->State = HAL_TIM_STATE_BUSY;
/* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
the OSSI State, the dead time value and the Automatic Output Enable Bit */
@@ -1759,12 +1770,12 @@
#if defined (STM32F765xx) || defined(STM32F767xx) || defined(STM32F769xx) || defined(STM32F777xx) || defined(STM32F779xx)
/**
* @brief Configures the break input source.
- * @param htim: TIM handle.
- * @param BreakInput: Break input to configure
+ * @param htim TIM handle.
+ * @param BreakInput Break input to configure
* This parameter can be one of the following values:
* @arg TIM_BREAKINPUT_BRK: Timer break input
* @arg TIM_BREAKINPUT_BRK2: Timer break 2 input
- * @param sBreakInputConfig: Break input source configuration
+ * @param sBreakInputConfig Break input source configuration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_TIMEx_ConfigBreakInput(TIM_HandleTypeDef *htim,
@@ -1774,13 +1785,19 @@
{
uint32_t tmporx = 0;
uint32_t bkin_enable_mask = 0;
+ uint32_t bkin_polarity_mask = 0;
uint32_t bkin_enable_bitpos = 0;
+ uint32_t bkin_polarity_bitpos = 0;
/* Check the parameters */
assert_param(IS_TIM_BREAK_INSTANCE(htim->Instance));
assert_param(IS_TIM_BREAKINPUT(BreakInput));
assert_param(IS_TIM_BREAKINPUTSOURCE(sBreakInputConfig->Source));
assert_param(IS_TIM_BREAKINPUTSOURCE_STATE(sBreakInputConfig->Enable));
+ if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
+ {
+ assert_param(IS_TIM_BREAKINPUTSOURCE_POLARITY(sBreakInputConfig->Polarity));
+ }
/* Check input state */
__HAL_LOCK(htim);
@@ -1791,6 +1808,8 @@
{
bkin_enable_mask = TIM1_AF1_BKINE;
bkin_enable_bitpos = 0;
+ bkin_polarity_mask = TIM1_AF1_BKINP;
+ bkin_polarity_bitpos = 9;
}
break;
@@ -1816,6 +1835,11 @@
tmporx &= ~bkin_enable_mask;
tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
+ if(sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
+ {
+ tmporx &= ~bkin_polarity_mask;
+ tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
+ }
/* Set TIMx_AF1 */
htim->Instance->AF1 = tmporx;
}
@@ -1824,11 +1848,17 @@
{
/* Get the TIMx_AF2 register value */
tmporx = htim->Instance->AF2;
-
+
/* Enable the break input */
tmporx &= ~bkin_enable_mask;
tmporx |= (sBreakInputConfig->Enable << bkin_enable_bitpos) & bkin_enable_mask;
-
+
+ if (sBreakInputConfig->Source != TIM_BREAKINPUTSOURCE_DFSDM1)
+ {
+ tmporx &= ~bkin_polarity_mask;
+ tmporx |= (sBreakInputConfig->Polarity << bkin_polarity_bitpos) & bkin_polarity_mask;
+ }
+
/* Set TIMx_AF2 */
htim->Instance->AF2 = tmporx;
}
@@ -1845,9 +1875,9 @@
/**
* @brief Configures the TIM2, TIM5 and TIM11 Remapping input capabilities.
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
- * @param Remap: specifies the TIM input remapping source.
+ * @param Remap specifies the TIM input remapping source.
* This parameter can be one of the following values:
* @arg TIM_TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default)
* @arg TIM_TIM2_ETH_PTP: TIM2 ITR1 input is connected to ETH PTP trigger output.
@@ -1884,8 +1914,8 @@
/**
* @brief Group channel 5 and channel 1, 2 or 3
- * @param htim: TIM handle.
- * @param OCRef: specifies the reference signal(s) the OC5REF is combined with.
+ * @param htim TIM handle.
+ * @param OCRef specifies the reference signal(s) the OC5REF is combined with.
* This parameter can be any combination of the following values:
* TIM_GROUPCH5_NONE: No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC
* TIM_GROUPCH5_OC1REFC: OC1REFC is the logical AND of OC1REFC and OC5REF
@@ -1938,7 +1968,7 @@
/**
* @brief Hall commutation changed callback in non blocking mode
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @retval None
*/
@@ -1954,7 +1984,7 @@
/**
* @brief Hall Break detection callback in non blocking mode
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @retval None
*/
@@ -1989,7 +2019,7 @@
/**
* @brief Return the TIM Hall Sensor interface state
- * @param htim: pointer to a TIM_HandleTypeDef structure that contains
+ * @param htim pointer to a TIM_HandleTypeDef structure that contains
* the configuration information for TIM module.
* @retval HAL state
*/
@@ -2004,7 +2034,7 @@
/**
* @brief TIM DMA Commutation callback.
- * @param hdma: pointer to a DMA_HandleTypeDef structure that contains
+ * @param hdma pointer to a DMA_HandleTypeDef structure that contains
* the configuration information for the specified DMA module.
* @retval None
*/
@@ -2013,8 +2043,12 @@
TIM_HandleTypeDef* htim = ( TIM_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
htim->State= HAL_TIM_STATE_READY;
-
+
+#if (USE_HAL_TIM_REGISTER_CALLBACKS == 1)
+ htim->CommutationCallback(htim);
+#else
HAL_TIMEx_CommutationCallback(htim);
+#endif /* USE_HAL_TIM_REGISTER_CALLBACKS */
}
/**
* @}
@@ -2022,10 +2056,10 @@
/**
* @brief Configures the OCRef clear feature
- * @param htim: TIM handle
- * @param sClearInputConfig: pointer to a TIM_ClearInputConfigTypeDef structure that
+ * @param htim TIM handle
+ * @param sClearInputConfig pointer to a TIM_ClearInputConfigTypeDef structure that
* contains the OCREF clear feature and parameters for the TIM peripheral.
- * @param Channel: specifies the TIM Channel
+ * @param Channel specifies the TIM Channel
* This parameter can be one of the following values:
* @arg TIM_Channel_1: TIM Channel 1
* @arg TIM_Channel_2: TIM Channel 2
@@ -2178,9 +2212,9 @@
/**
* @brief Initializes the TIM Output Compare Channels according to the specified
* parameters in the TIM_OC_InitTypeDef.
- * @param htim: TIM Output Compare handle
- * @param sConfig: TIM Output Compare configuration structure
- * @param Channel : TIM Channels to configure
+ * @param htim TIM Output Compare handle
+ * @param sConfig TIM Output Compare configuration structure
+ * @param Channel TIM Channels to configure
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2278,9 +2312,9 @@
/**
* @brief Initializes the TIM PWM channels according to the specified
* parameters in the TIM_OC_InitTypeDef.
- * @param htim: TIM PWM handle
- * @param sConfig: TIM PWM configuration structure
- * @param Channel : TIM Channels to be configured
+ * @param htim TIM PWM handle
+ * @param sConfig TIM PWM configuration structure
+ * @param Channel TIM Channels to be configured
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -2423,12 +2457,12 @@
/**
* @brief Enables or disables the TIM Capture Compare Channel xN.
* @param TIMx to select the TIM peripheral
- * @param Channel: specifies the TIM Channel
+ * @param Channel specifies the TIM Channel
* This parameter can be one of the following values:
* @arg TIM_Channel_1: TIM Channel 1
* @arg TIM_Channel_2: TIM Channel 2
* @arg TIM_Channel_3: TIM Channel 3
- * @param ChannelNState: specifies the TIM Channel CCxNE bit new state.
+ * @param ChannelNState specifies the TIM Channel CCxNE bit new state.
* This parameter can be: TIM_CCxN_ENABLE or TIM_CCxN_Disable.
* @retval None
*/
@@ -2452,7 +2486,7 @@
/**
* @brief Timer Output Compare 5 configuration
* @param TIMx to select the TIM peripheral
- * @param OC_Config: The output configuration structure
+ * @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC5_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
@@ -2504,7 +2538,7 @@
/**
* @brief Timer Output Compare 6 configuration
* @param TIMx to select the TIM peripheral
- * @param OC_Config: The output configuration structure
+ * @param OC_Config The output configuration structure
* @retval None
*/
static void TIM_OC6_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config)
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_tim_ex.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_tim_ex.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_tim_ex.h
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief Header file of TIM HAL Extension module.
******************************************************************************
* @attention
@@ -130,6 +128,9 @@
This parameter can be a value of @ref TIMEx_Break_Input_Source */
uint32_t Enable; /*!< Specifies whether or not the break input source is enabled.
This parameter can be a value of @ref TIMEx_Break_Input_Source_Enable */
+ uint32_t Polarity; /*!< Specifies the break input source polarity.
+ This parameter can be a value of @ref TIMEx_Break_Input_Source_Polarity
+ Not relevant when analog watchdog output of the DFSDM1 used as break input source */
} TIMEx_BreakInputConfigTypeDef;
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
/**
@@ -284,7 +285,7 @@
* @{
*/
#define TIM_BREAKINPUTSOURCE_BKIN ((uint32_t)0x00000001U) /* !< An external source (GPIO) is connected to the BKIN pin */
-#define TIM_BREAKINPUTSOURCE_DFSDM1 ((uint32_t)0x00000008U) /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */
+#define TIM_BREAKINPUTSOURCE_DFSDM1 ((uint32_t)0x00000008U) /* !< The analog watchdog output of the DFSDM1 peripheral is connected to the break input */
/**
* @}
*/
@@ -298,6 +299,15 @@
* @}
*/
+/** @defgroup TIMEx_Break_Input_Source_Polarity TIM Extended Break input polarity
+ * @{
+ */
+#define TIM_BREAKINPUTSOURCE_POLARITY_LOW ((uint32_t)(0x00000001)) /* !< Break input source is active low */
+#define TIM_BREAKINPUTSOURCE_POLARITY_HIGH ((uint32_t)(0x00000000)) /* !< Break input source is active_high */
+/**
+ * @}
+ */
+
/**
* @}
*/
@@ -314,8 +324,8 @@
/**
* @brief Sets the TIM Capture Compare Register value on runtime without
* calling another time ConfigChannel function.
- * @param __HANDLE__: TIM handle.
- * @param __CHANNEL__ : TIM Channels to be configured.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -323,7 +333,7 @@
* @arg TIM_CHANNEL_4: TIM Channel 4 selected
* @arg TIM_CHANNEL_5: TIM Channel 5 selected
* @arg TIM_CHANNEL_6: TIM Channel 6 selected
- * @param __COMPARE__: specifies the Capture Compare register new value.
+ * @param __COMPARE__ specifies the Capture Compare register new value.
* @retval None
*/
#define __HAL_TIM_SET_COMPARE(__HANDLE__, __CHANNEL__, __COMPARE__) \
@@ -336,8 +346,8 @@
/**
* @brief Gets the TIM Capture Compare Register value on runtime
- * @param __HANDLE__: TIM handle.
- * @param __CHANNEL__ : TIM Channel associated with the capture compare register
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channel associated with the capture compare register
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: get capture/compare 1 register value
* @arg TIM_CHANNEL_2: get capture/compare 2 register value
@@ -357,8 +367,8 @@
/**
* @brief Sets the TIM Output compare preload.
- * @param __HANDLE__: TIM handle.
- * @param __CHANNEL__: TIM Channels to be configured.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -378,8 +388,8 @@
/**
* @brief Resets the TIM Output compare preload.
- * @param __HANDLE__: TIM handle.
- * @param __CHANNEL__: TIM Channels to be configured.
+ * @param __HANDLE__ TIM handle.
+ * @param __CHANNEL__ TIM Channels to be configured.
* This parameter can be one of the following values:
* @arg TIM_CHANNEL_1: TIM Channel 1 selected
* @arg TIM_CHANNEL_2: TIM Channel 2 selected
@@ -616,7 +626,10 @@
#define IS_TIM_BREAKINPUTSOURCE_STATE(__STATE__) (((__STATE__) == TIM_BREAKINPUTSOURCE_DISABLE) || \
((__STATE__) == TIM_BREAKINPUTSOURCE_ENABLE))
-
+
+#define IS_TIM_BREAKINPUTSOURCE_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_LOW) || \
+ ((__POLARITY__) == TIM_BREAKINPUTSOURCE_POLARITY_HIGH))
+
#endif /* STM32F767xx || STM32F769xx || STM32F777xx || STM32F779xx */
/**
* @}
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_uart.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_uart.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_uart.c * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief UART HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Universal Asynchronous Receiver Transmitter (UART) peripheral: @@ -237,7 +235,7 @@ /** * @brief Initializes the UART mode according to the specified * parameters in the UART_InitTypeDef and creates the associated handle . - * @param huart: uart handle + * @param huart uart handle * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Init(UART_HandleTypeDef *huart) @@ -300,7 +298,7 @@ /** * @brief Initializes the half-duplex mode according to the specified * parameters in the UART_InitTypeDef and creates the associated handle . - * @param huart: UART handle + * @param huart UART handle * @retval HAL status */ HAL_StatusTypeDef HAL_HalfDuplex_Init(UART_HandleTypeDef *huart) @@ -356,8 +354,8 @@ /** * @brief Initialize the LIN mode according to the specified * parameters in the UART_InitTypeDef and creates the associated handle . - * @param huart: UART handle. - * @param BreakDetectLength: specifies the LIN break detection length. + * @param huart UART handle. + * @param BreakDetectLength specifies the LIN break detection length. * This parameter can be one of the following values: * @arg @ref UART_LINBREAKDETECTLENGTH_10B 10-bit break detection * @arg @ref UART_LINBREAKDETECTLENGTH_11B 11-bit break detection @@ -424,9 +422,9 @@ /** * @brief Initialize the multiprocessor mode according to the specified * parameters in the UART_InitTypeDef and initialize the associated handle. - * @param huart: UART handle. - * @param Address: UART node address (4-, 6-, 7- or 8-bit long). - * @param WakeUpMethod: specifies the UART wakeup method. + * @param huart UART handle. + * @param Address UART node address (4-, 6-, 7- or 8-bit long). + * @param WakeUpMethod specifies the UART wakeup method. * This parameter can be one of the following values: * @arg @ref UART_WAKEUPMETHOD_IDLELINE WakeUp by an idle line detection * @arg @ref UART_WAKEUPMETHOD_ADDRESSMARK WakeUp by an address mark @@ -499,16 +497,16 @@ /** * @brief Initialize the RS485 Driver enable feature according to the specified * parameters in the UART_InitTypeDef and creates the associated handle. - * @param huart: UART handle. - * @param Polarity: select the driver enable polarity. + * @param huart UART handle. + * @param Polarity select the driver enable polarity. * This parameter can be one of the following values: * @arg @ref UART_DE_POLARITY_HIGH DE signal is active high * @arg @ref UART_DE_POLARITY_LOW DE signal is active low - * @param AssertionTime: Driver Enable assertion time: + * @param AssertionTime Driver Enable assertion time: * 5-bit value defining the time between the activation of the DE (Driver Enable) * signal and the beginning of the start bit. It is expressed in sample time * units (1/8 or 1/16 bit time, depending on the oversampling rate) - * @param DeassertionTime: Driver Enable deassertion time: + * @param DeassertionTime Driver Enable deassertion time: * 5-bit value defining the time between the end of the last stop bit, in a * transmitted message, and the de-activation of the DE (Driver Enable) signal. * It is expressed in sample time units (1/8 or 1/16 bit time, depending on the @@ -581,7 +579,7 @@ /** * @brief DeInitializes the UART peripheral - * @param huart: uart handle + * @param huart uart handle * @retval HAL status */ HAL_StatusTypeDef HAL_UART_DeInit(UART_HandleTypeDef *huart) @@ -619,7 +617,7 @@ /** * @brief UART MSP Init - * @param huart: uart handle + * @param huart uart handle * @retval None */ __weak void HAL_UART_MspInit(UART_HandleTypeDef *huart) @@ -634,7 +632,7 @@ /** * @brief UART MSP DeInit - * @param huart: uart handle + * @param huart uart handle * @retval None */ __weak void HAL_UART_MspDeInit(UART_HandleTypeDef *huart) @@ -709,10 +707,10 @@ /** * @brief Send an amount of data in blocking mode. - * @param huart: UART handle. - * @param pData: Pointer to data buffer. - * @param Size: Amount of data to be sent. - * @param Timeout: Timeout duration. + * @param huart UART handle. + * @param pData Pointer to data buffer. + * @param Size Amount of data to be sent. + * @param Timeout Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) @@ -778,10 +776,10 @@ /** * @brief Receive an amount of data in blocking mode. - * @param huart: UART handle. - * @param pData: pointer to data buffer. - * @param Size: amount of data to be received. - * @param Timeout: Timeout duration. + * @param huart UART handle. + * @param pData pointer to data buffer. + * @param Size amount of data to be received. + * @param Timeout Timeout duration. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size, uint32_t Timeout) @@ -850,9 +848,9 @@ /** * @brief Send an amount of data in interrupt mode. - * @param huart: UART handle. - * @param pData: pointer to data buffer. - * @param Size: amount of data to be sent. + * @param huart UART handle. + * @param pData pointer to data buffer. + * @param Size amount of data to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) @@ -891,9 +889,9 @@ /** * @brief Receive an amount of data in interrupt mode. - * @param huart: UART handle. - * @param pData: pointer to data buffer. - * @param Size: amount of data to be received. + * @param huart UART handle. + * @param pData pointer to data buffer. + * @param Size amount of data to be received. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Receive_IT(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) @@ -938,9 +936,9 @@ /** * @brief Send an amount of data in DMA mode. - * @param huart: UART handle. - * @param pData: pointer to data buffer. - * @param Size: amount of data to be sent. + * @param huart UART handle. + * @param pData pointer to data buffer. + * @param Size amount of data to be sent. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_Transmit_DMA(UART_HandleTypeDef *huart, uint8_t *pData, uint16_t Size) @@ -1001,9 +999,9 @@ /** * @brief Receive an amount of data in DMA mode. - * @param huart: UART handle. - * @param pData: pointer to data buffer. - * @param Size: amount of data to be received. + * @param huart UART handle. + * @param pData pointer to data buffer. + * @param Size amount of data to be received. * @note When the UART parity is enabled (PCE = 1), the received data contain * the parity bit (MSB position). * @retval HAL status @@ -1068,7 +1066,7 @@ /** * @brief Pause the DMA Transfer. - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_DMAPause(UART_HandleTypeDef *huart) @@ -1101,7 +1099,7 @@ /** * @brief Resume the DMA Transfer. - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_DMAResume(UART_HandleTypeDef *huart) @@ -1139,7 +1137,7 @@ /** * @brief Stop the DMA Transfer. - * @param huart: UART handle. + * @param huart UART handle. * @retval HAL status */ HAL_StatusTypeDef HAL_UART_DMAStop(UART_HandleTypeDef *huart) @@ -1186,7 +1184,7 @@ /** * @brief This function handles UART interrupt request. - * @param huart: uart handle + * @param huart uart handle * @retval None */ void HAL_UART_IRQHandler(UART_HandleTypeDef *huart) @@ -1362,7 +1360,7 @@ /** * @brief DMA UART transmit process complete callback - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void UART_DMATransmitCplt(DMA_HandleTypeDef *hdma) @@ -1390,7 +1388,7 @@ /** * @brief DMA UART transmit process half complete callback - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void UART_DMATxHalfCplt(DMA_HandleTypeDef *hdma) @@ -1402,7 +1400,7 @@ /** * @brief DMA UART receive process complete callback - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void UART_DMAReceiveCplt(DMA_HandleTypeDef *hdma) @@ -1430,7 +1428,7 @@ /** * @brief DMA UART receive process half complete callback - * @param hdma : DMA handle + * @param hdma DMA handle * @retval None */ static void UART_DMARxHalfCplt(DMA_HandleTypeDef *hdma) @@ -1442,7 +1440,7 @@ /** * @brief DMA UART communication error callback - * @param hdma: DMA handle + * @param hdma DMA handle * @retval None */ static void UART_DMAError(DMA_HandleTypeDef *hdma) @@ -1470,7 +1468,7 @@ /** * @brief DMA UART communication abort callback, when call by HAL services on Error * (To be called at end of DMA Abort procedure following error occurrence). - * @param hdma: DMA handle. + * @param hdma DMA handle. * @retval None */ static void UART_DMAAbortOnError(DMA_HandleTypeDef *hdma) @@ -1484,7 +1482,7 @@ /** * @brief Tx Transfer completed callbacks - * @param huart: uart handle + * @param huart uart handle * @retval None */ __weak void HAL_UART_TxCpltCallback(UART_HandleTypeDef *huart) @@ -1499,7 +1497,7 @@ /** * @brief Tx Half Transfer completed callbacks. - * @param huart: UART handle + * @param huart UART handle * @retval None */ __weak void HAL_UART_TxHalfCpltCallback(UART_HandleTypeDef *huart) @@ -1514,7 +1512,7 @@ /** * @brief Rx Transfer completed callbacks - * @param huart: uart handle + * @param huart uart handle * @retval None */ __weak void HAL_UART_RxCpltCallback(UART_HandleTypeDef *huart) @@ -1529,7 +1527,7 @@ /** * @brief Rx Half Transfer completed callbacks. - * @param huart: UART handle + * @param huart UART handle * @retval None */ __weak void HAL_UART_RxHalfCpltCallback(UART_HandleTypeDef *huart) @@ -1544,7 +1542,7 @@ /** * @brief UART error callbacks - * @param huart: uart handle + * @param huart uart handle * @retval None */ __weak void HAL_UART_ErrorCallback(UART_HandleTypeDef *huart) @@ -1561,7 +1559,7 @@ * @brief Send an amount of data in interrupt mode * Function called under interruption only, once * interruptions have been enabled by HAL_UART_Transmit_IT() - * @param huart: UART handle + * @param huart UART handle * @retval HAL status */ static HAL_StatusTypeDef UART_Transmit_IT(UART_HandleTypeDef *huart) @@ -1608,7 +1606,7 @@ /** * @brief Wrap up transmission in non-blocking mode. - * @param huart: pointer to a UART_HandleTypeDef structure that contains + * @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART module. * @retval HAL status */ @@ -1629,7 +1627,7 @@ * @brief Receive an amount of data in interrupt mode * Function called under interruption only, once * interruptions have been enabled by HAL_UART_Receive_IT() - * @param huart: UART handle + * @param huart UART handle * @retval HAL status */ static HAL_StatusTypeDef UART_Receive_IT(UART_HandleTypeDef *huart) @@ -1681,7 +1679,7 @@ /** * @brief End ongoing Tx transfer on UART peripheral (following error detection or Transmit completion). - * @param huart: UART handle. + * @param huart UART handle. * @retval None */ static void UART_EndTxTransfer(UART_HandleTypeDef *huart) @@ -1696,7 +1694,7 @@ /** * @brief End ongoing Rx transfer on UART peripheral (following error detection or Reception completion). - * @param huart: UART handle. + * @param huart UART handle. * @retval None */ static void UART_EndRxTransfer(UART_HandleTypeDef *huart) @@ -1742,7 +1740,7 @@ /** * @brief Enable UART in mute mode (doesn't mean UART enters mute mode; * to enter mute mode, HAL_MultiProcessor_EnterMuteMode() API must be called) - * @param huart: UART handle + * @param huart UART handle * @retval HAL status */ HAL_StatusTypeDef HAL_MultiProcessor_EnableMuteMode(UART_HandleTypeDef *huart) @@ -1763,7 +1761,7 @@ /** * @brief Disable UART mute mode (doesn't mean it actually wakes up the software, * as it may not have been in mute mode at this very moment). - * @param huart: uart handle + * @param huart uart handle * @retval HAL status */ HAL_StatusTypeDef HAL_MultiProcessor_DisableMuteMode(UART_HandleTypeDef *huart) @@ -1784,7 +1782,7 @@ /** * @brief Enter UART mute mode (means UART actually enters mute mode). * To exit from mute mode, HAL_MultiProcessor_DisableMuteMode() API must be called. - * @param huart: uart handle + * @param huart uart handle * @retval HAL status */ void HAL_MultiProcessor_EnterMuteMode(UART_HandleTypeDef *huart) @@ -1796,7 +1794,7 @@ /** * @brief return the UART state - * @param huart: uart handle + * @param huart uart handle * @retval HAL state */ HAL_UART_StateTypeDef HAL_UART_GetState(UART_HandleTypeDef *huart) @@ -1810,7 +1808,7 @@ /** * @brief Return the UART error code -* @param huart : pointer to a UART_HandleTypeDef structure that contains +* @param huart pointer to a UART_HandleTypeDef structure that contains * the configuration information for the specified UART. * @retval UART Error Code */ @@ -1821,7 +1819,7 @@ /** * @brief Configure the UART peripheral - * @param huart: uart handle + * @param huart uart handle * @retval None */ HAL_StatusTypeDef UART_SetConfig(UART_HandleTypeDef *huart) @@ -1932,7 +1930,7 @@ /** * @brief Configure the UART peripheral advanced features - * @param huart: uart handle + * @param huart uart handle * @retval None */ void UART_AdvFeatureConfig(UART_HandleTypeDef *huart) @@ -2007,7 +2005,7 @@ /** * @brief Check the UART Idle State - * @param huart: uart handle + * @param huart uart handle * @retval HAL status */ HAL_StatusTypeDef UART_CheckIdleState(UART_HandleTypeDef *huart) @@ -2043,7 +2041,7 @@ /** * @brief Enables the UART transmitter and disables the UART receiver. - * @param huart: UART handle + * @param huart UART handle * @retval HAL status * @retval None */ @@ -2067,7 +2065,7 @@ /** * @brief Enables the UART receiver and disables the UART transmitter. - * @param huart: UART handle + * @param huart UART handle * @retval HAL status */ HAL_StatusTypeDef HAL_HalfDuplex_EnableReceiver(UART_HandleTypeDef *huart) @@ -2091,7 +2089,7 @@ /** * @brief Transmits break characters. - * @param huart: UART handle + * @param huart UART handle * @retval HAL status */ HAL_StatusTypeDef HAL_LIN_SendBreak(UART_HandleTypeDef *huart) @@ -2122,8 +2120,8 @@ * long). * @note Addresses detection lengths are: 6-bit address detection in 7-bit data mode, * 7-bit address detection in 8-bit data mode, 8-bit address detection in 9-bit data mode. - * @param huart: UART handle. - * @param AddressLength: this parameter can be one of the following values: + * @param huart UART handle. + * @param AddressLength this parameter can be one of the following values: * @arg @ref UART_ADDRESS_DETECT_4B 4-bit long address * @arg @ref UART_ADDRESS_DETECT_7B 6-, 7- or 8-bit long address * @retval HAL status
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_uart.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_uart.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_uart.h
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief Header file of UART HAL module.
******************************************************************************
* @attention
@@ -671,7 +669,7 @@
*/
/** @brief Reset UART handle state
- * @param __HANDLE__: UART handle.
+ * @param __HANDLE__ UART handle.
* @retval None
*/
#define __HAL_UART_RESET_HANDLE_STATE(__HANDLE__) do{ \
@@ -680,7 +678,7 @@
} while(0)
/** @brief Flush the UART Data registers
- * @param __HANDLE__: specifies the UART Handle.
+ * @param __HANDLE__ specifies the UART Handle.
*/
#define __HAL_UART_FLUSH_DRREGISTER(__HANDLE__) \
do{ \
@@ -689,8 +687,8 @@
} while(0)
/** @brief Clears the specified UART ISR flag, in setting the proper ICR register flag.
- * @param __HANDLE__: specifies the UART Handle.
- * @param __FLAG__: specifies the interrupt clear register flag that needs to be set
+ * @param __HANDLE__ specifies the UART Handle.
+ * @param __FLAG__ specifies the interrupt clear register flag that needs to be set
* to clear the corresponding interrupt
* This parameter can be one of the following values:
* @arg UART_CLEAR_PEF: Parity Error Clear Flag
@@ -709,38 +707,38 @@
#define __HAL_UART_CLEAR_IT(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__FLAG__))
/** @brief Clear the UART PE pending flag.
- * @param __HANDLE__: specifies the UART Handle.
+ * @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
#define __HAL_UART_CLEAR_PEFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_PEF)
/** @brief Clear the UART FE pending flag.
- * @param __HANDLE__: specifies the UART Handle.
+ * @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
#define __HAL_UART_CLEAR_FEFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_FEF)
/** @brief Clear the UART NE pending flag.
- * @param __HANDLE__: specifies the UART Handle.
+ * @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
#define __HAL_UART_CLEAR_NEFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_NEF)
/** @brief Clear the UART ORE pending flag.
- * @param __HANDLE__: specifies the UART Handle.
+ * @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
#define __HAL_UART_CLEAR_OREFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_OREF)
/** @brief Clear the UART IDLE pending flag.
- * @param __HANDLE__: specifies the UART Handle.
+ * @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
#define __HAL_UART_CLEAR_IDLEFLAG(__HANDLE__) __HAL_UART_CLEAR_IT((__HANDLE__),UART_CLEAR_IDLEF)
/** @brief Checks whether the specified UART flag is set or not.
- * @param __HANDLE__: specifies the UART Handle.
- * @param __FLAG__: specifies the flag to check.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg UART_FLAG_REACK: Receive enable acknowledge flag
* @arg UART_FLAG_TEACK: Transmit enable acknowledge flag
@@ -768,8 +766,8 @@
#define __HAL_UART_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->ISR & (__FLAG__)) == (__FLAG__))
/** @brief Enables the specified UART interrupt.
- * @param __HANDLE__: specifies the UART Handle.
- * @param __INTERRUPT__: specifies the UART interrupt source to enable.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @param __INTERRUPT__ specifies the UART interrupt source to enable.
* This parameter can be one of the following values:
* @arg UART_IT_WUF: Wakeup from stop mode interrupt
* @arg UART_IT_CM: Character match interrupt
@@ -789,8 +787,8 @@
/** @brief Disables the specified UART interrupt.
- * @param __HANDLE__: specifies the UART Handle.
- * @param __INTERRUPT__: specifies the UART interrupt source to disable.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @param __INTERRUPT__ specifies the UART interrupt source to disable.
* This parameter can be one of the following values:
* @arg UART_IT_CM: Character match interrupt
* @arg UART_IT_CTS: CTS change interrupt
@@ -808,8 +806,8 @@
((__HANDLE__)->Instance->CR3 &= ~ (1U << ((__INTERRUPT__) & UART_IT_MASK))))
/** @brief Checks whether the specified UART interrupt has occurred or not.
- * @param __HANDLE__: specifies the UART Handle.
- * @param __IT__: specifies the UART interrupt to check.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @param __IT__ specifies the UART interrupt to check.
* This parameter can be one of the following values:
* @arg UART_IT_CM: Character match interrupt
* @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
@@ -827,8 +825,8 @@
#define __HAL_UART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
/** @brief Checks whether the specified UART interrupt source is enabled.
- * @param __HANDLE__: specifies the UART Handle.
- * @param __IT__: specifies the UART interrupt source to check.
+ * @param __HANDLE__ specifies the UART Handle.
+ * @param __IT__ specifies the UART interrupt source to check.
* This parameter can be one of the following values:
* @arg UART_IT_CTS: CTS change interrupt (not available for UART4 and UART5)
* @arg UART_IT_LBD: LIN Break detection interrupt
@@ -846,8 +844,8 @@
(__HANDLE__)->Instance->CR2 : (__HANDLE__)->Instance->CR3)) & ((uint32_t)1 << (((uint16_t)(__IT__)) & UART_IT_MASK)))
/** @brief Set a specific UART request flag.
- * @param __HANDLE__: specifies the UART Handle.
- * @param __REQ__: specifies the request flag to set
+ * @param __HANDLE__ specifies the UART Handle.
+ * @param __REQ__ specifies the request flag to set
* This parameter can be one of the following values:
* @arg UART_AUTOBAUD_REQUEST: Auto-Baud Rate Request
* @arg UART_SENDBREAK_REQUEST: Send Break Request
@@ -859,25 +857,25 @@
#define __HAL_UART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint32_t)(__REQ__))
/** @brief Enables the UART one bit sample method
- * @param __HANDLE__: specifies the UART Handle.
+ * @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
#define __HAL_UART_ONE_BIT_SAMPLE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3|= USART_CR3_ONEBIT)
/** @brief Disables the UART one bit sample method
- * @param __HANDLE__: specifies the UART Handle.
+ * @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
#define __HAL_UART_ONE_BIT_SAMPLE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR3 &= (uint32_t)~((uint32_t)USART_CR3_ONEBIT))
/** @brief Enable UART
- * @param __HANDLE__: specifies the UART Handle.
+ * @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
#define __HAL_UART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
/** @brief Disable UART
- * @param __HANDLE__: specifies the UART Handle.
+ * @param __HANDLE__ specifies the UART Handle.
* @retval None
*/
#define __HAL_UART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
@@ -891,7 +889,7 @@
* - UART instance should have already been initialised (through call of HAL_UART_Init() )
* - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
* and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
- * @param __HANDLE__: specifies the UART Handle.
+ * @param __HANDLE__ specifies the UART Handle.
* The Handle Instance can be USART1, USART2 or LPUART.
* @retval None
*/
@@ -910,7 +908,7 @@
* - UART instance should have already been initialised (through call of HAL_UART_Init() )
* - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
* and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
- * @param __HANDLE__: specifies the UART Handle.
+ * @param __HANDLE__ specifies the UART Handle.
* The Handle Instance can be USART1, USART2 or LPUART.
* @retval None
*/
@@ -929,7 +927,7 @@
* - UART instance should have already been initialised (through call of HAL_UART_Init() )
* - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
* and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
- * @param __HANDLE__: specifies the UART Handle.
+ * @param __HANDLE__ specifies the UART Handle.
* The Handle Instance can be USART1, USART2 or LPUART.
* @retval None
*/
@@ -948,7 +946,7 @@
* - UART instance should have already been initialised (through call of HAL_UART_Init() )
* - macro could only be called when corresponding UART instance is disabled (i.e __HAL_UART_DISABLE(__HANDLE__))
* and should be followed by an Enable macro (i.e __HAL_UART_ENABLE(__HANDLE__)).
- * @param __HANDLE__: specifies the UART Handle.
+ * @param __HANDLE__ specifies the UART Handle.
* The Handle Instance can be USART1, USART2 or LPUART.
* @retval None
*/
@@ -967,28 +965,28 @@
* @{
*/
/** @brief BRR division operation to set BRR register with LPUART
- * @param _PCLK_: LPUART clock
- * @param _BAUD_: Baud rate set by the user
+ * @param _PCLK_ LPUART clock
+ * @param _BAUD_ Baud rate set by the user
* @retval Division result
*/
#define UART_DIV_LPUART(_PCLK_, _BAUD_) ((((_PCLK_)*256)+((_BAUD_)/2))/((_BAUD_)))
/** @brief BRR division operation to set BRR register in 8-bit oversampling mode
- * @param _PCLK_: UART clock
- * @param _BAUD_: Baud rate set by the user
+ * @param _PCLK_ UART clock
+ * @param _BAUD_ Baud rate set by the user
* @retval Division result
*/
#define UART_DIV_SAMPLING8(_PCLK_, _BAUD_) ((((_PCLK_)*2)+((_BAUD_)/2))/((_BAUD_)))
/** @brief BRR division operation to set BRR register in 16-bit oversampling mode
- * @param _PCLK_: UART clock
- * @param _BAUD_: Baud rate set by the user
+ * @param _PCLK_ UART clock
+ * @param _BAUD_ Baud rate set by the user
* @retval Division result
*/
#define UART_DIV_SAMPLING16(_PCLK_, _BAUD_) ((((_PCLK_))+((_BAUD_)/2))/((_BAUD_)))
/** @brief Check UART Baud rate
- * @param BAUDRATE: Baudrate specified by the user
+ * @param BAUDRATE Baudrate specified by the user
* The maximum Baud Rate is derived from the maximum clock on F7 (i.e. 216 MHz)
* divided by the smallest oversampling used on the USART (i.e. 8)
* @retval Test result (TRUE or FALSE).
@@ -996,13 +994,13 @@
#define IS_UART_BAUDRATE(BAUDRATE) ((BAUDRATE) < 9000001)
/** @brief Check UART assertion time
- * @param TIME: 5-bit value assertion time
+ * @param TIME 5-bit value assertion time
* @retval Test result (TRUE or FALSE).
*/
#define IS_UART_ASSERTIONTIME(TIME) ((TIME) <= 0x1F)
/** @brief Check UART deassertion time
- * @param TIME: 5-bit value deassertion time
+ * @param TIME 5-bit value deassertion time
* @retval Test result (TRUE or FALSE).
*/
#define IS_UART_DEASSERTIONTIME(TIME) ((TIME) <= 0x1F)
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_uart_ex.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_uart_ex.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_uart_ex.h
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief Header file of UART HAL Extension module.
******************************************************************************
* @attention
@@ -98,8 +96,8 @@
*/
/** @brief Reports the UART clock source.
- * @param __HANDLE__: specifies the UART Handle
- * @param __CLOCKSOURCE__: output variable
+ * @param __HANDLE__ specifies the UART Handle
+ * @param __CLOCKSOURCE__ output variable
* @retval UART clocking source, written in __CLOCKSOURCE__.
*/
#define UART_GETCLOCKSOURCE(__HANDLE__,__CLOCKSOURCE__) \
@@ -272,7 +270,7 @@
* by the reception API().
* This masking operation is not carried out in the case of
* DMA transfers.
- * @param __HANDLE__: specifies the UART Handle
+ * @param __HANDLE__ specifies the UART Handle
* @retval mask to apply to UART RDR register value.
*/
#define UART_MASK_COMPUTATION(__HANDLE__) \
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_usart.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_usart.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_usart.c
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief USART HAL module driver.
* This file provides firmware functions to manage the following
* functionalities of the Universal Synchronous/Asynchronous Receiver Transmitter
@@ -185,7 +183,7 @@
/**
* @brief Initializes the USART mode according to the specified
* parameters in the USART_InitTypeDef and create the associated handle.
- * @param husart: USART handle
+ * @param husart USART handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Init(USART_HandleTypeDef *husart)
@@ -233,7 +231,7 @@
/**
* @brief DeInitializes the USART peripheral
- * @param husart: USART handle
+ * @param husart USART handle
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_DeInit(USART_HandleTypeDef *husart)
@@ -267,7 +265,7 @@
/**
* @brief USART MSP Init
- * @param husart: USART handle
+ * @param husart USART handle
* @retval None
*/
__weak void HAL_USART_MspInit(USART_HandleTypeDef *husart)
@@ -282,7 +280,7 @@
/**
* @brief USART MSP DeInit
- * @param husart: USART handle
+ * @param husart USART handle
* @retval None
*/
__weak void HAL_USART_MspDeInit(USART_HandleTypeDef *husart)
@@ -358,10 +356,10 @@
/**
* @brief Simplex Send an amount of data in blocking mode
- * @param husart: USART handle
- * @param pTxData: pointer to data buffer
- * @param Size: amount of data to be sent
- * @param Timeout : Timeout duration
+ * @param husart USART handle
+ * @param pTxData pointer to data buffer
+ * @param Size amount of data to be sent
+ * @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Transmit(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size, uint32_t Timeout)
@@ -429,10 +427,10 @@
/**
* @brief Receive an amount of data in blocking mode
* @note To receive synchronous data, dummy data are simultaneously transmitted
- * @param husart: USART handle
- * @param pRxData: pointer to data buffer
- * @param Size: amount of data to be received
- * @param Timeout : Timeout duration
+ * @param husart USART handle
+ * @param pRxData pointer to data buffer
+ * @param Size amount of data to be received
+ * @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Receive(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
@@ -511,11 +509,11 @@
/**
* @brief Full-Duplex Send and Receive an amount of data in blocking mode
- * @param husart: USART handle
- * @param pTxData: pointer to TX data buffer
- * @param pRxData: pointer to RX data buffer
- * @param Size: amount of data to be sent (same amount to be received)
- * @param Timeout : Timeout duration
+ * @param husart USART handle
+ * @param pTxData pointer to TX data buffer
+ * @param pRxData pointer to RX data buffer
+ * @param Size amount of data to be sent (same amount to be received)
+ * @param Timeout Timeout duration
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_TransmitReceive(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size, uint32_t Timeout)
@@ -603,9 +601,9 @@
/**
* @brief Send an amount of data in interrupt mode
- * @param husart: USART handle
- * @param pTxData: pointer to data buffer
- * @param Size: amount of data to be sent
+ * @param husart USART handle
+ * @param pTxData pointer to data buffer
+ * @param Size amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Transmit_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
@@ -637,7 +635,7 @@
__HAL_UNLOCK(husart);
/* Enable the USART Transmit Data Register Empty Interrupt */
- SET_BIT(husart->Instance->CR3, USART_CR3_EIE);
+ __HAL_USART_ENABLE_IT(husart, USART_IT_TXE);
return HAL_OK;
}
@@ -650,9 +648,9 @@
/**
* @brief Receive an amount of data in blocking mode
* To receive synchronous data, dummy data are simultaneously transmitted
- * @param husart: USART handle
- * @param pRxData: pointer to data buffer
- * @param Size: amount of data to be received
+ * @param husart USART handle
+ * @param pRxData pointer to data buffer
+ * @param Size amount of data to be received
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Receive_IT(USART_HandleTypeDef *husart, uint8_t *pRxData, uint16_t Size)
@@ -705,10 +703,10 @@
/**
* @brief Full-Duplex Send and Receive an amount of data in interrupt mode
- * @param husart: USART handle
- * @param pTxData: pointer to TX data buffer
- * @param pRxData: pointer to RX data buffer
- * @param Size: amount of data to be sent (same amount to be received)
+ * @param husart USART handle
+ * @param pTxData pointer to TX data buffer
+ * @param pRxData pointer to RX data buffer
+ * @param Size amount of data to be sent (same amount to be received)
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_TransmitReceive_IT(USART_HandleTypeDef *husart, uint8_t *pTxData, uint8_t *pRxData, uint16_t Size)
@@ -761,9 +759,9 @@
/**
* @brief Send an amount of data in DMA mode
- * @param husart: USART handle
- * @param pTxData: pointer to data buffer
- * @param Size: amount of data to be sent
+ * @param husart USART handle
+ * @param pTxData pointer to data buffer
+ * @param Size amount of data to be sent
* @retval HAL status
*/
HAL_StatusTypeDef HAL_USART_Transmit_DMA(USART_HandleTypeDef *husart, uint8_t *pTxData, uint16_t Size)
@@ -823,9 +821,9 @@
/**
* @brief Receive an amount of data in DMA mode
- * @param husart: USART handle
- * @param pRxData: pointer to data buffer
- * @param Size: amount of data to be received
+ * @param husart USART handle
+ * @param pRxData pointer to data buffer
+ * @param Size amount of data to be received
* @note When the USART parity is enabled (PCE = 1), the received data contain
* the parity bit (MSB position)
* @retval HAL status
@@ -914,10 +912,10 @@
/**
* @brief Full-Duplex Transmit Receive an amount of data in non blocking mode
- * @param husart: USART handle
- * @param pTxData: pointer to TX data buffer
- * @param pRxData: pointer to RX data buffer
- * @param Size: amount of data to be received/sent
+ * @param husart USART handle
+ * @param pTxData pointer to TX data buffer
+ * @param pRxData pointer to RX data buffer
+ * @param Size amount of data to be received/sent
* @note When the USART parity is enabled (PCE = 1) the data received contain the parity bit.
* @retval HAL status
*/
@@ -1002,7 +1000,7 @@
/**
* @brief Pauses the DMA Transfer.
- * @param husart: USART handle
+ * @param husart USART handle
* @retval None
*/
HAL_StatusTypeDef HAL_USART_DMAPause(USART_HandleTypeDef *husart)
@@ -1039,7 +1037,7 @@
/**
* @brief Resumes the DMA Transfer.
- * @param husart: USART handle
+ * @param husart USART handle
* @retval None
*/
HAL_StatusTypeDef HAL_USART_DMAResume(USART_HandleTypeDef *husart)
@@ -1084,7 +1082,7 @@
/**
* @brief Stops the DMA Transfer.
- * @param husart: USART handle
+ * @param husart USART handle
* @retval None
*/
HAL_StatusTypeDef HAL_USART_DMAStop(USART_HandleTypeDef *husart)
@@ -1133,7 +1131,7 @@
/**
* @brief This function handles USART interrupt request.
- * @param husart: USART handle
+ * @param husart USART handle
* @retval None
*/
void HAL_USART_IRQHandler(USART_HandleTypeDef *husart)
@@ -1281,7 +1279,7 @@
/**
* @brief Tx Transfer completed callbacks
- * @param husart: USART handle
+ * @param husart USART handle
* @retval None
*/
__weak void HAL_USART_TxCpltCallback(USART_HandleTypeDef *husart)
@@ -1296,7 +1294,7 @@
/**
* @brief Tx Half Transfer completed callbacks.
- * @param husart: USART handle
+ * @param husart USART handle
* @retval None
*/
__weak void HAL_USART_TxHalfCpltCallback(USART_HandleTypeDef *husart)
@@ -1311,7 +1309,7 @@
/**
* @brief Rx Transfer completed callbacks.
- * @param husart: USART handle
+ * @param husart USART handle
* @retval None
*/
__weak void HAL_USART_RxCpltCallback(USART_HandleTypeDef *husart)
@@ -1326,7 +1324,7 @@
/**
* @brief Rx Half Transfer completed callbacks
- * @param husart: usart handle
+ * @param husart usart handle
* @retval None
*/
__weak void HAL_USART_RxHalfCpltCallback(USART_HandleTypeDef *husart)
@@ -1341,7 +1339,7 @@
/**
* @brief Tx/Rx Transfers completed callback for the non-blocking process
- * @param husart: USART handle
+ * @param husart USART handle
* @retval None
*/
__weak void HAL_USART_TxRxCpltCallback(USART_HandleTypeDef *husart)
@@ -1356,7 +1354,7 @@
/**
* @brief USART error callbacks
- * @param husart: USART handle
+ * @param husart USART handle
* @retval None
*/
__weak void HAL_USART_ErrorCallback(USART_HandleTypeDef *husart)
@@ -1394,7 +1392,7 @@
/**
* @brief return the USART state
- * @param husart: USART handle
+ * @param husart USART handle
* @retval HAL state
*/
HAL_USART_StateTypeDef HAL_USART_GetState(USART_HandleTypeDef *husart)
@@ -1404,7 +1402,7 @@
/**
* @brief Return the USART error code
- * @param husart : pointer to a USART_HandleTypeDef structure that contains
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART.
* @retval USART Error Code
*/
@@ -1422,7 +1420,7 @@
* @brief Simplex Send an amount of data in non-blocking mode.
* @note Function called under interruption only, once
* interruptions have been enabled by HAL_USART_Transmit_IT().
- * @param husart: USART handle
+ * @param husart USART handle
* @retval HAL status
* @note The USART errors are not managed to avoid the overrun error.
*/
@@ -1469,7 +1467,7 @@
/**
* @brief Wraps up transmission in non-blocking mode.
- * @param husart: pointer to a USART_HandleTypeDef structure that contains
+ * @param husart pointer to a USART_HandleTypeDef structure that contains
* the configuration information for the specified USART module.
* @retval HAL status
*/
@@ -1492,7 +1490,7 @@
* @brief Simplex Receive an amount of data in non-blocking mode.
* Function called under interruption only, once
* interruptions have been enabled by HAL_USART_Receive_IT()
- * @param husart: USART handle
+ * @param husart USART handle
* @retval HAL status
*/
static HAL_StatusTypeDef USART_Receive_IT(USART_HandleTypeDef *husart)
@@ -1545,7 +1543,7 @@
* @brief Full-Duplex Send receive an amount of data in full-duplex mode (non-blocking).
* Function called under interruption only, once
* interruptions have been enabled by HAL_USART_TransmitReceive_IT()
- * @param husart: USART handle
+ * @param husart USART handle
* @retval HAL status
*/
static HAL_StatusTypeDef USART_TransmitReceive_IT(USART_HandleTypeDef *husart)
@@ -1669,7 +1667,7 @@
/**
* @brief DMA USART transmit process complete callback
- * @param hdma: DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void USART_DMATransmitCplt(DMA_HandleTypeDef *hdma)
@@ -1704,7 +1702,7 @@
/**
* @brief DMA USART transmit process half complete callback
- * @param hdma : DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void USART_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
@@ -1716,7 +1714,7 @@
/**
* @brief DMA USART receive process complete callback
- * @param hdma: DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void USART_DMAReceiveCplt(DMA_HandleTypeDef *hdma)
@@ -1767,7 +1765,7 @@
/**
* @brief DMA USART receive process half complete callback
- * @param hdma : DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void USART_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
@@ -1779,7 +1777,7 @@
/**
* @brief DMA USART communication error callback
- * @param hdma: DMA handle
+ * @param hdma DMA handle
* @retval None
*/
static void USART_DMAError(DMA_HandleTypeDef *hdma)
@@ -1812,7 +1810,7 @@
/**
* @brief DMA USART communication abort callback
* (To be called at end of DMA Abort procedure).
- * @param hdma: DMA handle.
+ * @param hdma DMA handle.
* @retval None
*/
static void USART_DMAAbortOnError(DMA_HandleTypeDef *hdma)
@@ -1826,7 +1824,7 @@
/**
* @brief End ongoing Tx transfer on USART peripheral (following error detection or Transmit completion).
- * @param husart: USART handle.
+ * @param husart USART handle.
* @retval None
*/
static void USART_EndTxTransfer(USART_HandleTypeDef *husart)
@@ -1840,7 +1838,7 @@
/**
* @brief End ongoing Rx transfer on USART peripheral (following error detection or Reception completion).
- * @param husart: USART handle.
+ * @param husart USART handle.
* @retval None
*/
static void USART_EndRxTransfer(USART_HandleTypeDef *husart)
@@ -1855,7 +1853,7 @@
/**
* @brief Configure the USART peripheral
- * @param husart: USART handle
+ * @param husart USART handle
* @retval None
*/
static HAL_StatusTypeDef USART_SetConfig(USART_HandleTypeDef *husart)
@@ -1937,7 +1935,7 @@
/**
* @brief Check the USART Idle State
- * @param husart: USART handle
+ * @param husart USART handle
* @retval HAL status
*/
static HAL_StatusTypeDef USART_CheckIdleState(USART_HandleTypeDef *husart)
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_usart.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_usart.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_hal_usart.h
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief Header file of USART HAL module.
******************************************************************************
* @attention
@@ -340,14 +338,14 @@
*/
/** @brief Reset USART handle state
- * @param __HANDLE__: USART handle.
+ * @param __HANDLE__ USART handle.
* @retval None
*/
#define __HAL_USART_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_USART_STATE_RESET)
/** @brief Checks whether the specified USART flag is set or not.
- * @param __HANDLE__: specifies the USART Handle
- * @param __FLAG__: specifies the flag to check.
+ * @param __HANDLE__ specifies the USART Handle
+ * @param __FLAG__ specifies the flag to check.
* This parameter can be one of the following values:
* @arg USART_FLAG_REACK: Receive enable acknowledge flag
* @arg USART_FLAG_TEACK: Transmit enable acknowledge flag
@@ -367,8 +365,8 @@
/** @brief Enables the specified USART interrupt.
- * @param __HANDLE__: specifies the USART Handle
- * @param __INTERRUPT__: specifies the USART interrupt source to enable.
+ * @param __HANDLE__ specifies the USART Handle
+ * @param __INTERRUPT__ specifies the USART interrupt source to enable.
* This parameter can be one of the following values:
* @arg USART_IT_TXE: Transmit Data Register empty interrupt
* @arg USART_IT_TC: Transmission complete interrupt
@@ -383,8 +381,8 @@
((__HANDLE__)->Instance->CR3 |= (1U << ((__INTERRUPT__) & USART_IT_MASK))))
/** @brief Disables the specified USART interrupt.
- * @param __HANDLE__: specifies the USART Handle.
- * @param __INTERRUPT__: specifies the USART interrupt source to disable.
+ * @param __HANDLE__ specifies the USART Handle.
+ * @param __INTERRUPT__ specifies the USART interrupt source to disable.
* This parameter can be one of the following values:
* @arg USART_IT_TXE: Transmit Data Register empty interrupt
* @arg USART_IT_TC: Transmission complete interrupt
@@ -400,8 +398,8 @@
/** @brief Checks whether the specified USART interrupt has occurred or not.
- * @param __HANDLE__: specifies the USART Handle
- * @param __IT__: specifies the USART interrupt source to check.
+ * @param __HANDLE__ specifies the USART Handle
+ * @param __IT__ specifies the USART interrupt source to check.
* This parameter can be one of the following values:
* @arg USART_IT_TXE: Transmit Data Register empty interrupt
* @arg USART_IT_TC: Transmission complete interrupt
@@ -416,8 +414,8 @@
#define __HAL_USART_GET_IT(__HANDLE__, __IT__) ((__HANDLE__)->Instance->ISR & ((uint32_t)1 << ((__IT__)>> 0x08)))
/** @brief Checks whether the specified USART interrupt source is enabled.
- * @param __HANDLE__: specifies the USART Handle.
- * @param __IT__: specifies the USART interrupt source to check.
+ * @param __HANDLE__ specifies the USART Handle.
+ * @param __IT__ specifies the USART interrupt source to check.
* This parameter can be one of the following values:
* @arg USART_IT_TXE: Transmit Data Register empty interrupt
* @arg USART_IT_TC: Transmission complete interrupt
@@ -435,8 +433,8 @@
/** @brief Clears the specified USART ISR flag, in setting the proper ICR register flag.
- * @param __HANDLE__: specifies the USART Handle.
- * @param __IT_CLEAR__: specifies the interrupt clear register flag that needs to be set
+ * @param __HANDLE__ specifies the USART Handle.
+ * @param __IT_CLEAR__ specifies the interrupt clear register flag that needs to be set
* to clear the corresponding interrupt
* This parameter can be one of the following values:
* @arg USART_CLEAR_PEF: Parity Error Clear Flag
@@ -451,8 +449,8 @@
#define __HAL_USART_CLEAR_IT(__HANDLE__, __IT_CLEAR__) ((__HANDLE__)->Instance->ICR = (uint32_t)(__IT_CLEAR__))
/** @brief Set a specific USART request flag.
- * @param __HANDLE__: specifies the USART Handle.
- * @param __REQ__: specifies the request flag to set
+ * @param __HANDLE__ specifies the USART Handle.
+ * @param __REQ__ specifies the request flag to set
* This parameter can be one of the following values:
* @arg USART_RXDATA_FLUSH_REQUEST: Receive Data flush Request
* @arg USART_TXDATA_FLUSH_REQUEST: Transmit data flush Request
@@ -462,13 +460,13 @@
#define __HAL_USART_SEND_REQ(__HANDLE__, __REQ__) ((__HANDLE__)->Instance->RQR |= (uint16_t)(__REQ__))
/** @brief Enable USART
- * @param __HANDLE__: specifies the USART Handle.
+ * @param __HANDLE__ specifies the USART Handle.
* @retval None
*/
#define __HAL_USART_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= USART_CR1_UE)
/** @brief Disable USART
- * @param __HANDLE__: specifies the USART Handle.
+ * @param __HANDLE__ specifies the USART Handle.
* @retval None
*/
#define __HAL_USART_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= ~USART_CR1_UE)
@@ -558,8 +556,8 @@
* @{
*/
/** @brief Reports the USART clock source.
- * @param __HANDLE__: specifies the USART Handle
- * @param __CLOCKSOURCE__ : output variable
+ * @param __HANDLE__ specifies the USART Handle
+ * @param __CLOCKSOURCE__ output variable
* @retval the USART clocking source, written in __CLOCKSOURCE__.
*/
#define USART_GETCLOCKSOURCE(__HANDLE__, __CLOCKSOURCE__)\
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_usart_ex.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_usart_ex.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_usart_ex.h * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief Header file of USART HAL Extension module. ****************************************************************************** * @attention @@ -87,7 +85,7 @@ * by the reception API(). * This masking operation is not carried out in the case of * DMA transfers. - * @param __HANDLE__: specifies the USART Handle + * @param __HANDLE__ specifies the USART Handle * @retval none */ #define __HAL_USART_MASK_COMPUTATION(__HANDLE__) \
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_wwdg.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_wwdg.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_wwdg.c * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief WWDG HAL module driver. * This file provides firmware functions to manage the following * functionalities of the Window Watchdog (WWDG) peripheral:
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_wwdg.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_hal_wwdg.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_hal_wwdg.h * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief Header file of WWDG HAL module. ****************************************************************************** * @attention @@ -176,7 +174,7 @@ /** * @brief Enable the WWDG early wakeup interrupt. - * @param __HANDLE__: WWDG handle + * @param __HANDLE__ WWDG handle * @param __INTERRUPT__ specifies the interrupt to enable. * This parameter can be one of the following values: * @arg WWDG_IT_EWI: Early wakeup interrupt
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_adc.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_adc.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_ll_adc.c * @author MCD Application Team - * @version V1.2.0 - * @date 30-December-2016 * @brief ADC LL module driver ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_adc.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_adc.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_ll_adc.h * @author MCD Application Team - * @version V1.2.0 - * @date 30-December-2016 * @brief Header file of ADC LL module. ****************************************************************************** * @attention @@ -328,7 +326,7 @@ * a register from a register basis from which an offset * is applied. * @param __REG__ Register basis from which the offset is applied. - * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers). + * @param __REG_OFFFSET__ Offset to be applied (unit number of registers). * @retval Pointer to register address */ #define __ADC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ @@ -1177,7 +1175,7 @@ * @note Example: * __LL_ADC_DECIMAL_NB_TO_CHANNEL(4) * will return a data equivalent to "LL_ADC_CHANNEL_4". - * @param __DECIMAL_NB__: Value between Min_Data=0 and Max_Data=18 + * @param __DECIMAL_NB__ Value between Min_Data=0 and Max_Data=18 * @retval Returned value can be one of the following values: * @arg @ref LL_ADC_CHANNEL_0 * @arg @ref LL_ADC_CHANNEL_1 @@ -1647,7 +1645,7 @@ * @note Analog reference voltage (Vref+) must be either known from * user board environment or can be calculated using ADC measurement * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). - * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) + * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit mV) * @param __ADC_DATA__ ADC conversion data (resolution 12 bits) * (unit: digital value). * @param __ADC_RESOLUTION__ This parameter can be one of the following values: @@ -1680,7 +1678,7 @@ * internal voltage reference VrefInt. * Otherwise, this macro performs the processing to scale * ADC conversion data to 12 bits. - * @param __VREFINT_ADC_DATA__: ADC conversion data (resolution 12 bits) + * @param __VREFINT_ADC_DATA__ ADC conversion data (resolution 12 bits) * of internal voltage reference VrefInt (unit: digital value). * @param __ADC_RESOLUTION__ This parameter can be one of the following values: * @arg @ref LL_ADC_RESOLUTION_12B @@ -1730,7 +1728,7 @@ * temperature sensor. * Otherwise, this macro performs the processing to scale * ADC conversion data to 12 bits. - * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) + * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit mV) * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal * temperature sensor (unit: digital value). * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature @@ -1785,13 +1783,13 @@ * @note ADC measurement data must correspond to a resolution of 12bits * (full scale digital value 4095). If not the case, the data must be * preliminarily rescaled to an equivalent resolution of 12 bits. - * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data: Temperature sensor slope typical value (unit: uV/DegCelsius). + * @param __TEMPSENSOR_TYP_AVGSLOPE__ Device datasheet data Temperature sensor slope typical value (unit uV/DegCelsius). * On STM32F7, refer to device datasheet parameter "Avg_Slope". - * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data: Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit: mV). + * @param __TEMPSENSOR_TYP_CALX_V__ Device datasheet data Temperature sensor voltage typical value (at temperature and Vref+ defined in parameters below) (unit mV). * On STM32F4, refer to device datasheet parameter "V25". - * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data: Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit: mV) - * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit: mV) - * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit: digital value). + * @param __TEMPSENSOR_CALX_TEMP__ Device datasheet data Temperature at which temperature sensor voltage (see parameter above) is corresponding (unit mV) + * @param __VREFANALOG_VOLTAGE__ Analog voltage reference (Vref+) voltage (unit mV) + * @param __TEMPSENSOR_ADC_DATA__ ADC conversion data of internal temperature sensor (unit digital value). * @param __ADC_RESOLUTION__ ADC resolution at which internal temperature sensor voltage has been measured. * This parameter can be one of the following values: * @arg @ref LL_ADC_RESOLUTION_12B @@ -3577,7 +3575,7 @@ * @param AWDThresholdsHighLow This parameter can be one of the following values: * @arg @ref LL_ADC_AWD_THRESHOLD_HIGH * @arg @ref LL_ADC_AWD_THRESHOLD_LOW - * @param AWDThresholdValue: Value between Min_Data=0x000 and Max_Data=0xFFF + * @param AWDThresholdValue Value between Min_Data=0x000 and Max_Data=0xFFF * @retval None */ __STATIC_INLINE void LL_ADC_SetAnalogWDThresholds(ADC_TypeDef *ADCx, uint32_t AWDThresholdsHighLow, uint32_t AWDThresholdValue)
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_bus.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_bus.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_ll_bus.h * @author MCD Application Team - * @version V1.2.0 - * @date 30-December-2016 * @brief Header file of BUS LL module. @verbatim
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_cortex.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_cortex.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_ll_cortex.h * @author MCD Application Team - * @version V1.2.0 - * @date 30-December-2016 * @brief Header file of CORTEX LL module. @verbatim ==============================================================================
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_crc.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_crc.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_ll_crc.c * @author MCD Application Team - * @version V1.2.0 - * @date 30-December-2016 * @brief CRC LL module driver. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_crc.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_crc.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_ll_crc.h * @author MCD Application Team - * @version V1.2.0 - * @date 30-December-2016 * @brief Header file of CRC LL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_dac.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_dac.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_ll_dac.c * @author MCD Application Team - * @version V1.2.0 - * @date 30-December-2016 * @brief DAC LL module driver ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_dac.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_dac.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_ll_dac.h * @author MCD Application Team - * @version V1.2.0 - * @date 30-December-2016 * @brief Header file of DAC LL module. ****************************************************************************** * @attention @@ -127,7 +125,7 @@ * a register from a register basis from which an offset * is applied. * @param __REG__ Register basis from which the offset is applied. - * @param __REG_OFFFSET__ Offset to be applied (unit: number of registers). + * @param __REG_OFFFSET__ Offset to be applied (unit number of registers). * @retval Pointer to register address */ #define __DAC_PTR_REG_OFFSET(__REG__, __REG_OFFFSET__) \ @@ -456,7 +454,7 @@ * @note Analog reference voltage (Vref+) must be either known from * user board environment or can be calculated using ADC measurement * and ADC helper macro @ref __LL_ADC_CALC_VREFANALOG_VOLTAGE(). - * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit: mV) + * @param __VREFANALOG_VOLTAGE__ Analog reference voltage (unit mV) * @param __DAC_VOLTAGE__ Voltage to be generated by DAC channel * (unit: mVolt). * @param __DAC_RESOLUTION__ This parameter can be one of the following values:
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_dma.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_dma.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_ll_dma.c * @author MCD Application Team - * @version V1.2.0 - * @date 30-December-2016 * @brief DMA LL module driver. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_dma.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_dma.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_ll_dma.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 30-December-2016
* @brief Header file of DMA LL module.
******************************************************************************
* @attention
@@ -2130,7 +2128,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->LIFCR , DMA_LIFCR_CHTIF0);
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF0);
}
/**
@@ -2141,7 +2139,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->LIFCR , DMA_LIFCR_CHTIF1);
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF1);
}
/**
@@ -2152,7 +2150,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->LIFCR , DMA_LIFCR_CHTIF2);
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF2);
}
/**
@@ -2163,7 +2161,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->LIFCR , DMA_LIFCR_CHTIF3);
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CHTIF3);
}
/**
@@ -2174,7 +2172,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->HIFCR , DMA_HIFCR_CHTIF4);
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF4);
}
/**
@@ -2185,7 +2183,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->HIFCR , DMA_HIFCR_CHTIF5);
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF5);
}
/**
@@ -2196,7 +2194,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->HIFCR , DMA_HIFCR_CHTIF6);
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF6);
}
/**
@@ -2207,7 +2205,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->HIFCR , DMA_HIFCR_CHTIF7);
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CHTIF7);
}
/**
@@ -2218,7 +2216,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTCIF0);
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF0);
}
/**
@@ -2229,7 +2227,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTCIF1);
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF1);
}
/**
@@ -2240,7 +2238,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTCIF2);
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF2);
}
/**
@@ -2251,7 +2249,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTCIF3);
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTCIF3);
}
/**
@@ -2262,7 +2260,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTCIF4);
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF4);
}
/**
@@ -2273,7 +2271,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTCIF5);
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF5);
}
/**
@@ -2284,7 +2282,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTCIF6);
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF6);
}
/**
@@ -2295,7 +2293,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTCIF7);
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTCIF7);
}
/**
@@ -2306,7 +2304,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTEIF0);
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF0);
}
/**
@@ -2317,7 +2315,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTEIF1);
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF1);
}
/**
@@ -2328,7 +2326,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTEIF2);
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF2);
}
/**
@@ -2339,7 +2337,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTEIF3);
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CTEIF3);
}
/**
@@ -2350,7 +2348,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTEIF4);
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF4);
}
/**
@@ -2361,7 +2359,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTEIF5);
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF5);
}
/**
@@ -2372,7 +2370,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTEIF6);
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF6);
}
/**
@@ -2383,7 +2381,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTEIF7);
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CTEIF7);
}
/**
@@ -2394,7 +2392,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->LIFCR , DMA_LIFCR_CDMEIF0);
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF0);
}
/**
@@ -2405,7 +2403,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->LIFCR , DMA_LIFCR_CDMEIF1);
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF1);
}
/**
@@ -2416,7 +2414,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->LIFCR , DMA_LIFCR_CDMEIF2);
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF2);
}
/**
@@ -2427,7 +2425,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->LIFCR , DMA_LIFCR_CDMEIF3);
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CDMEIF3);
}
/**
@@ -2438,7 +2436,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->HIFCR , DMA_HIFCR_CDMEIF4);
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF4);
}
/**
@@ -2449,7 +2447,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->HIFCR , DMA_HIFCR_CDMEIF5);
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF5);
}
/**
@@ -2460,7 +2458,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->HIFCR , DMA_HIFCR_CDMEIF6);
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF6);
}
/**
@@ -2471,7 +2469,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->HIFCR , DMA_HIFCR_CDMEIF7);
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CDMEIF7);
}
/**
@@ -2482,7 +2480,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->LIFCR , DMA_LIFCR_CFEIF0);
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF0);
}
/**
@@ -2493,7 +2491,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->LIFCR , DMA_LIFCR_CFEIF1);
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF1);
}
/**
@@ -2504,7 +2502,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->LIFCR , DMA_LIFCR_CFEIF2);
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF2);
}
/**
@@ -2515,7 +2513,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->LIFCR , DMA_LIFCR_CFEIF3);
+ WRITE_REG(DMAx->LIFCR , DMA_LIFCR_CFEIF3);
}
/**
@@ -2526,7 +2524,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->HIFCR , DMA_HIFCR_CFEIF4);
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF4);
}
/**
@@ -2537,7 +2535,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->HIFCR , DMA_HIFCR_CFEIF5);
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF5);
}
/**
@@ -2548,7 +2546,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->HIFCR , DMA_HIFCR_CFEIF6);
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF6);
}
/**
@@ -2559,7 +2557,7 @@
*/
__STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx)
{
- SET_BIT(DMAx->HIFCR , DMA_HIFCR_CFEIF7);
+ WRITE_REG(DMAx->HIFCR , DMA_HIFCR_CFEIF7);
}
/**
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_dma2d.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_dma2d.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_ll_dma2d.c * @author MCD Application Team - * @version V1.2.0 - * @date 30-December-2016 * @brief DMA2D LL module driver. ****************************************************************************** * @attention @@ -172,7 +170,7 @@ * @note DMA2D transfers must be disabled to set initialization bits in configuration registers, * otherwise ERROR result is returned. * @param DMA2Dx DMA2D Instance - * @param DMA2D_InitStruct: pointer to a LL_DMA2D_InitTypeDef structure + * @param DMA2D_InitStruct pointer to a LL_DMA2D_InitTypeDef structure * that contains the configuration information for the specified DMA2D peripheral. * @retval An ErrorStatus enumeration value: * - SUCCESS: DMA2D registers are initialized according to DMA2D_InitStruct content @@ -243,7 +241,7 @@ /** * @brief Set each @ref LL_DMA2D_InitTypeDef field to default value. - * @param DMA2D_InitStruct: pointer to a @ref LL_DMA2D_InitTypeDef structure + * @param DMA2D_InitStruct pointer to a @ref LL_DMA2D_InitTypeDef structure * whose fields will be set to default values. * @retval None */ @@ -270,9 +268,9 @@ * @brief Configure the foreground or background according to the specified parameters * in the LL_DMA2D_LayerCfgTypeDef structure. * @param DMA2Dx DMA2D Instance - * @param DMA2D_LayerCfg: pointer to a LL_DMA2D_LayerCfgTypeDef structure that contains + * @param DMA2D_LayerCfg pointer to a LL_DMA2D_LayerCfgTypeDef structure that contains * the configuration information for the specified layer. - * @param LayerIdx: DMA2D Layer index. + * @param LayerIdx DMA2D Layer index. * This parameter can be one of the following values: * 0(background) / 1(foreground) * @retval None @@ -364,7 +362,7 @@ /** * @brief Set each @ref LL_DMA2D_LayerCfgTypeDef field to default value. - * @param DMA2D_LayerCfg: pointer to a @ref LL_DMA2D_LayerCfgTypeDef structure + * @param DMA2D_LayerCfg pointer to a @ref LL_DMA2D_LayerCfgTypeDef structure * whose fields will be set to default values. * @retval None */ @@ -392,7 +390,7 @@ * @brief Initialize DMA2D output color register according to the specified parameters * in DMA2D_ColorStruct. * @param DMA2Dx DMA2D Instance - * @param DMA2D_ColorStruct: pointer to a LL_DMA2D_ColorTypeDef structure that contains + * @param DMA2D_ColorStruct pointer to a LL_DMA2D_ColorTypeDef structure that contains * the color configuration information for the specified DMA2D peripheral. * @retval None */
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_dma2d.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_dma2d.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_ll_dma2d.h * @author MCD Application Team - * @version V1.2.0 - * @date 30-December-2016 * @brief Header file of DMA2D LL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_exti.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_exti.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_ll_exti.c * @author MCD Application Team - * @version V1.2.0 - * @date 30-December-2016 * @brief EXTI LL module driver. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_exti.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_exti.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_ll_exti.h * @author MCD Application Team - * @version V1.2.0 - * @date 30-December-2016 * @brief Header file of EXTI LL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_fmc.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_fmc.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_ll_fmc.c
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief FMC Low Layer HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -143,8 +141,8 @@
/**
* @brief Initialize the FMC_NORSRAM device according to the specified
* control parameters in the FMC_NORSRAM_InitTypeDef
- * @param Device: Pointer to NORSRAM device instance
- * @param Init: Pointer to NORSRAM Initialization structure
+ * @param Device Pointer to NORSRAM device instance
+ * @param Init Pointer to NORSRAM Initialization structure
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef* Init)
@@ -219,9 +217,9 @@
/**
* @brief DeInitialize the FMC_NORSRAM peripheral
- * @param Device: Pointer to NORSRAM device instance
- * @param ExDevice: Pointer to NORSRAM extended mode device instance
- * @param Bank: NORSRAM bank number
+ * @param Device Pointer to NORSRAM device instance
+ * @param ExDevice Pointer to NORSRAM extended mode device instance
+ * @param Bank NORSRAM bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank)
@@ -256,9 +254,9 @@
/**
* @brief Initialize the FMC_NORSRAM Timing according to the specified
* parameters in the FMC_NORSRAM_TimingTypeDef
- * @param Device: Pointer to NORSRAM device instance
- * @param Timing: Pointer to NORSRAM Timing structure
- * @param Bank: NORSRAM bank number
+ * @param Device Pointer to NORSRAM device instance
+ * @param Timing Pointer to NORSRAM Timing structure
+ * @param Bank NORSRAM bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank)
@@ -310,9 +308,9 @@
/**
* @brief Initialize the FMC_NORSRAM Extended mode Timing according to the specified
* parameters in the FMC_NORSRAM_TimingTypeDef
- * @param Device: Pointer to NORSRAM device instance
- * @param Timing: Pointer to NORSRAM Timing structure
- * @param Bank: NORSRAM bank number
+ * @param Device Pointer to NORSRAM device instance
+ * @param Timing Pointer to NORSRAM Timing structure
+ * @param Bank NORSRAM bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode)
@@ -379,8 +377,8 @@
/**
* @brief Enables dynamically FMC_NORSRAM write operation.
- * @param Device: Pointer to NORSRAM device instance
- * @param Bank: NORSRAM bank number
+ * @param Device Pointer to NORSRAM device instance
+ * @param Bank NORSRAM bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
@@ -397,8 +395,8 @@
/**
* @brief Disables dynamically FMC_NORSRAM write operation.
- * @param Device: Pointer to NORSRAM device instance
- * @param Bank: NORSRAM bank number
+ * @param Device Pointer to NORSRAM device instance
+ * @param Bank NORSRAM bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank)
@@ -466,8 +464,8 @@
/**
* @brief Initializes the FMC_NAND device according to the specified
* control parameters in the FMC_NAND_HandleTypeDef
- * @param Device: Pointer to NAND device instance
- * @param Init: Pointer to NAND Initialization structure
+ * @param Device Pointer to NAND device instance
+ * @param Init Pointer to NAND Initialization structure
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init)
@@ -510,9 +508,9 @@
/**
* @brief Initializes the FMC_NAND Common space Timing according to the specified
* parameters in the FMC_NAND_PCC_TimingTypeDef
- * @param Device: Pointer to NAND device instance
- * @param Timing: Pointer to NAND timing structure
- * @param Bank: NAND bank number
+ * @param Device Pointer to NAND device instance
+ * @param Timing Pointer to NAND timing structure
+ * @param Bank NAND bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
@@ -549,9 +547,9 @@
/**
* @brief Initializes the FMC_NAND Attribute space Timing according to the specified
* parameters in the FMC_NAND_PCC_TimingTypeDef
- * @param Device: Pointer to NAND device instance
- * @param Timing: Pointer to NAND timing structure
- * @param Bank: NAND bank number
+ * @param Device Pointer to NAND device instance
+ * @param Timing Pointer to NAND timing structure
+ * @param Bank NAND bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank)
@@ -586,8 +584,8 @@
/**
* @brief DeInitializes the FMC_NAND device
- * @param Device: Pointer to NAND device instance
- * @param Bank: NAND bank number
+ * @param Device Pointer to NAND device instance
+ * @param Bank NAND bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank)
@@ -630,8 +628,8 @@
/**
* @brief Enables dynamically FMC_NAND ECC feature.
- * @param Device: Pointer to NAND device instance
- * @param Bank: NAND bank number
+ * @param Device Pointer to NAND device instance
+ * @param Bank NAND bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank)
@@ -649,8 +647,8 @@
/**
* @brief Disables dynamically FMC_NAND ECC feature.
- * @param Device: Pointer to NAND device instance
- * @param Bank: NAND bank number
+ * @param Device Pointer to NAND device instance
+ * @param Bank NAND bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank)
@@ -667,10 +665,10 @@
/**
* @brief Disables dynamically FMC_NAND ECC feature.
- * @param Device: Pointer to NAND device instance
- * @param ECCval: Pointer to ECC value
- * @param Bank: NAND bank number
- * @param Timeout: Timeout wait value
+ * @param Device Pointer to NAND device instance
+ * @param ECCval Pointer to ECC value
+ * @param Bank NAND bank number
+ * @param Timeout Timeout wait value
* @retval HAL status
*/
HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout)
@@ -753,8 +751,8 @@
/**
* @brief Initializes the FMC_SDRAM device according to the specified
* control parameters in the FMC_SDRAM_InitTypeDef
- * @param Device: Pointer to SDRAM device instance
- * @param Init: Pointer to SDRAM Initialization structure
+ * @param Device Pointer to SDRAM device instance
+ * @param Init Pointer to SDRAM Initialization structure
* @retval HAL status
*/
HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init)
@@ -833,9 +831,9 @@
/**
* @brief Initializes the FMC_SDRAM device timing according to the specified
* parameters in the FMC_SDRAM_TimingTypeDef
- * @param Device: Pointer to SDRAM device instance
- * @param Timing: Pointer to SDRAM Timing structure
- * @param Bank: SDRAM bank number
+ * @param Device Pointer to SDRAM device instance
+ * @param Timing Pointer to SDRAM Timing structure
+ * @param Bank SDRAM bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank)
@@ -905,7 +903,7 @@
/**
* @brief DeInitializes the FMC_SDRAM peripheral
- * @param Device: Pointer to SDRAM device instance
+ * @param Device Pointer to SDRAM device instance
* @retval HAL status
*/
HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
@@ -945,8 +943,8 @@
/**
* @brief Enables dynamically FMC_SDRAM write protection.
- * @param Device: Pointer to SDRAM device instance
- * @param Bank: SDRAM bank number
+ * @param Device Pointer to SDRAM device instance
+ * @param Bank SDRAM bank number
* @retval HAL status
*/
HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
@@ -963,7 +961,7 @@
/**
* @brief Disables dynamically FMC_SDRAM write protection.
- * @param hsdram: FMC_SDRAM handle
+ * @param hsdram FMC_SDRAM handle
* @retval HAL status
*/
HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank)
@@ -980,16 +978,15 @@
/**
* @brief Send Command to the FMC SDRAM bank
- * @param Device: Pointer to SDRAM device instance
- * @param Command: Pointer to SDRAM command structure
- * @param Timing: Pointer to SDRAM Timing structure
- * @param Timeout: Timeout wait value
+ * @param Device Pointer to SDRAM device instance
+ * @param Command Pointer to SDRAM command structure
+ * @param Timing Pointer to SDRAM Timing structure
+ * @param Timeout Timeout wait value
* @retval HAL state
*/
HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout)
{
__IO uint32_t tmpr = 0;
- uint32_t tickstart = 0;
/* Check the parameters */
assert_param(IS_FMC_SDRAM_DEVICE(Device));
@@ -1006,30 +1003,14 @@
);
Device->SDCMR = tmpr;
-
- /* Get tick */
- tickstart = HAL_GetTick();
-
- /* wait until command is send */
- while(HAL_IS_BIT_SET(Device->SDSR, FMC_SDSR_BUSY))
- {
- /* Check for the Timeout */
- if(Timeout != HAL_MAX_DELAY)
- {
- if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
- {
- return HAL_TIMEOUT;
- }
- }
- }
return HAL_OK;
}
/**
* @brief Program the SDRAM Memory Refresh rate.
- * @param Device: Pointer to SDRAM device instance
- * @param RefreshRate: The SDRAM refresh rate value.
+ * @param Device Pointer to SDRAM device instance
+ * @param RefreshRate The SDRAM refresh rate value.
* @retval HAL state
*/
HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate)
@@ -1046,8 +1027,8 @@
/**
* @brief Set the Number of consecutive SDRAM Memory auto Refresh commands.
- * @param Device: Pointer to SDRAM device instance
- * @param AutoRefreshNumber: Specifies the auto Refresh number.
+ * @param Device Pointer to SDRAM device instance
+ * @param AutoRefreshNumber Specifies the auto Refresh number.
* @retval None
*/
HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber)
@@ -1064,8 +1045,8 @@
/**
* @brief Returns the indicated FMC SDRAM bank mode status.
- * @param Device: Pointer to SDRAM device instance
- * @param Bank: Defines the FMC SDRAM bank. This parameter can be
+ * @param Device Pointer to SDRAM device instance
+ * @param Bank Defines the FMC SDRAM bank. This parameter can be
* FMC_Bank1_SDRAM or FMC_Bank2_SDRAM.
* @retval The FMC SDRAM bank mode status, could be on of the following values:
* FMC_SDRAM_NORMAL_MODE, FMC_SDRAM_SELF_REFRESH_MODE or
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_fmc.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_fmc.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_ll_fmc.h
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief Header file of FMC HAL module.
******************************************************************************
* @attention
@@ -1087,16 +1085,16 @@
/**
* @brief Enable the NORSRAM device access.
- * @param __INSTANCE__: FMC_NORSRAM Instance
- * @param __BANK__: FMC_NORSRAM Bank
+ * @param __INSTANCE__ FMC_NORSRAM Instance
+ * @param __BANK__ FMC_NORSRAM Bank
* @retval None
*/
#define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCR1_MBKEN)
/**
* @brief Disable the NORSRAM device access.
- * @param __INSTANCE__: FMC_NORSRAM Instance
- * @param __BANK__: FMC_NORSRAM Bank
+ * @param __INSTANCE__ FMC_NORSRAM Instance
+ * @param __BANK__ FMC_NORSRAM Bank
* @retval None
*/
#define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
@@ -1112,14 +1110,14 @@
/**
* @brief Enable the NAND device access.
- * @param __INSTANCE__: FMC_NAND Instance
+ * @param __INSTANCE__ FMC_NAND Instance
* @retval None
*/
#define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN)
/**
* @brief Disable the NAND device access.
- * @param __INSTANCE__: FMC_NAND Instance
+ * @param __INSTANCE__ FMC_NAND Instance
* @retval None
*/
#define __FMC_NAND_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN)
@@ -1135,8 +1133,8 @@
/**
* @brief Enable the NAND device interrupt.
- * @param __INSTANCE__: FMC_NAND instance
- * @param __INTERRUPT__: FMC_NAND interrupt
+ * @param __INSTANCE__ FMC_NAND instance
+ * @param __INTERRUPT__ FMC_NAND interrupt
* This parameter can be any combination of the following values:
* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
* @arg FMC_IT_LEVEL: Interrupt level.
@@ -1147,8 +1145,8 @@
/**
* @brief Disable the NAND device interrupt.
- * @param __INSTANCE__: FMC_NAND Instance
- * @param __INTERRUPT__: FMC_NAND interrupt
+ * @param __INSTANCE__ FMC_NAND Instance
+ * @param __INTERRUPT__ FMC_NAND interrupt
* This parameter can be any combination of the following values:
* @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
* @arg FMC_IT_LEVEL: Interrupt level.
@@ -1159,9 +1157,9 @@
/**
* @brief Get flag status of the NAND device.
- * @param __INSTANCE__: FMC_NAND Instance
- * @param __BANK__: FMC_NAND Bank
- * @param __FLAG__: FMC_NAND flag
+ * @param __INSTANCE__ FMC_NAND Instance
+ * @param __BANK__ FMC_NAND Bank
+ * @param __FLAG__ FMC_NAND flag
* This parameter can be any combination of the following values:
* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
@@ -1173,8 +1171,8 @@
/**
* @brief Clear flag status of the NAND device.
- * @param __INSTANCE__: FMC_NAND Instance
- * @param __FLAG__: FMC_NAND flag
+ * @param __INSTANCE__ FMC_NAND Instance
+ * @param __FLAG__ FMC_NAND flag
* This parameter can be any combination of the following values:
* @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
* @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
@@ -1186,8 +1184,8 @@
/**
* @brief Enable the SDRAM device interrupt.
- * @param __INSTANCE__: FMC_SDRAM instance
- * @param __INTERRUPT__: FMC_SDRAM interrupt
+ * @param __INSTANCE__ FMC_SDRAM instance
+ * @param __INTERRUPT__ FMC_SDRAM interrupt
* This parameter can be any combination of the following values:
* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
* @retval None
@@ -1196,8 +1194,8 @@
/**
* @brief Disable the SDRAM device interrupt.
- * @param __INSTANCE__: FMC_SDRAM instance
- * @param __INTERRUPT__: FMC_SDRAM interrupt
+ * @param __INSTANCE__ FMC_SDRAM instance
+ * @param __INTERRUPT__ FMC_SDRAM interrupt
* This parameter can be any combination of the following values:
* @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
* @retval None
@@ -1206,8 +1204,8 @@
/**
* @brief Get flag status of the SDRAM device.
- * @param __INSTANCE__: FMC_SDRAM instance
- * @param __FLAG__: FMC_SDRAM flag
+ * @param __INSTANCE__ FMC_SDRAM instance
+ * @param __FLAG__ FMC_SDRAM flag
* This parameter can be any combination of the following values:
* @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.
* @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.
@@ -1218,8 +1216,8 @@
/**
* @brief Clear flag status of the SDRAM device.
- * @param __INSTANCE__: FMC_SDRAM instance
- * @param __FLAG__: FMC_SDRAM flag
+ * @param __INSTANCE__ FMC_SDRAM instance
+ * @param __FLAG__ FMC_SDRAM flag
* This parameter can be any combination of the following values:
* @arg FMC_SDRAM_FLAG_REFRESH_ERROR
* @retval None
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_gpio.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_gpio.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_ll_gpio.c * @author MCD Application Team - * @version V1.2.0 - * @date 30-December-2016 * @brief GPIO LL module driver. ****************************************************************************** * @attention @@ -209,7 +207,7 @@ /** * @brief Initialize GPIO registers according to the specified parameters in GPIO_InitStruct. * @param GPIOx GPIO Port - * @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure + * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure * that contains the configuration information for the specified GPIO peripheral. * @retval An ErrorStatus enumeration value: * - SUCCESS: GPIO registers are initialized according to GPIO_InitStruct content @@ -286,7 +284,7 @@ /** * @brief Set each @ref LL_GPIO_InitTypeDef field to default value. - * @param GPIO_InitStruct: pointer to a @ref LL_GPIO_InitTypeDef structure + * @param GPIO_InitStruct pointer to a @ref LL_GPIO_InitTypeDef structure * whose fields will be set to default values. * @retval None */
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_gpio.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_gpio.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_ll_gpio.h * @author MCD Application Team - * @version V1.2.0 - * @date 30-December-2016 * @brief Header file of GPIO LL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_i2c.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_i2c.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_ll_i2c.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 30-December-2016
* @brief I2C LL module driver.
******************************************************************************
* @attention
@@ -200,7 +198,12 @@
*/
LL_I2C_DisableOwnAddress1(I2Cx);
LL_I2C_SetOwnAddress1(I2Cx, I2C_InitStruct->OwnAddress1, I2C_InitStruct->OwnAddrSize);
- LL_I2C_EnableOwnAddress1(I2Cx);
+
+ /* OwnAdress1 == 0 is reserved for General Call address */
+ if (I2C_InitStruct->OwnAddress1 != 0U)
+ {
+ LL_I2C_EnableOwnAddress1(I2Cx);
+ }
/*---------------------------- I2Cx MODE Configuration -----------------------
* Configure I2Cx peripheral mode with parameter :
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_i2c.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_i2c.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_ll_i2c.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 30-December-2016
* @brief Header file of I2C LL module.
******************************************************************************
* @attention
@@ -283,14 +281,14 @@
/** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
* @{
*/
-#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U /*!< Don't Generate Stop and Start condition. */
-#define LL_I2C_GENERATE_STOP I2C_CR2_STOP /*!< Generate Stop condition (Size should be set to 0). */
-#define LL_I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Start for read request. */
-#define LL_I2C_GENERATE_START_WRITE I2C_CR2_START /*!< Generate Start for write request. */
-#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Restart for read request, slave 7Bit address. */
-#define LL_I2C_GENERATE_RESTART_7BIT_WRITE I2C_CR2_START /*!< Generate Restart for write request, slave 7Bit address. */
-#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) /*!< Generate Restart for read request, slave 10Bit address. */
-#define LL_I2C_GENERATE_RESTART_10BIT_WRITE I2C_CR2_START /*!< Generate Restart for write request, slave 10Bit address.*/
+#define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U /*!< Don't Generate Stop and Start condition. */
+#define LL_I2C_GENERATE_STOP (uint32_t)(0x80000000U | I2C_CR2_STOP) /*!< Generate Stop condition (Size should be set to 0). */
+#define LL_I2C_GENERATE_START_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Start for read request. */
+#define LL_I2C_GENERATE_START_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Start for write request. */
+#define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Restart for read request, slave 7Bit address. */
+#define LL_I2C_GENERATE_RESTART_7BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Restart for write request, slave 7Bit address. */
+#define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(0x80000000U | I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) /*!< Generate Restart for read request, slave 10Bit address. */
+#define LL_I2C_GENERATE_RESTART_10BIT_WRITE (uint32_t)(0x80000000U | I2C_CR2_START) /*!< Generate Restart for write request, slave 10Bit address.*/
/**
* @}
*/
@@ -2069,7 +2067,7 @@
__STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
{
- MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
+ MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | (I2C_CR2_RD_WRN & (uint32_t)(Request >> (31U - I2C_CR2_RD_WRN_Pos))) | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
SlaveAddr | SlaveAddrSize | TransferSize << I2C_CR2_NBYTES_Pos | EndMode | Request);
}
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_iwdg.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_iwdg.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_ll_iwdg.h * @author MCD Application Team - * @version V1.2.0 - * @date 30-December-2016 * @brief Header file of IWDG LL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_lptim.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_lptim.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_ll_lptim.c * @author MCD Application Team - * @version V1.2.0 - * @date 30-December-2016 * @brief LPTIM LL module driver. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_lptim.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_lptim.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_ll_lptim.h * @author MCD Application Team - * @version V1.2.0 - * @date 30-December-2016 * @brief Header file of LPTIM LL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_pwr.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_pwr.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_ll_pwr.c * @author MCD Application Team - * @version V1.2.0 - * @date 30-December-2016 * @brief PWR LL module driver. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_pwr.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_pwr.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_ll_pwr.h * @author MCD Application Team - * @version V1.2.0 - * @date 30-December-2016 * @brief Header file of PWR LL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_rcc.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_rcc.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_ll_rcc.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 30-December-2016
* @brief RCC LL module driver.
******************************************************************************
* @attention
@@ -168,7 +166,7 @@
* @brief Reset the RCC clock configuration to the default reset state.
* @note The default reset state of the clock configuration is given below:
* - HSI ON and used as system clock source
- * - HSE and PLL OFF
+ * - HSE, PLL, PLLI2S, PLLSAI OFF
* - AHB, APB1 and APB2 prescaler set to 1.
* - CSS, MCO OFF
* - All interrupts disabled
@@ -181,24 +179,20 @@
*/
ErrorStatus LL_RCC_DeInit(void)
{
- uint32_t vl_mask = 0U;
+ uint32_t vl_mask = 0xFFFFFFFFU;
/* Set HSION bit */
LL_RCC_HSI_Enable();
+ /* Wait for HSI READY bit */
+ while(LL_RCC_HSI_IsReady() != 1U)
+ {}
+
/* Reset CFGR register */
LL_RCC_WriteReg(CFGR, 0x00000000U);
- vl_mask = 0xFFFFFFFFU;
-
- /* Reset HSEON, PLLSYSON bits */
- CLEAR_BIT(vl_mask, (RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_PLLON | RCC_CR_CSSON));
-
- /* Reset PLLSAION bit */
- CLEAR_BIT(vl_mask, RCC_CR_PLLSAION);
-
- /* Reset PLLI2SON bit */
- CLEAR_BIT(vl_mask, RCC_CR_PLLI2SON);
+ /* Reset HSEON, HSEBYP, PLLON, CSSON, PLLI2SON and PLLSAION bits */
+ CLEAR_BIT(vl_mask, (RCC_CR_HSEON | RCC_CR_HSEBYP | RCC_CR_PLLON | RCC_CR_CSSON | RCC_CR_PLLSAION | RCC_CR_PLLI2SON));
/* Write new mask in CR register */
LL_RCC_WriteReg(CR, vl_mask);
@@ -206,6 +200,18 @@
/* Set HSITRIM bits to the reset value*/
LL_RCC_HSI_SetCalibTrimming(0x10U);
+ /* Wait for PLL READY bit to be reset */
+ while(LL_RCC_PLL_IsReady() != 0U)
+ {}
+
+ /* Wait for PLLI2S READY bit to be reset */
+ while(LL_RCC_PLLI2S_IsReady() != 0U)
+ {}
+
+ /* Wait for PLLSAI READY bit to be reset */
+ while(LL_RCC_PLLSAI_IsReady() != 0U)
+ {}
+
/* Reset PLLCFGR register */
LL_RCC_WriteReg(PLLCFGR, 0x24003010U);
@@ -215,11 +221,17 @@
/* Reset PLLSAICFGR register */
LL_RCC_WriteReg(PLLSAICFGR, 0x24003000U);
- /* Reset HSEBYP bit */
- LL_RCC_HSE_DisableBypass();
+ /* Disable all interrupts */
+ CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE | RCC_CIR_LSERDYIE | RCC_CIR_HSIRDYIE | RCC_CIR_HSERDYIE | RCC_CIR_PLLRDYIE | RCC_CIR_PLLI2SRDYIE | RCC_CIR_PLLSAIRDYIE);
+
+ /* Clear all interrupt flags */
+ SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC | RCC_CIR_LSERDYC | RCC_CIR_HSIRDYC | RCC_CIR_HSERDYC | RCC_CIR_PLLRDYC | RCC_CIR_PLLI2SRDYC | RCC_CIR_PLLSAIRDYC | RCC_CIR_CSSC);
- /* Disable all interrupts */
- LL_RCC_WriteReg(CIR, 0x00000000U);
+ /* Clear LSION bit */
+ CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
+
+ /* Reset all CSR flags */
+ SET_BIT(RCC->CSR, RCC_CSR_RMVF);
return SUCCESS;
}
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_rcc.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_rcc.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_ll_rcc.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 30-December-2016
* @brief Header file of RCC LL module.
******************************************************************************
* @attention
@@ -3451,6 +3449,31 @@
#endif /* DSI */
/**
+ * @brief Configure PLL clock source
+ * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_SetMainSource
+ * @param PLLSource This parameter can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ * @retval None
+ */
+__STATIC_INLINE void LL_RCC_PLL_SetMainSource(uint32_t PLLSource)
+{
+ MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC, PLLSource);
+}
+
+/**
+ * @brief Get the oscillator used as PLL clock source.
+ * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
+ * @retval Returned value can be one of the following values:
+ * @arg @ref LL_RCC_PLLSOURCE_HSI
+ * @arg @ref LL_RCC_PLLSOURCE_HSE
+ */
+__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
+{
+ return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
+}
+
+/**
* @brief Get Main PLL multiplication factor for VCO
* @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN
* @retval Between 50 and 432
@@ -3519,18 +3542,6 @@
#endif /* RCC_PLLCFGR_PLLR */
/**
- * @brief Get the oscillator used as PLL clock source.
- * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
- * @retval Returned value can be one of the following values:
- * @arg @ref LL_RCC_PLLSOURCE_HSI
- * @arg @ref LL_RCC_PLLSOURCE_HSE
- */
-__STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
-{
- return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
-}
-
-/**
* @brief Get Division factor for the main PLL and other PLL
* @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider
* @retval Returned value can be one of the following values:
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_rng.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_rng.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_ll_rng.c * @author MCD Application Team - * @version V1.2.0 - * @date 30-December-2016 * @brief RNG LL module driver. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_rng.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_rng.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_ll_rng.h * @author MCD Application Team - * @version V1.2.0 - * @date 30-December-2016 * @brief Header file of RNG LL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_rtc.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_rtc.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_ll_rtc.c * @author MCD Application Team - * @version V1.2.0 - * @date 30-December-2016 * @brief RTC LL module driver. ****************************************************************************** * @attention @@ -384,7 +382,7 @@ * @param RTC_Format This parameter can be one of the following values: * @arg @ref LL_RTC_FORMAT_BIN * @arg @ref LL_RTC_FORMAT_BCD - * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains + * @param RTC_DateStruct pointer to a RTC_DateTypeDef structure that contains * the date configuration information for the RTC. * @retval An ErrorStatus enumeration value: * - SUCCESS: RTC Day register is configured
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_rtc.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_rtc.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_ll_rtc.h * @author MCD Application Team - * @version V1.2.0 - * @date 30-December-2016 * @brief Header file of RTC LL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_sdmmc.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_sdmmc.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_ll_sdmmc.c
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief SDMMC Low Layer HAL module driver.
*
* This file provides firmware functions to manage the following
@@ -222,8 +220,8 @@
/**
* @brief Initializes the SDMMC according to the specified
* parameters in the SDMMC_InitTypeDef and create the associated handle.
- * @param SDMMCx: Pointer to SDMMC register base
- * @param Init: SDMMC initialization structure
+ * @param SDMMCx Pointer to SDMMC register base
+ * @param Init SDMMC initialization structure
* @retval HAL status
*/
HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init)
@@ -276,7 +274,7 @@
/**
* @brief Read data (word) from Rx FIFO in blocking mode (polling)
- * @param SDMMCx: Pointer to SDMMC register base
+ * @param SDMMCx Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx)
@@ -287,8 +285,8 @@
/**
* @brief Write data (word) to Tx FIFO in blocking mode (polling)
- * @param SDMMCx: Pointer to SDMMC register base
- * @param pWriteData: pointer to data to write
+ * @param SDMMCx Pointer to SDMMC register base
+ * @param pWriteData pointer to data to write
* @retval HAL status
*/
HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData)
@@ -320,7 +318,7 @@
/**
* @brief Set SDMMC Power state to ON.
- * @param SDMMCx: Pointer to SDMMC register base
+ * @param SDMMCx Pointer to SDMMC register base
* @retval HAL status
*/
HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx)
@@ -333,7 +331,7 @@
/**
* @brief Set SDMMC Power state to OFF.
- * @param SDMMCx: Pointer to SDMMC register base
+ * @param SDMMCx Pointer to SDMMC register base
* @retval HAL status
*/
HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx)
@@ -346,7 +344,7 @@
/**
* @brief Get SDMMC Power state.
- * @param SDMMCx: Pointer to SDMMC register base
+ * @param SDMMCx Pointer to SDMMC register base
* @retval Power status of the controller. The returned value can be one of the
* following values:
* - 0x00: Power OFF
@@ -361,8 +359,8 @@
/**
* @brief Configure the SDMMC command path according to the specified parameters in
* SDMMC_CmdInitTypeDef structure and send the command
- * @param SDMMCx: Pointer to SDMMC register base
- * @param Command: pointer to a SDMMC_CmdInitTypeDef structure that contains
+ * @param SDMMCx Pointer to SDMMC register base
+ * @param Command pointer to a SDMMC_CmdInitTypeDef structure that contains
* the configuration information for the SDMMC command
* @retval HAL status
*/
@@ -393,7 +391,7 @@
/**
* @brief Return the command index of last command for which response received
- * @param SDMMCx: Pointer to SDMMC register base
+ * @param SDMMCx Pointer to SDMMC register base
* @retval Command index of the last command response received
*/
uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx)
@@ -404,8 +402,8 @@
/**
* @brief Return the response received from the card for the last command
- * @param SDMMCx: Pointer to SDMMC register base
- * @param Response: Specifies the SDMMC response register.
+ * @param SDMMCx Pointer to SDMMC register base
+ * @param Response Specifies the SDMMC response register.
* This parameter can be one of the following values:
* @arg SDMMC_RESP1: Response Register 1
* @arg SDMMC_RESP2: Response Register 2
@@ -429,8 +427,8 @@
/**
* @brief Configure the SDMMC data path according to the specified
* parameters in the SDMMC_DataInitTypeDef.
- * @param SDMMCx: Pointer to SDMMC register base
- * @param Data : pointer to a SDMMC_DataInitTypeDef structure
+ * @param SDMMCx Pointer to SDMMC register base
+ * @param Data pointer to a SDMMC_DataInitTypeDef structure
* that contains the configuration information for the SDMMC data.
* @retval HAL status
*/
@@ -466,7 +464,7 @@
/**
* @brief Returns number of remaining data bytes to be transferred.
- * @param SDMMCx: Pointer to SDMMC register base
+ * @param SDMMCx Pointer to SDMMC register base
* @retval Number of remaining data bytes to be transferred
*/
uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx)
@@ -476,7 +474,7 @@
/**
* @brief Get the FIFO data
- * @param SDMMCx: Pointer to SDMMC register base
+ * @param SDMMCx Pointer to SDMMC register base
* @retval Data received
*/
uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx)
@@ -486,8 +484,8 @@
/**
* @brief Sets one of the two options of inserting read wait interval.
- * @param SDMMCx: Pointer to SDMMC register base
- * @param SDMMC_ReadWaitMode: SDMMC Read Wait operation mode.
+ * @param SDMMCx Pointer to SDMMC register base
+ * @param SDMMC_ReadWaitMode SDMMC Read Wait operation mode.
* This parameter can be:
* @arg SDMMC_READ_WAIT_MODE_CLK: Read Wait control by stopping SDMMCCLK
* @arg SDMMC_READ_WAIT_MODE_DATA2: Read Wait control using SDMMC_DATA2
@@ -525,7 +523,7 @@
/**
* @brief Send the Data Block Lenght command and check the response
- * @param SDMMCx: Pointer to SDMMC register base
+ * @param SDMMCx Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize)
@@ -549,7 +547,7 @@
/**
* @brief Send the Read Single Block command and check the response
- * @param SDMMCx: Pointer to SDMMC register base
+ * @param SDMMCx Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd)
@@ -573,7 +571,7 @@
/**
* @brief Send the Read Multi Block command and check the response
- * @param SDMMCx: Pointer to SDMMC register base
+ * @param SDMMCx Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd)
@@ -597,7 +595,7 @@
/**
* @brief Send the Write Single Block command and check the response
- * @param SDMMCx: Pointer to SDMMC register base
+ * @param SDMMCx Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd)
@@ -621,7 +619,7 @@
/**
* @brief Send the Write Multi Block command and check the response
- * @param SDMMCx: Pointer to SDMMC register base
+ * @param SDMMCx Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd)
@@ -645,7 +643,7 @@
/**
* @brief Send the Start Address Erase command for SD and check the response
- * @param SDMMCx: Pointer to SDMMC register base
+ * @param SDMMCx Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd)
@@ -669,7 +667,7 @@
/**
* @brief Send the End Address Erase command for SD and check the response
- * @param SDMMCx: Pointer to SDMMC register base
+ * @param SDMMCx Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd)
@@ -693,7 +691,7 @@
/**
* @brief Send the Start Address Erase command and check the response
- * @param SDMMCx: Pointer to SDMMC register base
+ * @param SDMMCx Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd)
@@ -717,7 +715,7 @@
/**
* @brief Send the End Address Erase command and check the response
- * @param SDMMCx: Pointer to SDMMC register base
+ * @param SDMMCx Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd)
@@ -741,7 +739,7 @@
/**
* @brief Send the Erase command and check the response
- * @param SDMMCx: Pointer to SDMMC register base
+ * @param SDMMCx Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx)
@@ -765,7 +763,7 @@
/**
* @brief Send the Stop Transfer command and check the response.
- * @param SDMMCx: Pointer to SDMMC register base
+ * @param SDMMCx Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx)
@@ -789,8 +787,8 @@
/**
* @brief Send the Select Deselect command and check the response.
- * @param SDMMCx: Pointer to SDMMC register base
- * @param addr: Address of the card to be selected
+ * @param SDMMCx Pointer to SDMMC register base
+ * @param addr Address of the card to be selected
* @retval HAL status
*/
uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr)
@@ -814,7 +812,7 @@
/**
* @brief Send the Go Idle State command and check the response.
- * @param SDMMCx: Pointer to SDMMC register base
+ * @param SDMMCx Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx)
@@ -837,7 +835,7 @@
/**
* @brief Send the Operating Condition command and check the response.
- * @param SDMMCx: Pointer to SDMMC register base
+ * @param SDMMCx Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx)
@@ -867,7 +865,7 @@
* @brief Send the Application command to verify that that the next command
* is an application specific com-mand rather than a standard command
* and check the response.
- * @param SDMMCx: Pointer to SDMMC register base
+ * @param SDMMCx Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
@@ -894,7 +892,7 @@
/**
* @brief Send the command asking the accessed card to send its operating
* condition register (OCR)
- * @param SDMMCx: Pointer to SDMMC register base
+ * @param SDMMCx Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t SdType)
@@ -917,7 +915,7 @@
/**
* @brief Send the Bus Width command and check the response.
- * @param SDMMCx: Pointer to SDMMC register base
+ * @param SDMMCx Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth)
@@ -940,7 +938,7 @@
/**
* @brief Send the Send SCR command and check the response.
- * @param SDMMCx: Pointer to SDMMC register base
+ * @param SDMMCx Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx)
@@ -964,7 +962,7 @@
/**
* @brief Send the Send CID command and check the response.
- * @param SDMMCx: Pointer to SDMMC register base
+ * @param SDMMCx Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx)
@@ -988,7 +986,7 @@
/**
* @brief Send the Send CSD command and check the response.
- * @param SDMMCx: Pointer to SDMMC register base
+ * @param SDMMCx Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
@@ -1012,7 +1010,7 @@
/**
* @brief Send the Send CSD command and check the response.
- * @param SDMMCx: Pointer to SDMMC register base
+ * @param SDMMCx Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA)
@@ -1036,7 +1034,7 @@
/**
* @brief Send the Status command and check the response.
- * @param SDMMCx: Pointer to SDMMC register base
+ * @param SDMMCx Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
@@ -1059,7 +1057,7 @@
/**
* @brief Send the Status register command and check the response.
- * @param SDMMCx: Pointer to SDMMC register base
+ * @param SDMMCx Pointer to SDMMC register base
* @retval HAL status
*/
uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx)
@@ -1083,8 +1081,8 @@
/**
* @brief Sends host capacity support information and activates the card's
* initialization process. Send SDMMC_CMD_SEND_OP_COND command
- * @param SDIOx: Pointer to SDIO register base
- * @parame Argument: Argument used for the command
+ * @param SDIOx Pointer to SDIO register base
+ * @parame Argument Argument used for the command
* @retval HAL status
*/
uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
@@ -1107,8 +1105,8 @@
/**
* @brief Checks switchable function and switch card function. SDMMC_CMD_HS_SWITCH comand
- * @param SDIOx: Pointer to SDIO register base
- * @parame Argument: Argument used for the command
+ * @param SDIOx Pointer to SDIO register base
+ * @parame Argument Argument used for the command
* @retval HAL status
*/
uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument)
@@ -1140,7 +1138,7 @@
/**
* @brief Checks for error conditions for CMD0.
- * @param hsd: SD handle
+ * @param hsd SD handle
* @retval SD Card error state
*/
static uint32_t SDMMC_GetCmdError(SDMMC_TypeDef *SDMMCx)
@@ -1166,8 +1164,8 @@
/**
* @brief Checks for error conditions for R1 response.
- * @param hsd: SD handle
- * @param SD_CMD: The sent command index
+ * @param hsd SD handle
+ * @param SD_CMD The sent command index
* @retval SD Card error state
*/
static uint32_t SDMMC_GetCmdResp1(SDMMC_TypeDef *SDMMCx, uint8_t SD_CMD, uint32_t Timeout)
@@ -1296,7 +1294,7 @@
/**
* @brief Checks for error conditions for R2 (CID or CSD) response.
- * @param hsd: SD handle
+ * @param hsd SD handle
* @retval SD Card error state
*/
static uint32_t SDMMC_GetCmdResp2(SDMMC_TypeDef *SDMMCx)
@@ -1338,7 +1336,7 @@
/**
* @brief Checks for error conditions for R3 (OCR) response.
- * @param hsd: SD handle
+ * @param hsd SD handle
* @retval SD Card error state
*/
static uint32_t SDMMC_GetCmdResp3(SDMMC_TypeDef *SDMMCx)
@@ -1374,9 +1372,9 @@
/**
* @brief Checks for error conditions for R6 (RCA) response.
- * @param hsd: SD handle
- * @param SD_CMD: The sent command index
- * @param pRCA: Pointer to the variable that will contain the SD card relative
+ * @param hsd SD handle
+ * @param SD_CMD The sent command index
+ * @param pRCA Pointer to the variable that will contain the SD card relative
* address RCA
* @retval SD Card error state
*/
@@ -1444,7 +1442,7 @@
/**
* @brief Checks for error conditions for R7 response.
- * @param hsd: SD handle
+ * @param hsd SD handle
* @retval SD Card error state
*/
static uint32_t SDMMC_GetCmdResp7(SDMMC_TypeDef *SDMMCx)
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_sdmmc.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_sdmmc.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_ll_sdmmc.h * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief Header file of SDMMC HAL module. ****************************************************************************** * @attention @@ -674,35 +672,35 @@ /** * @brief Enable the SDMMC device. - * @param __INSTANCE__: SDMMC Instance + * @param __INSTANCE__ SDMMC Instance * @retval None */ #define __SDMMC_ENABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR |= SDMMC_CLKCR_CLKEN) /** * @brief Disable the SDMMC device. - * @param __INSTANCE__: SDMMC Instance + * @param __INSTANCE__ SDMMC Instance * @retval None */ #define __SDMMC_DISABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR &= ~SDMMC_CLKCR_CLKEN) /** * @brief Enable the SDMMC DMA transfer. - * @param __INSTANCE__: SDMMC Instance + * @param __INSTANCE__ SDMMC Instance * @retval None */ #define __SDMMC_DMA_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_DMAEN) /** * @brief Disable the SDMMC DMA transfer. - * @param __INSTANCE__: SDMMC Instance + * @param __INSTANCE__ SDMMC Instance * @retval None */ #define __SDMMC_DMA_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_DMAEN) /** * @brief Enable the SDMMC device interrupt. - * @param __INSTANCE__ : Pointer to SDMMC register base - * @param __INTERRUPT__ : specifies the SDMMC interrupt sources to be enabled. + * @param __INSTANCE__ Pointer to SDMMC register base + * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be enabled. * This parameter can be one or a combination of the following values: * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -732,8 +730,8 @@ /** * @brief Disable the SDMMC device interrupt. - * @param __INSTANCE__ : Pointer to SDMMC register base - * @param __INTERRUPT__ : specifies the SDMMC interrupt sources to be disabled. + * @param __INSTANCE__ Pointer to SDMMC register base + * @param __INTERRUPT__ specifies the SDMMC interrupt sources to be disabled. * This parameter can be one or a combination of the following values: * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -763,8 +761,8 @@ /** * @brief Checks whether the specified SDMMC flag is set or not. - * @param __INSTANCE__ : Pointer to SDMMC register base - * @param __FLAG__: specifies the flag to check. + * @param __INSTANCE__ Pointer to SDMMC register base + * @param __FLAG__ specifies the flag to check. * This parameter can be one of the following values: * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) @@ -795,8 +793,8 @@ /** * @brief Clears the SDMMC pending flags. - * @param __INSTANCE__ : Pointer to SDMMC register base - * @param __FLAG__: specifies the flag to clear. + * @param __INSTANCE__ Pointer to SDMMC register base + * @param __FLAG__ specifies the flag to clear. * This parameter can be one or a combination of the following values: * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed) * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed) @@ -815,8 +813,8 @@ /** * @brief Checks whether the specified SDMMC interrupt has occurred or not. - * @param __INSTANCE__ : Pointer to SDMMC register base - * @param __INTERRUPT__: specifies the SDMMC interrupt source to check. + * @param __INSTANCE__ Pointer to SDMMC register base + * @param __INTERRUPT__ specifies the SDMMC interrupt source to check. * This parameter can be one of the following values: * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -846,8 +844,8 @@ /** * @brief Clears the SDMMC's interrupt pending bits. - * @param __INSTANCE__ : Pointer to SDMMC register base - * @param __INTERRUPT__: specifies the interrupt pending bit to clear. + * @param __INSTANCE__ Pointer to SDMMC register base + * @param __INTERRUPT__ specifies the interrupt pending bit to clear. * This parameter can be one or a combination of the following values: * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt @@ -865,56 +863,56 @@ /** * @brief Enable Start the SD I/O Read Wait operation. - * @param __INSTANCE__ : Pointer to SDMMC register base + * @param __INSTANCE__ Pointer to SDMMC register base * @retval None */ #define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTART) /** * @brief Disable Start the SD I/O Read Wait operations. - * @param __INSTANCE__ : Pointer to SDMMC register base + * @param __INSTANCE__ Pointer to SDMMC register base * @retval None */ #define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART) /** * @brief Enable Start the SD I/O Read Wait operation. - * @param __INSTANCE__ : Pointer to SDMMC register base + * @param __INSTANCE__ Pointer to SDMMC register base * @retval None */ #define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTOP) /** * @brief Disable Stop the SD I/O Read Wait operations. - * @param __INSTANCE__ : Pointer to SDMMC register base + * @param __INSTANCE__ Pointer to SDMMC register base * @retval None */ #define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP) /** * @brief Enable the SD I/O Mode Operation. - * @param __INSTANCE__ : Pointer to SDMMC register base + * @param __INSTANCE__ Pointer to SDMMC register base * @retval None */ #define __SDMMC_OPERATION_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_SDIOEN) /** * @brief Disable the SD I/O Mode Operation. - * @param __INSTANCE__ : Pointer to SDMMC register base + * @param __INSTANCE__ Pointer to SDMMC register base * @retval None */ #define __SDMMC_OPERATION_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN) /** * @brief Enable the SD I/O Suspend command sending. - * @param __INSTANCE__ : Pointer to SDMMC register base + * @param __INSTANCE__ Pointer to SDMMC register base * @retval None */ #define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_SDIOSUSPEND) /** * @brief Disable the SD I/O Suspend command sending. - * @param __INSTANCE__ : Pointer to SDMMC register base + * @param __INSTANCE__ Pointer to SDMMC register base * @retval None */ #define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_SDIOSUSPEND)
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_spi.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_spi.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_ll_spi.c * @author MCD Application Team - * @version V1.2.0 - * @date 30-December-2016 * @brief SPI LL module driver. ****************************************************************************** * @attention @@ -549,7 +547,7 @@ * @note To calculate value of PrescalerLinear(I2SDIV[7:0] bits) and PrescalerParity(ODD bit)\n * Check Audio frequency table and formulas inside Reference Manual (SPI/I2S). * @param SPIx SPI Instance - * @param PrescalerLinear value: Min_Data=0x02 and Max_Data=0xFF. + * @param PrescalerLinear value Min_Data=0x02 and Max_Data=0xFF. * @param PrescalerParity This parameter can be one of the following values: * @arg @ref LL_I2S_PRESCALER_PARITY_EVEN * @arg @ref LL_I2S_PRESCALER_PARITY_ODD
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_spi.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_spi.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_ll_spi.h * @author MCD Application Team - * @version V1.2.0 - * @date 30-December-2016 * @brief Header file of SPI LL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_system.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_system.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_ll_system.h * @author MCD Application Team - * @version V1.2.0 - * @date 30-December-2016 * @brief Header file of SYSTEM LL module. @verbatim ==============================================================================
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_tim.c Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_tim.c Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_ll_tim.c * @author MCD Application Team - * @version V1.2.0 - * @date 30-December-2016 * @brief TIM LL module driver. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_tim.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_tim.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_ll_tim.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 30-December-2016
* @brief Header file of TIM LL module.
******************************************************************************
* @attention
@@ -1313,7 +1311,7 @@
*/
__STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
{
- SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
+ CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
}
/**
@@ -1324,7 +1322,7 @@
*/
__STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
{
- CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
+ SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
}
/**
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_usart.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_usart.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_ll_usart.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 30-December-2016
* @brief USART LL module driver.
******************************************************************************
* @attention
@@ -78,8 +76,10 @@
#define IS_LL_USART_BAUDRATE(__BAUDRATE__) ((__BAUDRATE__) <= 27000000U)
/* __VALUE__ In case of oversampling by 16 and 8, BRR content must be greater than or equal to 16d. */
-#define IS_LL_USART_BRR(__VALUE__) (((__VALUE__) >= 16U) \
- && ((__VALUE__) <= 0x0000FFFFU))
+#define IS_LL_USART_BRR_MIN(__VALUE__) ((__VALUE__) >= 16U)
+
+/* __VALUE__ BRR content must be lower than or equal to 0xFFFF. */
+#define IS_LL_USART_BRR_MAX(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
#define IS_LL_USART_DIRECTION(__VALUE__) (((__VALUE__) == LL_USART_DIRECTION_NONE) \
|| ((__VALUE__) == LL_USART_DIRECTION_RX) \
@@ -227,7 +227,7 @@
* USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
* @note Baud rate value stored in USART_InitStruct BaudRate field, should be valid (different from 0).
* @param USARTx USART Instance
- * @param USART_InitStruct: pointer to a LL_USART_InitTypeDef structure
+ * @param USART_InitStruct pointer to a LL_USART_InitTypeDef structure
* that contains the configuration information for the specified USART peripheral.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: USART registers are initialized according to USART_InitStruct content
@@ -332,7 +332,10 @@
USART_InitStruct->BaudRate);
/* Check BRR is greater than or equal to 16d */
- assert_param(IS_LL_USART_BRR(USARTx->BRR));
+ assert_param(IS_LL_USART_BRR_MIN(USARTx->BRR));
+
+ /* Check BRR is greater than or equal to 16d */
+ assert_param(IS_LL_USART_BRR_MAX(USARTx->BRR));
}
}
/* Endif (=> USART not in Disabled state => return ERROR) */
@@ -342,7 +345,7 @@
/**
* @brief Set each @ref LL_USART_InitTypeDef field to default value.
- * @param USART_InitStruct: pointer to a @ref LL_USART_InitTypeDef structure
+ * @param USART_InitStruct pointer to a @ref LL_USART_InitTypeDef structure
* whose fields will be set to default values.
* @retval None
*/
@@ -365,7 +368,7 @@
* @note As some bits in USART configuration registers can only be written when the USART is disabled (USART_CR1_UE bit =0),
* USART IP should be in disabled state prior calling this function. Otherwise, ERROR result will be returned.
* @param USARTx USART Instance
- * @param USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure
+ * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
* that contains the Clock configuration information for the specified USART peripheral.
* @retval An ErrorStatus enumeration value:
* - SUCCESS: USART registers related to Clock settings are initialized according to USART_ClockInitStruct content
@@ -426,7 +429,7 @@
/**
* @brief Set each field of a @ref LL_USART_ClockInitTypeDef type structure to default value.
- * @param USART_ClockInitStruct: pointer to a @ref LL_USART_ClockInitTypeDef structure
+ * @param USART_ClockInitStruct pointer to a @ref LL_USART_ClockInitTypeDef structure
* whose fields will be set to default values.
* @retval None
*/
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_usart.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_usart.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_ll_usart.h * @author MCD Application Team - * @version V1.2.0 - * @date 30-December-2016 * @brief Header file of USART LL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_usb.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_usb.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,24 +2,22 @@
******************************************************************************
* @file stm32f7xx_ll_usb.c
* @author MCD Application Team
- * @version V1.2.2
- * @date 14-April-2017
* @brief USB Low Layer HAL module driver.
- *
- * This file provides firmware functions to manage the following
+ *
+ * This file provides firmware functions to manage the following
* functionalities of the USB Peripheral Controller:
* + Initialization/de-initialization functions
* + I/O operation functions
- * + Peripheral Control functions
+ * + Peripheral Control functions
* + Peripheral State functions
- *
+ *
@verbatim
==============================================================================
##### How to use this driver #####
==============================================================================
[..]
(#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure.
-
+
(#) Call USB_CoreInit() API to initialize the USB Core peripheral.
(#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.
@@ -53,7 +51,7 @@
* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
*
******************************************************************************
- */
+ */
/* Includes ------------------------------------------------------------------*/
#include "stm32f7xx_hal.h"
@@ -72,7 +70,7 @@
/* Private functions ---------------------------------------------------------*/
static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx);
-#ifdef USB_HS_PHYC
+#ifdef USB_HS_PHYC
static HAL_StatusTypeDef USB_HS_PHYCInit(USB_OTG_GlobalTypeDef *USBx);
#endif
@@ -81,23 +79,23 @@
* @{
*/
-/** @defgroup LL_USB_Group1 Initialization/de-initialization functions
- * @brief Initialization and Configuration functions
+/** @defgroup LL_USB_Group1 Initialization/de-initialization functions
+ * @brief Initialization and Configuration functions
*
-@verbatim
+@verbatim
===============================================================================
##### Initialization/de-initialization functions #####
===============================================================================
[..] This section provides functions allowing to:
-
+
@endverbatim
* @{
*/
/**
* @brief Initializes the USB Core
- * @param USBx: USB Instance
- * @param cfg : pointer to a USB_OTG_CfgTypeDef structure that contains
+ * @param USBx USB Instance
+ * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
* the configuration information for the specified USBx peripheral.
* @retval HAL status
*/
@@ -105,12 +103,12 @@
{
if (cfg.phy_itface == USB_OTG_ULPI_PHY)
{
-
+
USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
/* Init The ULPI Interface */
USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);
-
+
/* Select vbus source */
USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
if(cfg.use_external_vbus == 1)
@@ -118,53 +116,53 @@
USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD;
}
/* Reset after a PHY select */
- USB_CoreReset(USBx);
+ USB_CoreReset(USBx);
}
-#ifdef USB_HS_PHYC
-
+#ifdef USB_HS_PHYC
+
else if (cfg.phy_itface == USB_OTG_HS_EMBEDDED_PHY)
{
USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
-
+
/* Init The UTMI Interface */
USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);
-
+
/* Select vbus source */
USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
-
+
/* Select UTMI Interace */
USBx->GUSBCFG &= ~ USB_OTG_GUSBCFG_ULPI_UTMI_SEL;
USBx->GCCFG |= USB_OTG_GCCFG_PHYHSEN;
-
+
/* Enables control of a High Speed USB PHY */
USB_HS_PHYCInit(USBx);
-
+
if(cfg.use_external_vbus == 1)
{
USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD;
}
/* Reset after a PHY select */
- USB_CoreReset(USBx);
-
+ USB_CoreReset(USBx);
+
}
#endif
else /* FS interface (embedded Phy) */
{
/* Select FS Embedded PHY */
USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
-
+
/* Reset after a PHY select and set Host mode */
USB_CoreReset(USBx);
-
+
/* Deactivate the power down*/
USBx->GCCFG = USB_OTG_GCCFG_PWRDWN;
}
-
+
if(cfg.dma_enable == ENABLE)
{
USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2;
USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN;
- }
+ }
return HAL_OK;
}
@@ -172,7 +170,7 @@
/**
* @brief USB_EnableGlobalInt
* Enables the controller's Global Int in the AHB Config reg
- * @param USBx : Selected device
+ * @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
@@ -185,7 +183,7 @@
/**
* @brief USB_DisableGlobalInt
* Disable the controller's Global Int in the AHB Config reg
- * @param USBx : Selected device
+ * @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
@@ -193,39 +191,39 @@
USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;
return HAL_OK;
}
-
+
/**
* @brief USB_SetCurrentMode : Set functional mode
- * @param USBx : Selected device
- * @param mode : current core mode
+ * @param USBx Selected device
+ * @param mode current core mode
* This parameter can be one of these values:
* @arg USB_OTG_DEVICE_MODE: Peripheral mode
* @arg USB_OTG_HOST_MODE: Host mode
- * @arg USB_OTG_DRD_MODE: Dual Role Device mode
+ * @arg USB_OTG_DRD_MODE: Dual Role Device mode
* @retval HAL status
*/
HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_OTG_ModeTypeDef mode)
{
- USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD);
-
+ USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD);
+
if ( mode == USB_OTG_HOST_MODE)
{
- USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD;
+ USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD;
}
else if ( mode == USB_OTG_DEVICE_MODE)
{
- USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
+ USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
}
HAL_Delay(50);
-
+
return HAL_OK;
}
/**
- * @brief USB_DevInit : Initializes the USB_OTG controller registers
+ * @brief USB_DevInit : Initializes the USB_OTG controller registers
* for device mode
- * @param USBx : Selected device
- * @param cfg : pointer to a USB_OTG_CfgTypeDef structure that contains
+ * @param USBx Selected device
+ * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
* the configuration information for the specified USBx peripheral.
* @retval HAL status
*/
@@ -235,51 +233,51 @@
/*Activate VBUS Sensing B */
USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
-
+
if (cfg.vbus_sensing_enable == 0)
{
/* Deactivate VBUS Sensing B */
USBx->GCCFG &= ~ USB_OTG_GCCFG_VBDEN;
-
- /* B-peripheral session valid override enable*/
+
+ /* B-peripheral session valid override enable*/
USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
}
-
+
/* Restart the Phy Clock */
USBx_PCGCCTL = 0;
/* Device mode configuration */
USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80;
-
+
if(cfg.phy_itface == USB_OTG_ULPI_PHY)
{
if(cfg.speed == USB_OTG_SPEED_HIGH)
- {
+ {
/* Set High speed phy */
USB_SetDevSpeed (USBx , USB_OTG_SPEED_HIGH);
}
- else
+ else
{
/* set High speed phy in Full speed mode */
USB_SetDevSpeed (USBx , USB_OTG_SPEED_HIGH_IN_FULL);
}
}
-
+
else if(cfg.phy_itface == USB_OTG_HS_EMBEDDED_PHY)
{
if(cfg.speed == USB_OTG_SPEED_HIGH)
- {
+ {
/* Set High speed phy */
USB_SetDevSpeed (USBx , USB_OTG_SPEED_HIGH);
}
- else
+ else
{
/* set High speed phy in Full speed mode */
USB_SetDevSpeed (USBx , USB_OTG_SPEED_HIGH_IN_FULL);
}
}
-
+
else
{
/* Set Full speed phy */
@@ -289,13 +287,13 @@
/* Flush the FIFOs */
USB_FlushTxFifo(USBx , 0x10); /* all Tx FIFOs */
USB_FlushRxFifo(USBx);
-
+
/* Clear all pending Device Interrupts */
USBx_DEVICE->DIEPMSK = 0;
USBx_DEVICE->DOEPMSK = 0;
USBx_DEVICE->DAINT = 0xFFFFFFFF;
USBx_DEVICE->DAINTMSK = 0;
-
+
for (i = 0; i < cfg.dev_endpoints; i++)
{
if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
@@ -306,11 +304,11 @@
{
USBx_INEP(i)->DIEPCTL = 0;
}
-
+
USBx_INEP(i)->DIEPTSIZ = 0;
USBx_INEP(i)->DIEPINT = 0xFF;
}
-
+
for (i = 0; i < cfg.dev_endpoints; i++)
{
if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
@@ -321,40 +319,40 @@
{
USBx_OUTEP(i)->DOEPCTL = 0;
}
-
+
USBx_OUTEP(i)->DOEPTSIZ = 0;
USBx_OUTEP(i)->DOEPINT = 0xFF;
}
-
+
USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);
-
+
if (cfg.dma_enable == 1)
{
/*Set threshold parameters */
USBx_DEVICE->DTHRCTL = (USB_OTG_DTHRCTL_TXTHRLEN_6 | USB_OTG_DTHRCTL_RXTHRLEN_6);
USBx_DEVICE->DTHRCTL |= (USB_OTG_DTHRCTL_RXTHREN | USB_OTG_DTHRCTL_ISOTHREN | USB_OTG_DTHRCTL_NONISOTHREN);
-
+
i= USBx_DEVICE->DTHRCTL;
}
-
+
/* Disable all interrupts. */
USBx->GINTMSK = 0;
-
+
/* Clear any pending interrupts */
USBx->GINTSTS = 0xBFFFFFFF;
/* Enable the common interrupts */
if (cfg.dma_enable == DISABLE)
{
- USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
+ USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
}
-
+
/* Enable interrupts matching to the Device mode ONLY */
USBx->GINTMSK |= (USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |\
USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |\
USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM|\
USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM);
-
+
if(cfg.Sof_enable)
{
USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM;
@@ -362,17 +360,17 @@
if (cfg.vbus_sensing_enable == ENABLE)
{
- USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT);
+ USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT);
}
-
+
return HAL_OK;
}
/**
* @brief USB_OTG_FlushTxFifo : Flush a Tx FIFO
- * @param USBx : Selected device
- * @param num : FIFO number
+ * @param USBx Selected device
+ * @param num FIFO number
* This parameter can be a value from 1 to 15
15 means Flush all Tx FIFOs
* @retval HAL status
@@ -380,9 +378,9 @@
HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num )
{
uint32_t count = 0;
-
- USBx->GRSTCTL = ( USB_OTG_GRSTCTL_TXFFLSH |(uint32_t)( num << 6));
-
+
+ USBx->GRSTCTL = ( USB_OTG_GRSTCTL_TXFFLSH |(uint32_t)( num << 6));
+
do
{
if (++count > 200000)
@@ -391,22 +389,22 @@
}
}
while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);
-
+
return HAL_OK;
}
/**
* @brief USB_FlushRxFifo : Flush Rx FIFO
- * @param USBx : Selected device
+ * @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
{
uint32_t count = 0;
-
+
USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;
-
+
do
{
if (++count > 200000)
@@ -415,15 +413,15 @@
}
}
while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);
-
+
return HAL_OK;
}
/**
- * @brief USB_SetDevSpeed :Initializes the DevSpd field of DCFG register
+ * @brief USB_SetDevSpeed :Initializes the DevSpd field of DCFG register
* depending the PHY type and the enumeration speed of the device.
- * @param USBx : Selected device
- * @param speed : device speed
+ * @param USBx Selected device
+ * @param speed device speed
* This parameter can be one of these values:
* @arg USB_OTG_SPEED_HIGH: High speed mode
* @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode
@@ -438,8 +436,8 @@
}
/**
- * @brief USB_GetDevSpeed :Return the Dev Speed
- * @param USBx : Selected device
+ * @brief USB_GetDevSpeed :Return the Dev Speed
+ * @param USBx Selected device
* @retval speed : device speed
* This parameter can be one of these values:
* @arg USB_OTG_SPEED_HIGH: High speed mode
@@ -449,7 +447,7 @@
uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)
{
uint8_t speed = 0;
-
+
if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ)
{
speed = USB_OTG_SPEED_HIGH;
@@ -463,14 +461,14 @@
{
speed = USB_OTG_SPEED_LOW;
}
-
+
return speed;
}
/**
* @brief Activate and configure an endpoint
- * @param USBx : Selected device
- * @param ep: pointer to endpoint structure
+ * @param USBx Selected device
+ * @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
@@ -478,49 +476,49 @@
if (ep->is_in == 1)
{
USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)));
-
+
if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0)
{
USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\
- ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP));
- }
+ ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP));
+ }
}
else
{
USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16);
-
+
if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0)
{
USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\
(USB_OTG_DIEPCTL_SD0PID_SEVNFRM)| (USB_OTG_DOEPCTL_USBAEP));
- }
+ }
}
return HAL_OK;
}
/**
* @brief Activate and configure a dedicated endpoint
- * @param USBx : Selected device
- * @param ep: pointer to endpoint structure
+ * @param USBx Selected device
+ * @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
{
static __IO uint32_t debug = 0;
-
+
/* Read DEPCTLn register */
if (ep->is_in == 1)
{
if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0)
{
USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\
- ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP));
- }
-
-
+ ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP));
+ }
+
+
debug |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\
- ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP));
-
+ ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP));
+
USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)));
}
else
@@ -529,13 +527,13 @@
{
USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\
((ep->num) << 22 ) | (USB_OTG_DOEPCTL_USBAEP));
-
+
debug = (uint32_t)(((uint32_t )USBx) + USB_OTG_OUT_ENDPOINT_BASE + (0)*USB_OTG_EP_REG_SIZE);
debug = (uint32_t )&USBx_OUTEP(ep->num)->DOEPCTL;
debug |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\
- ((ep->num) << 22 ) | (USB_OTG_DOEPCTL_USBAEP));
- }
-
+ ((ep->num) << 22 ) | (USB_OTG_DOEPCTL_USBAEP));
+ }
+
USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16);
}
@@ -543,8 +541,8 @@
}
/**
* @brief De-activate and de-initialize an endpoint
- * @param USBx : Selected device
- * @param ep: pointer to endpoint structure
+ * @param USBx Selected device
+ * @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
@@ -553,22 +551,22 @@
if (ep->is_in == 1)
{
USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))));
- USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))));
- USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;
+ USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))));
+ USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;
}
else
{
USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));
- USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));
- USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;
+ USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));
+ USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;
}
return HAL_OK;
}
/**
* @brief De-activate and de-initialize a dedicated endpoint
- * @param USBx : Selected device
- * @param ep: pointer to endpoint structure
+ * @param USBx Selected device
+ * @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
@@ -581,7 +579,7 @@
}
else
{
- USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;
+ USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;
USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));
}
return HAL_OK;
@@ -589,27 +587,27 @@
/**
* @brief USB_EPStartXfer : setup and starts a transfer over an EP
- * @param USBx : Selected device
- * @param ep: pointer to endpoint structure
- * @param dma: USB dma enabled or disabled
+ * @param USBx Selected device
+ * @param ep pointer to endpoint structure
+ * @param dma USB dma enabled or disabled
* This parameter can be one of these values:
- * 0 : DMA feature not used
- * 1 : DMA feature used
+ * 0 : DMA feature not used
+ * 1 : DMA feature used
* @retval HAL status
*/
HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma)
{
uint16_t pktcnt = 0;
-
+
/* IN endpoint */
if (ep->is_in == 1)
{
/* Zero Length Packet? */
if (ep->xfer_len == 0)
{
- USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
+ USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ;
- USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
+ USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
}
else
{
@@ -619,15 +617,15 @@
* exist ? 1 : 0)
*/
USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
- USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
+ USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket -1)/ ep->maxpacket) << 19)) ;
- USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
-
+ USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
+
if (ep->type == EP_TYPE_ISOC)
{
- USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT);
- USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1 << 29));
- }
+ USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT);
+ USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1 << 29));
+ }
}
if (dma == 1)
@@ -641,7 +639,7 @@
/* Enable the Tx FIFO Empty Interrupt for this EP */
if (ep->xfer_len > 0)
{
- atomic_set_u32(&USBx_DEVICE->DIEPEMPMSK, 1 << ep->num);
+ atomic_set_u32(&USBx_DEVICE->DIEPEMPMSK, 1 << ep->num); // MBED: changed
}
}
}
@@ -656,42 +654,42 @@
{
USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
}
- }
-
+ }
+
/* EP enable, IN data in FIFO */
USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
-
+
if (ep->type == EP_TYPE_ISOC)
{
- USB_WritePacket(USBx, ep->xfer_buff, ep->num, ep->xfer_len, dma);
- }
+ USB_WritePacket(USBx, ep->xfer_buff, ep->num, ep->xfer_len, dma);
+ }
}
else /* OUT endpoint */
{
/* Program the transfer size and packet count as follows:
* pktcnt = N
* xfersize = N * maxpacket
- */
- USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
- USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
-
+ */
+ USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
+ USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
+
if (ep->xfer_len == 0)
{
USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket);
- USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)) ;
+ USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)) ;
}
else
{
- pktcnt = (ep->xfer_len + ep->maxpacket -1)/ ep->maxpacket;
+ pktcnt = (ep->xfer_len + ep->maxpacket -1)/ ep->maxpacket;
USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (pktcnt << 19));
- USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt));
+ USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt));
}
if (dma == 1)
{
USBx_OUTEP(ep->num)->DOEPDMA = (uint32_t)ep->xfer_buff;
}
-
+
if (ep->type == EP_TYPE_ISOC)
{
if ((USBx_DEVICE->DSTS & ( 1 << 8 )) == 0)
@@ -711,12 +709,12 @@
/**
* @brief USB_EP0StartXfer : setup and starts a transfer over the EP 0
- * @param USBx : Selected device
- * @param ep: pointer to endpoint structure
- * @param dma: USB dma enabled or disabled
+ * @param USBx Selected device
+ * @param ep pointer to endpoint structure
+ * @param dma USB dma enabled or disabled
* This parameter can be one of these values:
- * 0 : DMA feature not used
- * 1 : DMA feature used
+ * 0 : DMA feature not used
+ * 1 : DMA feature used
* @retval HAL status
*/
HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma)
@@ -727,9 +725,9 @@
/* Zero Length Packet? */
if (ep->xfer_len == 0)
{
- USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
+ USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ;
- USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
+ USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
}
else
{
@@ -739,20 +737,17 @@
* exist ? 1 : 0)
*/
USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
- USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
-
+ USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
+
if(ep->xfer_len > ep->maxpacket)
{
ep->xfer_len = ep->maxpacket;
}
USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ;
- USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
-
+ USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
+
}
-
- /* EP enable, IN data in FIFO */
- USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
-
+
if (dma == 1)
{
USBx_INEP(ep->num)->DIEPDMA = (uint32_t)(ep->dma_addr);
@@ -762,9 +757,12 @@
/* Enable the Tx FIFO Empty Interrupt for this EP */
if (ep->xfer_len > 0U)
{
- USBx_DEVICE->DIEPEMPMSK |= 1 << (ep->num);
+ USBx_DEVICE->DIEPEMPMSK |= 1U << (ep->num);
}
- }
+ }
+
+ /* EP enable, IN data in FIFO */
+ USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
}
else /* OUT endpoint */
{
@@ -772,46 +770,46 @@
* pktcnt = N
* xfersize = N * maxpacket
*/
- USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
- USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
-
+ USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
+ USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
+
if (ep->xfer_len > 0)
{
ep->xfer_len = ep->maxpacket;
}
-
+
USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19));
- USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket));
-
+ USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket));
+
if (dma == 1)
{
USBx_OUTEP(ep->num)->DOEPDMA = (uint32_t)(ep->xfer_buff);
}
-
+
/* EP enable */
- USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
+ USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
}
return HAL_OK;
}
/**
- * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated
+ * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated
* with the EP/channel
- * @param USBx : Selected device
- * @param src : pointer to source buffer
- * @param ch_ep_num : endpoint or host channel number
- * @param len : Number of bytes to write
- * @param dma: USB dma enabled or disabled
+ * @param USBx Selected device
+ * @param src pointer to source buffer
+ * @param ch_ep_num endpoint or host channel number
+ * @param len Number of bytes to write
+ * @param dma USB dma enabled or disabled
* This parameter can be one of these values:
- * 0 : DMA feature not used
- * 1 : DMA feature used
+ * 0 : DMA feature not used
+ * 1 : DMA feature used
* @retval HAL status
*/
HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma)
{
uint32_t count32b= 0 , i= 0;
-
+
if (dma == 0)
{
count32b = (len + 3) / 4;
@@ -824,35 +822,35 @@
}
/**
- * @brief USB_ReadPacket : read a packet from the Tx FIFO associated
+ * @brief USB_ReadPacket : read a packet from the Tx FIFO associated
* with the EP/channel
- * @param USBx : Selected device
- * @param src : source pointer
- * @param ch_ep_num : endpoint or host channel number
- * @param len : Number of bytes to read
- * @param dma: USB dma enabled or disabled
+ * @param USBx Selected device
+ * @param src source pointer
+ * @param ch_ep_num endpoint or host channel number
+ * @param len Number of bytes to read
+ * @param dma USB dma enabled or disabled
* This parameter can be one of these values:
- * 0 : DMA feature not used
- * 1 : DMA feature used
+ * 0 : DMA feature not used
+ * 1 : DMA feature used
* @retval pointer to destination buffer
*/
void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
{
uint32_t i=0;
uint32_t count32b = (len + 3) / 4;
-
+
for ( i = 0; i < count32b; i++, dest += 4 )
{
*(__packed uint32_t *)dest = USBx_DFIFO(0);
-
+
}
return ((void *)dest);
}
/**
* @brief USB_EPSetStall : set a stall condition over an EP
- * @param USBx : Selected device
- * @param ep: pointer to endpoint structure
+ * @param USBx Selected device
+ * @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep)
@@ -861,16 +859,16 @@
{
if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == 0)
{
- USBx_INEP(ep->num)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS);
- }
+ USBx_INEP(ep->num)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS);
+ }
USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_STALL;
}
else
{
if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == 0)
{
- USBx_OUTEP(ep->num)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS);
- }
+ USBx_OUTEP(ep->num)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS);
+ }
USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_STALL;
}
return HAL_OK;
@@ -879,8 +877,8 @@
/**
* @brief USB_EPClearStall : Clear a stall condition over an EP
- * @param USBx : Selected device
- * @param ep: pointer to endpoint structure
+ * @param USBx Selected device
+ * @param ep pointer to endpoint structure
* @retval HAL status
*/
HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
@@ -891,7 +889,7 @@
if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK)
{
USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */
- }
+ }
}
else
{
@@ -899,20 +897,20 @@
if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK)
{
USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */
- }
+ }
}
return HAL_OK;
}
/**
* @brief USB_StopDevice : Stop the usb device mode
- * @param USBx : Selected device
+ * @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx)
{
uint32_t i;
-
+
/* Clear Pending interrupt */
for (i = 0; i < 15 ; i++)
{
@@ -920,23 +918,23 @@
USBx_OUTEP(i)->DOEPINT = 0xFF;
}
USBx_DEVICE->DAINT = 0xFFFFFFFF;
-
+
/* Clear interrupt masks */
USBx_DEVICE->DIEPMSK = 0;
USBx_DEVICE->DOEPMSK = 0;
USBx_DEVICE->DAINTMSK = 0;
-
+
/* Flush the FIFO */
USB_FlushRxFifo(USBx);
- USB_FlushTxFifo(USBx , 0x10 );
-
+ USB_FlushTxFifo(USBx , 0x10 );
+
return HAL_OK;
}
/**
* @brief USB_SetDevAddress : Stop the usb device mode
- * @param USBx : Selected device
- * @param address : new device address to be assigned
+ * @param USBx Selected device
+ * @param address new device address to be assigned
* This parameter can be a value from 0 to 255
* @retval HAL status
*/
@@ -944,53 +942,53 @@
{
USBx_DEVICE->DCFG &= ~ (USB_OTG_DCFG_DAD);
USBx_DEVICE->DCFG |= (address << 4) & USB_OTG_DCFG_DAD ;
-
- return HAL_OK;
+
+ return HAL_OK;
}
/**
* @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down
- * @param USBx : Selected device
+ * @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx)
{
USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS ;
HAL_Delay(3);
-
- return HAL_OK;
+
+ return HAL_OK;
}
/**
* @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down
- * @param USBx : Selected device
+ * @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx)
{
USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS ;
HAL_Delay(3);
-
- return HAL_OK;
+
+ return HAL_OK;
}
/**
* @brief USB_ReadInterrupts: return the global USB interrupt status
- * @param USBx : Selected device
+ * @param USBx Selected device
* @retval HAL status
*/
uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx)
{
uint32_t v = 0;
-
+
v = USBx->GINTSTS;
v &= USBx->GINTMSK;
- return v;
+ return v;
}
/**
* @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status
- * @param USBx : Selected device
+ * @param USBx Selected device
* @retval HAL status
*/
uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx)
@@ -1003,7 +1001,7 @@
/**
* @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status
- * @param USBx : Selected device
+ * @param USBx Selected device
* @retval HAL status
*/
uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx)
@@ -1016,8 +1014,8 @@
/**
* @brief Returns Device OUT EP Interrupt register
- * @param USBx : Selected device
- * @param epnum : endpoint number
+ * @param USBx Selected device
+ * @param epnum endpoint number
* This parameter can be a value from 0 to 15
* @retval Device OUT EP Interrupt register
*/
@@ -1031,15 +1029,15 @@
/**
* @brief Returns Device IN EP Interrupt register
- * @param USBx : Selected device
- * @param epnum : endpoint number
+ * @param USBx Selected device
+ * @param epnum endpoint number
* This parameter can be a value from 0 to 15
* @retval Device IN EP Interrupt register
*/
uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum)
{
uint32_t v, msk, emp;
-
+
msk = USBx_DEVICE->DIEPMSK;
emp = USBx_DEVICE->DIEPEMPMSK;
msk |= ((emp >> epnum) & 0x1) << 7;
@@ -1049,21 +1047,21 @@
/**
* @brief USB_ClearInterrupts: clear a USB interrupt
- * @param USBx : Selected device
- * @param interrupt : interrupt flag
+ * @param USBx Selected device
+ * @param interrupt interrupt flag
* @retval None
*/
void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)
{
- USBx->GINTSTS |= interrupt;
+ USBx->GINTSTS |= interrupt;
}
/**
* @brief Returns USB core mode
- * @param USBx : Selected device
+ * @param USBx Selected device
* @retval return core mode : Host or Device
* This parameter can be one of these values:
- * 0 : Host
+ * 0 : Host
* 1 : Device
*/
uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx)
@@ -1074,14 +1072,14 @@
/**
* @brief Activate EP0 for Setup transactions
- * @param USBx : Selected device
+ * @param USBx Selected device
* @retval HAL status
*/
HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx)
{
/* Set the MPS of the IN EP based on the enumeration speed */
USBx_INEP(0)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ;
-
+
if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)
{
USBx_INEP(0)->DIEPCTL |= 3;
@@ -1094,12 +1092,12 @@
/**
* @brief Prepare the EP0 to start the first control setup
- * @param USBx : Selected device
- * @param dma: USB dma enabled or disabled
+ * @param USBx Selected device
+ * @param dma USB dma enabled or disabled
* This parameter can be one of these values:
- * 0 : DMA feature not used
- * 1 : DMA feature used
- * @param psetup : pointer to setup packet
+ * 0 : DMA feature not used
+ * 1 : DMA feature used
+ * @param psetup pointer to setup packet
* @retval HAL status
*/
HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup)
@@ -1107,22 +1105,22 @@
USBx_OUTEP(0)->DOEPTSIZ = 0;
USBx_OUTEP(0)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)) ;
USBx_OUTEP(0)->DOEPTSIZ |= (3 * 8);
- USBx_OUTEP(0)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT;
-
+ USBx_OUTEP(0)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT;
+
if (dma == 1)
{
USBx_OUTEP(0)->DOEPDMA = (uint32_t)psetup;
/* EP enable */
USBx_OUTEP(0)->DOEPCTL = 0x80008000;
}
-
- return HAL_OK;
+
+ return HAL_OK;
}
/**
* @brief Reset the USB Core (needed after USB clock settings change)
- * @param USBx : Selected device
+ * @param USBx Selected device
* @retval HAL status
*/
static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
@@ -1138,7 +1136,7 @@
}
}
while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0);
-
+
/* Core Soft Reset */
count = 0;
USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
@@ -1151,24 +1149,24 @@
}
}
while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);
-
+
return HAL_OK;
}
-#ifdef USB_HS_PHYC
+#ifdef USB_HS_PHYC
/**
- * @brief Enables control of a High Speed USB PHYs
- * Init the low level hardware : GPIO, CLOCK, NVIC...
- * @param USBx : Selected device
+ * @brief Enables control of a High Speed USB PHYÂs
+ * Init the low level hardware : GPIO, CLOCK, NVIC...
+ * @param USBx Selected device
* @retval HAL status
*/
static HAL_StatusTypeDef USB_HS_PHYCInit(USB_OTG_GlobalTypeDef *USBx)
{
uint32_t count = 0;
-
+
/* Enable LDO */
USB_HS_PHYC->USB_HS_PHYC_LDO |= USB_HS_PHYC_LDO_ENABLE;
-
+
/* wait for LDO Ready */
while((USB_HS_PHYC->USB_HS_PHYC_LDO & USB_HS_PHYC_LDO_STATUS) == RESET)
{
@@ -1191,7 +1189,7 @@
{
USB_HS_PHYC->USB_HS_PHYC_PLL = (uint32_t)(0x3 << 1);
}
-
+
else if (HSE_VALUE == 24000000) /* HSE = 24MHz */
{
USB_HS_PHYC->USB_HS_PHYC_PLL = (uint32_t)(0x4 << 1);
@@ -1204,47 +1202,47 @@
{
USB_HS_PHYC->USB_HS_PHYC_PLL = (uint32_t)(0x7 << 1);
}
-
+
/* Control the tuning interface of the High Speed PHY */
USB_HS_PHYC->USB_HS_PHYC_TUNE |= USB_HS_PHYC_TUNE_VALUE;
-
+
/* Enable PLL internal PHY */
USB_HS_PHYC->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL_PLLEN;
/* 2ms Delay required to get internal phy clock stable */
HAL_Delay(2);
-
+
return HAL_OK;
}
#endif /* USB_HS_PHYC */
/**
- * @brief USB_HostInit : Initializes the USB OTG controller registers
- * for Host mode
- * @param USBx : Selected device
- * @param cfg : pointer to a USB_OTG_CfgTypeDef structure that contains
+ * @brief USB_HostInit : Initializes the USB OTG controller registers
+ * for Host mode
+ * @param USBx Selected device
+ * @param cfg pointer to a USB_OTG_CfgTypeDef structure that contains
* the configuration information for the specified USBx peripheral.
* @retval HAL status
*/
HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
{
uint32_t i;
-
+
/* Restart the Phy Clock */
USBx_PCGCCTL = 0;
-
+
/*Activate VBUS Sensing B */
USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
-
+
/* Disable the FS/LS support mode only */
if((cfg.speed == USB_OTG_SPEED_FULL)&&
(USBx != USB_OTG_FS))
{
- USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS;
+ USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS;
}
else
{
- USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);
+ USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);
}
/* Make sure the FIFOs are flushed. */
@@ -1257,39 +1255,39 @@
USBx_HC(i)->HCINT = 0xFFFFFFFF;
USBx_HC(i)->HCINTMSK = 0;
}
-
+
/* Enable VBUS driving */
USB_DriveVbus(USBx, 1);
-
+
HAL_Delay(200);
-
+
/* Disable all interrupts. */
USBx->GINTMSK = 0;
-
+
/* Clear any pending interrupts */
USBx->GINTSTS = 0xFFFFFFFF;
-
+
if(USBx == USB_OTG_FS)
{
/* set Rx FIFO size */
- USBx->GRXFSIZ = (uint32_t )0x80;
+ USBx->GRXFSIZ = (uint32_t )0x80;
USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x60 << 16)& USB_OTG_NPTXFD) | 0x80);
USBx->HPTXFSIZ = (uint32_t )(((0x40 << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0);
}
else
{
/* set Rx FIFO size */
- USBx->GRXFSIZ = (uint32_t )0x200;
+ USBx->GRXFSIZ = (uint32_t )0x200;
USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x100 << 16)& USB_OTG_NPTXFD) | 0x200);
USBx->HPTXFSIZ = (uint32_t )(((0xE0 << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0x300);
}
-
+
/* Enable the common interrupts */
if (cfg.dma_enable == DISABLE)
{
- USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
+ USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
}
-
+
/* Enable interrupts matching to the Host mode ONLY */
USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM |\
USB_OTG_GINTMSK_SOFM |USB_OTG_GINTSTS_DISCINT|\
@@ -1299,20 +1297,20 @@
}
/**
- * @brief USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the
+ * @brief USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the
* HCFG register on the PHY type and set the right frame interval
- * @param USBx : Selected device
- * @param freq : clock frequency
+ * @param USBx Selected device
+ * @param freq clock frequency
* This parameter can be one of these values:
- * HCFG_48_MHZ : Full Speed 48 MHz Clock
- * HCFG_6_MHZ : Low Speed 6 MHz Clock
+ * HCFG_48_MHZ : Full Speed 48 MHz Clock
+ * HCFG_6_MHZ : Low Speed 6 MHz Clock
* @retval HAL status
*/
HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq)
{
USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS);
USBx_HOST->HCFG |= (freq & USB_OTG_HCFG_FSLSPCS);
-
+
if (freq == HCFG_48_MHZ)
{
USBx_HOST->HFIR = (uint32_t)48000;
@@ -1320,13 +1318,13 @@
else if (freq == HCFG_6_MHZ)
{
USBx_HOST->HFIR = (uint32_t)6000;
- }
- return HAL_OK;
+ }
+ return HAL_OK;
}
/**
* @brief USB_OTG_ResetPort : Reset Host Port
- * @param USBx : Selected device
+ * @param USBx Selected device
* @retval HAL status
* @note : (1)The application must wait at least 10 ms
* before clearing the reset bit.
@@ -1340,9 +1338,9 @@
hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |
USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
- USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0);
+ USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0);
HAL_Delay (100); /* See Note #1 */
- USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0);
+ USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0);
HAL_Delay (10);
return HAL_OK;
@@ -1350,9 +1348,9 @@
/**
* @brief USB_DriveVbus : activate or de-activate vbus
- * @param state : VBUS state
+ * @param state VBUS state
* This parameter can be one of these values:
- * 0 : VBUS Active
+ * 0 : VBUS Active
* 1 : VBUS Inactive
* @retval HAL status
*/
@@ -1367,18 +1365,18 @@
if (((hprt0 & USB_OTG_HPRT_PPWR) == 0 ) && (state == 1 ))
{
- USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0);
+ USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0);
}
if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0 ))
{
- USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0);
+ USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0);
}
- return HAL_OK;
+ return HAL_OK;
}
/**
* @brief Return Host Core speed
- * @param USBx : Selected device
+ * @param USBx Selected device
* @retval speed : Host speed
* This parameter can be one of these values:
* @arg USB_OTG_SPEED_HIGH: High speed mode
@@ -1388,14 +1386,14 @@
uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx)
{
__IO uint32_t hprt0;
-
+
hprt0 = USBx_HPRT0;
return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17);
}
/**
* @brief Return Host Current Frame number
- * @param USBx : Selected device
+ * @param USBx Selected device
* @retval current frame number
*/
uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx)
@@ -1405,29 +1403,29 @@
/**
* @brief Initialize a host channel
- * @param USBx : Selected device
- * @param ch_num : Channel number
+ * @param USBx Selected device
+ * @param ch_num Channel number
* This parameter can be a value from 1 to 15
- * @param epnum : Endpoint number
+ * @param epnum Endpoint number
* This parameter can be a value from 1 to 15
- * @param dev_address : Current device address
+ * @param dev_address Current device address
* This parameter can be a value from 0 to 255
- * @param speed : Current device speed
+ * @param speed Current device speed
* This parameter can be one of these values:
* @arg USB_OTG_SPEED_HIGH: High speed mode
* @arg USB_OTG_SPEED_FULL: Full speed mode
* @arg USB_OTG_SPEED_LOW: Low speed mode
- * @param ep_type : Endpoint Type
+ * @param ep_type Endpoint Type
* This parameter can be one of these values:
* @arg EP_TYPE_CTRL: Control type
* @arg EP_TYPE_ISOC: Isochronous type
* @arg EP_TYPE_BULK: Bulk type
* @arg EP_TYPE_INTR: Interrupt type
- * @param mps : Max Packet Size
+ * @param mps Max Packet Size
* This parameter can be a value from 0 to32K
* @retval HAL state
*/
-HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
+HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
uint8_t ch_num,
uint8_t epnum,
uint8_t dev_address,
@@ -1435,28 +1433,28 @@
uint8_t ep_type,
uint16_t mps)
{
-
+
/* Clear old interrupt conditions for this host channel. */
USBx_HC(ch_num)->HCINT = 0xFFFFFFFF;
-
+
/* Enable channel interrupts required for this transfer. */
- switch (ep_type)
+ switch (ep_type)
{
case EP_TYPE_CTRL:
case EP_TYPE_BULK:
-
+
USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\
USB_OTG_HCINTMSK_STALLM |\
USB_OTG_HCINTMSK_TXERRM |\
USB_OTG_HCINTMSK_DTERRM |\
USB_OTG_HCINTMSK_AHBERR |\
USB_OTG_HCINTMSK_NAKM ;
-
- if (epnum & 0x80)
+
+ if (epnum & 0x80)
{
USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
- }
- else
+ }
+ else
{
if(USBx != USB_OTG_FS)
{
@@ -1464,43 +1462,43 @@
}
}
break;
-
+
case EP_TYPE_INTR:
-
+
USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\
USB_OTG_HCINTMSK_STALLM |\
USB_OTG_HCINTMSK_TXERRM |\
USB_OTG_HCINTMSK_DTERRM |\
USB_OTG_HCINTMSK_NAKM |\
USB_OTG_HCINTMSK_AHBERR |\
- USB_OTG_HCINTMSK_FRMORM ;
-
- if (epnum & 0x80)
+ USB_OTG_HCINTMSK_FRMORM ;
+
+ if (epnum & 0x80)
{
USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
}
-
+
break;
case EP_TYPE_ISOC:
-
+
USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\
USB_OTG_HCINTMSK_ACKM |\
USB_OTG_HCINTMSK_AHBERR |\
- USB_OTG_HCINTMSK_FRMORM ;
-
- if (epnum & 0x80)
+ USB_OTG_HCINTMSK_FRMORM ;
+
+ if (epnum & 0x80)
{
- USBx_HC(ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM);
+ USBx_HC(ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM);
}
break;
}
-
+
/* Enable the top level host channel interrupt. */
USBx_HOST->HAINTMSK |= (1 << ch_num);
-
+
/* Make sure host channel interrupts are enabled. */
USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM;
-
+
/* Program the HCCHAR register */
USBx_HC(ch_num)->HCCHAR = (((dev_address << 22) & USB_OTG_HCCHAR_DAD) |\
(((epnum & 0x7F)<< 11) & USB_OTG_HCCHAR_EPNUM)|\
@@ -1508,33 +1506,33 @@
(((speed == HPRT0_PRTSPD_LOW_SPEED)<< 17) & USB_OTG_HCCHAR_LSDEV)|\
((ep_type << 18) & USB_OTG_HCCHAR_EPTYP)|\
(mps & USB_OTG_HCCHAR_MPSIZ));
-
+
if (ep_type == EP_TYPE_INTR)
{
USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ;
}
- return HAL_OK;
+ return HAL_OK;
}
/**
* @brief Start a transfer over a host channel
- * @param USBx : Selected device
- * @param hc : pointer to host channel structure
- * @param dma: USB dma enabled or disabled
+ * @param USBx Selected device
+ * @param hc pointer to host channel structure
+ * @param dma USB dma enabled or disabled
* This parameter can be one of these values:
- * 0 : DMA feature not used
- * 1 : DMA feature used
+ * 0 : DMA feature not used
+ * 1 : DMA feature used
* @retval HAL state
*/
HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma)
{
static __IO uint32_t tmpreg = 0;
- uint8_t is_oddframe = 0;
- uint16_t len_words = 0;
+ uint8_t is_oddframe = 0;
+ uint16_t len_words = 0;
uint16_t num_packets = 0;
uint16_t max_hc_pkt_count = 256;
-
+
if((USBx != USB_OTG_FS) && (hc->speed == USB_OTG_SPEED_HIGH))
{
if((dma == 0) && (hc->do_ping == 1))
@@ -1548,12 +1546,12 @@
hc->do_ping = 0;
}
}
-
+
/* Compute the expected number of packets associated to the transfer */
if (hc->xfer_len > 0)
{
num_packets = (hc->xfer_len + hc->max_packet - 1) / hc->max_packet;
-
+
if (num_packets > max_hc_pkt_count)
{
num_packets = max_hc_pkt_count;
@@ -1568,40 +1566,50 @@
{
hc->xfer_len = num_packets * hc->max_packet;
}
-
+
/* Initialize the HCTSIZn register */
USBx_HC(hc->ch_num)->HCTSIZ = (((hc->xfer_len) & USB_OTG_HCTSIZ_XFRSIZ)) |\
((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\
(((hc->data_pid) << 29) & USB_OTG_HCTSIZ_DPID);
-
+
if (dma)
{
/* xfer_buff MUST be 32-bits aligned */
USBx_HC(hc->ch_num)->HCDMA = (uint32_t)hc->xfer_buff;
}
-
+
is_oddframe = (USBx_HOST->HFNUM & 0x01) ? 0 : 1;
USBx_HC(hc->ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM;
USBx_HC(hc->ch_num)->HCCHAR |= (is_oddframe << 29);
-
+
/* Set host channel enable */
tmpreg = USBx_HC(hc->ch_num)->HCCHAR;
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
+
+ /* make sure to set the correct ep direction */
+ if (hc->ep_is_in)
+ {
+ tmpreg |= USB_OTG_HCCHAR_EPDIR;
+ }
+ else
+ {
+ tmpreg &= ~USB_OTG_HCCHAR_EPDIR;
+ }
tmpreg |= USB_OTG_HCCHAR_CHENA;
USBx_HC(hc->ch_num)->HCCHAR = tmpreg;
-
+
if (dma == 0) /* Slave mode */
- {
+ {
if((hc->ep_is_in == 0) && (hc->xfer_len > 0))
{
- switch(hc->ep_type)
+ switch(hc->ep_type)
{
/* Non periodic transfer */
case EP_TYPE_CTRL:
case EP_TYPE_BULK:
-
+
len_words = (hc->xfer_len + 3) / 4;
-
+
/* check if there is enough space in FIFO space */
if(len_words > (USBx->HNPTXSTS & 0xFFFF))
{
@@ -1617,27 +1625,26 @@
if(len_words > (USBx_HOST->HPTXSTS & 0xFFFF)) /* split the transfer */
{
/* need to process data in ptxfempty interrupt */
- USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM;
+ USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM;
}
break;
-
+
default:
break;
}
-
+
/* Write packet into the Tx FIFO. */
USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, hc->xfer_len, 0);
- hc->xfer_count = hc->xfer_len;
-
+ hc->xfer_count = hc->xfer_len; // MBED: added
}
}
-
+
return HAL_OK;
}
/**
* @brief Read all host channel interrupts status
- * @param USBx : Selected device
+ * @param USBx Selected device
* @retval HAL state
*/
uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx)
@@ -1647,71 +1654,71 @@
/**
* @brief Halt a host channel
- * @param USBx : Selected device
- * @param hc_num : Host Channel number
+ * @param USBx Selected device
+ * @param hc_num Host Channel number
* This parameter can be a value from 1 to 15
* @retval HAL state
*/
HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num)
{
uint32_t count = 0;
-
+
/* Check for space in the request queue to issue the halt. */
if (((((USBx_HC(hc_num)->HCCHAR) & USB_OTG_HCCHAR_EPTYP) >> 18) == HCCHAR_CTRL) ||
(((((USBx_HC(hc_num)->HCCHAR) & USB_OTG_HCCHAR_EPTYP) >> 18) == HCCHAR_BULK)))
{
USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
-
+
if ((USBx->HNPTXSTS & 0xFFFF) == 0)
{
USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
- USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+ USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
- do
+ do
{
- if (++count > 1000)
+ if (++count > 1000)
{
break;
}
- }
- while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
+ }
+ while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
}
else
{
- USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+ USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
}
}
else
{
USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
-
+
if ((USBx_HOST->HPTXSTS & 0xFFFF) == 0)
{
USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
- USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+ USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
- do
+ do
{
- if (++count > 1000)
+ if (++count > 1000)
{
break;
}
- }
- while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
+ }
+ while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
}
else
{
- USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
+ USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
}
}
-
+
return HAL_OK;
}
/**
* @brief Initiate Do Ping protocol
- * @param USBx : Selected device
- * @param hc_num : Host Channel number
+ * @param USBx Selected device
+ * @param hc_num Host Channel number
* This parameter can be a value from 1 to 15
* @retval HAL state
*/
@@ -1722,19 +1729,19 @@
USBx_HC(ch_num)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\
USB_OTG_HCTSIZ_DOPING;
-
+
/* Set host channel enable */
tmpreg = USBx_HC(ch_num)->HCCHAR;
tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
tmpreg |= USB_OTG_HCCHAR_CHENA;
USBx_HC(ch_num)->HCCHAR = tmpreg;
-
- return HAL_OK;
+
+ return HAL_OK;
}
/**
* @brief Stop Host Core
- * @param USBx : Selected device
+ * @param USBx Selected device
* @retval HAL state
*/
HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
@@ -1742,41 +1749,41 @@
uint8_t i;
uint32_t count = 0;
uint32_t value;
-
+
USB_DisableGlobalInt(USBx);
-
+
/* Flush FIFO */
USB_FlushTxFifo(USBx, 0x10);
USB_FlushRxFifo(USBx);
-
+
/* Flush out any leftover queued requests. */
for (i = 0; i <= 15; i++)
- {
+ {
value = USBx_HC(i)->HCCHAR ;
value |= USB_OTG_HCCHAR_CHDIS;
- value &= ~USB_OTG_HCCHAR_CHENA;
+ value &= ~USB_OTG_HCCHAR_CHENA;
value &= ~USB_OTG_HCCHAR_EPDIR;
USBx_HC(i)->HCCHAR = value;
}
-
- /* Halt all channels to put them into a known state. */
+
+ /* Halt all channels to put them into a known state. */
for (i = 0; i <= 15; i++)
{
value = USBx_HC(i)->HCCHAR ;
-
+
value |= USB_OTG_HCCHAR_CHDIS;
- value |= USB_OTG_HCCHAR_CHENA;
+ value |= USB_OTG_HCCHAR_CHENA;
value &= ~USB_OTG_HCCHAR_EPDIR;
-
+
USBx_HC(i)->HCCHAR = value;
- do
+ do
{
- if (++count > 1000)
+ if (++count > 1000)
{
break;
}
- }
+ }
while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
}
@@ -1784,7 +1791,7 @@
USBx_HOST->HAINT = 0xFFFFFFFF;
USBx->GINTSTS = 0xFFFFFFFF;
USB_EnableGlobalInt(USBx);
- return HAL_OK;
+ return HAL_OK;
}
/**
* @}
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_usb.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_usb.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_ll_usb.h * @author MCD Application Team - * @version V1.2.2 - * @date 14-April-2017 * @brief Header file of USB Core HAL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_utils.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_utils.c Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_ll_utils.c
* @author MCD Application Team
- * @version V1.2.0
- * @date 30-December-2016
* @brief UTILS LL module driver.
******************************************************************************
* @attention
@@ -39,6 +37,12 @@
#include "stm32f7xx_ll_rcc.h"
#include "stm32f7xx_ll_system.h"
#include "stm32f7xx_ll_pwr.h"
+// MBED: removed
+//#ifdef USE_FULL_ASSERT
+//#include "stm32_assert.h"
+//#else
+//#define assert_param(expr) ((void)0U)
+//#endif /* USE_FULL_ASSERT */
/** @addtogroup STM32F7xx_LL_Driver
* @{
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_utils.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_utils.h Tue Mar 20 16:56:18 2018 +0000
@@ -2,8 +2,6 @@
******************************************************************************
* @file stm32f7xx_ll_utils.h
* @author MCD Application Team
- * @version V1.2.0
- * @date 30-December-2016
* @brief Header file of UTILS LL module.
@verbatim
==============================================================================
@@ -238,7 +236,7 @@
*/
__STATIC_INLINE uint32_t LL_GetFlashSize(void)
{
- return (uint16_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)));
+ return (uint32_t)(READ_REG(*((uint32_t *)FLASHSIZE_BASE_ADDRESS)) & 0xFFFFU);
}
/**
@@ -253,7 +251,7 @@
*/
__STATIC_INLINE uint32_t LL_GetPackageType(void)
{
- return (uint16_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x0700U);
+ return (uint32_t)(READ_REG(*((uint32_t *)PACKAGE_BASE_ADDRESS)) & 0x0700U);
}
/**
--- a/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_wwdg.h Fri Feb 16 16:09:33 2018 +0000 +++ b/targets/TARGET_STM/TARGET_STM32F7/device/stm32f7xx_ll_wwdg.h Tue Mar 20 16:56:18 2018 +0000 @@ -2,8 +2,6 @@ ****************************************************************************** * @file stm32f7xx_ll_wwdg.h * @author MCD Application Team - * @version V1.2.0 - * @date 30-December-2016 * @brief Header file of WWDG LL module. ****************************************************************************** * @attention
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/system_clock.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_NUCLEO_L073RZ/device/system_clock.c Tue Mar 20 16:56:18 2018 +0000
@@ -209,7 +209,7 @@
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
- RCC_OscInitStruct.HSICalibrationValue = 16;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; /* For USB and RNG clock */
// PLLCLK = (16 MHz * 4)/2 = 32 MHz
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_DISCO_L053C8/system_clock.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_DISCO_L053C8/system_clock.c Tue Mar 20 16:56:18 2018 +0000
@@ -210,7 +210,7 @@
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
- RCC_OscInitStruct.HSICalibrationValue = 16;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; /* For USB and RNG clock */
// PLLCLK = (16 MHz * 4)/2 = 32 MHz
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_NUCLEO_L053R8/system_clock.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L053x8/TARGET_NUCLEO_L053R8/system_clock.c Tue Mar 20 16:56:18 2018 +0000
@@ -210,7 +210,7 @@
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
- RCC_OscInitStruct.HSICalibrationValue = 16;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; /* For USB and RNG clock */
// PLLCLK = (16 MHz * 4)/2 = 32 MHz
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
--- a/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L0x2xZ/TARGET_MTB_MURATA_ABZ/system_clock.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L0/TARGET_STM32L0x2xZ/TARGET_MTB_MURATA_ABZ/system_clock.c Tue Mar 20 16:56:18 2018 +0000
@@ -115,7 +115,7 @@
RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSI | RCC_OSCILLATORTYPE_HSI48;
RCC_OscInitStruct.HSEState = RCC_HSE_OFF;
RCC_OscInitStruct.HSIState = RCC_HSI_ON;
- RCC_OscInitStruct.HSICalibrationValue = 16;
+ RCC_OscInitStruct.HSICalibrationValue = RCC_HSICALIBRATION_DEFAULT;
RCC_OscInitStruct.HSI48State = RCC_HSI48_ON; /* For USB and RNG clock */
// PLLCLK = (16 MHz * 4)/2 = 32 MHz
RCC_OscInitStruct.PLL.PLLState = RCC_PLL_ON;
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_GCC_ARM/STM32L475XX.ld Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/device/TOOLCHAIN_GCC_ARM/STM32L475XX.ld Tue Mar 20 16:56:18 2018 +0000
@@ -139,24 +139,29 @@
__end__ = .;
end = __end__;
*(.heap*)
+ . += (ORIGIN(SRAM1) + LENGTH(SRAM1) - .);
__HeapLimit = .;
} > SRAM1
-
+ PROVIDE(__heap_size = SIZEOF(.heap));
+ PROVIDE(__mbed_sbrk_start = ADDR(.heap));
+ PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));
+ /* Check if data + heap exceeds RAM1 limit */
+ ASSERT((ORIGIN(SRAM1)+LENGTH(SRAM1)) >= __HeapLimit, "SRAM1 overflow")
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (COPY):
{
*(.stack*)
- } > SRAM1
+ } > SRAM2
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
- __StackTop = ORIGIN(SRAM1) + LENGTH(SRAM1);
+ __StackTop = ORIGIN(SRAM2) + LENGTH(SRAM2);
_estack = __StackTop;
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
PROVIDE(__stack = __StackTop);
+ /* Check if stack exceeds RAM2 limit */
+ ASSERT((ORIGIN(SRAM2)+LENGTH(SRAM2)) >= __StackLimit, "SRAM2 overflow")
- /* Check if data + heap + stack exceeds RAM limit */
- ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
}
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_GCC_ARM/STM32L476XX.ld Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L476xG/device/TOOLCHAIN_GCC_ARM/STM32L476XX.ld Tue Mar 20 16:56:18 2018 +0000
@@ -139,24 +139,29 @@
__end__ = .;
end = __end__;
*(.heap*)
+ . += (ORIGIN(SRAM1) + LENGTH(SRAM1) - .);
__HeapLimit = .;
} > SRAM1
-
+ PROVIDE(__heap_size = SIZEOF(.heap));
+ PROVIDE(__mbed_sbrk_start = ADDR(.heap));
+ PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));
+ /* Check if data + heap exceeds RAM1 limit */
+ ASSERT((ORIGIN(SRAM1)+LENGTH(SRAM1)) >= __HeapLimit, "SRAM1 overflow")
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (COPY):
{
*(.stack*)
- } > SRAM1
+ } > SRAM2
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
- __StackTop = ORIGIN(SRAM1) + LENGTH(SRAM1);
+ __StackTop = ORIGIN(SRAM2) + LENGTH(SRAM2);
_estack = __StackTop;
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
PROVIDE(__stack = __StackTop);
+ /* Check if stack exceeds RAM2 limit */
+ ASSERT((ORIGIN(SRAM2)+LENGTH(SRAM2)) >= __StackLimit, "SRAM2 overflow")
- /* Check if data + heap + stack exceeds RAM limit */
- ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
}
--- a/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_GCC_ARM/STM32L486XX.ld Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L486xG/device/TOOLCHAIN_GCC_ARM/STM32L486XX.ld Tue Mar 20 16:56:18 2018 +0000
@@ -131,24 +131,29 @@
__end__ = .;
end = __end__;
*(.heap*)
+ . += (ORIGIN(SRAM1) + LENGTH(SRAM1) - .);
__HeapLimit = .;
} > SRAM1
-
+ PROVIDE(__heap_size = SIZEOF(.heap));
+ PROVIDE(__mbed_sbrk_start = ADDR(.heap));
+ PROVIDE(__mbed_krbs_start = ADDR(.heap) + SIZEOF(.heap));
+ /* Check if data + heap exceeds RAM1 limit */
+ ASSERT((ORIGIN(SRAM1)+LENGTH(SRAM1)) >= __HeapLimit, "SRAM1 overflow")
/* .stack_dummy section doesn't contains any symbols. It is only
* used for linker to calculate size of stack sections, and assign
* values to stack symbols later */
.stack_dummy (COPY):
{
*(.stack*)
- } > SRAM1
+ } > SRAM2
/* Set stack top to end of RAM, and stack limit move down by
* size of stack_dummy section */
- __StackTop = ORIGIN(SRAM1) + LENGTH(SRAM1);
+ __StackTop = ORIGIN(SRAM2) + LENGTH(SRAM2);
_estack = __StackTop;
__StackLimit = __StackTop - SIZEOF(.stack_dummy);
PROVIDE(__stack = __StackTop);
+ /* Check if stack exceeds RAM2 limit */
+ ASSERT((ORIGIN(SRAM2)+LENGTH(SRAM2)) >= __StackLimit, "SRAM2 overflow")
- /* Check if data + heap + stack exceeds RAM limit */
- ASSERT(__StackLimit >= __HeapLimit, "region RAM overflowed with stack")
}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000
+++ b/targets/TARGET_STM/TARGET_STM32L4/l4_retarget.c Tue Mar 20 16:56:18 2018 +0000
@@ -0,0 +1,66 @@
+/**
+ ******************************************************************************
+ * @file l4_retarget.c
+ * @author MCD Application Team
+ * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Source File for STM32L475xG
+ ******************************************************************************
+ * @attention
+ *
+ * <h2><center>© COPYRIGHT(c) 2018 STMicroelectronics</center></h2>
+ *
+ * Redistribution and use in source and binary forms, with or without modification,
+ * are permitted provided that the following conditions are met:
+ * 1. Redistributions of source code must retain the above copyright notice,
+ * this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright notice,
+ * this list of conditions and the following disclaimer in the documentation
+ * and/or other materials provided with the distribution.
+ * 3. Neither the name of STMicroelectronics nor the names of its contributors
+ * may be used to endorse or promote products derived from this software
+ * without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
+ * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
+ * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
+ * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
+ * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
+ * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
+ * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
+ * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
+ * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ******************************************************************************
+ */
+#if (defined(TWO_RAM_REGIONS) && defined(__GNUC__) && !defined(__CC_ARM))
+#include <errno.h>
+#include "stm32l4xx.h"
+extern uint32_t __mbed_sbrk_start;
+extern uint32_t __mbed_krbs_start;
+
+#define STM32L4_HEAP_ALIGN 32
+#define STM32L4_ALIGN_UP(X, ALIGN) (((X) + (ALIGN) - 1) & ~((ALIGN) - 1))
+/**
+ * The default implementation of _sbrk() (in platform/mbed_retarget.cpp) for GCC_ARM requires one-region model (heap and
+ * stack share one region), which doesn't fit two-region model (heap and stack are two distinct regions), for example,
+ * STM32L475xG locates heap on SRAM1 and stack on SRAM2.
+ * Define __wrap__sbrk() to override the default _sbrk(). It is expected to get called through gcc
+ * hooking mechanism ('-Wl,--wrap,_sbrk') or in _sbrk().
+ */
+void *__wrap__sbrk(int incr)
+{
+ static uint32_t heap_ind = (uint32_t) &__mbed_sbrk_start;
+ uint32_t heap_ind_old = STM32L4_ALIGN_UP(heap_ind, STM32L4_HEAP_ALIGN);
+ uint32_t heap_ind_new = STM32L4_ALIGN_UP(heap_ind_old + incr, STM32L4_HEAP_ALIGN);
+
+ if (heap_ind_new > &__mbed_krbs_start) {
+ errno = ENOMEM;
+ return (void *) -1;
+ }
+
+ heap_ind = heap_ind_new;
+
+ return (void *) heap_ind_old;
+}
+#endif /* GCC_ARM toolchain && TWO_RAM_REGIONS*/
+
--- a/targets/TARGET_STM/mbed_rtx.h Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/mbed_rtx.h Tue Mar 20 16:56:18 2018 +0000
@@ -19,7 +19,21 @@
#ifndef INITIAL_SP
-#if (defined(TARGET_STM32F051R8) ||\
+#if (defined(TARGET_STM32L475VG) ||\
+ defined(TARGET_STM32L476RG) ||\
+ defined(TARGET_STM32L476JG) ||\
+ defined(TARGET_STM32L476VG) ||\
+ defined(TARGET_STM32L486RG))
+/* only GCC_ARM and IAR toolchains have the stack on SRAM2 */
+#if (((defined(__GNUC__) && !defined(__CC_ARM)) ||\
+ defined(__IAR_SYSTEMS_ICC__ )) &&\
+ defined(TWO_RAM_REGIONS))
+#define INITIAL_SP (0x10008000UL)
+#else
+#define INITIAL_SP (0x20018000UL)
+#endif /* toolchains */
+
+#elif (defined(TARGET_STM32F051R8) ||\
defined(TARGET_STM32F100RB) ||\
defined(TARGET_STM32L031K6) ||\
defined(TARGET_STM32L053C8) ||\
@@ -69,11 +83,7 @@
#define INITIAL_SP (0x20014000UL)
#elif (defined(TARGET_STM32F401RE) ||\
- defined(TARGET_STM32L475VG) ||\
- defined(TARGET_STM32L476RG) ||\
- defined(TARGET_STM32L476JG) ||\
- defined(TARGET_STM32L476VG) ||\
- defined(TARGET_STM32L486RG))
+ defined(TARGET_STM32F401VE))
#define INITIAL_SP (0x20018000UL)
#elif (defined(TARGET_STM32F207ZG) ||\
@@ -110,5 +120,15 @@
#endif
#endif // INITIAL_SP
+#if (defined(__GNUC__) && !defined(__CC_ARM) && defined(TWO_RAM_REGIONS))
+ extern uint32_t __StackLimit[];
+ extern uint32_t __StackTop[];
+ extern uint32_t __end__[];
+ extern uint32_t __HeapLimit[];
+ #define HEAP_START ((unsigned char*)__end__)
+ #define HEAP_SIZE ((uint32_t)((uint32_t)__HeapLimit - (uint32_t)HEAP_START))
+ #define ISR_STACK_START ((unsigned char*)__StackLimit)
+ #define ISR_STACK_SIZE ((uint32_t)((uint32_t)__StackTop - (uint32_t)__StackLimit))
+#endif
#endif // MBED_MBED_RTX_H
--- a/targets/TARGET_STM/rtc_api.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/rtc_api.c Tue Mar 20 16:56:18 2018 +0000
@@ -144,28 +144,8 @@
void rtc_free(void)
{
-#if !MBED_CONF_TARGET_LSE_AVAILABLE
- // Enable Power clock
- __HAL_RCC_PWR_CLK_ENABLE();
-
- // Enable access to Backup domain
- HAL_PWR_EnableBkUpAccess();
-
- // Reset Backup domain
- __HAL_RCC_BACKUPRESET_FORCE();
- __HAL_RCC_BACKUPRESET_RELEASE();
-
// Disable access to Backup domain
HAL_PWR_DisableBkUpAccess();
-#endif
-
- // Disable LSI and LSE clocks
- RCC_OscInitTypeDef RCC_OscInitStruct = {0};
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_LSI | RCC_OSCILLATORTYPE_LSE;
- RCC_OscInitStruct.PLL.PLLState = RCC_PLL_NONE;
- RCC_OscInitStruct.LSIState = RCC_LSI_OFF;
- RCC_OscInitStruct.LSEState = RCC_LSE_OFF;
- HAL_RCC_OscConfig(&RCC_OscInitStruct);
}
/*
@@ -209,7 +189,8 @@
68 is also a multiple of 4 so it let the leap year synchronized.
Information about STM32F1:
-32bit register is used (no BCD format) for the seconds and a software structure to store dates.
+32bit register is used (no BCD format) for the seconds.
+For date, there is no specific register, only a software structure.
It is then not a problem to not use shifts.
*/
@@ -226,16 +207,25 @@
HAL_RTC_GetTime(&RtcHandle, &timeStruct, RTC_FORMAT_BIN);
HAL_RTC_GetDate(&RtcHandle, &dateStruct, RTC_FORMAT_BIN);
+#if TARGET_STM32F1
+ /* date information is null before first write procedure */
+ /* set 01/01/1970 as default values */
+ if (dateStruct.Year == 0) {
+ dateStruct.Year = 2 ;
+ dateStruct.Month = 1 ;
+ dateStruct.Date = 1 ;
+ }
+#endif
+
// Setup a tm structure based on the RTC
- /* tm_wday information is ignored by mktime */
+ /* tm_wday information is ignored by _rtc_maketime */
+ /* tm_isdst information is ignored by _rtc_maketime */
timeinfo.tm_mon = dateStruct.Month - 1;
timeinfo.tm_mday = dateStruct.Date;
timeinfo.tm_year = dateStruct.Year + 68;
timeinfo.tm_hour = timeStruct.Hours;
timeinfo.tm_min = timeStruct.Minutes;
timeinfo.tm_sec = timeStruct.Seconds;
- // Daylight Saving Time information is not available
- timeinfo.tm_isdst = -1;
// Convert to timestamp
time_t t = _rtc_mktime(&timeinfo);
--- a/targets/TARGET_STM/serial_api.c Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/TARGET_STM/serial_api.c Tue Mar 20 16:56:18 2018 +0000
@@ -369,32 +369,30 @@
struct serial_s *obj_s = SERIAL_S(obj);
obj_s->baudrate = baudrate;
- if (init_uart(obj) != HAL_OK) {
-
#if defined(LPUART1_BASE)
/* Note that LPUART clock source must be in the range [3 x baud rate, 4096 x baud rate], check Ref Manual */
- if (obj_s->uart == LPUART_1) {
- /* Try to change LPUART clock source */
- RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
- if (baudrate == 9600) {
- PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1;
- PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_LSE;
- HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
- if (init_uart(obj) == HAL_OK){
- return;
- }
- }
- else {
- PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1;
- PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_SYSCLK;
- HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
- if (init_uart(obj) == HAL_OK){
- return;
- }
- }
+ if (obj_s->uart == LPUART_1) {
+ /* If baudrate is lower than 9600 try to change to LSE */
+ RCC_PeriphCLKInitTypeDef PeriphClkInitStruct = {0};
+ if (baudrate <= 9600 && __HAL_RCC_GET_FLAG(RCC_FLAG_LSERDY)) {
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1;
+ PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_LSE;
+ HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+ } else {
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1;
+ PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_PCLK1;
+ HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
}
+ if (init_uart(obj) == HAL_OK) {
+ return;
+ }
+ /* Change LPUART clock source and try again */
+ PeriphClkInitStruct.PeriphClockSelection = RCC_PERIPHCLK_LPUART1;
+ PeriphClkInitStruct.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_SYSCLK;
+ HAL_RCCEx_PeriphCLKConfig(&PeriphClkInitStruct);
+ }
#endif /* LPUART1_BASE */
-
+ if (init_uart(obj) != HAL_OK) {
debug("Cannot initialize UART with baud rate %u\n", baudrate);
}
}
@@ -527,6 +525,18 @@
huart->Init.Mode = UART_MODE_TX_RX;
}
+#if defined(LPUART1_BASE)
+ if (huart->Instance == LPUART1) {
+ if (obj_s->baudrate <= 9600) {
+ HAL_UARTEx_EnableClockStopMode(huart);
+ HAL_UARTEx_EnableStopMode(huart);
+ } else {
+ HAL_UARTEx_DisableClockStopMode(huart);
+ HAL_UARTEx_DisableStopMode(huart);
+ }
+ }
+#endif
+
return HAL_UART_Init(huart);
}
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/TARGET_64K/TOOLCHAIN_IAR/startup_efm32hg.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,257 @@ +;/**************************************************************************//** +; * @file startup_efm32hg.s +; * @brief CMSIS Core Device Startup File +; * Silicon Labs EFM32HG Device Series +; * @version 5.0.0 +; * @date 30. January 2012 +; * +; * @note +; * Copyright (C) 2012 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; +; When debugging in RAM, it can be located in RAM with at least a 128 byte +; alignment, 256 byte alignment is requied if all interrupt vectors are in use. +; +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(8) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD 0 + DCD 0 + DCD 0 +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD 0 + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + + DCD DMA_IRQHandler ; 0: DMA Interrupt + DCD GPIO_EVEN_IRQHandler ; 1: GPIO_EVEN Interrupt + DCD TIMER0_IRQHandler ; 2: TIMER0 Interrupt + DCD ACMP0_IRQHandler ; 3: ACMP0 Interrupt + DCD ADC0_IRQHandler ; 4: ADC0 Interrupt + DCD I2C0_IRQHandler ; 5: I2C0 Interrupt + DCD GPIO_ODD_IRQHandler ; 6: GPIO_ODD Interrupt + DCD TIMER1_IRQHandler ; 7: TIMER1 Interrupt + DCD USART1_RX_IRQHandler ; 8: USART1_RX Interrupt + DCD USART1_TX_IRQHandler ; 9: USART1_TX Interrupt + DCD LEUART0_IRQHandler ; 10: LEUART0 Interrupt + DCD PCNT0_IRQHandler ; 11: PCNT0 Interrupt + DCD RTC_IRQHandler ; 12: RTC Interrupt + DCD CMU_IRQHandler ; 13: CMU Interrupt + DCD VCMP_IRQHandler ; 14: VCMP Interrupt + DCD MSC_IRQHandler ; 15: MSC Interrupt + DCD AES_IRQHandler ; 16: AES Interrupt + DCD USART0_RX_IRQHandler ; 17: USART0_RX Interrupt + DCD USART0_TX_IRQHandler ; 18: USART0_TX Interrupt + DCD USB_IRQHandler ; 19: USB Interrupt + DCD TIMER2_IRQHandler ; 20: TIMER2 Interrupt + + +__Vectors_End +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + ; Device specific interrupt handlers + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA_IRQHandler + B DMA_IRQHandler + + PUBWEAK GPIO_EVEN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_EVEN_IRQHandler + B GPIO_EVEN_IRQHandler + + PUBWEAK TIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER0_IRQHandler + B TIMER0_IRQHandler + + PUBWEAK ACMP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ACMP0_IRQHandler + B ACMP0_IRQHandler + + PUBWEAK ADC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC0_IRQHandler + B ADC0_IRQHandler + + PUBWEAK I2C0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C0_IRQHandler + B I2C0_IRQHandler + + PUBWEAK GPIO_ODD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_ODD_IRQHandler + B GPIO_ODD_IRQHandler + + PUBWEAK TIMER1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER1_IRQHandler + B TIMER1_IRQHandler + + PUBWEAK USART1_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_RX_IRQHandler + B USART1_RX_IRQHandler + + PUBWEAK USART1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_TX_IRQHandler + B USART1_TX_IRQHandler + + PUBWEAK LEUART0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LEUART0_IRQHandler + B LEUART0_IRQHandler + + PUBWEAK PCNT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PCNT0_IRQHandler + B PCNT0_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK CMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CMU_IRQHandler + B CMU_IRQHandler + + PUBWEAK VCMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VCMP_IRQHandler + B VCMP_IRQHandler + + PUBWEAK MSC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MSC_IRQHandler + B MSC_IRQHandler + + PUBWEAK AES_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +AES_IRQHandler + B AES_IRQHandler + + PUBWEAK USART0_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART0_RX_IRQHandler + B USART0_RX_IRQHandler + + PUBWEAK USART0_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART0_TX_IRQHandler + B USART0_TX_IRQHandler + + PUBWEAK USB_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB_IRQHandler + B USB_IRQHandler + + PUBWEAK TIMER2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER2_IRQHandler + B TIMER2_IRQHandler + + + END
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG/device/TARGET_64K/TOOLCHAIN_IAR/startup_efm32hg.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,257 +0,0 @@ -;/**************************************************************************//** -; * @file startup_efm32hg.s -; * @brief CMSIS Core Device Startup File -; * Silicon Labs EFM32HG Device Series -; * @version 5.0.0 -; * @date 30. January 2012 -; * -; * @note -; * Copyright (C) 2012 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; -; When debugging in RAM, it can be located in RAM with at least a 128 byte -; alignment, 256 byte alignment is requied if all interrupt vectors are in use. -; -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(8) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler - DCD HardFault_Handler - DCD 0 - DCD 0 - DCD 0 -__vector_table_0x1c - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD SVC_Handler - DCD 0 - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - - DCD DMA_IRQHandler ; 0: DMA Interrupt - DCD GPIO_EVEN_IRQHandler ; 1: GPIO_EVEN Interrupt - DCD TIMER0_IRQHandler ; 2: TIMER0 Interrupt - DCD ACMP0_IRQHandler ; 3: ACMP0 Interrupt - DCD ADC0_IRQHandler ; 4: ADC0 Interrupt - DCD I2C0_IRQHandler ; 5: I2C0 Interrupt - DCD GPIO_ODD_IRQHandler ; 6: GPIO_ODD Interrupt - DCD TIMER1_IRQHandler ; 7: TIMER1 Interrupt - DCD USART1_RX_IRQHandler ; 8: USART1_RX Interrupt - DCD USART1_TX_IRQHandler ; 9: USART1_TX Interrupt - DCD LEUART0_IRQHandler ; 10: LEUART0 Interrupt - DCD PCNT0_IRQHandler ; 11: PCNT0 Interrupt - DCD RTC_IRQHandler ; 12: RTC Interrupt - DCD CMU_IRQHandler ; 13: CMU Interrupt - DCD VCMP_IRQHandler ; 14: VCMP Interrupt - DCD MSC_IRQHandler ; 15: MSC Interrupt - DCD AES_IRQHandler ; 16: AES Interrupt - DCD USART0_RX_IRQHandler ; 17: USART0_RX Interrupt - DCD USART0_TX_IRQHandler ; 18: USART0_TX Interrupt - DCD USB_IRQHandler ; 19: USB Interrupt - DCD TIMER2_IRQHandler ; 20: TIMER2 Interrupt - - -__Vectors_End -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - ; Device specific interrupt handlers - - PUBWEAK DMA_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA_IRQHandler - B DMA_IRQHandler - - PUBWEAK GPIO_EVEN_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO_EVEN_IRQHandler - B GPIO_EVEN_IRQHandler - - PUBWEAK TIMER0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER0_IRQHandler - B TIMER0_IRQHandler - - PUBWEAK ACMP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ACMP0_IRQHandler - B ACMP0_IRQHandler - - PUBWEAK ADC0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ADC0_IRQHandler - B ADC0_IRQHandler - - PUBWEAK I2C0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C0_IRQHandler - B I2C0_IRQHandler - - PUBWEAK GPIO_ODD_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO_ODD_IRQHandler - B GPIO_ODD_IRQHandler - - PUBWEAK TIMER1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER1_IRQHandler - B TIMER1_IRQHandler - - PUBWEAK USART1_RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART1_RX_IRQHandler - B USART1_RX_IRQHandler - - PUBWEAK USART1_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART1_TX_IRQHandler - B USART1_TX_IRQHandler - - PUBWEAK LEUART0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LEUART0_IRQHandler - B LEUART0_IRQHandler - - PUBWEAK PCNT0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PCNT0_IRQHandler - B PCNT0_IRQHandler - - PUBWEAK RTC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC_IRQHandler - B RTC_IRQHandler - - PUBWEAK CMU_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CMU_IRQHandler - B CMU_IRQHandler - - PUBWEAK VCMP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -VCMP_IRQHandler - B VCMP_IRQHandler - - PUBWEAK MSC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -MSC_IRQHandler - B MSC_IRQHandler - - PUBWEAK AES_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -AES_IRQHandler - B AES_IRQHandler - - PUBWEAK USART0_RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART0_RX_IRQHandler - B USART0_RX_IRQHandler - - PUBWEAK USART0_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART0_TX_IRQHandler - B USART0_TX_IRQHandler - - PUBWEAK USB_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USB_IRQHandler - B USB_IRQHandler - - PUBWEAK TIMER2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER2_IRQHandler - B TIMER2_IRQHandler - - - END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/TARGET_256K/TOOLCHAIN_IAR/startup_efm32lg.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,386 @@ +;/**************************************************************************//** +; * @file startup_efm32lg.s +; * @brief CMSIS Core Device Startup File +; * Silicon Labs EFM32LG Device Series +; * @version 5.0.0 +; * @date 30. January 2012 +; * +; * @note +; * Copyright (C) 2012 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; +; When debugging in RAM, it can be located in RAM with at least a 128 byte +; alignment, 256 byte alignment is requied if all interrupt vectors are in use. +; +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(8) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + + DCD DMA_IRQHandler ; 0: DMA Interrupt + DCD GPIO_EVEN_IRQHandler ; 1: GPIO_EVEN Interrupt + DCD TIMER0_IRQHandler ; 2: TIMER0 Interrupt + DCD USART0_RX_IRQHandler ; 3: USART0_RX Interrupt + DCD USART0_TX_IRQHandler ; 4: USART0_TX Interrupt + DCD USB_IRQHandler ; 5: USB Interrupt + DCD ACMP0_IRQHandler ; 6: ACMP0 Interrupt + DCD ADC0_IRQHandler ; 7: ADC0 Interrupt + DCD DAC0_IRQHandler ; 8: DAC0 Interrupt + DCD I2C0_IRQHandler ; 9: I2C0 Interrupt + DCD I2C1_IRQHandler ; 10: I2C1 Interrupt + DCD GPIO_ODD_IRQHandler ; 11: GPIO_ODD Interrupt + DCD TIMER1_IRQHandler ; 12: TIMER1 Interrupt + DCD TIMER2_IRQHandler ; 13: TIMER2 Interrupt + DCD TIMER3_IRQHandler ; 14: TIMER3 Interrupt + DCD USART1_RX_IRQHandler ; 15: USART1_RX Interrupt + DCD USART1_TX_IRQHandler ; 16: USART1_TX Interrupt + DCD LESENSE_IRQHandler ; 17: LESENSE Interrupt + DCD USART2_RX_IRQHandler ; 18: USART2_RX Interrupt + DCD USART2_TX_IRQHandler ; 19: USART2_TX Interrupt + DCD UART0_RX_IRQHandler ; 20: UART0_RX Interrupt + DCD UART0_TX_IRQHandler ; 21: UART0_TX Interrupt + DCD UART1_RX_IRQHandler ; 22: UART1_RX Interrupt + DCD UART1_TX_IRQHandler ; 23: UART1_TX Interrupt + DCD LEUART0_IRQHandler ; 24: LEUART0 Interrupt + DCD LEUART1_IRQHandler ; 25: LEUART1 Interrupt + DCD LETIMER0_IRQHandler ; 26: LETIMER0 Interrupt + DCD PCNT0_IRQHandler ; 27: PCNT0 Interrupt + DCD PCNT1_IRQHandler ; 28: PCNT1 Interrupt + DCD PCNT2_IRQHandler ; 29: PCNT2 Interrupt + DCD RTC_IRQHandler ; 30: RTC Interrupt + DCD BURTC_IRQHandler ; 31: BURTC Interrupt + DCD CMU_IRQHandler ; 32: CMU Interrupt + DCD VCMP_IRQHandler ; 33: VCMP Interrupt + DCD LCD_IRQHandler ; 34: LCD Interrupt + DCD MSC_IRQHandler ; 35: MSC Interrupt + DCD AES_IRQHandler ; 36: AES Interrupt + DCD EBI_IRQHandler ; 37: EBI Interrupt + DCD EMU_IRQHandler ; 38: EMU Interrupt + DCD 0 ; 39: Reserved Interrupt + + +__Vectors_End +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + ; Device specific interrupt handlers + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA_IRQHandler + B DMA_IRQHandler + + PUBWEAK GPIO_EVEN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_EVEN_IRQHandler + B GPIO_EVEN_IRQHandler + + PUBWEAK TIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER0_IRQHandler + B TIMER0_IRQHandler + + PUBWEAK USART0_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART0_RX_IRQHandler + B USART0_RX_IRQHandler + + PUBWEAK USART0_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART0_TX_IRQHandler + B USART0_TX_IRQHandler + + PUBWEAK USB_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB_IRQHandler + B USB_IRQHandler + + PUBWEAK ACMP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ACMP0_IRQHandler + B ACMP0_IRQHandler + + PUBWEAK ADC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC0_IRQHandler + B ADC0_IRQHandler + + PUBWEAK DAC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC0_IRQHandler + B DAC0_IRQHandler + + PUBWEAK I2C0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C0_IRQHandler + B I2C0_IRQHandler + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + PUBWEAK GPIO_ODD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_ODD_IRQHandler + B GPIO_ODD_IRQHandler + + PUBWEAK TIMER1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER1_IRQHandler + B TIMER1_IRQHandler + + PUBWEAK TIMER2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER2_IRQHandler + B TIMER2_IRQHandler + + PUBWEAK TIMER3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER3_IRQHandler + B TIMER3_IRQHandler + + PUBWEAK USART1_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_RX_IRQHandler + B USART1_RX_IRQHandler + + PUBWEAK USART1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_TX_IRQHandler + B USART1_TX_IRQHandler + + PUBWEAK LESENSE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LESENSE_IRQHandler + B LESENSE_IRQHandler + + PUBWEAK USART2_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_RX_IRQHandler + B USART2_RX_IRQHandler + + PUBWEAK USART2_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_TX_IRQHandler + B USART2_TX_IRQHandler + + PUBWEAK UART0_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART0_RX_IRQHandler + B UART0_RX_IRQHandler + + PUBWEAK UART0_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART0_TX_IRQHandler + B UART0_TX_IRQHandler + + PUBWEAK UART1_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART1_RX_IRQHandler + B UART1_RX_IRQHandler + + PUBWEAK UART1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART1_TX_IRQHandler + B UART1_TX_IRQHandler + + PUBWEAK LEUART0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LEUART0_IRQHandler + B LEUART0_IRQHandler + + PUBWEAK LEUART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LEUART1_IRQHandler + B LEUART1_IRQHandler + + PUBWEAK LETIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LETIMER0_IRQHandler + B LETIMER0_IRQHandler + + PUBWEAK PCNT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PCNT0_IRQHandler + B PCNT0_IRQHandler + + PUBWEAK PCNT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PCNT1_IRQHandler + B PCNT1_IRQHandler + + PUBWEAK PCNT2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PCNT2_IRQHandler + B PCNT2_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK BURTC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +BURTC_IRQHandler + B BURTC_IRQHandler + + PUBWEAK CMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CMU_IRQHandler + B CMU_IRQHandler + + PUBWEAK VCMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VCMP_IRQHandler + B VCMP_IRQHandler + + PUBWEAK LCD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LCD_IRQHandler + B LCD_IRQHandler + + PUBWEAK MSC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MSC_IRQHandler + B MSC_IRQHandler + + PUBWEAK AES_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +AES_IRQHandler + B AES_IRQHandler + + PUBWEAK EBI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EBI_IRQHandler + B EBI_IRQHandler + + PUBWEAK EMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EMU_IRQHandler + B EMU_IRQHandler + + + END
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG/device/TARGET_256K/TOOLCHAIN_IAR/startup_efm32lg.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,386 +0,0 @@ -;/**************************************************************************//** -; * @file startup_efm32lg.s -; * @brief CMSIS Core Device Startup File -; * Silicon Labs EFM32LG Device Series -; * @version 5.0.0 -; * @date 30. January 2012 -; * -; * @note -; * Copyright (C) 2012 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; -; When debugging in RAM, it can be located in RAM with at least a 128 byte -; alignment, 256 byte alignment is requied if all interrupt vectors are in use. -; -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(8) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler - DCD HardFault_Handler - DCD MemManage_Handler - DCD BusFault_Handler - DCD UsageFault_Handler -__vector_table_0x1c - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD SVC_Handler - DCD DebugMon_Handler - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - - DCD DMA_IRQHandler ; 0: DMA Interrupt - DCD GPIO_EVEN_IRQHandler ; 1: GPIO_EVEN Interrupt - DCD TIMER0_IRQHandler ; 2: TIMER0 Interrupt - DCD USART0_RX_IRQHandler ; 3: USART0_RX Interrupt - DCD USART0_TX_IRQHandler ; 4: USART0_TX Interrupt - DCD USB_IRQHandler ; 5: USB Interrupt - DCD ACMP0_IRQHandler ; 6: ACMP0 Interrupt - DCD ADC0_IRQHandler ; 7: ADC0 Interrupt - DCD DAC0_IRQHandler ; 8: DAC0 Interrupt - DCD I2C0_IRQHandler ; 9: I2C0 Interrupt - DCD I2C1_IRQHandler ; 10: I2C1 Interrupt - DCD GPIO_ODD_IRQHandler ; 11: GPIO_ODD Interrupt - DCD TIMER1_IRQHandler ; 12: TIMER1 Interrupt - DCD TIMER2_IRQHandler ; 13: TIMER2 Interrupt - DCD TIMER3_IRQHandler ; 14: TIMER3 Interrupt - DCD USART1_RX_IRQHandler ; 15: USART1_RX Interrupt - DCD USART1_TX_IRQHandler ; 16: USART1_TX Interrupt - DCD LESENSE_IRQHandler ; 17: LESENSE Interrupt - DCD USART2_RX_IRQHandler ; 18: USART2_RX Interrupt - DCD USART2_TX_IRQHandler ; 19: USART2_TX Interrupt - DCD UART0_RX_IRQHandler ; 20: UART0_RX Interrupt - DCD UART0_TX_IRQHandler ; 21: UART0_TX Interrupt - DCD UART1_RX_IRQHandler ; 22: UART1_RX Interrupt - DCD UART1_TX_IRQHandler ; 23: UART1_TX Interrupt - DCD LEUART0_IRQHandler ; 24: LEUART0 Interrupt - DCD LEUART1_IRQHandler ; 25: LEUART1 Interrupt - DCD LETIMER0_IRQHandler ; 26: LETIMER0 Interrupt - DCD PCNT0_IRQHandler ; 27: PCNT0 Interrupt - DCD PCNT1_IRQHandler ; 28: PCNT1 Interrupt - DCD PCNT2_IRQHandler ; 29: PCNT2 Interrupt - DCD RTC_IRQHandler ; 30: RTC Interrupt - DCD BURTC_IRQHandler ; 31: BURTC Interrupt - DCD CMU_IRQHandler ; 32: CMU Interrupt - DCD VCMP_IRQHandler ; 33: VCMP Interrupt - DCD LCD_IRQHandler ; 34: LCD Interrupt - DCD MSC_IRQHandler ; 35: MSC Interrupt - DCD AES_IRQHandler ; 36: AES Interrupt - DCD EBI_IRQHandler ; 37: EBI Interrupt - DCD EMU_IRQHandler ; 38: EMU Interrupt - DCD 0 ; 39: Reserved Interrupt - - -__Vectors_End -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - ; Device specific interrupt handlers - - PUBWEAK DMA_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA_IRQHandler - B DMA_IRQHandler - - PUBWEAK GPIO_EVEN_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO_EVEN_IRQHandler - B GPIO_EVEN_IRQHandler - - PUBWEAK TIMER0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER0_IRQHandler - B TIMER0_IRQHandler - - PUBWEAK USART0_RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART0_RX_IRQHandler - B USART0_RX_IRQHandler - - PUBWEAK USART0_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART0_TX_IRQHandler - B USART0_TX_IRQHandler - - PUBWEAK USB_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USB_IRQHandler - B USB_IRQHandler - - PUBWEAK ACMP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ACMP0_IRQHandler - B ACMP0_IRQHandler - - PUBWEAK ADC0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ADC0_IRQHandler - B ADC0_IRQHandler - - PUBWEAK DAC0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DAC0_IRQHandler - B DAC0_IRQHandler - - PUBWEAK I2C0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C0_IRQHandler - B I2C0_IRQHandler - - PUBWEAK I2C1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C1_IRQHandler - B I2C1_IRQHandler - - PUBWEAK GPIO_ODD_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO_ODD_IRQHandler - B GPIO_ODD_IRQHandler - - PUBWEAK TIMER1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER1_IRQHandler - B TIMER1_IRQHandler - - PUBWEAK TIMER2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER2_IRQHandler - B TIMER2_IRQHandler - - PUBWEAK TIMER3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER3_IRQHandler - B TIMER3_IRQHandler - - PUBWEAK USART1_RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART1_RX_IRQHandler - B USART1_RX_IRQHandler - - PUBWEAK USART1_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART1_TX_IRQHandler - B USART1_TX_IRQHandler - - PUBWEAK LESENSE_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LESENSE_IRQHandler - B LESENSE_IRQHandler - - PUBWEAK USART2_RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART2_RX_IRQHandler - B USART2_RX_IRQHandler - - PUBWEAK USART2_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART2_TX_IRQHandler - B USART2_TX_IRQHandler - - PUBWEAK UART0_RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART0_RX_IRQHandler - B UART0_RX_IRQHandler - - PUBWEAK UART0_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART0_TX_IRQHandler - B UART0_TX_IRQHandler - - PUBWEAK UART1_RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART1_RX_IRQHandler - B UART1_RX_IRQHandler - - PUBWEAK UART1_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART1_TX_IRQHandler - B UART1_TX_IRQHandler - - PUBWEAK LEUART0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LEUART0_IRQHandler - B LEUART0_IRQHandler - - PUBWEAK LEUART1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LEUART1_IRQHandler - B LEUART1_IRQHandler - - PUBWEAK LETIMER0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LETIMER0_IRQHandler - B LETIMER0_IRQHandler - - PUBWEAK PCNT0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PCNT0_IRQHandler - B PCNT0_IRQHandler - - PUBWEAK PCNT1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PCNT1_IRQHandler - B PCNT1_IRQHandler - - PUBWEAK PCNT2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PCNT2_IRQHandler - B PCNT2_IRQHandler - - PUBWEAK RTC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC_IRQHandler - B RTC_IRQHandler - - PUBWEAK BURTC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -BURTC_IRQHandler - B BURTC_IRQHandler - - PUBWEAK CMU_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CMU_IRQHandler - B CMU_IRQHandler - - PUBWEAK VCMP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -VCMP_IRQHandler - B VCMP_IRQHandler - - PUBWEAK LCD_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LCD_IRQHandler - B LCD_IRQHandler - - PUBWEAK MSC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -MSC_IRQHandler - B MSC_IRQHandler - - PUBWEAK AES_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -AES_IRQHandler - B AES_IRQHandler - - PUBWEAK EBI_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EBI_IRQHandler - B EBI_IRQHandler - - PUBWEAK EMU_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EMU_IRQHandler - B EMU_IRQHandler - - - END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_ARM_STD/startup_efm32pg12b.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,306 @@ +;/**************************************************************************//** +; * @file startup_efm32pg12b.s +; * @brief CMSIS Core Device Startup File for +; * Silicon Labs EFM32PG12B Device Series +; * @version 5.1.2 +; * @date 03. February 2012 +; * +; * @note +; * Copyright (C) 2012 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ +;/* +;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ +;*/ + +; <h> Stack Configuration +; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + IF :DEF: __STACK_SIZE +Stack_Size EQU __STACK_SIZE + ELSE +Stack_Size EQU 0x00001000 + ENDIF + + AREA STACK, NOINIT, READWRITE, ALIGN=3 +Stack_Mem SPACE Stack_Size +__initial_sp + + +; <h> Heap Configuration +; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> +; </h> + IF :DEF: __HEAP_SIZE +Heap_Size EQU __HEAP_SIZE + ELSE +Heap_Size EQU 0x00004000 + ENDIF + + AREA HEAP, NOINIT, READWRITE, ALIGN=3 +__heap_base +Heap_Mem SPACE Heap_Size +__heap_limit + + + PRESERVE8 + THUMB + + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY, ALIGN=8 + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD MemManage_Handler ; MPU Fault Handler + DCD BusFault_Handler ; Bus Fault Handler + DCD UsageFault_Handler ; Usage Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD DebugMon_Handler ; Debug Monitor Handler + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; External Interrupts + + DCD EMU_IRQHandler ; 0: EMU Interrupt + DCD 0 ; 1: Reserved + DCD WDOG0_IRQHandler ; 2: WDOG0 Interrupt + DCD WDOG1_IRQHandler ; 3: WDOG1 Interrupt + DCD 0 ; 4: Reserved + DCD 0 ; 5: Reserved + DCD 0 ; 6: Reserved + DCD 0 ; 7: Reserved + DCD 0 ; 8: Reserved + DCD LDMA_IRQHandler ; 9: LDMA Interrupt + DCD GPIO_EVEN_IRQHandler ; 10: GPIO_EVEN Interrupt + DCD TIMER0_IRQHandler ; 11: TIMER0 Interrupt + DCD USART0_RX_IRQHandler ; 12: USART0_RX Interrupt + DCD USART0_TX_IRQHandler ; 13: USART0_TX Interrupt + DCD ACMP0_IRQHandler ; 14: ACMP0 Interrupt + DCD ADC0_IRQHandler ; 15: ADC0 Interrupt + DCD IDAC0_IRQHandler ; 16: IDAC0 Interrupt + DCD I2C0_IRQHandler ; 17: I2C0 Interrupt + DCD GPIO_ODD_IRQHandler ; 18: GPIO_ODD Interrupt + DCD TIMER1_IRQHandler ; 19: TIMER1 Interrupt + DCD USART1_RX_IRQHandler ; 20: USART1_RX Interrupt + DCD USART1_TX_IRQHandler ; 21: USART1_TX Interrupt + DCD LEUART0_IRQHandler ; 22: LEUART0 Interrupt + DCD PCNT0_IRQHandler ; 23: PCNT0 Interrupt + DCD CMU_IRQHandler ; 24: CMU Interrupt + DCD MSC_IRQHandler ; 25: MSC Interrupt + DCD CRYPTO0_IRQHandler ; 26: CRYPTO0 Interrupt + DCD LETIMER0_IRQHandler ; 27: LETIMER0 Interrupt + DCD 0 ; 28: Reserved + DCD 0 ; 29: Reserved + DCD RTCC_IRQHandler ; 30: RTCC Interrupt + DCD 0 ; 31: Reserved + DCD CRYOTIMER_IRQHandler ; 32: CRYOTIMER Interrupt + DCD 0 ; 33: Reserved + DCD FPUEH_IRQHandler ; 34: FPUEH Interrupt + DCD SMU_IRQHandler ; 35: SMU Interrupt + DCD WTIMER0_IRQHandler ; 36: WTIMER0 Interrupt + DCD WTIMER1_IRQHandler ; 37: WTIMER1 Interrupt + DCD PCNT1_IRQHandler ; 38: PCNT1 Interrupt + DCD PCNT2_IRQHandler ; 39: PCNT2 Interrupt + DCD USART2_RX_IRQHandler ; 40: USART2_RX Interrupt + DCD USART2_TX_IRQHandler ; 41: USART2_TX Interrupt + DCD I2C1_IRQHandler ; 42: I2C1 Interrupt + DCD USART3_RX_IRQHandler ; 43: USART3_RX Interrupt + DCD USART3_TX_IRQHandler ; 44: USART3_TX Interrupt + DCD VDAC0_IRQHandler ; 45: VDAC0 Interrupt + DCD CSEN_IRQHandler ; 46: CSEN Interrupt + DCD LESENSE_IRQHandler ; 47: LESENSE Interrupt + DCD CRYPTO1_IRQHandler ; 48: CRYPTO1 Interrupt + DCD TRNG0_IRQHandler ; 49: TRNG0 Interrupt + DCD 0 ; 50: Reserved + +__Vectors_End +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +MemManage_Handler\ + PROC + EXPORT MemManage_Handler [WEAK] + B . + ENDP +BusFault_Handler\ + PROC + EXPORT BusFault_Handler [WEAK] + B . + ENDP +UsageFault_Handler\ + PROC + EXPORT UsageFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +DebugMon_Handler\ + PROC + EXPORT DebugMon_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT EMU_IRQHandler [WEAK] + EXPORT WDOG0_IRQHandler [WEAK] + EXPORT WDOG1_IRQHandler [WEAK] + EXPORT LDMA_IRQHandler [WEAK] + EXPORT GPIO_EVEN_IRQHandler [WEAK] + EXPORT TIMER0_IRQHandler [WEAK] + EXPORT USART0_RX_IRQHandler [WEAK] + EXPORT USART0_TX_IRQHandler [WEAK] + EXPORT ACMP0_IRQHandler [WEAK] + EXPORT ADC0_IRQHandler [WEAK] + EXPORT IDAC0_IRQHandler [WEAK] + EXPORT I2C0_IRQHandler [WEAK] + EXPORT GPIO_ODD_IRQHandler [WEAK] + EXPORT TIMER1_IRQHandler [WEAK] + EXPORT USART1_RX_IRQHandler [WEAK] + EXPORT USART1_TX_IRQHandler [WEAK] + EXPORT LEUART0_IRQHandler [WEAK] + EXPORT PCNT0_IRQHandler [WEAK] + EXPORT CMU_IRQHandler [WEAK] + EXPORT MSC_IRQHandler [WEAK] + EXPORT CRYPTO0_IRQHandler [WEAK] + EXPORT LETIMER0_IRQHandler [WEAK] + EXPORT RTCC_IRQHandler [WEAK] + EXPORT CRYOTIMER_IRQHandler [WEAK] + EXPORT FPUEH_IRQHandler [WEAK] + EXPORT SMU_IRQHandler [WEAK] + EXPORT WTIMER0_IRQHandler [WEAK] + EXPORT WTIMER1_IRQHandler [WEAK] + EXPORT PCNT1_IRQHandler [WEAK] + EXPORT PCNT2_IRQHandler [WEAK] + EXPORT USART2_RX_IRQHandler [WEAK] + EXPORT USART2_TX_IRQHandler [WEAK] + EXPORT I2C1_IRQHandler [WEAK] + EXPORT USART3_RX_IRQHandler [WEAK] + EXPORT USART3_TX_IRQHandler [WEAK] + EXPORT VDAC0_IRQHandler [WEAK] + EXPORT CSEN_IRQHandler [WEAK] + EXPORT LESENSE_IRQHandler [WEAK] + EXPORT CRYPTO1_IRQHandler [WEAK] + EXPORT TRNG0_IRQHandler [WEAK] + + +EMU_IRQHandler +WDOG0_IRQHandler +WDOG1_IRQHandler +LDMA_IRQHandler +GPIO_EVEN_IRQHandler +TIMER0_IRQHandler +USART0_RX_IRQHandler +USART0_TX_IRQHandler +ACMP0_IRQHandler +ADC0_IRQHandler +IDAC0_IRQHandler +I2C0_IRQHandler +GPIO_ODD_IRQHandler +TIMER1_IRQHandler +USART1_RX_IRQHandler +USART1_TX_IRQHandler +LEUART0_IRQHandler +PCNT0_IRQHandler +CMU_IRQHandler +MSC_IRQHandler +CRYPTO0_IRQHandler +LETIMER0_IRQHandler +RTCC_IRQHandler +CRYOTIMER_IRQHandler +FPUEH_IRQHandler +SMU_IRQHandler +WTIMER0_IRQHandler +WTIMER1_IRQHandler +PCNT1_IRQHandler +PCNT2_IRQHandler +USART2_RX_IRQHandler +USART2_TX_IRQHandler +I2C1_IRQHandler +USART3_RX_IRQHandler +USART3_TX_IRQHandler +VDAC0_IRQHandler +CSEN_IRQHandler +LESENSE_IRQHandler +CRYPTO1_IRQHandler +TRNG0_IRQHandler + B . + ENDP + + ALIGN + +; User Initial Stack & Heap + + IMPORT __use_two_region_memory + EXPORT __user_initial_stackheap + +__user_initial_stackheap PROC + LDR R0, = Heap_Mem + LDR R1, =(Stack_Mem + Stack_Size) + LDR R2, = (Heap_Mem + Heap_Size) + LDR R3, = Stack_Mem + BX LR + ENDP + + ALIGN + + END
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_ARM_STD/startup_efm32pg12b.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,306 +0,0 @@ -;/**************************************************************************//** -; * @file startup_efm32pg12b.s -; * @brief CMSIS Core Device Startup File for -; * Silicon Labs EFM32PG12B Device Series -; * @version 5.1.2 -; * @date 03. February 2012 -; * -; * @note -; * Copyright (C) 2012 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ -;/* -;//-------- <<< Use Configuration Wizard in Context Menu >>> ------------------ -;*/ - -; <h> Stack Configuration -; <o> Stack Size (in Bytes) <0x0-0xFFFFFFFF:8> -; </h> - IF :DEF: __STACK_SIZE -Stack_Size EQU __STACK_SIZE - ELSE -Stack_Size EQU 0x00001000 - ENDIF - - AREA STACK, NOINIT, READWRITE, ALIGN=3 -Stack_Mem SPACE Stack_Size -__initial_sp - - -; <h> Heap Configuration -; <o> Heap Size (in Bytes) <0x0-0xFFFFFFFF:8> -; </h> - IF :DEF: __HEAP_SIZE -Heap_Size EQU __HEAP_SIZE - ELSE -Heap_Size EQU 0x00004000 - ENDIF - - AREA HEAP, NOINIT, READWRITE, ALIGN=3 -__heap_base -Heap_Mem SPACE Heap_Size -__heap_limit - - - PRESERVE8 - THUMB - - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY, ALIGN=8 - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD MemManage_Handler ; MPU Fault Handler - DCD BusFault_Handler ; Bus Fault Handler - DCD UsageFault_Handler ; Usage Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD DebugMon_Handler ; Debug Monitor Handler - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; External Interrupts - - DCD EMU_IRQHandler ; 0: EMU Interrupt - DCD 0 ; 1: Reserved - DCD WDOG0_IRQHandler ; 2: WDOG0 Interrupt - DCD WDOG1_IRQHandler ; 3: WDOG1 Interrupt - DCD 0 ; 4: Reserved - DCD 0 ; 5: Reserved - DCD 0 ; 6: Reserved - DCD 0 ; 7: Reserved - DCD 0 ; 8: Reserved - DCD LDMA_IRQHandler ; 9: LDMA Interrupt - DCD GPIO_EVEN_IRQHandler ; 10: GPIO_EVEN Interrupt - DCD TIMER0_IRQHandler ; 11: TIMER0 Interrupt - DCD USART0_RX_IRQHandler ; 12: USART0_RX Interrupt - DCD USART0_TX_IRQHandler ; 13: USART0_TX Interrupt - DCD ACMP0_IRQHandler ; 14: ACMP0 Interrupt - DCD ADC0_IRQHandler ; 15: ADC0 Interrupt - DCD IDAC0_IRQHandler ; 16: IDAC0 Interrupt - DCD I2C0_IRQHandler ; 17: I2C0 Interrupt - DCD GPIO_ODD_IRQHandler ; 18: GPIO_ODD Interrupt - DCD TIMER1_IRQHandler ; 19: TIMER1 Interrupt - DCD USART1_RX_IRQHandler ; 20: USART1_RX Interrupt - DCD USART1_TX_IRQHandler ; 21: USART1_TX Interrupt - DCD LEUART0_IRQHandler ; 22: LEUART0 Interrupt - DCD PCNT0_IRQHandler ; 23: PCNT0 Interrupt - DCD CMU_IRQHandler ; 24: CMU Interrupt - DCD MSC_IRQHandler ; 25: MSC Interrupt - DCD CRYPTO0_IRQHandler ; 26: CRYPTO0 Interrupt - DCD LETIMER0_IRQHandler ; 27: LETIMER0 Interrupt - DCD 0 ; 28: Reserved - DCD 0 ; 29: Reserved - DCD RTCC_IRQHandler ; 30: RTCC Interrupt - DCD 0 ; 31: Reserved - DCD CRYOTIMER_IRQHandler ; 32: CRYOTIMER Interrupt - DCD 0 ; 33: Reserved - DCD FPUEH_IRQHandler ; 34: FPUEH Interrupt - DCD SMU_IRQHandler ; 35: SMU Interrupt - DCD WTIMER0_IRQHandler ; 36: WTIMER0 Interrupt - DCD WTIMER1_IRQHandler ; 37: WTIMER1 Interrupt - DCD PCNT1_IRQHandler ; 38: PCNT1 Interrupt - DCD PCNT2_IRQHandler ; 39: PCNT2 Interrupt - DCD USART2_RX_IRQHandler ; 40: USART2_RX Interrupt - DCD USART2_TX_IRQHandler ; 41: USART2_TX Interrupt - DCD I2C1_IRQHandler ; 42: I2C1 Interrupt - DCD USART3_RX_IRQHandler ; 43: USART3_RX Interrupt - DCD USART3_TX_IRQHandler ; 44: USART3_TX Interrupt - DCD VDAC0_IRQHandler ; 45: VDAC0 Interrupt - DCD CSEN_IRQHandler ; 46: CSEN Interrupt - DCD LESENSE_IRQHandler ; 47: LESENSE Interrupt - DCD CRYPTO1_IRQHandler ; 48: CRYPTO1 Interrupt - DCD TRNG0_IRQHandler ; 49: TRNG0 Interrupt - DCD 0 ; 50: Reserved - -__Vectors_End -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -MemManage_Handler\ - PROC - EXPORT MemManage_Handler [WEAK] - B . - ENDP -BusFault_Handler\ - PROC - EXPORT BusFault_Handler [WEAK] - B . - ENDP -UsageFault_Handler\ - PROC - EXPORT UsageFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -DebugMon_Handler\ - PROC - EXPORT DebugMon_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT EMU_IRQHandler [WEAK] - EXPORT WDOG0_IRQHandler [WEAK] - EXPORT WDOG1_IRQHandler [WEAK] - EXPORT LDMA_IRQHandler [WEAK] - EXPORT GPIO_EVEN_IRQHandler [WEAK] - EXPORT TIMER0_IRQHandler [WEAK] - EXPORT USART0_RX_IRQHandler [WEAK] - EXPORT USART0_TX_IRQHandler [WEAK] - EXPORT ACMP0_IRQHandler [WEAK] - EXPORT ADC0_IRQHandler [WEAK] - EXPORT IDAC0_IRQHandler [WEAK] - EXPORT I2C0_IRQHandler [WEAK] - EXPORT GPIO_ODD_IRQHandler [WEAK] - EXPORT TIMER1_IRQHandler [WEAK] - EXPORT USART1_RX_IRQHandler [WEAK] - EXPORT USART1_TX_IRQHandler [WEAK] - EXPORT LEUART0_IRQHandler [WEAK] - EXPORT PCNT0_IRQHandler [WEAK] - EXPORT CMU_IRQHandler [WEAK] - EXPORT MSC_IRQHandler [WEAK] - EXPORT CRYPTO0_IRQHandler [WEAK] - EXPORT LETIMER0_IRQHandler [WEAK] - EXPORT RTCC_IRQHandler [WEAK] - EXPORT CRYOTIMER_IRQHandler [WEAK] - EXPORT FPUEH_IRQHandler [WEAK] - EXPORT SMU_IRQHandler [WEAK] - EXPORT WTIMER0_IRQHandler [WEAK] - EXPORT WTIMER1_IRQHandler [WEAK] - EXPORT PCNT1_IRQHandler [WEAK] - EXPORT PCNT2_IRQHandler [WEAK] - EXPORT USART2_RX_IRQHandler [WEAK] - EXPORT USART2_TX_IRQHandler [WEAK] - EXPORT I2C1_IRQHandler [WEAK] - EXPORT USART3_RX_IRQHandler [WEAK] - EXPORT USART3_TX_IRQHandler [WEAK] - EXPORT VDAC0_IRQHandler [WEAK] - EXPORT CSEN_IRQHandler [WEAK] - EXPORT LESENSE_IRQHandler [WEAK] - EXPORT CRYPTO1_IRQHandler [WEAK] - EXPORT TRNG0_IRQHandler [WEAK] - - -EMU_IRQHandler -WDOG0_IRQHandler -WDOG1_IRQHandler -LDMA_IRQHandler -GPIO_EVEN_IRQHandler -TIMER0_IRQHandler -USART0_RX_IRQHandler -USART0_TX_IRQHandler -ACMP0_IRQHandler -ADC0_IRQHandler -IDAC0_IRQHandler -I2C0_IRQHandler -GPIO_ODD_IRQHandler -TIMER1_IRQHandler -USART1_RX_IRQHandler -USART1_TX_IRQHandler -LEUART0_IRQHandler -PCNT0_IRQHandler -CMU_IRQHandler -MSC_IRQHandler -CRYPTO0_IRQHandler -LETIMER0_IRQHandler -RTCC_IRQHandler -CRYOTIMER_IRQHandler -FPUEH_IRQHandler -SMU_IRQHandler -WTIMER0_IRQHandler -WTIMER1_IRQHandler -PCNT1_IRQHandler -PCNT2_IRQHandler -USART2_RX_IRQHandler -USART2_TX_IRQHandler -I2C1_IRQHandler -USART3_RX_IRQHandler -USART3_TX_IRQHandler -VDAC0_IRQHandler -CSEN_IRQHandler -LESENSE_IRQHandler -CRYPTO1_IRQHandler -TRNG0_IRQHandler - B . - ENDP - - ALIGN - -; User Initial Stack & Heap - - IMPORT __use_two_region_memory - EXPORT __user_initial_stackheap - -__user_initial_stackheap PROC - LDR R0, = Heap_Mem - LDR R1, =(Stack_Mem + Stack_Size) - LDR R2, = (Heap_Mem + Heap_Size) - LDR R3, = Stack_Mem - BX LR - ENDP - - ALIGN - - END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_IAR/startup_efm32pg12b.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,401 @@ +;/**************************************************************************//** +; * @file startup_efm32pg12b.s +; * @brief CMSIS Core Device Startup File +; * Silicon Labs EFM32PG12B Device Series +; * @version 5.1.2 +; * @date 30. January 2012 +; * +; * @note +; * Copyright (C) 2012 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; +; When debugging in RAM, it can be located in RAM with at least a 128 byte +; alignment, 256 byte alignment is requied if all interrupt vectors are in use. +; +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(8) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + + DCD EMU_IRQHandler ; 0: EMU Interrupt + DCD 0 ; 1: Reserved Interrupt + DCD WDOG0_IRQHandler ; 2: WDOG0 Interrupt + DCD WDOG1_IRQHandler ; 3: WDOG1 Interrupt + DCD 0 ; 4: Reserved Interrupt + DCD 0 ; 5: Reserved Interrupt + DCD 0 ; 6: Reserved Interrupt + DCD 0 ; 7: Reserved Interrupt + DCD 0 ; 8: Reserved Interrupt + DCD LDMA_IRQHandler ; 9: LDMA Interrupt + DCD GPIO_EVEN_IRQHandler ; 10: GPIO_EVEN Interrupt + DCD TIMER0_IRQHandler ; 11: TIMER0 Interrupt + DCD USART0_RX_IRQHandler ; 12: USART0_RX Interrupt + DCD USART0_TX_IRQHandler ; 13: USART0_TX Interrupt + DCD ACMP0_IRQHandler ; 14: ACMP0 Interrupt + DCD ADC0_IRQHandler ; 15: ADC0 Interrupt + DCD IDAC0_IRQHandler ; 16: IDAC0 Interrupt + DCD I2C0_IRQHandler ; 17: I2C0 Interrupt + DCD GPIO_ODD_IRQHandler ; 18: GPIO_ODD Interrupt + DCD TIMER1_IRQHandler ; 19: TIMER1 Interrupt + DCD USART1_RX_IRQHandler ; 20: USART1_RX Interrupt + DCD USART1_TX_IRQHandler ; 21: USART1_TX Interrupt + DCD LEUART0_IRQHandler ; 22: LEUART0 Interrupt + DCD PCNT0_IRQHandler ; 23: PCNT0 Interrupt + DCD CMU_IRQHandler ; 24: CMU Interrupt + DCD MSC_IRQHandler ; 25: MSC Interrupt + DCD CRYPTO0_IRQHandler ; 26: CRYPTO0 Interrupt + DCD LETIMER0_IRQHandler ; 27: LETIMER0 Interrupt + DCD 0 ; 28: Reserved Interrupt + DCD 0 ; 29: Reserved Interrupt + DCD RTCC_IRQHandler ; 30: RTCC Interrupt + DCD 0 ; 31: Reserved Interrupt + DCD CRYOTIMER_IRQHandler ; 32: CRYOTIMER Interrupt + DCD 0 ; 33: Reserved Interrupt + DCD FPUEH_IRQHandler ; 34: FPUEH Interrupt + DCD SMU_IRQHandler ; 35: SMU Interrupt + DCD WTIMER0_IRQHandler ; 36: WTIMER0 Interrupt + DCD WTIMER1_IRQHandler ; 37: WTIMER1 Interrupt + DCD PCNT1_IRQHandler ; 38: PCNT1 Interrupt + DCD PCNT2_IRQHandler ; 39: PCNT2 Interrupt + DCD USART2_RX_IRQHandler ; 40: USART2_RX Interrupt + DCD USART2_TX_IRQHandler ; 41: USART2_TX Interrupt + DCD I2C1_IRQHandler ; 42: I2C1 Interrupt + DCD USART3_RX_IRQHandler ; 43: USART3_RX Interrupt + DCD USART3_TX_IRQHandler ; 44: USART3_TX Interrupt + DCD VDAC0_IRQHandler ; 45: VDAC0 Interrupt + DCD CSEN_IRQHandler ; 46: CSEN Interrupt + DCD LESENSE_IRQHandler ; 47: LESENSE Interrupt + DCD CRYPTO1_IRQHandler ; 48: CRYPTO1 Interrupt + DCD TRNG0_IRQHandler ; 49: TRNG0 Interrupt + DCD 0 ; 50: Reserved Interrupt + +__Vectors_End +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + ; Device specific interrupt handlers + + PUBWEAK EMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EMU_IRQHandler + B EMU_IRQHandler + + PUBWEAK WDOG0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDOG0_IRQHandler + B WDOG0_IRQHandler + + PUBWEAK WDOG1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDOG1_IRQHandler + B WDOG1_IRQHandler + + PUBWEAK LDMA_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LDMA_IRQHandler + B LDMA_IRQHandler + + PUBWEAK GPIO_EVEN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_EVEN_IRQHandler + B GPIO_EVEN_IRQHandler + + PUBWEAK TIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER0_IRQHandler + B TIMER0_IRQHandler + + PUBWEAK USART0_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART0_RX_IRQHandler + B USART0_RX_IRQHandler + + PUBWEAK USART0_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART0_TX_IRQHandler + B USART0_TX_IRQHandler + + PUBWEAK ACMP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ACMP0_IRQHandler + B ACMP0_IRQHandler + + PUBWEAK ADC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC0_IRQHandler + B ADC0_IRQHandler + + PUBWEAK IDAC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +IDAC0_IRQHandler + B IDAC0_IRQHandler + + PUBWEAK I2C0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C0_IRQHandler + B I2C0_IRQHandler + + PUBWEAK GPIO_ODD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_ODD_IRQHandler + B GPIO_ODD_IRQHandler + + PUBWEAK TIMER1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER1_IRQHandler + B TIMER1_IRQHandler + + PUBWEAK USART1_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_RX_IRQHandler + B USART1_RX_IRQHandler + + PUBWEAK USART1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_TX_IRQHandler + B USART1_TX_IRQHandler + + PUBWEAK LEUART0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LEUART0_IRQHandler + B LEUART0_IRQHandler + + PUBWEAK PCNT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PCNT0_IRQHandler + B PCNT0_IRQHandler + + PUBWEAK CMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CMU_IRQHandler + B CMU_IRQHandler + + PUBWEAK MSC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MSC_IRQHandler + B MSC_IRQHandler + + PUBWEAK CRYPTO0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CRYPTO0_IRQHandler + B CRYPTO0_IRQHandler + + PUBWEAK LETIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LETIMER0_IRQHandler + B LETIMER0_IRQHandler + + PUBWEAK RTCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTCC_IRQHandler + B RTCC_IRQHandler + + PUBWEAK CRYOTIMER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CRYOTIMER_IRQHandler + B CRYOTIMER_IRQHandler + + PUBWEAK FPUEH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FPUEH_IRQHandler + B FPUEH_IRQHandler + + PUBWEAK SMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SMU_IRQHandler + B SMU_IRQHandler + + PUBWEAK WTIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WTIMER0_IRQHandler + B WTIMER0_IRQHandler + + PUBWEAK WTIMER1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WTIMER1_IRQHandler + B WTIMER1_IRQHandler + + PUBWEAK PCNT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PCNT1_IRQHandler + B PCNT1_IRQHandler + + PUBWEAK PCNT2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PCNT2_IRQHandler + B PCNT2_IRQHandler + + PUBWEAK USART2_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_RX_IRQHandler + B USART2_RX_IRQHandler + + PUBWEAK USART2_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_TX_IRQHandler + B USART2_TX_IRQHandler + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + PUBWEAK USART3_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_RX_IRQHandler + B USART3_RX_IRQHandler + + PUBWEAK USART3_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_TX_IRQHandler + B USART3_TX_IRQHandler + + PUBWEAK VDAC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VDAC0_IRQHandler + B VDAC0_IRQHandler + + PUBWEAK CSEN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CSEN_IRQHandler + B CSEN_IRQHandler + + PUBWEAK LESENSE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LESENSE_IRQHandler + B LESENSE_IRQHandler + + PUBWEAK CRYPTO1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CRYPTO1_IRQHandler + B CRYPTO1_IRQHandler + + PUBWEAK TRNG0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TRNG0_IRQHandler + B TRNG0_IRQHandler + + + END
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32PG12/device/TOOLCHAIN_IAR/startup_efm32pg12b.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,401 +0,0 @@ -;/**************************************************************************//** -; * @file startup_efm32pg12b.s -; * @brief CMSIS Core Device Startup File -; * Silicon Labs EFM32PG12B Device Series -; * @version 5.1.2 -; * @date 30. January 2012 -; * -; * @note -; * Copyright (C) 2012 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; -; When debugging in RAM, it can be located in RAM with at least a 128 byte -; alignment, 256 byte alignment is requied if all interrupt vectors are in use. -; -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(8) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler - DCD HardFault_Handler - DCD MemManage_Handler - DCD BusFault_Handler - DCD UsageFault_Handler -__vector_table_0x1c - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD SVC_Handler - DCD DebugMon_Handler - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - - DCD EMU_IRQHandler ; 0: EMU Interrupt - DCD 0 ; 1: Reserved Interrupt - DCD WDOG0_IRQHandler ; 2: WDOG0 Interrupt - DCD WDOG1_IRQHandler ; 3: WDOG1 Interrupt - DCD 0 ; 4: Reserved Interrupt - DCD 0 ; 5: Reserved Interrupt - DCD 0 ; 6: Reserved Interrupt - DCD 0 ; 7: Reserved Interrupt - DCD 0 ; 8: Reserved Interrupt - DCD LDMA_IRQHandler ; 9: LDMA Interrupt - DCD GPIO_EVEN_IRQHandler ; 10: GPIO_EVEN Interrupt - DCD TIMER0_IRQHandler ; 11: TIMER0 Interrupt - DCD USART0_RX_IRQHandler ; 12: USART0_RX Interrupt - DCD USART0_TX_IRQHandler ; 13: USART0_TX Interrupt - DCD ACMP0_IRQHandler ; 14: ACMP0 Interrupt - DCD ADC0_IRQHandler ; 15: ADC0 Interrupt - DCD IDAC0_IRQHandler ; 16: IDAC0 Interrupt - DCD I2C0_IRQHandler ; 17: I2C0 Interrupt - DCD GPIO_ODD_IRQHandler ; 18: GPIO_ODD Interrupt - DCD TIMER1_IRQHandler ; 19: TIMER1 Interrupt - DCD USART1_RX_IRQHandler ; 20: USART1_RX Interrupt - DCD USART1_TX_IRQHandler ; 21: USART1_TX Interrupt - DCD LEUART0_IRQHandler ; 22: LEUART0 Interrupt - DCD PCNT0_IRQHandler ; 23: PCNT0 Interrupt - DCD CMU_IRQHandler ; 24: CMU Interrupt - DCD MSC_IRQHandler ; 25: MSC Interrupt - DCD CRYPTO0_IRQHandler ; 26: CRYPTO0 Interrupt - DCD LETIMER0_IRQHandler ; 27: LETIMER0 Interrupt - DCD 0 ; 28: Reserved Interrupt - DCD 0 ; 29: Reserved Interrupt - DCD RTCC_IRQHandler ; 30: RTCC Interrupt - DCD 0 ; 31: Reserved Interrupt - DCD CRYOTIMER_IRQHandler ; 32: CRYOTIMER Interrupt - DCD 0 ; 33: Reserved Interrupt - DCD FPUEH_IRQHandler ; 34: FPUEH Interrupt - DCD SMU_IRQHandler ; 35: SMU Interrupt - DCD WTIMER0_IRQHandler ; 36: WTIMER0 Interrupt - DCD WTIMER1_IRQHandler ; 37: WTIMER1 Interrupt - DCD PCNT1_IRQHandler ; 38: PCNT1 Interrupt - DCD PCNT2_IRQHandler ; 39: PCNT2 Interrupt - DCD USART2_RX_IRQHandler ; 40: USART2_RX Interrupt - DCD USART2_TX_IRQHandler ; 41: USART2_TX Interrupt - DCD I2C1_IRQHandler ; 42: I2C1 Interrupt - DCD USART3_RX_IRQHandler ; 43: USART3_RX Interrupt - DCD USART3_TX_IRQHandler ; 44: USART3_TX Interrupt - DCD VDAC0_IRQHandler ; 45: VDAC0 Interrupt - DCD CSEN_IRQHandler ; 46: CSEN Interrupt - DCD LESENSE_IRQHandler ; 47: LESENSE Interrupt - DCD CRYPTO1_IRQHandler ; 48: CRYPTO1 Interrupt - DCD TRNG0_IRQHandler ; 49: TRNG0 Interrupt - DCD 0 ; 50: Reserved Interrupt - -__Vectors_End -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - ; Device specific interrupt handlers - - PUBWEAK EMU_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EMU_IRQHandler - B EMU_IRQHandler - - PUBWEAK WDOG0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -WDOG0_IRQHandler - B WDOG0_IRQHandler - - PUBWEAK WDOG1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -WDOG1_IRQHandler - B WDOG1_IRQHandler - - PUBWEAK LDMA_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LDMA_IRQHandler - B LDMA_IRQHandler - - PUBWEAK GPIO_EVEN_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO_EVEN_IRQHandler - B GPIO_EVEN_IRQHandler - - PUBWEAK TIMER0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER0_IRQHandler - B TIMER0_IRQHandler - - PUBWEAK USART0_RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART0_RX_IRQHandler - B USART0_RX_IRQHandler - - PUBWEAK USART0_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART0_TX_IRQHandler - B USART0_TX_IRQHandler - - PUBWEAK ACMP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ACMP0_IRQHandler - B ACMP0_IRQHandler - - PUBWEAK ADC0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ADC0_IRQHandler - B ADC0_IRQHandler - - PUBWEAK IDAC0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -IDAC0_IRQHandler - B IDAC0_IRQHandler - - PUBWEAK I2C0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C0_IRQHandler - B I2C0_IRQHandler - - PUBWEAK GPIO_ODD_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO_ODD_IRQHandler - B GPIO_ODD_IRQHandler - - PUBWEAK TIMER1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER1_IRQHandler - B TIMER1_IRQHandler - - PUBWEAK USART1_RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART1_RX_IRQHandler - B USART1_RX_IRQHandler - - PUBWEAK USART1_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART1_TX_IRQHandler - B USART1_TX_IRQHandler - - PUBWEAK LEUART0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LEUART0_IRQHandler - B LEUART0_IRQHandler - - PUBWEAK PCNT0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PCNT0_IRQHandler - B PCNT0_IRQHandler - - PUBWEAK CMU_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CMU_IRQHandler - B CMU_IRQHandler - - PUBWEAK MSC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -MSC_IRQHandler - B MSC_IRQHandler - - PUBWEAK CRYPTO0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CRYPTO0_IRQHandler - B CRYPTO0_IRQHandler - - PUBWEAK LETIMER0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LETIMER0_IRQHandler - B LETIMER0_IRQHandler - - PUBWEAK RTCC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTCC_IRQHandler - B RTCC_IRQHandler - - PUBWEAK CRYOTIMER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CRYOTIMER_IRQHandler - B CRYOTIMER_IRQHandler - - PUBWEAK FPUEH_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FPUEH_IRQHandler - B FPUEH_IRQHandler - - PUBWEAK SMU_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SMU_IRQHandler - B SMU_IRQHandler - - PUBWEAK WTIMER0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -WTIMER0_IRQHandler - B WTIMER0_IRQHandler - - PUBWEAK WTIMER1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -WTIMER1_IRQHandler - B WTIMER1_IRQHandler - - PUBWEAK PCNT1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PCNT1_IRQHandler - B PCNT1_IRQHandler - - PUBWEAK PCNT2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PCNT2_IRQHandler - B PCNT2_IRQHandler - - PUBWEAK USART2_RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART2_RX_IRQHandler - B USART2_RX_IRQHandler - - PUBWEAK USART2_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART2_TX_IRQHandler - B USART2_TX_IRQHandler - - PUBWEAK I2C1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C1_IRQHandler - B I2C1_IRQHandler - - PUBWEAK USART3_RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART3_RX_IRQHandler - B USART3_RX_IRQHandler - - PUBWEAK USART3_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART3_TX_IRQHandler - B USART3_TX_IRQHandler - - PUBWEAK VDAC0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -VDAC0_IRQHandler - B VDAC0_IRQHandler - - PUBWEAK CSEN_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CSEN_IRQHandler - B CSEN_IRQHandler - - PUBWEAK LESENSE_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LESENSE_IRQHandler - B LESENSE_IRQHandler - - PUBWEAK CRYPTO1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CRYPTO1_IRQHandler - B CRYPTO1_IRQHandler - - PUBWEAK TRNG0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TRNG0_IRQHandler - B TRNG0_IRQHandler - - - END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/TARGET_256K/TOOLCHAIN_IAR/startup_efm32wg.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,391 @@ +;/**************************************************************************//** +; * @file startup_efm32wg.s +; * @brief CMSIS Core Device Startup File +; * Silicon Labs EFM32WG Device Series +; * @version 5.0.0 +; * @date 30. January 2012 +; * +; * @note +; * Copyright (C) 2012 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; +; When debugging in RAM, it can be located in RAM with at least a 128 byte +; alignment, 256 byte alignment is requied if all interrupt vectors are in use. +; +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(8) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + + DCD DMA_IRQHandler ; 0: DMA Interrupt + DCD GPIO_EVEN_IRQHandler ; 1: GPIO_EVEN Interrupt + DCD TIMER0_IRQHandler ; 2: TIMER0 Interrupt + DCD USART0_RX_IRQHandler ; 3: USART0_RX Interrupt + DCD USART0_TX_IRQHandler ; 4: USART0_TX Interrupt + DCD USB_IRQHandler ; 5: USB Interrupt + DCD ACMP0_IRQHandler ; 6: ACMP0 Interrupt + DCD ADC0_IRQHandler ; 7: ADC0 Interrupt + DCD DAC0_IRQHandler ; 8: DAC0 Interrupt + DCD I2C0_IRQHandler ; 9: I2C0 Interrupt + DCD I2C1_IRQHandler ; 10: I2C1 Interrupt + DCD GPIO_ODD_IRQHandler ; 11: GPIO_ODD Interrupt + DCD TIMER1_IRQHandler ; 12: TIMER1 Interrupt + DCD TIMER2_IRQHandler ; 13: TIMER2 Interrupt + DCD TIMER3_IRQHandler ; 14: TIMER3 Interrupt + DCD USART1_RX_IRQHandler ; 15: USART1_RX Interrupt + DCD USART1_TX_IRQHandler ; 16: USART1_TX Interrupt + DCD LESENSE_IRQHandler ; 17: LESENSE Interrupt + DCD USART2_RX_IRQHandler ; 18: USART2_RX Interrupt + DCD USART2_TX_IRQHandler ; 19: USART2_TX Interrupt + DCD UART0_RX_IRQHandler ; 20: UART0_RX Interrupt + DCD UART0_TX_IRQHandler ; 21: UART0_TX Interrupt + DCD UART1_RX_IRQHandler ; 22: UART1_RX Interrupt + DCD UART1_TX_IRQHandler ; 23: UART1_TX Interrupt + DCD LEUART0_IRQHandler ; 24: LEUART0 Interrupt + DCD LEUART1_IRQHandler ; 25: LEUART1 Interrupt + DCD LETIMER0_IRQHandler ; 26: LETIMER0 Interrupt + DCD PCNT0_IRQHandler ; 27: PCNT0 Interrupt + DCD PCNT1_IRQHandler ; 28: PCNT1 Interrupt + DCD PCNT2_IRQHandler ; 29: PCNT2 Interrupt + DCD RTC_IRQHandler ; 30: RTC Interrupt + DCD BURTC_IRQHandler ; 31: BURTC Interrupt + DCD CMU_IRQHandler ; 32: CMU Interrupt + DCD VCMP_IRQHandler ; 33: VCMP Interrupt + DCD LCD_IRQHandler ; 34: LCD Interrupt + DCD MSC_IRQHandler ; 35: MSC Interrupt + DCD AES_IRQHandler ; 36: AES Interrupt + DCD EBI_IRQHandler ; 37: EBI Interrupt + DCD EMU_IRQHandler ; 38: EMU Interrupt + DCD FPUEH_IRQHandler ; 39: FPUEH Interrupt + + +__Vectors_End +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + ; Device specific interrupt handlers + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA_IRQHandler + B DMA_IRQHandler + + PUBWEAK GPIO_EVEN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_EVEN_IRQHandler + B GPIO_EVEN_IRQHandler + + PUBWEAK TIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER0_IRQHandler + B TIMER0_IRQHandler + + PUBWEAK USART0_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART0_RX_IRQHandler + B USART0_RX_IRQHandler + + PUBWEAK USART0_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART0_TX_IRQHandler + B USART0_TX_IRQHandler + + PUBWEAK USB_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USB_IRQHandler + B USB_IRQHandler + + PUBWEAK ACMP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ACMP0_IRQHandler + B ACMP0_IRQHandler + + PUBWEAK ADC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC0_IRQHandler + B ADC0_IRQHandler + + PUBWEAK DAC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DAC0_IRQHandler + B DAC0_IRQHandler + + PUBWEAK I2C0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C0_IRQHandler + B I2C0_IRQHandler + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + PUBWEAK GPIO_ODD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_ODD_IRQHandler + B GPIO_ODD_IRQHandler + + PUBWEAK TIMER1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER1_IRQHandler + B TIMER1_IRQHandler + + PUBWEAK TIMER2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER2_IRQHandler + B TIMER2_IRQHandler + + PUBWEAK TIMER3_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER3_IRQHandler + B TIMER3_IRQHandler + + PUBWEAK USART1_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_RX_IRQHandler + B USART1_RX_IRQHandler + + PUBWEAK USART1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_TX_IRQHandler + B USART1_TX_IRQHandler + + PUBWEAK LESENSE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LESENSE_IRQHandler + B LESENSE_IRQHandler + + PUBWEAK USART2_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_RX_IRQHandler + B USART2_RX_IRQHandler + + PUBWEAK USART2_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_TX_IRQHandler + B USART2_TX_IRQHandler + + PUBWEAK UART0_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART0_RX_IRQHandler + B UART0_RX_IRQHandler + + PUBWEAK UART0_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART0_TX_IRQHandler + B UART0_TX_IRQHandler + + PUBWEAK UART1_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART1_RX_IRQHandler + B UART1_RX_IRQHandler + + PUBWEAK UART1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +UART1_TX_IRQHandler + B UART1_TX_IRQHandler + + PUBWEAK LEUART0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LEUART0_IRQHandler + B LEUART0_IRQHandler + + PUBWEAK LEUART1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LEUART1_IRQHandler + B LEUART1_IRQHandler + + PUBWEAK LETIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LETIMER0_IRQHandler + B LETIMER0_IRQHandler + + PUBWEAK PCNT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PCNT0_IRQHandler + B PCNT0_IRQHandler + + PUBWEAK PCNT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PCNT1_IRQHandler + B PCNT1_IRQHandler + + PUBWEAK PCNT2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PCNT2_IRQHandler + B PCNT2_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK BURTC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +BURTC_IRQHandler + B BURTC_IRQHandler + + PUBWEAK CMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CMU_IRQHandler + B CMU_IRQHandler + + PUBWEAK VCMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VCMP_IRQHandler + B VCMP_IRQHandler + + PUBWEAK LCD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LCD_IRQHandler + B LCD_IRQHandler + + PUBWEAK MSC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MSC_IRQHandler + B MSC_IRQHandler + + PUBWEAK AES_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +AES_IRQHandler + B AES_IRQHandler + + PUBWEAK EBI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EBI_IRQHandler + B EBI_IRQHandler + + PUBWEAK EMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EMU_IRQHandler + B EMU_IRQHandler + + PUBWEAK FPUEH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FPUEH_IRQHandler + B FPUEH_IRQHandler + + + END
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32WG/device/TARGET_256K/TOOLCHAIN_IAR/startup_efm32wg.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,391 +0,0 @@ -;/**************************************************************************//** -; * @file startup_efm32wg.s -; * @brief CMSIS Core Device Startup File -; * Silicon Labs EFM32WG Device Series -; * @version 5.0.0 -; * @date 30. January 2012 -; * -; * @note -; * Copyright (C) 2012 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; -; When debugging in RAM, it can be located in RAM with at least a 128 byte -; alignment, 256 byte alignment is requied if all interrupt vectors are in use. -; -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(8) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler - DCD HardFault_Handler - DCD MemManage_Handler - DCD BusFault_Handler - DCD UsageFault_Handler -__vector_table_0x1c - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD SVC_Handler - DCD DebugMon_Handler - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - - DCD DMA_IRQHandler ; 0: DMA Interrupt - DCD GPIO_EVEN_IRQHandler ; 1: GPIO_EVEN Interrupt - DCD TIMER0_IRQHandler ; 2: TIMER0 Interrupt - DCD USART0_RX_IRQHandler ; 3: USART0_RX Interrupt - DCD USART0_TX_IRQHandler ; 4: USART0_TX Interrupt - DCD USB_IRQHandler ; 5: USB Interrupt - DCD ACMP0_IRQHandler ; 6: ACMP0 Interrupt - DCD ADC0_IRQHandler ; 7: ADC0 Interrupt - DCD DAC0_IRQHandler ; 8: DAC0 Interrupt - DCD I2C0_IRQHandler ; 9: I2C0 Interrupt - DCD I2C1_IRQHandler ; 10: I2C1 Interrupt - DCD GPIO_ODD_IRQHandler ; 11: GPIO_ODD Interrupt - DCD TIMER1_IRQHandler ; 12: TIMER1 Interrupt - DCD TIMER2_IRQHandler ; 13: TIMER2 Interrupt - DCD TIMER3_IRQHandler ; 14: TIMER3 Interrupt - DCD USART1_RX_IRQHandler ; 15: USART1_RX Interrupt - DCD USART1_TX_IRQHandler ; 16: USART1_TX Interrupt - DCD LESENSE_IRQHandler ; 17: LESENSE Interrupt - DCD USART2_RX_IRQHandler ; 18: USART2_RX Interrupt - DCD USART2_TX_IRQHandler ; 19: USART2_TX Interrupt - DCD UART0_RX_IRQHandler ; 20: UART0_RX Interrupt - DCD UART0_TX_IRQHandler ; 21: UART0_TX Interrupt - DCD UART1_RX_IRQHandler ; 22: UART1_RX Interrupt - DCD UART1_TX_IRQHandler ; 23: UART1_TX Interrupt - DCD LEUART0_IRQHandler ; 24: LEUART0 Interrupt - DCD LEUART1_IRQHandler ; 25: LEUART1 Interrupt - DCD LETIMER0_IRQHandler ; 26: LETIMER0 Interrupt - DCD PCNT0_IRQHandler ; 27: PCNT0 Interrupt - DCD PCNT1_IRQHandler ; 28: PCNT1 Interrupt - DCD PCNT2_IRQHandler ; 29: PCNT2 Interrupt - DCD RTC_IRQHandler ; 30: RTC Interrupt - DCD BURTC_IRQHandler ; 31: BURTC Interrupt - DCD CMU_IRQHandler ; 32: CMU Interrupt - DCD VCMP_IRQHandler ; 33: VCMP Interrupt - DCD LCD_IRQHandler ; 34: LCD Interrupt - DCD MSC_IRQHandler ; 35: MSC Interrupt - DCD AES_IRQHandler ; 36: AES Interrupt - DCD EBI_IRQHandler ; 37: EBI Interrupt - DCD EMU_IRQHandler ; 38: EMU Interrupt - DCD FPUEH_IRQHandler ; 39: FPUEH Interrupt - - -__Vectors_End -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - ; Device specific interrupt handlers - - PUBWEAK DMA_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA_IRQHandler - B DMA_IRQHandler - - PUBWEAK GPIO_EVEN_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO_EVEN_IRQHandler - B GPIO_EVEN_IRQHandler - - PUBWEAK TIMER0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER0_IRQHandler - B TIMER0_IRQHandler - - PUBWEAK USART0_RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART0_RX_IRQHandler - B USART0_RX_IRQHandler - - PUBWEAK USART0_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART0_TX_IRQHandler - B USART0_TX_IRQHandler - - PUBWEAK USB_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USB_IRQHandler - B USB_IRQHandler - - PUBWEAK ACMP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ACMP0_IRQHandler - B ACMP0_IRQHandler - - PUBWEAK ADC0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ADC0_IRQHandler - B ADC0_IRQHandler - - PUBWEAK DAC0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DAC0_IRQHandler - B DAC0_IRQHandler - - PUBWEAK I2C0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C0_IRQHandler - B I2C0_IRQHandler - - PUBWEAK I2C1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C1_IRQHandler - B I2C1_IRQHandler - - PUBWEAK GPIO_ODD_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO_ODD_IRQHandler - B GPIO_ODD_IRQHandler - - PUBWEAK TIMER1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER1_IRQHandler - B TIMER1_IRQHandler - - PUBWEAK TIMER2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER2_IRQHandler - B TIMER2_IRQHandler - - PUBWEAK TIMER3_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER3_IRQHandler - B TIMER3_IRQHandler - - PUBWEAK USART1_RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART1_RX_IRQHandler - B USART1_RX_IRQHandler - - PUBWEAK USART1_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART1_TX_IRQHandler - B USART1_TX_IRQHandler - - PUBWEAK LESENSE_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LESENSE_IRQHandler - B LESENSE_IRQHandler - - PUBWEAK USART2_RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART2_RX_IRQHandler - B USART2_RX_IRQHandler - - PUBWEAK USART2_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART2_TX_IRQHandler - B USART2_TX_IRQHandler - - PUBWEAK UART0_RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART0_RX_IRQHandler - B UART0_RX_IRQHandler - - PUBWEAK UART0_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART0_TX_IRQHandler - B UART0_TX_IRQHandler - - PUBWEAK UART1_RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART1_RX_IRQHandler - B UART1_RX_IRQHandler - - PUBWEAK UART1_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -UART1_TX_IRQHandler - B UART1_TX_IRQHandler - - PUBWEAK LEUART0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LEUART0_IRQHandler - B LEUART0_IRQHandler - - PUBWEAK LEUART1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LEUART1_IRQHandler - B LEUART1_IRQHandler - - PUBWEAK LETIMER0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LETIMER0_IRQHandler - B LETIMER0_IRQHandler - - PUBWEAK PCNT0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PCNT0_IRQHandler - B PCNT0_IRQHandler - - PUBWEAK PCNT1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PCNT1_IRQHandler - B PCNT1_IRQHandler - - PUBWEAK PCNT2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PCNT2_IRQHandler - B PCNT2_IRQHandler - - PUBWEAK RTC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC_IRQHandler - B RTC_IRQHandler - - PUBWEAK BURTC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -BURTC_IRQHandler - B BURTC_IRQHandler - - PUBWEAK CMU_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CMU_IRQHandler - B CMU_IRQHandler - - PUBWEAK VCMP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -VCMP_IRQHandler - B VCMP_IRQHandler - - PUBWEAK LCD_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LCD_IRQHandler - B LCD_IRQHandler - - PUBWEAK MSC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -MSC_IRQHandler - B MSC_IRQHandler - - PUBWEAK AES_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -AES_IRQHandler - B AES_IRQHandler - - PUBWEAK EBI_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EBI_IRQHandler - B EBI_IRQHandler - - PUBWEAK EMU_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EMU_IRQHandler - B EMU_IRQHandler - - PUBWEAK FPUEH_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FPUEH_IRQHandler - B FPUEH_IRQHandler - - - END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/TARGET_32K/TOOLCHAIN_IAR/startup_efm32zg.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,235 @@ +;/**************************************************************************//** +; * @file startup_efm32zg.s +; * @brief CMSIS Core Device Startup File +; * Silicon Labs EFM32ZG Device Series +; * @version 5.0.0 +; * @date 30. January 2012 +; * +; * @note +; * Copyright (C) 2012 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; +; When debugging in RAM, it can be located in RAM with at least a 128 byte +; alignment, 256 byte alignment is requied if all interrupt vectors are in use. +; +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(8) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD 0 + DCD 0 + DCD 0 +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD 0 + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + + DCD DMA_IRQHandler ; 0: DMA Interrupt + DCD GPIO_EVEN_IRQHandler ; 1: GPIO_EVEN Interrupt + DCD TIMER0_IRQHandler ; 2: TIMER0 Interrupt + DCD ACMP0_IRQHandler ; 3: ACMP0 Interrupt + DCD ADC0_IRQHandler ; 4: ADC0 Interrupt + DCD I2C0_IRQHandler ; 5: I2C0 Interrupt + DCD GPIO_ODD_IRQHandler ; 6: GPIO_ODD Interrupt + DCD TIMER1_IRQHandler ; 7: TIMER1 Interrupt + DCD USART1_RX_IRQHandler ; 8: USART1_RX Interrupt + DCD USART1_TX_IRQHandler ; 9: USART1_TX Interrupt + DCD LEUART0_IRQHandler ; 10: LEUART0 Interrupt + DCD PCNT0_IRQHandler ; 11: PCNT0 Interrupt + DCD RTC_IRQHandler ; 12: RTC Interrupt + DCD CMU_IRQHandler ; 13: CMU Interrupt + DCD VCMP_IRQHandler ; 14: VCMP Interrupt + DCD MSC_IRQHandler ; 15: MSC Interrupt + DCD AES_IRQHandler ; 16: AES Interrupt + DCD 0 ; 17: Reserved Interrupt + DCD 0 ; 18: Reserved Interrupt + + +__Vectors_End +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + ; Device specific interrupt handlers + + PUBWEAK DMA_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA_IRQHandler + B DMA_IRQHandler + + PUBWEAK GPIO_EVEN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_EVEN_IRQHandler + B GPIO_EVEN_IRQHandler + + PUBWEAK TIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER0_IRQHandler + B TIMER0_IRQHandler + + PUBWEAK ACMP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ACMP0_IRQHandler + B ACMP0_IRQHandler + + PUBWEAK ADC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC0_IRQHandler + B ADC0_IRQHandler + + PUBWEAK I2C0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C0_IRQHandler + B I2C0_IRQHandler + + PUBWEAK GPIO_ODD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_ODD_IRQHandler + B GPIO_ODD_IRQHandler + + PUBWEAK TIMER1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER1_IRQHandler + B TIMER1_IRQHandler + + PUBWEAK USART1_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_RX_IRQHandler + B USART1_RX_IRQHandler + + PUBWEAK USART1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_TX_IRQHandler + B USART1_TX_IRQHandler + + PUBWEAK LEUART0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LEUART0_IRQHandler + B LEUART0_IRQHandler + + PUBWEAK PCNT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PCNT0_IRQHandler + B PCNT0_IRQHandler + + PUBWEAK RTC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_IRQHandler + B RTC_IRQHandler + + PUBWEAK CMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CMU_IRQHandler + B CMU_IRQHandler + + PUBWEAK VCMP_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VCMP_IRQHandler + B VCMP_IRQHandler + + PUBWEAK MSC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MSC_IRQHandler + B MSC_IRQHandler + + PUBWEAK AES_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +AES_IRQHandler + B AES_IRQHandler + + + END
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32ZG/device/TARGET_32K/TOOLCHAIN_IAR/startup_efm32zg.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,235 +0,0 @@ -;/**************************************************************************//** -; * @file startup_efm32zg.s -; * @brief CMSIS Core Device Startup File -; * Silicon Labs EFM32ZG Device Series -; * @version 5.0.0 -; * @date 30. January 2012 -; * -; * @note -; * Copyright (C) 2012 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; -; When debugging in RAM, it can be located in RAM with at least a 128 byte -; alignment, 256 byte alignment is requied if all interrupt vectors are in use. -; -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(8) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler - DCD HardFault_Handler - DCD 0 - DCD 0 - DCD 0 -__vector_table_0x1c - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD SVC_Handler - DCD 0 - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - - DCD DMA_IRQHandler ; 0: DMA Interrupt - DCD GPIO_EVEN_IRQHandler ; 1: GPIO_EVEN Interrupt - DCD TIMER0_IRQHandler ; 2: TIMER0 Interrupt - DCD ACMP0_IRQHandler ; 3: ACMP0 Interrupt - DCD ADC0_IRQHandler ; 4: ADC0 Interrupt - DCD I2C0_IRQHandler ; 5: I2C0 Interrupt - DCD GPIO_ODD_IRQHandler ; 6: GPIO_ODD Interrupt - DCD TIMER1_IRQHandler ; 7: TIMER1 Interrupt - DCD USART1_RX_IRQHandler ; 8: USART1_RX Interrupt - DCD USART1_TX_IRQHandler ; 9: USART1_TX Interrupt - DCD LEUART0_IRQHandler ; 10: LEUART0 Interrupt - DCD PCNT0_IRQHandler ; 11: PCNT0 Interrupt - DCD RTC_IRQHandler ; 12: RTC Interrupt - DCD CMU_IRQHandler ; 13: CMU Interrupt - DCD VCMP_IRQHandler ; 14: VCMP Interrupt - DCD MSC_IRQHandler ; 15: MSC Interrupt - DCD AES_IRQHandler ; 16: AES Interrupt - DCD 0 ; 17: Reserved Interrupt - DCD 0 ; 18: Reserved Interrupt - - -__Vectors_End -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - ; Device specific interrupt handlers - - PUBWEAK DMA_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA_IRQHandler - B DMA_IRQHandler - - PUBWEAK GPIO_EVEN_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO_EVEN_IRQHandler - B GPIO_EVEN_IRQHandler - - PUBWEAK TIMER0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER0_IRQHandler - B TIMER0_IRQHandler - - PUBWEAK ACMP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ACMP0_IRQHandler - B ACMP0_IRQHandler - - PUBWEAK ADC0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ADC0_IRQHandler - B ADC0_IRQHandler - - PUBWEAK I2C0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C0_IRQHandler - B I2C0_IRQHandler - - PUBWEAK GPIO_ODD_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO_ODD_IRQHandler - B GPIO_ODD_IRQHandler - - PUBWEAK TIMER1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER1_IRQHandler - B TIMER1_IRQHandler - - PUBWEAK USART1_RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART1_RX_IRQHandler - B USART1_RX_IRQHandler - - PUBWEAK USART1_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART1_TX_IRQHandler - B USART1_TX_IRQHandler - - PUBWEAK LEUART0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LEUART0_IRQHandler - B LEUART0_IRQHandler - - PUBWEAK PCNT0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PCNT0_IRQHandler - B PCNT0_IRQHandler - - PUBWEAK RTC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC_IRQHandler - B RTC_IRQHandler - - PUBWEAK CMU_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CMU_IRQHandler - B CMU_IRQHandler - - PUBWEAK VCMP_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -VCMP_IRQHandler - B VCMP_IRQHandler - - PUBWEAK MSC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -MSC_IRQHandler - B MSC_IRQHandler - - PUBWEAK AES_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -AES_IRQHandler - B AES_IRQHandler - - - END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/TOOLCHAIN_IAR/startup_efr32mg1p.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,354 @@ +;/**************************************************************************//** +; * @file startup_efr32mg1p.s +; * @brief CMSIS Core Device Startup File +; * Silicon Labs EFR32MG1P Device Series +; * @version 5.0.0 +; * @date 30. January 2012 +; * +; * @note +; * Copyright (C) 2012 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; +; When debugging in RAM, it can be located in RAM with at least a 128 byte +; alignment, 256 byte alignment is requied if all interrupt vectors are in use. +; +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(8) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + + DCD EMU_IRQHandler ; 0: EMU Interrupt + DCD FRC_PRI_IRQHandler ; 1: FRC_PRI Interrupt + DCD WDOG0_IRQHandler ; 2: WDOG0 Interrupt + DCD FRC_IRQHandler ; 3: FRC Interrupt + DCD MODEM_IRQHandler ; 4: MODEM Interrupt + DCD RAC_SEQ_IRQHandler ; 5: RAC_SEQ Interrupt + DCD RAC_RSM_IRQHandler ; 6: RAC_RSM Interrupt + DCD BUFC_IRQHandler ; 7: BUFC Interrupt + DCD LDMA_IRQHandler ; 8: LDMA Interrupt + DCD GPIO_EVEN_IRQHandler ; 9: GPIO_EVEN Interrupt + DCD TIMER0_IRQHandler ; 10: TIMER0 Interrupt + DCD USART0_RX_IRQHandler ; 11: USART0_RX Interrupt + DCD USART0_TX_IRQHandler ; 12: USART0_TX Interrupt + DCD ACMP0_IRQHandler ; 13: ACMP0 Interrupt + DCD ADC0_IRQHandler ; 14: ADC0 Interrupt + DCD IDAC0_IRQHandler ; 15: IDAC0 Interrupt + DCD I2C0_IRQHandler ; 16: I2C0 Interrupt + DCD GPIO_ODD_IRQHandler ; 17: GPIO_ODD Interrupt + DCD TIMER1_IRQHandler ; 18: TIMER1 Interrupt + DCD USART1_RX_IRQHandler ; 19: USART1_RX Interrupt + DCD USART1_TX_IRQHandler ; 20: USART1_TX Interrupt + DCD LEUART0_IRQHandler ; 21: LEUART0 Interrupt + DCD PCNT0_IRQHandler ; 22: PCNT0 Interrupt + DCD CMU_IRQHandler ; 23: CMU Interrupt + DCD MSC_IRQHandler ; 24: MSC Interrupt + DCD CRYPTO_IRQHandler ; 25: CRYPTO Interrupt + DCD LETIMER0_IRQHandler ; 26: LETIMER0 Interrupt + DCD AGC_IRQHandler ; 27: AGC Interrupt + DCD PROTIMER_IRQHandler ; 28: PROTIMER Interrupt + DCD RTCC_IRQHandler ; 29: RTCC Interrupt + DCD SYNTH_IRQHandler ; 30: SYNTH Interrupt + DCD CRYOTIMER_IRQHandler ; 31: CRYOTIMER Interrupt + DCD RFSENSE_IRQHandler ; 32: RFSENSE Interrupt + DCD FPUEH_IRQHandler ; 33: FPUEH Interrupt + +__Vectors_End +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + ; Device specific interrupt handlers + + PUBWEAK EMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EMU_IRQHandler + B EMU_IRQHandler + + PUBWEAK FRC_PRI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FRC_PRI_IRQHandler + B FRC_PRI_IRQHandler + + PUBWEAK WDOG0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDOG0_IRQHandler + B WDOG0_IRQHandler + + PUBWEAK FRC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FRC_IRQHandler + B FRC_IRQHandler + + PUBWEAK MODEM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MODEM_IRQHandler + B MODEM_IRQHandler + + PUBWEAK RAC_SEQ_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RAC_SEQ_IRQHandler + B RAC_SEQ_IRQHandler + + PUBWEAK RAC_RSM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RAC_RSM_IRQHandler + B RAC_RSM_IRQHandler + + PUBWEAK BUFC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +BUFC_IRQHandler + B BUFC_IRQHandler + + PUBWEAK LDMA_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LDMA_IRQHandler + B LDMA_IRQHandler + + PUBWEAK GPIO_EVEN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_EVEN_IRQHandler + B GPIO_EVEN_IRQHandler + + PUBWEAK TIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER0_IRQHandler + B TIMER0_IRQHandler + + PUBWEAK USART0_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART0_RX_IRQHandler + B USART0_RX_IRQHandler + + PUBWEAK USART0_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART0_TX_IRQHandler + B USART0_TX_IRQHandler + + PUBWEAK ACMP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ACMP0_IRQHandler + B ACMP0_IRQHandler + + PUBWEAK ADC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC0_IRQHandler + B ADC0_IRQHandler + + PUBWEAK IDAC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +IDAC0_IRQHandler + B IDAC0_IRQHandler + + PUBWEAK I2C0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C0_IRQHandler + B I2C0_IRQHandler + + PUBWEAK GPIO_ODD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_ODD_IRQHandler + B GPIO_ODD_IRQHandler + + PUBWEAK TIMER1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER1_IRQHandler + B TIMER1_IRQHandler + + PUBWEAK USART1_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_RX_IRQHandler + B USART1_RX_IRQHandler + + PUBWEAK USART1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_TX_IRQHandler + B USART1_TX_IRQHandler + + PUBWEAK LEUART0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LEUART0_IRQHandler + B LEUART0_IRQHandler + + PUBWEAK PCNT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PCNT0_IRQHandler + B PCNT0_IRQHandler + + PUBWEAK CMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CMU_IRQHandler + B CMU_IRQHandler + + PUBWEAK MSC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MSC_IRQHandler + B MSC_IRQHandler + + PUBWEAK CRYPTO_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CRYPTO_IRQHandler + B CRYPTO_IRQHandler + + PUBWEAK LETIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LETIMER0_IRQHandler + B LETIMER0_IRQHandler + + PUBWEAK AGC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +AGC_IRQHandler + B AGC_IRQHandler + + PUBWEAK PROTIMER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PROTIMER_IRQHandler + B PROTIMER_IRQHandler + + PUBWEAK RTCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTCC_IRQHandler + B RTCC_IRQHandler + + PUBWEAK SYNTH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SYNTH_IRQHandler + B SYNTH_IRQHandler + + PUBWEAK CRYOTIMER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CRYOTIMER_IRQHandler + B CRYOTIMER_IRQHandler + + PUBWEAK RFSENSE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RFSENSE_IRQHandler + B RFSENSE_IRQHandler + + PUBWEAK FPUEH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FPUEH_IRQHandler + B FPUEH_IRQHandler + + + END
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG1/device/TOOLCHAIN_IAR/startup_efr32mg1p.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,354 +0,0 @@ -;/**************************************************************************//** -; * @file startup_efr32mg1p.s -; * @brief CMSIS Core Device Startup File -; * Silicon Labs EFR32MG1P Device Series -; * @version 5.0.0 -; * @date 30. January 2012 -; * -; * @note -; * Copyright (C) 2012 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; -; When debugging in RAM, it can be located in RAM with at least a 128 byte -; alignment, 256 byte alignment is requied if all interrupt vectors are in use. -; -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(8) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler - DCD HardFault_Handler - DCD MemManage_Handler - DCD BusFault_Handler - DCD UsageFault_Handler -__vector_table_0x1c - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD SVC_Handler - DCD DebugMon_Handler - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - - DCD EMU_IRQHandler ; 0: EMU Interrupt - DCD FRC_PRI_IRQHandler ; 1: FRC_PRI Interrupt - DCD WDOG0_IRQHandler ; 2: WDOG0 Interrupt - DCD FRC_IRQHandler ; 3: FRC Interrupt - DCD MODEM_IRQHandler ; 4: MODEM Interrupt - DCD RAC_SEQ_IRQHandler ; 5: RAC_SEQ Interrupt - DCD RAC_RSM_IRQHandler ; 6: RAC_RSM Interrupt - DCD BUFC_IRQHandler ; 7: BUFC Interrupt - DCD LDMA_IRQHandler ; 8: LDMA Interrupt - DCD GPIO_EVEN_IRQHandler ; 9: GPIO_EVEN Interrupt - DCD TIMER0_IRQHandler ; 10: TIMER0 Interrupt - DCD USART0_RX_IRQHandler ; 11: USART0_RX Interrupt - DCD USART0_TX_IRQHandler ; 12: USART0_TX Interrupt - DCD ACMP0_IRQHandler ; 13: ACMP0 Interrupt - DCD ADC0_IRQHandler ; 14: ADC0 Interrupt - DCD IDAC0_IRQHandler ; 15: IDAC0 Interrupt - DCD I2C0_IRQHandler ; 16: I2C0 Interrupt - DCD GPIO_ODD_IRQHandler ; 17: GPIO_ODD Interrupt - DCD TIMER1_IRQHandler ; 18: TIMER1 Interrupt - DCD USART1_RX_IRQHandler ; 19: USART1_RX Interrupt - DCD USART1_TX_IRQHandler ; 20: USART1_TX Interrupt - DCD LEUART0_IRQHandler ; 21: LEUART0 Interrupt - DCD PCNT0_IRQHandler ; 22: PCNT0 Interrupt - DCD CMU_IRQHandler ; 23: CMU Interrupt - DCD MSC_IRQHandler ; 24: MSC Interrupt - DCD CRYPTO_IRQHandler ; 25: CRYPTO Interrupt - DCD LETIMER0_IRQHandler ; 26: LETIMER0 Interrupt - DCD AGC_IRQHandler ; 27: AGC Interrupt - DCD PROTIMER_IRQHandler ; 28: PROTIMER Interrupt - DCD RTCC_IRQHandler ; 29: RTCC Interrupt - DCD SYNTH_IRQHandler ; 30: SYNTH Interrupt - DCD CRYOTIMER_IRQHandler ; 31: CRYOTIMER Interrupt - DCD RFSENSE_IRQHandler ; 32: RFSENSE Interrupt - DCD FPUEH_IRQHandler ; 33: FPUEH Interrupt - -__Vectors_End -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - ; Device specific interrupt handlers - - PUBWEAK EMU_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EMU_IRQHandler - B EMU_IRQHandler - - PUBWEAK FRC_PRI_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FRC_PRI_IRQHandler - B FRC_PRI_IRQHandler - - PUBWEAK WDOG0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -WDOG0_IRQHandler - B WDOG0_IRQHandler - - PUBWEAK FRC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FRC_IRQHandler - B FRC_IRQHandler - - PUBWEAK MODEM_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -MODEM_IRQHandler - B MODEM_IRQHandler - - PUBWEAK RAC_SEQ_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RAC_SEQ_IRQHandler - B RAC_SEQ_IRQHandler - - PUBWEAK RAC_RSM_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RAC_RSM_IRQHandler - B RAC_RSM_IRQHandler - - PUBWEAK BUFC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -BUFC_IRQHandler - B BUFC_IRQHandler - - PUBWEAK LDMA_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LDMA_IRQHandler - B LDMA_IRQHandler - - PUBWEAK GPIO_EVEN_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO_EVEN_IRQHandler - B GPIO_EVEN_IRQHandler - - PUBWEAK TIMER0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER0_IRQHandler - B TIMER0_IRQHandler - - PUBWEAK USART0_RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART0_RX_IRQHandler - B USART0_RX_IRQHandler - - PUBWEAK USART0_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART0_TX_IRQHandler - B USART0_TX_IRQHandler - - PUBWEAK ACMP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ACMP0_IRQHandler - B ACMP0_IRQHandler - - PUBWEAK ADC0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ADC0_IRQHandler - B ADC0_IRQHandler - - PUBWEAK IDAC0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -IDAC0_IRQHandler - B IDAC0_IRQHandler - - PUBWEAK I2C0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C0_IRQHandler - B I2C0_IRQHandler - - PUBWEAK GPIO_ODD_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO_ODD_IRQHandler - B GPIO_ODD_IRQHandler - - PUBWEAK TIMER1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER1_IRQHandler - B TIMER1_IRQHandler - - PUBWEAK USART1_RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART1_RX_IRQHandler - B USART1_RX_IRQHandler - - PUBWEAK USART1_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART1_TX_IRQHandler - B USART1_TX_IRQHandler - - PUBWEAK LEUART0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LEUART0_IRQHandler - B LEUART0_IRQHandler - - PUBWEAK PCNT0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PCNT0_IRQHandler - B PCNT0_IRQHandler - - PUBWEAK CMU_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CMU_IRQHandler - B CMU_IRQHandler - - PUBWEAK MSC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -MSC_IRQHandler - B MSC_IRQHandler - - PUBWEAK CRYPTO_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CRYPTO_IRQHandler - B CRYPTO_IRQHandler - - PUBWEAK LETIMER0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LETIMER0_IRQHandler - B LETIMER0_IRQHandler - - PUBWEAK AGC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -AGC_IRQHandler - B AGC_IRQHandler - - PUBWEAK PROTIMER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PROTIMER_IRQHandler - B PROTIMER_IRQHandler - - PUBWEAK RTCC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTCC_IRQHandler - B RTCC_IRQHandler - - PUBWEAK SYNTH_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SYNTH_IRQHandler - B SYNTH_IRQHandler - - PUBWEAK CRYOTIMER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CRYOTIMER_IRQHandler - B CRYOTIMER_IRQHandler - - PUBWEAK RFSENSE_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RFSENSE_IRQHandler - B RFSENSE_IRQHandler - - PUBWEAK FPUEH_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FPUEH_IRQHandler - B FPUEH_IRQHandler - - - END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_IAR/startup_efr32mg12p.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,451 @@ +;/**************************************************************************//** +; * @file startup_efr32mg12p.s +; * @brief CMSIS Core Device Startup File +; * Silicon Labs EFR32MG12P Device Series +; * @version 5.1.2 +; * @date 30. January 2012 +; * +; * @note +; * Copyright (C) 2012 ARM Limited. All rights reserved. +; * +; * @par +; * ARM Limited (ARM) is supplying this software for use with Cortex-M +; * processor based microcontrollers. This file can be freely distributed +; * within development tools that are supporting such ARM based processors. +; * +; * @par +; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED +; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF +; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. +; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR +; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. +; * +; ******************************************************************************/ + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; +; When debugging in RAM, it can be located in RAM with at least a 128 byte +; alignment, 256 byte alignment is requied if all interrupt vectors are in use. +; +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(8) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + + DCD NMI_Handler + DCD HardFault_Handler + DCD MemManage_Handler + DCD BusFault_Handler + DCD UsageFault_Handler +__vector_table_0x1c + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD DebugMon_Handler + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + + ; External Interrupts + + DCD EMU_IRQHandler ; 0: EMU Interrupt + DCD FRC_PRI_IRQHandler ; 1: FRC_PRI Interrupt + DCD WDOG0_IRQHandler ; 2: WDOG0 Interrupt + DCD WDOG1_IRQHandler ; 3: WDOG1 Interrupt + DCD FRC_IRQHandler ; 4: FRC Interrupt + DCD MODEM_IRQHandler ; 5: MODEM Interrupt + DCD RAC_SEQ_IRQHandler ; 6: RAC_SEQ Interrupt + DCD RAC_RSM_IRQHandler ; 7: RAC_RSM Interrupt + DCD BUFC_IRQHandler ; 8: BUFC Interrupt + DCD LDMA_IRQHandler ; 9: LDMA Interrupt + DCD GPIO_EVEN_IRQHandler ; 10: GPIO_EVEN Interrupt + DCD TIMER0_IRQHandler ; 11: TIMER0 Interrupt + DCD USART0_RX_IRQHandler ; 12: USART0_RX Interrupt + DCD USART0_TX_IRQHandler ; 13: USART0_TX Interrupt + DCD ACMP0_IRQHandler ; 14: ACMP0 Interrupt + DCD ADC0_IRQHandler ; 15: ADC0 Interrupt + DCD IDAC0_IRQHandler ; 16: IDAC0 Interrupt + DCD I2C0_IRQHandler ; 17: I2C0 Interrupt + DCD GPIO_ODD_IRQHandler ; 18: GPIO_ODD Interrupt + DCD TIMER1_IRQHandler ; 19: TIMER1 Interrupt + DCD USART1_RX_IRQHandler ; 20: USART1_RX Interrupt + DCD USART1_TX_IRQHandler ; 21: USART1_TX Interrupt + DCD LEUART0_IRQHandler ; 22: LEUART0 Interrupt + DCD PCNT0_IRQHandler ; 23: PCNT0 Interrupt + DCD CMU_IRQHandler ; 24: CMU Interrupt + DCD MSC_IRQHandler ; 25: MSC Interrupt + DCD CRYPTO0_IRQHandler ; 26: CRYPTO0 Interrupt + DCD LETIMER0_IRQHandler ; 27: LETIMER0 Interrupt + DCD AGC_IRQHandler ; 28: AGC Interrupt + DCD PROTIMER_IRQHandler ; 29: PROTIMER Interrupt + DCD RTCC_IRQHandler ; 30: RTCC Interrupt + DCD SYNTH_IRQHandler ; 31: SYNTH Interrupt + DCD CRYOTIMER_IRQHandler ; 32: CRYOTIMER Interrupt + DCD RFSENSE_IRQHandler ; 33: RFSENSE Interrupt + DCD FPUEH_IRQHandler ; 34: FPUEH Interrupt + DCD SMU_IRQHandler ; 35: SMU Interrupt + DCD WTIMER0_IRQHandler ; 36: WTIMER0 Interrupt + DCD WTIMER1_IRQHandler ; 37: WTIMER1 Interrupt + DCD PCNT1_IRQHandler ; 38: PCNT1 Interrupt + DCD PCNT2_IRQHandler ; 39: PCNT2 Interrupt + DCD USART2_RX_IRQHandler ; 40: USART2_RX Interrupt + DCD USART2_TX_IRQHandler ; 41: USART2_TX Interrupt + DCD I2C1_IRQHandler ; 42: I2C1 Interrupt + DCD USART3_RX_IRQHandler ; 43: USART3_RX Interrupt + DCD USART3_TX_IRQHandler ; 44: USART3_TX Interrupt + DCD VDAC0_IRQHandler ; 45: VDAC0 Interrupt + DCD CSEN_IRQHandler ; 46: CSEN Interrupt + DCD LESENSE_IRQHandler ; 47: LESENSE Interrupt + DCD CRYPTO1_IRQHandler ; 48: CRYPTO1 Interrupt + DCD TRNG0_IRQHandler ; 49: TRNG0 Interrupt + DCD 0 ; 50: Reserved Interrupt + +__Vectors_End +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK MemManage_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +MemManage_Handler + B MemManage_Handler + + PUBWEAK BusFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +BusFault_Handler + B BusFault_Handler + + PUBWEAK UsageFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UsageFault_Handler + B UsageFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK DebugMon_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DebugMon_Handler + B DebugMon_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + ; Device specific interrupt handlers + + PUBWEAK EMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +EMU_IRQHandler + B EMU_IRQHandler + + PUBWEAK FRC_PRI_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FRC_PRI_IRQHandler + B FRC_PRI_IRQHandler + + PUBWEAK WDOG0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDOG0_IRQHandler + B WDOG0_IRQHandler + + PUBWEAK WDOG1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WDOG1_IRQHandler + B WDOG1_IRQHandler + + PUBWEAK FRC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FRC_IRQHandler + B FRC_IRQHandler + + PUBWEAK MODEM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MODEM_IRQHandler + B MODEM_IRQHandler + + PUBWEAK RAC_SEQ_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RAC_SEQ_IRQHandler + B RAC_SEQ_IRQHandler + + PUBWEAK RAC_RSM_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RAC_RSM_IRQHandler + B RAC_RSM_IRQHandler + + PUBWEAK BUFC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +BUFC_IRQHandler + B BUFC_IRQHandler + + PUBWEAK LDMA_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LDMA_IRQHandler + B LDMA_IRQHandler + + PUBWEAK GPIO_EVEN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_EVEN_IRQHandler + B GPIO_EVEN_IRQHandler + + PUBWEAK TIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER0_IRQHandler + B TIMER0_IRQHandler + + PUBWEAK USART0_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART0_RX_IRQHandler + B USART0_RX_IRQHandler + + PUBWEAK USART0_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART0_TX_IRQHandler + B USART0_TX_IRQHandler + + PUBWEAK ACMP0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ACMP0_IRQHandler + B ACMP0_IRQHandler + + PUBWEAK ADC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC0_IRQHandler + B ADC0_IRQHandler + + PUBWEAK IDAC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +IDAC0_IRQHandler + B IDAC0_IRQHandler + + PUBWEAK I2C0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C0_IRQHandler + B I2C0_IRQHandler + + PUBWEAK GPIO_ODD_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +GPIO_ODD_IRQHandler + B GPIO_ODD_IRQHandler + + PUBWEAK TIMER1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TIMER1_IRQHandler + B TIMER1_IRQHandler + + PUBWEAK USART1_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_RX_IRQHandler + B USART1_RX_IRQHandler + + PUBWEAK USART1_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART1_TX_IRQHandler + B USART1_TX_IRQHandler + + PUBWEAK LEUART0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LEUART0_IRQHandler + B LEUART0_IRQHandler + + PUBWEAK PCNT0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PCNT0_IRQHandler + B PCNT0_IRQHandler + + PUBWEAK CMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CMU_IRQHandler + B CMU_IRQHandler + + PUBWEAK MSC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +MSC_IRQHandler + B MSC_IRQHandler + + PUBWEAK CRYPTO0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CRYPTO0_IRQHandler + B CRYPTO0_IRQHandler + + PUBWEAK LETIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LETIMER0_IRQHandler + B LETIMER0_IRQHandler + + PUBWEAK AGC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +AGC_IRQHandler + B AGC_IRQHandler + + PUBWEAK PROTIMER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PROTIMER_IRQHandler + B PROTIMER_IRQHandler + + PUBWEAK RTCC_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RTCC_IRQHandler + B RTCC_IRQHandler + + PUBWEAK SYNTH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SYNTH_IRQHandler + B SYNTH_IRQHandler + + PUBWEAK CRYOTIMER_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CRYOTIMER_IRQHandler + B CRYOTIMER_IRQHandler + + PUBWEAK RFSENSE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +RFSENSE_IRQHandler + B RFSENSE_IRQHandler + + PUBWEAK FPUEH_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +FPUEH_IRQHandler + B FPUEH_IRQHandler + + PUBWEAK SMU_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +SMU_IRQHandler + B SMU_IRQHandler + + PUBWEAK WTIMER0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WTIMER0_IRQHandler + B WTIMER0_IRQHandler + + PUBWEAK WTIMER1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +WTIMER1_IRQHandler + B WTIMER1_IRQHandler + + PUBWEAK PCNT1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PCNT1_IRQHandler + B PCNT1_IRQHandler + + PUBWEAK PCNT2_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +PCNT2_IRQHandler + B PCNT2_IRQHandler + + PUBWEAK USART2_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_RX_IRQHandler + B USART2_RX_IRQHandler + + PUBWEAK USART2_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART2_TX_IRQHandler + B USART2_TX_IRQHandler + + PUBWEAK I2C1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_IRQHandler + B I2C1_IRQHandler + + PUBWEAK USART3_RX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_RX_IRQHandler + B USART3_RX_IRQHandler + + PUBWEAK USART3_TX_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +USART3_TX_IRQHandler + B USART3_TX_IRQHandler + + PUBWEAK VDAC0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +VDAC0_IRQHandler + B VDAC0_IRQHandler + + PUBWEAK CSEN_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CSEN_IRQHandler + B CSEN_IRQHandler + + PUBWEAK LESENSE_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +LESENSE_IRQHandler + B LESENSE_IRQHandler + + PUBWEAK CRYPTO1_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +CRYPTO1_IRQHandler + B CRYPTO1_IRQHandler + + PUBWEAK TRNG0_IRQHandler + SECTION .text:CODE:REORDER:NOROOT(1) +TRNG0_IRQHandler + B TRNG0_IRQHandler + + + END
--- a/targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFR32MG12/device/TOOLCHAIN_IAR/startup_efr32mg12p.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,451 +0,0 @@ -;/**************************************************************************//** -; * @file startup_efr32mg12p.s -; * @brief CMSIS Core Device Startup File -; * Silicon Labs EFR32MG12P Device Series -; * @version 5.1.2 -; * @date 30. January 2012 -; * -; * @note -; * Copyright (C) 2012 ARM Limited. All rights reserved. -; * -; * @par -; * ARM Limited (ARM) is supplying this software for use with Cortex-M -; * processor based microcontrollers. This file can be freely distributed -; * within development tools that are supporting such ARM based processors. -; * -; * @par -; * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED -; * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF -; * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE. -; * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR -; * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER. -; * -; ******************************************************************************/ - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; -; When debugging in RAM, it can be located in RAM with at least a 128 byte -; alignment, 256 byte alignment is requied if all interrupt vectors are in use. -; -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(8) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - - DCD NMI_Handler - DCD HardFault_Handler - DCD MemManage_Handler - DCD BusFault_Handler - DCD UsageFault_Handler -__vector_table_0x1c - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD SVC_Handler - DCD DebugMon_Handler - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - - ; External Interrupts - - DCD EMU_IRQHandler ; 0: EMU Interrupt - DCD FRC_PRI_IRQHandler ; 1: FRC_PRI Interrupt - DCD WDOG0_IRQHandler ; 2: WDOG0 Interrupt - DCD WDOG1_IRQHandler ; 3: WDOG1 Interrupt - DCD FRC_IRQHandler ; 4: FRC Interrupt - DCD MODEM_IRQHandler ; 5: MODEM Interrupt - DCD RAC_SEQ_IRQHandler ; 6: RAC_SEQ Interrupt - DCD RAC_RSM_IRQHandler ; 7: RAC_RSM Interrupt - DCD BUFC_IRQHandler ; 8: BUFC Interrupt - DCD LDMA_IRQHandler ; 9: LDMA Interrupt - DCD GPIO_EVEN_IRQHandler ; 10: GPIO_EVEN Interrupt - DCD TIMER0_IRQHandler ; 11: TIMER0 Interrupt - DCD USART0_RX_IRQHandler ; 12: USART0_RX Interrupt - DCD USART0_TX_IRQHandler ; 13: USART0_TX Interrupt - DCD ACMP0_IRQHandler ; 14: ACMP0 Interrupt - DCD ADC0_IRQHandler ; 15: ADC0 Interrupt - DCD IDAC0_IRQHandler ; 16: IDAC0 Interrupt - DCD I2C0_IRQHandler ; 17: I2C0 Interrupt - DCD GPIO_ODD_IRQHandler ; 18: GPIO_ODD Interrupt - DCD TIMER1_IRQHandler ; 19: TIMER1 Interrupt - DCD USART1_RX_IRQHandler ; 20: USART1_RX Interrupt - DCD USART1_TX_IRQHandler ; 21: USART1_TX Interrupt - DCD LEUART0_IRQHandler ; 22: LEUART0 Interrupt - DCD PCNT0_IRQHandler ; 23: PCNT0 Interrupt - DCD CMU_IRQHandler ; 24: CMU Interrupt - DCD MSC_IRQHandler ; 25: MSC Interrupt - DCD CRYPTO0_IRQHandler ; 26: CRYPTO0 Interrupt - DCD LETIMER0_IRQHandler ; 27: LETIMER0 Interrupt - DCD AGC_IRQHandler ; 28: AGC Interrupt - DCD PROTIMER_IRQHandler ; 29: PROTIMER Interrupt - DCD RTCC_IRQHandler ; 30: RTCC Interrupt - DCD SYNTH_IRQHandler ; 31: SYNTH Interrupt - DCD CRYOTIMER_IRQHandler ; 32: CRYOTIMER Interrupt - DCD RFSENSE_IRQHandler ; 33: RFSENSE Interrupt - DCD FPUEH_IRQHandler ; 34: FPUEH Interrupt - DCD SMU_IRQHandler ; 35: SMU Interrupt - DCD WTIMER0_IRQHandler ; 36: WTIMER0 Interrupt - DCD WTIMER1_IRQHandler ; 37: WTIMER1 Interrupt - DCD PCNT1_IRQHandler ; 38: PCNT1 Interrupt - DCD PCNT2_IRQHandler ; 39: PCNT2 Interrupt - DCD USART2_RX_IRQHandler ; 40: USART2_RX Interrupt - DCD USART2_TX_IRQHandler ; 41: USART2_TX Interrupt - DCD I2C1_IRQHandler ; 42: I2C1 Interrupt - DCD USART3_RX_IRQHandler ; 43: USART3_RX Interrupt - DCD USART3_TX_IRQHandler ; 44: USART3_TX Interrupt - DCD VDAC0_IRQHandler ; 45: VDAC0 Interrupt - DCD CSEN_IRQHandler ; 46: CSEN Interrupt - DCD LESENSE_IRQHandler ; 47: LESENSE Interrupt - DCD CRYPTO1_IRQHandler ; 48: CRYPTO1 Interrupt - DCD TRNG0_IRQHandler ; 49: TRNG0 Interrupt - DCD 0 ; 50: Reserved Interrupt - -__Vectors_End -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK MemManage_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -MemManage_Handler - B MemManage_Handler - - PUBWEAK BusFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -BusFault_Handler - B BusFault_Handler - - PUBWEAK UsageFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UsageFault_Handler - B UsageFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK DebugMon_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DebugMon_Handler - B DebugMon_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - ; Device specific interrupt handlers - - PUBWEAK EMU_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -EMU_IRQHandler - B EMU_IRQHandler - - PUBWEAK FRC_PRI_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FRC_PRI_IRQHandler - B FRC_PRI_IRQHandler - - PUBWEAK WDOG0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -WDOG0_IRQHandler - B WDOG0_IRQHandler - - PUBWEAK WDOG1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -WDOG1_IRQHandler - B WDOG1_IRQHandler - - PUBWEAK FRC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FRC_IRQHandler - B FRC_IRQHandler - - PUBWEAK MODEM_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -MODEM_IRQHandler - B MODEM_IRQHandler - - PUBWEAK RAC_SEQ_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RAC_SEQ_IRQHandler - B RAC_SEQ_IRQHandler - - PUBWEAK RAC_RSM_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RAC_RSM_IRQHandler - B RAC_RSM_IRQHandler - - PUBWEAK BUFC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -BUFC_IRQHandler - B BUFC_IRQHandler - - PUBWEAK LDMA_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LDMA_IRQHandler - B LDMA_IRQHandler - - PUBWEAK GPIO_EVEN_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO_EVEN_IRQHandler - B GPIO_EVEN_IRQHandler - - PUBWEAK TIMER0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER0_IRQHandler - B TIMER0_IRQHandler - - PUBWEAK USART0_RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART0_RX_IRQHandler - B USART0_RX_IRQHandler - - PUBWEAK USART0_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART0_TX_IRQHandler - B USART0_TX_IRQHandler - - PUBWEAK ACMP0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ACMP0_IRQHandler - B ACMP0_IRQHandler - - PUBWEAK ADC0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -ADC0_IRQHandler - B ADC0_IRQHandler - - PUBWEAK IDAC0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -IDAC0_IRQHandler - B IDAC0_IRQHandler - - PUBWEAK I2C0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C0_IRQHandler - B I2C0_IRQHandler - - PUBWEAK GPIO_ODD_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -GPIO_ODD_IRQHandler - B GPIO_ODD_IRQHandler - - PUBWEAK TIMER1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TIMER1_IRQHandler - B TIMER1_IRQHandler - - PUBWEAK USART1_RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART1_RX_IRQHandler - B USART1_RX_IRQHandler - - PUBWEAK USART1_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART1_TX_IRQHandler - B USART1_TX_IRQHandler - - PUBWEAK LEUART0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LEUART0_IRQHandler - B LEUART0_IRQHandler - - PUBWEAK PCNT0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PCNT0_IRQHandler - B PCNT0_IRQHandler - - PUBWEAK CMU_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CMU_IRQHandler - B CMU_IRQHandler - - PUBWEAK MSC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -MSC_IRQHandler - B MSC_IRQHandler - - PUBWEAK CRYPTO0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CRYPTO0_IRQHandler - B CRYPTO0_IRQHandler - - PUBWEAK LETIMER0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LETIMER0_IRQHandler - B LETIMER0_IRQHandler - - PUBWEAK AGC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -AGC_IRQHandler - B AGC_IRQHandler - - PUBWEAK PROTIMER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PROTIMER_IRQHandler - B PROTIMER_IRQHandler - - PUBWEAK RTCC_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RTCC_IRQHandler - B RTCC_IRQHandler - - PUBWEAK SYNTH_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SYNTH_IRQHandler - B SYNTH_IRQHandler - - PUBWEAK CRYOTIMER_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CRYOTIMER_IRQHandler - B CRYOTIMER_IRQHandler - - PUBWEAK RFSENSE_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -RFSENSE_IRQHandler - B RFSENSE_IRQHandler - - PUBWEAK FPUEH_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -FPUEH_IRQHandler - B FPUEH_IRQHandler - - PUBWEAK SMU_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -SMU_IRQHandler - B SMU_IRQHandler - - PUBWEAK WTIMER0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -WTIMER0_IRQHandler - B WTIMER0_IRQHandler - - PUBWEAK WTIMER1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -WTIMER1_IRQHandler - B WTIMER1_IRQHandler - - PUBWEAK PCNT1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PCNT1_IRQHandler - B PCNT1_IRQHandler - - PUBWEAK PCNT2_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -PCNT2_IRQHandler - B PCNT2_IRQHandler - - PUBWEAK USART2_RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART2_RX_IRQHandler - B USART2_RX_IRQHandler - - PUBWEAK USART2_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART2_TX_IRQHandler - B USART2_TX_IRQHandler - - PUBWEAK I2C1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C1_IRQHandler - B I2C1_IRQHandler - - PUBWEAK USART3_RX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART3_RX_IRQHandler - B USART3_RX_IRQHandler - - PUBWEAK USART3_TX_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -USART3_TX_IRQHandler - B USART3_TX_IRQHandler - - PUBWEAK VDAC0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -VDAC0_IRQHandler - B VDAC0_IRQHandler - - PUBWEAK CSEN_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CSEN_IRQHandler - B CSEN_IRQHandler - - PUBWEAK LESENSE_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -LESENSE_IRQHandler - B LESENSE_IRQHandler - - PUBWEAK CRYPTO1_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -CRYPTO1_IRQHandler - B CRYPTO1_IRQHandler - - PUBWEAK TRNG0_IRQHandler - SECTION .text:CODE:REORDER:NOROOT(1) -TRNG0_IRQHandler - B TRNG0_IRQHandler - - - END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_IAR/startup_W7500.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,305 @@ +;/******************************************************************************************************************************************************* +; * Copyright ¨Ï 2016 <WIZnet Co.,Ltd.> +; * Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the ¡°Software¡±), +; * to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, +; * and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +; +; * THE SOFTWARE IS PROVIDED ¡°AS IS¡±, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +; * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +; * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +; * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +;*********************************************************************************************************************************************************/ +;/**************************************************************************//** +; * @file startup_ARMCM0.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM0 Device Series +; * @version V1.08 +; * @date 23. November 2012 +; * +; * @note +; * +; ******************************************************************************/ +;/* Copyright (c) 2011 - 2012 ARM LIMITED +; +; All rights reserved. +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; - Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; - Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; - Neither the name of ARM nor the names of its contributors may be used +; to endorse or promote products derived from this software without +; specific prior written permission. +; * +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +; ---------------------------------------------------------------------------*/ + + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved +__vector_table_0x1c + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; Exterval Interrupts + DCD SSP0_Handler ; 16+ 0: SSP 0 Handler + DCD SSP1_Handler ; 16+ 1: SSP 1 Handler + DCD UART0_Handler ; 16+ 2: UART 0 Handler + DCD UART1_Handler ; 16+ 3: UART 1 Handler + DCD UART2_Handler ; 16+ 4: UART 2 Handler + DCD I2C0_Handler ; 16+ 5: I2C 0 Handler + DCD I2C1_Handler ; 16+ 6: I2C 1 Handler + DCD PORT0_Handler ; 16+ 7: GPIO Port 0 Combined Handler + DCD PORT1_Handler ; 16+ 8: GPIO Port 1 Combined Handler + DCD PORT2_Handler ; 16+ 9: GPIO Port 2 Combined Handler + DCD PORT3_Handler ; 16+10: GPIO Port 3 Combined Handler + DCD DMA_Handler ; 16+11: DMA Combined Handler + DCD DUALTIMER0_Handler ; 16+12: Dual timer 0 handler + DCD DUALTIMER1_Handler ; 16+13: Dual timer 1 handler + DCD PWM0_Handler ; 16+14: PWM0 Handler + DCD PWM1_Handler ; 16+15: PWM1 Handler + DCD PWM2_Handler ; 16+16: PWM2 Handler + DCD PWM3_Handler ; 16+17: PWM3 Handler + DCD PWM4_Handler ; 16+18: PWM4 Handler + DCD PWM5_Handler ; 16+19: PWM5 Handler + DCD PWM6_Handler ; 16+20: PWM6 Handler + DCD PWM7_Handler ; 16+21: PWM7 Handler + DCD RTC_Handler ; 16+22: RTC Handler + DCD ADC_Handler ; 16+23: ADC Handler + DCD WZTOE_Handler ; 16+24: WZTOE_Handler + DCD EXTI_Handler ; 16+25: EXTI_Handler +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK SSP0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SSP0_Handler + B SSP0_Handler + + PUBWEAK SSP1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SSP1_Handler + B SSP1_Handler + + PUBWEAK UART0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UART0_Handler + B UART0_Handler + + PUBWEAK UART1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UART1_Handler + B UART1_Handler + + PUBWEAK UART2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UART2_Handler + B UART2_Handler + + PUBWEAK I2C0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C0_Handler + B I2C0_Handler + + PUBWEAK I2C1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_Handler + B I2C1_Handler + + PUBWEAK PORT0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_Handler + B PORT0_Handler + + PUBWEAK PORT1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT1_Handler + B PORT1_Handler + + PUBWEAK PORT2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT2_Handler + B PORT2_Handler + + PUBWEAK PORT3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT3_Handler + B PORT3_Handler + + PUBWEAK DMA_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA_Handler + B DMA_Handler + + PUBWEAK DUALTIMER0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DUALTIMER0_Handler + B DUALTIMER0_Handler + + PUBWEAK DUALTIMER1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DUALTIMER1_Handler + B DUALTIMER1_Handler + + PUBWEAK PWM0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM0_Handler + B PWM0_Handler + + PUBWEAK PWM1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM1_Handler + B PWM1_Handler + + PUBWEAK PWM2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM2_Handler + B PWM2_Handler + + PUBWEAK PWM3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM3_Handler + B PWM3_Handler + + PUBWEAK PWM4_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM4_Handler + B PWM4_Handler + + PUBWEAK PWM5_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM5_Handler + B PWM5_Handler + + PUBWEAK PWM6_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM6_Handler + B PWM6_Handler + + PUBWEAK PWM7_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM7_Handler + B PWM7_Handler + + PUBWEAK RTC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Handler + B RTC_Handler + + PUBWEAK ADC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_Handler + B ADC_Handler + + PUBWEAK WZTOE_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +WZTOE_Handler + B WZTOE_Handler + + PUBWEAK EXTI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI_Handler + B EXTI_Handler + + END
--- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500/device/TOOLCHAIN_IAR/startup_W7500.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,305 +0,0 @@ -;/******************************************************************************************************************************************************* -; * Copyright ¨Ï 2016 <WIZnet Co.,Ltd.> -; * Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the ¡°Software¡±), -; * to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, -; * and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: -; * -; * The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. -; -; * THE SOFTWARE IS PROVIDED ¡°AS IS¡±, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -; * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -; * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -; * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -;*********************************************************************************************************************************************************/ -;/**************************************************************************//** -; * @file startup_ARMCM0.s -; * @brief CMSIS Core Device Startup File for -; * ARMCM0 Device Series -; * @version V1.08 -; * @date 23. November 2012 -; * -; * @note -; * -; ******************************************************************************/ -;/* Copyright (c) 2011 - 2012 ARM LIMITED -; -; All rights reserved. -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; - Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; - Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; - Neither the name of ARM nor the names of its contributors may be used -; to endorse or promote products derived from this software without -; specific prior written permission. -; * -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE -; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; POSSIBILITY OF SUCH DAMAGE. -; ---------------------------------------------------------------------------*/ - - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved -__vector_table_0x1c - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; Exterval Interrupts - DCD SSP0_Handler ; 16+ 0: SSP 0 Handler - DCD SSP1_Handler ; 16+ 1: SSP 1 Handler - DCD UART0_Handler ; 16+ 2: UART 0 Handler - DCD UART1_Handler ; 16+ 3: UART 1 Handler - DCD UART2_Handler ; 16+ 4: UART 2 Handler - DCD I2C0_Handler ; 16+ 5: I2C 0 Handler - DCD I2C1_Handler ; 16+ 6: I2C 1 Handler - DCD PORT0_Handler ; 16+ 7: GPIO Port 0 Combined Handler - DCD PORT1_Handler ; 16+ 8: GPIO Port 1 Combined Handler - DCD PORT2_Handler ; 16+ 9: GPIO Port 2 Combined Handler - DCD PORT3_Handler ; 16+10: GPIO Port 3 Combined Handler - DCD DMA_Handler ; 16+11: DMA Combined Handler - DCD DUALTIMER0_Handler ; 16+12: Dual timer 0 handler - DCD DUALTIMER1_Handler ; 16+13: Dual timer 1 handler - DCD PWM0_Handler ; 16+14: PWM0 Handler - DCD PWM1_Handler ; 16+15: PWM1 Handler - DCD PWM2_Handler ; 16+16: PWM2 Handler - DCD PWM3_Handler ; 16+17: PWM3 Handler - DCD PWM4_Handler ; 16+18: PWM4 Handler - DCD PWM5_Handler ; 16+19: PWM5 Handler - DCD PWM6_Handler ; 16+20: PWM6 Handler - DCD PWM7_Handler ; 16+21: PWM7 Handler - DCD RTC_Handler ; 16+22: RTC Handler - DCD ADC_Handler ; 16+23: ADC Handler - DCD WZTOE_Handler ; 16+24: WZTOE_Handler - DCD EXTI_Handler ; 16+25: EXTI_Handler -__Vectors_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK SSP0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SSP0_Handler - B SSP0_Handler - - PUBWEAK SSP1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SSP1_Handler - B SSP1_Handler - - PUBWEAK UART0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UART0_Handler - B UART0_Handler - - PUBWEAK UART1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UART1_Handler - B UART1_Handler - - PUBWEAK UART2_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UART2_Handler - B UART2_Handler - - PUBWEAK I2C0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C0_Handler - B I2C0_Handler - - PUBWEAK I2C1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C1_Handler - B I2C1_Handler - - PUBWEAK PORT0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_Handler - B PORT0_Handler - - PUBWEAK PORT1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT1_Handler - B PORT1_Handler - - PUBWEAK PORT2_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT2_Handler - B PORT2_Handler - - PUBWEAK PORT3_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT3_Handler - B PORT3_Handler - - PUBWEAK DMA_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA_Handler - B DMA_Handler - - PUBWEAK DUALTIMER0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DUALTIMER0_Handler - B DUALTIMER0_Handler - - PUBWEAK DUALTIMER1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DUALTIMER1_Handler - B DUALTIMER1_Handler - - PUBWEAK PWM0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM0_Handler - B PWM0_Handler - - PUBWEAK PWM1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM1_Handler - B PWM1_Handler - - PUBWEAK PWM2_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM2_Handler - B PWM2_Handler - - PUBWEAK PWM3_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM3_Handler - B PWM3_Handler - - PUBWEAK PWM4_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM4_Handler - B PWM4_Handler - - PUBWEAK PWM5_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM5_Handler - B PWM5_Handler - - PUBWEAK PWM6_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM6_Handler - B PWM6_Handler - - PUBWEAK PWM7_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM7_Handler - B PWM7_Handler - - PUBWEAK RTC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC_Handler - B RTC_Handler - - PUBWEAK ADC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -ADC_Handler - B ADC_Handler - - PUBWEAK WZTOE_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -WZTOE_Handler - B WZTOE_Handler - - PUBWEAK EXTI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI_Handler - B EXTI_Handler - - END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_IAR/startup_W7500.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,305 @@ +;/******************************************************************************************************************************************************* +; * Copyright ¨Ï 2016 <WIZnet Co.,Ltd.> +; * Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the ¡°Software¡±), +; * to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, +; * and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +; +; * THE SOFTWARE IS PROVIDED ¡°AS IS¡±, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +; * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +; * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +; * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +;*********************************************************************************************************************************************************/ +;/**************************************************************************//** +; * @file startup_ARMCM0.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM0 Device Series +; * @version V1.08 +; * @date 23. November 2012 +; * +; * @note +; * +; ******************************************************************************/ +;/* Copyright (c) 2011 - 2012 ARM LIMITED +; +; All rights reserved. +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; - Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; - Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; - Neither the name of ARM nor the names of its contributors may be used +; to endorse or promote products derived from this software without +; specific prior written permission. +; * +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +; ---------------------------------------------------------------------------*/ + + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved +__vector_table_0x1c + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; Exterval Interrupts + DCD SSP0_Handler ; 16+ 0: SSP 0 Handler + DCD SSP1_Handler ; 16+ 1: SSP 1 Handler + DCD UART0_Handler ; 16+ 2: UART 0 Handler + DCD UART1_Handler ; 16+ 3: UART 1 Handler + DCD UART2_Handler ; 16+ 4: UART 2 Handler + DCD I2C0_Handler ; 16+ 5: I2C 0 Handler + DCD I2C1_Handler ; 16+ 6: I2C 1 Handler + DCD PORT0_Handler ; 16+ 7: GPIO Port 0 Combined Handler + DCD PORT1_Handler ; 16+ 8: GPIO Port 1 Combined Handler + DCD PORT2_Handler ; 16+ 9: GPIO Port 2 Combined Handler + DCD PORT3_Handler ; 16+10: GPIO Port 3 Combined Handler + DCD DMA_Handler ; 16+11: DMA Combined Handler + DCD DUALTIMER0_Handler ; 16+12: Dual timer 0 handler + DCD DUALTIMER1_Handler ; 16+13: Dual timer 1 handler + DCD PWM0_Handler ; 16+14: PWM0 Handler + DCD PWM1_Handler ; 16+15: PWM1 Handler + DCD PWM2_Handler ; 16+16: PWM2 Handler + DCD PWM3_Handler ; 16+17: PWM3 Handler + DCD PWM4_Handler ; 16+18: PWM4 Handler + DCD PWM5_Handler ; 16+19: PWM5 Handler + DCD PWM6_Handler ; 16+20: PWM6 Handler + DCD PWM7_Handler ; 16+21: PWM7 Handler + DCD RTC_Handler ; 16+22: RTC Handler + DCD ADC_Handler ; 16+23: ADC Handler + DCD WZTOE_Handler ; 16+24: WZTOE_Handler + DCD EXTI_Handler ; 16+25: EXTI_Handler +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK SSP0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SSP0_Handler + B SSP0_Handler + + PUBWEAK SSP1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SSP1_Handler + B SSP1_Handler + + PUBWEAK UART0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UART0_Handler + B UART0_Handler + + PUBWEAK UART1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UART1_Handler + B UART1_Handler + + PUBWEAK UART2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UART2_Handler + B UART2_Handler + + PUBWEAK I2C0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C0_Handler + B I2C0_Handler + + PUBWEAK I2C1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_Handler + B I2C1_Handler + + PUBWEAK PORT0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_Handler + B PORT0_Handler + + PUBWEAK PORT1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT1_Handler + B PORT1_Handler + + PUBWEAK PORT2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT2_Handler + B PORT2_Handler + + PUBWEAK PORT3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT3_Handler + B PORT3_Handler + + PUBWEAK DMA_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA_Handler + B DMA_Handler + + PUBWEAK DUALTIMER0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DUALTIMER0_Handler + B DUALTIMER0_Handler + + PUBWEAK DUALTIMER1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DUALTIMER1_Handler + B DUALTIMER1_Handler + + PUBWEAK PWM0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM0_Handler + B PWM0_Handler + + PUBWEAK PWM1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM1_Handler + B PWM1_Handler + + PUBWEAK PWM2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM2_Handler + B PWM2_Handler + + PUBWEAK PWM3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM3_Handler + B PWM3_Handler + + PUBWEAK PWM4_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM4_Handler + B PWM4_Handler + + PUBWEAK PWM5_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM5_Handler + B PWM5_Handler + + PUBWEAK PWM6_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM6_Handler + B PWM6_Handler + + PUBWEAK PWM7_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM7_Handler + B PWM7_Handler + + PUBWEAK RTC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Handler + B RTC_Handler + + PUBWEAK ADC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_Handler + B ADC_Handler + + PUBWEAK WZTOE_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +WZTOE_Handler + B WZTOE_Handler + + PUBWEAK EXTI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI_Handler + B EXTI_Handler + + END
--- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500ECO/device/TOOLCHAIN_IAR/startup_W7500.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,305 +0,0 @@ -;/******************************************************************************************************************************************************* -; * Copyright ¨Ï 2016 <WIZnet Co.,Ltd.> -; * Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the ¡°Software¡±), -; * to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, -; * and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: -; * -; * The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. -; -; * THE SOFTWARE IS PROVIDED ¡°AS IS¡±, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -; * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -; * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -; * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -;*********************************************************************************************************************************************************/ -;/**************************************************************************//** -; * @file startup_ARMCM0.s -; * @brief CMSIS Core Device Startup File for -; * ARMCM0 Device Series -; * @version V1.08 -; * @date 23. November 2012 -; * -; * @note -; * -; ******************************************************************************/ -;/* Copyright (c) 2011 - 2012 ARM LIMITED -; -; All rights reserved. -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; - Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; - Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; - Neither the name of ARM nor the names of its contributors may be used -; to endorse or promote products derived from this software without -; specific prior written permission. -; * -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE -; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; POSSIBILITY OF SUCH DAMAGE. -; ---------------------------------------------------------------------------*/ - - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved -__vector_table_0x1c - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; Exterval Interrupts - DCD SSP0_Handler ; 16+ 0: SSP 0 Handler - DCD SSP1_Handler ; 16+ 1: SSP 1 Handler - DCD UART0_Handler ; 16+ 2: UART 0 Handler - DCD UART1_Handler ; 16+ 3: UART 1 Handler - DCD UART2_Handler ; 16+ 4: UART 2 Handler - DCD I2C0_Handler ; 16+ 5: I2C 0 Handler - DCD I2C1_Handler ; 16+ 6: I2C 1 Handler - DCD PORT0_Handler ; 16+ 7: GPIO Port 0 Combined Handler - DCD PORT1_Handler ; 16+ 8: GPIO Port 1 Combined Handler - DCD PORT2_Handler ; 16+ 9: GPIO Port 2 Combined Handler - DCD PORT3_Handler ; 16+10: GPIO Port 3 Combined Handler - DCD DMA_Handler ; 16+11: DMA Combined Handler - DCD DUALTIMER0_Handler ; 16+12: Dual timer 0 handler - DCD DUALTIMER1_Handler ; 16+13: Dual timer 1 handler - DCD PWM0_Handler ; 16+14: PWM0 Handler - DCD PWM1_Handler ; 16+15: PWM1 Handler - DCD PWM2_Handler ; 16+16: PWM2 Handler - DCD PWM3_Handler ; 16+17: PWM3 Handler - DCD PWM4_Handler ; 16+18: PWM4 Handler - DCD PWM5_Handler ; 16+19: PWM5 Handler - DCD PWM6_Handler ; 16+20: PWM6 Handler - DCD PWM7_Handler ; 16+21: PWM7 Handler - DCD RTC_Handler ; 16+22: RTC Handler - DCD ADC_Handler ; 16+23: ADC Handler - DCD WZTOE_Handler ; 16+24: WZTOE_Handler - DCD EXTI_Handler ; 16+25: EXTI_Handler -__Vectors_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK SSP0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SSP0_Handler - B SSP0_Handler - - PUBWEAK SSP1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SSP1_Handler - B SSP1_Handler - - PUBWEAK UART0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UART0_Handler - B UART0_Handler - - PUBWEAK UART1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UART1_Handler - B UART1_Handler - - PUBWEAK UART2_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UART2_Handler - B UART2_Handler - - PUBWEAK I2C0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C0_Handler - B I2C0_Handler - - PUBWEAK I2C1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C1_Handler - B I2C1_Handler - - PUBWEAK PORT0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_Handler - B PORT0_Handler - - PUBWEAK PORT1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT1_Handler - B PORT1_Handler - - PUBWEAK PORT2_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT2_Handler - B PORT2_Handler - - PUBWEAK PORT3_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT3_Handler - B PORT3_Handler - - PUBWEAK DMA_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA_Handler - B DMA_Handler - - PUBWEAK DUALTIMER0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DUALTIMER0_Handler - B DUALTIMER0_Handler - - PUBWEAK DUALTIMER1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DUALTIMER1_Handler - B DUALTIMER1_Handler - - PUBWEAK PWM0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM0_Handler - B PWM0_Handler - - PUBWEAK PWM1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM1_Handler - B PWM1_Handler - - PUBWEAK PWM2_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM2_Handler - B PWM2_Handler - - PUBWEAK PWM3_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM3_Handler - B PWM3_Handler - - PUBWEAK PWM4_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM4_Handler - B PWM4_Handler - - PUBWEAK PWM5_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM5_Handler - B PWM5_Handler - - PUBWEAK PWM6_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM6_Handler - B PWM6_Handler - - PUBWEAK PWM7_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM7_Handler - B PWM7_Handler - - PUBWEAK RTC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC_Handler - B RTC_Handler - - PUBWEAK ADC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -ADC_Handler - B ADC_Handler - - PUBWEAK WZTOE_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -WZTOE_Handler - B WZTOE_Handler - - PUBWEAK EXTI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI_Handler - B EXTI_Handler - - END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device/TOOLCHAIN_IAR/startup_W7500.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,305 @@ +;/******************************************************************************************************************************************************* +; * Copyright ¨Ï 2016 <WIZnet Co.,Ltd.> +; * Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the ¡°Software¡±), +; * to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, +; * and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: +; * +; * The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. +; +; * THE SOFTWARE IS PROVIDED ¡°AS IS¡±, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, +; * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. +; * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, +; * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. +;*********************************************************************************************************************************************************/ +;/**************************************************************************//** +; * @file startup_ARMCM0.s +; * @brief CMSIS Core Device Startup File for +; * ARMCM0 Device Series +; * @version V1.08 +; * @date 23. November 2012 +; * +; * @note +; * +; ******************************************************************************/ +;/* Copyright (c) 2011 - 2012 ARM LIMITED +; +; All rights reserved. +; Redistribution and use in source and binary forms, with or without +; modification, are permitted provided that the following conditions are met: +; - Redistributions of source code must retain the above copyright +; notice, this list of conditions and the following disclaimer. +; - Redistributions in binary form must reproduce the above copyright +; notice, this list of conditions and the following disclaimer in the +; documentation and/or other materials provided with the distribution. +; - Neither the name of ARM nor the names of its contributors may be used +; to endorse or promote products derived from this software without +; specific prior written permission. +; * +; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" +; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE +; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE +; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE +; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR +; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF +; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS +; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN +; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) +; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +; POSSIBILITY OF SUCH DAMAGE. +; ---------------------------------------------------------------------------*/ + + +; +; The modules in this file are included in the libraries, and may be replaced +; by any user-defined modules that define the PUBLIC symbol _program_start or +; a user defined start symbol. +; To override the cstartup defined in the library, simply add your modified +; version to the workbench project. +; +; The vector table is normally located at address 0. +; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. +; The name "__vector_table" has special meaning for C-SPY: +; it is where the SP start value is found, and the NVIC vector +; table register (VTOR) is initialized to this address if != 0. +; +; Cortex-M version +; + + MODULE ?cstartup + + ;; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __vector_table_0x1c + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved +__vector_table_0x1c + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + + ; Exterval Interrupts + DCD SSP0_Handler ; 16+ 0: SSP 0 Handler + DCD SSP1_Handler ; 16+ 1: SSP 1 Handler + DCD UART0_Handler ; 16+ 2: UART 0 Handler + DCD UART1_Handler ; 16+ 3: UART 1 Handler + DCD UART2_Handler ; 16+ 4: UART 2 Handler + DCD I2C0_Handler ; 16+ 5: I2C 0 Handler + DCD I2C1_Handler ; 16+ 6: I2C 1 Handler + DCD PORT0_Handler ; 16+ 7: GPIO Port 0 Combined Handler + DCD PORT1_Handler ; 16+ 8: GPIO Port 1 Combined Handler + DCD PORT2_Handler ; 16+ 9: GPIO Port 2 Combined Handler + DCD PORT3_Handler ; 16+10: GPIO Port 3 Combined Handler + DCD DMA_Handler ; 16+11: DMA Combined Handler + DCD DUALTIMER0_Handler ; 16+12: Dual timer 0 handler + DCD DUALTIMER1_Handler ; 16+13: Dual timer 1 handler + DCD PWM0_Handler ; 16+14: PWM0 Handler + DCD PWM1_Handler ; 16+15: PWM1 Handler + DCD PWM2_Handler ; 16+16: PWM2 Handler + DCD PWM3_Handler ; 16+17: PWM3 Handler + DCD PWM4_Handler ; 16+18: PWM4 Handler + DCD PWM5_Handler ; 16+19: PWM5 Handler + DCD PWM6_Handler ; 16+20: PWM6 Handler + DCD PWM7_Handler ; 16+21: PWM7 Handler + DCD RTC_Handler ; 16+22: RTC Handler + DCD ADC_Handler ; 16+23: ADC Handler + DCD WZTOE_Handler ; 16+24: WZTOE_Handler + DCD EXTI_Handler ; 16+25: EXTI_Handler +__Vectors_End + +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + +;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; +;; +;; Default interrupt handlers. +;; + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B NMI_Handler + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B HardFault_Handler + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B SVC_Handler + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B PendSV_Handler + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B SysTick_Handler + + PUBWEAK SSP0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SSP0_Handler + B SSP0_Handler + + PUBWEAK SSP1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SSP1_Handler + B SSP1_Handler + + PUBWEAK UART0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UART0_Handler + B UART0_Handler + + PUBWEAK UART1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UART1_Handler + B UART1_Handler + + PUBWEAK UART2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +UART2_Handler + B UART2_Handler + + PUBWEAK I2C0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C0_Handler + B I2C0_Handler + + PUBWEAK I2C1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +I2C1_Handler + B I2C1_Handler + + PUBWEAK PORT0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT0_Handler + B PORT0_Handler + + PUBWEAK PORT1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT1_Handler + B PORT1_Handler + + PUBWEAK PORT2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT2_Handler + B PORT2_Handler + + PUBWEAK PORT3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PORT3_Handler + B PORT3_Handler + + PUBWEAK DMA_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DMA_Handler + B DMA_Handler + + PUBWEAK DUALTIMER0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DUALTIMER0_Handler + B DUALTIMER0_Handler + + PUBWEAK DUALTIMER1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +DUALTIMER1_Handler + B DUALTIMER1_Handler + + PUBWEAK PWM0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM0_Handler + B PWM0_Handler + + PUBWEAK PWM1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM1_Handler + B PWM1_Handler + + PUBWEAK PWM2_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM2_Handler + B PWM2_Handler + + PUBWEAK PWM3_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM3_Handler + B PWM3_Handler + + PUBWEAK PWM4_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM4_Handler + B PWM4_Handler + + PUBWEAK PWM5_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM5_Handler + B PWM5_Handler + + PUBWEAK PWM6_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM6_Handler + B PWM6_Handler + + PUBWEAK PWM7_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PWM7_Handler + B PWM7_Handler + + PUBWEAK RTC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +RTC_Handler + B RTC_Handler + + PUBWEAK ADC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +ADC_Handler + B ADC_Handler + + PUBWEAK WZTOE_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +WZTOE_Handler + B WZTOE_Handler + + PUBWEAK EXTI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +EXTI_Handler + B EXTI_Handler + + END
--- a/targets/TARGET_WIZNET/TARGET_W7500x/TARGET_WIZwiki_W7500P/device/TOOLCHAIN_IAR/startup_W7500.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,305 +0,0 @@ -;/******************************************************************************************************************************************************* -; * Copyright ¨Ï 2016 <WIZnet Co.,Ltd.> -; * Permission is hereby granted, free of charge, to any person obtaining a copy of this software and associated documentation files (the ¡°Software¡±), -; * to deal in the Software without restriction, including without limitation the rights to use, copy, modify, merge, publish, distribute, sublicense, -; * and/or sell copies of the Software, and to permit persons to whom the Software is furnished to do so, subject to the following conditions: -; * -; * The above copyright notice and this permission notice shall be included in all copies or substantial portions of the Software. -; -; * THE SOFTWARE IS PROVIDED ¡°AS IS¡±, WITHOUT WARRANTY OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, -; * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. -; * IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, -; * TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. -;*********************************************************************************************************************************************************/ -;/**************************************************************************//** -; * @file startup_ARMCM0.s -; * @brief CMSIS Core Device Startup File for -; * ARMCM0 Device Series -; * @version V1.08 -; * @date 23. November 2012 -; * -; * @note -; * -; ******************************************************************************/ -;/* Copyright (c) 2011 - 2012 ARM LIMITED -; -; All rights reserved. -; Redistribution and use in source and binary forms, with or without -; modification, are permitted provided that the following conditions are met: -; - Redistributions of source code must retain the above copyright -; notice, this list of conditions and the following disclaimer. -; - Redistributions in binary form must reproduce the above copyright -; notice, this list of conditions and the following disclaimer in the -; documentation and/or other materials provided with the distribution. -; - Neither the name of ARM nor the names of its contributors may be used -; to endorse or promote products derived from this software without -; specific prior written permission. -; * -; THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" -; AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE -; IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE -; ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE -; LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR -; CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF -; SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS -; INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN -; CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) -; ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE -; POSSIBILITY OF SUCH DAMAGE. -; ---------------------------------------------------------------------------*/ - - -; -; The modules in this file are included in the libraries, and may be replaced -; by any user-defined modules that define the PUBLIC symbol _program_start or -; a user defined start symbol. -; To override the cstartup defined in the library, simply add your modified -; version to the workbench project. -; -; The vector table is normally located at address 0. -; When debugging in RAM, it can be located in RAM, aligned to at least 2^6. -; The name "__vector_table" has special meaning for C-SPY: -; it is where the SP start value is found, and the NVIC vector -; table register (VTOR) is initialized to this address if != 0. -; -; Cortex-M version -; - - MODULE ?cstartup - - ;; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __vector_table_0x1c - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved -__vector_table_0x1c - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - - ; Exterval Interrupts - DCD SSP0_Handler ; 16+ 0: SSP 0 Handler - DCD SSP1_Handler ; 16+ 1: SSP 1 Handler - DCD UART0_Handler ; 16+ 2: UART 0 Handler - DCD UART1_Handler ; 16+ 3: UART 1 Handler - DCD UART2_Handler ; 16+ 4: UART 2 Handler - DCD I2C0_Handler ; 16+ 5: I2C 0 Handler - DCD I2C1_Handler ; 16+ 6: I2C 1 Handler - DCD PORT0_Handler ; 16+ 7: GPIO Port 0 Combined Handler - DCD PORT1_Handler ; 16+ 8: GPIO Port 1 Combined Handler - DCD PORT2_Handler ; 16+ 9: GPIO Port 2 Combined Handler - DCD PORT3_Handler ; 16+10: GPIO Port 3 Combined Handler - DCD DMA_Handler ; 16+11: DMA Combined Handler - DCD DUALTIMER0_Handler ; 16+12: Dual timer 0 handler - DCD DUALTIMER1_Handler ; 16+13: Dual timer 1 handler - DCD PWM0_Handler ; 16+14: PWM0 Handler - DCD PWM1_Handler ; 16+15: PWM1 Handler - DCD PWM2_Handler ; 16+16: PWM2 Handler - DCD PWM3_Handler ; 16+17: PWM3 Handler - DCD PWM4_Handler ; 16+18: PWM4 Handler - DCD PWM5_Handler ; 16+19: PWM5 Handler - DCD PWM6_Handler ; 16+20: PWM6 Handler - DCD PWM7_Handler ; 16+21: PWM7 Handler - DCD RTC_Handler ; 16+22: RTC Handler - DCD ADC_Handler ; 16+23: ADC Handler - DCD WZTOE_Handler ; 16+24: WZTOE_Handler - DCD EXTI_Handler ; 16+25: EXTI_Handler -__Vectors_End - -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - -;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;; -;; -;; Default interrupt handlers. -;; - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B NMI_Handler - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B HardFault_Handler - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B SVC_Handler - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B PendSV_Handler - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B SysTick_Handler - - PUBWEAK SSP0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SSP0_Handler - B SSP0_Handler - - PUBWEAK SSP1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SSP1_Handler - B SSP1_Handler - - PUBWEAK UART0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UART0_Handler - B UART0_Handler - - PUBWEAK UART1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UART1_Handler - B UART1_Handler - - PUBWEAK UART2_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -UART2_Handler - B UART2_Handler - - PUBWEAK I2C0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C0_Handler - B I2C0_Handler - - PUBWEAK I2C1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -I2C1_Handler - B I2C1_Handler - - PUBWEAK PORT0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT0_Handler - B PORT0_Handler - - PUBWEAK PORT1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT1_Handler - B PORT1_Handler - - PUBWEAK PORT2_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT2_Handler - B PORT2_Handler - - PUBWEAK PORT3_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PORT3_Handler - B PORT3_Handler - - PUBWEAK DMA_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DMA_Handler - B DMA_Handler - - PUBWEAK DUALTIMER0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DUALTIMER0_Handler - B DUALTIMER0_Handler - - PUBWEAK DUALTIMER1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -DUALTIMER1_Handler - B DUALTIMER1_Handler - - PUBWEAK PWM0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM0_Handler - B PWM0_Handler - - PUBWEAK PWM1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM1_Handler - B PWM1_Handler - - PUBWEAK PWM2_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM2_Handler - B PWM2_Handler - - PUBWEAK PWM3_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM3_Handler - B PWM3_Handler - - PUBWEAK PWM4_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM4_Handler - B PWM4_Handler - - PUBWEAK PWM5_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM5_Handler - B PWM5_Handler - - PUBWEAK PWM6_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM6_Handler - B PWM6_Handler - - PUBWEAK PWM7_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PWM7_Handler - B PWM7_Handler - - PUBWEAK RTC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -RTC_Handler - B RTC_Handler - - PUBWEAK ADC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -ADC_Handler - B ADC_Handler - - PUBWEAK WZTOE_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -WZTOE_Handler - B WZTOE_Handler - - PUBWEAK EXTI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -EXTI_Handler - B EXTI_Handler - - END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_ublox/TARGET_HI2110/device/TOOLCHAIN_ARM_STD/startup_hi2110.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,163 @@ +; mbed Microcontroller Library +; Copyright (c) 2016 u-blox. +;Licensed under the Apache License, Version 2.0 (the "License"); +;you may not use this file except in compliance with the License. +;You may obtain a copy of the License at +;http://www.apache.org/licenses/LICENSE-2.0 +;Unless required by applicable law or agreed to in writing, software +;distributed under the License is distributed on an "AS IS" BASIS, +;WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +;See the License for the specific language governing permissions and +;limitations under the License. + +; Description message + +__initial_sp EQU (0x01000000 + 0x5000 - 256) + + PRESERVE8 + THUMB + +; Vector Table Mapped to Address 0 at Reset + + AREA RESET, DATA, READONLY + EXPORT __Vectors + EXPORT __Vectors_End + EXPORT __Vectors_Size + +__Vectors DCD __initial_sp ; Top of Stack + DCD Reset_Handler ; Reset Handler + DCD NMI_Handler ; NMI Handler + DCD HardFault_Handler ; Hard Fault Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD SVC_Handler ; SVCall Handler + DCD 0 ; Reserved + DCD 0 ; Reserved + DCD PendSV_Handler ; PendSV Handler + DCD SysTick_Handler ; SysTick Handler + +; External Interrupts + DCD IRQ0_RTC_Handler + DCD IRQ1_TMR0_Handler + DCD IRQ2_SECURITY_Handler + DCD IRQ3_PROTOCOL_Handler + DCD IRQ4_APPS_Handler + DCD IRQ5_GPIO_Handler + DCD IRQ6_DMA_Handler + DCD IRQ7_UART0_Handler + DCD IRQ8_UART1_Handler + DCD IRQ9_SSP0_Handler + DCD IRQ10_SSP1_Handler + DCD IRQ11_PWM0IN_Handler + DCD IRQ12_PWM0OUT_Handler + DCD IRQ13_PWM1IN_Handler + DCD IRQ14_PWM1OUT_Handler + DCD IRQ15_I2C_Handler + DCD IRQ16_LPUART_Handler + DCD IRQ17_CAP_Handler + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD 0 + +__Vectors_End + +__Vectors_Size EQU __Vectors_End - __Vectors + + AREA |.text|, CODE, READONLY + +; Reset Handler + +Reset_Handler PROC + EXPORT Reset_Handler [WEAK] + IMPORT SystemInit + IMPORT __main + + LDR R0, =SystemInit + BLX R0 + LDR R0, =__main + BX R0 + ENDP + +; Dummy Exception Handlers (infinite loops which can be modified) + +NMI_Handler PROC + EXPORT NMI_Handler [WEAK] + B . + ENDP +HardFault_Handler\ + PROC + EXPORT HardFault_Handler [WEAK] + B . + ENDP +SVC_Handler PROC + EXPORT SVC_Handler [WEAK] + B . + ENDP +PendSV_Handler PROC + EXPORT PendSV_Handler [WEAK] + B . + ENDP +SysTick_Handler PROC + EXPORT SysTick_Handler [WEAK] + B . + ENDP + +Default_Handler PROC + + EXPORT IRQ0_RTC_Handler [WEAK] + EXPORT IRQ1_TMR0_Handler [WEAK] + EXPORT IRQ2_SECURITY_Handler [WEAK] + EXPORT IRQ3_PROTOCOL_Handler [WEAK] + EXPORT IRQ4_APPS_Handler [WEAK] + EXPORT IRQ5_GPIO_Handler [WEAK] + EXPORT IRQ6_DMA_Handler [WEAK] + EXPORT IRQ7_UART0_Handler [WEAK] + EXPORT IRQ8_UART1_Handler [WEAK] + EXPORT IRQ9_SSP0_Handler [WEAK] + EXPORT IRQ10_SSP1_Handler [WEAK] + EXPORT IRQ11_PWM0IN_Handler [WEAK] + EXPORT IRQ12_PWM0OUT_Handler [WEAK] + EXPORT IRQ13_PWM1IN_Handler [WEAK] + EXPORT IRQ14_PWM1OUT_Handler [WEAK] + EXPORT IRQ15_I2C_Handler [WEAK] + EXPORT IRQ16_LPUART_Handler [WEAK] + EXPORT IRQ17_CAP_Handler [WEAK] +IRQ0_RTC_Handler +IRQ1_TMR0_Handler +IRQ2_SECURITY_Handler +IRQ3_PROTOCOL_Handler +IRQ4_APPS_Handler +IRQ5_GPIO_Handler +IRQ6_DMA_Handler +IRQ7_UART0_Handler +IRQ8_UART1_Handler +IRQ9_SSP0_Handler +IRQ10_SSP1_Handler +IRQ11_PWM0IN_Handler +IRQ12_PWM0OUT_Handler +IRQ13_PWM1IN_Handler +IRQ14_PWM1OUT_Handler +IRQ15_I2C_Handler +IRQ16_LPUART_Handler +IRQ17_CAP_Handler + + B . + ENDP + ALIGN + END
--- a/targets/TARGET_ublox/TARGET_HI2110/device/TOOLCHAIN_ARM_STD/startup_hi2110.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,163 +0,0 @@ -; mbed Microcontroller Library -; Copyright (c) 2016 u-blox. -;Licensed under the Apache License, Version 2.0 (the "License"); -;you may not use this file except in compliance with the License. -;You may obtain a copy of the License at -;http://www.apache.org/licenses/LICENSE-2.0 -;Unless required by applicable law or agreed to in writing, software -;distributed under the License is distributed on an "AS IS" BASIS, -;WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -;See the License for the specific language governing permissions and -;limitations under the License. - -; Description message - -__initial_sp EQU (0x01000000 + 0x5000 - 256) - - PRESERVE8 - THUMB - -; Vector Table Mapped to Address 0 at Reset - - AREA RESET, DATA, READONLY - EXPORT __Vectors - EXPORT __Vectors_End - EXPORT __Vectors_Size - -__Vectors DCD __initial_sp ; Top of Stack - DCD Reset_Handler ; Reset Handler - DCD NMI_Handler ; NMI Handler - DCD HardFault_Handler ; Hard Fault Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD SVC_Handler ; SVCall Handler - DCD 0 ; Reserved - DCD 0 ; Reserved - DCD PendSV_Handler ; PendSV Handler - DCD SysTick_Handler ; SysTick Handler - -; External Interrupts - DCD IRQ0_RTC_Handler - DCD IRQ1_TMR0_Handler - DCD IRQ2_SECURITY_Handler - DCD IRQ3_PROTOCOL_Handler - DCD IRQ4_APPS_Handler - DCD IRQ5_GPIO_Handler - DCD IRQ6_DMA_Handler - DCD IRQ7_UART0_Handler - DCD IRQ8_UART1_Handler - DCD IRQ9_SSP0_Handler - DCD IRQ10_SSP1_Handler - DCD IRQ11_PWM0IN_Handler - DCD IRQ12_PWM0OUT_Handler - DCD IRQ13_PWM1IN_Handler - DCD IRQ14_PWM1OUT_Handler - DCD IRQ15_I2C_Handler - DCD IRQ16_LPUART_Handler - DCD IRQ17_CAP_Handler - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD 0 - -__Vectors_End - -__Vectors_Size EQU __Vectors_End - __Vectors - - AREA |.text|, CODE, READONLY - -; Reset Handler - -Reset_Handler PROC - EXPORT Reset_Handler [WEAK] - IMPORT SystemInit - IMPORT __main - - LDR R0, =SystemInit - BLX R0 - LDR R0, =__main - BX R0 - ENDP - -; Dummy Exception Handlers (infinite loops which can be modified) - -NMI_Handler PROC - EXPORT NMI_Handler [WEAK] - B . - ENDP -HardFault_Handler\ - PROC - EXPORT HardFault_Handler [WEAK] - B . - ENDP -SVC_Handler PROC - EXPORT SVC_Handler [WEAK] - B . - ENDP -PendSV_Handler PROC - EXPORT PendSV_Handler [WEAK] - B . - ENDP -SysTick_Handler PROC - EXPORT SysTick_Handler [WEAK] - B . - ENDP - -Default_Handler PROC - - EXPORT IRQ0_RTC_Handler [WEAK] - EXPORT IRQ1_TMR0_Handler [WEAK] - EXPORT IRQ2_SECURITY_Handler [WEAK] - EXPORT IRQ3_PROTOCOL_Handler [WEAK] - EXPORT IRQ4_APPS_Handler [WEAK] - EXPORT IRQ5_GPIO_Handler [WEAK] - EXPORT IRQ6_DMA_Handler [WEAK] - EXPORT IRQ7_UART0_Handler [WEAK] - EXPORT IRQ8_UART1_Handler [WEAK] - EXPORT IRQ9_SSP0_Handler [WEAK] - EXPORT IRQ10_SSP1_Handler [WEAK] - EXPORT IRQ11_PWM0IN_Handler [WEAK] - EXPORT IRQ12_PWM0OUT_Handler [WEAK] - EXPORT IRQ13_PWM1IN_Handler [WEAK] - EXPORT IRQ14_PWM1OUT_Handler [WEAK] - EXPORT IRQ15_I2C_Handler [WEAK] - EXPORT IRQ16_LPUART_Handler [WEAK] - EXPORT IRQ17_CAP_Handler [WEAK] -IRQ0_RTC_Handler -IRQ1_TMR0_Handler -IRQ2_SECURITY_Handler -IRQ3_PROTOCOL_Handler -IRQ4_APPS_Handler -IRQ5_GPIO_Handler -IRQ6_DMA_Handler -IRQ7_UART0_Handler -IRQ8_UART1_Handler -IRQ9_SSP0_Handler -IRQ10_SSP1_Handler -IRQ11_PWM0IN_Handler -IRQ12_PWM0OUT_Handler -IRQ13_PWM1IN_Handler -IRQ14_PWM1OUT_Handler -IRQ15_I2C_Handler -IRQ16_LPUART_Handler -IRQ17_CAP_Handler - - B . - ENDP - ALIGN - END
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_ublox/TARGET_HI2110/device/TOOLCHAIN_GCC_ARM/startup_hi2110.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,254 @@ +/* mbed Microcontroller Library + * Copyright (c) 2016 u-blox + * + * Licensed under the Apache License, Version 2.0 (the "License"); + * you may not use this file except in compliance with the License. + * You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, + * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + * See the License for the specific language governing permissions and + * limitations under the License. + */ + .syntax unified + .cpu cortex-m0 + .fpu softvfp + .thumb + +/* Setup the stack + * Since it grows downward the stack_system is the first location is the highest address + * The first other usage should therefore be at stack_system + 4 + * Should the stack overflow, there would be a hard fault in the core + */ + + .section .stacks,"aw",%progbits + +#ifdef __STACK_SIZE + .equ Stack_Size, __STACK_SIZE +#else + .equ Stack_Size, 1024 +#endif + .globl Stack_Size + .globl __StackTop + .globl __StackLimit + .align 2 + .type stack_system, %object + .size stack_system, Stack_Size +stack_system_end: + .space Stack_Size - 4 +stack_system: + .space 4 + + +/* This is the code that gets called when the processor first + * starts execution following a reset event. Only the absolutely + * necessary set is performed, after which the application + * supplied main() routine is called. + */ + .section .text.Reset_Handler,"ax",%progbits + .weak Reset_Handler + .type Reset_Handler, %function + .thumb + .func Reset_Handler +Reset_Handler: + + /* Make sure SP is really at the start of the stack */ + ldr r0, =stack_system + msr msp, r0 + + /* Prefill the system stack with 0xefbeadde (or deafbeef in little endian) */ + ldr r1, =__SYSTEM_STACK_START__ + ldr r3, =__SYSTEM_STACK_END__ + subs r3, r3, r1 + beq .stack_fill_loop_end + ldr r2, =0xefbeadde +.stack_fill_loop: + str r2, [r1, #0] /* Store the quad octet initialisation value in r2 into address in r1 */ + adds r1, r1, #4 /* Increased address in r1 by a quad octet */ + subs r3, r3, #4 /* Decrease the number of bytes to do by a quad octet */ + bgt .stack_fill_loop /* Keep going until it is all done */ +.stack_fill_loop_end: + + /* setup .data section */ + ldr r1, =__data_start__ + ldr r2, =__data_load__ + ldr r3, =__data_size__ + cmp r3, #0 + beq .end_set_data_loop + +.set_data_loop: + ldrb r4, [r2, #0] /* Load the octet value into r4 from address in r2 */ + strb r4, [r1, #0] /* Store the octet value in r4 to address in r1 */ + adds r2, r2, #1 /* Move onto next octet */ + adds r1, r1, #1 + subs r3, r3, #1 /* Decrease the number of bytes to do by an octet */ + bgt .set_data_loop /* Keep going until it is all done */ +.end_set_data_loop: + + /* Call init function */ + ldr r0, =SystemInit + blx r0 + + /* Call C++ startup */ + ldr r0, =_start + bx r0 + bl . + + .size Reset_Handler, .-Reset_Handler + .endfunc + +/* This is the code that gets called when the processor receives an + * unexpected interrupt. This simply enters an infinite loop, preserving + * the system state for examination by a debugger. + */ + .section .text.Default_Handler,"ax",%progbits + .global Default_Handler + .func Default_Handler +Default_Handler: +Infinite_Loop: + b Infinite_Loop + + .endfunc + .size Default_Handler, .-Default_Handler + +/****************************************************************************** + * The minimal vector table for a Cortex M0+. Note that the proper constructs + * must be placed on this to ensure that it ends up at physical address 0x0000.0000. + *******************************************************************************/ + + .section .isr_vector,"a",%progbits + .type g_pfnVectors, %object + .size g_pfnVectors, .-g_pfnVectors + .global g_pfnVectors + +g_pfnVectors: + .word stack_system + .word Reset_Handler + .word NMI_Handler + .word HardFault_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word SVC_Handler + .word 0 + .word 0 + .word PendSV_Handler + .word SysTick_Handler + +/* External Interrupts */ + .word IRQ0_RTC_Handler + .word IRQ1_TMR0_Handler + .word IRQ2_SECURITY_Handler + .word IRQ3_PROTOCOL_Handler + .word IRQ4_APPS_Handler + .word IRQ5_GPIO_Handler + .word IRQ6_DMA_Handler + .word IRQ7_UART0_Handler + .word IRQ8_UART1_Handler + .word IRQ9_SSP0_Handler + .word IRQ10_SSP1_Handler + .word IRQ11_PWM0IN_Handler + .word IRQ12_PWM0OUT_Handler + .word IRQ13_PWM1IN_Handler + .word IRQ14_PWM1OUT_Handler + .word IRQ15_I2C_Handler + .word IRQ16_LPUART_Handler + .word IRQ17_CAP_Handler + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + .word 0 + +/******************************************************************************* + * Provide weak aliases for each Exception handler to the Default_Handler. + * As they are weak aliases, any function with the same name will override this definition. + * Note: For system exception handlers we don't want those references to be weak + * - we want to force someone to write those handlers. + *******************************************************************************/ + + .weak NMI_Handler + .thumb_set NMI_Handler,Default_Handler + + .weak HardFault_Handler + .thumb_set HardFault_Handler,Default_Handler + + .weak SVC_Handler + .thumb_set SVC_Handler,Default_Handler + + .weak PendSV_Handler + .thumb_set PendSV_Handler,Default_Handler + + .weak SysTick_Handler + .thumb_set SysTick_Handler,Default_Handler + + .weak IRQ0_RTC_Handler + .thumb_set IRQ0_RTC_Handler,Default_Handler + + .weak IRQ1_TMR0_Handler + .thumb_set IRQ1_TMR0_Handler,Default_Handler + + .weak IRQ2_SECURITY_Handler + .thumb_set IRQ2_SECURITY_Handler,Default_Handler + + .weak IRQ3_PROTOCOL_Handler + .thumb_set IRQ3_PROTOCOL_Handler,Default_Handler + + .weak IRQ4_APPS_Handler + .thumb_set IRQ4_APPS_Handler,Default_Handler + + .weak IRQ5_GPIO_Handler + .thumb_set IRQ5_GPIO_Handler,Default_Handler + + .weak IRQ6_DMA_Handler + .thumb_set IRQ6_DMA_Handler,Default_Handler + + .weak IRQ7_UART0_Handler + .thumb_set IRQ7_UART0_Handler,Default_Handler + + .weak IRQ8_UART1_Handler + .thumb_set IRQ8_UART1_Handler,Default_Handler + + .weak IRQ9_SSP0_Handler + .thumb_set IRQ9_SSP0_Handler,Default_Handler + + .weak IRQ10_SSP1_Handler + .thumb_set IRQ10_SSP1_Handler,Default_Handler + + .weak IRQ11_PWM0IN_Handler + .thumb_set IRQ11_PWM0IN_Handler,Default_Handler + + .weak IRQ12_PWM0OUT_Handler + .thumb_set IRQ12_PWM0OUT_Handler,Default_Handler + + .weak IRQ13_PWM1IN_Handler + .thumb_set IRQ13_PWM1IN_Handler,Default_Handler + + .weak IRQ14_PWM1OUT_Handler + .thumb_set IRQ14_PWM1OUT_Handler,Default_Handler + + .weak IRQ15_I2C_Handler + .thumb_set IRQ15_I2C_Handler,Default_Handler + + .weak IRQ16_LPUART_Handler + .thumb_set IRQ16_LPUART_Handler,Default_Handler + + .weak IRQ17_CAP_Handler + .thumb_set IRQ17_CAP_Handler,Default_Handler +
--- a/targets/TARGET_ublox/TARGET_HI2110/device/TOOLCHAIN_GCC_ARM/startup_hi2110.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,254 +0,0 @@ -/* mbed Microcontroller Library - * Copyright (c) 2016 u-blox - * - * Licensed under the Apache License, Version 2.0 (the "License"); - * you may not use this file except in compliance with the License. - * You may obtain a copy of the License at - * - * http://www.apache.org/licenses/LICENSE-2.0 - * - * Unless required by applicable law or agreed to in writing, software - * distributed under the License is distributed on an "AS IS" BASIS, - * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - * See the License for the specific language governing permissions and - * limitations under the License. - */ - .syntax unified - .cpu cortex-m0 - .fpu softvfp - .thumb - -/* Setup the stack - * Since it grows downward the stack_system is the first location is the highest address - * The first other usage should therefore be at stack_system + 4 - * Should the stack overflow, there would be a hard fault in the core - */ - - .section .stacks,"aw",%progbits - -#ifdef __STACK_SIZE - .equ Stack_Size, __STACK_SIZE -#else - .equ Stack_Size, 1024 -#endif - .globl Stack_Size - .globl __StackTop - .globl __StackLimit - .align 2 - .type stack_system, %object - .size stack_system, Stack_Size -stack_system_end: - .space Stack_Size - 4 -stack_system: - .space 4 - - -/* This is the code that gets called when the processor first - * starts execution following a reset event. Only the absolutely - * necessary set is performed, after which the application - * supplied main() routine is called. - */ - .section .text.Reset_Handler,"ax",%progbits - .weak Reset_Handler - .type Reset_Handler, %function - .thumb - .func Reset_Handler -Reset_Handler: - - /* Make sure SP is really at the start of the stack */ - ldr r0, =stack_system - msr msp, r0 - - /* Prefill the system stack with 0xefbeadde (or deafbeef in little endian) */ - ldr r1, =__SYSTEM_STACK_START__ - ldr r3, =__SYSTEM_STACK_END__ - subs r3, r3, r1 - beq .stack_fill_loop_end - ldr r2, =0xefbeadde -.stack_fill_loop: - str r2, [r1, #0] /* Store the quad octet initialisation value in r2 into address in r1 */ - adds r1, r1, #4 /* Increased address in r1 by a quad octet */ - subs r3, r3, #4 /* Decrease the number of bytes to do by a quad octet */ - bgt .stack_fill_loop /* Keep going until it is all done */ -.stack_fill_loop_end: - - /* setup .data section */ - ldr r1, =__data_start__ - ldr r2, =__data_load__ - ldr r3, =__data_size__ - cmp r3, #0 - beq .end_set_data_loop - -.set_data_loop: - ldrb r4, [r2, #0] /* Load the octet value into r4 from address in r2 */ - strb r4, [r1, #0] /* Store the octet value in r4 to address in r1 */ - adds r2, r2, #1 /* Move onto next octet */ - adds r1, r1, #1 - subs r3, r3, #1 /* Decrease the number of bytes to do by an octet */ - bgt .set_data_loop /* Keep going until it is all done */ -.end_set_data_loop: - - /* Call init function */ - ldr r0, =SystemInit - blx r0 - - /* Call C++ startup */ - ldr r0, =_start - bx r0 - bl . - - .size Reset_Handler, .-Reset_Handler - .endfunc - -/* This is the code that gets called when the processor receives an - * unexpected interrupt. This simply enters an infinite loop, preserving - * the system state for examination by a debugger. - */ - .section .text.Default_Handler,"ax",%progbits - .global Default_Handler - .func Default_Handler -Default_Handler: -Infinite_Loop: - b Infinite_Loop - - .endfunc - .size Default_Handler, .-Default_Handler - -/****************************************************************************** - * The minimal vector table for a Cortex M0+. Note that the proper constructs - * must be placed on this to ensure that it ends up at physical address 0x0000.0000. - *******************************************************************************/ - - .section .isr_vector,"a",%progbits - .type g_pfnVectors, %object - .size g_pfnVectors, .-g_pfnVectors - .global g_pfnVectors - -g_pfnVectors: - .word stack_system - .word Reset_Handler - .word NMI_Handler - .word HardFault_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word SVC_Handler - .word 0 - .word 0 - .word PendSV_Handler - .word SysTick_Handler - -/* External Interrupts */ - .word IRQ0_RTC_Handler - .word IRQ1_TMR0_Handler - .word IRQ2_SECURITY_Handler - .word IRQ3_PROTOCOL_Handler - .word IRQ4_APPS_Handler - .word IRQ5_GPIO_Handler - .word IRQ6_DMA_Handler - .word IRQ7_UART0_Handler - .word IRQ8_UART1_Handler - .word IRQ9_SSP0_Handler - .word IRQ10_SSP1_Handler - .word IRQ11_PWM0IN_Handler - .word IRQ12_PWM0OUT_Handler - .word IRQ13_PWM1IN_Handler - .word IRQ14_PWM1OUT_Handler - .word IRQ15_I2C_Handler - .word IRQ16_LPUART_Handler - .word IRQ17_CAP_Handler - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - .word 0 - -/******************************************************************************* - * Provide weak aliases for each Exception handler to the Default_Handler. - * As they are weak aliases, any function with the same name will override this definition. - * Note: For system exception handlers we don't want those references to be weak - * - we want to force someone to write those handlers. - *******************************************************************************/ - - .weak NMI_Handler - .thumb_set NMI_Handler,Default_Handler - - .weak HardFault_Handler - .thumb_set HardFault_Handler,Default_Handler - - .weak SVC_Handler - .thumb_set SVC_Handler,Default_Handler - - .weak PendSV_Handler - .thumb_set PendSV_Handler,Default_Handler - - .weak SysTick_Handler - .thumb_set SysTick_Handler,Default_Handler - - .weak IRQ0_RTC_Handler - .thumb_set IRQ0_RTC_Handler,Default_Handler - - .weak IRQ1_TMR0_Handler - .thumb_set IRQ1_TMR0_Handler,Default_Handler - - .weak IRQ2_SECURITY_Handler - .thumb_set IRQ2_SECURITY_Handler,Default_Handler - - .weak IRQ3_PROTOCOL_Handler - .thumb_set IRQ3_PROTOCOL_Handler,Default_Handler - - .weak IRQ4_APPS_Handler - .thumb_set IRQ4_APPS_Handler,Default_Handler - - .weak IRQ5_GPIO_Handler - .thumb_set IRQ5_GPIO_Handler,Default_Handler - - .weak IRQ6_DMA_Handler - .thumb_set IRQ6_DMA_Handler,Default_Handler - - .weak IRQ7_UART0_Handler - .thumb_set IRQ7_UART0_Handler,Default_Handler - - .weak IRQ8_UART1_Handler - .thumb_set IRQ8_UART1_Handler,Default_Handler - - .weak IRQ9_SSP0_Handler - .thumb_set IRQ9_SSP0_Handler,Default_Handler - - .weak IRQ10_SSP1_Handler - .thumb_set IRQ10_SSP1_Handler,Default_Handler - - .weak IRQ11_PWM0IN_Handler - .thumb_set IRQ11_PWM0IN_Handler,Default_Handler - - .weak IRQ12_PWM0OUT_Handler - .thumb_set IRQ12_PWM0OUT_Handler,Default_Handler - - .weak IRQ13_PWM1IN_Handler - .thumb_set IRQ13_PWM1IN_Handler,Default_Handler - - .weak IRQ14_PWM1OUT_Handler - .thumb_set IRQ14_PWM1OUT_Handler,Default_Handler - - .weak IRQ15_I2C_Handler - .thumb_set IRQ15_I2C_Handler,Default_Handler - - .weak IRQ16_LPUART_Handler - .thumb_set IRQ16_LPUART_Handler,Default_Handler - - .weak IRQ17_CAP_Handler - .thumb_set IRQ17_CAP_Handler,Default_Handler -
--- /dev/null Thu Jan 01 00:00:00 1970 +0000 +++ b/targets/TARGET_ublox/TARGET_HI2110/device/TOOLCHAIN_IAR/startup_hi2110.S Tue Mar 20 16:56:18 2018 +0000 @@ -0,0 +1,202 @@ +; mbed Microcontroller Library +; Copyright (c) 2016 u-blox. +; Licensed under the Apache License, Version 2.0 (the "License"); +; you may not use this file except in compliance with the License. +; You may obtain a copy of the License at +; http://www.apache.org/licenses/LICENSE-2.0 +; Unless required by applicable law or agreed to in writing, software +; distributed under the License is distributed on an "AS IS" BASIS, +; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +; See the License for the specific language governing permissions and +; limitations under the License. + +; Description message + + MODULE ?cstartup + + ; Stack size default : 1024 + ; Heap size default : 2048 + + ; Forward declaration of sections. + SECTION CSTACK:DATA:NOROOT(3) + + SECTION .intvec:CODE:NOROOT(2) + + EXTERN __iar_program_start + EXTERN SystemInit + PUBLIC __vector_table + PUBLIC __Vectors + PUBLIC __Vectors_End + PUBLIC __Vectors_Size + + DATA + +__vector_table + DCD sfe(CSTACK) + DCD Reset_Handler + DCD NMI_Handler + DCD HardFault_Handler + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD SVC_Handler + DCD 0 + DCD 0 + DCD PendSV_Handler + DCD SysTick_Handler + +; External Interrupts + DCD IRQ0_RTC_Handler + DCD IRQ1_TMR0_Handler + DCD IRQ2_SECURITY_Handler + DCD IRQ3_PROTOCOL_Handler + DCD IRQ4_APPS_Handler + DCD IRQ5_GPIO_Handler + DCD IRQ6_DMA_Handler + DCD IRQ7_UART0_Handler + DCD IRQ8_UART1_Handler + DCD IRQ9_SSP0_Handler + DCD IRQ10_SSP1_Handler + DCD IRQ11_PWM0IN_Handler + DCD IRQ12_PWM0OUT_Handler + DCD IRQ13_PWM1IN_Handler + DCD IRQ14_PWM1OUT_Handler + DCD IRQ15_I2C_Handler + DCD IRQ16_LPUART_Handler + DCD IRQ17_CAP_Handler + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD 0 + DCD 0 + +__Vectors_End +__Vectors EQU __vector_table +__Vectors_Size EQU __Vectors_End - __Vectors + +; Default handlers. + THUMB + + PUBWEAK Reset_Handler + SECTION .text:CODE:REORDER:NOROOT(2) +Reset_Handler + LDR R0, =SystemInit + BLX R0 + LDR R0, =__iar_program_start + BX R0 + + ; Dummy exception handlers + + PUBWEAK NMI_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +NMI_Handler + B . + + PUBWEAK HardFault_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +HardFault_Handler + B . + + PUBWEAK SVC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SVC_Handler + B . + + PUBWEAK PendSV_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +PendSV_Handler + B . + + PUBWEAK SysTick_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +SysTick_Handler + B . + + ; Dummy interrupt handlers + + PUBWEAK IRQ0_RTC_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +IRQ0_RTC_Handler + B . + PUBWEAK IRQ1_TMR0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +IRQ1_TMR0_Handler + B . + PUBWEAK IRQ2_SECURITY_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +IRQ2_SECURITY_Handler + B . + PUBWEAK IRQ3_PROTOCOL_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +IRQ3_PROTOCOL_Handler + B . + PUBWEAK IRQ4_APPS_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +IRQ4_APPS_Handler + B . + PUBWEAK IRQ5_GPIO_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +IRQ5_GPIO_Handler + B . + PUBWEAK IRQ6_DMA_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +IRQ6_DMA_Handler + B . + PUBWEAK IRQ7_UART0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +IRQ7_UART0_Handler + B . + PUBWEAK IRQ8_UART1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +IRQ8_UART1_Handler + B . + PUBWEAK IRQ9_SSP0_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +IRQ9_SSP0_Handler + B . + PUBWEAK IRQ10_SSP1_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +IRQ10_SSP1_Handler + B . + PUBWEAK IRQ11_PWM0IN_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +IRQ11_PWM0IN_Handler + B . + PUBWEAK IRQ12_PWM0OUT_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +IRQ12_PWM0OUT_Handler + B . + PUBWEAK IRQ13_PWM1IN_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +IRQ13_PWM1IN_Handler + B . + PUBWEAK IRQ14_PWM1OUT_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +IRQ14_PWM1OUT_Handler + B . + PUBWEAK IRQ15_I2C_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +IRQ15_I2C_Handler + B . + PUBWEAK IRQ16_LPUART_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +IRQ16_LPUART_Handler + B . + PUBWEAK IRQ17_CAP_Handler + SECTION .text:CODE:REORDER:NOROOT(1) +IRQ17_CAP_Handler + + END
--- a/targets/TARGET_ublox/TARGET_HI2110/device/TOOLCHAIN_IAR/startup_hi2110.s Fri Feb 16 16:09:33 2018 +0000 +++ /dev/null Thu Jan 01 00:00:00 1970 +0000 @@ -1,202 +0,0 @@ -; mbed Microcontroller Library -; Copyright (c) 2016 u-blox. -; Licensed under the Apache License, Version 2.0 (the "License"); -; you may not use this file except in compliance with the License. -; You may obtain a copy of the License at -; http://www.apache.org/licenses/LICENSE-2.0 -; Unless required by applicable law or agreed to in writing, software -; distributed under the License is distributed on an "AS IS" BASIS, -; WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. -; See the License for the specific language governing permissions and -; limitations under the License. - -; Description message - - MODULE ?cstartup - - ; Stack size default : 1024 - ; Heap size default : 2048 - - ; Forward declaration of sections. - SECTION CSTACK:DATA:NOROOT(3) - - SECTION .intvec:CODE:NOROOT(2) - - EXTERN __iar_program_start - EXTERN SystemInit - PUBLIC __vector_table - PUBLIC __Vectors - PUBLIC __Vectors_End - PUBLIC __Vectors_Size - - DATA - -__vector_table - DCD sfe(CSTACK) - DCD Reset_Handler - DCD NMI_Handler - DCD HardFault_Handler - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD SVC_Handler - DCD 0 - DCD 0 - DCD PendSV_Handler - DCD SysTick_Handler - -; External Interrupts - DCD IRQ0_RTC_Handler - DCD IRQ1_TMR0_Handler - DCD IRQ2_SECURITY_Handler - DCD IRQ3_PROTOCOL_Handler - DCD IRQ4_APPS_Handler - DCD IRQ5_GPIO_Handler - DCD IRQ6_DMA_Handler - DCD IRQ7_UART0_Handler - DCD IRQ8_UART1_Handler - DCD IRQ9_SSP0_Handler - DCD IRQ10_SSP1_Handler - DCD IRQ11_PWM0IN_Handler - DCD IRQ12_PWM0OUT_Handler - DCD IRQ13_PWM1IN_Handler - DCD IRQ14_PWM1OUT_Handler - DCD IRQ15_I2C_Handler - DCD IRQ16_LPUART_Handler - DCD IRQ17_CAP_Handler - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD 0 - DCD 0 - -__Vectors_End -__Vectors EQU __vector_table -__Vectors_Size EQU __Vectors_End - __Vectors - -; Default handlers. - THUMB - - PUBWEAK Reset_Handler - SECTION .text:CODE:REORDER:NOROOT(2) -Reset_Handler - LDR R0, =SystemInit - BLX R0 - LDR R0, =__iar_program_start - BX R0 - - ; Dummy exception handlers - - PUBWEAK NMI_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -NMI_Handler - B . - - PUBWEAK HardFault_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -HardFault_Handler - B . - - PUBWEAK SVC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SVC_Handler - B . - - PUBWEAK PendSV_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -PendSV_Handler - B . - - PUBWEAK SysTick_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -SysTick_Handler - B . - - ; Dummy interrupt handlers - - PUBWEAK IRQ0_RTC_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -IRQ0_RTC_Handler - B . - PUBWEAK IRQ1_TMR0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -IRQ1_TMR0_Handler - B . - PUBWEAK IRQ2_SECURITY_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -IRQ2_SECURITY_Handler - B . - PUBWEAK IRQ3_PROTOCOL_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -IRQ3_PROTOCOL_Handler - B . - PUBWEAK IRQ4_APPS_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -IRQ4_APPS_Handler - B . - PUBWEAK IRQ5_GPIO_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -IRQ5_GPIO_Handler - B . - PUBWEAK IRQ6_DMA_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -IRQ6_DMA_Handler - B . - PUBWEAK IRQ7_UART0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -IRQ7_UART0_Handler - B . - PUBWEAK IRQ8_UART1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -IRQ8_UART1_Handler - B . - PUBWEAK IRQ9_SSP0_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -IRQ9_SSP0_Handler - B . - PUBWEAK IRQ10_SSP1_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -IRQ10_SSP1_Handler - B . - PUBWEAK IRQ11_PWM0IN_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -IRQ11_PWM0IN_Handler - B . - PUBWEAK IRQ12_PWM0OUT_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -IRQ12_PWM0OUT_Handler - B . - PUBWEAK IRQ13_PWM1IN_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -IRQ13_PWM1IN_Handler - B . - PUBWEAK IRQ14_PWM1OUT_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -IRQ14_PWM1OUT_Handler - B . - PUBWEAK IRQ15_I2C_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -IRQ15_I2C_Handler - B . - PUBWEAK IRQ16_LPUART_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -IRQ16_LPUART_Handler - B . - PUBWEAK IRQ17_CAP_Handler - SECTION .text:CODE:REORDER:NOROOT(1) -IRQ17_CAP_Handler - - END
--- a/targets/targets.json Fri Feb 16 16:09:33 2018 +0000
+++ b/targets/targets.json Tue Mar 20 16:56:18 2018 +0000
@@ -710,6 +710,12 @@
"lse_available": {
"help": "Define if a Low Speed External xtal (LSE) is available on the board (0 = No, 1 = Yes). If Yes, the LSE will be used to clock the RTC, LPUART, ... otherwise the Low Speed Internal clock (LSI) will be used",
"value": "1"
+ },
+ "stdio_uart_tx": {
+ "help": "default TX STDIO pins is defined in PinNames.h file, but it can be overridden"
+ },
+ "stdio_uart_rx": {
+ "help": "default RX STDIO pins is defined in PinNames.h file, but it can be overridden"
}
},
"device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "I2C_ASYNCH", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "SPI_ASYNCH", "STDIO_MESSAGES"]
@@ -740,27 +746,28 @@
"release_versions": ["2", "5"],
"device_name" : "LPC54114J256BD64"
},
- "MCU_LPC546XX": {
+ "MCU_LPC546XX": {
"core": "Cortex-M4F",
"supported_toolchains": ["ARM", "IAR", "GCC_ARM"],
"extra_labels": ["NXP", "MCUXpresso_MCUS", "LPCXpresso", "LPC", "LPC546XX"],
"is_disk_virtual": true,
- "macros": ["CPU_LPC54618J512ET180", "FSL_RTOS_MBED"],
+ "macros": ["CPU_LPC54628J512ET180", "FSL_RTOS_MBED"],
"inherits": ["Target"],
"device_has": ["ANALOGIN", "I2C", "I2CSLAVE", "INTERRUPTIN", "PORTIN", "PORTINOUT", "PORTOUT", "RTC", "SERIAL", "SLEEP", "SPI", "SPISLAVE", "STDIO_MESSAGES"],
"features": ["LWIP"],
- "release_versions": ["2", "5"],
- "device_name" : "LPC54618J512ET180"
+ "device_name" : "LPC54628J512ET180"
},
"LPC546XX": {
"supported_form_factors": ["ARDUINO"],
"inherits": ["MCU_LPC546XX"],
- "detect_code": ["1056"]
+ "detect_code": ["1056"],
+ "release_versions": ["2", "5"]
},
"FF_LPC546XX": {
"inherits": ["MCU_LPC546XX"],
"extra_labels_remove" : ["LPCXpresso"],
- "detect_code": ["8081"]
+ "detect_code": ["8081"],
+ "release_versions": ["2", "5"]
},
"NUCLEO_F030R8": {
"inherits": ["FAMILY_STM32"],
@@ -1030,6 +1037,23 @@
"release_versions": ["2", "5"],
"device_name": "STM32F401RE"
},
+ "STEVAL_3DP001V1": {
+ "inherits": ["FAMILY_STM32"],
+ "core": "Cortex-M4F",
+ "extra_labels_add": ["STM32F4", "STM32F401xE", "STM32F401VE"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_XTAL|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "macros_add": ["USB_STM_HAL", "USBHOST_OTHER", "HSE_VALUE=25000000"],
+ "device_has_add": ["SERIAL_ASYNCH", "SERIAL_FC", "FLASH", "LOWPOWERTIMER"],
+ "overrides": {"lse_available": 0},
+ "release_versions": ["2", "5"],
+ "device_name": "STM32F401VE"
+ },
"NUCLEO_F410RB": {
"inherits": ["FAMILY_STM32"],
"supported_form_factors": ["ARDUINO", "MORPHO"],
@@ -1103,14 +1127,6 @@
"device_name": "STM32F412ZG",
"bootloader_supported": true,
"config": {
- "stdio_uart_tx": {
- "help": "Value PB_6",
- "value": "PB_6"
- },
- "stdio_uart_rx": {
- "help": "Value PB_7",
- "value": "PB_7"
- },
"clock_source": {
"help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSE_XTAL (need HW patch) | USE_PLL_HSI",
"value": "USE_PLL_HSI",
@@ -1194,7 +1210,7 @@
},
"extra_labels_add": ["STM32F4", "STM32F429", "STM32F429ZI", "STM32F429xx", "STM32F429xI"],
"macros_add": ["USB_STM_HAL", "USBHOST_OTHER"],
- "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC", "TRNG", "FLASH"],
+ "device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
"detect_code": ["0796"],
"features": ["LWIP"],
"release_versions": ["2", "5"],
@@ -1552,7 +1568,7 @@
}
},
"detect_code": ["0765"],
- "macros_add": ["USBHOST_OTHER"],
+ "macros_add": ["USBHOST_OTHER", "TWO_RAM_REGIONS"],
"device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
"release_versions": ["2", "5"],
"device_name": "STM32L476RG",
@@ -1571,7 +1587,7 @@
}
},
"detect_code": ["0766"],
- "macros_add": ["USBHOST_OTHER"],
+ "macros_add": ["USBHOST_OTHER", "TWO_RAM_REGIONS"],
"device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_ASYNCH", "SERIAL_FC", "TRNG", "FLASH"],
"release_versions": ["5"],
"device_name": "STM32L476JG"
@@ -1655,7 +1671,15 @@
"core": "Cortex-M4F",
"extra_labels_add": ["STM32F3", "STM32F303", "STM32F303xC", "STM32F303VC"],
"overrides": {"lse_available": 0},
- "supported_toolchains": ["GCC_ARM"],
+ "config": {
+ "clock_source": {
+ "help": "Mask value : USE_PLL_HSE_EXTC | USE_PLL_HSI",
+ "value": "USE_PLL_HSE_EXTC|USE_PLL_HSI",
+ "macro_name": "CLOCK_SOURCE"
+ }
+ },
+ "supported_toolchains": ["ARM", "uARM", "GCC_ARM", "IAR"],
+ "release_versions": ["2", "5"],
"device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC"],
"device_name": "STM32F303VC"
},
@@ -1855,7 +1879,7 @@
},
"supported_form_factors": ["ARDUINO"],
"detect_code": ["0764"],
- "macros_add": ["USBHOST_OTHER"],
+ "macros_add": ["USBHOST_OTHER", "TWO_RAM_REGIONS"],
"device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC", "TRNG", "FLASH"],
"release_versions": ["2", "5"],
"device_name": "STM32L475VG",
@@ -1877,7 +1901,7 @@
}
},
"detect_code": ["0820"],
- "macros_add": ["USBHOST_OTHER"],
+ "macros_add": ["USBHOST_OTHER", "TWO_RAM_REGIONS"],
"device_has_add": ["ANALOGOUT", "CAN", "LOWPOWERTIMER", "SERIAL_FC", "TRNG", "FLASH"],
"release_versions": ["2", "5"],
"device_name": "STM32L476VG",
@@ -1946,14 +1970,6 @@
"help": "Value: Defines how an on-board modem is wired up to the MCU, e.g., data connection can be a UART or USB and so forth.",
"value": 1,
"macro_name": "MODEM_ON_BOARD_UART"
- },
- "stdio_uart_tx": {
- "help": "Value PB_6",
- "value": "PB_6"
- },
- "stdio_uart_rx": {
- "help": "Value PB_7",
- "value": "PB_7"
}
},
"overrides": {
@@ -1999,16 +2015,12 @@
"hse_value": {
"value": "24000000",
"macro_name": "HSE_VALUE"
- },
- "stdio_uart_tx": {
- "help": "Value PA_2",
- "value": "PA_2"
- },
- "stdio_uart_rx": {
- "help": "Value PA_3",
- "value": "PA_3"
}
},
+ "overrides": {
+ "stdio_uart_tx": "PA_2",
+ "stdio_uart_rx": "PA_3"
+ },
"supported_toolchains": ["ARM", "GCC_ARM", "IAR"],
"device_has_add": ["ANALOGOUT", "FLASH"],
"release_versions": ["5"],
@@ -2052,28 +2064,32 @@
"supported_form_factors": ["ARDUINO"],
"release_versions": ["5"],
"config": {
- "stdio_uart_tx": {
- "help": "Value: D8(default) or D1",
- "value": "D8"
+ "stdio_uart_tx_help": {
+ "help": "Value: D8(default) or D1"
},
- "stdio_uart_rx": {
- "help": "Value: D2(default) or D0",
- "value": "D2"
+ "stdio_uart_rx_help": {
+ "help": "Value: D2(default) or D0"
}
+ },
+ "overrides": {
+ "stdio_uart_tx": "D8",
+ "stdio_uart_rx": "D2"
}
},
"MBED_CONNECT_ODIN": {
"inherits": ["MODULE_UBLOX_ODIN_W2"],
"release_versions": ["5"],
"config": {
- "stdio_uart_tx": {
- "help": "Value: PA_9(default) or PD_8",
- "value": "PA_9"
+ "stdio_uart_tx_help": {
+ "help": "Value: PA_9(default) or PD_8"
},
- "stdio_uart_rx": {
- "help": "Value: PA_10(default) or PD_9",
- "value": "PA_10"
+ "stdio_uart_rx_help": {
+ "help": "Value: PA_10(default) or PD_9"
}
+ },
+ "overrides": {
+ "stdio_uart_tx": "PA_9",
+ "stdio_uart_rx": "PA_10"
}
},
"MTB_UBLOX_ODIN_W2": {
@@ -2114,6 +2130,10 @@
"inherits": ["UBLOX_C030"],
"release_versions": ["5"]
},
+ "UBLOX_C030_R410M": {
+ "inherits": ["UBLOX_C030"],
+ "release_versions": ["5"]
+ },
"NZ32_SC151": {
"inherits": ["FAMILY_STM32"],
"core": "Cortex-M3",
@@ -3425,11 +3445,17 @@
"device_has": ["I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
"release_versions": ["2", "5"]
},
+ "OSHCHIP": {
+ "inherits": ["MCU_NRF51_32K_UNIFIED"],
+ "overrides": {"lf_clock_src": "NRF_LF_SRC_RC"},
+ "device_has": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "SERIAL", "SLEEP", "SPI", "SPISLAVE"],
+ "device_name": "nRF51822_xxAC"
+ },
"MCU_NRF52": {
"inherits": ["Target"],
"core": "Cortex-M4F",
"macros": ["NRF52", "TARGET_NRF52832", "BLE_STACK_SUPPORT_REQD", "SOFTDEVICE_PRESENT", "S132", "CMSIS_VECTAB_VIRTUAL", "CMSIS_VECTAB_VIRTUAL_HEADER_FILE=\"cmsis_nvic.h\"", "MBED_TICKLESS"],
- "device_has": ["STCLK_OFF_DURING_SLEEP"],
+ "device_has": ["STCLK_OFF_DURING_SLEEP", "ITM", "TRNG"],
"extra_labels": ["NORDIC", "MCU_NRF52", "MCU_NRF52832", "NRF5", "SDK11", "NRF52_COMMON"],
"OUTPUT_EXT": "hex",
"is_disk_virtual": true,
@@ -3483,7 +3509,7 @@
"supported_form_factors": ["ARDUINO"],
"inherits": ["MCU_NRF52"],
"macros_add": ["BOARD_PCA10040", "NRF52_PAN_12", "NRF52_PAN_15", "NRF52_PAN_58", "NRF52_PAN_55", "NRF52_PAN_54", "NRF52_PAN_31", "NRF52_PAN_30", "NRF52_PAN_51", "NRF52_PAN_36", "NRF52_PAN_53", "S132", "CONFIG_GPIO_AS_PINRESET", "BLE_STACK_SUPPORT_REQD", "SWI_DISABLE0", "NRF52_PAN_20", "NRF52_PAN_64", "NRF52_PAN_62", "NRF52_PAN_63"],
- "device_has_add": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
+ "device_has_add": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE", "FLASH"],
"release_versions": ["2", "5"],
"device_name": "nRF52832_xxAA"
},
@@ -3509,6 +3535,29 @@
}
}
},
+ "MTB_LAIRD_BL652": {
+ "inherits": ["MCU_NRF52"],
+ "macros_add": ["BOARD_PCA10040", "NRF52_PAN_12", "NRF52_PAN_15", "NRF52_PAN_58", "NRF52_PAN_55", "NRF52_PAN_54", "NRF52_PAN_31", "NRF52_PAN_30", "NRF52_PAN_51", "NRF52_PAN_36", "NRF52_PAN_53", "S132", "CONFIG_GPIO_AS_PINRESET", "BLE_STACK_SUPPORT_REQD", "SWI_DISABLE0", "NRF52_PAN_20", "NRF52_PAN_64", "NRF52_PAN_62", "NRF52_PAN_63"],
+ "device_has_add": ["ANALOGIN", "I2C", "I2C_ASYNCH", "INTERRUPTIN", "LOWPOWERTIMER", "PORTIN", "PORTINOUT", "PORTOUT", "PWMOUT", "RTC", "SERIAL", "SERIAL_ASYNCH", "SERIAL_FC", "SLEEP", "SPI", "SPI_ASYNCH", "SPISLAVE"],
+ "extra_labels_add": ["MTB_LAIRD_BL652"],
+ "release_versions": ["5"],
+ "device_name": "nRF52832_xxAA",
+ "bootloader_supported": true,
+ "config": {
+ "usb_tx": {
+ "help": "Value SIO_06",
+ "value": "SIO_6"
+ },
+ "usb_rx": {
+ "help": "Value SIO_08",
+ "value": "SIO_8"
+ }
+ },
+ "overrides": {
+ "lf_clock_src": "NRF_LF_SRC_RC",
+ "uart_hwfc": 0
+ }
+ },
"DELTA_DFBM_NQ620": {
"supported_form_factors": ["ARDUINO"],
"inherits": ["MCU_NRF52"],