Diff: targets/TARGET_NXP/TARGET_LPC11UXX/spi_api.c

Revision:

172:7d866c31b3c5

Parent:

170:19eb464bc2be

--- a/targets/TARGET_NXP/TARGET_LPC11UXX/spi_api.c	Wed Aug 16 18:27:13 2017 +0100
+++ b/targets/TARGET_NXP/TARGET_LPC11UXX/spi_api.c	Thu Aug 31 17:27:04 2017 +0100
@@ -76,7 +76,7 @@
     
     int FRF = 0;                   // FRF (frame format) = SPI
     uint32_t tmp = obj->spi->CR0;
-    tmp &= ~(0xFFFF);
+    tmp &= ~(0x00FF);              // Clear DSS, FRF, CPOL and CPHA [7:0]
     tmp |= DSS << 0
         | FRF << 4
         | SPO << 6
@@ -112,7 +112,7 @@
             obj->spi->CPSR = prescaler;
             
             // divider
-            obj->spi->CR0 &= ~(0xFFFF << 8);
+            obj->spi->CR0 &= ~(0xFF00);  // Clear SCR: Serial clock rate [15:8]
             obj->spi->CR0 |= (divider - 1) << 8;
             ssp_enable(obj);
             return;