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Dependents:   STM32_F103-C8T6basecanblink_led

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targets/TARGET_STM/TARGET_STM32F1/device/stm32f1xx_hal_eth.h@154:37f96f9d4de2, 2017-01-04 (annotated)

Committer:
<>
Date:
Wed Jan 04 16:58:05 2017 +0000
Revision:
154:37f96f9d4de2
Parent:
149:156823d33999
Child:
165:e614a9f1c9e2
This updates the lib to the mbed lib v133

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file stm32f1xx_hal_eth.h
<> 144:ef7eb2e8f9f7 4 * @author MCD Application Team
<> 154:37f96f9d4de2 5 * @version V1.0.5
<> 154:37f96f9d4de2 6 * @date 06-December-2016
<> 144:ef7eb2e8f9f7 7 * @brief Header file of ETH HAL module.
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 * @attention
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * <h2><center>&copy; COPYRIGHT(c) 2016 STMicroelectronics</center></h2>
<> 144:ef7eb2e8f9f7 12 *
<> 144:ef7eb2e8f9f7 13 * Redistribution and use in source and binary forms, with or without modification,
<> 144:ef7eb2e8f9f7 14 * are permitted provided that the following conditions are met:
<> 144:ef7eb2e8f9f7 15 * 1. Redistributions of source code must retain the above copyright notice,
<> 144:ef7eb2e8f9f7 16 * this list of conditions and the following disclaimer.
<> 144:ef7eb2e8f9f7 17 * 2. Redistributions in binary form must reproduce the above copyright notice,
<> 144:ef7eb2e8f9f7 18 * this list of conditions and the following disclaimer in the documentation
<> 144:ef7eb2e8f9f7 19 * and/or other materials provided with the distribution.
<> 144:ef7eb2e8f9f7 20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
<> 144:ef7eb2e8f9f7 21 * may be used to endorse or promote products derived from this software
<> 144:ef7eb2e8f9f7 22 * without specific prior written permission.
<> 144:ef7eb2e8f9f7 23 *
<> 144:ef7eb2e8f9f7 24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
<> 144:ef7eb2e8f9f7 25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
<> 144:ef7eb2e8f9f7 26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 144:ef7eb2e8f9f7 27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
<> 144:ef7eb2e8f9f7 28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
<> 144:ef7eb2e8f9f7 29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
<> 144:ef7eb2e8f9f7 30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
<> 144:ef7eb2e8f9f7 31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
<> 144:ef7eb2e8f9f7 32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
<> 144:ef7eb2e8f9f7 33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 144:ef7eb2e8f9f7 34 *
<> 144:ef7eb2e8f9f7 35 ******************************************************************************
<> 144:ef7eb2e8f9f7 36 */
<> 144:ef7eb2e8f9f7 37
<> 144:ef7eb2e8f9f7 38 /* Define to prevent recursive inclusion -------------------------------------*/
<> 144:ef7eb2e8f9f7 39 #ifndef __STM32F1xx_HAL_ETH_H
<> 144:ef7eb2e8f9f7 40 #define __STM32F1xx_HAL_ETH_H
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 43 extern "C" {
<> 144:ef7eb2e8f9f7 44 #endif
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 /* Includes ------------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 47 #include "stm32f1xx_hal_def.h"
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /** @addtogroup STM32F1xx_HAL_Driver
<> 144:ef7eb2e8f9f7 50 * @{
<> 144:ef7eb2e8f9f7 51 */
<> 144:ef7eb2e8f9f7 52 #if defined (STM32F107xC)
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 /** @addtogroup ETH
<> 144:ef7eb2e8f9f7 55 * @{
<> 144:ef7eb2e8f9f7 56 */
<> 144:ef7eb2e8f9f7 57
<> 144:ef7eb2e8f9f7 58 /** @addtogroup ETH_Private_Macros
<> 144:ef7eb2e8f9f7 59 * @{
<> 144:ef7eb2e8f9f7 60 */
<> 144:ef7eb2e8f9f7 61 #define IS_ETH_PHY_ADDRESS(ADDRESS) ((ADDRESS) <= 0x20)
<> 144:ef7eb2e8f9f7 62 #define IS_ETH_AUTONEGOTIATION(CMD) (((CMD) == ETH_AUTONEGOTIATION_ENABLE) || \
<> 144:ef7eb2e8f9f7 63 ((CMD) == ETH_AUTONEGOTIATION_DISABLE))
<> 144:ef7eb2e8f9f7 64 #define IS_ETH_SPEED(SPEED) (((SPEED) == ETH_SPEED_10M) || \
<> 144:ef7eb2e8f9f7 65 ((SPEED) == ETH_SPEED_100M))
<> 144:ef7eb2e8f9f7 66 #define IS_ETH_DUPLEX_MODE(MODE) (((MODE) == ETH_MODE_FULLDUPLEX) || \
<> 144:ef7eb2e8f9f7 67 ((MODE) == ETH_MODE_HALFDUPLEX))
<> 144:ef7eb2e8f9f7 68 #define IS_ETH_RX_MODE(MODE) (((MODE) == ETH_RXPOLLING_MODE) || \
<> 144:ef7eb2e8f9f7 69 ((MODE) == ETH_RXINTERRUPT_MODE))
<> 144:ef7eb2e8f9f7 70 #define IS_ETH_CHECKSUM_MODE(MODE) (((MODE) == ETH_CHECKSUM_BY_HARDWARE) || \
<> 144:ef7eb2e8f9f7 71 ((MODE) == ETH_CHECKSUM_BY_SOFTWARE))
<> 144:ef7eb2e8f9f7 72 #define IS_ETH_MEDIA_INTERFACE(MODE) (((MODE) == ETH_MEDIA_INTERFACE_MII) || \
<> 144:ef7eb2e8f9f7 73 ((MODE) == ETH_MEDIA_INTERFACE_RMII))
<> 144:ef7eb2e8f9f7 74 #define IS_ETH_WATCHDOG(CMD) (((CMD) == ETH_WATCHDOG_ENABLE) || \
<> 144:ef7eb2e8f9f7 75 ((CMD) == ETH_WATCHDOG_DISABLE))
<> 144:ef7eb2e8f9f7 76 #define IS_ETH_JABBER(CMD) (((CMD) == ETH_JABBER_ENABLE) || \
<> 144:ef7eb2e8f9f7 77 ((CMD) == ETH_JABBER_DISABLE))
<> 144:ef7eb2e8f9f7 78 #define IS_ETH_INTER_FRAME_GAP(GAP) (((GAP) == ETH_INTERFRAMEGAP_96BIT) || \
<> 144:ef7eb2e8f9f7 79 ((GAP) == ETH_INTERFRAMEGAP_88BIT) || \
<> 144:ef7eb2e8f9f7 80 ((GAP) == ETH_INTERFRAMEGAP_80BIT) || \
<> 144:ef7eb2e8f9f7 81 ((GAP) == ETH_INTERFRAMEGAP_72BIT) || \
<> 144:ef7eb2e8f9f7 82 ((GAP) == ETH_INTERFRAMEGAP_64BIT) || \
<> 144:ef7eb2e8f9f7 83 ((GAP) == ETH_INTERFRAMEGAP_56BIT) || \
<> 144:ef7eb2e8f9f7 84 ((GAP) == ETH_INTERFRAMEGAP_48BIT) || \
<> 144:ef7eb2e8f9f7 85 ((GAP) == ETH_INTERFRAMEGAP_40BIT))
<> 144:ef7eb2e8f9f7 86 #define IS_ETH_CARRIER_SENSE(CMD) (((CMD) == ETH_CARRIERSENCE_ENABLE) || \
<> 144:ef7eb2e8f9f7 87 ((CMD) == ETH_CARRIERSENCE_DISABLE))
<> 144:ef7eb2e8f9f7 88 #define IS_ETH_RECEIVE_OWN(CMD) (((CMD) == ETH_RECEIVEOWN_ENABLE) || \
<> 144:ef7eb2e8f9f7 89 ((CMD) == ETH_RECEIVEOWN_DISABLE))
<> 144:ef7eb2e8f9f7 90 #define IS_ETH_LOOPBACK_MODE(CMD) (((CMD) == ETH_LOOPBACKMODE_ENABLE) || \
<> 144:ef7eb2e8f9f7 91 ((CMD) == ETH_LOOPBACKMODE_DISABLE))
<> 144:ef7eb2e8f9f7 92 #define IS_ETH_CHECKSUM_OFFLOAD(CMD) (((CMD) == ETH_CHECKSUMOFFLAOD_ENABLE) || \
<> 144:ef7eb2e8f9f7 93 ((CMD) == ETH_CHECKSUMOFFLAOD_DISABLE))
<> 144:ef7eb2e8f9f7 94 #define IS_ETH_RETRY_TRANSMISSION(CMD) (((CMD) == ETH_RETRYTRANSMISSION_ENABLE) || \
<> 144:ef7eb2e8f9f7 95 ((CMD) == ETH_RETRYTRANSMISSION_DISABLE))
<> 144:ef7eb2e8f9f7 96 #define IS_ETH_AUTOMATIC_PADCRC_STRIP(CMD) (((CMD) == ETH_AUTOMATICPADCRCSTRIP_ENABLE) || \
<> 144:ef7eb2e8f9f7 97 ((CMD) == ETH_AUTOMATICPADCRCSTRIP_DISABLE))
<> 144:ef7eb2e8f9f7 98 #define IS_ETH_BACKOFF_LIMIT(LIMIT) (((LIMIT) == ETH_BACKOFFLIMIT_10) || \
<> 144:ef7eb2e8f9f7 99 ((LIMIT) == ETH_BACKOFFLIMIT_8) || \
<> 144:ef7eb2e8f9f7 100 ((LIMIT) == ETH_BACKOFFLIMIT_4) || \
<> 144:ef7eb2e8f9f7 101 ((LIMIT) == ETH_BACKOFFLIMIT_1))
<> 144:ef7eb2e8f9f7 102 #define IS_ETH_DEFERRAL_CHECK(CMD) (((CMD) == ETH_DEFFERRALCHECK_ENABLE) || \
<> 144:ef7eb2e8f9f7 103 ((CMD) == ETH_DEFFERRALCHECK_DISABLE))
<> 144:ef7eb2e8f9f7 104 #define IS_ETH_RECEIVE_ALL(CMD) (((CMD) == ETH_RECEIVEALL_ENABLE) || \
<> 144:ef7eb2e8f9f7 105 ((CMD) == ETH_RECEIVEAll_DISABLE))
<> 144:ef7eb2e8f9f7 106 #define IS_ETH_SOURCE_ADDR_FILTER(CMD) (((CMD) == ETH_SOURCEADDRFILTER_NORMAL_ENABLE) || \
<> 144:ef7eb2e8f9f7 107 ((CMD) == ETH_SOURCEADDRFILTER_INVERSE_ENABLE) || \
<> 144:ef7eb2e8f9f7 108 ((CMD) == ETH_SOURCEADDRFILTER_DISABLE))
<> 144:ef7eb2e8f9f7 109 #define IS_ETH_CONTROL_FRAMES(PASS) (((PASS) == ETH_PASSCONTROLFRAMES_BLOCKALL) || \
<> 144:ef7eb2e8f9f7 110 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDALL) || \
<> 144:ef7eb2e8f9f7 111 ((PASS) == ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER))
<> 144:ef7eb2e8f9f7 112 #define IS_ETH_BROADCAST_FRAMES_RECEPTION(CMD) (((CMD) == ETH_BROADCASTFRAMESRECEPTION_ENABLE) || \
<> 144:ef7eb2e8f9f7 113 ((CMD) == ETH_BROADCASTFRAMESRECEPTION_DISABLE))
<> 144:ef7eb2e8f9f7 114 #define IS_ETH_DESTINATION_ADDR_FILTER(FILTER) (((FILTER) == ETH_DESTINATIONADDRFILTER_NORMAL) || \
<> 144:ef7eb2e8f9f7 115 ((FILTER) == ETH_DESTINATIONADDRFILTER_INVERSE))
<> 144:ef7eb2e8f9f7 116 #define IS_ETH_PROMISCUOUS_MODE(CMD) (((CMD) == ETH_PROMISCUOUS_MODE_ENABLE) || \
<> 144:ef7eb2e8f9f7 117 ((CMD) == ETH_PROMISCUOUS_MODE_DISABLE))
<> 144:ef7eb2e8f9f7 118 #define IS_ETH_MULTICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE) || \
<> 144:ef7eb2e8f9f7 119 ((FILTER) == ETH_MULTICASTFRAMESFILTER_HASHTABLE) || \
<> 144:ef7eb2e8f9f7 120 ((FILTER) == ETH_MULTICASTFRAMESFILTER_PERFECT) || \
<> 144:ef7eb2e8f9f7 121 ((FILTER) == ETH_MULTICASTFRAMESFILTER_NONE))
<> 144:ef7eb2e8f9f7 122 #define IS_ETH_UNICAST_FRAMES_FILTER(FILTER) (((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE) || \
<> 144:ef7eb2e8f9f7 123 ((FILTER) == ETH_UNICASTFRAMESFILTER_HASHTABLE) || \
<> 144:ef7eb2e8f9f7 124 ((FILTER) == ETH_UNICASTFRAMESFILTER_PERFECT))
<> 144:ef7eb2e8f9f7 125 #define IS_ETH_PAUSE_TIME(TIME) ((TIME) <= 0xFFFF)
<> 144:ef7eb2e8f9f7 126 #define IS_ETH_ZEROQUANTA_PAUSE(CMD) (((CMD) == ETH_ZEROQUANTAPAUSE_ENABLE) || \
<> 144:ef7eb2e8f9f7 127 ((CMD) == ETH_ZEROQUANTAPAUSE_DISABLE))
<> 144:ef7eb2e8f9f7 128 #define IS_ETH_PAUSE_LOW_THRESHOLD(THRESHOLD) (((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS4) || \
<> 144:ef7eb2e8f9f7 129 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS28) || \
<> 144:ef7eb2e8f9f7 130 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS144) || \
<> 144:ef7eb2e8f9f7 131 ((THRESHOLD) == ETH_PAUSELOWTHRESHOLD_MINUS256))
<> 144:ef7eb2e8f9f7 132 #define IS_ETH_UNICAST_PAUSE_FRAME_DETECT(CMD) (((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_ENABLE) || \
<> 144:ef7eb2e8f9f7 133 ((CMD) == ETH_UNICASTPAUSEFRAMEDETECT_DISABLE))
<> 144:ef7eb2e8f9f7 134 #define IS_ETH_RECEIVE_FLOWCONTROL(CMD) (((CMD) == ETH_RECEIVEFLOWCONTROL_ENABLE) || \
<> 144:ef7eb2e8f9f7 135 ((CMD) == ETH_RECEIVEFLOWCONTROL_DISABLE))
<> 144:ef7eb2e8f9f7 136 #define IS_ETH_TRANSMIT_FLOWCONTROL(CMD) (((CMD) == ETH_TRANSMITFLOWCONTROL_ENABLE) || \
<> 144:ef7eb2e8f9f7 137 ((CMD) == ETH_TRANSMITFLOWCONTROL_DISABLE))
<> 144:ef7eb2e8f9f7 138 #define IS_ETH_VLAN_TAG_COMPARISON(COMPARISON) (((COMPARISON) == ETH_VLANTAGCOMPARISON_12BIT) || \
<> 144:ef7eb2e8f9f7 139 ((COMPARISON) == ETH_VLANTAGCOMPARISON_16BIT))
<> 144:ef7eb2e8f9f7 140 #define IS_ETH_VLAN_TAG_IDENTIFIER(IDENTIFIER) ((IDENTIFIER) <= 0xFFFF)
<> 144:ef7eb2e8f9f7 141 #define IS_ETH_MAC_ADDRESS0123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS0) || \
<> 144:ef7eb2e8f9f7 142 ((ADDRESS) == ETH_MAC_ADDRESS1) || \
<> 144:ef7eb2e8f9f7 143 ((ADDRESS) == ETH_MAC_ADDRESS2) || \
<> 144:ef7eb2e8f9f7 144 ((ADDRESS) == ETH_MAC_ADDRESS3))
<> 144:ef7eb2e8f9f7 145 #define IS_ETH_MAC_ADDRESS123(ADDRESS) (((ADDRESS) == ETH_MAC_ADDRESS1) || \
<> 144:ef7eb2e8f9f7 146 ((ADDRESS) == ETH_MAC_ADDRESS2) || \
<> 144:ef7eb2e8f9f7 147 ((ADDRESS) == ETH_MAC_ADDRESS3))
<> 144:ef7eb2e8f9f7 148 #define IS_ETH_MAC_ADDRESS_FILTER(FILTER) (((FILTER) == ETH_MAC_ADDRESSFILTER_SA) || \
<> 144:ef7eb2e8f9f7 149 ((FILTER) == ETH_MAC_ADDRESSFILTER_DA))
<> 144:ef7eb2e8f9f7 150 #define IS_ETH_MAC_ADDRESS_MASK(MASK) (((MASK) == ETH_MAC_ADDRESSMASK_BYTE6) || \
<> 144:ef7eb2e8f9f7 151 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE5) || \
<> 144:ef7eb2e8f9f7 152 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE4) || \
<> 144:ef7eb2e8f9f7 153 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE3) || \
<> 144:ef7eb2e8f9f7 154 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE2) || \
<> 144:ef7eb2e8f9f7 155 ((MASK) == ETH_MAC_ADDRESSMASK_BYTE1))
<> 144:ef7eb2e8f9f7 156 #define IS_ETH_DROP_TCPIP_CHECKSUM_FRAME(CMD) (((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE) || \
<> 144:ef7eb2e8f9f7 157 ((CMD) == ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE))
<> 144:ef7eb2e8f9f7 158 #define IS_ETH_RECEIVE_STORE_FORWARD(CMD) (((CMD) == ETH_RECEIVESTOREFORWARD_ENABLE) || \
<> 144:ef7eb2e8f9f7 159 ((CMD) == ETH_RECEIVESTOREFORWARD_DISABLE))
<> 144:ef7eb2e8f9f7 160 #define IS_ETH_FLUSH_RECEIVE_FRAME(CMD) (((CMD) == ETH_FLUSHRECEIVEDFRAME_ENABLE) || \
<> 144:ef7eb2e8f9f7 161 ((CMD) == ETH_FLUSHRECEIVEDFRAME_DISABLE))
<> 144:ef7eb2e8f9f7 162 #define IS_ETH_TRANSMIT_STORE_FORWARD(CMD) (((CMD) == ETH_TRANSMITSTOREFORWARD_ENABLE) || \
<> 144:ef7eb2e8f9f7 163 ((CMD) == ETH_TRANSMITSTOREFORWARD_DISABLE))
<> 144:ef7eb2e8f9f7 164 #define IS_ETH_TRANSMIT_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_64BYTES) || \
<> 144:ef7eb2e8f9f7 165 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_128BYTES) || \
<> 144:ef7eb2e8f9f7 166 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_192BYTES) || \
<> 144:ef7eb2e8f9f7 167 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_256BYTES) || \
<> 144:ef7eb2e8f9f7 168 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_40BYTES) || \
<> 144:ef7eb2e8f9f7 169 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_32BYTES) || \
<> 144:ef7eb2e8f9f7 170 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_24BYTES) || \
<> 144:ef7eb2e8f9f7 171 ((THRESHOLD) == ETH_TRANSMITTHRESHOLDCONTROL_16BYTES))
<> 144:ef7eb2e8f9f7 172 #define IS_ETH_FORWARD_ERROR_FRAMES(CMD) (((CMD) == ETH_FORWARDERRORFRAMES_ENABLE) || \
<> 144:ef7eb2e8f9f7 173 ((CMD) == ETH_FORWARDERRORFRAMES_DISABLE))
<> 144:ef7eb2e8f9f7 174 #define IS_ETH_FORWARD_UNDERSIZED_GOOD_FRAMES(CMD) (((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE) || \
<> 144:ef7eb2e8f9f7 175 ((CMD) == ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE))
<> 144:ef7eb2e8f9f7 176 #define IS_ETH_RECEIVE_THRESHOLD_CONTROL(THRESHOLD) (((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES) || \
<> 144:ef7eb2e8f9f7 177 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES) || \
<> 144:ef7eb2e8f9f7 178 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES) || \
<> 144:ef7eb2e8f9f7 179 ((THRESHOLD) == ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES))
<> 144:ef7eb2e8f9f7 180 #define IS_ETH_SECOND_FRAME_OPERATE(CMD) (((CMD) == ETH_SECONDFRAMEOPERARTE_ENABLE) || \
<> 144:ef7eb2e8f9f7 181 ((CMD) == ETH_SECONDFRAMEOPERARTE_DISABLE))
<> 144:ef7eb2e8f9f7 182 #define IS_ETH_ADDRESS_ALIGNED_BEATS(CMD) (((CMD) == ETH_ADDRESSALIGNEDBEATS_ENABLE) || \
<> 144:ef7eb2e8f9f7 183 ((CMD) == ETH_ADDRESSALIGNEDBEATS_DISABLE))
<> 144:ef7eb2e8f9f7 184 #define IS_ETH_FIXED_BURST(CMD) (((CMD) == ETH_FIXEDBURST_ENABLE) || \
<> 144:ef7eb2e8f9f7 185 ((CMD) == ETH_FIXEDBURST_DISABLE))
<> 144:ef7eb2e8f9f7 186 #define IS_ETH_RXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_RXDMABURSTLENGTH_1BEAT) || \
<> 144:ef7eb2e8f9f7 187 ((LENGTH) == ETH_RXDMABURSTLENGTH_2BEAT) || \
<> 144:ef7eb2e8f9f7 188 ((LENGTH) == ETH_RXDMABURSTLENGTH_4BEAT) || \
<> 144:ef7eb2e8f9f7 189 ((LENGTH) == ETH_RXDMABURSTLENGTH_8BEAT) || \
<> 144:ef7eb2e8f9f7 190 ((LENGTH) == ETH_RXDMABURSTLENGTH_16BEAT) || \
<> 144:ef7eb2e8f9f7 191 ((LENGTH) == ETH_RXDMABURSTLENGTH_32BEAT) || \
<> 144:ef7eb2e8f9f7 192 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_4BEAT) || \
<> 144:ef7eb2e8f9f7 193 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_8BEAT) || \
<> 144:ef7eb2e8f9f7 194 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_16BEAT) || \
<> 144:ef7eb2e8f9f7 195 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_32BEAT) || \
<> 144:ef7eb2e8f9f7 196 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_64BEAT) || \
<> 144:ef7eb2e8f9f7 197 ((LENGTH) == ETH_RXDMABURSTLENGTH_4XPBL_128BEAT))
<> 144:ef7eb2e8f9f7 198 #define IS_ETH_TXDMA_BURST_LENGTH(LENGTH) (((LENGTH) == ETH_TXDMABURSTLENGTH_1BEAT) || \
<> 144:ef7eb2e8f9f7 199 ((LENGTH) == ETH_TXDMABURSTLENGTH_2BEAT) || \
<> 144:ef7eb2e8f9f7 200 ((LENGTH) == ETH_TXDMABURSTLENGTH_4BEAT) || \
<> 144:ef7eb2e8f9f7 201 ((LENGTH) == ETH_TXDMABURSTLENGTH_8BEAT) || \
<> 144:ef7eb2e8f9f7 202 ((LENGTH) == ETH_TXDMABURSTLENGTH_16BEAT) || \
<> 144:ef7eb2e8f9f7 203 ((LENGTH) == ETH_TXDMABURSTLENGTH_32BEAT) || \
<> 144:ef7eb2e8f9f7 204 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_4BEAT) || \
<> 144:ef7eb2e8f9f7 205 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_8BEAT) || \
<> 144:ef7eb2e8f9f7 206 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_16BEAT) || \
<> 144:ef7eb2e8f9f7 207 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_32BEAT) || \
<> 144:ef7eb2e8f9f7 208 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_64BEAT) || \
<> 144:ef7eb2e8f9f7 209 ((LENGTH) == ETH_TXDMABURSTLENGTH_4XPBL_128BEAT))
<> 144:ef7eb2e8f9f7 210 #define IS_ETH_DMA_DESC_SKIP_LENGTH(LENGTH) ((LENGTH) <= 0x1F)
<> 144:ef7eb2e8f9f7 211 #define IS_ETH_DMA_ARBITRATION_ROUNDROBIN_RXTX(RATIO) (((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1) || \
<> 144:ef7eb2e8f9f7 212 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1) || \
<> 144:ef7eb2e8f9f7 213 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1) || \
<> 144:ef7eb2e8f9f7 214 ((RATIO) == ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1) || \
<> 144:ef7eb2e8f9f7 215 ((RATIO) == ETH_DMAARBITRATION_RXPRIORTX))
<> 144:ef7eb2e8f9f7 216
<> 144:ef7eb2e8f9f7 217 #define IS_ETH_DMA_TXDESC_SEGMENT(SEGMENT) (((SEGMENT) == ETH_DMATXDESC_LASTSEGMENTS) || \
<> 144:ef7eb2e8f9f7 218 ((SEGMENT) == ETH_DMATXDESC_FIRSTSEGMENT))
<> 144:ef7eb2e8f9f7 219 #define IS_ETH_DMA_TXDESC_CHECKSUM(CHECKSUM) (((CHECKSUM) == ETH_DMATXDESC_CHECKSUMBYPASS) || \
<> 144:ef7eb2e8f9f7 220 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMIPV4HEADER) || \
<> 144:ef7eb2e8f9f7 221 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT) || \
<> 144:ef7eb2e8f9f7 222 ((CHECKSUM) == ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL))
<> 144:ef7eb2e8f9f7 223 #define IS_ETH_DMATXDESC_BUFFER_SIZE(SIZE) ((SIZE) <= 0x1FFF)
<> 144:ef7eb2e8f9f7 224
<> 144:ef7eb2e8f9f7 225 #define IS_ETH_DMA_RXDESC_BUFFER(BUFFER) (((BUFFER) == ETH_DMARXDESC_BUFFER1) || \
<> 144:ef7eb2e8f9f7 226 ((BUFFER) == ETH_DMARXDESC_BUFFER2))
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 #define IS_ETH_DMA_GET_OVERFLOW(OVERFLOW) (((OVERFLOW) == ETH_DMA_OVERFLOW_RXFIFOCOUNTER) || \
<> 144:ef7eb2e8f9f7 229 ((OVERFLOW) == ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER))
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 /**
<> 144:ef7eb2e8f9f7 232 * @}
<> 144:ef7eb2e8f9f7 233 */
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 /** @addtogroup ETH_Private_Constants
<> 144:ef7eb2e8f9f7 236 * @{
<> 144:ef7eb2e8f9f7 237 */
<> 144:ef7eb2e8f9f7 238 /* Delay to wait when writing to some Ethernet registers */
<> 144:ef7eb2e8f9f7 239 #define ETH_REG_WRITE_DELAY ((uint32_t)0x00000001)
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 /* ETHERNET Errors */
<> 144:ef7eb2e8f9f7 242 #define ETH_SUCCESS ((uint32_t)0)
<> 144:ef7eb2e8f9f7 243 #define ETH_ERROR ((uint32_t)1)
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 /* ETHERNET DMA Tx descriptors Collision Count Shift */
<> 144:ef7eb2e8f9f7 246 #define ETH_DMATXDESC_COLLISION_COUNTSHIFT ((uint32_t)3)
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 /* ETHERNET DMA Tx descriptors Buffer2 Size Shift */
<> 144:ef7eb2e8f9f7 249 #define ETH_DMATXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 /* ETHERNET DMA Rx descriptors Frame Length Shift */
<> 144:ef7eb2e8f9f7 252 #define ETH_DMARXDESC_FRAME_LENGTHSHIFT ((uint32_t)16)
<> 144:ef7eb2e8f9f7 253
<> 144:ef7eb2e8f9f7 254 /* ETHERNET DMA Rx descriptors Buffer2 Size Shift */
<> 144:ef7eb2e8f9f7 255 #define ETH_DMARXDESC_BUFFER2_SIZESHIFT ((uint32_t)16)
<> 144:ef7eb2e8f9f7 256
<> 144:ef7eb2e8f9f7 257 /* ETHERNET DMA Rx descriptors Frame length Shift */
<> 144:ef7eb2e8f9f7 258 #define ETH_DMARXDESC_FRAMELENGTHSHIFT ((uint32_t)16)
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 /* ETHERNET MAC address offsets */
<> 144:ef7eb2e8f9f7 261 #define ETH_MAC_ADDR_HBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x40) /* ETHERNET MAC address high offset */
<> 144:ef7eb2e8f9f7 262 #define ETH_MAC_ADDR_LBASE (uint32_t)(ETH_MAC_BASE + (uint32_t)0x44) /* ETHERNET MAC address low offset */
<> 144:ef7eb2e8f9f7 263
<> 144:ef7eb2e8f9f7 264 /* ETHERNET MACMIIAR register Mask */
<> 144:ef7eb2e8f9f7 265 #define ETH_MACMIIAR_CR_MASK ((uint32_t)0xFFFFFFE3)
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267 /* ETHERNET MACCR register Mask */
<> 144:ef7eb2e8f9f7 268 #define ETH_MACCR_CLEAR_MASK ((uint32_t)0xFF20810F)
<> 144:ef7eb2e8f9f7 269
<> 144:ef7eb2e8f9f7 270 /* ETHERNET MACFCR register Mask */
<> 144:ef7eb2e8f9f7 271 #define ETH_MACFCR_CLEAR_MASK ((uint32_t)0x0000FF41)
<> 144:ef7eb2e8f9f7 272
<> 144:ef7eb2e8f9f7 273 /* ETHERNET DMAOMR register Mask */
<> 144:ef7eb2e8f9f7 274 #define ETH_DMAOMR_CLEAR_MASK ((uint32_t)0xF8DE3F23)
<> 144:ef7eb2e8f9f7 275
<> 144:ef7eb2e8f9f7 276 /* ETHERNET Remote Wake-up frame register length */
<> 144:ef7eb2e8f9f7 277 #define ETH_WAKEUP_REGISTER_LENGTH 8
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279 /* ETHERNET Missed frames counter Shift */
<> 144:ef7eb2e8f9f7 280 #define ETH_DMA_RX_OVERFLOW_MISSEDFRAMES_COUNTERSHIFT 17
<> 144:ef7eb2e8f9f7 281 /**
<> 144:ef7eb2e8f9f7 282 * @}
<> 144:ef7eb2e8f9f7 283 */
<> 144:ef7eb2e8f9f7 284
<> 144:ef7eb2e8f9f7 285 /* Exported types ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 286 /** @defgroup ETH_Exported_Types ETH Exported Types
<> 144:ef7eb2e8f9f7 287 * @{
<> 144:ef7eb2e8f9f7 288 */
<> 144:ef7eb2e8f9f7 289
<> 144:ef7eb2e8f9f7 290 /**
<> 144:ef7eb2e8f9f7 291 * @brief HAL State structures definition
<> 144:ef7eb2e8f9f7 292 */
<> 144:ef7eb2e8f9f7 293 typedef enum
<> 144:ef7eb2e8f9f7 294 {
<> 144:ef7eb2e8f9f7 295 HAL_ETH_STATE_RESET = 0x00, /*!< Peripheral not yet Initialized or disabled */
<> 144:ef7eb2e8f9f7 296 HAL_ETH_STATE_READY = 0x01, /*!< Peripheral Initialized and ready for use */
<> 144:ef7eb2e8f9f7 297 HAL_ETH_STATE_BUSY = 0x02, /*!< an internal process is ongoing */
<> 144:ef7eb2e8f9f7 298 HAL_ETH_STATE_BUSY_TX = 0x12, /*!< Data Transmission process is ongoing */
<> 144:ef7eb2e8f9f7 299 HAL_ETH_STATE_BUSY_RX = 0x22, /*!< Data Reception process is ongoing */
<> 144:ef7eb2e8f9f7 300 HAL_ETH_STATE_BUSY_TX_RX = 0x32, /*!< Data Transmission and Reception process is ongoing */
<> 144:ef7eb2e8f9f7 301 HAL_ETH_STATE_BUSY_WR = 0x42, /*!< Write process is ongoing */
<> 144:ef7eb2e8f9f7 302 HAL_ETH_STATE_BUSY_RD = 0x82, /*!< Read process is ongoing */
<> 144:ef7eb2e8f9f7 303 HAL_ETH_STATE_TIMEOUT = 0x03, /*!< Timeout state */
<> 144:ef7eb2e8f9f7 304 HAL_ETH_STATE_ERROR = 0x04 /*!< Reception process is ongoing */
<> 144:ef7eb2e8f9f7 305 }HAL_ETH_StateTypeDef;
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 /**
<> 144:ef7eb2e8f9f7 308 * @brief ETH Init Structure definition
<> 144:ef7eb2e8f9f7 309 */
<> 144:ef7eb2e8f9f7 310
<> 144:ef7eb2e8f9f7 311 typedef struct
<> 144:ef7eb2e8f9f7 312 {
<> 144:ef7eb2e8f9f7 313 uint32_t AutoNegotiation; /*!< Selects or not the AutoNegotiation mode for the external PHY
<> 144:ef7eb2e8f9f7 314 The AutoNegotiation allows an automatic setting of the Speed (10/100Mbps)
<> 144:ef7eb2e8f9f7 315 and the mode (half/full-duplex).
<> 144:ef7eb2e8f9f7 316 This parameter can be a value of @ref ETH_AutoNegotiation */
<> 144:ef7eb2e8f9f7 317
<> 144:ef7eb2e8f9f7 318 uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps.
<> 144:ef7eb2e8f9f7 319 This parameter can be a value of @ref ETH_Speed */
<> 144:ef7eb2e8f9f7 320
<> 144:ef7eb2e8f9f7 321 uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
<> 144:ef7eb2e8f9f7 322 This parameter can be a value of @ref ETH_Duplex_Mode */
<> 144:ef7eb2e8f9f7 323
<> 144:ef7eb2e8f9f7 324 uint16_t PhyAddress; /*!< Ethernet PHY address.
<> 144:ef7eb2e8f9f7 325 This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
<> 144:ef7eb2e8f9f7 326
<> 144:ef7eb2e8f9f7 327 uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
<> 144:ef7eb2e8f9f7 328
<> 144:ef7eb2e8f9f7 329 uint32_t RxMode; /*!< Selects the Ethernet Rx mode: Polling mode, Interrupt mode.
<> 144:ef7eb2e8f9f7 330 This parameter can be a value of @ref ETH_Rx_Mode */
<> 144:ef7eb2e8f9f7 331
<> 144:ef7eb2e8f9f7 332 uint32_t ChecksumMode; /*!< Selects if the checksum is check by hardware or by software.
<> 144:ef7eb2e8f9f7 333 This parameter can be a value of @ref ETH_Checksum_Mode */
<> 144:ef7eb2e8f9f7 334
<> 144:ef7eb2e8f9f7 335 uint32_t MediaInterface ; /*!< Selects the media-independent interface or the reduced media-independent interface.
<> 144:ef7eb2e8f9f7 336 This parameter can be a value of @ref ETH_Media_Interface */
<> 144:ef7eb2e8f9f7 337
<> 144:ef7eb2e8f9f7 338 } ETH_InitTypeDef;
<> 144:ef7eb2e8f9f7 339
<> 144:ef7eb2e8f9f7 340
<> 144:ef7eb2e8f9f7 341 /**
<> 144:ef7eb2e8f9f7 342 * @brief ETH MAC Configuration Structure definition
<> 144:ef7eb2e8f9f7 343 */
<> 144:ef7eb2e8f9f7 344
<> 144:ef7eb2e8f9f7 345 typedef struct
<> 144:ef7eb2e8f9f7 346 {
<> 144:ef7eb2e8f9f7 347 uint32_t Watchdog; /*!< Selects or not the Watchdog timer
<> 144:ef7eb2e8f9f7 348 When enabled, the MAC allows no more then 2048 bytes to be received.
<> 144:ef7eb2e8f9f7 349 When disabled, the MAC can receive up to 16384 bytes.
<> 144:ef7eb2e8f9f7 350 This parameter can be a value of @ref ETH_Watchdog */
<> 144:ef7eb2e8f9f7 351
<> 144:ef7eb2e8f9f7 352 uint32_t Jabber; /*!< Selects or not Jabber timer
<> 144:ef7eb2e8f9f7 353 When enabled, the MAC allows no more then 2048 bytes to be sent.
<> 144:ef7eb2e8f9f7 354 When disabled, the MAC can send up to 16384 bytes.
<> 144:ef7eb2e8f9f7 355 This parameter can be a value of @ref ETH_Jabber */
<> 144:ef7eb2e8f9f7 356
<> 144:ef7eb2e8f9f7 357 uint32_t InterFrameGap; /*!< Selects the minimum IFG between frames during transmission.
<> 144:ef7eb2e8f9f7 358 This parameter can be a value of @ref ETH_Inter_Frame_Gap */
<> 144:ef7eb2e8f9f7 359
<> 144:ef7eb2e8f9f7 360 uint32_t CarrierSense; /*!< Selects or not the Carrier Sense.
<> 144:ef7eb2e8f9f7 361 This parameter can be a value of @ref ETH_Carrier_Sense */
<> 144:ef7eb2e8f9f7 362
<> 144:ef7eb2e8f9f7 363 uint32_t ReceiveOwn; /*!< Selects or not the ReceiveOwn,
<> 144:ef7eb2e8f9f7 364 ReceiveOwn allows the reception of frames when the TX_EN signal is asserted
<> 144:ef7eb2e8f9f7 365 in Half-Duplex mode.
<> 144:ef7eb2e8f9f7 366 This parameter can be a value of @ref ETH_Receive_Own */
<> 144:ef7eb2e8f9f7 367
<> 144:ef7eb2e8f9f7 368 uint32_t LoopbackMode; /*!< Selects or not the internal MAC MII Loopback mode.
<> 144:ef7eb2e8f9f7 369 This parameter can be a value of @ref ETH_Loop_Back_Mode */
<> 144:ef7eb2e8f9f7 370
<> 144:ef7eb2e8f9f7 371 uint32_t ChecksumOffload; /*!< Selects or not the IPv4 checksum checking for received frame payloads' TCP/UDP/ICMP headers.
<> 144:ef7eb2e8f9f7 372 This parameter can be a value of @ref ETH_Checksum_Offload */
<> 144:ef7eb2e8f9f7 373
<> 144:ef7eb2e8f9f7 374 uint32_t RetryTransmission; /*!< Selects or not the MAC attempt retries transmission, based on the settings of BL,
<> 144:ef7eb2e8f9f7 375 when a collision occurs (Half-Duplex mode).
<> 144:ef7eb2e8f9f7 376 This parameter can be a value of @ref ETH_Retry_Transmission */
<> 144:ef7eb2e8f9f7 377
<> 144:ef7eb2e8f9f7 378 uint32_t AutomaticPadCRCStrip; /*!< Selects or not the Automatic MAC Pad/CRC Stripping.
<> 144:ef7eb2e8f9f7 379 This parameter can be a value of @ref ETH_Automatic_Pad_CRC_Strip */
<> 144:ef7eb2e8f9f7 380
<> 144:ef7eb2e8f9f7 381 uint32_t BackOffLimit; /*!< Selects the BackOff limit value.
<> 144:ef7eb2e8f9f7 382 This parameter can be a value of @ref ETH_Back_Off_Limit */
<> 144:ef7eb2e8f9f7 383
<> 144:ef7eb2e8f9f7 384 uint32_t DeferralCheck; /*!< Selects or not the deferral check function (Half-Duplex mode).
<> 144:ef7eb2e8f9f7 385 This parameter can be a value of @ref ETH_Deferral_Check */
<> 144:ef7eb2e8f9f7 386
<> 144:ef7eb2e8f9f7 387 uint32_t ReceiveAll; /*!< Selects or not all frames reception by the MAC (No filtering).
<> 144:ef7eb2e8f9f7 388 This parameter can be a value of @ref ETH_Receive_All */
<> 144:ef7eb2e8f9f7 389
<> 144:ef7eb2e8f9f7 390 uint32_t SourceAddrFilter; /*!< Selects the Source Address Filter mode.
<> 144:ef7eb2e8f9f7 391 This parameter can be a value of @ref ETH_Source_Addr_Filter */
<> 144:ef7eb2e8f9f7 392
<> 144:ef7eb2e8f9f7 393 uint32_t PassControlFrames; /*!< Sets the forwarding mode of the control frames (including unicast and multicast PAUSE frames)
<> 144:ef7eb2e8f9f7 394 This parameter can be a value of @ref ETH_Pass_Control_Frames */
<> 144:ef7eb2e8f9f7 395
<> 144:ef7eb2e8f9f7 396 uint32_t BroadcastFramesReception; /*!< Selects or not the reception of Broadcast Frames.
<> 144:ef7eb2e8f9f7 397 This parameter can be a value of @ref ETH_Broadcast_Frames_Reception */
<> 144:ef7eb2e8f9f7 398
<> 144:ef7eb2e8f9f7 399 uint32_t DestinationAddrFilter; /*!< Sets the destination filter mode for both unicast and multicast frames.
<> 144:ef7eb2e8f9f7 400 This parameter can be a value of @ref ETH_Destination_Addr_Filter */
<> 144:ef7eb2e8f9f7 401
<> 144:ef7eb2e8f9f7 402 uint32_t PromiscuousMode; /*!< Selects or not the Promiscuous Mode
<> 144:ef7eb2e8f9f7 403 This parameter can be a value of @ref ETH_Promiscuous_Mode */
<> 144:ef7eb2e8f9f7 404
<> 144:ef7eb2e8f9f7 405 uint32_t MulticastFramesFilter; /*!< Selects the Multicast Frames filter mode: None/HashTableFilter/PerfectFilter/PerfectHashTableFilter.
<> 144:ef7eb2e8f9f7 406 This parameter can be a value of @ref ETH_Multicast_Frames_Filter */
<> 144:ef7eb2e8f9f7 407
<> 144:ef7eb2e8f9f7 408 uint32_t UnicastFramesFilter; /*!< Selects the Unicast Frames filter mode: HashTableFilter/PerfectFilter/PerfectHashTableFilter.
<> 144:ef7eb2e8f9f7 409 This parameter can be a value of @ref ETH_Unicast_Frames_Filter */
<> 144:ef7eb2e8f9f7 410
<> 144:ef7eb2e8f9f7 411 uint32_t HashTableHigh; /*!< This field holds the higher 32 bits of Hash table.
<> 144:ef7eb2e8f9f7 412 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
<> 144:ef7eb2e8f9f7 413
<> 144:ef7eb2e8f9f7 414 uint32_t HashTableLow; /*!< This field holds the lower 32 bits of Hash table.
<> 144:ef7eb2e8f9f7 415 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFFFFFF */
<> 144:ef7eb2e8f9f7 416
<> 144:ef7eb2e8f9f7 417 uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control frame.
<> 144:ef7eb2e8f9f7 418 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */
<> 144:ef7eb2e8f9f7 419
<> 144:ef7eb2e8f9f7 420 uint32_t ZeroQuantaPause; /*!< Selects or not the automatic generation of Zero-Quanta Pause Control frames.
<> 144:ef7eb2e8f9f7 421 This parameter can be a value of @ref ETH_Zero_Quanta_Pause */
<> 144:ef7eb2e8f9f7 422
<> 144:ef7eb2e8f9f7 423 uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for
<> 144:ef7eb2e8f9f7 424 automatic retransmission of PAUSE Frame.
<> 144:ef7eb2e8f9f7 425 This parameter can be a value of @ref ETH_Pause_Low_Threshold */
<> 144:ef7eb2e8f9f7 426
<> 144:ef7eb2e8f9f7 427 uint32_t UnicastPauseFrameDetect; /*!< Selects or not the MAC detection of the Pause frames (with MAC Address0
<> 144:ef7eb2e8f9f7 428 unicast address and unique multicast address).
<> 144:ef7eb2e8f9f7 429 This parameter can be a value of @ref ETH_Unicast_Pause_Frame_Detect */
<> 144:ef7eb2e8f9f7 430
<> 144:ef7eb2e8f9f7 431 uint32_t ReceiveFlowControl; /*!< Enables or disables the MAC to decode the received Pause frame and
<> 144:ef7eb2e8f9f7 432 disable its transmitter for a specified time (Pause Time)
<> 144:ef7eb2e8f9f7 433 This parameter can be a value of @ref ETH_Receive_Flow_Control */
<> 144:ef7eb2e8f9f7 434
<> 144:ef7eb2e8f9f7 435 uint32_t TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause frames (Full-Duplex mode)
<> 144:ef7eb2e8f9f7 436 or the MAC back-pressure operation (Half-Duplex mode)
<> 144:ef7eb2e8f9f7 437 This parameter can be a value of @ref ETH_Transmit_Flow_Control */
<> 144:ef7eb2e8f9f7 438
<> 144:ef7eb2e8f9f7 439 uint32_t VLANTagComparison; /*!< Selects the 12-bit VLAN identifier or the complete 16-bit VLAN tag for
<> 144:ef7eb2e8f9f7 440 comparison and filtering.
<> 144:ef7eb2e8f9f7 441 This parameter can be a value of @ref ETH_VLAN_Tag_Comparison */
<> 144:ef7eb2e8f9f7 442
<> 144:ef7eb2e8f9f7 443 uint32_t VLANTagIdentifier; /*!< Holds the VLAN tag identifier for receive frames */
<> 144:ef7eb2e8f9f7 444
<> 144:ef7eb2e8f9f7 445 } ETH_MACInitTypeDef;
<> 144:ef7eb2e8f9f7 446
<> 144:ef7eb2e8f9f7 447
<> 144:ef7eb2e8f9f7 448 /**
<> 144:ef7eb2e8f9f7 449 * @brief ETH DMA Configuration Structure definition
<> 144:ef7eb2e8f9f7 450 */
<> 144:ef7eb2e8f9f7 451
<> 144:ef7eb2e8f9f7 452 typedef struct
<> 144:ef7eb2e8f9f7 453 {
<> 144:ef7eb2e8f9f7 454 uint32_t DropTCPIPChecksumErrorFrame; /*!< Selects or not the Dropping of TCP/IP Checksum Error Frames.
<> 144:ef7eb2e8f9f7 455 This parameter can be a value of @ref ETH_Drop_TCP_IP_Checksum_Error_Frame */
<> 144:ef7eb2e8f9f7 456
<> 144:ef7eb2e8f9f7 457 uint32_t ReceiveStoreForward; /*!< Enables or disables the Receive store and forward mode.
<> 144:ef7eb2e8f9f7 458 This parameter can be a value of @ref ETH_Receive_Store_Forward */
<> 144:ef7eb2e8f9f7 459
<> 144:ef7eb2e8f9f7 460 uint32_t FlushReceivedFrame; /*!< Enables or disables the flushing of received frames.
<> 144:ef7eb2e8f9f7 461 This parameter can be a value of @ref ETH_Flush_Received_Frame */
<> 144:ef7eb2e8f9f7 462
<> 144:ef7eb2e8f9f7 463 uint32_t TransmitStoreForward; /*!< Enables or disables Transmit store and forward mode.
<> 144:ef7eb2e8f9f7 464 This parameter can be a value of @ref ETH_Transmit_Store_Forward */
<> 144:ef7eb2e8f9f7 465
<> 144:ef7eb2e8f9f7 466 uint32_t TransmitThresholdControl; /*!< Selects or not the Transmit Threshold Control.
<> 144:ef7eb2e8f9f7 467 This parameter can be a value of @ref ETH_Transmit_Threshold_Control */
<> 144:ef7eb2e8f9f7 468
<> 144:ef7eb2e8f9f7 469 uint32_t ForwardErrorFrames; /*!< Selects or not the forward to the DMA of erroneous frames.
<> 144:ef7eb2e8f9f7 470 This parameter can be a value of @ref ETH_Forward_Error_Frames */
<> 144:ef7eb2e8f9f7 471
<> 144:ef7eb2e8f9f7 472 uint32_t ForwardUndersizedGoodFrames; /*!< Enables or disables the Rx FIFO to forward Undersized frames (frames with no Error
<> 144:ef7eb2e8f9f7 473 and length less than 64 bytes) including pad-bytes and CRC)
<> 144:ef7eb2e8f9f7 474 This parameter can be a value of @ref ETH_Forward_Undersized_Good_Frames */
<> 144:ef7eb2e8f9f7 475
<> 144:ef7eb2e8f9f7 476 uint32_t ReceiveThresholdControl; /*!< Selects the threshold level of the Receive FIFO.
<> 144:ef7eb2e8f9f7 477 This parameter can be a value of @ref ETH_Receive_Threshold_Control */
<> 144:ef7eb2e8f9f7 478
<> 144:ef7eb2e8f9f7 479 uint32_t SecondFrameOperate; /*!< Selects or not the Operate on second frame mode, which allows the DMA to process a second
<> 144:ef7eb2e8f9f7 480 frame of Transmit data even before obtaining the status for the first frame.
<> 144:ef7eb2e8f9f7 481 This parameter can be a value of @ref ETH_Second_Frame_Operate */
<> 144:ef7eb2e8f9f7 482
<> 144:ef7eb2e8f9f7 483 uint32_t AddressAlignedBeats; /*!< Enables or disables the Address Aligned Beats.
<> 144:ef7eb2e8f9f7 484 This parameter can be a value of @ref ETH_Address_Aligned_Beats */
<> 144:ef7eb2e8f9f7 485
<> 144:ef7eb2e8f9f7 486 uint32_t FixedBurst; /*!< Enables or disables the AHB Master interface fixed burst transfers.
<> 144:ef7eb2e8f9f7 487 This parameter can be a value of @ref ETH_Fixed_Burst */
<> 144:ef7eb2e8f9f7 488
<> 144:ef7eb2e8f9f7 489 uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
<> 144:ef7eb2e8f9f7 490 This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
<> 144:ef7eb2e8f9f7 491
<> 144:ef7eb2e8f9f7 492 uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
<> 144:ef7eb2e8f9f7 493 This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
<> 144:ef7eb2e8f9f7 494
<> 144:ef7eb2e8f9f7 495 uint32_t DescriptorSkipLength; /*!< Specifies the number of word to skip between two unchained descriptors (Ring mode)
<> 144:ef7eb2e8f9f7 496 This parameter must be a number between Min_Data = 0 and Max_Data = 32 */
<> 144:ef7eb2e8f9f7 497
<> 144:ef7eb2e8f9f7 498 uint32_t DMAArbitration; /*!< Selects the DMA Tx/Rx arbitration.
<> 144:ef7eb2e8f9f7 499 This parameter can be a value of @ref ETH_DMA_Arbitration */
<> 144:ef7eb2e8f9f7 500 } ETH_DMAInitTypeDef;
<> 144:ef7eb2e8f9f7 501
<> 144:ef7eb2e8f9f7 502
<> 144:ef7eb2e8f9f7 503 /**
<> 144:ef7eb2e8f9f7 504 * @brief ETH DMA Descriptors data structure definition
<> 144:ef7eb2e8f9f7 505 */
<> 144:ef7eb2e8f9f7 506
<> 144:ef7eb2e8f9f7 507 typedef struct
<> 144:ef7eb2e8f9f7 508 {
<> 144:ef7eb2e8f9f7 509 __IO uint32_t Status; /*!< Status */
<> 144:ef7eb2e8f9f7 510
<> 144:ef7eb2e8f9f7 511 uint32_t ControlBufferSize; /*!< Control and Buffer1, Buffer2 lengths */
<> 144:ef7eb2e8f9f7 512
<> 144:ef7eb2e8f9f7 513 uint32_t Buffer1Addr; /*!< Buffer1 address pointer */
<> 144:ef7eb2e8f9f7 514
<> 144:ef7eb2e8f9f7 515 uint32_t Buffer2NextDescAddr; /*!< Buffer2 or next descriptor address pointer */
<> 144:ef7eb2e8f9f7 516
<> 144:ef7eb2e8f9f7 517 } ETH_DMADescTypeDef;
<> 144:ef7eb2e8f9f7 518
<> 144:ef7eb2e8f9f7 519
<> 144:ef7eb2e8f9f7 520 /**
<> 144:ef7eb2e8f9f7 521 * @brief Received Frame Informations structure definition
<> 144:ef7eb2e8f9f7 522 */
<> 144:ef7eb2e8f9f7 523 typedef struct
<> 144:ef7eb2e8f9f7 524 {
<> 144:ef7eb2e8f9f7 525 ETH_DMADescTypeDef *FSRxDesc; /*!< First Segment Rx Desc */
<> 144:ef7eb2e8f9f7 526
<> 144:ef7eb2e8f9f7 527 ETH_DMADescTypeDef *LSRxDesc; /*!< Last Segment Rx Desc */
<> 144:ef7eb2e8f9f7 528
<> 144:ef7eb2e8f9f7 529 uint32_t SegCount; /*!< Segment count */
<> 144:ef7eb2e8f9f7 530
<> 144:ef7eb2e8f9f7 531 uint32_t length; /*!< Frame length */
<> 144:ef7eb2e8f9f7 532
<> 144:ef7eb2e8f9f7 533 uint32_t buffer; /*!< Frame buffer */
<> 144:ef7eb2e8f9f7 534
<> 144:ef7eb2e8f9f7 535 } ETH_DMARxFrameInfos;
<> 144:ef7eb2e8f9f7 536
<> 144:ef7eb2e8f9f7 537
<> 144:ef7eb2e8f9f7 538 /**
<> 144:ef7eb2e8f9f7 539 * @brief ETH Handle Structure definition
<> 144:ef7eb2e8f9f7 540 */
<> 144:ef7eb2e8f9f7 541
<> 144:ef7eb2e8f9f7 542 typedef struct
<> 144:ef7eb2e8f9f7 543 {
<> 144:ef7eb2e8f9f7 544 ETH_TypeDef *Instance; /*!< Register base address */
<> 144:ef7eb2e8f9f7 545
<> 144:ef7eb2e8f9f7 546 ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */
<> 144:ef7eb2e8f9f7 547
<> 144:ef7eb2e8f9f7 548 uint32_t LinkStatus; /*!< Ethernet link status */
<> 144:ef7eb2e8f9f7 549
<> 144:ef7eb2e8f9f7 550 ETH_DMADescTypeDef *RxDesc; /*!< Rx descriptor to Get */
<> 144:ef7eb2e8f9f7 551
<> 144:ef7eb2e8f9f7 552 ETH_DMADescTypeDef *TxDesc; /*!< Tx descriptor to Set */
<> 144:ef7eb2e8f9f7 553
<> 144:ef7eb2e8f9f7 554 ETH_DMARxFrameInfos RxFrameInfos; /*!< last Rx frame infos */
<> 144:ef7eb2e8f9f7 555
<> 144:ef7eb2e8f9f7 556 __IO HAL_ETH_StateTypeDef State; /*!< ETH communication state */
<> 144:ef7eb2e8f9f7 557
<> 144:ef7eb2e8f9f7 558 HAL_LockTypeDef Lock; /*!< ETH Lock */
<> 144:ef7eb2e8f9f7 559
<> 144:ef7eb2e8f9f7 560 } ETH_HandleTypeDef;
<> 144:ef7eb2e8f9f7 561
<> 144:ef7eb2e8f9f7 562 /**
<> 144:ef7eb2e8f9f7 563 * @}
<> 144:ef7eb2e8f9f7 564 */
<> 144:ef7eb2e8f9f7 565
<> 144:ef7eb2e8f9f7 566 /* Exported constants --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 567 /** @defgroup ETH_Exported_Constants ETH Exported Constants
<> 144:ef7eb2e8f9f7 568 * @{
<> 144:ef7eb2e8f9f7 569 */
<> 144:ef7eb2e8f9f7 570
<> 144:ef7eb2e8f9f7 571 /** @defgroup ETH_Buffers_setting ETH Buffers setting
<> 144:ef7eb2e8f9f7 572 * @{
<> 144:ef7eb2e8f9f7 573 */
<> 144:ef7eb2e8f9f7 574 #define ETH_MAX_PACKET_SIZE ((uint32_t)1524) /*!< ETH_HEADER + ETH_EXTRA + ETH_VLAN_TAG + ETH_MAX_ETH_PAYLOAD + ETH_CRC */
<> 144:ef7eb2e8f9f7 575 #define ETH_HEADER ((uint32_t)14) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
<> 144:ef7eb2e8f9f7 576 #define ETH_CRC ((uint32_t)4) /*!< Ethernet CRC */
<> 144:ef7eb2e8f9f7 577 #define ETH_EXTRA ((uint32_t)2) /*!< Extra bytes in some cases */
<> 144:ef7eb2e8f9f7 578 #define ETH_VLAN_TAG ((uint32_t)4) /*!< optional 802.1q VLAN Tag */
<> 144:ef7eb2e8f9f7 579 #define ETH_MIN_ETH_PAYLOAD ((uint32_t)46) /*!< Minimum Ethernet payload size */
<> 144:ef7eb2e8f9f7 580 #define ETH_MAX_ETH_PAYLOAD ((uint32_t)1500) /*!< Maximum Ethernet payload size */
<> 144:ef7eb2e8f9f7 581 #define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000) /*!< Jumbo frame payload size */
<> 144:ef7eb2e8f9f7 582
<> 144:ef7eb2e8f9f7 583 /* Ethernet driver receive buffers are organized in a chained linked-list, when
<> 144:ef7eb2e8f9f7 584 an ethernet packet is received, the Rx-DMA will transfer the packet from RxFIFO
<> 144:ef7eb2e8f9f7 585 to the driver receive buffers memory.
<> 144:ef7eb2e8f9f7 586
<> 144:ef7eb2e8f9f7 587 Depending on the size of the received ethernet packet and the size of
<> 144:ef7eb2e8f9f7 588 each ethernet driver receive buffer, the received packet can take one or more
<> 144:ef7eb2e8f9f7 589 ethernet driver receive buffer.
<> 144:ef7eb2e8f9f7 590
<> 144:ef7eb2e8f9f7 591 In below are defined the size of one ethernet driver receive buffer ETH_RX_BUF_SIZE
<> 144:ef7eb2e8f9f7 592 and the total count of the driver receive buffers ETH_RXBUFNB.
<> 144:ef7eb2e8f9f7 593
<> 144:ef7eb2e8f9f7 594 The configured value for ETH_RX_BUF_SIZE and ETH_RXBUFNB are only provided as
<> 144:ef7eb2e8f9f7 595 example, they can be reconfigured in the application layer to fit the application
<> 144:ef7eb2e8f9f7 596 needs */
<> 144:ef7eb2e8f9f7 597
<> 144:ef7eb2e8f9f7 598 /* Here we configure each Ethernet driver receive buffer to fit the Max size Ethernet
<> 144:ef7eb2e8f9f7 599 packet */
<> 144:ef7eb2e8f9f7 600 #ifndef ETH_RX_BUF_SIZE
<> 144:ef7eb2e8f9f7 601 #define ETH_RX_BUF_SIZE ETH_MAX_PACKET_SIZE
<> 144:ef7eb2e8f9f7 602 #endif
<> 144:ef7eb2e8f9f7 603
<> 144:ef7eb2e8f9f7 604 /* 5 Ethernet driver receive buffers are used (in a chained linked list)*/
<> 144:ef7eb2e8f9f7 605 #ifndef ETH_RXBUFNB
<> 144:ef7eb2e8f9f7 606 #define ETH_RXBUFNB ((uint32_t)5 /* 5 Rx buffers of size ETH_RX_BUF_SIZE */
<> 144:ef7eb2e8f9f7 607 #endif
<> 144:ef7eb2e8f9f7 608
<> 144:ef7eb2e8f9f7 609
<> 144:ef7eb2e8f9f7 610 /* Ethernet driver transmit buffers are organized in a chained linked-list, when
<> 144:ef7eb2e8f9f7 611 an ethernet packet is transmitted, Tx-DMA will transfer the packet from the
<> 144:ef7eb2e8f9f7 612 driver transmit buffers memory to the TxFIFO.
<> 144:ef7eb2e8f9f7 613
<> 144:ef7eb2e8f9f7 614 Depending on the size of the Ethernet packet to be transmitted and the size of
<> 144:ef7eb2e8f9f7 615 each ethernet driver transmit buffer, the packet to be transmitted can take
<> 144:ef7eb2e8f9f7 616 one or more ethernet driver transmit buffer.
<> 144:ef7eb2e8f9f7 617
<> 144:ef7eb2e8f9f7 618 In below are defined the size of one ethernet driver transmit buffer ETH_TX_BUF_SIZE
<> 144:ef7eb2e8f9f7 619 and the total count of the driver transmit buffers ETH_TXBUFNB.
<> 144:ef7eb2e8f9f7 620
<> 144:ef7eb2e8f9f7 621 The configured value for ETH_TX_BUF_SIZE and ETH_TXBUFNB are only provided as
<> 144:ef7eb2e8f9f7 622 example, they can be reconfigured in the application layer to fit the application
<> 144:ef7eb2e8f9f7 623 needs */
<> 144:ef7eb2e8f9f7 624
<> 144:ef7eb2e8f9f7 625 /* Here we configure each Ethernet driver transmit buffer to fit the Max size Ethernet
<> 144:ef7eb2e8f9f7 626 packet */
<> 144:ef7eb2e8f9f7 627 #ifndef ETH_TX_BUF_SIZE
<> 144:ef7eb2e8f9f7 628 #define ETH_TX_BUF_SIZE ETH_MAX_PACKET_SIZE
<> 144:ef7eb2e8f9f7 629 #endif
<> 144:ef7eb2e8f9f7 630
<> 144:ef7eb2e8f9f7 631 /* 5 ethernet driver transmit buffers are used (in a chained linked list)*/
<> 144:ef7eb2e8f9f7 632 #ifndef ETH_TXBUFNB
<> 144:ef7eb2e8f9f7 633 #define ETH_TXBUFNB ((uint32_t)5 /* 5 Tx buffers of size ETH_TX_BUF_SIZE */
<> 144:ef7eb2e8f9f7 634 #endif
<> 144:ef7eb2e8f9f7 635
<> 144:ef7eb2e8f9f7 636 /**
<> 144:ef7eb2e8f9f7 637 * @}
<> 144:ef7eb2e8f9f7 638 */
<> 144:ef7eb2e8f9f7 639
<> 144:ef7eb2e8f9f7 640 /** @defgroup ETH_DMA_TX_Descriptor ETH DMA TX Descriptor
<> 144:ef7eb2e8f9f7 641 * @{
<> 144:ef7eb2e8f9f7 642 */
<> 144:ef7eb2e8f9f7 643
<> 144:ef7eb2e8f9f7 644 /*
<> 144:ef7eb2e8f9f7 645 DMA Tx Desciptor
<> 144:ef7eb2e8f9f7 646 -----------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 647 TDES0 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
<> 144:ef7eb2e8f9f7 648 -----------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 649 TDES1 | Reserved[31:29] | Buffer2 ByteCount[28:16] | Reserved[15:13] | Buffer1 ByteCount[12:0] |
<> 144:ef7eb2e8f9f7 650 -----------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 651 TDES2 | Buffer1 Address [31:0] |
<> 144:ef7eb2e8f9f7 652 -----------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 653 TDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
<> 144:ef7eb2e8f9f7 654 -----------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 655 */
<> 144:ef7eb2e8f9f7 656
<> 144:ef7eb2e8f9f7 657 /**
<> 144:ef7eb2e8f9f7 658 * @brief Bit definition of TDES0 register: DMA Tx descriptor status register
<> 144:ef7eb2e8f9f7 659 */
<> 144:ef7eb2e8f9f7 660 #define ETH_DMATXDESC_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */
<> 144:ef7eb2e8f9f7 661 #define ETH_DMATXDESC_IC ((uint32_t)0x40000000) /*!< Interrupt on Completion */
<> 144:ef7eb2e8f9f7 662 #define ETH_DMATXDESC_LS ((uint32_t)0x20000000) /*!< Last Segment */
<> 144:ef7eb2e8f9f7 663 #define ETH_DMATXDESC_FS ((uint32_t)0x10000000) /*!< First Segment */
<> 144:ef7eb2e8f9f7 664 #define ETH_DMATXDESC_DC ((uint32_t)0x08000000) /*!< Disable CRC */
<> 144:ef7eb2e8f9f7 665 #define ETH_DMATXDESC_DP ((uint32_t)0x04000000) /*!< Disable Padding */
<> 144:ef7eb2e8f9f7 666 #define ETH_DMATXDESC_TTSE ((uint32_t)0x02000000) /*!< Transmit Time Stamp Enable */
<> 144:ef7eb2e8f9f7 667 #define ETH_DMATXDESC_CIC ((uint32_t)0x00C00000) /*!< Checksum Insertion Control: 4 cases */
<> 144:ef7eb2e8f9f7 668 #define ETH_DMATXDESC_CIC_BYPASS ((uint32_t)0x00000000) /*!< Do Nothing: Checksum Engine is bypassed */
<> 144:ef7eb2e8f9f7 669 #define ETH_DMATXDESC_CIC_IPV4HEADER ((uint32_t)0x00400000) /*!< IPV4 header Checksum Insertion */
<> 144:ef7eb2e8f9f7 670 #define ETH_DMATXDESC_CIC_TCPUDPICMP_SEGMENT ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP Checksum Insertion calculated over segment only */
<> 144:ef7eb2e8f9f7 671 #define ETH_DMATXDESC_CIC_TCPUDPICMP_FULL ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP Checksum Insertion fully calculated */
<> 144:ef7eb2e8f9f7 672 #define ETH_DMATXDESC_TER ((uint32_t)0x00200000) /*!< Transmit End of Ring */
<> 144:ef7eb2e8f9f7 673 #define ETH_DMATXDESC_TCH ((uint32_t)0x00100000) /*!< Second Address Chained */
<> 144:ef7eb2e8f9f7 674 #define ETH_DMATXDESC_TTSS ((uint32_t)0x00020000) /*!< Tx Time Stamp Status */
<> 144:ef7eb2e8f9f7 675 #define ETH_DMATXDESC_IHE ((uint32_t)0x00010000) /*!< IP Header Error */
<> 144:ef7eb2e8f9f7 676 #define ETH_DMATXDESC_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: UE || ED || EC || LCO || NC || LCA || FF || JT */
<> 144:ef7eb2e8f9f7 677 #define ETH_DMATXDESC_JT ((uint32_t)0x00004000) /*!< Jabber Timeout */
<> 144:ef7eb2e8f9f7 678 #define ETH_DMATXDESC_FF ((uint32_t)0x00002000) /*!< Frame Flushed: DMA/MTL flushed the frame due to SW flush */
<> 144:ef7eb2e8f9f7 679 #define ETH_DMATXDESC_PCE ((uint32_t)0x00001000) /*!< Payload Checksum Error */
<> 144:ef7eb2e8f9f7 680 #define ETH_DMATXDESC_LCA ((uint32_t)0x00000800) /*!< Loss of Carrier: carrier lost during transmission */
<> 144:ef7eb2e8f9f7 681 #define ETH_DMATXDESC_NC ((uint32_t)0x00000400) /*!< No Carrier: no carrier signal from the transceiver */
<> 144:ef7eb2e8f9f7 682 #define ETH_DMATXDESC_LCO ((uint32_t)0x00000200) /*!< Late Collision: transmission aborted due to collision */
<> 144:ef7eb2e8f9f7 683 #define ETH_DMATXDESC_EC ((uint32_t)0x00000100) /*!< Excessive Collision: transmission aborted after 16 collisions */
<> 144:ef7eb2e8f9f7 684 #define ETH_DMATXDESC_VF ((uint32_t)0x00000080) /*!< VLAN Frame */
<> 144:ef7eb2e8f9f7 685 #define ETH_DMATXDESC_CC ((uint32_t)0x00000078) /*!< Collision Count */
<> 144:ef7eb2e8f9f7 686 #define ETH_DMATXDESC_ED ((uint32_t)0x00000004) /*!< Excessive Deferral */
<> 144:ef7eb2e8f9f7 687 #define ETH_DMATXDESC_UF ((uint32_t)0x00000002) /*!< Underflow Error: late data arrival from the memory */
<> 144:ef7eb2e8f9f7 688 #define ETH_DMATXDESC_DB ((uint32_t)0x00000001) /*!< Deferred Bit */
<> 144:ef7eb2e8f9f7 689
<> 144:ef7eb2e8f9f7 690 /**
<> 144:ef7eb2e8f9f7 691 * @brief Bit definition of TDES1 register
<> 144:ef7eb2e8f9f7 692 */
<> 144:ef7eb2e8f9f7 693 #define ETH_DMATXDESC_TBS2 ((uint32_t)0x1FFF0000) /*!< Transmit Buffer2 Size */
<> 144:ef7eb2e8f9f7 694 #define ETH_DMATXDESC_TBS1 ((uint32_t)0x00001FFF) /*!< Transmit Buffer1 Size */
<> 144:ef7eb2e8f9f7 695
<> 144:ef7eb2e8f9f7 696 /**
<> 144:ef7eb2e8f9f7 697 * @brief Bit definition of TDES2 register
<> 144:ef7eb2e8f9f7 698 */
<> 144:ef7eb2e8f9f7 699 #define ETH_DMATXDESC_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */
<> 144:ef7eb2e8f9f7 700
<> 144:ef7eb2e8f9f7 701 /**
<> 144:ef7eb2e8f9f7 702 * @brief Bit definition of TDES3 register
<> 144:ef7eb2e8f9f7 703 */
<> 144:ef7eb2e8f9f7 704 #define ETH_DMATXDESC_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */
<> 144:ef7eb2e8f9f7 705
<> 144:ef7eb2e8f9f7 706 /**
<> 144:ef7eb2e8f9f7 707 * @}
<> 144:ef7eb2e8f9f7 708 */
<> 144:ef7eb2e8f9f7 709 /** @defgroup ETH_DMA_RX_Descriptor ETH DMA RX Descriptor
<> 144:ef7eb2e8f9f7 710 * @{
<> 144:ef7eb2e8f9f7 711 */
<> 144:ef7eb2e8f9f7 712
<> 144:ef7eb2e8f9f7 713 /*
<> 144:ef7eb2e8f9f7 714 DMA Rx Descriptor
<> 144:ef7eb2e8f9f7 715 --------------------------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 716 RDES0 | OWN(31) | Status [30:0] |
<> 144:ef7eb2e8f9f7 717 ---------------------------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 718 RDES1 | CTRL(31) | Reserved[30:29] | Buffer2 ByteCount[28:16] | CTRL[15:14] | Reserved(13) | Buffer1 ByteCount[12:0] |
<> 144:ef7eb2e8f9f7 719 ---------------------------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 720 RDES2 | Buffer1 Address [31:0] |
<> 144:ef7eb2e8f9f7 721 ---------------------------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 722 RDES3 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
<> 144:ef7eb2e8f9f7 723 ---------------------------------------------------------------------------------------------------------------------
<> 144:ef7eb2e8f9f7 724 */
<> 144:ef7eb2e8f9f7 725
<> 144:ef7eb2e8f9f7 726 /**
<> 144:ef7eb2e8f9f7 727 * @brief Bit definition of RDES0 register: DMA Rx descriptor status register
<> 144:ef7eb2e8f9f7 728 */
<> 144:ef7eb2e8f9f7 729 #define ETH_DMARXDESC_OWN ((uint32_t)0x80000000) /*!< OWN bit: descriptor is owned by DMA engine */
<> 144:ef7eb2e8f9f7 730 #define ETH_DMARXDESC_AFM ((uint32_t)0x40000000) /*!< DA Filter Fail for the rx frame */
<> 144:ef7eb2e8f9f7 731 #define ETH_DMARXDESC_FL ((uint32_t)0x3FFF0000) /*!< Receive descriptor frame length */
<> 144:ef7eb2e8f9f7 732 #define ETH_DMARXDESC_ES ((uint32_t)0x00008000) /*!< Error summary: OR of the following bits: DE || OE || IPC || LC || RWT || RE || CE */
<> 144:ef7eb2e8f9f7 733 #define ETH_DMARXDESC_DE ((uint32_t)0x00004000) /*!< Descriptor error: no more descriptors for receive frame */
<> 144:ef7eb2e8f9f7 734 #define ETH_DMARXDESC_SAF ((uint32_t)0x00002000) /*!< SA Filter Fail for the received frame */
<> 144:ef7eb2e8f9f7 735 #define ETH_DMARXDESC_LE ((uint32_t)0x00001000) /*!< Frame size not matching with length field */
<> 144:ef7eb2e8f9f7 736 #define ETH_DMARXDESC_OE ((uint32_t)0x00000800) /*!< Overflow Error: Frame was damaged due to buffer overflow */
<> 144:ef7eb2e8f9f7 737 #define ETH_DMARXDESC_VLAN ((uint32_t)0x00000400) /*!< VLAN Tag: received frame is a VLAN frame */
<> 144:ef7eb2e8f9f7 738 #define ETH_DMARXDESC_FS ((uint32_t)0x00000200) /*!< First descriptor of the frame */
<> 144:ef7eb2e8f9f7 739 #define ETH_DMARXDESC_LS ((uint32_t)0x00000100) /*!< Last descriptor of the frame */
<> 144:ef7eb2e8f9f7 740 #define ETH_DMARXDESC_IPV4HCE ((uint32_t)0x00000080) /*!< IPC Checksum Error: Rx Ipv4 header checksum error */
<> 144:ef7eb2e8f9f7 741 #define ETH_DMARXDESC_LC ((uint32_t)0x00000040) /*!< Late collision occurred during reception */
<> 144:ef7eb2e8f9f7 742 #define ETH_DMARXDESC_FT ((uint32_t)0x00000020) /*!< Frame type - Ethernet, otherwise 802.3 */
<> 144:ef7eb2e8f9f7 743 #define ETH_DMARXDESC_RWT ((uint32_t)0x00000010) /*!< Receive Watchdog Timeout: watchdog timer expired during reception */
<> 144:ef7eb2e8f9f7 744 #define ETH_DMARXDESC_RE ((uint32_t)0x00000008) /*!< Receive error: error reported by MII interface */
<> 144:ef7eb2e8f9f7 745 #define ETH_DMARXDESC_DBE ((uint32_t)0x00000004) /*!< Dribble bit error: frame contains non int multiple of 8 bits */
<> 144:ef7eb2e8f9f7 746 #define ETH_DMARXDESC_CE ((uint32_t)0x00000002) /*!< CRC error */
<> 144:ef7eb2e8f9f7 747 #define ETH_DMARXDESC_MAMPCE ((uint32_t)0x00000001) /*!< Rx MAC Address/Payload Checksum Error: Rx MAC address matched/ Rx Payload Checksum Error */
<> 144:ef7eb2e8f9f7 748
<> 144:ef7eb2e8f9f7 749 /**
<> 144:ef7eb2e8f9f7 750 * @brief Bit definition of RDES1 register
<> 144:ef7eb2e8f9f7 751 */
<> 144:ef7eb2e8f9f7 752 #define ETH_DMARXDESC_DIC ((uint32_t)0x80000000) /*!< Disable Interrupt on Completion */
<> 144:ef7eb2e8f9f7 753 #define ETH_DMARXDESC_RBS2 ((uint32_t)0x1FFF0000) /*!< Receive Buffer2 Size */
<> 144:ef7eb2e8f9f7 754 #define ETH_DMARXDESC_RER ((uint32_t)0x00008000) /*!< Receive End of Ring */
<> 144:ef7eb2e8f9f7 755 #define ETH_DMARXDESC_RCH ((uint32_t)0x00004000) /*!< Second Address Chained */
<> 144:ef7eb2e8f9f7 756 #define ETH_DMARXDESC_RBS1 ((uint32_t)0x00001FFF) /*!< Receive Buffer1 Size */
<> 144:ef7eb2e8f9f7 757
<> 144:ef7eb2e8f9f7 758 /**
<> 144:ef7eb2e8f9f7 759 * @brief Bit definition of RDES2 register
<> 144:ef7eb2e8f9f7 760 */
<> 144:ef7eb2e8f9f7 761 #define ETH_DMARXDESC_B1AP ((uint32_t)0xFFFFFFFF) /*!< Buffer1 Address Pointer */
<> 144:ef7eb2e8f9f7 762
<> 144:ef7eb2e8f9f7 763 /**
<> 144:ef7eb2e8f9f7 764 * @brief Bit definition of RDES3 register
<> 144:ef7eb2e8f9f7 765 */
<> 144:ef7eb2e8f9f7 766 #define ETH_DMARXDESC_B2AP ((uint32_t)0xFFFFFFFF) /*!< Buffer2 Address Pointer */
<> 144:ef7eb2e8f9f7 767
<> 144:ef7eb2e8f9f7 768 /**
<> 144:ef7eb2e8f9f7 769 * @}
<> 144:ef7eb2e8f9f7 770 */
<> 144:ef7eb2e8f9f7 771 /** @defgroup ETH_AutoNegotiation ETH AutoNegotiation
<> 144:ef7eb2e8f9f7 772 * @{
<> 144:ef7eb2e8f9f7 773 */
<> 144:ef7eb2e8f9f7 774 #define ETH_AUTONEGOTIATION_ENABLE ((uint32_t)0x00000001)
<> 144:ef7eb2e8f9f7 775 #define ETH_AUTONEGOTIATION_DISABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 776
<> 144:ef7eb2e8f9f7 777 /**
<> 144:ef7eb2e8f9f7 778 * @}
<> 144:ef7eb2e8f9f7 779 */
<> 144:ef7eb2e8f9f7 780 /** @defgroup ETH_Speed ETH Speed
<> 144:ef7eb2e8f9f7 781 * @{
<> 144:ef7eb2e8f9f7 782 */
<> 144:ef7eb2e8f9f7 783 #define ETH_SPEED_10M ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 784 #define ETH_SPEED_100M ((uint32_t)0x00004000)
<> 144:ef7eb2e8f9f7 785
<> 144:ef7eb2e8f9f7 786 /**
<> 144:ef7eb2e8f9f7 787 * @}
<> 144:ef7eb2e8f9f7 788 */
<> 144:ef7eb2e8f9f7 789 /** @defgroup ETH_Duplex_Mode ETH Duplex Mode
<> 144:ef7eb2e8f9f7 790 * @{
<> 144:ef7eb2e8f9f7 791 */
<> 144:ef7eb2e8f9f7 792 #define ETH_MODE_FULLDUPLEX ((uint32_t)0x00000800)
<> 144:ef7eb2e8f9f7 793 #define ETH_MODE_HALFDUPLEX ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 794 /**
<> 144:ef7eb2e8f9f7 795 * @}
<> 144:ef7eb2e8f9f7 796 */
<> 144:ef7eb2e8f9f7 797 /** @defgroup ETH_Rx_Mode ETH Rx Mode
<> 144:ef7eb2e8f9f7 798 * @{
<> 144:ef7eb2e8f9f7 799 */
<> 144:ef7eb2e8f9f7 800 #define ETH_RXPOLLING_MODE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 801 #define ETH_RXINTERRUPT_MODE ((uint32_t)0x00000001)
<> 144:ef7eb2e8f9f7 802 /**
<> 144:ef7eb2e8f9f7 803 * @}
<> 144:ef7eb2e8f9f7 804 */
<> 144:ef7eb2e8f9f7 805
<> 144:ef7eb2e8f9f7 806 /** @defgroup ETH_Checksum_Mode ETH Checksum Mode
<> 144:ef7eb2e8f9f7 807 * @{
<> 144:ef7eb2e8f9f7 808 */
<> 144:ef7eb2e8f9f7 809 #define ETH_CHECKSUM_BY_HARDWARE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 810 #define ETH_CHECKSUM_BY_SOFTWARE ((uint32_t)0x00000001)
<> 144:ef7eb2e8f9f7 811 /**
<> 144:ef7eb2e8f9f7 812 * @}
<> 144:ef7eb2e8f9f7 813 */
<> 144:ef7eb2e8f9f7 814
<> 144:ef7eb2e8f9f7 815 /** @defgroup ETH_Media_Interface ETH Media Interface
<> 144:ef7eb2e8f9f7 816 * @{
<> 144:ef7eb2e8f9f7 817 */
<> 144:ef7eb2e8f9f7 818 #define ETH_MEDIA_INTERFACE_MII ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 819 #define ETH_MEDIA_INTERFACE_RMII ((uint32_t)AFIO_MAPR_MII_RMII_SEL)
<> 144:ef7eb2e8f9f7 820
<> 144:ef7eb2e8f9f7 821 /**
<> 144:ef7eb2e8f9f7 822 * @}
<> 144:ef7eb2e8f9f7 823 */
<> 144:ef7eb2e8f9f7 824
<> 144:ef7eb2e8f9f7 825 /** @defgroup ETH_Watchdog ETH Watchdog
<> 144:ef7eb2e8f9f7 826 * @{
<> 144:ef7eb2e8f9f7 827 */
<> 144:ef7eb2e8f9f7 828 #define ETH_WATCHDOG_ENABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 829 #define ETH_WATCHDOG_DISABLE ((uint32_t)0x00800000)
<> 144:ef7eb2e8f9f7 830
<> 144:ef7eb2e8f9f7 831 /**
<> 144:ef7eb2e8f9f7 832 * @}
<> 144:ef7eb2e8f9f7 833 */
<> 144:ef7eb2e8f9f7 834
<> 144:ef7eb2e8f9f7 835 /** @defgroup ETH_Jabber ETH Jabber
<> 144:ef7eb2e8f9f7 836 * @{
<> 144:ef7eb2e8f9f7 837 */
<> 144:ef7eb2e8f9f7 838 #define ETH_JABBER_ENABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 839 #define ETH_JABBER_DISABLE ((uint32_t)0x00400000)
<> 144:ef7eb2e8f9f7 840
<> 144:ef7eb2e8f9f7 841 /**
<> 144:ef7eb2e8f9f7 842 * @}
<> 144:ef7eb2e8f9f7 843 */
<> 144:ef7eb2e8f9f7 844
<> 144:ef7eb2e8f9f7 845 /** @defgroup ETH_Inter_Frame_Gap ETH Inter Frame Gap
<> 144:ef7eb2e8f9f7 846 * @{
<> 144:ef7eb2e8f9f7 847 */
<> 144:ef7eb2e8f9f7 848 #define ETH_INTERFRAMEGAP_96BIT ((uint32_t)0x00000000) /*!< minimum IFG between frames during transmission is 96Bit */
<> 144:ef7eb2e8f9f7 849 #define ETH_INTERFRAMEGAP_88BIT ((uint32_t)0x00020000) /*!< minimum IFG between frames during transmission is 88Bit */
<> 144:ef7eb2e8f9f7 850 #define ETH_INTERFRAMEGAP_80BIT ((uint32_t)0x00040000) /*!< minimum IFG between frames during transmission is 80Bit */
<> 144:ef7eb2e8f9f7 851 #define ETH_INTERFRAMEGAP_72BIT ((uint32_t)0x00060000) /*!< minimum IFG between frames during transmission is 72Bit */
<> 144:ef7eb2e8f9f7 852 #define ETH_INTERFRAMEGAP_64BIT ((uint32_t)0x00080000) /*!< minimum IFG between frames during transmission is 64Bit */
<> 144:ef7eb2e8f9f7 853 #define ETH_INTERFRAMEGAP_56BIT ((uint32_t)0x000A0000) /*!< minimum IFG between frames during transmission is 56Bit */
<> 144:ef7eb2e8f9f7 854 #define ETH_INTERFRAMEGAP_48BIT ((uint32_t)0x000C0000) /*!< minimum IFG between frames during transmission is 48Bit */
<> 144:ef7eb2e8f9f7 855 #define ETH_INTERFRAMEGAP_40BIT ((uint32_t)0x000E0000) /*!< minimum IFG between frames during transmission is 40Bit */
<> 144:ef7eb2e8f9f7 856
<> 144:ef7eb2e8f9f7 857 /**
<> 144:ef7eb2e8f9f7 858 * @}
<> 144:ef7eb2e8f9f7 859 */
<> 144:ef7eb2e8f9f7 860
<> 144:ef7eb2e8f9f7 861 /** @defgroup ETH_Carrier_Sense ETH Carrier Sense
<> 144:ef7eb2e8f9f7 862 * @{
<> 144:ef7eb2e8f9f7 863 */
<> 144:ef7eb2e8f9f7 864 #define ETH_CARRIERSENCE_ENABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 865 #define ETH_CARRIERSENCE_DISABLE ((uint32_t)0x00010000)
<> 144:ef7eb2e8f9f7 866
<> 144:ef7eb2e8f9f7 867 /**
<> 144:ef7eb2e8f9f7 868 * @}
<> 144:ef7eb2e8f9f7 869 */
<> 144:ef7eb2e8f9f7 870
<> 144:ef7eb2e8f9f7 871 /** @defgroup ETH_Receive_Own ETH Receive Own
<> 144:ef7eb2e8f9f7 872 * @{
<> 144:ef7eb2e8f9f7 873 */
<> 144:ef7eb2e8f9f7 874 #define ETH_RECEIVEOWN_ENABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 875 #define ETH_RECEIVEOWN_DISABLE ((uint32_t)0x00002000)
<> 144:ef7eb2e8f9f7 876
<> 144:ef7eb2e8f9f7 877 /**
<> 144:ef7eb2e8f9f7 878 * @}
<> 144:ef7eb2e8f9f7 879 */
<> 144:ef7eb2e8f9f7 880
<> 144:ef7eb2e8f9f7 881 /** @defgroup ETH_Loop_Back_Mode ETH Loop Back Mode
<> 144:ef7eb2e8f9f7 882 * @{
<> 144:ef7eb2e8f9f7 883 */
<> 144:ef7eb2e8f9f7 884 #define ETH_LOOPBACKMODE_ENABLE ((uint32_t)0x00001000)
<> 144:ef7eb2e8f9f7 885 #define ETH_LOOPBACKMODE_DISABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 886
<> 144:ef7eb2e8f9f7 887 /**
<> 144:ef7eb2e8f9f7 888 * @}
<> 144:ef7eb2e8f9f7 889 */
<> 144:ef7eb2e8f9f7 890
<> 144:ef7eb2e8f9f7 891 /** @defgroup ETH_Checksum_Offload ETH Checksum Offload
<> 144:ef7eb2e8f9f7 892 * @{
<> 144:ef7eb2e8f9f7 893 */
<> 144:ef7eb2e8f9f7 894 #define ETH_CHECKSUMOFFLAOD_ENABLE ((uint32_t)0x00000400)
<> 144:ef7eb2e8f9f7 895 #define ETH_CHECKSUMOFFLAOD_DISABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 896
<> 144:ef7eb2e8f9f7 897 /**
<> 144:ef7eb2e8f9f7 898 * @}
<> 144:ef7eb2e8f9f7 899 */
<> 144:ef7eb2e8f9f7 900
<> 144:ef7eb2e8f9f7 901 /** @defgroup ETH_Retry_Transmission ETH Retry Transmission
<> 144:ef7eb2e8f9f7 902 * @{
<> 144:ef7eb2e8f9f7 903 */
<> 144:ef7eb2e8f9f7 904 #define ETH_RETRYTRANSMISSION_ENABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 905 #define ETH_RETRYTRANSMISSION_DISABLE ((uint32_t)0x00000200)
<> 144:ef7eb2e8f9f7 906
<> 144:ef7eb2e8f9f7 907 /**
<> 144:ef7eb2e8f9f7 908 * @}
<> 144:ef7eb2e8f9f7 909 */
<> 144:ef7eb2e8f9f7 910
<> 144:ef7eb2e8f9f7 911 /** @defgroup ETH_Automatic_Pad_CRC_Strip ETH Automatic Pad CRC Strip
<> 144:ef7eb2e8f9f7 912 * @{
<> 144:ef7eb2e8f9f7 913 */
<> 144:ef7eb2e8f9f7 914 #define ETH_AUTOMATICPADCRCSTRIP_ENABLE ((uint32_t)0x00000080)
<> 144:ef7eb2e8f9f7 915 #define ETH_AUTOMATICPADCRCSTRIP_DISABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 916
<> 144:ef7eb2e8f9f7 917 /**
<> 144:ef7eb2e8f9f7 918 * @}
<> 144:ef7eb2e8f9f7 919 */
<> 144:ef7eb2e8f9f7 920
<> 144:ef7eb2e8f9f7 921 /** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
<> 144:ef7eb2e8f9f7 922 * @{
<> 144:ef7eb2e8f9f7 923 */
<> 144:ef7eb2e8f9f7 924 #define ETH_BACKOFFLIMIT_10 ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 925 #define ETH_BACKOFFLIMIT_8 ((uint32_t)0x00000020)
<> 144:ef7eb2e8f9f7 926 #define ETH_BACKOFFLIMIT_4 ((uint32_t)0x00000040)
<> 144:ef7eb2e8f9f7 927 #define ETH_BACKOFFLIMIT_1 ((uint32_t)0x00000060)
<> 144:ef7eb2e8f9f7 928
<> 144:ef7eb2e8f9f7 929 /**
<> 144:ef7eb2e8f9f7 930 * @}
<> 144:ef7eb2e8f9f7 931 */
<> 144:ef7eb2e8f9f7 932
<> 144:ef7eb2e8f9f7 933 /** @defgroup ETH_Deferral_Check ETH Deferral Check
<> 144:ef7eb2e8f9f7 934 * @{
<> 144:ef7eb2e8f9f7 935 */
<> 144:ef7eb2e8f9f7 936 #define ETH_DEFFERRALCHECK_ENABLE ((uint32_t)0x00000010)
<> 144:ef7eb2e8f9f7 937 #define ETH_DEFFERRALCHECK_DISABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 938
<> 144:ef7eb2e8f9f7 939 /**
<> 144:ef7eb2e8f9f7 940 * @}
<> 144:ef7eb2e8f9f7 941 */
<> 144:ef7eb2e8f9f7 942
<> 144:ef7eb2e8f9f7 943 /** @defgroup ETH_Receive_All ETH Receive All
<> 144:ef7eb2e8f9f7 944 * @{
<> 144:ef7eb2e8f9f7 945 */
<> 144:ef7eb2e8f9f7 946 #define ETH_RECEIVEALL_ENABLE ((uint32_t)0x80000000)
<> 144:ef7eb2e8f9f7 947 #define ETH_RECEIVEAll_DISABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 948
<> 144:ef7eb2e8f9f7 949 /**
<> 144:ef7eb2e8f9f7 950 * @}
<> 144:ef7eb2e8f9f7 951 */
<> 144:ef7eb2e8f9f7 952
<> 144:ef7eb2e8f9f7 953 /** @defgroup ETH_Source_Addr_Filter ETH Source Addr Filter
<> 144:ef7eb2e8f9f7 954 * @{
<> 144:ef7eb2e8f9f7 955 */
<> 144:ef7eb2e8f9f7 956 #define ETH_SOURCEADDRFILTER_NORMAL_ENABLE ((uint32_t)0x00000200)
<> 144:ef7eb2e8f9f7 957 #define ETH_SOURCEADDRFILTER_INVERSE_ENABLE ((uint32_t)0x00000300)
<> 144:ef7eb2e8f9f7 958 #define ETH_SOURCEADDRFILTER_DISABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 959
<> 144:ef7eb2e8f9f7 960 /**
<> 144:ef7eb2e8f9f7 961 * @}
<> 144:ef7eb2e8f9f7 962 */
<> 144:ef7eb2e8f9f7 963
<> 144:ef7eb2e8f9f7 964 /** @defgroup ETH_Pass_Control_Frames ETH Pass Control Frames
<> 144:ef7eb2e8f9f7 965 * @{
<> 144:ef7eb2e8f9f7 966 */
<> 144:ef7eb2e8f9f7 967 #define ETH_PASSCONTROLFRAMES_BLOCKALL ((uint32_t)0x00000040) /*!< MAC filters all control frames from reaching the application */
<> 144:ef7eb2e8f9f7 968 #define ETH_PASSCONTROLFRAMES_FORWARDALL ((uint32_t)0x00000080) /*!< MAC forwards all control frames to application even if they fail the Address Filter */
<> 144:ef7eb2e8f9f7 969 #define ETH_PASSCONTROLFRAMES_FORWARDPASSEDADDRFILTER ((uint32_t)0x000000C0) /*!< MAC forwards control frames that pass the Address Filter. */
<> 144:ef7eb2e8f9f7 970
<> 144:ef7eb2e8f9f7 971 /**
<> 144:ef7eb2e8f9f7 972 * @}
<> 144:ef7eb2e8f9f7 973 */
<> 144:ef7eb2e8f9f7 974
<> 144:ef7eb2e8f9f7 975 /** @defgroup ETH_Broadcast_Frames_Reception ETH Broadcast Frames Reception
<> 144:ef7eb2e8f9f7 976 * @{
<> 144:ef7eb2e8f9f7 977 */
<> 144:ef7eb2e8f9f7 978 #define ETH_BROADCASTFRAMESRECEPTION_ENABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 979 #define ETH_BROADCASTFRAMESRECEPTION_DISABLE ((uint32_t)0x00000020)
<> 144:ef7eb2e8f9f7 980
<> 144:ef7eb2e8f9f7 981 /**
<> 144:ef7eb2e8f9f7 982 * @}
<> 144:ef7eb2e8f9f7 983 */
<> 144:ef7eb2e8f9f7 984
<> 144:ef7eb2e8f9f7 985 /** @defgroup ETH_Destination_Addr_Filter ETH Destination Addr Filter
<> 144:ef7eb2e8f9f7 986 * @{
<> 144:ef7eb2e8f9f7 987 */
<> 144:ef7eb2e8f9f7 988 #define ETH_DESTINATIONADDRFILTER_NORMAL ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 989 #define ETH_DESTINATIONADDRFILTER_INVERSE ((uint32_t)0x00000008)
<> 144:ef7eb2e8f9f7 990
<> 144:ef7eb2e8f9f7 991 /**
<> 144:ef7eb2e8f9f7 992 * @}
<> 144:ef7eb2e8f9f7 993 */
<> 144:ef7eb2e8f9f7 994
<> 144:ef7eb2e8f9f7 995 /** @defgroup ETH_Promiscuous_Mode ETH Promiscuous Mode
<> 144:ef7eb2e8f9f7 996 * @{
<> 144:ef7eb2e8f9f7 997 */
<> 144:ef7eb2e8f9f7 998 #define ETH_PROMISCUOUS_MODE_ENABLE ((uint32_t)0x00000001)
<> 144:ef7eb2e8f9f7 999 #define ETH_PROMISCUOUS_MODE_DISABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 1000
<> 144:ef7eb2e8f9f7 1001 /**
<> 144:ef7eb2e8f9f7 1002 * @}
<> 144:ef7eb2e8f9f7 1003 */
<> 144:ef7eb2e8f9f7 1004
<> 144:ef7eb2e8f9f7 1005 /** @defgroup ETH_Multicast_Frames_Filter ETH Multicast Frames Filter
<> 144:ef7eb2e8f9f7 1006 * @{
<> 144:ef7eb2e8f9f7 1007 */
<> 144:ef7eb2e8f9f7 1008 #define ETH_MULTICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000404)
<> 144:ef7eb2e8f9f7 1009 #define ETH_MULTICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000004)
<> 144:ef7eb2e8f9f7 1010 #define ETH_MULTICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 1011 #define ETH_MULTICASTFRAMESFILTER_NONE ((uint32_t)0x00000010)
<> 144:ef7eb2e8f9f7 1012
<> 144:ef7eb2e8f9f7 1013 /**
<> 144:ef7eb2e8f9f7 1014 * @}
<> 144:ef7eb2e8f9f7 1015 */
<> 144:ef7eb2e8f9f7 1016
<> 144:ef7eb2e8f9f7 1017 /** @defgroup ETH_Unicast_Frames_Filter ETH Unicast Frames Filter
<> 144:ef7eb2e8f9f7 1018 * @{
<> 144:ef7eb2e8f9f7 1019 */
<> 144:ef7eb2e8f9f7 1020 #define ETH_UNICASTFRAMESFILTER_PERFECTHASHTABLE ((uint32_t)0x00000402)
<> 144:ef7eb2e8f9f7 1021 #define ETH_UNICASTFRAMESFILTER_HASHTABLE ((uint32_t)0x00000002)
<> 144:ef7eb2e8f9f7 1022 #define ETH_UNICASTFRAMESFILTER_PERFECT ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 1023
<> 144:ef7eb2e8f9f7 1024 /**
<> 144:ef7eb2e8f9f7 1025 * @}
<> 144:ef7eb2e8f9f7 1026 */
<> 144:ef7eb2e8f9f7 1027
<> 144:ef7eb2e8f9f7 1028 /** @defgroup ETH_Zero_Quanta_Pause ETH Zero Quanta Pause
<> 144:ef7eb2e8f9f7 1029 * @{
<> 144:ef7eb2e8f9f7 1030 */
<> 144:ef7eb2e8f9f7 1031 #define ETH_ZEROQUANTAPAUSE_ENABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 1032 #define ETH_ZEROQUANTAPAUSE_DISABLE ((uint32_t)0x00000080)
<> 144:ef7eb2e8f9f7 1033
<> 144:ef7eb2e8f9f7 1034 /**
<> 144:ef7eb2e8f9f7 1035 * @}
<> 144:ef7eb2e8f9f7 1036 */
<> 144:ef7eb2e8f9f7 1037
<> 144:ef7eb2e8f9f7 1038 /** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold
<> 144:ef7eb2e8f9f7 1039 * @{
<> 144:ef7eb2e8f9f7 1040 */
<> 144:ef7eb2e8f9f7 1041 #define ETH_PAUSELOWTHRESHOLD_MINUS4 ((uint32_t)0x00000000) /*!< Pause time minus 4 slot times */
<> 144:ef7eb2e8f9f7 1042 #define ETH_PAUSELOWTHRESHOLD_MINUS28 ((uint32_t)0x00000010) /*!< Pause time minus 28 slot times */
<> 144:ef7eb2e8f9f7 1043 #define ETH_PAUSELOWTHRESHOLD_MINUS144 ((uint32_t)0x00000020) /*!< Pause time minus 144 slot times */
<> 144:ef7eb2e8f9f7 1044 #define ETH_PAUSELOWTHRESHOLD_MINUS256 ((uint32_t)0x00000030) /*!< Pause time minus 256 slot times */
<> 144:ef7eb2e8f9f7 1045
<> 144:ef7eb2e8f9f7 1046 /**
<> 144:ef7eb2e8f9f7 1047 * @}
<> 144:ef7eb2e8f9f7 1048 */
<> 144:ef7eb2e8f9f7 1049
<> 144:ef7eb2e8f9f7 1050 /** @defgroup ETH_Unicast_Pause_Frame_Detect ETH Unicast Pause Frame Detect
<> 144:ef7eb2e8f9f7 1051 * @{
<> 144:ef7eb2e8f9f7 1052 */
<> 144:ef7eb2e8f9f7 1053 #define ETH_UNICASTPAUSEFRAMEDETECT_ENABLE ((uint32_t)0x00000008)
<> 144:ef7eb2e8f9f7 1054 #define ETH_UNICASTPAUSEFRAMEDETECT_DISABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 1055
<> 144:ef7eb2e8f9f7 1056 /**
<> 144:ef7eb2e8f9f7 1057 * @}
<> 144:ef7eb2e8f9f7 1058 */
<> 144:ef7eb2e8f9f7 1059
<> 144:ef7eb2e8f9f7 1060 /** @defgroup ETH_Receive_Flow_Control ETH Receive Flow Control
<> 144:ef7eb2e8f9f7 1061 * @{
<> 144:ef7eb2e8f9f7 1062 */
<> 144:ef7eb2e8f9f7 1063 #define ETH_RECEIVEFLOWCONTROL_ENABLE ((uint32_t)0x00000004)
<> 144:ef7eb2e8f9f7 1064 #define ETH_RECEIVEFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 1065
<> 144:ef7eb2e8f9f7 1066 /**
<> 144:ef7eb2e8f9f7 1067 * @}
<> 144:ef7eb2e8f9f7 1068 */
<> 144:ef7eb2e8f9f7 1069
<> 144:ef7eb2e8f9f7 1070 /** @defgroup ETH_Transmit_Flow_Control ETH Transmit Flow Control
<> 144:ef7eb2e8f9f7 1071 * @{
<> 144:ef7eb2e8f9f7 1072 */
<> 144:ef7eb2e8f9f7 1073 #define ETH_TRANSMITFLOWCONTROL_ENABLE ((uint32_t)0x00000002)
<> 144:ef7eb2e8f9f7 1074 #define ETH_TRANSMITFLOWCONTROL_DISABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 1075
<> 144:ef7eb2e8f9f7 1076 /**
<> 144:ef7eb2e8f9f7 1077 * @}
<> 144:ef7eb2e8f9f7 1078 */
<> 144:ef7eb2e8f9f7 1079
<> 144:ef7eb2e8f9f7 1080 /** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
<> 144:ef7eb2e8f9f7 1081 * @{
<> 144:ef7eb2e8f9f7 1082 */
<> 144:ef7eb2e8f9f7 1083 #define ETH_VLANTAGCOMPARISON_12BIT ((uint32_t)0x00010000)
<> 144:ef7eb2e8f9f7 1084 #define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 1085
<> 144:ef7eb2e8f9f7 1086 /**
<> 144:ef7eb2e8f9f7 1087 * @}
<> 144:ef7eb2e8f9f7 1088 */
<> 144:ef7eb2e8f9f7 1089
<> 144:ef7eb2e8f9f7 1090 /** @defgroup ETH_MAC_addresses ETH MAC addresses
<> 144:ef7eb2e8f9f7 1091 * @{
<> 144:ef7eb2e8f9f7 1092 */
<> 144:ef7eb2e8f9f7 1093 #define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 1094 #define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008)
<> 144:ef7eb2e8f9f7 1095 #define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010)
<> 144:ef7eb2e8f9f7 1096 #define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018)
<> 144:ef7eb2e8f9f7 1097
<> 144:ef7eb2e8f9f7 1098 /**
<> 144:ef7eb2e8f9f7 1099 * @}
<> 144:ef7eb2e8f9f7 1100 */
<> 144:ef7eb2e8f9f7 1101
<> 144:ef7eb2e8f9f7 1102 /** @defgroup ETH_MAC_Addresses_Filter_SA_DA ETH MAC Addresses Filter SA DA
<> 144:ef7eb2e8f9f7 1103 * @{
<> 144:ef7eb2e8f9f7 1104 */
<> 144:ef7eb2e8f9f7 1105 #define ETH_MAC_ADDRESSFILTER_SA ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 1106 #define ETH_MAC_ADDRESSFILTER_DA ((uint32_t)0x00000008)
<> 144:ef7eb2e8f9f7 1107 /**
<> 144:ef7eb2e8f9f7 1108 * @}
<> 144:ef7eb2e8f9f7 1109 */
<> 144:ef7eb2e8f9f7 1110
<> 144:ef7eb2e8f9f7 1111 /** @defgroup ETH_MAC_Addresses_Filter_Mask_Bytes ETH_MAC Addresses Filter Mask Bytes
<> 144:ef7eb2e8f9f7 1112 * @{
<> 144:ef7eb2e8f9f7 1113 */
<> 144:ef7eb2e8f9f7 1114 #define ETH_MAC_ADDRESSMASK_BYTE6 ((uint32_t)0x20000000) /*!< Mask MAC Address high reg bits [15:8] */
<> 144:ef7eb2e8f9f7 1115 #define ETH_MAC_ADDRESSMASK_BYTE5 ((uint32_t)0x10000000) /*!< Mask MAC Address high reg bits [7:0] */
<> 144:ef7eb2e8f9f7 1116 #define ETH_MAC_ADDRESSMASK_BYTE4 ((uint32_t)0x08000000) /*!< Mask MAC Address low reg bits [31:24] */
<> 144:ef7eb2e8f9f7 1117 #define ETH_MAC_ADDRESSMASK_BYTE3 ((uint32_t)0x04000000) /*!< Mask MAC Address low reg bits [23:16] */
<> 144:ef7eb2e8f9f7 1118 #define ETH_MAC_ADDRESSMASK_BYTE2 ((uint32_t)0x02000000) /*!< Mask MAC Address low reg bits [15:8] */
<> 144:ef7eb2e8f9f7 1119 #define ETH_MAC_ADDRESSMASK_BYTE1 ((uint32_t)0x01000000) /*!< Mask MAC Address low reg bits [70] */
<> 144:ef7eb2e8f9f7 1120
<> 144:ef7eb2e8f9f7 1121 /**
<> 144:ef7eb2e8f9f7 1122 * @}
<> 144:ef7eb2e8f9f7 1123 */
<> 144:ef7eb2e8f9f7 1124
<> 144:ef7eb2e8f9f7 1125 /** @defgroup ETH_Drop_TCP_IP_Checksum_Error_Frame ETH Drop TCP IP Checksum Error Frame
<> 144:ef7eb2e8f9f7 1126 * @{
<> 144:ef7eb2e8f9f7 1127 */
<> 144:ef7eb2e8f9f7 1128 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_ENABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 1129 #define ETH_DROPTCPIPCHECKSUMERRORFRAME_DISABLE ((uint32_t)0x04000000)
<> 144:ef7eb2e8f9f7 1130
<> 144:ef7eb2e8f9f7 1131 /**
<> 144:ef7eb2e8f9f7 1132 * @}
<> 144:ef7eb2e8f9f7 1133 */
<> 144:ef7eb2e8f9f7 1134
<> 144:ef7eb2e8f9f7 1135 /** @defgroup ETH_Receive_Store_Forward ETH Receive Store Forward
<> 144:ef7eb2e8f9f7 1136 * @{
<> 144:ef7eb2e8f9f7 1137 */
<> 144:ef7eb2e8f9f7 1138 #define ETH_RECEIVESTOREFORWARD_ENABLE ((uint32_t)0x02000000)
<> 144:ef7eb2e8f9f7 1139 #define ETH_RECEIVESTOREFORWARD_DISABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 1140
<> 144:ef7eb2e8f9f7 1141 /**
<> 144:ef7eb2e8f9f7 1142 * @}
<> 144:ef7eb2e8f9f7 1143 */
<> 144:ef7eb2e8f9f7 1144
<> 144:ef7eb2e8f9f7 1145 /** @defgroup ETH_Flush_Received_Frame ETH Flush Received Frame
<> 144:ef7eb2e8f9f7 1146 * @{
<> 144:ef7eb2e8f9f7 1147 */
<> 144:ef7eb2e8f9f7 1148 #define ETH_FLUSHRECEIVEDFRAME_ENABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 1149 #define ETH_FLUSHRECEIVEDFRAME_DISABLE ((uint32_t)0x01000000)
<> 144:ef7eb2e8f9f7 1150
<> 144:ef7eb2e8f9f7 1151 /**
<> 144:ef7eb2e8f9f7 1152 * @}
<> 144:ef7eb2e8f9f7 1153 */
<> 144:ef7eb2e8f9f7 1154
<> 144:ef7eb2e8f9f7 1155 /** @defgroup ETH_Transmit_Store_Forward ETH Transmit Store Forward
<> 144:ef7eb2e8f9f7 1156 * @{
<> 144:ef7eb2e8f9f7 1157 */
<> 144:ef7eb2e8f9f7 1158 #define ETH_TRANSMITSTOREFORWARD_ENABLE ((uint32_t)0x00200000)
<> 144:ef7eb2e8f9f7 1159 #define ETH_TRANSMITSTOREFORWARD_DISABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 1160
<> 144:ef7eb2e8f9f7 1161 /**
<> 144:ef7eb2e8f9f7 1162 * @}
<> 144:ef7eb2e8f9f7 1163 */
<> 144:ef7eb2e8f9f7 1164
<> 144:ef7eb2e8f9f7 1165 /** @defgroup ETH_Transmit_Threshold_Control ETH Transmit Threshold Control
<> 144:ef7eb2e8f9f7 1166 * @{
<> 144:ef7eb2e8f9f7 1167 */
<> 144:ef7eb2e8f9f7 1168 #define ETH_TRANSMITTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /*!< threshold level of the MTL Transmit FIFO is 64 Bytes */
<> 144:ef7eb2e8f9f7 1169 #define ETH_TRANSMITTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00004000) /*!< threshold level of the MTL Transmit FIFO is 128 Bytes */
<> 144:ef7eb2e8f9f7 1170 #define ETH_TRANSMITTHRESHOLDCONTROL_192BYTES ((uint32_t)0x00008000) /*!< threshold level of the MTL Transmit FIFO is 192 Bytes */
<> 144:ef7eb2e8f9f7 1171 #define ETH_TRANSMITTHRESHOLDCONTROL_256BYTES ((uint32_t)0x0000C000) /*!< threshold level of the MTL Transmit FIFO is 256 Bytes */
<> 144:ef7eb2e8f9f7 1172 #define ETH_TRANSMITTHRESHOLDCONTROL_40BYTES ((uint32_t)0x00010000) /*!< threshold level of the MTL Transmit FIFO is 40 Bytes */
<> 144:ef7eb2e8f9f7 1173 #define ETH_TRANSMITTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00014000) /*!< threshold level of the MTL Transmit FIFO is 32 Bytes */
<> 144:ef7eb2e8f9f7 1174 #define ETH_TRANSMITTHRESHOLDCONTROL_24BYTES ((uint32_t)0x00018000) /*!< threshold level of the MTL Transmit FIFO is 24 Bytes */
<> 144:ef7eb2e8f9f7 1175 #define ETH_TRANSMITTHRESHOLDCONTROL_16BYTES ((uint32_t)0x0001C000) /*!< threshold level of the MTL Transmit FIFO is 16 Bytes */
<> 144:ef7eb2e8f9f7 1176
<> 144:ef7eb2e8f9f7 1177 /**
<> 144:ef7eb2e8f9f7 1178 * @}
<> 144:ef7eb2e8f9f7 1179 */
<> 144:ef7eb2e8f9f7 1180
<> 144:ef7eb2e8f9f7 1181 /** @defgroup ETH_Forward_Error_Frames ETH Forward Error Frames
<> 144:ef7eb2e8f9f7 1182 * @{
<> 144:ef7eb2e8f9f7 1183 */
<> 144:ef7eb2e8f9f7 1184 #define ETH_FORWARDERRORFRAMES_ENABLE ((uint32_t)0x00000080)
<> 144:ef7eb2e8f9f7 1185 #define ETH_FORWARDERRORFRAMES_DISABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 1186
<> 144:ef7eb2e8f9f7 1187 /**
<> 144:ef7eb2e8f9f7 1188 * @}
<> 144:ef7eb2e8f9f7 1189 */
<> 144:ef7eb2e8f9f7 1190
<> 144:ef7eb2e8f9f7 1191 /** @defgroup ETH_Forward_Undersized_Good_Frames ETH Forward Undersized Good Frames
<> 144:ef7eb2e8f9f7 1192 * @{
<> 144:ef7eb2e8f9f7 1193 */
<> 144:ef7eb2e8f9f7 1194 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_ENABLE ((uint32_t)0x00000040)
<> 144:ef7eb2e8f9f7 1195 #define ETH_FORWARDUNDERSIZEDGOODFRAMES_DISABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 1196
<> 144:ef7eb2e8f9f7 1197 /**
<> 144:ef7eb2e8f9f7 1198 * @}
<> 144:ef7eb2e8f9f7 1199 */
<> 144:ef7eb2e8f9f7 1200
<> 144:ef7eb2e8f9f7 1201 /** @defgroup ETH_Receive_Threshold_Control ETH Receive Threshold Control
<> 144:ef7eb2e8f9f7 1202 * @{
<> 144:ef7eb2e8f9f7 1203 */
<> 144:ef7eb2e8f9f7 1204 #define ETH_RECEIVEDTHRESHOLDCONTROL_64BYTES ((uint32_t)0x00000000) /*!< threshold level of the MTL Receive FIFO is 64 Bytes */
<> 144:ef7eb2e8f9f7 1205 #define ETH_RECEIVEDTHRESHOLDCONTROL_32BYTES ((uint32_t)0x00000008) /*!< threshold level of the MTL Receive FIFO is 32 Bytes */
<> 144:ef7eb2e8f9f7 1206 #define ETH_RECEIVEDTHRESHOLDCONTROL_96BYTES ((uint32_t)0x00000010) /*!< threshold level of the MTL Receive FIFO is 96 Bytes */
<> 144:ef7eb2e8f9f7 1207 #define ETH_RECEIVEDTHRESHOLDCONTROL_128BYTES ((uint32_t)0x00000018) /*!< threshold level of the MTL Receive FIFO is 128 Bytes */
<> 144:ef7eb2e8f9f7 1208
<> 144:ef7eb2e8f9f7 1209 /**
<> 144:ef7eb2e8f9f7 1210 * @}
<> 144:ef7eb2e8f9f7 1211 */
<> 144:ef7eb2e8f9f7 1212
<> 144:ef7eb2e8f9f7 1213 /** @defgroup ETH_Second_Frame_Operate ETH Second Frame Operate
<> 144:ef7eb2e8f9f7 1214 * @{
<> 144:ef7eb2e8f9f7 1215 */
<> 144:ef7eb2e8f9f7 1216 #define ETH_SECONDFRAMEOPERARTE_ENABLE ((uint32_t)0x00000004)
<> 144:ef7eb2e8f9f7 1217 #define ETH_SECONDFRAMEOPERARTE_DISABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 1218
<> 144:ef7eb2e8f9f7 1219 /**
<> 144:ef7eb2e8f9f7 1220 * @}
<> 144:ef7eb2e8f9f7 1221 */
<> 144:ef7eb2e8f9f7 1222
<> 144:ef7eb2e8f9f7 1223 /** @defgroup ETH_Address_Aligned_Beats ETH Address Aligned Beats
<> 144:ef7eb2e8f9f7 1224 * @{
<> 144:ef7eb2e8f9f7 1225 */
<> 144:ef7eb2e8f9f7 1226 #define ETH_ADDRESSALIGNEDBEATS_ENABLE ((uint32_t)0x02000000)
<> 144:ef7eb2e8f9f7 1227 #define ETH_ADDRESSALIGNEDBEATS_DISABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 1228
<> 144:ef7eb2e8f9f7 1229 /**
<> 144:ef7eb2e8f9f7 1230 * @}
<> 144:ef7eb2e8f9f7 1231 */
<> 144:ef7eb2e8f9f7 1232
<> 144:ef7eb2e8f9f7 1233 /** @defgroup ETH_Fixed_Burst ETH Fixed Burst
<> 144:ef7eb2e8f9f7 1234 * @{
<> 144:ef7eb2e8f9f7 1235 */
<> 144:ef7eb2e8f9f7 1236 #define ETH_FIXEDBURST_ENABLE ((uint32_t)0x00010000)
<> 144:ef7eb2e8f9f7 1237 #define ETH_FIXEDBURST_DISABLE ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 1238
<> 144:ef7eb2e8f9f7 1239 /**
<> 144:ef7eb2e8f9f7 1240 * @}
<> 144:ef7eb2e8f9f7 1241 */
<> 144:ef7eb2e8f9f7 1242
<> 144:ef7eb2e8f9f7 1243 /** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA_Burst Length
<> 144:ef7eb2e8f9f7 1244 * @{
<> 144:ef7eb2e8f9f7 1245 */
<> 144:ef7eb2e8f9f7 1246 #define ETH_RXDMABURSTLENGTH_1BEAT ((uint32_t)0x00020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 1 */
<> 144:ef7eb2e8f9f7 1247 #define ETH_RXDMABURSTLENGTH_2BEAT ((uint32_t)0x00040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 2 */
<> 144:ef7eb2e8f9f7 1248 #define ETH_RXDMABURSTLENGTH_4BEAT ((uint32_t)0x00080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
<> 144:ef7eb2e8f9f7 1249 #define ETH_RXDMABURSTLENGTH_8BEAT ((uint32_t)0x00100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
<> 144:ef7eb2e8f9f7 1250 #define ETH_RXDMABURSTLENGTH_16BEAT ((uint32_t)0x00200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
<> 144:ef7eb2e8f9f7 1251 #define ETH_RXDMABURSTLENGTH_32BEAT ((uint32_t)0x00400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
<> 144:ef7eb2e8f9f7 1252 #define ETH_RXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01020000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 4 */
<> 144:ef7eb2e8f9f7 1253 #define ETH_RXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01040000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 8 */
<> 144:ef7eb2e8f9f7 1254 #define ETH_RXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01080000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 16 */
<> 144:ef7eb2e8f9f7 1255 #define ETH_RXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01100000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 32 */
<> 144:ef7eb2e8f9f7 1256 #define ETH_RXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01200000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 64 */
<> 144:ef7eb2e8f9f7 1257 #define ETH_RXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01400000) /*!< maximum number of beats to be transferred in one RxDMA transaction is 128 */
<> 144:ef7eb2e8f9f7 1258
<> 144:ef7eb2e8f9f7 1259 /**
<> 144:ef7eb2e8f9f7 1260 * @}
<> 144:ef7eb2e8f9f7 1261 */
<> 144:ef7eb2e8f9f7 1262
<> 144:ef7eb2e8f9f7 1263 /** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
<> 144:ef7eb2e8f9f7 1264 * @{
<> 144:ef7eb2e8f9f7 1265 */
<> 144:ef7eb2e8f9f7 1266 #define ETH_TXDMABURSTLENGTH_1BEAT ((uint32_t)0x00000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 1 */
<> 144:ef7eb2e8f9f7 1267 #define ETH_TXDMABURSTLENGTH_2BEAT ((uint32_t)0x00000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 2 */
<> 144:ef7eb2e8f9f7 1268 #define ETH_TXDMABURSTLENGTH_4BEAT ((uint32_t)0x00000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
<> 144:ef7eb2e8f9f7 1269 #define ETH_TXDMABURSTLENGTH_8BEAT ((uint32_t)0x00000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
<> 144:ef7eb2e8f9f7 1270 #define ETH_TXDMABURSTLENGTH_16BEAT ((uint32_t)0x00001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
<> 144:ef7eb2e8f9f7 1271 #define ETH_TXDMABURSTLENGTH_32BEAT ((uint32_t)0x00002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
<> 144:ef7eb2e8f9f7 1272 #define ETH_TXDMABURSTLENGTH_4XPBL_4BEAT ((uint32_t)0x01000100) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 4 */
<> 144:ef7eb2e8f9f7 1273 #define ETH_TXDMABURSTLENGTH_4XPBL_8BEAT ((uint32_t)0x01000200) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 8 */
<> 144:ef7eb2e8f9f7 1274 #define ETH_TXDMABURSTLENGTH_4XPBL_16BEAT ((uint32_t)0x01000400) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 16 */
<> 144:ef7eb2e8f9f7 1275 #define ETH_TXDMABURSTLENGTH_4XPBL_32BEAT ((uint32_t)0x01000800) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 32 */
<> 144:ef7eb2e8f9f7 1276 #define ETH_TXDMABURSTLENGTH_4XPBL_64BEAT ((uint32_t)0x01001000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 64 */
<> 144:ef7eb2e8f9f7 1277 #define ETH_TXDMABURSTLENGTH_4XPBL_128BEAT ((uint32_t)0x01002000) /*!< maximum number of beats to be transferred in one TxDMA (or both) transaction is 128 */
<> 144:ef7eb2e8f9f7 1278
<> 144:ef7eb2e8f9f7 1279 /**
<> 144:ef7eb2e8f9f7 1280 * @}
<> 144:ef7eb2e8f9f7 1281 */
<> 144:ef7eb2e8f9f7 1282
<> 144:ef7eb2e8f9f7 1283 /** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
<> 144:ef7eb2e8f9f7 1284 * @{
<> 144:ef7eb2e8f9f7 1285 */
<> 144:ef7eb2e8f9f7 1286 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_1_1 ((uint32_t)0x00000000)
<> 144:ef7eb2e8f9f7 1287 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_2_1 ((uint32_t)0x00004000)
<> 144:ef7eb2e8f9f7 1288 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_3_1 ((uint32_t)0x00008000)
<> 144:ef7eb2e8f9f7 1289 #define ETH_DMAARBITRATION_ROUNDROBIN_RXTX_4_1 ((uint32_t)0x0000C000)
<> 144:ef7eb2e8f9f7 1290 #define ETH_DMAARBITRATION_RXPRIORTX ((uint32_t)0x00000002)
<> 144:ef7eb2e8f9f7 1291
<> 144:ef7eb2e8f9f7 1292 /**
<> 144:ef7eb2e8f9f7 1293 * @}
<> 144:ef7eb2e8f9f7 1294 */
<> 144:ef7eb2e8f9f7 1295
<> 144:ef7eb2e8f9f7 1296 /** @defgroup ETH_DMA_Tx_Descriptor_Segment ETH DMA Tx Descriptor Segment
<> 144:ef7eb2e8f9f7 1297 * @{
<> 144:ef7eb2e8f9f7 1298 */
<> 144:ef7eb2e8f9f7 1299 #define ETH_DMATXDESC_LASTSEGMENTS ((uint32_t)0x40000000) /*!< Last Segment */
<> 144:ef7eb2e8f9f7 1300 #define ETH_DMATXDESC_FIRSTSEGMENT ((uint32_t)0x20000000) /*!< First Segment */
<> 144:ef7eb2e8f9f7 1301
<> 144:ef7eb2e8f9f7 1302 /**
<> 144:ef7eb2e8f9f7 1303 * @}
<> 144:ef7eb2e8f9f7 1304 */
<> 144:ef7eb2e8f9f7 1305
<> 144:ef7eb2e8f9f7 1306 /** @defgroup ETH_DMA_Tx_Descriptor_Checksum_Insertion_Control ETH DMA Tx Descriptor Checksum Insertion Control
<> 144:ef7eb2e8f9f7 1307 * @{
<> 144:ef7eb2e8f9f7 1308 */
<> 144:ef7eb2e8f9f7 1309 #define ETH_DMATXDESC_CHECKSUMBYPASS ((uint32_t)0x00000000) /*!< Checksum engine bypass */
<> 144:ef7eb2e8f9f7 1310 #define ETH_DMATXDESC_CHECKSUMIPV4HEADER ((uint32_t)0x00400000) /*!< IPv4 header checksum insertion */
<> 144:ef7eb2e8f9f7 1311 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT ((uint32_t)0x00800000) /*!< TCP/UDP/ICMP checksum insertion. Pseudo header checksum is assumed to be present */
<> 144:ef7eb2e8f9f7 1312 #define ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL ((uint32_t)0x00C00000) /*!< TCP/UDP/ICMP checksum fully in hardware including pseudo header */
<> 144:ef7eb2e8f9f7 1313
<> 144:ef7eb2e8f9f7 1314 /**
<> 144:ef7eb2e8f9f7 1315 * @}
<> 144:ef7eb2e8f9f7 1316 */
<> 144:ef7eb2e8f9f7 1317
<> 144:ef7eb2e8f9f7 1318 /** @defgroup ETH_DMA_Rx_Descriptor_Buffers ETH DMA Rx Descriptor Buffers
<> 144:ef7eb2e8f9f7 1319 * @{
<> 144:ef7eb2e8f9f7 1320 */
<> 144:ef7eb2e8f9f7 1321 #define ETH_DMARXDESC_BUFFER1 ((uint32_t)0x00000000) /*!< DMA Rx Desc Buffer1 */
<> 144:ef7eb2e8f9f7 1322 #define ETH_DMARXDESC_BUFFER2 ((uint32_t)0x00000001) /*!< DMA Rx Desc Buffer2 */
<> 144:ef7eb2e8f9f7 1323
<> 144:ef7eb2e8f9f7 1324 /**
<> 144:ef7eb2e8f9f7 1325 * @}
<> 144:ef7eb2e8f9f7 1326 */
<> 144:ef7eb2e8f9f7 1327
<> 144:ef7eb2e8f9f7 1328 /** @defgroup ETH_PMT_Flags ETH PMT Flags
<> 144:ef7eb2e8f9f7 1329 * @{
<> 144:ef7eb2e8f9f7 1330 */
<> 144:ef7eb2e8f9f7 1331 #define ETH_PMT_FLAG_WUFFRPR ((uint32_t)0x80000000) /*!< Wake-Up Frame Filter Register Pointer Reset */
<> 144:ef7eb2e8f9f7 1332 #define ETH_PMT_FLAG_WUFR ((uint32_t)0x00000040) /*!< Wake-Up Frame Received */
<> 144:ef7eb2e8f9f7 1333 #define ETH_PMT_FLAG_MPR ((uint32_t)0x00000020) /*!< Magic Packet Received */
<> 144:ef7eb2e8f9f7 1334
<> 144:ef7eb2e8f9f7 1335 /**
<> 144:ef7eb2e8f9f7 1336 * @}
<> 144:ef7eb2e8f9f7 1337 */
<> 144:ef7eb2e8f9f7 1338
<> 144:ef7eb2e8f9f7 1339 /** @defgroup ETH_MMC_Tx_Interrupts ETH MMC Tx Interrupts
<> 144:ef7eb2e8f9f7 1340 * @{
<> 144:ef7eb2e8f9f7 1341 */
<> 144:ef7eb2e8f9f7 1342 #define ETH_MMC_IT_TGF ((uint32_t)0x00200000) /*!< When Tx good frame counter reaches half the maximum value */
<> 144:ef7eb2e8f9f7 1343 #define ETH_MMC_IT_TGFMSC ((uint32_t)0x00008000) /*!< When Tx good multi col counter reaches half the maximum value */
<> 144:ef7eb2e8f9f7 1344 #define ETH_MMC_IT_TGFSC ((uint32_t)0x00004000) /*!< When Tx good single col counter reaches half the maximum value */
<> 144:ef7eb2e8f9f7 1345
<> 144:ef7eb2e8f9f7 1346 /**
<> 144:ef7eb2e8f9f7 1347 * @}
<> 144:ef7eb2e8f9f7 1348 */
<> 144:ef7eb2e8f9f7 1349
<> 144:ef7eb2e8f9f7 1350 /** @defgroup ETH_MMC_Rx_Interrupts ETH MMC Rx Interrupts
<> 144:ef7eb2e8f9f7 1351 * @{
<> 144:ef7eb2e8f9f7 1352 */
<> 144:ef7eb2e8f9f7 1353 #define ETH_MMC_IT_RGUF ((uint32_t)0x10020000) /*!< When Rx good unicast frames counter reaches half the maximum value */
<> 144:ef7eb2e8f9f7 1354 #define ETH_MMC_IT_RFAE ((uint32_t)0x10000040) /*!< When Rx alignment error counter reaches half the maximum value */
<> 144:ef7eb2e8f9f7 1355 #define ETH_MMC_IT_RFCE ((uint32_t)0x10000020) /*!< When Rx crc error counter reaches half the maximum value */
<> 144:ef7eb2e8f9f7 1356
<> 144:ef7eb2e8f9f7 1357 /**
<> 144:ef7eb2e8f9f7 1358 * @}
<> 144:ef7eb2e8f9f7 1359 */
<> 144:ef7eb2e8f9f7 1360
<> 144:ef7eb2e8f9f7 1361 /** @defgroup ETH_MAC_Flags ETH MAC Flags
<> 144:ef7eb2e8f9f7 1362 * @{
<> 144:ef7eb2e8f9f7 1363 */
<> 144:ef7eb2e8f9f7 1364 #define ETH_MAC_FLAG_TST ((uint32_t)0x00000200) /*!< Time stamp trigger flag (on MAC) */
<> 144:ef7eb2e8f9f7 1365 #define ETH_MAC_FLAG_MMCT ((uint32_t)0x00000040) /*!< MMC transmit flag */
<> 144:ef7eb2e8f9f7 1366 #define ETH_MAC_FLAG_MMCR ((uint32_t)0x00000020) /*!< MMC receive flag */
<> 144:ef7eb2e8f9f7 1367 #define ETH_MAC_FLAG_MMC ((uint32_t)0x00000010) /*!< MMC flag (on MAC) */
<> 144:ef7eb2e8f9f7 1368 #define ETH_MAC_FLAG_PMT ((uint32_t)0x00000008) /*!< PMT flag (on MAC) */
<> 144:ef7eb2e8f9f7 1369
<> 144:ef7eb2e8f9f7 1370 /**
<> 144:ef7eb2e8f9f7 1371 * @}
<> 144:ef7eb2e8f9f7 1372 */
<> 144:ef7eb2e8f9f7 1373
<> 144:ef7eb2e8f9f7 1374 /** @defgroup ETH_DMA_Flags ETH DMA Flags
<> 144:ef7eb2e8f9f7 1375 * @{
<> 144:ef7eb2e8f9f7 1376 */
<> 144:ef7eb2e8f9f7 1377 #define ETH_DMA_FLAG_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */
<> 144:ef7eb2e8f9f7 1378 #define ETH_DMA_FLAG_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */
<> 144:ef7eb2e8f9f7 1379 #define ETH_DMA_FLAG_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */
<> 144:ef7eb2e8f9f7 1380 #define ETH_DMA_FLAG_DATATRANSFERERROR ((uint32_t)0x00800000) /*!< Error bits 0-Rx DMA, 1-Tx DMA */
<> 144:ef7eb2e8f9f7 1381 #define ETH_DMA_FLAG_READWRITEERROR ((uint32_t)0x01000000) /*!< Error bits 0-write trnsf, 1-read transfr */
<> 144:ef7eb2e8f9f7 1382 #define ETH_DMA_FLAG_ACCESSERROR ((uint32_t)0x02000000) /*!< Error bits 0-data buffer, 1-desc. access */
<> 144:ef7eb2e8f9f7 1383 #define ETH_DMA_FLAG_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary flag */
<> 144:ef7eb2e8f9f7 1384 #define ETH_DMA_FLAG_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary flag */
<> 144:ef7eb2e8f9f7 1385 #define ETH_DMA_FLAG_ER ((uint32_t)0x00004000) /*!< Early receive flag */
<> 144:ef7eb2e8f9f7 1386 #define ETH_DMA_FLAG_FBE ((uint32_t)0x00002000) /*!< Fatal bus error flag */
<> 144:ef7eb2e8f9f7 1387 #define ETH_DMA_FLAG_ET ((uint32_t)0x00000400) /*!< Early transmit flag */
<> 144:ef7eb2e8f9f7 1388 #define ETH_DMA_FLAG_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout flag */
<> 144:ef7eb2e8f9f7 1389 #define ETH_DMA_FLAG_RPS ((uint32_t)0x00000100) /*!< Receive process stopped flag */
<> 144:ef7eb2e8f9f7 1390 #define ETH_DMA_FLAG_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable flag */
<> 144:ef7eb2e8f9f7 1391 #define ETH_DMA_FLAG_R ((uint32_t)0x00000040) /*!< Receive flag */
<> 144:ef7eb2e8f9f7 1392 #define ETH_DMA_FLAG_TU ((uint32_t)0x00000020) /*!< Underflow flag */
<> 144:ef7eb2e8f9f7 1393 #define ETH_DMA_FLAG_RO ((uint32_t)0x00000010) /*!< Overflow flag */
<> 144:ef7eb2e8f9f7 1394 #define ETH_DMA_FLAG_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout flag */
<> 144:ef7eb2e8f9f7 1395 #define ETH_DMA_FLAG_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable flag */
<> 144:ef7eb2e8f9f7 1396 #define ETH_DMA_FLAG_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped flag */
<> 144:ef7eb2e8f9f7 1397 #define ETH_DMA_FLAG_T ((uint32_t)0x00000001) /*!< Transmit flag */
<> 144:ef7eb2e8f9f7 1398
<> 144:ef7eb2e8f9f7 1399 /**
<> 144:ef7eb2e8f9f7 1400 * @}
<> 144:ef7eb2e8f9f7 1401 */
<> 144:ef7eb2e8f9f7 1402
<> 144:ef7eb2e8f9f7 1403 /** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
<> 144:ef7eb2e8f9f7 1404 * @{
<> 144:ef7eb2e8f9f7 1405 */
<> 144:ef7eb2e8f9f7 1406 #define ETH_MAC_IT_TST ((uint32_t)0x00000200) /*!< Time stamp trigger interrupt (on MAC) */
<> 144:ef7eb2e8f9f7 1407 #define ETH_MAC_IT_MMCT ((uint32_t)0x00000040) /*!< MMC transmit interrupt */
<> 144:ef7eb2e8f9f7 1408 #define ETH_MAC_IT_MMCR ((uint32_t)0x00000020) /*!< MMC receive interrupt */
<> 144:ef7eb2e8f9f7 1409 #define ETH_MAC_IT_MMC ((uint32_t)0x00000010) /*!< MMC interrupt (on MAC) */
<> 144:ef7eb2e8f9f7 1410 #define ETH_MAC_IT_PMT ((uint32_t)0x00000008) /*!< PMT interrupt (on MAC) */
<> 144:ef7eb2e8f9f7 1411
<> 144:ef7eb2e8f9f7 1412 /**
<> 144:ef7eb2e8f9f7 1413 * @}
<> 144:ef7eb2e8f9f7 1414 */
<> 144:ef7eb2e8f9f7 1415
<> 144:ef7eb2e8f9f7 1416 /** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
<> 144:ef7eb2e8f9f7 1417 * @{
<> 144:ef7eb2e8f9f7 1418 */
<> 144:ef7eb2e8f9f7 1419 #define ETH_DMA_IT_TST ((uint32_t)0x20000000) /*!< Time-stamp trigger interrupt (on DMA) */
<> 144:ef7eb2e8f9f7 1420 #define ETH_DMA_IT_PMT ((uint32_t)0x10000000) /*!< PMT interrupt (on DMA) */
<> 144:ef7eb2e8f9f7 1421 #define ETH_DMA_IT_MMC ((uint32_t)0x08000000) /*!< MMC interrupt (on DMA) */
<> 144:ef7eb2e8f9f7 1422 #define ETH_DMA_IT_NIS ((uint32_t)0x00010000) /*!< Normal interrupt summary */
<> 144:ef7eb2e8f9f7 1423 #define ETH_DMA_IT_AIS ((uint32_t)0x00008000) /*!< Abnormal interrupt summary */
<> 144:ef7eb2e8f9f7 1424 #define ETH_DMA_IT_ER ((uint32_t)0x00004000) /*!< Early receive interrupt */
<> 144:ef7eb2e8f9f7 1425 #define ETH_DMA_IT_FBE ((uint32_t)0x00002000) /*!< Fatal bus error interrupt */
<> 144:ef7eb2e8f9f7 1426 #define ETH_DMA_IT_ET ((uint32_t)0x00000400) /*!< Early transmit interrupt */
<> 144:ef7eb2e8f9f7 1427 #define ETH_DMA_IT_RWT ((uint32_t)0x00000200) /*!< Receive watchdog timeout interrupt */
<> 144:ef7eb2e8f9f7 1428 #define ETH_DMA_IT_RPS ((uint32_t)0x00000100) /*!< Receive process stopped interrupt */
<> 144:ef7eb2e8f9f7 1429 #define ETH_DMA_IT_RBU ((uint32_t)0x00000080) /*!< Receive buffer unavailable interrupt */
<> 144:ef7eb2e8f9f7 1430 #define ETH_DMA_IT_R ((uint32_t)0x00000040) /*!< Receive interrupt */
<> 144:ef7eb2e8f9f7 1431 #define ETH_DMA_IT_TU ((uint32_t)0x00000020) /*!< Underflow interrupt */
<> 144:ef7eb2e8f9f7 1432 #define ETH_DMA_IT_RO ((uint32_t)0x00000010) /*!< Overflow interrupt */
<> 144:ef7eb2e8f9f7 1433 #define ETH_DMA_IT_TJT ((uint32_t)0x00000008) /*!< Transmit jabber timeout interrupt */
<> 144:ef7eb2e8f9f7 1434 #define ETH_DMA_IT_TBU ((uint32_t)0x00000004) /*!< Transmit buffer unavailable interrupt */
<> 144:ef7eb2e8f9f7 1435 #define ETH_DMA_IT_TPS ((uint32_t)0x00000002) /*!< Transmit process stopped interrupt */
<> 144:ef7eb2e8f9f7 1436 #define ETH_DMA_IT_T ((uint32_t)0x00000001) /*!< Transmit interrupt */
<> 144:ef7eb2e8f9f7 1437
<> 144:ef7eb2e8f9f7 1438 /**
<> 144:ef7eb2e8f9f7 1439 * @}
<> 144:ef7eb2e8f9f7 1440 */
<> 144:ef7eb2e8f9f7 1441
<> 144:ef7eb2e8f9f7 1442 /** @defgroup ETH_DMA_transmit_process_state ETH DMA transmit process state
<> 144:ef7eb2e8f9f7 1443 * @{
<> 144:ef7eb2e8f9f7 1444 */
<> 144:ef7eb2e8f9f7 1445 #define ETH_DMA_TRANSMITPROCESS_STOPPED ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Tx Command issued */
<> 144:ef7eb2e8f9f7 1446 #define ETH_DMA_TRANSMITPROCESS_FETCHING ((uint32_t)0x00100000) /*!< Running - fetching the Tx descriptor */
<> 144:ef7eb2e8f9f7 1447 #define ETH_DMA_TRANSMITPROCESS_WAITING ((uint32_t)0x00200000) /*!< Running - waiting for status */
<> 144:ef7eb2e8f9f7 1448 #define ETH_DMA_TRANSMITPROCESS_READING ((uint32_t)0x00300000) /*!< Running - reading the data from host memory */
<> 144:ef7eb2e8f9f7 1449 #define ETH_DMA_TRANSMITPROCESS_SUSPENDED ((uint32_t)0x00600000) /*!< Suspended - Tx Descriptor unavailable */
<> 144:ef7eb2e8f9f7 1450 #define ETH_DMA_TRANSMITPROCESS_CLOSING ((uint32_t)0x00700000) /*!< Running - closing Rx descriptor */
<> 144:ef7eb2e8f9f7 1451
<> 144:ef7eb2e8f9f7 1452 /**
<> 144:ef7eb2e8f9f7 1453 * @}
<> 144:ef7eb2e8f9f7 1454 */
<> 144:ef7eb2e8f9f7 1455
<> 144:ef7eb2e8f9f7 1456
<> 144:ef7eb2e8f9f7 1457 /** @defgroup ETH_DMA_receive_process_state ETH DMA receive process state
<> 144:ef7eb2e8f9f7 1458 * @{
<> 144:ef7eb2e8f9f7 1459 */
<> 144:ef7eb2e8f9f7 1460 #define ETH_DMA_RECEIVEPROCESS_STOPPED ((uint32_t)0x00000000) /*!< Stopped - Reset or Stop Rx Command issued */
<> 144:ef7eb2e8f9f7 1461 #define ETH_DMA_RECEIVEPROCESS_FETCHING ((uint32_t)0x00020000) /*!< Running - fetching the Rx descriptor */
<> 144:ef7eb2e8f9f7 1462 #define ETH_DMA_RECEIVEPROCESS_WAITING ((uint32_t)0x00060000) /*!< Running - waiting for packet */
<> 144:ef7eb2e8f9f7 1463 #define ETH_DMA_RECEIVEPROCESS_SUSPENDED ((uint32_t)0x00080000) /*!< Suspended - Rx Descriptor unavailable */
<> 144:ef7eb2e8f9f7 1464 #define ETH_DMA_RECEIVEPROCESS_CLOSING ((uint32_t)0x000A0000) /*!< Running - closing descriptor */
<> 144:ef7eb2e8f9f7 1465 #define ETH_DMA_RECEIVEPROCESS_QUEUING ((uint32_t)0x000E0000) /*!< Running - queuing the receive frame into host memory */
<> 144:ef7eb2e8f9f7 1466
<> 144:ef7eb2e8f9f7 1467 /**
<> 144:ef7eb2e8f9f7 1468 * @}
<> 144:ef7eb2e8f9f7 1469 */
<> 144:ef7eb2e8f9f7 1470
<> 144:ef7eb2e8f9f7 1471 /** @defgroup ETH_DMA_overflow ETH DMA overflow
<> 144:ef7eb2e8f9f7 1472 * @{
<> 144:ef7eb2e8f9f7 1473 */
<> 144:ef7eb2e8f9f7 1474 #define ETH_DMA_OVERFLOW_RXFIFOCOUNTER ((uint32_t)0x10000000) /*!< Overflow bit for FIFO overflow counter */
<> 144:ef7eb2e8f9f7 1475 #define ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER ((uint32_t)0x00010000) /*!< Overflow bit for missed frame counter */
<> 144:ef7eb2e8f9f7 1476
<> 144:ef7eb2e8f9f7 1477 /**
<> 144:ef7eb2e8f9f7 1478 * @}
<> 144:ef7eb2e8f9f7 1479 */
<> 144:ef7eb2e8f9f7 1480
<> 144:ef7eb2e8f9f7 1481 /** @defgroup ETH_EXTI_LINE_WAKEUP ETH EXTI LINE WAKEUP
<> 144:ef7eb2e8f9f7 1482 * @{
<> 144:ef7eb2e8f9f7 1483 */
<> 144:ef7eb2e8f9f7 1484 #define ETH_EXTI_LINE_WAKEUP ((uint32_t)0x00080000) /*!< External interrupt line 19 Connected to the ETH EXTI Line */
<> 144:ef7eb2e8f9f7 1485
<> 144:ef7eb2e8f9f7 1486 /**
<> 144:ef7eb2e8f9f7 1487 * @}
<> 144:ef7eb2e8f9f7 1488 */
<> 144:ef7eb2e8f9f7 1489
<> 144:ef7eb2e8f9f7 1490 /**
<> 144:ef7eb2e8f9f7 1491 * @}
<> 144:ef7eb2e8f9f7 1492 */
<> 144:ef7eb2e8f9f7 1493
<> 144:ef7eb2e8f9f7 1494 /* Exported macro ------------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 1495 /** @defgroup ETH_Exported_Macros ETH Exported Macros
<> 144:ef7eb2e8f9f7 1496 * @brief macros to handle interrupts and specific clock configurations
<> 144:ef7eb2e8f9f7 1497 * @{
<> 144:ef7eb2e8f9f7 1498 */
<> 144:ef7eb2e8f9f7 1499
<> 144:ef7eb2e8f9f7 1500 /** @brief Reset ETH handle state
<> 144:ef7eb2e8f9f7 1501 * @param __HANDLE__: specifies the ETH handle.
<> 144:ef7eb2e8f9f7 1502 * @retval None
<> 144:ef7eb2e8f9f7 1503 */
<> 144:ef7eb2e8f9f7 1504 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ETH_STATE_RESET)
<> 144:ef7eb2e8f9f7 1505
<> 144:ef7eb2e8f9f7 1506 /**
<> 144:ef7eb2e8f9f7 1507 * @brief Checks whether the specified ETHERNET DMA Tx Desc flag is set or not.
<> 144:ef7eb2e8f9f7 1508 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1509 * @param __FLAG__: specifies the flag of TDES0 to check .
<> 144:ef7eb2e8f9f7 1510 * @retval the ETH_DMATxDescFlag (SET or RESET).
<> 144:ef7eb2e8f9f7 1511 */
<> 144:ef7eb2e8f9f7 1512 #define __HAL_ETH_DMATXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->TxDesc->Status & (__FLAG__) == (__FLAG__))
<> 144:ef7eb2e8f9f7 1513
<> 144:ef7eb2e8f9f7 1514 /**
<> 144:ef7eb2e8f9f7 1515 * @brief Checks whether the specified ETHERNET DMA Rx Desc flag is set or not.
<> 144:ef7eb2e8f9f7 1516 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1517 * @param __FLAG__: specifies the flag of RDES0 to check.
<> 144:ef7eb2e8f9f7 1518 * @retval the ETH_DMATxDescFlag (SET or RESET).
<> 144:ef7eb2e8f9f7 1519 */
<> 144:ef7eb2e8f9f7 1520 #define __HAL_ETH_DMARXDESC_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->RxDesc->Status & (__FLAG__) == (__FLAG__))
<> 144:ef7eb2e8f9f7 1521
<> 144:ef7eb2e8f9f7 1522 /**
<> 144:ef7eb2e8f9f7 1523 * @brief Enables the specified DMA Rx Desc receive interrupt.
<> 144:ef7eb2e8f9f7 1524 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1525 * @retval None
<> 144:ef7eb2e8f9f7 1526 */
<> 144:ef7eb2e8f9f7 1527 #define __HAL_ETH_DMARXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize &=(~(uint32_t)ETH_DMARXDESC_DIC))
<> 144:ef7eb2e8f9f7 1528
<> 144:ef7eb2e8f9f7 1529 /**
<> 144:ef7eb2e8f9f7 1530 * @brief Disables the specified DMA Rx Desc receive interrupt.
<> 144:ef7eb2e8f9f7 1531 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1532 * @retval None
<> 144:ef7eb2e8f9f7 1533 */
<> 144:ef7eb2e8f9f7 1534 #define __HAL_ETH_DMARXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->RxDesc->ControlBufferSize |= ETH_DMARXDESC_DIC)
<> 144:ef7eb2e8f9f7 1535
<> 144:ef7eb2e8f9f7 1536 /**
<> 144:ef7eb2e8f9f7 1537 * @brief Set the specified DMA Rx Desc Own bit.
<> 144:ef7eb2e8f9f7 1538 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1539 * @retval None
<> 144:ef7eb2e8f9f7 1540 */
<> 144:ef7eb2e8f9f7 1541 #define __HAL_ETH_DMARXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->RxDesc->Status |= ETH_DMARXDESC_OWN)
<> 144:ef7eb2e8f9f7 1542
<> 144:ef7eb2e8f9f7 1543 /**
<> 144:ef7eb2e8f9f7 1544 * @brief Returns the specified ETHERNET DMA Tx Desc collision count.
<> 144:ef7eb2e8f9f7 1545 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1546 * @retval The Transmit descriptor collision counter value.
<> 144:ef7eb2e8f9f7 1547 */
<> 144:ef7eb2e8f9f7 1548 #define __HAL_ETH_DMATXDESC_GET_COLLISION_COUNT(__HANDLE__) (((__HANDLE__)->TxDesc->Status & ETH_DMATXDESC_CC) >> ETH_DMATXDESC_COLLISION_COUNTSHIFT)
<> 144:ef7eb2e8f9f7 1549
<> 144:ef7eb2e8f9f7 1550 /**
<> 144:ef7eb2e8f9f7 1551 * @brief Set the specified DMA Tx Desc Own bit.
<> 144:ef7eb2e8f9f7 1552 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1553 * @retval None
<> 144:ef7eb2e8f9f7 1554 */
<> 144:ef7eb2e8f9f7 1555 #define __HAL_ETH_DMATXDESC_SET_OWN_BIT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_OWN)
<> 144:ef7eb2e8f9f7 1556
<> 144:ef7eb2e8f9f7 1557 /**
<> 144:ef7eb2e8f9f7 1558 * @brief Enables the specified DMA Tx Desc Transmit interrupt.
<> 144:ef7eb2e8f9f7 1559 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1560 * @retval None
<> 144:ef7eb2e8f9f7 1561 */
<> 144:ef7eb2e8f9f7 1562 #define __HAL_ETH_DMATXDESC_ENABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_IC)
<> 144:ef7eb2e8f9f7 1563
<> 144:ef7eb2e8f9f7 1564 /**
<> 144:ef7eb2e8f9f7 1565 * @brief Disables the specified DMA Tx Desc Transmit interrupt.
<> 144:ef7eb2e8f9f7 1566 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1567 * @retval None
<> 144:ef7eb2e8f9f7 1568 */
<> 144:ef7eb2e8f9f7 1569 #define __HAL_ETH_DMATXDESC_DISABLE_IT(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_IC)
<> 144:ef7eb2e8f9f7 1570
<> 144:ef7eb2e8f9f7 1571 /**
<> 144:ef7eb2e8f9f7 1572 * @brief Selects the specified ETHERNET DMA Tx Desc Checksum Insertion.
<> 144:ef7eb2e8f9f7 1573 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1574 * @param __CHECKSUM__: specifies is the DMA Tx desc checksum insertion.
<> 144:ef7eb2e8f9f7 1575 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1576 * @arg ETH_DMATXDESC_CHECKSUMBYPASS : Checksum bypass
<> 144:ef7eb2e8f9f7 1577 * @arg ETH_DMATXDESC_CHECKSUMIPV4HEADER : IPv4 header checksum
<> 144:ef7eb2e8f9f7 1578 * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPSEGMENT : TCP/UDP/ICMP checksum. Pseudo header checksum is assumed to be present
<> 144:ef7eb2e8f9f7 1579 * @arg ETH_DMATXDESC_CHECKSUMTCPUDPICMPFULL : TCP/UDP/ICMP checksum fully in hardware including pseudo header
<> 144:ef7eb2e8f9f7 1580 * @retval None
<> 144:ef7eb2e8f9f7 1581 */
<> 144:ef7eb2e8f9f7 1582 #define __HAL_ETH_DMATXDESC_CHECKSUM_INSERTION(__HANDLE__, __CHECKSUM__) ((__HANDLE__)->TxDesc->Status |= (__CHECKSUM__))
<> 144:ef7eb2e8f9f7 1583
<> 144:ef7eb2e8f9f7 1584 /**
<> 144:ef7eb2e8f9f7 1585 * @brief Enables the DMA Tx Desc CRC.
<> 144:ef7eb2e8f9f7 1586 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1587 * @retval None
<> 144:ef7eb2e8f9f7 1588 */
<> 144:ef7eb2e8f9f7 1589 #define __HAL_ETH_DMATXDESC_CRC_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DC)
<> 144:ef7eb2e8f9f7 1590
<> 144:ef7eb2e8f9f7 1591 /**
<> 144:ef7eb2e8f9f7 1592 * @brief Disables the DMA Tx Desc CRC.
<> 144:ef7eb2e8f9f7 1593 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1594 * @retval None
<> 144:ef7eb2e8f9f7 1595 */
<> 144:ef7eb2e8f9f7 1596 #define __HAL_ETH_DMATXDESC_CRC_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DC)
<> 144:ef7eb2e8f9f7 1597
<> 144:ef7eb2e8f9f7 1598 /**
<> 144:ef7eb2e8f9f7 1599 * @brief Enables the DMA Tx Desc padding for frame shorter than 64 bytes.
<> 144:ef7eb2e8f9f7 1600 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1601 * @retval None
<> 144:ef7eb2e8f9f7 1602 */
<> 144:ef7eb2e8f9f7 1603 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_ENABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status &= ~ETH_DMATXDESC_DP)
<> 144:ef7eb2e8f9f7 1604
<> 144:ef7eb2e8f9f7 1605 /**
<> 144:ef7eb2e8f9f7 1606 * @brief Disables the DMA Tx Desc padding for frame shorter than 64 bytes.
<> 144:ef7eb2e8f9f7 1607 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1608 * @retval None
<> 144:ef7eb2e8f9f7 1609 */
<> 144:ef7eb2e8f9f7 1610 #define __HAL_ETH_DMATXDESC_SHORT_FRAME_PADDING_DISABLE(__HANDLE__) ((__HANDLE__)->TxDesc->Status |= ETH_DMATXDESC_DP)
<> 144:ef7eb2e8f9f7 1611
<> 144:ef7eb2e8f9f7 1612 /**
<> 144:ef7eb2e8f9f7 1613 * @brief Enables the specified ETHERNET MAC interrupts.
<> 144:ef7eb2e8f9f7 1614 * @param __HANDLE__ : ETH Handle
<> 144:ef7eb2e8f9f7 1615 * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
<> 144:ef7eb2e8f9f7 1616 * enabled or disabled.
<> 144:ef7eb2e8f9f7 1617 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 1618 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
<> 144:ef7eb2e8f9f7 1619 * @arg ETH_MAC_IT_PMT : PMT interrupt
<> 144:ef7eb2e8f9f7 1620 * @retval None
<> 144:ef7eb2e8f9f7 1621 */
<> 144:ef7eb2e8f9f7 1622 #define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR |= (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 1623
<> 144:ef7eb2e8f9f7 1624 /**
<> 144:ef7eb2e8f9f7 1625 * @brief Disables the specified ETHERNET MAC interrupts.
<> 144:ef7eb2e8f9f7 1626 * @param __HANDLE__ : ETH Handle
<> 144:ef7eb2e8f9f7 1627 * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
<> 144:ef7eb2e8f9f7 1628 * enabled or disabled.
<> 144:ef7eb2e8f9f7 1629 * This parameter can be any combination of the following values:
<> 144:ef7eb2e8f9f7 1630 * @arg ETH_MAC_IT_TST : Time stamp trigger interrupt
<> 144:ef7eb2e8f9f7 1631 * @arg ETH_MAC_IT_PMT : PMT interrupt
<> 144:ef7eb2e8f9f7 1632 * @retval None
<> 144:ef7eb2e8f9f7 1633 */
<> 144:ef7eb2e8f9f7 1634 #define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIMR &= ~(__INTERRUPT__))
<> 144:ef7eb2e8f9f7 1635
<> 144:ef7eb2e8f9f7 1636 /**
<> 144:ef7eb2e8f9f7 1637 * @brief Initiate a Pause Control Frame (Full-duplex only).
<> 144:ef7eb2e8f9f7 1638 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1639 * @retval None
<> 144:ef7eb2e8f9f7 1640 */
<> 144:ef7eb2e8f9f7 1641 #define __HAL_ETH_INITIATE_PAUSE_CONTROL_FRAME(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
<> 144:ef7eb2e8f9f7 1642
<> 144:ef7eb2e8f9f7 1643 /**
<> 144:ef7eb2e8f9f7 1644 * @brief Checks whether the ETHERNET flow control busy bit is set or not.
<> 144:ef7eb2e8f9f7 1645 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1646 * @retval The new state of flow control busy status bit (SET or RESET).
<> 144:ef7eb2e8f9f7 1647 */
<> 144:ef7eb2e8f9f7 1648 #define __HAL_ETH_GET_FLOW_CONTROL_BUSY_STATUS(__HANDLE__) (((__HANDLE__)->Instance->MACFCR & ETH_MACFCR_FCBBPA) == ETH_MACFCR_FCBBPA)
<> 144:ef7eb2e8f9f7 1649
<> 144:ef7eb2e8f9f7 1650 /**
<> 144:ef7eb2e8f9f7 1651 * @brief Enables the MAC Back Pressure operation activation (Half-duplex only).
<> 144:ef7eb2e8f9f7 1652 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1653 * @retval None
<> 144:ef7eb2e8f9f7 1654 */
<> 144:ef7eb2e8f9f7 1655 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR |= ETH_MACFCR_FCBBPA)
<> 144:ef7eb2e8f9f7 1656
<> 144:ef7eb2e8f9f7 1657 /**
<> 144:ef7eb2e8f9f7 1658 * @brief Disables the MAC BackPressure operation activation (Half-duplex only).
<> 144:ef7eb2e8f9f7 1659 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1660 * @retval None
<> 144:ef7eb2e8f9f7 1661 */
<> 144:ef7eb2e8f9f7 1662 #define __HAL_ETH_BACK_PRESSURE_ACTIVATION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACFCR &= ~ETH_MACFCR_FCBBPA)
<> 144:ef7eb2e8f9f7 1663
<> 144:ef7eb2e8f9f7 1664 /**
<> 144:ef7eb2e8f9f7 1665 * @brief Checks whether the specified ETHERNET MAC flag is set or not.
<> 144:ef7eb2e8f9f7 1666 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1667 * @param __FLAG__: specifies the flag to check.
<> 144:ef7eb2e8f9f7 1668 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1669 * @arg ETH_MAC_FLAG_TST : Time stamp trigger flag
<> 144:ef7eb2e8f9f7 1670 * @arg ETH_MAC_FLAG_MMCT : MMC transmit flag
<> 144:ef7eb2e8f9f7 1671 * @arg ETH_MAC_FLAG_MMCR : MMC receive flag
<> 144:ef7eb2e8f9f7 1672 * @arg ETH_MAC_FLAG_MMC : MMC flag
<> 144:ef7eb2e8f9f7 1673 * @arg ETH_MAC_FLAG_PMT : PMT flag
<> 144:ef7eb2e8f9f7 1674 * @retval The state of ETHERNET MAC flag.
<> 144:ef7eb2e8f9f7 1675 */
<> 144:ef7eb2e8f9f7 1676 #define __HAL_ETH_MAC_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACSR &( __FLAG__)) == ( __FLAG__))
<> 144:ef7eb2e8f9f7 1677
<> 144:ef7eb2e8f9f7 1678 /**
<> 144:ef7eb2e8f9f7 1679 * @brief Enables the specified ETHERNET DMA interrupts.
<> 144:ef7eb2e8f9f7 1680 * @param __HANDLE__ : ETH Handle
<> 144:ef7eb2e8f9f7 1681 * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
<> 144:ef7eb2e8f9f7 1682 * enabled @ref ETH_DMA_Interrupts
<> 144:ef7eb2e8f9f7 1683 * @retval None
<> 144:ef7eb2e8f9f7 1684 */
<> 144:ef7eb2e8f9f7 1685 #define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER |= (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 1686
<> 144:ef7eb2e8f9f7 1687 /**
<> 144:ef7eb2e8f9f7 1688 * @brief Disables the specified ETHERNET DMA interrupts.
<> 144:ef7eb2e8f9f7 1689 * @param __HANDLE__ : ETH Handle
<> 144:ef7eb2e8f9f7 1690 * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
<> 144:ef7eb2e8f9f7 1691 * disabled. @ref ETH_DMA_Interrupts
<> 144:ef7eb2e8f9f7 1692 * @retval None
<> 144:ef7eb2e8f9f7 1693 */
<> 144:ef7eb2e8f9f7 1694 #define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMAIER &= ~(__INTERRUPT__))
<> 144:ef7eb2e8f9f7 1695
<> 144:ef7eb2e8f9f7 1696 /**
<> 144:ef7eb2e8f9f7 1697 * @brief Clears the ETHERNET DMA IT pending bit.
<> 144:ef7eb2e8f9f7 1698 * @param __HANDLE__ : ETH Handle
<> 144:ef7eb2e8f9f7 1699 * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
<> 144:ef7eb2e8f9f7 1700 * @retval None
<> 144:ef7eb2e8f9f7 1701 */
<> 144:ef7eb2e8f9f7 1702 #define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMASR =(__INTERRUPT__))
<> 144:ef7eb2e8f9f7 1703
<> 144:ef7eb2e8f9f7 1704 /**
<> 144:ef7eb2e8f9f7 1705 * @brief Checks whether the specified ETHERNET DMA flag is set or not.
<> 144:ef7eb2e8f9f7 1706 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1707 * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Flags
<> 144:ef7eb2e8f9f7 1708 * @retval The new state of ETH_DMA_FLAG (SET or RESET).
<> 144:ef7eb2e8f9f7 1709 */
<> 144:ef7eb2e8f9f7 1710 #define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMASR &( __FLAG__)) == ( __FLAG__))
<> 144:ef7eb2e8f9f7 1711
<> 144:ef7eb2e8f9f7 1712 /**
<> 144:ef7eb2e8f9f7 1713 * @brief Checks whether the specified ETHERNET DMA flag is set or not.
<> 144:ef7eb2e8f9f7 1714 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1715 * @param __FLAG__: specifies the flag to clear. @ref ETH_DMA_Flags
<> 144:ef7eb2e8f9f7 1716 * @retval The new state of ETH_DMA_FLAG (SET or RESET).
<> 144:ef7eb2e8f9f7 1717 */
<> 144:ef7eb2e8f9f7 1718 #define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMASR = (__FLAG__))
<> 144:ef7eb2e8f9f7 1719
<> 144:ef7eb2e8f9f7 1720 /**
<> 144:ef7eb2e8f9f7 1721 * @brief Checks whether the specified ETHERNET DMA overflow flag is set or not.
<> 144:ef7eb2e8f9f7 1722 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1723 * @param __OVERFLOW__: specifies the DMA overflow flag to check.
<> 144:ef7eb2e8f9f7 1724 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1725 * @arg ETH_DMA_OVERFLOW_RXFIFOCOUNTER : Overflow for FIFO Overflows Counter
<> 144:ef7eb2e8f9f7 1726 * @arg ETH_DMA_OVERFLOW_MISSEDFRAMECOUNTER : Overflow for Buffer Unavailable Missed Frame Counter
<> 144:ef7eb2e8f9f7 1727 * @retval The state of ETHERNET DMA overflow Flag (SET or RESET).
<> 144:ef7eb2e8f9f7 1728 */
<> 144:ef7eb2e8f9f7 1729 #define __HAL_ETH_GET_DMA_OVERFLOW_STATUS(__HANDLE__, __OVERFLOW__) (((__HANDLE__)->Instance->DMAMFBOCR & (__OVERFLOW__)) == (__OVERFLOW__))
<> 144:ef7eb2e8f9f7 1730
<> 144:ef7eb2e8f9f7 1731 /**
<> 144:ef7eb2e8f9f7 1732 * @brief Set the DMA Receive status watchdog timer register value
<> 144:ef7eb2e8f9f7 1733 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1734 * @param __VALUE__: DMA Receive status watchdog timer register value
<> 144:ef7eb2e8f9f7 1735 * @retval None
<> 144:ef7eb2e8f9f7 1736 */
<> 144:ef7eb2e8f9f7 1737 #define __HAL_ETH_SET_RECEIVE_WATCHDOG_TIMER(__HANDLE__, __VALUE__) ((__HANDLE__)->Instance->DMARSWTR = (__VALUE__))
<> 144:ef7eb2e8f9f7 1738
<> 144:ef7eb2e8f9f7 1739 /**
<> 144:ef7eb2e8f9f7 1740 * @brief Enables any unicast packet filtered by the MAC address
<> 144:ef7eb2e8f9f7 1741 * recognition to be a wake-up frame.
<> 144:ef7eb2e8f9f7 1742 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1743 * @retval None
<> 144:ef7eb2e8f9f7 1744 */
<> 144:ef7eb2e8f9f7 1745 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_GU)
<> 144:ef7eb2e8f9f7 1746
<> 144:ef7eb2e8f9f7 1747 /**
<> 144:ef7eb2e8f9f7 1748 * @brief Disables any unicast packet filtered by the MAC address
<> 144:ef7eb2e8f9f7 1749 * recognition to be a wake-up frame.
<> 144:ef7eb2e8f9f7 1750 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1751 * @retval None
<> 144:ef7eb2e8f9f7 1752 */
<> 144:ef7eb2e8f9f7 1753 #define __HAL_ETH_GLOBAL_UNICAST_WAKEUP_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_GU)
<> 144:ef7eb2e8f9f7 1754
<> 144:ef7eb2e8f9f7 1755 /**
<> 144:ef7eb2e8f9f7 1756 * @brief Enables the MAC Wake-Up Frame Detection.
<> 144:ef7eb2e8f9f7 1757 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1758 * @retval None
<> 144:ef7eb2e8f9f7 1759 */
<> 144:ef7eb2e8f9f7 1760 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_WFE)
<> 144:ef7eb2e8f9f7 1761
<> 144:ef7eb2e8f9f7 1762 /**
<> 144:ef7eb2e8f9f7 1763 * @brief Disables the MAC Wake-Up Frame Detection.
<> 144:ef7eb2e8f9f7 1764 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1765 * @retval None
<> 144:ef7eb2e8f9f7 1766 */
<> 144:ef7eb2e8f9f7 1767 #define __HAL_ETH_WAKEUP_FRAME_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
<> 144:ef7eb2e8f9f7 1768
<> 144:ef7eb2e8f9f7 1769 /**
<> 144:ef7eb2e8f9f7 1770 * @brief Enables the MAC Magic Packet Detection.
<> 144:ef7eb2e8f9f7 1771 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1772 * @retval None
<> 144:ef7eb2e8f9f7 1773 */
<> 144:ef7eb2e8f9f7 1774 #define __HAL_ETH_MAGIC_PACKET_DETECTION_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_MPE)
<> 144:ef7eb2e8f9f7 1775
<> 144:ef7eb2e8f9f7 1776 /**
<> 144:ef7eb2e8f9f7 1777 * @brief Disables the MAC Magic Packet Detection.
<> 144:ef7eb2e8f9f7 1778 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1779 * @retval None
<> 144:ef7eb2e8f9f7 1780 */
<> 144:ef7eb2e8f9f7 1781 #define __HAL_ETH_MAGIC_PACKET_DETECTION_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_WFE)
<> 144:ef7eb2e8f9f7 1782
<> 144:ef7eb2e8f9f7 1783 /**
<> 144:ef7eb2e8f9f7 1784 * @brief Enables the MAC Power Down.
<> 144:ef7eb2e8f9f7 1785 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1786 * @retval None
<> 144:ef7eb2e8f9f7 1787 */
<> 144:ef7eb2e8f9f7 1788 #define __HAL_ETH_POWER_DOWN_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR |= ETH_MACPMTCSR_PD)
<> 144:ef7eb2e8f9f7 1789
<> 144:ef7eb2e8f9f7 1790 /**
<> 144:ef7eb2e8f9f7 1791 * @brief Disables the MAC Power Down.
<> 144:ef7eb2e8f9f7 1792 * @param __HANDLE__: ETH Handle
<> 144:ef7eb2e8f9f7 1793 * @retval None
<> 144:ef7eb2e8f9f7 1794 */
<> 144:ef7eb2e8f9f7 1795 #define __HAL_ETH_POWER_DOWN_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MACPMTCSR &= ~ETH_MACPMTCSR_PD)
<> 144:ef7eb2e8f9f7 1796
<> 144:ef7eb2e8f9f7 1797 /**
<> 144:ef7eb2e8f9f7 1798 * @brief Checks whether the specified ETHERNET PMT flag is set or not.
<> 144:ef7eb2e8f9f7 1799 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1800 * @param __FLAG__: specifies the flag to check.
<> 144:ef7eb2e8f9f7 1801 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1802 * @arg ETH_PMT_FLAG_WUFFRPR : Wake-Up Frame Filter Register Pointer Reset
<> 144:ef7eb2e8f9f7 1803 * @arg ETH_PMT_FLAG_WUFR : Wake-Up Frame Received
<> 144:ef7eb2e8f9f7 1804 * @arg ETH_PMT_FLAG_MPR : Magic Packet Received
<> 144:ef7eb2e8f9f7 1805 * @retval The new state of ETHERNET PMT Flag (SET or RESET).
<> 144:ef7eb2e8f9f7 1806 */
<> 144:ef7eb2e8f9f7 1807 #define __HAL_ETH_GET_PMT_FLAG_STATUS(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->MACPMTCSR &( __FLAG__)) == ( __FLAG__))
<> 144:ef7eb2e8f9f7 1808
<> 144:ef7eb2e8f9f7 1809 /**
<> 144:ef7eb2e8f9f7 1810 * @brief Preset and Initialize the MMC counters to almost-full value: 0xFFFF_FFF0 (full - 16)
<> 144:ef7eb2e8f9f7 1811 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1812 * @retval None
<> 144:ef7eb2e8f9f7 1813 */
<> 144:ef7eb2e8f9f7 1814 #define __HAL_ETH_MMC_COUNTER_FULL_PRESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= (ETH_MMCCR_MCFHP | ETH_MMCCR_MCP))
<> 144:ef7eb2e8f9f7 1815
<> 144:ef7eb2e8f9f7 1816 /**
<> 144:ef7eb2e8f9f7 1817 * @brief Preset and Initialize the MMC counters to almost-half value: 0x7FFF_FFF0 (half - 16)
<> 144:ef7eb2e8f9f7 1818 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1819 * @retval None
<> 144:ef7eb2e8f9f7 1820 */
<> 144:ef7eb2e8f9f7 1821 #define __HAL_ETH_MMC_COUNTER_HALF_PRESET(__HANDLE__) do{(__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCFHP;\
<> 144:ef7eb2e8f9f7 1822 (__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCP;} while (0)
<> 144:ef7eb2e8f9f7 1823
<> 144:ef7eb2e8f9f7 1824 /**
<> 144:ef7eb2e8f9f7 1825 * @brief Enables the MMC Counter Freeze.
<> 144:ef7eb2e8f9f7 1826 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1827 * @retval None
<> 144:ef7eb2e8f9f7 1828 */
<> 144:ef7eb2e8f9f7 1829 #define __HAL_ETH_MMC_COUNTER_FREEZE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_MCF)
<> 144:ef7eb2e8f9f7 1830
<> 144:ef7eb2e8f9f7 1831 /**
<> 144:ef7eb2e8f9f7 1832 * @brief Disables the MMC Counter Freeze.
<> 144:ef7eb2e8f9f7 1833 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1834 * @retval None
<> 144:ef7eb2e8f9f7 1835 */
<> 144:ef7eb2e8f9f7 1836 #define __HAL_ETH_MMC_COUNTER_FREEZE_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_MCF)
<> 144:ef7eb2e8f9f7 1837
<> 144:ef7eb2e8f9f7 1838 /**
<> 144:ef7eb2e8f9f7 1839 * @brief Enables the MMC Reset On Read.
<> 144:ef7eb2e8f9f7 1840 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1841 * @retval None
<> 144:ef7eb2e8f9f7 1842 */
<> 144:ef7eb2e8f9f7 1843 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_ROR)
<> 144:ef7eb2e8f9f7 1844
<> 144:ef7eb2e8f9f7 1845 /**
<> 144:ef7eb2e8f9f7 1846 * @brief Disables the MMC Reset On Read.
<> 144:ef7eb2e8f9f7 1847 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1848 * @retval None
<> 144:ef7eb2e8f9f7 1849 */
<> 144:ef7eb2e8f9f7 1850 #define __HAL_ETH_ETH_MMC_RESET_ONREAD_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_ROR)
<> 144:ef7eb2e8f9f7 1851
<> 144:ef7eb2e8f9f7 1852 /**
<> 144:ef7eb2e8f9f7 1853 * @brief Enables the MMC Counter Stop Rollover.
<> 144:ef7eb2e8f9f7 1854 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1855 * @retval None
<> 144:ef7eb2e8f9f7 1856 */
<> 144:ef7eb2e8f9f7 1857 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR &= ~ETH_MMCCR_CSR)
<> 144:ef7eb2e8f9f7 1858
<> 144:ef7eb2e8f9f7 1859 /**
<> 144:ef7eb2e8f9f7 1860 * @brief Disables the MMC Counter Stop Rollover.
<> 144:ef7eb2e8f9f7 1861 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1862 * @retval None
<> 144:ef7eb2e8f9f7 1863 */
<> 144:ef7eb2e8f9f7 1864 #define __HAL_ETH_ETH_MMC_COUNTER_ROLLOVER_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CSR)
<> 144:ef7eb2e8f9f7 1865
<> 144:ef7eb2e8f9f7 1866 /**
<> 144:ef7eb2e8f9f7 1867 * @brief Resets the MMC Counters.
<> 144:ef7eb2e8f9f7 1868 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1869 * @retval None
<> 144:ef7eb2e8f9f7 1870 */
<> 144:ef7eb2e8f9f7 1871 #define __HAL_ETH_MMC_COUNTERS_RESET(__HANDLE__) ((__HANDLE__)->Instance->MMCCR |= ETH_MMCCR_CR)
<> 144:ef7eb2e8f9f7 1872
<> 144:ef7eb2e8f9f7 1873 /**
<> 144:ef7eb2e8f9f7 1874 * @brief Enables the specified ETHERNET MMC Rx interrupts.
<> 144:ef7eb2e8f9f7 1875 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1876 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
<> 144:ef7eb2e8f9f7 1877 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1878 * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
<> 144:ef7eb2e8f9f7 1879 * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
<> 144:ef7eb2e8f9f7 1880 * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
<> 144:ef7eb2e8f9f7 1881 * @retval None
<> 144:ef7eb2e8f9f7 1882 */
<> 144:ef7eb2e8f9f7 1883 #define __HAL_ETH_MMC_RX_IT_ENABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR &= ~((__INTERRUPT__) & 0xEFFFFFFF)
<> 144:ef7eb2e8f9f7 1884 /**
<> 144:ef7eb2e8f9f7 1885 * @brief Disables the specified ETHERNET MMC Rx interrupts.
<> 144:ef7eb2e8f9f7 1886 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1887 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
<> 144:ef7eb2e8f9f7 1888 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1889 * @arg ETH_MMC_IT_RGUF : When Rx good unicast frames counter reaches half the maximum value
<> 144:ef7eb2e8f9f7 1890 * @arg ETH_MMC_IT_RFAE : When Rx alignment error counter reaches half the maximum value
<> 144:ef7eb2e8f9f7 1891 * @arg ETH_MMC_IT_RFCE : When Rx crc error counter reaches half the maximum value
<> 144:ef7eb2e8f9f7 1892 * @retval None
<> 144:ef7eb2e8f9f7 1893 */
<> 144:ef7eb2e8f9f7 1894 #define __HAL_ETH_MMC_RX_IT_DISABLE(__HANDLE__, __INTERRUPT__) (__HANDLE__)->Instance->MMCRIMR |= ((__INTERRUPT__) & 0xEFFFFFFF)
<> 144:ef7eb2e8f9f7 1895 /**
<> 144:ef7eb2e8f9f7 1896 * @brief Enables the specified ETHERNET MMC Tx interrupts.
<> 144:ef7eb2e8f9f7 1897 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1898 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
<> 144:ef7eb2e8f9f7 1899 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1900 * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
<> 144:ef7eb2e8f9f7 1901 * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
<> 144:ef7eb2e8f9f7 1902 * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
<> 144:ef7eb2e8f9f7 1903 * @retval None
<> 144:ef7eb2e8f9f7 1904 */
<> 144:ef7eb2e8f9f7 1905 #define __HAL_ETH_MMC_TX_IT_ENABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR &= ~ (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 1906
<> 144:ef7eb2e8f9f7 1907 /**
<> 144:ef7eb2e8f9f7 1908 * @brief Disables the specified ETHERNET MMC Tx interrupts.
<> 144:ef7eb2e8f9f7 1909 * @param __HANDLE__: ETH Handle.
<> 144:ef7eb2e8f9f7 1910 * @param __INTERRUPT__: specifies the ETHERNET MMC interrupt sources to be enabled or disabled.
<> 144:ef7eb2e8f9f7 1911 * This parameter can be one of the following values:
<> 144:ef7eb2e8f9f7 1912 * @arg ETH_MMC_IT_TGF : When Tx good frame counter reaches half the maximum value
<> 144:ef7eb2e8f9f7 1913 * @arg ETH_MMC_IT_TGFMSC: When Tx good multi col counter reaches half the maximum value
<> 144:ef7eb2e8f9f7 1914 * @arg ETH_MMC_IT_TGFSC : When Tx good single col counter reaches half the maximum value
<> 144:ef7eb2e8f9f7 1915 * @retval None
<> 144:ef7eb2e8f9f7 1916 */
<> 144:ef7eb2e8f9f7 1917 #define __HAL_ETH_MMC_TX_IT_DISABLE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MMCRIMR |= (__INTERRUPT__))
<> 144:ef7eb2e8f9f7 1918
<> 144:ef7eb2e8f9f7 1919 /**
<> 144:ef7eb2e8f9f7 1920 * @brief Enables the ETH External interrupt line.
<> 144:ef7eb2e8f9f7 1921 * @retval None
<> 144:ef7eb2e8f9f7 1922 */
<> 144:ef7eb2e8f9f7 1923 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT() EXTI->IMR |= (ETH_EXTI_LINE_WAKEUP)
<> 144:ef7eb2e8f9f7 1924
<> 144:ef7eb2e8f9f7 1925 /**
<> 144:ef7eb2e8f9f7 1926 * @brief Disables the ETH External interrupt line.
<> 144:ef7eb2e8f9f7 1927 * @retval None
<> 144:ef7eb2e8f9f7 1928 */
<> 144:ef7eb2e8f9f7 1929 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_IT() EXTI->IMR &= ~(ETH_EXTI_LINE_WAKEUP)
<> 144:ef7eb2e8f9f7 1930
<> 144:ef7eb2e8f9f7 1931 /**
<> 144:ef7eb2e8f9f7 1932 * @brief Enable event on ETH External event line.
<> 144:ef7eb2e8f9f7 1933 * @retval None.
<> 144:ef7eb2e8f9f7 1934 */
<> 144:ef7eb2e8f9f7 1935 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_EVENT() EXTI->EMR |= (ETH_EXTI_LINE_WAKEUP)
<> 144:ef7eb2e8f9f7 1936
<> 144:ef7eb2e8f9f7 1937 /**
<> 144:ef7eb2e8f9f7 1938 * @brief Disable event on ETH External event line
<> 144:ef7eb2e8f9f7 1939 * @retval None.
<> 144:ef7eb2e8f9f7 1940 */
<> 144:ef7eb2e8f9f7 1941 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_EVENT() EXTI->EMR &= ~(ETH_EXTI_LINE_WAKEUP)
<> 144:ef7eb2e8f9f7 1942
<> 144:ef7eb2e8f9f7 1943 /**
<> 144:ef7eb2e8f9f7 1944 * @brief Get flag of the ETH External interrupt line.
<> 144:ef7eb2e8f9f7 1945 * @retval None
<> 144:ef7eb2e8f9f7 1946 */
<> 144:ef7eb2e8f9f7 1947 #define __HAL_ETH_WAKEUP_EXTI_GET_FLAG() EXTI->PR & (ETH_EXTI_LINE_WAKEUP)
<> 144:ef7eb2e8f9f7 1948
<> 144:ef7eb2e8f9f7 1949 /**
<> 144:ef7eb2e8f9f7 1950 * @brief Clear flag of the ETH External interrupt line.
<> 144:ef7eb2e8f9f7 1951 * @retval None
<> 144:ef7eb2e8f9f7 1952 */
<> 144:ef7eb2e8f9f7 1953 #define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG() EXTI->PR = (ETH_EXTI_LINE_WAKEUP)
<> 144:ef7eb2e8f9f7 1954
<> 144:ef7eb2e8f9f7 1955 /**
<> 144:ef7eb2e8f9f7 1956 * @brief Enables rising edge trigger to the ETH External interrupt line.
<> 144:ef7eb2e8f9f7 1957 * @retval None
<> 144:ef7eb2e8f9f7 1958 */
<> 144:ef7eb2e8f9f7 1959 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE_TRIGGER() EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP
<> 144:ef7eb2e8f9f7 1960
<> 144:ef7eb2e8f9f7 1961 /**
<> 144:ef7eb2e8f9f7 1962 * @brief Disables the rising edge trigger to the ETH External interrupt line.
<> 144:ef7eb2e8f9f7 1963 * @retval None
<> 144:ef7eb2e8f9f7 1964 */
<> 144:ef7eb2e8f9f7 1965 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_RISING_EDGE_TRIGGER() EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP)
<> 144:ef7eb2e8f9f7 1966
<> 144:ef7eb2e8f9f7 1967 /**
<> 144:ef7eb2e8f9f7 1968 * @brief Enables falling edge trigger to the ETH External interrupt line.
<> 144:ef7eb2e8f9f7 1969 * @retval None
<> 144:ef7eb2e8f9f7 1970 */
<> 144:ef7eb2e8f9f7 1971 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR |= (ETH_EXTI_LINE_WAKEUP)
<> 144:ef7eb2e8f9f7 1972
<> 144:ef7eb2e8f9f7 1973 /**
<> 144:ef7eb2e8f9f7 1974 * @brief Disables falling edge trigger to the ETH External interrupt line.
<> 144:ef7eb2e8f9f7 1975 * @retval None
<> 144:ef7eb2e8f9f7 1976 */
<> 144:ef7eb2e8f9f7 1977 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLING_EDGE_TRIGGER() EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP)
<> 144:ef7eb2e8f9f7 1978
<> 144:ef7eb2e8f9f7 1979
<> 144:ef7eb2e8f9f7 1980 /**
<> 144:ef7eb2e8f9f7 1981 * @brief Enables rising/falling edge trigger to the ETH External interrupt line.
<> 144:ef7eb2e8f9f7 1982 * @retval None
<> 144:ef7eb2e8f9f7 1983 */
<> 144:ef7eb2e8f9f7 1984 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLINGRISING_TRIGGER() \
<> 144:ef7eb2e8f9f7 1985 do{ \
<> 144:ef7eb2e8f9f7 1986 EXTI->RTSR |= ETH_EXTI_LINE_WAKEUP;\
<> 144:ef7eb2e8f9f7 1987 EXTI->FTSR |= ETH_EXTI_LINE_WAKEUP;\
<> 144:ef7eb2e8f9f7 1988 } while(0)
<> 144:ef7eb2e8f9f7 1989
<> 144:ef7eb2e8f9f7 1990 /**
<> 144:ef7eb2e8f9f7 1991 * @brief Disables rising/falling edge trigger to the ETH External interrupt line.
<> 144:ef7eb2e8f9f7 1992 * @retval None
<> 144:ef7eb2e8f9f7 1993 */
<> 144:ef7eb2e8f9f7 1994 #define __HAL_ETH_WAKEUP_EXTI_DISABLE_FALLINGRISING_TRIGGER() \
<> 144:ef7eb2e8f9f7 1995 do{ \
<> 144:ef7eb2e8f9f7 1996 EXTI->RTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
<> 144:ef7eb2e8f9f7 1997 EXTI->FTSR &= ~(ETH_EXTI_LINE_WAKEUP);\
<> 144:ef7eb2e8f9f7 1998 } while(0)
<> 144:ef7eb2e8f9f7 1999
<> 144:ef7eb2e8f9f7 2000 /**
<> 144:ef7eb2e8f9f7 2001 * @brief Generate a Software interrupt on selected EXTI line.
<> 144:ef7eb2e8f9f7 2002 * @retval None.
<> 144:ef7eb2e8f9f7 2003 */
<> 144:ef7eb2e8f9f7 2004 #define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT() EXTI->SWIER|= ETH_EXTI_LINE_WAKEUP
<> 144:ef7eb2e8f9f7 2005
<> 144:ef7eb2e8f9f7 2006 /**
<> 144:ef7eb2e8f9f7 2007 * @}
<> 144:ef7eb2e8f9f7 2008 */
<> 144:ef7eb2e8f9f7 2009
<> 144:ef7eb2e8f9f7 2010 /* Exported functions --------------------------------------------------------*/
<> 144:ef7eb2e8f9f7 2011
<> 144:ef7eb2e8f9f7 2012 /** @addtogroup ETH_Exported_Functions
<> 144:ef7eb2e8f9f7 2013 * @{
<> 144:ef7eb2e8f9f7 2014 */
<> 144:ef7eb2e8f9f7 2015
<> 144:ef7eb2e8f9f7 2016 /* Initialization and de-initialization functions ****************************/
<> 144:ef7eb2e8f9f7 2017
<> 144:ef7eb2e8f9f7 2018 /** @addtogroup ETH_Exported_Functions_Group1
<> 144:ef7eb2e8f9f7 2019 * @{
<> 144:ef7eb2e8f9f7 2020 */
<> 144:ef7eb2e8f9f7 2021
<> 144:ef7eb2e8f9f7 2022 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
<> 144:ef7eb2e8f9f7 2023 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
<> 144:ef7eb2e8f9f7 2024 void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
<> 144:ef7eb2e8f9f7 2025 void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
<> 144:ef7eb2e8f9f7 2026 HAL_StatusTypeDef HAL_ETH_DMATxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMATxDescTab, uint8_t* TxBuff, uint32_t TxBuffCount);
<> 144:ef7eb2e8f9f7 2027 HAL_StatusTypeDef HAL_ETH_DMARxDescListInit(ETH_HandleTypeDef *heth, ETH_DMADescTypeDef *DMARxDescTab, uint8_t *RxBuff, uint32_t RxBuffCount);
<> 144:ef7eb2e8f9f7 2028
<> 144:ef7eb2e8f9f7 2029 /**
<> 144:ef7eb2e8f9f7 2030 * @}
<> 144:ef7eb2e8f9f7 2031 */
<> 144:ef7eb2e8f9f7 2032
<> 144:ef7eb2e8f9f7 2033 /* IO operation functions ****************************************************/
<> 144:ef7eb2e8f9f7 2034
<> 144:ef7eb2e8f9f7 2035 /** @addtogroup ETH_Exported_Functions_Group2
<> 144:ef7eb2e8f9f7 2036 * @{
<> 144:ef7eb2e8f9f7 2037 */
<> 144:ef7eb2e8f9f7 2038 HAL_StatusTypeDef HAL_ETH_TransmitFrame(ETH_HandleTypeDef *heth, uint32_t FrameLength);
<> 144:ef7eb2e8f9f7 2039 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame(ETH_HandleTypeDef *heth);
<> 144:ef7eb2e8f9f7 2040 /* Communication with PHY functions*/
<> 144:ef7eb2e8f9f7 2041 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t *RegValue);
<> 144:ef7eb2e8f9f7 2042 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint16_t PHYReg, uint32_t RegValue);
<> 144:ef7eb2e8f9f7 2043 /* Non-Blocking mode: Interrupt */
<> 144:ef7eb2e8f9f7 2044 HAL_StatusTypeDef HAL_ETH_GetReceivedFrame_IT(ETH_HandleTypeDef *heth);
<> 144:ef7eb2e8f9f7 2045 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
<> 144:ef7eb2e8f9f7 2046 /* Callback in non blocking modes (Interrupt) */
<> 144:ef7eb2e8f9f7 2047 void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
<> 144:ef7eb2e8f9f7 2048 void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
<> 144:ef7eb2e8f9f7 2049 void HAL_ETH_ErrorCallback(ETH_HandleTypeDef *heth);
<> 144:ef7eb2e8f9f7 2050
<> 144:ef7eb2e8f9f7 2051 /**
<> 144:ef7eb2e8f9f7 2052 * @}
<> 144:ef7eb2e8f9f7 2053 */
<> 144:ef7eb2e8f9f7 2054
<> 144:ef7eb2e8f9f7 2055 /* Peripheral Control functions **********************************************/
<> 144:ef7eb2e8f9f7 2056
<> 144:ef7eb2e8f9f7 2057 /** @addtogroup ETH_Exported_Functions_Group3
<> 144:ef7eb2e8f9f7 2058 * @{
<> 144:ef7eb2e8f9f7 2059 */
<> 144:ef7eb2e8f9f7 2060 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
<> 144:ef7eb2e8f9f7 2061 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
<> 144:ef7eb2e8f9f7 2062 HAL_StatusTypeDef HAL_ETH_ConfigMAC(ETH_HandleTypeDef *heth, ETH_MACInitTypeDef *macconf);
<> 144:ef7eb2e8f9f7 2063 HAL_StatusTypeDef HAL_ETH_ConfigDMA(ETH_HandleTypeDef *heth, ETH_DMAInitTypeDef *dmaconf);
<> 144:ef7eb2e8f9f7 2064 /**
<> 144:ef7eb2e8f9f7 2065 * @}
<> 144:ef7eb2e8f9f7 2066 */
<> 144:ef7eb2e8f9f7 2067
<> 144:ef7eb2e8f9f7 2068 /* Peripheral State functions ************************************************/
<> 144:ef7eb2e8f9f7 2069
<> 144:ef7eb2e8f9f7 2070 /** @addtogroup ETH_Exported_Functions_Group4
<> 144:ef7eb2e8f9f7 2071 * @{
<> 144:ef7eb2e8f9f7 2072 */
<> 144:ef7eb2e8f9f7 2073 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
<> 144:ef7eb2e8f9f7 2074
<> 144:ef7eb2e8f9f7 2075 /**
<> 144:ef7eb2e8f9f7 2076 * @}
<> 144:ef7eb2e8f9f7 2077 */
<> 144:ef7eb2e8f9f7 2078
<> 144:ef7eb2e8f9f7 2079 /**
<> 144:ef7eb2e8f9f7 2080 * @}
<> 144:ef7eb2e8f9f7 2081 */
<> 144:ef7eb2e8f9f7 2082
<> 144:ef7eb2e8f9f7 2083 /**
<> 144:ef7eb2e8f9f7 2084 * @}
<> 144:ef7eb2e8f9f7 2085 */
<> 144:ef7eb2e8f9f7 2086
<> 144:ef7eb2e8f9f7 2087 #endif /* STM32F107xC */
<> 144:ef7eb2e8f9f7 2088 /**
<> 144:ef7eb2e8f9f7 2089 * @}
<> 144:ef7eb2e8f9f7 2090 */
<> 144:ef7eb2e8f9f7 2091
<> 144:ef7eb2e8f9f7 2092 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 2093 }
<> 144:ef7eb2e8f9f7 2094 #endif
<> 144:ef7eb2e8f9f7 2095
<> 144:ef7eb2e8f9f7 2096 #endif /* __STM32F1xx_HAL_ETH_H */
<> 144:ef7eb2e8f9f7 2097
<> 144:ef7eb2e8f9f7 2098
<> 144:ef7eb2e8f9f7 2099
<> 144:ef7eb2e8f9f7 2100 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/