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Dependents:   STM32_F103-C8T6basecanblink_led

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targets/TARGET_Freescale/TARGET_MCUXpresso_MCUS/TARGET_MCU_K64F/drivers/fsl_gpio.h@154:37f96f9d4de2, 2017-01-04 (annotated)

Committer:
<>
Date:
Wed Jan 04 16:58:05 2017 +0000
Revision:
154:37f96f9d4de2
This updates the lib to the mbed lib v133

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 154:37f96f9d4de2 1 /*
<> 154:37f96f9d4de2 2 * Copyright (c) 2015, Freescale Semiconductor, Inc.
<> 154:37f96f9d4de2 3 * All rights reserved.
<> 154:37f96f9d4de2 4 *
<> 154:37f96f9d4de2 5 * Redistribution and use in source and binary forms, with or without modification,
<> 154:37f96f9d4de2 6 * are permitted provided that the following conditions are met:
<> 154:37f96f9d4de2 7 *
<> 154:37f96f9d4de2 8 * o Redistributions of source code must retain the above copyright notice, this list
<> 154:37f96f9d4de2 9 * of conditions and the following disclaimer.
<> 154:37f96f9d4de2 10 *
<> 154:37f96f9d4de2 11 * o Redistributions in binary form must reproduce the above copyright notice, this
<> 154:37f96f9d4de2 12 * list of conditions and the following disclaimer in the documentation and/or
<> 154:37f96f9d4de2 13 * other materials provided with the distribution.
<> 154:37f96f9d4de2 14 *
<> 154:37f96f9d4de2 15 * o Neither the name of Freescale Semiconductor, Inc. nor the names of its
<> 154:37f96f9d4de2 16 * contributors may be used to endorse or promote products derived from this
<> 154:37f96f9d4de2 17 * software without specific prior written permission.
<> 154:37f96f9d4de2 18 *
<> 154:37f96f9d4de2 19 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
<> 154:37f96f9d4de2 20 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED
<> 154:37f96f9d4de2 21 * WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
<> 154:37f96f9d4de2 22 * DISCLAIMED. IN NO EVENT SDRVL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR
<> 154:37f96f9d4de2 23 * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
<> 154:37f96f9d4de2 24 * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES;
<> 154:37f96f9d4de2 25 * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
<> 154:37f96f9d4de2 26 * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
<> 154:37f96f9d4de2 27 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS
<> 154:37f96f9d4de2 28 * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
<> 154:37f96f9d4de2 29 */
<> 154:37f96f9d4de2 30
<> 154:37f96f9d4de2 31 #ifndef _FSL_GPIO_H_
<> 154:37f96f9d4de2 32 #define _FSL_GPIO_H_
<> 154:37f96f9d4de2 33
<> 154:37f96f9d4de2 34 #include "fsl_common.h"
<> 154:37f96f9d4de2 35
<> 154:37f96f9d4de2 36 /*!
<> 154:37f96f9d4de2 37 * @addtogroup gpio
<> 154:37f96f9d4de2 38 * @{
<> 154:37f96f9d4de2 39 */
<> 154:37f96f9d4de2 40
<> 154:37f96f9d4de2 41 /*******************************************************************************
<> 154:37f96f9d4de2 42 * Definitions
<> 154:37f96f9d4de2 43 ******************************************************************************/
<> 154:37f96f9d4de2 44
<> 154:37f96f9d4de2 45 /*! @name Driver version */
<> 154:37f96f9d4de2 46 /*@{*/
<> 154:37f96f9d4de2 47 /*! @brief GPIO driver version 2.1.1. */
<> 154:37f96f9d4de2 48 #define FSL_GPIO_DRIVER_VERSION (MAKE_VERSION(2, 1, 1))
<> 154:37f96f9d4de2 49 /*@}*/
<> 154:37f96f9d4de2 50
<> 154:37f96f9d4de2 51 /*! @brief GPIO direction definition */
<> 154:37f96f9d4de2 52 typedef enum _gpio_pin_direction
<> 154:37f96f9d4de2 53 {
<> 154:37f96f9d4de2 54 kGPIO_DigitalInput = 0U, /*!< Set current pin as digital input*/
<> 154:37f96f9d4de2 55 kGPIO_DigitalOutput = 1U, /*!< Set current pin as digital output*/
<> 154:37f96f9d4de2 56 } gpio_pin_direction_t;
<> 154:37f96f9d4de2 57
<> 154:37f96f9d4de2 58 #if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER
<> 154:37f96f9d4de2 59 /*! @brief GPIO checker attribute */
<> 154:37f96f9d4de2 60 typedef enum _gpio_checker_attribute
<> 154:37f96f9d4de2 61 {
<> 154:37f96f9d4de2 62 kGPIO_UsernonsecureRWUsersecureRWPrivilegedsecureRW =
<> 154:37f96f9d4de2 63 0x00U, /*!< User nonsecure:Read+Write; User Secure:Read+Write; Privileged Secure:Read+Write */
<> 154:37f96f9d4de2 64 kGPIO_UsernonsecureRUsersecureRWPrivilegedsecureRW =
<> 154:37f96f9d4de2 65 0x01U, /*!< User nonsecure:Read; User Secure:Read+Write; Privileged Secure:Read+Write */
<> 154:37f96f9d4de2 66 kGPIO_UsernonsecureNUsersecureRWPrivilegedsecureRW =
<> 154:37f96f9d4de2 67 0x02U, /*!< User nonsecure:None; User Secure:Read+Write; Privileged Secure:Read+Write */
<> 154:37f96f9d4de2 68 kGPIO_UsernonsecureRUsersecureRPrivilegedsecureRW =
<> 154:37f96f9d4de2 69 0x03U, /*!< User nonsecure:Read; User Secure:Read; Privileged Secure:Read+Write */
<> 154:37f96f9d4de2 70 kGPIO_UsernonsecureNUsersecureRPrivilegedsecureRW =
<> 154:37f96f9d4de2 71 0x04U, /*!< User nonsecure:None; User Secure:Read; Privileged Secure:Read+Write */
<> 154:37f96f9d4de2 72 kGPIO_UsernonsecureNUsersecureNPrivilegedsecureRW =
<> 154:37f96f9d4de2 73 0x05U, /*!< User nonsecure:None; User Secure:None; Privileged Secure:Read+Write */
<> 154:37f96f9d4de2 74 kGPIO_UsernonsecureNUsersecureNPrivilegedsecureR =
<> 154:37f96f9d4de2 75 0x06U, /*!< User nonsecure:None; User Secure:None; Privileged Secure:Read */
<> 154:37f96f9d4de2 76 kGPIO_UsernonsecureNUsersecureNPrivilegedsecureN =
<> 154:37f96f9d4de2 77 0x07U, /*!< User nonsecure:None; User Secure:None; Privileged Secure:None */
<> 154:37f96f9d4de2 78 kGPIO_IgnoreAttributeCheck = 0x10U, /*!< Ignores the attribute check */
<> 154:37f96f9d4de2 79 } gpio_checker_attribute_t;
<> 154:37f96f9d4de2 80 #endif
<> 154:37f96f9d4de2 81
<> 154:37f96f9d4de2 82 /*!
<> 154:37f96f9d4de2 83 * @brief The GPIO pin configuration structure.
<> 154:37f96f9d4de2 84 *
<> 154:37f96f9d4de2 85 * Each pin can only be configured as either an output pin or an input pin at a time.
<> 154:37f96f9d4de2 86 * If configured as an input pin, leave the outputConfig unused.
<> 154:37f96f9d4de2 87 * Note that in some use cases, the corresponding port property should be configured in advance
<> 154:37f96f9d4de2 88 * with the PORT_SetPinConfig().
<> 154:37f96f9d4de2 89 */
<> 154:37f96f9d4de2 90 typedef struct _gpio_pin_config
<> 154:37f96f9d4de2 91 {
<> 154:37f96f9d4de2 92 gpio_pin_direction_t pinDirection; /*!< GPIO direction, input or output */
<> 154:37f96f9d4de2 93 /* Output configurations; ignore if configured as an input pin */
<> 154:37f96f9d4de2 94 uint8_t outputLogic; /*!< Set a default output logic, which has no use in input */
<> 154:37f96f9d4de2 95 } gpio_pin_config_t;
<> 154:37f96f9d4de2 96
<> 154:37f96f9d4de2 97 /*! @} */
<> 154:37f96f9d4de2 98
<> 154:37f96f9d4de2 99 /*******************************************************************************
<> 154:37f96f9d4de2 100 * API
<> 154:37f96f9d4de2 101 ******************************************************************************/
<> 154:37f96f9d4de2 102
<> 154:37f96f9d4de2 103 #if defined(__cplusplus)
<> 154:37f96f9d4de2 104 extern "C" {
<> 154:37f96f9d4de2 105 #endif
<> 154:37f96f9d4de2 106
<> 154:37f96f9d4de2 107 /*!
<> 154:37f96f9d4de2 108 * @addtogroup gpio_driver
<> 154:37f96f9d4de2 109 * @{
<> 154:37f96f9d4de2 110 */
<> 154:37f96f9d4de2 111
<> 154:37f96f9d4de2 112 /*! @name GPIO Configuration */
<> 154:37f96f9d4de2 113 /*@{*/
<> 154:37f96f9d4de2 114
<> 154:37f96f9d4de2 115 /*!
<> 154:37f96f9d4de2 116 * @brief Initializes a GPIO pin used by the board.
<> 154:37f96f9d4de2 117 *
<> 154:37f96f9d4de2 118 * To initialize the GPIO, define a pin configuration, as either input or output, in the user file.
<> 154:37f96f9d4de2 119 * Then, call the GPIO_PinInit() function.
<> 154:37f96f9d4de2 120 *
<> 154:37f96f9d4de2 121 * This is an example to define an input pin or an output pin configuration.
<> 154:37f96f9d4de2 122 * @code
<> 154:37f96f9d4de2 123 * // Define a digital input pin configuration,
<> 154:37f96f9d4de2 124 * gpio_pin_config_t config =
<> 154:37f96f9d4de2 125 * {
<> 154:37f96f9d4de2 126 * kGPIO_DigitalInput,
<> 154:37f96f9d4de2 127 * 0,
<> 154:37f96f9d4de2 128 * }
<> 154:37f96f9d4de2 129 * //Define a digital output pin configuration,
<> 154:37f96f9d4de2 130 * gpio_pin_config_t config =
<> 154:37f96f9d4de2 131 * {
<> 154:37f96f9d4de2 132 * kGPIO_DigitalOutput,
<> 154:37f96f9d4de2 133 * 0,
<> 154:37f96f9d4de2 134 * }
<> 154:37f96f9d4de2 135 * @endcode
<> 154:37f96f9d4de2 136 *
<> 154:37f96f9d4de2 137 * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
<> 154:37f96f9d4de2 138 * @param pin GPIO port pin number
<> 154:37f96f9d4de2 139 * @param config GPIO pin configuration pointer
<> 154:37f96f9d4de2 140 */
<> 154:37f96f9d4de2 141 void GPIO_PinInit(GPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config);
<> 154:37f96f9d4de2 142
<> 154:37f96f9d4de2 143 /*@}*/
<> 154:37f96f9d4de2 144
<> 154:37f96f9d4de2 145 /*! @name GPIO Output Operations */
<> 154:37f96f9d4de2 146 /*@{*/
<> 154:37f96f9d4de2 147
<> 154:37f96f9d4de2 148 /*!
<> 154:37f96f9d4de2 149 * @brief Sets the output level of the multiple GPIO pins to the logic 1 or 0.
<> 154:37f96f9d4de2 150 *
<> 154:37f96f9d4de2 151 * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
<> 154:37f96f9d4de2 152 * @param pin GPIO pin number
<> 154:37f96f9d4de2 153 * @param output GPIO pin output logic level.
<> 154:37f96f9d4de2 154 * - 0: corresponding pin output low-logic level.
<> 154:37f96f9d4de2 155 * - 1: corresponding pin output high-logic level.
<> 154:37f96f9d4de2 156 */
<> 154:37f96f9d4de2 157 static inline void GPIO_WritePinOutput(GPIO_Type *base, uint32_t pin, uint8_t output)
<> 154:37f96f9d4de2 158 {
<> 154:37f96f9d4de2 159 if (output == 0U)
<> 154:37f96f9d4de2 160 {
<> 154:37f96f9d4de2 161 base->PCOR = 1U << pin;
<> 154:37f96f9d4de2 162 }
<> 154:37f96f9d4de2 163 else
<> 154:37f96f9d4de2 164 {
<> 154:37f96f9d4de2 165 base->PSOR = 1U << pin;
<> 154:37f96f9d4de2 166 }
<> 154:37f96f9d4de2 167 }
<> 154:37f96f9d4de2 168
<> 154:37f96f9d4de2 169 /*!
<> 154:37f96f9d4de2 170 * @brief Sets the output level of the multiple GPIO pins to the logic 1.
<> 154:37f96f9d4de2 171 *
<> 154:37f96f9d4de2 172 * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
<> 154:37f96f9d4de2 173 * @param mask GPIO pin number macro
<> 154:37f96f9d4de2 174 */
<> 154:37f96f9d4de2 175 static inline void GPIO_SetPinsOutput(GPIO_Type *base, uint32_t mask)
<> 154:37f96f9d4de2 176 {
<> 154:37f96f9d4de2 177 base->PSOR = mask;
<> 154:37f96f9d4de2 178 }
<> 154:37f96f9d4de2 179
<> 154:37f96f9d4de2 180 /*!
<> 154:37f96f9d4de2 181 * @brief Sets the output level of the multiple GPIO pins to the logic 0.
<> 154:37f96f9d4de2 182 *
<> 154:37f96f9d4de2 183 * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
<> 154:37f96f9d4de2 184 * @param mask GPIO pin number macro
<> 154:37f96f9d4de2 185 */
<> 154:37f96f9d4de2 186 static inline void GPIO_ClearPinsOutput(GPIO_Type *base, uint32_t mask)
<> 154:37f96f9d4de2 187 {
<> 154:37f96f9d4de2 188 base->PCOR = mask;
<> 154:37f96f9d4de2 189 }
<> 154:37f96f9d4de2 190
<> 154:37f96f9d4de2 191 /*!
<> 154:37f96f9d4de2 192 * @brief Reverses the current output logic of the multiple GPIO pins.
<> 154:37f96f9d4de2 193 *
<> 154:37f96f9d4de2 194 * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
<> 154:37f96f9d4de2 195 * @param mask GPIO pin number macro
<> 154:37f96f9d4de2 196 */
<> 154:37f96f9d4de2 197 static inline void GPIO_TogglePinsOutput(GPIO_Type *base, uint32_t mask)
<> 154:37f96f9d4de2 198 {
<> 154:37f96f9d4de2 199 base->PTOR = mask;
<> 154:37f96f9d4de2 200 }
<> 154:37f96f9d4de2 201 /*@}*/
<> 154:37f96f9d4de2 202
<> 154:37f96f9d4de2 203 /*! @name GPIO Input Operations */
<> 154:37f96f9d4de2 204 /*@{*/
<> 154:37f96f9d4de2 205
<> 154:37f96f9d4de2 206 /*!
<> 154:37f96f9d4de2 207 * @brief Reads the current input value of the GPIO port.
<> 154:37f96f9d4de2 208 *
<> 154:37f96f9d4de2 209 * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
<> 154:37f96f9d4de2 210 * @param pin GPIO pin number
<> 154:37f96f9d4de2 211 * @retval GPIO port input value
<> 154:37f96f9d4de2 212 * - 0: corresponding pin input low-logic level.
<> 154:37f96f9d4de2 213 * - 1: corresponding pin input high-logic level.
<> 154:37f96f9d4de2 214 */
<> 154:37f96f9d4de2 215 static inline uint32_t GPIO_ReadPinInput(GPIO_Type *base, uint32_t pin)
<> 154:37f96f9d4de2 216 {
<> 154:37f96f9d4de2 217 return (((base->PDIR) >> pin) & 0x01U);
<> 154:37f96f9d4de2 218 }
<> 154:37f96f9d4de2 219 /*@}*/
<> 154:37f96f9d4de2 220
<> 154:37f96f9d4de2 221 /*! @name GPIO Interrupt */
<> 154:37f96f9d4de2 222 /*@{*/
<> 154:37f96f9d4de2 223
<> 154:37f96f9d4de2 224 /*!
<> 154:37f96f9d4de2 225 * @brief Reads the GPIO port interrupt status flag.
<> 154:37f96f9d4de2 226 *
<> 154:37f96f9d4de2 227 * If a pin is configured to generate the DMA request, the corresponding flag
<> 154:37f96f9d4de2 228 * is cleared automatically at the completion of the requested DMA transfer.
<> 154:37f96f9d4de2 229 * Otherwise, the flag remains set until a logic one is written to that flag.
<> 154:37f96f9d4de2 230 * If configured for a level sensitive interrupt that remains asserted, the flag
<> 154:37f96f9d4de2 231 * is set again immediately.
<> 154:37f96f9d4de2 232 *
<> 154:37f96f9d4de2 233 * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
<> 154:37f96f9d4de2 234 * @retval The current GPIO port interrupt status flag, for example, 0x00010001 means the
<> 154:37f96f9d4de2 235 * pin 0 and 17 have the interrupt.
<> 154:37f96f9d4de2 236 */
<> 154:37f96f9d4de2 237 uint32_t GPIO_GetPinsInterruptFlags(GPIO_Type *base);
<> 154:37f96f9d4de2 238
<> 154:37f96f9d4de2 239 /*!
<> 154:37f96f9d4de2 240 * @brief Clears multiple GPIO pin interrupt status flags.
<> 154:37f96f9d4de2 241 *
<> 154:37f96f9d4de2 242 * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
<> 154:37f96f9d4de2 243 * @param mask GPIO pin number macro
<> 154:37f96f9d4de2 244 */
<> 154:37f96f9d4de2 245 void GPIO_ClearPinsInterruptFlags(GPIO_Type *base, uint32_t mask);
<> 154:37f96f9d4de2 246
<> 154:37f96f9d4de2 247 #if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER
<> 154:37f96f9d4de2 248 /*!
<> 154:37f96f9d4de2 249 * @brief The GPIO module supports a device-specific number of data ports, organized as 32-bit
<> 154:37f96f9d4de2 250 * words. Each 32-bit data port includes a GACR register, which defines the byte-level
<> 154:37f96f9d4de2 251 * attributes required for a successful access to the GPIO programming model. The attribute controls for the 4 data
<> 154:37f96f9d4de2 252 * bytes in the GACR follow a standard little endian
<> 154:37f96f9d4de2 253 * data convention.
<> 154:37f96f9d4de2 254 *
<> 154:37f96f9d4de2 255 * @param base GPIO peripheral base pointer (GPIOA, GPIOB, GPIOC, and so on.)
<> 154:37f96f9d4de2 256 * @param mask GPIO pin number macro
<> 154:37f96f9d4de2 257 */
<> 154:37f96f9d4de2 258 void GPIO_CheckAttributeBytes(GPIO_Type *base, gpio_checker_attribute_t attribute);
<> 154:37f96f9d4de2 259 #endif
<> 154:37f96f9d4de2 260
<> 154:37f96f9d4de2 261 /*@}*/
<> 154:37f96f9d4de2 262 /*! @} */
<> 154:37f96f9d4de2 263
<> 154:37f96f9d4de2 264 /*!
<> 154:37f96f9d4de2 265 * @addtogroup fgpio_driver
<> 154:37f96f9d4de2 266 * @{
<> 154:37f96f9d4de2 267 */
<> 154:37f96f9d4de2 268
<> 154:37f96f9d4de2 269 /*
<> 154:37f96f9d4de2 270 * Introduces the FGPIO feature.
<> 154:37f96f9d4de2 271 *
<> 154:37f96f9d4de2 272 * The FGPIO features are only support on some Kinetis MCUs. The FGPIO registers are aliased to the IOPORT
<> 154:37f96f9d4de2 273 * interface. Accesses via the IOPORT interface occur in parallel with any instruction fetches and
<> 154:37f96f9d4de2 274 * complete in a single cycle. This aliased Fast GPIO memory map is called FGPIO.
<> 154:37f96f9d4de2 275 */
<> 154:37f96f9d4de2 276
<> 154:37f96f9d4de2 277 #if defined(FSL_FEATURE_SOC_FGPIO_COUNT) && FSL_FEATURE_SOC_FGPIO_COUNT
<> 154:37f96f9d4de2 278
<> 154:37f96f9d4de2 279 /*! @name FGPIO Configuration */
<> 154:37f96f9d4de2 280 /*@{*/
<> 154:37f96f9d4de2 281
<> 154:37f96f9d4de2 282 /*!
<> 154:37f96f9d4de2 283 * @brief Initializes a FGPIO pin used by the board.
<> 154:37f96f9d4de2 284 *
<> 154:37f96f9d4de2 285 * To initialize the FGPIO driver, define a pin configuration, as either input or output, in the user file.
<> 154:37f96f9d4de2 286 * Then, call the FGPIO_PinInit() function.
<> 154:37f96f9d4de2 287 *
<> 154:37f96f9d4de2 288 * This is an example to define an input pin or an output pin configuration:
<> 154:37f96f9d4de2 289 * @code
<> 154:37f96f9d4de2 290 * // Define a digital input pin configuration,
<> 154:37f96f9d4de2 291 * gpio_pin_config_t config =
<> 154:37f96f9d4de2 292 * {
<> 154:37f96f9d4de2 293 * kGPIO_DigitalInput,
<> 154:37f96f9d4de2 294 * 0,
<> 154:37f96f9d4de2 295 * }
<> 154:37f96f9d4de2 296 * //Define a digital output pin configuration,
<> 154:37f96f9d4de2 297 * gpio_pin_config_t config =
<> 154:37f96f9d4de2 298 * {
<> 154:37f96f9d4de2 299 * kGPIO_DigitalOutput,
<> 154:37f96f9d4de2 300 * 0,
<> 154:37f96f9d4de2 301 * }
<> 154:37f96f9d4de2 302 * @endcode
<> 154:37f96f9d4de2 303 *
<> 154:37f96f9d4de2 304 * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
<> 154:37f96f9d4de2 305 * @param pin FGPIO port pin number
<> 154:37f96f9d4de2 306 * @param config FGPIO pin configuration pointer
<> 154:37f96f9d4de2 307 */
<> 154:37f96f9d4de2 308 void FGPIO_PinInit(FGPIO_Type *base, uint32_t pin, const gpio_pin_config_t *config);
<> 154:37f96f9d4de2 309
<> 154:37f96f9d4de2 310 /*@}*/
<> 154:37f96f9d4de2 311
<> 154:37f96f9d4de2 312 /*! @name FGPIO Output Operations */
<> 154:37f96f9d4de2 313 /*@{*/
<> 154:37f96f9d4de2 314
<> 154:37f96f9d4de2 315 /*!
<> 154:37f96f9d4de2 316 * @brief Sets the output level of the multiple FGPIO pins to the logic 1 or 0.
<> 154:37f96f9d4de2 317 *
<> 154:37f96f9d4de2 318 * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
<> 154:37f96f9d4de2 319 * @param pin FGPIO pin number
<> 154:37f96f9d4de2 320 * @param output FGPIOpin output logic level.
<> 154:37f96f9d4de2 321 * - 0: corresponding pin output low-logic level.
<> 154:37f96f9d4de2 322 * - 1: corresponding pin output high-logic level.
<> 154:37f96f9d4de2 323 */
<> 154:37f96f9d4de2 324 static inline void FGPIO_WritePinOutput(FGPIO_Type *base, uint32_t pin, uint8_t output)
<> 154:37f96f9d4de2 325 {
<> 154:37f96f9d4de2 326 if (output == 0U)
<> 154:37f96f9d4de2 327 {
<> 154:37f96f9d4de2 328 base->PCOR = 1 << pin;
<> 154:37f96f9d4de2 329 }
<> 154:37f96f9d4de2 330 else
<> 154:37f96f9d4de2 331 {
<> 154:37f96f9d4de2 332 base->PSOR = 1 << pin;
<> 154:37f96f9d4de2 333 }
<> 154:37f96f9d4de2 334 }
<> 154:37f96f9d4de2 335
<> 154:37f96f9d4de2 336 /*!
<> 154:37f96f9d4de2 337 * @brief Sets the output level of the multiple FGPIO pins to the logic 1.
<> 154:37f96f9d4de2 338 *
<> 154:37f96f9d4de2 339 * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
<> 154:37f96f9d4de2 340 * @param mask FGPIO pin number macro
<> 154:37f96f9d4de2 341 */
<> 154:37f96f9d4de2 342 static inline void FGPIO_SetPinsOutput(FGPIO_Type *base, uint32_t mask)
<> 154:37f96f9d4de2 343 {
<> 154:37f96f9d4de2 344 base->PSOR = mask;
<> 154:37f96f9d4de2 345 }
<> 154:37f96f9d4de2 346
<> 154:37f96f9d4de2 347 /*!
<> 154:37f96f9d4de2 348 * @brief Sets the output level of the multiple FGPIO pins to the logic 0.
<> 154:37f96f9d4de2 349 *
<> 154:37f96f9d4de2 350 * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
<> 154:37f96f9d4de2 351 * @param mask FGPIO pin number macro
<> 154:37f96f9d4de2 352 */
<> 154:37f96f9d4de2 353 static inline void FGPIO_ClearPinsOutput(FGPIO_Type *base, uint32_t mask)
<> 154:37f96f9d4de2 354 {
<> 154:37f96f9d4de2 355 base->PCOR = mask;
<> 154:37f96f9d4de2 356 }
<> 154:37f96f9d4de2 357
<> 154:37f96f9d4de2 358 /*!
<> 154:37f96f9d4de2 359 * @brief Reverses the current output logic of the multiple FGPIO pins.
<> 154:37f96f9d4de2 360 *
<> 154:37f96f9d4de2 361 * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
<> 154:37f96f9d4de2 362 * @param mask FGPIO pin number macro
<> 154:37f96f9d4de2 363 */
<> 154:37f96f9d4de2 364 static inline void FGPIO_TogglePinsOutput(FGPIO_Type *base, uint32_t mask)
<> 154:37f96f9d4de2 365 {
<> 154:37f96f9d4de2 366 base->PTOR = mask;
<> 154:37f96f9d4de2 367 }
<> 154:37f96f9d4de2 368 /*@}*/
<> 154:37f96f9d4de2 369
<> 154:37f96f9d4de2 370 /*! @name FGPIO Input Operations */
<> 154:37f96f9d4de2 371 /*@{*/
<> 154:37f96f9d4de2 372
<> 154:37f96f9d4de2 373 /*!
<> 154:37f96f9d4de2 374 * @brief Reads the current input value of the FGPIO port.
<> 154:37f96f9d4de2 375 *
<> 154:37f96f9d4de2 376 * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
<> 154:37f96f9d4de2 377 * @param pin FGPIO pin number
<> 154:37f96f9d4de2 378 * @retval FGPIO port input value
<> 154:37f96f9d4de2 379 * - 0: corresponding pin input low-logic level.
<> 154:37f96f9d4de2 380 * - 1: corresponding pin input high-logic level.
<> 154:37f96f9d4de2 381 */
<> 154:37f96f9d4de2 382 static inline uint32_t FGPIO_ReadPinInput(FGPIO_Type *base, uint32_t pin)
<> 154:37f96f9d4de2 383 {
<> 154:37f96f9d4de2 384 return (((base->PDIR) >> pin) & 0x01U);
<> 154:37f96f9d4de2 385 }
<> 154:37f96f9d4de2 386 /*@}*/
<> 154:37f96f9d4de2 387
<> 154:37f96f9d4de2 388 /*! @name FGPIO Interrupt */
<> 154:37f96f9d4de2 389 /*@{*/
<> 154:37f96f9d4de2 390
<> 154:37f96f9d4de2 391 /*!
<> 154:37f96f9d4de2 392 * @brief Reads the FGPIO port interrupt status flag.
<> 154:37f96f9d4de2 393 *
<> 154:37f96f9d4de2 394 * If a pin is configured to generate the DMA request, the corresponding flag
<> 154:37f96f9d4de2 395 * is cleared automatically at the completion of the requested DMA transfer.
<> 154:37f96f9d4de2 396 * Otherwise, the flag remains set until a logic one is written to that flag.
<> 154:37f96f9d4de2 397 * If configured for a level-sensitive interrupt that remains asserted, the flag
<> 154:37f96f9d4de2 398 * is set again immediately.
<> 154:37f96f9d4de2 399 *
<> 154:37f96f9d4de2 400 * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
<> 154:37f96f9d4de2 401 * @retval The current FGPIO port interrupt status flags, for example, 0x00010001 means the
<> 154:37f96f9d4de2 402 * pin 0 and 17 have the interrupt.
<> 154:37f96f9d4de2 403 */
<> 154:37f96f9d4de2 404 uint32_t FGPIO_GetPinsInterruptFlags(FGPIO_Type *base);
<> 154:37f96f9d4de2 405
<> 154:37f96f9d4de2 406 /*!
<> 154:37f96f9d4de2 407 * @brief Clears the multiple FGPIO pin interrupt status flag.
<> 154:37f96f9d4de2 408 *
<> 154:37f96f9d4de2 409 * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
<> 154:37f96f9d4de2 410 * @param mask FGPIO pin number macro
<> 154:37f96f9d4de2 411 */
<> 154:37f96f9d4de2 412 void FGPIO_ClearPinsInterruptFlags(FGPIO_Type *base, uint32_t mask);
<> 154:37f96f9d4de2 413
<> 154:37f96f9d4de2 414 #if defined(FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER) && FSL_FEATURE_GPIO_HAS_ATTRIBUTE_CHECKER
<> 154:37f96f9d4de2 415 /*!
<> 154:37f96f9d4de2 416 * @brief The FGPIO module supports a device-specific number of data ports, organized as 32-bit
<> 154:37f96f9d4de2 417 * words. Each 32-bit data port includes a GACR register, which defines the byte-level
<> 154:37f96f9d4de2 418 * attributes required for a successful access to the GPIO programming model. The attribute controls for the 4 data
<> 154:37f96f9d4de2 419 * bytes in the GACR follow a standard little endian
<> 154:37f96f9d4de2 420 * data convention.
<> 154:37f96f9d4de2 421 *
<> 154:37f96f9d4de2 422 * @param base FGPIO peripheral base pointer (FGPIOA, FGPIOB, FGPIOC, and so on.)
<> 154:37f96f9d4de2 423 * @param mask FGPIO pin number macro
<> 154:37f96f9d4de2 424 */
<> 154:37f96f9d4de2 425 void FGPIO_CheckAttributeBytes(FGPIO_Type *base, gpio_checker_attribute_t attribute);
<> 154:37f96f9d4de2 426 #endif
<> 154:37f96f9d4de2 427
<> 154:37f96f9d4de2 428 /*@}*/
<> 154:37f96f9d4de2 429
<> 154:37f96f9d4de2 430 #endif /* FSL_FEATURE_SOC_FGPIO_COUNT */
<> 154:37f96f9d4de2 431
<> 154:37f96f9d4de2 432 #if defined(__cplusplus)
<> 154:37f96f9d4de2 433 }
<> 154:37f96f9d4de2 434 #endif
<> 154:37f96f9d4de2 435
<> 154:37f96f9d4de2 436 /*!
<> 154:37f96f9d4de2 437 * @}
<> 154:37f96f9d4de2 438 */
<> 154:37f96f9d4de2 439
<> 154:37f96f9d4de2 440 #endif /* _FSL_GPIO_H_*/