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targets/hal/TARGET_ONSEMI/TARGET_NCS36510/rfAna.c@147:30b64687e01f, 2016-09-16 (annotated)

Committer:
<>
Date:
Fri Sep 16 16:24:25 2016 +0100
Revision:
147:30b64687e01f
Parent:
144:ef7eb2e8f9f7 
This updates the lib to the mbed lib v126

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file rfAna.c
<> 144:ef7eb2e8f9f7 4 * @brief Implementation of rfAna hw module functions
<> 144:ef7eb2e8f9f7 5 * @internal
<> 144:ef7eb2e8f9f7 6 * @author ON Semiconductor
<> 144:ef7eb2e8f9f7 7 * $Rev: 3445 $
<> 144:ef7eb2e8f9f7 8 * $Date: 2015-06-22 13:51:24 +0530 (Mon, 22 Jun 2015) $
<> 144:ef7eb2e8f9f7 9 ******************************************************************************
<> 147:30b64687e01f 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
<> 147:30b64687e01f 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
<> 147:30b64687e01f 12 * under limited terms and conditions. The terms and conditions pertaining to the software
<> 147:30b64687e01f 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
<> 147:30b64687e01f 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
<> 147:30b64687e01f 15 * if applicable the software license agreement. Do not use this software and/or
<> 147:30b64687e01f 16 * documentation unless you have carefully read and you agree to the limited terms and
<> 147:30b64687e01f 17 * conditions. By using this software and/or documentation, you agree to the limited
<> 147:30b64687e01f 18 * terms and conditions.
<> 144:ef7eb2e8f9f7 19 *
<> 144:ef7eb2e8f9f7 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 144:ef7eb2e8f9f7 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 144:ef7eb2e8f9f7 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 144:ef7eb2e8f9f7 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 144:ef7eb2e8f9f7 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 144:ef7eb2e8f9f7 25 * @endinternal
<> 144:ef7eb2e8f9f7 26 *
<> 144:ef7eb2e8f9f7 27 * @ingroup rfAna
<> 144:ef7eb2e8f9f7 28 *
<> 144:ef7eb2e8f9f7 29 * @details
<> 144:ef7eb2e8f9f7 30 *
<> 144:ef7eb2e8f9f7 31 * <h1> Reference document(s) </h1>
<> 144:ef7eb2e8f9f7 32 */
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 /*************************************************************************************************
<> 144:ef7eb2e8f9f7 35 * *
<> 144:ef7eb2e8f9f7 36 * Header files *
<> 144:ef7eb2e8f9f7 37 * *
<> 144:ef7eb2e8f9f7 38 *************************************************************************************************/
<> 144:ef7eb2e8f9f7 39
<> 144:ef7eb2e8f9f7 40 #include "memory_map.h"
<> 144:ef7eb2e8f9f7 41 #include "rfAna.h"
<> 144:ef7eb2e8f9f7 42 #include "clock.h"
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 #ifdef REVA
<> 144:ef7eb2e8f9f7 45 #include "test.h"
<> 144:ef7eb2e8f9f7 46 #endif
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48 /*************************************************************************************************
<> 144:ef7eb2e8f9f7 49 * *
<> 144:ef7eb2e8f9f7 50 * Global variables *
<> 144:ef7eb2e8f9f7 51 * *
<> 144:ef7eb2e8f9f7 52 *************************************************************************************************/
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 /** Rf channel and tx power lookup tables (constant)
<> 144:ef7eb2e8f9f7 55 * @details
<> 144:ef7eb2e8f9f7 56 *
<> 144:ef7eb2e8f9f7 57 * The rf channel table is used to program internal hardware register for different 15.4 rf channels.
<> 144:ef7eb2e8f9f7 58 * It has 16 entries corresponding to 16 15.4 channels.
<> 144:ef7eb2e8f9f7 59 * Entry 1 <-> Channel 11
<> 144:ef7eb2e8f9f7 60 * ...
<> 144:ef7eb2e8f9f7 61 * Entry 16 <-> Channel 26
<> 144:ef7eb2e8f9f7 62 *
<> 144:ef7eb2e8f9f7 63 * Each entry is compound of 4 items.
<> 144:ef7eb2e8f9f7 64 * Item 0: Rx Frequency integer divide portion
<> 144:ef7eb2e8f9f7 65 * Item 1: Rx Frequency fractional divide portion
<> 144:ef7eb2e8f9f7 66 * Item 2: Tx Frequency integer divide portion
<> 144:ef7eb2e8f9f7 67 * Item 3: Tx Frequency fractional divide portion
<> 144:ef7eb2e8f9f7 68 *
<> 144:ef7eb2e8f9f7 69 * The tx power table is used to program internal hardware register for different 15.4 tx power levels.
<> 144:ef7eb2e8f9f7 70 * It has 43 entries corresponding to tx power levels from -32dBm to +10dBm.
<> 144:ef7eb2e8f9f7 71 * Entry 1 <-> -32dB
<> 144:ef7eb2e8f9f7 72 * Entry 2 <-> -31dB
<> 144:ef7eb2e8f9f7 73 * ...
<> 144:ef7eb2e8f9f7 74 * Entry 2 <-> 9dB
<> 144:ef7eb2e8f9f7 75 * Entry 43 <-> +10dB
<> 144:ef7eb2e8f9f7 76 *
<> 144:ef7eb2e8f9f7 77 * Each entry is compound of 1 byte.
<> 144:ef7eb2e8f9f7 78 */
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 // RR: Making high side injection changes to RevD
<> 144:ef7eb2e8f9f7 81 #ifdef REVD
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 /** This rf LUT is built for high side injection, using low side injection
<> 144:ef7eb2e8f9f7 84 * would requiere to change this LUT. */
<> 144:ef7eb2e8f9f7 85 const uint32_t rfLut[16][4] = {{0x50,0x00D4A7,0x4B,0x00A000},
<> 144:ef7eb2e8f9f7 86 {0x50,0x017F52,0x4B,0x014001},
<> 144:ef7eb2e8f9f7 87 {0x51,0xFE29FB,0x4B,0x01E001},
<> 144:ef7eb2e8f9f7 88 {0x51,0xFED4A6,0x4C,0xFE7FFF},
<> 144:ef7eb2e8f9f7 89 {0x51,0xFF7F51,0x4C,0xFF1FFF},
<> 144:ef7eb2e8f9f7 90 {0x51,0x0029FC,0x4C,0xFFC000},
<> 144:ef7eb2e8f9f7 91 {0x51,0x00D4A7,0x4C,0x006000},
<> 144:ef7eb2e8f9f7 92 {0x51,0x017F52,0x4C,0x010001},
<> 144:ef7eb2e8f9f7 93 {0x52,0xFE29FB,0x4C,0x01A001},
<> 144:ef7eb2e8f9f7 94 {0x52,0xFED4A6,0x4D,0xFE3FFF},
<> 144:ef7eb2e8f9f7 95 {0x52,0xFF7F51,0x4D,0xFEDFFF},
<> 144:ef7eb2e8f9f7 96 {0x52,0x0029FC,0x4D,0xFF8000},
<> 144:ef7eb2e8f9f7 97 {0x52,0x00D4A7,0x4D,0x002000},
<> 144:ef7eb2e8f9f7 98 {0x52,0x017F52,0x4D,0x00C001},
<> 144:ef7eb2e8f9f7 99 {0x53,0xFE29FB,0x4D,0x016001},
<> 144:ef7eb2e8f9f7 100 {0x53,0xFED4A6,0x4E,0xFDFFFE}
<> 144:ef7eb2e8f9f7 101 };
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 const uint8_t txPowerLut[43] = {0,0,0, // -32dBm to -30dBm
<> 144:ef7eb2e8f9f7 104 0,0,0,0,0,0,0,0,0,0, // -29dBm to -20dBm
<> 144:ef7eb2e8f9f7 105 0,0,0,0,0,0,0,0,1,2, // -19dBm to -10dBm
<> 144:ef7eb2e8f9f7 106 3,4,5,6,7,8,9,10,11,12, // -9dBm to 0dBm
<> 144:ef7eb2e8f9f7 107 13,14,15,16,17,18,19,20,20,20
<> 144:ef7eb2e8f9f7 108 }; // +1dBm to +10 dBm
<> 144:ef7eb2e8f9f7 109
<> 144:ef7eb2e8f9f7 110 #endif /* REVD */
<> 144:ef7eb2e8f9f7 111
<> 144:ef7eb2e8f9f7 112 #ifdef REVC
<> 144:ef7eb2e8f9f7 113 /** This rf LUT is built for low side injection, using high side injection
<> 144:ef7eb2e8f9f7 114 * would requiere to change this LUT. */
<> 144:ef7eb2e8f9f7 115 const uint32_t rfLut[16][4] = {{0x47,0xFF15FC,0x4B,0x00A000},
<> 144:ef7eb2e8f9f7 116 {0x47,0xFFAC93,0x4B,0x014001},
<> 144:ef7eb2e8f9f7 117 {0x47,0x00432A,0x4B,0x01E001},
<> 144:ef7eb2e8f9f7 118 {0x47,0x00D9C1,0x4C,0xFE7FFF},
<> 144:ef7eb2e8f9f7 119 {0x47,0x017058,0x4C,0xFF1FFF},
<> 144:ef7eb2e8f9f7 120 {0x48,0xFE06EC,0x4C,0xFFC000},
<> 144:ef7eb2e8f9f7 121 {0x48,0xFE9D83,0x4C,0x006000},
<> 144:ef7eb2e8f9f7 122 {0x48,0xFF341A,0x4C,0x010001},
<> 144:ef7eb2e8f9f7 123 {0x48,0xFFCAB1,0x4C,0x01A001},
<> 144:ef7eb2e8f9f7 124 {0x48,0x006148,0x4D,0xFE3FFF},
<> 144:ef7eb2e8f9f7 125 {0x48,0x00F7DF,0x4D,0xFEDFFF},
<> 144:ef7eb2e8f9f7 126 {0x48,0x018E76,0x4D,0xFF8000},
<> 144:ef7eb2e8f9f7 127 {0x49,0xFE250A,0x4D,0x002000},
<> 144:ef7eb2e8f9f7 128 {0x49,0xFEBBA1,0x4D,0x00C001},
<> 144:ef7eb2e8f9f7 129 {0x49,0xFF5238,0x4D,0x016001},
<> 144:ef7eb2e8f9f7 130 {0x49,0xFFE8CF,0x4E,0xFDFFFE}
<> 144:ef7eb2e8f9f7 131 };
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 const uint8_t txPowerLut[43] = {0,0,0, // -32dBm to -30dBm
<> 144:ef7eb2e8f9f7 134 0,0,0,0,0,0,0,0,0,0, // -29dBm to -20dBm
<> 144:ef7eb2e8f9f7 135 0,0,0,0,0,0,1,1,2,2, // -19dBm to -10dBm (clamp low at -14dB)
<> 144:ef7eb2e8f9f7 136 3,3,4,6,7,9,10,12,13,15, // -9dBm to 0dBm
<> 144:ef7eb2e8f9f7 137 17,19,20,20,20,20,20,20,20,20
<> 144:ef7eb2e8f9f7 138 }; // +1dBm to +10 dBm (clamp high at +3dB)
<> 144:ef7eb2e8f9f7 139 #endif /* REVC */
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 #ifdef REVB
<> 144:ef7eb2e8f9f7 142 /** This rf LUT is built for low side injection, using high side injection
<> 144:ef7eb2e8f9f7 143 * would requiere to change this LUT. */
<> 144:ef7eb2e8f9f7 144 const uint32_t rfLut[16][4] = {{0x47,0xFF15FC,0x4B,0x00A000},
<> 144:ef7eb2e8f9f7 145 {0x47,0xFFAC93,0x4B,0x014001},
<> 144:ef7eb2e8f9f7 146 {0x47,0x00432A,0x4B,0x01E001},
<> 144:ef7eb2e8f9f7 147 {0x47,0x00D9C1,0x4C,0xFE7FFF},
<> 144:ef7eb2e8f9f7 148 {0x47,0x017058,0x4C,0xFF1FFF},
<> 144:ef7eb2e8f9f7 149 {0x48,0xFE06EC,0x4C,0xFFC000},
<> 144:ef7eb2e8f9f7 150 {0x48,0xFE9D83,0x4C,0x006000},
<> 144:ef7eb2e8f9f7 151 {0x48,0xFF341A,0x4C,0x010001},
<> 144:ef7eb2e8f9f7 152 {0x48,0xFFCAB1,0x4C,0x01A001},
<> 144:ef7eb2e8f9f7 153 {0x48,0x006148,0x4D,0xFE3FFF},
<> 144:ef7eb2e8f9f7 154 {0x48,0x00F7DF,0x4D,0xFEDFFF},
<> 144:ef7eb2e8f9f7 155 {0x48,0x018E76,0x4D,0xFF8000},
<> 144:ef7eb2e8f9f7 156 {0x49,0xFE250A,0x4D,0x002000},
<> 144:ef7eb2e8f9f7 157 {0x49,0xFEBBA1,0x4D,0x00C001},
<> 144:ef7eb2e8f9f7 158 {0x49,0xFF5238,0x4D,0x016001},
<> 144:ef7eb2e8f9f7 159 {0x49,0xFFE8CF,0x4E,0xFDFFFE}
<> 144:ef7eb2e8f9f7 160 };
<> 144:ef7eb2e8f9f7 161
<> 144:ef7eb2e8f9f7 162 const uint8_t txPowerLut[43] = {0,0,0, // -32dBm to -30dBm
<> 144:ef7eb2e8f9f7 163 0,0,0,0,0,0,0,0,0,0, // -29dBm to -20dBm
<> 144:ef7eb2e8f9f7 164 0,0,0,0,0,0,1,1,2,2, // -19dBm to -10dBm (clamp low at -14dB)
<> 144:ef7eb2e8f9f7 165 3,3,4,6,7,9,10,12,13,15, // -9dBm to 0dBm
<> 144:ef7eb2e8f9f7 166 17,19,20,20,20,20,20,20,20,20
<> 144:ef7eb2e8f9f7 167 }; // +1dBm to +10 dBm (clamp high at +3dB)
<> 144:ef7eb2e8f9f7 168 #endif
<> 144:ef7eb2e8f9f7 169
<> 144:ef7eb2e8f9f7 170 #ifdef REVA
<> 144:ef7eb2e8f9f7 171 const uint32_t rfLut[16][4] = {{0x57,0xFF5D2F,0x51,0x018001},
<> 144:ef7eb2e8f9f7 172 {0x57,0x0007DA,0x52,0xFE1FFF},
<> 144:ef7eb2e8f9f7 173 {0x57,0x00B285,0x52,0xFEBFFF},
<> 144:ef7eb2e8f9f7 174 {0x57,0x015D30,0x52,0xFF6000},
<> 144:ef7eb2e8f9f7 175 {0x58,0xFE07D8,0x52,0x000000},
<> 144:ef7eb2e8f9f7 176 {0x58,0xFEB283,0x52,0x00A000},
<> 144:ef7eb2e8f9f7 177 {0x58,0xFF5D2F,0x52,0x014001},
<> 144:ef7eb2e8f9f7 178 {0x58,0x0007DA,0x52,0x01E001},
<> 144:ef7eb2e8f9f7 179 {0x58,0x00B285,0x53,0xFE7FFF},
<> 144:ef7eb2e8f9f7 180 {0x58,0x015D30,0x53,0xFF1FFF},
<> 144:ef7eb2e8f9f7 181 {0x59,0xFE07D8,0x53,0xFFC000},
<> 144:ef7eb2e8f9f7 182 {0x59,0xFEB283,0x53,0x006000},
<> 144:ef7eb2e8f9f7 183 {0x59,0xFF5D2F,0x53,0x010001},
<> 144:ef7eb2e8f9f7 184 {0x59,0x0007DA,0x53,0x01A001},
<> 144:ef7eb2e8f9f7 185 {0x59,0x00B285,0x53,0xFE3FFF},
<> 144:ef7eb2e8f9f7 186 {0x59,0x015D30,0x53,0xFEDFFF}
<> 144:ef7eb2e8f9f7 187 };
<> 144:ef7eb2e8f9f7 188
<> 144:ef7eb2e8f9f7 189 const uint8_t txPowerLut[43] = {1,2,3, // -32dBm to -30dBm
<> 144:ef7eb2e8f9f7 190 4,5,5,5,5,5,5,5,5,5, // -29dBm to -20dBm (clamp at -28dB)
<> 144:ef7eb2e8f9f7 191 5,5,5,5,5,5,5,5,5,5, // -19dBm to -10dBm
<> 144:ef7eb2e8f9f7 192 5,5,5,5,5,5,5,5,5,5, // -9dBm to 0dBm
<> 144:ef7eb2e8f9f7 193 5,5,5,5,5,5,5,5,5,5
<> 144:ef7eb2e8f9f7 194 }; // +1dBm to +10 dBm
<> 144:ef7eb2e8f9f7 195 #endif
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 /*************************************************************************************************
<> 144:ef7eb2e8f9f7 198 * *
<> 144:ef7eb2e8f9f7 199 * Functions *
<> 144:ef7eb2e8f9f7 200 * *
<> 144:ef7eb2e8f9f7 201 *************************************************************************************************/
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 void fRfAnaInit()
<> 144:ef7eb2e8f9f7 204 {
<> 144:ef7eb2e8f9f7 205 // Enable rfana clock
<> 144:ef7eb2e8f9f7 206 CLOCK_ENABLE(CLOCK_RFANA);
<> 144:ef7eb2e8f9f7 207
<> 144:ef7eb2e8f9f7 208 #ifdef REVA
<> 144:ef7eb2e8f9f7 209 // Force Pll lock (it shouldn't be needed for either silicon if the part is configured/trimmed properly)
<> 144:ef7eb2e8f9f7 210 fTestForcePllLock();
<> 144:ef7eb2e8f9f7 211 // Bypass Pll regulator
<> 144:ef7eb2e8f9f7 212 fTestBypassPllReg();
<> 144:ef7eb2e8f9f7 213 #endif
<> 144:ef7eb2e8f9f7 214
<> 144:ef7eb2e8f9f7 215 // Set PLL timing
<> 144:ef7eb2e8f9f7 216 RFANAREG->PLL_TIMING.BITS.PLL_RESET_TIME = 0x1E; // 30us
<> 144:ef7eb2e8f9f7 217 RFANAREG->PLL_TIMING.BITS.PLL_LOCK_TIME = 0x2F; // 47us
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 // Set other parameters
<> 144:ef7eb2e8f9f7 220 RFANAREG->RX_CONTROL.BITS.LNA_GAIN_MODE = 0x1; // High Gain mode
<> 144:ef7eb2e8f9f7 221 RFANAREG->RX_CONTROL.BITS.ADC_DITHER_MODE = 0x0; // Dither mode disabled
<> 144:ef7eb2e8f9f7 222 }
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 boolean fRfAnaIoctl (uint32_t request, void *argument)
<> 144:ef7eb2e8f9f7 225 {
<> 144:ef7eb2e8f9f7 226 uint8_t channel, txPower;
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 // Enable rfana clock (in case fRfAnaIoctl is used before call of fRfAnaInit)
<> 144:ef7eb2e8f9f7 229 CLOCK_ENABLE(CLOCK_RFANA);
<> 144:ef7eb2e8f9f7 230
<> 144:ef7eb2e8f9f7 231 switch(request) {
<> 144:ef7eb2e8f9f7 232 case SET_RF_CHANNEL:
<> 144:ef7eb2e8f9f7 233 channel = *(uint8_t*)argument;
<> 144:ef7eb2e8f9f7 234
<> 144:ef7eb2e8f9f7 235 // Set tx/rx integer/fractional divide portions
<> 144:ef7eb2e8f9f7 236 RFANAREG->TX_LO_CONTROL.BITS.FRACT_WORD = rfLut[channel - 11][3];
<> 144:ef7eb2e8f9f7 237 RFANAREG->TX_LO_CONTROL.BITS.INT_WORD = rfLut[channel - 11][2];
<> 144:ef7eb2e8f9f7 238 RFANAREG->RX_LO_CONTROL.BITS.FRACT_WORD = rfLut[channel - 11][1];
<> 144:ef7eb2e8f9f7 239 RFANAREG->RX_LO_CONTROL.BITS.INT_WORD = rfLut[channel - 11][0];
<> 144:ef7eb2e8f9f7 240
<> 144:ef7eb2e8f9f7 241 // Set tx/rx vco trims
<> 144:ef7eb2e8f9f7 242 #ifdef REVB
<> 144:ef7eb2e8f9f7 243 /** REVB is requiering to adjust tx/rx vco trims each time a new 15.4 channel is used, in revB it is done
<> 144:ef7eb2e8f9f7 244 * from trims stored in flash A, it has the drawback that it is not workable when flash A is not accessible.*/
<> 144:ef7eb2e8f9f7 245 if (channel < 19) {
<> 144:ef7eb2e8f9f7 246 RFANATRIMREG->PLL_TRIM.BITS.TX_VCO_TRIM = (TRIMREG->TX_VCO_LUT1.WORD) >> ((channel - 11) * 4);
<> 144:ef7eb2e8f9f7 247 RFANATRIMREG->PLL_TRIM.BITS.RX_VCO_TRIM = (TRIMREG->RX_VCO_LUT1.WORD) >> ((channel - 11) * 4);
<> 144:ef7eb2e8f9f7 248 } else {
<> 144:ef7eb2e8f9f7 249 RFANATRIMREG->PLL_TRIM.BITS.TX_VCO_TRIM = (TRIMREG->TX_VCO_LUT2.WORD) >> ((channel - 19) * 4);
<> 144:ef7eb2e8f9f7 250 RFANATRIMREG->PLL_TRIM.BITS.RX_VCO_TRIM = (TRIMREG->RX_VCO_LUT2.WORD) >> ((channel - 19) * 4);
<> 144:ef7eb2e8f9f7 251 }
<> 144:ef7eb2e8f9f7 252 #endif /* REVB */
<> 144:ef7eb2e8f9f7 253 #ifdef REVC
<> 144:ef7eb2e8f9f7 254 /** REVC is requiering to adjust tx/rx vco trims each time a new 15.4 channel is used, in revB it is done
<> 144:ef7eb2e8f9f7 255 * from trims stored in dedicated registers available in digital.*/
<> 144:ef7eb2e8f9f7 256 if (channel < 19) {
<> 144:ef7eb2e8f9f7 257 RFANATRIMREG->PLL_TRIM.BITS.TX_VCO_TRIM = (RFANATRIMREG->TX_VCO_TRIM_LUT1) >> ((channel - 11) * 4);
<> 144:ef7eb2e8f9f7 258 RFANATRIMREG->PLL_TRIM.BITS.RX_VCO_TRIM = (RFANATRIMREG->RX_VCO_TRIM_LUT1) >> ((channel - 11) * 4);
<> 144:ef7eb2e8f9f7 259 } else {
<> 144:ef7eb2e8f9f7 260 RFANATRIMREG->PLL_TRIM.BITS.TX_VCO_TRIM = (RFANATRIMREG->TX_VCO_TRIM_LUT2) >> ((channel - 19) * 4);
<> 144:ef7eb2e8f9f7 261 RFANATRIMREG->PLL_TRIM.BITS.RX_VCO_TRIM = (RFANATRIMREG->RX_VCO_TRIM_LUT2) >> ((channel - 19) * 4);
<> 144:ef7eb2e8f9f7 262 }
<> 144:ef7eb2e8f9f7 263 #endif /* REVC */
<> 144:ef7eb2e8f9f7 264 #ifdef REVD
<> 144:ef7eb2e8f9f7 265 /** REVD is requiering to adjust tx/rx vco trims each time a new 15.4 channel is used, in revB it is done
<> 144:ef7eb2e8f9f7 266 * from trims stored in dedicated registers available in digital.*/
<> 144:ef7eb2e8f9f7 267 if (channel < 19) {
<> 144:ef7eb2e8f9f7 268 RFANATRIMREG->PLL_TRIM.BITS.TX_VCO_TRIM = (RFANATRIMREG->TX_VCO_TRIM_LUT1) >> ((channel - 11) * 4);
<> 144:ef7eb2e8f9f7 269 RFANATRIMREG->PLL_TRIM.BITS.RX_VCO_TRIM = (RFANATRIMREG->RX_VCO_TRIM_LUT1) >> ((channel - 11) * 4);
<> 144:ef7eb2e8f9f7 270 } else {
<> 144:ef7eb2e8f9f7 271 RFANATRIMREG->PLL_TRIM.BITS.TX_VCO_TRIM = (RFANATRIMREG->TX_VCO_TRIM_LUT2) >> ((channel - 19) * 4);
<> 144:ef7eb2e8f9f7 272 RFANATRIMREG->PLL_TRIM.BITS.RX_VCO_TRIM = (RFANATRIMREG->RX_VCO_TRIM_LUT2) >> ((channel - 19) * 4);
<> 144:ef7eb2e8f9f7 273 }
<> 144:ef7eb2e8f9f7 274 #endif /* REVD */
<> 144:ef7eb2e8f9f7 275 break;
<> 144:ef7eb2e8f9f7 276 case SET_TX_POWER:
<> 144:ef7eb2e8f9f7 277 txPower = *(uint8_t*)argument;
<> 144:ef7eb2e8f9f7 278
<> 144:ef7eb2e8f9f7 279 // Set tx power register
<> 144:ef7eb2e8f9f7 280 if ((txPower & 0x20) == 0) {
<> 144:ef7eb2e8f9f7 281 RFANAREG->TX_POWER = (txPowerLut[txPower + 32] & 0xFF);
<> 144:ef7eb2e8f9f7 282 } else {
<> 144:ef7eb2e8f9f7 283 RFANAREG->TX_POWER = (txPowerLut[txPower - 32] & 0xFF);
<> 144:ef7eb2e8f9f7 284 }
<> 144:ef7eb2e8f9f7 285
<> 144:ef7eb2e8f9f7 286 break;
<> 144:ef7eb2e8f9f7 287 default:
<> 144:ef7eb2e8f9f7 288 return False;
<> 144:ef7eb2e8f9f7 289 }
<> 144:ef7eb2e8f9f7 290 return True;
<> 144:ef7eb2e8f9f7 291 }