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targets/hal/TARGET_ONSEMI/TARGET_NCS36510/ncs36510Init.c@147:30b64687e01f, 2016-09-16 (annotated)

Committer:
<>
Date:
Fri Sep 16 16:24:25 2016 +0100
Revision:
147:30b64687e01f
Parent:
144:ef7eb2e8f9f7 
This updates the lib to the mbed lib v126

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ***************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file ncs36510_init.c
<> 144:ef7eb2e8f9f7 4 * @brief Initialization of Orion SoC
<> 144:ef7eb2e8f9f7 5 * @internal
<> 144:ef7eb2e8f9f7 6 * @author ON Semiconductor
<> 144:ef7eb2e8f9f7 7 * $Rev:
<> 144:ef7eb2e8f9f7 8 * $Date: $
<> 144:ef7eb2e8f9f7 9 ******************************************************************************
<> 147:30b64687e01f 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
<> 147:30b64687e01f 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
<> 147:30b64687e01f 12 * under limited terms and conditions. The terms and conditions pertaining to the software
<> 147:30b64687e01f 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
<> 147:30b64687e01f 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
<> 147:30b64687e01f 15 * if applicable the software license agreement. Do not use this software and/or
<> 147:30b64687e01f 16 * documentation unless you have carefully read and you agree to the limited terms and
<> 147:30b64687e01f 17 * conditions. By using this software and/or documentation, you agree to the limited
<> 147:30b64687e01f 18 * terms and conditions.
<> 144:ef7eb2e8f9f7 19 *
<> 144:ef7eb2e8f9f7 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 144:ef7eb2e8f9f7 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 144:ef7eb2e8f9f7 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 144:ef7eb2e8f9f7 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 144:ef7eb2e8f9f7 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 144:ef7eb2e8f9f7 25 * @endinternal
<> 144:ef7eb2e8f9f7 26 *
<> 144:ef7eb2e8f9f7 27 * @ingroup main
<> 144:ef7eb2e8f9f7 28 *
<> 144:ef7eb2e8f9f7 29 * @details
<> 144:ef7eb2e8f9f7 30 */
<> 144:ef7eb2e8f9f7 31
<> 144:ef7eb2e8f9f7 32 /*************************************************************************************************
<> 144:ef7eb2e8f9f7 33 * *
<> 144:ef7eb2e8f9f7 34 * Header files *
<> 144:ef7eb2e8f9f7 35 * *
<> 144:ef7eb2e8f9f7 36 *************************************************************************************************/
<> 147:30b64687e01f 37 #include "ncs36510Init.h"
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 void fPmuInit(void);
<> 144:ef7eb2e8f9f7 40 /**
<> 144:ef7eb2e8f9f7 41 * @brief
<> 144:ef7eb2e8f9f7 42 * Hardware trimming function
<> 144:ef7eb2e8f9f7 43 * This function copies trim codes from specific flash location
<> 144:ef7eb2e8f9f7 44 * where they are stored to proper hw registers.
<> 144:ef7eb2e8f9f7 45 */
<> 144:ef7eb2e8f9f7 46 boolean fTrim()
<> 144:ef7eb2e8f9f7 47 {
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /**- Check if trim values are present */
<> 144:ef7eb2e8f9f7 50 /**- If Trim data is present. Only trim if valid trim values are present. */
<> 144:ef7eb2e8f9f7 51 /**- Copy trims in registers */
<> 144:ef7eb2e8f9f7 52 if (TRIMREG->REVISION_CODE != 0xFFFFFFFF) {
<> 144:ef7eb2e8f9f7 53
<> 144:ef7eb2e8f9f7 54 /**- board specific clock trims may only be done when present, writing all 1's is not good */
<> 144:ef7eb2e8f9f7 55 if ((TRIMREG->TRIM_32K_EXT & 0xFFFF0000) != 0xFFFF0000) {
<> 144:ef7eb2e8f9f7 56 CLOCKREG->TRIM_32K_EXT = TRIMREG->TRIM_32K_EXT;
<> 144:ef7eb2e8f9f7 57 }
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 if ((TRIMREG->TRIM_32M_EXT & 0xFFFF0000) != 0xFFFF0000) {
<> 144:ef7eb2e8f9f7 60 CLOCKREG->TRIM_32M_EXT = TRIMREG->TRIM_32M_EXT;
<> 144:ef7eb2e8f9f7 61 }
<> 144:ef7eb2e8f9f7 62
<> 144:ef7eb2e8f9f7 63 MACHWREG->TX_LENGTH.BITS.TX_PRE_CHIPS = TRIMREG->TX_PRE_CHIPS;
<> 144:ef7eb2e8f9f7 64
<> 144:ef7eb2e8f9f7 65 RFANATRIMREG->TX_CHAIN_TRIM = TRIMREG->TX_CHAIN_TRIM;
<> 144:ef7eb2e8f9f7 66 RFANATRIMREG->PLL_VCO_TAP_LOCATION = TRIMREG->PLL_VCO_TAP_LOCATION;
<> 144:ef7eb2e8f9f7 67 RFANATRIMREG->PLL_TRIM.WORD = TRIMREG->PLL_TRIM;
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 /**- board specific RSSI trims may only be done when present, writing all 1's is not good */
<> 144:ef7eb2e8f9f7 70 if ((TRIMREG->RSSI_OFFSET & 0xFFFF0000) != 0xFFFF0000) {
<> 144:ef7eb2e8f9f7 71 DMDREG->DMD_CONTROL2.BITS.RSSI_OFFSET = TRIMREG->RSSI_OFFSET;
<> 144:ef7eb2e8f9f7 72 }
<> 144:ef7eb2e8f9f7 73
<> 144:ef7eb2e8f9f7 74 RFANATRIMREG->RX_CHAIN_TRIM = TRIMREG->RX_CHAIN_TRIM;
<> 144:ef7eb2e8f9f7 75 RFANATRIMREG->PMU_TRIM = TRIMREG->PMU_TRIM;
<> 144:ef7eb2e8f9f7 76 RANDREG->WR_SEED_RD_RAND = TRIMREG->WR_SEED_RD_RAND;
<> 144:ef7eb2e8f9f7 77
<> 144:ef7eb2e8f9f7 78 /** REVD boards are trimmed (in flash) with rx vco trims specific for high side injection,
<> 144:ef7eb2e8f9f7 79 * */
<> 144:ef7eb2e8f9f7 80 RFANATRIMREG->RX_VCO_TRIM_LUT1 = TRIMREG->RX_VCO_LUT1.WORD;;
<> 144:ef7eb2e8f9f7 81 RFANATRIMREG->RX_VCO_TRIM_LUT2 = TRIMREG->RX_VCO_LUT2.WORD;;
<> 144:ef7eb2e8f9f7 82
<> 144:ef7eb2e8f9f7 83 RFANATRIMREG->TX_VCO_TRIM_LUT1 = TRIMREG->TX_VCO_LUT1.WORD;;
<> 144:ef7eb2e8f9f7 84 RFANATRIMREG->TX_VCO_TRIM_LUT2 = TRIMREG->TX_VCO_LUT2.WORD;;
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86
<> 144:ef7eb2e8f9f7 87 return True;
<> 144:ef7eb2e8f9f7 88 } else {
<> 144:ef7eb2e8f9f7 89 /**- If no trim values are present, update the global status variable. */
<> 144:ef7eb2e8f9f7 90 return False;
<> 144:ef7eb2e8f9f7 91 }
<> 144:ef7eb2e8f9f7 92 }
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 /* See clock.h for documentation. */
<> 144:ef7eb2e8f9f7 95 void fClockInit()
<> 144:ef7eb2e8f9f7 96 {
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 /** Enable external 32MHz oscillator */
<> 144:ef7eb2e8f9f7 99 CLOCKREG->CCR.BITS.OSC_SEL = 1;
<> 144:ef7eb2e8f9f7 100
<> 144:ef7eb2e8f9f7 101 /** - Wait external 32MHz oscillator to be ready */
<> 144:ef7eb2e8f9f7 102 while(CLOCKREG->CSR.BITS.XTAL32M != 1) {} /* If you get stuck here, something is wrong with board or trim values */
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 /** Internal 32MHz calibration \n *//** - Enable internal 32MHz clock */
<> 144:ef7eb2e8f9f7 105 PMUREG->CONTROL.BITS.INT32M = 0;
<> 144:ef7eb2e8f9f7 106
<> 144:ef7eb2e8f9f7 107 /** - Wait 5 uSec for clock to stabilize */
<> 144:ef7eb2e8f9f7 108 volatile uint8_t Timer;
<> 144:ef7eb2e8f9f7 109 for(Timer = 0; Timer < 10; Timer++);
<> 144:ef7eb2e8f9f7 110
<> 144:ef7eb2e8f9f7 111 /** - Enable calibration */
<> 144:ef7eb2e8f9f7 112 CLOCKREG->CCR.BITS.CAL32M = True;
<> 144:ef7eb2e8f9f7 113
<> 144:ef7eb2e8f9f7 114 /** - Wait calibration to be completed */
<> 144:ef7eb2e8f9f7 115 while(CLOCKREG->CSR.BITS.CAL32MDONE == False); /* If you stuck here, issue with internal 32M calibration */
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 /** - Check calibration status */
<> 144:ef7eb2e8f9f7 118 while(CLOCKREG->CSR.BITS.CAL32MFAIL == True); /* If you stuck here, issue with internal 32M calibration */
<> 144:ef7eb2e8f9f7 119
<> 144:ef7eb2e8f9f7 120 /** - Power down internal 32MHz osc */
<> 144:ef7eb2e8f9f7 121 PMUREG->CONTROL.BITS.INT32M = 1;
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 /** Internal 32KHz calibration \n */ /** - Enable internal 32KHz clock */
<> 144:ef7eb2e8f9f7 124 PMUREG->CONTROL.BITS.INT32K = 0;
<> 144:ef7eb2e8f9f7 125
<> 144:ef7eb2e8f9f7 126 /** - Wait 5 uSec for clock to stabilize */
<> 144:ef7eb2e8f9f7 127 for(Timer = 0; Timer < 10; Timer++);
<> 144:ef7eb2e8f9f7 128
<> 144:ef7eb2e8f9f7 129 /** - Enable calibration */
<> 144:ef7eb2e8f9f7 130 CLOCKREG->CCR.BITS.CAL32K = True;
<> 144:ef7eb2e8f9f7 131
<> 144:ef7eb2e8f9f7 132 /** - Wait calibration to be completed */
<> 144:ef7eb2e8f9f7 133 while(CLOCKREG->CSR.BITS.DONE32K == False); /* If you stuck here, issue with internal 32K calibration */
<> 144:ef7eb2e8f9f7 134
<> 144:ef7eb2e8f9f7 135 /** - Check calibration status */
<> 144:ef7eb2e8f9f7 136 while(CLOCKREG->CSR.BITS.CAL32K == True); /* If you stuck here, issue with internal 32M calibration */
<> 144:ef7eb2e8f9f7 137
<> 144:ef7eb2e8f9f7 138 /** - Power down external 32KHz osc */
<> 144:ef7eb2e8f9f7 139 PMUREG->CONTROL.BITS.EXT32K = 1;
<> 144:ef7eb2e8f9f7 140
<> 144:ef7eb2e8f9f7 141 /** Disable all peripheral clocks by default */
<> 144:ef7eb2e8f9f7 142 CLOCKREG->PDIS.WORD = 0xFFFFFFFF;
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 /** Set core frequency */
<> 144:ef7eb2e8f9f7 145 CLOCKREG->FDIV = CPU_CLOCK_DIV - 1;
<> 144:ef7eb2e8f9f7 146 }
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 /* Initializes PMU module */
<> 144:ef7eb2e8f9f7 149 void fPmuInit()
<> 144:ef7eb2e8f9f7 150 {
<> 144:ef7eb2e8f9f7 151 /** Enable the clock for PMU peripheral device */
<> 144:ef7eb2e8f9f7 152 CLOCK_ENABLE(CLOCK_PMU);
<> 144:ef7eb2e8f9f7 153
<> 144:ef7eb2e8f9f7 154 /** Unset wakeup on pending (only enabled irq can wakeup) */
<> 144:ef7eb2e8f9f7 155 SCB->SCR &= ~SCB_SCR_SEVONPEND_Msk;
<> 144:ef7eb2e8f9f7 156
<> 144:ef7eb2e8f9f7 157 /** Unset auto sleep when returning from wakeup irq */
<> 144:ef7eb2e8f9f7 158 SCB->SCR &= ~SCB_SCR_SLEEPONEXIT_Msk;
<> 144:ef7eb2e8f9f7 159
<> 144:ef7eb2e8f9f7 160 /** Set regulator timings */
<> 144:ef7eb2e8f9f7 161 PMUREG->FVDD_TSETTLE = 160;
<> 144:ef7eb2e8f9f7 162 PMUREG->FVDD_TSTARTUP = 400;
<> 144:ef7eb2e8f9f7 163
<> 144:ef7eb2e8f9f7 164 /** Keep SRAMA & SRAMB powered in coma mode */
<> 144:ef7eb2e8f9f7 165 PMUREG->CONTROL.BITS.SRAMA = False;
<> 144:ef7eb2e8f9f7 166 PMUREG->CONTROL.BITS.SRAMB = False;
<> 144:ef7eb2e8f9f7 167
<> 144:ef7eb2e8f9f7 168 PMUREG->CONTROL.BITS.N1V1 = True; /* Enable ACTIVE mode switching regulator */
<> 144:ef7eb2e8f9f7 169 PMUREG->CONTROL.BITS.C1V1 = True; /* Enable COMA mode switching regulator */
<> 144:ef7eb2e8f9f7 170
<> 144:ef7eb2e8f9f7 171 /** Disable the clock for PMU peripheral device, all settings are done */
<> 144:ef7eb2e8f9f7 172 CLOCK_DISABLE(CLOCK_PMU);
<> 144:ef7eb2e8f9f7 173 }
<> 144:ef7eb2e8f9f7 174
<> 144:ef7eb2e8f9f7 175 /* See clock.h for documentation. */
<> 144:ef7eb2e8f9f7 176 uint32_t fClockGetPeriphClockfrequency()
<> 144:ef7eb2e8f9f7 177 {
<> 144:ef7eb2e8f9f7 178 return (CPU_CLOCK_ROOT_HZ / CPU_CLOCK_DIV);
<> 144:ef7eb2e8f9f7 179 }
<> 144:ef7eb2e8f9f7 180
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 /**
<> 144:ef7eb2e8f9f7 183 * @brief
<> 144:ef7eb2e8f9f7 184 * Hardware initialization function
<> 144:ef7eb2e8f9f7 185 * This function initializes hardware at application start up prior
<> 144:ef7eb2e8f9f7 186 * to other initializations or OS operations.
<> 144:ef7eb2e8f9f7 187 */
<> 144:ef7eb2e8f9f7 188 static void fHwInit(void)
<> 144:ef7eb2e8f9f7 189 {
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 /* Trim register settings */
<> 144:ef7eb2e8f9f7 192 fTrim();
<> 144:ef7eb2e8f9f7 193
<> 144:ef7eb2e8f9f7 194 /* Clock setting */
<> 144:ef7eb2e8f9f7 195 /** - Initialize clock */
<> 144:ef7eb2e8f9f7 196 fClockInit();
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 /** - Initialize pmu */
<> 144:ef7eb2e8f9f7 199 fPmuInit();
<> 144:ef7eb2e8f9f7 200
<> 144:ef7eb2e8f9f7 201 /** Orion has 4 interrupt bits in interrupt priority register
<> 144:ef7eb2e8f9f7 202 * The lowest 4 bits are not used.
<> 144:ef7eb2e8f9f7 203 *
<> 144:ef7eb2e8f9f7 204 @verbatim
<> 144:ef7eb2e8f9f7 205 +-----+-----+-----+-----+-----+-----+-----+-----+
<> 144:ef7eb2e8f9f7 206 |bit 7|bit 6|bit 5|bit 4|bit 3|bit 2|bit 1|bit 0|
<> 144:ef7eb2e8f9f7 207 | | | | | 0 | 0 | 0 | 0 |
<> 144:ef7eb2e8f9f7 208 +-----+-----+-----+-----+-----+-----+-----+-----+
<> 144:ef7eb2e8f9f7 209 |
<> 144:ef7eb2e8f9f7 210 INTERRUPT PRIORITY | NOT IMPLEMENTED,
<> 144:ef7eb2e8f9f7 211 | read as 0
<> 144:ef7eb2e8f9f7 212 Valid priorities are 0x00, 0x10, 0x20, 0x30
<> 144:ef7eb2e8f9f7 213 0x40, 0x50, 0x60, 0x70
<> 144:ef7eb2e8f9f7 214 0x80, 0x90, 0xA0, 0xB0
<> 144:ef7eb2e8f9f7 215 0xC0, 0xD0, 0xE0, 0xF0
<> 144:ef7eb2e8f9f7 216 @endverbatim
<> 144:ef7eb2e8f9f7 217 * Lowest number is highest priority
<> 144:ef7eb2e8f9f7 218 *
<> 144:ef7eb2e8f9f7 219 *
<> 144:ef7eb2e8f9f7 220 * This range is defined by
<> 144:ef7eb2e8f9f7 221 * configKERNEL_INTERRUPT_PRIORITY (lowest)
<> 144:ef7eb2e8f9f7 222 * and configMAX_SYSCALL_INTERRUPT_PRIORITY (highest). All interrupt
<> 144:ef7eb2e8f9f7 223 * priorities need to fall in that range.
<> 144:ef7eb2e8f9f7 224 *
<> 144:ef7eb2e8f9f7 225 * To be future safe, the LSbits of the priority are set to 0xF.
<> 144:ef7eb2e8f9f7 226 * This wil lmake sure that if more interrupt bits are used, the
<> 144:ef7eb2e8f9f7 227 * priority is maintained.
<> 144:ef7eb2e8f9f7 228 */
<> 144:ef7eb2e8f9f7 229
<> 144:ef7eb2e8f9f7 230 /** - Set IRQs priorities */
<> 144:ef7eb2e8f9f7 231 NVIC_SetPriority(Tim0_IRQn, 14);
<> 144:ef7eb2e8f9f7 232 NVIC_SetPriority(Tim1_IRQn, 14);
<> 144:ef7eb2e8f9f7 233 NVIC_SetPriority(Tim2_IRQn, 14);
<> 144:ef7eb2e8f9f7 234 NVIC_SetPriority(Uart1_IRQn,14);
<> 144:ef7eb2e8f9f7 235 NVIC_SetPriority(Spi_IRQn, 14);
<> 144:ef7eb2e8f9f7 236 NVIC_SetPriority(I2C_IRQn, 14);
<> 144:ef7eb2e8f9f7 237 NVIC_SetPriority(Gpio_IRQn, 14);
<> 144:ef7eb2e8f9f7 238 NVIC_SetPriority(Rtc_IRQn, 14);
<> 144:ef7eb2e8f9f7 239 NVIC_SetPriority(MacHw_IRQn, 13);
<> 144:ef7eb2e8f9f7 240 NVIC_SetPriority(Aes_IRQn, 13);
<> 144:ef7eb2e8f9f7 241 NVIC_SetPriority(Adc_IRQn, 14);
<> 144:ef7eb2e8f9f7 242 NVIC_SetPriority(ClockCal_IRQn, 14);
<> 144:ef7eb2e8f9f7 243 NVIC_SetPriority(Uart2_IRQn, 14);
<> 144:ef7eb2e8f9f7 244 NVIC_SetPriority(Dma_IRQn, 14);
<> 144:ef7eb2e8f9f7 245 NVIC_SetPriority(Uvi_IRQn, 14);
<> 144:ef7eb2e8f9f7 246 NVIC_SetPriority(DbgPwrUp_IRQn, 14);
<> 144:ef7eb2e8f9f7 247 NVIC_SetPriority(Spi2_IRQn, 14);
<> 144:ef7eb2e8f9f7 248 NVIC_SetPriority(I2C2_IRQn, 14);
<> 144:ef7eb2e8f9f7 249 }
<> 144:ef7eb2e8f9f7 250
<> 144:ef7eb2e8f9f7 251 extern void __Vectors;
<> 144:ef7eb2e8f9f7 252
<> 144:ef7eb2e8f9f7 253 void fNcs36510Init(void)
<> 144:ef7eb2e8f9f7 254 {
<> 144:ef7eb2e8f9f7 255 /** Setting this register is helping to debug imprecise bus access faults
<> 144:ef7eb2e8f9f7 256 * making them precise bus access faults. It has an impact on application
<> 144:ef7eb2e8f9f7 257 * performance. */
<> 144:ef7eb2e8f9f7 258 // SCnSCB->ACTLR |= SCnSCB_ACTLR_DISDEFWBUF_Msk;
<> 144:ef7eb2e8f9f7 259
<> 144:ef7eb2e8f9f7 260 /** This main function implements: */
<> 144:ef7eb2e8f9f7 261 /**- Disable all interrupts */
<> 144:ef7eb2e8f9f7 262 NVIC->ICER[0] = 0x1F;
<> 144:ef7eb2e8f9f7 263
<> 144:ef7eb2e8f9f7 264 /**- Clear all Pending interrupts */
<> 144:ef7eb2e8f9f7 265 NVIC->ICPR[0] = 0x1F;
<> 144:ef7eb2e8f9f7 266
<> 144:ef7eb2e8f9f7 267 /**- Clear all pending SV and systick */
<> 144:ef7eb2e8f9f7 268 SCB->ICSR = (uint32_t)0x0A000000;
<> 144:ef7eb2e8f9f7 269 SCB->VTOR = (uint32_t) (&__Vectors);
<> 144:ef7eb2e8f9f7 270
<> 144:ef7eb2e8f9f7 271 /**- Initialize hardware */
<> 144:ef7eb2e8f9f7 272 fHwInit();
<> 144:ef7eb2e8f9f7 273 }