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targets/hal/TARGET_ONSEMI/TARGET_NCS36510/architecture.h@147:30b64687e01f, 2016-09-16 (annotated)

Committer:
<>
Date:
Fri Sep 16 16:24:25 2016 +0100
Revision:
147:30b64687e01f
Parent:
144:ef7eb2e8f9f7 
This updates the lib to the mbed lib v126

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**
<> 144:ef7eb2e8f9f7 2 ******************************************************************************
<> 144:ef7eb2e8f9f7 3 * @file architecture.h
<> 144:ef7eb2e8f9f7 4 * @brief CM3 architecture specific inclusions and defines.
<> 144:ef7eb2e8f9f7 5 * @internal
<> 144:ef7eb2e8f9f7 6 * @author ON Semiconductor
<> 144:ef7eb2e8f9f7 7 * $Rev: $
<> 144:ef7eb2e8f9f7 8 * $Date: $
<> 144:ef7eb2e8f9f7 9 ******************************************************************************
<> 147:30b64687e01f 10 * Copyright 2016 Semiconductor Components Industries LLC (d/b/a “ON Semiconductor”).
<> 147:30b64687e01f 11 * All rights reserved. This software and/or documentation is licensed by ON Semiconductor
<> 147:30b64687e01f 12 * under limited terms and conditions. The terms and conditions pertaining to the software
<> 147:30b64687e01f 13 * and/or documentation are available at http://www.onsemi.com/site/pdf/ONSEMI_T&C.pdf
<> 147:30b64687e01f 14 * (“ON Semiconductor Standard Terms and Conditions of Sale, Section 8 Software”) and
<> 147:30b64687e01f 15 * if applicable the software license agreement. Do not use this software and/or
<> 147:30b64687e01f 16 * documentation unless you have carefully read and you agree to the limited terms and
<> 147:30b64687e01f 17 * conditions. By using this software and/or documentation, you agree to the limited
<> 147:30b64687e01f 18 * terms and conditions.
<> 144:ef7eb2e8f9f7 19 *
<> 144:ef7eb2e8f9f7 20 * THIS SOFTWARE IS PROVIDED "AS IS". NO WARRANTIES, WHETHER EXPRESS, IMPLIED
<> 144:ef7eb2e8f9f7 21 * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
<> 144:ef7eb2e8f9f7 22 * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
<> 144:ef7eb2e8f9f7 23 * ON SEMICONDUCTOR SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL,
<> 144:ef7eb2e8f9f7 24 * INCIDENTAL, OR CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
<> 144:ef7eb2e8f9f7 25 * @endinternal
<> 144:ef7eb2e8f9f7 26 *
<> 144:ef7eb2e8f9f7 27 * @ingroup bsp
<> 144:ef7eb2e8f9f7 28 */
<> 144:ef7eb2e8f9f7 29
<> 144:ef7eb2e8f9f7 30 #ifndef ARCHITECTURE_H_
<> 144:ef7eb2e8f9f7 31 #define ARCHITECTURE_H_
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 /*************************************************************************************************
<> 144:ef7eb2e8f9f7 34 * *
<> 144:ef7eb2e8f9f7 35 * Header files *
<> 144:ef7eb2e8f9f7 36 * *
<> 144:ef7eb2e8f9f7 37 *************************************************************************************************/
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 //#include <ncs36510.h>
<> 144:ef7eb2e8f9f7 40 //#include <system_ncs36510.h>
<> 144:ef7eb2e8f9f7 41 //#include <core_cm3.h>
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 #include "NCS36510.h"
<> 144:ef7eb2e8f9f7 44 #include "system_NCS36510.h"
<> 144:ef7eb2e8f9f7 45 #include "core_cm3.h"
<> 144:ef7eb2e8f9f7 46 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 47
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 /*************************************************************************************************
<> 144:ef7eb2e8f9f7 50 * *
<> 144:ef7eb2e8f9f7 51 * Symbolic Constants *
<> 144:ef7eb2e8f9f7 52 * *
<> 144:ef7eb2e8f9f7 53 *************************************************************************************************/
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 /* Interrupt Control and State Register (0xE000ED04)
<> 144:ef7eb2e8f9f7 56 * 31 NMIPENDSET R/W 0 NMI pended
<> 144:ef7eb2e8f9f7 57 * 28 PENDSVSET R/W 0 Write 1 to pend system call; Read value
<> 144:ef7eb2e8f9f7 58 * indicates pending status
<> 144:ef7eb2e8f9f7 59 * 27 PENDSVCLR W 0 Write 1 to clear PendSV pending status
<> 144:ef7eb2e8f9f7 60 * 26 PENDSTSET R/W 0 Write 1 to pend Systick exception; Read
<> 144:ef7eb2e8f9f7 61 * value indicates pending status
<> 144:ef7eb2e8f9f7 62 * 25 PENDSTCLR W 0 Write 1 to clear Systick pending status
<> 144:ef7eb2e8f9f7 63 * 23 ISRPREEMPT R 0 Indicate that a pending interrupt is going
<> 144:ef7eb2e8f9f7 64 * to be active in next step (for debug)
<> 144:ef7eb2e8f9f7 65 * 22 ISRPENDING R 0 External interrupt pending (excluding
<> 144:ef7eb2e8f9f7 66 * system exceptions such as NMI for
<> 144:ef7eb2e8f9f7 67 * fault)
<> 144:ef7eb2e8f9f7 68 * 21:12 VECTPENDING R 0 Pending ISR number
<> 144:ef7eb2e8f9f7 69 * 11 RETTOBASE R 0 Set to 1 when the processor is running
<> 144:ef7eb2e8f9f7 70 * an exception handler and will return to
<> 144:ef7eb2e8f9f7 71 * thread level if interrupt return and no
<> 144:ef7eb2e8f9f7 72 * other exceptions pending
<> 144:ef7eb2e8f9f7 73 * 9:0 VECTACTIVE R 0 Current running interrupt service routine
<> 144:ef7eb2e8f9f7 74 */
<> 144:ef7eb2e8f9f7 75 #define RUNNING_IN_ISR (((SCB->ICSR & 0x3FF) > 0 ) ? 1 : 0)
<> 144:ef7eb2e8f9f7 76
<> 144:ef7eb2e8f9f7 77 #endif /* ARCHITECTURE_H_ */