schneider françois / FT800_2

Lib FT800 Modifiee

Dependents:   FT800_Lib_perso

FT_Gpu_Hal.cpp@0:7ea2f058a713, 2022-02-08 (annotated)

Committer:
schnf30
Date:
Tue Feb 08 08:17:31 2022 +0000
Revision:
0:7ea2f058a713
Librairie FT800 adaptee avec drawline, Brigntness etc...

Who changed what in which revision?

UserRevisionLine numberNew contents of line
schnf30 0:7ea2f058a713 1 /* mbed Library for FTDI FT800 Enbedded Video Engine "EVE"
schnf30 0:7ea2f058a713 2 * based on Original Code Sample from FTDI
schnf30 0:7ea2f058a713 3 * ported to mbed by Peter Drescher, DC2PD 2014
schnf30 0:7ea2f058a713 4 * Released under the MIT License: http://mbed.org/license/mit
schnf30 0:7ea2f058a713 5 * 19.09.14 changed to shorter function names
schnf30 0:7ea2f058a713 6 * FTDI was using very long names.
schnf30 0:7ea2f058a713 7 * Ft_App_Flush_Co_Buffer -> Flush_Co_Buffer ... */
schnf30 0:7ea2f058a713 8
schnf30 0:7ea2f058a713 9 #include "FT_Platform.h"
schnf30 0:7ea2f058a713 10 #include "mbed.h"
schnf30 0:7ea2f058a713 11 #include "FT_LCD_Type.h"
schnf30 0:7ea2f058a713 12
schnf30 0:7ea2f058a713 13 FT800::FT800(PinName mosi,
schnf30 0:7ea2f058a713 14 PinName miso,
schnf30 0:7ea2f058a713 15 PinName sck,
schnf30 0:7ea2f058a713 16 PinName ss,
schnf30 0:7ea2f058a713 17 PinName intr,
schnf30 0:7ea2f058a713 18 PinName pd)
schnf30 0:7ea2f058a713 19 :
schnf30 0:7ea2f058a713 20 _spi(mosi, miso, sck),
schnf30 0:7ea2f058a713 21 _ss(ss),
schnf30 0:7ea2f058a713 22 _pd(pd),
schnf30 0:7ea2f058a713 23 _f800_isr(InterruptIn(intr))
schnf30 0:7ea2f058a713 24 {
schnf30 0:7ea2f058a713 25 _spi.format(8,0); // 8 bit spi mode 0
schnf30 0:7ea2f058a713 26 _spi.frequency(2000000); // start with 10 Mhz SPI clock
schnf30 0:7ea2f058a713 27 _ss = 1; // cs high
schnf30 0:7ea2f058a713 28 _pd = 1; // PD high
schnf30 0:7ea2f058a713 29 Bootup();
schnf30 0:7ea2f058a713 30 }
schnf30 0:7ea2f058a713 31
schnf30 0:7ea2f058a713 32
schnf30 0:7ea2f058a713 33 ft_bool_t FT800::Bootup(void){
schnf30 0:7ea2f058a713 34 Open();
schnf30 0:7ea2f058a713 35 BootupConfig();
schnf30 0:7ea2f058a713 36
schnf30 0:7ea2f058a713 37 return(1);
schnf30 0:7ea2f058a713 38 }
schnf30 0:7ea2f058a713 39
schnf30 0:7ea2f058a713 40
schnf30 0:7ea2f058a713 41 ft_void_t FT800::BootupConfig(void){
schnf30 0:7ea2f058a713 42 ft_uint8_t chipid;
schnf30 0:7ea2f058a713 43 /* Do a power cycle for safer side */
schnf30 0:7ea2f058a713 44 Powercycle( FT_TRUE);
schnf30 0:7ea2f058a713 45
schnf30 0:7ea2f058a713 46 /* Access address 0 to wake up the FT800 */
schnf30 0:7ea2f058a713 47 HostCommand( FT_GPU_ACTIVE_M);
schnf30 0:7ea2f058a713 48 Sleep(20);
schnf30 0:7ea2f058a713 49
schnf30 0:7ea2f058a713 50 /* Set the clk to external clock */
schnf30 0:7ea2f058a713 51 HostCommand( FT_GPU_EXTERNAL_OSC);
schnf30 0:7ea2f058a713 52 Sleep(10);
schnf30 0:7ea2f058a713 53
schnf30 0:7ea2f058a713 54
schnf30 0:7ea2f058a713 55 /* Switch PLL output to 48MHz */
schnf30 0:7ea2f058a713 56 HostCommand( FT_GPU_PLL_48M);
schnf30 0:7ea2f058a713 57 Sleep(10);
schnf30 0:7ea2f058a713 58
schnf30 0:7ea2f058a713 59 /* Do a core reset for safer side */
schnf30 0:7ea2f058a713 60 HostCommand( FT_GPU_CORE_RESET);
schnf30 0:7ea2f058a713 61
schnf30 0:7ea2f058a713 62 //Read Register ID to check if FT800 is ready.
schnf30 0:7ea2f058a713 63 chipid = Rd8( REG_ID);
schnf30 0:7ea2f058a713 64 while(chipid != 0x7C)
schnf30 0:7ea2f058a713 65 chipid = Rd8( REG_ID);
schnf30 0:7ea2f058a713 66
schnf30 0:7ea2f058a713 67
schnf30 0:7ea2f058a713 68 // Speed up
schnf30 0:7ea2f058a713 69 _spi.frequency(20000000); // 20 Mhz SPI clock
schnf30 0:7ea2f058a713 70
schnf30 0:7ea2f058a713 71 /* Configuration of LCD display */
schnf30 0:7ea2f058a713 72 DispHCycle = my_DispHCycle;
schnf30 0:7ea2f058a713 73 Wr16( REG_HCYCLE, DispHCycle);
schnf30 0:7ea2f058a713 74 DispHOffset = my_DispHOffset;
schnf30 0:7ea2f058a713 75 Wr16( REG_HOFFSET, DispHOffset);
schnf30 0:7ea2f058a713 76 DispWidth = my_DispWidth;
schnf30 0:7ea2f058a713 77 Wr16( REG_HSIZE, DispWidth);
schnf30 0:7ea2f058a713 78 DispHSync0 = my_DispHSync0;
schnf30 0:7ea2f058a713 79 Wr16( REG_HSYNC0, DispHSync0);
schnf30 0:7ea2f058a713 80 DispHSync1 = my_DispHSync1;
schnf30 0:7ea2f058a713 81 Wr16( REG_HSYNC1, DispHSync1);
schnf30 0:7ea2f058a713 82 DispVCycle = my_DispVCycle;
schnf30 0:7ea2f058a713 83 Wr16( REG_VCYCLE, DispVCycle);
schnf30 0:7ea2f058a713 84 DispVOffset = my_DispVOffset;
schnf30 0:7ea2f058a713 85 Wr16( REG_VOFFSET, DispVOffset);
schnf30 0:7ea2f058a713 86 DispHeight = my_DispHeight;
schnf30 0:7ea2f058a713 87 Wr16( REG_VSIZE, DispHeight);
schnf30 0:7ea2f058a713 88 DispVSync0 = my_DispVSync0;
schnf30 0:7ea2f058a713 89 Wr16( REG_VSYNC0, DispVSync0);
schnf30 0:7ea2f058a713 90 DispVSync1 = my_DispVSync1;
schnf30 0:7ea2f058a713 91 Wr16( REG_VSYNC1, DispVSync1);
schnf30 0:7ea2f058a713 92 DispSwizzle = my_DispSwizzle;
schnf30 0:7ea2f058a713 93 Wr8( REG_SWIZZLE, DispSwizzle);
schnf30 0:7ea2f058a713 94 DispPCLKPol = my_DispPCLKPol;
schnf30 0:7ea2f058a713 95 Wr8( REG_PCLK_POL, DispPCLKPol);
schnf30 0:7ea2f058a713 96 Wr8( REG_CSPREAD, 1);
schnf30 0:7ea2f058a713 97 DispPCLK = my_DispPCLK;
schnf30 0:7ea2f058a713 98 Wr8( REG_PCLK, DispPCLK);//after this display is visible on the LCD
schnf30 0:7ea2f058a713 99
schnf30 0:7ea2f058a713 100 Wr16( REG_PWM_HZ, 1000);
schnf30 0:7ea2f058a713 101
schnf30 0:7ea2f058a713 102 #ifdef Inv_Backlite // turn on backlite
schnf30 0:7ea2f058a713 103 Wr16( REG_PWM_DUTY, 0);
schnf30 0:7ea2f058a713 104 #else
schnf30 0:7ea2f058a713 105 Wr16( REG_PWM_DUTY, 100);
schnf30 0:7ea2f058a713 106 #endif
schnf30 0:7ea2f058a713 107
schnf30 0:7ea2f058a713 108 Wr8( REG_GPIO_DIR,0x82); //| Rd8( REG_GPIO_DIR));
schnf30 0:7ea2f058a713 109 Wr8( REG_GPIO,0x080); //| Rd8( REG_GPIO));
schnf30 0:7ea2f058a713 110
schnf30 0:7ea2f058a713 111 Wr32( RAM_DL, CLEAR(1,1,1));
schnf30 0:7ea2f058a713 112 Wr32( RAM_DL+4, DISPLAY());
schnf30 0:7ea2f058a713 113 Wr32( REG_DLSWAP,1);
schnf30 0:7ea2f058a713 114
schnf30 0:7ea2f058a713 115 Wr16( REG_PCLK, DispPCLK);
schnf30 0:7ea2f058a713 116
schnf30 0:7ea2f058a713 117 /* Touch configuration - configure the resistance value to 1200 - this value is specific to customer requirement and derived by experiment */
schnf30 0:7ea2f058a713 118 Wr16( REG_TOUCH_RZTHRESH,1200);
schnf30 0:7ea2f058a713 119
schnf30 0:7ea2f058a713 120 }
schnf30 0:7ea2f058a713 121
schnf30 0:7ea2f058a713 122
schnf30 0:7ea2f058a713 123
schnf30 0:7ea2f058a713 124 /* API to initialize the SPI interface */
schnf30 0:7ea2f058a713 125 ft_bool_t FT800::Init()
schnf30 0:7ea2f058a713 126 {
schnf30 0:7ea2f058a713 127 // is done in constructor
schnf30 0:7ea2f058a713 128 return 1;
schnf30 0:7ea2f058a713 129 }
schnf30 0:7ea2f058a713 130
schnf30 0:7ea2f058a713 131
schnf30 0:7ea2f058a713 132 ft_bool_t FT800::Open()
schnf30 0:7ea2f058a713 133 {
schnf30 0:7ea2f058a713 134 cmd_fifo_wp = dl_buff_wp = 0;
schnf30 0:7ea2f058a713 135 status = OPENED;
schnf30 0:7ea2f058a713 136 return 1;
schnf30 0:7ea2f058a713 137 }
schnf30 0:7ea2f058a713 138
schnf30 0:7ea2f058a713 139 ft_void_t FT800::Close( )
schnf30 0:7ea2f058a713 140 {
schnf30 0:7ea2f058a713 141 status = CLOSED;
schnf30 0:7ea2f058a713 142 }
schnf30 0:7ea2f058a713 143
schnf30 0:7ea2f058a713 144 ft_void_t FT800::DeInit()
schnf30 0:7ea2f058a713 145 {
schnf30 0:7ea2f058a713 146
schnf30 0:7ea2f058a713 147 }
schnf30 0:7ea2f058a713 148
schnf30 0:7ea2f058a713 149 /*The APIs for reading/writing transfer continuously only with small buffer system*/
schnf30 0:7ea2f058a713 150 ft_void_t FT800::StartTransfer( FT_GPU_TRANSFERDIR_T rw,ft_uint32_t addr)
schnf30 0:7ea2f058a713 151 {
schnf30 0:7ea2f058a713 152 if (FT_GPU_READ == rw){
schnf30 0:7ea2f058a713 153 _ss = 0; // cs low
schnf30 0:7ea2f058a713 154 _spi.write(addr >> 16);
schnf30 0:7ea2f058a713 155 _spi.write(addr >> 8);
schnf30 0:7ea2f058a713 156 _spi.write(addr & 0xff);
schnf30 0:7ea2f058a713 157 _spi.write(0); //Dummy Read Byte
schnf30 0:7ea2f058a713 158 status = READING;
schnf30 0:7ea2f058a713 159 }else{
schnf30 0:7ea2f058a713 160 _ss = 0; // cs low
schnf30 0:7ea2f058a713 161 _spi.write(0x80 | (addr >> 16));
schnf30 0:7ea2f058a713 162 _spi.write(addr >> 8);
schnf30 0:7ea2f058a713 163 _spi.write(addr & 0xff);
schnf30 0:7ea2f058a713 164 status = WRITING;
schnf30 0:7ea2f058a713 165 }
schnf30 0:7ea2f058a713 166 }
schnf30 0:7ea2f058a713 167
schnf30 0:7ea2f058a713 168
schnf30 0:7ea2f058a713 169 /*The APIs for writing transfer continuously only*/
schnf30 0:7ea2f058a713 170 ft_void_t FT800::StartCmdTransfer( FT_GPU_TRANSFERDIR_T rw, ft_uint16_t count)
schnf30 0:7ea2f058a713 171 {
schnf30 0:7ea2f058a713 172 StartTransfer( rw, cmd_fifo_wp + RAM_CMD);
schnf30 0:7ea2f058a713 173 }
schnf30 0:7ea2f058a713 174
schnf30 0:7ea2f058a713 175 ft_uint8_t FT800::TransferString( const ft_char8_t *string)
schnf30 0:7ea2f058a713 176 {
schnf30 0:7ea2f058a713 177 ft_uint16_t length = strlen(string);
schnf30 0:7ea2f058a713 178 while(length --){
schnf30 0:7ea2f058a713 179 Transfer8( *string);
schnf30 0:7ea2f058a713 180 string ++;
schnf30 0:7ea2f058a713 181 }
schnf30 0:7ea2f058a713 182 //Append one null as ending flag
schnf30 0:7ea2f058a713 183 Transfer8( 0);
schnf30 0:7ea2f058a713 184 return(1);
schnf30 0:7ea2f058a713 185 }
schnf30 0:7ea2f058a713 186
schnf30 0:7ea2f058a713 187
schnf30 0:7ea2f058a713 188 ft_uint8_t FT800::Transfer8( ft_uint8_t value)
schnf30 0:7ea2f058a713 189 {
schnf30 0:7ea2f058a713 190 return _spi.write(value);
schnf30 0:7ea2f058a713 191 }
schnf30 0:7ea2f058a713 192
schnf30 0:7ea2f058a713 193
schnf30 0:7ea2f058a713 194 ft_uint16_t FT800::Transfer16( ft_uint16_t value)
schnf30 0:7ea2f058a713 195 {
schnf30 0:7ea2f058a713 196 ft_uint16_t retVal = 0;
schnf30 0:7ea2f058a713 197
schnf30 0:7ea2f058a713 198 if (status == WRITING){
schnf30 0:7ea2f058a713 199 Transfer8( value & 0xFF);//LSB first
schnf30 0:7ea2f058a713 200 Transfer8( (value >> 8) & 0xFF);
schnf30 0:7ea2f058a713 201 }else{
schnf30 0:7ea2f058a713 202 retVal = Transfer8( 0);
schnf30 0:7ea2f058a713 203 retVal |= (ft_uint16_t)Transfer8( 0) << 8;
schnf30 0:7ea2f058a713 204 }
schnf30 0:7ea2f058a713 205
schnf30 0:7ea2f058a713 206 return retVal;
schnf30 0:7ea2f058a713 207 }
schnf30 0:7ea2f058a713 208
schnf30 0:7ea2f058a713 209 ft_uint32_t FT800::Transfer32( ft_uint32_t value)
schnf30 0:7ea2f058a713 210 {
schnf30 0:7ea2f058a713 211 ft_uint32_t retVal = 0;
schnf30 0:7ea2f058a713 212 if (status == WRITING){
schnf30 0:7ea2f058a713 213 Transfer16( value & 0xFFFF);//LSB first
schnf30 0:7ea2f058a713 214 Transfer16( (value >> 16) & 0xFFFF);
schnf30 0:7ea2f058a713 215 }else{
schnf30 0:7ea2f058a713 216 retVal = Transfer16( 0);
schnf30 0:7ea2f058a713 217 retVal |= (ft_uint32_t)Transfer16( 0) << 16;
schnf30 0:7ea2f058a713 218 }
schnf30 0:7ea2f058a713 219 return retVal;
schnf30 0:7ea2f058a713 220 }
schnf30 0:7ea2f058a713 221
schnf30 0:7ea2f058a713 222 ft_void_t FT800::EndTransfer( )
schnf30 0:7ea2f058a713 223 {
schnf30 0:7ea2f058a713 224 _ss = 1;
schnf30 0:7ea2f058a713 225 status = OPENED;
schnf30 0:7ea2f058a713 226 }
schnf30 0:7ea2f058a713 227
schnf30 0:7ea2f058a713 228
schnf30 0:7ea2f058a713 229 ft_uint8_t FT800::Rd8( ft_uint32_t addr)
schnf30 0:7ea2f058a713 230 {
schnf30 0:7ea2f058a713 231 ft_uint8_t value;
schnf30 0:7ea2f058a713 232 StartTransfer( FT_GPU_READ,addr);
schnf30 0:7ea2f058a713 233 value = Transfer8( 0);
schnf30 0:7ea2f058a713 234 EndTransfer( );
schnf30 0:7ea2f058a713 235 return value;
schnf30 0:7ea2f058a713 236 }
schnf30 0:7ea2f058a713 237 ft_uint16_t FT800::Rd16( ft_uint32_t addr)
schnf30 0:7ea2f058a713 238 {
schnf30 0:7ea2f058a713 239 ft_uint16_t value;
schnf30 0:7ea2f058a713 240 StartTransfer( FT_GPU_READ,addr);
schnf30 0:7ea2f058a713 241 value = Transfer16( 0);
schnf30 0:7ea2f058a713 242 EndTransfer( );
schnf30 0:7ea2f058a713 243 return value;
schnf30 0:7ea2f058a713 244 }
schnf30 0:7ea2f058a713 245 ft_uint32_t FT800::Rd32( ft_uint32_t addr)
schnf30 0:7ea2f058a713 246 {
schnf30 0:7ea2f058a713 247 ft_uint32_t value;
schnf30 0:7ea2f058a713 248 StartTransfer( FT_GPU_READ,addr);
schnf30 0:7ea2f058a713 249 value = Transfer32( 0);
schnf30 0:7ea2f058a713 250 EndTransfer( );
schnf30 0:7ea2f058a713 251 return value;
schnf30 0:7ea2f058a713 252 }
schnf30 0:7ea2f058a713 253
schnf30 0:7ea2f058a713 254 ft_void_t FT800::Wr8( ft_uint32_t addr, ft_uint8_t v)
schnf30 0:7ea2f058a713 255 {
schnf30 0:7ea2f058a713 256 StartTransfer( FT_GPU_WRITE,addr);
schnf30 0:7ea2f058a713 257 Transfer8( v);
schnf30 0:7ea2f058a713 258 EndTransfer( );
schnf30 0:7ea2f058a713 259 }
schnf30 0:7ea2f058a713 260 ft_void_t FT800::Wr16( ft_uint32_t addr, ft_uint16_t v)
schnf30 0:7ea2f058a713 261 {
schnf30 0:7ea2f058a713 262 StartTransfer( FT_GPU_WRITE,addr);
schnf30 0:7ea2f058a713 263 Transfer16( v);
schnf30 0:7ea2f058a713 264 EndTransfer( );
schnf30 0:7ea2f058a713 265 }
schnf30 0:7ea2f058a713 266 ft_void_t FT800::Wr32( ft_uint32_t addr, ft_uint32_t v)
schnf30 0:7ea2f058a713 267 {
schnf30 0:7ea2f058a713 268 StartTransfer( FT_GPU_WRITE,addr);
schnf30 0:7ea2f058a713 269 Transfer32( v);
schnf30 0:7ea2f058a713 270 EndTransfer( );
schnf30 0:7ea2f058a713 271 }
schnf30 0:7ea2f058a713 272
schnf30 0:7ea2f058a713 273 ft_void_t FT800::HostCommand( ft_uint8_t cmd)
schnf30 0:7ea2f058a713 274 {
schnf30 0:7ea2f058a713 275 _ss = 0;
schnf30 0:7ea2f058a713 276 _spi.write(cmd);
schnf30 0:7ea2f058a713 277 _spi.write(0);
schnf30 0:7ea2f058a713 278 _spi.write(0);
schnf30 0:7ea2f058a713 279 _ss = 1;
schnf30 0:7ea2f058a713 280 }
schnf30 0:7ea2f058a713 281
schnf30 0:7ea2f058a713 282 ft_void_t FT800::ClockSelect( FT_GPU_PLL_SOURCE_T pllsource)
schnf30 0:7ea2f058a713 283 {
schnf30 0:7ea2f058a713 284 HostCommand( pllsource);
schnf30 0:7ea2f058a713 285 }
schnf30 0:7ea2f058a713 286
schnf30 0:7ea2f058a713 287 ft_void_t FT800::PLL_FreqSelect( FT_GPU_PLL_FREQ_T freq)
schnf30 0:7ea2f058a713 288 {
schnf30 0:7ea2f058a713 289 HostCommand( freq);
schnf30 0:7ea2f058a713 290 }
schnf30 0:7ea2f058a713 291
schnf30 0:7ea2f058a713 292 ft_void_t FT800::PowerModeSwitch( FT_GPU_POWER_MODE_T pwrmode)
schnf30 0:7ea2f058a713 293 {
schnf30 0:7ea2f058a713 294 HostCommand( pwrmode);
schnf30 0:7ea2f058a713 295 }
schnf30 0:7ea2f058a713 296
schnf30 0:7ea2f058a713 297 ft_void_t FT800::CoreReset( )
schnf30 0:7ea2f058a713 298 {
schnf30 0:7ea2f058a713 299 HostCommand( 0x68);
schnf30 0:7ea2f058a713 300 }
schnf30 0:7ea2f058a713 301
schnf30 0:7ea2f058a713 302
schnf30 0:7ea2f058a713 303 ft_void_t FT800::Updatecmdfifo( ft_uint16_t count)
schnf30 0:7ea2f058a713 304 {
schnf30 0:7ea2f058a713 305 cmd_fifo_wp = ( cmd_fifo_wp + count) & 4095;
schnf30 0:7ea2f058a713 306 //4 byte alignment
schnf30 0:7ea2f058a713 307 cmd_fifo_wp = ( cmd_fifo_wp + 3) & 0xffc;
schnf30 0:7ea2f058a713 308 Wr16( REG_CMD_WRITE, cmd_fifo_wp);
schnf30 0:7ea2f058a713 309 }
schnf30 0:7ea2f058a713 310
schnf30 0:7ea2f058a713 311
schnf30 0:7ea2f058a713 312 ft_uint16_t FT800::fifo_Freespace( )
schnf30 0:7ea2f058a713 313 {
schnf30 0:7ea2f058a713 314 ft_uint16_t fullness,retval;
schnf30 0:7ea2f058a713 315
schnf30 0:7ea2f058a713 316 fullness = ( cmd_fifo_wp - Rd16( REG_CMD_READ)) & 4095;
schnf30 0:7ea2f058a713 317 retval = (FT_CMD_FIFO_SIZE - 4) - fullness;
schnf30 0:7ea2f058a713 318 return (retval);
schnf30 0:7ea2f058a713 319 }
schnf30 0:7ea2f058a713 320
schnf30 0:7ea2f058a713 321 ft_void_t FT800::WrCmdBuf( ft_uint8_t *buffer,ft_uint16_t count)
schnf30 0:7ea2f058a713 322 {
schnf30 0:7ea2f058a713 323 ft_uint32_t length =0, SizeTransfered = 0;
schnf30 0:7ea2f058a713 324
schnf30 0:7ea2f058a713 325 #define MAX_CMD_FIFO_TRANSFER fifo_Freespace( )
schnf30 0:7ea2f058a713 326 do {
schnf30 0:7ea2f058a713 327 length = count;
schnf30 0:7ea2f058a713 328 if (length > MAX_CMD_FIFO_TRANSFER){
schnf30 0:7ea2f058a713 329 length = MAX_CMD_FIFO_TRANSFER;
schnf30 0:7ea2f058a713 330 }
schnf30 0:7ea2f058a713 331 CheckCmdBuffer( length);
schnf30 0:7ea2f058a713 332
schnf30 0:7ea2f058a713 333 StartCmdTransfer( FT_GPU_WRITE,length);
schnf30 0:7ea2f058a713 334
schnf30 0:7ea2f058a713 335 SizeTransfered = 0;
schnf30 0:7ea2f058a713 336 while (length--) {
schnf30 0:7ea2f058a713 337 Transfer8( *buffer);
schnf30 0:7ea2f058a713 338 buffer++;
schnf30 0:7ea2f058a713 339 SizeTransfered ++;
schnf30 0:7ea2f058a713 340 }
schnf30 0:7ea2f058a713 341 length = SizeTransfered;
schnf30 0:7ea2f058a713 342
schnf30 0:7ea2f058a713 343 EndTransfer( );
schnf30 0:7ea2f058a713 344 Updatecmdfifo( length);
schnf30 0:7ea2f058a713 345
schnf30 0:7ea2f058a713 346 WaitCmdfifo_empty( );
schnf30 0:7ea2f058a713 347
schnf30 0:7ea2f058a713 348 count -= length;
schnf30 0:7ea2f058a713 349 }while (count > 0);
schnf30 0:7ea2f058a713 350 }
schnf30 0:7ea2f058a713 351
schnf30 0:7ea2f058a713 352
schnf30 0:7ea2f058a713 353 ft_void_t FT800::WrCmdBufFromFlash( FT_PROGMEM ft_prog_uchar8_t *buffer,ft_uint16_t count)
schnf30 0:7ea2f058a713 354 {
schnf30 0:7ea2f058a713 355 ft_uint32_t length =0, SizeTransfered = 0;
schnf30 0:7ea2f058a713 356
schnf30 0:7ea2f058a713 357 #define MAX_CMD_FIFO_TRANSFER fifo_Freespace( )
schnf30 0:7ea2f058a713 358 do {
schnf30 0:7ea2f058a713 359 length = count;
schnf30 0:7ea2f058a713 360 if (length > MAX_CMD_FIFO_TRANSFER){
schnf30 0:7ea2f058a713 361 length = MAX_CMD_FIFO_TRANSFER;
schnf30 0:7ea2f058a713 362 }
schnf30 0:7ea2f058a713 363 CheckCmdBuffer( length);
schnf30 0:7ea2f058a713 364
schnf30 0:7ea2f058a713 365 StartCmdTransfer( FT_GPU_WRITE,length);
schnf30 0:7ea2f058a713 366
schnf30 0:7ea2f058a713 367
schnf30 0:7ea2f058a713 368 SizeTransfered = 0;
schnf30 0:7ea2f058a713 369 while (length--) {
schnf30 0:7ea2f058a713 370 Transfer8( ft_pgm_read_byte_near(buffer));
schnf30 0:7ea2f058a713 371 buffer++;
schnf30 0:7ea2f058a713 372 SizeTransfered ++;
schnf30 0:7ea2f058a713 373 }
schnf30 0:7ea2f058a713 374 length = SizeTransfered;
schnf30 0:7ea2f058a713 375
schnf30 0:7ea2f058a713 376 EndTransfer( );
schnf30 0:7ea2f058a713 377 Updatecmdfifo( length);
schnf30 0:7ea2f058a713 378
schnf30 0:7ea2f058a713 379 WaitCmdfifo_empty( );
schnf30 0:7ea2f058a713 380
schnf30 0:7ea2f058a713 381 count -= length;
schnf30 0:7ea2f058a713 382 }while (count > 0);
schnf30 0:7ea2f058a713 383 }
schnf30 0:7ea2f058a713 384
schnf30 0:7ea2f058a713 385
schnf30 0:7ea2f058a713 386 ft_void_t FT800::CheckCmdBuffer( ft_uint16_t count)
schnf30 0:7ea2f058a713 387 {
schnf30 0:7ea2f058a713 388 ft_uint16_t getfreespace;
schnf30 0:7ea2f058a713 389 do{
schnf30 0:7ea2f058a713 390 getfreespace = fifo_Freespace( );
schnf30 0:7ea2f058a713 391 }while(getfreespace < count);
schnf30 0:7ea2f058a713 392 }
schnf30 0:7ea2f058a713 393
schnf30 0:7ea2f058a713 394 ft_void_t FT800::WaitCmdfifo_empty( )
schnf30 0:7ea2f058a713 395 {
schnf30 0:7ea2f058a713 396 while(Rd16( REG_CMD_READ) != Rd16( REG_CMD_WRITE));
schnf30 0:7ea2f058a713 397
schnf30 0:7ea2f058a713 398 cmd_fifo_wp = Rd16( REG_CMD_WRITE);
schnf30 0:7ea2f058a713 399 }
schnf30 0:7ea2f058a713 400
schnf30 0:7ea2f058a713 401 ft_void_t FT800::WaitLogo_Finish( )
schnf30 0:7ea2f058a713 402 {
schnf30 0:7ea2f058a713 403 ft_int16_t cmdrdptr,cmdwrptr;
schnf30 0:7ea2f058a713 404
schnf30 0:7ea2f058a713 405 do{
schnf30 0:7ea2f058a713 406 cmdrdptr = Rd16( REG_CMD_READ);
schnf30 0:7ea2f058a713 407 cmdwrptr = Rd16( REG_CMD_WRITE);
schnf30 0:7ea2f058a713 408 }while ((cmdwrptr != cmdrdptr) || (cmdrdptr != 0));
schnf30 0:7ea2f058a713 409 cmd_fifo_wp = 0;
schnf30 0:7ea2f058a713 410 }
schnf30 0:7ea2f058a713 411
schnf30 0:7ea2f058a713 412
schnf30 0:7ea2f058a713 413 ft_void_t FT800::ResetCmdFifo( )
schnf30 0:7ea2f058a713 414 {
schnf30 0:7ea2f058a713 415 cmd_fifo_wp = 0;
schnf30 0:7ea2f058a713 416 }
schnf30 0:7ea2f058a713 417
schnf30 0:7ea2f058a713 418
schnf30 0:7ea2f058a713 419 ft_void_t FT800::WrCmd32( ft_uint32_t cmd)
schnf30 0:7ea2f058a713 420 {
schnf30 0:7ea2f058a713 421 CheckCmdBuffer( sizeof(cmd));
schnf30 0:7ea2f058a713 422
schnf30 0:7ea2f058a713 423 Wr32( RAM_CMD + cmd_fifo_wp,cmd);
schnf30 0:7ea2f058a713 424
schnf30 0:7ea2f058a713 425 Updatecmdfifo( sizeof(cmd));
schnf30 0:7ea2f058a713 426 }
schnf30 0:7ea2f058a713 427
schnf30 0:7ea2f058a713 428
schnf30 0:7ea2f058a713 429 ft_void_t FT800::ResetDLBuffer( )
schnf30 0:7ea2f058a713 430 {
schnf30 0:7ea2f058a713 431 dl_buff_wp = 0;
schnf30 0:7ea2f058a713 432 }
schnf30 0:7ea2f058a713 433
schnf30 0:7ea2f058a713 434 /* Toggle PD_N pin of FT800 board for a power cycle*/
schnf30 0:7ea2f058a713 435 ft_void_t FT800::Powercycle( ft_bool_t up)
schnf30 0:7ea2f058a713 436 {
schnf30 0:7ea2f058a713 437 if (up)
schnf30 0:7ea2f058a713 438 {
schnf30 0:7ea2f058a713 439 //Toggle PD_N from low to high for power up switch
schnf30 0:7ea2f058a713 440 _pd = 0;
schnf30 0:7ea2f058a713 441 Sleep(20);
schnf30 0:7ea2f058a713 442
schnf30 0:7ea2f058a713 443 _pd = 1;
schnf30 0:7ea2f058a713 444 Sleep(20);
schnf30 0:7ea2f058a713 445 }else
schnf30 0:7ea2f058a713 446 {
schnf30 0:7ea2f058a713 447 //Toggle PD_N from high to low for power down switch
schnf30 0:7ea2f058a713 448 _pd = 1;
schnf30 0:7ea2f058a713 449 Sleep(20);
schnf30 0:7ea2f058a713 450
schnf30 0:7ea2f058a713 451 _pd = 0;
schnf30 0:7ea2f058a713 452 Sleep(20);
schnf30 0:7ea2f058a713 453 }
schnf30 0:7ea2f058a713 454 }
schnf30 0:7ea2f058a713 455
schnf30 0:7ea2f058a713 456 ft_void_t FT800::WrMemFromFlash( ft_uint32_t addr,const ft_prog_uchar8_t *buffer, ft_uint32_t length)
schnf30 0:7ea2f058a713 457 {
schnf30 0:7ea2f058a713 458 //ft_uint32_t SizeTransfered = 0;
schnf30 0:7ea2f058a713 459
schnf30 0:7ea2f058a713 460 StartTransfer( FT_GPU_WRITE,addr);
schnf30 0:7ea2f058a713 461
schnf30 0:7ea2f058a713 462 while (length--) {
schnf30 0:7ea2f058a713 463 Transfer8( ft_pgm_read_byte_near(buffer));
schnf30 0:7ea2f058a713 464 buffer++;
schnf30 0:7ea2f058a713 465 }
schnf30 0:7ea2f058a713 466
schnf30 0:7ea2f058a713 467 EndTransfer( );
schnf30 0:7ea2f058a713 468 }
schnf30 0:7ea2f058a713 469
schnf30 0:7ea2f058a713 470 ft_void_t FT800::WrMem( ft_uint32_t addr,const ft_uint8_t *buffer, ft_uint32_t length)
schnf30 0:7ea2f058a713 471 {
schnf30 0:7ea2f058a713 472 //ft_uint32_t SizeTransfered = 0;
schnf30 0:7ea2f058a713 473
schnf30 0:7ea2f058a713 474 StartTransfer( FT_GPU_WRITE,addr);
schnf30 0:7ea2f058a713 475
schnf30 0:7ea2f058a713 476 while (length--) {
schnf30 0:7ea2f058a713 477 Transfer8( *buffer);
schnf30 0:7ea2f058a713 478 buffer++;
schnf30 0:7ea2f058a713 479 }
schnf30 0:7ea2f058a713 480
schnf30 0:7ea2f058a713 481 EndTransfer( );
schnf30 0:7ea2f058a713 482 }
schnf30 0:7ea2f058a713 483
schnf30 0:7ea2f058a713 484
schnf30 0:7ea2f058a713 485 ft_void_t FT800::RdMem( ft_uint32_t addr, ft_uint8_t *buffer, ft_uint32_t length)
schnf30 0:7ea2f058a713 486 {
schnf30 0:7ea2f058a713 487 //ft_uint32_t SizeTransfered = 0;
schnf30 0:7ea2f058a713 488
schnf30 0:7ea2f058a713 489 StartTransfer( FT_GPU_READ,addr);
schnf30 0:7ea2f058a713 490
schnf30 0:7ea2f058a713 491 while (length--) {
schnf30 0:7ea2f058a713 492 *buffer = Transfer8( 0);
schnf30 0:7ea2f058a713 493 buffer++;
schnf30 0:7ea2f058a713 494 }
schnf30 0:7ea2f058a713 495
schnf30 0:7ea2f058a713 496 EndTransfer( );
schnf30 0:7ea2f058a713 497 }
schnf30 0:7ea2f058a713 498
schnf30 0:7ea2f058a713 499 ft_int32_t FT800::Dec2Ascii(ft_char8_t *pSrc,ft_int32_t value)
schnf30 0:7ea2f058a713 500 {
schnf30 0:7ea2f058a713 501 ft_int16_t Length;
schnf30 0:7ea2f058a713 502 ft_char8_t *pdst,charval;
schnf30 0:7ea2f058a713 503 ft_int32_t CurrVal = value,tmpval,i;
schnf30 0:7ea2f058a713 504 ft_char8_t tmparray[16],idx = 0;
schnf30 0:7ea2f058a713 505
schnf30 0:7ea2f058a713 506 Length = strlen(pSrc);
schnf30 0:7ea2f058a713 507 pdst = pSrc + Length;
schnf30 0:7ea2f058a713 508
schnf30 0:7ea2f058a713 509 if(0 == value)
schnf30 0:7ea2f058a713 510 {
schnf30 0:7ea2f058a713 511 *pdst++ = '0';
schnf30 0:7ea2f058a713 512 *pdst++ = '\0';
schnf30 0:7ea2f058a713 513 return 0;
schnf30 0:7ea2f058a713 514 }
schnf30 0:7ea2f058a713 515
schnf30 0:7ea2f058a713 516 if(CurrVal < 0)
schnf30 0:7ea2f058a713 517 {
schnf30 0:7ea2f058a713 518 *pdst++ = '-';
schnf30 0:7ea2f058a713 519 CurrVal = - CurrVal;
schnf30 0:7ea2f058a713 520 }
schnf30 0:7ea2f058a713 521 /* insert the value */
schnf30 0:7ea2f058a713 522 while(CurrVal > 0){
schnf30 0:7ea2f058a713 523 tmpval = CurrVal;
schnf30 0:7ea2f058a713 524 CurrVal /= 10;
schnf30 0:7ea2f058a713 525 tmpval = tmpval - CurrVal*10;
schnf30 0:7ea2f058a713 526 charval = '0' + tmpval;
schnf30 0:7ea2f058a713 527 tmparray[idx++] = charval;
schnf30 0:7ea2f058a713 528 }
schnf30 0:7ea2f058a713 529
schnf30 0:7ea2f058a713 530 for(i=0;i<idx;i++)
schnf30 0:7ea2f058a713 531 {
schnf30 0:7ea2f058a713 532 *pdst++ = tmparray[idx - i - 1];
schnf30 0:7ea2f058a713 533 }
schnf30 0:7ea2f058a713 534 *pdst++ = '\0';
schnf30 0:7ea2f058a713 535
schnf30 0:7ea2f058a713 536 return 0;
schnf30 0:7ea2f058a713 537 }
schnf30 0:7ea2f058a713 538
schnf30 0:7ea2f058a713 539
schnf30 0:7ea2f058a713 540 ft_void_t FT800::Sleep(ft_uint16_t ms)
schnf30 0:7ea2f058a713 541 {
schnf30 0:7ea2f058a713 542 wait_ms(ms);
schnf30 0:7ea2f058a713 543 }
schnf30 0:7ea2f058a713 544
schnf30 0:7ea2f058a713 545 ft_void_t FT800::Sound_ON(){
schnf30 0:7ea2f058a713 546 Wr8( REG_GPIO, 0x02 | Rd8( REG_GPIO));
schnf30 0:7ea2f058a713 547 }
schnf30 0:7ea2f058a713 548
schnf30 0:7ea2f058a713 549 ft_void_t FT800::Sound_OFF(){
schnf30 0:7ea2f058a713 550 Wr8( REG_GPIO, 0xFD & Rd8( REG_GPIO));
schnf30 0:7ea2f058a713 551 }
schnf30 0:7ea2f058a713 552
schnf30 0:7ea2f058a713 553
schnf30 0:7ea2f058a713 554
schnf30 0:7ea2f058a713 555
schnf30 0:7ea2f058a713 556