eeprom adding
Fork of SEEED_CAN by
seeed_can_defs.h@2:fd026fcfde94, 2013-11-12 (annotated)
- Committer:
- Just4pLeisure
- Date:
- Tue Nov 12 20:54:16 2013 +0000
- Revision:
- 2:fd026fcfde94
- Parent:
- 1:ad71faa09868
Updated 12-11-2013 - attach functions are now usable. Changes to allow the the library to be used with more mbeds (e.g. LPC1768). I have also added new functions/methods which give more information about errors and interrupts.
Who changed what in which revision?
User | Revision | Line number | New contents of line |
---|---|---|---|
Just4pLeisure | 0:f5d099885d3d | 1 | /* seeed_can_defs.h |
Just4pLeisure | 0:f5d099885d3d | 2 | * Copyright (c) 2013 Sophie Dexter |
Just4pLeisure | 0:f5d099885d3d | 3 | * |
Just4pLeisure | 0:f5d099885d3d | 4 | * Licensed under the Apache License, Version 2.0 (the "License"); |
Just4pLeisure | 0:f5d099885d3d | 5 | * you may not use this file except in compliance with the License. |
Just4pLeisure | 0:f5d099885d3d | 6 | * You may obtain a copy of the License at |
Just4pLeisure | 0:f5d099885d3d | 7 | * |
Just4pLeisure | 0:f5d099885d3d | 8 | * http://www.apache.org/licenses/LICENSE-2.0 |
Just4pLeisure | 0:f5d099885d3d | 9 | * |
Just4pLeisure | 0:f5d099885d3d | 10 | * Unless required by applicable law or agreed to in writing, software |
Just4pLeisure | 0:f5d099885d3d | 11 | * distributed under the License is distributed on an "AS IS" BASIS, |
Just4pLeisure | 0:f5d099885d3d | 12 | * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. |
Just4pLeisure | 0:f5d099885d3d | 13 | * See the License for the specific language governing permissions and |
Just4pLeisure | 0:f5d099885d3d | 14 | * limitations under the License. |
Just4pLeisure | 0:f5d099885d3d | 15 | */ |
Just4pLeisure | 0:f5d099885d3d | 16 | #ifndef SEEED_CAN_DEFS_H |
Just4pLeisure | 0:f5d099885d3d | 17 | #define SEEED_CAN_DEFS_H |
Just4pLeisure | 0:f5d099885d3d | 18 | |
Just4pLeisure | 0:f5d099885d3d | 19 | #include "mbed.h" |
Just4pLeisure | 0:f5d099885d3d | 20 | |
Just4pLeisure | 0:f5d099885d3d | 21 | #ifdef __cplusplus |
Just4pLeisure | 0:f5d099885d3d | 22 | extern "C" { |
Just4pLeisure | 0:f5d099885d3d | 23 | #endif |
Just4pLeisure | 0:f5d099885d3d | 24 | |
Just4pLeisure | 0:f5d099885d3d | 25 | /** FRDM-KL25Z port pins used by Seeed Studios CAN-BUS Shield |
Just4pLeisure | 0:f5d099885d3d | 26 | */ |
Just4pLeisure | 1:ad71faa09868 | 27 | #define SEEED_CAN_CS PTD0 |
Just4pLeisure | 1:ad71faa09868 | 28 | #define SEEED_CAN_CLK PTD1 |
Just4pLeisure | 0:f5d099885d3d | 29 | #define SEEED_CAN_MOSI PTD2 |
Just4pLeisure | 0:f5d099885d3d | 30 | #define SEEED_CAN_MISO PTD3 |
Just4pLeisure | 1:ad71faa09868 | 31 | #define SEEED_CAN_IRQ PTD4 |
Just4pLeisure | 0:f5d099885d3d | 32 | #define SEEED_CAN_IO9 PTD5 |
Just4pLeisure | 0:f5d099885d3d | 33 | /** Define MCP2515 register addresses |
Just4pLeisure | 0:f5d099885d3d | 34 | */ |
Just4pLeisure | 0:f5d099885d3d | 35 | #define MCP_RXF0SIDH 0x00 |
Just4pLeisure | 0:f5d099885d3d | 36 | #define MCP_RXF0SIDL 0x01 |
Just4pLeisure | 0:f5d099885d3d | 37 | #define MCP_RXF0EID8 0x02 |
Just4pLeisure | 0:f5d099885d3d | 38 | #define MCP_RXF0EID0 0x03 |
Just4pLeisure | 0:f5d099885d3d | 39 | #define MCP_RXF1SIDH 0x04 |
Just4pLeisure | 0:f5d099885d3d | 40 | #define MCP_RXF1SIDL 0x05 |
Just4pLeisure | 0:f5d099885d3d | 41 | #define MCP_RXF1EID8 0x06 |
Just4pLeisure | 0:f5d099885d3d | 42 | #define MCP_RXF1EID0 0x07 |
Just4pLeisure | 0:f5d099885d3d | 43 | #define MCP_RXF2SIDH 0x08 |
Just4pLeisure | 0:f5d099885d3d | 44 | #define MCP_RXF2SIDL 0x09 |
Just4pLeisure | 0:f5d099885d3d | 45 | #define MCP_RXF2EID8 0x0A |
Just4pLeisure | 0:f5d099885d3d | 46 | #define MCP_RXF2EID0 0x0B |
Just4pLeisure | 0:f5d099885d3d | 47 | #define MCP_CANSTAT 0x0E |
Just4pLeisure | 0:f5d099885d3d | 48 | #define MCP_CANCTRL 0x0F |
Just4pLeisure | 0:f5d099885d3d | 49 | #define MCP_RXF3SIDH 0x10 |
Just4pLeisure | 0:f5d099885d3d | 50 | #define MCP_RXF3SIDL 0x11 |
Just4pLeisure | 0:f5d099885d3d | 51 | #define MCP_RXF3EID8 0x12 |
Just4pLeisure | 0:f5d099885d3d | 52 | #define MCP_RXF3EID0 0x13 |
Just4pLeisure | 0:f5d099885d3d | 53 | #define MCP_RXF4SIDH 0x14 |
Just4pLeisure | 0:f5d099885d3d | 54 | #define MCP_RXF4SIDL 0x15 |
Just4pLeisure | 0:f5d099885d3d | 55 | #define MCP_RXF4EID8 0x16 |
Just4pLeisure | 0:f5d099885d3d | 56 | #define MCP_RXF4EID0 0x17 |
Just4pLeisure | 0:f5d099885d3d | 57 | #define MCP_RXF5SIDH 0x18 |
Just4pLeisure | 0:f5d099885d3d | 58 | #define MCP_RXF5SIDL 0x19 |
Just4pLeisure | 0:f5d099885d3d | 59 | #define MCP_RXF5EID8 0x1A |
Just4pLeisure | 0:f5d099885d3d | 60 | #define MCP_RXF5EID0 0x1B |
Just4pLeisure | 0:f5d099885d3d | 61 | #define MCP_TEC 0x1C |
Just4pLeisure | 0:f5d099885d3d | 62 | #define MCP_REC 0x1D |
Just4pLeisure | 0:f5d099885d3d | 63 | #define MCP_RXM0SIDH 0x20 |
Just4pLeisure | 0:f5d099885d3d | 64 | #define MCP_RXM0SIDL 0x21 |
Just4pLeisure | 0:f5d099885d3d | 65 | #define MCP_RXM0EID8 0x22 |
Just4pLeisure | 0:f5d099885d3d | 66 | #define MCP_RXM0EID0 0x23 |
Just4pLeisure | 0:f5d099885d3d | 67 | #define MCP_RXM1SIDH 0x24 |
Just4pLeisure | 0:f5d099885d3d | 68 | #define MCP_RXM1SIDL 0x25 |
Just4pLeisure | 0:f5d099885d3d | 69 | #define MCP_RXM1EID8 0x26 |
Just4pLeisure | 0:f5d099885d3d | 70 | #define MCP_RXM1EID0 0x27 |
Just4pLeisure | 0:f5d099885d3d | 71 | #define MCP_CNF3 0x28 |
Just4pLeisure | 0:f5d099885d3d | 72 | #define MCP_CNF2 0x29 |
Just4pLeisure | 0:f5d099885d3d | 73 | #define MCP_CNF1 0x2A |
Just4pLeisure | 0:f5d099885d3d | 74 | #define MCP_CANINTE 0x2B |
Just4pLeisure | 0:f5d099885d3d | 75 | #define MCP_CANINTF 0x2C |
Just4pLeisure | 0:f5d099885d3d | 76 | #define MCP_EFLG 0x2D |
Just4pLeisure | 0:f5d099885d3d | 77 | #define MCP_TXB0CTRL 0x30 |
Just4pLeisure | 0:f5d099885d3d | 78 | #define MCP_TXB1CTRL 0x40 |
Just4pLeisure | 0:f5d099885d3d | 79 | #define MCP_TXB2CTRL 0x50 |
Just4pLeisure | 0:f5d099885d3d | 80 | #define MCP_RXB0CTRL 0x60 |
Just4pLeisure | 0:f5d099885d3d | 81 | #define MCP_RXB0SIDH 0x61 |
Just4pLeisure | 0:f5d099885d3d | 82 | #define MCP_RXB1CTRL 0x70 |
Just4pLeisure | 0:f5d099885d3d | 83 | #define MCP_RXB1SIDH 0x71 |
Just4pLeisure | 0:f5d099885d3d | 84 | /** Define MCP2515 SPI Instructions |
Just4pLeisure | 0:f5d099885d3d | 85 | */ |
Just4pLeisure | 0:f5d099885d3d | 86 | #define MCP_WRITE 0x02 |
Just4pLeisure | 0:f5d099885d3d | 87 | |
Just4pLeisure | 0:f5d099885d3d | 88 | #define MCP_READ 0x03 |
Just4pLeisure | 0:f5d099885d3d | 89 | |
Just4pLeisure | 0:f5d099885d3d | 90 | #define MCP_BITMOD 0x05 |
Just4pLeisure | 0:f5d099885d3d | 91 | |
Just4pLeisure | 0:f5d099885d3d | 92 | #define MCP_WRITE_TX0 0x40 |
Just4pLeisure | 0:f5d099885d3d | 93 | #define MCP_WRITE_TX1 0x42 |
Just4pLeisure | 0:f5d099885d3d | 94 | #define MCP_WRITE_TX2 0x44 |
Just4pLeisure | 0:f5d099885d3d | 95 | |
Just4pLeisure | 0:f5d099885d3d | 96 | #define MCP_RTS_TX0 0x81 |
Just4pLeisure | 0:f5d099885d3d | 97 | #define MCP_RTS_TX1 0x82 |
Just4pLeisure | 0:f5d099885d3d | 98 | #define MCP_RTS_TX2 0x84 |
Just4pLeisure | 0:f5d099885d3d | 99 | #define MCP_RTS_ALL 0x87 |
Just4pLeisure | 0:f5d099885d3d | 100 | |
Just4pLeisure | 0:f5d099885d3d | 101 | #define MCP_READ_RX0 0x90 |
Just4pLeisure | 0:f5d099885d3d | 102 | #define MCP_READ_RX1 0x94 |
Just4pLeisure | 0:f5d099885d3d | 103 | |
Just4pLeisure | 0:f5d099885d3d | 104 | #define MCP_READ_STATUS 0xA0 |
Just4pLeisure | 0:f5d099885d3d | 105 | |
Just4pLeisure | 0:f5d099885d3d | 106 | #define MCP_RX_STATUS 0xB0 |
Just4pLeisure | 0:f5d099885d3d | 107 | |
Just4pLeisure | 0:f5d099885d3d | 108 | #define MCP_RESET 0xC0 |
Just4pLeisure | 0:f5d099885d3d | 109 | |
Just4pLeisure | 0:f5d099885d3d | 110 | //#define TIMEOUTVALUE 50 |
Just4pLeisure | 0:f5d099885d3d | 111 | //#define MCP_SIDH 0 |
Just4pLeisure | 0:f5d099885d3d | 112 | //#define MCP_SIDL 1 |
Just4pLeisure | 0:f5d099885d3d | 113 | //#define MCP_EID8 2 |
Just4pLeisure | 0:f5d099885d3d | 114 | //#define MCP_EID0 3 |
Just4pLeisure | 0:f5d099885d3d | 115 | |
Just4pLeisure | 0:f5d099885d3d | 116 | #define MCP_TXB_EXIDE_M 0x08 /* In TXBnSIDL */ |
Just4pLeisure | 0:f5d099885d3d | 117 | #define MCP_DLC_MASK 0x0F /* 4 LSBits */ |
Just4pLeisure | 0:f5d099885d3d | 118 | #define MCP_RTR_MASK 0x40 /* (1<<6) Bit 6 */ |
Just4pLeisure | 0:f5d099885d3d | 119 | |
Just4pLeisure | 0:f5d099885d3d | 120 | #define MCP_RXB_RX_ANY 0x60 |
Just4pLeisure | 0:f5d099885d3d | 121 | #define MCP_RXB_RX_EXT 0x40 |
Just4pLeisure | 0:f5d099885d3d | 122 | #define MCP_RXB_RX_STD 0x20 |
Just4pLeisure | 0:f5d099885d3d | 123 | #define MCP_RXB_RX_STDEXT 0x00 |
Just4pLeisure | 0:f5d099885d3d | 124 | #define MCP_RXB_RX_MASK 0x60 |
Just4pLeisure | 0:f5d099885d3d | 125 | #define MCP_RXB_BUKT_MASK (1<<2) |
Just4pLeisure | 0:f5d099885d3d | 126 | /** Bits in the TXBnCTRL registers. |
Just4pLeisure | 0:f5d099885d3d | 127 | */ |
Just4pLeisure | 0:f5d099885d3d | 128 | #define MCP_TXB_TXBUFE_M 0x80 |
Just4pLeisure | 0:f5d099885d3d | 129 | #define MCP_TXB_ABTF_M 0x40 |
Just4pLeisure | 0:f5d099885d3d | 130 | #define MCP_TXB_MLOA_M 0x20 |
Just4pLeisure | 0:f5d099885d3d | 131 | #define MCP_TXB_TXERR_M 0x10 |
Just4pLeisure | 0:f5d099885d3d | 132 | #define MCP_TXB_TXREQ_M 0x08 |
Just4pLeisure | 0:f5d099885d3d | 133 | #define MCP_TXB_TXIE_M 0x04 |
Just4pLeisure | 0:f5d099885d3d | 134 | #define MCP_TXB_TXP10_M 0x03 |
Just4pLeisure | 0:f5d099885d3d | 135 | |
Just4pLeisure | 0:f5d099885d3d | 136 | #define MCP_TXB_RTR_M 0x40 /* In TXBnDLC */ |
Just4pLeisure | 0:f5d099885d3d | 137 | #define MCP_RXB_IDE_M 0x08 /* In RXBnSIDL */ |
Just4pLeisure | 0:f5d099885d3d | 138 | #define MCP_RXB_RTR_M 0x40 /* In RXBnDLC */ |
Just4pLeisure | 0:f5d099885d3d | 139 | |
Just4pLeisure | 0:f5d099885d3d | 140 | /** STATUS Command Values |
Just4pLeisure | 0:f5d099885d3d | 141 | */ |
Just4pLeisure | 0:f5d099885d3d | 142 | #define MCP_STAT_RXIF_MASK (0x03) |
Just4pLeisure | 0:f5d099885d3d | 143 | #define MCP_STAT_RX0IF (1<<0) |
Just4pLeisure | 0:f5d099885d3d | 144 | #define MCP_STAT_RX1IF (1<<1) |
Just4pLeisure | 0:f5d099885d3d | 145 | #define MCP_STAT_TX0REQ (1<<2) |
Just4pLeisure | 0:f5d099885d3d | 146 | #define MCP_STAT_TX0IF (1<<3) |
Just4pLeisure | 0:f5d099885d3d | 147 | #define MCP_STAT_TX1REQ (1<<4) |
Just4pLeisure | 0:f5d099885d3d | 148 | #define MCP_STAT_TX1IF (1<<5) |
Just4pLeisure | 0:f5d099885d3d | 149 | #define MCP_STAT_TX2REQ (1<<6) |
Just4pLeisure | 0:f5d099885d3d | 150 | #define MCP_STAT_TX2IF (1<<7) |
Just4pLeisure | 0:f5d099885d3d | 151 | |
Just4pLeisure | 0:f5d099885d3d | 152 | /** RX STATUS Command Values |
Just4pLeisure | 0:f5d099885d3d | 153 | */ |
Just4pLeisure | 0:f5d099885d3d | 154 | #define MCP_RXSTAT_RXF_MASK (7<<0) |
Just4pLeisure | 0:f5d099885d3d | 155 | #define MCP_RXSTAT_RXF0 (0<<0) |
Just4pLeisure | 0:f5d099885d3d | 156 | #define MCP_RXSTAT_RXF1 (1<<0) |
Just4pLeisure | 0:f5d099885d3d | 157 | #define MCP_RXSTAT_RXF2 (2<<0) |
Just4pLeisure | 0:f5d099885d3d | 158 | #define MCP_RXSTAT_RXF3 (3<<0) |
Just4pLeisure | 0:f5d099885d3d | 159 | #define MCP_RXSTAT_RXF4 (4<<0) |
Just4pLeisure | 0:f5d099885d3d | 160 | #define MCP_RXSTAT_RXF5 (5<<0) |
Just4pLeisure | 0:f5d099885d3d | 161 | #define MCP_RXSTAT_RXROF0 (6<<0) // RXF0 rollover to RXB1 |
Just4pLeisure | 0:f5d099885d3d | 162 | #define MCP_RXSTAT_RXROF1 (7<<0) // RXF1 rollover to RXB1 |
Just4pLeisure | 0:f5d099885d3d | 163 | #define MCP_RXSTAT_RTR (1<<3) |
Just4pLeisure | 0:f5d099885d3d | 164 | #define MCP_RXSTAT_IDE (1<<4) |
Just4pLeisure | 0:f5d099885d3d | 165 | #define MCP_RXSTAT_RXB_MASK (3<<6) |
Just4pLeisure | 0:f5d099885d3d | 166 | #define MCP_RXSTAT_NONE (0<<6) |
Just4pLeisure | 0:f5d099885d3d | 167 | #define MCP_RXSTAT_RXB0 (1<<6) |
Just4pLeisure | 0:f5d099885d3d | 168 | #define MCP_RXSTAT_RXB1 (2<<6) |
Just4pLeisure | 0:f5d099885d3d | 169 | #define MCP_RXSTAT_BOTH (3<<6) |
Just4pLeisure | 0:f5d099885d3d | 170 | |
Just4pLeisure | 0:f5d099885d3d | 171 | /** EFLG Register Values |
Just4pLeisure | 0:f5d099885d3d | 172 | */ |
Just4pLeisure | 2:fd026fcfde94 | 173 | #define MCP_EFLG_ALLMASK (0xFF) // All Bits |
Just4pLeisure | 2:fd026fcfde94 | 174 | #define MCP_EFLG_ERRORMASK (0xF8) // 5 MS-Bits |
Just4pLeisure | 2:fd026fcfde94 | 175 | #define MCP_EFLG_WARNMASK (0x07) // 3 LS-Bits |
Just4pLeisure | 0:f5d099885d3d | 176 | #define MCP_EFLG_EWARN (1<<0) |
Just4pLeisure | 0:f5d099885d3d | 177 | #define MCP_EFLG_RXWAR (1<<1) |
Just4pLeisure | 0:f5d099885d3d | 178 | #define MCP_EFLG_TXWAR (1<<2) |
Just4pLeisure | 0:f5d099885d3d | 179 | #define MCP_EFLG_RXEP (1<<3) |
Just4pLeisure | 0:f5d099885d3d | 180 | #define MCP_EFLG_TXEP (1<<4) |
Just4pLeisure | 0:f5d099885d3d | 181 | #define MCP_EFLG_TXBO (1<<5) |
Just4pLeisure | 0:f5d099885d3d | 182 | #define MCP_EFLG_RX0OVR (1<<6) |
Just4pLeisure | 0:f5d099885d3d | 183 | #define MCP_EFLG_RX1OVR (1<<7) |
Just4pLeisure | 0:f5d099885d3d | 184 | |
Just4pLeisure | 0:f5d099885d3d | 185 | /** CANCTRL Register Values |
Just4pLeisure | 0:f5d099885d3d | 186 | */ |
Just4pLeisure | 0:f5d099885d3d | 187 | #define CLKOUT_PS1 (0<<0) |
Just4pLeisure | 0:f5d099885d3d | 188 | #define CLKOUT_PS2 (1<<0) |
Just4pLeisure | 0:f5d099885d3d | 189 | #define CLKOUT_PS4 (2<<0) |
Just4pLeisure | 0:f5d099885d3d | 190 | #define CLKOUT_PS8 (3<<0) |
Just4pLeisure | 0:f5d099885d3d | 191 | #define CLKOUT_ENABLE (1<<2) |
Just4pLeisure | 0:f5d099885d3d | 192 | #define CLKOUT_DISABLE (0<<2) |
Just4pLeisure | 0:f5d099885d3d | 193 | #define MODE_ONESHOT (1<<3) |
Just4pLeisure | 0:f5d099885d3d | 194 | #define ABORT_TX (1<<4) |
Just4pLeisure | 0:f5d099885d3d | 195 | #define MODE_NORMAL (0<<5) |
Just4pLeisure | 0:f5d099885d3d | 196 | #define MODE_SLEEP (1<<5) |
Just4pLeisure | 0:f5d099885d3d | 197 | #define MODE_LOOPBACK (2<<5) |
Just4pLeisure | 0:f5d099885d3d | 198 | #define MODE_LISTENONLY (3<<5) |
Just4pLeisure | 0:f5d099885d3d | 199 | #define MODE_CONFIG (4<<5) |
Just4pLeisure | 0:f5d099885d3d | 200 | #define MODE_POWERUP (7<<5) |
Just4pLeisure | 0:f5d099885d3d | 201 | #define MODE_MASK (7<<5) |
Just4pLeisure | 0:f5d099885d3d | 202 | |
Just4pLeisure | 0:f5d099885d3d | 203 | /** Bit Rate timing |
Just4pLeisure | 0:f5d099885d3d | 204 | */ |
Just4pLeisure | 2:fd026fcfde94 | 205 | #define MCP_CLOCK_FREQ 16000000 // 16 MHz Crystal frequency |
Just4pLeisure | 2:fd026fcfde94 | 206 | #define CAN_SYNCSEG 1 // CAN-BUS Sync segment is always 1 Time Quantum |
Just4pLeisure | 0:f5d099885d3d | 207 | #define CAN_MAX_RATE MCP_CLOCK_FREQ/(2 * MCP_MIN_TIME_QUANTA) |
Just4pLeisure | 0:f5d099885d3d | 208 | #define CAN_MIN_RATE MCP_CLOCK_FREQ/(2 * MCP_MAX_PRESCALER * MCP_MAX_TIME_QUANTA) |
Just4pLeisure | 0:f5d099885d3d | 209 | #define MCP_MAX_TIME_QUANTA 25 |
Just4pLeisure | 0:f5d099885d3d | 210 | #define MCP_MIN_TIME_QUANTA 8 |
Just4pLeisure | 0:f5d099885d3d | 211 | #define MCP_MAX_PRESCALER 64 |
Just4pLeisure | 0:f5d099885d3d | 212 | #define MCP_MIN_PRESCALER 1 |
Just4pLeisure | 0:f5d099885d3d | 213 | /** CNF1 Register Values |
Just4pLeisure | 0:f5d099885d3d | 214 | */ |
Just4pLeisure | 0:f5d099885d3d | 215 | #define SJW1 (0<<6) |
Just4pLeisure | 0:f5d099885d3d | 216 | #define SJW2 (1<<6) |
Just4pLeisure | 0:f5d099885d3d | 217 | #define SJW3 (2<<6) |
Just4pLeisure | 0:f5d099885d3d | 218 | #define SJW4 (3<<6) |
Just4pLeisure | 0:f5d099885d3d | 219 | /** CNF2 Register Values |
Just4pLeisure | 0:f5d099885d3d | 220 | */ |
Just4pLeisure | 0:f5d099885d3d | 221 | #define BTLMODE (1<<7) |
Just4pLeisure | 0:f5d099885d3d | 222 | #define SAMPLE_1X (0<<4) |
Just4pLeisure | 0:f5d099885d3d | 223 | #define SAMPLE_3X (1<<4) |
Just4pLeisure | 0:f5d099885d3d | 224 | /** CNF3 Register Values |
Just4pLeisure | 0:f5d099885d3d | 225 | */ |
Just4pLeisure | 0:f5d099885d3d | 226 | #define WAKFIL_ENABLE (1<<4) |
Just4pLeisure | 0:f5d099885d3d | 227 | #define WAKFIL_DISABLE (0<<4) |
Just4pLeisure | 0:f5d099885d3d | 228 | #define SOF_ENABLE (1<<7) |
Just4pLeisure | 0:f5d099885d3d | 229 | #define SOF_DISABLE (0<<7) |
Just4pLeisure | 0:f5d099885d3d | 230 | /** CANINTF Register Bits |
Just4pLeisure | 0:f5d099885d3d | 231 | */ |
Just4pLeisure | 2:fd026fcfde94 | 232 | #define MCP_NO_INTS (0x00) // Disable all interrupts |
Just4pLeisure | 2:fd026fcfde94 | 233 | #define MCP_ALL_INTS (0xFF) // All Bits |
Just4pLeisure | 2:fd026fcfde94 | 234 | #define MCP_RX_INTS (MCP_RX1IF | MCP_RX0IF) // Enable all receive interrupts |
Just4pLeisure | 2:fd026fcfde94 | 235 | #define MCP_TX_INTS (MCP_TX2IF | MCP_TX1IF | MCP_TX0IF) // Enable all transmit interrupts |
Just4pLeisure | 0:f5d099885d3d | 236 | #define MCP_RX0IF (1<<0) |
Just4pLeisure | 0:f5d099885d3d | 237 | #define MCP_RX1IF (1<<1) |
Just4pLeisure | 0:f5d099885d3d | 238 | #define MCP_TX0IF (1<<2) |
Just4pLeisure | 0:f5d099885d3d | 239 | #define MCP_TX1IF (1<<3) |
Just4pLeisure | 0:f5d099885d3d | 240 | #define MCP_TX2IF (1<<4) |
Just4pLeisure | 0:f5d099885d3d | 241 | #define MCP_ERRIF (1<<5) |
Just4pLeisure | 0:f5d099885d3d | 242 | #define MCP_WAKIF (1<<6) |
Just4pLeisure | 0:f5d099885d3d | 243 | #define MCP_MERRF (1<<7) |
Just4pLeisure | 0:f5d099885d3d | 244 | |
Just4pLeisure | 0:f5d099885d3d | 245 | //#define MCP_RXBUF_0 (MCP_RXB0SIDH) |
Just4pLeisure | 0:f5d099885d3d | 246 | //#define MCP_RXBUF_1 (MCP_RXB1SIDH) |
Just4pLeisure | 0:f5d099885d3d | 247 | |
Just4pLeisure | 0:f5d099885d3d | 248 | #ifdef __cplusplus |
Just4pLeisure | 0:f5d099885d3d | 249 | }; |
Just4pLeisure | 0:f5d099885d3d | 250 | #endif |
Just4pLeisure | 0:f5d099885d3d | 251 | |
Just4pLeisure | 0:f5d099885d3d | 252 | #endif // SEEED_CAN_DEFS_H |
Just4pLeisure | 0:f5d099885d3d | 253 | /********************************************************************************************************* |
Just4pLeisure | 0:f5d099885d3d | 254 | END FILE |
Just4pLeisure | 0:f5d099885d3d | 255 | *********************************************************************************************************/ |