Santiago Gil / SX1276GenericLib-node1

LoRa node acquiring analog input and sending to LoRa Server - Working ok

Dependents:   DISCO-L072CZ-LRWAN1_LoRa_node EIoT_LoRa_node_1 EIoT_LoRa_node_2 EIoT_LoRa_node_3

Fork of SX1276GenericLib by Helmut Tschemernjak

sx1276/sx1276.cpp@89:b0203b4a36ec, 2017-08-30 (annotated)

Committer:
Helmut Tschemernjak
Date:
Wed Aug 30 12:02:09 2017 +0200
Revision:
89:b0203b4a36ec
Parent:
83:019da451b283
Child:
94:e6c0279f550a
Fixed calculation of the frequency error with negative numbers

Who changed what in which revision?

UserRevisionLine numberNew contents of line
GregCr 0:e6ceb13d2d05 1 /*
GregCr 0:e6ceb13d2d05 2 / _____) _ | |
GregCr 0:e6ceb13d2d05 3 ( (____ _____ ____ _| |_ _____ ____| |__
GregCr 0:e6ceb13d2d05 4 \____ \| ___ | (_ _) ___ |/ ___) _ \
GregCr 0:e6ceb13d2d05 5 _____) ) ____| | | || |_| ____( (___| | | |
GregCr 0:e6ceb13d2d05 6 (______/|_____)_|_|_| \__)_____)\____)_| |_|
mluis 22:7f3aab69cca9 7 (C) 2014 Semtech
GregCr 0:e6ceb13d2d05 8
GregCr 0:e6ceb13d2d05 9 Description: Actual implementation of a SX1276 radio, inherits Radio
GregCr 0:e6ceb13d2d05 10
GregCr 0:e6ceb13d2d05 11 License: Revised BSD License, see LICENSE.TXT file include in the project
GregCr 0:e6ceb13d2d05 12
GregCr 0:e6ceb13d2d05 13 Maintainers: Miguel Luis, Gregory Cristian and Nicolas Huguenin
GregCr 0:e6ceb13d2d05 14 */
Helmut Tschemernjak 34:07e89f23c734 15
Helmut Tschemernjak 34:07e89f23c734 16 /*
Helmut Tschemernjak 38:d9189d958db8 17 * additional development to make it more generic across multiple OS versions
Helmut Tschemernjak 34:07e89f23c734 18 * (c) 2017 Helmut Tschemernjak
Helmut Tschemernjak 34:07e89f23c734 19 * 30826 Garbsen (Hannover) Germany
Helmut Tschemernjak 34:07e89f23c734 20 */
Helmut Tschemernjak 34:07e89f23c734 21
GregCr 0:e6ceb13d2d05 22 #include "sx1276.h"
GregCr 0:e6ceb13d2d05 23
Helmut Tschemernjak 38:d9189d958db8 24
Helmut Tschemernjak 38:d9189d958db8 25
Helmut Tschemernjak 55:00c1f5b83920 26 const SX1276::BandwidthMap SX1276::FskBandwidths[] =
Helmut Tschemernjak 31:e50929bd3f32 27 {
GregCr 0:e6ceb13d2d05 28 { 2600 , 0x17 },
GregCr 0:e6ceb13d2d05 29 { 3100 , 0x0F },
GregCr 0:e6ceb13d2d05 30 { 3900 , 0x07 },
GregCr 0:e6ceb13d2d05 31 { 5200 , 0x16 },
GregCr 0:e6ceb13d2d05 32 { 6300 , 0x0E },
GregCr 0:e6ceb13d2d05 33 { 7800 , 0x06 },
GregCr 0:e6ceb13d2d05 34 { 10400 , 0x15 },
GregCr 0:e6ceb13d2d05 35 { 12500 , 0x0D },
GregCr 0:e6ceb13d2d05 36 { 15600 , 0x05 },
GregCr 0:e6ceb13d2d05 37 { 20800 , 0x14 },
GregCr 0:e6ceb13d2d05 38 { 25000 , 0x0C },
GregCr 0:e6ceb13d2d05 39 { 31300 , 0x04 },
GregCr 0:e6ceb13d2d05 40 { 41700 , 0x13 },
GregCr 0:e6ceb13d2d05 41 { 50000 , 0x0B },
GregCr 0:e6ceb13d2d05 42 { 62500 , 0x03 },
GregCr 0:e6ceb13d2d05 43 { 83333 , 0x12 },
GregCr 0:e6ceb13d2d05 44 { 100000, 0x0A },
GregCr 0:e6ceb13d2d05 45 { 125000, 0x02 },
GregCr 0:e6ceb13d2d05 46 { 166700, 0x11 },
GregCr 0:e6ceb13d2d05 47 { 200000, 0x09 },
mluis 15:04374b1c33fa 48 { 250000, 0x01 },
Helmut Tschemernjak 31:e50929bd3f32 49 { 300000, 0x00 }, // Invalid Bandwidth
GregCr 0:e6ceb13d2d05 50 };
GregCr 0:e6ceb13d2d05 51
Helmut Tschemernjak 55:00c1f5b83920 52 const SX1276::BandwidthMap SX1276::LoRaBandwidths[] =
Helmut Tschemernjak 55:00c1f5b83920 53 {
Helmut Tschemernjak 55:00c1f5b83920 54 { 7800, 0 }, // 7.8 kHz requires TCXO
Helmut Tschemernjak 55:00c1f5b83920 55 { 10400, 1 }, // 10.4 kHz requires TCXO
Helmut Tschemernjak 55:00c1f5b83920 56 { 15600, 2 }, // 15.6 kHz requires TCXO
Helmut Tschemernjak 55:00c1f5b83920 57 { 20800, 3 }, // 20.8 kHz requires TCXO
Helmut Tschemernjak 82:b93c4169ce41 58 { 31250, 4 }, // 31.25 kHz requires TCXO
Helmut Tschemernjak 82:b93c4169ce41 59 { 41700, 5 }, // 41.7 kHz requires TCXO
Helmut Tschemernjak 55:00c1f5b83920 60 { 62500, 6 }, // 62.5 kHz requires TCXO
Helmut Tschemernjak 82:b93c4169ce41 61 { 125000, 7 }, // 125 kHz the LoRa protocol default
Helmut Tschemernjak 82:b93c4169ce41 62 { 250000, 8 }, // 250 kHz
Helmut Tschemernjak 82:b93c4169ce41 63 { 500000, 9 }, // 500 kHz
Helmut Tschemernjak 62:835c5e20834e 64 { 600000, 10 }, // Invalid Bandwidth, reserved
Helmut Tschemernjak 55:00c1f5b83920 65 };
Helmut Tschemernjak 55:00c1f5b83920 66
GregCr 0:e6ceb13d2d05 67
Helmut Tschemernjak 38:d9189d958db8 68
Helmut Tschemernjak 38:d9189d958db8 69 /*!
Helmut Tschemernjak 38:d9189d958db8 70 * @brief Radio hardware registers initialization definition
Helmut Tschemernjak 38:d9189d958db8 71 *
Helmut Tschemernjak 38:d9189d958db8 72 * @remark Can be automatically generated by the SX1276 GUI (not yet implemented)
Helmut Tschemernjak 38:d9189d958db8 73 */
Helmut Tschemernjak 38:d9189d958db8 74
Helmut Tschemernjak 55:00c1f5b83920 75 const SX1276::RadioRegisters SX1276::RadioRegsInit[] = {
Helmut Tschemernjak 38:d9189d958db8 76 { MODEM_FSK , REG_LNA , 0x23 },
Helmut Tschemernjak 38:d9189d958db8 77 { MODEM_FSK , REG_RXCONFIG , 0x1E },
Helmut Tschemernjak 38:d9189d958db8 78 { MODEM_FSK , REG_RSSICONFIG , 0xD2 },
Helmut Tschemernjak 38:d9189d958db8 79 { MODEM_FSK , REG_AFCFEI , 0x01 },
Helmut Tschemernjak 38:d9189d958db8 80 { MODEM_FSK , REG_PREAMBLEDETECT , 0xAA },
Helmut Tschemernjak 38:d9189d958db8 81 { MODEM_FSK , REG_OSC , 0x07 },
Helmut Tschemernjak 38:d9189d958db8 82 { MODEM_FSK , REG_SYNCCONFIG , 0x12 },
Helmut Tschemernjak 38:d9189d958db8 83 { MODEM_FSK , REG_SYNCVALUE1 , 0xC1 },
Helmut Tschemernjak 38:d9189d958db8 84 { MODEM_FSK , REG_SYNCVALUE2 , 0x94 },
Helmut Tschemernjak 38:d9189d958db8 85 { MODEM_FSK , REG_SYNCVALUE3 , 0xC1 },
Helmut Tschemernjak 38:d9189d958db8 86 { MODEM_FSK , REG_PACKETCONFIG1 , 0xD8 },
Helmut Tschemernjak 38:d9189d958db8 87 { MODEM_FSK , REG_FIFOTHRESH , 0x8F },
Helmut Tschemernjak 38:d9189d958db8 88 { MODEM_FSK , REG_IMAGECAL , 0x02 },
Helmut Tschemernjak 38:d9189d958db8 89 { MODEM_FSK , REG_DIOMAPPING1 , 0x00 },
Helmut Tschemernjak 38:d9189d958db8 90 { MODEM_FSK , REG_DIOMAPPING2 , 0x30 },
Helmut Tschemernjak 38:d9189d958db8 91 { MODEM_LORA, REG_LR_PAYLOADMAXLENGTH, 0x40 },
Helmut Tschemernjak 38:d9189d958db8 92
Helmut Tschemernjak 38:d9189d958db8 93 };
Helmut Tschemernjak 38:d9189d958db8 94
Helmut Tschemernjak 38:d9189d958db8 95
Helmut Tschemernjak 34:07e89f23c734 96 SX1276::SX1276( RadioEvents_t *events) : Radio( events ), isRadioActive( false )
GregCr 0:e6ceb13d2d05 97 {
GregCr 23:1e143575df0f 98 this->rxtxBuffer = new uint8_t[RX_BUFFER_SIZE];
mluis 13:618826a997e2 99
mluis 21:2e496deb7858 100 this->RadioEvents = events;
mluis 21:2e496deb7858 101
mluis 13:618826a997e2 102 this->dioIrq = new DioIrqHandler[6];
GregCr 0:e6ceb13d2d05 103
mluis 13:618826a997e2 104 this->dioIrq[0] = &SX1276::OnDio0Irq;
mluis 13:618826a997e2 105 this->dioIrq[1] = &SX1276::OnDio1Irq;
mluis 13:618826a997e2 106 this->dioIrq[2] = &SX1276::OnDio2Irq;
mluis 13:618826a997e2 107 this->dioIrq[3] = &SX1276::OnDio3Irq;
mluis 13:618826a997e2 108 this->dioIrq[4] = &SX1276::OnDio4Irq;
mluis 13:618826a997e2 109 this->dioIrq[5] = NULL;
mluis 13:618826a997e2 110
mluis 21:2e496deb7858 111 this->settings.State = RF_IDLE;
GregCr 0:e6ceb13d2d05 112 }
GregCr 0:e6ceb13d2d05 113
GregCr 0:e6ceb13d2d05 114 SX1276::~SX1276( )
GregCr 0:e6ceb13d2d05 115 {
GregCr 23:1e143575df0f 116 delete this->rxtxBuffer;
mluis 13:618826a997e2 117 delete this->dioIrq;
GregCr 0:e6ceb13d2d05 118 }
GregCr 0:e6ceb13d2d05 119
Helmut Tschemernjak 54:0d8ea87fbab9 120 bool SX1276::Init( RadioEvents_t *events )
mluis 21:2e496deb7858 121 {
Helmut Tschemernjak 54:0d8ea87fbab9 122 if (Read(REG_VERSION) == 0x00)
Helmut Tschemernjak 54:0d8ea87fbab9 123 return false;
Helmut Tschemernjak 54:0d8ea87fbab9 124
mluis 21:2e496deb7858 125 this->RadioEvents = events;
Helmut Tschemernjak 54:0d8ea87fbab9 126 return true;
mluis 21:2e496deb7858 127 }
mluis 21:2e496deb7858 128
Helmut Tschemernjak 38:d9189d958db8 129
Helmut Tschemernjak 38:d9189d958db8 130 void SX1276::RadioRegistersInit( )
Helmut Tschemernjak 38:d9189d958db8 131 {
Helmut Tschemernjak 38:d9189d958db8 132 uint8_t i = 0;
Helmut Tschemernjak 55:00c1f5b83920 133 for( i = 0; i < sizeof( RadioRegsInit ) / sizeof( RadioRegisters ); i++ )
Helmut Tschemernjak 38:d9189d958db8 134 {
Helmut Tschemernjak 38:d9189d958db8 135 SetModem( RadioRegsInit[i].Modem );
Helmut Tschemernjak 38:d9189d958db8 136 Write( RadioRegsInit[i].Addr, RadioRegsInit[i].Value );
Helmut Tschemernjak 38:d9189d958db8 137 }
Helmut Tschemernjak 38:d9189d958db8 138 }
Helmut Tschemernjak 38:d9189d958db8 139
Helmut Tschemernjak 38:d9189d958db8 140
GregCr 19:71a47bb03fbb 141 RadioState SX1276::GetStatus( void )
GregCr 0:e6ceb13d2d05 142 {
GregCr 0:e6ceb13d2d05 143 return this->settings.State;
GregCr 0:e6ceb13d2d05 144 }
GregCr 0:e6ceb13d2d05 145
GregCr 0:e6ceb13d2d05 146 void SX1276::SetChannel( uint32_t freq )
GregCr 0:e6ceb13d2d05 147 {
GregCr 0:e6ceb13d2d05 148 this->settings.Channel = freq;
GregCr 0:e6ceb13d2d05 149 freq = ( uint32_t )( ( double )freq / ( double )FREQ_STEP );
GregCr 0:e6ceb13d2d05 150 Write( REG_FRFMSB, ( uint8_t )( ( freq >> 16 ) & 0xFF ) );
GregCr 0:e6ceb13d2d05 151 Write( REG_FRFMID, ( uint8_t )( ( freq >> 8 ) & 0xFF ) );
GregCr 0:e6ceb13d2d05 152 Write( REG_FRFLSB, ( uint8_t )( freq & 0xFF ) );
GregCr 0:e6ceb13d2d05 153 }
GregCr 0:e6ceb13d2d05 154
mluis 22:7f3aab69cca9 155 bool SX1276::IsChannelFree( RadioModems_t modem, uint32_t freq, int16_t rssiThresh )
GregCr 0:e6ceb13d2d05 156 {
GregCr 7:2b555111463f 157 int16_t rssi = 0;
mluis 25:3778e6204cc1 158
GregCr 0:e6ceb13d2d05 159 SetModem( modem );
GregCr 0:e6ceb13d2d05 160
GregCr 0:e6ceb13d2d05 161 SetChannel( freq );
mluis 25:3778e6204cc1 162
GregCr 0:e6ceb13d2d05 163 SetOpMode( RF_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 164
Helmut Tschemernjak 64:b721e6ab656a 165 Sleep_ms( 1 );
mluis 25:3778e6204cc1 166
GregCr 0:e6ceb13d2d05 167 rssi = GetRssi( modem );
mluis 25:3778e6204cc1 168
GregCr 0:e6ceb13d2d05 169 Sleep( );
mluis 25:3778e6204cc1 170
mluis 22:7f3aab69cca9 171 if( rssi > rssiThresh )
GregCr 0:e6ceb13d2d05 172 {
GregCr 0:e6ceb13d2d05 173 return false;
GregCr 0:e6ceb13d2d05 174 }
GregCr 0:e6ceb13d2d05 175 return true;
GregCr 0:e6ceb13d2d05 176 }
GregCr 0:e6ceb13d2d05 177
GregCr 0:e6ceb13d2d05 178 uint32_t SX1276::Random( void )
GregCr 0:e6ceb13d2d05 179 {
GregCr 0:e6ceb13d2d05 180 uint8_t i;
GregCr 0:e6ceb13d2d05 181 uint32_t rnd = 0;
GregCr 0:e6ceb13d2d05 182
GregCr 0:e6ceb13d2d05 183 /*
mluis 25:3778e6204cc1 184 * Radio setup for random number generation
GregCr 0:e6ceb13d2d05 185 */
GregCr 0:e6ceb13d2d05 186 // Set LoRa modem ON
GregCr 0:e6ceb13d2d05 187 SetModem( MODEM_LORA );
GregCr 0:e6ceb13d2d05 188
GregCr 0:e6ceb13d2d05 189 // Disable LoRa modem interrupts
GregCr 0:e6ceb13d2d05 190 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 0:e6ceb13d2d05 191 RFLR_IRQFLAGS_RXDONE |
GregCr 0:e6ceb13d2d05 192 RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 0:e6ceb13d2d05 193 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 0:e6ceb13d2d05 194 RFLR_IRQFLAGS_TXDONE |
GregCr 0:e6ceb13d2d05 195 RFLR_IRQFLAGS_CADDONE |
GregCr 0:e6ceb13d2d05 196 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
GregCr 0:e6ceb13d2d05 197 RFLR_IRQFLAGS_CADDETECTED );
GregCr 0:e6ceb13d2d05 198
GregCr 0:e6ceb13d2d05 199 // Set radio in continuous reception
GregCr 0:e6ceb13d2d05 200 SetOpMode( RF_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 201
GregCr 0:e6ceb13d2d05 202 for( i = 0; i < 32; i++ )
GregCr 0:e6ceb13d2d05 203 {
Helmut Tschemernjak 64:b721e6ab656a 204 Sleep_ms( 1 );
GregCr 0:e6ceb13d2d05 205 // Unfiltered RSSI value reading. Only takes the LSB value
GregCr 0:e6ceb13d2d05 206 rnd |= ( ( uint32_t )Read( REG_LR_RSSIWIDEBAND ) & 0x01 ) << i;
GregCr 0:e6ceb13d2d05 207 }
GregCr 0:e6ceb13d2d05 208
GregCr 0:e6ceb13d2d05 209 Sleep( );
GregCr 0:e6ceb13d2d05 210
GregCr 0:e6ceb13d2d05 211 return rnd;
GregCr 0:e6ceb13d2d05 212 }
GregCr 0:e6ceb13d2d05 213
GregCr 0:e6ceb13d2d05 214 /*!
mluis 22:7f3aab69cca9 215 * Performs the Rx chain calibration for LF and HF bands
mluis 22:7f3aab69cca9 216 * \remark Must be called just after the reset so all registers are at their
mluis 22:7f3aab69cca9 217 * default values
mluis 22:7f3aab69cca9 218 */
mluis 22:7f3aab69cca9 219 void SX1276::RxChainCalibration( void )
mluis 22:7f3aab69cca9 220 {
mluis 22:7f3aab69cca9 221 uint8_t regPaConfigInitVal;
mluis 22:7f3aab69cca9 222 uint32_t initialFreq;
mluis 22:7f3aab69cca9 223
mluis 22:7f3aab69cca9 224 // Save context
mluis 22:7f3aab69cca9 225 regPaConfigInitVal = this->Read( REG_PACONFIG );
mluis 22:7f3aab69cca9 226 initialFreq = ( double )( ( ( uint32_t )this->Read( REG_FRFMSB ) << 16 ) |
mluis 22:7f3aab69cca9 227 ( ( uint32_t )this->Read( REG_FRFMID ) << 8 ) |
mluis 22:7f3aab69cca9 228 ( ( uint32_t )this->Read( REG_FRFLSB ) ) ) * ( double )FREQ_STEP;
mluis 22:7f3aab69cca9 229
mluis 22:7f3aab69cca9 230 // Cut the PA just in case, RFO output, power = -1 dBm
mluis 22:7f3aab69cca9 231 this->Write( REG_PACONFIG, 0x00 );
mluis 22:7f3aab69cca9 232
mluis 22:7f3aab69cca9 233 // Launch Rx chain calibration for LF band
mluis 22:7f3aab69cca9 234 Write ( REG_IMAGECAL, ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START );
mluis 22:7f3aab69cca9 235 while( ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING )
mluis 22:7f3aab69cca9 236 {
mluis 22:7f3aab69cca9 237 }
mluis 22:7f3aab69cca9 238
mluis 22:7f3aab69cca9 239 // Sets a Frequency in HF band
mluis 22:7f3aab69cca9 240 SetChannel( 868000000 );
mluis 22:7f3aab69cca9 241
Helmut Tschemernjak 31:e50929bd3f32 242 // Launch Rx chain calibration for HF band
mluis 22:7f3aab69cca9 243 Write ( REG_IMAGECAL, ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_MASK ) | RF_IMAGECAL_IMAGECAL_START );
mluis 22:7f3aab69cca9 244 while( ( Read( REG_IMAGECAL ) & RF_IMAGECAL_IMAGECAL_RUNNING ) == RF_IMAGECAL_IMAGECAL_RUNNING )
mluis 22:7f3aab69cca9 245 {
mluis 22:7f3aab69cca9 246 }
mluis 22:7f3aab69cca9 247
mluis 22:7f3aab69cca9 248 // Restore context
mluis 22:7f3aab69cca9 249 this->Write( REG_PACONFIG, regPaConfigInitVal );
mluis 22:7f3aab69cca9 250 SetChannel( initialFreq );
mluis 22:7f3aab69cca9 251 }
mluis 22:7f3aab69cca9 252
mluis 22:7f3aab69cca9 253 /*!
GregCr 0:e6ceb13d2d05 254 * Returns the known FSK bandwidth registers value
GregCr 0:e6ceb13d2d05 255 *
GregCr 0:e6ceb13d2d05 256 * \param [IN] bandwidth Bandwidth value in Hz
GregCr 0:e6ceb13d2d05 257 * \retval regValue Bandwidth register value.
GregCr 0:e6ceb13d2d05 258 */
GregCr 0:e6ceb13d2d05 259 uint8_t SX1276::GetFskBandwidthRegValue( uint32_t bandwidth )
GregCr 0:e6ceb13d2d05 260 {
GregCr 0:e6ceb13d2d05 261 uint8_t i;
GregCr 0:e6ceb13d2d05 262
Helmut Tschemernjak 55:00c1f5b83920 263 for( i = 0; i < ( sizeof( FskBandwidths ) / sizeof( BandwidthMap ) ) - 1; i++ )
GregCr 0:e6ceb13d2d05 264 {
GregCr 0:e6ceb13d2d05 265 if( ( bandwidth >= FskBandwidths[i].bandwidth ) && ( bandwidth < FskBandwidths[i + 1].bandwidth ) )
GregCr 0:e6ceb13d2d05 266 {
GregCr 0:e6ceb13d2d05 267 return FskBandwidths[i].RegValue;
GregCr 0:e6ceb13d2d05 268 }
GregCr 0:e6ceb13d2d05 269 }
GregCr 0:e6ceb13d2d05 270 // ERROR: Value not found
GregCr 0:e6ceb13d2d05 271 while( 1 );
GregCr 0:e6ceb13d2d05 272 }
GregCr 0:e6ceb13d2d05 273
Helmut Tschemernjak 55:00c1f5b83920 274 /*!
Helmut Tschemernjak 55:00c1f5b83920 275 * Returns the known LoRa bandwidth registers value
Helmut Tschemernjak 55:00c1f5b83920 276 *
Helmut Tschemernjak 55:00c1f5b83920 277 * \param [IN] bandwidth Bandwidth value in Hz
Helmut Tschemernjak 55:00c1f5b83920 278 * \retval regValue Bandwidth register value.
Helmut Tschemernjak 55:00c1f5b83920 279 */
Helmut Tschemernjak 55:00c1f5b83920 280 uint8_t SX1276::GetLoRaBandwidthRegValue( uint32_t bandwidth )
Helmut Tschemernjak 55:00c1f5b83920 281 {
Helmut Tschemernjak 55:00c1f5b83920 282 uint8_t i;
Helmut Tschemernjak 55:00c1f5b83920 283
Helmut Tschemernjak 55:00c1f5b83920 284 for( i = 0; i < ( sizeof( LoRaBandwidths ) / sizeof( BandwidthMap ) ) - 1; i++ )
Helmut Tschemernjak 55:00c1f5b83920 285 {
Helmut Tschemernjak 55:00c1f5b83920 286 if( ( bandwidth >= LoRaBandwidths[i].bandwidth ) && ( bandwidth < LoRaBandwidths[i + 1].bandwidth ) )
Helmut Tschemernjak 55:00c1f5b83920 287 {
Helmut Tschemernjak 55:00c1f5b83920 288 return LoRaBandwidths[i].RegValue;
Helmut Tschemernjak 55:00c1f5b83920 289 }
Helmut Tschemernjak 55:00c1f5b83920 290 }
Helmut Tschemernjak 55:00c1f5b83920 291 // ERROR: Value not found
Helmut Tschemernjak 55:00c1f5b83920 292 while( 1 );
Helmut Tschemernjak 55:00c1f5b83920 293 }
Helmut Tschemernjak 55:00c1f5b83920 294
mluis 22:7f3aab69cca9 295 void SX1276::SetRxConfig( RadioModems_t modem, uint32_t bandwidth,
GregCr 0:e6ceb13d2d05 296 uint32_t datarate, uint8_t coderate,
GregCr 0:e6ceb13d2d05 297 uint32_t bandwidthAfc, uint16_t preambleLen,
GregCr 0:e6ceb13d2d05 298 uint16_t symbTimeout, bool fixLen,
mluis 13:618826a997e2 299 uint8_t payloadLen,
mluis 13:618826a997e2 300 bool crcOn, bool freqHopOn, uint8_t hopPeriod,
GregCr 6:e7f02929cd3d 301 bool iqInverted, bool rxContinuous )
GregCr 0:e6ceb13d2d05 302 {
GregCr 0:e6ceb13d2d05 303 SetModem( modem );
GregCr 0:e6ceb13d2d05 304
GregCr 0:e6ceb13d2d05 305 switch( modem )
GregCr 0:e6ceb13d2d05 306 {
GregCr 0:e6ceb13d2d05 307 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 308 {
GregCr 0:e6ceb13d2d05 309 this->settings.Fsk.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 310 this->settings.Fsk.Datarate = datarate;
GregCr 0:e6ceb13d2d05 311 this->settings.Fsk.BandwidthAfc = bandwidthAfc;
GregCr 0:e6ceb13d2d05 312 this->settings.Fsk.FixLen = fixLen;
mluis 13:618826a997e2 313 this->settings.Fsk.PayloadLen = payloadLen;
GregCr 0:e6ceb13d2d05 314 this->settings.Fsk.CrcOn = crcOn;
GregCr 0:e6ceb13d2d05 315 this->settings.Fsk.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 316 this->settings.Fsk.RxContinuous = rxContinuous;
GregCr 0:e6ceb13d2d05 317 this->settings.Fsk.PreambleLen = preambleLen;
Helmut Tschemernjak 31:e50929bd3f32 318 this->settings.Fsk.RxSingleTimeout = symbTimeout * ( ( 1.0 / ( double )datarate ) * 8.0 ) * 1e3;
Helmut Tschemernjak 31:e50929bd3f32 319
mluis 25:3778e6204cc1 320
GregCr 0:e6ceb13d2d05 321 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
GregCr 0:e6ceb13d2d05 322 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
GregCr 0:e6ceb13d2d05 323 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
GregCr 0:e6ceb13d2d05 324
GregCr 0:e6ceb13d2d05 325 Write( REG_RXBW, GetFskBandwidthRegValue( bandwidth ) );
GregCr 0:e6ceb13d2d05 326 Write( REG_AFCBW, GetFskBandwidthRegValue( bandwidthAfc ) );
GregCr 0:e6ceb13d2d05 327
mluis 14:8552d0b840be 328 Write( REG_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
mluis 14:8552d0b840be 329 Write( REG_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
mluis 25:3778e6204cc1 330
mluis 22:7f3aab69cca9 331 if( fixLen == 1 )
mluis 22:7f3aab69cca9 332 {
mluis 22:7f3aab69cca9 333 Write( REG_PAYLOADLENGTH, payloadLen );
mluis 22:7f3aab69cca9 334 }
GregCr 23:1e143575df0f 335 else
GregCr 23:1e143575df0f 336 {
mluis 25:3778e6204cc1 337 Write( REG_PAYLOADLENGTH, 0xFF ); // Set payload length to the maximum
GregCr 23:1e143575df0f 338 }
GregCr 23:1e143575df0f 339
GregCr 0:e6ceb13d2d05 340 Write( REG_PACKETCONFIG1,
Helmut Tschemernjak 31:e50929bd3f32 341 ( Read( REG_PACKETCONFIG1 ) &
GregCr 0:e6ceb13d2d05 342 RF_PACKETCONFIG1_CRC_MASK &
GregCr 0:e6ceb13d2d05 343 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
GregCr 0:e6ceb13d2d05 344 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
GregCr 0:e6ceb13d2d05 345 ( crcOn << 4 ) );
Helmut Tschemernjak 31:e50929bd3f32 346 Write( REG_PACKETCONFIG2, ( Read( REG_PACKETCONFIG2 ) | RF_PACKETCONFIG2_DATAMODE_PACKET ) );
GregCr 0:e6ceb13d2d05 347 }
GregCr 0:e6ceb13d2d05 348 break;
GregCr 0:e6ceb13d2d05 349 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 350 {
Helmut Tschemernjak 56:4fddac05ac07 351 if (bandwidth > 11) // specified in Hz, needs mapping
Helmut Tschemernjak 56:4fddac05ac07 352 bandwidth = GetLoRaBandwidthRegValue(bandwidth);
Helmut Tschemernjak 33:5db0d1e716b1 353 if( bandwidth > LORA_BANKWIDTH_500kHz )
GregCr 0:e6ceb13d2d05 354 {
GregCr 0:e6ceb13d2d05 355 // Fatal error: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
GregCr 0:e6ceb13d2d05 356 while( 1 );
GregCr 0:e6ceb13d2d05 357 }
GregCr 0:e6ceb13d2d05 358 this->settings.LoRa.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 359 this->settings.LoRa.Datarate = datarate;
GregCr 0:e6ceb13d2d05 360 this->settings.LoRa.Coderate = coderate;
mluis 22:7f3aab69cca9 361 this->settings.LoRa.PreambleLen = preambleLen;
GregCr 0:e6ceb13d2d05 362 this->settings.LoRa.FixLen = fixLen;
mluis 13:618826a997e2 363 this->settings.LoRa.PayloadLen = payloadLen;
GregCr 0:e6ceb13d2d05 364 this->settings.LoRa.CrcOn = crcOn;
mluis 13:618826a997e2 365 this->settings.LoRa.FreqHopOn = freqHopOn;
mluis 13:618826a997e2 366 this->settings.LoRa.HopPeriod = hopPeriod;
GregCr 0:e6ceb13d2d05 367 this->settings.LoRa.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 368 this->settings.LoRa.RxContinuous = rxContinuous;
mluis 22:7f3aab69cca9 369
Helmut Tschemernjak 33:5db0d1e716b1 370 if( datarate > LORA_SF12 )
GregCr 0:e6ceb13d2d05 371 {
Helmut Tschemernjak 33:5db0d1e716b1 372 datarate = LORA_SF12;
GregCr 0:e6ceb13d2d05 373 }
Helmut Tschemernjak 33:5db0d1e716b1 374 else if( datarate < LORA_SF6 )
GregCr 0:e6ceb13d2d05 375 {
Helmut Tschemernjak 33:5db0d1e716b1 376 datarate = LORA_SF6;
GregCr 0:e6ceb13d2d05 377 }
mluis 25:3778e6204cc1 378
Helmut Tschemernjak 33:5db0d1e716b1 379 if( ( ( bandwidth == LORA_BANKWIDTH_125kHz ) && ( ( datarate == LORA_SF11 ) || ( datarate == LORA_SF12 ) ) ) ||
Helmut Tschemernjak 33:5db0d1e716b1 380 ( ( bandwidth == LORA_BANKWIDTH_250kHz ) && ( datarate == LORA_SF12 ) ) )
GregCr 0:e6ceb13d2d05 381 {
GregCr 0:e6ceb13d2d05 382 this->settings.LoRa.LowDatarateOptimize = 0x01;
GregCr 0:e6ceb13d2d05 383 }
GregCr 0:e6ceb13d2d05 384 else
GregCr 0:e6ceb13d2d05 385 {
GregCr 0:e6ceb13d2d05 386 this->settings.LoRa.LowDatarateOptimize = 0x00;
GregCr 0:e6ceb13d2d05 387 }
GregCr 0:e6ceb13d2d05 388
Helmut Tschemernjak 31:e50929bd3f32 389 Write( REG_LR_MODEMCONFIG1,
GregCr 0:e6ceb13d2d05 390 ( Read( REG_LR_MODEMCONFIG1 ) &
GregCr 0:e6ceb13d2d05 391 RFLR_MODEMCONFIG1_BW_MASK &
GregCr 0:e6ceb13d2d05 392 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
GregCr 0:e6ceb13d2d05 393 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) |
mluis 25:3778e6204cc1 394 ( bandwidth << 4 ) | ( coderate << 1 ) |
GregCr 0:e6ceb13d2d05 395 fixLen );
mluis 25:3778e6204cc1 396
GregCr 0:e6ceb13d2d05 397 Write( REG_LR_MODEMCONFIG2,
GregCr 0:e6ceb13d2d05 398 ( Read( REG_LR_MODEMCONFIG2 ) &
GregCr 0:e6ceb13d2d05 399 RFLR_MODEMCONFIG2_SF_MASK &
GregCr 0:e6ceb13d2d05 400 RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK &
GregCr 0:e6ceb13d2d05 401 RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) |
GregCr 0:e6ceb13d2d05 402 ( datarate << 4 ) | ( crcOn << 2 ) |
GregCr 0:e6ceb13d2d05 403 ( ( symbTimeout >> 8 ) & ~RFLR_MODEMCONFIG2_SYMBTIMEOUTMSB_MASK ) );
GregCr 0:e6ceb13d2d05 404
Helmut Tschemernjak 31:e50929bd3f32 405 Write( REG_LR_MODEMCONFIG3,
GregCr 0:e6ceb13d2d05 406 ( Read( REG_LR_MODEMCONFIG3 ) &
GregCr 0:e6ceb13d2d05 407 RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 408 ( this->settings.LoRa.LowDatarateOptimize << 3 ) );
GregCr 0:e6ceb13d2d05 409
GregCr 0:e6ceb13d2d05 410 Write( REG_LR_SYMBTIMEOUTLSB, ( uint8_t )( symbTimeout & 0xFF ) );
mluis 25:3778e6204cc1 411
GregCr 0:e6ceb13d2d05 412 Write( REG_LR_PREAMBLEMSB, ( uint8_t )( ( preambleLen >> 8 ) & 0xFF ) );
GregCr 0:e6ceb13d2d05 413 Write( REG_LR_PREAMBLELSB, ( uint8_t )( preambleLen & 0xFF ) );
GregCr 0:e6ceb13d2d05 414
mluis 13:618826a997e2 415 if( fixLen == 1 )
mluis 13:618826a997e2 416 {
mluis 13:618826a997e2 417 Write( REG_LR_PAYLOADLENGTH, payloadLen );
mluis 13:618826a997e2 418 }
mluis 13:618826a997e2 419
GregCr 6:e7f02929cd3d 420 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 421 {
GregCr 6:e7f02929cd3d 422 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
GregCr 6:e7f02929cd3d 423 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
GregCr 6:e7f02929cd3d 424 }
GregCr 6:e7f02929cd3d 425
Helmut Tschemernjak 33:5db0d1e716b1 426 if( ( bandwidth == LORA_BANKWIDTH_500kHz ) && ( this->settings.Channel > RF_MID_BAND_THRESH ) )
mluis 22:7f3aab69cca9 427 {
mluis 25:3778e6204cc1 428 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
mluis 22:7f3aab69cca9 429 Write( REG_LR_TEST36, 0x02 );
mluis 22:7f3aab69cca9 430 Write( REG_LR_TEST3A, 0x64 );
mluis 22:7f3aab69cca9 431 }
Helmut Tschemernjak 33:5db0d1e716b1 432 else if( bandwidth == LORA_BANKWIDTH_500kHz )
mluis 22:7f3aab69cca9 433 {
mluis 22:7f3aab69cca9 434 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
mluis 22:7f3aab69cca9 435 Write( REG_LR_TEST36, 0x02 );
mluis 22:7f3aab69cca9 436 Write( REG_LR_TEST3A, 0x7F );
mluis 22:7f3aab69cca9 437 }
mluis 22:7f3aab69cca9 438 else
mluis 22:7f3aab69cca9 439 {
mluis 22:7f3aab69cca9 440 // ERRATA 2.1 - Sensitivity Optimization with a 500 kHz Bandwidth
mluis 22:7f3aab69cca9 441 Write( REG_LR_TEST36, 0x03 );
mluis 22:7f3aab69cca9 442 }
mluis 25:3778e6204cc1 443
Helmut Tschemernjak 33:5db0d1e716b1 444 if( datarate == LORA_SF6 )
GregCr 0:e6ceb13d2d05 445 {
Helmut Tschemernjak 31:e50929bd3f32 446 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 447 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 448 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 449 RFLR_DETECTIONOPTIMIZE_SF6 );
mluis 25:3778e6204cc1 450 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 451 RFLR_DETECTIONTHRESH_SF6 );
GregCr 0:e6ceb13d2d05 452 }
GregCr 0:e6ceb13d2d05 453 else
GregCr 0:e6ceb13d2d05 454 {
GregCr 0:e6ceb13d2d05 455 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 456 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 457 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 458 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
Helmut Tschemernjak 31:e50929bd3f32 459 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 460 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
GregCr 0:e6ceb13d2d05 461 }
GregCr 0:e6ceb13d2d05 462 }
GregCr 0:e6ceb13d2d05 463 break;
GregCr 0:e6ceb13d2d05 464 }
GregCr 0:e6ceb13d2d05 465 }
GregCr 0:e6ceb13d2d05 466
mluis 25:3778e6204cc1 467 void SX1276::SetTxConfig( RadioModems_t modem, int8_t power, uint32_t fdev,
GregCr 0:e6ceb13d2d05 468 uint32_t bandwidth, uint32_t datarate,
GregCr 0:e6ceb13d2d05 469 uint8_t coderate, uint16_t preambleLen,
mluis 25:3778e6204cc1 470 bool fixLen, bool crcOn, bool freqHopOn,
mluis 13:618826a997e2 471 uint8_t hopPeriod, bool iqInverted, uint32_t timeout )
GregCr 0:e6ceb13d2d05 472 {
GregCr 0:e6ceb13d2d05 473 SetModem( modem );
Helmut Tschemernjak 31:e50929bd3f32 474 SetRfTxPower( power );
GregCr 0:e6ceb13d2d05 475
Helmut Tschemernjak 31:e50929bd3f32 476 switch( modem )
GregCr 0:e6ceb13d2d05 477 {
GregCr 0:e6ceb13d2d05 478 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 479 {
GregCr 0:e6ceb13d2d05 480 this->settings.Fsk.Power = power;
GregCr 0:e6ceb13d2d05 481 this->settings.Fsk.Fdev = fdev;
GregCr 0:e6ceb13d2d05 482 this->settings.Fsk.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 483 this->settings.Fsk.Datarate = datarate;
GregCr 0:e6ceb13d2d05 484 this->settings.Fsk.PreambleLen = preambleLen;
GregCr 0:e6ceb13d2d05 485 this->settings.Fsk.FixLen = fixLen;
GregCr 0:e6ceb13d2d05 486 this->settings.Fsk.CrcOn = crcOn;
GregCr 0:e6ceb13d2d05 487 this->settings.Fsk.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 488 this->settings.Fsk.TxTimeout = timeout;
mluis 25:3778e6204cc1 489
GregCr 0:e6ceb13d2d05 490 fdev = ( uint16_t )( ( double )fdev / ( double )FREQ_STEP );
GregCr 0:e6ceb13d2d05 491 Write( REG_FDEVMSB, ( uint8_t )( fdev >> 8 ) );
GregCr 0:e6ceb13d2d05 492 Write( REG_FDEVLSB, ( uint8_t )( fdev & 0xFF ) );
GregCr 0:e6ceb13d2d05 493
GregCr 0:e6ceb13d2d05 494 datarate = ( uint16_t )( ( double )XTAL_FREQ / ( double )datarate );
GregCr 0:e6ceb13d2d05 495 Write( REG_BITRATEMSB, ( uint8_t )( datarate >> 8 ) );
GregCr 0:e6ceb13d2d05 496 Write( REG_BITRATELSB, ( uint8_t )( datarate & 0xFF ) );
GregCr 0:e6ceb13d2d05 497
GregCr 0:e6ceb13d2d05 498 Write( REG_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
GregCr 0:e6ceb13d2d05 499 Write( REG_PREAMBLELSB, preambleLen & 0xFF );
GregCr 0:e6ceb13d2d05 500
GregCr 0:e6ceb13d2d05 501 Write( REG_PACKETCONFIG1,
mluis 25:3778e6204cc1 502 ( Read( REG_PACKETCONFIG1 ) &
GregCr 0:e6ceb13d2d05 503 RF_PACKETCONFIG1_CRC_MASK &
GregCr 0:e6ceb13d2d05 504 RF_PACKETCONFIG1_PACKETFORMAT_MASK ) |
GregCr 0:e6ceb13d2d05 505 ( ( fixLen == 1 ) ? RF_PACKETCONFIG1_PACKETFORMAT_FIXED : RF_PACKETCONFIG1_PACKETFORMAT_VARIABLE ) |
GregCr 0:e6ceb13d2d05 506 ( crcOn << 4 ) );
Helmut Tschemernjak 31:e50929bd3f32 507 Write( REG_PACKETCONFIG2, ( Read( REG_PACKETCONFIG2 ) | RF_PACKETCONFIG2_DATAMODE_PACKET ) );
GregCr 0:e6ceb13d2d05 508 }
GregCr 0:e6ceb13d2d05 509 break;
GregCr 0:e6ceb13d2d05 510 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 511 {
GregCr 0:e6ceb13d2d05 512 this->settings.LoRa.Power = power;
Helmut Tschemernjak 56:4fddac05ac07 513 if (bandwidth > 11) // specified in Hz, needs mapping
Helmut Tschemernjak 56:4fddac05ac07 514 bandwidth = GetLoRaBandwidthRegValue(bandwidth);
Helmut Tschemernjak 33:5db0d1e716b1 515 if( bandwidth > LORA_BANKWIDTH_500kHz )
GregCr 0:e6ceb13d2d05 516 {
GregCr 0:e6ceb13d2d05 517 // Fatal error: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
GregCr 0:e6ceb13d2d05 518 while( 1 );
GregCr 0:e6ceb13d2d05 519 }
GregCr 0:e6ceb13d2d05 520 this->settings.LoRa.Bandwidth = bandwidth;
GregCr 0:e6ceb13d2d05 521 this->settings.LoRa.Datarate = datarate;
GregCr 0:e6ceb13d2d05 522 this->settings.LoRa.Coderate = coderate;
GregCr 0:e6ceb13d2d05 523 this->settings.LoRa.PreambleLen = preambleLen;
GregCr 0:e6ceb13d2d05 524 this->settings.LoRa.FixLen = fixLen;
mluis 13:618826a997e2 525 this->settings.LoRa.FreqHopOn = freqHopOn;
mluis 13:618826a997e2 526 this->settings.LoRa.HopPeriod = hopPeriod;
mluis 22:7f3aab69cca9 527 this->settings.LoRa.CrcOn = crcOn;
GregCr 0:e6ceb13d2d05 528 this->settings.LoRa.IqInverted = iqInverted;
GregCr 0:e6ceb13d2d05 529 this->settings.LoRa.TxTimeout = timeout;
GregCr 0:e6ceb13d2d05 530
Helmut Tschemernjak 33:5db0d1e716b1 531 if( datarate > LORA_SF12 )
GregCr 0:e6ceb13d2d05 532 {
Helmut Tschemernjak 33:5db0d1e716b1 533 datarate = LORA_SF12;
GregCr 0:e6ceb13d2d05 534 }
Helmut Tschemernjak 33:5db0d1e716b1 535 else if( datarate < LORA_SF6 )
GregCr 0:e6ceb13d2d05 536 {
Helmut Tschemernjak 33:5db0d1e716b1 537 datarate = LORA_SF6;
GregCr 0:e6ceb13d2d05 538 }
Helmut Tschemernjak 33:5db0d1e716b1 539 if( ( ( bandwidth == LORA_BANKWIDTH_125kHz ) && ( ( datarate == LORA_SF11 ) || ( datarate == LORA_SF12 ) ) ) ||
Helmut Tschemernjak 33:5db0d1e716b1 540 ( ( bandwidth == LORA_BANKWIDTH_250kHz ) && ( datarate == LORA_SF12 ) ) )
GregCr 0:e6ceb13d2d05 541 {
GregCr 0:e6ceb13d2d05 542 this->settings.LoRa.LowDatarateOptimize = 0x01;
GregCr 0:e6ceb13d2d05 543 }
GregCr 0:e6ceb13d2d05 544 else
GregCr 0:e6ceb13d2d05 545 {
GregCr 0:e6ceb13d2d05 546 this->settings.LoRa.LowDatarateOptimize = 0x00;
GregCr 0:e6ceb13d2d05 547 }
mluis 22:7f3aab69cca9 548
GregCr 6:e7f02929cd3d 549 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 550 {
GregCr 6:e7f02929cd3d 551 Write( REG_LR_PLLHOP, ( Read( REG_LR_PLLHOP ) & RFLR_PLLHOP_FASTHOP_MASK ) | RFLR_PLLHOP_FASTHOP_ON );
GregCr 6:e7f02929cd3d 552 Write( REG_LR_HOPPERIOD, this->settings.LoRa.HopPeriod );
GregCr 6:e7f02929cd3d 553 }
mluis 22:7f3aab69cca9 554
mluis 25:3778e6204cc1 555 Write( REG_LR_MODEMCONFIG1,
GregCr 0:e6ceb13d2d05 556 ( Read( REG_LR_MODEMCONFIG1 ) &
GregCr 0:e6ceb13d2d05 557 RFLR_MODEMCONFIG1_BW_MASK &
GregCr 0:e6ceb13d2d05 558 RFLR_MODEMCONFIG1_CODINGRATE_MASK &
GregCr 0:e6ceb13d2d05 559 RFLR_MODEMCONFIG1_IMPLICITHEADER_MASK ) |
mluis 25:3778e6204cc1 560 ( bandwidth << 4 ) | ( coderate << 1 ) |
GregCr 0:e6ceb13d2d05 561 fixLen );
GregCr 0:e6ceb13d2d05 562
GregCr 0:e6ceb13d2d05 563 Write( REG_LR_MODEMCONFIG2,
GregCr 0:e6ceb13d2d05 564 ( Read( REG_LR_MODEMCONFIG2 ) &
GregCr 0:e6ceb13d2d05 565 RFLR_MODEMCONFIG2_SF_MASK &
GregCr 0:e6ceb13d2d05 566 RFLR_MODEMCONFIG2_RXPAYLOADCRC_MASK ) |
GregCr 0:e6ceb13d2d05 567 ( datarate << 4 ) | ( crcOn << 2 ) );
GregCr 0:e6ceb13d2d05 568
Helmut Tschemernjak 31:e50929bd3f32 569 Write( REG_LR_MODEMCONFIG3,
GregCr 0:e6ceb13d2d05 570 ( Read( REG_LR_MODEMCONFIG3 ) &
GregCr 0:e6ceb13d2d05 571 RFLR_MODEMCONFIG3_LOWDATARATEOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 572 ( this->settings.LoRa.LowDatarateOptimize << 3 ) );
mluis 25:3778e6204cc1 573
GregCr 0:e6ceb13d2d05 574 Write( REG_LR_PREAMBLEMSB, ( preambleLen >> 8 ) & 0x00FF );
GregCr 0:e6ceb13d2d05 575 Write( REG_LR_PREAMBLELSB, preambleLen & 0xFF );
mluis 25:3778e6204cc1 576
Helmut Tschemernjak 33:5db0d1e716b1 577 if( datarate == LORA_SF6 )
GregCr 0:e6ceb13d2d05 578 {
mluis 25:3778e6204cc1 579 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 580 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 581 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 582 RFLR_DETECTIONOPTIMIZE_SF6 );
mluis 25:3778e6204cc1 583 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 584 RFLR_DETECTIONTHRESH_SF6 );
GregCr 0:e6ceb13d2d05 585 }
GregCr 0:e6ceb13d2d05 586 else
GregCr 0:e6ceb13d2d05 587 {
GregCr 0:e6ceb13d2d05 588 Write( REG_LR_DETECTOPTIMIZE,
GregCr 0:e6ceb13d2d05 589 ( Read( REG_LR_DETECTOPTIMIZE ) &
GregCr 0:e6ceb13d2d05 590 RFLR_DETECTIONOPTIMIZE_MASK ) |
GregCr 0:e6ceb13d2d05 591 RFLR_DETECTIONOPTIMIZE_SF7_TO_SF12 );
mluis 25:3778e6204cc1 592 Write( REG_LR_DETECTIONTHRESHOLD,
GregCr 0:e6ceb13d2d05 593 RFLR_DETECTIONTHRESH_SF7_TO_SF12 );
GregCr 0:e6ceb13d2d05 594 }
GregCr 0:e6ceb13d2d05 595 }
GregCr 0:e6ceb13d2d05 596 break;
GregCr 0:e6ceb13d2d05 597 }
GregCr 0:e6ceb13d2d05 598 }
GregCr 0:e6ceb13d2d05 599
Helmut Tschemernjak 59:38e56c85fa44 600 uint32_t SX1276::TimeOnAir( RadioModems_t modem, int16_t pktLen )
GregCr 0:e6ceb13d2d05 601 {
mluis 22:7f3aab69cca9 602 uint32_t airTime = 0;
GregCr 0:e6ceb13d2d05 603
GregCr 0:e6ceb13d2d05 604 switch( modem )
GregCr 0:e6ceb13d2d05 605 {
GregCr 0:e6ceb13d2d05 606 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 607 {
mluis 22:7f3aab69cca9 608 airTime = rint( ( 8 * ( this->settings.Fsk.PreambleLen +
GregCr 0:e6ceb13d2d05 609 ( ( Read( REG_SYNCCONFIG ) & ~RF_SYNCCONFIG_SYNCSIZE_MASK ) + 1 ) +
GregCr 0:e6ceb13d2d05 610 ( ( this->settings.Fsk.FixLen == 0x01 ) ? 0.0 : 1.0 ) +
GregCr 0:e6ceb13d2d05 611 ( ( ( Read( REG_PACKETCONFIG1 ) & ~RF_PACKETCONFIG1_ADDRSFILTERING_MASK ) != 0x00 ) ? 1.0 : 0 ) +
GregCr 0:e6ceb13d2d05 612 pktLen +
GregCr 0:e6ceb13d2d05 613 ( ( this->settings.Fsk.CrcOn == 0x01 ) ? 2.0 : 0 ) ) /
Helmut Tschemernjak 31:e50929bd3f32 614 this->settings.Fsk.Datarate ) * 1e3 );
GregCr 0:e6ceb13d2d05 615 }
GregCr 0:e6ceb13d2d05 616 break;
GregCr 0:e6ceb13d2d05 617 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 618 {
GregCr 0:e6ceb13d2d05 619 double bw = 0.0;
GregCr 0:e6ceb13d2d05 620 // REMARK: When using LoRa modem only bandwidths 125, 250 and 500 kHz are supported
GregCr 0:e6ceb13d2d05 621 switch( this->settings.LoRa.Bandwidth )
GregCr 0:e6ceb13d2d05 622 {
Helmut Tschemernjak 33:5db0d1e716b1 623 case LORA_BANKWIDTH_7kHz: // 7.8 kHz
Helmut Tschemernjak 33:5db0d1e716b1 624 bw = 78e2;
Helmut Tschemernjak 33:5db0d1e716b1 625 break;
Helmut Tschemernjak 33:5db0d1e716b1 626 case LORA_BANKWIDTH_10kHz: // 10.4 kHz
Helmut Tschemernjak 33:5db0d1e716b1 627 bw = 104e2;
Helmut Tschemernjak 33:5db0d1e716b1 628 break;
Helmut Tschemernjak 33:5db0d1e716b1 629 case LORA_BANKWIDTH_15kHz: // 15.6 kHz
Helmut Tschemernjak 33:5db0d1e716b1 630 bw = 156e2;
Helmut Tschemernjak 33:5db0d1e716b1 631 break;
Helmut Tschemernjak 33:5db0d1e716b1 632 case LORA_BANKWIDTH_20kHz: // 20.8 kHz
Helmut Tschemernjak 33:5db0d1e716b1 633 bw = 208e2;
Helmut Tschemernjak 33:5db0d1e716b1 634 break;
Helmut Tschemernjak 83:019da451b283 635 case LORA_BANKWIDTH_31kHz: // 31.25 kHz
Helmut Tschemernjak 33:5db0d1e716b1 636 bw = 312e2;
Helmut Tschemernjak 33:5db0d1e716b1 637 break;
Helmut Tschemernjak 83:019da451b283 638 case LORA_BANKWIDTH_41kHz: // 41.7 kHz
Helmut Tschemernjak 33:5db0d1e716b1 639 bw = 414e2;
Helmut Tschemernjak 33:5db0d1e716b1 640 break;
Helmut Tschemernjak 33:5db0d1e716b1 641 case LORA_BANKWIDTH_62kHz: // 62.5 kHz
Helmut Tschemernjak 33:5db0d1e716b1 642 bw = 625e2;
Helmut Tschemernjak 33:5db0d1e716b1 643 break;
Helmut Tschemernjak 33:5db0d1e716b1 644 case LORA_BANKWIDTH_125kHz: // 125 kHz
GregCr 0:e6ceb13d2d05 645 bw = 125e3;
GregCr 0:e6ceb13d2d05 646 break;
Helmut Tschemernjak 33:5db0d1e716b1 647 case LORA_BANKWIDTH_250kHz: // 250 kHz
GregCr 0:e6ceb13d2d05 648 bw = 250e3;
GregCr 0:e6ceb13d2d05 649 break;
Helmut Tschemernjak 33:5db0d1e716b1 650 case LORA_BANKWIDTH_500kHz: // 500 kHz
GregCr 0:e6ceb13d2d05 651 bw = 500e3;
GregCr 0:e6ceb13d2d05 652 break;
GregCr 0:e6ceb13d2d05 653 }
GregCr 0:e6ceb13d2d05 654
GregCr 0:e6ceb13d2d05 655 // Symbol rate : time for one symbol (secs)
GregCr 0:e6ceb13d2d05 656 double rs = bw / ( 1 << this->settings.LoRa.Datarate );
GregCr 0:e6ceb13d2d05 657 double ts = 1 / rs;
GregCr 0:e6ceb13d2d05 658 // time of preamble
GregCr 0:e6ceb13d2d05 659 double tPreamble = ( this->settings.LoRa.PreambleLen + 4.25 ) * ts;
GregCr 0:e6ceb13d2d05 660 // Symbol length of payload and time
GregCr 0:e6ceb13d2d05 661 double tmp = ceil( ( 8 * pktLen - 4 * this->settings.LoRa.Datarate +
GregCr 0:e6ceb13d2d05 662 28 + 16 * this->settings.LoRa.CrcOn -
GregCr 0:e6ceb13d2d05 663 ( this->settings.LoRa.FixLen ? 20 : 0 ) ) /
Helmut Tschemernjak 31:e50929bd3f32 664 ( double )( 4 * ( this->settings.LoRa.Datarate -
Helmut Tschemernjak 31:e50929bd3f32 665 ( ( this->settings.LoRa.LowDatarateOptimize > 0 ) ? 2 : 0 ) ) ) ) *
GregCr 0:e6ceb13d2d05 666 ( this->settings.LoRa.Coderate + 4 );
GregCr 0:e6ceb13d2d05 667 double nPayload = 8 + ( ( tmp > 0 ) ? tmp : 0 );
GregCr 0:e6ceb13d2d05 668 double tPayload = nPayload * ts;
mluis 25:3778e6204cc1 669 // Time on air
GregCr 0:e6ceb13d2d05 670 double tOnAir = tPreamble + tPayload;
Helmut Tschemernjak 31:e50929bd3f32 671 // return ms secs
Helmut Tschemernjak 31:e50929bd3f32 672 airTime = floor( tOnAir * 1e3 + 0.999 );
GregCr 0:e6ceb13d2d05 673 }
GregCr 0:e6ceb13d2d05 674 break;
GregCr 0:e6ceb13d2d05 675 }
GregCr 0:e6ceb13d2d05 676 return airTime;
GregCr 0:e6ceb13d2d05 677 }
GregCr 0:e6ceb13d2d05 678
Helmut Tschemernjak 51:aef3234bcb71 679 void SX1276::Send( void *buffer, int16_t size, void *header, int16_t hsize )
GregCr 0:e6ceb13d2d05 680 {
GregCr 0:e6ceb13d2d05 681 uint32_t txTimeout = 0;
GregCr 0:e6ceb13d2d05 682
GregCr 0:e6ceb13d2d05 683 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 684 {
GregCr 0:e6ceb13d2d05 685 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 686 {
GregCr 0:e6ceb13d2d05 687 this->settings.FskPacketHandler.NbBytes = 0;
Helmut Tschemernjak 50:43f7160e869c 688 this->settings.FskPacketHandler.Size = size + hsize;
GregCr 0:e6ceb13d2d05 689
GregCr 0:e6ceb13d2d05 690 if( this->settings.Fsk.FixLen == false )
GregCr 0:e6ceb13d2d05 691 {
Helmut Tschemernjak 50:43f7160e869c 692 uint8_t tmpsize = size + hsize;
Helmut Tschemernjak 50:43f7160e869c 693 WriteFifo( ( uint8_t* )&tmpsize, 1 );
GregCr 0:e6ceb13d2d05 694 }
GregCr 0:e6ceb13d2d05 695 else
GregCr 0:e6ceb13d2d05 696 {
Helmut Tschemernjak 50:43f7160e869c 697 Write( REG_PAYLOADLENGTH, size + hsize);
Helmut Tschemernjak 31:e50929bd3f32 698 }
mluis 25:3778e6204cc1 699
Helmut Tschemernjak 50:43f7160e869c 700 if( ( size + hsize > 0 ) && ( size + hsize <= 64 ) )
GregCr 0:e6ceb13d2d05 701 {
Helmut Tschemernjak 50:43f7160e869c 702 this->settings.FskPacketHandler.ChunkSize = size + hsize;
GregCr 0:e6ceb13d2d05 703 }
GregCr 0:e6ceb13d2d05 704 else
GregCr 0:e6ceb13d2d05 705 {
Helmut Tschemernjak 50:43f7160e869c 706 if (header) {
Helmut Tschemernjak 50:43f7160e869c 707 WriteFifo( header, hsize );
Helmut Tschemernjak 50:43f7160e869c 708 memcpy( rxtxBuffer, header, hsize );
Helmut Tschemernjak 50:43f7160e869c 709 }
Helmut Tschemernjak 51:aef3234bcb71 710 memcpy( rxtxBuffer+hsize, (uint8_t *)buffer+hsize, size );
GregCr 0:e6ceb13d2d05 711 this->settings.FskPacketHandler.ChunkSize = 32;
GregCr 0:e6ceb13d2d05 712 }
GregCr 0:e6ceb13d2d05 713
GregCr 0:e6ceb13d2d05 714 // Write payload buffer
Helmut Tschemernjak 50:43f7160e869c 715 if (header)
Helmut Tschemernjak 50:43f7160e869c 716 WriteFifo( header, hsize );
GregCr 0:e6ceb13d2d05 717 WriteFifo( buffer, this->settings.FskPacketHandler.ChunkSize );
GregCr 0:e6ceb13d2d05 718 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
GregCr 0:e6ceb13d2d05 719 txTimeout = this->settings.Fsk.TxTimeout;
GregCr 0:e6ceb13d2d05 720 }
GregCr 0:e6ceb13d2d05 721 break;
GregCr 0:e6ceb13d2d05 722 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 723 {
GregCr 0:e6ceb13d2d05 724 if( this->settings.LoRa.IqInverted == true )
GregCr 0:e6ceb13d2d05 725 {
GregCr 0:e6ceb13d2d05 726 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_ON ) );
mluis 22:7f3aab69cca9 727 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON );
GregCr 0:e6ceb13d2d05 728 }
GregCr 0:e6ceb13d2d05 729 else
GregCr 0:e6ceb13d2d05 730 {
GregCr 0:e6ceb13d2d05 731 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
mluis 22:7f3aab69cca9 732 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF );
mluis 25:3778e6204cc1 733 }
mluis 25:3778e6204cc1 734
Helmut Tschemernjak 50:43f7160e869c 735 this->settings.LoRaPacketHandler.Size = size + hsize;
GregCr 0:e6ceb13d2d05 736
GregCr 0:e6ceb13d2d05 737 // Initializes the payload size
Helmut Tschemernjak 50:43f7160e869c 738 Write( REG_LR_PAYLOADLENGTH, size + hsize);
GregCr 0:e6ceb13d2d05 739
mluis 25:3778e6204cc1 740 // Full buffer used for Tx
GregCr 0:e6ceb13d2d05 741 Write( REG_LR_FIFOTXBASEADDR, 0 );
GregCr 0:e6ceb13d2d05 742 Write( REG_LR_FIFOADDRPTR, 0 );
GregCr 0:e6ceb13d2d05 743
GregCr 0:e6ceb13d2d05 744 // FIFO operations can not take place in Sleep mode
GregCr 0:e6ceb13d2d05 745 if( ( Read( REG_OPMODE ) & ~RF_OPMODE_MASK ) == RF_OPMODE_SLEEP )
GregCr 0:e6ceb13d2d05 746 {
GregCr 0:e6ceb13d2d05 747 Standby( );
Helmut Tschemernjak 64:b721e6ab656a 748 Sleep_ms( 1 );
GregCr 0:e6ceb13d2d05 749 }
GregCr 0:e6ceb13d2d05 750 // Write payload buffer
Helmut Tschemernjak 50:43f7160e869c 751 if (header)
Helmut Tschemernjak 50:43f7160e869c 752 WriteFifo( header, hsize );
GregCr 0:e6ceb13d2d05 753 WriteFifo( buffer, size );
GregCr 0:e6ceb13d2d05 754 txTimeout = this->settings.LoRa.TxTimeout;
GregCr 0:e6ceb13d2d05 755 }
GregCr 0:e6ceb13d2d05 756 break;
GregCr 0:e6ceb13d2d05 757 }
GregCr 0:e6ceb13d2d05 758
GregCr 0:e6ceb13d2d05 759 Tx( txTimeout );
GregCr 0:e6ceb13d2d05 760 }
GregCr 0:e6ceb13d2d05 761
GregCr 0:e6ceb13d2d05 762 void SX1276::Sleep( void )
GregCr 0:e6ceb13d2d05 763 {
Helmut Tschemernjak 44:544add59b26d 764 SetTimeout(TXTimeoutTimer, NULL);
Helmut Tschemernjak 44:544add59b26d 765 SetTimeout(RXTimeoutTimer, NULL);
mluis 22:7f3aab69cca9 766
GregCr 0:e6ceb13d2d05 767 SetOpMode( RF_OPMODE_SLEEP );
mluis 22:7f3aab69cca9 768 this->settings.State = RF_IDLE;
GregCr 0:e6ceb13d2d05 769 }
GregCr 0:e6ceb13d2d05 770
GregCr 0:e6ceb13d2d05 771 void SX1276::Standby( void )
GregCr 0:e6ceb13d2d05 772 {
Helmut Tschemernjak 44:544add59b26d 773 SetTimeout(TXTimeoutTimer, NULL);
Helmut Tschemernjak 44:544add59b26d 774 SetTimeout(RXTimeoutTimer, NULL);
mluis 22:7f3aab69cca9 775
GregCr 0:e6ceb13d2d05 776 SetOpMode( RF_OPMODE_STANDBY );
mluis 22:7f3aab69cca9 777 this->settings.State = RF_IDLE;
GregCr 0:e6ceb13d2d05 778 }
GregCr 0:e6ceb13d2d05 779
GregCr 0:e6ceb13d2d05 780 void SX1276::Rx( uint32_t timeout )
GregCr 0:e6ceb13d2d05 781 {
GregCr 0:e6ceb13d2d05 782 bool rxContinuous = false;
mluis 22:7f3aab69cca9 783
GregCr 0:e6ceb13d2d05 784 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 785 {
GregCr 0:e6ceb13d2d05 786 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 787 {
GregCr 0:e6ceb13d2d05 788 rxContinuous = this->settings.Fsk.RxContinuous;
mluis 25:3778e6204cc1 789
GregCr 0:e6ceb13d2d05 790 // DIO0=PayloadReady
GregCr 0:e6ceb13d2d05 791 // DIO1=FifoLevel
GregCr 0:e6ceb13d2d05 792 // DIO2=SyncAddr
GregCr 0:e6ceb13d2d05 793 // DIO3=FifoEmpty
GregCr 0:e6ceb13d2d05 794 // DIO4=Preamble
GregCr 0:e6ceb13d2d05 795 // DIO5=ModeReady
mluis 22:7f3aab69cca9 796 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK &
GregCr 23:1e143575df0f 797 RF_DIOMAPPING1_DIO1_MASK &
GregCr 0:e6ceb13d2d05 798 RF_DIOMAPPING1_DIO2_MASK ) |
GregCr 0:e6ceb13d2d05 799 RF_DIOMAPPING1_DIO0_00 |
mluis 25:3778e6204cc1 800 RF_DIOMAPPING1_DIO1_00 |
GregCr 0:e6ceb13d2d05 801 RF_DIOMAPPING1_DIO2_11 );
mluis 25:3778e6204cc1 802
GregCr 0:e6ceb13d2d05 803 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
mluis 25:3778e6204cc1 804 RF_DIOMAPPING2_MAP_MASK ) |
GregCr 0:e6ceb13d2d05 805 RF_DIOMAPPING2_DIO4_11 |
GregCr 0:e6ceb13d2d05 806 RF_DIOMAPPING2_MAP_PREAMBLEDETECT );
mluis 25:3778e6204cc1 807
GregCr 0:e6ceb13d2d05 808 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
mluis 25:3778e6204cc1 809
mluis 25:3778e6204cc1 810 Write( REG_RXCONFIG, RF_RXCONFIG_AFCAUTO_ON | RF_RXCONFIG_AGCAUTO_ON | RF_RXCONFIG_RXTRIGER_PREAMBLEDETECT );
mluis 25:3778e6204cc1 811
GregCr 0:e6ceb13d2d05 812 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 0:e6ceb13d2d05 813 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 0:e6ceb13d2d05 814 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 815 this->settings.FskPacketHandler.Size = 0;
GregCr 0:e6ceb13d2d05 816 }
GregCr 0:e6ceb13d2d05 817 break;
GregCr 0:e6ceb13d2d05 818 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 819 {
GregCr 0:e6ceb13d2d05 820 if( this->settings.LoRa.IqInverted == true )
GregCr 0:e6ceb13d2d05 821 {
GregCr 0:e6ceb13d2d05 822 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_ON | RFLR_INVERTIQ_TX_OFF ) );
mluis 22:7f3aab69cca9 823 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_ON );
GregCr 0:e6ceb13d2d05 824 }
GregCr 0:e6ceb13d2d05 825 else
GregCr 0:e6ceb13d2d05 826 {
GregCr 0:e6ceb13d2d05 827 Write( REG_LR_INVERTIQ, ( ( Read( REG_LR_INVERTIQ ) & RFLR_INVERTIQ_TX_MASK & RFLR_INVERTIQ_RX_MASK ) | RFLR_INVERTIQ_RX_OFF | RFLR_INVERTIQ_TX_OFF ) );
mluis 22:7f3aab69cca9 828 Write( REG_LR_INVERTIQ2, RFLR_INVERTIQ2_OFF );
Helmut Tschemernjak 31:e50929bd3f32 829 }
mluis 22:7f3aab69cca9 830
mluis 22:7f3aab69cca9 831 // ERRATA 2.3 - Receiver Spurious Reception of a LoRa Signal
Helmut Tschemernjak 33:5db0d1e716b1 832 if( this->settings.LoRa.Bandwidth < LORA_BANKWIDTH_500kHz )
mluis 22:7f3aab69cca9 833 {
mluis 22:7f3aab69cca9 834 Write( REG_LR_DETECTOPTIMIZE, Read( REG_LR_DETECTOPTIMIZE ) & 0x7F );
mluis 22:7f3aab69cca9 835 Write( REG_LR_TEST30, 0x00 );
mluis 22:7f3aab69cca9 836 switch( this->settings.LoRa.Bandwidth )
mluis 22:7f3aab69cca9 837 {
Helmut Tschemernjak 33:5db0d1e716b1 838 case LORA_BANKWIDTH_7kHz: // 7.8 kHz
mluis 22:7f3aab69cca9 839 Write( REG_LR_TEST2F, 0x48 );
mluis 22:7f3aab69cca9 840 SetChannel(this->settings.Channel + 7.81e3 );
mluis 22:7f3aab69cca9 841 break;
Helmut Tschemernjak 33:5db0d1e716b1 842 case LORA_BANKWIDTH_10kHz: // 10.4 kHz
mluis 22:7f3aab69cca9 843 Write( REG_LR_TEST2F, 0x44 );
mluis 22:7f3aab69cca9 844 SetChannel(this->settings.Channel + 10.42e3 );
mluis 22:7f3aab69cca9 845 break;
Helmut Tschemernjak 33:5db0d1e716b1 846 case LORA_BANKWIDTH_15kHz: // 15.6 kHz
mluis 22:7f3aab69cca9 847 Write( REG_LR_TEST2F, 0x44 );
mluis 22:7f3aab69cca9 848 SetChannel(this->settings.Channel + 15.62e3 );
mluis 22:7f3aab69cca9 849 break;
Helmut Tschemernjak 33:5db0d1e716b1 850 case LORA_BANKWIDTH_20kHz: // 20.8 kHz
mluis 22:7f3aab69cca9 851 Write( REG_LR_TEST2F, 0x44 );
mluis 22:7f3aab69cca9 852 SetChannel(this->settings.Channel + 20.83e3 );
mluis 22:7f3aab69cca9 853 break;
Helmut Tschemernjak 83:019da451b283 854 case LORA_BANKWIDTH_31kHz: // 31.25 kHz
mluis 22:7f3aab69cca9 855 Write( REG_LR_TEST2F, 0x44 );
mluis 22:7f3aab69cca9 856 SetChannel(this->settings.Channel + 31.25e3 );
mluis 22:7f3aab69cca9 857 break;
Helmut Tschemernjak 33:5db0d1e716b1 858 case LORA_BANKWIDTH_41kHz: // 41.4 kHz
mluis 22:7f3aab69cca9 859 Write( REG_LR_TEST2F, 0x44 );
mluis 22:7f3aab69cca9 860 SetChannel(this->settings.Channel + 41.67e3 );
mluis 22:7f3aab69cca9 861 break;
Helmut Tschemernjak 33:5db0d1e716b1 862 case LORA_BANKWIDTH_62kHz: // 62.5 kHz
mluis 22:7f3aab69cca9 863 Write( REG_LR_TEST2F, 0x40 );
mluis 22:7f3aab69cca9 864 break;
Helmut Tschemernjak 33:5db0d1e716b1 865 case LORA_BANKWIDTH_125kHz: // 125 kHz
mluis 22:7f3aab69cca9 866 Write( REG_LR_TEST2F, 0x40 );
mluis 22:7f3aab69cca9 867 break;
Helmut Tschemernjak 33:5db0d1e716b1 868 case LORA_BANKWIDTH_250kHz: // 250 kHz
mluis 22:7f3aab69cca9 869 Write( REG_LR_TEST2F, 0x40 );
mluis 22:7f3aab69cca9 870 break;
mluis 22:7f3aab69cca9 871 }
mluis 22:7f3aab69cca9 872 }
mluis 22:7f3aab69cca9 873 else
mluis 22:7f3aab69cca9 874 {
mluis 22:7f3aab69cca9 875 Write( REG_LR_DETECTOPTIMIZE, Read( REG_LR_DETECTOPTIMIZE ) | 0x80 );
mluis 22:7f3aab69cca9 876 }
mluis 22:7f3aab69cca9 877
GregCr 0:e6ceb13d2d05 878 rxContinuous = this->settings.LoRa.RxContinuous;
mluis 25:3778e6204cc1 879
GregCr 6:e7f02929cd3d 880 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 881 {
GregCr 6:e7f02929cd3d 882 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
mluis 22:7f3aab69cca9 883 //RFLR_IRQFLAGS_RXDONE |
mluis 22:7f3aab69cca9 884 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 22:7f3aab69cca9 885 RFLR_IRQFLAGS_VALIDHEADER |
mluis 22:7f3aab69cca9 886 RFLR_IRQFLAGS_TXDONE |
mluis 22:7f3aab69cca9 887 RFLR_IRQFLAGS_CADDONE |
mluis 22:7f3aab69cca9 888 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 22:7f3aab69cca9 889 RFLR_IRQFLAGS_CADDETECTED );
mluis 25:3778e6204cc1 890
mluis 13:618826a997e2 891 // DIO0=RxDone, DIO2=FhssChangeChannel
mluis 13:618826a997e2 892 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_00 | RFLR_DIOMAPPING1_DIO2_00 );
GregCr 6:e7f02929cd3d 893 }
GregCr 6:e7f02929cd3d 894 else
GregCr 6:e7f02929cd3d 895 {
GregCr 6:e7f02929cd3d 896 Write( REG_LR_IRQFLAGSMASK, //RFLR_IRQFLAGS_RXTIMEOUT |
mluis 22:7f3aab69cca9 897 //RFLR_IRQFLAGS_RXDONE |
mluis 22:7f3aab69cca9 898 //RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 22:7f3aab69cca9 899 RFLR_IRQFLAGS_VALIDHEADER |
mluis 22:7f3aab69cca9 900 RFLR_IRQFLAGS_TXDONE |
mluis 22:7f3aab69cca9 901 RFLR_IRQFLAGS_CADDONE |
mluis 22:7f3aab69cca9 902 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 22:7f3aab69cca9 903 RFLR_IRQFLAGS_CADDETECTED );
mluis 25:3778e6204cc1 904
GregCr 6:e7f02929cd3d 905 // DIO0=RxDone
GregCr 6:e7f02929cd3d 906 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_00 );
GregCr 6:e7f02929cd3d 907 }
GregCr 0:e6ceb13d2d05 908 Write( REG_LR_FIFORXBASEADDR, 0 );
GregCr 0:e6ceb13d2d05 909 Write( REG_LR_FIFOADDRPTR, 0 );
GregCr 0:e6ceb13d2d05 910 }
GregCr 0:e6ceb13d2d05 911 break;
GregCr 0:e6ceb13d2d05 912 }
Helmut Tschemernjak 58:113d2ef978d2 913
mluis 21:2e496deb7858 914 this->settings.State = RF_RX_RUNNING;
GregCr 0:e6ceb13d2d05 915 if( timeout != 0 )
GregCr 0:e6ceb13d2d05 916 {
Helmut Tschemernjak 44:544add59b26d 917 SetTimeout(RXTimeoutTimer, &SX1276::OnTimeoutIrq, timeout * 1e3);
GregCr 0:e6ceb13d2d05 918 }
GregCr 0:e6ceb13d2d05 919
GregCr 0:e6ceb13d2d05 920 if( this->settings.Modem == MODEM_FSK )
GregCr 0:e6ceb13d2d05 921 {
GregCr 0:e6ceb13d2d05 922 SetOpMode( RF_OPMODE_RECEIVER );
mluis 25:3778e6204cc1 923
GregCr 0:e6ceb13d2d05 924 if( rxContinuous == false )
GregCr 0:e6ceb13d2d05 925 {
Helmut Tschemernjak 53:6d3adad59633 926 SetTimeout(RXTimeoutSyncWordTimer, &SX1276::OnTimeoutIrq, this->settings.Fsk.RxSingleTimeout * 1e3);
GregCr 0:e6ceb13d2d05 927 }
GregCr 0:e6ceb13d2d05 928 }
GregCr 0:e6ceb13d2d05 929 else
GregCr 0:e6ceb13d2d05 930 {
GregCr 0:e6ceb13d2d05 931 if( rxContinuous == true )
GregCr 0:e6ceb13d2d05 932 {
GregCr 0:e6ceb13d2d05 933 SetOpMode( RFLR_OPMODE_RECEIVER );
GregCr 0:e6ceb13d2d05 934 }
GregCr 0:e6ceb13d2d05 935 else
GregCr 0:e6ceb13d2d05 936 {
GregCr 0:e6ceb13d2d05 937 SetOpMode( RFLR_OPMODE_RECEIVER_SINGLE );
GregCr 0:e6ceb13d2d05 938 }
GregCr 0:e6ceb13d2d05 939 }
GregCr 0:e6ceb13d2d05 940 }
GregCr 0:e6ceb13d2d05 941
Helmut Tschemernjak 54:0d8ea87fbab9 942 bool SX1276::RxSignalPending()
Helmut Tschemernjak 54:0d8ea87fbab9 943 {
Helmut Tschemernjak 54:0d8ea87fbab9 944 if (this->settings.State != RF_RX_RUNNING)
Helmut Tschemernjak 54:0d8ea87fbab9 945 return false;
Helmut Tschemernjak 54:0d8ea87fbab9 946
Helmut Tschemernjak 54:0d8ea87fbab9 947 switch( this->settings.Modem )
Helmut Tschemernjak 54:0d8ea87fbab9 948 {
Helmut Tschemernjak 54:0d8ea87fbab9 949 case MODEM_FSK:
Helmut Tschemernjak 54:0d8ea87fbab9 950 break;
Helmut Tschemernjak 54:0d8ea87fbab9 951 case MODEM_LORA:
Helmut Tschemernjak 81:d288917af0ce 952 if (Read(REG_LR_MODEMSTAT) & (RFLR_MODEMSTAT_SIGNAL_DETECTED|RFLR_MODEMSTAT_SIGNAL_SYNCRONIZED|RFLR_MODEMSTAT_HEADERINFO_VALID|RFLR_MODEMSTAT_MODEM_CLEAR))
Helmut Tschemernjak 81:d288917af0ce 953 return true;
Helmut Tschemernjak 54:0d8ea87fbab9 954 break;
Helmut Tschemernjak 54:0d8ea87fbab9 955 }
Helmut Tschemernjak 54:0d8ea87fbab9 956 return false;
Helmut Tschemernjak 54:0d8ea87fbab9 957 }
Helmut Tschemernjak 54:0d8ea87fbab9 958
GregCr 0:e6ceb13d2d05 959 void SX1276::Tx( uint32_t timeout )
mluis 22:7f3aab69cca9 960 {
mluis 22:7f3aab69cca9 961
GregCr 0:e6ceb13d2d05 962 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 963 {
GregCr 0:e6ceb13d2d05 964 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 965 {
GregCr 0:e6ceb13d2d05 966 // DIO0=PacketSent
GregCr 23:1e143575df0f 967 // DIO1=FifoEmpty
GregCr 0:e6ceb13d2d05 968 // DIO2=FifoFull
GregCr 0:e6ceb13d2d05 969 // DIO3=FifoEmpty
GregCr 0:e6ceb13d2d05 970 // DIO4=LowBat
GregCr 0:e6ceb13d2d05 971 // DIO5=ModeReady
mluis 22:7f3aab69cca9 972 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RF_DIOMAPPING1_DIO0_MASK &
Helmut Tschemernjak 31:e50929bd3f32 973 RF_DIOMAPPING1_DIO1_MASK &
Helmut Tschemernjak 31:e50929bd3f32 974 RF_DIOMAPPING1_DIO2_MASK ) |
Helmut Tschemernjak 31:e50929bd3f32 975 RF_DIOMAPPING1_DIO1_01 );
GregCr 0:e6ceb13d2d05 976
GregCr 0:e6ceb13d2d05 977 Write( REG_DIOMAPPING2, ( Read( REG_DIOMAPPING2 ) & RF_DIOMAPPING2_DIO4_MASK &
GregCr 0:e6ceb13d2d05 978 RF_DIOMAPPING2_MAP_MASK ) );
GregCr 0:e6ceb13d2d05 979 this->settings.FskPacketHandler.FifoThresh = Read( REG_FIFOTHRESH ) & 0x3F;
GregCr 0:e6ceb13d2d05 980 }
GregCr 0:e6ceb13d2d05 981 break;
GregCr 0:e6ceb13d2d05 982 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 983 {
GregCr 6:e7f02929cd3d 984 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 985 {
GregCr 6:e7f02929cd3d 986 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
mluis 22:7f3aab69cca9 987 RFLR_IRQFLAGS_RXDONE |
mluis 22:7f3aab69cca9 988 RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 22:7f3aab69cca9 989 RFLR_IRQFLAGS_VALIDHEADER |
mluis 22:7f3aab69cca9 990 //RFLR_IRQFLAGS_TXDONE |
mluis 22:7f3aab69cca9 991 RFLR_IRQFLAGS_CADDONE |
mluis 22:7f3aab69cca9 992 //RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 22:7f3aab69cca9 993 RFLR_IRQFLAGS_CADDETECTED );
mluis 25:3778e6204cc1 994
mluis 22:7f3aab69cca9 995 // DIO0=TxDone, DIO2=FhssChangeChannel
mluis 22:7f3aab69cca9 996 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK & RFLR_DIOMAPPING1_DIO2_MASK ) | RFLR_DIOMAPPING1_DIO0_01 | RFLR_DIOMAPPING1_DIO2_00 );
GregCr 6:e7f02929cd3d 997 }
GregCr 6:e7f02929cd3d 998 else
GregCr 6:e7f02929cd3d 999 {
GregCr 6:e7f02929cd3d 1000 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
mluis 22:7f3aab69cca9 1001 RFLR_IRQFLAGS_RXDONE |
mluis 22:7f3aab69cca9 1002 RFLR_IRQFLAGS_PAYLOADCRCERROR |
mluis 22:7f3aab69cca9 1003 RFLR_IRQFLAGS_VALIDHEADER |
mluis 22:7f3aab69cca9 1004 //RFLR_IRQFLAGS_TXDONE |
mluis 22:7f3aab69cca9 1005 RFLR_IRQFLAGS_CADDONE |
mluis 22:7f3aab69cca9 1006 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL |
mluis 22:7f3aab69cca9 1007 RFLR_IRQFLAGS_CADDETECTED );
mluis 22:7f3aab69cca9 1008
GregCr 6:e7f02929cd3d 1009 // DIO0=TxDone
mluis 22:7f3aab69cca9 1010 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO0_MASK ) | RFLR_DIOMAPPING1_DIO0_01 );
GregCr 6:e7f02929cd3d 1011 }
GregCr 0:e6ceb13d2d05 1012 }
GregCr 0:e6ceb13d2d05 1013 break;
GregCr 0:e6ceb13d2d05 1014 }
GregCr 0:e6ceb13d2d05 1015
mluis 21:2e496deb7858 1016 this->settings.State = RF_TX_RUNNING;
Helmut Tschemernjak 44:544add59b26d 1017 SetTimeout(TXTimeoutTimer, &SX1276::OnTimeoutIrq, timeout * 1e3);
GregCr 0:e6ceb13d2d05 1018 SetOpMode( RF_OPMODE_TRANSMITTER );
GregCr 0:e6ceb13d2d05 1019 }
GregCr 0:e6ceb13d2d05 1020
GregCr 7:2b555111463f 1021 void SX1276::StartCad( void )
GregCr 0:e6ceb13d2d05 1022 {
GregCr 7:2b555111463f 1023 switch( this->settings.Modem )
GregCr 7:2b555111463f 1024 {
GregCr 7:2b555111463f 1025 case MODEM_FSK:
GregCr 7:2b555111463f 1026 {
mluis 25:3778e6204cc1 1027
GregCr 7:2b555111463f 1028 }
GregCr 7:2b555111463f 1029 break;
GregCr 7:2b555111463f 1030 case MODEM_LORA:
GregCr 7:2b555111463f 1031 {
GregCr 7:2b555111463f 1032 Write( REG_LR_IRQFLAGSMASK, RFLR_IRQFLAGS_RXTIMEOUT |
GregCr 7:2b555111463f 1033 RFLR_IRQFLAGS_RXDONE |
GregCr 7:2b555111463f 1034 RFLR_IRQFLAGS_PAYLOADCRCERROR |
GregCr 7:2b555111463f 1035 RFLR_IRQFLAGS_VALIDHEADER |
GregCr 7:2b555111463f 1036 RFLR_IRQFLAGS_TXDONE |
GregCr 7:2b555111463f 1037 //RFLR_IRQFLAGS_CADDONE |
GregCr 12:aa5b3bf7fdf4 1038 RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL // |
Helmut Tschemernjak 31:e50929bd3f32 1039 //RFLR_IRQFLAGS_CADDETECTED
GregCr 12:aa5b3bf7fdf4 1040 );
mluis 25:3778e6204cc1 1041
GregCr 7:2b555111463f 1042 // DIO3=CADDone
Helmut Tschemernjak 31:e50929bd3f32 1043 Write( REG_DIOMAPPING1, ( Read( REG_DIOMAPPING1 ) & RFLR_DIOMAPPING1_DIO3_MASK ) | RFLR_DIOMAPPING1_DIO3_00 );
mluis 25:3778e6204cc1 1044
mluis 21:2e496deb7858 1045 this->settings.State = RF_CAD;
GregCr 7:2b555111463f 1046 SetOpMode( RFLR_OPMODE_CAD );
GregCr 7:2b555111463f 1047 }
GregCr 7:2b555111463f 1048 break;
GregCr 7:2b555111463f 1049 default:
GregCr 7:2b555111463f 1050 break;
GregCr 7:2b555111463f 1051 }
GregCr 7:2b555111463f 1052 }
GregCr 7:2b555111463f 1053
Helmut Tschemernjak 31:e50929bd3f32 1054 void SX1276::SetTxContinuousWave( uint32_t freq, int8_t power, uint16_t time )
Helmut Tschemernjak 31:e50929bd3f32 1055 {
Helmut Tschemernjak 31:e50929bd3f32 1056 uint32_t timeout = ( uint32_t )( time * 1e6 );
Helmut Tschemernjak 31:e50929bd3f32 1057
Helmut Tschemernjak 31:e50929bd3f32 1058 SetChannel( freq );
Helmut Tschemernjak 31:e50929bd3f32 1059
Helmut Tschemernjak 31:e50929bd3f32 1060 SetTxConfig( MODEM_FSK, power, 0, 0, 4800, 0, 5, false, false, 0, 0, 0, timeout );
Helmut Tschemernjak 31:e50929bd3f32 1061
Helmut Tschemernjak 31:e50929bd3f32 1062 Write( REG_PACKETCONFIG2, ( Read( REG_PACKETCONFIG2 ) & RF_PACKETCONFIG2_DATAMODE_MASK ) );
Helmut Tschemernjak 31:e50929bd3f32 1063 // Disable radio interrupts
Helmut Tschemernjak 31:e50929bd3f32 1064 Write( REG_DIOMAPPING1, RF_DIOMAPPING1_DIO0_11 | RF_DIOMAPPING1_DIO1_11 );
Helmut Tschemernjak 31:e50929bd3f32 1065 Write( REG_DIOMAPPING2, RF_DIOMAPPING2_DIO4_10 | RF_DIOMAPPING2_DIO5_10 );
Helmut Tschemernjak 31:e50929bd3f32 1066
Helmut Tschemernjak 31:e50929bd3f32 1067 this->settings.State = RF_TX_RUNNING;
Helmut Tschemernjak 44:544add59b26d 1068 SetTimeout(TXTimeoutTimer, &SX1276::OnTimeoutIrq, timeout);
Helmut Tschemernjak 31:e50929bd3f32 1069 SetOpMode( RF_OPMODE_TRANSMITTER );
Helmut Tschemernjak 31:e50929bd3f32 1070 }
Helmut Tschemernjak 31:e50929bd3f32 1071
Helmut Tschemernjak 50:43f7160e869c 1072 int16_t SX1276::MaxMTUSize( RadioModems_t modem )
Helmut Tschemernjak 50:43f7160e869c 1073 {
Helmut Tschemernjak 50:43f7160e869c 1074 int16_t mtuSize = 0;
Helmut Tschemernjak 50:43f7160e869c 1075
Helmut Tschemernjak 50:43f7160e869c 1076 switch( modem )
Helmut Tschemernjak 50:43f7160e869c 1077 {
Helmut Tschemernjak 50:43f7160e869c 1078 case MODEM_FSK:
Helmut Tschemernjak 50:43f7160e869c 1079 mtuSize = RX_BUFFER_SIZE;
Helmut Tschemernjak 50:43f7160e869c 1080 case MODEM_LORA:
Helmut Tschemernjak 50:43f7160e869c 1081 mtuSize = RX_BUFFER_SIZE;
Helmut Tschemernjak 50:43f7160e869c 1082 break;
Helmut Tschemernjak 50:43f7160e869c 1083 default:
Helmut Tschemernjak 50:43f7160e869c 1084 mtuSize = -1;
Helmut Tschemernjak 50:43f7160e869c 1085 break;
Helmut Tschemernjak 50:43f7160e869c 1086 }
Helmut Tschemernjak 50:43f7160e869c 1087 return mtuSize;
Helmut Tschemernjak 50:43f7160e869c 1088 }
Helmut Tschemernjak 50:43f7160e869c 1089
mluis 22:7f3aab69cca9 1090 int16_t SX1276::GetRssi( RadioModems_t modem )
GregCr 7:2b555111463f 1091 {
GregCr 7:2b555111463f 1092 int16_t rssi = 0;
GregCr 0:e6ceb13d2d05 1093
GregCr 0:e6ceb13d2d05 1094 switch( modem )
GregCr 0:e6ceb13d2d05 1095 {
GregCr 0:e6ceb13d2d05 1096 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1097 rssi = -( Read( REG_RSSIVALUE ) >> 1 );
GregCr 0:e6ceb13d2d05 1098 break;
GregCr 0:e6ceb13d2d05 1099 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1100 if( this->settings.Channel > RF_MID_BAND_THRESH )
GregCr 0:e6ceb13d2d05 1101 {
GregCr 0:e6ceb13d2d05 1102 rssi = RSSI_OFFSET_HF + Read( REG_LR_RSSIVALUE );
GregCr 0:e6ceb13d2d05 1103 }
GregCr 0:e6ceb13d2d05 1104 else
GregCr 0:e6ceb13d2d05 1105 {
GregCr 0:e6ceb13d2d05 1106 rssi = RSSI_OFFSET_LF + Read( REG_LR_RSSIVALUE );
GregCr 0:e6ceb13d2d05 1107 }
GregCr 0:e6ceb13d2d05 1108 break;
GregCr 0:e6ceb13d2d05 1109 default:
GregCr 0:e6ceb13d2d05 1110 rssi = -1;
GregCr 0:e6ceb13d2d05 1111 break;
GregCr 0:e6ceb13d2d05 1112 }
GregCr 0:e6ceb13d2d05 1113 return rssi;
GregCr 0:e6ceb13d2d05 1114 }
GregCr 0:e6ceb13d2d05 1115
Helmut Tschemernjak 83:019da451b283 1116 int32_t SX1276::GetFrequencyError(RadioModems_t modem )
Helmut Tschemernjak 83:019da451b283 1117 {
Helmut Tschemernjak 83:019da451b283 1118 int32_t val = 0;
Helmut Tschemernjak 83:019da451b283 1119
Helmut Tschemernjak 83:019da451b283 1120 if (modem != MODEM_LORA)
Helmut Tschemernjak 83:019da451b283 1121 return 0;
Helmut Tschemernjak 83:019da451b283 1122
Helmut Tschemernjak 83:019da451b283 1123 val = (Read(REG_LR_FEIMSB) & 0b1111) << 16; // high word, 4 valid bits only
Helmut Tschemernjak 89:b0203b4a36ec 1124 val |= ((Read(REG_LR_FEIMID) << 8) | Read(REG_LR_FEILSB)); // high byte, low byte
Helmut Tschemernjak 89:b0203b4a36ec 1125 if (val & 0x80000) //convert sign bit
Helmut Tschemernjak 83:019da451b283 1126 val |= 0xfff00000;
Helmut Tschemernjak 83:019da451b283 1127
Helmut Tschemernjak 83:019da451b283 1128 int32_t bandwidth = 0;
Helmut Tschemernjak 83:019da451b283 1129 for (int i = 0; i < (int)(sizeof(LoRaBandwidths) / sizeof(BandwidthMap)) -1; i++ ) {
Helmut Tschemernjak 83:019da451b283 1130 if (LoRaBandwidths[i].RegValue == this->settings.LoRa.Bandwidth) {
Helmut Tschemernjak 83:019da451b283 1131 bandwidth = LoRaBandwidths[i].bandwidth;
Helmut Tschemernjak 83:019da451b283 1132 break;
Helmut Tschemernjak 83:019da451b283 1133 }
Helmut Tschemernjak 83:019da451b283 1134 }
Helmut Tschemernjak 83:019da451b283 1135 if (!bandwidth)
Helmut Tschemernjak 83:019da451b283 1136 return 0;
Helmut Tschemernjak 83:019da451b283 1137
Helmut Tschemernjak 83:019da451b283 1138 float bandWidthkHz = (float)bandwidth/1000;
Helmut Tschemernjak 83:019da451b283 1139
Helmut Tschemernjak 83:019da451b283 1140 int32_t hz = (((float)val * (float)(1<<24)) / ((float)XTAL_FREQ)) * (bandWidthkHz / 500.0);
Helmut Tschemernjak 83:019da451b283 1141
Helmut Tschemernjak 83:019da451b283 1142 return hz;
Helmut Tschemernjak 83:019da451b283 1143 }
Helmut Tschemernjak 83:019da451b283 1144
Helmut Tschemernjak 83:019da451b283 1145
GregCr 0:e6ceb13d2d05 1146 void SX1276::SetOpMode( uint8_t opMode )
GregCr 0:e6ceb13d2d05 1147 {
mluis 25:3778e6204cc1 1148 if( opMode == RF_OPMODE_SLEEP )
GregCr 0:e6ceb13d2d05 1149 {
mluis 25:3778e6204cc1 1150 SetAntSwLowPower( true );
mluis 25:3778e6204cc1 1151 }
mluis 25:3778e6204cc1 1152 else
mluis 25:3778e6204cc1 1153 {
mluis 25:3778e6204cc1 1154 SetAntSwLowPower( false );
Helmut Tschemernjak 31:e50929bd3f32 1155 SetAntSw( opMode );
GregCr 0:e6ceb13d2d05 1156 }
mluis 25:3778e6204cc1 1157 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RF_OPMODE_MASK ) | opMode );
GregCr 0:e6ceb13d2d05 1158 }
GregCr 0:e6ceb13d2d05 1159
mluis 22:7f3aab69cca9 1160 void SX1276::SetModem( RadioModems_t modem )
GregCr 0:e6ceb13d2d05 1161 {
Helmut Tschemernjak 31:e50929bd3f32 1162 if( ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_ON ) != 0 )
Helmut Tschemernjak 31:e50929bd3f32 1163 {
Helmut Tschemernjak 31:e50929bd3f32 1164 this->settings.Modem = MODEM_LORA;
Helmut Tschemernjak 31:e50929bd3f32 1165 }
Helmut Tschemernjak 31:e50929bd3f32 1166 else
Helmut Tschemernjak 31:e50929bd3f32 1167 {
Helmut Tschemernjak 31:e50929bd3f32 1168 this->settings.Modem = MODEM_FSK;
Helmut Tschemernjak 31:e50929bd3f32 1169 }
Helmut Tschemernjak 31:e50929bd3f32 1170
mluis 22:7f3aab69cca9 1171 if( this->settings.Modem == modem )
mluis 22:7f3aab69cca9 1172 {
mluis 22:7f3aab69cca9 1173 return;
mluis 22:7f3aab69cca9 1174 }
mluis 22:7f3aab69cca9 1175
mluis 22:7f3aab69cca9 1176 this->settings.Modem = modem;
mluis 22:7f3aab69cca9 1177 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1178 {
mluis 22:7f3aab69cca9 1179 default:
mluis 22:7f3aab69cca9 1180 case MODEM_FSK:
Helmut Tschemernjak 31:e50929bd3f32 1181 Sleep( );
mluis 22:7f3aab69cca9 1182 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_OFF );
mluis 22:7f3aab69cca9 1183
mluis 22:7f3aab69cca9 1184 Write( REG_DIOMAPPING1, 0x00 );
mluis 22:7f3aab69cca9 1185 Write( REG_DIOMAPPING2, 0x30 ); // DIO5=ModeReady
mluis 22:7f3aab69cca9 1186 break;
mluis 22:7f3aab69cca9 1187 case MODEM_LORA:
Helmut Tschemernjak 31:e50929bd3f32 1188 Sleep( );
mluis 22:7f3aab69cca9 1189 Write( REG_OPMODE, ( Read( REG_OPMODE ) & RFLR_OPMODE_LONGRANGEMODE_MASK ) | RFLR_OPMODE_LONGRANGEMODE_ON );
mluis 22:7f3aab69cca9 1190
mluis 22:7f3aab69cca9 1191 Write( REG_DIOMAPPING1, 0x00 );
mluis 22:7f3aab69cca9 1192 Write( REG_DIOMAPPING2, 0x00 );
mluis 22:7f3aab69cca9 1193 break;
GregCr 0:e6ceb13d2d05 1194 }
GregCr 0:e6ceb13d2d05 1195 }
GregCr 0:e6ceb13d2d05 1196
mluis 22:7f3aab69cca9 1197 void SX1276::SetMaxPayloadLength( RadioModems_t modem, uint8_t max )
mluis 20:e05596ba4166 1198 {
mluis 20:e05596ba4166 1199 this->SetModem( modem );
mluis 20:e05596ba4166 1200
mluis 20:e05596ba4166 1201 switch( modem )
mluis 20:e05596ba4166 1202 {
mluis 20:e05596ba4166 1203 case MODEM_FSK:
mluis 20:e05596ba4166 1204 if( this->settings.Fsk.FixLen == false )
mluis 20:e05596ba4166 1205 {
mluis 20:e05596ba4166 1206 this->Write( REG_PAYLOADLENGTH, max );
mluis 20:e05596ba4166 1207 }
mluis 20:e05596ba4166 1208 break;
mluis 20:e05596ba4166 1209 case MODEM_LORA:
mluis 20:e05596ba4166 1210 this->Write( REG_LR_PAYLOADMAXLENGTH, max );
mluis 20:e05596ba4166 1211 break;
mluis 20:e05596ba4166 1212 }
mluis 20:e05596ba4166 1213 }
mluis 20:e05596ba4166 1214
Helmut Tschemernjak 31:e50929bd3f32 1215 void SX1276::SetPublicNetwork( bool enable )
Helmut Tschemernjak 31:e50929bd3f32 1216 {
Helmut Tschemernjak 31:e50929bd3f32 1217 SetModem( MODEM_LORA );
Helmut Tschemernjak 31:e50929bd3f32 1218 this->settings.LoRa.PublicNetwork = enable;
Helmut Tschemernjak 31:e50929bd3f32 1219 if( enable == true )
Helmut Tschemernjak 31:e50929bd3f32 1220 {
Helmut Tschemernjak 31:e50929bd3f32 1221 // Change LoRa modem SyncWord
Helmut Tschemernjak 31:e50929bd3f32 1222 Write( REG_LR_SYNCWORD, LORA_MAC_PUBLIC_SYNCWORD );
Helmut Tschemernjak 31:e50929bd3f32 1223 }
Helmut Tschemernjak 31:e50929bd3f32 1224 else
Helmut Tschemernjak 31:e50929bd3f32 1225 {
Helmut Tschemernjak 31:e50929bd3f32 1226 // Change LoRa modem SyncWord
Helmut Tschemernjak 31:e50929bd3f32 1227 Write( REG_LR_SYNCWORD, LORA_MAC_PRIVATE_SYNCWORD );
Helmut Tschemernjak 31:e50929bd3f32 1228 }
Helmut Tschemernjak 31:e50929bd3f32 1229 }
Helmut Tschemernjak 31:e50929bd3f32 1230
Helmut Tschemernjak 31:e50929bd3f32 1231
GregCr 0:e6ceb13d2d05 1232 void SX1276::OnTimeoutIrq( void )
GregCr 0:e6ceb13d2d05 1233 {
GregCr 0:e6ceb13d2d05 1234 switch( this->settings.State )
GregCr 0:e6ceb13d2d05 1235 {
mluis 21:2e496deb7858 1236 case RF_RX_RUNNING:
GregCr 0:e6ceb13d2d05 1237 if( this->settings.Modem == MODEM_FSK )
GregCr 0:e6ceb13d2d05 1238 {
GregCr 0:e6ceb13d2d05 1239 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 0:e6ceb13d2d05 1240 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 0:e6ceb13d2d05 1241 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 1242 this->settings.FskPacketHandler.Size = 0;
GregCr 0:e6ceb13d2d05 1243
GregCr 0:e6ceb13d2d05 1244 // Clear Irqs
Helmut Tschemernjak 31:e50929bd3f32 1245 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
GregCr 0:e6ceb13d2d05 1246 RF_IRQFLAGS1_PREAMBLEDETECT |
GregCr 0:e6ceb13d2d05 1247 RF_IRQFLAGS1_SYNCADDRESSMATCH );
GregCr 0:e6ceb13d2d05 1248 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
GregCr 0:e6ceb13d2d05 1249
GregCr 0:e6ceb13d2d05 1250 if( this->settings.Fsk.RxContinuous == true )
GregCr 0:e6ceb13d2d05 1251 {
GregCr 0:e6ceb13d2d05 1252 // Continuous mode restart Rx chain
GregCr 0:e6ceb13d2d05 1253 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
Helmut Tschemernjak 53:6d3adad59633 1254 SetTimeout(RXTimeoutSyncWordTimer, &SX1276::OnTimeoutIrq, this->settings.Fsk.RxSingleTimeout * 1e3);
GregCr 0:e6ceb13d2d05 1255 }
GregCr 0:e6ceb13d2d05 1256 else
GregCr 0:e6ceb13d2d05 1257 {
mluis 21:2e496deb7858 1258 this->settings.State = RF_IDLE;
Helmut Tschemernjak 53:6d3adad59633 1259 SetTimeout(RXTimeoutSyncWordTimer, NULL);
GregCr 0:e6ceb13d2d05 1260 }
GregCr 0:e6ceb13d2d05 1261 }
Helmut Tschemernjak 63:5b9d391244dc 1262 if (this->RadioEvents && this->RadioEvents->RxTimeout)
GregCr 0:e6ceb13d2d05 1263 {
Helmut Tschemernjak 63:5b9d391244dc 1264 this->RadioEvents->RxTimeout(this, this->RadioEvents->userThisPtr, this->RadioEvents->userData);
GregCr 0:e6ceb13d2d05 1265 }
GregCr 0:e6ceb13d2d05 1266 break;
mluis 21:2e496deb7858 1267 case RF_TX_RUNNING:
Helmut Tschemernjak 31:e50929bd3f32 1268 // Tx timeout shouldn't happen.
Helmut Tschemernjak 31:e50929bd3f32 1269 // But it has been observed that when it happens it is a result of a corrupted SPI transfer
Helmut Tschemernjak 31:e50929bd3f32 1270 // it depends on the platform design.
Helmut Tschemernjak 31:e50929bd3f32 1271 //
Helmut Tschemernjak 31:e50929bd3f32 1272 // The workaround is to put the radio in a known state. Thus, we re-initialize it.
Helmut Tschemernjak 31:e50929bd3f32 1273 // BEGIN WORKAROUND
Helmut Tschemernjak 31:e50929bd3f32 1274
Helmut Tschemernjak 31:e50929bd3f32 1275 // Reset the radio
Helmut Tschemernjak 31:e50929bd3f32 1276 Reset( );
Helmut Tschemernjak 31:e50929bd3f32 1277
Helmut Tschemernjak 31:e50929bd3f32 1278 // Calibrate Rx chain
Helmut Tschemernjak 31:e50929bd3f32 1279 RxChainCalibration( );
Helmut Tschemernjak 31:e50929bd3f32 1280
Helmut Tschemernjak 31:e50929bd3f32 1281 // Initialize radio default values
Helmut Tschemernjak 31:e50929bd3f32 1282 SetOpMode( RF_OPMODE_SLEEP );
Helmut Tschemernjak 31:e50929bd3f32 1283
Helmut Tschemernjak 31:e50929bd3f32 1284 RadioRegistersInit( );
Helmut Tschemernjak 31:e50929bd3f32 1285
Helmut Tschemernjak 31:e50929bd3f32 1286 SetModem( MODEM_FSK );
Helmut Tschemernjak 31:e50929bd3f32 1287
Helmut Tschemernjak 31:e50929bd3f32 1288 // Restore previous network type setting.
Helmut Tschemernjak 31:e50929bd3f32 1289 SetPublicNetwork( this->settings.LoRa.PublicNetwork );
Helmut Tschemernjak 31:e50929bd3f32 1290 // END WORKAROUND
Helmut Tschemernjak 31:e50929bd3f32 1291
mluis 21:2e496deb7858 1292 this->settings.State = RF_IDLE;
Helmut Tschemernjak 63:5b9d391244dc 1293 if (this->RadioEvents && this->RadioEvents->TxTimeout)
GregCr 0:e6ceb13d2d05 1294 {
Helmut Tschemernjak 63:5b9d391244dc 1295 this->RadioEvents->TxTimeout(this, this->RadioEvents->userThisPtr, this->RadioEvents->userData);
GregCr 0:e6ceb13d2d05 1296 }
GregCr 0:e6ceb13d2d05 1297 break;
GregCr 0:e6ceb13d2d05 1298 default:
GregCr 0:e6ceb13d2d05 1299 break;
GregCr 0:e6ceb13d2d05 1300 }
GregCr 0:e6ceb13d2d05 1301 }
GregCr 0:e6ceb13d2d05 1302
GregCr 0:e6ceb13d2d05 1303 void SX1276::OnDio0Irq( void )
GregCr 0:e6ceb13d2d05 1304 {
mluis 20:e05596ba4166 1305 volatile uint8_t irqFlags = 0;
mluis 22:7f3aab69cca9 1306
GregCr 0:e6ceb13d2d05 1307 switch( this->settings.State )
mluis 25:3778e6204cc1 1308 {
mluis 21:2e496deb7858 1309 case RF_RX_RUNNING:
GregCr 0:e6ceb13d2d05 1310 //TimerStop( &RxTimeoutTimer );
GregCr 0:e6ceb13d2d05 1311 // RxDone interrupt
GregCr 0:e6ceb13d2d05 1312 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1313 {
GregCr 0:e6ceb13d2d05 1314 case MODEM_FSK:
GregCr 18:99c6e44c1672 1315 if( this->settings.Fsk.CrcOn == true )
GregCr 0:e6ceb13d2d05 1316 {
GregCr 18:99c6e44c1672 1317 irqFlags = Read( REG_IRQFLAGS2 );
GregCr 18:99c6e44c1672 1318 if( ( irqFlags & RF_IRQFLAGS2_CRCOK ) != RF_IRQFLAGS2_CRCOK )
GregCr 0:e6ceb13d2d05 1319 {
GregCr 18:99c6e44c1672 1320 // Clear Irqs
mluis 25:3778e6204cc1 1321 Write( REG_IRQFLAGS1, RF_IRQFLAGS1_RSSI |
GregCr 18:99c6e44c1672 1322 RF_IRQFLAGS1_PREAMBLEDETECT |
GregCr 18:99c6e44c1672 1323 RF_IRQFLAGS1_SYNCADDRESSMATCH );
GregCr 18:99c6e44c1672 1324 Write( REG_IRQFLAGS2, RF_IRQFLAGS2_FIFOOVERRUN );
mluis 25:3778e6204cc1 1325
Helmut Tschemernjak 44:544add59b26d 1326 SetTimeout(RXTimeoutTimer, NULL);
mluis 25:3778e6204cc1 1327
GregCr 18:99c6e44c1672 1328 if( this->settings.Fsk.RxContinuous == false )
GregCr 18:99c6e44c1672 1329 {
Helmut Tschemernjak 53:6d3adad59633 1330 SetTimeout(RXTimeoutSyncWordTimer, NULL);
mluis 21:2e496deb7858 1331 this->settings.State = RF_IDLE;
GregCr 18:99c6e44c1672 1332 }
GregCr 18:99c6e44c1672 1333 else
GregCr 18:99c6e44c1672 1334 {
GregCr 18:99c6e44c1672 1335 // Continuous mode restart Rx chain
GregCr 18:99c6e44c1672 1336 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
Helmut Tschemernjak 53:6d3adad59633 1337 SetTimeout(RXTimeoutSyncWordTimer, &SX1276::OnTimeoutIrq, this->settings.Fsk.RxSingleTimeout * 1e3);
GregCr 18:99c6e44c1672 1338 }
mluis 25:3778e6204cc1 1339
Helmut Tschemernjak 63:5b9d391244dc 1340 if (this->RadioEvents && this->RadioEvents->RxError)
GregCr 18:99c6e44c1672 1341 {
Helmut Tschemernjak 63:5b9d391244dc 1342 this->RadioEvents->RxError(this, this->RadioEvents->userThisPtr, this->RadioEvents->userData);
GregCr 18:99c6e44c1672 1343 }
GregCr 18:99c6e44c1672 1344 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 18:99c6e44c1672 1345 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 18:99c6e44c1672 1346 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 18:99c6e44c1672 1347 this->settings.FskPacketHandler.Size = 0;
GregCr 18:99c6e44c1672 1348 break;
GregCr 0:e6ceb13d2d05 1349 }
GregCr 0:e6ceb13d2d05 1350 }
mluis 25:3778e6204cc1 1351
GregCr 0:e6ceb13d2d05 1352 // Read received packet size
GregCr 0:e6ceb13d2d05 1353 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
GregCr 0:e6ceb13d2d05 1354 {
GregCr 0:e6ceb13d2d05 1355 if( this->settings.Fsk.FixLen == false )
GregCr 0:e6ceb13d2d05 1356 {
GregCr 0:e6ceb13d2d05 1357 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
GregCr 0:e6ceb13d2d05 1358 }
GregCr 0:e6ceb13d2d05 1359 else
GregCr 0:e6ceb13d2d05 1360 {
GregCr 0:e6ceb13d2d05 1361 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
GregCr 0:e6ceb13d2d05 1362 }
GregCr 23:1e143575df0f 1363 ReadFifo( rxtxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1364 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1365 }
GregCr 0:e6ceb13d2d05 1366 else
GregCr 0:e6ceb13d2d05 1367 {
GregCr 23:1e143575df0f 1368 ReadFifo( rxtxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1369 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1370 }
GregCr 0:e6ceb13d2d05 1371
Helmut Tschemernjak 44:544add59b26d 1372 SetTimeout(RXTimeoutTimer, NULL);
Helmut Tschemernjak 42:72deced1a4c4 1373
GregCr 0:e6ceb13d2d05 1374 if( this->settings.Fsk.RxContinuous == false )
GregCr 0:e6ceb13d2d05 1375 {
mluis 21:2e496deb7858 1376 this->settings.State = RF_IDLE;
Helmut Tschemernjak 53:6d3adad59633 1377 SetTimeout(RXTimeoutSyncWordTimer, NULL);
GregCr 0:e6ceb13d2d05 1378 }
GregCr 0:e6ceb13d2d05 1379 else
GregCr 0:e6ceb13d2d05 1380 {
GregCr 0:e6ceb13d2d05 1381 // Continuous mode restart Rx chain
GregCr 0:e6ceb13d2d05 1382 Write( REG_RXCONFIG, Read( REG_RXCONFIG ) | RF_RXCONFIG_RESTARTRXWITHOUTPLLLOCK );
Helmut Tschemernjak 53:6d3adad59633 1383 SetTimeout(RXTimeoutSyncWordTimer, &SX1276::OnTimeoutIrq, this->settings.Fsk.RxSingleTimeout * 1e3);
Helmut Tschemernjak 31:e50929bd3f32 1384 }
GregCr 0:e6ceb13d2d05 1385
Helmut Tschemernjak 63:5b9d391244dc 1386 if (this->RadioEvents && this->RadioEvents->RxDone)
GregCr 0:e6ceb13d2d05 1387 {
Helmut Tschemernjak 63:5b9d391244dc 1388 this->RadioEvents->RxDone(this, this->RadioEvents->userThisPtr, this->RadioEvents->userData, rxtxBuffer, this->settings.FskPacketHandler.Size, this->settings.FskPacketHandler.RssiValue, 0 );
mluis 25:3778e6204cc1 1389 }
GregCr 0:e6ceb13d2d05 1390 this->settings.FskPacketHandler.PreambleDetected = false;
GregCr 0:e6ceb13d2d05 1391 this->settings.FskPacketHandler.SyncWordDetected = false;
GregCr 0:e6ceb13d2d05 1392 this->settings.FskPacketHandler.NbBytes = 0;
GregCr 0:e6ceb13d2d05 1393 this->settings.FskPacketHandler.Size = 0;
GregCr 0:e6ceb13d2d05 1394 break;
GregCr 0:e6ceb13d2d05 1395 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1396 {
mluis 22:7f3aab69cca9 1397 int8_t snr = 0;
GregCr 0:e6ceb13d2d05 1398
GregCr 0:e6ceb13d2d05 1399 // Clear Irq
GregCr 0:e6ceb13d2d05 1400 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXDONE );
GregCr 0:e6ceb13d2d05 1401
GregCr 0:e6ceb13d2d05 1402 irqFlags = Read( REG_LR_IRQFLAGS );
GregCr 0:e6ceb13d2d05 1403 if( ( irqFlags & RFLR_IRQFLAGS_PAYLOADCRCERROR_MASK ) == RFLR_IRQFLAGS_PAYLOADCRCERROR )
GregCr 0:e6ceb13d2d05 1404 {
GregCr 0:e6ceb13d2d05 1405 // Clear Irq
GregCr 0:e6ceb13d2d05 1406 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_PAYLOADCRCERROR );
GregCr 0:e6ceb13d2d05 1407
GregCr 0:e6ceb13d2d05 1408 if( this->settings.LoRa.RxContinuous == false )
GregCr 0:e6ceb13d2d05 1409 {
mluis 21:2e496deb7858 1410 this->settings.State = RF_IDLE;
GregCr 0:e6ceb13d2d05 1411 }
Helmut Tschemernjak 44:544add59b26d 1412 SetTimeout(RXTimeoutTimer, NULL);
Helmut Tschemernjak 42:72deced1a4c4 1413
Helmut Tschemernjak 63:5b9d391244dc 1414 if(this->RadioEvents && this->RadioEvents->RxError)
GregCr 0:e6ceb13d2d05 1415 {
Helmut Tschemernjak 63:5b9d391244dc 1416 this->RadioEvents->RxError(this, this->RadioEvents->userThisPtr, this->RadioEvents->userData);
GregCr 0:e6ceb13d2d05 1417 }
GregCr 0:e6ceb13d2d05 1418 break;
GregCr 0:e6ceb13d2d05 1419 }
GregCr 0:e6ceb13d2d05 1420
GregCr 0:e6ceb13d2d05 1421 this->settings.LoRaPacketHandler.SnrValue = Read( REG_LR_PKTSNRVALUE );
GregCr 0:e6ceb13d2d05 1422 if( this->settings.LoRaPacketHandler.SnrValue & 0x80 ) // The SNR sign bit is 1
GregCr 0:e6ceb13d2d05 1423 {
GregCr 0:e6ceb13d2d05 1424 // Invert and divide by 4
GregCr 0:e6ceb13d2d05 1425 snr = ( ( ~this->settings.LoRaPacketHandler.SnrValue + 1 ) & 0xFF ) >> 2;
GregCr 0:e6ceb13d2d05 1426 snr = -snr;
GregCr 0:e6ceb13d2d05 1427 }
GregCr 0:e6ceb13d2d05 1428 else
GregCr 0:e6ceb13d2d05 1429 {
GregCr 0:e6ceb13d2d05 1430 // Divide by 4
GregCr 0:e6ceb13d2d05 1431 snr = ( this->settings.LoRaPacketHandler.SnrValue & 0xFF ) >> 2;
GregCr 0:e6ceb13d2d05 1432 }
GregCr 0:e6ceb13d2d05 1433
GregCr 7:2b555111463f 1434 int16_t rssi = Read( REG_LR_PKTRSSIVALUE );
mluis 22:7f3aab69cca9 1435 if( snr < 0 )
GregCr 0:e6ceb13d2d05 1436 {
GregCr 0:e6ceb13d2d05 1437 if( this->settings.Channel > RF_MID_BAND_THRESH )
GregCr 0:e6ceb13d2d05 1438 {
GregCr 0:e6ceb13d2d05 1439 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 ) +
GregCr 0:e6ceb13d2d05 1440 snr;
GregCr 0:e6ceb13d2d05 1441 }
GregCr 0:e6ceb13d2d05 1442 else
GregCr 0:e6ceb13d2d05 1443 {
GregCr 0:e6ceb13d2d05 1444 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 ) +
GregCr 0:e6ceb13d2d05 1445 snr;
GregCr 0:e6ceb13d2d05 1446 }
GregCr 0:e6ceb13d2d05 1447 }
GregCr 0:e6ceb13d2d05 1448 else
mluis 25:3778e6204cc1 1449 {
GregCr 0:e6ceb13d2d05 1450 if( this->settings.Channel > RF_MID_BAND_THRESH )
GregCr 0:e6ceb13d2d05 1451 {
GregCr 0:e6ceb13d2d05 1452 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_HF + rssi + ( rssi >> 4 );
GregCr 0:e6ceb13d2d05 1453 }
GregCr 0:e6ceb13d2d05 1454 else
GregCr 0:e6ceb13d2d05 1455 {
GregCr 0:e6ceb13d2d05 1456 this->settings.LoRaPacketHandler.RssiValue = RSSI_OFFSET_LF + rssi + ( rssi >> 4 );
GregCr 0:e6ceb13d2d05 1457 }
GregCr 0:e6ceb13d2d05 1458 }
GregCr 0:e6ceb13d2d05 1459
GregCr 0:e6ceb13d2d05 1460 this->settings.LoRaPacketHandler.Size = Read( REG_LR_RXNBBYTES );
GregCr 23:1e143575df0f 1461 ReadFifo( rxtxBuffer, this->settings.LoRaPacketHandler.Size );
mluis 25:3778e6204cc1 1462
GregCr 0:e6ceb13d2d05 1463 if( this->settings.LoRa.RxContinuous == false )
GregCr 0:e6ceb13d2d05 1464 {
mluis 21:2e496deb7858 1465 this->settings.State = RF_IDLE;
GregCr 0:e6ceb13d2d05 1466 }
Helmut Tschemernjak 44:544add59b26d 1467 SetTimeout(RXTimeoutTimer, NULL);
Helmut Tschemernjak 42:72deced1a4c4 1468
Helmut Tschemernjak 63:5b9d391244dc 1469 if(this->RadioEvents && this->RadioEvents->RxDone)
GregCr 0:e6ceb13d2d05 1470 {
Helmut Tschemernjak 63:5b9d391244dc 1471 this->RadioEvents->RxDone(this, this->RadioEvents->userThisPtr, this->RadioEvents->userData, rxtxBuffer, this->settings.LoRaPacketHandler.Size, this->settings.LoRaPacketHandler.RssiValue, this->settings.LoRaPacketHandler.SnrValue );
GregCr 0:e6ceb13d2d05 1472 }
GregCr 0:e6ceb13d2d05 1473 }
GregCr 0:e6ceb13d2d05 1474 break;
GregCr 0:e6ceb13d2d05 1475 default:
GregCr 0:e6ceb13d2d05 1476 break;
GregCr 0:e6ceb13d2d05 1477 }
GregCr 0:e6ceb13d2d05 1478 break;
mluis 21:2e496deb7858 1479 case RF_TX_RUNNING:
Helmut Tschemernjak 44:544add59b26d 1480 SetTimeout(TXTimeoutTimer, NULL);
GregCr 0:e6ceb13d2d05 1481 // TxDone interrupt
GregCr 0:e6ceb13d2d05 1482 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1483 {
GregCr 0:e6ceb13d2d05 1484 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1485 // Clear Irq
GregCr 0:e6ceb13d2d05 1486 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_TXDONE );
GregCr 0:e6ceb13d2d05 1487 // Intentional fall through
GregCr 0:e6ceb13d2d05 1488 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1489 default:
mluis 21:2e496deb7858 1490 this->settings.State = RF_IDLE;
Helmut Tschemernjak 63:5b9d391244dc 1491 if (this->RadioEvents && this->RadioEvents->TxDone)
GregCr 0:e6ceb13d2d05 1492 {
Helmut Tschemernjak 63:5b9d391244dc 1493 this->RadioEvents->TxDone(this, this->RadioEvents->userThisPtr, this->RadioEvents->userData);
mluis 25:3778e6204cc1 1494 }
GregCr 0:e6ceb13d2d05 1495 break;
GregCr 0:e6ceb13d2d05 1496 }
GregCr 0:e6ceb13d2d05 1497 break;
GregCr 0:e6ceb13d2d05 1498 default:
GregCr 0:e6ceb13d2d05 1499 break;
GregCr 0:e6ceb13d2d05 1500 }
GregCr 0:e6ceb13d2d05 1501 }
GregCr 0:e6ceb13d2d05 1502
GregCr 0:e6ceb13d2d05 1503 void SX1276::OnDio1Irq( void )
GregCr 0:e6ceb13d2d05 1504 {
GregCr 0:e6ceb13d2d05 1505 switch( this->settings.State )
mluis 25:3778e6204cc1 1506 {
mluis 21:2e496deb7858 1507 case RF_RX_RUNNING:
GregCr 0:e6ceb13d2d05 1508 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1509 {
GregCr 0:e6ceb13d2d05 1510 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1511 // FifoLevel interrupt
GregCr 0:e6ceb13d2d05 1512 // Read received packet size
GregCr 0:e6ceb13d2d05 1513 if( ( this->settings.FskPacketHandler.Size == 0 ) && ( this->settings.FskPacketHandler.NbBytes == 0 ) )
GregCr 0:e6ceb13d2d05 1514 {
GregCr 0:e6ceb13d2d05 1515 if( this->settings.Fsk.FixLen == false )
GregCr 0:e6ceb13d2d05 1516 {
GregCr 0:e6ceb13d2d05 1517 ReadFifo( ( uint8_t* )&this->settings.FskPacketHandler.Size, 1 );
GregCr 0:e6ceb13d2d05 1518 }
GregCr 0:e6ceb13d2d05 1519 else
GregCr 0:e6ceb13d2d05 1520 {
GregCr 0:e6ceb13d2d05 1521 this->settings.FskPacketHandler.Size = Read( REG_PAYLOADLENGTH );
GregCr 0:e6ceb13d2d05 1522 }
GregCr 0:e6ceb13d2d05 1523 }
GregCr 0:e6ceb13d2d05 1524
GregCr 0:e6ceb13d2d05 1525 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.FifoThresh )
GregCr 0:e6ceb13d2d05 1526 {
GregCr 23:1e143575df0f 1527 ReadFifo( ( rxtxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.FifoThresh );
GregCr 0:e6ceb13d2d05 1528 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.FifoThresh;
GregCr 0:e6ceb13d2d05 1529 }
GregCr 0:e6ceb13d2d05 1530 else
GregCr 0:e6ceb13d2d05 1531 {
GregCr 23:1e143575df0f 1532 ReadFifo( ( rxtxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1533 this->settings.FskPacketHandler.NbBytes += ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1534 }
GregCr 0:e6ceb13d2d05 1535 break;
GregCr 0:e6ceb13d2d05 1536 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1537 // Sync time out
Helmut Tschemernjak 44:544add59b26d 1538 SetTimeout(RXTimeoutTimer, NULL);
Helmut Tschemernjak 42:72deced1a4c4 1539 // Clear Irq
Helmut Tschemernjak 31:e50929bd3f32 1540 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_RXTIMEOUT );
Helmut Tschemernjak 31:e50929bd3f32 1541
mluis 21:2e496deb7858 1542 this->settings.State = RF_IDLE;
Helmut Tschemernjak 63:5b9d391244dc 1543 if (this->RadioEvents && this->RadioEvents->RxTimeout)
GregCr 0:e6ceb13d2d05 1544 {
Helmut Tschemernjak 63:5b9d391244dc 1545 this->RadioEvents->RxTimeout(this, this->RadioEvents->userThisPtr, this->RadioEvents->userData);
GregCr 0:e6ceb13d2d05 1546 }
GregCr 0:e6ceb13d2d05 1547 break;
GregCr 0:e6ceb13d2d05 1548 default:
GregCr 0:e6ceb13d2d05 1549 break;
GregCr 0:e6ceb13d2d05 1550 }
GregCr 0:e6ceb13d2d05 1551 break;
mluis 21:2e496deb7858 1552 case RF_TX_RUNNING:
GregCr 0:e6ceb13d2d05 1553 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1554 {
GregCr 0:e6ceb13d2d05 1555 case MODEM_FSK:
mluis 25:3778e6204cc1 1556 // FifoEmpty interrupt
GregCr 0:e6ceb13d2d05 1557 if( ( this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes ) > this->settings.FskPacketHandler.ChunkSize )
GregCr 0:e6ceb13d2d05 1558 {
GregCr 23:1e143575df0f 1559 WriteFifo( ( rxtxBuffer + this->settings.FskPacketHandler.NbBytes ), this->settings.FskPacketHandler.ChunkSize );
GregCr 0:e6ceb13d2d05 1560 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.ChunkSize;
GregCr 0:e6ceb13d2d05 1561 }
mluis 25:3778e6204cc1 1562 else
GregCr 0:e6ceb13d2d05 1563 {
GregCr 0:e6ceb13d2d05 1564 // Write the last chunk of data
GregCr 23:1e143575df0f 1565 WriteFifo( rxtxBuffer + this->settings.FskPacketHandler.NbBytes, this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes );
GregCr 0:e6ceb13d2d05 1566 this->settings.FskPacketHandler.NbBytes += this->settings.FskPacketHandler.Size - this->settings.FskPacketHandler.NbBytes;
GregCr 0:e6ceb13d2d05 1567 }
GregCr 0:e6ceb13d2d05 1568 break;
GregCr 0:e6ceb13d2d05 1569 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1570 break;
GregCr 0:e6ceb13d2d05 1571 default:
GregCr 0:e6ceb13d2d05 1572 break;
GregCr 0:e6ceb13d2d05 1573 }
mluis 22:7f3aab69cca9 1574 break;
GregCr 0:e6ceb13d2d05 1575 default:
GregCr 0:e6ceb13d2d05 1576 break;
GregCr 0:e6ceb13d2d05 1577 }
GregCr 0:e6ceb13d2d05 1578 }
GregCr 0:e6ceb13d2d05 1579
GregCr 0:e6ceb13d2d05 1580 void SX1276::OnDio2Irq( void )
GregCr 0:e6ceb13d2d05 1581 {
GregCr 0:e6ceb13d2d05 1582 switch( this->settings.State )
mluis 25:3778e6204cc1 1583 {
mluis 21:2e496deb7858 1584 case RF_RX_RUNNING:
GregCr 0:e6ceb13d2d05 1585 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1586 {
GregCr 0:e6ceb13d2d05 1587 case MODEM_FSK:
Helmut Tschemernjak 31:e50929bd3f32 1588 // Checks if DIO4 is connected. If it is not PreambleDtected is set to true.
Helmut Tschemernjak 31:e50929bd3f32 1589 if( this->dioIrq[4] == NULL )
Helmut Tschemernjak 31:e50929bd3f32 1590 {
Helmut Tschemernjak 31:e50929bd3f32 1591 this->settings.FskPacketHandler.PreambleDetected = true;
Helmut Tschemernjak 31:e50929bd3f32 1592 }
Helmut Tschemernjak 31:e50929bd3f32 1593
GregCr 0:e6ceb13d2d05 1594 if( ( this->settings.FskPacketHandler.PreambleDetected == true ) && ( this->settings.FskPacketHandler.SyncWordDetected == false ) )
GregCr 0:e6ceb13d2d05 1595 {
Helmut Tschemernjak 53:6d3adad59633 1596 SetTimeout(RXTimeoutSyncWordTimer, NULL);
Helmut Tschemernjak 42:72deced1a4c4 1597
GregCr 0:e6ceb13d2d05 1598 this->settings.FskPacketHandler.SyncWordDetected = true;
mluis 25:3778e6204cc1 1599
GregCr 0:e6ceb13d2d05 1600 this->settings.FskPacketHandler.RssiValue = -( Read( REG_RSSIVALUE ) >> 1 );
GregCr 0:e6ceb13d2d05 1601
GregCr 0:e6ceb13d2d05 1602 this->settings.FskPacketHandler.AfcValue = ( int32_t )( double )( ( ( uint16_t )Read( REG_AFCMSB ) << 8 ) |
GregCr 0:e6ceb13d2d05 1603 ( uint16_t )Read( REG_AFCLSB ) ) *
GregCr 0:e6ceb13d2d05 1604 ( double )FREQ_STEP;
GregCr 0:e6ceb13d2d05 1605 this->settings.FskPacketHandler.RxGain = ( Read( REG_LNA ) >> 5 ) & 0x07;
GregCr 0:e6ceb13d2d05 1606 }
GregCr 0:e6ceb13d2d05 1607 break;
GregCr 0:e6ceb13d2d05 1608 case MODEM_LORA:
GregCr 6:e7f02929cd3d 1609 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 1610 {
GregCr 6:e7f02929cd3d 1611 // Clear Irq
GregCr 6:e7f02929cd3d 1612 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
mluis 25:3778e6204cc1 1613
Helmut Tschemernjak 63:5b9d391244dc 1614 if (this->RadioEvents && this->RadioEvents->FhssChangeChannel)
mluis 13:618826a997e2 1615 {
Helmut Tschemernjak 63:5b9d391244dc 1616 this->RadioEvents->FhssChangeChannel(this, this->RadioEvents->userThisPtr, this->RadioEvents->userData, ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
mluis 13:618826a997e2 1617 }
mluis 22:7f3aab69cca9 1618 }
GregCr 0:e6ceb13d2d05 1619 break;
GregCr 0:e6ceb13d2d05 1620 default:
GregCr 0:e6ceb13d2d05 1621 break;
GregCr 0:e6ceb13d2d05 1622 }
GregCr 0:e6ceb13d2d05 1623 break;
mluis 21:2e496deb7858 1624 case RF_TX_RUNNING:
GregCr 0:e6ceb13d2d05 1625 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1626 {
GregCr 0:e6ceb13d2d05 1627 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1628 break;
GregCr 0:e6ceb13d2d05 1629 case MODEM_LORA:
GregCr 6:e7f02929cd3d 1630 if( this->settings.LoRa.FreqHopOn == true )
GregCr 6:e7f02929cd3d 1631 {
GregCr 6:e7f02929cd3d 1632 // Clear Irq
GregCr 6:e7f02929cd3d 1633 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_FHSSCHANGEDCHANNEL );
mluis 25:3778e6204cc1 1634
Helmut Tschemernjak 63:5b9d391244dc 1635 if (this->RadioEvents && this->RadioEvents->FhssChangeChannel)
mluis 13:618826a997e2 1636 {
Helmut Tschemernjak 63:5b9d391244dc 1637 this->RadioEvents->FhssChangeChannel(this, this->RadioEvents->userThisPtr, this->RadioEvents->userData, ( Read( REG_LR_HOPCHANNEL ) & RFLR_HOPCHANNEL_CHANNEL_MASK ) );
mluis 13:618826a997e2 1638 }
mluis 22:7f3aab69cca9 1639 }
GregCr 0:e6ceb13d2d05 1640 break;
GregCr 0:e6ceb13d2d05 1641 default:
GregCr 0:e6ceb13d2d05 1642 break;
GregCr 0:e6ceb13d2d05 1643 }
mluis 22:7f3aab69cca9 1644 break;
GregCr 0:e6ceb13d2d05 1645 default:
GregCr 0:e6ceb13d2d05 1646 break;
GregCr 0:e6ceb13d2d05 1647 }
GregCr 0:e6ceb13d2d05 1648 }
GregCr 0:e6ceb13d2d05 1649
GregCr 0:e6ceb13d2d05 1650 void SX1276::OnDio3Irq( void )
GregCr 0:e6ceb13d2d05 1651 {
GregCr 0:e6ceb13d2d05 1652 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1653 {
GregCr 0:e6ceb13d2d05 1654 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1655 break;
GregCr 0:e6ceb13d2d05 1656 case MODEM_LORA:
mluis 22:7f3aab69cca9 1657 if( ( Read( REG_LR_IRQFLAGS ) & RFLR_IRQFLAGS_CADDETECTED ) == RFLR_IRQFLAGS_CADDETECTED )
mluis 13:618826a997e2 1658 {
mluis 13:618826a997e2 1659 // Clear Irq
mluis 22:7f3aab69cca9 1660 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDETECTED | RFLR_IRQFLAGS_CADDONE );
Helmut Tschemernjak 63:5b9d391244dc 1661 if (this->RadioEvents && this->RadioEvents->CadDone)
mluis 13:618826a997e2 1662 {
Helmut Tschemernjak 63:5b9d391244dc 1663 this->RadioEvents->CadDone(this, this->RadioEvents->userThisPtr, this->RadioEvents->userData, true );
mluis 13:618826a997e2 1664 }
GregCr 12:aa5b3bf7fdf4 1665 }
GregCr 12:aa5b3bf7fdf4 1666 else
mluis 25:3778e6204cc1 1667 {
mluis 13:618826a997e2 1668 // Clear Irq
mluis 13:618826a997e2 1669 Write( REG_LR_IRQFLAGS, RFLR_IRQFLAGS_CADDONE );
Helmut Tschemernjak 63:5b9d391244dc 1670 if (this->RadioEvents && this->RadioEvents->CadDone)
mluis 13:618826a997e2 1671 {
Helmut Tschemernjak 63:5b9d391244dc 1672 this->RadioEvents->CadDone(this, this->RadioEvents->userThisPtr, this->RadioEvents->userData, false );
mluis 13:618826a997e2 1673 }
GregCr 7:2b555111463f 1674 }
GregCr 0:e6ceb13d2d05 1675 break;
GregCr 0:e6ceb13d2d05 1676 default:
GregCr 0:e6ceb13d2d05 1677 break;
GregCr 0:e6ceb13d2d05 1678 }
GregCr 0:e6ceb13d2d05 1679 }
GregCr 0:e6ceb13d2d05 1680
GregCr 0:e6ceb13d2d05 1681 void SX1276::OnDio4Irq( void )
GregCr 0:e6ceb13d2d05 1682 {
GregCr 0:e6ceb13d2d05 1683 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1684 {
GregCr 0:e6ceb13d2d05 1685 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1686 {
GregCr 0:e6ceb13d2d05 1687 if( this->settings.FskPacketHandler.PreambleDetected == false )
GregCr 0:e6ceb13d2d05 1688 {
GregCr 0:e6ceb13d2d05 1689 this->settings.FskPacketHandler.PreambleDetected = true;
mluis 25:3778e6204cc1 1690 }
GregCr 0:e6ceb13d2d05 1691 }
GregCr 0:e6ceb13d2d05 1692 break;
GregCr 0:e6ceb13d2d05 1693 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1694 break;
GregCr 0:e6ceb13d2d05 1695 default:
GregCr 0:e6ceb13d2d05 1696 break;
GregCr 0:e6ceb13d2d05 1697 }
GregCr 0:e6ceb13d2d05 1698 }
GregCr 0:e6ceb13d2d05 1699
GregCr 0:e6ceb13d2d05 1700 void SX1276::OnDio5Irq( void )
GregCr 0:e6ceb13d2d05 1701 {
GregCr 0:e6ceb13d2d05 1702 switch( this->settings.Modem )
GregCr 0:e6ceb13d2d05 1703 {
GregCr 0:e6ceb13d2d05 1704 case MODEM_FSK:
GregCr 0:e6ceb13d2d05 1705 break;
GregCr 0:e6ceb13d2d05 1706 case MODEM_LORA:
GregCr 0:e6ceb13d2d05 1707 break;
GregCr 0:e6ceb13d2d05 1708 default:
GregCr 0:e6ceb13d2d05 1709 break;
GregCr 0:e6ceb13d2d05 1710 }
mluis 13:618826a997e2 1711 }