Xuyi Wang / SSD1963

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SSD1963.cpp@2:d8a9ebd28f0a, 2020-10-08 (annotated)

Committer:
sPymbed
Date:
Thu Oct 08 06:50:37 2020 +0000
Revision:
2:d8a9ebd28f0a
Parent:
1:74bac5f988d8
Child:
3:31ca3cd96572
final version

Who changed what in which revision?

UserRevisionLine numberNew contents of line
sPymbed 0:94df05e3330d 1 /*****************************************************************************
sPymbed 0:94df05e3330d 2 * Project : 7" TFT LCD 800x480 [AT070TN92]
sPymbed 0:94df05e3330d 3 * Compiler : mbed Online
sPymbed 0:94df05e3330d 4 * Type : Libraries
sPymbed 0:94df05e3330d 5 * Comment : Support mbed ST Nucleo Board.
sPymbed 0:94df05e3330d 6 * : Support Chip = SSD1963
sPymbed 0:94df05e3330d 7 * File : SSD1963.c
sPymbed 0:94df05e3330d 8 *
sPymbed 0:94df05e3330d 9 * Author : Mr.Thongchai Artsamart [Bird Techstep]
sPymbed 0:94df05e3330d 10 * E-Mail : t.artsamart@gmail.com
sPymbed 0:94df05e3330d 11 * : tbird_th@hotmail.com
sPymbed 0:94df05e3330d 12 * Start Date : 20/03/2014 [dd/mm/yyyy]
sPymbed 0:94df05e3330d 13 * Version Date : 20/03/2014 [dd/mm/yyyy]
sPymbed 0:94df05e3330d 14 * Licensed under a Creative Commons Attribution-ShareAlike 3.0 License.
sPymbed 0:94df05e3330d 15 *****************************************************************************
sPymbed 0:94df05e3330d 16 * Remark : Thank you -. no1wudi [CooCox]
sPymbed 0:94df05e3330d 17 * -.
sPymbed 0:94df05e3330d 18 *****************************************************************************/
sPymbed 0:94df05e3330d 19 #include "mbed.h"
sPymbed 0:94df05e3330d 20 #include "SSD1963.h"
sPymbed 0:94df05e3330d 21
sPymbed 0:94df05e3330d 22 /*
sPymbed 0:94df05e3330d 23 #define HDP 799 // [ 799][ 799] Horizontal Display Period
sPymbed 0:94df05e3330d 24 #define HT 928 // [ 928][1000] Horizontal Total
sPymbed 0:94df05e3330d 25 #define HPS 46 // [ 46][ 51] LLINE Pulse Start Position
sPymbed 0:94df05e3330d 26 #define LPS 15 // [ 15][ 3] Horizontal Display Period Start Position
sPymbed 0:94df05e3330d 27 #define HPW 48 // [ 48][ 8] LLINE Pulse Width
sPymbed 0:94df05e3330d 28 #define VDP 479 // [ 479][ 479] Vertical Display Period
sPymbed 0:94df05e3330d 29 #define VT 525 // [ 525][ 530] Vertical Total
sPymbed 0:94df05e3330d 30 #define VPS 16 // [ 16][ 24] LFRAME Pulse Start Position
sPymbed 0:94df05e3330d 31 #define FPS 8 // [ 8][ 23] Vertical Display Period Start Position
sPymbed 0:94df05e3330d 32 #define VPW 16 // [ 16][ 3] LFRAME Pulse Width
sPymbed 0:94df05e3330d 33 */
sPymbed 0:94df05e3330d 34
sPymbed 1:74bac5f988d8 35 SSD1963::SSD1963(PinName CS, PinName RESET, PinName RS, PinName WR, BusInOut* DATA_PORT, PinName RD):
sPymbed 2:d8a9ebd28f0a 36 LCD( 272, 480, CS, RS, RESET, NC, Constant, 1.0 ), _lcd_pin_wr( WR ), _lcd_pin_rd(RD)
sPymbed 1:74bac5f988d8 37 {
sPymbed 2:d8a9ebd28f0a 38 _lcd_port = DATA_PORT;
sPymbed 0:94df05e3330d 39 }
sPymbed 0:94df05e3330d 40
sPymbed 2:d8a9ebd28f0a 41 void SSD1963::WriteData(unsigned short data) {
sPymbed 1:74bac5f988d8 42 Activate();
sPymbed 1:74bac5f988d8 43 _lcd_pin_rs = HIGH;
sPymbed 1:74bac5f988d8 44 _lcd_pin_wr = LOW;
sPymbed 1:74bac5f988d8 45 _lcd_port->output();
sPymbed 1:74bac5f988d8 46 _lcd_port->write( data );
sPymbed 1:74bac5f988d8 47 wait_us(1);
sPymbed 1:74bac5f988d8 48 _lcd_pin_wr = HIGH;
sPymbed 1:74bac5f988d8 49 Deactivate();
sPymbed 0:94df05e3330d 50 }
sPymbed 0:94df05e3330d 51
sPymbed 2:d8a9ebd28f0a 52 void SSD1963::WriteCmd(unsigned short cmd) {
sPymbed 1:74bac5f988d8 53 Activate();
sPymbed 1:74bac5f988d8 54 _lcd_pin_rs = LOW;
sPymbed 1:74bac5f988d8 55 _lcd_pin_wr = LOW;
sPymbed 1:74bac5f988d8 56 _lcd_port->output();
sPymbed 1:74bac5f988d8 57 _lcd_port->write( cmd );
sPymbed 1:74bac5f988d8 58 wait_us(1);
sPymbed 1:74bac5f988d8 59 _lcd_pin_wr = HIGH;
sPymbed 1:74bac5f988d8 60 _lcd_pin_rs = HIGH;
sPymbed 1:74bac5f988d8 61 Deactivate();
sPymbed 0:94df05e3330d 62 }
sPymbed 0:94df05e3330d 63
sPymbed 0:94df05e3330d 64 uint16_t SSD1963::readData(void) {
sPymbed 0:94df05e3330d 65 uint16_t data = 0x0000;
sPymbed 1:74bac5f988d8 66 Activate();
sPymbed 1:74bac5f988d8 67 _lcd_pin_rs = HIGH; _lcd_pin_rd = LOW;
sPymbed 0:94df05e3330d 68 wait_us(10);
sPymbed 1:74bac5f988d8 69 _lcd_port->input();
sPymbed 1:74bac5f988d8 70 data = _lcd_port->read() & 0xFFFF;
sPymbed 1:74bac5f988d8 71 wait_us(1);
sPymbed 1:74bac5f988d8 72 _lcd_pin_rd = HIGH;
sPymbed 1:74bac5f988d8 73 Deactivate();
sPymbed 0:94df05e3330d 74 return data;
sPymbed 0:94df05e3330d 75 }
sPymbed 0:94df05e3330d 76
sPymbed 0:94df05e3330d 77 void SSD1963::writeRegister(uint16_t addr, uint16_t data) {
sPymbed 2:d8a9ebd28f0a 78 WriteCmd(addr);
sPymbed 2:d8a9ebd28f0a 79 WriteData(data);
sPymbed 0:94df05e3330d 80 }
sPymbed 0:94df05e3330d 81
sPymbed 0:94df05e3330d 82 void SSD1963::reset(void) {
sPymbed 1:74bac5f988d8 83 _lcd_pin_reset = HIGH;
sPymbed 1:74bac5f988d8 84 wait_ms( 5 );
sPymbed 1:74bac5f988d8 85 _lcd_pin_reset = LOW;
sPymbed 1:74bac5f988d8 86 wait_ms( 15 );
sPymbed 1:74bac5f988d8 87 _lcd_pin_reset = HIGH;
sPymbed 1:74bac5f988d8 88 _lcd_pin_cs = HIGH;
sPymbed 1:74bac5f988d8 89 _lcd_pin_rd = HIGH;
sPymbed 1:74bac5f988d8 90 _lcd_pin_wr = HIGH;
sPymbed 1:74bac5f988d8 91 _lcd_pin_rs = HIGH;
sPymbed 0:94df05e3330d 92 }
sPymbed 0:94df05e3330d 93
sPymbed 0:94df05e3330d 94 void SSD1963::begin() {
sPymbed 0:94df05e3330d 95 reset();
sPymbed 0:94df05e3330d 96 wait_ms(10);
sPymbed 0:94df05e3330d 97 // Set PLL MN -------------------------------------------------------------
sPymbed 0:94df05e3330d 98 // @Parameters : 3
sPymbed 2:d8a9ebd28f0a 99 WriteCmd(Com_SetPLLConfig);
sPymbed 2:d8a9ebd28f0a 100 WriteData(0x1d); // N[7:0] : Multiplier (N) of PLL. (POR = 00101101) b00100011
sPymbed 2:d8a9ebd28f0a 101 WriteData(0x02); // M[3:0] : Divider (M) of PLL. (POR = 0011)
sPymbed 2:d8a9ebd28f0a 102 WriteData(0x54); // C[2] : Effectuate MN value (POR = 100) - Effectuate the multiplier and divider
sPymbed 2:d8a9ebd28f0a 103
sPymbed 0:94df05e3330d 104 // Set PLL
sPymbed 0:94df05e3330d 105 // @Parameters : 1
sPymbed 2:d8a9ebd28f0a 106 WriteCmd(Com_SetPLLStart);
sPymbed 2:d8a9ebd28f0a 107 WriteData(0x01); // Use reference clock as system clock & Enable PLL
sPymbed 2:d8a9ebd28f0a 108 wait_us(100); // Wait 100us to let the PLL stable
sPymbed 2:d8a9ebd28f0a 109 WriteCmd(Com_SetPLLStart); // Set PLL
sPymbed 2:d8a9ebd28f0a 110 WriteData(0x03); // Use PLL output as system clock & Enable PLL
sPymbed 2:d8a9ebd28f0a 111 wait_us(100);
sPymbed 0:94df05e3330d 112
sPymbed 0:94df05e3330d 113 // Software Reset ---------------------------------------------------------
sPymbed 2:d8a9ebd28f0a 114 WriteCmd(Com_Reset);
sPymbed 2:d8a9ebd28f0a 115 wait_ms(100);
sPymbed 0:94df05e3330d 116
sPymbed 0:94df05e3330d 117 // Set LSHIFT Frequency ---------------------------------------------------
sPymbed 0:94df05e3330d 118 // @Parameters : 3
sPymbed 2:d8a9ebd28f0a 119 WriteCmd(Com_SetPixelClock); // Set LSHIFT Frequency
sPymbed 2:d8a9ebd28f0a 120 WriteData(0x01); // LCDC_FPR[19:16] : The highest 4 bits for the pixel clock frequency settings
sPymbed 2:d8a9ebd28f0a 121 WriteData(0x70); // LCDC_FPR[15:8] : The higher byte for the pixel clock frequency settings
sPymbed 2:d8a9ebd28f0a 122 WriteData(0xa2); // LCDC_FPR[7:0] : The low byte for the pixel clock frequency settings
sPymbed 2:d8a9ebd28f0a 123 wait_ms(1);
sPymbed 0:94df05e3330d 124
sPymbed 2:d8a9ebd28f0a 125 // Set Horizontal Period ---------------------
sPymbed 0:94df05e3330d 126 // Set LCD Mode
sPymbed 0:94df05e3330d 127 // @Parameters : 7
sPymbed 2:d8a9ebd28f0a 128 WriteCmd(Com_SetLCDMode);
sPymbed 0:94df05e3330d 129 /*
sPymbed 0:94df05e3330d 130 writeData(0x00); // A[5..0] TFT
sPymbed 0:94df05e3330d 131 //writeData(0x10);
sPymbed 0:94df05e3330d 132 writeData(0x00); // B[7..5] : Hsync+Vsync +DE mode & TFT mode
sPymbed 0:94df05e3330d 133 //writeData(0x80);
sPymbed 0:94df05e3330d 134 writeData((HDP>>8)&0xFF); // HPS[10:8] : Set the horizontal panel size (POR = 010)
sPymbed 0:94df05e3330d 135 writeData(HDP&0xFF); // HPS[7:0] : Set the horizontal panel size (POR = 01111111)
sPymbed 0:94df05e3330d 136 writeData((VDP>>8)&0xFF); // VPS[10:8] : Set the vertical panel size (POR = 001)
sPymbed 0:94df05e3330d 137 writeData(VDP&0xFF); // VPS[7:0] : Set the vertical panel size (POR = 11011111)
sPymbed 0:94df05e3330d 138 writeData(0x00); // G[5..0] : Even line RGB sequence & Odd line RGB sequence
sPymbed 0:94df05e3330d 139 */
sPymbed 2:d8a9ebd28f0a 140 WriteData(0x0c); // set 18-bit for 7" panel TY700TFT800480
sPymbed 2:d8a9ebd28f0a 141 WriteData(0x00); // set TTL mode
sPymbed 2:d8a9ebd28f0a 142 WriteData((DISP_HOR_RESOLUTION - 1) >> 8); //Set panel size
sPymbed 2:d8a9ebd28f0a 143 WriteData(DISP_HOR_RESOLUTION - 1);
sPymbed 2:d8a9ebd28f0a 144 WriteData((DISP_VER_RESOLUTION - 1) >> 8);
sPymbed 2:d8a9ebd28f0a 145 WriteData(DISP_VER_RESOLUTION - 1);
sPymbed 2:d8a9ebd28f0a 146 WriteData(0x00);
sPymbed 2:d8a9ebd28f0a 147
sPymbed 0:94df05e3330d 148 // Set Horizontal Period --------------------------------------------------
sPymbed 0:94df05e3330d 149 // @Parameters : 8
sPymbed 2:d8a9ebd28f0a 150 WriteCmd(Com_SetHoriPeriod);
sPymbed 0:94df05e3330d 151 /*
sPymbed 0:94df05e3330d 152 writeData((HT>>8)&0xFF); // HT[10:8] : High byte of horizontal total period (display + non-display) in pixel clock
sPymbed 0:94df05e3330d 153 writeData(HT&0xFF); // HT[7:0] : Low byte of the horizontal total period (display + non-display) in pixel clock
sPymbed 0:94df05e3330d 154 writeData((HPS>>8)&0xFF); // HPS[10:8] : High byte of the non-display period between the start of the horizontal sync (LLINE) signal
sPymbed 0:94df05e3330d 155 writeData(HPS&0xFF); // HPS[7:0] : Low byte of the non-display period between the start of the horizontal sync (LLINE) signal
sPymbed 0:94df05e3330d 156 writeData(HPW&0xFF); // HPW[6:0] : Set the horizontal sync pulse width (LLINE) in pixel clock
sPymbed 0:94df05e3330d 157 writeData((LPS>>8)&0xFF); // LPS[10:8] : Set the horizontal sync pulse (LLINE) start location in pixel clock
sPymbed 0:94df05e3330d 158 writeData(LPS&0xFF); // LPS[7:0] : Set the horizontal sync pulse width (LLINE) in start.
sPymbed 0:94df05e3330d 159 writeData(0x00); // LPSPP[1:0] : Set the horizontal sync pulse subpixel start position
sPymbed 0:94df05e3330d 160 */
sPymbed 2:d8a9ebd28f0a 161 #define HT (DISP_HOR_RESOLUTION + DISP_HOR_PULSE_WIDTH + DISP_HOR_BACK_PORCH + DISP_HOR_FRONT_PORCH)
sPymbed 2:d8a9ebd28f0a 162 WriteData((HT - 1) >> 8);
sPymbed 2:d8a9ebd28f0a 163 WriteData(HT - 1);
sPymbed 2:d8a9ebd28f0a 164 #define HPS (DISP_HOR_PULSE_WIDTH + DISP_HOR_BACK_PORCH)
sPymbed 2:d8a9ebd28f0a 165 WriteData((HPS - 1) >> 8);
sPymbed 2:d8a9ebd28f0a 166 WriteData(HPS - 1);
sPymbed 2:d8a9ebd28f0a 167 WriteData(DISP_HOR_PULSE_WIDTH - 1);
sPymbed 2:d8a9ebd28f0a 168 WriteData(0x00);
sPymbed 2:d8a9ebd28f0a 169 WriteData(0x00);
sPymbed 2:d8a9ebd28f0a 170 WriteData(0x00);
sPymbed 2:d8a9ebd28f0a 171
sPymbed 0:94df05e3330d 172 // Set Vertical Period ----------------------------------------------------
sPymbed 0:94df05e3330d 173 // @Parameters : 7
sPymbed 2:d8a9ebd28f0a 174 WriteCmd(Com_SetVertPeriod);
sPymbed 0:94df05e3330d 175 /*
sPymbed 0:94df05e3330d 176 writeData((VT>>8)&0xFF); // VT[10:8] : High byte of the vertical total (display + non-display) period in lines
sPymbed 0:94df05e3330d 177 writeData(VT&0xFF); // VT[7:0] : Low byte of the vertical total (display + non-display) period in lines
sPymbed 0:94df05e3330d 178 writeData((VPS>>8)&0xFF); // VPS[10:8] : High byte the non-display period in lines between the start of the frame and the first display data in line
sPymbed 0:94df05e3330d 179 writeData(VPS&0xFF); // VPS[7:0] : The non-display period in lines between the start of the frame and the first display data in line
sPymbed 0:94df05e3330d 180 writeData(VPW&0xFF); // VPW[6:0] : Set the vertical sync pulse width (LFRAME) in lines
sPymbed 0:94df05e3330d 181 writeData((FPS>>8)&0xFF); // FPS[10:8] : High byte of the vertical sync pulse (LFRAME) start location in lines
sPymbed 0:94df05e3330d 182 writeData(FPS&0xFF); // FPS[7:0] : Low byte of the vertical sync pulse (LFRAME) start location in lines
sPymbed 0:94df05e3330d 183 */
sPymbed 2:d8a9ebd28f0a 184 #define VT (DISP_VER_PULSE_WIDTH + DISP_VER_BACK_PORCH + DISP_VER_FRONT_PORCH + DISP_VER_RESOLUTION)
sPymbed 2:d8a9ebd28f0a 185 WriteData((VT - 1) >> 8);
sPymbed 2:d8a9ebd28f0a 186 WriteData(VT - 1);
sPymbed 2:d8a9ebd28f0a 187 #define VSP (DISP_VER_PULSE_WIDTH + DISP_VER_BACK_PORCH)
sPymbed 2:d8a9ebd28f0a 188 WriteData((VSP - 1) >> 8);
sPymbed 2:d8a9ebd28f0a 189 WriteData(VSP - 1);
sPymbed 2:d8a9ebd28f0a 190 WriteData(DISP_VER_PULSE_WIDTH - 1);
sPymbed 2:d8a9ebd28f0a 191 WriteData(0x00);
sPymbed 2:d8a9ebd28f0a 192 WriteData(0x00);
sPymbed 2:d8a9ebd28f0a 193
sPymbed 0:94df05e3330d 194 // Set GPIO Value ---------------------------------------------------------
sPymbed 0:94df05e3330d 195 // @Parameters : 1
sPymbed 2:d8a9ebd28f0a 196 WriteCmd(Com_SetGPIOValue);
sPymbed 2:d8a9ebd28f0a 197 WriteData(0x0f); // A[3..0] : GPIO[2:0] Output 1
sPymbed 0:94df05e3330d 198
sPymbed 0:94df05e3330d 199 // Set GPIO Configuration
sPymbed 0:94df05e3330d 200 // @Parameters : 2
sPymbed 2:d8a9ebd28f0a 201 WriteCmd(Com_SetGPIOConf);
sPymbed 2:d8a9ebd28f0a 202 WriteData(0x07); // A[7..0] : GPIO3 = Input, GPIO[2:0] = Output
sPymbed 2:d8a9ebd28f0a 203 WriteData(0x01); // B[0] : GPIO0 Normal
sPymbed 0:94df05e3330d 204
sPymbed 2:d8a9ebd28f0a 205 //Set pixel format, i.e. the bpp
sPymbed 2:d8a9ebd28f0a 206 //writeCommand(Com_SetPixelFormat);
sPymbed 2:d8a9ebd28f0a 207 //writeData(0x55); // set 16bpp
sPymbed 0:94df05e3330d 208
sPymbed 0:94df05e3330d 209 // Set Address Mode -------------------------------------------------------
sPymbed 0:94df05e3330d 210 // @Parameters : 1
sPymbed 0:94df05e3330d 211 //writeCommand(0x36); // Set Rotation
sPymbed 2:d8a9ebd28f0a 212 //writeData(0x2a); // A[7..0] : Set the read order from host processor to frame buffer by A[7:5] and A[3] and
sPymbed 0:94df05e3330d 213 // from frame buffer to the display panel by A[2:0] and A[4].
sPymbed 0:94df05e3330d 214 // A[7] : Page address order
sPymbed 2:d8a9ebd28f0a 215
sPymbed 0:94df05e3330d 216 // Set Pixel Data Interface -----------------------------------------------
sPymbed 0:94df05e3330d 217 // @Parameters : 1
sPymbed 2:d8a9ebd28f0a 218 WriteCmd(Com_SetPixelInterface); // A[2:0] : Pixel Data Interface Format
sPymbed 2:d8a9ebd28f0a 219 WriteData(0x03); // 16-bit (565 format)
sPymbed 0:94df05e3330d 220 wait_us(100);
sPymbed 0:94df05e3330d 221
sPymbed 2:d8a9ebd28f0a 222 /*writeCommand(Com_SetTearOff);*/
sPymbed 1:74bac5f988d8 223 wait_ms(1);
sPymbed 2:d8a9ebd28f0a 224 WriteCmd(Com_SetGPIOConf);
sPymbed 2:d8a9ebd28f0a 225 WriteData(0x0f); //GPIO is controlled by host GPIO[3:0]=output GPIO[0]=1 LCD ON GPIO[0]=1 LCD OFF
sPymbed 2:d8a9ebd28f0a 226 WriteData(0x01); //GPIO0 normal
sPymbed 2:d8a9ebd28f0a 227
sPymbed 2:d8a9ebd28f0a 228 WriteCmd(Com_SetGPIOValue);
sPymbed 2:d8a9ebd28f0a 229 WriteData(0x01); //GPIO[0] out 1 --- LCD display on/off control PIN
sPymbed 1:74bac5f988d8 230
sPymbed 0:94df05e3330d 231 // enter_partial_mode
sPymbed 0:94df05e3330d 232 //writeCommand(0x12); // Part of the display area is used for image display
sPymbed 0:94df05e3330d 233 // set_display_on
sPymbed 2:d8a9ebd28f0a 234 WriteCmd(Com_SetDisplayOn); // Show the image on the display device
sPymbed 2:d8a9ebd28f0a 235
sPymbed 0:94df05e3330d 236 //writeCommand(0x2C);
sPymbed 0:94df05e3330d 237 }
sPymbed 0:94df05e3330d 238
sPymbed 2:d8a9ebd28f0a 239 void SSD1963::SetXY( unsigned short x1, unsigned short y1, unsigned short x2, unsigned short y2 )
sPymbed 2:d8a9ebd28f0a 240 {
sPymbed 2:d8a9ebd28f0a 241 //if ( _orientation == PORTRAIT || _orientation == PORTRAIT_REV )
sPymbed 2:d8a9ebd28f0a 242 //{
sPymbed 2:d8a9ebd28f0a 243 WriteCmd(Com_SetColumnAddress);
sPymbed 2:d8a9ebd28f0a 244 WriteData( x1>>8 );
sPymbed 2:d8a9ebd28f0a 245 WriteData( x1 );
sPymbed 2:d8a9ebd28f0a 246 WriteData( x2>>8 );
sPymbed 2:d8a9ebd28f0a 247 WriteData( x2 );
sPymbed 2:d8a9ebd28f0a 248 WriteCmd( Com_SetPageAddress);
sPymbed 2:d8a9ebd28f0a 249 WriteData( y1>>8 );
sPymbed 2:d8a9ebd28f0a 250 WriteData( y1 );
sPymbed 2:d8a9ebd28f0a 251 WriteData( y2>>8 );
sPymbed 2:d8a9ebd28f0a 252 WriteData( y2 );
sPymbed 2:d8a9ebd28f0a 253 /*}
sPymbed 2:d8a9ebd28f0a 254 else
sPymbed 2:d8a9ebd28f0a 255 {
sPymbed 2:d8a9ebd28f0a 256 WriteCmd( 0x2A);
sPymbed 2:d8a9ebd28f0a 257 WriteData( y1>>8 );
sPymbed 2:d8a9ebd28f0a 258 WriteData( y1 );
sPymbed 2:d8a9ebd28f0a 259 WriteData( y2>>8 );
sPymbed 2:d8a9ebd28f0a 260 WriteData( y2 );
sPymbed 2:d8a9ebd28f0a 261 WriteCmd( 0x2B);
sPymbed 2:d8a9ebd28f0a 262 WriteData( x1>>8 );
sPymbed 2:d8a9ebd28f0a 263 WriteData( x1 );
sPymbed 2:d8a9ebd28f0a 264 WriteData( x2>>8 );
sPymbed 2:d8a9ebd28f0a 265 WriteData( x2 );
sPymbed 2:d8a9ebd28f0a 266 WriteCmd( 0x2B);
sPymbed 2:d8a9ebd28f0a 267 }*/
sPymbed 2:d8a9ebd28f0a 268 WriteCmd(Com_WriteMemory);
sPymbed 2:d8a9ebd28f0a 269 }
sPymbed 0:94df05e3330d 270
sPymbed 2:d8a9ebd28f0a 271 void SSD1963::SetPixelColor( unsigned int color, colordepth_t mode )
sPymbed 2:d8a9ebd28f0a 272 {
sPymbed 2:d8a9ebd28f0a 273 unsigned char r, g, b;
sPymbed 2:d8a9ebd28f0a 274 unsigned short clr;
sPymbed 2:d8a9ebd28f0a 275 if ( _colorDepth == RGB16 )
sPymbed 2:d8a9ebd28f0a 276 {
sPymbed 2:d8a9ebd28f0a 277 switch ( mode )
sPymbed 2:d8a9ebd28f0a 278 {
sPymbed 2:d8a9ebd28f0a 279 case RGB16:
sPymbed 2:d8a9ebd28f0a 280 WriteData( color & 0xFFFF );
sPymbed 2:d8a9ebd28f0a 281 break;
sPymbed 2:d8a9ebd28f0a 282 case RGB18:
sPymbed 2:d8a9ebd28f0a 283 r = ( color >> 10 ) & 0xF8;
sPymbed 2:d8a9ebd28f0a 284 g = ( color >> 4 ) & 0xFC;
sPymbed 2:d8a9ebd28f0a 285 b = ( color >> 1 ) & 0x1F;
sPymbed 2:d8a9ebd28f0a 286 clr = ( ( r | ( g >> 5 ) ) << 8 ) | ( ( g << 3 ) | b );
sPymbed 2:d8a9ebd28f0a 287 WriteData( clr );
sPymbed 2:d8a9ebd28f0a 288 break;
sPymbed 2:d8a9ebd28f0a 289 case RGB24:
sPymbed 2:d8a9ebd28f0a 290 r = ( color >> 16 ) & 0xF8;
sPymbed 2:d8a9ebd28f0a 291 g = ( color >> 8 ) & 0xFC;
sPymbed 2:d8a9ebd28f0a 292 b = color & 0xF8;
sPymbed 2:d8a9ebd28f0a 293 clr = ( ( r | ( g >> 5 ) ) << 8 ) | ( ( g << 3 ) | ( b >> 3 ) );
sPymbed 2:d8a9ebd28f0a 294 WriteData( clr );
sPymbed 2:d8a9ebd28f0a 295 break;
sPymbed 2:d8a9ebd28f0a 296 }
sPymbed 2:d8a9ebd28f0a 297 }
sPymbed 2:d8a9ebd28f0a 298 else if ( _colorDepth == RGB18 )
sPymbed 2:d8a9ebd28f0a 299 {
sPymbed 2:d8a9ebd28f0a 300 switch ( mode )
sPymbed 2:d8a9ebd28f0a 301 {
sPymbed 2:d8a9ebd28f0a 302 case RGB16:
sPymbed 2:d8a9ebd28f0a 303 r = ( ( color >> 8 ) & 0xF8 ) | ( ( color & 0x8000 ) >> 13 );
sPymbed 2:d8a9ebd28f0a 304 g = ( color >> 3 ) & 0xFC;
sPymbed 2:d8a9ebd28f0a 305 b = ( ( color << 3 ) & 0xFC ) | ( ( color >> 3 ) & 0x01 );
sPymbed 2:d8a9ebd28f0a 306 WriteData( ( r << 8 ) | g );
sPymbed 2:d8a9ebd28f0a 307 WriteData( b );
sPymbed 2:d8a9ebd28f0a 308 break;
sPymbed 2:d8a9ebd28f0a 309 case RGB18:
sPymbed 2:d8a9ebd28f0a 310 b = ( color << 2 ) & 0xFC;
sPymbed 2:d8a9ebd28f0a 311 g = ( color >> 4 ) & 0xFC;
sPymbed 2:d8a9ebd28f0a 312 r = ( color >> 10 ) & 0xFC;
sPymbed 2:d8a9ebd28f0a 313 WriteData( ( r << 8 ) | g );
sPymbed 2:d8a9ebd28f0a 314 WriteData( b );
sPymbed 2:d8a9ebd28f0a 315 break;
sPymbed 2:d8a9ebd28f0a 316 case RGB24:
sPymbed 2:d8a9ebd28f0a 317 r = ( color >> 16 ) & 0xFC;
sPymbed 2:d8a9ebd28f0a 318 g = ( color >> 8 ) & 0xFC;
sPymbed 2:d8a9ebd28f0a 319 b = color & 0xFC;
sPymbed 2:d8a9ebd28f0a 320 WriteData( ( r << 8 ) | g );
sPymbed 2:d8a9ebd28f0a 321 WriteData( b );
sPymbed 2:d8a9ebd28f0a 322 break;
sPymbed 0:94df05e3330d 323 }
sPymbed 0:94df05e3330d 324 }
sPymbed 0:94df05e3330d 325 }
sPymbed 0:94df05e3330d 326
sPymbed 0:94df05e3330d 327 // - Color RGB R5 G6 B5 -------------------------------------------------------
sPymbed 0:94df05e3330d 328 uint16_t SSD1963::Color565(uint8_t r, uint8_t g, uint8_t b) {
sPymbed 0:94df05e3330d 329 uint16_t c;
sPymbed 0:94df05e3330d 330 c = r >> 3;
sPymbed 0:94df05e3330d 331 c <<= 6;
sPymbed 0:94df05e3330d 332 c |= g >> 2;
sPymbed 0:94df05e3330d 333 c <<= 5;
sPymbed 0:94df05e3330d 334 c |= b >> 3;
sPymbed 0:94df05e3330d 335 return c;
sPymbed 0:94df05e3330d 336 }