Руслан Бредун / Mbed 2 deprecated stm32-sensor-base2

test

Dependencies:   mbed Watchdog

Dependents:   STM32-MC_node

mbed/hal/spi_api.h@0:d383e2dee0f7, 2020-07-06 (annotated)

Committer:
ommpy
Date:
Mon Jul 06 17:18:59 2020 +0530
Revision:
0:d383e2dee0f7
first commit

Who changed what in which revision?

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ommpy 0:d383e2dee0f7 1
ommpy 0:d383e2dee0f7 2 /** \addtogroup hal */
ommpy 0:d383e2dee0f7 3 /** @{*/
ommpy 0:d383e2dee0f7 4 /* mbed Microcontroller Library
ommpy 0:d383e2dee0f7 5 * Copyright (c) 2006-2013 ARM Limited
ommpy 0:d383e2dee0f7 6 * SPDX-License-Identifier: Apache-2.0
ommpy 0:d383e2dee0f7 7 *
ommpy 0:d383e2dee0f7 8 * Licensed under the Apache License, Version 2.0 (the "License");
ommpy 0:d383e2dee0f7 9 * you may not use this file except in compliance with the License.
ommpy 0:d383e2dee0f7 10 * You may obtain a copy of the License at
ommpy 0:d383e2dee0f7 11 *
ommpy 0:d383e2dee0f7 12 * http://www.apache.org/licenses/LICENSE-2.0
ommpy 0:d383e2dee0f7 13 *
ommpy 0:d383e2dee0f7 14 * Unless required by applicable law or agreed to in writing, software
ommpy 0:d383e2dee0f7 15 * distributed under the License is distributed on an "AS IS" BASIS,
ommpy 0:d383e2dee0f7 16 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
ommpy 0:d383e2dee0f7 17 * See the License for the specific language governing permissions and
ommpy 0:d383e2dee0f7 18 * limitations under the License.
ommpy 0:d383e2dee0f7 19 */
ommpy 0:d383e2dee0f7 20 #ifndef MBED_SPI_API_H
ommpy 0:d383e2dee0f7 21 #define MBED_SPI_API_H
ommpy 0:d383e2dee0f7 22
ommpy 0:d383e2dee0f7 23 #include "device.h"
ommpy 0:d383e2dee0f7 24 #include "hal/dma_api.h"
ommpy 0:d383e2dee0f7 25 #include "hal/buffer.h"
ommpy 0:d383e2dee0f7 26
ommpy 0:d383e2dee0f7 27 #if DEVICE_SPI
ommpy 0:d383e2dee0f7 28
ommpy 0:d383e2dee0f7 29 #define SPI_EVENT_ERROR (1 << 1)
ommpy 0:d383e2dee0f7 30 #define SPI_EVENT_COMPLETE (1 << 2)
ommpy 0:d383e2dee0f7 31 #define SPI_EVENT_RX_OVERFLOW (1 << 3)
ommpy 0:d383e2dee0f7 32 #define SPI_EVENT_ALL (SPI_EVENT_ERROR | SPI_EVENT_COMPLETE | SPI_EVENT_RX_OVERFLOW)
ommpy 0:d383e2dee0f7 33
ommpy 0:d383e2dee0f7 34 #define SPI_EVENT_INTERNAL_TRANSFER_COMPLETE (1 << 30) // Internal flag to report that an event occurred
ommpy 0:d383e2dee0f7 35
ommpy 0:d383e2dee0f7 36 #define SPI_FILL_WORD (0xFFFF)
ommpy 0:d383e2dee0f7 37 #define SPI_FILL_CHAR (0xFF)
ommpy 0:d383e2dee0f7 38
ommpy 0:d383e2dee0f7 39 #if DEVICE_SPI_ASYNCH
ommpy 0:d383e2dee0f7 40 /** Asynch SPI HAL structure
ommpy 0:d383e2dee0f7 41 */
ommpy 0:d383e2dee0f7 42 typedef struct {
ommpy 0:d383e2dee0f7 43 struct spi_s spi; /**< Target specific SPI structure */
ommpy 0:d383e2dee0f7 44 struct buffer_s tx_buff; /**< Tx buffer */
ommpy 0:d383e2dee0f7 45 struct buffer_s rx_buff; /**< Rx buffer */
ommpy 0:d383e2dee0f7 46 } spi_t;
ommpy 0:d383e2dee0f7 47
ommpy 0:d383e2dee0f7 48 #else
ommpy 0:d383e2dee0f7 49 /** Non-asynch SPI HAL structure
ommpy 0:d383e2dee0f7 50 */
ommpy 0:d383e2dee0f7 51 typedef struct spi_s spi_t;
ommpy 0:d383e2dee0f7 52
ommpy 0:d383e2dee0f7 53 #endif
ommpy 0:d383e2dee0f7 54
ommpy 0:d383e2dee0f7 55 #ifdef __cplusplus
ommpy 0:d383e2dee0f7 56 extern "C" {
ommpy 0:d383e2dee0f7 57 #endif
ommpy 0:d383e2dee0f7 58
ommpy 0:d383e2dee0f7 59 /**
ommpy 0:d383e2dee0f7 60 * \defgroup hal_GeneralSPI SPI Configuration Functions
ommpy 0:d383e2dee0f7 61 * @{
ommpy 0:d383e2dee0f7 62 */
ommpy 0:d383e2dee0f7 63
ommpy 0:d383e2dee0f7 64 /** Initialize the SPI peripheral
ommpy 0:d383e2dee0f7 65 *
ommpy 0:d383e2dee0f7 66 * Configures the pins used by SPI, sets a default format and frequency, and enables the peripheral
ommpy 0:d383e2dee0f7 67 * @param[out] obj The SPI object to initialize
ommpy 0:d383e2dee0f7 68 * @param[in] mosi The pin to use for MOSI
ommpy 0:d383e2dee0f7 69 * @param[in] miso The pin to use for MISO
ommpy 0:d383e2dee0f7 70 * @param[in] sclk The pin to use for SCLK
ommpy 0:d383e2dee0f7 71 * @param[in] ssel The pin to use for SSEL
ommpy 0:d383e2dee0f7 72 */
ommpy 0:d383e2dee0f7 73 void spi_init(spi_t *obj, PinName mosi, PinName miso, PinName sclk, PinName ssel);
ommpy 0:d383e2dee0f7 74
ommpy 0:d383e2dee0f7 75 /** Release a SPI object
ommpy 0:d383e2dee0f7 76 *
ommpy 0:d383e2dee0f7 77 * TODO: spi_free is currently unimplemented
ommpy 0:d383e2dee0f7 78 * This will require reference counting at the C++ level to be safe
ommpy 0:d383e2dee0f7 79 *
ommpy 0:d383e2dee0f7 80 * Return the pins owned by the SPI object to their reset state
ommpy 0:d383e2dee0f7 81 * Disable the SPI peripheral
ommpy 0:d383e2dee0f7 82 * Disable the SPI clock
ommpy 0:d383e2dee0f7 83 * @param[in] obj The SPI object to deinitialize
ommpy 0:d383e2dee0f7 84 */
ommpy 0:d383e2dee0f7 85 void spi_free(spi_t *obj);
ommpy 0:d383e2dee0f7 86
ommpy 0:d383e2dee0f7 87 /** Configure the SPI format
ommpy 0:d383e2dee0f7 88 *
ommpy 0:d383e2dee0f7 89 * Set the number of bits per frame, configure clock polarity and phase, shift order and master/slave mode.
ommpy 0:d383e2dee0f7 90 * The default bit order is MSB.
ommpy 0:d383e2dee0f7 91 * @param[in,out] obj The SPI object to configure
ommpy 0:d383e2dee0f7 92 * @param[in] bits The number of bits per frame
ommpy 0:d383e2dee0f7 93 * @param[in] mode The SPI mode (clock polarity, phase, and shift direction)
ommpy 0:d383e2dee0f7 94 * @param[in] slave Zero for master mode or non-zero for slave mode
ommpy 0:d383e2dee0f7 95 */
ommpy 0:d383e2dee0f7 96 void spi_format(spi_t *obj, int bits, int mode, int slave);
ommpy 0:d383e2dee0f7 97
ommpy 0:d383e2dee0f7 98 /** Set the SPI baud rate
ommpy 0:d383e2dee0f7 99 *
ommpy 0:d383e2dee0f7 100 * Actual frequency may differ from the desired frequency due to available dividers and bus clock
ommpy 0:d383e2dee0f7 101 * Configures the SPI peripheral's baud rate
ommpy 0:d383e2dee0f7 102 * @param[in,out] obj The SPI object to configure
ommpy 0:d383e2dee0f7 103 * @param[in] hz The baud rate in Hz
ommpy 0:d383e2dee0f7 104 */
ommpy 0:d383e2dee0f7 105 void spi_frequency(spi_t *obj, int hz);
ommpy 0:d383e2dee0f7 106
ommpy 0:d383e2dee0f7 107 /**@}*/
ommpy 0:d383e2dee0f7 108 /**
ommpy 0:d383e2dee0f7 109 * \defgroup SynchSPI Synchronous SPI Hardware Abstraction Layer
ommpy 0:d383e2dee0f7 110 * @{
ommpy 0:d383e2dee0f7 111 */
ommpy 0:d383e2dee0f7 112
ommpy 0:d383e2dee0f7 113 /** Write a byte out in master mode and receive a value
ommpy 0:d383e2dee0f7 114 *
ommpy 0:d383e2dee0f7 115 * @param[in] obj The SPI peripheral to use for sending
ommpy 0:d383e2dee0f7 116 * @param[in] value The value to send
ommpy 0:d383e2dee0f7 117 * @return Returns the value received during send
ommpy 0:d383e2dee0f7 118 */
ommpy 0:d383e2dee0f7 119 int spi_master_write(spi_t *obj, int value);
ommpy 0:d383e2dee0f7 120
ommpy 0:d383e2dee0f7 121 /** Write a block out in master mode and receive a value
ommpy 0:d383e2dee0f7 122 *
ommpy 0:d383e2dee0f7 123 * The total number of bytes sent and received will be the maximum of
ommpy 0:d383e2dee0f7 124 * tx_length and rx_length. The bytes written will be padded with the
ommpy 0:d383e2dee0f7 125 * value 0xff.
ommpy 0:d383e2dee0f7 126 *
ommpy 0:d383e2dee0f7 127 * @param[in] obj The SPI peripheral to use for sending
ommpy 0:d383e2dee0f7 128 * @param[in] tx_buffer Pointer to the byte-array of data to write to the device
ommpy 0:d383e2dee0f7 129 * @param[in] tx_length Number of bytes to write, may be zero
ommpy 0:d383e2dee0f7 130 * @param[in] rx_buffer Pointer to the byte-array of data to read from the device
ommpy 0:d383e2dee0f7 131 * @param[in] rx_length Number of bytes to read, may be zero
ommpy 0:d383e2dee0f7 132 * @param[in] write_fill Default data transmitted while performing a read
ommpy 0:d383e2dee0f7 133 * @returns
ommpy 0:d383e2dee0f7 134 * The number of bytes written and read from the device. This is
ommpy 0:d383e2dee0f7 135 * maximum of tx_length and rx_length.
ommpy 0:d383e2dee0f7 136 */
ommpy 0:d383e2dee0f7 137 int spi_master_block_write(spi_t *obj, const char *tx_buffer, int tx_length, char *rx_buffer, int rx_length, char write_fill);
ommpy 0:d383e2dee0f7 138
ommpy 0:d383e2dee0f7 139 /** Check if a value is available to read
ommpy 0:d383e2dee0f7 140 *
ommpy 0:d383e2dee0f7 141 * @param[in] obj The SPI peripheral to check
ommpy 0:d383e2dee0f7 142 * @return non-zero if a value is available
ommpy 0:d383e2dee0f7 143 */
ommpy 0:d383e2dee0f7 144 int spi_slave_receive(spi_t *obj);
ommpy 0:d383e2dee0f7 145
ommpy 0:d383e2dee0f7 146 /** Get a received value out of the SPI receive buffer in slave mode
ommpy 0:d383e2dee0f7 147 *
ommpy 0:d383e2dee0f7 148 * Blocks until a value is available
ommpy 0:d383e2dee0f7 149 * @param[in] obj The SPI peripheral to read
ommpy 0:d383e2dee0f7 150 * @return The value received
ommpy 0:d383e2dee0f7 151 */
ommpy 0:d383e2dee0f7 152 int spi_slave_read(spi_t *obj);
ommpy 0:d383e2dee0f7 153
ommpy 0:d383e2dee0f7 154 /** Write a value to the SPI peripheral in slave mode
ommpy 0:d383e2dee0f7 155 *
ommpy 0:d383e2dee0f7 156 * Blocks until the SPI peripheral can be written to
ommpy 0:d383e2dee0f7 157 * @param[in] obj The SPI peripheral to write
ommpy 0:d383e2dee0f7 158 * @param[in] value The value to write
ommpy 0:d383e2dee0f7 159 */
ommpy 0:d383e2dee0f7 160 void spi_slave_write(spi_t *obj, int value);
ommpy 0:d383e2dee0f7 161
ommpy 0:d383e2dee0f7 162 /** Checks if the specified SPI peripheral is in use
ommpy 0:d383e2dee0f7 163 *
ommpy 0:d383e2dee0f7 164 * @param[in] obj The SPI peripheral to check
ommpy 0:d383e2dee0f7 165 * @return non-zero if the peripheral is currently transmitting
ommpy 0:d383e2dee0f7 166 */
ommpy 0:d383e2dee0f7 167 int spi_busy(spi_t *obj);
ommpy 0:d383e2dee0f7 168
ommpy 0:d383e2dee0f7 169 /** Get the module number
ommpy 0:d383e2dee0f7 170 *
ommpy 0:d383e2dee0f7 171 * @param[in] obj The SPI peripheral to check
ommpy 0:d383e2dee0f7 172 * @return The module number
ommpy 0:d383e2dee0f7 173 */
ommpy 0:d383e2dee0f7 174 uint8_t spi_get_module(spi_t *obj);
ommpy 0:d383e2dee0f7 175
ommpy 0:d383e2dee0f7 176 /**@}*/
ommpy 0:d383e2dee0f7 177
ommpy 0:d383e2dee0f7 178 #if DEVICE_SPI_ASYNCH
ommpy 0:d383e2dee0f7 179 /**
ommpy 0:d383e2dee0f7 180 * \defgroup AsynchSPI Asynchronous SPI Hardware Abstraction Layer
ommpy 0:d383e2dee0f7 181 * @{
ommpy 0:d383e2dee0f7 182 */
ommpy 0:d383e2dee0f7 183
ommpy 0:d383e2dee0f7 184 /** Begin the SPI transfer. Buffer pointers and lengths are specified in tx_buff and rx_buff
ommpy 0:d383e2dee0f7 185 *
ommpy 0:d383e2dee0f7 186 * @param[in] obj The SPI object that holds the transfer information
ommpy 0:d383e2dee0f7 187 * @param[in] tx The transmit buffer
ommpy 0:d383e2dee0f7 188 * @param[in] tx_length The number of bytes to transmit
ommpy 0:d383e2dee0f7 189 * @param[in] rx The receive buffer
ommpy 0:d383e2dee0f7 190 * @param[in] rx_length The number of bytes to receive
ommpy 0:d383e2dee0f7 191 * @param[in] bit_width The bit width of buffer words
ommpy 0:d383e2dee0f7 192 * @param[in] event The logical OR of events to be registered
ommpy 0:d383e2dee0f7 193 * @param[in] handler SPI interrupt handler
ommpy 0:d383e2dee0f7 194 * @param[in] hint A suggestion for how to use DMA with this transfer
ommpy 0:d383e2dee0f7 195 */
ommpy 0:d383e2dee0f7 196 void spi_master_transfer(spi_t *obj, const void *tx, size_t tx_length, void *rx, size_t rx_length, uint8_t bit_width, uint32_t handler, uint32_t event, DMAUsage hint);
ommpy 0:d383e2dee0f7 197
ommpy 0:d383e2dee0f7 198 /** The asynchronous IRQ handler
ommpy 0:d383e2dee0f7 199 *
ommpy 0:d383e2dee0f7 200 * Reads the received values out of the RX FIFO, writes values into the TX FIFO and checks for transfer termination
ommpy 0:d383e2dee0f7 201 * conditions, such as buffer overflows or transfer complete.
ommpy 0:d383e2dee0f7 202 * @param[in] obj The SPI object that holds the transfer information
ommpy 0:d383e2dee0f7 203 * @return Event flags if a transfer termination condition was met; otherwise 0.
ommpy 0:d383e2dee0f7 204 */
ommpy 0:d383e2dee0f7 205 uint32_t spi_irq_handler_asynch(spi_t *obj);
ommpy 0:d383e2dee0f7 206
ommpy 0:d383e2dee0f7 207 /** Attempts to determine if the SPI peripheral is already in use
ommpy 0:d383e2dee0f7 208 *
ommpy 0:d383e2dee0f7 209 * If a temporary DMA channel has been allocated, peripheral is in use.
ommpy 0:d383e2dee0f7 210 * If a permanent DMA channel has been allocated, check if the DMA channel is in use. If not, proceed as though no DMA
ommpy 0:d383e2dee0f7 211 * channel were allocated.
ommpy 0:d383e2dee0f7 212 * If no DMA channel is allocated, check whether tx and rx buffers have been assigned. For each assigned buffer, check
ommpy 0:d383e2dee0f7 213 * if the corresponding buffer position is less than the buffer length. If buffers do not indicate activity, check if
ommpy 0:d383e2dee0f7 214 * there are any bytes in the FIFOs.
ommpy 0:d383e2dee0f7 215 * @param[in] obj The SPI object to check for activity
ommpy 0:d383e2dee0f7 216 * @return Non-zero if the SPI port is active or zero if it is not.
ommpy 0:d383e2dee0f7 217 */
ommpy 0:d383e2dee0f7 218 uint8_t spi_active(spi_t *obj);
ommpy 0:d383e2dee0f7 219
ommpy 0:d383e2dee0f7 220 /** Abort an SPI transfer
ommpy 0:d383e2dee0f7 221 *
ommpy 0:d383e2dee0f7 222 * @param obj The SPI peripheral to stop
ommpy 0:d383e2dee0f7 223 */
ommpy 0:d383e2dee0f7 224 void spi_abort_asynch(spi_t *obj);
ommpy 0:d383e2dee0f7 225
ommpy 0:d383e2dee0f7 226
ommpy 0:d383e2dee0f7 227 #endif
ommpy 0:d383e2dee0f7 228
ommpy 0:d383e2dee0f7 229 /**@}*/
ommpy 0:d383e2dee0f7 230
ommpy 0:d383e2dee0f7 231 #ifdef __cplusplus
ommpy 0:d383e2dee0f7 232 }
ommpy 0:d383e2dee0f7 233 #endif // __cplusplus
ommpy 0:d383e2dee0f7 234
ommpy 0:d383e2dee0f7 235 #endif // SPI_DEVICE
ommpy 0:d383e2dee0f7 236
ommpy 0:d383e2dee0f7 237 #endif // MBED_SPI_API_H
ommpy 0:d383e2dee0f7 238
ommpy 0:d383e2dee0f7 239 /** @}*/