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Dependencies:   mbed Watchdog

Dependents:   STM32-MC_node

mbed/TARGET_NUCLEO_F030R8/stm32f030x8.h@0:d383e2dee0f7, 2020-07-06 (annotated)

Committer:
ommpy
Date:
Mon Jul 06 17:18:59 2020 +0530
Revision:
0:d383e2dee0f7
first commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ommpy 0:d383e2dee0f7 1 /**
ommpy 0:d383e2dee0f7 2 ******************************************************************************
ommpy 0:d383e2dee0f7 3 * @file stm32f030x8.h
ommpy 0:d383e2dee0f7 4 * @author MCD Application Team
ommpy 0:d383e2dee0f7 5 * @version V2.2.2
ommpy 0:d383e2dee0f7 6 * @date 26-June-2015
ommpy 0:d383e2dee0f7 7 * @brief CMSIS STM32F030x8 devices Peripheral Access Layer Header File.
ommpy 0:d383e2dee0f7 8 *
ommpy 0:d383e2dee0f7 9 * This file contains:
ommpy 0:d383e2dee0f7 10 * - Data structures and the address mapping for all peripherals
ommpy 0:d383e2dee0f7 11 * - Peripheral's registers declarations and bits definition
ommpy 0:d383e2dee0f7 12 * - Macros to access peripheral’s registers hardware
ommpy 0:d383e2dee0f7 13 *
ommpy 0:d383e2dee0f7 14 ******************************************************************************
ommpy 0:d383e2dee0f7 15 * @attention
ommpy 0:d383e2dee0f7 16 *
ommpy 0:d383e2dee0f7 17 * <h2><center>&copy; COPYRIGHT(c) 2015 STMicroelectronics</center></h2>
ommpy 0:d383e2dee0f7 18 *
ommpy 0:d383e2dee0f7 19 * Redistribution and use in source and binary forms, with or without modification,
ommpy 0:d383e2dee0f7 20 * are permitted provided that the following conditions are met:
ommpy 0:d383e2dee0f7 21 * 1. Redistributions of source code must retain the above copyright notice,
ommpy 0:d383e2dee0f7 22 * this list of conditions and the following disclaimer.
ommpy 0:d383e2dee0f7 23 * 2. Redistributions in binary form must reproduce the above copyright notice,
ommpy 0:d383e2dee0f7 24 * this list of conditions and the following disclaimer in the documentation
ommpy 0:d383e2dee0f7 25 * and/or other materials provided with the distribution.
ommpy 0:d383e2dee0f7 26 * 3. Neither the name of STMicroelectronics nor the names of its contributors
ommpy 0:d383e2dee0f7 27 * may be used to endorse or promote products derived from this software
ommpy 0:d383e2dee0f7 28 * without specific prior written permission.
ommpy 0:d383e2dee0f7 29 *
ommpy 0:d383e2dee0f7 30 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
ommpy 0:d383e2dee0f7 31 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
ommpy 0:d383e2dee0f7 32 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
ommpy 0:d383e2dee0f7 33 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
ommpy 0:d383e2dee0f7 34 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
ommpy 0:d383e2dee0f7 35 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
ommpy 0:d383e2dee0f7 36 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
ommpy 0:d383e2dee0f7 37 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
ommpy 0:d383e2dee0f7 38 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
ommpy 0:d383e2dee0f7 39 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
ommpy 0:d383e2dee0f7 40 *
ommpy 0:d383e2dee0f7 41 ******************************************************************************
ommpy 0:d383e2dee0f7 42 */
ommpy 0:d383e2dee0f7 43
ommpy 0:d383e2dee0f7 44 /** @addtogroup CMSIS_Device
ommpy 0:d383e2dee0f7 45 * @{
ommpy 0:d383e2dee0f7 46 */
ommpy 0:d383e2dee0f7 47
ommpy 0:d383e2dee0f7 48 /** @addtogroup stm32f030x8
ommpy 0:d383e2dee0f7 49 * @{
ommpy 0:d383e2dee0f7 50 */
ommpy 0:d383e2dee0f7 51
ommpy 0:d383e2dee0f7 52 #ifndef __STM32F030x8_H
ommpy 0:d383e2dee0f7 53 #define __STM32F030x8_H
ommpy 0:d383e2dee0f7 54
ommpy 0:d383e2dee0f7 55 #ifdef __cplusplus
ommpy 0:d383e2dee0f7 56 extern "C" {
ommpy 0:d383e2dee0f7 57 #endif /* __cplusplus */
ommpy 0:d383e2dee0f7 58
ommpy 0:d383e2dee0f7 59 /** @addtogroup Configuration_section_for_CMSIS
ommpy 0:d383e2dee0f7 60 * @{
ommpy 0:d383e2dee0f7 61 */
ommpy 0:d383e2dee0f7 62 /**
ommpy 0:d383e2dee0f7 63 * @brief Configuration of the Cortex-M0 Processor and Core Peripherals
ommpy 0:d383e2dee0f7 64 */
ommpy 0:d383e2dee0f7 65 #define __CM0_REV 0 /*!< Core Revision r0p0 */
ommpy 0:d383e2dee0f7 66 #define __MPU_PRESENT 0 /*!< STM32F0xx do not provide MPU */
ommpy 0:d383e2dee0f7 67 #define __NVIC_PRIO_BITS 2 /*!< STM32F0xx uses 2 Bits for the Priority Levels */
ommpy 0:d383e2dee0f7 68 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
ommpy 0:d383e2dee0f7 69
ommpy 0:d383e2dee0f7 70 /**
ommpy 0:d383e2dee0f7 71 * @}
ommpy 0:d383e2dee0f7 72 */
ommpy 0:d383e2dee0f7 73
ommpy 0:d383e2dee0f7 74 /** @addtogroup Peripheral_interrupt_number_definition
ommpy 0:d383e2dee0f7 75 * @{
ommpy 0:d383e2dee0f7 76 */
ommpy 0:d383e2dee0f7 77
ommpy 0:d383e2dee0f7 78 /**
ommpy 0:d383e2dee0f7 79 * @brief STM32F030x8 device Interrupt Number Definition
ommpy 0:d383e2dee0f7 80 */
ommpy 0:d383e2dee0f7 81 typedef enum
ommpy 0:d383e2dee0f7 82 {
ommpy 0:d383e2dee0f7 83 /****** Cortex-M0 Processor Exceptions Numbers **************************************************************/
ommpy 0:d383e2dee0f7 84 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
ommpy 0:d383e2dee0f7 85 HardFault_IRQn = -13, /*!< 3 Cortex-M0 Hard Fault Interrupt */
ommpy 0:d383e2dee0f7 86 SVC_IRQn = -5, /*!< 11 Cortex-M0 SV Call Interrupt */
ommpy 0:d383e2dee0f7 87 PendSV_IRQn = -2, /*!< 14 Cortex-M0 Pend SV Interrupt */
ommpy 0:d383e2dee0f7 88 SysTick_IRQn = -1, /*!< 15 Cortex-M0 System Tick Interrupt */
ommpy 0:d383e2dee0f7 89
ommpy 0:d383e2dee0f7 90 /****** STM32F030x8 specific Interrupt Numbers **************************************************************/
ommpy 0:d383e2dee0f7 91 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt */
ommpy 0:d383e2dee0f7 92 RTC_IRQn = 2, /*!< RTC Interrupt through EXTI Lines 17, 19 and 20 */
ommpy 0:d383e2dee0f7 93 FLASH_IRQn = 3, /*!< FLASH global Interrupt */
ommpy 0:d383e2dee0f7 94 RCC_IRQn = 4, /*!< RCC global Interrupt */
ommpy 0:d383e2dee0f7 95 EXTI0_1_IRQn = 5, /*!< EXTI Line 0 and 1 Interrupts */
ommpy 0:d383e2dee0f7 96 EXTI2_3_IRQn = 6, /*!< EXTI Line 2 and 3 Interrupts */
ommpy 0:d383e2dee0f7 97 EXTI4_15_IRQn = 7, /*!< EXTI Line 4 to 15 Interrupts */
ommpy 0:d383e2dee0f7 98 DMA1_Channel1_IRQn = 9, /*!< DMA1 Channel 1 Interrupt */
ommpy 0:d383e2dee0f7 99 DMA1_Channel2_3_IRQn = 10, /*!< DMA1 Channel 2 and Channel 3 Interrupts */
ommpy 0:d383e2dee0f7 100 DMA1_Channel4_5_IRQn = 11, /*!< DMA1 Channel 4 and Channel 5 Interrupts */
ommpy 0:d383e2dee0f7 101 ADC1_IRQn = 12, /*!< ADC1 global Interrupt */
ommpy 0:d383e2dee0f7 102 TIM1_BRK_UP_TRG_COM_IRQn = 13, /*!< TIM1 Break, Update, Trigger and Commutation Interrupts */
ommpy 0:d383e2dee0f7 103 TIM1_CC_IRQn = 14, /*!< TIM1 Capture Compare Interrupt */
ommpy 0:d383e2dee0f7 104 TIM3_IRQn = 16, /*!< TIM3 global Interrupt */
ommpy 0:d383e2dee0f7 105 TIM6_IRQn = 17, /*!< TIM6 global Interrupt */
ommpy 0:d383e2dee0f7 106 TIM14_IRQn = 19, /*!< TIM14 global Interrupt */
ommpy 0:d383e2dee0f7 107 TIM15_IRQn = 20, /*!< TIM15 global Interrupt */
ommpy 0:d383e2dee0f7 108 TIM16_IRQn = 21, /*!< TIM16 global Interrupt */
ommpy 0:d383e2dee0f7 109 TIM17_IRQn = 22, /*!< TIM17 global Interrupt */
ommpy 0:d383e2dee0f7 110 I2C1_IRQn = 23, /*!< I2C1 Event Interrupt */
ommpy 0:d383e2dee0f7 111 I2C2_IRQn = 24, /*!< I2C2 Event Interrupt */
ommpy 0:d383e2dee0f7 112 SPI1_IRQn = 25, /*!< SPI1 global Interrupt */
ommpy 0:d383e2dee0f7 113 SPI2_IRQn = 26, /*!< SPI2 global Interrupt */
ommpy 0:d383e2dee0f7 114 USART1_IRQn = 27, /*!< USART1 global Interrupt */
ommpy 0:d383e2dee0f7 115 USART2_IRQn = 28 /*!< USART2 global Interrupt */
ommpy 0:d383e2dee0f7 116 } IRQn_Type;
ommpy 0:d383e2dee0f7 117
ommpy 0:d383e2dee0f7 118 /**
ommpy 0:d383e2dee0f7 119 * @}
ommpy 0:d383e2dee0f7 120 */
ommpy 0:d383e2dee0f7 121
ommpy 0:d383e2dee0f7 122 #include "core_cm0.h" /* Cortex-M0 processor and core peripherals */
ommpy 0:d383e2dee0f7 123 #include "system_stm32f0xx.h" /* STM32F0xx System Header */
ommpy 0:d383e2dee0f7 124 #include <stdint.h>
ommpy 0:d383e2dee0f7 125
ommpy 0:d383e2dee0f7 126 /** @addtogroup Peripheral_registers_structures
ommpy 0:d383e2dee0f7 127 * @{
ommpy 0:d383e2dee0f7 128 */
ommpy 0:d383e2dee0f7 129
ommpy 0:d383e2dee0f7 130 /**
ommpy 0:d383e2dee0f7 131 * @brief Analog to Digital Converter
ommpy 0:d383e2dee0f7 132 */
ommpy 0:d383e2dee0f7 133
ommpy 0:d383e2dee0f7 134 typedef struct
ommpy 0:d383e2dee0f7 135 {
ommpy 0:d383e2dee0f7 136 __IO uint32_t ISR; /*!< ADC Interrupt and Status register, Address offset:0x00 */
ommpy 0:d383e2dee0f7 137 __IO uint32_t IER; /*!< ADC Interrupt Enable register, Address offset:0x04 */
ommpy 0:d383e2dee0f7 138 __IO uint32_t CR; /*!< ADC Control register, Address offset:0x08 */
ommpy 0:d383e2dee0f7 139 __IO uint32_t CFGR1; /*!< ADC Configuration register 1, Address offset:0x0C */
ommpy 0:d383e2dee0f7 140 __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset:0x10 */
ommpy 0:d383e2dee0f7 141 __IO uint32_t SMPR; /*!< ADC Sampling time register, Address offset:0x14 */
ommpy 0:d383e2dee0f7 142 uint32_t RESERVED1; /*!< Reserved, 0x18 */
ommpy 0:d383e2dee0f7 143 uint32_t RESERVED2; /*!< Reserved, 0x1C */
ommpy 0:d383e2dee0f7 144 __IO uint32_t TR; /*!< ADC watchdog threshold register, Address offset:0x20 */
ommpy 0:d383e2dee0f7 145 uint32_t RESERVED3; /*!< Reserved, 0x24 */
ommpy 0:d383e2dee0f7 146 __IO uint32_t CHSELR; /*!< ADC channel selection register, Address offset:0x28 */
ommpy 0:d383e2dee0f7 147 uint32_t RESERVED4[5]; /*!< Reserved, 0x2C */
ommpy 0:d383e2dee0f7 148 __IO uint32_t DR; /*!< ADC data register, Address offset:0x40 */
ommpy 0:d383e2dee0f7 149 }ADC_TypeDef;
ommpy 0:d383e2dee0f7 150
ommpy 0:d383e2dee0f7 151 typedef struct
ommpy 0:d383e2dee0f7 152 {
ommpy 0:d383e2dee0f7 153 __IO uint32_t CCR;
ommpy 0:d383e2dee0f7 154 }ADC_Common_TypeDef;
ommpy 0:d383e2dee0f7 155
ommpy 0:d383e2dee0f7 156 /**
ommpy 0:d383e2dee0f7 157 * @brief CRC calculation unit
ommpy 0:d383e2dee0f7 158 */
ommpy 0:d383e2dee0f7 159
ommpy 0:d383e2dee0f7 160 typedef struct
ommpy 0:d383e2dee0f7 161 {
ommpy 0:d383e2dee0f7 162 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
ommpy 0:d383e2dee0f7 163 __IO uint8_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
ommpy 0:d383e2dee0f7 164 uint8_t RESERVED0; /*!< Reserved, 0x05 */
ommpy 0:d383e2dee0f7 165 uint16_t RESERVED1; /*!< Reserved, 0x06 */
ommpy 0:d383e2dee0f7 166 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
ommpy 0:d383e2dee0f7 167 uint32_t RESERVED2; /*!< Reserved, 0x0C */
ommpy 0:d383e2dee0f7 168 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
ommpy 0:d383e2dee0f7 169 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
ommpy 0:d383e2dee0f7 170 }CRC_TypeDef;
ommpy 0:d383e2dee0f7 171
ommpy 0:d383e2dee0f7 172 /**
ommpy 0:d383e2dee0f7 173 * @brief Debug MCU
ommpy 0:d383e2dee0f7 174 */
ommpy 0:d383e2dee0f7 175
ommpy 0:d383e2dee0f7 176 typedef struct
ommpy 0:d383e2dee0f7 177 {
ommpy 0:d383e2dee0f7 178 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
ommpy 0:d383e2dee0f7 179 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
ommpy 0:d383e2dee0f7 180 __IO uint32_t APB1FZ; /*!< Debug MCU APB1 freeze register, Address offset: 0x08 */
ommpy 0:d383e2dee0f7 181 __IO uint32_t APB2FZ; /*!< Debug MCU APB2 freeze register, Address offset: 0x0C */
ommpy 0:d383e2dee0f7 182 }DBGMCU_TypeDef;
ommpy 0:d383e2dee0f7 183
ommpy 0:d383e2dee0f7 184 /**
ommpy 0:d383e2dee0f7 185 * @brief DMA Controller
ommpy 0:d383e2dee0f7 186 */
ommpy 0:d383e2dee0f7 187
ommpy 0:d383e2dee0f7 188 typedef struct
ommpy 0:d383e2dee0f7 189 {
ommpy 0:d383e2dee0f7 190 __IO uint32_t CCR; /*!< DMA channel x configuration register */
ommpy 0:d383e2dee0f7 191 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
ommpy 0:d383e2dee0f7 192 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
ommpy 0:d383e2dee0f7 193 __IO uint32_t CMAR; /*!< DMA channel x memory address register */
ommpy 0:d383e2dee0f7 194 }DMA_Channel_TypeDef;
ommpy 0:d383e2dee0f7 195
ommpy 0:d383e2dee0f7 196 typedef struct
ommpy 0:d383e2dee0f7 197 {
ommpy 0:d383e2dee0f7 198 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
ommpy 0:d383e2dee0f7 199 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
ommpy 0:d383e2dee0f7 200 }DMA_TypeDef;
ommpy 0:d383e2dee0f7 201
ommpy 0:d383e2dee0f7 202 /**
ommpy 0:d383e2dee0f7 203 * @brief External Interrupt/Event Controller
ommpy 0:d383e2dee0f7 204 */
ommpy 0:d383e2dee0f7 205
ommpy 0:d383e2dee0f7 206 typedef struct
ommpy 0:d383e2dee0f7 207 {
ommpy 0:d383e2dee0f7 208 __IO uint32_t IMR; /*!<EXTI Interrupt mask register, Address offset: 0x00 */
ommpy 0:d383e2dee0f7 209 __IO uint32_t EMR; /*!<EXTI Event mask register, Address offset: 0x04 */
ommpy 0:d383e2dee0f7 210 __IO uint32_t RTSR; /*!<EXTI Rising trigger selection register , Address offset: 0x08 */
ommpy 0:d383e2dee0f7 211 __IO uint32_t FTSR; /*!<EXTI Falling trigger selection register, Address offset: 0x0C */
ommpy 0:d383e2dee0f7 212 __IO uint32_t SWIER; /*!<EXTI Software interrupt event register, Address offset: 0x10 */
ommpy 0:d383e2dee0f7 213 __IO uint32_t PR; /*!<EXTI Pending register, Address offset: 0x14 */
ommpy 0:d383e2dee0f7 214 }EXTI_TypeDef;
ommpy 0:d383e2dee0f7 215
ommpy 0:d383e2dee0f7 216 /**
ommpy 0:d383e2dee0f7 217 * @brief FLASH Registers
ommpy 0:d383e2dee0f7 218 */
ommpy 0:d383e2dee0f7 219 typedef struct
ommpy 0:d383e2dee0f7 220 {
ommpy 0:d383e2dee0f7 221 __IO uint32_t ACR; /*!<FLASH access control register, Address offset: 0x00 */
ommpy 0:d383e2dee0f7 222 __IO uint32_t KEYR; /*!<FLASH key register, Address offset: 0x04 */
ommpy 0:d383e2dee0f7 223 __IO uint32_t OPTKEYR; /*!<FLASH OPT key register, Address offset: 0x08 */
ommpy 0:d383e2dee0f7 224 __IO uint32_t SR; /*!<FLASH status register, Address offset: 0x0C */
ommpy 0:d383e2dee0f7 225 __IO uint32_t CR; /*!<FLASH control register, Address offset: 0x10 */
ommpy 0:d383e2dee0f7 226 __IO uint32_t AR; /*!<FLASH address register, Address offset: 0x14 */
ommpy 0:d383e2dee0f7 227 __IO uint32_t RESERVED; /*!< Reserved, 0x18 */
ommpy 0:d383e2dee0f7 228 __IO uint32_t OBR; /*!<FLASH option bytes register, Address offset: 0x1C */
ommpy 0:d383e2dee0f7 229 __IO uint32_t WRPR; /*!<FLASH option bytes register, Address offset: 0x20 */
ommpy 0:d383e2dee0f7 230 }FLASH_TypeDef;
ommpy 0:d383e2dee0f7 231
ommpy 0:d383e2dee0f7 232
ommpy 0:d383e2dee0f7 233 /**
ommpy 0:d383e2dee0f7 234 * @brief Option Bytes Registers
ommpy 0:d383e2dee0f7 235 */
ommpy 0:d383e2dee0f7 236 typedef struct
ommpy 0:d383e2dee0f7 237 {
ommpy 0:d383e2dee0f7 238 __IO uint16_t RDP; /*!< FLASH option byte Read protection, Address offset: 0x00 */
ommpy 0:d383e2dee0f7 239 __IO uint16_t USER; /*!< FLASH option byte user options, Address offset: 0x02 */
ommpy 0:d383e2dee0f7 240 __IO uint16_t DATA0; /*!< User data byte 0 (stored in FLASH_OBR[23:16]), Address offset: 0x04 */
ommpy 0:d383e2dee0f7 241 __IO uint16_t DATA1; /*!< User data byte 1 (stored in FLASH_OBR[31:24]), Address offset: 0x06 */
ommpy 0:d383e2dee0f7 242 __IO uint16_t WRP0; /*!< FLASH option byte write protection 0, Address offset: 0x08 */
ommpy 0:d383e2dee0f7 243 __IO uint16_t WRP1; /*!< FLASH option byte write protection 1, Address offset: 0x0A */
ommpy 0:d383e2dee0f7 244 }OB_TypeDef;
ommpy 0:d383e2dee0f7 245
ommpy 0:d383e2dee0f7 246 /**
ommpy 0:d383e2dee0f7 247 * @brief General Purpose I/O
ommpy 0:d383e2dee0f7 248 */
ommpy 0:d383e2dee0f7 249
ommpy 0:d383e2dee0f7 250 typedef struct
ommpy 0:d383e2dee0f7 251 {
ommpy 0:d383e2dee0f7 252 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
ommpy 0:d383e2dee0f7 253 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
ommpy 0:d383e2dee0f7 254 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
ommpy 0:d383e2dee0f7 255 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
ommpy 0:d383e2dee0f7 256 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
ommpy 0:d383e2dee0f7 257 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
ommpy 0:d383e2dee0f7 258 __IO uint32_t BSRR; /*!< GPIO port bit set/reset register, Address offset: 0x1A */
ommpy 0:d383e2dee0f7 259 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
ommpy 0:d383e2dee0f7 260 __IO uint32_t AFR[2]; /*!< GPIO alternate function low register, Address offset: 0x20-0x24 */
ommpy 0:d383e2dee0f7 261 __IO uint32_t BRR; /*!< GPIO bit reset register, Address offset: 0x28 */
ommpy 0:d383e2dee0f7 262 }GPIO_TypeDef;
ommpy 0:d383e2dee0f7 263
ommpy 0:d383e2dee0f7 264 /**
ommpy 0:d383e2dee0f7 265 * @brief SysTem Configuration
ommpy 0:d383e2dee0f7 266 */
ommpy 0:d383e2dee0f7 267
ommpy 0:d383e2dee0f7 268 typedef struct
ommpy 0:d383e2dee0f7 269 {
ommpy 0:d383e2dee0f7 270 __IO uint32_t CFGR1; /*!< SYSCFG configuration register 1, Address offset: 0x00 */
ommpy 0:d383e2dee0f7 271 uint32_t RESERVED; /*!< Reserved, 0x04 */
ommpy 0:d383e2dee0f7 272 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration register, Address offset: 0x14-0x08 */
ommpy 0:d383e2dee0f7 273 __IO uint32_t CFGR2; /*!< SYSCFG configuration register 2, Address offset: 0x18 */
ommpy 0:d383e2dee0f7 274 }SYSCFG_TypeDef;
ommpy 0:d383e2dee0f7 275
ommpy 0:d383e2dee0f7 276 /**
ommpy 0:d383e2dee0f7 277 * @brief Inter-integrated Circuit Interface
ommpy 0:d383e2dee0f7 278 */
ommpy 0:d383e2dee0f7 279
ommpy 0:d383e2dee0f7 280 typedef struct
ommpy 0:d383e2dee0f7 281 {
ommpy 0:d383e2dee0f7 282 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
ommpy 0:d383e2dee0f7 283 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
ommpy 0:d383e2dee0f7 284 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
ommpy 0:d383e2dee0f7 285 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
ommpy 0:d383e2dee0f7 286 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
ommpy 0:d383e2dee0f7 287 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
ommpy 0:d383e2dee0f7 288 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
ommpy 0:d383e2dee0f7 289 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
ommpy 0:d383e2dee0f7 290 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
ommpy 0:d383e2dee0f7 291 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
ommpy 0:d383e2dee0f7 292 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
ommpy 0:d383e2dee0f7 293 }I2C_TypeDef;
ommpy 0:d383e2dee0f7 294
ommpy 0:d383e2dee0f7 295 /**
ommpy 0:d383e2dee0f7 296 * @brief Independent WATCHDOG
ommpy 0:d383e2dee0f7 297 */
ommpy 0:d383e2dee0f7 298
ommpy 0:d383e2dee0f7 299 typedef struct
ommpy 0:d383e2dee0f7 300 {
ommpy 0:d383e2dee0f7 301 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
ommpy 0:d383e2dee0f7 302 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
ommpy 0:d383e2dee0f7 303 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
ommpy 0:d383e2dee0f7 304 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
ommpy 0:d383e2dee0f7 305 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
ommpy 0:d383e2dee0f7 306 }IWDG_TypeDef;
ommpy 0:d383e2dee0f7 307
ommpy 0:d383e2dee0f7 308 /**
ommpy 0:d383e2dee0f7 309 * @brief Power Control
ommpy 0:d383e2dee0f7 310 */
ommpy 0:d383e2dee0f7 311
ommpy 0:d383e2dee0f7 312 typedef struct
ommpy 0:d383e2dee0f7 313 {
ommpy 0:d383e2dee0f7 314 __IO uint32_t CR; /*!< PWR power control register, Address offset: 0x00 */
ommpy 0:d383e2dee0f7 315 __IO uint32_t CSR; /*!< PWR power control/status register, Address offset: 0x04 */
ommpy 0:d383e2dee0f7 316 }PWR_TypeDef;
ommpy 0:d383e2dee0f7 317
ommpy 0:d383e2dee0f7 318 /**
ommpy 0:d383e2dee0f7 319 * @brief Reset and Clock Control
ommpy 0:d383e2dee0f7 320 */
ommpy 0:d383e2dee0f7 321
ommpy 0:d383e2dee0f7 322 typedef struct
ommpy 0:d383e2dee0f7 323 {
ommpy 0:d383e2dee0f7 324 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
ommpy 0:d383e2dee0f7 325 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x04 */
ommpy 0:d383e2dee0f7 326 __IO uint32_t CIR; /*!< RCC clock interrupt register, Address offset: 0x08 */
ommpy 0:d383e2dee0f7 327 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x0C */
ommpy 0:d383e2dee0f7 328 __IO uint32_t APB1RSTR; /*!< RCC APB1 peripheral reset register, Address offset: 0x10 */
ommpy 0:d383e2dee0f7 329 __IO uint32_t AHBENR; /*!< RCC AHB peripheral clock register, Address offset: 0x14 */
ommpy 0:d383e2dee0f7 330 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock enable register, Address offset: 0x18 */
ommpy 0:d383e2dee0f7 331 __IO uint32_t APB1ENR; /*!< RCC APB1 peripheral clock enable register, Address offset: 0x1C */
ommpy 0:d383e2dee0f7 332 __IO uint32_t BDCR; /*!< RCC Backup domain control register, Address offset: 0x20 */
ommpy 0:d383e2dee0f7 333 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x24 */
ommpy 0:d383e2dee0f7 334 __IO uint32_t AHBRSTR; /*!< RCC AHB peripheral reset register, Address offset: 0x28 */
ommpy 0:d383e2dee0f7 335 __IO uint32_t CFGR2; /*!< RCC clock configuration register 2, Address offset: 0x2C */
ommpy 0:d383e2dee0f7 336 __IO uint32_t CFGR3; /*!< RCC clock configuration register 3, Address offset: 0x30 */
ommpy 0:d383e2dee0f7 337 __IO uint32_t CR2; /*!< RCC clock control register 2, Address offset: 0x34 */
ommpy 0:d383e2dee0f7 338 }RCC_TypeDef;
ommpy 0:d383e2dee0f7 339
ommpy 0:d383e2dee0f7 340 /**
ommpy 0:d383e2dee0f7 341 * @brief Real-Time Clock
ommpy 0:d383e2dee0f7 342 */
ommpy 0:d383e2dee0f7 343 typedef struct
ommpy 0:d383e2dee0f7 344 {
ommpy 0:d383e2dee0f7 345 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
ommpy 0:d383e2dee0f7 346 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
ommpy 0:d383e2dee0f7 347 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
ommpy 0:d383e2dee0f7 348 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
ommpy 0:d383e2dee0f7 349 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
ommpy 0:d383e2dee0f7 350 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
ommpy 0:d383e2dee0f7 351 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x18 */
ommpy 0:d383e2dee0f7 352 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
ommpy 0:d383e2dee0f7 353 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x20 */
ommpy 0:d383e2dee0f7 354 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
ommpy 0:d383e2dee0f7 355 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
ommpy 0:d383e2dee0f7 356 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
ommpy 0:d383e2dee0f7 357 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
ommpy 0:d383e2dee0f7 358 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
ommpy 0:d383e2dee0f7 359 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
ommpy 0:d383e2dee0f7 360 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
ommpy 0:d383e2dee0f7 361 __IO uint32_t TAFCR; /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
ommpy 0:d383e2dee0f7 362 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
ommpy 0:d383e2dee0f7 363 }RTC_TypeDef;
ommpy 0:d383e2dee0f7 364
ommpy 0:d383e2dee0f7 365 /**
ommpy 0:d383e2dee0f7 366 * @brief Serial Peripheral Interface
ommpy 0:d383e2dee0f7 367 */
ommpy 0:d383e2dee0f7 368
ommpy 0:d383e2dee0f7 369 typedef struct
ommpy 0:d383e2dee0f7 370 {
ommpy 0:d383e2dee0f7 371 __IO uint32_t CR1; /*!< SPI Control register 1 (not used in I2S mode), Address offset: 0x00 */
ommpy 0:d383e2dee0f7 372 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
ommpy 0:d383e2dee0f7 373 __IO uint32_t SR; /*!< SPI Status register, Address offset: 0x08 */
ommpy 0:d383e2dee0f7 374 __IO uint32_t DR; /*!< SPI data register, Address offset: 0x0C */
ommpy 0:d383e2dee0f7 375 __IO uint32_t CRCPR; /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
ommpy 0:d383e2dee0f7 376 __IO uint32_t RXCRCR; /*!< SPI Rx CRC register (not used in I2S mode), Address offset: 0x14 */
ommpy 0:d383e2dee0f7 377 __IO uint32_t TXCRCR; /*!< SPI Tx CRC register (not used in I2S mode), Address offset: 0x18 */
ommpy 0:d383e2dee0f7 378 __IO uint32_t I2SCFGR; /*!< SPI_I2S configuration register, Address offset: 0x1C */
ommpy 0:d383e2dee0f7 379 __IO uint32_t I2SPR; /*!< SPI_I2S prescaler register, Address offset: 0x20 */
ommpy 0:d383e2dee0f7 380 }SPI_TypeDef;
ommpy 0:d383e2dee0f7 381
ommpy 0:d383e2dee0f7 382 /**
ommpy 0:d383e2dee0f7 383 * @brief TIM
ommpy 0:d383e2dee0f7 384 */
ommpy 0:d383e2dee0f7 385 typedef struct
ommpy 0:d383e2dee0f7 386 {
ommpy 0:d383e2dee0f7 387 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
ommpy 0:d383e2dee0f7 388 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
ommpy 0:d383e2dee0f7 389 __IO uint32_t SMCR; /*!< TIM slave Mode Control register, Address offset: 0x08 */
ommpy 0:d383e2dee0f7 390 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
ommpy 0:d383e2dee0f7 391 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
ommpy 0:d383e2dee0f7 392 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
ommpy 0:d383e2dee0f7 393 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
ommpy 0:d383e2dee0f7 394 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
ommpy 0:d383e2dee0f7 395 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
ommpy 0:d383e2dee0f7 396 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
ommpy 0:d383e2dee0f7 397 __IO uint32_t PSC; /*!< TIM prescaler register, Address offset: 0x28 */
ommpy 0:d383e2dee0f7 398 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
ommpy 0:d383e2dee0f7 399 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
ommpy 0:d383e2dee0f7 400 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
ommpy 0:d383e2dee0f7 401 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
ommpy 0:d383e2dee0f7 402 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
ommpy 0:d383e2dee0f7 403 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
ommpy 0:d383e2dee0f7 404 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
ommpy 0:d383e2dee0f7 405 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
ommpy 0:d383e2dee0f7 406 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer register, Address offset: 0x4C */
ommpy 0:d383e2dee0f7 407 __IO uint32_t OR; /*!< TIM option register, Address offset: 0x50 */
ommpy 0:d383e2dee0f7 408 }TIM_TypeDef;
ommpy 0:d383e2dee0f7 409
ommpy 0:d383e2dee0f7 410 /**
ommpy 0:d383e2dee0f7 411 * @brief Universal Synchronous Asynchronous Receiver Transmitter
ommpy 0:d383e2dee0f7 412 */
ommpy 0:d383e2dee0f7 413
ommpy 0:d383e2dee0f7 414 typedef struct
ommpy 0:d383e2dee0f7 415 {
ommpy 0:d383e2dee0f7 416 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
ommpy 0:d383e2dee0f7 417 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
ommpy 0:d383e2dee0f7 418 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
ommpy 0:d383e2dee0f7 419 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
ommpy 0:d383e2dee0f7 420 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
ommpy 0:d383e2dee0f7 421 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
ommpy 0:d383e2dee0f7 422 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
ommpy 0:d383e2dee0f7 423 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
ommpy 0:d383e2dee0f7 424 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
ommpy 0:d383e2dee0f7 425 __IO uint16_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
ommpy 0:d383e2dee0f7 426 uint16_t RESERVED1; /*!< Reserved, 0x26 */
ommpy 0:d383e2dee0f7 427 __IO uint16_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
ommpy 0:d383e2dee0f7 428 uint16_t RESERVED2; /*!< Reserved, 0x2A */
ommpy 0:d383e2dee0f7 429 }USART_TypeDef;
ommpy 0:d383e2dee0f7 430
ommpy 0:d383e2dee0f7 431 /**
ommpy 0:d383e2dee0f7 432 * @brief Window WATCHDOG
ommpy 0:d383e2dee0f7 433 */
ommpy 0:d383e2dee0f7 434 typedef struct
ommpy 0:d383e2dee0f7 435 {
ommpy 0:d383e2dee0f7 436 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
ommpy 0:d383e2dee0f7 437 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
ommpy 0:d383e2dee0f7 438 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
ommpy 0:d383e2dee0f7 439 }WWDG_TypeDef;
ommpy 0:d383e2dee0f7 440
ommpy 0:d383e2dee0f7 441 /**
ommpy 0:d383e2dee0f7 442 * @}
ommpy 0:d383e2dee0f7 443 */
ommpy 0:d383e2dee0f7 444
ommpy 0:d383e2dee0f7 445 /** @addtogroup Peripheral_memory_map
ommpy 0:d383e2dee0f7 446 * @{
ommpy 0:d383e2dee0f7 447 */
ommpy 0:d383e2dee0f7 448
ommpy 0:d383e2dee0f7 449 #define FLASH_BASE ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
ommpy 0:d383e2dee0f7 450 #define FLASH_BANK1_END ((uint32_t)0x0800FFFF) /*!< FLASH END address of bank1 */
ommpy 0:d383e2dee0f7 451 #define SRAM_BASE ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
ommpy 0:d383e2dee0f7 452 #define PERIPH_BASE ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
ommpy 0:d383e2dee0f7 453
ommpy 0:d383e2dee0f7 454 /*!< Peripheral memory map */
ommpy 0:d383e2dee0f7 455 #define APBPERIPH_BASE PERIPH_BASE
ommpy 0:d383e2dee0f7 456 #define AHBPERIPH_BASE (PERIPH_BASE + 0x00020000)
ommpy 0:d383e2dee0f7 457 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000)
ommpy 0:d383e2dee0f7 458
ommpy 0:d383e2dee0f7 459 #define TIM3_BASE (APBPERIPH_BASE + 0x00000400)
ommpy 0:d383e2dee0f7 460 #define TIM6_BASE (APBPERIPH_BASE + 0x00001000)
ommpy 0:d383e2dee0f7 461 #define TIM14_BASE (APBPERIPH_BASE + 0x00002000)
ommpy 0:d383e2dee0f7 462 #define RTC_BASE (APBPERIPH_BASE + 0x00002800)
ommpy 0:d383e2dee0f7 463 #define WWDG_BASE (APBPERIPH_BASE + 0x00002C00)
ommpy 0:d383e2dee0f7 464 #define IWDG_BASE (APBPERIPH_BASE + 0x00003000)
ommpy 0:d383e2dee0f7 465 #define SPI2_BASE (APBPERIPH_BASE + 0x00003800)
ommpy 0:d383e2dee0f7 466 #define USART2_BASE (APBPERIPH_BASE + 0x00004400)
ommpy 0:d383e2dee0f7 467 #define I2C1_BASE (APBPERIPH_BASE + 0x00005400)
ommpy 0:d383e2dee0f7 468 #define I2C2_BASE (APBPERIPH_BASE + 0x00005800)
ommpy 0:d383e2dee0f7 469 #define PWR_BASE (APBPERIPH_BASE + 0x00007000)
ommpy 0:d383e2dee0f7 470 #define SYSCFG_BASE (APBPERIPH_BASE + 0x00010000)
ommpy 0:d383e2dee0f7 471 #define EXTI_BASE (APBPERIPH_BASE + 0x00010400)
ommpy 0:d383e2dee0f7 472 #define ADC1_BASE (APBPERIPH_BASE + 0x00012400)
ommpy 0:d383e2dee0f7 473 #define ADC_BASE (APBPERIPH_BASE + 0x00012708)
ommpy 0:d383e2dee0f7 474 #define TIM1_BASE (APBPERIPH_BASE + 0x00012C00)
ommpy 0:d383e2dee0f7 475 #define SPI1_BASE (APBPERIPH_BASE + 0x00013000)
ommpy 0:d383e2dee0f7 476 #define USART1_BASE (APBPERIPH_BASE + 0x00013800)
ommpy 0:d383e2dee0f7 477 #define TIM15_BASE (APBPERIPH_BASE + 0x00014000)
ommpy 0:d383e2dee0f7 478 #define TIM16_BASE (APBPERIPH_BASE + 0x00014400)
ommpy 0:d383e2dee0f7 479 #define TIM17_BASE (APBPERIPH_BASE + 0x00014800)
ommpy 0:d383e2dee0f7 480 #define DBGMCU_BASE (APBPERIPH_BASE + 0x00015800)
ommpy 0:d383e2dee0f7 481
ommpy 0:d383e2dee0f7 482 #define DMA1_BASE (AHBPERIPH_BASE + 0x00000000)
ommpy 0:d383e2dee0f7 483 #define DMA1_Channel1_BASE (DMA1_BASE + 0x00000008)
ommpy 0:d383e2dee0f7 484 #define DMA1_Channel2_BASE (DMA1_BASE + 0x0000001C)
ommpy 0:d383e2dee0f7 485 #define DMA1_Channel3_BASE (DMA1_BASE + 0x00000030)
ommpy 0:d383e2dee0f7 486 #define DMA1_Channel4_BASE (DMA1_BASE + 0x00000044)
ommpy 0:d383e2dee0f7 487 #define DMA1_Channel5_BASE (DMA1_BASE + 0x00000058)
ommpy 0:d383e2dee0f7 488
ommpy 0:d383e2dee0f7 489 #define RCC_BASE (AHBPERIPH_BASE + 0x00001000)
ommpy 0:d383e2dee0f7 490 #define FLASH_R_BASE (AHBPERIPH_BASE + 0x00002000) /*!< FLASH registers base address */
ommpy 0:d383e2dee0f7 491 #define OB_BASE ((uint32_t)0x1FFFF800) /*!< FLASH Option Bytes base address */
ommpy 0:d383e2dee0f7 492 #define CRC_BASE (AHBPERIPH_BASE + 0x00003000)
ommpy 0:d383e2dee0f7 493
ommpy 0:d383e2dee0f7 494 #define GPIOA_BASE (AHB2PERIPH_BASE + 0x00000000)
ommpy 0:d383e2dee0f7 495 #define GPIOB_BASE (AHB2PERIPH_BASE + 0x00000400)
ommpy 0:d383e2dee0f7 496 #define GPIOC_BASE (AHB2PERIPH_BASE + 0x00000800)
ommpy 0:d383e2dee0f7 497 #define GPIOD_BASE (AHB2PERIPH_BASE + 0x00000C00)
ommpy 0:d383e2dee0f7 498 #define GPIOF_BASE (AHB2PERIPH_BASE + 0x00001400)
ommpy 0:d383e2dee0f7 499
ommpy 0:d383e2dee0f7 500 /**
ommpy 0:d383e2dee0f7 501 * @}
ommpy 0:d383e2dee0f7 502 */
ommpy 0:d383e2dee0f7 503
ommpy 0:d383e2dee0f7 504 /** @addtogroup Peripheral_declaration
ommpy 0:d383e2dee0f7 505 * @{
ommpy 0:d383e2dee0f7 506 */
ommpy 0:d383e2dee0f7 507
ommpy 0:d383e2dee0f7 508 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
ommpy 0:d383e2dee0f7 509 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
ommpy 0:d383e2dee0f7 510 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
ommpy 0:d383e2dee0f7 511 #define RTC ((RTC_TypeDef *) RTC_BASE)
ommpy 0:d383e2dee0f7 512 #define WWDG ((WWDG_TypeDef *) WWDG_BASE)
ommpy 0:d383e2dee0f7 513 #define IWDG ((IWDG_TypeDef *) IWDG_BASE)
ommpy 0:d383e2dee0f7 514 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
ommpy 0:d383e2dee0f7 515 #define USART2 ((USART_TypeDef *) USART2_BASE)
ommpy 0:d383e2dee0f7 516 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
ommpy 0:d383e2dee0f7 517 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
ommpy 0:d383e2dee0f7 518 #define PWR ((PWR_TypeDef *) PWR_BASE)
ommpy 0:d383e2dee0f7 519 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
ommpy 0:d383e2dee0f7 520 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
ommpy 0:d383e2dee0f7 521 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
ommpy 0:d383e2dee0f7 522 #define ADC ((ADC_Common_TypeDef *) ADC_BASE)
ommpy 0:d383e2dee0f7 523 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
ommpy 0:d383e2dee0f7 524 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
ommpy 0:d383e2dee0f7 525 #define USART1 ((USART_TypeDef *) USART1_BASE)
ommpy 0:d383e2dee0f7 526 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
ommpy 0:d383e2dee0f7 527 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
ommpy 0:d383e2dee0f7 528 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
ommpy 0:d383e2dee0f7 529 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
ommpy 0:d383e2dee0f7 530 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
ommpy 0:d383e2dee0f7 531 #define DMA1_Channel1 ((DMA_Channel_TypeDef *) DMA1_Channel1_BASE)
ommpy 0:d383e2dee0f7 532 #define DMA1_Channel2 ((DMA_Channel_TypeDef *) DMA1_Channel2_BASE)
ommpy 0:d383e2dee0f7 533 #define DMA1_Channel3 ((DMA_Channel_TypeDef *) DMA1_Channel3_BASE)
ommpy 0:d383e2dee0f7 534 #define DMA1_Channel4 ((DMA_Channel_TypeDef *) DMA1_Channel4_BASE)
ommpy 0:d383e2dee0f7 535 #define DMA1_Channel5 ((DMA_Channel_TypeDef *) DMA1_Channel5_BASE)
ommpy 0:d383e2dee0f7 536 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
ommpy 0:d383e2dee0f7 537 #define OB ((OB_TypeDef *) OB_BASE)
ommpy 0:d383e2dee0f7 538 #define RCC ((RCC_TypeDef *) RCC_BASE)
ommpy 0:d383e2dee0f7 539 #define CRC ((CRC_TypeDef *) CRC_BASE)
ommpy 0:d383e2dee0f7 540 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
ommpy 0:d383e2dee0f7 541 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
ommpy 0:d383e2dee0f7 542 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
ommpy 0:d383e2dee0f7 543 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
ommpy 0:d383e2dee0f7 544 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
ommpy 0:d383e2dee0f7 545 /**
ommpy 0:d383e2dee0f7 546 * @}
ommpy 0:d383e2dee0f7 547 */
ommpy 0:d383e2dee0f7 548
ommpy 0:d383e2dee0f7 549 /** @addtogroup Exported_constants
ommpy 0:d383e2dee0f7 550 * @{
ommpy 0:d383e2dee0f7 551 */
ommpy 0:d383e2dee0f7 552
ommpy 0:d383e2dee0f7 553 /** @addtogroup Peripheral_Registers_Bits_Definition
ommpy 0:d383e2dee0f7 554 * @{
ommpy 0:d383e2dee0f7 555 */
ommpy 0:d383e2dee0f7 556
ommpy 0:d383e2dee0f7 557 /******************************************************************************/
ommpy 0:d383e2dee0f7 558 /* Peripheral Registers Bits Definition */
ommpy 0:d383e2dee0f7 559 /******************************************************************************/
ommpy 0:d383e2dee0f7 560 /******************************************************************************/
ommpy 0:d383e2dee0f7 561 /* */
ommpy 0:d383e2dee0f7 562 /* Analog to Digital Converter (ADC) */
ommpy 0:d383e2dee0f7 563 /* */
ommpy 0:d383e2dee0f7 564 /******************************************************************************/
ommpy 0:d383e2dee0f7 565 /******************** Bits definition for ADC_ISR register ******************/
ommpy 0:d383e2dee0f7 566 #define ADC_ISR_AWD ((uint32_t)0x00000080) /*!< Analog watchdog flag */
ommpy 0:d383e2dee0f7 567 #define ADC_ISR_OVR ((uint32_t)0x00000010) /*!< Overrun flag */
ommpy 0:d383e2dee0f7 568 #define ADC_ISR_EOSEQ ((uint32_t)0x00000008) /*!< End of Sequence flag */
ommpy 0:d383e2dee0f7 569 #define ADC_ISR_EOC ((uint32_t)0x00000004) /*!< End of Conversion */
ommpy 0:d383e2dee0f7 570 #define ADC_ISR_EOSMP ((uint32_t)0x00000002) /*!< End of sampling flag */
ommpy 0:d383e2dee0f7 571 #define ADC_ISR_ADRDY ((uint32_t)0x00000001) /*!< ADC Ready */
ommpy 0:d383e2dee0f7 572
ommpy 0:d383e2dee0f7 573 /* Old EOSEQ bit definition, maintained for legacy purpose */
ommpy 0:d383e2dee0f7 574 #define ADC_ISR_EOS ADC_ISR_EOSEQ
ommpy 0:d383e2dee0f7 575
ommpy 0:d383e2dee0f7 576 /******************** Bits definition for ADC_IER register ******************/
ommpy 0:d383e2dee0f7 577 #define ADC_IER_AWDIE ((uint32_t)0x00000080) /*!< Analog Watchdog interrupt enable */
ommpy 0:d383e2dee0f7 578 #define ADC_IER_OVRIE ((uint32_t)0x00000010) /*!< Overrun interrupt enable */
ommpy 0:d383e2dee0f7 579 #define ADC_IER_EOSEQIE ((uint32_t)0x00000008) /*!< End of Sequence of conversion interrupt enable */
ommpy 0:d383e2dee0f7 580 #define ADC_IER_EOCIE ((uint32_t)0x00000004) /*!< End of Conversion interrupt enable */
ommpy 0:d383e2dee0f7 581 #define ADC_IER_EOSMPIE ((uint32_t)0x00000002) /*!< End of sampling interrupt enable */
ommpy 0:d383e2dee0f7 582 #define ADC_IER_ADRDYIE ((uint32_t)0x00000001) /*!< ADC Ready interrupt enable */
ommpy 0:d383e2dee0f7 583
ommpy 0:d383e2dee0f7 584 /* Old EOSEQIE bit definition, maintained for legacy purpose */
ommpy 0:d383e2dee0f7 585 #define ADC_IER_EOSIE ADC_IER_EOSEQIE
ommpy 0:d383e2dee0f7 586
ommpy 0:d383e2dee0f7 587 /******************** Bits definition for ADC_CR register *******************/
ommpy 0:d383e2dee0f7 588 #define ADC_CR_ADCAL ((uint32_t)0x80000000) /*!< ADC calibration */
ommpy 0:d383e2dee0f7 589 #define ADC_CR_ADSTP ((uint32_t)0x00000010) /*!< ADC stop of conversion command */
ommpy 0:d383e2dee0f7 590 #define ADC_CR_ADSTART ((uint32_t)0x00000004) /*!< ADC start of conversion */
ommpy 0:d383e2dee0f7 591 #define ADC_CR_ADDIS ((uint32_t)0x00000002) /*!< ADC disable command */
ommpy 0:d383e2dee0f7 592 #define ADC_CR_ADEN ((uint32_t)0x00000001) /*!< ADC enable control */
ommpy 0:d383e2dee0f7 593
ommpy 0:d383e2dee0f7 594 /******************* Bits definition for ADC_CFGR1 register *****************/
ommpy 0:d383e2dee0f7 595 #define ADC_CFGR1_AWDCH ((uint32_t)0x7C000000) /*!< AWDCH[4:0] bits (Analog watchdog channel select bits) */
ommpy 0:d383e2dee0f7 596 #define ADC_CFGR1_AWDCH_0 ((uint32_t)0x04000000) /*!< Bit 0 */
ommpy 0:d383e2dee0f7 597 #define ADC_CFGR1_AWDCH_1 ((uint32_t)0x08000000) /*!< Bit 1 */
ommpy 0:d383e2dee0f7 598 #define ADC_CFGR1_AWDCH_2 ((uint32_t)0x10000000) /*!< Bit 2 */
ommpy 0:d383e2dee0f7 599 #define ADC_CFGR1_AWDCH_3 ((uint32_t)0x20000000) /*!< Bit 3 */
ommpy 0:d383e2dee0f7 600 #define ADC_CFGR1_AWDCH_4 ((uint32_t)0x40000000) /*!< Bit 4 */
ommpy 0:d383e2dee0f7 601 #define ADC_CFGR1_AWDEN ((uint32_t)0x00800000) /*!< Analog watchdog enable on regular channels */
ommpy 0:d383e2dee0f7 602 #define ADC_CFGR1_AWDSGL ((uint32_t)0x00400000) /*!< Enable the watchdog on a single channel or on all channels */
ommpy 0:d383e2dee0f7 603 #define ADC_CFGR1_DISCEN ((uint32_t)0x00010000) /*!< Discontinuous mode on regular channels */
ommpy 0:d383e2dee0f7 604 #define ADC_CFGR1_AUTOFF ((uint32_t)0x00008000) /*!< ADC auto power off */
ommpy 0:d383e2dee0f7 605 #define ADC_CFGR1_WAIT ((uint32_t)0x00004000) /*!< ADC wait conversion mode */
ommpy 0:d383e2dee0f7 606 #define ADC_CFGR1_CONT ((uint32_t)0x00002000) /*!< Continuous Conversion */
ommpy 0:d383e2dee0f7 607 #define ADC_CFGR1_OVRMOD ((uint32_t)0x00001000) /*!< Overrun mode */
ommpy 0:d383e2dee0f7 608 #define ADC_CFGR1_EXTEN ((uint32_t)0x00000C00) /*!< EXTEN[1:0] bits (External Trigger Conversion mode for regular channels) */
ommpy 0:d383e2dee0f7 609 #define ADC_CFGR1_EXTEN_0 ((uint32_t)0x00000400) /*!< Bit 0 */
ommpy 0:d383e2dee0f7 610 #define ADC_CFGR1_EXTEN_1 ((uint32_t)0x00000800) /*!< Bit 1 */
ommpy 0:d383e2dee0f7 611 #define ADC_CFGR1_EXTSEL ((uint32_t)0x000001C0) /*!< EXTSEL[2:0] bits (External Event Select for regular group) */
ommpy 0:d383e2dee0f7 612 #define ADC_CFGR1_EXTSEL_0 ((uint32_t)0x00000040) /*!< Bit 0 */
ommpy 0:d383e2dee0f7 613 #define ADC_CFGR1_EXTSEL_1 ((uint32_t)0x00000080) /*!< Bit 1 */
ommpy 0:d383e2dee0f7 614 #define ADC_CFGR1_EXTSEL_2 ((uint32_t)0x00000100) /*!< Bit 2 */
ommpy 0:d383e2dee0f7 615 #define ADC_CFGR1_ALIGN ((uint32_t)0x00000020) /*!< Data Alignment */
ommpy 0:d383e2dee0f7 616 #define ADC_CFGR1_RES ((uint32_t)0x00000018) /*!< RES[1:0] bits (Resolution) */
ommpy 0:d383e2dee0f7 617 #define ADC_CFGR1_RES_0 ((uint32_t)0x00000008) /*!< Bit 0 */
ommpy 0:d383e2dee0f7 618 #define ADC_CFGR1_RES_1 ((uint32_t)0x00000010) /*!< Bit 1 */
ommpy 0:d383e2dee0f7 619 #define ADC_CFGR1_SCANDIR ((uint32_t)0x00000004) /*!< Sequence scan direction */
ommpy 0:d383e2dee0f7 620 #define ADC_CFGR1_DMACFG ((uint32_t)0x00000002) /*!< Direct memory access configuration */
ommpy 0:d383e2dee0f7 621 #define ADC_CFGR1_DMAEN ((uint32_t)0x00000001) /*!< Direct memory access enable */
ommpy 0:d383e2dee0f7 622
ommpy 0:d383e2dee0f7 623 /* Old WAIT bit definition, maintained for legacy purpose */
ommpy 0:d383e2dee0f7 624 #define ADC_CFGR1_AUTDLY ADC_CFGR1_WAIT
ommpy 0:d383e2dee0f7 625
ommpy 0:d383e2dee0f7 626 /******************* Bits definition for ADC_CFGR2 register *****************/
ommpy 0:d383e2dee0f7 627 #define ADC_CFGR2_CKMODE ((uint32_t)0xC0000000) /*!< ADC clock mode */
ommpy 0:d383e2dee0f7 628 #define ADC_CFGR2_CKMODE_1 ((uint32_t)0x80000000) /*!< ADC clocked by PCLK div4 */
ommpy 0:d383e2dee0f7 629 #define ADC_CFGR2_CKMODE_0 ((uint32_t)0x40000000) /*!< ADC clocked by PCLK div2 */
ommpy 0:d383e2dee0f7 630
ommpy 0:d383e2dee0f7 631 /* Old bit definition, maintained for legacy purpose */
ommpy 0:d383e2dee0f7 632 #define ADC_CFGR2_JITOFFDIV4 ADC_CFGR2_CKMODE_1 /*!< ADC clocked by PCLK div4 */
ommpy 0:d383e2dee0f7 633 #define ADC_CFGR2_JITOFFDIV2 ADC_CFGR2_CKMODE_0 /*!< ADC clocked by PCLK div2 */
ommpy 0:d383e2dee0f7 634
ommpy 0:d383e2dee0f7 635 /****************** Bit definition for ADC_SMPR register ********************/
ommpy 0:d383e2dee0f7 636 #define ADC_SMPR_SMP ((uint32_t)0x00000007) /*!< SMP[2:0] bits (Sampling time selection) */
ommpy 0:d383e2dee0f7 637 #define ADC_SMPR_SMP_0 ((uint32_t)0x00000001) /*!< Bit 0 */
ommpy 0:d383e2dee0f7 638 #define ADC_SMPR_SMP_1 ((uint32_t)0x00000002) /*!< Bit 1 */
ommpy 0:d383e2dee0f7 639 #define ADC_SMPR_SMP_2 ((uint32_t)0x00000004) /*!< Bit 2 */
ommpy 0:d383e2dee0f7 640
ommpy 0:d383e2dee0f7 641 /* Old bit definition, maintained for legacy purpose */
ommpy 0:d383e2dee0f7 642 #define ADC_SMPR1_SMPR ADC_SMPR_SMP /*!< SMP[2:0] bits (Sampling time selection) */
ommpy 0:d383e2dee0f7 643 #define ADC_SMPR1_SMPR_0 ADC_SMPR_SMP_0 /*!< Bit 0 */
ommpy 0:d383e2dee0f7 644 #define ADC_SMPR1_SMPR_1 ADC_SMPR_SMP_1 /*!< Bit 1 */
ommpy 0:d383e2dee0f7 645 #define ADC_SMPR1_SMPR_2 ADC_SMPR_SMP_2 /*!< Bit 2 */
ommpy 0:d383e2dee0f7 646
ommpy 0:d383e2dee0f7 647 /******************* Bit definition for ADC_TR register ********************/
ommpy 0:d383e2dee0f7 648 #define ADC_TR_HT ((uint32_t)0x0FFF0000) /*!< Analog watchdog high threshold */
ommpy 0:d383e2dee0f7 649 #define ADC_TR_LT ((uint32_t)0x00000FFF) /*!< Analog watchdog low threshold */
ommpy 0:d383e2dee0f7 650
ommpy 0:d383e2dee0f7 651 /* Old bit definition, maintained for legacy purpose */
ommpy 0:d383e2dee0f7 652 #define ADC_HTR_HT ADC_TR_HT /*!< Analog watchdog high threshold */
ommpy 0:d383e2dee0f7 653 #define ADC_LTR_LT ADC_TR_LT /*!< Analog watchdog low threshold */
ommpy 0:d383e2dee0f7 654
ommpy 0:d383e2dee0f7 655 /****************** Bit definition for ADC_CHSELR register ******************/
ommpy 0:d383e2dee0f7 656 #define ADC_CHSELR_CHSEL18 ((uint32_t)0x00040000) /*!< Channel 18 selection */
ommpy 0:d383e2dee0f7 657 #define ADC_CHSELR_CHSEL17 ((uint32_t)0x00020000) /*!< Channel 17 selection */
ommpy 0:d383e2dee0f7 658 #define ADC_CHSELR_CHSEL16 ((uint32_t)0x00010000) /*!< Channel 16 selection */
ommpy 0:d383e2dee0f7 659 #define ADC_CHSELR_CHSEL15 ((uint32_t)0x00008000) /*!< Channel 15 selection */
ommpy 0:d383e2dee0f7 660 #define ADC_CHSELR_CHSEL14 ((uint32_t)0x00004000) /*!< Channel 14 selection */
ommpy 0:d383e2dee0f7 661 #define ADC_CHSELR_CHSEL13 ((uint32_t)0x00002000) /*!< Channel 13 selection */
ommpy 0:d383e2dee0f7 662 #define ADC_CHSELR_CHSEL12 ((uint32_t)0x00001000) /*!< Channel 12 selection */
ommpy 0:d383e2dee0f7 663 #define ADC_CHSELR_CHSEL11 ((uint32_t)0x00000800) /*!< Channel 11 selection */
ommpy 0:d383e2dee0f7 664 #define ADC_CHSELR_CHSEL10 ((uint32_t)0x00000400) /*!< Channel 10 selection */
ommpy 0:d383e2dee0f7 665 #define ADC_CHSELR_CHSEL9 ((uint32_t)0x00000200) /*!< Channel 9 selection */
ommpy 0:d383e2dee0f7 666 #define ADC_CHSELR_CHSEL8 ((uint32_t)0x00000100) /*!< Channel 8 selection */
ommpy 0:d383e2dee0f7 667 #define ADC_CHSELR_CHSEL7 ((uint32_t)0x00000080) /*!< Channel 7 selection */
ommpy 0:d383e2dee0f7 668 #define ADC_CHSELR_CHSEL6 ((uint32_t)0x00000040) /*!< Channel 6 selection */
ommpy 0:d383e2dee0f7 669 #define ADC_CHSELR_CHSEL5 ((uint32_t)0x00000020) /*!< Channel 5 selection */
ommpy 0:d383e2dee0f7 670 #define ADC_CHSELR_CHSEL4 ((uint32_t)0x00000010) /*!< Channel 4 selection */
ommpy 0:d383e2dee0f7 671 #define ADC_CHSELR_CHSEL3 ((uint32_t)0x00000008) /*!< Channel 3 selection */
ommpy 0:d383e2dee0f7 672 #define ADC_CHSELR_CHSEL2 ((uint32_t)0x00000004) /*!< Channel 2 selection */
ommpy 0:d383e2dee0f7 673 #define ADC_CHSELR_CHSEL1 ((uint32_t)0x00000002) /*!< Channel 1 selection */
ommpy 0:d383e2dee0f7 674 #define ADC_CHSELR_CHSEL0 ((uint32_t)0x00000001) /*!< Channel 0 selection */
ommpy 0:d383e2dee0f7 675
ommpy 0:d383e2dee0f7 676 /******************** Bit definition for ADC_DR register ********************/
ommpy 0:d383e2dee0f7 677 #define ADC_DR_DATA ((uint32_t)0x0000FFFF) /*!< Regular data */
ommpy 0:d383e2dee0f7 678
ommpy 0:d383e2dee0f7 679 /******************* Bit definition for ADC_CCR register ********************/
ommpy 0:d383e2dee0f7 680 #define ADC_CCR_TSEN ((uint32_t)0x00800000) /*!< Tempurature sensore enable */
ommpy 0:d383e2dee0f7 681 #define ADC_CCR_VREFEN ((uint32_t)0x00400000) /*!< Vrefint enable */
ommpy 0:d383e2dee0f7 682
ommpy 0:d383e2dee0f7 683 /******************************************************************************/
ommpy 0:d383e2dee0f7 684 /* */
ommpy 0:d383e2dee0f7 685 /* CRC calculation unit (CRC) */
ommpy 0:d383e2dee0f7 686 /* */
ommpy 0:d383e2dee0f7 687 /******************************************************************************/
ommpy 0:d383e2dee0f7 688 /******************* Bit definition for CRC_DR register *********************/
ommpy 0:d383e2dee0f7 689 #define CRC_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data register bits */
ommpy 0:d383e2dee0f7 690
ommpy 0:d383e2dee0f7 691 /******************* Bit definition for CRC_IDR register ********************/
ommpy 0:d383e2dee0f7 692 #define CRC_IDR_IDR ((uint8_t)0xFF) /*!< General-purpose 8-bit data register bits */
ommpy 0:d383e2dee0f7 693
ommpy 0:d383e2dee0f7 694 /******************** Bit definition for CRC_CR register ********************/
ommpy 0:d383e2dee0f7 695 #define CRC_CR_RESET ((uint32_t)0x00000001) /*!< RESET the CRC computation unit bit */
ommpy 0:d383e2dee0f7 696 #define CRC_CR_REV_IN ((uint32_t)0x00000060) /*!< REV_IN Reverse Input Data bits */
ommpy 0:d383e2dee0f7 697 #define CRC_CR_REV_IN_0 ((uint32_t)0x00000020) /*!< REV_IN Bit 0 */
ommpy 0:d383e2dee0f7 698 #define CRC_CR_REV_IN_1 ((uint32_t)0x00000040) /*!< REV_IN Bit 1 */
ommpy 0:d383e2dee0f7 699 #define CRC_CR_REV_OUT ((uint32_t)0x00000080) /*!< REV_OUT Reverse Output Data bits */
ommpy 0:d383e2dee0f7 700
ommpy 0:d383e2dee0f7 701 /******************* Bit definition for CRC_INIT register *******************/
ommpy 0:d383e2dee0f7 702 #define CRC_INIT_INIT ((uint32_t)0xFFFFFFFF) /*!< Initial CRC value bits */
ommpy 0:d383e2dee0f7 703
ommpy 0:d383e2dee0f7 704 /******************************************************************************/
ommpy 0:d383e2dee0f7 705 /* */
ommpy 0:d383e2dee0f7 706 /* Debug MCU (DBGMCU) */
ommpy 0:d383e2dee0f7 707 /* */
ommpy 0:d383e2dee0f7 708 /******************************************************************************/
ommpy 0:d383e2dee0f7 709
ommpy 0:d383e2dee0f7 710 /**************** Bit definition for DBGMCU_IDCODE register *****************/
ommpy 0:d383e2dee0f7 711 #define DBGMCU_IDCODE_DEV_ID ((uint32_t)0x00000FFF) /*!< Device Identifier */
ommpy 0:d383e2dee0f7 712
ommpy 0:d383e2dee0f7 713 #define DBGMCU_IDCODE_REV_ID ((uint32_t)0xFFFF0000) /*!< REV_ID[15:0] bits (Revision Identifier) */
ommpy 0:d383e2dee0f7 714 #define DBGMCU_IDCODE_REV_ID_0 ((uint32_t)0x00010000) /*!< Bit 0 */
ommpy 0:d383e2dee0f7 715 #define DBGMCU_IDCODE_REV_ID_1 ((uint32_t)0x00020000) /*!< Bit 1 */
ommpy 0:d383e2dee0f7 716 #define DBGMCU_IDCODE_REV_ID_2 ((uint32_t)0x00040000) /*!< Bit 2 */
ommpy 0:d383e2dee0f7 717 #define DBGMCU_IDCODE_REV_ID_3 ((uint32_t)0x00080000) /*!< Bit 3 */
ommpy 0:d383e2dee0f7 718 #define DBGMCU_IDCODE_REV_ID_4 ((uint32_t)0x00100000) /*!< Bit 4 */
ommpy 0:d383e2dee0f7 719 #define DBGMCU_IDCODE_REV_ID_5 ((uint32_t)0x00200000) /*!< Bit 5 */
ommpy 0:d383e2dee0f7 720 #define DBGMCU_IDCODE_REV_ID_6 ((uint32_t)0x00400000) /*!< Bit 6 */
ommpy 0:d383e2dee0f7 721 #define DBGMCU_IDCODE_REV_ID_7 ((uint32_t)0x00800000) /*!< Bit 7 */
ommpy 0:d383e2dee0f7 722 #define DBGMCU_IDCODE_REV_ID_8 ((uint32_t)0x01000000) /*!< Bit 8 */
ommpy 0:d383e2dee0f7 723 #define DBGMCU_IDCODE_REV_ID_9 ((uint32_t)0x02000000) /*!< Bit 9 */
ommpy 0:d383e2dee0f7 724 #define DBGMCU_IDCODE_REV_ID_10 ((uint32_t)0x04000000) /*!< Bit 10 */
ommpy 0:d383e2dee0f7 725 #define DBGMCU_IDCODE_REV_ID_11 ((uint32_t)0x08000000) /*!< Bit 11 */
ommpy 0:d383e2dee0f7 726 #define DBGMCU_IDCODE_REV_ID_12 ((uint32_t)0x10000000) /*!< Bit 12 */
ommpy 0:d383e2dee0f7 727 #define DBGMCU_IDCODE_REV_ID_13 ((uint32_t)0x20000000) /*!< Bit 13 */
ommpy 0:d383e2dee0f7 728 #define DBGMCU_IDCODE_REV_ID_14 ((uint32_t)0x40000000) /*!< Bit 14 */
ommpy 0:d383e2dee0f7 729 #define DBGMCU_IDCODE_REV_ID_15 ((uint32_t)0x80000000) /*!< Bit 15 */
ommpy 0:d383e2dee0f7 730
ommpy 0:d383e2dee0f7 731 /****************** Bit definition for DBGMCU_CR register *******************/
ommpy 0:d383e2dee0f7 732 #define DBGMCU_CR_DBG_STOP ((uint32_t)0x00000002) /*!< Debug Stop Mode */
ommpy 0:d383e2dee0f7 733 #define DBGMCU_CR_DBG_STANDBY ((uint32_t)0x00000004) /*!< Debug Standby mode */
ommpy 0:d383e2dee0f7 734
ommpy 0:d383e2dee0f7 735 /****************** Bit definition for DBGMCU_APB1_FZ register **************/
ommpy 0:d383e2dee0f7 736 #define DBGMCU_APB1_FZ_DBG_TIM3_STOP ((uint32_t)0x00000002) /*!< TIM3 counter stopped when core is halted */
ommpy 0:d383e2dee0f7 737 #define DBGMCU_APB1_FZ_DBG_TIM6_STOP ((uint32_t)0x00000010) /*!< TIM6 counter stopped when core is halted */
ommpy 0:d383e2dee0f7 738 #define DBGMCU_APB1_FZ_DBG_TIM14_STOP ((uint32_t)0x00000100) /*!< TIM14 counter stopped when core is halted */
ommpy 0:d383e2dee0f7 739 #define DBGMCU_APB1_FZ_DBG_RTC_STOP ((uint32_t)0x00000400) /*!< RTC Calendar frozen when core is halted */
ommpy 0:d383e2dee0f7 740 #define DBGMCU_APB1_FZ_DBG_WWDG_STOP ((uint32_t)0x00000800) /*!< Debug Window Watchdog stopped when Core is halted */
ommpy 0:d383e2dee0f7 741 #define DBGMCU_APB1_FZ_DBG_IWDG_STOP ((uint32_t)0x00001000) /*!< Debug Independent Watchdog stopped when Core is halted */
ommpy 0:d383e2dee0f7 742 #define DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT ((uint32_t)0x00200000) /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
ommpy 0:d383e2dee0f7 743
ommpy 0:d383e2dee0f7 744 /****************** Bit definition for DBGMCU_APB2_FZ register **************/
ommpy 0:d383e2dee0f7 745 #define DBGMCU_APB2_FZ_DBG_TIM1_STOP ((uint32_t)0x00000800) /*!< TIM1 counter stopped when core is halted */
ommpy 0:d383e2dee0f7 746 #define DBGMCU_APB2_FZ_DBG_TIM15_STOP ((uint32_t)0x00010000) /*!< TIM15 counter stopped when core is halted */
ommpy 0:d383e2dee0f7 747 #define DBGMCU_APB2_FZ_DBG_TIM16_STOP ((uint32_t)0x00020000) /*!< TIM16 counter stopped when core is halted */
ommpy 0:d383e2dee0f7 748 #define DBGMCU_APB2_FZ_DBG_TIM17_STOP ((uint32_t)0x00040000) /*!< TIM17 counter stopped when core is halted */
ommpy 0:d383e2dee0f7 749
ommpy 0:d383e2dee0f7 750 /******************************************************************************/
ommpy 0:d383e2dee0f7 751 /* */
ommpy 0:d383e2dee0f7 752 /* DMA Controller (DMA) */
ommpy 0:d383e2dee0f7 753 /* */
ommpy 0:d383e2dee0f7 754 /******************************************************************************/
ommpy 0:d383e2dee0f7 755 /******************* Bit definition for DMA_ISR register ********************/
ommpy 0:d383e2dee0f7 756 #define DMA_ISR_GIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt flag */
ommpy 0:d383e2dee0f7 757 #define DMA_ISR_TCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete flag */
ommpy 0:d383e2dee0f7 758 #define DMA_ISR_HTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer flag */
ommpy 0:d383e2dee0f7 759 #define DMA_ISR_TEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error flag */
ommpy 0:d383e2dee0f7 760 #define DMA_ISR_GIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt flag */
ommpy 0:d383e2dee0f7 761 #define DMA_ISR_TCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete flag */
ommpy 0:d383e2dee0f7 762 #define DMA_ISR_HTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer flag */
ommpy 0:d383e2dee0f7 763 #define DMA_ISR_TEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error flag */
ommpy 0:d383e2dee0f7 764 #define DMA_ISR_GIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt flag */
ommpy 0:d383e2dee0f7 765 #define DMA_ISR_TCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete flag */
ommpy 0:d383e2dee0f7 766 #define DMA_ISR_HTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer flag */
ommpy 0:d383e2dee0f7 767 #define DMA_ISR_TEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error flag */
ommpy 0:d383e2dee0f7 768 #define DMA_ISR_GIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt flag */
ommpy 0:d383e2dee0f7 769 #define DMA_ISR_TCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete flag */
ommpy 0:d383e2dee0f7 770 #define DMA_ISR_HTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer flag */
ommpy 0:d383e2dee0f7 771 #define DMA_ISR_TEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error flag */
ommpy 0:d383e2dee0f7 772 #define DMA_ISR_GIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt flag */
ommpy 0:d383e2dee0f7 773 #define DMA_ISR_TCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete flag */
ommpy 0:d383e2dee0f7 774 #define DMA_ISR_HTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer flag */
ommpy 0:d383e2dee0f7 775 #define DMA_ISR_TEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error flag */
ommpy 0:d383e2dee0f7 776
ommpy 0:d383e2dee0f7 777 /******************* Bit definition for DMA_IFCR register *******************/
ommpy 0:d383e2dee0f7 778 #define DMA_IFCR_CGIF1 ((uint32_t)0x00000001) /*!< Channel 1 Global interrupt clear */
ommpy 0:d383e2dee0f7 779 #define DMA_IFCR_CTCIF1 ((uint32_t)0x00000002) /*!< Channel 1 Transfer Complete clear */
ommpy 0:d383e2dee0f7 780 #define DMA_IFCR_CHTIF1 ((uint32_t)0x00000004) /*!< Channel 1 Half Transfer clear */
ommpy 0:d383e2dee0f7 781 #define DMA_IFCR_CTEIF1 ((uint32_t)0x00000008) /*!< Channel 1 Transfer Error clear */
ommpy 0:d383e2dee0f7 782 #define DMA_IFCR_CGIF2 ((uint32_t)0x00000010) /*!< Channel 2 Global interrupt clear */
ommpy 0:d383e2dee0f7 783 #define DMA_IFCR_CTCIF2 ((uint32_t)0x00000020) /*!< Channel 2 Transfer Complete clear */
ommpy 0:d383e2dee0f7 784 #define DMA_IFCR_CHTIF2 ((uint32_t)0x00000040) /*!< Channel 2 Half Transfer clear */
ommpy 0:d383e2dee0f7 785 #define DMA_IFCR_CTEIF2 ((uint32_t)0x00000080) /*!< Channel 2 Transfer Error clear */
ommpy 0:d383e2dee0f7 786 #define DMA_IFCR_CGIF3 ((uint32_t)0x00000100) /*!< Channel 3 Global interrupt clear */
ommpy 0:d383e2dee0f7 787 #define DMA_IFCR_CTCIF3 ((uint32_t)0x00000200) /*!< Channel 3 Transfer Complete clear */
ommpy 0:d383e2dee0f7 788 #define DMA_IFCR_CHTIF3 ((uint32_t)0x00000400) /*!< Channel 3 Half Transfer clear */
ommpy 0:d383e2dee0f7 789 #define DMA_IFCR_CTEIF3 ((uint32_t)0x00000800) /*!< Channel 3 Transfer Error clear */
ommpy 0:d383e2dee0f7 790 #define DMA_IFCR_CGIF4 ((uint32_t)0x00001000) /*!< Channel 4 Global interrupt clear */
ommpy 0:d383e2dee0f7 791 #define DMA_IFCR_CTCIF4 ((uint32_t)0x00002000) /*!< Channel 4 Transfer Complete clear */
ommpy 0:d383e2dee0f7 792 #define DMA_IFCR_CHTIF4 ((uint32_t)0x00004000) /*!< Channel 4 Half Transfer clear */
ommpy 0:d383e2dee0f7 793 #define DMA_IFCR_CTEIF4 ((uint32_t)0x00008000) /*!< Channel 4 Transfer Error clear */
ommpy 0:d383e2dee0f7 794 #define DMA_IFCR_CGIF5 ((uint32_t)0x00010000) /*!< Channel 5 Global interrupt clear */
ommpy 0:d383e2dee0f7 795 #define DMA_IFCR_CTCIF5 ((uint32_t)0x00020000) /*!< Channel 5 Transfer Complete clear */
ommpy 0:d383e2dee0f7 796 #define DMA_IFCR_CHTIF5 ((uint32_t)0x00040000) /*!< Channel 5 Half Transfer clear */
ommpy 0:d383e2dee0f7 797 #define DMA_IFCR_CTEIF5 ((uint32_t)0x00080000) /*!< Channel 5 Transfer Error clear */
ommpy 0:d383e2dee0f7 798
ommpy 0:d383e2dee0f7 799 /******************* Bit definition for DMA_CCR register ********************/
ommpy 0:d383e2dee0f7 800 #define DMA_CCR_EN ((uint32_t)0x00000001) /*!< Channel enable */
ommpy 0:d383e2dee0f7 801 #define DMA_CCR_TCIE ((uint32_t)0x00000002) /*!< Transfer complete interrupt enable */
ommpy 0:d383e2dee0f7 802 #define DMA_CCR_HTIE ((uint32_t)0x00000004) /*!< Half Transfer interrupt enable */
ommpy 0:d383e2dee0f7 803 #define DMA_CCR_TEIE ((uint32_t)0x00000008) /*!< Transfer error interrupt enable */
ommpy 0:d383e2dee0f7 804 #define DMA_CCR_DIR ((uint32_t)0x00000010) /*!< Data transfer direction */
ommpy 0:d383e2dee0f7 805 #define DMA_CCR_CIRC ((uint32_t)0x00000020) /*!< Circular mode */
ommpy 0:d383e2dee0f7 806 #define DMA_CCR_PINC ((uint32_t)0x00000040) /*!< Peripheral increment mode */
ommpy 0:d383e2dee0f7 807 #define DMA_CCR_MINC ((uint32_t)0x00000080) /*!< Memory increment mode */
ommpy 0:d383e2dee0f7 808
ommpy 0:d383e2dee0f7 809 #define DMA_CCR_PSIZE ((uint32_t)0x00000300) /*!< PSIZE[1:0] bits (Peripheral size) */
ommpy 0:d383e2dee0f7 810 #define DMA_CCR_PSIZE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
ommpy 0:d383e2dee0f7 811 #define DMA_CCR_PSIZE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
ommpy 0:d383e2dee0f7 812
ommpy 0:d383e2dee0f7 813 #define DMA_CCR_MSIZE ((uint32_t)0x00000C00) /*!< MSIZE[1:0] bits (Memory size) */
ommpy 0:d383e2dee0f7 814 #define DMA_CCR_MSIZE_0 ((uint32_t)0x00000400) /*!< Bit 0 */
ommpy 0:d383e2dee0f7 815 #define DMA_CCR_MSIZE_1 ((uint32_t)0x00000800) /*!< Bit 1 */
ommpy 0:d383e2dee0f7 816
ommpy 0:d383e2dee0f7 817 #define DMA_CCR_PL ((uint32_t)0x00003000) /*!< PL[1:0] bits(Channel Priority level)*/
ommpy 0:d383e2dee0f7 818 #define DMA_CCR_PL_0 ((uint32_t)0x00001000) /*!< Bit 0 */
ommpy 0:d383e2dee0f7 819 #define DMA_CCR_PL_1 ((uint32_t)0x00002000) /*!< Bit 1 */
ommpy 0:d383e2dee0f7 820
ommpy 0:d383e2dee0f7 821 #define DMA_CCR_MEM2MEM ((uint32_t)0x00004000) /*!< Memory to memory mode */
ommpy 0:d383e2dee0f7 822
ommpy 0:d383e2dee0f7 823 /****************** Bit definition for DMA_CNDTR register *******************/
ommpy 0:d383e2dee0f7 824 #define DMA_CNDTR_NDT ((uint32_t)0x0000FFFF) /*!< Number of data to Transfer */
ommpy 0:d383e2dee0f7 825
ommpy 0:d383e2dee0f7 826 /****************** Bit definition for DMA_CPAR register ********************/
ommpy 0:d383e2dee0f7 827 #define DMA_CPAR_PA ((uint32_t)0xFFFFFFFF) /*!< Peripheral Address */
ommpy 0:d383e2dee0f7 828
ommpy 0:d383e2dee0f7 829 /****************** Bit definition for DMA_CMAR register ********************/
ommpy 0:d383e2dee0f7 830 #define DMA_CMAR_MA ((uint32_t)0xFFFFFFFF) /*!< Memory Address */
ommpy 0:d383e2dee0f7 831
ommpy 0:d383e2dee0f7 832 /******************************************************************************/
ommpy 0:d383e2dee0f7 833 /* */
ommpy 0:d383e2dee0f7 834 /* External Interrupt/Event Controller (EXTI) */
ommpy 0:d383e2dee0f7 835 /* */
ommpy 0:d383e2dee0f7 836 /******************************************************************************/
ommpy 0:d383e2dee0f7 837 /******************* Bit definition for EXTI_IMR register *******************/
ommpy 0:d383e2dee0f7 838 #define EXTI_IMR_MR0 ((uint32_t)0x00000001) /*!< Interrupt Mask on line 0 */
ommpy 0:d383e2dee0f7 839 #define EXTI_IMR_MR1 ((uint32_t)0x00000002) /*!< Interrupt Mask on line 1 */
ommpy 0:d383e2dee0f7 840 #define EXTI_IMR_MR2 ((uint32_t)0x00000004) /*!< Interrupt Mask on line 2 */
ommpy 0:d383e2dee0f7 841 #define EXTI_IMR_MR3 ((uint32_t)0x00000008) /*!< Interrupt Mask on line 3 */
ommpy 0:d383e2dee0f7 842 #define EXTI_IMR_MR4 ((uint32_t)0x00000010) /*!< Interrupt Mask on line 4 */
ommpy 0:d383e2dee0f7 843 #define EXTI_IMR_MR5 ((uint32_t)0x00000020) /*!< Interrupt Mask on line 5 */
ommpy 0:d383e2dee0f7 844 #define EXTI_IMR_MR6 ((uint32_t)0x00000040) /*!< Interrupt Mask on line 6 */
ommpy 0:d383e2dee0f7 845 #define EXTI_IMR_MR7 ((uint32_t)0x00000080) /*!< Interrupt Mask on line 7 */
ommpy 0:d383e2dee0f7 846 #define EXTI_IMR_MR8 ((uint32_t)0x00000100) /*!< Interrupt Mask on line 8 */
ommpy 0:d383e2dee0f7 847 #define EXTI_IMR_MR9 ((uint32_t)0x00000200) /*!< Interrupt Mask on line 9 */
ommpy 0:d383e2dee0f7 848 #define EXTI_IMR_MR10 ((uint32_t)0x00000400) /*!< Interrupt Mask on line 10 */
ommpy 0:d383e2dee0f7 849 #define EXTI_IMR_MR11 ((uint32_t)0x00000800) /*!< Interrupt Mask on line 11 */
ommpy 0:d383e2dee0f7 850 #define EXTI_IMR_MR12 ((uint32_t)0x00001000) /*!< Interrupt Mask on line 12 */
ommpy 0:d383e2dee0f7 851 #define EXTI_IMR_MR13 ((uint32_t)0x00002000) /*!< Interrupt Mask on line 13 */
ommpy 0:d383e2dee0f7 852 #define EXTI_IMR_MR14 ((uint32_t)0x00004000) /*!< Interrupt Mask on line 14 */
ommpy 0:d383e2dee0f7 853 #define EXTI_IMR_MR15 ((uint32_t)0x00008000) /*!< Interrupt Mask on line 15 */
ommpy 0:d383e2dee0f7 854 #define EXTI_IMR_MR16 ((uint32_t)0x00010000) /*!< Interrupt Mask on line 16 */
ommpy 0:d383e2dee0f7 855 #define EXTI_IMR_MR17 ((uint32_t)0x00020000) /*!< Interrupt Mask on line 17 */
ommpy 0:d383e2dee0f7 856 #define EXTI_IMR_MR19 ((uint32_t)0x00080000) /*!< Interrupt Mask on line 19 */
ommpy 0:d383e2dee0f7 857 #define EXTI_IMR_MR21 ((uint32_t)0x00200000) /*!< Interrupt Mask on line 21 */
ommpy 0:d383e2dee0f7 858 #define EXTI_IMR_MR22 ((uint32_t)0x00400000) /*!< Interrupt Mask on line 22 */
ommpy 0:d383e2dee0f7 859 #define EXTI_IMR_MR23 ((uint32_t)0x00800000) /*!< Interrupt Mask on line 23 */
ommpy 0:d383e2dee0f7 860 #define EXTI_IMR_MR25 ((uint32_t)0x02000000) /*!< Interrupt Mask on line 25 */
ommpy 0:d383e2dee0f7 861 #define EXTI_IMR_MR27 ((uint32_t)0x08000000) /*!< Interrupt Mask on line 27 */
ommpy 0:d383e2dee0f7 862
ommpy 0:d383e2dee0f7 863 /****************** Bit definition for EXTI_EMR register ********************/
ommpy 0:d383e2dee0f7 864 #define EXTI_EMR_MR0 ((uint32_t)0x00000001) /*!< Event Mask on line 0 */
ommpy 0:d383e2dee0f7 865 #define EXTI_EMR_MR1 ((uint32_t)0x00000002) /*!< Event Mask on line 1 */
ommpy 0:d383e2dee0f7 866 #define EXTI_EMR_MR2 ((uint32_t)0x00000004) /*!< Event Mask on line 2 */
ommpy 0:d383e2dee0f7 867 #define EXTI_EMR_MR3 ((uint32_t)0x00000008) /*!< Event Mask on line 3 */
ommpy 0:d383e2dee0f7 868 #define EXTI_EMR_MR4 ((uint32_t)0x00000010) /*!< Event Mask on line 4 */
ommpy 0:d383e2dee0f7 869 #define EXTI_EMR_MR5 ((uint32_t)0x00000020) /*!< Event Mask on line 5 */
ommpy 0:d383e2dee0f7 870 #define EXTI_EMR_MR6 ((uint32_t)0x00000040) /*!< Event Mask on line 6 */
ommpy 0:d383e2dee0f7 871 #define EXTI_EMR_MR7 ((uint32_t)0x00000080) /*!< Event Mask on line 7 */
ommpy 0:d383e2dee0f7 872 #define EXTI_EMR_MR8 ((uint32_t)0x00000100) /*!< Event Mask on line 8 */
ommpy 0:d383e2dee0f7 873 #define EXTI_EMR_MR9 ((uint32_t)0x00000200) /*!< Event Mask on line 9 */
ommpy 0:d383e2dee0f7 874 #define EXTI_EMR_MR10 ((uint32_t)0x00000400) /*!< Event Mask on line 10 */
ommpy 0:d383e2dee0f7 875 #define EXTI_EMR_MR11 ((uint32_t)0x00000800) /*!< Event Mask on line 11 */
ommpy 0:d383e2dee0f7 876 #define EXTI_EMR_MR12 ((uint32_t)0x00001000) /*!< Event Mask on line 12 */
ommpy 0:d383e2dee0f7 877 #define EXTI_EMR_MR13 ((uint32_t)0x00002000) /*!< Event Mask on line 13 */
ommpy 0:d383e2dee0f7 878 #define EXTI_EMR_MR14 ((uint32_t)0x00004000) /*!< Event Mask on line 14 */
ommpy 0:d383e2dee0f7 879 #define EXTI_EMR_MR15 ((uint32_t)0x00008000) /*!< Event Mask on line 15 */
ommpy 0:d383e2dee0f7 880 #define EXTI_EMR_MR16 ((uint32_t)0x00010000) /*!< Event Mask on line 16 */
ommpy 0:d383e2dee0f7 881 #define EXTI_EMR_MR17 ((uint32_t)0x00020000) /*!< Event Mask on line 17 */
ommpy 0:d383e2dee0f7 882 #define EXTI_EMR_MR19 ((uint32_t)0x00080000) /*!< Event Mask on line 19 */
ommpy 0:d383e2dee0f7 883 #define EXTI_EMR_MR21 ((uint32_t)0x00200000) /*!< Event Mask on line 21 */
ommpy 0:d383e2dee0f7 884 #define EXTI_EMR_MR22 ((uint32_t)0x00400000) /*!< Event Mask on line 22 */
ommpy 0:d383e2dee0f7 885 #define EXTI_EMR_MR23 ((uint32_t)0x00800000) /*!< Event Mask on line 23 */
ommpy 0:d383e2dee0f7 886 #define EXTI_EMR_MR25 ((uint32_t)0x02000000) /*!< Event Mask on line 25 */
ommpy 0:d383e2dee0f7 887 #define EXTI_EMR_MR27 ((uint32_t)0x08000000) /*!< Event Mask on line 27 */
ommpy 0:d383e2dee0f7 888
ommpy 0:d383e2dee0f7 889 /******************* Bit definition for EXTI_RTSR register ******************/
ommpy 0:d383e2dee0f7 890 #define EXTI_RTSR_TR0 ((uint32_t)0x00000001) /*!< Rising trigger event configuration bit of line 0 */
ommpy 0:d383e2dee0f7 891 #define EXTI_RTSR_TR1 ((uint32_t)0x00000002) /*!< Rising trigger event configuration bit of line 1 */
ommpy 0:d383e2dee0f7 892 #define EXTI_RTSR_TR2 ((uint32_t)0x00000004) /*!< Rising trigger event configuration bit of line 2 */
ommpy 0:d383e2dee0f7 893 #define EXTI_RTSR_TR3 ((uint32_t)0x00000008) /*!< Rising trigger event configuration bit of line 3 */
ommpy 0:d383e2dee0f7 894 #define EXTI_RTSR_TR4 ((uint32_t)0x00000010) /*!< Rising trigger event configuration bit of line 4 */
ommpy 0:d383e2dee0f7 895 #define EXTI_RTSR_TR5 ((uint32_t)0x00000020) /*!< Rising trigger event configuration bit of line 5 */
ommpy 0:d383e2dee0f7 896 #define EXTI_RTSR_TR6 ((uint32_t)0x00000040) /*!< Rising trigger event configuration bit of line 6 */
ommpy 0:d383e2dee0f7 897 #define EXTI_RTSR_TR7 ((uint32_t)0x00000080) /*!< Rising trigger event configuration bit of line 7 */
ommpy 0:d383e2dee0f7 898 #define EXTI_RTSR_TR8 ((uint32_t)0x00000100) /*!< Rising trigger event configuration bit of line 8 */
ommpy 0:d383e2dee0f7 899 #define EXTI_RTSR_TR9 ((uint32_t)0x00000200) /*!< Rising trigger event configuration bit of line 9 */
ommpy 0:d383e2dee0f7 900 #define EXTI_RTSR_TR10 ((uint32_t)0x00000400) /*!< Rising trigger event configuration bit of line 10 */
ommpy 0:d383e2dee0f7 901 #define EXTI_RTSR_TR11 ((uint32_t)0x00000800) /*!< Rising trigger event configuration bit of line 11 */
ommpy 0:d383e2dee0f7 902 #define EXTI_RTSR_TR12 ((uint32_t)0x00001000) /*!< Rising trigger event configuration bit of line 12 */
ommpy 0:d383e2dee0f7 903 #define EXTI_RTSR_TR13 ((uint32_t)0x00002000) /*!< Rising trigger event configuration bit of line 13 */
ommpy 0:d383e2dee0f7 904 #define EXTI_RTSR_TR14 ((uint32_t)0x00004000) /*!< Rising trigger event configuration bit of line 14 */
ommpy 0:d383e2dee0f7 905 #define EXTI_RTSR_TR15 ((uint32_t)0x00008000) /*!< Rising trigger event configuration bit of line 15 */
ommpy 0:d383e2dee0f7 906 #define EXTI_RTSR_TR16 ((uint32_t)0x00010000) /*!< Rising trigger event configuration bit of line 16 */
ommpy 0:d383e2dee0f7 907 #define EXTI_RTSR_TR17 ((uint32_t)0x00020000) /*!< Rising trigger event configuration bit of line 17 */
ommpy 0:d383e2dee0f7 908 #define EXTI_RTSR_TR19 ((uint32_t)0x00080000) /*!< Rising trigger event configuration bit of line 19 */
ommpy 0:d383e2dee0f7 909
ommpy 0:d383e2dee0f7 910 /******************* Bit definition for EXTI_FTSR register *******************/
ommpy 0:d383e2dee0f7 911 #define EXTI_FTSR_TR0 ((uint32_t)0x00000001) /*!< Falling trigger event configuration bit of line 0 */
ommpy 0:d383e2dee0f7 912 #define EXTI_FTSR_TR1 ((uint32_t)0x00000002) /*!< Falling trigger event configuration bit of line 1 */
ommpy 0:d383e2dee0f7 913 #define EXTI_FTSR_TR2 ((uint32_t)0x00000004) /*!< Falling trigger event configuration bit of line 2 */
ommpy 0:d383e2dee0f7 914 #define EXTI_FTSR_TR3 ((uint32_t)0x00000008) /*!< Falling trigger event configuration bit of line 3 */
ommpy 0:d383e2dee0f7 915 #define EXTI_FTSR_TR4 ((uint32_t)0x00000010) /*!< Falling trigger event configuration bit of line 4 */
ommpy 0:d383e2dee0f7 916 #define EXTI_FTSR_TR5 ((uint32_t)0x00000020) /*!< Falling trigger event configuration bit of line 5 */
ommpy 0:d383e2dee0f7 917 #define EXTI_FTSR_TR6 ((uint32_t)0x00000040) /*!< Falling trigger event configuration bit of line 6 */
ommpy 0:d383e2dee0f7 918 #define EXTI_FTSR_TR7 ((uint32_t)0x00000080) /*!< Falling trigger event configuration bit of line 7 */
ommpy 0:d383e2dee0f7 919 #define EXTI_FTSR_TR8 ((uint32_t)0x00000100) /*!< Falling trigger event configuration bit of line 8 */
ommpy 0:d383e2dee0f7 920 #define EXTI_FTSR_TR9 ((uint32_t)0x00000200) /*!< Falling trigger event configuration bit of line 9 */
ommpy 0:d383e2dee0f7 921 #define EXTI_FTSR_TR10 ((uint32_t)0x00000400) /*!< Falling trigger event configuration bit of line 10 */
ommpy 0:d383e2dee0f7 922 #define EXTI_FTSR_TR11 ((uint32_t)0x00000800) /*!< Falling trigger event configuration bit of line 11 */
ommpy 0:d383e2dee0f7 923 #define EXTI_FTSR_TR12 ((uint32_t)0x00001000) /*!< Falling trigger event configuration bit of line 12 */
ommpy 0:d383e2dee0f7 924 #define EXTI_FTSR_TR13 ((uint32_t)0x00002000) /*!< Falling trigger event configuration bit of line 13 */
ommpy 0:d383e2dee0f7 925 #define EXTI_FTSR_TR14 ((uint32_t)0x00004000) /*!< Falling trigger event configuration bit of line 14 */
ommpy 0:d383e2dee0f7 926 #define EXTI_FTSR_TR15 ((uint32_t)0x00008000) /*!< Falling trigger event configuration bit of line 15 */
ommpy 0:d383e2dee0f7 927 #define EXTI_FTSR_TR16 ((uint32_t)0x00010000) /*!< Falling trigger event configuration bit of line 16 */
ommpy 0:d383e2dee0f7 928 #define EXTI_FTSR_TR17 ((uint32_t)0x00020000) /*!< Falling trigger event configuration bit of line 17 */
ommpy 0:d383e2dee0f7 929 #define EXTI_FTSR_TR19 ((uint32_t)0x00080000) /*!< Falling trigger event configuration bit of line 19 */
ommpy 0:d383e2dee0f7 930
ommpy 0:d383e2dee0f7 931 /******************* Bit definition for EXTI_SWIER register *******************/
ommpy 0:d383e2dee0f7 932 #define EXTI_SWIER_SWIER0 ((uint32_t)0x00000001) /*!< Software Interrupt on line 0 */
ommpy 0:d383e2dee0f7 933 #define EXTI_SWIER_SWIER1 ((uint32_t)0x00000002) /*!< Software Interrupt on line 1 */
ommpy 0:d383e2dee0f7 934 #define EXTI_SWIER_SWIER2 ((uint32_t)0x00000004) /*!< Software Interrupt on line 2 */
ommpy 0:d383e2dee0f7 935 #define EXTI_SWIER_SWIER3 ((uint32_t)0x00000008) /*!< Software Interrupt on line 3 */
ommpy 0:d383e2dee0f7 936 #define EXTI_SWIER_SWIER4 ((uint32_t)0x00000010) /*!< Software Interrupt on line 4 */
ommpy 0:d383e2dee0f7 937 #define EXTI_SWIER_SWIER5 ((uint32_t)0x00000020) /*!< Software Interrupt on line 5 */
ommpy 0:d383e2dee0f7 938 #define EXTI_SWIER_SWIER6 ((uint32_t)0x00000040) /*!< Software Interrupt on line 6 */
ommpy 0:d383e2dee0f7 939 #define EXTI_SWIER_SWIER7 ((uint32_t)0x00000080) /*!< Software Interrupt on line 7 */
ommpy 0:d383e2dee0f7 940 #define EXTI_SWIER_SWIER8 ((uint32_t)0x00000100) /*!< Software Interrupt on line 8 */
ommpy 0:d383e2dee0f7 941 #define EXTI_SWIER_SWIER9 ((uint32_t)0x00000200) /*!< Software Interrupt on line 9 */
ommpy 0:d383e2dee0f7 942 #define EXTI_SWIER_SWIER10 ((uint32_t)0x00000400) /*!< Software Interrupt on line 10 */
ommpy 0:d383e2dee0f7 943 #define EXTI_SWIER_SWIER11 ((uint32_t)0x00000800) /*!< Software Interrupt on line 11 */
ommpy 0:d383e2dee0f7 944 #define EXTI_SWIER_SWIER12 ((uint32_t)0x00001000) /*!< Software Interrupt on line 12 */
ommpy 0:d383e2dee0f7 945 #define EXTI_SWIER_SWIER13 ((uint32_t)0x00002000) /*!< Software Interrupt on line 13 */
ommpy 0:d383e2dee0f7 946 #define EXTI_SWIER_SWIER14 ((uint32_t)0x00004000) /*!< Software Interrupt on line 14 */
ommpy 0:d383e2dee0f7 947 #define EXTI_SWIER_SWIER15 ((uint32_t)0x00008000) /*!< Software Interrupt on line 15 */
ommpy 0:d383e2dee0f7 948 #define EXTI_SWIER_SWIER16 ((uint32_t)0x00010000) /*!< Software Interrupt on line 16 */
ommpy 0:d383e2dee0f7 949 #define EXTI_SWIER_SWIER17 ((uint32_t)0x00020000) /*!< Software Interrupt on line 17 */
ommpy 0:d383e2dee0f7 950 #define EXTI_SWIER_SWIER19 ((uint32_t)0x00080000) /*!< Software Interrupt on line 19 */
ommpy 0:d383e2dee0f7 951
ommpy 0:d383e2dee0f7 952 /****************** Bit definition for EXTI_PR register *********************/
ommpy 0:d383e2dee0f7 953 #define EXTI_PR_PR0 ((uint32_t)0x00000001) /*!< Pending bit 0 */
ommpy 0:d383e2dee0f7 954 #define EXTI_PR_PR1 ((uint32_t)0x00000002) /*!< Pending bit 1 */
ommpy 0:d383e2dee0f7 955 #define EXTI_PR_PR2 ((uint32_t)0x00000004) /*!< Pending bit 2 */
ommpy 0:d383e2dee0f7 956 #define EXTI_PR_PR3 ((uint32_t)0x00000008) /*!< Pending bit 3 */
ommpy 0:d383e2dee0f7 957 #define EXTI_PR_PR4 ((uint32_t)0x00000010) /*!< Pending bit 4 */
ommpy 0:d383e2dee0f7 958 #define EXTI_PR_PR5 ((uint32_t)0x00000020) /*!< Pending bit 5 */
ommpy 0:d383e2dee0f7 959 #define EXTI_PR_PR6 ((uint32_t)0x00000040) /*!< Pending bit 6 */
ommpy 0:d383e2dee0f7 960 #define EXTI_PR_PR7 ((uint32_t)0x00000080) /*!< Pending bit 7 */
ommpy 0:d383e2dee0f7 961 #define EXTI_PR_PR8 ((uint32_t)0x00000100) /*!< Pending bit 8 */
ommpy 0:d383e2dee0f7 962 #define EXTI_PR_PR9 ((uint32_t)0x00000200) /*!< Pending bit 9 */
ommpy 0:d383e2dee0f7 963 #define EXTI_PR_PR10 ((uint32_t)0x00000400) /*!< Pending bit 10 */
ommpy 0:d383e2dee0f7 964 #define EXTI_PR_PR11 ((uint32_t)0x00000800) /*!< Pending bit 11 */
ommpy 0:d383e2dee0f7 965 #define EXTI_PR_PR12 ((uint32_t)0x00001000) /*!< Pending bit 12 */
ommpy 0:d383e2dee0f7 966 #define EXTI_PR_PR13 ((uint32_t)0x00002000) /*!< Pending bit 13 */
ommpy 0:d383e2dee0f7 967 #define EXTI_PR_PR14 ((uint32_t)0x00004000) /*!< Pending bit 14 */
ommpy 0:d383e2dee0f7 968 #define EXTI_PR_PR15 ((uint32_t)0x00008000) /*!< Pending bit 15 */
ommpy 0:d383e2dee0f7 969 #define EXTI_PR_PR16 ((uint32_t)0x00010000) /*!< Pending bit 16 */
ommpy 0:d383e2dee0f7 970 #define EXTI_PR_PR17 ((uint32_t)0x00020000) /*!< Pending bit 17 */
ommpy 0:d383e2dee0f7 971 #define EXTI_PR_PR19 ((uint32_t)0x00080000) /*!< Pending bit 19 */
ommpy 0:d383e2dee0f7 972
ommpy 0:d383e2dee0f7 973 /******************************************************************************/
ommpy 0:d383e2dee0f7 974 /* */
ommpy 0:d383e2dee0f7 975 /* FLASH and Option Bytes Registers */
ommpy 0:d383e2dee0f7 976 /* */
ommpy 0:d383e2dee0f7 977 /******************************************************************************/
ommpy 0:d383e2dee0f7 978
ommpy 0:d383e2dee0f7 979 /******************* Bit definition for FLASH_ACR register ******************/
ommpy 0:d383e2dee0f7 980 #define FLASH_ACR_LATENCY ((uint32_t)0x00000001) /*!< LATENCY bit (Latency) */
ommpy 0:d383e2dee0f7 981
ommpy 0:d383e2dee0f7 982 #define FLASH_ACR_PRFTBE ((uint32_t)0x00000010) /*!< Prefetch Buffer Enable */
ommpy 0:d383e2dee0f7 983 #define FLASH_ACR_PRFTBS ((uint32_t)0x00000020) /*!< Prefetch Buffer Status */
ommpy 0:d383e2dee0f7 984
ommpy 0:d383e2dee0f7 985 /****************** Bit definition for FLASH_KEYR register ******************/
ommpy 0:d383e2dee0f7 986 #define FLASH_KEYR_FKEYR ((uint32_t)0xFFFFFFFF) /*!< FPEC Key */
ommpy 0:d383e2dee0f7 987
ommpy 0:d383e2dee0f7 988 /***************** Bit definition for FLASH_OPTKEYR register ****************/
ommpy 0:d383e2dee0f7 989 #define FLASH_OPTKEYR_OPTKEYR ((uint32_t)0xFFFFFFFF) /*!< Option Byte Key */
ommpy 0:d383e2dee0f7 990
ommpy 0:d383e2dee0f7 991 /****************** FLASH Keys **********************************************/
ommpy 0:d383e2dee0f7 992 #define FLASH_KEY1 ((uint32_t)0x45670123) /*!< Flash program erase key1 */
ommpy 0:d383e2dee0f7 993 #define FLASH_KEY2 ((uint32_t)0xCDEF89AB) /*!< Flash program erase key2: used with FLASH_PEKEY1
ommpy 0:d383e2dee0f7 994 to unlock the write access to the FPEC. */
ommpy 0:d383e2dee0f7 995
ommpy 0:d383e2dee0f7 996 #define FLASH_OPTKEY1 ((uint32_t)0x45670123) /*!< Flash option key1 */
ommpy 0:d383e2dee0f7 997 #define FLASH_OPTKEY2 ((uint32_t)0xCDEF89AB) /*!< Flash option key2: used with FLASH_OPTKEY1 to
ommpy 0:d383e2dee0f7 998 unlock the write access to the option byte block */
ommpy 0:d383e2dee0f7 999
ommpy 0:d383e2dee0f7 1000 /****************** Bit definition for FLASH_SR register *******************/
ommpy 0:d383e2dee0f7 1001 #define FLASH_SR_BSY ((uint32_t)0x00000001) /*!< Busy */
ommpy 0:d383e2dee0f7 1002 #define FLASH_SR_PGERR ((uint32_t)0x00000004) /*!< Programming Error */
ommpy 0:d383e2dee0f7 1003 #define FLASH_SR_WRPRTERR ((uint32_t)0x00000010) /*!< Write Protection Error */
ommpy 0:d383e2dee0f7 1004 #define FLASH_SR_EOP ((uint32_t)0x00000020) /*!< End of operation */
ommpy 0:d383e2dee0f7 1005 #define FLASH_SR_WRPERR FLASH_SR_WRPRTERR /*!< Legacy of Write Protection Error */
ommpy 0:d383e2dee0f7 1006
ommpy 0:d383e2dee0f7 1007 /******************* Bit definition for FLASH_CR register *******************/
ommpy 0:d383e2dee0f7 1008 #define FLASH_CR_PG ((uint32_t)0x00000001) /*!< Programming */
ommpy 0:d383e2dee0f7 1009 #define FLASH_CR_PER ((uint32_t)0x00000002) /*!< Page Erase */
ommpy 0:d383e2dee0f7 1010 #define FLASH_CR_MER ((uint32_t)0x00000004) /*!< Mass Erase */
ommpy 0:d383e2dee0f7 1011 #define FLASH_CR_OPTPG ((uint32_t)0x00000010) /*!< Option Byte Programming */
ommpy 0:d383e2dee0f7 1012 #define FLASH_CR_OPTER ((uint32_t)0x00000020) /*!< Option Byte Erase */
ommpy 0:d383e2dee0f7 1013 #define FLASH_CR_STRT ((uint32_t)0x00000040) /*!< Start */
ommpy 0:d383e2dee0f7 1014 #define FLASH_CR_LOCK ((uint32_t)0x00000080) /*!< Lock */
ommpy 0:d383e2dee0f7 1015 #define FLASH_CR_OPTWRE ((uint32_t)0x00000200) /*!< Option Bytes Write Enable */
ommpy 0:d383e2dee0f7 1016 #define FLASH_CR_ERRIE ((uint32_t)0x00000400) /*!< Error Interrupt Enable */
ommpy 0:d383e2dee0f7 1017 #define FLASH_CR_EOPIE ((uint32_t)0x00001000) /*!< End of operation interrupt enable */
ommpy 0:d383e2dee0f7 1018 #define FLASH_CR_OBL_LAUNCH ((uint32_t)0x00002000) /*!< Option Bytes Loader Launch */
ommpy 0:d383e2dee0f7 1019
ommpy 0:d383e2dee0f7 1020 /******************* Bit definition for FLASH_AR register *******************/
ommpy 0:d383e2dee0f7 1021 #define FLASH_AR_FAR ((uint32_t)0xFFFFFFFF) /*!< Flash Address */
ommpy 0:d383e2dee0f7 1022
ommpy 0:d383e2dee0f7 1023 /****************** Bit definition for FLASH_OBR register *******************/
ommpy 0:d383e2dee0f7 1024 #define FLASH_OBR_OPTERR ((uint32_t)0x00000001) /*!< Option Byte Error */
ommpy 0:d383e2dee0f7 1025 #define FLASH_OBR_RDPRT1 ((uint32_t)0x00000002) /*!< Read protection Level 1 */
ommpy 0:d383e2dee0f7 1026 #define FLASH_OBR_RDPRT2 ((uint32_t)0x00000004) /*!< Read protection Level 2 */
ommpy 0:d383e2dee0f7 1027
ommpy 0:d383e2dee0f7 1028 #define FLASH_OBR_USER ((uint32_t)0x00007700) /*!< User Option Bytes */
ommpy 0:d383e2dee0f7 1029 #define FLASH_OBR_IWDG_SW ((uint32_t)0x00000100) /*!< IWDG SW */
ommpy 0:d383e2dee0f7 1030 #define FLASH_OBR_nRST_STOP ((uint32_t)0x00000200) /*!< nRST_STOP */
ommpy 0:d383e2dee0f7 1031 #define FLASH_OBR_nRST_STDBY ((uint32_t)0x00000400) /*!< nRST_STDBY */
ommpy 0:d383e2dee0f7 1032 #define FLASH_OBR_nBOOT1 ((uint32_t)0x00001000) /*!< nBOOT1 */
ommpy 0:d383e2dee0f7 1033 #define FLASH_OBR_VDDA_MONITOR ((uint32_t)0x00002000) /*!< VDDA power supply supervisor */
ommpy 0:d383e2dee0f7 1034 #define FLASH_OBR_RAM_PARITY_CHECK ((uint32_t)0x00004000) /*!< RAM parity check */
ommpy 0:d383e2dee0f7 1035
ommpy 0:d383e2dee0f7 1036 /* Old BOOT1 bit definition, maintained for legacy purpose */
ommpy 0:d383e2dee0f7 1037 #define FLASH_OBR_BOOT1 FLASH_OBR_nBOOT1
ommpy 0:d383e2dee0f7 1038
ommpy 0:d383e2dee0f7 1039 /* Old OBR_VDDA bit definition, maintained for legacy purpose */
ommpy 0:d383e2dee0f7 1040 #define FLASH_OBR_VDDA_ANALOG FLASH_OBR_VDDA_MONITOR
ommpy 0:d383e2dee0f7 1041
ommpy 0:d383e2dee0f7 1042 /****************** Bit definition for FLASH_WRPR register ******************/
ommpy 0:d383e2dee0f7 1043 #define FLASH_WRPR_WRP ((uint32_t)0x0000FFFF) /*!< Write Protect */
ommpy 0:d383e2dee0f7 1044
ommpy 0:d383e2dee0f7 1045 /*----------------------------------------------------------------------------*/
ommpy 0:d383e2dee0f7 1046
ommpy 0:d383e2dee0f7 1047 /****************** Bit definition for OB_RDP register **********************/
ommpy 0:d383e2dee0f7 1048 #define OB_RDP_RDP ((uint32_t)0x000000FF) /*!< Read protection option byte */
ommpy 0:d383e2dee0f7 1049 #define OB_RDP_nRDP ((uint32_t)0x0000FF00) /*!< Read protection complemented option byte */
ommpy 0:d383e2dee0f7 1050
ommpy 0:d383e2dee0f7 1051 /****************** Bit definition for OB_USER register *********************/
ommpy 0:d383e2dee0f7 1052 #define OB_USER_USER ((uint32_t)0x00FF0000) /*!< User option byte */
ommpy 0:d383e2dee0f7 1053 #define OB_USER_nUSER ((uint32_t)0xFF000000) /*!< User complemented option byte */
ommpy 0:d383e2dee0f7 1054
ommpy 0:d383e2dee0f7 1055 /****************** Bit definition for OB_WRP0 register *********************/
ommpy 0:d383e2dee0f7 1056 #define OB_WRP0_WRP0 ((uint32_t)0x000000FF) /*!< Flash memory write protection option bytes */
ommpy 0:d383e2dee0f7 1057 #define OB_WRP0_nWRP0 ((uint32_t)0x0000FF00) /*!< Flash memory write protection complemented option bytes */
ommpy 0:d383e2dee0f7 1058
ommpy 0:d383e2dee0f7 1059 /****************** Bit definition for OB_WRP1 register *********************/
ommpy 0:d383e2dee0f7 1060 #define OB_WRP1_WRP1 ((uint32_t)0x00FF0000) /*!< Flash memory write protection option bytes */
ommpy 0:d383e2dee0f7 1061 #define OB_WRP1_nWRP1 ((uint32_t)0xFF000000) /*!< Flash memory write protection complemented option bytes */
ommpy 0:d383e2dee0f7 1062
ommpy 0:d383e2dee0f7 1063 /******************************************************************************/
ommpy 0:d383e2dee0f7 1064 /* */
ommpy 0:d383e2dee0f7 1065 /* General Purpose IOs (GPIO) */
ommpy 0:d383e2dee0f7 1066 /* */
ommpy 0:d383e2dee0f7 1067 /******************************************************************************/
ommpy 0:d383e2dee0f7 1068 /******************* Bit definition for GPIO_MODER register *****************/
ommpy 0:d383e2dee0f7 1069 #define GPIO_MODER_MODER0 ((uint32_t)0x00000003)
ommpy 0:d383e2dee0f7 1070 #define GPIO_MODER_MODER0_0 ((uint32_t)0x00000001)
ommpy 0:d383e2dee0f7 1071 #define GPIO_MODER_MODER0_1 ((uint32_t)0x00000002)
ommpy 0:d383e2dee0f7 1072 #define GPIO_MODER_MODER1 ((uint32_t)0x0000000C)
ommpy 0:d383e2dee0f7 1073 #define GPIO_MODER_MODER1_0 ((uint32_t)0x00000004)
ommpy 0:d383e2dee0f7 1074 #define GPIO_MODER_MODER1_1 ((uint32_t)0x00000008)
ommpy 0:d383e2dee0f7 1075 #define GPIO_MODER_MODER2 ((uint32_t)0x00000030)
ommpy 0:d383e2dee0f7 1076 #define GPIO_MODER_MODER2_0 ((uint32_t)0x00000010)
ommpy 0:d383e2dee0f7 1077 #define GPIO_MODER_MODER2_1 ((uint32_t)0x00000020)
ommpy 0:d383e2dee0f7 1078 #define GPIO_MODER_MODER3 ((uint32_t)0x000000C0)
ommpy 0:d383e2dee0f7 1079 #define GPIO_MODER_MODER3_0 ((uint32_t)0x00000040)
ommpy 0:d383e2dee0f7 1080 #define GPIO_MODER_MODER3_1 ((uint32_t)0x00000080)
ommpy 0:d383e2dee0f7 1081 #define GPIO_MODER_MODER4 ((uint32_t)0x00000300)
ommpy 0:d383e2dee0f7 1082 #define GPIO_MODER_MODER4_0 ((uint32_t)0x00000100)
ommpy 0:d383e2dee0f7 1083 #define GPIO_MODER_MODER4_1 ((uint32_t)0x00000200)
ommpy 0:d383e2dee0f7 1084 #define GPIO_MODER_MODER5 ((uint32_t)0x00000C00)
ommpy 0:d383e2dee0f7 1085 #define GPIO_MODER_MODER5_0 ((uint32_t)0x00000400)
ommpy 0:d383e2dee0f7 1086 #define GPIO_MODER_MODER5_1 ((uint32_t)0x00000800)
ommpy 0:d383e2dee0f7 1087 #define GPIO_MODER_MODER6 ((uint32_t)0x00003000)
ommpy 0:d383e2dee0f7 1088 #define GPIO_MODER_MODER6_0 ((uint32_t)0x00001000)
ommpy 0:d383e2dee0f7 1089 #define GPIO_MODER_MODER6_1 ((uint32_t)0x00002000)
ommpy 0:d383e2dee0f7 1090 #define GPIO_MODER_MODER7 ((uint32_t)0x0000C000)
ommpy 0:d383e2dee0f7 1091 #define GPIO_MODER_MODER7_0 ((uint32_t)0x00004000)
ommpy 0:d383e2dee0f7 1092 #define GPIO_MODER_MODER7_1 ((uint32_t)0x00008000)
ommpy 0:d383e2dee0f7 1093 #define GPIO_MODER_MODER8 ((uint32_t)0x00030000)
ommpy 0:d383e2dee0f7 1094 #define GPIO_MODER_MODER8_0 ((uint32_t)0x00010000)
ommpy 0:d383e2dee0f7 1095 #define GPIO_MODER_MODER8_1 ((uint32_t)0x00020000)
ommpy 0:d383e2dee0f7 1096 #define GPIO_MODER_MODER9 ((uint32_t)0x000C0000)
ommpy 0:d383e2dee0f7 1097 #define GPIO_MODER_MODER9_0 ((uint32_t)0x00040000)
ommpy 0:d383e2dee0f7 1098 #define GPIO_MODER_MODER9_1 ((uint32_t)0x00080000)
ommpy 0:d383e2dee0f7 1099 #define GPIO_MODER_MODER10 ((uint32_t)0x00300000)
ommpy 0:d383e2dee0f7 1100 #define GPIO_MODER_MODER10_0 ((uint32_t)0x00100000)
ommpy 0:d383e2dee0f7 1101 #define GPIO_MODER_MODER10_1 ((uint32_t)0x00200000)
ommpy 0:d383e2dee0f7 1102 #define GPIO_MODER_MODER11 ((uint32_t)0x00C00000)
ommpy 0:d383e2dee0f7 1103 #define GPIO_MODER_MODER11_0 ((uint32_t)0x00400000)
ommpy 0:d383e2dee0f7 1104 #define GPIO_MODER_MODER11_1 ((uint32_t)0x00800000)
ommpy 0:d383e2dee0f7 1105 #define GPIO_MODER_MODER12 ((uint32_t)0x03000000)
ommpy 0:d383e2dee0f7 1106 #define GPIO_MODER_MODER12_0 ((uint32_t)0x01000000)
ommpy 0:d383e2dee0f7 1107 #define GPIO_MODER_MODER12_1 ((uint32_t)0x02000000)
ommpy 0:d383e2dee0f7 1108 #define GPIO_MODER_MODER13 ((uint32_t)0x0C000000)
ommpy 0:d383e2dee0f7 1109 #define GPIO_MODER_MODER13_0 ((uint32_t)0x04000000)
ommpy 0:d383e2dee0f7 1110 #define GPIO_MODER_MODER13_1 ((uint32_t)0x08000000)
ommpy 0:d383e2dee0f7 1111 #define GPIO_MODER_MODER14 ((uint32_t)0x30000000)
ommpy 0:d383e2dee0f7 1112 #define GPIO_MODER_MODER14_0 ((uint32_t)0x10000000)
ommpy 0:d383e2dee0f7 1113 #define GPIO_MODER_MODER14_1 ((uint32_t)0x20000000)
ommpy 0:d383e2dee0f7 1114 #define GPIO_MODER_MODER15 ((uint32_t)0xC0000000)
ommpy 0:d383e2dee0f7 1115 #define GPIO_MODER_MODER15_0 ((uint32_t)0x40000000)
ommpy 0:d383e2dee0f7 1116 #define GPIO_MODER_MODER15_1 ((uint32_t)0x80000000)
ommpy 0:d383e2dee0f7 1117
ommpy 0:d383e2dee0f7 1118 /****************** Bit definition for GPIO_OTYPER register *****************/
ommpy 0:d383e2dee0f7 1119 #define GPIO_OTYPER_OT_0 ((uint32_t)0x00000001)
ommpy 0:d383e2dee0f7 1120 #define GPIO_OTYPER_OT_1 ((uint32_t)0x00000002)
ommpy 0:d383e2dee0f7 1121 #define GPIO_OTYPER_OT_2 ((uint32_t)0x00000004)
ommpy 0:d383e2dee0f7 1122 #define GPIO_OTYPER_OT_3 ((uint32_t)0x00000008)
ommpy 0:d383e2dee0f7 1123 #define GPIO_OTYPER_OT_4 ((uint32_t)0x00000010)
ommpy 0:d383e2dee0f7 1124 #define GPIO_OTYPER_OT_5 ((uint32_t)0x00000020)
ommpy 0:d383e2dee0f7 1125 #define GPIO_OTYPER_OT_6 ((uint32_t)0x00000040)
ommpy 0:d383e2dee0f7 1126 #define GPIO_OTYPER_OT_7 ((uint32_t)0x00000080)
ommpy 0:d383e2dee0f7 1127 #define GPIO_OTYPER_OT_8 ((uint32_t)0x00000100)
ommpy 0:d383e2dee0f7 1128 #define GPIO_OTYPER_OT_9 ((uint32_t)0x00000200)
ommpy 0:d383e2dee0f7 1129 #define GPIO_OTYPER_OT_10 ((uint32_t)0x00000400)
ommpy 0:d383e2dee0f7 1130 #define GPIO_OTYPER_OT_11 ((uint32_t)0x00000800)
ommpy 0:d383e2dee0f7 1131 #define GPIO_OTYPER_OT_12 ((uint32_t)0x00001000)
ommpy 0:d383e2dee0f7 1132 #define GPIO_OTYPER_OT_13 ((uint32_t)0x00002000)
ommpy 0:d383e2dee0f7 1133 #define GPIO_OTYPER_OT_14 ((uint32_t)0x00004000)
ommpy 0:d383e2dee0f7 1134 #define GPIO_OTYPER_OT_15 ((uint32_t)0x00008000)
ommpy 0:d383e2dee0f7 1135
ommpy 0:d383e2dee0f7 1136 /**************** Bit definition for GPIO_OSPEEDR register ******************/
ommpy 0:d383e2dee0f7 1137 #define GPIO_OSPEEDR_OSPEEDR0 ((uint32_t)0x00000003)
ommpy 0:d383e2dee0f7 1138 #define GPIO_OSPEEDR_OSPEEDR0_0 ((uint32_t)0x00000001)
ommpy 0:d383e2dee0f7 1139 #define GPIO_OSPEEDR_OSPEEDR0_1 ((uint32_t)0x00000002)
ommpy 0:d383e2dee0f7 1140 #define GPIO_OSPEEDR_OSPEEDR1 ((uint32_t)0x0000000C)
ommpy 0:d383e2dee0f7 1141 #define GPIO_OSPEEDR_OSPEEDR1_0 ((uint32_t)0x00000004)
ommpy 0:d383e2dee0f7 1142 #define GPIO_OSPEEDR_OSPEEDR1_1 ((uint32_t)0x00000008)
ommpy 0:d383e2dee0f7 1143 #define GPIO_OSPEEDR_OSPEEDR2 ((uint32_t)0x00000030)
ommpy 0:d383e2dee0f7 1144 #define GPIO_OSPEEDR_OSPEEDR2_0 ((uint32_t)0x00000010)
ommpy 0:d383e2dee0f7 1145 #define GPIO_OSPEEDR_OSPEEDR2_1 ((uint32_t)0x00000020)
ommpy 0:d383e2dee0f7 1146 #define GPIO_OSPEEDR_OSPEEDR3 ((uint32_t)0x000000C0)
ommpy 0:d383e2dee0f7 1147 #define GPIO_OSPEEDR_OSPEEDR3_0 ((uint32_t)0x00000040)
ommpy 0:d383e2dee0f7 1148 #define GPIO_OSPEEDR_OSPEEDR3_1 ((uint32_t)0x00000080)
ommpy 0:d383e2dee0f7 1149 #define GPIO_OSPEEDR_OSPEEDR4 ((uint32_t)0x00000300)
ommpy 0:d383e2dee0f7 1150 #define GPIO_OSPEEDR_OSPEEDR4_0 ((uint32_t)0x00000100)
ommpy 0:d383e2dee0f7 1151 #define GPIO_OSPEEDR_OSPEEDR4_1 ((uint32_t)0x00000200)
ommpy 0:d383e2dee0f7 1152 #define GPIO_OSPEEDR_OSPEEDR5 ((uint32_t)0x00000C00)
ommpy 0:d383e2dee0f7 1153 #define GPIO_OSPEEDR_OSPEEDR5_0 ((uint32_t)0x00000400)
ommpy 0:d383e2dee0f7 1154 #define GPIO_OSPEEDR_OSPEEDR5_1 ((uint32_t)0x00000800)
ommpy 0:d383e2dee0f7 1155 #define GPIO_OSPEEDR_OSPEEDR6 ((uint32_t)0x00003000)
ommpy 0:d383e2dee0f7 1156 #define GPIO_OSPEEDR_OSPEEDR6_0 ((uint32_t)0x00001000)
ommpy 0:d383e2dee0f7 1157 #define GPIO_OSPEEDR_OSPEEDR6_1 ((uint32_t)0x00002000)
ommpy 0:d383e2dee0f7 1158 #define GPIO_OSPEEDR_OSPEEDR7 ((uint32_t)0x0000C000)
ommpy 0:d383e2dee0f7 1159 #define GPIO_OSPEEDR_OSPEEDR7_0 ((uint32_t)0x00004000)
ommpy 0:d383e2dee0f7 1160 #define GPIO_OSPEEDR_OSPEEDR7_1 ((uint32_t)0x00008000)
ommpy 0:d383e2dee0f7 1161 #define GPIO_OSPEEDR_OSPEEDR8 ((uint32_t)0x00030000)
ommpy 0:d383e2dee0f7 1162 #define GPIO_OSPEEDR_OSPEEDR8_0 ((uint32_t)0x00010000)
ommpy 0:d383e2dee0f7 1163 #define GPIO_OSPEEDR_OSPEEDR8_1 ((uint32_t)0x00020000)
ommpy 0:d383e2dee0f7 1164 #define GPIO_OSPEEDR_OSPEEDR9 ((uint32_t)0x000C0000)
ommpy 0:d383e2dee0f7 1165 #define GPIO_OSPEEDR_OSPEEDR9_0 ((uint32_t)0x00040000)
ommpy 0:d383e2dee0f7 1166 #define GPIO_OSPEEDR_OSPEEDR9_1 ((uint32_t)0x00080000)
ommpy 0:d383e2dee0f7 1167 #define GPIO_OSPEEDR_OSPEEDR10 ((uint32_t)0x00300000)
ommpy 0:d383e2dee0f7 1168 #define GPIO_OSPEEDR_OSPEEDR10_0 ((uint32_t)0x00100000)
ommpy 0:d383e2dee0f7 1169 #define GPIO_OSPEEDR_OSPEEDR10_1 ((uint32_t)0x00200000)
ommpy 0:d383e2dee0f7 1170 #define GPIO_OSPEEDR_OSPEEDR11 ((uint32_t)0x00C00000)
ommpy 0:d383e2dee0f7 1171 #define GPIO_OSPEEDR_OSPEEDR11_0 ((uint32_t)0x00400000)
ommpy 0:d383e2dee0f7 1172 #define GPIO_OSPEEDR_OSPEEDR11_1 ((uint32_t)0x00800000)
ommpy 0:d383e2dee0f7 1173 #define GPIO_OSPEEDR_OSPEEDR12 ((uint32_t)0x03000000)
ommpy 0:d383e2dee0f7 1174 #define GPIO_OSPEEDR_OSPEEDR12_0 ((uint32_t)0x01000000)
ommpy 0:d383e2dee0f7 1175 #define GPIO_OSPEEDR_OSPEEDR12_1 ((uint32_t)0x02000000)
ommpy 0:d383e2dee0f7 1176 #define GPIO_OSPEEDR_OSPEEDR13 ((uint32_t)0x0C000000)
ommpy 0:d383e2dee0f7 1177 #define GPIO_OSPEEDR_OSPEEDR13_0 ((uint32_t)0x04000000)
ommpy 0:d383e2dee0f7 1178 #define GPIO_OSPEEDR_OSPEEDR13_1 ((uint32_t)0x08000000)
ommpy 0:d383e2dee0f7 1179 #define GPIO_OSPEEDR_OSPEEDR14 ((uint32_t)0x30000000)
ommpy 0:d383e2dee0f7 1180 #define GPIO_OSPEEDR_OSPEEDR14_0 ((uint32_t)0x10000000)
ommpy 0:d383e2dee0f7 1181 #define GPIO_OSPEEDR_OSPEEDR14_1 ((uint32_t)0x20000000)
ommpy 0:d383e2dee0f7 1182 #define GPIO_OSPEEDR_OSPEEDR15 ((uint32_t)0xC0000000)
ommpy 0:d383e2dee0f7 1183 #define GPIO_OSPEEDR_OSPEEDR15_0 ((uint32_t)0x40000000)
ommpy 0:d383e2dee0f7 1184 #define GPIO_OSPEEDR_OSPEEDR15_1 ((uint32_t)0x80000000)
ommpy 0:d383e2dee0f7 1185
ommpy 0:d383e2dee0f7 1186 /* Old Bit definition for GPIO_OSPEEDR register maintained for legacy purpose */
ommpy 0:d383e2dee0f7 1187 #define GPIO_OSPEEDER_OSPEEDR0 GPIO_OSPEEDR_OSPEEDR0
ommpy 0:d383e2dee0f7 1188 #define GPIO_OSPEEDER_OSPEEDR0_0 GPIO_OSPEEDR_OSPEEDR0_0
ommpy 0:d383e2dee0f7 1189 #define GPIO_OSPEEDER_OSPEEDR0_1 GPIO_OSPEEDR_OSPEEDR0_1
ommpy 0:d383e2dee0f7 1190 #define GPIO_OSPEEDER_OSPEEDR1 GPIO_OSPEEDR_OSPEEDR1
ommpy 0:d383e2dee0f7 1191 #define GPIO_OSPEEDER_OSPEEDR1_0 GPIO_OSPEEDR_OSPEEDR1_0
ommpy 0:d383e2dee0f7 1192 #define GPIO_OSPEEDER_OSPEEDR1_1 GPIO_OSPEEDR_OSPEEDR1_1
ommpy 0:d383e2dee0f7 1193 #define GPIO_OSPEEDER_OSPEEDR2 GPIO_OSPEEDR_OSPEEDR2
ommpy 0:d383e2dee0f7 1194 #define GPIO_OSPEEDER_OSPEEDR2_0 GPIO_OSPEEDR_OSPEEDR2_0
ommpy 0:d383e2dee0f7 1195 #define GPIO_OSPEEDER_OSPEEDR2_1 GPIO_OSPEEDR_OSPEEDR2_1
ommpy 0:d383e2dee0f7 1196 #define GPIO_OSPEEDER_OSPEEDR3 GPIO_OSPEEDR_OSPEEDR3
ommpy 0:d383e2dee0f7 1197 #define GPIO_OSPEEDER_OSPEEDR3_0 GPIO_OSPEEDR_OSPEEDR3_0
ommpy 0:d383e2dee0f7 1198 #define GPIO_OSPEEDER_OSPEEDR3_1 GPIO_OSPEEDR_OSPEEDR3_1
ommpy 0:d383e2dee0f7 1199 #define GPIO_OSPEEDER_OSPEEDR4 GPIO_OSPEEDR_OSPEEDR4
ommpy 0:d383e2dee0f7 1200 #define GPIO_OSPEEDER_OSPEEDR4_0 GPIO_OSPEEDR_OSPEEDR4_0
ommpy 0:d383e2dee0f7 1201 #define GPIO_OSPEEDER_OSPEEDR4_1 GPIO_OSPEEDR_OSPEEDR4_1
ommpy 0:d383e2dee0f7 1202 #define GPIO_OSPEEDER_OSPEEDR5 GPIO_OSPEEDR_OSPEEDR5
ommpy 0:d383e2dee0f7 1203 #define GPIO_OSPEEDER_OSPEEDR5_0 GPIO_OSPEEDR_OSPEEDR5_0
ommpy 0:d383e2dee0f7 1204 #define GPIO_OSPEEDER_OSPEEDR5_1 GPIO_OSPEEDR_OSPEEDR5_1
ommpy 0:d383e2dee0f7 1205 #define GPIO_OSPEEDER_OSPEEDR6 GPIO_OSPEEDR_OSPEEDR6
ommpy 0:d383e2dee0f7 1206 #define GPIO_OSPEEDER_OSPEEDR6_0 GPIO_OSPEEDR_OSPEEDR6_0
ommpy 0:d383e2dee0f7 1207 #define GPIO_OSPEEDER_OSPEEDR6_1 GPIO_OSPEEDR_OSPEEDR6_1
ommpy 0:d383e2dee0f7 1208 #define GPIO_OSPEEDER_OSPEEDR7 GPIO_OSPEEDR_OSPEEDR7
ommpy 0:d383e2dee0f7 1209 #define GPIO_OSPEEDER_OSPEEDR7_0 GPIO_OSPEEDR_OSPEEDR7_0
ommpy 0:d383e2dee0f7 1210 #define GPIO_OSPEEDER_OSPEEDR7_1 GPIO_OSPEEDR_OSPEEDR7_1
ommpy 0:d383e2dee0f7 1211 #define GPIO_OSPEEDER_OSPEEDR8 GPIO_OSPEEDR_OSPEEDR8
ommpy 0:d383e2dee0f7 1212 #define GPIO_OSPEEDER_OSPEEDR8_0 GPIO_OSPEEDR_OSPEEDR8_0
ommpy 0:d383e2dee0f7 1213 #define GPIO_OSPEEDER_OSPEEDR8_1 GPIO_OSPEEDR_OSPEEDR8_1
ommpy 0:d383e2dee0f7 1214 #define GPIO_OSPEEDER_OSPEEDR9 GPIO_OSPEEDR_OSPEEDR9
ommpy 0:d383e2dee0f7 1215 #define GPIO_OSPEEDER_OSPEEDR9_0 GPIO_OSPEEDR_OSPEEDR9_0
ommpy 0:d383e2dee0f7 1216 #define GPIO_OSPEEDER_OSPEEDR9_1 GPIO_OSPEEDR_OSPEEDR9_1
ommpy 0:d383e2dee0f7 1217 #define GPIO_OSPEEDER_OSPEEDR10 GPIO_OSPEEDR_OSPEEDR10
ommpy 0:d383e2dee0f7 1218 #define GPIO_OSPEEDER_OSPEEDR10_0 GPIO_OSPEEDR_OSPEEDR10_0
ommpy 0:d383e2dee0f7 1219 #define GPIO_OSPEEDER_OSPEEDR10_1 GPIO_OSPEEDR_OSPEEDR10_1
ommpy 0:d383e2dee0f7 1220 #define GPIO_OSPEEDER_OSPEEDR11 GPIO_OSPEEDR_OSPEEDR11
ommpy 0:d383e2dee0f7 1221 #define GPIO_OSPEEDER_OSPEEDR11_0 GPIO_OSPEEDR_OSPEEDR11_0
ommpy 0:d383e2dee0f7 1222 #define GPIO_OSPEEDER_OSPEEDR11_1 GPIO_OSPEEDR_OSPEEDR11_1
ommpy 0:d383e2dee0f7 1223 #define GPIO_OSPEEDER_OSPEEDR12 GPIO_OSPEEDR_OSPEEDR12
ommpy 0:d383e2dee0f7 1224 #define GPIO_OSPEEDER_OSPEEDR12_0 GPIO_OSPEEDR_OSPEEDR12_0
ommpy 0:d383e2dee0f7 1225 #define GPIO_OSPEEDER_OSPEEDR12_1 GPIO_OSPEEDR_OSPEEDR12_1
ommpy 0:d383e2dee0f7 1226 #define GPIO_OSPEEDER_OSPEEDR13 GPIO_OSPEEDR_OSPEEDR13
ommpy 0:d383e2dee0f7 1227 #define GPIO_OSPEEDER_OSPEEDR13_0 GPIO_OSPEEDR_OSPEEDR13_0
ommpy 0:d383e2dee0f7 1228 #define GPIO_OSPEEDER_OSPEEDR13_1 GPIO_OSPEEDR_OSPEEDR13_1
ommpy 0:d383e2dee0f7 1229 #define GPIO_OSPEEDER_OSPEEDR14 GPIO_OSPEEDR_OSPEEDR14
ommpy 0:d383e2dee0f7 1230 #define GPIO_OSPEEDER_OSPEEDR14_0 GPIO_OSPEEDR_OSPEEDR14_0
ommpy 0:d383e2dee0f7 1231 #define GPIO_OSPEEDER_OSPEEDR14_1 GPIO_OSPEEDR_OSPEEDR14_1
ommpy 0:d383e2dee0f7 1232 #define GPIO_OSPEEDER_OSPEEDR15 GPIO_OSPEEDR_OSPEEDR15
ommpy 0:d383e2dee0f7 1233 #define GPIO_OSPEEDER_OSPEEDR15_0 GPIO_OSPEEDR_OSPEEDR15_0
ommpy 0:d383e2dee0f7 1234 #define GPIO_OSPEEDER_OSPEEDR15_1 GPIO_OSPEEDR_OSPEEDR15_1
ommpy 0:d383e2dee0f7 1235
ommpy 0:d383e2dee0f7 1236 /******************* Bit definition for GPIO_PUPDR register ******************/
ommpy 0:d383e2dee0f7 1237 #define GPIO_PUPDR_PUPDR0 ((uint32_t)0x00000003)
ommpy 0:d383e2dee0f7 1238 #define GPIO_PUPDR_PUPDR0_0 ((uint32_t)0x00000001)
ommpy 0:d383e2dee0f7 1239 #define GPIO_PUPDR_PUPDR0_1 ((uint32_t)0x00000002)
ommpy 0:d383e2dee0f7 1240 #define GPIO_PUPDR_PUPDR1 ((uint32_t)0x0000000C)
ommpy 0:d383e2dee0f7 1241 #define GPIO_PUPDR_PUPDR1_0 ((uint32_t)0x00000004)
ommpy 0:d383e2dee0f7 1242 #define GPIO_PUPDR_PUPDR1_1 ((uint32_t)0x00000008)
ommpy 0:d383e2dee0f7 1243 #define GPIO_PUPDR_PUPDR2 ((uint32_t)0x00000030)
ommpy 0:d383e2dee0f7 1244 #define GPIO_PUPDR_PUPDR2_0 ((uint32_t)0x00000010)
ommpy 0:d383e2dee0f7 1245 #define GPIO_PUPDR_PUPDR2_1 ((uint32_t)0x00000020)
ommpy 0:d383e2dee0f7 1246 #define GPIO_PUPDR_PUPDR3 ((uint32_t)0x000000C0)
ommpy 0:d383e2dee0f7 1247 #define GPIO_PUPDR_PUPDR3_0 ((uint32_t)0x00000040)
ommpy 0:d383e2dee0f7 1248 #define GPIO_PUPDR_PUPDR3_1 ((uint32_t)0x00000080)
ommpy 0:d383e2dee0f7 1249 #define GPIO_PUPDR_PUPDR4 ((uint32_t)0x00000300)
ommpy 0:d383e2dee0f7 1250 #define GPIO_PUPDR_PUPDR4_0 ((uint32_t)0x00000100)
ommpy 0:d383e2dee0f7 1251 #define GPIO_PUPDR_PUPDR4_1 ((uint32_t)0x00000200)
ommpy 0:d383e2dee0f7 1252 #define GPIO_PUPDR_PUPDR5 ((uint32_t)0x00000C00)
ommpy 0:d383e2dee0f7 1253 #define GPIO_PUPDR_PUPDR5_0 ((uint32_t)0x00000400)
ommpy 0:d383e2dee0f7 1254 #define GPIO_PUPDR_PUPDR5_1 ((uint32_t)0x00000800)
ommpy 0:d383e2dee0f7 1255 #define GPIO_PUPDR_PUPDR6 ((uint32_t)0x00003000)
ommpy 0:d383e2dee0f7 1256 #define GPIO_PUPDR_PUPDR6_0 ((uint32_t)0x00001000)
ommpy 0:d383e2dee0f7 1257 #define GPIO_PUPDR_PUPDR6_1 ((uint32_t)0x00002000)
ommpy 0:d383e2dee0f7 1258 #define GPIO_PUPDR_PUPDR7 ((uint32_t)0x0000C000)
ommpy 0:d383e2dee0f7 1259 #define GPIO_PUPDR_PUPDR7_0 ((uint32_t)0x00004000)
ommpy 0:d383e2dee0f7 1260 #define GPIO_PUPDR_PUPDR7_1 ((uint32_t)0x00008000)
ommpy 0:d383e2dee0f7 1261 #define GPIO_PUPDR_PUPDR8 ((uint32_t)0x00030000)
ommpy 0:d383e2dee0f7 1262 #define GPIO_PUPDR_PUPDR8_0 ((uint32_t)0x00010000)
ommpy 0:d383e2dee0f7 1263 #define GPIO_PUPDR_PUPDR8_1 ((uint32_t)0x00020000)
ommpy 0:d383e2dee0f7 1264 #define GPIO_PUPDR_PUPDR9 ((uint32_t)0x000C0000)
ommpy 0:d383e2dee0f7 1265 #define GPIO_PUPDR_PUPDR9_0 ((uint32_t)0x00040000)
ommpy 0:d383e2dee0f7 1266 #define GPIO_PUPDR_PUPDR9_1 ((uint32_t)0x00080000)
ommpy 0:d383e2dee0f7 1267 #define GPIO_PUPDR_PUPDR10 ((uint32_t)0x00300000)
ommpy 0:d383e2dee0f7 1268 #define GPIO_PUPDR_PUPDR10_0 ((uint32_t)0x00100000)
ommpy 0:d383e2dee0f7 1269 #define GPIO_PUPDR_PUPDR10_1 ((uint32_t)0x00200000)
ommpy 0:d383e2dee0f7 1270 #define GPIO_PUPDR_PUPDR11 ((uint32_t)0x00C00000)
ommpy 0:d383e2dee0f7 1271 #define GPIO_PUPDR_PUPDR11_0 ((uint32_t)0x00400000)
ommpy 0:d383e2dee0f7 1272 #define GPIO_PUPDR_PUPDR11_1 ((uint32_t)0x00800000)
ommpy 0:d383e2dee0f7 1273 #define GPIO_PUPDR_PUPDR12 ((uint32_t)0x03000000)
ommpy 0:d383e2dee0f7 1274 #define GPIO_PUPDR_PUPDR12_0 ((uint32_t)0x01000000)
ommpy 0:d383e2dee0f7 1275 #define GPIO_PUPDR_PUPDR12_1 ((uint32_t)0x02000000)
ommpy 0:d383e2dee0f7 1276 #define GPIO_PUPDR_PUPDR13 ((uint32_t)0x0C000000)
ommpy 0:d383e2dee0f7 1277 #define GPIO_PUPDR_PUPDR13_0 ((uint32_t)0x04000000)
ommpy 0:d383e2dee0f7 1278 #define GPIO_PUPDR_PUPDR13_1 ((uint32_t)0x08000000)
ommpy 0:d383e2dee0f7 1279 #define GPIO_PUPDR_PUPDR14 ((uint32_t)0x30000000)
ommpy 0:d383e2dee0f7 1280 #define GPIO_PUPDR_PUPDR14_0 ((uint32_t)0x10000000)
ommpy 0:d383e2dee0f7 1281 #define GPIO_PUPDR_PUPDR14_1 ((uint32_t)0x20000000)
ommpy 0:d383e2dee0f7 1282 #define GPIO_PUPDR_PUPDR15 ((uint32_t)0xC0000000)
ommpy 0:d383e2dee0f7 1283 #define GPIO_PUPDR_PUPDR15_0 ((uint32_t)0x40000000)
ommpy 0:d383e2dee0f7 1284 #define GPIO_PUPDR_PUPDR15_1 ((uint32_t)0x80000000)
ommpy 0:d383e2dee0f7 1285
ommpy 0:d383e2dee0f7 1286 /******************* Bit definition for GPIO_IDR register *******************/
ommpy 0:d383e2dee0f7 1287 #define GPIO_IDR_0 ((uint32_t)0x00000001)
ommpy 0:d383e2dee0f7 1288 #define GPIO_IDR_1 ((uint32_t)0x00000002)
ommpy 0:d383e2dee0f7 1289 #define GPIO_IDR_2 ((uint32_t)0x00000004)
ommpy 0:d383e2dee0f7 1290 #define GPIO_IDR_3 ((uint32_t)0x00000008)
ommpy 0:d383e2dee0f7 1291 #define GPIO_IDR_4 ((uint32_t)0x00000010)
ommpy 0:d383e2dee0f7 1292 #define GPIO_IDR_5 ((uint32_t)0x00000020)
ommpy 0:d383e2dee0f7 1293 #define GPIO_IDR_6 ((uint32_t)0x00000040)
ommpy 0:d383e2dee0f7 1294 #define GPIO_IDR_7 ((uint32_t)0x00000080)
ommpy 0:d383e2dee0f7 1295 #define GPIO_IDR_8 ((uint32_t)0x00000100)
ommpy 0:d383e2dee0f7 1296 #define GPIO_IDR_9 ((uint32_t)0x00000200)
ommpy 0:d383e2dee0f7 1297 #define GPIO_IDR_10 ((uint32_t)0x00000400)
ommpy 0:d383e2dee0f7 1298 #define GPIO_IDR_11 ((uint32_t)0x00000800)
ommpy 0:d383e2dee0f7 1299 #define GPIO_IDR_12 ((uint32_t)0x00001000)
ommpy 0:d383e2dee0f7 1300 #define GPIO_IDR_13 ((uint32_t)0x00002000)
ommpy 0:d383e2dee0f7 1301 #define GPIO_IDR_14 ((uint32_t)0x00004000)
ommpy 0:d383e2dee0f7 1302 #define GPIO_IDR_15 ((uint32_t)0x00008000)
ommpy 0:d383e2dee0f7 1303
ommpy 0:d383e2dee0f7 1304 /****************** Bit definition for GPIO_ODR register ********************/
ommpy 0:d383e2dee0f7 1305 #define GPIO_ODR_0 ((uint32_t)0x00000001)
ommpy 0:d383e2dee0f7 1306 #define GPIO_ODR_1 ((uint32_t)0x00000002)
ommpy 0:d383e2dee0f7 1307 #define GPIO_ODR_2 ((uint32_t)0x00000004)
ommpy 0:d383e2dee0f7 1308 #define GPIO_ODR_3 ((uint32_t)0x00000008)
ommpy 0:d383e2dee0f7 1309 #define GPIO_ODR_4 ((uint32_t)0x00000010)
ommpy 0:d383e2dee0f7 1310 #define GPIO_ODR_5 ((uint32_t)0x00000020)
ommpy 0:d383e2dee0f7 1311 #define GPIO_ODR_6 ((uint32_t)0x00000040)
ommpy 0:d383e2dee0f7 1312 #define GPIO_ODR_7 ((uint32_t)0x00000080)
ommpy 0:d383e2dee0f7 1313 #define GPIO_ODR_8 ((uint32_t)0x00000100)
ommpy 0:d383e2dee0f7 1314 #define GPIO_ODR_9 ((uint32_t)0x00000200)
ommpy 0:d383e2dee0f7 1315 #define GPIO_ODR_10 ((uint32_t)0x00000400)
ommpy 0:d383e2dee0f7 1316 #define GPIO_ODR_11 ((uint32_t)0x00000800)
ommpy 0:d383e2dee0f7 1317 #define GPIO_ODR_12 ((uint32_t)0x00001000)
ommpy 0:d383e2dee0f7 1318 #define GPIO_ODR_13 ((uint32_t)0x00002000)
ommpy 0:d383e2dee0f7 1319 #define GPIO_ODR_14 ((uint32_t)0x00004000)
ommpy 0:d383e2dee0f7 1320 #define GPIO_ODR_15 ((uint32_t)0x00008000)
ommpy 0:d383e2dee0f7 1321
ommpy 0:d383e2dee0f7 1322 /****************** Bit definition for GPIO_BSRR register ********************/
ommpy 0:d383e2dee0f7 1323 #define GPIO_BSRR_BS_0 ((uint32_t)0x00000001)
ommpy 0:d383e2dee0f7 1324 #define GPIO_BSRR_BS_1 ((uint32_t)0x00000002)
ommpy 0:d383e2dee0f7 1325 #define GPIO_BSRR_BS_2 ((uint32_t)0x00000004)
ommpy 0:d383e2dee0f7 1326 #define GPIO_BSRR_BS_3 ((uint32_t)0x00000008)
ommpy 0:d383e2dee0f7 1327 #define GPIO_BSRR_BS_4 ((uint32_t)0x00000010)
ommpy 0:d383e2dee0f7 1328 #define GPIO_BSRR_BS_5 ((uint32_t)0x00000020)
ommpy 0:d383e2dee0f7 1329 #define GPIO_BSRR_BS_6 ((uint32_t)0x00000040)
ommpy 0:d383e2dee0f7 1330 #define GPIO_BSRR_BS_7 ((uint32_t)0x00000080)
ommpy 0:d383e2dee0f7 1331 #define GPIO_BSRR_BS_8 ((uint32_t)0x00000100)
ommpy 0:d383e2dee0f7 1332 #define GPIO_BSRR_BS_9 ((uint32_t)0x00000200)
ommpy 0:d383e2dee0f7 1333 #define GPIO_BSRR_BS_10 ((uint32_t)0x00000400)
ommpy 0:d383e2dee0f7 1334 #define GPIO_BSRR_BS_11 ((uint32_t)0x00000800)
ommpy 0:d383e2dee0f7 1335 #define GPIO_BSRR_BS_12 ((uint32_t)0x00001000)
ommpy 0:d383e2dee0f7 1336 #define GPIO_BSRR_BS_13 ((uint32_t)0x00002000)
ommpy 0:d383e2dee0f7 1337 #define GPIO_BSRR_BS_14 ((uint32_t)0x00004000)
ommpy 0:d383e2dee0f7 1338 #define GPIO_BSRR_BS_15 ((uint32_t)0x00008000)
ommpy 0:d383e2dee0f7 1339 #define GPIO_BSRR_BR_0 ((uint32_t)0x00010000)
ommpy 0:d383e2dee0f7 1340 #define GPIO_BSRR_BR_1 ((uint32_t)0x00020000)
ommpy 0:d383e2dee0f7 1341 #define GPIO_BSRR_BR_2 ((uint32_t)0x00040000)
ommpy 0:d383e2dee0f7 1342 #define GPIO_BSRR_BR_3 ((uint32_t)0x00080000)
ommpy 0:d383e2dee0f7 1343 #define GPIO_BSRR_BR_4 ((uint32_t)0x00100000)
ommpy 0:d383e2dee0f7 1344 #define GPIO_BSRR_BR_5 ((uint32_t)0x00200000)
ommpy 0:d383e2dee0f7 1345 #define GPIO_BSRR_BR_6 ((uint32_t)0x00400000)
ommpy 0:d383e2dee0f7 1346 #define GPIO_BSRR_BR_7 ((uint32_t)0x00800000)
ommpy 0:d383e2dee0f7 1347 #define GPIO_BSRR_BR_8 ((uint32_t)0x01000000)
ommpy 0:d383e2dee0f7 1348 #define GPIO_BSRR_BR_9 ((uint32_t)0x02000000)
ommpy 0:d383e2dee0f7 1349 #define GPIO_BSRR_BR_10 ((uint32_t)0x04000000)
ommpy 0:d383e2dee0f7 1350 #define GPIO_BSRR_BR_11 ((uint32_t)0x08000000)
ommpy 0:d383e2dee0f7 1351 #define GPIO_BSRR_BR_12 ((uint32_t)0x10000000)
ommpy 0:d383e2dee0f7 1352 #define GPIO_BSRR_BR_13 ((uint32_t)0x20000000)
ommpy 0:d383e2dee0f7 1353 #define GPIO_BSRR_BR_14 ((uint32_t)0x40000000)
ommpy 0:d383e2dee0f7 1354 #define GPIO_BSRR_BR_15 ((uint32_t)0x80000000)
ommpy 0:d383e2dee0f7 1355
ommpy 0:d383e2dee0f7 1356 /****************** Bit definition for GPIO_LCKR register ********************/
ommpy 0:d383e2dee0f7 1357 #define GPIO_LCKR_LCK0 ((uint32_t)0x00000001)
ommpy 0:d383e2dee0f7 1358 #define GPIO_LCKR_LCK1 ((uint32_t)0x00000002)
ommpy 0:d383e2dee0f7 1359 #define GPIO_LCKR_LCK2 ((uint32_t)0x00000004)
ommpy 0:d383e2dee0f7 1360 #define GPIO_LCKR_LCK3 ((uint32_t)0x00000008)
ommpy 0:d383e2dee0f7 1361 #define GPIO_LCKR_LCK4 ((uint32_t)0x00000010)
ommpy 0:d383e2dee0f7 1362 #define GPIO_LCKR_LCK5 ((uint32_t)0x00000020)
ommpy 0:d383e2dee0f7 1363 #define GPIO_LCKR_LCK6 ((uint32_t)0x00000040)
ommpy 0:d383e2dee0f7 1364 #define GPIO_LCKR_LCK7 ((uint32_t)0x00000080)
ommpy 0:d383e2dee0f7 1365 #define GPIO_LCKR_LCK8 ((uint32_t)0x00000100)
ommpy 0:d383e2dee0f7 1366 #define GPIO_LCKR_LCK9 ((uint32_t)0x00000200)
ommpy 0:d383e2dee0f7 1367 #define GPIO_LCKR_LCK10 ((uint32_t)0x00000400)
ommpy 0:d383e2dee0f7 1368 #define GPIO_LCKR_LCK11 ((uint32_t)0x00000800)
ommpy 0:d383e2dee0f7 1369 #define GPIO_LCKR_LCK12 ((uint32_t)0x00001000)
ommpy 0:d383e2dee0f7 1370 #define GPIO_LCKR_LCK13 ((uint32_t)0x00002000)
ommpy 0:d383e2dee0f7 1371 #define GPIO_LCKR_LCK14 ((uint32_t)0x00004000)
ommpy 0:d383e2dee0f7 1372 #define GPIO_LCKR_LCK15 ((uint32_t)0x00008000)
ommpy 0:d383e2dee0f7 1373 #define GPIO_LCKR_LCKK ((uint32_t)0x00010000)
ommpy 0:d383e2dee0f7 1374
ommpy 0:d383e2dee0f7 1375 /****************** Bit definition for GPIO_AFRL register ********************/
ommpy 0:d383e2dee0f7 1376 #define GPIO_AFRL_AFRL0 ((uint32_t)0x0000000F)
ommpy 0:d383e2dee0f7 1377 #define GPIO_AFRL_AFRL1 ((uint32_t)0x000000F0)
ommpy 0:d383e2dee0f7 1378 #define GPIO_AFRL_AFRL2 ((uint32_t)0x00000F00)
ommpy 0:d383e2dee0f7 1379 #define GPIO_AFRL_AFRL3 ((uint32_t)0x0000F000)
ommpy 0:d383e2dee0f7 1380 #define GPIO_AFRL_AFRL4 ((uint32_t)0x000F0000)
ommpy 0:d383e2dee0f7 1381 #define GPIO_AFRL_AFRL5 ((uint32_t)0x00F00000)
ommpy 0:d383e2dee0f7 1382 #define GPIO_AFRL_AFRL6 ((uint32_t)0x0F000000)
ommpy 0:d383e2dee0f7 1383 #define GPIO_AFRL_AFRL7 ((uint32_t)0xF0000000)
ommpy 0:d383e2dee0f7 1384
ommpy 0:d383e2dee0f7 1385 /****************** Bit definition for GPIO_AFRH register ********************/
ommpy 0:d383e2dee0f7 1386 #define GPIO_AFRH_AFRH0 ((uint32_t)0x0000000F)
ommpy 0:d383e2dee0f7 1387 #define GPIO_AFRH_AFRH1 ((uint32_t)0x000000F0)
ommpy 0:d383e2dee0f7 1388 #define GPIO_AFRH_AFRH2 ((uint32_t)0x00000F00)
ommpy 0:d383e2dee0f7 1389 #define GPIO_AFRH_AFRH3 ((uint32_t)0x0000F000)
ommpy 0:d383e2dee0f7 1390 #define GPIO_AFRH_AFRH4 ((uint32_t)0x000F0000)
ommpy 0:d383e2dee0f7 1391 #define GPIO_AFRH_AFRH5 ((uint32_t)0x00F00000)
ommpy 0:d383e2dee0f7 1392 #define GPIO_AFRH_AFRH6 ((uint32_t)0x0F000000)
ommpy 0:d383e2dee0f7 1393 #define GPIO_AFRH_AFRH7 ((uint32_t)0xF0000000)
ommpy 0:d383e2dee0f7 1394
ommpy 0:d383e2dee0f7 1395 /****************** Bit definition for GPIO_BRR register *********************/
ommpy 0:d383e2dee0f7 1396 #define GPIO_BRR_BR_0 ((uint32_t)0x00000001)
ommpy 0:d383e2dee0f7 1397 #define GPIO_BRR_BR_1 ((uint32_t)0x00000002)
ommpy 0:d383e2dee0f7 1398 #define GPIO_BRR_BR_2 ((uint32_t)0x00000004)
ommpy 0:d383e2dee0f7 1399 #define GPIO_BRR_BR_3 ((uint32_t)0x00000008)
ommpy 0:d383e2dee0f7 1400 #define GPIO_BRR_BR_4 ((uint32_t)0x00000010)
ommpy 0:d383e2dee0f7 1401 #define GPIO_BRR_BR_5 ((uint32_t)0x00000020)
ommpy 0:d383e2dee0f7 1402 #define GPIO_BRR_BR_6 ((uint32_t)0x00000040)
ommpy 0:d383e2dee0f7 1403 #define GPIO_BRR_BR_7 ((uint32_t)0x00000080)
ommpy 0:d383e2dee0f7 1404 #define GPIO_BRR_BR_8 ((uint32_t)0x00000100)
ommpy 0:d383e2dee0f7 1405 #define GPIO_BRR_BR_9 ((uint32_t)0x00000200)
ommpy 0:d383e2dee0f7 1406 #define GPIO_BRR_BR_10 ((uint32_t)0x00000400)
ommpy 0:d383e2dee0f7 1407 #define GPIO_BRR_BR_11 ((uint32_t)0x00000800)
ommpy 0:d383e2dee0f7 1408 #define GPIO_BRR_BR_12 ((uint32_t)0x00001000)
ommpy 0:d383e2dee0f7 1409 #define GPIO_BRR_BR_13 ((uint32_t)0x00002000)
ommpy 0:d383e2dee0f7 1410 #define GPIO_BRR_BR_14 ((uint32_t)0x00004000)
ommpy 0:d383e2dee0f7 1411 #define GPIO_BRR_BR_15 ((uint32_t)0x00008000)
ommpy 0:d383e2dee0f7 1412
ommpy 0:d383e2dee0f7 1413 /******************************************************************************/
ommpy 0:d383e2dee0f7 1414 /* */
ommpy 0:d383e2dee0f7 1415 /* Inter-integrated Circuit Interface (I2C) */
ommpy 0:d383e2dee0f7 1416 /* */
ommpy 0:d383e2dee0f7 1417 /******************************************************************************/
ommpy 0:d383e2dee0f7 1418
ommpy 0:d383e2dee0f7 1419 /******************* Bit definition for I2C_CR1 register *******************/
ommpy 0:d383e2dee0f7 1420 #define I2C_CR1_PE ((uint32_t)0x00000001) /*!< Peripheral enable */
ommpy 0:d383e2dee0f7 1421 #define I2C_CR1_TXIE ((uint32_t)0x00000002) /*!< TX interrupt enable */
ommpy 0:d383e2dee0f7 1422 #define I2C_CR1_RXIE ((uint32_t)0x00000004) /*!< RX interrupt enable */
ommpy 0:d383e2dee0f7 1423 #define I2C_CR1_ADDRIE ((uint32_t)0x00000008) /*!< Address match interrupt enable */
ommpy 0:d383e2dee0f7 1424 #define I2C_CR1_NACKIE ((uint32_t)0x00000010) /*!< NACK received interrupt enable */
ommpy 0:d383e2dee0f7 1425 #define I2C_CR1_STOPIE ((uint32_t)0x00000020) /*!< STOP detection interrupt enable */
ommpy 0:d383e2dee0f7 1426 #define I2C_CR1_TCIE ((uint32_t)0x00000040) /*!< Transfer complete interrupt enable */
ommpy 0:d383e2dee0f7 1427 #define I2C_CR1_ERRIE ((uint32_t)0x00000080) /*!< Errors interrupt enable */
ommpy 0:d383e2dee0f7 1428 #define I2C_CR1_DFN ((uint32_t)0x00000F00) /*!< Digital noise filter */
ommpy 0:d383e2dee0f7 1429 #define I2C_CR1_ANFOFF ((uint32_t)0x00001000) /*!< Analog noise filter OFF */
ommpy 0:d383e2dee0f7 1430 #define I2C_CR1_SWRST ((uint32_t)0x00002000) /*!< Software reset */
ommpy 0:d383e2dee0f7 1431 #define I2C_CR1_TXDMAEN ((uint32_t)0x00004000) /*!< DMA transmission requests enable */
ommpy 0:d383e2dee0f7 1432 #define I2C_CR1_RXDMAEN ((uint32_t)0x00008000) /*!< DMA reception requests enable */
ommpy 0:d383e2dee0f7 1433 #define I2C_CR1_SBC ((uint32_t)0x00010000) /*!< Slave byte control */
ommpy 0:d383e2dee0f7 1434 #define I2C_CR1_NOSTRETCH ((uint32_t)0x00020000) /*!< Clock stretching disable */
ommpy 0:d383e2dee0f7 1435 #define I2C_CR1_WUPEN ((uint32_t)0x00040000) /*!< Wakeup from STOP enable */
ommpy 0:d383e2dee0f7 1436 #define I2C_CR1_GCEN ((uint32_t)0x00080000) /*!< General call enable */
ommpy 0:d383e2dee0f7 1437 #define I2C_CR1_SMBHEN ((uint32_t)0x00100000) /*!< SMBus host address enable */
ommpy 0:d383e2dee0f7 1438 #define I2C_CR1_SMBDEN ((uint32_t)0x00200000) /*!< SMBus device default address enable */
ommpy 0:d383e2dee0f7 1439 #define I2C_CR1_ALERTEN ((uint32_t)0x00400000) /*!< SMBus alert enable */
ommpy 0:d383e2dee0f7 1440 #define I2C_CR1_PECEN ((uint32_t)0x00800000) /*!< PEC enable */
ommpy 0:d383e2dee0f7 1441
ommpy 0:d383e2dee0f7 1442 /****************** Bit definition for I2C_CR2 register ********************/
ommpy 0:d383e2dee0f7 1443 #define I2C_CR2_SADD ((uint32_t)0x000003FF) /*!< Slave address (master mode) */
ommpy 0:d383e2dee0f7 1444 #define I2C_CR2_RD_WRN ((uint32_t)0x00000400) /*!< Transfer direction (master mode) */
ommpy 0:d383e2dee0f7 1445 #define I2C_CR2_ADD10 ((uint32_t)0x00000800) /*!< 10-bit addressing mode (master mode) */
ommpy 0:d383e2dee0f7 1446 #define I2C_CR2_HEAD10R ((uint32_t)0x00001000) /*!< 10-bit address header only read direction (master mode) */
ommpy 0:d383e2dee0f7 1447 #define I2C_CR2_START ((uint32_t)0x00002000) /*!< START generation */
ommpy 0:d383e2dee0f7 1448 #define I2C_CR2_STOP ((uint32_t)0x00004000) /*!< STOP generation (master mode) */
ommpy 0:d383e2dee0f7 1449 #define I2C_CR2_NACK ((uint32_t)0x00008000) /*!< NACK generation (slave mode) */
ommpy 0:d383e2dee0f7 1450 #define I2C_CR2_NBYTES ((uint32_t)0x00FF0000) /*!< Number of bytes */
ommpy 0:d383e2dee0f7 1451 #define I2C_CR2_RELOAD ((uint32_t)0x01000000) /*!< NBYTES reload mode */
ommpy 0:d383e2dee0f7 1452 #define I2C_CR2_AUTOEND ((uint32_t)0x02000000) /*!< Automatic end mode (master mode) */
ommpy 0:d383e2dee0f7 1453 #define I2C_CR2_PECBYTE ((uint32_t)0x04000000) /*!< Packet error checking byte */
ommpy 0:d383e2dee0f7 1454
ommpy 0:d383e2dee0f7 1455 /******************* Bit definition for I2C_OAR1 register ******************/
ommpy 0:d383e2dee0f7 1456 #define I2C_OAR1_OA1 ((uint32_t)0x000003FF) /*!< Interface own address 1 */
ommpy 0:d383e2dee0f7 1457 #define I2C_OAR1_OA1MODE ((uint32_t)0x00000400) /*!< Own address 1 10-bit mode */
ommpy 0:d383e2dee0f7 1458 #define I2C_OAR1_OA1EN ((uint32_t)0x00008000) /*!< Own address 1 enable */
ommpy 0:d383e2dee0f7 1459
ommpy 0:d383e2dee0f7 1460 /******************* Bit definition for I2C_OAR2 register ******************/
ommpy 0:d383e2dee0f7 1461 #define I2C_OAR2_OA2 ((uint32_t)0x000000FE) /*!< Interface own address 2 */
ommpy 0:d383e2dee0f7 1462 #define I2C_OAR2_OA2MSK ((uint32_t)0x00000700) /*!< Own address 2 masks */
ommpy 0:d383e2dee0f7 1463 #define I2C_OAR2_OA2EN ((uint32_t)0x00008000) /*!< Own address 2 enable */
ommpy 0:d383e2dee0f7 1464
ommpy 0:d383e2dee0f7 1465 /******************* Bit definition for I2C_TIMINGR register ****************/
ommpy 0:d383e2dee0f7 1466 #define I2C_TIMINGR_SCLL ((uint32_t)0x000000FF) /*!< SCL low period (master mode) */
ommpy 0:d383e2dee0f7 1467 #define I2C_TIMINGR_SCLH ((uint32_t)0x0000FF00) /*!< SCL high period (master mode) */
ommpy 0:d383e2dee0f7 1468 #define I2C_TIMINGR_SDADEL ((uint32_t)0x000F0000) /*!< Data hold time */
ommpy 0:d383e2dee0f7 1469 #define I2C_TIMINGR_SCLDEL ((uint32_t)0x00F00000) /*!< Data setup time */
ommpy 0:d383e2dee0f7 1470 #define I2C_TIMINGR_PRESC ((uint32_t)0xF0000000) /*!< Timings prescaler */
ommpy 0:d383e2dee0f7 1471
ommpy 0:d383e2dee0f7 1472 /******************* Bit definition for I2C_TIMEOUTR register ****************/
ommpy 0:d383e2dee0f7 1473 #define I2C_TIMEOUTR_TIMEOUTA ((uint32_t)0x00000FFF) /*!< Bus timeout A */
ommpy 0:d383e2dee0f7 1474 #define I2C_TIMEOUTR_TIDLE ((uint32_t)0x00001000) /*!< Idle clock timeout detection */
ommpy 0:d383e2dee0f7 1475 #define I2C_TIMEOUTR_TIMOUTEN ((uint32_t)0x00008000) /*!< Clock timeout enable */
ommpy 0:d383e2dee0f7 1476 #define I2C_TIMEOUTR_TIMEOUTB ((uint32_t)0x0FFF0000) /*!< Bus timeout B*/
ommpy 0:d383e2dee0f7 1477 #define I2C_TIMEOUTR_TEXTEN ((uint32_t)0x80000000) /*!< Extended clock timeout enable */
ommpy 0:d383e2dee0f7 1478
ommpy 0:d383e2dee0f7 1479 /****************** Bit definition for I2C_ISR register ********************/
ommpy 0:d383e2dee0f7 1480 #define I2C_ISR_TXE ((uint32_t)0x00000001) /*!< Transmit data register empty */
ommpy 0:d383e2dee0f7 1481 #define I2C_ISR_TXIS ((uint32_t)0x00000002) /*!< Transmit interrupt status */
ommpy 0:d383e2dee0f7 1482 #define I2C_ISR_RXNE ((uint32_t)0x00000004) /*!< Receive data register not empty */
ommpy 0:d383e2dee0f7 1483 #define I2C_ISR_ADDR ((uint32_t)0x00000008) /*!< Address matched (slave mode)*/
ommpy 0:d383e2dee0f7 1484 #define I2C_ISR_NACKF ((uint32_t)0x00000010) /*!< NACK received flag */
ommpy 0:d383e2dee0f7 1485 #define I2C_ISR_STOPF ((uint32_t)0x00000020) /*!< STOP detection flag */
ommpy 0:d383e2dee0f7 1486 #define I2C_ISR_TC ((uint32_t)0x00000040) /*!< Transfer complete (master mode) */
ommpy 0:d383e2dee0f7 1487 #define I2C_ISR_TCR ((uint32_t)0x00000080) /*!< Transfer complete reload */
ommpy 0:d383e2dee0f7 1488 #define I2C_ISR_BERR ((uint32_t)0x00000100) /*!< Bus error */
ommpy 0:d383e2dee0f7 1489 #define I2C_ISR_ARLO ((uint32_t)0x00000200) /*!< Arbitration lost */
ommpy 0:d383e2dee0f7 1490 #define I2C_ISR_OVR ((uint32_t)0x00000400) /*!< Overrun/Underrun */
ommpy 0:d383e2dee0f7 1491 #define I2C_ISR_PECERR ((uint32_t)0x00000800) /*!< PEC error in reception */
ommpy 0:d383e2dee0f7 1492 #define I2C_ISR_TIMEOUT ((uint32_t)0x00001000) /*!< Timeout or Tlow detection flag */
ommpy 0:d383e2dee0f7 1493 #define I2C_ISR_ALERT ((uint32_t)0x00002000) /*!< SMBus alert */
ommpy 0:d383e2dee0f7 1494 #define I2C_ISR_BUSY ((uint32_t)0x00008000) /*!< Bus busy */
ommpy 0:d383e2dee0f7 1495 #define I2C_ISR_DIR ((uint32_t)0x00010000) /*!< Transfer direction (slave mode) */
ommpy 0:d383e2dee0f7 1496 #define I2C_ISR_ADDCODE ((uint32_t)0x00FE0000) /*!< Address match code (slave mode) */
ommpy 0:d383e2dee0f7 1497
ommpy 0:d383e2dee0f7 1498 /****************** Bit definition for I2C_ICR register ********************/
ommpy 0:d383e2dee0f7 1499 #define I2C_ICR_ADDRCF ((uint32_t)0x00000008) /*!< Address matched clear flag */
ommpy 0:d383e2dee0f7 1500 #define I2C_ICR_NACKCF ((uint32_t)0x00000010) /*!< NACK clear flag */
ommpy 0:d383e2dee0f7 1501 #define I2C_ICR_STOPCF ((uint32_t)0x00000020) /*!< STOP detection clear flag */
ommpy 0:d383e2dee0f7 1502 #define I2C_ICR_BERRCF ((uint32_t)0x00000100) /*!< Bus error clear flag */
ommpy 0:d383e2dee0f7 1503 #define I2C_ICR_ARLOCF ((uint32_t)0x00000200) /*!< Arbitration lost clear flag */
ommpy 0:d383e2dee0f7 1504 #define I2C_ICR_OVRCF ((uint32_t)0x00000400) /*!< Overrun/Underrun clear flag */
ommpy 0:d383e2dee0f7 1505 #define I2C_ICR_PECCF ((uint32_t)0x00000800) /*!< PAC error clear flag */
ommpy 0:d383e2dee0f7 1506 #define I2C_ICR_TIMOUTCF ((uint32_t)0x00001000) /*!< Timeout clear flag */
ommpy 0:d383e2dee0f7 1507 #define I2C_ICR_ALERTCF ((uint32_t)0x00002000) /*!< Alert clear flag */
ommpy 0:d383e2dee0f7 1508
ommpy 0:d383e2dee0f7 1509 /****************** Bit definition for I2C_PECR register *******************/
ommpy 0:d383e2dee0f7 1510 #define I2C_PECR_PEC ((uint32_t)0x000000FF) /*!< PEC register */
ommpy 0:d383e2dee0f7 1511
ommpy 0:d383e2dee0f7 1512 /****************** Bit definition for I2C_RXDR register *********************/
ommpy 0:d383e2dee0f7 1513 #define I2C_RXDR_RXDATA ((uint32_t)0x000000FF) /*!< 8-bit receive data */
ommpy 0:d383e2dee0f7 1514
ommpy 0:d383e2dee0f7 1515 /****************** Bit definition for I2C_TXDR register *******************/
ommpy 0:d383e2dee0f7 1516 #define I2C_TXDR_TXDATA ((uint32_t)0x000000FF) /*!< 8-bit transmit data */
ommpy 0:d383e2dee0f7 1517
ommpy 0:d383e2dee0f7 1518 /*****************************************************************************/
ommpy 0:d383e2dee0f7 1519 /* */
ommpy 0:d383e2dee0f7 1520 /* Independent WATCHDOG (IWDG) */
ommpy 0:d383e2dee0f7 1521 /* */
ommpy 0:d383e2dee0f7 1522 /*****************************************************************************/
ommpy 0:d383e2dee0f7 1523 /******************* Bit definition for IWDG_KR register *******************/
ommpy 0:d383e2dee0f7 1524 #define IWDG_KR_KEY ((uint32_t)0xFFFF) /*!< Key value (write only, read 0000h) */
ommpy 0:d383e2dee0f7 1525
ommpy 0:d383e2dee0f7 1526 /******************* Bit definition for IWDG_PR register *******************/
ommpy 0:d383e2dee0f7 1527 #define IWDG_PR_PR ((uint32_t)0x07) /*!< PR[2:0] (Prescaler divider) */
ommpy 0:d383e2dee0f7 1528 #define IWDG_PR_PR_0 ((uint32_t)0x01) /*!< Bit 0 */
ommpy 0:d383e2dee0f7 1529 #define IWDG_PR_PR_1 ((uint32_t)0x02) /*!< Bit 1 */
ommpy 0:d383e2dee0f7 1530 #define IWDG_PR_PR_2 ((uint32_t)0x04) /*!< Bit 2 */
ommpy 0:d383e2dee0f7 1531
ommpy 0:d383e2dee0f7 1532 /******************* Bit definition for IWDG_RLR register ******************/
ommpy 0:d383e2dee0f7 1533 #define IWDG_RLR_RL ((uint32_t)0x0FFF) /*!< Watchdog counter reload value */
ommpy 0:d383e2dee0f7 1534
ommpy 0:d383e2dee0f7 1535 /******************* Bit definition for IWDG_SR register *******************/
ommpy 0:d383e2dee0f7 1536 #define IWDG_SR_PVU ((uint32_t)0x01) /*!< Watchdog prescaler value update */
ommpy 0:d383e2dee0f7 1537 #define IWDG_SR_RVU ((uint32_t)0x02) /*!< Watchdog counter reload value update */
ommpy 0:d383e2dee0f7 1538 #define IWDG_SR_WVU ((uint32_t)0x04) /*!< Watchdog counter window value update */
ommpy 0:d383e2dee0f7 1539
ommpy 0:d383e2dee0f7 1540 /******************* Bit definition for IWDG_KR register *******************/
ommpy 0:d383e2dee0f7 1541 #define IWDG_WINR_WIN ((uint32_t)0x0FFF) /*!< Watchdog counter window value */
ommpy 0:d383e2dee0f7 1542
ommpy 0:d383e2dee0f7 1543 /*****************************************************************************/
ommpy 0:d383e2dee0f7 1544 /* */
ommpy 0:d383e2dee0f7 1545 /* Power Control (PWR) */
ommpy 0:d383e2dee0f7 1546 /* */
ommpy 0:d383e2dee0f7 1547 /*****************************************************************************/
ommpy 0:d383e2dee0f7 1548
ommpy 0:d383e2dee0f7 1549 /******************** Bit definition for PWR_CR register *******************/
ommpy 0:d383e2dee0f7 1550 #define PWR_CR_LPDS ((uint32_t)0x00000001) /*!< Low-power Deepsleep */
ommpy 0:d383e2dee0f7 1551 #define PWR_CR_PDDS ((uint32_t)0x00000002) /*!< Power Down Deepsleep */
ommpy 0:d383e2dee0f7 1552 #define PWR_CR_CWUF ((uint32_t)0x00000004) /*!< Clear Wakeup Flag */
ommpy 0:d383e2dee0f7 1553 #define PWR_CR_CSBF ((uint32_t)0x00000008) /*!< Clear Standby Flag */
ommpy 0:d383e2dee0f7 1554 #define PWR_CR_DBP ((uint32_t)0x00000100) /*!< Disable Backup Domain write protection */
ommpy 0:d383e2dee0f7 1555
ommpy 0:d383e2dee0f7 1556 /******************* Bit definition for PWR_CSR register *******************/
ommpy 0:d383e2dee0f7 1557 #define PWR_CSR_WUF ((uint32_t)0x00000001) /*!< Wakeup Flag */
ommpy 0:d383e2dee0f7 1558 #define PWR_CSR_SBF ((uint32_t)0x00000002) /*!< Standby Flag */
ommpy 0:d383e2dee0f7 1559
ommpy 0:d383e2dee0f7 1560 #define PWR_CSR_EWUP1 ((uint32_t)0x00000100) /*!< Enable WKUP pin 1 */
ommpy 0:d383e2dee0f7 1561 #define PWR_CSR_EWUP2 ((uint32_t)0x00000200) /*!< Enable WKUP pin 2 */
ommpy 0:d383e2dee0f7 1562
ommpy 0:d383e2dee0f7 1563 /*****************************************************************************/
ommpy 0:d383e2dee0f7 1564 /* */
ommpy 0:d383e2dee0f7 1565 /* Reset and Clock Control */
ommpy 0:d383e2dee0f7 1566 /* */
ommpy 0:d383e2dee0f7 1567 /*****************************************************************************/
ommpy 0:d383e2dee0f7 1568
ommpy 0:d383e2dee0f7 1569 /******************** Bit definition for RCC_CR register *******************/
ommpy 0:d383e2dee0f7 1570 #define RCC_CR_HSION ((uint32_t)0x00000001) /*!< Internal High Speed clock enable */
ommpy 0:d383e2dee0f7 1571 #define RCC_CR_HSIRDY ((uint32_t)0x00000002) /*!< Internal High Speed clock ready flag */
ommpy 0:d383e2dee0f7 1572
ommpy 0:d383e2dee0f7 1573 #define RCC_CR_HSITRIM ((uint32_t)0x000000F8) /*!< Internal High Speed clock trimming */
ommpy 0:d383e2dee0f7 1574 #define RCC_CR_HSITRIM_0 ((uint32_t)0x00000008) /*!<Bit 0 */
ommpy 0:d383e2dee0f7 1575 #define RCC_CR_HSITRIM_1 ((uint32_t)0x00000010) /*!<Bit 1 */
ommpy 0:d383e2dee0f7 1576 #define RCC_CR_HSITRIM_2 ((uint32_t)0x00000020) /*!<Bit 2 */
ommpy 0:d383e2dee0f7 1577 #define RCC_CR_HSITRIM_3 ((uint32_t)0x00000040) /*!<Bit 3 */
ommpy 0:d383e2dee0f7 1578 #define RCC_CR_HSITRIM_4 ((uint32_t)0x00000080) /*!<Bit 4 */
ommpy 0:d383e2dee0f7 1579
ommpy 0:d383e2dee0f7 1580 #define RCC_CR_HSICAL ((uint32_t)0x0000FF00) /*!< Internal High Speed clock Calibration */
ommpy 0:d383e2dee0f7 1581 #define RCC_CR_HSICAL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
ommpy 0:d383e2dee0f7 1582 #define RCC_CR_HSICAL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
ommpy 0:d383e2dee0f7 1583 #define RCC_CR_HSICAL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
ommpy 0:d383e2dee0f7 1584 #define RCC_CR_HSICAL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
ommpy 0:d383e2dee0f7 1585 #define RCC_CR_HSICAL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
ommpy 0:d383e2dee0f7 1586 #define RCC_CR_HSICAL_5 ((uint32_t)0x00002000) /*!<Bit 5 */
ommpy 0:d383e2dee0f7 1587 #define RCC_CR_HSICAL_6 ((uint32_t)0x00004000) /*!<Bit 6 */
ommpy 0:d383e2dee0f7 1588 #define RCC_CR_HSICAL_7 ((uint32_t)0x00008000) /*!<Bit 7 */
ommpy 0:d383e2dee0f7 1589
ommpy 0:d383e2dee0f7 1590 #define RCC_CR_HSEON ((uint32_t)0x00010000) /*!< External High Speed clock enable */
ommpy 0:d383e2dee0f7 1591 #define RCC_CR_HSERDY ((uint32_t)0x00020000) /*!< External High Speed clock ready flag */
ommpy 0:d383e2dee0f7 1592 #define RCC_CR_HSEBYP ((uint32_t)0x00040000) /*!< External High Speed clock Bypass */
ommpy 0:d383e2dee0f7 1593 #define RCC_CR_CSSON ((uint32_t)0x00080000) /*!< Clock Security System enable */
ommpy 0:d383e2dee0f7 1594 #define RCC_CR_PLLON ((uint32_t)0x01000000) /*!< PLL enable */
ommpy 0:d383e2dee0f7 1595 #define RCC_CR_PLLRDY ((uint32_t)0x02000000) /*!< PLL clock ready flag */
ommpy 0:d383e2dee0f7 1596
ommpy 0:d383e2dee0f7 1597 /******************** Bit definition for RCC_CFGR register *****************/
ommpy 0:d383e2dee0f7 1598 /*!< SW configuration */
ommpy 0:d383e2dee0f7 1599 #define RCC_CFGR_SW ((uint32_t)0x00000003) /*!< SW[1:0] bits (System clock Switch) */
ommpy 0:d383e2dee0f7 1600 #define RCC_CFGR_SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
ommpy 0:d383e2dee0f7 1601 #define RCC_CFGR_SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
ommpy 0:d383e2dee0f7 1602
ommpy 0:d383e2dee0f7 1603 #define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /*!< HSI selected as system clock */
ommpy 0:d383e2dee0f7 1604 #define RCC_CFGR_SW_HSE ((uint32_t)0x00000001) /*!< HSE selected as system clock */
ommpy 0:d383e2dee0f7 1605 #define RCC_CFGR_SW_PLL ((uint32_t)0x00000002) /*!< PLL selected as system clock */
ommpy 0:d383e2dee0f7 1606
ommpy 0:d383e2dee0f7 1607 /*!< SWS configuration */
ommpy 0:d383e2dee0f7 1608 #define RCC_CFGR_SWS ((uint32_t)0x0000000C) /*!< SWS[1:0] bits (System Clock Switch Status) */
ommpy 0:d383e2dee0f7 1609 #define RCC_CFGR_SWS_0 ((uint32_t)0x00000004) /*!< Bit 0 */
ommpy 0:d383e2dee0f7 1610 #define RCC_CFGR_SWS_1 ((uint32_t)0x00000008) /*!< Bit 1 */
ommpy 0:d383e2dee0f7 1611
ommpy 0:d383e2dee0f7 1612 #define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /*!< HSI oscillator used as system clock */
ommpy 0:d383e2dee0f7 1613 #define RCC_CFGR_SWS_HSE ((uint32_t)0x00000004) /*!< HSE oscillator used as system clock */
ommpy 0:d383e2dee0f7 1614 #define RCC_CFGR_SWS_PLL ((uint32_t)0x00000008) /*!< PLL used as system clock */
ommpy 0:d383e2dee0f7 1615
ommpy 0:d383e2dee0f7 1616 /*!< HPRE configuration */
ommpy 0:d383e2dee0f7 1617 #define RCC_CFGR_HPRE ((uint32_t)0x000000F0) /*!< HPRE[3:0] bits (AHB prescaler) */
ommpy 0:d383e2dee0f7 1618 #define RCC_CFGR_HPRE_0 ((uint32_t)0x00000010) /*!< Bit 0 */
ommpy 0:d383e2dee0f7 1619 #define RCC_CFGR_HPRE_1 ((uint32_t)0x00000020) /*!< Bit 1 */
ommpy 0:d383e2dee0f7 1620 #define RCC_CFGR_HPRE_2 ((uint32_t)0x00000040) /*!< Bit 2 */
ommpy 0:d383e2dee0f7 1621 #define RCC_CFGR_HPRE_3 ((uint32_t)0x00000080) /*!< Bit 3 */
ommpy 0:d383e2dee0f7 1622
ommpy 0:d383e2dee0f7 1623 #define RCC_CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< SYSCLK not divided */
ommpy 0:d383e2dee0f7 1624 #define RCC_CFGR_HPRE_DIV2 ((uint32_t)0x00000080) /*!< SYSCLK divided by 2 */
ommpy 0:d383e2dee0f7 1625 #define RCC_CFGR_HPRE_DIV4 ((uint32_t)0x00000090) /*!< SYSCLK divided by 4 */
ommpy 0:d383e2dee0f7 1626 #define RCC_CFGR_HPRE_DIV8 ((uint32_t)0x000000A0) /*!< SYSCLK divided by 8 */
ommpy 0:d383e2dee0f7 1627 #define RCC_CFGR_HPRE_DIV16 ((uint32_t)0x000000B0) /*!< SYSCLK divided by 16 */
ommpy 0:d383e2dee0f7 1628 #define RCC_CFGR_HPRE_DIV64 ((uint32_t)0x000000C0) /*!< SYSCLK divided by 64 */
ommpy 0:d383e2dee0f7 1629 #define RCC_CFGR_HPRE_DIV128 ((uint32_t)0x000000D0) /*!< SYSCLK divided by 128 */
ommpy 0:d383e2dee0f7 1630 #define RCC_CFGR_HPRE_DIV256 ((uint32_t)0x000000E0) /*!< SYSCLK divided by 256 */
ommpy 0:d383e2dee0f7 1631 #define RCC_CFGR_HPRE_DIV512 ((uint32_t)0x000000F0) /*!< SYSCLK divided by 512 */
ommpy 0:d383e2dee0f7 1632
ommpy 0:d383e2dee0f7 1633 /*!< PPRE configuration */
ommpy 0:d383e2dee0f7 1634 #define RCC_CFGR_PPRE ((uint32_t)0x00000700) /*!< PRE[2:0] bits (APB prescaler) */
ommpy 0:d383e2dee0f7 1635 #define RCC_CFGR_PPRE_0 ((uint32_t)0x00000100) /*!< Bit 0 */
ommpy 0:d383e2dee0f7 1636 #define RCC_CFGR_PPRE_1 ((uint32_t)0x00000200) /*!< Bit 1 */
ommpy 0:d383e2dee0f7 1637 #define RCC_CFGR_PPRE_2 ((uint32_t)0x00000400) /*!< Bit 2 */
ommpy 0:d383e2dee0f7 1638
ommpy 0:d383e2dee0f7 1639 #define RCC_CFGR_PPRE_DIV1 ((uint32_t)0x00000000) /*!< HCLK not divided */
ommpy 0:d383e2dee0f7 1640 #define RCC_CFGR_PPRE_DIV2 ((uint32_t)0x00000400) /*!< HCLK divided by 2 */
ommpy 0:d383e2dee0f7 1641 #define RCC_CFGR_PPRE_DIV4 ((uint32_t)0x00000500) /*!< HCLK divided by 4 */
ommpy 0:d383e2dee0f7 1642 #define RCC_CFGR_PPRE_DIV8 ((uint32_t)0x00000600) /*!< HCLK divided by 8 */
ommpy 0:d383e2dee0f7 1643 #define RCC_CFGR_PPRE_DIV16 ((uint32_t)0x00000700) /*!< HCLK divided by 16 */
ommpy 0:d383e2dee0f7 1644
ommpy 0:d383e2dee0f7 1645 /*!< ADCPPRE configuration */
ommpy 0:d383e2dee0f7 1646 #define RCC_CFGR_ADCPRE ((uint32_t)0x00004000) /*!< ADCPRE bit (ADC prescaler) */
ommpy 0:d383e2dee0f7 1647
ommpy 0:d383e2dee0f7 1648 #define RCC_CFGR_ADCPRE_DIV2 ((uint32_t)0x00000000) /*!< PCLK divided by 2 */
ommpy 0:d383e2dee0f7 1649 #define RCC_CFGR_ADCPRE_DIV4 ((uint32_t)0x00004000) /*!< PCLK divided by 4 */
ommpy 0:d383e2dee0f7 1650
ommpy 0:d383e2dee0f7 1651 #define RCC_CFGR_PLLSRC ((uint32_t)0x00010000) /*!< PLL entry clock source */
ommpy 0:d383e2dee0f7 1652 #define RCC_CFGR_PLLSRC_HSI_DIV2 ((uint32_t)0x00000000) /*!< HSI clock divided by 2 selected as PLL entry clock source */
ommpy 0:d383e2dee0f7 1653 #define RCC_CFGR_PLLSRC_HSE_PREDIV ((uint32_t)0x00010000) /*!< HSE/PREDIV clock selected as PLL entry clock source */
ommpy 0:d383e2dee0f7 1654
ommpy 0:d383e2dee0f7 1655 #define RCC_CFGR_PLLXTPRE ((uint32_t)0x00020000) /*!< HSE divider for PLL entry */
ommpy 0:d383e2dee0f7 1656 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< HSE/PREDIV clock not divided for PLL entry */
ommpy 0:d383e2dee0f7 1657 #define RCC_CFGR_PLLXTPRE_HSE_PREDIV_DIV2 ((uint32_t)0x00020000) /*!< HSE/PREDIV clock divided by 2 for PLL entry */
ommpy 0:d383e2dee0f7 1658
ommpy 0:d383e2dee0f7 1659 /*!< PLLMUL configuration */
ommpy 0:d383e2dee0f7 1660 #define RCC_CFGR_PLLMUL ((uint32_t)0x003C0000) /*!< PLLMUL[3:0] bits (PLL multiplication factor) */
ommpy 0:d383e2dee0f7 1661 #define RCC_CFGR_PLLMUL_0 ((uint32_t)0x00040000) /*!< Bit 0 */
ommpy 0:d383e2dee0f7 1662 #define RCC_CFGR_PLLMUL_1 ((uint32_t)0x00080000) /*!< Bit 1 */
ommpy 0:d383e2dee0f7 1663 #define RCC_CFGR_PLLMUL_2 ((uint32_t)0x00100000) /*!< Bit 2 */
ommpy 0:d383e2dee0f7 1664 #define RCC_CFGR_PLLMUL_3 ((uint32_t)0x00200000) /*!< Bit 3 */
ommpy 0:d383e2dee0f7 1665
ommpy 0:d383e2dee0f7 1666 #define RCC_CFGR_PLLMUL2 ((uint32_t)0x00000000) /*!< PLL input clock*2 */
ommpy 0:d383e2dee0f7 1667 #define RCC_CFGR_PLLMUL3 ((uint32_t)0x00040000) /*!< PLL input clock*3 */
ommpy 0:d383e2dee0f7 1668 #define RCC_CFGR_PLLMUL4 ((uint32_t)0x00080000) /*!< PLL input clock*4 */
ommpy 0:d383e2dee0f7 1669 #define RCC_CFGR_PLLMUL5 ((uint32_t)0x000C0000) /*!< PLL input clock*5 */
ommpy 0:d383e2dee0f7 1670 #define RCC_CFGR_PLLMUL6 ((uint32_t)0x00100000) /*!< PLL input clock*6 */
ommpy 0:d383e2dee0f7 1671 #define RCC_CFGR_PLLMUL7 ((uint32_t)0x00140000) /*!< PLL input clock*7 */
ommpy 0:d383e2dee0f7 1672 #define RCC_CFGR_PLLMUL8 ((uint32_t)0x00180000) /*!< PLL input clock*8 */
ommpy 0:d383e2dee0f7 1673 #define RCC_CFGR_PLLMUL9 ((uint32_t)0x001C0000) /*!< PLL input clock*9 */
ommpy 0:d383e2dee0f7 1674 #define RCC_CFGR_PLLMUL10 ((uint32_t)0x00200000) /*!< PLL input clock10 */
ommpy 0:d383e2dee0f7 1675 #define RCC_CFGR_PLLMUL11 ((uint32_t)0x00240000) /*!< PLL input clock*11 */
ommpy 0:d383e2dee0f7 1676 #define RCC_CFGR_PLLMUL12 ((uint32_t)0x00280000) /*!< PLL input clock*12 */
ommpy 0:d383e2dee0f7 1677 #define RCC_CFGR_PLLMUL13 ((uint32_t)0x002C0000) /*!< PLL input clock*13 */
ommpy 0:d383e2dee0f7 1678 #define RCC_CFGR_PLLMUL14 ((uint32_t)0x00300000) /*!< PLL input clock*14 */
ommpy 0:d383e2dee0f7 1679 #define RCC_CFGR_PLLMUL15 ((uint32_t)0x00340000) /*!< PLL input clock*15 */
ommpy 0:d383e2dee0f7 1680 #define RCC_CFGR_PLLMUL16 ((uint32_t)0x00380000) /*!< PLL input clock*16 */
ommpy 0:d383e2dee0f7 1681
ommpy 0:d383e2dee0f7 1682 /*!< MCO configuration */
ommpy 0:d383e2dee0f7 1683 #define RCC_CFGR_MCO ((uint32_t)0x0F000000) /*!< MCO[3:0] bits (Microcontroller Clock Output) */
ommpy 0:d383e2dee0f7 1684 #define RCC_CFGR_MCO_0 ((uint32_t)0x01000000) /*!< Bit 0 */
ommpy 0:d383e2dee0f7 1685 #define RCC_CFGR_MCO_1 ((uint32_t)0x02000000) /*!< Bit 1 */
ommpy 0:d383e2dee0f7 1686 #define RCC_CFGR_MCO_2 ((uint32_t)0x04000000) /*!< Bit 2 */
ommpy 0:d383e2dee0f7 1687 #define RCC_CFGR_MCO_3 ((uint32_t)0x08000000) /*!< Bit 3 */
ommpy 0:d383e2dee0f7 1688
ommpy 0:d383e2dee0f7 1689 #define RCC_CFGR_MCO_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
ommpy 0:d383e2dee0f7 1690 #define RCC_CFGR_MCO_HSI14 ((uint32_t)0x01000000) /*!< HSI14 clock selected as MCO source */
ommpy 0:d383e2dee0f7 1691 #define RCC_CFGR_MCO_LSI ((uint32_t)0x02000000) /*!< LSI clock selected as MCO source */
ommpy 0:d383e2dee0f7 1692 #define RCC_CFGR_MCO_LSE ((uint32_t)0x03000000) /*!< LSE clock selected as MCO source */
ommpy 0:d383e2dee0f7 1693 #define RCC_CFGR_MCO_SYSCLK ((uint32_t)0x04000000) /*!< System clock selected as MCO source */
ommpy 0:d383e2dee0f7 1694 #define RCC_CFGR_MCO_HSI ((uint32_t)0x05000000) /*!< HSI clock selected as MCO source */
ommpy 0:d383e2dee0f7 1695 #define RCC_CFGR_MCO_HSE ((uint32_t)0x06000000) /*!< HSE clock selected as MCO source */
ommpy 0:d383e2dee0f7 1696 #define RCC_CFGR_MCO_PLL ((uint32_t)0x07000000) /*!< PLL clock divided by 2 selected as MCO source */
ommpy 0:d383e2dee0f7 1697
ommpy 0:d383e2dee0f7 1698 /*!<****************** Bit definition for RCC_CIR register *****************/
ommpy 0:d383e2dee0f7 1699 #define RCC_CIR_LSIRDYF ((uint32_t)0x00000001) /*!< LSI Ready Interrupt flag */
ommpy 0:d383e2dee0f7 1700 #define RCC_CIR_LSERDYF ((uint32_t)0x00000002) /*!< LSE Ready Interrupt flag */
ommpy 0:d383e2dee0f7 1701 #define RCC_CIR_HSIRDYF ((uint32_t)0x00000004) /*!< HSI Ready Interrupt flag */
ommpy 0:d383e2dee0f7 1702 #define RCC_CIR_HSERDYF ((uint32_t)0x00000008) /*!< HSE Ready Interrupt flag */
ommpy 0:d383e2dee0f7 1703 #define RCC_CIR_PLLRDYF ((uint32_t)0x00000010) /*!< PLL Ready Interrupt flag */
ommpy 0:d383e2dee0f7 1704 #define RCC_CIR_HSI14RDYF ((uint32_t)0x00000020) /*!< HSI14 Ready Interrupt flag */
ommpy 0:d383e2dee0f7 1705 #define RCC_CIR_CSSF ((uint32_t)0x00000080) /*!< Clock Security System Interrupt flag */
ommpy 0:d383e2dee0f7 1706 #define RCC_CIR_LSIRDYIE ((uint32_t)0x00000100) /*!< LSI Ready Interrupt Enable */
ommpy 0:d383e2dee0f7 1707 #define RCC_CIR_LSERDYIE ((uint32_t)0x00000200) /*!< LSE Ready Interrupt Enable */
ommpy 0:d383e2dee0f7 1708 #define RCC_CIR_HSIRDYIE ((uint32_t)0x00000400) /*!< HSI Ready Interrupt Enable */
ommpy 0:d383e2dee0f7 1709 #define RCC_CIR_HSERDYIE ((uint32_t)0x00000800) /*!< HSE Ready Interrupt Enable */
ommpy 0:d383e2dee0f7 1710 #define RCC_CIR_PLLRDYIE ((uint32_t)0x00001000) /*!< PLL Ready Interrupt Enable */
ommpy 0:d383e2dee0f7 1711 #define RCC_CIR_HSI14RDYIE ((uint32_t)0x00002000) /*!< HSI14 Ready Interrupt Enable */
ommpy 0:d383e2dee0f7 1712 #define RCC_CIR_LSIRDYC ((uint32_t)0x00010000) /*!< LSI Ready Interrupt Clear */
ommpy 0:d383e2dee0f7 1713 #define RCC_CIR_LSERDYC ((uint32_t)0x00020000) /*!< LSE Ready Interrupt Clear */
ommpy 0:d383e2dee0f7 1714 #define RCC_CIR_HSIRDYC ((uint32_t)0x00040000) /*!< HSI Ready Interrupt Clear */
ommpy 0:d383e2dee0f7 1715 #define RCC_CIR_HSERDYC ((uint32_t)0x00080000) /*!< HSE Ready Interrupt Clear */
ommpy 0:d383e2dee0f7 1716 #define RCC_CIR_PLLRDYC ((uint32_t)0x00100000) /*!< PLL Ready Interrupt Clear */
ommpy 0:d383e2dee0f7 1717 #define RCC_CIR_HSI14RDYC ((uint32_t)0x00200000) /*!< HSI14 Ready Interrupt Clear */
ommpy 0:d383e2dee0f7 1718 #define RCC_CIR_CSSC ((uint32_t)0x00800000) /*!< Clock Security System Interrupt Clear */
ommpy 0:d383e2dee0f7 1719
ommpy 0:d383e2dee0f7 1720 /***************** Bit definition for RCC_APB2RSTR register ****************/
ommpy 0:d383e2dee0f7 1721 #define RCC_APB2RSTR_SYSCFGRST ((uint32_t)0x00000001) /*!< SYSCFG clock reset */
ommpy 0:d383e2dee0f7 1722 #define RCC_APB2RSTR_ADCRST ((uint32_t)0x00000200) /*!< ADC clock reset */
ommpy 0:d383e2dee0f7 1723 #define RCC_APB2RSTR_TIM1RST ((uint32_t)0x00000800) /*!< TIM1 clock reset */
ommpy 0:d383e2dee0f7 1724 #define RCC_APB2RSTR_SPI1RST ((uint32_t)0x00001000) /*!< SPI1 clock reset */
ommpy 0:d383e2dee0f7 1725 #define RCC_APB2RSTR_USART1RST ((uint32_t)0x00004000) /*!< USART1 clock reset */
ommpy 0:d383e2dee0f7 1726 #define RCC_APB2RSTR_TIM15RST ((uint32_t)0x00010000) /*!< TIM15 clock reset */
ommpy 0:d383e2dee0f7 1727 #define RCC_APB2RSTR_TIM16RST ((uint32_t)0x00020000) /*!< TIM16 clock reset */
ommpy 0:d383e2dee0f7 1728 #define RCC_APB2RSTR_TIM17RST ((uint32_t)0x00040000) /*!< TIM17 clock reset */
ommpy 0:d383e2dee0f7 1729 #define RCC_APB2RSTR_DBGMCURST ((uint32_t)0x00400000) /*!< DBGMCU clock reset */
ommpy 0:d383e2dee0f7 1730
ommpy 0:d383e2dee0f7 1731 /*!< Old ADC1 clock reset bit definition maintained for legacy purpose */
ommpy 0:d383e2dee0f7 1732 #define RCC_APB2RSTR_ADC1RST RCC_APB2RSTR_ADCRST
ommpy 0:d383e2dee0f7 1733
ommpy 0:d383e2dee0f7 1734 /***************** Bit definition for RCC_APB1RSTR register ****************/
ommpy 0:d383e2dee0f7 1735 #define RCC_APB1RSTR_TIM3RST ((uint32_t)0x00000002) /*!< Timer 3 clock reset */
ommpy 0:d383e2dee0f7 1736 #define RCC_APB1RSTR_TIM6RST ((uint32_t)0x00000010) /*!< Timer 6 clock reset */
ommpy 0:d383e2dee0f7 1737 #define RCC_APB1RSTR_TIM14RST ((uint32_t)0x00000100) /*!< Timer 14 clock reset */
ommpy 0:d383e2dee0f7 1738 #define RCC_APB1RSTR_WWDGRST ((uint32_t)0x00000800) /*!< Window Watchdog clock reset */
ommpy 0:d383e2dee0f7 1739 #define RCC_APB1RSTR_SPI2RST ((uint32_t)0x00004000) /*!< SPI2 clock reset */
ommpy 0:d383e2dee0f7 1740 #define RCC_APB1RSTR_USART2RST ((uint32_t)0x00020000) /*!< USART 2 clock reset */
ommpy 0:d383e2dee0f7 1741 #define RCC_APB1RSTR_I2C1RST ((uint32_t)0x00200000) /*!< I2C 1 clock reset */
ommpy 0:d383e2dee0f7 1742 #define RCC_APB1RSTR_I2C2RST ((uint32_t)0x00400000) /*!< I2C 2 clock reset */
ommpy 0:d383e2dee0f7 1743 #define RCC_APB1RSTR_PWRRST ((uint32_t)0x10000000) /*!< PWR clock reset */
ommpy 0:d383e2dee0f7 1744
ommpy 0:d383e2dee0f7 1745 /****************** Bit definition for RCC_AHBENR register *****************/
ommpy 0:d383e2dee0f7 1746 #define RCC_AHBENR_DMAEN ((uint32_t)0x00000001) /*!< DMA1 clock enable */
ommpy 0:d383e2dee0f7 1747 #define RCC_AHBENR_SRAMEN ((uint32_t)0x00000004) /*!< SRAM interface clock enable */
ommpy 0:d383e2dee0f7 1748 #define RCC_AHBENR_FLITFEN ((uint32_t)0x00000010) /*!< FLITF clock enable */
ommpy 0:d383e2dee0f7 1749 #define RCC_AHBENR_CRCEN ((uint32_t)0x00000040) /*!< CRC clock enable */
ommpy 0:d383e2dee0f7 1750 #define RCC_AHBENR_GPIOAEN ((uint32_t)0x00020000) /*!< GPIOA clock enable */
ommpy 0:d383e2dee0f7 1751 #define RCC_AHBENR_GPIOBEN ((uint32_t)0x00040000) /*!< GPIOB clock enable */
ommpy 0:d383e2dee0f7 1752 #define RCC_AHBENR_GPIOCEN ((uint32_t)0x00080000) /*!< GPIOC clock enable */
ommpy 0:d383e2dee0f7 1753 #define RCC_AHBENR_GPIODEN ((uint32_t)0x00100000) /*!< GPIOD clock enable */
ommpy 0:d383e2dee0f7 1754 #define RCC_AHBENR_GPIOFEN ((uint32_t)0x00400000) /*!< GPIOF clock enable */
ommpy 0:d383e2dee0f7 1755
ommpy 0:d383e2dee0f7 1756 /* Old Bit definition maintained for legacy purpose */
ommpy 0:d383e2dee0f7 1757 #define RCC_AHBENR_DMA1EN RCC_AHBENR_DMAEN /*!< DMA1 clock enable */
ommpy 0:d383e2dee0f7 1758 #define RCC_AHBENR_TSEN RCC_AHBENR_TSCEN /*!< TS clock enable */
ommpy 0:d383e2dee0f7 1759
ommpy 0:d383e2dee0f7 1760 /***************** Bit definition for RCC_APB2ENR register *****************/
ommpy 0:d383e2dee0f7 1761 #define RCC_APB2ENR_SYSCFGCOMPEN ((uint32_t)0x00000001) /*!< SYSCFG and comparator clock enable */
ommpy 0:d383e2dee0f7 1762 #define RCC_APB2ENR_ADCEN ((uint32_t)0x00000200) /*!< ADC1 clock enable */
ommpy 0:d383e2dee0f7 1763 #define RCC_APB2ENR_TIM1EN ((uint32_t)0x00000800) /*!< TIM1 clock enable */
ommpy 0:d383e2dee0f7 1764 #define RCC_APB2ENR_SPI1EN ((uint32_t)0x00001000) /*!< SPI1 clock enable */
ommpy 0:d383e2dee0f7 1765 #define RCC_APB2ENR_USART1EN ((uint32_t)0x00004000) /*!< USART1 clock enable */
ommpy 0:d383e2dee0f7 1766 #define RCC_APB2ENR_TIM15EN ((uint32_t)0x00010000) /*!< TIM15 clock enable */
ommpy 0:d383e2dee0f7 1767 #define RCC_APB2ENR_TIM16EN ((uint32_t)0x00020000) /*!< TIM16 clock enable */
ommpy 0:d383e2dee0f7 1768 #define RCC_APB2ENR_TIM17EN ((uint32_t)0x00040000) /*!< TIM17 clock enable */
ommpy 0:d383e2dee0f7 1769 #define RCC_APB2ENR_DBGMCUEN ((uint32_t)0x00400000) /*!< DBGMCU clock enable */
ommpy 0:d383e2dee0f7 1770
ommpy 0:d383e2dee0f7 1771 /* Old Bit definition maintained for legacy purpose */
ommpy 0:d383e2dee0f7 1772 #define RCC_APB2ENR_SYSCFGEN RCC_APB2ENR_SYSCFGCOMPEN /*!< SYSCFG clock enable */
ommpy 0:d383e2dee0f7 1773 #define RCC_APB2ENR_ADC1EN RCC_APB2ENR_ADCEN /*!< ADC1 clock enable */
ommpy 0:d383e2dee0f7 1774
ommpy 0:d383e2dee0f7 1775 /***************** Bit definition for RCC_APB1ENR register *****************/
ommpy 0:d383e2dee0f7 1776 #define RCC_APB1ENR_TIM3EN ((uint32_t)0x00000002) /*!< Timer 3 clock enable */
ommpy 0:d383e2dee0f7 1777 #define RCC_APB1ENR_TIM6EN ((uint32_t)0x00000010) /*!< Timer 6 clock enable */
ommpy 0:d383e2dee0f7 1778 #define RCC_APB1ENR_TIM14EN ((uint32_t)0x00000100) /*!< Timer 14 clock enable */
ommpy 0:d383e2dee0f7 1779 #define RCC_APB1ENR_WWDGEN ((uint32_t)0x00000800) /*!< Window Watchdog clock enable */
ommpy 0:d383e2dee0f7 1780 #define RCC_APB1ENR_SPI2EN ((uint32_t)0x00004000) /*!< SPI2 clock enable */
ommpy 0:d383e2dee0f7 1781 #define RCC_APB1ENR_USART2EN ((uint32_t)0x00020000) /*!< USART2 clock enable */
ommpy 0:d383e2dee0f7 1782 #define RCC_APB1ENR_I2C1EN ((uint32_t)0x00200000) /*!< I2C1 clock enable */
ommpy 0:d383e2dee0f7 1783 #define RCC_APB1ENR_I2C2EN ((uint32_t)0x00400000) /*!< I2C2 clock enable */
ommpy 0:d383e2dee0f7 1784 #define RCC_APB1ENR_PWREN ((uint32_t)0x10000000) /*!< PWR clock enable */
ommpy 0:d383e2dee0f7 1785
ommpy 0:d383e2dee0f7 1786 /******************* Bit definition for RCC_BDCR register ******************/
ommpy 0:d383e2dee0f7 1787 #define RCC_BDCR_LSEON ((uint32_t)0x00000001) /*!< External Low Speed oscillator enable */
ommpy 0:d383e2dee0f7 1788 #define RCC_BDCR_LSERDY ((uint32_t)0x00000002) /*!< External Low Speed oscillator Ready */
ommpy 0:d383e2dee0f7 1789 #define RCC_BDCR_LSEBYP ((uint32_t)0x00000004) /*!< External Low Speed oscillator Bypass */
ommpy 0:d383e2dee0f7 1790
ommpy 0:d383e2dee0f7 1791 #define RCC_BDCR_LSEDRV ((uint32_t)0x00000018) /*!< LSEDRV[1:0] bits (LSE Osc. drive capability) */
ommpy 0:d383e2dee0f7 1792 #define RCC_BDCR_LSEDRV_0 ((uint32_t)0x00000008) /*!< Bit 0 */
ommpy 0:d383e2dee0f7 1793 #define RCC_BDCR_LSEDRV_1 ((uint32_t)0x00000010) /*!< Bit 1 */
ommpy 0:d383e2dee0f7 1794
ommpy 0:d383e2dee0f7 1795 #define RCC_BDCR_RTCSEL ((uint32_t)0x00000300) /*!< RTCSEL[1:0] bits (RTC clock source selection) */
ommpy 0:d383e2dee0f7 1796 #define RCC_BDCR_RTCSEL_0 ((uint32_t)0x00000100) /*!< Bit 0 */
ommpy 0:d383e2dee0f7 1797 #define RCC_BDCR_RTCSEL_1 ((uint32_t)0x00000200) /*!< Bit 1 */
ommpy 0:d383e2dee0f7 1798
ommpy 0:d383e2dee0f7 1799 /*!< RTC configuration */
ommpy 0:d383e2dee0f7 1800 #define RCC_BDCR_RTCSEL_NOCLOCK ((uint32_t)0x00000000) /*!< No clock */
ommpy 0:d383e2dee0f7 1801 #define RCC_BDCR_RTCSEL_LSE ((uint32_t)0x00000100) /*!< LSE oscillator clock used as RTC clock */
ommpy 0:d383e2dee0f7 1802 #define RCC_BDCR_RTCSEL_LSI ((uint32_t)0x00000200) /*!< LSI oscillator clock used as RTC clock */
ommpy 0:d383e2dee0f7 1803 #define RCC_BDCR_RTCSEL_HSE ((uint32_t)0x00000300) /*!< HSE oscillator clock divided by 128 used as RTC clock */
ommpy 0:d383e2dee0f7 1804
ommpy 0:d383e2dee0f7 1805 #define RCC_BDCR_RTCEN ((uint32_t)0x00008000) /*!< RTC clock enable */
ommpy 0:d383e2dee0f7 1806 #define RCC_BDCR_BDRST ((uint32_t)0x00010000) /*!< Backup domain software reset */
ommpy 0:d383e2dee0f7 1807
ommpy 0:d383e2dee0f7 1808 /******************* Bit definition for RCC_CSR register *******************/
ommpy 0:d383e2dee0f7 1809 #define RCC_CSR_LSION ((uint32_t)0x00000001) /*!< Internal Low Speed oscillator enable */
ommpy 0:d383e2dee0f7 1810 #define RCC_CSR_LSIRDY ((uint32_t)0x00000002) /*!< Internal Low Speed oscillator Ready */
ommpy 0:d383e2dee0f7 1811 #define RCC_CSR_V18PWRRSTF ((uint32_t)0x00800000) /*!< V1.8 power domain reset flag */
ommpy 0:d383e2dee0f7 1812 #define RCC_CSR_RMVF ((uint32_t)0x01000000) /*!< Remove reset flag */
ommpy 0:d383e2dee0f7 1813 #define RCC_CSR_OBLRSTF ((uint32_t)0x02000000) /*!< OBL reset flag */
ommpy 0:d383e2dee0f7 1814 #define RCC_CSR_PINRSTF ((uint32_t)0x04000000) /*!< PIN reset flag */
ommpy 0:d383e2dee0f7 1815 #define RCC_CSR_PORRSTF ((uint32_t)0x08000000) /*!< POR/PDR reset flag */
ommpy 0:d383e2dee0f7 1816 #define RCC_CSR_SFTRSTF ((uint32_t)0x10000000) /*!< Software Reset flag */
ommpy 0:d383e2dee0f7 1817 #define RCC_CSR_IWDGRSTF ((uint32_t)0x20000000) /*!< Independent Watchdog reset flag */
ommpy 0:d383e2dee0f7 1818 #define RCC_CSR_WWDGRSTF ((uint32_t)0x40000000) /*!< Window watchdog reset flag */
ommpy 0:d383e2dee0f7 1819 #define RCC_CSR_LPWRRSTF ((uint32_t)0x80000000) /*!< Low-Power reset flag */
ommpy 0:d383e2dee0f7 1820
ommpy 0:d383e2dee0f7 1821 /* Old Bit definition maintained for legacy purpose */
ommpy 0:d383e2dee0f7 1822 #define RCC_CSR_OBL RCC_CSR_OBLRSTF /*!< OBL reset flag */
ommpy 0:d383e2dee0f7 1823
ommpy 0:d383e2dee0f7 1824 /******************* Bit definition for RCC_AHBRSTR register ***************/
ommpy 0:d383e2dee0f7 1825 #define RCC_AHBRSTR_GPIOARST ((uint32_t)0x00020000) /*!< GPIOA clock reset */
ommpy 0:d383e2dee0f7 1826 #define RCC_AHBRSTR_GPIOBRST ((uint32_t)0x00040000) /*!< GPIOB clock reset */
ommpy 0:d383e2dee0f7 1827 #define RCC_AHBRSTR_GPIOCRST ((uint32_t)0x00080000) /*!< GPIOC clock reset */
ommpy 0:d383e2dee0f7 1828 #define RCC_AHBRSTR_GPIODRST ((uint32_t)0x00100000) /*!< GPIOD clock reset */
ommpy 0:d383e2dee0f7 1829 #define RCC_AHBRSTR_GPIOFRST ((uint32_t)0x00400000) /*!< GPIOF clock reset */
ommpy 0:d383e2dee0f7 1830
ommpy 0:d383e2dee0f7 1831 /******************* Bit definition for RCC_CFGR2 register *****************/
ommpy 0:d383e2dee0f7 1832 /*!< PREDIV configuration */
ommpy 0:d383e2dee0f7 1833 #define RCC_CFGR2_PREDIV ((uint32_t)0x0000000F) /*!< PREDIV[3:0] bits */
ommpy 0:d383e2dee0f7 1834 #define RCC_CFGR2_PREDIV_0 ((uint32_t)0x00000001) /*!< Bit 0 */
ommpy 0:d383e2dee0f7 1835 #define RCC_CFGR2_PREDIV_1 ((uint32_t)0x00000002) /*!< Bit 1 */
ommpy 0:d383e2dee0f7 1836 #define RCC_CFGR2_PREDIV_2 ((uint32_t)0x00000004) /*!< Bit 2 */
ommpy 0:d383e2dee0f7 1837 #define RCC_CFGR2_PREDIV_3 ((uint32_t)0x00000008) /*!< Bit 3 */
ommpy 0:d383e2dee0f7 1838
ommpy 0:d383e2dee0f7 1839 #define RCC_CFGR2_PREDIV_DIV1 ((uint32_t)0x00000000) /*!< PREDIV input clock not divided */
ommpy 0:d383e2dee0f7 1840 #define RCC_CFGR2_PREDIV_DIV2 ((uint32_t)0x00000001) /*!< PREDIV input clock divided by 2 */
ommpy 0:d383e2dee0f7 1841 #define RCC_CFGR2_PREDIV_DIV3 ((uint32_t)0x00000002) /*!< PREDIV input clock divided by 3 */
ommpy 0:d383e2dee0f7 1842 #define RCC_CFGR2_PREDIV_DIV4 ((uint32_t)0x00000003) /*!< PREDIV input clock divided by 4 */
ommpy 0:d383e2dee0f7 1843 #define RCC_CFGR2_PREDIV_DIV5 ((uint32_t)0x00000004) /*!< PREDIV input clock divided by 5 */
ommpy 0:d383e2dee0f7 1844 #define RCC_CFGR2_PREDIV_DIV6 ((uint32_t)0x00000005) /*!< PREDIV input clock divided by 6 */
ommpy 0:d383e2dee0f7 1845 #define RCC_CFGR2_PREDIV_DIV7 ((uint32_t)0x00000006) /*!< PREDIV input clock divided by 7 */
ommpy 0:d383e2dee0f7 1846 #define RCC_CFGR2_PREDIV_DIV8 ((uint32_t)0x00000007) /*!< PREDIV input clock divided by 8 */
ommpy 0:d383e2dee0f7 1847 #define RCC_CFGR2_PREDIV_DIV9 ((uint32_t)0x00000008) /*!< PREDIV input clock divided by 9 */
ommpy 0:d383e2dee0f7 1848 #define RCC_CFGR2_PREDIV_DIV10 ((uint32_t)0x00000009) /*!< PREDIV input clock divided by 10 */
ommpy 0:d383e2dee0f7 1849 #define RCC_CFGR2_PREDIV_DIV11 ((uint32_t)0x0000000A) /*!< PREDIV input clock divided by 11 */
ommpy 0:d383e2dee0f7 1850 #define RCC_CFGR2_PREDIV_DIV12 ((uint32_t)0x0000000B) /*!< PREDIV input clock divided by 12 */
ommpy 0:d383e2dee0f7 1851 #define RCC_CFGR2_PREDIV_DIV13 ((uint32_t)0x0000000C) /*!< PREDIV input clock divided by 13 */
ommpy 0:d383e2dee0f7 1852 #define RCC_CFGR2_PREDIV_DIV14 ((uint32_t)0x0000000D) /*!< PREDIV input clock divided by 14 */
ommpy 0:d383e2dee0f7 1853 #define RCC_CFGR2_PREDIV_DIV15 ((uint32_t)0x0000000E) /*!< PREDIV input clock divided by 15 */
ommpy 0:d383e2dee0f7 1854 #define RCC_CFGR2_PREDIV_DIV16 ((uint32_t)0x0000000F) /*!< PREDIV input clock divided by 16 */
ommpy 0:d383e2dee0f7 1855
ommpy 0:d383e2dee0f7 1856 /******************* Bit definition for RCC_CFGR3 register *****************/
ommpy 0:d383e2dee0f7 1857 /*!< USART1 Clock source selection */
ommpy 0:d383e2dee0f7 1858 #define RCC_CFGR3_USART1SW ((uint32_t)0x00000003) /*!< USART1SW[1:0] bits */
ommpy 0:d383e2dee0f7 1859 #define RCC_CFGR3_USART1SW_0 ((uint32_t)0x00000001) /*!< Bit 0 */
ommpy 0:d383e2dee0f7 1860 #define RCC_CFGR3_USART1SW_1 ((uint32_t)0x00000002) /*!< Bit 1 */
ommpy 0:d383e2dee0f7 1861
ommpy 0:d383e2dee0f7 1862 #define RCC_CFGR3_USART1SW_PCLK ((uint32_t)0x00000000) /*!< PCLK clock used as USART1 clock source */
ommpy 0:d383e2dee0f7 1863 #define RCC_CFGR3_USART1SW_SYSCLK ((uint32_t)0x00000001) /*!< System clock selected as USART1 clock source */
ommpy 0:d383e2dee0f7 1864 #define RCC_CFGR3_USART1SW_LSE ((uint32_t)0x00000002) /*!< LSE oscillator clock used as USART1 clock source */
ommpy 0:d383e2dee0f7 1865 #define RCC_CFGR3_USART1SW_HSI ((uint32_t)0x00000003) /*!< HSI oscillator clock used as USART1 clock source */
ommpy 0:d383e2dee0f7 1866
ommpy 0:d383e2dee0f7 1867 /*!< I2C1 Clock source selection */
ommpy 0:d383e2dee0f7 1868 #define RCC_CFGR3_I2C1SW ((uint32_t)0x00000010) /*!< I2C1SW bits */
ommpy 0:d383e2dee0f7 1869
ommpy 0:d383e2dee0f7 1870 #define RCC_CFGR3_I2C1SW_HSI ((uint32_t)0x00000000) /*!< HSI oscillator clock used as I2C1 clock source */
ommpy 0:d383e2dee0f7 1871 #define RCC_CFGR3_I2C1SW_SYSCLK ((uint32_t)0x00000010) /*!< System clock selected as I2C1 clock source */
ommpy 0:d383e2dee0f7 1872
ommpy 0:d383e2dee0f7 1873 /******************* Bit definition for RCC_CR2 register *******************/
ommpy 0:d383e2dee0f7 1874 #define RCC_CR2_HSI14ON ((uint32_t)0x00000001) /*!< Internal High Speed 14MHz clock enable */
ommpy 0:d383e2dee0f7 1875 #define RCC_CR2_HSI14RDY ((uint32_t)0x00000002) /*!< Internal High Speed 14MHz clock ready flag */
ommpy 0:d383e2dee0f7 1876 #define RCC_CR2_HSI14DIS ((uint32_t)0x00000004) /*!< Internal High Speed 14MHz clock disable */
ommpy 0:d383e2dee0f7 1877 #define RCC_CR2_HSI14TRIM ((uint32_t)0x000000F8) /*!< Internal High Speed 14MHz clock trimming */
ommpy 0:d383e2dee0f7 1878 #define RCC_CR2_HSI14CAL ((uint32_t)0x0000FF00) /*!< Internal High Speed 14MHz clock Calibration */
ommpy 0:d383e2dee0f7 1879
ommpy 0:d383e2dee0f7 1880 /*****************************************************************************/
ommpy 0:d383e2dee0f7 1881 /* */
ommpy 0:d383e2dee0f7 1882 /* Real-Time Clock (RTC) */
ommpy 0:d383e2dee0f7 1883 /* */
ommpy 0:d383e2dee0f7 1884 /*****************************************************************************/
ommpy 0:d383e2dee0f7 1885 /******************** Bits definition for RTC_TR register ******************/
ommpy 0:d383e2dee0f7 1886 #define RTC_TR_PM ((uint32_t)0x00400000)
ommpy 0:d383e2dee0f7 1887 #define RTC_TR_HT ((uint32_t)0x00300000)
ommpy 0:d383e2dee0f7 1888 #define RTC_TR_HT_0 ((uint32_t)0x00100000)
ommpy 0:d383e2dee0f7 1889 #define RTC_TR_HT_1 ((uint32_t)0x00200000)
ommpy 0:d383e2dee0f7 1890 #define RTC_TR_HU ((uint32_t)0x000F0000)
ommpy 0:d383e2dee0f7 1891 #define RTC_TR_HU_0 ((uint32_t)0x00010000)
ommpy 0:d383e2dee0f7 1892 #define RTC_TR_HU_1 ((uint32_t)0x00020000)
ommpy 0:d383e2dee0f7 1893 #define RTC_TR_HU_2 ((uint32_t)0x00040000)
ommpy 0:d383e2dee0f7 1894 #define RTC_TR_HU_3 ((uint32_t)0x00080000)
ommpy 0:d383e2dee0f7 1895 #define RTC_TR_MNT ((uint32_t)0x00007000)
ommpy 0:d383e2dee0f7 1896 #define RTC_TR_MNT_0 ((uint32_t)0x00001000)
ommpy 0:d383e2dee0f7 1897 #define RTC_TR_MNT_1 ((uint32_t)0x00002000)
ommpy 0:d383e2dee0f7 1898 #define RTC_TR_MNT_2 ((uint32_t)0x00004000)
ommpy 0:d383e2dee0f7 1899 #define RTC_TR_MNU ((uint32_t)0x00000F00)
ommpy 0:d383e2dee0f7 1900 #define RTC_TR_MNU_0 ((uint32_t)0x00000100)
ommpy 0:d383e2dee0f7 1901 #define RTC_TR_MNU_1 ((uint32_t)0x00000200)
ommpy 0:d383e2dee0f7 1902 #define RTC_TR_MNU_2 ((uint32_t)0x00000400)
ommpy 0:d383e2dee0f7 1903 #define RTC_TR_MNU_3 ((uint32_t)0x00000800)
ommpy 0:d383e2dee0f7 1904 #define RTC_TR_ST ((uint32_t)0x00000070)
ommpy 0:d383e2dee0f7 1905 #define RTC_TR_ST_0 ((uint32_t)0x00000010)
ommpy 0:d383e2dee0f7 1906 #define RTC_TR_ST_1 ((uint32_t)0x00000020)
ommpy 0:d383e2dee0f7 1907 #define RTC_TR_ST_2 ((uint32_t)0x00000040)
ommpy 0:d383e2dee0f7 1908 #define RTC_TR_SU ((uint32_t)0x0000000F)
ommpy 0:d383e2dee0f7 1909 #define RTC_TR_SU_0 ((uint32_t)0x00000001)
ommpy 0:d383e2dee0f7 1910 #define RTC_TR_SU_1 ((uint32_t)0x00000002)
ommpy 0:d383e2dee0f7 1911 #define RTC_TR_SU_2 ((uint32_t)0x00000004)
ommpy 0:d383e2dee0f7 1912 #define RTC_TR_SU_3 ((uint32_t)0x00000008)
ommpy 0:d383e2dee0f7 1913
ommpy 0:d383e2dee0f7 1914 /******************** Bits definition for RTC_DR register ******************/
ommpy 0:d383e2dee0f7 1915 #define RTC_DR_YT ((uint32_t)0x00F00000)
ommpy 0:d383e2dee0f7 1916 #define RTC_DR_YT_0 ((uint32_t)0x00100000)
ommpy 0:d383e2dee0f7 1917 #define RTC_DR_YT_1 ((uint32_t)0x00200000)
ommpy 0:d383e2dee0f7 1918 #define RTC_DR_YT_2 ((uint32_t)0x00400000)
ommpy 0:d383e2dee0f7 1919 #define RTC_DR_YT_3 ((uint32_t)0x00800000)
ommpy 0:d383e2dee0f7 1920 #define RTC_DR_YU ((uint32_t)0x000F0000)
ommpy 0:d383e2dee0f7 1921 #define RTC_DR_YU_0 ((uint32_t)0x00010000)
ommpy 0:d383e2dee0f7 1922 #define RTC_DR_YU_1 ((uint32_t)0x00020000)
ommpy 0:d383e2dee0f7 1923 #define RTC_DR_YU_2 ((uint32_t)0x00040000)
ommpy 0:d383e2dee0f7 1924 #define RTC_DR_YU_3 ((uint32_t)0x00080000)
ommpy 0:d383e2dee0f7 1925 #define RTC_DR_WDU ((uint32_t)0x0000E000)
ommpy 0:d383e2dee0f7 1926 #define RTC_DR_WDU_0 ((uint32_t)0x00002000)
ommpy 0:d383e2dee0f7 1927 #define RTC_DR_WDU_1 ((uint32_t)0x00004000)
ommpy 0:d383e2dee0f7 1928 #define RTC_DR_WDU_2 ((uint32_t)0x00008000)
ommpy 0:d383e2dee0f7 1929 #define RTC_DR_MT ((uint32_t)0x00001000)
ommpy 0:d383e2dee0f7 1930 #define RTC_DR_MU ((uint32_t)0x00000F00)
ommpy 0:d383e2dee0f7 1931 #define RTC_DR_MU_0 ((uint32_t)0x00000100)
ommpy 0:d383e2dee0f7 1932 #define RTC_DR_MU_1 ((uint32_t)0x00000200)
ommpy 0:d383e2dee0f7 1933 #define RTC_DR_MU_2 ((uint32_t)0x00000400)
ommpy 0:d383e2dee0f7 1934 #define RTC_DR_MU_3 ((uint32_t)0x00000800)
ommpy 0:d383e2dee0f7 1935 #define RTC_DR_DT ((uint32_t)0x00000030)
ommpy 0:d383e2dee0f7 1936 #define RTC_DR_DT_0 ((uint32_t)0x00000010)
ommpy 0:d383e2dee0f7 1937 #define RTC_DR_DT_1 ((uint32_t)0x00000020)
ommpy 0:d383e2dee0f7 1938 #define RTC_DR_DU ((uint32_t)0x0000000F)
ommpy 0:d383e2dee0f7 1939 #define RTC_DR_DU_0 ((uint32_t)0x00000001)
ommpy 0:d383e2dee0f7 1940 #define RTC_DR_DU_1 ((uint32_t)0x00000002)
ommpy 0:d383e2dee0f7 1941 #define RTC_DR_DU_2 ((uint32_t)0x00000004)
ommpy 0:d383e2dee0f7 1942 #define RTC_DR_DU_3 ((uint32_t)0x00000008)
ommpy 0:d383e2dee0f7 1943
ommpy 0:d383e2dee0f7 1944 /******************** Bits definition for RTC_CR register ******************/
ommpy 0:d383e2dee0f7 1945 #define RTC_CR_COE ((uint32_t)0x00800000)
ommpy 0:d383e2dee0f7 1946 #define RTC_CR_OSEL ((uint32_t)0x00600000)
ommpy 0:d383e2dee0f7 1947 #define RTC_CR_OSEL_0 ((uint32_t)0x00200000)
ommpy 0:d383e2dee0f7 1948 #define RTC_CR_OSEL_1 ((uint32_t)0x00400000)
ommpy 0:d383e2dee0f7 1949 #define RTC_CR_POL ((uint32_t)0x00100000)
ommpy 0:d383e2dee0f7 1950 #define RTC_CR_COSEL ((uint32_t)0x00080000)
ommpy 0:d383e2dee0f7 1951 #define RTC_CR_BCK ((uint32_t)0x00040000)
ommpy 0:d383e2dee0f7 1952 #define RTC_CR_SUB1H ((uint32_t)0x00020000)
ommpy 0:d383e2dee0f7 1953 #define RTC_CR_ADD1H ((uint32_t)0x00010000)
ommpy 0:d383e2dee0f7 1954 #define RTC_CR_TSIE ((uint32_t)0x00008000)
ommpy 0:d383e2dee0f7 1955 #define RTC_CR_ALRAIE ((uint32_t)0x00001000)
ommpy 0:d383e2dee0f7 1956 #define RTC_CR_TSE ((uint32_t)0x00000800)
ommpy 0:d383e2dee0f7 1957 #define RTC_CR_ALRAE ((uint32_t)0x00000100)
ommpy 0:d383e2dee0f7 1958 #define RTC_CR_FMT ((uint32_t)0x00000040)
ommpy 0:d383e2dee0f7 1959 #define RTC_CR_BYPSHAD ((uint32_t)0x00000020)
ommpy 0:d383e2dee0f7 1960 #define RTC_CR_REFCKON ((uint32_t)0x00000010)
ommpy 0:d383e2dee0f7 1961 #define RTC_CR_TSEDGE ((uint32_t)0x00000008)
ommpy 0:d383e2dee0f7 1962
ommpy 0:d383e2dee0f7 1963 /******************** Bits definition for RTC_ISR register *****************/
ommpy 0:d383e2dee0f7 1964 #define RTC_ISR_RECALPF ((uint32_t)0x00010000)
ommpy 0:d383e2dee0f7 1965 #define RTC_ISR_TAMP2F ((uint32_t)0x00004000)
ommpy 0:d383e2dee0f7 1966 #define RTC_ISR_TAMP1F ((uint32_t)0x00002000)
ommpy 0:d383e2dee0f7 1967 #define RTC_ISR_TSOVF ((uint32_t)0x00001000)
ommpy 0:d383e2dee0f7 1968 #define RTC_ISR_TSF ((uint32_t)0x00000800)
ommpy 0:d383e2dee0f7 1969 #define RTC_ISR_ALRAF ((uint32_t)0x00000100)
ommpy 0:d383e2dee0f7 1970 #define RTC_ISR_INIT ((uint32_t)0x00000080)
ommpy 0:d383e2dee0f7 1971 #define RTC_ISR_INITF ((uint32_t)0x00000040)
ommpy 0:d383e2dee0f7 1972 #define RTC_ISR_RSF ((uint32_t)0x00000020)
ommpy 0:d383e2dee0f7 1973 #define RTC_ISR_INITS ((uint32_t)0x00000010)
ommpy 0:d383e2dee0f7 1974 #define RTC_ISR_SHPF ((uint32_t)0x00000008)
ommpy 0:d383e2dee0f7 1975 #define RTC_ISR_ALRAWF ((uint32_t)0x00000001)
ommpy 0:d383e2dee0f7 1976
ommpy 0:d383e2dee0f7 1977 /******************** Bits definition for RTC_PRER register ****************/
ommpy 0:d383e2dee0f7 1978 #define RTC_PRER_PREDIV_A ((uint32_t)0x007F0000)
ommpy 0:d383e2dee0f7 1979 #define RTC_PRER_PREDIV_S ((uint32_t)0x00007FFF)
ommpy 0:d383e2dee0f7 1980
ommpy 0:d383e2dee0f7 1981 /******************** Bits definition for RTC_ALRMAR register **************/
ommpy 0:d383e2dee0f7 1982 #define RTC_ALRMAR_MSK4 ((uint32_t)0x80000000)
ommpy 0:d383e2dee0f7 1983 #define RTC_ALRMAR_WDSEL ((uint32_t)0x40000000)
ommpy 0:d383e2dee0f7 1984 #define RTC_ALRMAR_DT ((uint32_t)0x30000000)
ommpy 0:d383e2dee0f7 1985 #define RTC_ALRMAR_DT_0 ((uint32_t)0x10000000)
ommpy 0:d383e2dee0f7 1986 #define RTC_ALRMAR_DT_1 ((uint32_t)0x20000000)
ommpy 0:d383e2dee0f7 1987 #define RTC_ALRMAR_DU ((uint32_t)0x0F000000)
ommpy 0:d383e2dee0f7 1988 #define RTC_ALRMAR_DU_0 ((uint32_t)0x01000000)
ommpy 0:d383e2dee0f7 1989 #define RTC_ALRMAR_DU_1 ((uint32_t)0x02000000)
ommpy 0:d383e2dee0f7 1990 #define RTC_ALRMAR_DU_2 ((uint32_t)0x04000000)
ommpy 0:d383e2dee0f7 1991 #define RTC_ALRMAR_DU_3 ((uint32_t)0x08000000)
ommpy 0:d383e2dee0f7 1992 #define RTC_ALRMAR_MSK3 ((uint32_t)0x00800000)
ommpy 0:d383e2dee0f7 1993 #define RTC_ALRMAR_PM ((uint32_t)0x00400000)
ommpy 0:d383e2dee0f7 1994 #define RTC_ALRMAR_HT ((uint32_t)0x00300000)
ommpy 0:d383e2dee0f7 1995 #define RTC_ALRMAR_HT_0 ((uint32_t)0x00100000)
ommpy 0:d383e2dee0f7 1996 #define RTC_ALRMAR_HT_1 ((uint32_t)0x00200000)
ommpy 0:d383e2dee0f7 1997 #define RTC_ALRMAR_HU ((uint32_t)0x000F0000)
ommpy 0:d383e2dee0f7 1998 #define RTC_ALRMAR_HU_0 ((uint32_t)0x00010000)
ommpy 0:d383e2dee0f7 1999 #define RTC_ALRMAR_HU_1 ((uint32_t)0x00020000)
ommpy 0:d383e2dee0f7 2000 #define RTC_ALRMAR_HU_2 ((uint32_t)0x00040000)
ommpy 0:d383e2dee0f7 2001 #define RTC_ALRMAR_HU_3 ((uint32_t)0x00080000)
ommpy 0:d383e2dee0f7 2002 #define RTC_ALRMAR_MSK2 ((uint32_t)0x00008000)
ommpy 0:d383e2dee0f7 2003 #define RTC_ALRMAR_MNT ((uint32_t)0x00007000)
ommpy 0:d383e2dee0f7 2004 #define RTC_ALRMAR_MNT_0 ((uint32_t)0x00001000)
ommpy 0:d383e2dee0f7 2005 #define RTC_ALRMAR_MNT_1 ((uint32_t)0x00002000)
ommpy 0:d383e2dee0f7 2006 #define RTC_ALRMAR_MNT_2 ((uint32_t)0x00004000)
ommpy 0:d383e2dee0f7 2007 #define RTC_ALRMAR_MNU ((uint32_t)0x00000F00)
ommpy 0:d383e2dee0f7 2008 #define RTC_ALRMAR_MNU_0 ((uint32_t)0x00000100)
ommpy 0:d383e2dee0f7 2009 #define RTC_ALRMAR_MNU_1 ((uint32_t)0x00000200)
ommpy 0:d383e2dee0f7 2010 #define RTC_ALRMAR_MNU_2 ((uint32_t)0x00000400)
ommpy 0:d383e2dee0f7 2011 #define RTC_ALRMAR_MNU_3 ((uint32_t)0x00000800)
ommpy 0:d383e2dee0f7 2012 #define RTC_ALRMAR_MSK1 ((uint32_t)0x00000080)
ommpy 0:d383e2dee0f7 2013 #define RTC_ALRMAR_ST ((uint32_t)0x00000070)
ommpy 0:d383e2dee0f7 2014 #define RTC_ALRMAR_ST_0 ((uint32_t)0x00000010)
ommpy 0:d383e2dee0f7 2015 #define RTC_ALRMAR_ST_1 ((uint32_t)0x00000020)
ommpy 0:d383e2dee0f7 2016 #define RTC_ALRMAR_ST_2 ((uint32_t)0x00000040)
ommpy 0:d383e2dee0f7 2017 #define RTC_ALRMAR_SU ((uint32_t)0x0000000F)
ommpy 0:d383e2dee0f7 2018 #define RTC_ALRMAR_SU_0 ((uint32_t)0x00000001)
ommpy 0:d383e2dee0f7 2019 #define RTC_ALRMAR_SU_1 ((uint32_t)0x00000002)
ommpy 0:d383e2dee0f7 2020 #define RTC_ALRMAR_SU_2 ((uint32_t)0x00000004)
ommpy 0:d383e2dee0f7 2021 #define RTC_ALRMAR_SU_3 ((uint32_t)0x00000008)
ommpy 0:d383e2dee0f7 2022
ommpy 0:d383e2dee0f7 2023 /******************** Bits definition for RTC_WPR register *****************/
ommpy 0:d383e2dee0f7 2024 #define RTC_WPR_KEY ((uint32_t)0x000000FF)
ommpy 0:d383e2dee0f7 2025
ommpy 0:d383e2dee0f7 2026 /******************** Bits definition for RTC_SSR register *****************/
ommpy 0:d383e2dee0f7 2027 #define RTC_SSR_SS ((uint32_t)0x0000FFFF)
ommpy 0:d383e2dee0f7 2028
ommpy 0:d383e2dee0f7 2029 /******************** Bits definition for RTC_SHIFTR register **************/
ommpy 0:d383e2dee0f7 2030 #define RTC_SHIFTR_SUBFS ((uint32_t)0x00007FFF)
ommpy 0:d383e2dee0f7 2031 #define RTC_SHIFTR_ADD1S ((uint32_t)0x80000000)
ommpy 0:d383e2dee0f7 2032
ommpy 0:d383e2dee0f7 2033 /******************** Bits definition for RTC_TSTR register ****************/
ommpy 0:d383e2dee0f7 2034 #define RTC_TSTR_PM ((uint32_t)0x00400000)
ommpy 0:d383e2dee0f7 2035 #define RTC_TSTR_HT ((uint32_t)0x00300000)
ommpy 0:d383e2dee0f7 2036 #define RTC_TSTR_HT_0 ((uint32_t)0x00100000)
ommpy 0:d383e2dee0f7 2037 #define RTC_TSTR_HT_1 ((uint32_t)0x00200000)
ommpy 0:d383e2dee0f7 2038 #define RTC_TSTR_HU ((uint32_t)0x000F0000)
ommpy 0:d383e2dee0f7 2039 #define RTC_TSTR_HU_0 ((uint32_t)0x00010000)
ommpy 0:d383e2dee0f7 2040 #define RTC_TSTR_HU_1 ((uint32_t)0x00020000)
ommpy 0:d383e2dee0f7 2041 #define RTC_TSTR_HU_2 ((uint32_t)0x00040000)
ommpy 0:d383e2dee0f7 2042 #define RTC_TSTR_HU_3 ((uint32_t)0x00080000)
ommpy 0:d383e2dee0f7 2043 #define RTC_TSTR_MNT ((uint32_t)0x00007000)
ommpy 0:d383e2dee0f7 2044 #define RTC_TSTR_MNT_0 ((uint32_t)0x00001000)
ommpy 0:d383e2dee0f7 2045 #define RTC_TSTR_MNT_1 ((uint32_t)0x00002000)
ommpy 0:d383e2dee0f7 2046 #define RTC_TSTR_MNT_2 ((uint32_t)0x00004000)
ommpy 0:d383e2dee0f7 2047 #define RTC_TSTR_MNU ((uint32_t)0x00000F00)
ommpy 0:d383e2dee0f7 2048 #define RTC_TSTR_MNU_0 ((uint32_t)0x00000100)
ommpy 0:d383e2dee0f7 2049 #define RTC_TSTR_MNU_1 ((uint32_t)0x00000200)
ommpy 0:d383e2dee0f7 2050 #define RTC_TSTR_MNU_2 ((uint32_t)0x00000400)
ommpy 0:d383e2dee0f7 2051 #define RTC_TSTR_MNU_3 ((uint32_t)0x00000800)
ommpy 0:d383e2dee0f7 2052 #define RTC_TSTR_ST ((uint32_t)0x00000070)
ommpy 0:d383e2dee0f7 2053 #define RTC_TSTR_ST_0 ((uint32_t)0x00000010)
ommpy 0:d383e2dee0f7 2054 #define RTC_TSTR_ST_1 ((uint32_t)0x00000020)
ommpy 0:d383e2dee0f7 2055 #define RTC_TSTR_ST_2 ((uint32_t)0x00000040)
ommpy 0:d383e2dee0f7 2056 #define RTC_TSTR_SU ((uint32_t)0x0000000F)
ommpy 0:d383e2dee0f7 2057 #define RTC_TSTR_SU_0 ((uint32_t)0x00000001)
ommpy 0:d383e2dee0f7 2058 #define RTC_TSTR_SU_1 ((uint32_t)0x00000002)
ommpy 0:d383e2dee0f7 2059 #define RTC_TSTR_SU_2 ((uint32_t)0x00000004)
ommpy 0:d383e2dee0f7 2060 #define RTC_TSTR_SU_3 ((uint32_t)0x00000008)
ommpy 0:d383e2dee0f7 2061
ommpy 0:d383e2dee0f7 2062 /******************** Bits definition for RTC_TSDR register ****************/
ommpy 0:d383e2dee0f7 2063 #define RTC_TSDR_WDU ((uint32_t)0x0000E000)
ommpy 0:d383e2dee0f7 2064 #define RTC_TSDR_WDU_0 ((uint32_t)0x00002000)
ommpy 0:d383e2dee0f7 2065 #define RTC_TSDR_WDU_1 ((uint32_t)0x00004000)
ommpy 0:d383e2dee0f7 2066 #define RTC_TSDR_WDU_2 ((uint32_t)0x00008000)
ommpy 0:d383e2dee0f7 2067 #define RTC_TSDR_MT ((uint32_t)0x00001000)
ommpy 0:d383e2dee0f7 2068 #define RTC_TSDR_MU ((uint32_t)0x00000F00)
ommpy 0:d383e2dee0f7 2069 #define RTC_TSDR_MU_0 ((uint32_t)0x00000100)
ommpy 0:d383e2dee0f7 2070 #define RTC_TSDR_MU_1 ((uint32_t)0x00000200)
ommpy 0:d383e2dee0f7 2071 #define RTC_TSDR_MU_2 ((uint32_t)0x00000400)
ommpy 0:d383e2dee0f7 2072 #define RTC_TSDR_MU_3 ((uint32_t)0x00000800)
ommpy 0:d383e2dee0f7 2073 #define RTC_TSDR_DT ((uint32_t)0x00000030)
ommpy 0:d383e2dee0f7 2074 #define RTC_TSDR_DT_0 ((uint32_t)0x00000010)
ommpy 0:d383e2dee0f7 2075 #define RTC_TSDR_DT_1 ((uint32_t)0x00000020)
ommpy 0:d383e2dee0f7 2076 #define RTC_TSDR_DU ((uint32_t)0x0000000F)
ommpy 0:d383e2dee0f7 2077 #define RTC_TSDR_DU_0 ((uint32_t)0x00000001)
ommpy 0:d383e2dee0f7 2078 #define RTC_TSDR_DU_1 ((uint32_t)0x00000002)
ommpy 0:d383e2dee0f7 2079 #define RTC_TSDR_DU_2 ((uint32_t)0x00000004)
ommpy 0:d383e2dee0f7 2080 #define RTC_TSDR_DU_3 ((uint32_t)0x00000008)
ommpy 0:d383e2dee0f7 2081
ommpy 0:d383e2dee0f7 2082 /******************** Bits definition for RTC_TSSSR register ***************/
ommpy 0:d383e2dee0f7 2083 #define RTC_TSSSR_SS ((uint32_t)0x0000FFFF)
ommpy 0:d383e2dee0f7 2084
ommpy 0:d383e2dee0f7 2085 /******************** Bits definition for RTC_CALR register ****************/
ommpy 0:d383e2dee0f7 2086 #define RTC_CALR_CALP ((uint32_t)0x00008000)
ommpy 0:d383e2dee0f7 2087 #define RTC_CALR_CALW8 ((uint32_t)0x00004000)
ommpy 0:d383e2dee0f7 2088 #define RTC_CALR_CALW16 ((uint32_t)0x00002000)
ommpy 0:d383e2dee0f7 2089 #define RTC_CALR_CALM ((uint32_t)0x000001FF)
ommpy 0:d383e2dee0f7 2090 #define RTC_CALR_CALM_0 ((uint32_t)0x00000001)
ommpy 0:d383e2dee0f7 2091 #define RTC_CALR_CALM_1 ((uint32_t)0x00000002)
ommpy 0:d383e2dee0f7 2092 #define RTC_CALR_CALM_2 ((uint32_t)0x00000004)
ommpy 0:d383e2dee0f7 2093 #define RTC_CALR_CALM_3 ((uint32_t)0x00000008)
ommpy 0:d383e2dee0f7 2094 #define RTC_CALR_CALM_4 ((uint32_t)0x00000010)
ommpy 0:d383e2dee0f7 2095 #define RTC_CALR_CALM_5 ((uint32_t)0x00000020)
ommpy 0:d383e2dee0f7 2096 #define RTC_CALR_CALM_6 ((uint32_t)0x00000040)
ommpy 0:d383e2dee0f7 2097 #define RTC_CALR_CALM_7 ((uint32_t)0x00000080)
ommpy 0:d383e2dee0f7 2098 #define RTC_CALR_CALM_8 ((uint32_t)0x00000100)
ommpy 0:d383e2dee0f7 2099
ommpy 0:d383e2dee0f7 2100 /******************** Bits definition for RTC_TAFCR register ***************/
ommpy 0:d383e2dee0f7 2101 #define RTC_TAFCR_ALARMOUTTYPE ((uint32_t)0x00040000)
ommpy 0:d383e2dee0f7 2102 #define RTC_TAFCR_TAMPPUDIS ((uint32_t)0x00008000)
ommpy 0:d383e2dee0f7 2103 #define RTC_TAFCR_TAMPPRCH ((uint32_t)0x00006000)
ommpy 0:d383e2dee0f7 2104 #define RTC_TAFCR_TAMPPRCH_0 ((uint32_t)0x00002000)
ommpy 0:d383e2dee0f7 2105 #define RTC_TAFCR_TAMPPRCH_1 ((uint32_t)0x00004000)
ommpy 0:d383e2dee0f7 2106 #define RTC_TAFCR_TAMPFLT ((uint32_t)0x00001800)
ommpy 0:d383e2dee0f7 2107 #define RTC_TAFCR_TAMPFLT_0 ((uint32_t)0x00000800)
ommpy 0:d383e2dee0f7 2108 #define RTC_TAFCR_TAMPFLT_1 ((uint32_t)0x00001000)
ommpy 0:d383e2dee0f7 2109 #define RTC_TAFCR_TAMPFREQ ((uint32_t)0x00000700)
ommpy 0:d383e2dee0f7 2110 #define RTC_TAFCR_TAMPFREQ_0 ((uint32_t)0x00000100)
ommpy 0:d383e2dee0f7 2111 #define RTC_TAFCR_TAMPFREQ_1 ((uint32_t)0x00000200)
ommpy 0:d383e2dee0f7 2112 #define RTC_TAFCR_TAMPFREQ_2 ((uint32_t)0x00000400)
ommpy 0:d383e2dee0f7 2113 #define RTC_TAFCR_TAMPTS ((uint32_t)0x00000080)
ommpy 0:d383e2dee0f7 2114 #define RTC_TAFCR_TAMP2TRG ((uint32_t)0x00000010)
ommpy 0:d383e2dee0f7 2115 #define RTC_TAFCR_TAMP2E ((uint32_t)0x00000008)
ommpy 0:d383e2dee0f7 2116 #define RTC_TAFCR_TAMPIE ((uint32_t)0x00000004)
ommpy 0:d383e2dee0f7 2117 #define RTC_TAFCR_TAMP1TRG ((uint32_t)0x00000002)
ommpy 0:d383e2dee0f7 2118 #define RTC_TAFCR_TAMP1E ((uint32_t)0x00000001)
ommpy 0:d383e2dee0f7 2119
ommpy 0:d383e2dee0f7 2120 /******************** Bits definition for RTC_ALRMASSR register ************/
ommpy 0:d383e2dee0f7 2121 #define RTC_ALRMASSR_MASKSS ((uint32_t)0x0F000000)
ommpy 0:d383e2dee0f7 2122 #define RTC_ALRMASSR_MASKSS_0 ((uint32_t)0x01000000)
ommpy 0:d383e2dee0f7 2123 #define RTC_ALRMASSR_MASKSS_1 ((uint32_t)0x02000000)
ommpy 0:d383e2dee0f7 2124 #define RTC_ALRMASSR_MASKSS_2 ((uint32_t)0x04000000)
ommpy 0:d383e2dee0f7 2125 #define RTC_ALRMASSR_MASKSS_3 ((uint32_t)0x08000000)
ommpy 0:d383e2dee0f7 2126 #define RTC_ALRMASSR_SS ((uint32_t)0x00007FFF)
ommpy 0:d383e2dee0f7 2127
ommpy 0:d383e2dee0f7 2128 /*****************************************************************************/
ommpy 0:d383e2dee0f7 2129 /* */
ommpy 0:d383e2dee0f7 2130 /* Serial Peripheral Interface (SPI) */
ommpy 0:d383e2dee0f7 2131 /* */
ommpy 0:d383e2dee0f7 2132 /*****************************************************************************/
ommpy 0:d383e2dee0f7 2133 /******************* Bit definition for SPI_CR1 register *******************/
ommpy 0:d383e2dee0f7 2134 #define SPI_CR1_CPHA ((uint32_t)0x00000001) /*!< Clock Phase */
ommpy 0:d383e2dee0f7 2135 #define SPI_CR1_CPOL ((uint32_t)0x00000002) /*!< Clock Polarity */
ommpy 0:d383e2dee0f7 2136 #define SPI_CR1_MSTR ((uint32_t)0x00000004) /*!< Master Selection */
ommpy 0:d383e2dee0f7 2137 #define SPI_CR1_BR ((uint32_t)0x00000038) /*!< BR[2:0] bits (Baud Rate Control) */
ommpy 0:d383e2dee0f7 2138 #define SPI_CR1_BR_0 ((uint32_t)0x00000008) /*!< Bit 0 */
ommpy 0:d383e2dee0f7 2139 #define SPI_CR1_BR_1 ((uint32_t)0x00000010) /*!< Bit 1 */
ommpy 0:d383e2dee0f7 2140 #define SPI_CR1_BR_2 ((uint32_t)0x00000020) /*!< Bit 2 */
ommpy 0:d383e2dee0f7 2141 #define SPI_CR1_SPE ((uint32_t)0x00000040) /*!< SPI Enable */
ommpy 0:d383e2dee0f7 2142 #define SPI_CR1_LSBFIRST ((uint32_t)0x00000080) /*!< Frame Format */
ommpy 0:d383e2dee0f7 2143 #define SPI_CR1_SSI ((uint32_t)0x00000100) /*!< Internal slave select */
ommpy 0:d383e2dee0f7 2144 #define SPI_CR1_SSM ((uint32_t)0x00000200) /*!< Software slave management */
ommpy 0:d383e2dee0f7 2145 #define SPI_CR1_RXONLY ((uint32_t)0x00000400) /*!< Receive only */
ommpy 0:d383e2dee0f7 2146 #define SPI_CR1_CRCL ((uint32_t)0x00000800) /*!< CRC Length */
ommpy 0:d383e2dee0f7 2147 #define SPI_CR1_CRCNEXT ((uint32_t)0x00001000) /*!< Transmit CRC next */
ommpy 0:d383e2dee0f7 2148 #define SPI_CR1_CRCEN ((uint32_t)0x00002000) /*!< Hardware CRC calculation enable */
ommpy 0:d383e2dee0f7 2149 #define SPI_CR1_BIDIOE ((uint32_t)0x00004000) /*!< Output enable in bidirectional mode */
ommpy 0:d383e2dee0f7 2150 #define SPI_CR1_BIDIMODE ((uint32_t)0x00008000) /*!< Bidirectional data mode enable */
ommpy 0:d383e2dee0f7 2151
ommpy 0:d383e2dee0f7 2152 /******************* Bit definition for SPI_CR2 register *******************/
ommpy 0:d383e2dee0f7 2153 #define SPI_CR2_RXDMAEN ((uint32_t)0x00000001) /*!< Rx Buffer DMA Enable */
ommpy 0:d383e2dee0f7 2154 #define SPI_CR2_TXDMAEN ((uint32_t)0x00000002) /*!< Tx Buffer DMA Enable */
ommpy 0:d383e2dee0f7 2155 #define SPI_CR2_SSOE ((uint32_t)0x00000004) /*!< SS Output Enable */
ommpy 0:d383e2dee0f7 2156 #define SPI_CR2_NSSP ((uint32_t)0x00000008) /*!< NSS pulse management Enable */
ommpy 0:d383e2dee0f7 2157 #define SPI_CR2_FRF ((uint32_t)0x00000010) /*!< Frame Format Enable */
ommpy 0:d383e2dee0f7 2158 #define SPI_CR2_ERRIE ((uint32_t)0x00000020) /*!< Error Interrupt Enable */
ommpy 0:d383e2dee0f7 2159 #define SPI_CR2_RXNEIE ((uint32_t)0x00000040) /*!< RX buffer Not Empty Interrupt Enable */
ommpy 0:d383e2dee0f7 2160 #define SPI_CR2_TXEIE ((uint32_t)0x00000080) /*!< Tx buffer Empty Interrupt Enable */
ommpy 0:d383e2dee0f7 2161 #define SPI_CR2_DS ((uint32_t)0x00000F00) /*!< DS[3:0] Data Size */
ommpy 0:d383e2dee0f7 2162 #define SPI_CR2_DS_0 ((uint32_t)0x00000100) /*!< Bit 0 */
ommpy 0:d383e2dee0f7 2163 #define SPI_CR2_DS_1 ((uint32_t)0x00000200) /*!< Bit 1 */
ommpy 0:d383e2dee0f7 2164 #define SPI_CR2_DS_2 ((uint32_t)0x00000400) /*!< Bit 2 */
ommpy 0:d383e2dee0f7 2165 #define SPI_CR2_DS_3 ((uint32_t)0x00000800) /*!< Bit 3 */
ommpy 0:d383e2dee0f7 2166 #define SPI_CR2_FRXTH ((uint32_t)0x00001000) /*!< FIFO reception Threshold */
ommpy 0:d383e2dee0f7 2167 #define SPI_CR2_LDMARX ((uint32_t)0x00002000) /*!< Last DMA transfer for reception */
ommpy 0:d383e2dee0f7 2168 #define SPI_CR2_LDMATX ((uint32_t)0x00004000) /*!< Last DMA transfer for transmission */
ommpy 0:d383e2dee0f7 2169
ommpy 0:d383e2dee0f7 2170 /******************** Bit definition for SPI_SR register *******************/
ommpy 0:d383e2dee0f7 2171 #define SPI_SR_RXNE ((uint32_t)0x00000001) /*!< Receive buffer Not Empty */
ommpy 0:d383e2dee0f7 2172 #define SPI_SR_TXE ((uint32_t)0x00000002) /*!< Transmit buffer Empty */
ommpy 0:d383e2dee0f7 2173 #define SPI_SR_CHSIDE ((uint32_t)0x00000004) /*!< Channel side */
ommpy 0:d383e2dee0f7 2174 #define SPI_SR_UDR ((uint32_t)0x00000008) /*!< Underrun flag */
ommpy 0:d383e2dee0f7 2175 #define SPI_SR_CRCERR ((uint32_t)0x00000010) /*!< CRC Error flag */
ommpy 0:d383e2dee0f7 2176 #define SPI_SR_MODF ((uint32_t)0x00000020) /*!< Mode fault */
ommpy 0:d383e2dee0f7 2177 #define SPI_SR_OVR ((uint32_t)0x00000040) /*!< Overrun flag */
ommpy 0:d383e2dee0f7 2178 #define SPI_SR_BSY ((uint32_t)0x00000080) /*!< Busy flag */
ommpy 0:d383e2dee0f7 2179 #define SPI_SR_FRE ((uint32_t)0x00000100) /*!< TI frame format error */
ommpy 0:d383e2dee0f7 2180 #define SPI_SR_FRLVL ((uint32_t)0x00000600) /*!< FIFO Reception Level */
ommpy 0:d383e2dee0f7 2181 #define SPI_SR_FRLVL_0 ((uint32_t)0x00000200) /*!< Bit 0 */
ommpy 0:d383e2dee0f7 2182 #define SPI_SR_FRLVL_1 ((uint32_t)0x00000400) /*!< Bit 1 */
ommpy 0:d383e2dee0f7 2183 #define SPI_SR_FTLVL ((uint32_t)0x00001800) /*!< FIFO Transmission Level */
ommpy 0:d383e2dee0f7 2184 #define SPI_SR_FTLVL_0 ((uint32_t)0x00000800) /*!< Bit 0 */
ommpy 0:d383e2dee0f7 2185 #define SPI_SR_FTLVL_1 ((uint32_t)0x00001000) /*!< Bit 1 */
ommpy 0:d383e2dee0f7 2186
ommpy 0:d383e2dee0f7 2187 /******************** Bit definition for SPI_DR register *******************/
ommpy 0:d383e2dee0f7 2188 #define SPI_DR_DR ((uint32_t)0xFFFFFFFF) /*!< Data Register */
ommpy 0:d383e2dee0f7 2189
ommpy 0:d383e2dee0f7 2190 /******************* Bit definition for SPI_CRCPR register *****************/
ommpy 0:d383e2dee0f7 2191 #define SPI_CRCPR_CRCPOLY ((uint32_t)0xFFFFFFFF) /*!< CRC polynomial register */
ommpy 0:d383e2dee0f7 2192
ommpy 0:d383e2dee0f7 2193 /****************** Bit definition for SPI_RXCRCR register *****************/
ommpy 0:d383e2dee0f7 2194 #define SPI_RXCRCR_RXCRC ((uint32_t)0xFFFFFFFF) /*!< Rx CRC Register */
ommpy 0:d383e2dee0f7 2195
ommpy 0:d383e2dee0f7 2196 /****************** Bit definition for SPI_TXCRCR register *****************/
ommpy 0:d383e2dee0f7 2197 #define SPI_TXCRCR_TXCRC ((uint32_t)0xFFFFFFFF) /*!< Tx CRC Register */
ommpy 0:d383e2dee0f7 2198
ommpy 0:d383e2dee0f7 2199 /****************** Bit definition for SPI_I2SCFGR register ****************/
ommpy 0:d383e2dee0f7 2200 #define SPI_I2SCFGR_CHLEN ((uint32_t)0x00000001) /*!<Channel length (number of bits per audio channel) */
ommpy 0:d383e2dee0f7 2201 #define SPI_I2SCFGR_DATLEN ((uint32_t)0x00000006) /*!<DATLEN[1:0] bits (Data length to be transferred) */
ommpy 0:d383e2dee0f7 2202 #define SPI_I2SCFGR_DATLEN_0 ((uint32_t)0x00000002) /*!<Bit 0 */
ommpy 0:d383e2dee0f7 2203 #define SPI_I2SCFGR_DATLEN_1 ((uint32_t)0x00000004) /*!<Bit 1 */
ommpy 0:d383e2dee0f7 2204 #define SPI_I2SCFGR_CKPOL ((uint32_t)0x00000008) /*!<steady state clock polarity */
ommpy 0:d383e2dee0f7 2205 #define SPI_I2SCFGR_I2SSTD ((uint32_t)0x00000030) /*!<I2SSTD[1:0] bits (I2S standard selection) */
ommpy 0:d383e2dee0f7 2206 #define SPI_I2SCFGR_I2SSTD_0 ((uint32_t)0x00000010) /*!<Bit 0 */
ommpy 0:d383e2dee0f7 2207 #define SPI_I2SCFGR_I2SSTD_1 ((uint32_t)0x00000020) /*!<Bit 1 */
ommpy 0:d383e2dee0f7 2208 #define SPI_I2SCFGR_PCMSYNC ((uint32_t)0x00000080) /*!<PCM frame synchronization */
ommpy 0:d383e2dee0f7 2209 #define SPI_I2SCFGR_I2SCFG ((uint32_t)0x00000300) /*!<I2SCFG[1:0] bits (I2S configuration mode) */
ommpy 0:d383e2dee0f7 2210 #define SPI_I2SCFGR_I2SCFG_0 ((uint32_t)0x00000100) /*!<Bit 0 */
ommpy 0:d383e2dee0f7 2211 #define SPI_I2SCFGR_I2SCFG_1 ((uint32_t)0x00000200) /*!<Bit 1 */
ommpy 0:d383e2dee0f7 2212 #define SPI_I2SCFGR_I2SE ((uint32_t)0x00000400) /*!<I2S Enable */
ommpy 0:d383e2dee0f7 2213 #define SPI_I2SCFGR_I2SMOD ((uint32_t)0x00000800) /*!<I2S mode selection */
ommpy 0:d383e2dee0f7 2214
ommpy 0:d383e2dee0f7 2215 /****************** Bit definition for SPI_I2SPR register ******************/
ommpy 0:d383e2dee0f7 2216 #define SPI_I2SPR_I2SDIV ((uint32_t)0x000000FF) /*!<I2S Linear prescaler */
ommpy 0:d383e2dee0f7 2217 #define SPI_I2SPR_ODD ((uint32_t)0x00000100) /*!<Odd factor for the prescaler */
ommpy 0:d383e2dee0f7 2218 #define SPI_I2SPR_MCKOE ((uint32_t)0x00000200) /*!<Master Clock Output Enable */
ommpy 0:d383e2dee0f7 2219
ommpy 0:d383e2dee0f7 2220 /*****************************************************************************/
ommpy 0:d383e2dee0f7 2221 /* */
ommpy 0:d383e2dee0f7 2222 /* System Configuration (SYSCFG) */
ommpy 0:d383e2dee0f7 2223 /* */
ommpy 0:d383e2dee0f7 2224 /*****************************************************************************/
ommpy 0:d383e2dee0f7 2225 /***************** Bit definition for SYSCFG_CFGR1 register ****************/
ommpy 0:d383e2dee0f7 2226 #define SYSCFG_CFGR1_MEM_MODE ((uint32_t)0x00000003) /*!< SYSCFG_Memory Remap Config */
ommpy 0:d383e2dee0f7 2227 #define SYSCFG_CFGR1_MEM_MODE_0 ((uint32_t)0x00000001) /*!< SYSCFG_Memory Remap Config Bit 0 */
ommpy 0:d383e2dee0f7 2228 #define SYSCFG_CFGR1_MEM_MODE_1 ((uint32_t)0x00000002) /*!< SYSCFG_Memory Remap Config Bit 1 */
ommpy 0:d383e2dee0f7 2229
ommpy 0:d383e2dee0f7 2230
ommpy 0:d383e2dee0f7 2231 #define SYSCFG_CFGR1_DMA_RMP ((uint32_t)0x00001F00) /*!< DMA remap mask */
ommpy 0:d383e2dee0f7 2232 #define SYSCFG_CFGR1_ADC_DMA_RMP ((uint32_t)0x00000100) /*!< ADC DMA remap */
ommpy 0:d383e2dee0f7 2233 #define SYSCFG_CFGR1_USART1TX_DMA_RMP ((uint32_t)0x00000200) /*!< USART1 TX DMA remap */
ommpy 0:d383e2dee0f7 2234 #define SYSCFG_CFGR1_USART1RX_DMA_RMP ((uint32_t)0x00000400) /*!< USART1 RX DMA remap */
ommpy 0:d383e2dee0f7 2235 #define SYSCFG_CFGR1_TIM16_DMA_RMP ((uint32_t)0x00000800) /*!< Timer 16 DMA remap */
ommpy 0:d383e2dee0f7 2236 #define SYSCFG_CFGR1_TIM17_DMA_RMP ((uint32_t)0x00001000) /*!< Timer 17 DMA remap */
ommpy 0:d383e2dee0f7 2237
ommpy 0:d383e2dee0f7 2238 #define SYSCFG_CFGR1_I2C_FMP_PB6 ((uint32_t)0x00010000) /*!< I2C PB6 Fast mode plus */
ommpy 0:d383e2dee0f7 2239 #define SYSCFG_CFGR1_I2C_FMP_PB7 ((uint32_t)0x00020000) /*!< I2C PB7 Fast mode plus */
ommpy 0:d383e2dee0f7 2240 #define SYSCFG_CFGR1_I2C_FMP_PB8 ((uint32_t)0x00040000) /*!< I2C PB8 Fast mode plus */
ommpy 0:d383e2dee0f7 2241 #define SYSCFG_CFGR1_I2C_FMP_PB9 ((uint32_t)0x00080000) /*!< I2C PB9 Fast mode plus */
ommpy 0:d383e2dee0f7 2242
ommpy 0:d383e2dee0f7 2243
ommpy 0:d383e2dee0f7 2244 /***************** Bit definition for SYSCFG_EXTICR1 register **************/
ommpy 0:d383e2dee0f7 2245 #define SYSCFG_EXTICR1_EXTI0 ((uint32_t)0x0000000F) /*!< EXTI 0 configuration */
ommpy 0:d383e2dee0f7 2246 #define SYSCFG_EXTICR1_EXTI1 ((uint32_t)0x000000F0) /*!< EXTI 1 configuration */
ommpy 0:d383e2dee0f7 2247 #define SYSCFG_EXTICR1_EXTI2 ((uint32_t)0x00000F00) /*!< EXTI 2 configuration */
ommpy 0:d383e2dee0f7 2248 #define SYSCFG_EXTICR1_EXTI3 ((uint32_t)0x0000F000) /*!< EXTI 3 configuration */
ommpy 0:d383e2dee0f7 2249
ommpy 0:d383e2dee0f7 2250 /**
ommpy 0:d383e2dee0f7 2251 * @brief EXTI0 configuration
ommpy 0:d383e2dee0f7 2252 */
ommpy 0:d383e2dee0f7 2253 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!< PA[0] pin */
ommpy 0:d383e2dee0f7 2254 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!< PB[0] pin */
ommpy 0:d383e2dee0f7 2255 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!< PC[0] pin */
ommpy 0:d383e2dee0f7 2256 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!< PD[0] pin */
ommpy 0:d383e2dee0f7 2257 #define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!< PF[0] pin */
ommpy 0:d383e2dee0f7 2258
ommpy 0:d383e2dee0f7 2259 /**
ommpy 0:d383e2dee0f7 2260 * @brief EXTI1 configuration
ommpy 0:d383e2dee0f7 2261 */
ommpy 0:d383e2dee0f7 2262 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!< PA[1] pin */
ommpy 0:d383e2dee0f7 2263 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!< PB[1] pin */
ommpy 0:d383e2dee0f7 2264 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!< PC[1] pin */
ommpy 0:d383e2dee0f7 2265 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!< PD[1] pin */
ommpy 0:d383e2dee0f7 2266 #define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!< PF[1] pin */
ommpy 0:d383e2dee0f7 2267
ommpy 0:d383e2dee0f7 2268 /**
ommpy 0:d383e2dee0f7 2269 * @brief EXTI2 configuration
ommpy 0:d383e2dee0f7 2270 */
ommpy 0:d383e2dee0f7 2271 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!< PA[2] pin */
ommpy 0:d383e2dee0f7 2272 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!< PB[2] pin */
ommpy 0:d383e2dee0f7 2273 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!< PC[2] pin */
ommpy 0:d383e2dee0f7 2274 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!< PD[2] pin */
ommpy 0:d383e2dee0f7 2275 #define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!< PF[2] pin */
ommpy 0:d383e2dee0f7 2276
ommpy 0:d383e2dee0f7 2277 /**
ommpy 0:d383e2dee0f7 2278 * @brief EXTI3 configuration
ommpy 0:d383e2dee0f7 2279 */
ommpy 0:d383e2dee0f7 2280 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!< PA[3] pin */
ommpy 0:d383e2dee0f7 2281 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!< PB[3] pin */
ommpy 0:d383e2dee0f7 2282 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!< PC[3] pin */
ommpy 0:d383e2dee0f7 2283 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!< PD[3] pin */
ommpy 0:d383e2dee0f7 2284 #define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!< PF[3] pin */
ommpy 0:d383e2dee0f7 2285
ommpy 0:d383e2dee0f7 2286 /***************** Bit definition for SYSCFG_EXTICR2 register **************/
ommpy 0:d383e2dee0f7 2287 #define SYSCFG_EXTICR2_EXTI4 ((uint32_t)0x0000000F) /*!< EXTI 4 configuration */
ommpy 0:d383e2dee0f7 2288 #define SYSCFG_EXTICR2_EXTI5 ((uint32_t)0x000000F0) /*!< EXTI 5 configuration */
ommpy 0:d383e2dee0f7 2289 #define SYSCFG_EXTICR2_EXTI6 ((uint32_t)0x00000F00) /*!< EXTI 6 configuration */
ommpy 0:d383e2dee0f7 2290 #define SYSCFG_EXTICR2_EXTI7 ((uint32_t)0x0000F000) /*!< EXTI 7 configuration */
ommpy 0:d383e2dee0f7 2291
ommpy 0:d383e2dee0f7 2292 /**
ommpy 0:d383e2dee0f7 2293 * @brief EXTI4 configuration
ommpy 0:d383e2dee0f7 2294 */
ommpy 0:d383e2dee0f7 2295 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!< PA[4] pin */
ommpy 0:d383e2dee0f7 2296 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!< PB[4] pin */
ommpy 0:d383e2dee0f7 2297 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!< PC[4] pin */
ommpy 0:d383e2dee0f7 2298 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!< PD[4] pin */
ommpy 0:d383e2dee0f7 2299 #define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!< PF[4] pin */
ommpy 0:d383e2dee0f7 2300
ommpy 0:d383e2dee0f7 2301 /**
ommpy 0:d383e2dee0f7 2302 * @brief EXTI5 configuration
ommpy 0:d383e2dee0f7 2303 */
ommpy 0:d383e2dee0f7 2304 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!< PA[5] pin */
ommpy 0:d383e2dee0f7 2305 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!< PB[5] pin */
ommpy 0:d383e2dee0f7 2306 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!< PC[5] pin */
ommpy 0:d383e2dee0f7 2307 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!< PD[5] pin */
ommpy 0:d383e2dee0f7 2308 #define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!< PF[5] pin */
ommpy 0:d383e2dee0f7 2309
ommpy 0:d383e2dee0f7 2310 /**
ommpy 0:d383e2dee0f7 2311 * @brief EXTI6 configuration
ommpy 0:d383e2dee0f7 2312 */
ommpy 0:d383e2dee0f7 2313 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!< PA[6] pin */
ommpy 0:d383e2dee0f7 2314 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!< PB[6] pin */
ommpy 0:d383e2dee0f7 2315 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!< PC[6] pin */
ommpy 0:d383e2dee0f7 2316 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!< PD[6] pin */
ommpy 0:d383e2dee0f7 2317 #define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!< PF[6] pin */
ommpy 0:d383e2dee0f7 2318
ommpy 0:d383e2dee0f7 2319 /**
ommpy 0:d383e2dee0f7 2320 * @brief EXTI7 configuration
ommpy 0:d383e2dee0f7 2321 */
ommpy 0:d383e2dee0f7 2322 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!< PA[7] pin */
ommpy 0:d383e2dee0f7 2323 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!< PB[7] pin */
ommpy 0:d383e2dee0f7 2324 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!< PC[7] pin */
ommpy 0:d383e2dee0f7 2325 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!< PD[7] pin */
ommpy 0:d383e2dee0f7 2326 #define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!< PF[7] pin */
ommpy 0:d383e2dee0f7 2327
ommpy 0:d383e2dee0f7 2328 /***************** Bit definition for SYSCFG_EXTICR3 register **************/
ommpy 0:d383e2dee0f7 2329 #define SYSCFG_EXTICR3_EXTI8 ((uint32_t)0x0000000F) /*!< EXTI 8 configuration */
ommpy 0:d383e2dee0f7 2330 #define SYSCFG_EXTICR3_EXTI9 ((uint32_t)0x000000F0) /*!< EXTI 9 configuration */
ommpy 0:d383e2dee0f7 2331 #define SYSCFG_EXTICR3_EXTI10 ((uint32_t)0x00000F00) /*!< EXTI 10 configuration */
ommpy 0:d383e2dee0f7 2332 #define SYSCFG_EXTICR3_EXTI11 ((uint32_t)0x0000F000) /*!< EXTI 11 configuration */
ommpy 0:d383e2dee0f7 2333
ommpy 0:d383e2dee0f7 2334 /**
ommpy 0:d383e2dee0f7 2335 * @brief EXTI8 configuration
ommpy 0:d383e2dee0f7 2336 */
ommpy 0:d383e2dee0f7 2337 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!< PA[8] pin */
ommpy 0:d383e2dee0f7 2338 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!< PB[8] pin */
ommpy 0:d383e2dee0f7 2339 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!< PC[8] pin */
ommpy 0:d383e2dee0f7 2340 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!< PD[8] pin */
ommpy 0:d383e2dee0f7 2341 #define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!< PF[8] pin */
ommpy 0:d383e2dee0f7 2342
ommpy 0:d383e2dee0f7 2343 /**
ommpy 0:d383e2dee0f7 2344 * @brief EXTI9 configuration
ommpy 0:d383e2dee0f7 2345 */
ommpy 0:d383e2dee0f7 2346 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!< PA[9] pin */
ommpy 0:d383e2dee0f7 2347 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!< PB[9] pin */
ommpy 0:d383e2dee0f7 2348 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!< PC[9] pin */
ommpy 0:d383e2dee0f7 2349 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!< PD[9] pin */
ommpy 0:d383e2dee0f7 2350 #define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!< PF[9] pin */
ommpy 0:d383e2dee0f7 2351
ommpy 0:d383e2dee0f7 2352 /**
ommpy 0:d383e2dee0f7 2353 * @brief EXTI10 configuration
ommpy 0:d383e2dee0f7 2354 */
ommpy 0:d383e2dee0f7 2355 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!< PA[10] pin */
ommpy 0:d383e2dee0f7 2356 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!< PB[10] pin */
ommpy 0:d383e2dee0f7 2357 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!< PC[10] pin */
ommpy 0:d383e2dee0f7 2358 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!< PD[10] pin */
ommpy 0:d383e2dee0f7 2359 #define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!< PF[10] pin */
ommpy 0:d383e2dee0f7 2360
ommpy 0:d383e2dee0f7 2361 /**
ommpy 0:d383e2dee0f7 2362 * @brief EXTI11 configuration
ommpy 0:d383e2dee0f7 2363 */
ommpy 0:d383e2dee0f7 2364 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!< PA[11] pin */
ommpy 0:d383e2dee0f7 2365 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!< PB[11] pin */
ommpy 0:d383e2dee0f7 2366 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!< PC[11] pin */
ommpy 0:d383e2dee0f7 2367 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!< PD[11] pin */
ommpy 0:d383e2dee0f7 2368 #define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!< PF[11] pin */
ommpy 0:d383e2dee0f7 2369
ommpy 0:d383e2dee0f7 2370 /***************** Bit definition for SYSCFG_EXTICR4 register **************/
ommpy 0:d383e2dee0f7 2371 #define SYSCFG_EXTICR4_EXTI12 ((uint32_t)0x0000000F) /*!< EXTI 12 configuration */
ommpy 0:d383e2dee0f7 2372 #define SYSCFG_EXTICR4_EXTI13 ((uint32_t)0x000000F0) /*!< EXTI 13 configuration */
ommpy 0:d383e2dee0f7 2373 #define SYSCFG_EXTICR4_EXTI14 ((uint32_t)0x00000F00) /*!< EXTI 14 configuration */
ommpy 0:d383e2dee0f7 2374 #define SYSCFG_EXTICR4_EXTI15 ((uint32_t)0x0000F000) /*!< EXTI 15 configuration */
ommpy 0:d383e2dee0f7 2375
ommpy 0:d383e2dee0f7 2376 /**
ommpy 0:d383e2dee0f7 2377 * @brief EXTI12 configuration
ommpy 0:d383e2dee0f7 2378 */
ommpy 0:d383e2dee0f7 2379 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!< PA[12] pin */
ommpy 0:d383e2dee0f7 2380 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!< PB[12] pin */
ommpy 0:d383e2dee0f7 2381 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!< PC[12] pin */
ommpy 0:d383e2dee0f7 2382 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!< PD[12] pin */
ommpy 0:d383e2dee0f7 2383 #define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!< PF[12] pin */
ommpy 0:d383e2dee0f7 2384
ommpy 0:d383e2dee0f7 2385 /**
ommpy 0:d383e2dee0f7 2386 * @brief EXTI13 configuration
ommpy 0:d383e2dee0f7 2387 */
ommpy 0:d383e2dee0f7 2388 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!< PA[13] pin */
ommpy 0:d383e2dee0f7 2389 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!< PB[13] pin */
ommpy 0:d383e2dee0f7 2390 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!< PC[13] pin */
ommpy 0:d383e2dee0f7 2391 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!< PD[13] pin */
ommpy 0:d383e2dee0f7 2392 #define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!< PF[13] pin */
ommpy 0:d383e2dee0f7 2393
ommpy 0:d383e2dee0f7 2394 /**
ommpy 0:d383e2dee0f7 2395 * @brief EXTI14 configuration
ommpy 0:d383e2dee0f7 2396 */
ommpy 0:d383e2dee0f7 2397 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!< PA[14] pin */
ommpy 0:d383e2dee0f7 2398 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!< PB[14] pin */
ommpy 0:d383e2dee0f7 2399 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!< PC[14] pin */
ommpy 0:d383e2dee0f7 2400 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!< PD[14] pin */
ommpy 0:d383e2dee0f7 2401 #define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!< PF[14] pin */
ommpy 0:d383e2dee0f7 2402
ommpy 0:d383e2dee0f7 2403 /**
ommpy 0:d383e2dee0f7 2404 * @brief EXTI15 configuration
ommpy 0:d383e2dee0f7 2405 */
ommpy 0:d383e2dee0f7 2406 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!< PA[15] pin */
ommpy 0:d383e2dee0f7 2407 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!< PB[15] pin */
ommpy 0:d383e2dee0f7 2408 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!< PC[15] pin */
ommpy 0:d383e2dee0f7 2409 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!< PD[15] pin */
ommpy 0:d383e2dee0f7 2410 #define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!< PF[15] pin */
ommpy 0:d383e2dee0f7 2411
ommpy 0:d383e2dee0f7 2412 /***************** Bit definition for SYSCFG_CFGR2 register ****************/
ommpy 0:d383e2dee0f7 2413 #define SYSCFG_CFGR2_LOCKUP_LOCK ((uint32_t)0x00000001) /*!< Enables and locks the LOCKUP (Hardfault) output of CortexM0 with Break Input of TIMER1 */
ommpy 0:d383e2dee0f7 2414 #define SYSCFG_CFGR2_SRAM_PARITY_LOCK ((uint32_t)0x00000002) /*!< Enables and locks the SRAM_PARITY error signal with Break Input of TIMER1 */
ommpy 0:d383e2dee0f7 2415 #define SYSCFG_CFGR2_SRAM_PEF ((uint32_t)0x00000100) /*!< SRAM Parity error flag */
ommpy 0:d383e2dee0f7 2416 #define SYSCFG_CFGR2_SRAM_PE SYSCFG_CFGR2_SRAM_PEF /*!< SRAM Parity error flag (define maintained for legacy purpose) */
ommpy 0:d383e2dee0f7 2417
ommpy 0:d383e2dee0f7 2418 /*****************************************************************************/
ommpy 0:d383e2dee0f7 2419 /* */
ommpy 0:d383e2dee0f7 2420 /* Timers (TIM) */
ommpy 0:d383e2dee0f7 2421 /* */
ommpy 0:d383e2dee0f7 2422 /*****************************************************************************/
ommpy 0:d383e2dee0f7 2423 /******************* Bit definition for TIM_CR1 register *******************/
ommpy 0:d383e2dee0f7 2424 #define TIM_CR1_CEN ((uint32_t)0x00000001) /*!<Counter enable */
ommpy 0:d383e2dee0f7 2425 #define TIM_CR1_UDIS ((uint32_t)0x00000002) /*!<Update disable */
ommpy 0:d383e2dee0f7 2426 #define TIM_CR1_URS ((uint32_t)0x00000004) /*!<Update request source */
ommpy 0:d383e2dee0f7 2427 #define TIM_CR1_OPM ((uint32_t)0x00000008) /*!<One pulse mode */
ommpy 0:d383e2dee0f7 2428 #define TIM_CR1_DIR ((uint32_t)0x00000010) /*!<Direction */
ommpy 0:d383e2dee0f7 2429
ommpy 0:d383e2dee0f7 2430 #define TIM_CR1_CMS ((uint32_t)0x00000060) /*!<CMS[1:0] bits (Center-aligned mode selection) */
ommpy 0:d383e2dee0f7 2431 #define TIM_CR1_CMS_0 ((uint32_t)0x00000020) /*!<Bit 0 */
ommpy 0:d383e2dee0f7 2432 #define TIM_CR1_CMS_1 ((uint32_t)0x00000040) /*!<Bit 1 */
ommpy 0:d383e2dee0f7 2433
ommpy 0:d383e2dee0f7 2434 #define TIM_CR1_ARPE ((uint32_t)0x00000080) /*!<Auto-reload preload enable */
ommpy 0:d383e2dee0f7 2435
ommpy 0:d383e2dee0f7 2436 #define TIM_CR1_CKD ((uint32_t)0x00000300) /*!<CKD[1:0] bits (clock division) */
ommpy 0:d383e2dee0f7 2437 #define TIM_CR1_CKD_0 ((uint32_t)0x00000100) /*!<Bit 0 */
ommpy 0:d383e2dee0f7 2438 #define TIM_CR1_CKD_1 ((uint32_t)0x00000200) /*!<Bit 1 */
ommpy 0:d383e2dee0f7 2439
ommpy 0:d383e2dee0f7 2440 /******************* Bit definition for TIM_CR2 register *******************/
ommpy 0:d383e2dee0f7 2441 #define TIM_CR2_CCPC ((uint32_t)0x00000001) /*!<Capture/Compare Preloaded Control */
ommpy 0:d383e2dee0f7 2442 #define TIM_CR2_CCUS ((uint32_t)0x00000004) /*!<Capture/Compare Control Update Selection */
ommpy 0:d383e2dee0f7 2443 #define TIM_CR2_CCDS ((uint32_t)0x00000008) /*!<Capture/Compare DMA Selection */
ommpy 0:d383e2dee0f7 2444
ommpy 0:d383e2dee0f7 2445 #define TIM_CR2_MMS ((uint32_t)0x00000070) /*!<MMS[2:0] bits (Master Mode Selection) */
ommpy 0:d383e2dee0f7 2446 #define TIM_CR2_MMS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
ommpy 0:d383e2dee0f7 2447 #define TIM_CR2_MMS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
ommpy 0:d383e2dee0f7 2448 #define TIM_CR2_MMS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
ommpy 0:d383e2dee0f7 2449
ommpy 0:d383e2dee0f7 2450 #define TIM_CR2_TI1S ((uint32_t)0x00000080) /*!<TI1 Selection */
ommpy 0:d383e2dee0f7 2451 #define TIM_CR2_OIS1 ((uint32_t)0x00000100) /*!<Output Idle state 1 (OC1 output) */
ommpy 0:d383e2dee0f7 2452 #define TIM_CR2_OIS1N ((uint32_t)0x00000200) /*!<Output Idle state 1 (OC1N output) */
ommpy 0:d383e2dee0f7 2453 #define TIM_CR2_OIS2 ((uint32_t)0x00000400) /*!<Output Idle state 2 (OC2 output) */
ommpy 0:d383e2dee0f7 2454 #define TIM_CR2_OIS2N ((uint32_t)0x00000800) /*!<Output Idle state 2 (OC2N output) */
ommpy 0:d383e2dee0f7 2455 #define TIM_CR2_OIS3 ((uint32_t)0x00001000) /*!<Output Idle state 3 (OC3 output) */
ommpy 0:d383e2dee0f7 2456 #define TIM_CR2_OIS3N ((uint32_t)0x00002000) /*!<Output Idle state 3 (OC3N output) */
ommpy 0:d383e2dee0f7 2457 #define TIM_CR2_OIS4 ((uint32_t)0x00004000) /*!<Output Idle state 4 (OC4 output) */
ommpy 0:d383e2dee0f7 2458
ommpy 0:d383e2dee0f7 2459 /******************* Bit definition for TIM_SMCR register ******************/
ommpy 0:d383e2dee0f7 2460 #define TIM_SMCR_SMS ((uint32_t)0x00000007) /*!<SMS[2:0] bits (Slave mode selection) */
ommpy 0:d383e2dee0f7 2461 #define TIM_SMCR_SMS_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ommpy 0:d383e2dee0f7 2462 #define TIM_SMCR_SMS_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ommpy 0:d383e2dee0f7 2463 #define TIM_SMCR_SMS_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ommpy 0:d383e2dee0f7 2464
ommpy 0:d383e2dee0f7 2465 #define TIM_SMCR_OCCS ((uint32_t)0x00000008) /*!< OCREF clear selection */
ommpy 0:d383e2dee0f7 2466
ommpy 0:d383e2dee0f7 2467 #define TIM_SMCR_TS ((uint32_t)0x00000070) /*!<TS[2:0] bits (Trigger selection) */
ommpy 0:d383e2dee0f7 2468 #define TIM_SMCR_TS_0 ((uint32_t)0x00000010) /*!<Bit 0 */
ommpy 0:d383e2dee0f7 2469 #define TIM_SMCR_TS_1 ((uint32_t)0x00000020) /*!<Bit 1 */
ommpy 0:d383e2dee0f7 2470 #define TIM_SMCR_TS_2 ((uint32_t)0x00000040) /*!<Bit 2 */
ommpy 0:d383e2dee0f7 2471
ommpy 0:d383e2dee0f7 2472 #define TIM_SMCR_MSM ((uint32_t)0x00000080) /*!<Master/slave mode */
ommpy 0:d383e2dee0f7 2473
ommpy 0:d383e2dee0f7 2474 #define TIM_SMCR_ETF ((uint32_t)0x00000F00) /*!<ETF[3:0] bits (External trigger filter) */
ommpy 0:d383e2dee0f7 2475 #define TIM_SMCR_ETF_0 ((uint32_t)0x00000100) /*!<Bit 0 */
ommpy 0:d383e2dee0f7 2476 #define TIM_SMCR_ETF_1 ((uint32_t)0x00000200) /*!<Bit 1 */
ommpy 0:d383e2dee0f7 2477 #define TIM_SMCR_ETF_2 ((uint32_t)0x00000400) /*!<Bit 2 */
ommpy 0:d383e2dee0f7 2478 #define TIM_SMCR_ETF_3 ((uint32_t)0x00000800) /*!<Bit 3 */
ommpy 0:d383e2dee0f7 2479
ommpy 0:d383e2dee0f7 2480 #define TIM_SMCR_ETPS ((uint32_t)0x00003000) /*!<ETPS[1:0] bits (External trigger prescaler) */
ommpy 0:d383e2dee0f7 2481 #define TIM_SMCR_ETPS_0 ((uint32_t)0x00001000) /*!<Bit 0 */
ommpy 0:d383e2dee0f7 2482 #define TIM_SMCR_ETPS_1 ((uint32_t)0x00002000) /*!<Bit 1 */
ommpy 0:d383e2dee0f7 2483
ommpy 0:d383e2dee0f7 2484 #define TIM_SMCR_ECE ((uint32_t)0x00004000) /*!<External clock enable */
ommpy 0:d383e2dee0f7 2485 #define TIM_SMCR_ETP ((uint32_t)0x00008000) /*!<External trigger polarity */
ommpy 0:d383e2dee0f7 2486
ommpy 0:d383e2dee0f7 2487 /******************* Bit definition for TIM_DIER register ******************/
ommpy 0:d383e2dee0f7 2488 #define TIM_DIER_UIE ((uint32_t)0x00000001) /*!<Update interrupt enable */
ommpy 0:d383e2dee0f7 2489 #define TIM_DIER_CC1IE ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt enable */
ommpy 0:d383e2dee0f7 2490 #define TIM_DIER_CC2IE ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt enable */
ommpy 0:d383e2dee0f7 2491 #define TIM_DIER_CC3IE ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt enable */
ommpy 0:d383e2dee0f7 2492 #define TIM_DIER_CC4IE ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt enable */
ommpy 0:d383e2dee0f7 2493 #define TIM_DIER_COMIE ((uint32_t)0x00000020) /*!<COM interrupt enable */
ommpy 0:d383e2dee0f7 2494 #define TIM_DIER_TIE ((uint32_t)0x00000040) /*!<Trigger interrupt enable */
ommpy 0:d383e2dee0f7 2495 #define TIM_DIER_BIE ((uint32_t)0x00000080) /*!<Break interrupt enable */
ommpy 0:d383e2dee0f7 2496 #define TIM_DIER_UDE ((uint32_t)0x00000100) /*!<Update DMA request enable */
ommpy 0:d383e2dee0f7 2497 #define TIM_DIER_CC1DE ((uint32_t)0x00000200) /*!<Capture/Compare 1 DMA request enable */
ommpy 0:d383e2dee0f7 2498 #define TIM_DIER_CC2DE ((uint32_t)0x00000400) /*!<Capture/Compare 2 DMA request enable */
ommpy 0:d383e2dee0f7 2499 #define TIM_DIER_CC3DE ((uint32_t)0x00000800) /*!<Capture/Compare 3 DMA request enable */
ommpy 0:d383e2dee0f7 2500 #define TIM_DIER_CC4DE ((uint32_t)0x00001000) /*!<Capture/Compare 4 DMA request enable */
ommpy 0:d383e2dee0f7 2501 #define TIM_DIER_COMDE ((uint32_t)0x00002000) /*!<COM DMA request enable */
ommpy 0:d383e2dee0f7 2502 #define TIM_DIER_TDE ((uint32_t)0x00004000) /*!<Trigger DMA request enable */
ommpy 0:d383e2dee0f7 2503
ommpy 0:d383e2dee0f7 2504 /******************** Bit definition for TIM_SR register *******************/
ommpy 0:d383e2dee0f7 2505 #define TIM_SR_UIF ((uint32_t)0x00000001) /*!<Update interrupt Flag */
ommpy 0:d383e2dee0f7 2506 #define TIM_SR_CC1IF ((uint32_t)0x00000002) /*!<Capture/Compare 1 interrupt Flag */
ommpy 0:d383e2dee0f7 2507 #define TIM_SR_CC2IF ((uint32_t)0x00000004) /*!<Capture/Compare 2 interrupt Flag */
ommpy 0:d383e2dee0f7 2508 #define TIM_SR_CC3IF ((uint32_t)0x00000008) /*!<Capture/Compare 3 interrupt Flag */
ommpy 0:d383e2dee0f7 2509 #define TIM_SR_CC4IF ((uint32_t)0x00000010) /*!<Capture/Compare 4 interrupt Flag */
ommpy 0:d383e2dee0f7 2510 #define TIM_SR_COMIF ((uint32_t)0x00000020) /*!<COM interrupt Flag */
ommpy 0:d383e2dee0f7 2511 #define TIM_SR_TIF ((uint32_t)0x00000040) /*!<Trigger interrupt Flag */
ommpy 0:d383e2dee0f7 2512 #define TIM_SR_BIF ((uint32_t)0x00000080) /*!<Break interrupt Flag */
ommpy 0:d383e2dee0f7 2513 #define TIM_SR_CC1OF ((uint32_t)0x00000200) /*!<Capture/Compare 1 Overcapture Flag */
ommpy 0:d383e2dee0f7 2514 #define TIM_SR_CC2OF ((uint32_t)0x00000400) /*!<Capture/Compare 2 Overcapture Flag */
ommpy 0:d383e2dee0f7 2515 #define TIM_SR_CC3OF ((uint32_t)0x00000800) /*!<Capture/Compare 3 Overcapture Flag */
ommpy 0:d383e2dee0f7 2516 #define TIM_SR_CC4OF ((uint32_t)0x00001000) /*!<Capture/Compare 4 Overcapture Flag */
ommpy 0:d383e2dee0f7 2517
ommpy 0:d383e2dee0f7 2518 /******************* Bit definition for TIM_EGR register *******************/
ommpy 0:d383e2dee0f7 2519 #define TIM_EGR_UG ((uint32_t)0x00000001) /*!<Update Generation */
ommpy 0:d383e2dee0f7 2520 #define TIM_EGR_CC1G ((uint32_t)0x00000002) /*!<Capture/Compare 1 Generation */
ommpy 0:d383e2dee0f7 2521 #define TIM_EGR_CC2G ((uint32_t)0x00000004) /*!<Capture/Compare 2 Generation */
ommpy 0:d383e2dee0f7 2522 #define TIM_EGR_CC3G ((uint32_t)0x00000008) /*!<Capture/Compare 3 Generation */
ommpy 0:d383e2dee0f7 2523 #define TIM_EGR_CC4G ((uint32_t)0x00000010) /*!<Capture/Compare 4 Generation */
ommpy 0:d383e2dee0f7 2524 #define TIM_EGR_COMG ((uint32_t)0x00000020) /*!<Capture/Compare Control Update Generation */
ommpy 0:d383e2dee0f7 2525 #define TIM_EGR_TG ((uint32_t)0x00000040) /*!<Trigger Generation */
ommpy 0:d383e2dee0f7 2526 #define TIM_EGR_BG ((uint32_t)0x00000080) /*!<Break Generation */
ommpy 0:d383e2dee0f7 2527
ommpy 0:d383e2dee0f7 2528 /****************** Bit definition for TIM_CCMR1 register ******************/
ommpy 0:d383e2dee0f7 2529 #define TIM_CCMR1_CC1S ((uint32_t)0x00000003) /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
ommpy 0:d383e2dee0f7 2530 #define TIM_CCMR1_CC1S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ommpy 0:d383e2dee0f7 2531 #define TIM_CCMR1_CC1S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ommpy 0:d383e2dee0f7 2532
ommpy 0:d383e2dee0f7 2533 #define TIM_CCMR1_OC1FE ((uint32_t)0x00000004) /*!<Output Compare 1 Fast enable */
ommpy 0:d383e2dee0f7 2534 #define TIM_CCMR1_OC1PE ((uint32_t)0x00000008) /*!<Output Compare 1 Preload enable */
ommpy 0:d383e2dee0f7 2535
ommpy 0:d383e2dee0f7 2536 #define TIM_CCMR1_OC1M ((uint32_t)0x00000070) /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
ommpy 0:d383e2dee0f7 2537 #define TIM_CCMR1_OC1M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
ommpy 0:d383e2dee0f7 2538 #define TIM_CCMR1_OC1M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
ommpy 0:d383e2dee0f7 2539 #define TIM_CCMR1_OC1M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
ommpy 0:d383e2dee0f7 2540
ommpy 0:d383e2dee0f7 2541 #define TIM_CCMR1_OC1CE ((uint32_t)0x00000080) /*!<Output Compare 1Clear Enable */
ommpy 0:d383e2dee0f7 2542
ommpy 0:d383e2dee0f7 2543 #define TIM_CCMR1_CC2S ((uint32_t)0x00000300) /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
ommpy 0:d383e2dee0f7 2544 #define TIM_CCMR1_CC2S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
ommpy 0:d383e2dee0f7 2545 #define TIM_CCMR1_CC2S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
ommpy 0:d383e2dee0f7 2546
ommpy 0:d383e2dee0f7 2547 #define TIM_CCMR1_OC2FE ((uint32_t)0x00000400) /*!<Output Compare 2 Fast enable */
ommpy 0:d383e2dee0f7 2548 #define TIM_CCMR1_OC2PE ((uint32_t)0x00000800) /*!<Output Compare 2 Preload enable */
ommpy 0:d383e2dee0f7 2549
ommpy 0:d383e2dee0f7 2550 #define TIM_CCMR1_OC2M ((uint32_t)0x00007000) /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
ommpy 0:d383e2dee0f7 2551 #define TIM_CCMR1_OC2M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
ommpy 0:d383e2dee0f7 2552 #define TIM_CCMR1_OC2M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
ommpy 0:d383e2dee0f7 2553 #define TIM_CCMR1_OC2M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
ommpy 0:d383e2dee0f7 2554
ommpy 0:d383e2dee0f7 2555 #define TIM_CCMR1_OC2CE ((uint32_t)0x00008000) /*!<Output Compare 2 Clear Enable */
ommpy 0:d383e2dee0f7 2556
ommpy 0:d383e2dee0f7 2557 /*---------------------------------------------------------------------------*/
ommpy 0:d383e2dee0f7 2558
ommpy 0:d383e2dee0f7 2559 #define TIM_CCMR1_IC1PSC ((uint32_t)0x0000000C) /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
ommpy 0:d383e2dee0f7 2560 #define TIM_CCMR1_IC1PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
ommpy 0:d383e2dee0f7 2561 #define TIM_CCMR1_IC1PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
ommpy 0:d383e2dee0f7 2562
ommpy 0:d383e2dee0f7 2563 #define TIM_CCMR1_IC1F ((uint32_t)0x000000F0) /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
ommpy 0:d383e2dee0f7 2564 #define TIM_CCMR1_IC1F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
ommpy 0:d383e2dee0f7 2565 #define TIM_CCMR1_IC1F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
ommpy 0:d383e2dee0f7 2566 #define TIM_CCMR1_IC1F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
ommpy 0:d383e2dee0f7 2567 #define TIM_CCMR1_IC1F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
ommpy 0:d383e2dee0f7 2568
ommpy 0:d383e2dee0f7 2569 #define TIM_CCMR1_IC2PSC ((uint32_t)0x00000C00) /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
ommpy 0:d383e2dee0f7 2570 #define TIM_CCMR1_IC2PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
ommpy 0:d383e2dee0f7 2571 #define TIM_CCMR1_IC2PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
ommpy 0:d383e2dee0f7 2572
ommpy 0:d383e2dee0f7 2573 #define TIM_CCMR1_IC2F ((uint32_t)0x0000F000) /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
ommpy 0:d383e2dee0f7 2574 #define TIM_CCMR1_IC2F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
ommpy 0:d383e2dee0f7 2575 #define TIM_CCMR1_IC2F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
ommpy 0:d383e2dee0f7 2576 #define TIM_CCMR1_IC2F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
ommpy 0:d383e2dee0f7 2577 #define TIM_CCMR1_IC2F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
ommpy 0:d383e2dee0f7 2578
ommpy 0:d383e2dee0f7 2579 /****************** Bit definition for TIM_CCMR2 register ******************/
ommpy 0:d383e2dee0f7 2580 #define TIM_CCMR2_CC3S ((uint32_t)0x00000003) /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
ommpy 0:d383e2dee0f7 2581 #define TIM_CCMR2_CC3S_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ommpy 0:d383e2dee0f7 2582 #define TIM_CCMR2_CC3S_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ommpy 0:d383e2dee0f7 2583
ommpy 0:d383e2dee0f7 2584 #define TIM_CCMR2_OC3FE ((uint32_t)0x00000004) /*!<Output Compare 3 Fast enable */
ommpy 0:d383e2dee0f7 2585 #define TIM_CCMR2_OC3PE ((uint32_t)0x00000008) /*!<Output Compare 3 Preload enable */
ommpy 0:d383e2dee0f7 2586
ommpy 0:d383e2dee0f7 2587 #define TIM_CCMR2_OC3M ((uint32_t)0x00000070) /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
ommpy 0:d383e2dee0f7 2588 #define TIM_CCMR2_OC3M_0 ((uint32_t)0x00000010) /*!<Bit 0 */
ommpy 0:d383e2dee0f7 2589 #define TIM_CCMR2_OC3M_1 ((uint32_t)0x00000020) /*!<Bit 1 */
ommpy 0:d383e2dee0f7 2590 #define TIM_CCMR2_OC3M_2 ((uint32_t)0x00000040) /*!<Bit 2 */
ommpy 0:d383e2dee0f7 2591
ommpy 0:d383e2dee0f7 2592 #define TIM_CCMR2_OC3CE ((uint32_t)0x00000080) /*!<Output Compare 3 Clear Enable */
ommpy 0:d383e2dee0f7 2593
ommpy 0:d383e2dee0f7 2594 #define TIM_CCMR2_CC4S ((uint32_t)0x00000300) /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
ommpy 0:d383e2dee0f7 2595 #define TIM_CCMR2_CC4S_0 ((uint32_t)0x00000100) /*!<Bit 0 */
ommpy 0:d383e2dee0f7 2596 #define TIM_CCMR2_CC4S_1 ((uint32_t)0x00000200) /*!<Bit 1 */
ommpy 0:d383e2dee0f7 2597
ommpy 0:d383e2dee0f7 2598 #define TIM_CCMR2_OC4FE ((uint32_t)0x00000400) /*!<Output Compare 4 Fast enable */
ommpy 0:d383e2dee0f7 2599 #define TIM_CCMR2_OC4PE ((uint32_t)0x00000800) /*!<Output Compare 4 Preload enable */
ommpy 0:d383e2dee0f7 2600
ommpy 0:d383e2dee0f7 2601 #define TIM_CCMR2_OC4M ((uint32_t)0x00007000) /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
ommpy 0:d383e2dee0f7 2602 #define TIM_CCMR2_OC4M_0 ((uint32_t)0x00001000) /*!<Bit 0 */
ommpy 0:d383e2dee0f7 2603 #define TIM_CCMR2_OC4M_1 ((uint32_t)0x00002000) /*!<Bit 1 */
ommpy 0:d383e2dee0f7 2604 #define TIM_CCMR2_OC4M_2 ((uint32_t)0x00004000) /*!<Bit 2 */
ommpy 0:d383e2dee0f7 2605
ommpy 0:d383e2dee0f7 2606 #define TIM_CCMR2_OC4CE ((uint32_t)0x00008000) /*!<Output Compare 4 Clear Enable */
ommpy 0:d383e2dee0f7 2607
ommpy 0:d383e2dee0f7 2608 /*---------------------------------------------------------------------------*/
ommpy 0:d383e2dee0f7 2609
ommpy 0:d383e2dee0f7 2610 #define TIM_CCMR2_IC3PSC ((uint32_t)0x0000000C) /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
ommpy 0:d383e2dee0f7 2611 #define TIM_CCMR2_IC3PSC_0 ((uint32_t)0x00000004) /*!<Bit 0 */
ommpy 0:d383e2dee0f7 2612 #define TIM_CCMR2_IC3PSC_1 ((uint32_t)0x00000008) /*!<Bit 1 */
ommpy 0:d383e2dee0f7 2613
ommpy 0:d383e2dee0f7 2614 #define TIM_CCMR2_IC3F ((uint32_t)0x000000F0) /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
ommpy 0:d383e2dee0f7 2615 #define TIM_CCMR2_IC3F_0 ((uint32_t)0x00000010) /*!<Bit 0 */
ommpy 0:d383e2dee0f7 2616 #define TIM_CCMR2_IC3F_1 ((uint32_t)0x00000020) /*!<Bit 1 */
ommpy 0:d383e2dee0f7 2617 #define TIM_CCMR2_IC3F_2 ((uint32_t)0x00000040) /*!<Bit 2 */
ommpy 0:d383e2dee0f7 2618 #define TIM_CCMR2_IC3F_3 ((uint32_t)0x00000080) /*!<Bit 3 */
ommpy 0:d383e2dee0f7 2619
ommpy 0:d383e2dee0f7 2620 #define TIM_CCMR2_IC4PSC ((uint32_t)0x00000C00) /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
ommpy 0:d383e2dee0f7 2621 #define TIM_CCMR2_IC4PSC_0 ((uint32_t)0x00000400) /*!<Bit 0 */
ommpy 0:d383e2dee0f7 2622 #define TIM_CCMR2_IC4PSC_1 ((uint32_t)0x00000800) /*!<Bit 1 */
ommpy 0:d383e2dee0f7 2623
ommpy 0:d383e2dee0f7 2624 #define TIM_CCMR2_IC4F ((uint32_t)0x0000F000) /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
ommpy 0:d383e2dee0f7 2625 #define TIM_CCMR2_IC4F_0 ((uint32_t)0x00001000) /*!<Bit 0 */
ommpy 0:d383e2dee0f7 2626 #define TIM_CCMR2_IC4F_1 ((uint32_t)0x00002000) /*!<Bit 1 */
ommpy 0:d383e2dee0f7 2627 #define TIM_CCMR2_IC4F_2 ((uint32_t)0x00004000) /*!<Bit 2 */
ommpy 0:d383e2dee0f7 2628 #define TIM_CCMR2_IC4F_3 ((uint32_t)0x00008000) /*!<Bit 3 */
ommpy 0:d383e2dee0f7 2629
ommpy 0:d383e2dee0f7 2630 /******************* Bit definition for TIM_CCER register ******************/
ommpy 0:d383e2dee0f7 2631 #define TIM_CCER_CC1E ((uint32_t)0x00000001) /*!<Capture/Compare 1 output enable */
ommpy 0:d383e2dee0f7 2632 #define TIM_CCER_CC1P ((uint32_t)0x00000002) /*!<Capture/Compare 1 output Polarity */
ommpy 0:d383e2dee0f7 2633 #define TIM_CCER_CC1NE ((uint32_t)0x00000004) /*!<Capture/Compare 1 Complementary output enable */
ommpy 0:d383e2dee0f7 2634 #define TIM_CCER_CC1NP ((uint32_t)0x00000008) /*!<Capture/Compare 1 Complementary output Polarity */
ommpy 0:d383e2dee0f7 2635 #define TIM_CCER_CC2E ((uint32_t)0x00000010) /*!<Capture/Compare 2 output enable */
ommpy 0:d383e2dee0f7 2636 #define TIM_CCER_CC2P ((uint32_t)0x00000020) /*!<Capture/Compare 2 output Polarity */
ommpy 0:d383e2dee0f7 2637 #define TIM_CCER_CC2NE ((uint32_t)0x00000040) /*!<Capture/Compare 2 Complementary output enable */
ommpy 0:d383e2dee0f7 2638 #define TIM_CCER_CC2NP ((uint32_t)0x00000080) /*!<Capture/Compare 2 Complementary output Polarity */
ommpy 0:d383e2dee0f7 2639 #define TIM_CCER_CC3E ((uint32_t)0x00000100) /*!<Capture/Compare 3 output enable */
ommpy 0:d383e2dee0f7 2640 #define TIM_CCER_CC3P ((uint32_t)0x00000200) /*!<Capture/Compare 3 output Polarity */
ommpy 0:d383e2dee0f7 2641 #define TIM_CCER_CC3NE ((uint32_t)0x00000400) /*!<Capture/Compare 3 Complementary output enable */
ommpy 0:d383e2dee0f7 2642 #define TIM_CCER_CC3NP ((uint32_t)0x00000800) /*!<Capture/Compare 3 Complementary output Polarity */
ommpy 0:d383e2dee0f7 2643 #define TIM_CCER_CC4E ((uint32_t)0x00001000) /*!<Capture/Compare 4 output enable */
ommpy 0:d383e2dee0f7 2644 #define TIM_CCER_CC4P ((uint32_t)0x00002000) /*!<Capture/Compare 4 output Polarity */
ommpy 0:d383e2dee0f7 2645 #define TIM_CCER_CC4NP ((uint32_t)0x00008000) /*!<Capture/Compare 4 Complementary output Polarity */
ommpy 0:d383e2dee0f7 2646
ommpy 0:d383e2dee0f7 2647 /******************* Bit definition for TIM_CNT register *******************/
ommpy 0:d383e2dee0f7 2648 #define TIM_CNT_CNT ((uint32_t)0xFFFFFFFF) /*!<Counter Value */
ommpy 0:d383e2dee0f7 2649
ommpy 0:d383e2dee0f7 2650 /******************* Bit definition for TIM_PSC register *******************/
ommpy 0:d383e2dee0f7 2651 #define TIM_PSC_PSC ((uint32_t)0x0000FFFF) /*!<Prescaler Value */
ommpy 0:d383e2dee0f7 2652
ommpy 0:d383e2dee0f7 2653 /******************* Bit definition for TIM_ARR register *******************/
ommpy 0:d383e2dee0f7 2654 #define TIM_ARR_ARR ((uint32_t)0xFFFFFFFF) /*!<actual auto-reload Value */
ommpy 0:d383e2dee0f7 2655
ommpy 0:d383e2dee0f7 2656 /******************* Bit definition for TIM_RCR register *******************/
ommpy 0:d383e2dee0f7 2657 #define TIM_RCR_REP ((uint32_t)0x000000FF) /*!<Repetition Counter Value */
ommpy 0:d383e2dee0f7 2658
ommpy 0:d383e2dee0f7 2659 /******************* Bit definition for TIM_CCR1 register ******************/
ommpy 0:d383e2dee0f7 2660 #define TIM_CCR1_CCR1 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 1 Value */
ommpy 0:d383e2dee0f7 2661
ommpy 0:d383e2dee0f7 2662 /******************* Bit definition for TIM_CCR2 register ******************/
ommpy 0:d383e2dee0f7 2663 #define TIM_CCR2_CCR2 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 2 Value */
ommpy 0:d383e2dee0f7 2664
ommpy 0:d383e2dee0f7 2665 /******************* Bit definition for TIM_CCR3 register ******************/
ommpy 0:d383e2dee0f7 2666 #define TIM_CCR3_CCR3 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 3 Value */
ommpy 0:d383e2dee0f7 2667
ommpy 0:d383e2dee0f7 2668 /******************* Bit definition for TIM_CCR4 register ******************/
ommpy 0:d383e2dee0f7 2669 #define TIM_CCR4_CCR4 ((uint32_t)0x0000FFFF) /*!<Capture/Compare 4 Value */
ommpy 0:d383e2dee0f7 2670
ommpy 0:d383e2dee0f7 2671 /******************* Bit definition for TIM_BDTR register ******************/
ommpy 0:d383e2dee0f7 2672 #define TIM_BDTR_DTG ((uint32_t)0x000000FF) /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
ommpy 0:d383e2dee0f7 2673 #define TIM_BDTR_DTG_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ommpy 0:d383e2dee0f7 2674 #define TIM_BDTR_DTG_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ommpy 0:d383e2dee0f7 2675 #define TIM_BDTR_DTG_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ommpy 0:d383e2dee0f7 2676 #define TIM_BDTR_DTG_3 ((uint32_t)0x00000008) /*!<Bit 3 */
ommpy 0:d383e2dee0f7 2677 #define TIM_BDTR_DTG_4 ((uint32_t)0x00000010) /*!<Bit 4 */
ommpy 0:d383e2dee0f7 2678 #define TIM_BDTR_DTG_5 ((uint32_t)0x00000020) /*!<Bit 5 */
ommpy 0:d383e2dee0f7 2679 #define TIM_BDTR_DTG_6 ((uint32_t)0x00000040) /*!<Bit 6 */
ommpy 0:d383e2dee0f7 2680 #define TIM_BDTR_DTG_7 ((uint32_t)0x00000080) /*!<Bit 7 */
ommpy 0:d383e2dee0f7 2681
ommpy 0:d383e2dee0f7 2682 #define TIM_BDTR_LOCK ((uint32_t)0x00000300) /*!<LOCK[1:0] bits (Lock Configuration) */
ommpy 0:d383e2dee0f7 2683 #define TIM_BDTR_LOCK_0 ((uint32_t)0x00000100) /*!<Bit 0 */
ommpy 0:d383e2dee0f7 2684 #define TIM_BDTR_LOCK_1 ((uint32_t)0x00000200) /*!<Bit 1 */
ommpy 0:d383e2dee0f7 2685
ommpy 0:d383e2dee0f7 2686 #define TIM_BDTR_OSSI ((uint32_t)0x00000400) /*!<Off-State Selection for Idle mode */
ommpy 0:d383e2dee0f7 2687 #define TIM_BDTR_OSSR ((uint32_t)0x00000800) /*!<Off-State Selection for Run mode */
ommpy 0:d383e2dee0f7 2688 #define TIM_BDTR_BKE ((uint32_t)0x00001000) /*!<Break enable */
ommpy 0:d383e2dee0f7 2689 #define TIM_BDTR_BKP ((uint32_t)0x00002000) /*!<Break Polarity */
ommpy 0:d383e2dee0f7 2690 #define TIM_BDTR_AOE ((uint32_t)0x00004000) /*!<Automatic Output enable */
ommpy 0:d383e2dee0f7 2691 #define TIM_BDTR_MOE ((uint32_t)0x00008000) /*!<Main Output enable */
ommpy 0:d383e2dee0f7 2692
ommpy 0:d383e2dee0f7 2693 /******************* Bit definition for TIM_DCR register *******************/
ommpy 0:d383e2dee0f7 2694 #define TIM_DCR_DBA ((uint32_t)0x0000001F) /*!<DBA[4:0] bits (DMA Base Address) */
ommpy 0:d383e2dee0f7 2695 #define TIM_DCR_DBA_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ommpy 0:d383e2dee0f7 2696 #define TIM_DCR_DBA_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ommpy 0:d383e2dee0f7 2697 #define TIM_DCR_DBA_2 ((uint32_t)0x00000004) /*!<Bit 2 */
ommpy 0:d383e2dee0f7 2698 #define TIM_DCR_DBA_3 ((uint32_t)0x00000008) /*!<Bit 3 */
ommpy 0:d383e2dee0f7 2699 #define TIM_DCR_DBA_4 ((uint32_t)0x00000010) /*!<Bit 4 */
ommpy 0:d383e2dee0f7 2700
ommpy 0:d383e2dee0f7 2701 #define TIM_DCR_DBL ((uint32_t)0x00001F00) /*!<DBL[4:0] bits (DMA Burst Length) */
ommpy 0:d383e2dee0f7 2702 #define TIM_DCR_DBL_0 ((uint32_t)0x00000100) /*!<Bit 0 */
ommpy 0:d383e2dee0f7 2703 #define TIM_DCR_DBL_1 ((uint32_t)0x00000200) /*!<Bit 1 */
ommpy 0:d383e2dee0f7 2704 #define TIM_DCR_DBL_2 ((uint32_t)0x00000400) /*!<Bit 2 */
ommpy 0:d383e2dee0f7 2705 #define TIM_DCR_DBL_3 ((uint32_t)0x00000800) /*!<Bit 3 */
ommpy 0:d383e2dee0f7 2706 #define TIM_DCR_DBL_4 ((uint32_t)0x00001000) /*!<Bit 4 */
ommpy 0:d383e2dee0f7 2707
ommpy 0:d383e2dee0f7 2708 /******************* Bit definition for TIM_DMAR register ******************/
ommpy 0:d383e2dee0f7 2709 #define TIM_DMAR_DMAB ((uint32_t)0x0000FFFF) /*!<DMA register for burst accesses */
ommpy 0:d383e2dee0f7 2710
ommpy 0:d383e2dee0f7 2711 /******************* Bit definition for TIM14_OR register ********************/
ommpy 0:d383e2dee0f7 2712 #define TIM14_OR_TI1_RMP ((uint32_t)0x00000003) /*!<TI1_RMP[1:0] bits (TIM14 Input 4 remap) */
ommpy 0:d383e2dee0f7 2713 #define TIM14_OR_TI1_RMP_0 ((uint32_t)0x00000001) /*!<Bit 0 */
ommpy 0:d383e2dee0f7 2714 #define TIM14_OR_TI1_RMP_1 ((uint32_t)0x00000002) /*!<Bit 1 */
ommpy 0:d383e2dee0f7 2715
ommpy 0:d383e2dee0f7 2716 /******************************************************************************/
ommpy 0:d383e2dee0f7 2717 /* */
ommpy 0:d383e2dee0f7 2718 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
ommpy 0:d383e2dee0f7 2719 /* */
ommpy 0:d383e2dee0f7 2720 /******************************************************************************/
ommpy 0:d383e2dee0f7 2721 /****************** Bit definition for USART_CR1 register *******************/
ommpy 0:d383e2dee0f7 2722 #define USART_CR1_UE ((uint32_t)0x00000001) /*!< USART Enable */
ommpy 0:d383e2dee0f7 2723 #define USART_CR1_UESM ((uint32_t)0x00000002) /*!< USART Enable in STOP Mode */
ommpy 0:d383e2dee0f7 2724 #define USART_CR1_RE ((uint32_t)0x00000004) /*!< Receiver Enable */
ommpy 0:d383e2dee0f7 2725 #define USART_CR1_TE ((uint32_t)0x00000008) /*!< Transmitter Enable */
ommpy 0:d383e2dee0f7 2726 #define USART_CR1_IDLEIE ((uint32_t)0x00000010) /*!< IDLE Interrupt Enable */
ommpy 0:d383e2dee0f7 2727 #define USART_CR1_RXNEIE ((uint32_t)0x00000020) /*!< RXNE Interrupt Enable */
ommpy 0:d383e2dee0f7 2728 #define USART_CR1_TCIE ((uint32_t)0x00000040) /*!< Transmission Complete Interrupt Enable */
ommpy 0:d383e2dee0f7 2729 #define USART_CR1_TXEIE ((uint32_t)0x00000080) /*!< TXE Interrupt Enable */
ommpy 0:d383e2dee0f7 2730 #define USART_CR1_PEIE ((uint32_t)0x00000100) /*!< PE Interrupt Enable */
ommpy 0:d383e2dee0f7 2731 #define USART_CR1_PS ((uint32_t)0x00000200) /*!< Parity Selection */
ommpy 0:d383e2dee0f7 2732 #define USART_CR1_PCE ((uint32_t)0x00000400) /*!< Parity Control Enable */
ommpy 0:d383e2dee0f7 2733 #define USART_CR1_WAKE ((uint32_t)0x00000800) /*!< Receiver Wakeup method */
ommpy 0:d383e2dee0f7 2734 #define USART_CR1_M0 ((uint32_t)0x00001000) /*!< Word length bit 0 */
ommpy 0:d383e2dee0f7 2735 #define USART_CR1_M ((uint32_t)0x00001000) /*!< SmartCard Length */
ommpy 0:d383e2dee0f7 2736 #define USART_CR1_MME ((uint32_t)0x00002000) /*!< Mute Mode Enable */
ommpy 0:d383e2dee0f7 2737 #define USART_CR1_CMIE ((uint32_t)0x00004000) /*!< Character match interrupt enable */
ommpy 0:d383e2dee0f7 2738 #define USART_CR1_OVER8 ((uint32_t)0x00008000) /*!< Oversampling by 8-bit or 16-bit mode */
ommpy 0:d383e2dee0f7 2739 #define USART_CR1_DEDT ((uint32_t)0x001F0000) /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
ommpy 0:d383e2dee0f7 2740 #define USART_CR1_DEDT_0 ((uint32_t)0x00010000) /*!< Bit 0 */
ommpy 0:d383e2dee0f7 2741 #define USART_CR1_DEDT_1 ((uint32_t)0x00020000) /*!< Bit 1 */
ommpy 0:d383e2dee0f7 2742 #define USART_CR1_DEDT_2 ((uint32_t)0x00040000) /*!< Bit 2 */
ommpy 0:d383e2dee0f7 2743 #define USART_CR1_DEDT_3 ((uint32_t)0x00080000) /*!< Bit 3 */
ommpy 0:d383e2dee0f7 2744 #define USART_CR1_DEDT_4 ((uint32_t)0x00100000) /*!< Bit 4 */
ommpy 0:d383e2dee0f7 2745 #define USART_CR1_DEAT ((uint32_t)0x03E00000) /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
ommpy 0:d383e2dee0f7 2746 #define USART_CR1_DEAT_0 ((uint32_t)0x00200000) /*!< Bit 0 */
ommpy 0:d383e2dee0f7 2747 #define USART_CR1_DEAT_1 ((uint32_t)0x00400000) /*!< Bit 1 */
ommpy 0:d383e2dee0f7 2748 #define USART_CR1_DEAT_2 ((uint32_t)0x00800000) /*!< Bit 2 */
ommpy 0:d383e2dee0f7 2749 #define USART_CR1_DEAT_3 ((uint32_t)0x01000000) /*!< Bit 3 */
ommpy 0:d383e2dee0f7 2750 #define USART_CR1_DEAT_4 ((uint32_t)0x02000000) /*!< Bit 4 */
ommpy 0:d383e2dee0f7 2751 #define USART_CR1_RTOIE ((uint32_t)0x04000000) /*!< Receive Time Out interrupt enable */
ommpy 0:d383e2dee0f7 2752 #define USART_CR1_EOBIE ((uint32_t)0x08000000) /*!< End of Block interrupt enable */
ommpy 0:d383e2dee0f7 2753
ommpy 0:d383e2dee0f7 2754 /****************** Bit definition for USART_CR2 register *******************/
ommpy 0:d383e2dee0f7 2755 #define USART_CR2_ADDM7 ((uint32_t)0x00000010) /*!< 7-bit or 4-bit Address Detection */
ommpy 0:d383e2dee0f7 2756 #define USART_CR2_LBDL ((uint32_t)0x00000020) /*!< LIN Break Detection Length */
ommpy 0:d383e2dee0f7 2757 #define USART_CR2_LBDIE ((uint32_t)0x00000040) /*!< LIN Break Detection Interrupt Enable */
ommpy 0:d383e2dee0f7 2758 #define USART_CR2_LBCL ((uint32_t)0x00000100) /*!< Last Bit Clock pulse */
ommpy 0:d383e2dee0f7 2759 #define USART_CR2_CPHA ((uint32_t)0x00000200) /*!< Clock Phase */
ommpy 0:d383e2dee0f7 2760 #define USART_CR2_CPOL ((uint32_t)0x00000400) /*!< Clock Polarity */
ommpy 0:d383e2dee0f7 2761 #define USART_CR2_CLKEN ((uint32_t)0x00000800) /*!< Clock Enable */
ommpy 0:d383e2dee0f7 2762 #define USART_CR2_STOP ((uint32_t)0x00003000) /*!< STOP[1:0] bits (STOP bits) */
ommpy 0:d383e2dee0f7 2763 #define USART_CR2_STOP_0 ((uint32_t)0x00001000) /*!< Bit 0 */
ommpy 0:d383e2dee0f7 2764 #define USART_CR2_STOP_1 ((uint32_t)0x00002000) /*!< Bit 1 */
ommpy 0:d383e2dee0f7 2765 #define USART_CR2_LINEN ((uint32_t)0x00004000) /*!< LIN mode enable */
ommpy 0:d383e2dee0f7 2766 #define USART_CR2_SWAP ((uint32_t)0x00008000) /*!< SWAP TX/RX pins */
ommpy 0:d383e2dee0f7 2767 #define USART_CR2_RXINV ((uint32_t)0x00010000) /*!< RX pin active level inversion */
ommpy 0:d383e2dee0f7 2768 #define USART_CR2_TXINV ((uint32_t)0x00020000) /*!< TX pin active level inversion */
ommpy 0:d383e2dee0f7 2769 #define USART_CR2_DATAINV ((uint32_t)0x00040000) /*!< Binary data inversion */
ommpy 0:d383e2dee0f7 2770 #define USART_CR2_MSBFIRST ((uint32_t)0x00080000) /*!< Most Significant Bit First */
ommpy 0:d383e2dee0f7 2771 #define USART_CR2_ABREN ((uint32_t)0x00100000) /*!< Auto Baud-Rate Enable*/
ommpy 0:d383e2dee0f7 2772 #define USART_CR2_ABRMODE ((uint32_t)0x00600000) /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
ommpy 0:d383e2dee0f7 2773 #define USART_CR2_ABRMODE_0 ((uint32_t)0x00200000) /*!< Bit 0 */
ommpy 0:d383e2dee0f7 2774 #define USART_CR2_ABRMODE_1 ((uint32_t)0x00400000) /*!< Bit 1 */
ommpy 0:d383e2dee0f7 2775 #define USART_CR2_RTOEN ((uint32_t)0x00800000) /*!< Receiver Time-Out enable */
ommpy 0:d383e2dee0f7 2776 #define USART_CR2_ADD ((uint32_t)0xFF000000) /*!< Address of the USART node */
ommpy 0:d383e2dee0f7 2777
ommpy 0:d383e2dee0f7 2778 /****************** Bit definition for USART_CR3 register *******************/
ommpy 0:d383e2dee0f7 2779 #define USART_CR3_EIE ((uint32_t)0x00000001) /*!< Error Interrupt Enable */
ommpy 0:d383e2dee0f7 2780 #define USART_CR3_IREN ((uint32_t)0x00000002) /*!< IrDA mode Enable */
ommpy 0:d383e2dee0f7 2781 #define USART_CR3_IRLP ((uint32_t)0x00000004) /*!< IrDA Low-Power */
ommpy 0:d383e2dee0f7 2782 #define USART_CR3_HDSEL ((uint32_t)0x00000008) /*!< Half-Duplex Selection */
ommpy 0:d383e2dee0f7 2783 #define USART_CR3_NACK ((uint32_t)0x00000010) /*!< SmartCard NACK enable */
ommpy 0:d383e2dee0f7 2784 #define USART_CR3_SCEN ((uint32_t)0x00000020) /*!< SmartCard mode enable */
ommpy 0:d383e2dee0f7 2785 #define USART_CR3_DMAR ((uint32_t)0x00000040) /*!< DMA Enable Receiver */
ommpy 0:d383e2dee0f7 2786 #define USART_CR3_DMAT ((uint32_t)0x00000080) /*!< DMA Enable Transmitter */
ommpy 0:d383e2dee0f7 2787 #define USART_CR3_RTSE ((uint32_t)0x00000100) /*!< RTS Enable */
ommpy 0:d383e2dee0f7 2788 #define USART_CR3_CTSE ((uint32_t)0x00000200) /*!< CTS Enable */
ommpy 0:d383e2dee0f7 2789 #define USART_CR3_CTSIE ((uint32_t)0x00000400) /*!< CTS Interrupt Enable */
ommpy 0:d383e2dee0f7 2790 #define USART_CR3_ONEBIT ((uint32_t)0x00000800) /*!< One sample bit method enable */
ommpy 0:d383e2dee0f7 2791 #define USART_CR3_OVRDIS ((uint32_t)0x00001000) /*!< Overrun Disable */
ommpy 0:d383e2dee0f7 2792 #define USART_CR3_DDRE ((uint32_t)0x00002000) /*!< DMA Disable on Reception Error */
ommpy 0:d383e2dee0f7 2793 #define USART_CR3_DEM ((uint32_t)0x00004000) /*!< Driver Enable Mode */
ommpy 0:d383e2dee0f7 2794 #define USART_CR3_DEP ((uint32_t)0x00008000) /*!< Driver Enable Polarity Selection */
ommpy 0:d383e2dee0f7 2795 #define USART_CR3_SCARCNT ((uint32_t)0x000E0000) /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
ommpy 0:d383e2dee0f7 2796 #define USART_CR3_SCARCNT_0 ((uint32_t)0x00020000) /*!< Bit 0 */
ommpy 0:d383e2dee0f7 2797 #define USART_CR3_SCARCNT_1 ((uint32_t)0x00040000) /*!< Bit 1 */
ommpy 0:d383e2dee0f7 2798 #define USART_CR3_SCARCNT_2 ((uint32_t)0x00080000) /*!< Bit 2 */
ommpy 0:d383e2dee0f7 2799 #define USART_CR3_WUS ((uint32_t)0x00300000) /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
ommpy 0:d383e2dee0f7 2800 #define USART_CR3_WUS_0 ((uint32_t)0x00100000) /*!< Bit 0 */
ommpy 0:d383e2dee0f7 2801 #define USART_CR3_WUS_1 ((uint32_t)0x00200000) /*!< Bit 1 */
ommpy 0:d383e2dee0f7 2802 #define USART_CR3_WUFIE ((uint32_t)0x00400000) /*!< Wake Up Interrupt Enable */
ommpy 0:d383e2dee0f7 2803
ommpy 0:d383e2dee0f7 2804 /****************** Bit definition for USART_BRR register *******************/
ommpy 0:d383e2dee0f7 2805 #define USART_BRR_DIV_FRACTION ((uint32_t)0x0000000F) /*!< Fraction of USARTDIV */
ommpy 0:d383e2dee0f7 2806 #define USART_BRR_DIV_MANTISSA ((uint32_t)0x0000FFF0) /*!< Mantissa of USARTDIV */
ommpy 0:d383e2dee0f7 2807
ommpy 0:d383e2dee0f7 2808 /****************** Bit definition for USART_GTPR register ******************/
ommpy 0:d383e2dee0f7 2809 #define USART_GTPR_PSC ((uint32_t)0x000000FF) /*!< PSC[7:0] bits (Prescaler value) */
ommpy 0:d383e2dee0f7 2810 #define USART_GTPR_GT ((uint32_t)0x0000FF00) /*!< GT[7:0] bits (Guard time value) */
ommpy 0:d383e2dee0f7 2811
ommpy 0:d383e2dee0f7 2812
ommpy 0:d383e2dee0f7 2813 /******************* Bit definition for USART_RTOR register *****************/
ommpy 0:d383e2dee0f7 2814 #define USART_RTOR_RTO ((uint32_t)0x00FFFFFF) /*!< Receiver Time Out Value */
ommpy 0:d383e2dee0f7 2815 #define USART_RTOR_BLEN ((uint32_t)0xFF000000) /*!< Block Length */
ommpy 0:d383e2dee0f7 2816
ommpy 0:d383e2dee0f7 2817 /******************* Bit definition for USART_RQR register ******************/
ommpy 0:d383e2dee0f7 2818 #define USART_RQR_ABRRQ ((uint32_t)0x00000001) /*!< Auto-Baud Rate Request */
ommpy 0:d383e2dee0f7 2819 #define USART_RQR_SBKRQ ((uint32_t)0x00000002) /*!< Send Break Request */
ommpy 0:d383e2dee0f7 2820 #define USART_RQR_MMRQ ((uint32_t)0x00000004) /*!< Mute Mode Request */
ommpy 0:d383e2dee0f7 2821 #define USART_RQR_RXFRQ ((uint32_t)0x00000008) /*!< Receive Data flush Request */
ommpy 0:d383e2dee0f7 2822 #define USART_RQR_TXFRQ ((uint32_t)0x00000010) /*!< Transmit data flush Request */
ommpy 0:d383e2dee0f7 2823
ommpy 0:d383e2dee0f7 2824 /******************* Bit definition for USART_ISR register ******************/
ommpy 0:d383e2dee0f7 2825 #define USART_ISR_PE ((uint32_t)0x00000001) /*!< Parity Error */
ommpy 0:d383e2dee0f7 2826 #define USART_ISR_FE ((uint32_t)0x00000002) /*!< Framing Error */
ommpy 0:d383e2dee0f7 2827 #define USART_ISR_NE ((uint32_t)0x00000004) /*!< Noise detected Flag */
ommpy 0:d383e2dee0f7 2828 #define USART_ISR_ORE ((uint32_t)0x00000008) /*!< OverRun Error */
ommpy 0:d383e2dee0f7 2829 #define USART_ISR_IDLE ((uint32_t)0x00000010) /*!< IDLE line detected */
ommpy 0:d383e2dee0f7 2830 #define USART_ISR_RXNE ((uint32_t)0x00000020) /*!< Read Data Register Not Empty */
ommpy 0:d383e2dee0f7 2831 #define USART_ISR_TC ((uint32_t)0x00000040) /*!< Transmission Complete */
ommpy 0:d383e2dee0f7 2832 #define USART_ISR_TXE ((uint32_t)0x00000080) /*!< Transmit Data Register Empty */
ommpy 0:d383e2dee0f7 2833 #define USART_ISR_LBDF ((uint32_t)0x00000100) /*!< LIN Break Detection Flag */
ommpy 0:d383e2dee0f7 2834 #define USART_ISR_CTSIF ((uint32_t)0x00000200) /*!< CTS interrupt flag */
ommpy 0:d383e2dee0f7 2835 #define USART_ISR_CTS ((uint32_t)0x00000400) /*!< CTS flag */
ommpy 0:d383e2dee0f7 2836 #define USART_ISR_RTOF ((uint32_t)0x00000800) /*!< Receiver Time Out */
ommpy 0:d383e2dee0f7 2837 #define USART_ISR_EOBF ((uint32_t)0x00001000) /*!< End Of Block Flag */
ommpy 0:d383e2dee0f7 2838 #define USART_ISR_ABRE ((uint32_t)0x00004000) /*!< Auto-Baud Rate Error */
ommpy 0:d383e2dee0f7 2839 #define USART_ISR_ABRF ((uint32_t)0x00008000) /*!< Auto-Baud Rate Flag */
ommpy 0:d383e2dee0f7 2840 #define USART_ISR_BUSY ((uint32_t)0x00010000) /*!< Busy Flag */
ommpy 0:d383e2dee0f7 2841 #define USART_ISR_CMF ((uint32_t)0x00020000) /*!< Character Match Flag */
ommpy 0:d383e2dee0f7 2842 #define USART_ISR_SBKF ((uint32_t)0x00040000) /*!< Send Break Flag */
ommpy 0:d383e2dee0f7 2843 #define USART_ISR_RWU ((uint32_t)0x00080000) /*!< Receive Wake Up from mute mode Flag */
ommpy 0:d383e2dee0f7 2844 #define USART_ISR_WUF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Flag */
ommpy 0:d383e2dee0f7 2845 #define USART_ISR_TEACK ((uint32_t)0x00200000) /*!< Transmit Enable Acknowledge Flag */
ommpy 0:d383e2dee0f7 2846 #define USART_ISR_REACK ((uint32_t)0x00400000) /*!< Receive Enable Acknowledge Flag */
ommpy 0:d383e2dee0f7 2847
ommpy 0:d383e2dee0f7 2848 /******************* Bit definition for USART_ICR register ******************/
ommpy 0:d383e2dee0f7 2849 #define USART_ICR_PECF ((uint32_t)0x00000001) /*!< Parity Error Clear Flag */
ommpy 0:d383e2dee0f7 2850 #define USART_ICR_FECF ((uint32_t)0x00000002) /*!< Framing Error Clear Flag */
ommpy 0:d383e2dee0f7 2851 #define USART_ICR_NCF ((uint32_t)0x00000004) /*!< Noise detected Clear Flag */
ommpy 0:d383e2dee0f7 2852 #define USART_ICR_ORECF ((uint32_t)0x00000008) /*!< OverRun Error Clear Flag */
ommpy 0:d383e2dee0f7 2853 #define USART_ICR_IDLECF ((uint32_t)0x00000010) /*!< IDLE line detected Clear Flag */
ommpy 0:d383e2dee0f7 2854 #define USART_ICR_TCCF ((uint32_t)0x00000040) /*!< Transmission Complete Clear Flag */
ommpy 0:d383e2dee0f7 2855 #define USART_ICR_LBDCF ((uint32_t)0x00000100) /*!< LIN Break Detection Clear Flag */
ommpy 0:d383e2dee0f7 2856 #define USART_ICR_CTSCF ((uint32_t)0x00000200) /*!< CTS Interrupt Clear Flag */
ommpy 0:d383e2dee0f7 2857 #define USART_ICR_RTOCF ((uint32_t)0x00000800) /*!< Receiver Time Out Clear Flag */
ommpy 0:d383e2dee0f7 2858 #define USART_ICR_EOBCF ((uint32_t)0x00001000) /*!< End Of Block Clear Flag */
ommpy 0:d383e2dee0f7 2859 #define USART_ICR_CMCF ((uint32_t)0x00020000) /*!< Character Match Clear Flag */
ommpy 0:d383e2dee0f7 2860 #define USART_ICR_WUCF ((uint32_t)0x00100000) /*!< Wake Up from stop mode Clear Flag */
ommpy 0:d383e2dee0f7 2861
ommpy 0:d383e2dee0f7 2862 /******************* Bit definition for USART_RDR register ******************/
ommpy 0:d383e2dee0f7 2863 #define USART_RDR_RDR ((uint16_t)0x01FF) /*!< RDR[8:0] bits (Receive Data value) */
ommpy 0:d383e2dee0f7 2864
ommpy 0:d383e2dee0f7 2865 /******************* Bit definition for USART_TDR register ******************/
ommpy 0:d383e2dee0f7 2866 #define USART_TDR_TDR ((uint16_t)0x01FF) /*!< TDR[8:0] bits (Transmit Data value) */
ommpy 0:d383e2dee0f7 2867
ommpy 0:d383e2dee0f7 2868 /******************************************************************************/
ommpy 0:d383e2dee0f7 2869 /* */
ommpy 0:d383e2dee0f7 2870 /* Window WATCHDOG (WWDG) */
ommpy 0:d383e2dee0f7 2871 /* */
ommpy 0:d383e2dee0f7 2872 /******************************************************************************/
ommpy 0:d383e2dee0f7 2873 /******************* Bit definition for WWDG_CR register ********************/
ommpy 0:d383e2dee0f7 2874 #define WWDG_CR_T ((uint32_t)0x7F) /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
ommpy 0:d383e2dee0f7 2875 #define WWDG_CR_T0 ((uint32_t)0x01) /*!<Bit 0 */
ommpy 0:d383e2dee0f7 2876 #define WWDG_CR_T1 ((uint32_t)0x02) /*!<Bit 1 */
ommpy 0:d383e2dee0f7 2877 #define WWDG_CR_T2 ((uint32_t)0x04) /*!<Bit 2 */
ommpy 0:d383e2dee0f7 2878 #define WWDG_CR_T3 ((uint32_t)0x08) /*!<Bit 3 */
ommpy 0:d383e2dee0f7 2879 #define WWDG_CR_T4 ((uint32_t)0x10) /*!<Bit 4 */
ommpy 0:d383e2dee0f7 2880 #define WWDG_CR_T5 ((uint32_t)0x20) /*!<Bit 5 */
ommpy 0:d383e2dee0f7 2881 #define WWDG_CR_T6 ((uint32_t)0x40) /*!<Bit 6 */
ommpy 0:d383e2dee0f7 2882
ommpy 0:d383e2dee0f7 2883 #define WWDG_CR_WDGA ((uint32_t)0x80) /*!<Activation bit */
ommpy 0:d383e2dee0f7 2884
ommpy 0:d383e2dee0f7 2885 /******************* Bit definition for WWDG_CFR register *******************/
ommpy 0:d383e2dee0f7 2886 #define WWDG_CFR_W ((uint32_t)0x007F) /*!<W[6:0] bits (7-bit window value) */
ommpy 0:d383e2dee0f7 2887 #define WWDG_CFR_W0 ((uint32_t)0x0001) /*!<Bit 0 */
ommpy 0:d383e2dee0f7 2888 #define WWDG_CFR_W1 ((uint32_t)0x0002) /*!<Bit 1 */
ommpy 0:d383e2dee0f7 2889 #define WWDG_CFR_W2 ((uint32_t)0x0004) /*!<Bit 2 */
ommpy 0:d383e2dee0f7 2890 #define WWDG_CFR_W3 ((uint32_t)0x0008) /*!<Bit 3 */
ommpy 0:d383e2dee0f7 2891 #define WWDG_CFR_W4 ((uint32_t)0x0010) /*!<Bit 4 */
ommpy 0:d383e2dee0f7 2892 #define WWDG_CFR_W5 ((uint32_t)0x0020) /*!<Bit 5 */
ommpy 0:d383e2dee0f7 2893 #define WWDG_CFR_W6 ((uint32_t)0x0040) /*!<Bit 6 */
ommpy 0:d383e2dee0f7 2894
ommpy 0:d383e2dee0f7 2895 #define WWDG_CFR_WDGTB ((uint32_t)0x0180) /*!<WDGTB[1:0] bits (Timer Base) */
ommpy 0:d383e2dee0f7 2896 #define WWDG_CFR_WDGTB0 ((uint32_t)0x0080) /*!<Bit 0 */
ommpy 0:d383e2dee0f7 2897 #define WWDG_CFR_WDGTB1 ((uint32_t)0x0100) /*!<Bit 1 */
ommpy 0:d383e2dee0f7 2898
ommpy 0:d383e2dee0f7 2899 #define WWDG_CFR_EWI ((uint32_t)0x0200) /*!<Early Wakeup Interrupt */
ommpy 0:d383e2dee0f7 2900
ommpy 0:d383e2dee0f7 2901 /******************* Bit definition for WWDG_SR register ********************/
ommpy 0:d383e2dee0f7 2902 #define WWDG_SR_EWIF ((uint32_t)0x01) /*!<Early Wakeup Interrupt Flag */
ommpy 0:d383e2dee0f7 2903
ommpy 0:d383e2dee0f7 2904 /**
ommpy 0:d383e2dee0f7 2905 * @}
ommpy 0:d383e2dee0f7 2906 */
ommpy 0:d383e2dee0f7 2907
ommpy 0:d383e2dee0f7 2908 /**
ommpy 0:d383e2dee0f7 2909 * @}
ommpy 0:d383e2dee0f7 2910 */
ommpy 0:d383e2dee0f7 2911
ommpy 0:d383e2dee0f7 2912
ommpy 0:d383e2dee0f7 2913 /** @addtogroup Exported_macro
ommpy 0:d383e2dee0f7 2914 * @{
ommpy 0:d383e2dee0f7 2915 */
ommpy 0:d383e2dee0f7 2916
ommpy 0:d383e2dee0f7 2917 /****************************** ADC Instances *********************************/
ommpy 0:d383e2dee0f7 2918 #define IS_ADC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
ommpy 0:d383e2dee0f7 2919
ommpy 0:d383e2dee0f7 2920 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC)
ommpy 0:d383e2dee0f7 2921
ommpy 0:d383e2dee0f7 2922 /****************************** CRC Instances *********************************/
ommpy 0:d383e2dee0f7 2923 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
ommpy 0:d383e2dee0f7 2924
ommpy 0:d383e2dee0f7 2925 /******************************* DMA Instances ******************************/
ommpy 0:d383e2dee0f7 2926 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Channel1) || \
ommpy 0:d383e2dee0f7 2927 ((INSTANCE) == DMA1_Channel2) || \
ommpy 0:d383e2dee0f7 2928 ((INSTANCE) == DMA1_Channel3) || \
ommpy 0:d383e2dee0f7 2929 ((INSTANCE) == DMA1_Channel4) || \
ommpy 0:d383e2dee0f7 2930 ((INSTANCE) == DMA1_Channel5))
ommpy 0:d383e2dee0f7 2931
ommpy 0:d383e2dee0f7 2932 /****************************** GPIO Instances ********************************/
ommpy 0:d383e2dee0f7 2933 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
ommpy 0:d383e2dee0f7 2934 ((INSTANCE) == GPIOB) || \
ommpy 0:d383e2dee0f7 2935 ((INSTANCE) == GPIOC) || \
ommpy 0:d383e2dee0f7 2936 ((INSTANCE) == GPIOD) || \
ommpy 0:d383e2dee0f7 2937 ((INSTANCE) == GPIOF))
ommpy 0:d383e2dee0f7 2938
ommpy 0:d383e2dee0f7 2939 #define IS_GPIO_AF_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
ommpy 0:d383e2dee0f7 2940 ((INSTANCE) == GPIOB))
ommpy 0:d383e2dee0f7 2941
ommpy 0:d383e2dee0f7 2942 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
ommpy 0:d383e2dee0f7 2943 ((INSTANCE) == GPIOB))
ommpy 0:d383e2dee0f7 2944
ommpy 0:d383e2dee0f7 2945 /****************************** I2C Instances *********************************/
ommpy 0:d383e2dee0f7 2946 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
ommpy 0:d383e2dee0f7 2947 ((INSTANCE) == I2C2))
ommpy 0:d383e2dee0f7 2948
ommpy 0:d383e2dee0f7 2949
ommpy 0:d383e2dee0f7 2950 /****************************** IWDG Instances ********************************/
ommpy 0:d383e2dee0f7 2951 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG)
ommpy 0:d383e2dee0f7 2952
ommpy 0:d383e2dee0f7 2953 /****************************** RTC Instances *********************************/
ommpy 0:d383e2dee0f7 2954 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
ommpy 0:d383e2dee0f7 2955
ommpy 0:d383e2dee0f7 2956 /****************************** SMBUS Instances *********************************/
ommpy 0:d383e2dee0f7 2957 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
ommpy 0:d383e2dee0f7 2958
ommpy 0:d383e2dee0f7 2959 /****************************** SPI Instances *********************************/
ommpy 0:d383e2dee0f7 2960 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
ommpy 0:d383e2dee0f7 2961 ((INSTANCE) == SPI2))
ommpy 0:d383e2dee0f7 2962
ommpy 0:d383e2dee0f7 2963 /****************************** TIM Instances *********************************/
ommpy 0:d383e2dee0f7 2964 #define IS_TIM_INSTANCE(INSTANCE)\
ommpy 0:d383e2dee0f7 2965 (((INSTANCE) == TIM1) || \
ommpy 0:d383e2dee0f7 2966 ((INSTANCE) == TIM3) || \
ommpy 0:d383e2dee0f7 2967 ((INSTANCE) == TIM6) || \
ommpy 0:d383e2dee0f7 2968 ((INSTANCE) == TIM14) || \
ommpy 0:d383e2dee0f7 2969 ((INSTANCE) == TIM15) || \
ommpy 0:d383e2dee0f7 2970 ((INSTANCE) == TIM16) || \
ommpy 0:d383e2dee0f7 2971 ((INSTANCE) == TIM17))
ommpy 0:d383e2dee0f7 2972
ommpy 0:d383e2dee0f7 2973 #define IS_TIM_CC1_INSTANCE(INSTANCE)\
ommpy 0:d383e2dee0f7 2974 (((INSTANCE) == TIM1) || \
ommpy 0:d383e2dee0f7 2975 ((INSTANCE) == TIM3) || \
ommpy 0:d383e2dee0f7 2976 ((INSTANCE) == TIM14) || \
ommpy 0:d383e2dee0f7 2977 ((INSTANCE) == TIM15) || \
ommpy 0:d383e2dee0f7 2978 ((INSTANCE) == TIM16) || \
ommpy 0:d383e2dee0f7 2979 ((INSTANCE) == TIM17))
ommpy 0:d383e2dee0f7 2980
ommpy 0:d383e2dee0f7 2981 #define IS_TIM_CC2_INSTANCE(INSTANCE)\
ommpy 0:d383e2dee0f7 2982 (((INSTANCE) == TIM1) || \
ommpy 0:d383e2dee0f7 2983 ((INSTANCE) == TIM3) || \
ommpy 0:d383e2dee0f7 2984 ((INSTANCE) == TIM15))
ommpy 0:d383e2dee0f7 2985
ommpy 0:d383e2dee0f7 2986 #define IS_TIM_CC3_INSTANCE(INSTANCE)\
ommpy 0:d383e2dee0f7 2987 (((INSTANCE) == TIM1) || \
ommpy 0:d383e2dee0f7 2988 ((INSTANCE) == TIM3))
ommpy 0:d383e2dee0f7 2989
ommpy 0:d383e2dee0f7 2990 #define IS_TIM_CC4_INSTANCE(INSTANCE)\
ommpy 0:d383e2dee0f7 2991 (((INSTANCE) == TIM1) || \
ommpy 0:d383e2dee0f7 2992 ((INSTANCE) == TIM3))
ommpy 0:d383e2dee0f7 2993
ommpy 0:d383e2dee0f7 2994 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
ommpy 0:d383e2dee0f7 2995 (((INSTANCE) == TIM1) || \
ommpy 0:d383e2dee0f7 2996 ((INSTANCE) == TIM3))
ommpy 0:d383e2dee0f7 2997
ommpy 0:d383e2dee0f7 2998 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
ommpy 0:d383e2dee0f7 2999 (((INSTANCE) == TIM1) || \
ommpy 0:d383e2dee0f7 3000 ((INSTANCE) == TIM3))
ommpy 0:d383e2dee0f7 3001
ommpy 0:d383e2dee0f7 3002 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
ommpy 0:d383e2dee0f7 3003 (((INSTANCE) == TIM1) || \
ommpy 0:d383e2dee0f7 3004 ((INSTANCE) == TIM3) || \
ommpy 0:d383e2dee0f7 3005 ((INSTANCE) == TIM15))
ommpy 0:d383e2dee0f7 3006
ommpy 0:d383e2dee0f7 3007 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
ommpy 0:d383e2dee0f7 3008 (((INSTANCE) == TIM1) || \
ommpy 0:d383e2dee0f7 3009 ((INSTANCE) == TIM3) || \
ommpy 0:d383e2dee0f7 3010 ((INSTANCE) == TIM15))
ommpy 0:d383e2dee0f7 3011
ommpy 0:d383e2dee0f7 3012 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
ommpy 0:d383e2dee0f7 3013 (((INSTANCE) == TIM1) || \
ommpy 0:d383e2dee0f7 3014 ((INSTANCE) == TIM3))
ommpy 0:d383e2dee0f7 3015
ommpy 0:d383e2dee0f7 3016 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(INSTANCE)\
ommpy 0:d383e2dee0f7 3017 (((INSTANCE) == TIM1) || \
ommpy 0:d383e2dee0f7 3018 ((INSTANCE) == TIM3))
ommpy 0:d383e2dee0f7 3019
ommpy 0:d383e2dee0f7 3020 #define IS_TIM_HALL_INTERFACE_INSTANCE(INSTANCE)\
ommpy 0:d383e2dee0f7 3021 (((INSTANCE) == TIM1))
ommpy 0:d383e2dee0f7 3022
ommpy 0:d383e2dee0f7 3023 #define IS_TIM_XOR_INSTANCE(INSTANCE)\
ommpy 0:d383e2dee0f7 3024 (((INSTANCE) == TIM1) || \
ommpy 0:d383e2dee0f7 3025 ((INSTANCE) == TIM3))
ommpy 0:d383e2dee0f7 3026
ommpy 0:d383e2dee0f7 3027 #define IS_TIM_MASTER_INSTANCE(INSTANCE)\
ommpy 0:d383e2dee0f7 3028 (((INSTANCE) == TIM1) || \
ommpy 0:d383e2dee0f7 3029 ((INSTANCE) == TIM3) || \
ommpy 0:d383e2dee0f7 3030 ((INSTANCE) == TIM15))
ommpy 0:d383e2dee0f7 3031
ommpy 0:d383e2dee0f7 3032 #define IS_TIM_SLAVE_INSTANCE(INSTANCE)\
ommpy 0:d383e2dee0f7 3033 (((INSTANCE) == TIM1) || \
ommpy 0:d383e2dee0f7 3034 ((INSTANCE) == TIM3) || \
ommpy 0:d383e2dee0f7 3035 ((INSTANCE) == TIM15))
ommpy 0:d383e2dee0f7 3036
ommpy 0:d383e2dee0f7 3037 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE) (0)
ommpy 0:d383e2dee0f7 3038
ommpy 0:d383e2dee0f7 3039 #define IS_TIM_DMABURST_INSTANCE(INSTANCE)\
ommpy 0:d383e2dee0f7 3040 (((INSTANCE) == TIM1) || \
ommpy 0:d383e2dee0f7 3041 ((INSTANCE) == TIM3) || \
ommpy 0:d383e2dee0f7 3042 ((INSTANCE) == TIM15) || \
ommpy 0:d383e2dee0f7 3043 ((INSTANCE) == TIM16) || \
ommpy 0:d383e2dee0f7 3044 ((INSTANCE) == TIM17))
ommpy 0:d383e2dee0f7 3045
ommpy 0:d383e2dee0f7 3046 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
ommpy 0:d383e2dee0f7 3047 (((INSTANCE) == TIM1) || \
ommpy 0:d383e2dee0f7 3048 ((INSTANCE) == TIM15) || \
ommpy 0:d383e2dee0f7 3049 ((INSTANCE) == TIM16) || \
ommpy 0:d383e2dee0f7 3050 ((INSTANCE) == TIM17))
ommpy 0:d383e2dee0f7 3051
ommpy 0:d383e2dee0f7 3052 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
ommpy 0:d383e2dee0f7 3053 ((((INSTANCE) == TIM1) && \
ommpy 0:d383e2dee0f7 3054 (((CHANNEL) == TIM_CHANNEL_1) || \
ommpy 0:d383e2dee0f7 3055 ((CHANNEL) == TIM_CHANNEL_2) || \
ommpy 0:d383e2dee0f7 3056 ((CHANNEL) == TIM_CHANNEL_3) || \
ommpy 0:d383e2dee0f7 3057 ((CHANNEL) == TIM_CHANNEL_4))) \
ommpy 0:d383e2dee0f7 3058 || \
ommpy 0:d383e2dee0f7 3059 (((INSTANCE) == TIM3) && \
ommpy 0:d383e2dee0f7 3060 (((CHANNEL) == TIM_CHANNEL_1) || \
ommpy 0:d383e2dee0f7 3061 ((CHANNEL) == TIM_CHANNEL_2) || \
ommpy 0:d383e2dee0f7 3062 ((CHANNEL) == TIM_CHANNEL_3) || \
ommpy 0:d383e2dee0f7 3063 ((CHANNEL) == TIM_CHANNEL_4))) \
ommpy 0:d383e2dee0f7 3064 || \
ommpy 0:d383e2dee0f7 3065 (((INSTANCE) == TIM14) && \
ommpy 0:d383e2dee0f7 3066 (((CHANNEL) == TIM_CHANNEL_1))) \
ommpy 0:d383e2dee0f7 3067 || \
ommpy 0:d383e2dee0f7 3068 (((INSTANCE) == TIM15) && \
ommpy 0:d383e2dee0f7 3069 (((CHANNEL) == TIM_CHANNEL_1) || \
ommpy 0:d383e2dee0f7 3070 ((CHANNEL) == TIM_CHANNEL_2))) \
ommpy 0:d383e2dee0f7 3071 || \
ommpy 0:d383e2dee0f7 3072 (((INSTANCE) == TIM16) && \
ommpy 0:d383e2dee0f7 3073 (((CHANNEL) == TIM_CHANNEL_1))) \
ommpy 0:d383e2dee0f7 3074 || \
ommpy 0:d383e2dee0f7 3075 (((INSTANCE) == TIM17) && \
ommpy 0:d383e2dee0f7 3076 (((CHANNEL) == TIM_CHANNEL_1))))
ommpy 0:d383e2dee0f7 3077
ommpy 0:d383e2dee0f7 3078 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
ommpy 0:d383e2dee0f7 3079 ((((INSTANCE) == TIM1) && \
ommpy 0:d383e2dee0f7 3080 (((CHANNEL) == TIM_CHANNEL_1) || \
ommpy 0:d383e2dee0f7 3081 ((CHANNEL) == TIM_CHANNEL_2) || \
ommpy 0:d383e2dee0f7 3082 ((CHANNEL) == TIM_CHANNEL_3))) \
ommpy 0:d383e2dee0f7 3083 || \
ommpy 0:d383e2dee0f7 3084 (((INSTANCE) == TIM15) && \
ommpy 0:d383e2dee0f7 3085 ((CHANNEL) == TIM_CHANNEL_1)) \
ommpy 0:d383e2dee0f7 3086 || \
ommpy 0:d383e2dee0f7 3087 (((INSTANCE) == TIM16) && \
ommpy 0:d383e2dee0f7 3088 ((CHANNEL) == TIM_CHANNEL_1)) \
ommpy 0:d383e2dee0f7 3089 || \
ommpy 0:d383e2dee0f7 3090 (((INSTANCE) == TIM17) && \
ommpy 0:d383e2dee0f7 3091 ((CHANNEL) == TIM_CHANNEL_1)))
ommpy 0:d383e2dee0f7 3092
ommpy 0:d383e2dee0f7 3093 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
ommpy 0:d383e2dee0f7 3094 (((INSTANCE) == TIM1) || \
ommpy 0:d383e2dee0f7 3095 ((INSTANCE) == TIM3))
ommpy 0:d383e2dee0f7 3096
ommpy 0:d383e2dee0f7 3097 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
ommpy 0:d383e2dee0f7 3098 (((INSTANCE) == TIM1) || \
ommpy 0:d383e2dee0f7 3099 ((INSTANCE) == TIM15) || \
ommpy 0:d383e2dee0f7 3100 ((INSTANCE) == TIM16) || \
ommpy 0:d383e2dee0f7 3101 ((INSTANCE) == TIM17))
ommpy 0:d383e2dee0f7 3102
ommpy 0:d383e2dee0f7 3103 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
ommpy 0:d383e2dee0f7 3104 (((INSTANCE) == TIM1) || \
ommpy 0:d383e2dee0f7 3105 ((INSTANCE) == TIM3) || \
ommpy 0:d383e2dee0f7 3106 ((INSTANCE) == TIM14) || \
ommpy 0:d383e2dee0f7 3107 ((INSTANCE) == TIM15) || \
ommpy 0:d383e2dee0f7 3108 ((INSTANCE) == TIM16) || \
ommpy 0:d383e2dee0f7 3109 ((INSTANCE) == TIM17))
ommpy 0:d383e2dee0f7 3110
ommpy 0:d383e2dee0f7 3111 #define IS_TIM_DMA_INSTANCE(INSTANCE)\
ommpy 0:d383e2dee0f7 3112 (((INSTANCE) == TIM1) || \
ommpy 0:d383e2dee0f7 3113 ((INSTANCE) == TIM3) || \
ommpy 0:d383e2dee0f7 3114 ((INSTANCE) == TIM6) || \
ommpy 0:d383e2dee0f7 3115 ((INSTANCE) == TIM15) || \
ommpy 0:d383e2dee0f7 3116 ((INSTANCE) == TIM16) || \
ommpy 0:d383e2dee0f7 3117 ((INSTANCE) == TIM17))
ommpy 0:d383e2dee0f7 3118
ommpy 0:d383e2dee0f7 3119 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE)\
ommpy 0:d383e2dee0f7 3120 (((INSTANCE) == TIM1) || \
ommpy 0:d383e2dee0f7 3121 ((INSTANCE) == TIM3) || \
ommpy 0:d383e2dee0f7 3122 ((INSTANCE) == TIM15) || \
ommpy 0:d383e2dee0f7 3123 ((INSTANCE) == TIM16) || \
ommpy 0:d383e2dee0f7 3124 ((INSTANCE) == TIM17))
ommpy 0:d383e2dee0f7 3125
ommpy 0:d383e2dee0f7 3126 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE)\
ommpy 0:d383e2dee0f7 3127 (((INSTANCE) == TIM1) || \
ommpy 0:d383e2dee0f7 3128 ((INSTANCE) == TIM15) || \
ommpy 0:d383e2dee0f7 3129 ((INSTANCE) == TIM16) || \
ommpy 0:d383e2dee0f7 3130 ((INSTANCE) == TIM17))
ommpy 0:d383e2dee0f7 3131
ommpy 0:d383e2dee0f7 3132 #define IS_TIM_REMAP_INSTANCE(INSTANCE)\
ommpy 0:d383e2dee0f7 3133 ((INSTANCE) == TIM14)
ommpy 0:d383e2dee0f7 3134
ommpy 0:d383e2dee0f7 3135 /******************** USART Instances : Synchronous mode **********************/
ommpy 0:d383e2dee0f7 3136 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
ommpy 0:d383e2dee0f7 3137 ((INSTANCE) == USART2))
ommpy 0:d383e2dee0f7 3138
ommpy 0:d383e2dee0f7 3139 /******************** USART Instances : auto Baud rate detection **************/
ommpy 0:d383e2dee0f7 3140 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
ommpy 0:d383e2dee0f7 3141
ommpy 0:d383e2dee0f7 3142 /******************** UART Instances : Asynchronous mode **********************/
ommpy 0:d383e2dee0f7 3143 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
ommpy 0:d383e2dee0f7 3144 ((INSTANCE) == USART2))
ommpy 0:d383e2dee0f7 3145
ommpy 0:d383e2dee0f7 3146 /******************** UART Instances : Half-Duplex mode **********************/
ommpy 0:d383e2dee0f7 3147 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
ommpy 0:d383e2dee0f7 3148 ((INSTANCE) == USART2))
ommpy 0:d383e2dee0f7 3149
ommpy 0:d383e2dee0f7 3150 /****************** UART Instances : Hardware Flow control ********************/
ommpy 0:d383e2dee0f7 3151 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
ommpy 0:d383e2dee0f7 3152 ((INSTANCE) == USART2))
ommpy 0:d383e2dee0f7 3153
ommpy 0:d383e2dee0f7 3154 /****************** UART Instances : Auto Baud Rate detection ********************/
ommpy 0:d383e2dee0f7 3155 #define IS_UART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) ((INSTANCE) == USART1)
ommpy 0:d383e2dee0f7 3156
ommpy 0:d383e2dee0f7 3157 /****************** UART Instances : Driver enable detection ********************/
ommpy 0:d383e2dee0f7 3158 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
ommpy 0:d383e2dee0f7 3159 ((INSTANCE) == USART2))
ommpy 0:d383e2dee0f7 3160 /****************************** WWDG Instances ********************************/
ommpy 0:d383e2dee0f7 3161 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG)
ommpy 0:d383e2dee0f7 3162
ommpy 0:d383e2dee0f7 3163 /**
ommpy 0:d383e2dee0f7 3164 * @}
ommpy 0:d383e2dee0f7 3165 */
ommpy 0:d383e2dee0f7 3166
ommpy 0:d383e2dee0f7 3167
ommpy 0:d383e2dee0f7 3168 /******************************************************************************/
ommpy 0:d383e2dee0f7 3169 /* For a painless codes migration between the STM32F0xx device product */
ommpy 0:d383e2dee0f7 3170 /* lines, the aliases defined below are put in place to overcome the */
ommpy 0:d383e2dee0f7 3171 /* differences in the interrupt handlers and IRQn definitions. */
ommpy 0:d383e2dee0f7 3172 /* No need to update developed interrupt code when moving across */
ommpy 0:d383e2dee0f7 3173 /* product lines within the same STM32F0 Family */
ommpy 0:d383e2dee0f7 3174 /******************************************************************************/
ommpy 0:d383e2dee0f7 3175
ommpy 0:d383e2dee0f7 3176 /* Aliases for __IRQn */
ommpy 0:d383e2dee0f7 3177 #define RCC_CRS_IRQn RCC_IRQn
ommpy 0:d383e2dee0f7 3178 #define DMA1_Channel4_5_6_7_IRQn DMA1_Channel4_5_IRQn
ommpy 0:d383e2dee0f7 3179 #define ADC1_COMP_IRQn ADC1_IRQn
ommpy 0:d383e2dee0f7 3180 #define TIM6_DAC_IRQn TIM6_IRQn
ommpy 0:d383e2dee0f7 3181
ommpy 0:d383e2dee0f7 3182 /* Aliases for __IRQHandler */
ommpy 0:d383e2dee0f7 3183 #define RCC_CRS_IRQHandler RCC_IRQHandler
ommpy 0:d383e2dee0f7 3184 #define DMA1_Channel4_5_6_7_IRQHandler DMA1_Channel4_5_IRQHandler
ommpy 0:d383e2dee0f7 3185 #define ADC1_COMP_IRQHandler ADC1_IRQHandler
ommpy 0:d383e2dee0f7 3186 #define TIM6_DAC_IRQHandler TIM6_IRQHandler
ommpy 0:d383e2dee0f7 3187
ommpy 0:d383e2dee0f7 3188 #ifdef __cplusplus
ommpy 0:d383e2dee0f7 3189 }
ommpy 0:d383e2dee0f7 3190 #endif /* __cplusplus */
ommpy 0:d383e2dee0f7 3191
ommpy 0:d383e2dee0f7 3192 #endif /* __STM32F030x8_H */
ommpy 0:d383e2dee0f7 3193
ommpy 0:d383e2dee0f7 3194 /**
ommpy 0:d383e2dee0f7 3195 * @}
ommpy 0:d383e2dee0f7 3196 */
ommpy 0:d383e2dee0f7 3197
ommpy 0:d383e2dee0f7 3198 /**
ommpy 0:d383e2dee0f7 3199 * @}
ommpy 0:d383e2dee0f7 3200 */
ommpy 0:d383e2dee0f7 3201
ommpy 0:d383e2dee0f7 3202 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/