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Dependencies:   mbed Watchdog stm32-sensor-base2

mbed/TARGET_NUCLEO_F103RB/TOOLCHAIN_ARM_STD/mpu_armv7.h@2:b7fdc74e5c5d, 2020-07-07 (annotated)

Committer:
ommpy
Date:
Tue Jul 07 15:19:06 2020 +0530
Revision:
2:b7fdc74e5c5d
new board files

Who changed what in which revision?

UserRevisionLine numberNew contents of line
ommpy 2:b7fdc74e5c5d 1 /******************************************************************************
ommpy 2:b7fdc74e5c5d 2 * @file mpu_armv7.h
ommpy 2:b7fdc74e5c5d 3 * @brief CMSIS MPU API for Armv7-M MPU
ommpy 2:b7fdc74e5c5d 4 * @version V5.0.5
ommpy 2:b7fdc74e5c5d 5 * @date 06. September 2018
ommpy 2:b7fdc74e5c5d 6 ******************************************************************************/
ommpy 2:b7fdc74e5c5d 7 /*
ommpy 2:b7fdc74e5c5d 8 * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
ommpy 2:b7fdc74e5c5d 9 *
ommpy 2:b7fdc74e5c5d 10 * SPDX-License-Identifier: Apache-2.0
ommpy 2:b7fdc74e5c5d 11 *
ommpy 2:b7fdc74e5c5d 12 * Licensed under the Apache License, Version 2.0 (the License); you may
ommpy 2:b7fdc74e5c5d 13 * not use this file except in compliance with the License.
ommpy 2:b7fdc74e5c5d 14 * You may obtain a copy of the License at
ommpy 2:b7fdc74e5c5d 15 *
ommpy 2:b7fdc74e5c5d 16 * www.apache.org/licenses/LICENSE-2.0
ommpy 2:b7fdc74e5c5d 17 *
ommpy 2:b7fdc74e5c5d 18 * Unless required by applicable law or agreed to in writing, software
ommpy 2:b7fdc74e5c5d 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
ommpy 2:b7fdc74e5c5d 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
ommpy 2:b7fdc74e5c5d 21 * See the License for the specific language governing permissions and
ommpy 2:b7fdc74e5c5d 22 * limitations under the License.
ommpy 2:b7fdc74e5c5d 23 */
ommpy 2:b7fdc74e5c5d 24
ommpy 2:b7fdc74e5c5d 25 #if defined ( __ICCARM__ )
ommpy 2:b7fdc74e5c5d 26 #pragma system_include /* treat file as system include file for MISRA check */
ommpy 2:b7fdc74e5c5d 27 #elif defined (__clang__)
ommpy 2:b7fdc74e5c5d 28 #pragma clang system_header /* treat file as system include file */
ommpy 2:b7fdc74e5c5d 29 #endif
ommpy 2:b7fdc74e5c5d 30
ommpy 2:b7fdc74e5c5d 31 #ifndef ARM_MPU_ARMV7_H
ommpy 2:b7fdc74e5c5d 32 #define ARM_MPU_ARMV7_H
ommpy 2:b7fdc74e5c5d 33
ommpy 2:b7fdc74e5c5d 34 #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U) ///!< MPU Region Size 32 Bytes
ommpy 2:b7fdc74e5c5d 35 #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U) ///!< MPU Region Size 64 Bytes
ommpy 2:b7fdc74e5c5d 36 #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U) ///!< MPU Region Size 128 Bytes
ommpy 2:b7fdc74e5c5d 37 #define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U) ///!< MPU Region Size 256 Bytes
ommpy 2:b7fdc74e5c5d 38 #define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U) ///!< MPU Region Size 512 Bytes
ommpy 2:b7fdc74e5c5d 39 #define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U) ///!< MPU Region Size 1 KByte
ommpy 2:b7fdc74e5c5d 40 #define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU) ///!< MPU Region Size 2 KBytes
ommpy 2:b7fdc74e5c5d 41 #define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU) ///!< MPU Region Size 4 KBytes
ommpy 2:b7fdc74e5c5d 42 #define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU) ///!< MPU Region Size 8 KBytes
ommpy 2:b7fdc74e5c5d 43 #define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU) ///!< MPU Region Size 16 KBytes
ommpy 2:b7fdc74e5c5d 44 #define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU) ///!< MPU Region Size 32 KBytes
ommpy 2:b7fdc74e5c5d 45 #define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU) ///!< MPU Region Size 64 KBytes
ommpy 2:b7fdc74e5c5d 46 #define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U) ///!< MPU Region Size 128 KBytes
ommpy 2:b7fdc74e5c5d 47 #define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U) ///!< MPU Region Size 256 KBytes
ommpy 2:b7fdc74e5c5d 48 #define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U) ///!< MPU Region Size 512 KBytes
ommpy 2:b7fdc74e5c5d 49 #define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U) ///!< MPU Region Size 1 MByte
ommpy 2:b7fdc74e5c5d 50 #define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U) ///!< MPU Region Size 2 MBytes
ommpy 2:b7fdc74e5c5d 51 #define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U) ///!< MPU Region Size 4 MBytes
ommpy 2:b7fdc74e5c5d 52 #define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U) ///!< MPU Region Size 8 MBytes
ommpy 2:b7fdc74e5c5d 53 #define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U) ///!< MPU Region Size 16 MBytes
ommpy 2:b7fdc74e5c5d 54 #define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U) ///!< MPU Region Size 32 MBytes
ommpy 2:b7fdc74e5c5d 55 #define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U) ///!< MPU Region Size 64 MBytes
ommpy 2:b7fdc74e5c5d 56 #define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU) ///!< MPU Region Size 128 MBytes
ommpy 2:b7fdc74e5c5d 57 #define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU) ///!< MPU Region Size 256 MBytes
ommpy 2:b7fdc74e5c5d 58 #define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU) ///!< MPU Region Size 512 MBytes
ommpy 2:b7fdc74e5c5d 59 #define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU) ///!< MPU Region Size 1 GByte
ommpy 2:b7fdc74e5c5d 60 #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU) ///!< MPU Region Size 2 GBytes
ommpy 2:b7fdc74e5c5d 61 #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU) ///!< MPU Region Size 4 GBytes
ommpy 2:b7fdc74e5c5d 62
ommpy 2:b7fdc74e5c5d 63 #define ARM_MPU_AP_NONE 0U ///!< MPU Access Permission no access
ommpy 2:b7fdc74e5c5d 64 #define ARM_MPU_AP_PRIV 1U ///!< MPU Access Permission privileged access only
ommpy 2:b7fdc74e5c5d 65 #define ARM_MPU_AP_URO 2U ///!< MPU Access Permission unprivileged access read-only
ommpy 2:b7fdc74e5c5d 66 #define ARM_MPU_AP_FULL 3U ///!< MPU Access Permission full access
ommpy 2:b7fdc74e5c5d 67 #define ARM_MPU_AP_PRO 5U ///!< MPU Access Permission privileged access read-only
ommpy 2:b7fdc74e5c5d 68 #define ARM_MPU_AP_RO 6U ///!< MPU Access Permission read-only access
ommpy 2:b7fdc74e5c5d 69
ommpy 2:b7fdc74e5c5d 70 /** MPU Region Base Address Register Value
ommpy 2:b7fdc74e5c5d 71 *
ommpy 2:b7fdc74e5c5d 72 * \param Region The region to be configured, number 0 to 15.
ommpy 2:b7fdc74e5c5d 73 * \param BaseAddress The base address for the region.
ommpy 2:b7fdc74e5c5d 74 */
ommpy 2:b7fdc74e5c5d 75 #define ARM_MPU_RBAR(Region, BaseAddress) \
ommpy 2:b7fdc74e5c5d 76 (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
ommpy 2:b7fdc74e5c5d 77 ((Region) & MPU_RBAR_REGION_Msk) | \
ommpy 2:b7fdc74e5c5d 78 (MPU_RBAR_VALID_Msk))
ommpy 2:b7fdc74e5c5d 79
ommpy 2:b7fdc74e5c5d 80 /**
ommpy 2:b7fdc74e5c5d 81 * MPU Memory Access Attributes
ommpy 2:b7fdc74e5c5d 82 *
ommpy 2:b7fdc74e5c5d 83 * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
ommpy 2:b7fdc74e5c5d 84 * \param IsShareable Region is shareable between multiple bus masters.
ommpy 2:b7fdc74e5c5d 85 * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
ommpy 2:b7fdc74e5c5d 86 * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
ommpy 2:b7fdc74e5c5d 87 */
ommpy 2:b7fdc74e5c5d 88 #define ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable) \
ommpy 2:b7fdc74e5c5d 89 ((((TypeExtField) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
ommpy 2:b7fdc74e5c5d 90 (((IsShareable) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
ommpy 2:b7fdc74e5c5d 91 (((IsCacheable) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
ommpy 2:b7fdc74e5c5d 92 (((IsBufferable) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk))
ommpy 2:b7fdc74e5c5d 93
ommpy 2:b7fdc74e5c5d 94 /**
ommpy 2:b7fdc74e5c5d 95 * MPU Region Attribute and Size Register Value
ommpy 2:b7fdc74e5c5d 96 *
ommpy 2:b7fdc74e5c5d 97 * \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
ommpy 2:b7fdc74e5c5d 98 * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
ommpy 2:b7fdc74e5c5d 99 * \param AccessAttributes Memory access attribution, see \ref ARM_MPU_ACCESS_.
ommpy 2:b7fdc74e5c5d 100 * \param SubRegionDisable Sub-region disable field.
ommpy 2:b7fdc74e5c5d 101 * \param Size Region size of the region to be configured, for example 4K, 8K.
ommpy 2:b7fdc74e5c5d 102 */
ommpy 2:b7fdc74e5c5d 103 #define ARM_MPU_RASR_EX(DisableExec, AccessPermission, AccessAttributes, SubRegionDisable, Size) \
ommpy 2:b7fdc74e5c5d 104 ((((DisableExec) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
ommpy 2:b7fdc74e5c5d 105 (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
ommpy 2:b7fdc74e5c5d 106 (((AccessAttributes) & (MPU_RASR_TEX_Msk | MPU_RASR_S_Msk | MPU_RASR_C_Msk | MPU_RASR_B_Msk))) | \
ommpy 2:b7fdc74e5c5d 107 (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
ommpy 2:b7fdc74e5c5d 108 (((Size) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
ommpy 2:b7fdc74e5c5d 109 (((MPU_RASR_ENABLE_Msk))))
ommpy 2:b7fdc74e5c5d 110
ommpy 2:b7fdc74e5c5d 111 /**
ommpy 2:b7fdc74e5c5d 112 * MPU Region Attribute and Size Register Value
ommpy 2:b7fdc74e5c5d 113 *
ommpy 2:b7fdc74e5c5d 114 * \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
ommpy 2:b7fdc74e5c5d 115 * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
ommpy 2:b7fdc74e5c5d 116 * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
ommpy 2:b7fdc74e5c5d 117 * \param IsShareable Region is shareable between multiple bus masters.
ommpy 2:b7fdc74e5c5d 118 * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
ommpy 2:b7fdc74e5c5d 119 * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
ommpy 2:b7fdc74e5c5d 120 * \param SubRegionDisable Sub-region disable field.
ommpy 2:b7fdc74e5c5d 121 * \param Size Region size of the region to be configured, for example 4K, 8K.
ommpy 2:b7fdc74e5c5d 122 */
ommpy 2:b7fdc74e5c5d 123 #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
ommpy 2:b7fdc74e5c5d 124 ARM_MPU_RASR_EX(DisableExec, AccessPermission, ARM_MPU_ACCESS_(TypeExtField, IsShareable, IsCacheable, IsBufferable), SubRegionDisable, Size)
ommpy 2:b7fdc74e5c5d 125
ommpy 2:b7fdc74e5c5d 126 /**
ommpy 2:b7fdc74e5c5d 127 * MPU Memory Access Attribute for strongly ordered memory.
ommpy 2:b7fdc74e5c5d 128 * - TEX: 000b
ommpy 2:b7fdc74e5c5d 129 * - Shareable
ommpy 2:b7fdc74e5c5d 130 * - Non-cacheable
ommpy 2:b7fdc74e5c5d 131 * - Non-bufferable
ommpy 2:b7fdc74e5c5d 132 */
ommpy 2:b7fdc74e5c5d 133 #define ARM_MPU_ACCESS_ORDERED ARM_MPU_ACCESS_(0U, 1U, 0U, 0U)
ommpy 2:b7fdc74e5c5d 134
ommpy 2:b7fdc74e5c5d 135 /**
ommpy 2:b7fdc74e5c5d 136 * MPU Memory Access Attribute for device memory.
ommpy 2:b7fdc74e5c5d 137 * - TEX: 000b (if non-shareable) or 010b (if shareable)
ommpy 2:b7fdc74e5c5d 138 * - Shareable or non-shareable
ommpy 2:b7fdc74e5c5d 139 * - Non-cacheable
ommpy 2:b7fdc74e5c5d 140 * - Bufferable (if shareable) or non-bufferable (if non-shareable)
ommpy 2:b7fdc74e5c5d 141 *
ommpy 2:b7fdc74e5c5d 142 * \param IsShareable Configures the device memory as shareable or non-shareable.
ommpy 2:b7fdc74e5c5d 143 */
ommpy 2:b7fdc74e5c5d 144 #define ARM_MPU_ACCESS_DEVICE(IsShareable) ((IsShareable) ? ARM_MPU_ACCESS_(0U, 1U, 0U, 1U) : ARM_MPU_ACCESS_(2U, 0U, 0U, 0U))
ommpy 2:b7fdc74e5c5d 145
ommpy 2:b7fdc74e5c5d 146 /**
ommpy 2:b7fdc74e5c5d 147 * MPU Memory Access Attribute for normal memory.
ommpy 2:b7fdc74e5c5d 148 * - TEX: 1BBb (reflecting outer cacheability rules)
ommpy 2:b7fdc74e5c5d 149 * - Shareable or non-shareable
ommpy 2:b7fdc74e5c5d 150 * - Cacheable or non-cacheable (reflecting inner cacheability rules)
ommpy 2:b7fdc74e5c5d 151 * - Bufferable or non-bufferable (reflecting inner cacheability rules)
ommpy 2:b7fdc74e5c5d 152 *
ommpy 2:b7fdc74e5c5d 153 * \param OuterCp Configures the outer cache policy.
ommpy 2:b7fdc74e5c5d 154 * \param InnerCp Configures the inner cache policy.
ommpy 2:b7fdc74e5c5d 155 * \param IsShareable Configures the memory as shareable or non-shareable.
ommpy 2:b7fdc74e5c5d 156 */
ommpy 2:b7fdc74e5c5d 157 #define ARM_MPU_ACCESS_NORMAL(OuterCp, InnerCp, IsShareable) ARM_MPU_ACCESS_((4U | (OuterCp)), IsShareable, ((InnerCp) & 2U), ((InnerCp) & 1U))
ommpy 2:b7fdc74e5c5d 158
ommpy 2:b7fdc74e5c5d 159 /**
ommpy 2:b7fdc74e5c5d 160 * MPU Memory Access Attribute non-cacheable policy.
ommpy 2:b7fdc74e5c5d 161 */
ommpy 2:b7fdc74e5c5d 162 #define ARM_MPU_CACHEP_NOCACHE 0U
ommpy 2:b7fdc74e5c5d 163
ommpy 2:b7fdc74e5c5d 164 /**
ommpy 2:b7fdc74e5c5d 165 * MPU Memory Access Attribute write-back, write and read allocate policy.
ommpy 2:b7fdc74e5c5d 166 */
ommpy 2:b7fdc74e5c5d 167 #define ARM_MPU_CACHEP_WB_WRA 1U
ommpy 2:b7fdc74e5c5d 168
ommpy 2:b7fdc74e5c5d 169 /**
ommpy 2:b7fdc74e5c5d 170 * MPU Memory Access Attribute write-through, no write allocate policy.
ommpy 2:b7fdc74e5c5d 171 */
ommpy 2:b7fdc74e5c5d 172 #define ARM_MPU_CACHEP_WT_NWA 2U
ommpy 2:b7fdc74e5c5d 173
ommpy 2:b7fdc74e5c5d 174 /**
ommpy 2:b7fdc74e5c5d 175 * MPU Memory Access Attribute write-back, no write allocate policy.
ommpy 2:b7fdc74e5c5d 176 */
ommpy 2:b7fdc74e5c5d 177 #define ARM_MPU_CACHEP_WB_NWA 3U
ommpy 2:b7fdc74e5c5d 178
ommpy 2:b7fdc74e5c5d 179
ommpy 2:b7fdc74e5c5d 180 /**
ommpy 2:b7fdc74e5c5d 181 * Struct for a single MPU Region
ommpy 2:b7fdc74e5c5d 182 */
ommpy 2:b7fdc74e5c5d 183 typedef struct {
ommpy 2:b7fdc74e5c5d 184 uint32_t RBAR; //!< The region base address register value (RBAR)
ommpy 2:b7fdc74e5c5d 185 uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
ommpy 2:b7fdc74e5c5d 186 } ARM_MPU_Region_t;
ommpy 2:b7fdc74e5c5d 187
ommpy 2:b7fdc74e5c5d 188 /** Enable the MPU.
ommpy 2:b7fdc74e5c5d 189 * \param MPU_Control Default access permissions for unconfigured regions.
ommpy 2:b7fdc74e5c5d 190 */
ommpy 2:b7fdc74e5c5d 191 __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
ommpy 2:b7fdc74e5c5d 192 {
ommpy 2:b7fdc74e5c5d 193 __DSB();
ommpy 2:b7fdc74e5c5d 194 __ISB();
ommpy 2:b7fdc74e5c5d 195 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
ommpy 2:b7fdc74e5c5d 196 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
ommpy 2:b7fdc74e5c5d 197 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
ommpy 2:b7fdc74e5c5d 198 #endif
ommpy 2:b7fdc74e5c5d 199 }
ommpy 2:b7fdc74e5c5d 200
ommpy 2:b7fdc74e5c5d 201 /** Disable the MPU.
ommpy 2:b7fdc74e5c5d 202 */
ommpy 2:b7fdc74e5c5d 203 __STATIC_INLINE void ARM_MPU_Disable(void)
ommpy 2:b7fdc74e5c5d 204 {
ommpy 2:b7fdc74e5c5d 205 __DSB();
ommpy 2:b7fdc74e5c5d 206 __ISB();
ommpy 2:b7fdc74e5c5d 207 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
ommpy 2:b7fdc74e5c5d 208 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
ommpy 2:b7fdc74e5c5d 209 #endif
ommpy 2:b7fdc74e5c5d 210 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
ommpy 2:b7fdc74e5c5d 211 }
ommpy 2:b7fdc74e5c5d 212
ommpy 2:b7fdc74e5c5d 213 /** Clear and disable the given MPU region.
ommpy 2:b7fdc74e5c5d 214 * \param rnr Region number to be cleared.
ommpy 2:b7fdc74e5c5d 215 */
ommpy 2:b7fdc74e5c5d 216 __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
ommpy 2:b7fdc74e5c5d 217 {
ommpy 2:b7fdc74e5c5d 218 MPU->RNR = rnr;
ommpy 2:b7fdc74e5c5d 219 MPU->RASR = 0U;
ommpy 2:b7fdc74e5c5d 220 }
ommpy 2:b7fdc74e5c5d 221
ommpy 2:b7fdc74e5c5d 222 /** Configure an MPU region.
ommpy 2:b7fdc74e5c5d 223 * \param rbar Value for RBAR register.
ommpy 2:b7fdc74e5c5d 224 * \param rsar Value for RSAR register.
ommpy 2:b7fdc74e5c5d 225 */
ommpy 2:b7fdc74e5c5d 226 __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
ommpy 2:b7fdc74e5c5d 227 {
ommpy 2:b7fdc74e5c5d 228 MPU->RBAR = rbar;
ommpy 2:b7fdc74e5c5d 229 MPU->RASR = rasr;
ommpy 2:b7fdc74e5c5d 230 }
ommpy 2:b7fdc74e5c5d 231
ommpy 2:b7fdc74e5c5d 232 /** Configure the given MPU region.
ommpy 2:b7fdc74e5c5d 233 * \param rnr Region number to be configured.
ommpy 2:b7fdc74e5c5d 234 * \param rbar Value for RBAR register.
ommpy 2:b7fdc74e5c5d 235 * \param rsar Value for RSAR register.
ommpy 2:b7fdc74e5c5d 236 */
ommpy 2:b7fdc74e5c5d 237 __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
ommpy 2:b7fdc74e5c5d 238 {
ommpy 2:b7fdc74e5c5d 239 MPU->RNR = rnr;
ommpy 2:b7fdc74e5c5d 240 MPU->RBAR = rbar;
ommpy 2:b7fdc74e5c5d 241 MPU->RASR = rasr;
ommpy 2:b7fdc74e5c5d 242 }
ommpy 2:b7fdc74e5c5d 243
ommpy 2:b7fdc74e5c5d 244 /** Memcopy with strictly ordered memory access, e.g. for register targets.
ommpy 2:b7fdc74e5c5d 245 * \param dst Destination data is copied to.
ommpy 2:b7fdc74e5c5d 246 * \param src Source data is copied from.
ommpy 2:b7fdc74e5c5d 247 * \param len Amount of data words to be copied.
ommpy 2:b7fdc74e5c5d 248 */
ommpy 2:b7fdc74e5c5d 249 __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
ommpy 2:b7fdc74e5c5d 250 {
ommpy 2:b7fdc74e5c5d 251 uint32_t i;
ommpy 2:b7fdc74e5c5d 252 for (i = 0U; i < len; ++i)
ommpy 2:b7fdc74e5c5d 253 {
ommpy 2:b7fdc74e5c5d 254 dst[i] = src[i];
ommpy 2:b7fdc74e5c5d 255 }
ommpy 2:b7fdc74e5c5d 256 }
ommpy 2:b7fdc74e5c5d 257
ommpy 2:b7fdc74e5c5d 258 /** Load the given number of MPU regions from a table.
ommpy 2:b7fdc74e5c5d 259 * \param table Pointer to the MPU configuration table.
ommpy 2:b7fdc74e5c5d 260 * \param cnt Amount of regions to be configured.
ommpy 2:b7fdc74e5c5d 261 */
ommpy 2:b7fdc74e5c5d 262 __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
ommpy 2:b7fdc74e5c5d 263 {
ommpy 2:b7fdc74e5c5d 264 const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
ommpy 2:b7fdc74e5c5d 265 while (cnt > MPU_TYPE_RALIASES) {
ommpy 2:b7fdc74e5c5d 266 orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
ommpy 2:b7fdc74e5c5d 267 table += MPU_TYPE_RALIASES;
ommpy 2:b7fdc74e5c5d 268 cnt -= MPU_TYPE_RALIASES;
ommpy 2:b7fdc74e5c5d 269 }
ommpy 2:b7fdc74e5c5d 270 orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
ommpy 2:b7fdc74e5c5d 271 }
ommpy 2:b7fdc74e5c5d 272
ommpy 2:b7fdc74e5c5d 273 #endif