one wire driver

Dependents:   09_PT1000 10_PT1000 11_PT1000

Committer:
rs27
Date:
Sat Jul 26 07:27:00 2014 +0000
Revision:
5:d94037eb31ed
Parent:
4:c29e67d55f86
one wire driver

Who changed what in which revision?

UserRevisionLine numberNew contents of line
rs27 0:c57706d25cf0 1 // \file ds2482x_app.h \brief Dallas DS2482 I2C-to-Dallas1Wire Master Library.
rs27 0:c57706d25cf0 2 //*****************************************************************************
rs27 0:c57706d25cf0 3 // Target MCU : Atmel AVR Series
rs27 0:c57706d25cf0 4 //*****************************************************************************
rs27 0:c57706d25cf0 5 //
rs27 0:c57706d25cf0 6
rs27 0:c57706d25cf0 7 #ifndef DS2482_H
rs27 0:c57706d25cf0 8 #define DS2482_H
rs27 0:c57706d25cf0 9
rs27 0:c57706d25cf0 10 #include "mbed.h"
rs27 0:c57706d25cf0 11
rs27 1:0950824b1ca3 12 #define OW_MASTER_START 0
rs27 1:0950824b1ca3 13 #define OW_MASTER_DEBUG 0
rs27 0:c57706d25cf0 14
rs27 0:c57706d25cf0 15 // constants/macros/typdefs
rs27 0:c57706d25cf0 16 #define OW_I2C_DEVICE 0x30 // < Change this to the address of your 1-Wire master
rs27 0:c57706d25cf0 17
rs27 0:c57706d25cf0 18 #define FALSE 0
rs27 0:c57706d25cf0 19 #define TRUE 1
rs27 0:c57706d25cf0 20
rs27 0:c57706d25cf0 21 #define NAK 0
rs27 0:c57706d25cf0 22 #define ACK 1
rs27 0:c57706d25cf0 23
rs27 0:c57706d25cf0 24 #define I2C_READ 1
rs27 0:c57706d25cf0 25 #define I2C_WRITE 0
rs27 0:c57706d25cf0 26
rs27 1:0950824b1ca3 27 #define POLL_LIMIT 100
rs27 0:c57706d25cf0 28
rs27 0:c57706d25cf0 29 // Maximale Anzahl der Bausteine am Bus
rs27 0:c57706d25cf0 30 #define OW_MAX_DEVICES 16
rs27 0:c57706d25cf0 31 #define OW_SECOND_PORT 8
rs27 0:c57706d25cf0 32
rs27 0:c57706d25cf0 33 // Memory definitions
rs27 0:c57706d25cf0 34 #define OW_SCRATCHPAD_BYTES 9
rs27 0:c57706d25cf0 35 #define OW_ROM_CODE_BYTES 8
rs27 0:c57706d25cf0 36 #define OW_CRC_BYTE 8
rs27 0:c57706d25cf0 37
rs27 0:c57706d25cf0 38
rs27 0:c57706d25cf0 39 //-----------------------------------------------------------------------------
rs27 0:c57706d25cf0 40
rs27 0:c57706d25cf0 41 // Commands
rs27 0:c57706d25cf0 42 #define OW_CMD_SEARCH_ROM 0xF0 // Command Search ROM code
rs27 0:c57706d25cf0 43 #define OW_CMD_READ_ROM 0x33 // Command Read ROM code
rs27 0:c57706d25cf0 44 #define OW_CMD_MATCH_ROM 0x55 // Command Match ROM code
rs27 0:c57706d25cf0 45 #define OW_CMD_SKIP_ROM 0xCC // Command Skip ROM code
rs27 0:c57706d25cf0 46 #define OW_CMD_ALARM_SEARCH 0xEC // Command Alarm Search
rs27 0:c57706d25cf0 47
rs27 0:c57706d25cf0 48 #define OW_CMD_CONVERT_T 0x44 // Command Initiate temperature conversion
rs27 0:c57706d25cf0 49 #define OW_CMD_WRITE_SCRATCHPAD 0x4E // Command Write scratchpad
rs27 0:c57706d25cf0 50 #define OW_CMD_READ_SCRATCHPAD 0xBE // Command Read scratchpad
rs27 0:c57706d25cf0 51 #define OW_CMD_COPY_SCRATCHPAD 0x48 // Command Copy scratchpad
rs27 0:c57706d25cf0 52 #define OW_CMD_RECALL_EE 0xB8 // Command Recall Th and Tl from EEPROM
rs27 0:c57706d25cf0 53 #define OW_CMD_READ_POWER_SUPPLY 0xB4 // Command Signal power supply mode
rs27 0:c57706d25cf0 54
rs27 0:c57706d25cf0 55 // Error codes
rs27 1:0950824b1ca3 56 #define OW_RESET_ERROR 0x01
rs27 1:0950824b1ca3 57 #define OW_CRC_ERROR 0x02
rs27 0:c57706d25cf0 58
rs27 0:c57706d25cf0 59 // DS2482 command defines
rs27 0:c57706d25cf0 60 #define DS2482_CMD_DRST 0xF0 //< DS2482 Device Reset
rs27 0:c57706d25cf0 61 #define DS2482_CMD_WCFG 0xD2 //< DS2482 Write Configuration
rs27 0:c57706d25cf0 62 #define DS2482_CMD_CHSL 0xC3 //< DS2482 Channel Select
rs27 0:c57706d25cf0 63 #define DS2482_CMD_SRP 0xE1 //< DS2482 Set Read Pointer
rs27 0:c57706d25cf0 64 #define DS2482_CMD_1WRS 0xB4 //< DS2482 1-Wire Reset
rs27 0:c57706d25cf0 65 #define DS2482_CMD_1WWB 0xA5 //< DS2482 1-Wire Write Byte
rs27 0:c57706d25cf0 66 #define DS2482_CMD_1WRB 0x96 //< DS2482 1-Wire Read Byte
rs27 0:c57706d25cf0 67 #define DS2482_CMD_1WSB 0x87 //< DS2482 1-Wire Single Bit
rs27 0:c57706d25cf0 68 #define DS2482_CMD_1WT 0x78 //< DS2482 1-Wire Triplet
rs27 0:c57706d25cf0 69
rs27 0:c57706d25cf0 70 // DS2482 status register bit defines
rs27 0:c57706d25cf0 71 #define DS2482_STATUS_1WB 0x01 //< DS2482 Status 1-Wire Busy
rs27 0:c57706d25cf0 72 #define DS2482_STATUS_PPD 0x02 //< DS2482 Status Presence Pulse Detect
rs27 0:c57706d25cf0 73 #define DS2482_STATUS_SD 0x04 //< DS2482 Status Short Detected
rs27 0:c57706d25cf0 74 #define DS2482_STATUS_LL 0x08 //< DS2482 Status 1-Wire Logic Level
rs27 0:c57706d25cf0 75 #define DS2482_STATUS_RST 0x10 //< DS2482 Status Device Reset
rs27 0:c57706d25cf0 76 #define DS2482_STATUS_SBR 0x20 //< DS2482 Status Single Bit Result
rs27 0:c57706d25cf0 77 #define DS2482_STATUS_TSB 0x40 //< DS2482 Status Triplet Second Bit
rs27 0:c57706d25cf0 78 #define DS2482_STATUS_DIR 0x80 //< DS2482 Status Branch Direction Taken
rs27 0:c57706d25cf0 79
rs27 0:c57706d25cf0 80 // DS2482 configuration register bit defines
rs27 0:c57706d25cf0 81 #define DS2482_CFG_APU 0x01 //< DS2482 Config Active Pull-Up
rs27 0:c57706d25cf0 82 #define DS2482_CFG_PPM 0x02 //< DS2482 Config Presence Pulse Masking
rs27 0:c57706d25cf0 83 #define DS2482_CFG_SPU 0x04 //< DS2482 Config Strong Pull-Up
rs27 0:c57706d25cf0 84 #define DS2482_CFG_1WS 0x08 //< DS2482 Config 1-Wire Speed
rs27 0:c57706d25cf0 85
rs27 0:c57706d25cf0 86 // DS2482 channel selection code defines
rs27 0:c57706d25cf0 87 #define DS2482_CH_IO0 0xF0 //< DS2482 Select Channel IO0
rs27 0:c57706d25cf0 88 #define DS2482_CH_IO1 0xE1 //< DS2482 Select Channel IO1
rs27 0:c57706d25cf0 89 #define DS2482_CH_IO2 0xD2 //< DS2482 Select Channel IO2
rs27 0:c57706d25cf0 90 #define DS2482_CH_IO3 0xC3 //< DS2482 Select Channel IO3
rs27 0:c57706d25cf0 91 #define DS2482_CH_IO4 0xB4 //< DS2482 Select Channel IO4
rs27 0:c57706d25cf0 92 #define DS2482_CH_IO5 0xA5 //< DS2482 Select Channel IO5
rs27 0:c57706d25cf0 93 #define DS2482_CH_IO6 0x96 //< DS2482 Select Channel IO6
rs27 0:c57706d25cf0 94 #define DS2482_CH_IO7 0x87 //< DS2482 Select Channel IO7
rs27 0:c57706d25cf0 95
rs27 0:c57706d25cf0 96 // DS2482 read pointer code defines
rs27 0:c57706d25cf0 97 #define DS2482_READPTR_SR 0xF0 //< DS2482 Status Register
rs27 0:c57706d25cf0 98 #define DS2482_READPTR_RDR 0xE1 //< DS2482 Read Data Register
rs27 0:c57706d25cf0 99 #define DS2482_READPTR_CSR 0xD2 //< DS2482 Channel Selection Register
rs27 0:c57706d25cf0 100 #define DS2482_READPTR_CR 0xC3 //< DS2482 Configuration Register
rs27 0:c57706d25cf0 101
rs27 0:c57706d25cf0 102
rs27 0:c57706d25cf0 103 // API mode bit flags
rs27 0:c57706d25cf0 104 #define MODE_STANDARD 0x00
rs27 0:c57706d25cf0 105 #define MODE_OVERDRIVE 0x01
rs27 0:c57706d25cf0 106 #define MODE_STRONG 0x02
rs27 0:c57706d25cf0 107
rs27 0:c57706d25cf0 108 // One Wire
rs27 0:c57706d25cf0 109 #define OW_MATCH_ROM 0x55
rs27 0:c57706d25cf0 110 #define OW_SKIP_ROM 0xCC
rs27 0:c57706d25cf0 111 #define OW_CONVERT_TEMP 0x44
rs27 0:c57706d25cf0 112 #define OW_WR_SCRATCHPAD 0x4E
rs27 0:c57706d25cf0 113 #define OW_RD_SCRATCHPAD 0xBE
rs27 0:c57706d25cf0 114 #define OW_SEARCH_ROM 0xF0
rs27 0:c57706d25cf0 115
rs27 3:e773b0d83471 116 #define DS1820_LSB 0
rs27 3:e773b0d83471 117 #define DS1820_MSB 1
rs27 3:e773b0d83471 118
rs27 0:c57706d25cf0 119 // ============================================================================
rs27 0:c57706d25cf0 120
rs27 0:c57706d25cf0 121 class DS2482
rs27 0:c57706d25cf0 122 {
rs27 2:e9048135901b 123 public:
rs27 2:e9048135901b 124
rs27 2:e9048135901b 125 // ROM code structure
rs27 2:e9048135901b 126 typedef struct sOW_ROM_CODE_ITEM
rs27 2:e9048135901b 127 {
rs27 5:d94037eb31ed 128 uint8_t adr; // Adresse fuer den Baustein
rs27 5:d94037eb31ed 129 uint8_t status; // Status fuer den Wandler
rs27 5:d94037eb31ed 130 // bit 1 bis 4 0 = inaktiv
rs27 5:d94037eb31ed 131 // 1 = Baustein erkannt
rs27 5:d94037eb31ed 132 // 2 = wird als trigger verwendet
rs27 5:d94037eb31ed 133 // 3 = Messung duchgeführt
rs27 5:d94037eb31ed 134 // 4 = Übertagungsfehler
rs27 5:d94037eb31ed 135 // bit 8 ist fuerBuskennung
rs27 5:d94037eb31ed 136 int16_t result; // Ablage fuer Temperaturwert
rs27 5:d94037eb31ed 137 float value; // Ablage fuer Stromwert
rs27 5:d94037eb31ed 138 int16_t value_2; // Ablage fuer Spannungwert
rs27 2:e9048135901b 139 uint8_t rom[8]; // 8 Bytes for ROM code
rs27 2:e9048135901b 140 } tOW_ROM_CODE_ITEM;
rs27 2:e9048135901b 141
rs27 2:e9048135901b 142 typedef struct sOW
rs27 2:e9048135901b 143 {
rs27 2:e9048135901b 144 uint8_t devices; // Number of devices
rs27 2:e9048135901b 145 uint8_t device_table_index;
rs27 2:e9048135901b 146 tOW_ROM_CODE_ITEM device_table[OW_MAX_DEVICES]; // OW-Device data table
rs27 2:e9048135901b 147 } tOW;
rs27 0:c57706d25cf0 148
rs27 1:0950824b1ca3 149 // global vars
rs27 1:0950824b1ca3 150 tOW ow;
rs27 1:0950824b1ca3 151
rs27 0:c57706d25cf0 152 /** Create an instance of the PCF8574 connected to specfied I2C pins, with the specified address.
rs27 0:c57706d25cf0 153 *
rs27 0:c57706d25cf0 154 * @param sda The I2C data pin
rs27 0:c57706d25cf0 155 * @param scl The I2C clock pin
rs27 0:c57706d25cf0 156 * @param address The I2C address for this DS2482
rs27 0:c57706d25cf0 157 */
rs27 0:c57706d25cf0 158
rs27 0:c57706d25cf0 159 DS2482(PinName sda, PinName scl, int address);
rs27 0:c57706d25cf0 160
rs27 0:c57706d25cf0 161 //-----------------------------------------------------------------------------
rs27 0:c57706d25cf0 162 // functions
rs27 1:0950824b1ca3 163
rs27 1:0950824b1ca3 164 // crc buffer
rs27 1:0950824b1ca3 165 uint8_t crc_calc(uint8_t x);
rs27 1:0950824b1ca3 166 uint8_t crc_calc_buffer(uint8_t* pbuffer,uint8_t count);
rs27 0:c57706d25cf0 167
rs27 0:c57706d25cf0 168 uint8_t detect(void);
rs27 0:c57706d25cf0 169 int reset(void);
rs27 0:c57706d25cf0 170 uint8_t write_config(uint8_t config);
rs27 0:c57706d25cf0 171
rs27 0:c57706d25cf0 172 //uint8_t DS2482_channel_select(uint8_t channel);
rs27 0:c57706d25cf0 173 uint8_t OWReset(void);
rs27 0:c57706d25cf0 174 void OWWriteBit(uint8_t sendbit);
rs27 0:c57706d25cf0 175 uint8_t OWReadBit(void);
rs27 0:c57706d25cf0 176 uint8_t OWTouchBit(uint8_t sendbit);
rs27 0:c57706d25cf0 177 void OWWriteByte(uint8_t sendbyte);
rs27 0:c57706d25cf0 178 uint8_t OWReadByte(void);
rs27 0:c57706d25cf0 179 void OWBlock(uint8_t *tran_buf, uint8_t tran_len);
rs27 0:c57706d25cf0 180 uint8_t OWTouchByte(uint8_t sendbyte);
rs27 0:c57706d25cf0 181 uint8_t OWFirst(void);
rs27 0:c57706d25cf0 182 uint8_t OWNext(void);
rs27 0:c57706d25cf0 183 int OWVerify(void);
rs27 0:c57706d25cf0 184 void OWTargetSetup(uint8_t family_code);
rs27 0:c57706d25cf0 185 void OWFamilySkipSetup(void);
rs27 0:c57706d25cf0 186 uint8_t OWSearch(void);
rs27 0:c57706d25cf0 187 uint8_t search_triplet(uint8_t search_direction);
rs27 0:c57706d25cf0 188 uint8_t OWSpeed(uint8_t new_speed);
rs27 0:c57706d25cf0 189 uint8_t OWLevel(uint8_t new_level);
rs27 0:c57706d25cf0 190 uint8_t OWReadBitPower(uint8_t applyPowerResponse);
rs27 0:c57706d25cf0 191 uint8_t OWWriteBytePower(uint8_t sendbyte);
rs27 1:0950824b1ca3 192
rs27 0:c57706d25cf0 193 void DS18XX_Read_Address(void);
rs27 1:0950824b1ca3 194 void start_conversion(void);
rs27 2:e9048135901b 195
rs27 2:e9048135901b 196 bool ds1820_start_conversion(uint8_t command);
rs27 2:e9048135901b 197 bool ds18B20_read_hrtemp(void);
rs27 0:c57706d25cf0 198
rs27 0:c57706d25cf0 199 protected:
rs27 1:0950824b1ca3 200
rs27 1:0950824b1ca3 201 bool ow_read_rom(void);
rs27 1:0950824b1ca3 202 bool ow_read_scratchpad(void);
rs27 1:0950824b1ca3 203 bool ow_read_scratchpad_ds2438(uint8_t page);
rs27 1:0950824b1ca3 204 bool ow_write_scratchpad_ds18x20 (uint8_t th, uint8_t tl);
rs27 1:0950824b1ca3 205 bool ow_write_scratchpad_ds2438 (uint8_t th, uint8_t tl);
rs27 1:0950824b1ca3 206 bool ow_write_eeprom_ds18x20 (void);
rs27 1:0950824b1ca3 207 bool ow_write_eeprom_ds2438 (void);
rs27 0:c57706d25cf0 208 void ow_read_address (void);
rs27 0:c57706d25cf0 209 //-----------------------------------------------------------------------------
rs27 0:c57706d25cf0 210 // vars
rs27 0:c57706d25cf0 211
rs27 0:c57706d25cf0 212 I2C i2c;
rs27 0:c57706d25cf0 213 int addr;
rs27 0:c57706d25cf0 214 uint8_t crc_value;
rs27 0:c57706d25cf0 215
rs27 0:c57706d25cf0 216 // Search state
rs27 1:0950824b1ca3 217 // Variablen in einem Block ablegen
rs27 0:c57706d25cf0 218 uint8_t ow_scratchpad[OW_SCRATCHPAD_BYTES]; // Scratchpad memory
rs27 0:c57706d25cf0 219 uint8_t ow_rom_code[OW_ROM_CODE_BYTES]; // Temporary ROM code
rs27 0:c57706d25cf0 220 uint8_t ow_flags;
rs27 0:c57706d25cf0 221 uint8_t ROM_NO[8]; // temporary ROM Code
rs27 0:c57706d25cf0 222 uint8_t LastDiscrepancy;
rs27 0:c57706d25cf0 223 uint8_t LastFamilyDiscrepancy;
rs27 0:c57706d25cf0 224 uint8_t LastDeviceFlag;
rs27 0:c57706d25cf0 225
rs27 0:c57706d25cf0 226 // DS2482 state
rs27 0:c57706d25cf0 227 uint8_t c1WS, cSPU, cPPM, cAPU;
rs27 0:c57706d25cf0 228 uint8_t short_detected;
rs27 0:c57706d25cf0 229
rs27 4:c29e67d55f86 230 bool ds1820_request_pending;
rs27 1:0950824b1ca3 231
rs27 0:c57706d25cf0 232 }; // end class
rs27 0:c57706d25cf0 233
rs27 0:c57706d25cf0 234 #endif