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Dependencies:   mbed mbed-rtos PinDetect

PowerControl/EthernetPowerControl.h@0:0ca943ce4014, 2020-04-27 (annotated)

Committer:
rpavoor3
Date:
Mon Apr 27 23:18:38 2020 +0000
Revision:
0:0ca943ce4014
4180 Your Fitness Buddy

Who changed what in which revision?

UserRevisionLine numberNew contents of line
rpavoor3 0:0ca943ce4014 1 /* mbed PowerControl Library
rpavoor3 0:0ca943ce4014 2 * Copyright (c) 2010 Michael Wei
rpavoor3 0:0ca943ce4014 3 */
rpavoor3 0:0ca943ce4014 4
rpavoor3 0:0ca943ce4014 5 #ifndef MBED_POWERCONTROL_ETH_H
rpavoor3 0:0ca943ce4014 6 #define MBED_POWERCONTROL_ETH_H
rpavoor3 0:0ca943ce4014 7
rpavoor3 0:0ca943ce4014 8 #include "mbed.h"
rpavoor3 0:0ca943ce4014 9 #include "PowerControl.h"
rpavoor3 0:0ca943ce4014 10
rpavoor3 0:0ca943ce4014 11 #define PHY_REG_BMCR_POWERDOWN 0xB
rpavoor3 0:0ca943ce4014 12 #define PHY_REG_EDCR_ENABLE 0xF
rpavoor3 0:0ca943ce4014 13
rpavoor3 0:0ca943ce4014 14
rpavoor3 0:0ca943ce4014 15 void EMAC_Init();
rpavoor3 0:0ca943ce4014 16 static unsigned short read_PHY (unsigned int PhyReg);
rpavoor3 0:0ca943ce4014 17 static void write_PHY (unsigned int PhyReg, unsigned short Value);
rpavoor3 0:0ca943ce4014 18
rpavoor3 0:0ca943ce4014 19 void PHY_PowerDown(void);
rpavoor3 0:0ca943ce4014 20 void PHY_PowerUp(void);
rpavoor3 0:0ca943ce4014 21 void PHY_EnergyDetect_Enable(void);
rpavoor3 0:0ca943ce4014 22 void PHY_EnergyDetect_Disable(void);
rpavoor3 0:0ca943ce4014 23
rpavoor3 0:0ca943ce4014 24 //From NXP Sample Code .... Probably from KEIL sample code
rpavoor3 0:0ca943ce4014 25 /* EMAC Memory Buffer configuration for 16K Ethernet RAM. */
rpavoor3 0:0ca943ce4014 26 #define NUM_RX_FRAG 4 /* Num.of RX Fragments 4*1536= 6.0kB */
rpavoor3 0:0ca943ce4014 27 #define NUM_TX_FRAG 3 /* Num.of TX Fragments 3*1536= 4.6kB */
rpavoor3 0:0ca943ce4014 28 #define ETH_FRAG_SIZE 1536 /* Packet Fragment size 1536 Bytes */
rpavoor3 0:0ca943ce4014 29
rpavoor3 0:0ca943ce4014 30 #define ETH_MAX_FLEN 1536 /* Max. Ethernet Frame Size */
rpavoor3 0:0ca943ce4014 31
rpavoor3 0:0ca943ce4014 32 /* EMAC variables located in 16K Ethernet SRAM */
rpavoor3 0:0ca943ce4014 33 #define RX_DESC_BASE 0x20080000
rpavoor3 0:0ca943ce4014 34 #define RX_STAT_BASE (RX_DESC_BASE + NUM_RX_FRAG*8)
rpavoor3 0:0ca943ce4014 35 #define TX_DESC_BASE (RX_STAT_BASE + NUM_RX_FRAG*8)
rpavoor3 0:0ca943ce4014 36 #define TX_STAT_BASE (TX_DESC_BASE + NUM_TX_FRAG*8)
rpavoor3 0:0ca943ce4014 37 #define RX_BUF_BASE (TX_STAT_BASE + NUM_TX_FRAG*4)
rpavoor3 0:0ca943ce4014 38 #define TX_BUF_BASE (RX_BUF_BASE + NUM_RX_FRAG*ETH_FRAG_SIZE)
rpavoor3 0:0ca943ce4014 39
rpavoor3 0:0ca943ce4014 40 /* RX and TX descriptor and status definitions. */
rpavoor3 0:0ca943ce4014 41 #define RX_DESC_PACKET(i) (*(unsigned int *)(RX_DESC_BASE + 8*i))
rpavoor3 0:0ca943ce4014 42 #define RX_DESC_CTRL(i) (*(unsigned int *)(RX_DESC_BASE+4 + 8*i))
rpavoor3 0:0ca943ce4014 43 #define RX_STAT_INFO(i) (*(unsigned int *)(RX_STAT_BASE + 8*i))
rpavoor3 0:0ca943ce4014 44 #define RX_STAT_HASHCRC(i) (*(unsigned int *)(RX_STAT_BASE+4 + 8*i))
rpavoor3 0:0ca943ce4014 45 #define TX_DESC_PACKET(i) (*(unsigned int *)(TX_DESC_BASE + 8*i))
rpavoor3 0:0ca943ce4014 46 #define TX_DESC_CTRL(i) (*(unsigned int *)(TX_DESC_BASE+4 + 8*i))
rpavoor3 0:0ca943ce4014 47 #define TX_STAT_INFO(i) (*(unsigned int *)(TX_STAT_BASE + 4*i))
rpavoor3 0:0ca943ce4014 48 #define RX_BUF(i) (RX_BUF_BASE + ETH_FRAG_SIZE*i)
rpavoor3 0:0ca943ce4014 49 #define TX_BUF(i) (TX_BUF_BASE + ETH_FRAG_SIZE*i)
rpavoor3 0:0ca943ce4014 50
rpavoor3 0:0ca943ce4014 51 /* MAC Configuration Register 1 */
rpavoor3 0:0ca943ce4014 52 #define MAC1_REC_EN 0x00000001 /* Receive Enable */
rpavoor3 0:0ca943ce4014 53 #define MAC1_PASS_ALL 0x00000002 /* Pass All Receive Frames */
rpavoor3 0:0ca943ce4014 54 #define MAC1_RX_FLOWC 0x00000004 /* RX Flow Control */
rpavoor3 0:0ca943ce4014 55 #define MAC1_TX_FLOWC 0x00000008 /* TX Flow Control */
rpavoor3 0:0ca943ce4014 56 #define MAC1_LOOPB 0x00000010 /* Loop Back Mode */
rpavoor3 0:0ca943ce4014 57 #define MAC1_RES_TX 0x00000100 /* Reset TX Logic */
rpavoor3 0:0ca943ce4014 58 #define MAC1_RES_MCS_TX 0x00000200 /* Reset MAC TX Control Sublayer */
rpavoor3 0:0ca943ce4014 59 #define MAC1_RES_RX 0x00000400 /* Reset RX Logic */
rpavoor3 0:0ca943ce4014 60 #define MAC1_RES_MCS_RX 0x00000800 /* Reset MAC RX Control Sublayer */
rpavoor3 0:0ca943ce4014 61 #define MAC1_SIM_RES 0x00004000 /* Simulation Reset */
rpavoor3 0:0ca943ce4014 62 #define MAC1_SOFT_RES 0x00008000 /* Soft Reset MAC */
rpavoor3 0:0ca943ce4014 63
rpavoor3 0:0ca943ce4014 64 /* MAC Configuration Register 2 */
rpavoor3 0:0ca943ce4014 65 #define MAC2_FULL_DUP 0x00000001 /* Full Duplex Mode */
rpavoor3 0:0ca943ce4014 66 #define MAC2_FRM_LEN_CHK 0x00000002 /* Frame Length Checking */
rpavoor3 0:0ca943ce4014 67 #define MAC2_HUGE_FRM_EN 0x00000004 /* Huge Frame Enable */
rpavoor3 0:0ca943ce4014 68 #define MAC2_DLY_CRC 0x00000008 /* Delayed CRC Mode */
rpavoor3 0:0ca943ce4014 69 #define MAC2_CRC_EN 0x00000010 /* Append CRC to every Frame */
rpavoor3 0:0ca943ce4014 70 #define MAC2_PAD_EN 0x00000020 /* Pad all Short Frames */
rpavoor3 0:0ca943ce4014 71 #define MAC2_VLAN_PAD_EN 0x00000040 /* VLAN Pad Enable */
rpavoor3 0:0ca943ce4014 72 #define MAC2_ADET_PAD_EN 0x00000080 /* Auto Detect Pad Enable */
rpavoor3 0:0ca943ce4014 73 #define MAC2_PPREAM_ENF 0x00000100 /* Pure Preamble Enforcement */
rpavoor3 0:0ca943ce4014 74 #define MAC2_LPREAM_ENF 0x00000200 /* Long Preamble Enforcement */
rpavoor3 0:0ca943ce4014 75 #define MAC2_NO_BACKOFF 0x00001000 /* No Backoff Algorithm */
rpavoor3 0:0ca943ce4014 76 #define MAC2_BACK_PRESSURE 0x00002000 /* Backoff Presurre / No Backoff */
rpavoor3 0:0ca943ce4014 77 #define MAC2_EXCESS_DEF 0x00004000 /* Excess Defer */
rpavoor3 0:0ca943ce4014 78
rpavoor3 0:0ca943ce4014 79 /* Back-to-Back Inter-Packet-Gap Register */
rpavoor3 0:0ca943ce4014 80 #define IPGT_FULL_DUP 0x00000015 /* Recommended value for Full Duplex */
rpavoor3 0:0ca943ce4014 81 #define IPGT_HALF_DUP 0x00000012 /* Recommended value for Half Duplex */
rpavoor3 0:0ca943ce4014 82
rpavoor3 0:0ca943ce4014 83 /* Non Back-to-Back Inter-Packet-Gap Register */
rpavoor3 0:0ca943ce4014 84 #define IPGR_DEF 0x00000012 /* Recommended value */
rpavoor3 0:0ca943ce4014 85
rpavoor3 0:0ca943ce4014 86 /* Collision Window/Retry Register */
rpavoor3 0:0ca943ce4014 87 #define CLRT_DEF 0x0000370F /* Default value */
rpavoor3 0:0ca943ce4014 88
rpavoor3 0:0ca943ce4014 89 /* PHY Support Register */
rpavoor3 0:0ca943ce4014 90 #define SUPP_SPEED 0x00000100 /* Reduced MII Logic Current Speed */
rpavoor3 0:0ca943ce4014 91 #define SUPP_RES_RMII 0x00000800 /* Reset Reduced MII Logic */
rpavoor3 0:0ca943ce4014 92
rpavoor3 0:0ca943ce4014 93 /* Test Register */
rpavoor3 0:0ca943ce4014 94 #define TEST_SHCUT_PQUANTA 0x00000001 /* Shortcut Pause Quanta */
rpavoor3 0:0ca943ce4014 95 #define TEST_TST_PAUSE 0x00000002 /* Test Pause */
rpavoor3 0:0ca943ce4014 96 #define TEST_TST_BACKP 0x00000004 /* Test Back Pressure */
rpavoor3 0:0ca943ce4014 97
rpavoor3 0:0ca943ce4014 98 /* MII Management Configuration Register */
rpavoor3 0:0ca943ce4014 99 #define MCFG_SCAN_INC 0x00000001 /* Scan Increment PHY Address */
rpavoor3 0:0ca943ce4014 100 #define MCFG_SUPP_PREAM 0x00000002 /* Suppress Preamble */
rpavoor3 0:0ca943ce4014 101 #define MCFG_CLK_SEL 0x0000001C /* Clock Select Mask */
rpavoor3 0:0ca943ce4014 102 #define MCFG_RES_MII 0x00008000 /* Reset MII Management Hardware */
rpavoor3 0:0ca943ce4014 103
rpavoor3 0:0ca943ce4014 104 /* MII Management Command Register */
rpavoor3 0:0ca943ce4014 105 #define MCMD_READ 0x00000001 /* MII Read */
rpavoor3 0:0ca943ce4014 106 #define MCMD_SCAN 0x00000002 /* MII Scan continuously */
rpavoor3 0:0ca943ce4014 107
rpavoor3 0:0ca943ce4014 108 #define MII_WR_TOUT 0x00050000 /* MII Write timeout count */
rpavoor3 0:0ca943ce4014 109 #define MII_RD_TOUT 0x00050000 /* MII Read timeout count */
rpavoor3 0:0ca943ce4014 110
rpavoor3 0:0ca943ce4014 111 /* MII Management Address Register */
rpavoor3 0:0ca943ce4014 112 #define MADR_REG_ADR 0x0000001F /* MII Register Address Mask */
rpavoor3 0:0ca943ce4014 113 #define MADR_PHY_ADR 0x00001F00 /* PHY Address Mask */
rpavoor3 0:0ca943ce4014 114
rpavoor3 0:0ca943ce4014 115 /* MII Management Indicators Register */
rpavoor3 0:0ca943ce4014 116 #define MIND_BUSY 0x00000001 /* MII is Busy */
rpavoor3 0:0ca943ce4014 117 #define MIND_SCAN 0x00000002 /* MII Scanning in Progress */
rpavoor3 0:0ca943ce4014 118 #define MIND_NOT_VAL 0x00000004 /* MII Read Data not valid */
rpavoor3 0:0ca943ce4014 119 #define MIND_MII_LINK_FAIL 0x00000008 /* MII Link Failed */
rpavoor3 0:0ca943ce4014 120
rpavoor3 0:0ca943ce4014 121 /* Command Register */
rpavoor3 0:0ca943ce4014 122 #define CR_RX_EN 0x00000001 /* Enable Receive */
rpavoor3 0:0ca943ce4014 123 #define CR_TX_EN 0x00000002 /* Enable Transmit */
rpavoor3 0:0ca943ce4014 124 #define CR_REG_RES 0x00000008 /* Reset Host Registers */
rpavoor3 0:0ca943ce4014 125 #define CR_TX_RES 0x00000010 /* Reset Transmit Datapath */
rpavoor3 0:0ca943ce4014 126 #define CR_RX_RES 0x00000020 /* Reset Receive Datapath */
rpavoor3 0:0ca943ce4014 127 #define CR_PASS_RUNT_FRM 0x00000040 /* Pass Runt Frames */
rpavoor3 0:0ca943ce4014 128 #define CR_PASS_RX_FILT 0x00000080 /* Pass RX Filter */
rpavoor3 0:0ca943ce4014 129 #define CR_TX_FLOW_CTRL 0x00000100 /* TX Flow Control */
rpavoor3 0:0ca943ce4014 130 #define CR_RMII 0x00000200 /* Reduced MII Interface */
rpavoor3 0:0ca943ce4014 131 #define CR_FULL_DUP 0x00000400 /* Full Duplex */
rpavoor3 0:0ca943ce4014 132
rpavoor3 0:0ca943ce4014 133 /* Status Register */
rpavoor3 0:0ca943ce4014 134 #define SR_RX_EN 0x00000001 /* Enable Receive */
rpavoor3 0:0ca943ce4014 135 #define SR_TX_EN 0x00000002 /* Enable Transmit */
rpavoor3 0:0ca943ce4014 136
rpavoor3 0:0ca943ce4014 137 /* Transmit Status Vector 0 Register */
rpavoor3 0:0ca943ce4014 138 #define TSV0_CRC_ERR 0x00000001 /* CRC error */
rpavoor3 0:0ca943ce4014 139 #define TSV0_LEN_CHKERR 0x00000002 /* Length Check Error */
rpavoor3 0:0ca943ce4014 140 #define TSV0_LEN_OUTRNG 0x00000004 /* Length Out of Range */
rpavoor3 0:0ca943ce4014 141 #define TSV0_DONE 0x00000008 /* Tramsmission Completed */
rpavoor3 0:0ca943ce4014 142 #define TSV0_MCAST 0x00000010 /* Multicast Destination */
rpavoor3 0:0ca943ce4014 143 #define TSV0_BCAST 0x00000020 /* Broadcast Destination */
rpavoor3 0:0ca943ce4014 144 #define TSV0_PKT_DEFER 0x00000040 /* Packet Deferred */
rpavoor3 0:0ca943ce4014 145 #define TSV0_EXC_DEFER 0x00000080 /* Excessive Packet Deferral */
rpavoor3 0:0ca943ce4014 146 #define TSV0_EXC_COLL 0x00000100 /* Excessive Collision */
rpavoor3 0:0ca943ce4014 147 #define TSV0_LATE_COLL 0x00000200 /* Late Collision Occured */
rpavoor3 0:0ca943ce4014 148 #define TSV0_GIANT 0x00000400 /* Giant Frame */
rpavoor3 0:0ca943ce4014 149 #define TSV0_UNDERRUN 0x00000800 /* Buffer Underrun */
rpavoor3 0:0ca943ce4014 150 #define TSV0_BYTES 0x0FFFF000 /* Total Bytes Transferred */
rpavoor3 0:0ca943ce4014 151 #define TSV0_CTRL_FRAME 0x10000000 /* Control Frame */
rpavoor3 0:0ca943ce4014 152 #define TSV0_PAUSE 0x20000000 /* Pause Frame */
rpavoor3 0:0ca943ce4014 153 #define TSV0_BACK_PRESS 0x40000000 /* Backpressure Method Applied */
rpavoor3 0:0ca943ce4014 154 #define TSV0_VLAN 0x80000000 /* VLAN Frame */
rpavoor3 0:0ca943ce4014 155
rpavoor3 0:0ca943ce4014 156 /* Transmit Status Vector 1 Register */
rpavoor3 0:0ca943ce4014 157 #define TSV1_BYTE_CNT 0x0000FFFF /* Transmit Byte Count */
rpavoor3 0:0ca943ce4014 158 #define TSV1_COLL_CNT 0x000F0000 /* Transmit Collision Count */
rpavoor3 0:0ca943ce4014 159
rpavoor3 0:0ca943ce4014 160 /* Receive Status Vector Register */
rpavoor3 0:0ca943ce4014 161 #define RSV_BYTE_CNT 0x0000FFFF /* Receive Byte Count */
rpavoor3 0:0ca943ce4014 162 #define RSV_PKT_IGNORED 0x00010000 /* Packet Previously Ignored */
rpavoor3 0:0ca943ce4014 163 #define RSV_RXDV_SEEN 0x00020000 /* RXDV Event Previously Seen */
rpavoor3 0:0ca943ce4014 164 #define RSV_CARR_SEEN 0x00040000 /* Carrier Event Previously Seen */
rpavoor3 0:0ca943ce4014 165 #define RSV_REC_CODEV 0x00080000 /* Receive Code Violation */
rpavoor3 0:0ca943ce4014 166 #define RSV_CRC_ERR 0x00100000 /* CRC Error */
rpavoor3 0:0ca943ce4014 167 #define RSV_LEN_CHKERR 0x00200000 /* Length Check Error */
rpavoor3 0:0ca943ce4014 168 #define RSV_LEN_OUTRNG 0x00400000 /* Length Out of Range */
rpavoor3 0:0ca943ce4014 169 #define RSV_REC_OK 0x00800000 /* Frame Received OK */
rpavoor3 0:0ca943ce4014 170 #define RSV_MCAST 0x01000000 /* Multicast Frame */
rpavoor3 0:0ca943ce4014 171 #define RSV_BCAST 0x02000000 /* Broadcast Frame */
rpavoor3 0:0ca943ce4014 172 #define RSV_DRIB_NIBB 0x04000000 /* Dribble Nibble */
rpavoor3 0:0ca943ce4014 173 #define RSV_CTRL_FRAME 0x08000000 /* Control Frame */
rpavoor3 0:0ca943ce4014 174 #define RSV_PAUSE 0x10000000 /* Pause Frame */
rpavoor3 0:0ca943ce4014 175 #define RSV_UNSUPP_OPC 0x20000000 /* Unsupported Opcode */
rpavoor3 0:0ca943ce4014 176 #define RSV_VLAN 0x40000000 /* VLAN Frame */
rpavoor3 0:0ca943ce4014 177
rpavoor3 0:0ca943ce4014 178 /* Flow Control Counter Register */
rpavoor3 0:0ca943ce4014 179 #define FCC_MIRR_CNT 0x0000FFFF /* Mirror Counter */
rpavoor3 0:0ca943ce4014 180 #define FCC_PAUSE_TIM 0xFFFF0000 /* Pause Timer */
rpavoor3 0:0ca943ce4014 181
rpavoor3 0:0ca943ce4014 182 /* Flow Control Status Register */
rpavoor3 0:0ca943ce4014 183 #define FCS_MIRR_CNT 0x0000FFFF /* Mirror Counter Current */
rpavoor3 0:0ca943ce4014 184
rpavoor3 0:0ca943ce4014 185 /* Receive Filter Control Register */
rpavoor3 0:0ca943ce4014 186 #define RFC_UCAST_EN 0x00000001 /* Accept Unicast Frames Enable */
rpavoor3 0:0ca943ce4014 187 #define RFC_BCAST_EN 0x00000002 /* Accept Broadcast Frames Enable */
rpavoor3 0:0ca943ce4014 188 #define RFC_MCAST_EN 0x00000004 /* Accept Multicast Frames Enable */
rpavoor3 0:0ca943ce4014 189 #define RFC_UCAST_HASH_EN 0x00000008 /* Accept Unicast Hash Filter Frames */
rpavoor3 0:0ca943ce4014 190 #define RFC_MCAST_HASH_EN 0x00000010 /* Accept Multicast Hash Filter Fram.*/
rpavoor3 0:0ca943ce4014 191 #define RFC_PERFECT_EN 0x00000020 /* Accept Perfect Match Enable */
rpavoor3 0:0ca943ce4014 192 #define RFC_MAGP_WOL_EN 0x00001000 /* Magic Packet Filter WoL Enable */
rpavoor3 0:0ca943ce4014 193 #define RFC_PFILT_WOL_EN 0x00002000 /* Perfect Filter WoL Enable */
rpavoor3 0:0ca943ce4014 194
rpavoor3 0:0ca943ce4014 195 /* Receive Filter WoL Status/Clear Registers */
rpavoor3 0:0ca943ce4014 196 #define WOL_UCAST 0x00000001 /* Unicast Frame caused WoL */
rpavoor3 0:0ca943ce4014 197 #define WOL_BCAST 0x00000002 /* Broadcast Frame caused WoL */
rpavoor3 0:0ca943ce4014 198 #define WOL_MCAST 0x00000004 /* Multicast Frame caused WoL */
rpavoor3 0:0ca943ce4014 199 #define WOL_UCAST_HASH 0x00000008 /* Unicast Hash Filter Frame WoL */
rpavoor3 0:0ca943ce4014 200 #define WOL_MCAST_HASH 0x00000010 /* Multicast Hash Filter Frame WoL */
rpavoor3 0:0ca943ce4014 201 #define WOL_PERFECT 0x00000020 /* Perfect Filter WoL */
rpavoor3 0:0ca943ce4014 202 #define WOL_RX_FILTER 0x00000080 /* RX Filter caused WoL */
rpavoor3 0:0ca943ce4014 203 #define WOL_MAG_PACKET 0x00000100 /* Magic Packet Filter caused WoL */
rpavoor3 0:0ca943ce4014 204
rpavoor3 0:0ca943ce4014 205 /* Interrupt Status/Enable/Clear/Set Registers */
rpavoor3 0:0ca943ce4014 206 #define INT_RX_OVERRUN 0x00000001 /* Overrun Error in RX Queue */
rpavoor3 0:0ca943ce4014 207 #define INT_RX_ERR 0x00000002 /* Receive Error */
rpavoor3 0:0ca943ce4014 208 #define INT_RX_FIN 0x00000004 /* RX Finished Process Descriptors */
rpavoor3 0:0ca943ce4014 209 #define INT_RX_DONE 0x00000008 /* Receive Done */
rpavoor3 0:0ca943ce4014 210 #define INT_TX_UNDERRUN 0x00000010 /* Transmit Underrun */
rpavoor3 0:0ca943ce4014 211 #define INT_TX_ERR 0x00000020 /* Transmit Error */
rpavoor3 0:0ca943ce4014 212 #define INT_TX_FIN 0x00000040 /* TX Finished Process Descriptors */
rpavoor3 0:0ca943ce4014 213 #define INT_TX_DONE 0x00000080 /* Transmit Done */
rpavoor3 0:0ca943ce4014 214 #define INT_SOFT_INT 0x00001000 /* Software Triggered Interrupt */
rpavoor3 0:0ca943ce4014 215 #define INT_WAKEUP 0x00002000 /* Wakeup Event Interrupt */
rpavoor3 0:0ca943ce4014 216
rpavoor3 0:0ca943ce4014 217 /* Power Down Register */
rpavoor3 0:0ca943ce4014 218 #define PD_POWER_DOWN 0x80000000 /* Power Down MAC */
rpavoor3 0:0ca943ce4014 219
rpavoor3 0:0ca943ce4014 220 /* RX Descriptor Control Word */
rpavoor3 0:0ca943ce4014 221 #define RCTRL_SIZE 0x000007FF /* Buffer size mask */
rpavoor3 0:0ca943ce4014 222 #define RCTRL_INT 0x80000000 /* Generate RxDone Interrupt */
rpavoor3 0:0ca943ce4014 223
rpavoor3 0:0ca943ce4014 224 /* RX Status Hash CRC Word */
rpavoor3 0:0ca943ce4014 225 #define RHASH_SA 0x000001FF /* Hash CRC for Source Address */
rpavoor3 0:0ca943ce4014 226 #define RHASH_DA 0x001FF000 /* Hash CRC for Destination Address */
rpavoor3 0:0ca943ce4014 227
rpavoor3 0:0ca943ce4014 228 /* RX Status Information Word */
rpavoor3 0:0ca943ce4014 229 #define RINFO_SIZE 0x000007FF /* Data size in bytes */
rpavoor3 0:0ca943ce4014 230 #define RINFO_CTRL_FRAME 0x00040000 /* Control Frame */
rpavoor3 0:0ca943ce4014 231 #define RINFO_VLAN 0x00080000 /* VLAN Frame */
rpavoor3 0:0ca943ce4014 232 #define RINFO_FAIL_FILT 0x00100000 /* RX Filter Failed */
rpavoor3 0:0ca943ce4014 233 #define RINFO_MCAST 0x00200000 /* Multicast Frame */
rpavoor3 0:0ca943ce4014 234 #define RINFO_BCAST 0x00400000 /* Broadcast Frame */
rpavoor3 0:0ca943ce4014 235 #define RINFO_CRC_ERR 0x00800000 /* CRC Error in Frame */
rpavoor3 0:0ca943ce4014 236 #define RINFO_SYM_ERR 0x01000000 /* Symbol Error from PHY */
rpavoor3 0:0ca943ce4014 237 #define RINFO_LEN_ERR 0x02000000 /* Length Error */
rpavoor3 0:0ca943ce4014 238 #define RINFO_RANGE_ERR 0x04000000 /* Range Error (exceeded max. size) */
rpavoor3 0:0ca943ce4014 239 #define RINFO_ALIGN_ERR 0x08000000 /* Alignment Error */
rpavoor3 0:0ca943ce4014 240 #define RINFO_OVERRUN 0x10000000 /* Receive overrun */
rpavoor3 0:0ca943ce4014 241 #define RINFO_NO_DESCR 0x20000000 /* No new Descriptor available */
rpavoor3 0:0ca943ce4014 242 #define RINFO_LAST_FLAG 0x40000000 /* Last Fragment in Frame */
rpavoor3 0:0ca943ce4014 243 #define RINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */
rpavoor3 0:0ca943ce4014 244
rpavoor3 0:0ca943ce4014 245 #define RINFO_ERR_MASK (RINFO_FAIL_FILT | RINFO_CRC_ERR | RINFO_SYM_ERR | \
rpavoor3 0:0ca943ce4014 246 RINFO_LEN_ERR | RINFO_ALIGN_ERR | RINFO_OVERRUN)
rpavoor3 0:0ca943ce4014 247
rpavoor3 0:0ca943ce4014 248 /* TX Descriptor Control Word */
rpavoor3 0:0ca943ce4014 249 #define TCTRL_SIZE 0x000007FF /* Size of data buffer in bytes */
rpavoor3 0:0ca943ce4014 250 #define TCTRL_OVERRIDE 0x04000000 /* Override Default MAC Registers */
rpavoor3 0:0ca943ce4014 251 #define TCTRL_HUGE 0x08000000 /* Enable Huge Frame */
rpavoor3 0:0ca943ce4014 252 #define TCTRL_PAD 0x10000000 /* Pad short Frames to 64 bytes */
rpavoor3 0:0ca943ce4014 253 #define TCTRL_CRC 0x20000000 /* Append a hardware CRC to Frame */
rpavoor3 0:0ca943ce4014 254 #define TCTRL_LAST 0x40000000 /* Last Descriptor for TX Frame */
rpavoor3 0:0ca943ce4014 255 #define TCTRL_INT 0x80000000 /* Generate TxDone Interrupt */
rpavoor3 0:0ca943ce4014 256
rpavoor3 0:0ca943ce4014 257 /* TX Status Information Word */
rpavoor3 0:0ca943ce4014 258 #define TINFO_COL_CNT 0x01E00000 /* Collision Count */
rpavoor3 0:0ca943ce4014 259 #define TINFO_DEFER 0x02000000 /* Packet Deferred (not an error) */
rpavoor3 0:0ca943ce4014 260 #define TINFO_EXCESS_DEF 0x04000000 /* Excessive Deferral */
rpavoor3 0:0ca943ce4014 261 #define TINFO_EXCESS_COL 0x08000000 /* Excessive Collision */
rpavoor3 0:0ca943ce4014 262 #define TINFO_LATE_COL 0x10000000 /* Late Collision Occured */
rpavoor3 0:0ca943ce4014 263 #define TINFO_UNDERRUN 0x20000000 /* Transmit Underrun */
rpavoor3 0:0ca943ce4014 264 #define TINFO_NO_DESCR 0x40000000 /* No new Descriptor available */
rpavoor3 0:0ca943ce4014 265 #define TINFO_ERR 0x80000000 /* Error Occured (OR of all errors) */
rpavoor3 0:0ca943ce4014 266
rpavoor3 0:0ca943ce4014 267 /* DP83848C PHY Registers */
rpavoor3 0:0ca943ce4014 268 #define PHY_REG_BMCR 0x00 /* Basic Mode Control Register */
rpavoor3 0:0ca943ce4014 269 #define PHY_REG_BMSR 0x01 /* Basic Mode Status Register */
rpavoor3 0:0ca943ce4014 270 #define PHY_REG_IDR1 0x02 /* PHY Identifier 1 */
rpavoor3 0:0ca943ce4014 271 #define PHY_REG_IDR2 0x03 /* PHY Identifier 2 */
rpavoor3 0:0ca943ce4014 272 #define PHY_REG_ANAR 0x04 /* Auto-Negotiation Advertisement */
rpavoor3 0:0ca943ce4014 273 #define PHY_REG_ANLPAR 0x05 /* Auto-Neg. Link Partner Abitily */
rpavoor3 0:0ca943ce4014 274 #define PHY_REG_ANER 0x06 /* Auto-Neg. Expansion Register */
rpavoor3 0:0ca943ce4014 275 #define PHY_REG_ANNPTR 0x07 /* Auto-Neg. Next Page TX */
rpavoor3 0:0ca943ce4014 276
rpavoor3 0:0ca943ce4014 277 /* PHY Extended Registers */
rpavoor3 0:0ca943ce4014 278 #define PHY_REG_STS 0x10 /* Status Register */
rpavoor3 0:0ca943ce4014 279 #define PHY_REG_MICR 0x11 /* MII Interrupt Control Register */
rpavoor3 0:0ca943ce4014 280 #define PHY_REG_MISR 0x12 /* MII Interrupt Status Register */
rpavoor3 0:0ca943ce4014 281 #define PHY_REG_FCSCR 0x14 /* False Carrier Sense Counter */
rpavoor3 0:0ca943ce4014 282 #define PHY_REG_RECR 0x15 /* Receive Error Counter */
rpavoor3 0:0ca943ce4014 283 #define PHY_REG_PCSR 0x16 /* PCS Sublayer Config. and Status */
rpavoor3 0:0ca943ce4014 284 #define PHY_REG_RBR 0x17 /* RMII and Bypass Register */
rpavoor3 0:0ca943ce4014 285 #define PHY_REG_LEDCR 0x18 /* LED Direct Control Register */
rpavoor3 0:0ca943ce4014 286 #define PHY_REG_PHYCR 0x19 /* PHY Control Register */
rpavoor3 0:0ca943ce4014 287 #define PHY_REG_10BTSCR 0x1A /* 10Base-T Status/Control Register */
rpavoor3 0:0ca943ce4014 288 #define PHY_REG_CDCTRL1 0x1B /* CD Test Control and BIST Extens. */
rpavoor3 0:0ca943ce4014 289 #define PHY_REG_EDCR 0x1D /* Energy Detect Control Register */
rpavoor3 0:0ca943ce4014 290
rpavoor3 0:0ca943ce4014 291 #define PHY_FULLD_100M 0x2100 /* Full Duplex 100Mbit */
rpavoor3 0:0ca943ce4014 292 #define PHY_HALFD_100M 0x2000 /* Half Duplex 100Mbit */
rpavoor3 0:0ca943ce4014 293 #define PHY_FULLD_10M 0x0100 /* Full Duplex 10Mbit */
rpavoor3 0:0ca943ce4014 294 #define PHY_HALFD_10M 0x0000 /* Half Duplex 10MBit */
rpavoor3 0:0ca943ce4014 295 #define PHY_AUTO_NEG 0x3000 /* Select Auto Negotiation */
rpavoor3 0:0ca943ce4014 296
rpavoor3 0:0ca943ce4014 297 #define DP83848C_DEF_ADR 0x0100 /* Default PHY device address */
rpavoor3 0:0ca943ce4014 298 #define DP83848C_ID 0x20005C90 /* PHY Identifier */
rpavoor3 0:0ca943ce4014 299 #endif