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Dependencies:   mbed mbed-rtos PinDetect

PowerControl/EthernetPowerControl.cpp@0:0ca943ce4014, 2020-04-27 (annotated)

Committer:
rpavoor3
Date:
Mon Apr 27 23:18:38 2020 +0000
Revision:
0:0ca943ce4014
4180 Your Fitness Buddy

Who changed what in which revision?

UserRevisionLine numberNew contents of line
rpavoor3 0:0ca943ce4014 1 #include "EthernetPowerControl.h"
rpavoor3 0:0ca943ce4014 2
rpavoor3 0:0ca943ce4014 3 static void write_PHY (unsigned int PhyReg, unsigned short Value) {
rpavoor3 0:0ca943ce4014 4 /* Write a data 'Value' to PHY register 'PhyReg'. */
rpavoor3 0:0ca943ce4014 5 unsigned int tout;
rpavoor3 0:0ca943ce4014 6 /* Hardware MII Management for LPC176x devices. */
rpavoor3 0:0ca943ce4014 7 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
rpavoor3 0:0ca943ce4014 8 LPC_EMAC->MWTD = Value;
rpavoor3 0:0ca943ce4014 9
rpavoor3 0:0ca943ce4014 10 /* Wait utill operation completed */
rpavoor3 0:0ca943ce4014 11 for (tout = 0; tout < MII_WR_TOUT; tout++) {
rpavoor3 0:0ca943ce4014 12 if ((LPC_EMAC->MIND & MIND_BUSY) == 0) {
rpavoor3 0:0ca943ce4014 13 break;
rpavoor3 0:0ca943ce4014 14 }
rpavoor3 0:0ca943ce4014 15 }
rpavoor3 0:0ca943ce4014 16 }
rpavoor3 0:0ca943ce4014 17
rpavoor3 0:0ca943ce4014 18 static unsigned short read_PHY (unsigned int PhyReg) {
rpavoor3 0:0ca943ce4014 19 /* Read a PHY register 'PhyReg'. */
rpavoor3 0:0ca943ce4014 20 unsigned int tout, val;
rpavoor3 0:0ca943ce4014 21
rpavoor3 0:0ca943ce4014 22 LPC_EMAC->MADR = DP83848C_DEF_ADR | PhyReg;
rpavoor3 0:0ca943ce4014 23 LPC_EMAC->MCMD = MCMD_READ;
rpavoor3 0:0ca943ce4014 24
rpavoor3 0:0ca943ce4014 25 /* Wait until operation completed */
rpavoor3 0:0ca943ce4014 26 for (tout = 0; tout < MII_RD_TOUT; tout++) {
rpavoor3 0:0ca943ce4014 27 if ((LPC_EMAC->MIND & MIND_BUSY) == 0) {
rpavoor3 0:0ca943ce4014 28 break;
rpavoor3 0:0ca943ce4014 29 }
rpavoor3 0:0ca943ce4014 30 }
rpavoor3 0:0ca943ce4014 31 LPC_EMAC->MCMD = 0;
rpavoor3 0:0ca943ce4014 32 val = LPC_EMAC->MRDD;
rpavoor3 0:0ca943ce4014 33
rpavoor3 0:0ca943ce4014 34 return (val);
rpavoor3 0:0ca943ce4014 35 }
rpavoor3 0:0ca943ce4014 36
rpavoor3 0:0ca943ce4014 37 void EMAC_Init()
rpavoor3 0:0ca943ce4014 38 {
rpavoor3 0:0ca943ce4014 39 unsigned int tout,regv;
rpavoor3 0:0ca943ce4014 40 /* Power Up the EMAC controller. */
rpavoor3 0:0ca943ce4014 41 Peripheral_PowerUp(LPC1768_PCONP_PCENET);
rpavoor3 0:0ca943ce4014 42
rpavoor3 0:0ca943ce4014 43 LPC_PINCON->PINSEL2 = 0x50150105;
rpavoor3 0:0ca943ce4014 44 LPC_PINCON->PINSEL3 &= ~0x0000000F;
rpavoor3 0:0ca943ce4014 45 LPC_PINCON->PINSEL3 |= 0x00000005;
rpavoor3 0:0ca943ce4014 46
rpavoor3 0:0ca943ce4014 47 /* Reset all EMAC internal modules. */
rpavoor3 0:0ca943ce4014 48 LPC_EMAC->MAC1 = MAC1_RES_TX | MAC1_RES_MCS_TX | MAC1_RES_RX | MAC1_RES_MCS_RX |
rpavoor3 0:0ca943ce4014 49 MAC1_SIM_RES | MAC1_SOFT_RES;
rpavoor3 0:0ca943ce4014 50 LPC_EMAC->Command = CR_REG_RES | CR_TX_RES | CR_RX_RES;
rpavoor3 0:0ca943ce4014 51
rpavoor3 0:0ca943ce4014 52 /* A short delay after reset. */
rpavoor3 0:0ca943ce4014 53 for (tout = 100; tout; tout--);
rpavoor3 0:0ca943ce4014 54
rpavoor3 0:0ca943ce4014 55 /* Initialize MAC control registers. */
rpavoor3 0:0ca943ce4014 56 LPC_EMAC->MAC1 = MAC1_PASS_ALL;
rpavoor3 0:0ca943ce4014 57 LPC_EMAC->MAC2 = MAC2_CRC_EN | MAC2_PAD_EN;
rpavoor3 0:0ca943ce4014 58 LPC_EMAC->MAXF = ETH_MAX_FLEN;
rpavoor3 0:0ca943ce4014 59 LPC_EMAC->CLRT = CLRT_DEF;
rpavoor3 0:0ca943ce4014 60 LPC_EMAC->IPGR = IPGR_DEF;
rpavoor3 0:0ca943ce4014 61
rpavoor3 0:0ca943ce4014 62 /* Enable Reduced MII interface. */
rpavoor3 0:0ca943ce4014 63 LPC_EMAC->Command = CR_RMII | CR_PASS_RUNT_FRM;
rpavoor3 0:0ca943ce4014 64
rpavoor3 0:0ca943ce4014 65 /* Reset Reduced MII Logic. */
rpavoor3 0:0ca943ce4014 66 LPC_EMAC->SUPP = SUPP_RES_RMII;
rpavoor3 0:0ca943ce4014 67 for (tout = 100; tout; tout--);
rpavoor3 0:0ca943ce4014 68 LPC_EMAC->SUPP = 0;
rpavoor3 0:0ca943ce4014 69
rpavoor3 0:0ca943ce4014 70 /* Put the DP83848C in reset mode */
rpavoor3 0:0ca943ce4014 71 write_PHY (PHY_REG_BMCR, 0x8000);
rpavoor3 0:0ca943ce4014 72
rpavoor3 0:0ca943ce4014 73 /* Wait for hardware reset to end. */
rpavoor3 0:0ca943ce4014 74 for (tout = 0; tout < 0x100000; tout++) {
rpavoor3 0:0ca943ce4014 75 regv = read_PHY (PHY_REG_BMCR);
rpavoor3 0:0ca943ce4014 76 if (!(regv & 0x8000)) {
rpavoor3 0:0ca943ce4014 77 /* Reset complete */
rpavoor3 0:0ca943ce4014 78 break;
rpavoor3 0:0ca943ce4014 79 }
rpavoor3 0:0ca943ce4014 80 }
rpavoor3 0:0ca943ce4014 81 }
rpavoor3 0:0ca943ce4014 82
rpavoor3 0:0ca943ce4014 83
rpavoor3 0:0ca943ce4014 84 void PHY_PowerDown()
rpavoor3 0:0ca943ce4014 85 {
rpavoor3 0:0ca943ce4014 86 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
rpavoor3 0:0ca943ce4014 87 EMAC_Init(); //init EMAC if it is not already init'd
rpavoor3 0:0ca943ce4014 88
rpavoor3 0:0ca943ce4014 89 unsigned int regv;
rpavoor3 0:0ca943ce4014 90 regv = read_PHY(PHY_REG_BMCR);
rpavoor3 0:0ca943ce4014 91 write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_BMCR_POWERDOWN));
rpavoor3 0:0ca943ce4014 92 regv = read_PHY(PHY_REG_BMCR);
rpavoor3 0:0ca943ce4014 93
rpavoor3 0:0ca943ce4014 94 //shouldn't need the EMAC now.
rpavoor3 0:0ca943ce4014 95 Peripheral_PowerDown(LPC1768_PCONP_PCENET);
rpavoor3 0:0ca943ce4014 96
rpavoor3 0:0ca943ce4014 97 //and turn off the PHY OSC
rpavoor3 0:0ca943ce4014 98 LPC_GPIO1->FIODIR |= 0x8000000;
rpavoor3 0:0ca943ce4014 99 LPC_GPIO1->FIOCLR = 0x8000000;
rpavoor3 0:0ca943ce4014 100 }
rpavoor3 0:0ca943ce4014 101
rpavoor3 0:0ca943ce4014 102 void PHY_PowerUp()
rpavoor3 0:0ca943ce4014 103 {
rpavoor3 0:0ca943ce4014 104 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
rpavoor3 0:0ca943ce4014 105 EMAC_Init(); //init EMAC if it is not already init'd
rpavoor3 0:0ca943ce4014 106
rpavoor3 0:0ca943ce4014 107 LPC_GPIO1->FIODIR |= 0x8000000;
rpavoor3 0:0ca943ce4014 108 LPC_GPIO1->FIOSET = 0x8000000;
rpavoor3 0:0ca943ce4014 109
rpavoor3 0:0ca943ce4014 110 //wait for osc to be stable
rpavoor3 0:0ca943ce4014 111 wait_ms(200);
rpavoor3 0:0ca943ce4014 112
rpavoor3 0:0ca943ce4014 113 unsigned int regv;
rpavoor3 0:0ca943ce4014 114 regv = read_PHY(PHY_REG_BMCR);
rpavoor3 0:0ca943ce4014 115 write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_BMCR_POWERDOWN));
rpavoor3 0:0ca943ce4014 116 regv = read_PHY(PHY_REG_BMCR);
rpavoor3 0:0ca943ce4014 117 }
rpavoor3 0:0ca943ce4014 118
rpavoor3 0:0ca943ce4014 119 void PHY_EnergyDetect_Enable()
rpavoor3 0:0ca943ce4014 120 {
rpavoor3 0:0ca943ce4014 121 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
rpavoor3 0:0ca943ce4014 122 EMAC_Init(); //init EMAC if it is not already init'd
rpavoor3 0:0ca943ce4014 123
rpavoor3 0:0ca943ce4014 124 unsigned int regv;
rpavoor3 0:0ca943ce4014 125 regv = read_PHY(PHY_REG_EDCR);
rpavoor3 0:0ca943ce4014 126 write_PHY(PHY_REG_BMCR, regv | (1 << PHY_REG_EDCR_ENABLE));
rpavoor3 0:0ca943ce4014 127 regv = read_PHY(PHY_REG_EDCR);
rpavoor3 0:0ca943ce4014 128 }
rpavoor3 0:0ca943ce4014 129
rpavoor3 0:0ca943ce4014 130 void PHY_EnergyDetect_Disable()
rpavoor3 0:0ca943ce4014 131 {
rpavoor3 0:0ca943ce4014 132 if (!Peripheral_GetStatus(LPC1768_PCONP_PCENET))
rpavoor3 0:0ca943ce4014 133 EMAC_Init(); //init EMAC if it is not already init'd
rpavoor3 0:0ca943ce4014 134 unsigned int regv;
rpavoor3 0:0ca943ce4014 135 regv = read_PHY(PHY_REG_EDCR);
rpavoor3 0:0ca943ce4014 136 write_PHY(PHY_REG_BMCR, regv & ~(1 << PHY_REG_EDCR_ENABLE));
rpavoor3 0:0ca943ce4014 137 regv = read_PHY(PHY_REG_EDCR);
rpavoor3 0:0ca943ce4014 138 }