一関 Aチーム / ArduinoUsbHostShield

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USB_Host/cdc_XR21B1411.h@0:b1ce54272580, 2020-01-18 (annotated)

Committer:
kotakku
Date:
Sat Jan 18 15:06:35 2020 +0000
Revision:
0:b1ce54272580
1.0.0 first commit

Who changed what in which revision?

UserRevisionLine numberNew contents of line
kotakku 0:b1ce54272580 1 /* Copyright (C) 2015 Andrew J. Kroll
kotakku 0:b1ce54272580 2 and
kotakku 0:b1ce54272580 3 Circuits At Home, LTD. All rights reserved.
kotakku 0:b1ce54272580 4
kotakku 0:b1ce54272580 5 This software may be distributed and modified under the terms of the GNU
kotakku 0:b1ce54272580 6 General Public License version 2 (GPL2) as published by the Free Software
kotakku 0:b1ce54272580 7 Foundation and appearing in the file GPL2.TXT included in the packaging of
kotakku 0:b1ce54272580 8 this file. Please note that GPL2 Section 2[b] requires that all works based
kotakku 0:b1ce54272580 9 on this software must also be made publicly available under the terms of
kotakku 0:b1ce54272580 10 the GPL2 ("Copyleft").
kotakku 0:b1ce54272580 11
kotakku 0:b1ce54272580 12 Contact information
kotakku 0:b1ce54272580 13 -------------------
kotakku 0:b1ce54272580 14
kotakku 0:b1ce54272580 15 Circuits At Home, LTD
kotakku 0:b1ce54272580 16 Web : http://www.circuitsathome.com
kotakku 0:b1ce54272580 17 e-mail : support@circuitsathome.com
kotakku 0:b1ce54272580 18 */
kotakku 0:b1ce54272580 19 #if !defined(__CDC_XR21B1411_H__)
kotakku 0:b1ce54272580 20 #define __CDC_XR21B1411_H__
kotakku 0:b1ce54272580 21
kotakku 0:b1ce54272580 22 #include "cdcacm.h"
kotakku 0:b1ce54272580 23
kotakku 0:b1ce54272580 24 #define XR_REG_CUSTOM_DRIVER (0x020DU) // DRIVER SELECT
kotakku 0:b1ce54272580 25 #define XR_REG_CUSTOM_DRIVER_ACTIVE (0x0001U) // 0: CDC 1: CUSTOM
kotakku 0:b1ce54272580 26
kotakku 0:b1ce54272580 27 #define XR_REG_ACM_FLOW_CTL (0x0216U) // FLOW CONTROL REGISTER CDCACM MODE
kotakku 0:b1ce54272580 28 #define XR_REG_FLOW_CTL (0x0C06U) // FLOW CONTROL REGISTER CUSTOM MODE
kotakku 0:b1ce54272580 29 #define XR_REG_FLOW_CTL_HALF_DPLX (0x0008U) // 0:FULL DUPLEX 1:HALF DUPLEX
kotakku 0:b1ce54272580 30 #define XR_REG_FLOW_CTL_MODE_MASK (0x0007U) // MODE BITMASK
kotakku 0:b1ce54272580 31 #define XR_REG_FLOW_CTL_NONE (0x0000U) // NO FLOW CONTROL
kotakku 0:b1ce54272580 32 #define XR_REG_FLOW_CTL_HW (0x0001U) // HARDWARE FLOW CONTROL
kotakku 0:b1ce54272580 33 #define XR_REG_FLOW_CTL_SW (0x0002U) // SOFTWARE FLOW CONTROL
kotakku 0:b1ce54272580 34 #define XR_REG_FLOW_CTL_MMMRX (0x0003U) // MULTIDROP RX UPON ADDRESS MATCH
kotakku 0:b1ce54272580 35 #define XR_REG_FLOW_CTL_MMMRXTX (0x0004U) // MULTIDROP RX/TX UPON ADDRESS MATCH
kotakku 0:b1ce54272580 36
kotakku 0:b1ce54272580 37 #define XR_REG_ACM_GPIO_MODE (0x0217U) // GPIO MODE REGISTER IN CDCACM MODE
kotakku 0:b1ce54272580 38 #define XR_REG_GPIO_MODE (0x0C0CU) // GPIO MODE REGISTER IN CUSTOM MODE
kotakku 0:b1ce54272580 39 #define XR_REG_GPIO_MODE_GPIO (0x0000U) // ALL GPIO PINS ACM PROGRAMMABLE
kotakku 0:b1ce54272580 40 #define XR_REG_GPIO_MODE_FC_RTSCTS (0x0001U) // AUTO RTSCTS HW FC (GPIO 4/5)
kotakku 0:b1ce54272580 41 #define XR_REG_GPIO_MODE_FC_DTRDSR (0x0002U) // AUTO DTRDSR HW FC (GPIO 2/3)
kotakku 0:b1ce54272580 42 #define XR_REG_GPIO_MODE_ATE (0x0003U) // AUTO TRANSCEIVER ENABLE DURING TX (GPIO 5)
kotakku 0:b1ce54272580 43 #define XR_REG_GPIO_MODE_ATE_ADDRESS (0x0004U) // AUTO TRANSCEIVER ENABLE ON ADDRESS MATCH (GPIO 5)
kotakku 0:b1ce54272580 44
kotakku 0:b1ce54272580 45 #define XR_REG_ACM_GPIO_DIR (0x0218U) // GPIO DIRECTION REGISTER CDCACM MODE, 0:IN 1:OUT
kotakku 0:b1ce54272580 46 #define XR_REG_GPIO_DIR (0x0C0DU) // GPIO DIRECTION REGISTER CUSTOM MODE, 0:IN 1:OUT
kotakku 0:b1ce54272580 47
kotakku 0:b1ce54272580 48 #define XR_REG_ACM_GPIO_INT (0x0219U) // GPIO PIN CHANGE INTERRUPT ENABLE CDCACM MODE, 0: ENABLED 1: DISABLED
kotakku 0:b1ce54272580 49 #define XR_REG_GPIO_INT (0x0C11U) // GPIO PIN CHANGE INTERRUPT ENABLE CUSTOM MODE, 0: ENABLED 1: DISABLED
kotakku 0:b1ce54272580 50 #define XR_REG_GPIO_MASK (0x001FU) // GPIO REGISTERS BITMASK
kotakku 0:b1ce54272580 51
kotakku 0:b1ce54272580 52 #define XR_REG_UART_ENABLE (0x0C00U) // UART I/O ENABLE REGISTER
kotakku 0:b1ce54272580 53 #define XR_REG_UART_ENABLE_RX (0x0002U) // 0:DISABLED 1:ENABLED
kotakku 0:b1ce54272580 54 #define XR_REG_UART_ENABLE_TX (0x0001U) // 0:DISABLED 1:ENABLED
kotakku 0:b1ce54272580 55
kotakku 0:b1ce54272580 56 #define XR_REG_ERROR_STATUS (0x0C09U) // ERROR STATUS REGISTER
kotakku 0:b1ce54272580 57 #define XR_REG_ERROR_STATUS_MASK (0x00F8U) // ERROR STATUS BITMASK
kotakku 0:b1ce54272580 58 #define XR_REG_ERROR_STATUS_ERROR (0x0070U) // ERROR STATUS ERROR BITMASK
kotakku 0:b1ce54272580 59 #define XR_REG_ERROR_STATUS_BREAK (0x0008U) // BREAK HAS BEEN DETECTED
kotakku 0:b1ce54272580 60 #define XR_REG_ERROR_STATUS_OVERRUN (0x0010U) // RX OVERRUN ERROR
kotakku 0:b1ce54272580 61 #define XR_REG_ERROR_STATUS_PARITY (0x0020U) // PARITY ERROR
kotakku 0:b1ce54272580 62 #define XR_REG_ERROR_STATUS_FRAME (0x0040U) // FRAMING ERROR
kotakku 0:b1ce54272580 63 #define XR_REG_ERROR_STATUS_BREAKING (0x0080U) // BREAK IS BEING DETECTED
kotakku 0:b1ce54272580 64
kotakku 0:b1ce54272580 65 #define XR_REG_TX_BREAK (0x0C0AU) // TRANSMIT BREAK. 0X0001-0XFFE TIME IN MS, 0X0000 STOP, 0X0FFF BREAK ON
kotakku 0:b1ce54272580 66
kotakku 0:b1ce54272580 67 #define XR_REG_XCVR_EN_DELAY (0x0C0BU) // TURN-ARROUND DELAY IN BIT-TIMES 0X0000-0X000F
kotakku 0:b1ce54272580 68
kotakku 0:b1ce54272580 69 #define XR_REG_GPIO_SET (0x0C0EU) // 1:SET GPIO PIN
kotakku 0:b1ce54272580 70
kotakku 0:b1ce54272580 71 #define XR_REG_GPIO_CLR (0x0C0FU) // 1:CLEAR GPIO PIN
kotakku 0:b1ce54272580 72
kotakku 0:b1ce54272580 73 #define XR_REG_GPIO_STATUS (0x0C10U) // READ GPIO PINS
kotakku 0:b1ce54272580 74
kotakku 0:b1ce54272580 75 #define XR_REG_CUSTOMISED_INT (0x0C12U) // 0:STANDARD 1:CUSTOM SEE DATA SHEET
kotakku 0:b1ce54272580 76
kotakku 0:b1ce54272580 77 #define XR_REG_PIN_PULLUP_ENABLE (0x0C14U) // 0:DISABLE 1:ENABLE, BITS 0-5:GPIO, 6:RX 7:TX
kotakku 0:b1ce54272580 78
kotakku 0:b1ce54272580 79 #define XR_REG_PIN_PULLDOWN_ENABLE (0x0C15U) // 0:DISABLE 1:ENABLE, BITS 0-5:GPIO, 6:RX 7:TX
kotakku 0:b1ce54272580 80
kotakku 0:b1ce54272580 81 #define XR_REG_LOOPBACK (0x0C16U) // 0:DISABLE 1:ENABLE, SEE DATA SHEET
kotakku 0:b1ce54272580 82
kotakku 0:b1ce54272580 83 #define XR_REG_RX_FIFO_LATENCY (0x0CC2U) // FIFO LATENCY REGISTER
kotakku 0:b1ce54272580 84 #define XR_REG_RX_FIFO_LATENCY_ENABLE (0x0001U) //
kotakku 0:b1ce54272580 85
kotakku 0:b1ce54272580 86 #define XR_REG_WIDE_MODE (0x0D02U)
kotakku 0:b1ce54272580 87 #define XR_REG_WIDE_MODE_ENABLE (0x0001U)
kotakku 0:b1ce54272580 88
kotakku 0:b1ce54272580 89 #define XR_REG_XON_CHAR (0x0C07U)
kotakku 0:b1ce54272580 90 #define XR_REG_XOFF_CHAR (0x0C08U)
kotakku 0:b1ce54272580 91
kotakku 0:b1ce54272580 92 #define XR_REG_TX_FIFO_RESET (0x0C80U) // 1: RESET, SELF-CLEARING
kotakku 0:b1ce54272580 93 #define XR_REG_TX_FIFO_COUNT (0x0C81U) // READ-ONLY
kotakku 0:b1ce54272580 94 #define XR_REG_RX_FIFO_RESET (0x0CC0U) // 1: RESET, SELF-CLEARING
kotakku 0:b1ce54272580 95 #define XR_REG_RX_FIFO_COUNT (0x0CC1U) // READ-ONLY
kotakku 0:b1ce54272580 96
kotakku 0:b1ce54272580 97 #define XR_WRITE_REQUEST_TYPE (0x40U)
kotakku 0:b1ce54272580 98
kotakku 0:b1ce54272580 99 #define XR_READ_REQUEST_TYPE (0xC0U)
kotakku 0:b1ce54272580 100
kotakku 0:b1ce54272580 101 #define XR_MAX_ENDPOINTS 4
kotakku 0:b1ce54272580 102
kotakku 0:b1ce54272580 103 class XR21B1411 : public ACM {
kotakku 0:b1ce54272580 104 protected:
kotakku 0:b1ce54272580 105
kotakku 0:b1ce54272580 106 public:
kotakku 0:b1ce54272580 107 XR21B1411(USB *pusb, CDCAsyncOper *pasync);
kotakku 0:b1ce54272580 108
kotakku 0:b1ce54272580 109 /**
kotakku 0:b1ce54272580 110 * Used by the USB core to check what this driver support.
kotakku 0:b1ce54272580 111 * @param vid The device's VID.
kotakku 0:b1ce54272580 112 * @param pid The device's PID.
kotakku 0:b1ce54272580 113 * @return Returns true if the device's VID and PID matches this driver.
kotakku 0:b1ce54272580 114 */
kotakku 0:b1ce54272580 115 virtual bool VIDPIDOK(uint16_t vid, uint16_t pid) {
kotakku 0:b1ce54272580 116 return (((vid == 0x2890U) && (pid == 0x0201U)) || ((vid == 0x04e2U) && (pid == 0x1411U)));
kotakku 0:b1ce54272580 117 };
kotakku 0:b1ce54272580 118
kotakku 0:b1ce54272580 119 uint8_t Init(uint8_t parent, uint8_t port, bool lowspeed);
kotakku 0:b1ce54272580 120
kotakku 0:b1ce54272580 121 virtual tty_features enhanced_features(void) {
kotakku 0:b1ce54272580 122 tty_features rv;
kotakku 0:b1ce54272580 123 rv.enhanced = true;
kotakku 0:b1ce54272580 124 rv.autoflow_RTS = true;
kotakku 0:b1ce54272580 125 rv.autoflow_DSR = true;
kotakku 0:b1ce54272580 126 rv.autoflow_XON = true;
kotakku 0:b1ce54272580 127 rv.half_duplex = true;
kotakku 0:b1ce54272580 128 rv.wide = true;
kotakku 0:b1ce54272580 129 return rv;
kotakku 0:b1ce54272580 130 };
kotakku 0:b1ce54272580 131
kotakku 0:b1ce54272580 132 uint8_t read_register(uint16_t reg, uint16_t *val) {
kotakku 0:b1ce54272580 133 return (pUsb->ctrlReq(bAddress, 0, XR_READ_REQUEST_TYPE, 1, 0, 0, reg, 2, 2, (uint8_t *)val, NULL));
kotakku 0:b1ce54272580 134 }
kotakku 0:b1ce54272580 135
kotakku 0:b1ce54272580 136 uint8_t write_register(uint16_t reg, uint16_t val) {
kotakku 0:b1ce54272580 137 return (pUsb->ctrlReq(bAddress, 0, XR_WRITE_REQUEST_TYPE, 0, BGRAB0(val), BGRAB1(val), reg, 0, 0, NULL, NULL));
kotakku 0:b1ce54272580 138 }
kotakku 0:b1ce54272580 139
kotakku 0:b1ce54272580 140
kotakku 0:b1ce54272580 141 ////////////////////////////////////////////////////////////////////////
kotakku 0:b1ce54272580 142 // The following methods set the CDC-ACM defaults.
kotakku 0:b1ce54272580 143 ////////////////////////////////////////////////////////////////////////
kotakku 0:b1ce54272580 144
kotakku 0:b1ce54272580 145 virtual void autoflowRTS(bool s) {
kotakku 0:b1ce54272580 146 uint16_t val;
kotakku 0:b1ce54272580 147 uint8_t rval;
kotakku 0:b1ce54272580 148 rval = read_register(XR_REG_ACM_FLOW_CTL, &val);
kotakku 0:b1ce54272580 149 if(!rval) {
kotakku 0:b1ce54272580 150 if(s) {
kotakku 0:b1ce54272580 151 val &= XR_REG_FLOW_CTL_HALF_DPLX;
kotakku 0:b1ce54272580 152 val |= XR_REG_FLOW_CTL_HW;
kotakku 0:b1ce54272580 153 } else {
kotakku 0:b1ce54272580 154 val &= XR_REG_FLOW_CTL_HALF_DPLX;
kotakku 0:b1ce54272580 155 }
kotakku 0:b1ce54272580 156 rval = write_register(XR_REG_ACM_FLOW_CTL, val);
kotakku 0:b1ce54272580 157 if(!rval) {
kotakku 0:b1ce54272580 158 rval = write_register(XR_REG_ACM_GPIO_MODE, XR_REG_GPIO_MODE_GPIO);
kotakku 0:b1ce54272580 159 if(!rval) {
kotakku 0:b1ce54272580 160 // ACM commands apply the new settings.
kotakku 0:b1ce54272580 161 LINE_CODING LCT;
kotakku 0:b1ce54272580 162 rval = GetLineCoding(&LCT);
kotakku 0:b1ce54272580 163 if(!rval) {
kotakku 0:b1ce54272580 164 rval = SetLineCoding(&LCT);
kotakku 0:b1ce54272580 165 if(!rval) {
kotakku 0:b1ce54272580 166 _enhanced_status.autoflow_XON = false;
kotakku 0:b1ce54272580 167 _enhanced_status.autoflow_DSR = false;
kotakku 0:b1ce54272580 168 _enhanced_status.autoflow_RTS = s;
kotakku 0:b1ce54272580 169 }
kotakku 0:b1ce54272580 170 }
kotakku 0:b1ce54272580 171 }
kotakku 0:b1ce54272580 172 }
kotakku 0:b1ce54272580 173 }
kotakku 0:b1ce54272580 174 };
kotakku 0:b1ce54272580 175
kotakku 0:b1ce54272580 176 virtual void autoflowDSR(bool s) {
kotakku 0:b1ce54272580 177 uint16_t val;
kotakku 0:b1ce54272580 178 uint8_t rval;
kotakku 0:b1ce54272580 179 rval = read_register(XR_REG_ACM_FLOW_CTL, &val);
kotakku 0:b1ce54272580 180 if(!rval) {
kotakku 0:b1ce54272580 181 if(s) {
kotakku 0:b1ce54272580 182 val &= XR_REG_FLOW_CTL_HALF_DPLX;
kotakku 0:b1ce54272580 183 val |= XR_REG_FLOW_CTL_HW;
kotakku 0:b1ce54272580 184 } else {
kotakku 0:b1ce54272580 185 val &= XR_REG_FLOW_CTL_HALF_DPLX;
kotakku 0:b1ce54272580 186 }
kotakku 0:b1ce54272580 187 rval = write_register(XR_REG_ACM_FLOW_CTL, val);
kotakku 0:b1ce54272580 188 if(!rval) {
kotakku 0:b1ce54272580 189 if(s) {
kotakku 0:b1ce54272580 190 rval = write_register(XR_REG_ACM_GPIO_MODE, XR_REG_GPIO_MODE_FC_DTRDSR);
kotakku 0:b1ce54272580 191 } else {
kotakku 0:b1ce54272580 192 rval = write_register(XR_REG_ACM_GPIO_MODE, XR_REG_GPIO_MODE_GPIO);
kotakku 0:b1ce54272580 193 }
kotakku 0:b1ce54272580 194 if(!rval) {
kotakku 0:b1ce54272580 195 // ACM commands apply the new settings.
kotakku 0:b1ce54272580 196 LINE_CODING LCT;
kotakku 0:b1ce54272580 197 rval = GetLineCoding(&LCT);
kotakku 0:b1ce54272580 198 if(!rval) {
kotakku 0:b1ce54272580 199 rval = SetLineCoding(&LCT);
kotakku 0:b1ce54272580 200 if(!rval) {
kotakku 0:b1ce54272580 201 _enhanced_status.autoflow_XON = false;
kotakku 0:b1ce54272580 202 _enhanced_status.autoflow_RTS = false;
kotakku 0:b1ce54272580 203 _enhanced_status.autoflow_DSR = s;
kotakku 0:b1ce54272580 204 }
kotakku 0:b1ce54272580 205 }
kotakku 0:b1ce54272580 206 }
kotakku 0:b1ce54272580 207 }
kotakku 0:b1ce54272580 208 }
kotakku 0:b1ce54272580 209 };
kotakku 0:b1ce54272580 210
kotakku 0:b1ce54272580 211 virtual void autoflowXON(bool s) {
kotakku 0:b1ce54272580 212 // NOTE: hardware defaults to the normal XON/XOFF
kotakku 0:b1ce54272580 213 uint16_t val;
kotakku 0:b1ce54272580 214 uint8_t rval;
kotakku 0:b1ce54272580 215 rval = read_register(XR_REG_ACM_FLOW_CTL, &val);
kotakku 0:b1ce54272580 216 if(!rval) {
kotakku 0:b1ce54272580 217 if(s) {
kotakku 0:b1ce54272580 218 val &= XR_REG_FLOW_CTL_HALF_DPLX;
kotakku 0:b1ce54272580 219 val |= XR_REG_FLOW_CTL_SW;
kotakku 0:b1ce54272580 220 } else {
kotakku 0:b1ce54272580 221 val &= XR_REG_FLOW_CTL_HALF_DPLX;
kotakku 0:b1ce54272580 222 }
kotakku 0:b1ce54272580 223 rval = write_register(XR_REG_ACM_FLOW_CTL, val);
kotakku 0:b1ce54272580 224 if(!rval) {
kotakku 0:b1ce54272580 225 rval = write_register(XR_REG_ACM_GPIO_MODE, XR_REG_GPIO_MODE_GPIO);
kotakku 0:b1ce54272580 226 if(!rval) {
kotakku 0:b1ce54272580 227 // ACM commands apply the new settings.
kotakku 0:b1ce54272580 228 LINE_CODING LCT;
kotakku 0:b1ce54272580 229 rval = GetLineCoding(&LCT);
kotakku 0:b1ce54272580 230 if(!rval) {
kotakku 0:b1ce54272580 231 rval = SetLineCoding(&LCT);
kotakku 0:b1ce54272580 232 if(!rval) {
kotakku 0:b1ce54272580 233 _enhanced_status.autoflow_RTS = false;
kotakku 0:b1ce54272580 234 _enhanced_status.autoflow_DSR = false;
kotakku 0:b1ce54272580 235 _enhanced_status.autoflow_XON = s;
kotakku 0:b1ce54272580 236 }
kotakku 0:b1ce54272580 237 }
kotakku 0:b1ce54272580 238 }
kotakku 0:b1ce54272580 239 }
kotakku 0:b1ce54272580 240 }
kotakku 0:b1ce54272580 241 };
kotakku 0:b1ce54272580 242
kotakku 0:b1ce54272580 243 virtual void half_duplex(bool s) {
kotakku 0:b1ce54272580 244 uint16_t val;
kotakku 0:b1ce54272580 245 uint8_t rval;
kotakku 0:b1ce54272580 246 rval = read_register(XR_REG_ACM_FLOW_CTL, &val);
kotakku 0:b1ce54272580 247 if(!rval) {
kotakku 0:b1ce54272580 248 if(s) {
kotakku 0:b1ce54272580 249 val |= XR_REG_FLOW_CTL_HALF_DPLX;
kotakku 0:b1ce54272580 250 } else {
kotakku 0:b1ce54272580 251 val &= XR_REG_FLOW_CTL_MODE_MASK;
kotakku 0:b1ce54272580 252 }
kotakku 0:b1ce54272580 253 rval = write_register(XR_REG_ACM_FLOW_CTL, val);
kotakku 0:b1ce54272580 254 if(!rval) {
kotakku 0:b1ce54272580 255 // ACM commands apply the new settings.
kotakku 0:b1ce54272580 256 LINE_CODING LCT;
kotakku 0:b1ce54272580 257 rval = GetLineCoding(&LCT);
kotakku 0:b1ce54272580 258 if(!rval) {
kotakku 0:b1ce54272580 259 rval = SetLineCoding(&LCT);
kotakku 0:b1ce54272580 260 if(!rval) {
kotakku 0:b1ce54272580 261 _enhanced_status.half_duplex = s;
kotakku 0:b1ce54272580 262 }
kotakku 0:b1ce54272580 263 }
kotakku 0:b1ce54272580 264 }
kotakku 0:b1ce54272580 265 }
kotakku 0:b1ce54272580 266 };
kotakku 0:b1ce54272580 267
kotakku 0:b1ce54272580 268
kotakku 0:b1ce54272580 269
kotakku 0:b1ce54272580 270 };
kotakku 0:b1ce54272580 271
kotakku 0:b1ce54272580 272 #endif // __CDCPROLIFIC_H__
kotakku 0:b1ce54272580 273