Robert Lopez / CMSIS5

Aded CMSIS5 DSP and NN folder. Needs some work

NN/source/ActivationFunctions/arm_relu_q7.c@0:eedb7d567a5d, 2018-04-12 (annotated)

Committer:
robert_lp
Date:
Thu Apr 12 01:31:58 2018 +0000
Revision:
0:eedb7d567a5d
CMSIS5 Library

Who changed what in which revision?

UserRevisionLine numberNew contents of line
robert_lp 0:eedb7d567a5d 1 /*
robert_lp 0:eedb7d567a5d 2 * Copyright (C) 2010-2018 Arm Limited or its affiliates. All rights reserved.
robert_lp 0:eedb7d567a5d 3 *
robert_lp 0:eedb7d567a5d 4 * SPDX-License-Identifier: Apache-2.0
robert_lp 0:eedb7d567a5d 5 *
robert_lp 0:eedb7d567a5d 6 * Licensed under the Apache License, Version 2.0 (the License); you may
robert_lp 0:eedb7d567a5d 7 * not use this file except in compliance with the License.
robert_lp 0:eedb7d567a5d 8 * You may obtain a copy of the License at
robert_lp 0:eedb7d567a5d 9 *
robert_lp 0:eedb7d567a5d 10 * www.apache.org/licenses/LICENSE-2.0
robert_lp 0:eedb7d567a5d 11 *
robert_lp 0:eedb7d567a5d 12 * Unless required by applicable law or agreed to in writing, software
robert_lp 0:eedb7d567a5d 13 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
robert_lp 0:eedb7d567a5d 14 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
robert_lp 0:eedb7d567a5d 15 * See the License for the specific language governing permissions and
robert_lp 0:eedb7d567a5d 16 * limitations under the License.
robert_lp 0:eedb7d567a5d 17 */
robert_lp 0:eedb7d567a5d 18
robert_lp 0:eedb7d567a5d 19 /* ----------------------------------------------------------------------
robert_lp 0:eedb7d567a5d 20 * Project: CMSIS NN Library
robert_lp 0:eedb7d567a5d 21 * Title: arm_relu_q7.c
robert_lp 0:eedb7d567a5d 22 * Description: Q7 version of ReLU
robert_lp 0:eedb7d567a5d 23 *
robert_lp 0:eedb7d567a5d 24 * $Date: 17. January 2018
robert_lp 0:eedb7d567a5d 25 * $Revision: V.1.0.0
robert_lp 0:eedb7d567a5d 26 *
robert_lp 0:eedb7d567a5d 27 * Target Processor: Cortex-M cores
robert_lp 0:eedb7d567a5d 28 *
robert_lp 0:eedb7d567a5d 29 * -------------------------------------------------------------------- */
robert_lp 0:eedb7d567a5d 30
robert_lp 0:eedb7d567a5d 31 #include "arm_math.h"
robert_lp 0:eedb7d567a5d 32 #include "arm_nnfunctions.h"
robert_lp 0:eedb7d567a5d 33
robert_lp 0:eedb7d567a5d 34 /**
robert_lp 0:eedb7d567a5d 35 * @ingroup groupNN
robert_lp 0:eedb7d567a5d 36 */
robert_lp 0:eedb7d567a5d 37
robert_lp 0:eedb7d567a5d 38 /**
robert_lp 0:eedb7d567a5d 39 * @addtogroup Acti
robert_lp 0:eedb7d567a5d 40 * @{
robert_lp 0:eedb7d567a5d 41 */
robert_lp 0:eedb7d567a5d 42
robert_lp 0:eedb7d567a5d 43 /**
robert_lp 0:eedb7d567a5d 44 * @brief Q7 RELU function
robert_lp 0:eedb7d567a5d 45 * @param[in,out] data pointer to input
robert_lp 0:eedb7d567a5d 46 * @param[in] size number of elements
robert_lp 0:eedb7d567a5d 47 * @return none.
robert_lp 0:eedb7d567a5d 48 *
robert_lp 0:eedb7d567a5d 49 * @details
robert_lp 0:eedb7d567a5d 50 *
robert_lp 0:eedb7d567a5d 51 * Optimized relu with QSUB instructions.
robert_lp 0:eedb7d567a5d 52 *
robert_lp 0:eedb7d567a5d 53 */
robert_lp 0:eedb7d567a5d 54
robert_lp 0:eedb7d567a5d 55 void arm_relu_q7(q7_t * data, uint16_t size)
robert_lp 0:eedb7d567a5d 56 {
robert_lp 0:eedb7d567a5d 57
robert_lp 0:eedb7d567a5d 58 #if defined (ARM_MATH_DSP)
robert_lp 0:eedb7d567a5d 59 /* Run the following code for Cortex-M4 and Cortex-M7 */
robert_lp 0:eedb7d567a5d 60
robert_lp 0:eedb7d567a5d 61 uint16_t i = size >> 2;
robert_lp 0:eedb7d567a5d 62 q7_t *pIn = data;
robert_lp 0:eedb7d567a5d 63 q7_t *pOut = data;
robert_lp 0:eedb7d567a5d 64 q31_t in;
robert_lp 0:eedb7d567a5d 65 q31_t buf;
robert_lp 0:eedb7d567a5d 66 q31_t mask;
robert_lp 0:eedb7d567a5d 67
robert_lp 0:eedb7d567a5d 68 while (i)
robert_lp 0:eedb7d567a5d 69 {
robert_lp 0:eedb7d567a5d 70 in = *__SIMD32(pIn)++;
robert_lp 0:eedb7d567a5d 71
robert_lp 0:eedb7d567a5d 72 /* extract the first bit */
robert_lp 0:eedb7d567a5d 73 buf = __ROR(in & 0x80808080, 7);
robert_lp 0:eedb7d567a5d 74
robert_lp 0:eedb7d567a5d 75 /* if MSB=1, mask will be 0xFF, 0x0 otherwise */
robert_lp 0:eedb7d567a5d 76 mask = __QSUB8(0x00000000, buf);
robert_lp 0:eedb7d567a5d 77
robert_lp 0:eedb7d567a5d 78 *__SIMD32(pOut)++ = in & (~mask);
robert_lp 0:eedb7d567a5d 79 i--;
robert_lp 0:eedb7d567a5d 80 }
robert_lp 0:eedb7d567a5d 81
robert_lp 0:eedb7d567a5d 82 i = size & 0x3;
robert_lp 0:eedb7d567a5d 83 while (i)
robert_lp 0:eedb7d567a5d 84 {
robert_lp 0:eedb7d567a5d 85 if (*pIn < 0)
robert_lp 0:eedb7d567a5d 86 {
robert_lp 0:eedb7d567a5d 87 *pIn = 0;
robert_lp 0:eedb7d567a5d 88 }
robert_lp 0:eedb7d567a5d 89 pIn++;
robert_lp 0:eedb7d567a5d 90 i--;
robert_lp 0:eedb7d567a5d 91 }
robert_lp 0:eedb7d567a5d 92
robert_lp 0:eedb7d567a5d 93 #else
robert_lp 0:eedb7d567a5d 94 /* Run the following code as reference implementation for Cortex-M0 and Cortex-M3 */
robert_lp 0:eedb7d567a5d 95
robert_lp 0:eedb7d567a5d 96 uint16_t i;
robert_lp 0:eedb7d567a5d 97
robert_lp 0:eedb7d567a5d 98 for (i = 0; i < size; i++)
robert_lp 0:eedb7d567a5d 99 {
robert_lp 0:eedb7d567a5d 100 if (data[i] < 0)
robert_lp 0:eedb7d567a5d 101 data[i] = 0;
robert_lp 0:eedb7d567a5d 102 }
robert_lp 0:eedb7d567a5d 103
robert_lp 0:eedb7d567a5d 104 #endif /* ARM_MATH_DSP */
robert_lp 0:eedb7d567a5d 105
robert_lp 0:eedb7d567a5d 106 }
robert_lp 0:eedb7d567a5d 107
robert_lp 0:eedb7d567a5d 108 /**
robert_lp 0:eedb7d567a5d 109 * @} end of Acti group
robert_lp 0:eedb7d567a5d 110 */
robert_lp 0:eedb7d567a5d 111