Robert Lopez / CMSIS5

Aded CMSIS5 DSP and NN folder. Needs some work

Core/include/mpu_armv7.h@0:eedb7d567a5d, 2018-04-12 (annotated)

Committer:
robert_lp
Date:
Thu Apr 12 01:31:58 2018 +0000
Revision:
0:eedb7d567a5d
CMSIS5 Library

Who changed what in which revision?

UserRevisionLine numberNew contents of line
robert_lp 0:eedb7d567a5d 1 /******************************************************************************
robert_lp 0:eedb7d567a5d 2 * @file mpu_armv7.h
robert_lp 0:eedb7d567a5d 3 * @brief CMSIS MPU API for Armv7-M MPU
robert_lp 0:eedb7d567a5d 4 * @version V5.0.4
robert_lp 0:eedb7d567a5d 5 * @date 10. January 2018
robert_lp 0:eedb7d567a5d 6 ******************************************************************************/
robert_lp 0:eedb7d567a5d 7 /*
robert_lp 0:eedb7d567a5d 8 * Copyright (c) 2017-2018 Arm Limited. All rights reserved.
robert_lp 0:eedb7d567a5d 9 *
robert_lp 0:eedb7d567a5d 10 * SPDX-License-Identifier: Apache-2.0
robert_lp 0:eedb7d567a5d 11 *
robert_lp 0:eedb7d567a5d 12 * Licensed under the Apache License, Version 2.0 (the License); you may
robert_lp 0:eedb7d567a5d 13 * not use this file except in compliance with the License.
robert_lp 0:eedb7d567a5d 14 * You may obtain a copy of the License at
robert_lp 0:eedb7d567a5d 15 *
robert_lp 0:eedb7d567a5d 16 * www.apache.org/licenses/LICENSE-2.0
robert_lp 0:eedb7d567a5d 17 *
robert_lp 0:eedb7d567a5d 18 * Unless required by applicable law or agreed to in writing, software
robert_lp 0:eedb7d567a5d 19 * distributed under the License is distributed on an AS IS BASIS, WITHOUT
robert_lp 0:eedb7d567a5d 20 * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
robert_lp 0:eedb7d567a5d 21 * See the License for the specific language governing permissions and
robert_lp 0:eedb7d567a5d 22 * limitations under the License.
robert_lp 0:eedb7d567a5d 23 */
robert_lp 0:eedb7d567a5d 24
robert_lp 0:eedb7d567a5d 25 #if defined ( __ICCARM__ )
robert_lp 0:eedb7d567a5d 26 #pragma system_include /* treat file as system include file for MISRA check */
robert_lp 0:eedb7d567a5d 27 #elif defined (__clang__)
robert_lp 0:eedb7d567a5d 28 #pragma clang system_header /* treat file as system include file */
robert_lp 0:eedb7d567a5d 29 #endif
robert_lp 0:eedb7d567a5d 30
robert_lp 0:eedb7d567a5d 31 #ifndef ARM_MPU_ARMV7_H
robert_lp 0:eedb7d567a5d 32 #define ARM_MPU_ARMV7_H
robert_lp 0:eedb7d567a5d 33
robert_lp 0:eedb7d567a5d 34 #define ARM_MPU_REGION_SIZE_32B ((uint8_t)0x04U)
robert_lp 0:eedb7d567a5d 35 #define ARM_MPU_REGION_SIZE_64B ((uint8_t)0x05U)
robert_lp 0:eedb7d567a5d 36 #define ARM_MPU_REGION_SIZE_128B ((uint8_t)0x06U)
robert_lp 0:eedb7d567a5d 37 #define ARM_MPU_REGION_SIZE_256B ((uint8_t)0x07U)
robert_lp 0:eedb7d567a5d 38 #define ARM_MPU_REGION_SIZE_512B ((uint8_t)0x08U)
robert_lp 0:eedb7d567a5d 39 #define ARM_MPU_REGION_SIZE_1KB ((uint8_t)0x09U)
robert_lp 0:eedb7d567a5d 40 #define ARM_MPU_REGION_SIZE_2KB ((uint8_t)0x0AU)
robert_lp 0:eedb7d567a5d 41 #define ARM_MPU_REGION_SIZE_4KB ((uint8_t)0x0BU)
robert_lp 0:eedb7d567a5d 42 #define ARM_MPU_REGION_SIZE_8KB ((uint8_t)0x0CU)
robert_lp 0:eedb7d567a5d 43 #define ARM_MPU_REGION_SIZE_16KB ((uint8_t)0x0DU)
robert_lp 0:eedb7d567a5d 44 #define ARM_MPU_REGION_SIZE_32KB ((uint8_t)0x0EU)
robert_lp 0:eedb7d567a5d 45 #define ARM_MPU_REGION_SIZE_64KB ((uint8_t)0x0FU)
robert_lp 0:eedb7d567a5d 46 #define ARM_MPU_REGION_SIZE_128KB ((uint8_t)0x10U)
robert_lp 0:eedb7d567a5d 47 #define ARM_MPU_REGION_SIZE_256KB ((uint8_t)0x11U)
robert_lp 0:eedb7d567a5d 48 #define ARM_MPU_REGION_SIZE_512KB ((uint8_t)0x12U)
robert_lp 0:eedb7d567a5d 49 #define ARM_MPU_REGION_SIZE_1MB ((uint8_t)0x13U)
robert_lp 0:eedb7d567a5d 50 #define ARM_MPU_REGION_SIZE_2MB ((uint8_t)0x14U)
robert_lp 0:eedb7d567a5d 51 #define ARM_MPU_REGION_SIZE_4MB ((uint8_t)0x15U)
robert_lp 0:eedb7d567a5d 52 #define ARM_MPU_REGION_SIZE_8MB ((uint8_t)0x16U)
robert_lp 0:eedb7d567a5d 53 #define ARM_MPU_REGION_SIZE_16MB ((uint8_t)0x17U)
robert_lp 0:eedb7d567a5d 54 #define ARM_MPU_REGION_SIZE_32MB ((uint8_t)0x18U)
robert_lp 0:eedb7d567a5d 55 #define ARM_MPU_REGION_SIZE_64MB ((uint8_t)0x19U)
robert_lp 0:eedb7d567a5d 56 #define ARM_MPU_REGION_SIZE_128MB ((uint8_t)0x1AU)
robert_lp 0:eedb7d567a5d 57 #define ARM_MPU_REGION_SIZE_256MB ((uint8_t)0x1BU)
robert_lp 0:eedb7d567a5d 58 #define ARM_MPU_REGION_SIZE_512MB ((uint8_t)0x1CU)
robert_lp 0:eedb7d567a5d 59 #define ARM_MPU_REGION_SIZE_1GB ((uint8_t)0x1DU)
robert_lp 0:eedb7d567a5d 60 #define ARM_MPU_REGION_SIZE_2GB ((uint8_t)0x1EU)
robert_lp 0:eedb7d567a5d 61 #define ARM_MPU_REGION_SIZE_4GB ((uint8_t)0x1FU)
robert_lp 0:eedb7d567a5d 62
robert_lp 0:eedb7d567a5d 63 #define ARM_MPU_AP_NONE 0U
robert_lp 0:eedb7d567a5d 64 #define ARM_MPU_AP_PRIV 1U
robert_lp 0:eedb7d567a5d 65 #define ARM_MPU_AP_URO 2U
robert_lp 0:eedb7d567a5d 66 #define ARM_MPU_AP_FULL 3U
robert_lp 0:eedb7d567a5d 67 #define ARM_MPU_AP_PRO 5U
robert_lp 0:eedb7d567a5d 68 #define ARM_MPU_AP_RO 6U
robert_lp 0:eedb7d567a5d 69
robert_lp 0:eedb7d567a5d 70 /** MPU Region Base Address Register Value
robert_lp 0:eedb7d567a5d 71 *
robert_lp 0:eedb7d567a5d 72 * \param Region The region to be configured, number 0 to 15.
robert_lp 0:eedb7d567a5d 73 * \param BaseAddress The base address for the region.
robert_lp 0:eedb7d567a5d 74 */
robert_lp 0:eedb7d567a5d 75 #define ARM_MPU_RBAR(Region, BaseAddress) \
robert_lp 0:eedb7d567a5d 76 (((BaseAddress) & MPU_RBAR_ADDR_Msk) | \
robert_lp 0:eedb7d567a5d 77 ((Region) & MPU_RBAR_REGION_Msk) | \
robert_lp 0:eedb7d567a5d 78 (MPU_RBAR_VALID_Msk))
robert_lp 0:eedb7d567a5d 79
robert_lp 0:eedb7d567a5d 80 /**
robert_lp 0:eedb7d567a5d 81 * MPU Region Attribute and Size Register Value
robert_lp 0:eedb7d567a5d 82 *
robert_lp 0:eedb7d567a5d 83 * \param DisableExec Instruction access disable bit, 1= disable instruction fetches.
robert_lp 0:eedb7d567a5d 84 * \param AccessPermission Data access permissions, allows you to configure read/write access for User and Privileged mode.
robert_lp 0:eedb7d567a5d 85 * \param TypeExtField Type extension field, allows you to configure memory access type, for example strongly ordered, peripheral.
robert_lp 0:eedb7d567a5d 86 * \param IsShareable Region is shareable between multiple bus masters.
robert_lp 0:eedb7d567a5d 87 * \param IsCacheable Region is cacheable, i.e. its value may be kept in cache.
robert_lp 0:eedb7d567a5d 88 * \param IsBufferable Region is bufferable, i.e. using write-back caching. Cacheable but non-bufferable regions use write-through policy.
robert_lp 0:eedb7d567a5d 89 * \param SubRegionDisable Sub-region disable field.
robert_lp 0:eedb7d567a5d 90 * \param Size Region size of the region to be configured, for example 4K, 8K.
robert_lp 0:eedb7d567a5d 91 */
robert_lp 0:eedb7d567a5d 92 #define ARM_MPU_RASR(DisableExec, AccessPermission, TypeExtField, IsShareable, IsCacheable, IsBufferable, SubRegionDisable, Size) \
robert_lp 0:eedb7d567a5d 93 ((((DisableExec ) << MPU_RASR_XN_Pos) & MPU_RASR_XN_Msk) | \
robert_lp 0:eedb7d567a5d 94 (((AccessPermission) << MPU_RASR_AP_Pos) & MPU_RASR_AP_Msk) | \
robert_lp 0:eedb7d567a5d 95 (((TypeExtField ) << MPU_RASR_TEX_Pos) & MPU_RASR_TEX_Msk) | \
robert_lp 0:eedb7d567a5d 96 (((IsShareable ) << MPU_RASR_S_Pos) & MPU_RASR_S_Msk) | \
robert_lp 0:eedb7d567a5d 97 (((IsCacheable ) << MPU_RASR_C_Pos) & MPU_RASR_C_Msk) | \
robert_lp 0:eedb7d567a5d 98 (((IsBufferable ) << MPU_RASR_B_Pos) & MPU_RASR_B_Msk) | \
robert_lp 0:eedb7d567a5d 99 (((SubRegionDisable) << MPU_RASR_SRD_Pos) & MPU_RASR_SRD_Msk) | \
robert_lp 0:eedb7d567a5d 100 (((Size ) << MPU_RASR_SIZE_Pos) & MPU_RASR_SIZE_Msk) | \
robert_lp 0:eedb7d567a5d 101 (MPU_RASR_ENABLE_Msk))
robert_lp 0:eedb7d567a5d 102
robert_lp 0:eedb7d567a5d 103
robert_lp 0:eedb7d567a5d 104 /**
robert_lp 0:eedb7d567a5d 105 * Struct for a single MPU Region
robert_lp 0:eedb7d567a5d 106 */
robert_lp 0:eedb7d567a5d 107 typedef struct {
robert_lp 0:eedb7d567a5d 108 uint32_t RBAR; //!< The region base address register value (RBAR)
robert_lp 0:eedb7d567a5d 109 uint32_t RASR; //!< The region attribute and size register value (RASR) \ref MPU_RASR
robert_lp 0:eedb7d567a5d 110 } ARM_MPU_Region_t;
robert_lp 0:eedb7d567a5d 111
robert_lp 0:eedb7d567a5d 112 /** Enable the MPU.
robert_lp 0:eedb7d567a5d 113 * \param MPU_Control Default access permissions for unconfigured regions.
robert_lp 0:eedb7d567a5d 114 */
robert_lp 0:eedb7d567a5d 115 __STATIC_INLINE void ARM_MPU_Enable(uint32_t MPU_Control)
robert_lp 0:eedb7d567a5d 116 {
robert_lp 0:eedb7d567a5d 117 __DSB();
robert_lp 0:eedb7d567a5d 118 __ISB();
robert_lp 0:eedb7d567a5d 119 MPU->CTRL = MPU_Control | MPU_CTRL_ENABLE_Msk;
robert_lp 0:eedb7d567a5d 120 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
robert_lp 0:eedb7d567a5d 121 SCB->SHCSR |= SCB_SHCSR_MEMFAULTENA_Msk;
robert_lp 0:eedb7d567a5d 122 #endif
robert_lp 0:eedb7d567a5d 123 }
robert_lp 0:eedb7d567a5d 124
robert_lp 0:eedb7d567a5d 125 /** Disable the MPU.
robert_lp 0:eedb7d567a5d 126 */
robert_lp 0:eedb7d567a5d 127 __STATIC_INLINE void ARM_MPU_Disable(void)
robert_lp 0:eedb7d567a5d 128 {
robert_lp 0:eedb7d567a5d 129 __DSB();
robert_lp 0:eedb7d567a5d 130 __ISB();
robert_lp 0:eedb7d567a5d 131 #ifdef SCB_SHCSR_MEMFAULTENA_Msk
robert_lp 0:eedb7d567a5d 132 SCB->SHCSR &= ~SCB_SHCSR_MEMFAULTENA_Msk;
robert_lp 0:eedb7d567a5d 133 #endif
robert_lp 0:eedb7d567a5d 134 MPU->CTRL &= ~MPU_CTRL_ENABLE_Msk;
robert_lp 0:eedb7d567a5d 135 }
robert_lp 0:eedb7d567a5d 136
robert_lp 0:eedb7d567a5d 137 /** Clear and disable the given MPU region.
robert_lp 0:eedb7d567a5d 138 * \param rnr Region number to be cleared.
robert_lp 0:eedb7d567a5d 139 */
robert_lp 0:eedb7d567a5d 140 __STATIC_INLINE void ARM_MPU_ClrRegion(uint32_t rnr)
robert_lp 0:eedb7d567a5d 141 {
robert_lp 0:eedb7d567a5d 142 MPU->RNR = rnr;
robert_lp 0:eedb7d567a5d 143 MPU->RASR = 0U;
robert_lp 0:eedb7d567a5d 144 }
robert_lp 0:eedb7d567a5d 145
robert_lp 0:eedb7d567a5d 146 /** Configure an MPU region.
robert_lp 0:eedb7d567a5d 147 * \param rbar Value for RBAR register.
robert_lp 0:eedb7d567a5d 148 * \param rsar Value for RSAR register.
robert_lp 0:eedb7d567a5d 149 */
robert_lp 0:eedb7d567a5d 150 __STATIC_INLINE void ARM_MPU_SetRegion(uint32_t rbar, uint32_t rasr)
robert_lp 0:eedb7d567a5d 151 {
robert_lp 0:eedb7d567a5d 152 MPU->RBAR = rbar;
robert_lp 0:eedb7d567a5d 153 MPU->RASR = rasr;
robert_lp 0:eedb7d567a5d 154 }
robert_lp 0:eedb7d567a5d 155
robert_lp 0:eedb7d567a5d 156 /** Configure the given MPU region.
robert_lp 0:eedb7d567a5d 157 * \param rnr Region number to be configured.
robert_lp 0:eedb7d567a5d 158 * \param rbar Value for RBAR register.
robert_lp 0:eedb7d567a5d 159 * \param rsar Value for RSAR register.
robert_lp 0:eedb7d567a5d 160 */
robert_lp 0:eedb7d567a5d 161 __STATIC_INLINE void ARM_MPU_SetRegionEx(uint32_t rnr, uint32_t rbar, uint32_t rasr)
robert_lp 0:eedb7d567a5d 162 {
robert_lp 0:eedb7d567a5d 163 MPU->RNR = rnr;
robert_lp 0:eedb7d567a5d 164 MPU->RBAR = rbar;
robert_lp 0:eedb7d567a5d 165 MPU->RASR = rasr;
robert_lp 0:eedb7d567a5d 166 }
robert_lp 0:eedb7d567a5d 167
robert_lp 0:eedb7d567a5d 168 /** Memcopy with strictly ordered memory access, e.g. for register targets.
robert_lp 0:eedb7d567a5d 169 * \param dst Destination data is copied to.
robert_lp 0:eedb7d567a5d 170 * \param src Source data is copied from.
robert_lp 0:eedb7d567a5d 171 * \param len Amount of data words to be copied.
robert_lp 0:eedb7d567a5d 172 */
robert_lp 0:eedb7d567a5d 173 __STATIC_INLINE void orderedCpy(volatile uint32_t* dst, const uint32_t* __RESTRICT src, uint32_t len)
robert_lp 0:eedb7d567a5d 174 {
robert_lp 0:eedb7d567a5d 175 uint32_t i;
robert_lp 0:eedb7d567a5d 176 for (i = 0U; i < len; ++i)
robert_lp 0:eedb7d567a5d 177 {
robert_lp 0:eedb7d567a5d 178 dst[i] = src[i];
robert_lp 0:eedb7d567a5d 179 }
robert_lp 0:eedb7d567a5d 180 }
robert_lp 0:eedb7d567a5d 181
robert_lp 0:eedb7d567a5d 182 /** Load the given number of MPU regions from a table.
robert_lp 0:eedb7d567a5d 183 * \param table Pointer to the MPU configuration table.
robert_lp 0:eedb7d567a5d 184 * \param cnt Amount of regions to be configured.
robert_lp 0:eedb7d567a5d 185 */
robert_lp 0:eedb7d567a5d 186 __STATIC_INLINE void ARM_MPU_Load(ARM_MPU_Region_t const* table, uint32_t cnt)
robert_lp 0:eedb7d567a5d 187 {
robert_lp 0:eedb7d567a5d 188 const uint32_t rowWordSize = sizeof(ARM_MPU_Region_t)/4U;
robert_lp 0:eedb7d567a5d 189 while (cnt > MPU_TYPE_RALIASES) {
robert_lp 0:eedb7d567a5d 190 orderedCpy(&(MPU->RBAR), &(table->RBAR), MPU_TYPE_RALIASES*rowWordSize);
robert_lp 0:eedb7d567a5d 191 table += MPU_TYPE_RALIASES;
robert_lp 0:eedb7d567a5d 192 cnt -= MPU_TYPE_RALIASES;
robert_lp 0:eedb7d567a5d 193 }
robert_lp 0:eedb7d567a5d 194 orderedCpy(&(MPU->RBAR), &(table->RBAR), cnt*rowWordSize);
robert_lp 0:eedb7d567a5d 195 }
robert_lp 0:eedb7d567a5d 196
robert_lp 0:eedb7d567a5d 197 #endif
robert_lp 0:eedb7d567a5d 198