CMSIS5 - Aded CMSIS5 DSP and NN folder. Needs some work

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Aded CMSIS5 DSP and NN folder. Needs some work

Core/include/core_armv8mbl.h@0:eedb7d567a5d, 2018-04-12 (annotated)

Committer:: robert_lp
Date:: Thu Apr 12 01:31:58 2018 +0000
Revision:: 0:eedb7d567a5d

CMSIS5 Library

Who changed what in which revision?

User	Revision	Line number	New contents of line
robert_lp	0:eedb7d567a5d	1	/************************************************************************//
robert_lp	0:eedb7d567a5d	2	* @file core_armv8mbl.h
robert_lp	0:eedb7d567a5d	3	* @brief CMSIS Armv8-M Baseline Core Peripheral Access Layer Header File
robert_lp	0:eedb7d567a5d	4	* @version V5.0.4
robert_lp	0:eedb7d567a5d	5	* @date 10. January 2018
robert_lp	0:eedb7d567a5d	6	******************************************************************************/
robert_lp	0:eedb7d567a5d	7	/*
robert_lp	0:eedb7d567a5d	8	* Copyright (c) 2009-2018 Arm Limited. All rights reserved.
robert_lp	0:eedb7d567a5d	9	*
robert_lp	0:eedb7d567a5d	10	* SPDX-License-Identifier: Apache-2.0
robert_lp	0:eedb7d567a5d	11	*
robert_lp	0:eedb7d567a5d	12	* Licensed under the Apache License, Version 2.0 (the License); you may
robert_lp	0:eedb7d567a5d	13	* not use this file except in compliance with the License.
robert_lp	0:eedb7d567a5d	14	* You may obtain a copy of the License at
robert_lp	0:eedb7d567a5d	15	*
robert_lp	0:eedb7d567a5d	16	* www.apache.org/licenses/LICENSE-2.0
robert_lp	0:eedb7d567a5d	17	*
robert_lp	0:eedb7d567a5d	18	* Unless required by applicable law or agreed to in writing, software
robert_lp	0:eedb7d567a5d	19	* distributed under the License is distributed on an AS IS BASIS, WITHOUT
robert_lp	0:eedb7d567a5d	20	* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
robert_lp	0:eedb7d567a5d	21	* See the License for the specific language governing permissions and
robert_lp	0:eedb7d567a5d	22	* limitations under the License.
robert_lp	0:eedb7d567a5d	23	*/
robert_lp	0:eedb7d567a5d	24
robert_lp	0:eedb7d567a5d	25	#if defined ( __ICCARM__ )
robert_lp	0:eedb7d567a5d	26	#pragma system_include /* treat file as system include file for MISRA check */
robert_lp	0:eedb7d567a5d	27	#elif defined (__clang__)
robert_lp	0:eedb7d567a5d	28	#pragma clang system_header /* treat file as system include file */
robert_lp	0:eedb7d567a5d	29	#endif
robert_lp	0:eedb7d567a5d	30
robert_lp	0:eedb7d567a5d	31	#ifndef __CORE_ARMV8MBL_H_GENERIC
robert_lp	0:eedb7d567a5d	32	#define __CORE_ARMV8MBL_H_GENERIC
robert_lp	0:eedb7d567a5d	33
robert_lp	0:eedb7d567a5d	34	#include <stdint.h>
robert_lp	0:eedb7d567a5d	35
robert_lp	0:eedb7d567a5d	36	#ifdef __cplusplus
robert_lp	0:eedb7d567a5d	37	extern "C" {
robert_lp	0:eedb7d567a5d	38	#endif
robert_lp	0:eedb7d567a5d	39
robert_lp	0:eedb7d567a5d	40	/**
robert_lp	0:eedb7d567a5d	41	\page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
robert_lp	0:eedb7d567a5d	42	CMSIS violates the following MISRA-C:2004 rules:
robert_lp	0:eedb7d567a5d	43
robert_lp	0:eedb7d567a5d	44	\li Required Rule 8.5, object/function definition in header file.<br>
robert_lp	0:eedb7d567a5d	45	Function definitions in header files are used to allow 'inlining'.
robert_lp	0:eedb7d567a5d	46
robert_lp	0:eedb7d567a5d	47	\li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
robert_lp	0:eedb7d567a5d	48	Unions are used for effective representation of core registers.
robert_lp	0:eedb7d567a5d	49
robert_lp	0:eedb7d567a5d	50	\li Advisory Rule 19.7, Function-like macro defined.<br>
robert_lp	0:eedb7d567a5d	51	Function-like macros are used to allow more efficient code.
robert_lp	0:eedb7d567a5d	52	*/
robert_lp	0:eedb7d567a5d	53
robert_lp	0:eedb7d567a5d	54
robert_lp	0:eedb7d567a5d	55	/*******************************************************************************
robert_lp	0:eedb7d567a5d	56	* CMSIS definitions
robert_lp	0:eedb7d567a5d	57	******************************************************************************/
robert_lp	0:eedb7d567a5d	58	/**
robert_lp	0:eedb7d567a5d	59	\ingroup Cortex_ARMv8MBL
robert_lp	0:eedb7d567a5d	60	@{
robert_lp	0:eedb7d567a5d	61	*/
robert_lp	0:eedb7d567a5d	62
robert_lp	0:eedb7d567a5d	63	#include "cmsis_version.h"
robert_lp	0:eedb7d567a5d	64
robert_lp	0:eedb7d567a5d	65	/* CMSIS definitions */
robert_lp	0:eedb7d567a5d	66	#define __ARMv8MBL_CMSIS_VERSION_MAIN (__CM_CMSIS_VERSION_MAIN) /!< \deprecated [31:16] CMSIS HAL main version /
robert_lp	0:eedb7d567a5d	67	#define __ARMv8MBL_CMSIS_VERSION_SUB (__CM_CMSIS_VERSION_SUB) /!< \deprecated [15:0] CMSIS HAL sub version /
robert_lp	0:eedb7d567a5d	68	#define __ARMv8MBL_CMSIS_VERSION ((__ARMv8MBL_CMSIS_VERSION_MAIN << 16U) \| \
robert_lp	0:eedb7d567a5d	69	__ARMv8MBL_CMSIS_VERSION_SUB ) /!< \deprecated CMSIS HAL version number /
robert_lp	0:eedb7d567a5d	70
robert_lp	0:eedb7d567a5d	71	#define __CORTEX_M ( 2U) /!< Cortex-M Core /
robert_lp	0:eedb7d567a5d	72
robert_lp	0:eedb7d567a5d	73	/** __FPU_USED indicates whether an FPU is used or not.
robert_lp	0:eedb7d567a5d	74	This core does not support an FPU at all
robert_lp	0:eedb7d567a5d	75	*/
robert_lp	0:eedb7d567a5d	76	#define __FPU_USED 0U
robert_lp	0:eedb7d567a5d	77
robert_lp	0:eedb7d567a5d	78	#if defined ( __CC_ARM )
robert_lp	0:eedb7d567a5d	79	#if defined __TARGET_FPU_VFP
robert_lp	0:eedb7d567a5d	80	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
robert_lp	0:eedb7d567a5d	81	#endif
robert_lp	0:eedb7d567a5d	82
robert_lp	0:eedb7d567a5d	83	#elif defined (__ARMCC_VERSION) && (__ARMCC_VERSION >= 6010050)
robert_lp	0:eedb7d567a5d	84	#if defined __ARM_PCS_VFP
robert_lp	0:eedb7d567a5d	85	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
robert_lp	0:eedb7d567a5d	86	#endif
robert_lp	0:eedb7d567a5d	87
robert_lp	0:eedb7d567a5d	88	#elif defined ( __GNUC__ )
robert_lp	0:eedb7d567a5d	89	#if defined (__VFP_FP__) && !defined(__SOFTFP__)
robert_lp	0:eedb7d567a5d	90	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
robert_lp	0:eedb7d567a5d	91	#endif
robert_lp	0:eedb7d567a5d	92
robert_lp	0:eedb7d567a5d	93	#elif defined ( __ICCARM__ )
robert_lp	0:eedb7d567a5d	94	#if defined __ARMVFP__
robert_lp	0:eedb7d567a5d	95	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
robert_lp	0:eedb7d567a5d	96	#endif
robert_lp	0:eedb7d567a5d	97
robert_lp	0:eedb7d567a5d	98	#elif defined ( __TI_ARM__ )
robert_lp	0:eedb7d567a5d	99	#if defined __TI_VFP_SUPPORT__
robert_lp	0:eedb7d567a5d	100	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
robert_lp	0:eedb7d567a5d	101	#endif
robert_lp	0:eedb7d567a5d	102
robert_lp	0:eedb7d567a5d	103	#elif defined ( __TASKING__ )
robert_lp	0:eedb7d567a5d	104	#if defined __FPU_VFP__
robert_lp	0:eedb7d567a5d	105	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
robert_lp	0:eedb7d567a5d	106	#endif
robert_lp	0:eedb7d567a5d	107
robert_lp	0:eedb7d567a5d	108	#elif defined ( __CSMC__ )
robert_lp	0:eedb7d567a5d	109	#if ( __CSMC__ & 0x400U)
robert_lp	0:eedb7d567a5d	110	#error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
robert_lp	0:eedb7d567a5d	111	#endif
robert_lp	0:eedb7d567a5d	112
robert_lp	0:eedb7d567a5d	113	#endif
robert_lp	0:eedb7d567a5d	114
robert_lp	0:eedb7d567a5d	115	#include "cmsis_compiler.h" /* CMSIS compiler specific defines */
robert_lp	0:eedb7d567a5d	116
robert_lp	0:eedb7d567a5d	117
robert_lp	0:eedb7d567a5d	118	#ifdef __cplusplus
robert_lp	0:eedb7d567a5d	119	}
robert_lp	0:eedb7d567a5d	120	#endif
robert_lp	0:eedb7d567a5d	121
robert_lp	0:eedb7d567a5d	122	#endif /* __CORE_ARMV8MBL_H_GENERIC */
robert_lp	0:eedb7d567a5d	123
robert_lp	0:eedb7d567a5d	124	#ifndef __CMSIS_GENERIC
robert_lp	0:eedb7d567a5d	125
robert_lp	0:eedb7d567a5d	126	#ifndef __CORE_ARMV8MBL_H_DEPENDANT
robert_lp	0:eedb7d567a5d	127	#define __CORE_ARMV8MBL_H_DEPENDANT
robert_lp	0:eedb7d567a5d	128
robert_lp	0:eedb7d567a5d	129	#ifdef __cplusplus
robert_lp	0:eedb7d567a5d	130	extern "C" {
robert_lp	0:eedb7d567a5d	131	#endif
robert_lp	0:eedb7d567a5d	132
robert_lp	0:eedb7d567a5d	133	/* check device defines and use defaults */
robert_lp	0:eedb7d567a5d	134	#if defined __CHECK_DEVICE_DEFINES
robert_lp	0:eedb7d567a5d	135	#ifndef __ARMv8MBL_REV
robert_lp	0:eedb7d567a5d	136	#define __ARMv8MBL_REV 0x0000U
robert_lp	0:eedb7d567a5d	137	#warning "__ARMv8MBL_REV not defined in device header file; using default!"
robert_lp	0:eedb7d567a5d	138	#endif
robert_lp	0:eedb7d567a5d	139
robert_lp	0:eedb7d567a5d	140	#ifndef __FPU_PRESENT
robert_lp	0:eedb7d567a5d	141	#define __FPU_PRESENT 0U
robert_lp	0:eedb7d567a5d	142	#warning "__FPU_PRESENT not defined in device header file; using default!"
robert_lp	0:eedb7d567a5d	143	#endif
robert_lp	0:eedb7d567a5d	144
robert_lp	0:eedb7d567a5d	145	#ifndef __MPU_PRESENT
robert_lp	0:eedb7d567a5d	146	#define __MPU_PRESENT 0U
robert_lp	0:eedb7d567a5d	147	#warning "__MPU_PRESENT not defined in device header file; using default!"
robert_lp	0:eedb7d567a5d	148	#endif
robert_lp	0:eedb7d567a5d	149
robert_lp	0:eedb7d567a5d	150	#ifndef __SAUREGION_PRESENT
robert_lp	0:eedb7d567a5d	151	#define __SAUREGION_PRESENT 0U
robert_lp	0:eedb7d567a5d	152	#warning "__SAUREGION_PRESENT not defined in device header file; using default!"
robert_lp	0:eedb7d567a5d	153	#endif
robert_lp	0:eedb7d567a5d	154
robert_lp	0:eedb7d567a5d	155	#ifndef __VTOR_PRESENT
robert_lp	0:eedb7d567a5d	156	#define __VTOR_PRESENT 0U
robert_lp	0:eedb7d567a5d	157	#warning "__VTOR_PRESENT not defined in device header file; using default!"
robert_lp	0:eedb7d567a5d	158	#endif
robert_lp	0:eedb7d567a5d	159
robert_lp	0:eedb7d567a5d	160	#ifndef __NVIC_PRIO_BITS
robert_lp	0:eedb7d567a5d	161	#define __NVIC_PRIO_BITS 2U
robert_lp	0:eedb7d567a5d	162	#warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
robert_lp	0:eedb7d567a5d	163	#endif
robert_lp	0:eedb7d567a5d	164
robert_lp	0:eedb7d567a5d	165	#ifndef __Vendor_SysTickConfig
robert_lp	0:eedb7d567a5d	166	#define __Vendor_SysTickConfig 0U
robert_lp	0:eedb7d567a5d	167	#warning "__Vendor_SysTickConfig not defined in device header file; using default!"
robert_lp	0:eedb7d567a5d	168	#endif
robert_lp	0:eedb7d567a5d	169
robert_lp	0:eedb7d567a5d	170	#ifndef __ETM_PRESENT
robert_lp	0:eedb7d567a5d	171	#define __ETM_PRESENT 0U
robert_lp	0:eedb7d567a5d	172	#warning "__ETM_PRESENT not defined in device header file; using default!"
robert_lp	0:eedb7d567a5d	173	#endif
robert_lp	0:eedb7d567a5d	174
robert_lp	0:eedb7d567a5d	175	#ifndef __MTB_PRESENT
robert_lp	0:eedb7d567a5d	176	#define __MTB_PRESENT 0U
robert_lp	0:eedb7d567a5d	177	#warning "__MTB_PRESENT not defined in device header file; using default!"
robert_lp	0:eedb7d567a5d	178	#endif
robert_lp	0:eedb7d567a5d	179
robert_lp	0:eedb7d567a5d	180	#endif
robert_lp	0:eedb7d567a5d	181
robert_lp	0:eedb7d567a5d	182	/* IO definitions (access restrictions to peripheral registers) */
robert_lp	0:eedb7d567a5d	183	/**
robert_lp	0:eedb7d567a5d	184	\defgroup CMSIS_glob_defs CMSIS Global Defines
robert_lp	0:eedb7d567a5d	185
robert_lp	0:eedb7d567a5d	186	<strong>IO Type Qualifiers</strong> are used
robert_lp	0:eedb7d567a5d	187	\li to specify the access to peripheral variables.
robert_lp	0:eedb7d567a5d	188	\li for automatic generation of peripheral register debug information.
robert_lp	0:eedb7d567a5d	189	*/
robert_lp	0:eedb7d567a5d	190	#ifdef __cplusplus
robert_lp	0:eedb7d567a5d	191	#define __I volatile /!< Defines 'read only' permissions /
robert_lp	0:eedb7d567a5d	192	#else
robert_lp	0:eedb7d567a5d	193	#define __I volatile const /!< Defines 'read only' permissions /
robert_lp	0:eedb7d567a5d	194	#endif
robert_lp	0:eedb7d567a5d	195	#define __O volatile /!< Defines 'write only' permissions /
robert_lp	0:eedb7d567a5d	196	#define __IO volatile /!< Defines 'read / write' permissions /
robert_lp	0:eedb7d567a5d	197
robert_lp	0:eedb7d567a5d	198	/* following defines should be used for structure members */
robert_lp	0:eedb7d567a5d	199	#define __IM volatile const /! Defines 'read only' structure member permissions /
robert_lp	0:eedb7d567a5d	200	#define __OM volatile /! Defines 'write only' structure member permissions /
robert_lp	0:eedb7d567a5d	201	#define __IOM volatile /! Defines 'read / write' structure member permissions /
robert_lp	0:eedb7d567a5d	202
robert_lp	0:eedb7d567a5d	203	/@} end of group ARMv8MBL /
robert_lp	0:eedb7d567a5d	204
robert_lp	0:eedb7d567a5d	205
robert_lp	0:eedb7d567a5d	206
robert_lp	0:eedb7d567a5d	207	/*******************************************************************************
robert_lp	0:eedb7d567a5d	208	* Register Abstraction
robert_lp	0:eedb7d567a5d	209	Core Register contain:
robert_lp	0:eedb7d567a5d	210	- Core Register
robert_lp	0:eedb7d567a5d	211	- Core NVIC Register
robert_lp	0:eedb7d567a5d	212	- Core SCB Register
robert_lp	0:eedb7d567a5d	213	- Core SysTick Register
robert_lp	0:eedb7d567a5d	214	- Core Debug Register
robert_lp	0:eedb7d567a5d	215	- Core MPU Register
robert_lp	0:eedb7d567a5d	216	- Core SAU Register
robert_lp	0:eedb7d567a5d	217	******************************************************************************/
robert_lp	0:eedb7d567a5d	218	/**
robert_lp	0:eedb7d567a5d	219	\defgroup CMSIS_core_register Defines and Type Definitions
robert_lp	0:eedb7d567a5d	220	\brief Type definitions and defines for Cortex-M processor based devices.
robert_lp	0:eedb7d567a5d	221	*/
robert_lp	0:eedb7d567a5d	222
robert_lp	0:eedb7d567a5d	223	/**
robert_lp	0:eedb7d567a5d	224	\ingroup CMSIS_core_register
robert_lp	0:eedb7d567a5d	225	\defgroup CMSIS_CORE Status and Control Registers
robert_lp	0:eedb7d567a5d	226	\brief Core Register type definitions.
robert_lp	0:eedb7d567a5d	227	@{
robert_lp	0:eedb7d567a5d	228	*/
robert_lp	0:eedb7d567a5d	229
robert_lp	0:eedb7d567a5d	230	/**
robert_lp	0:eedb7d567a5d	231	\brief Union type to access the Application Program Status Register (APSR).
robert_lp	0:eedb7d567a5d	232	*/
robert_lp	0:eedb7d567a5d	233	typedef union
robert_lp	0:eedb7d567a5d	234	{
robert_lp	0:eedb7d567a5d	235	struct
robert_lp	0:eedb7d567a5d	236	{
robert_lp	0:eedb7d567a5d	237	uint32_t _reserved0:28; /!< bit: 0..27 Reserved /
robert_lp	0:eedb7d567a5d	238	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
robert_lp	0:eedb7d567a5d	239	uint32_t C:1; /!< bit: 29 Carry condition code flag /
robert_lp	0:eedb7d567a5d	240	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
robert_lp	0:eedb7d567a5d	241	uint32_t N:1; /!< bit: 31 Negative condition code flag /
robert_lp	0:eedb7d567a5d	242	} b; /!< Structure used for bit access /
robert_lp	0:eedb7d567a5d	243	uint32_t w; /!< Type used for word access /
robert_lp	0:eedb7d567a5d	244	} APSR_Type;
robert_lp	0:eedb7d567a5d	245
robert_lp	0:eedb7d567a5d	246	/* APSR Register Definitions */
robert_lp	0:eedb7d567a5d	247	#define APSR_N_Pos 31U /!< APSR: N Position /
robert_lp	0:eedb7d567a5d	248	#define APSR_N_Msk (1UL << APSR_N_Pos) /!< APSR: N Mask /
robert_lp	0:eedb7d567a5d	249
robert_lp	0:eedb7d567a5d	250	#define APSR_Z_Pos 30U /!< APSR: Z Position /
robert_lp	0:eedb7d567a5d	251	#define APSR_Z_Msk (1UL << APSR_Z_Pos) /!< APSR: Z Mask /
robert_lp	0:eedb7d567a5d	252
robert_lp	0:eedb7d567a5d	253	#define APSR_C_Pos 29U /!< APSR: C Position /
robert_lp	0:eedb7d567a5d	254	#define APSR_C_Msk (1UL << APSR_C_Pos) /!< APSR: C Mask /
robert_lp	0:eedb7d567a5d	255
robert_lp	0:eedb7d567a5d	256	#define APSR_V_Pos 28U /!< APSR: V Position /
robert_lp	0:eedb7d567a5d	257	#define APSR_V_Msk (1UL << APSR_V_Pos) /!< APSR: V Mask /
robert_lp	0:eedb7d567a5d	258
robert_lp	0:eedb7d567a5d	259
robert_lp	0:eedb7d567a5d	260	/**
robert_lp	0:eedb7d567a5d	261	\brief Union type to access the Interrupt Program Status Register (IPSR).
robert_lp	0:eedb7d567a5d	262	*/
robert_lp	0:eedb7d567a5d	263	typedef union
robert_lp	0:eedb7d567a5d	264	{
robert_lp	0:eedb7d567a5d	265	struct
robert_lp	0:eedb7d567a5d	266	{
robert_lp	0:eedb7d567a5d	267	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
robert_lp	0:eedb7d567a5d	268	uint32_t _reserved0:23; /!< bit: 9..31 Reserved /
robert_lp	0:eedb7d567a5d	269	} b; /!< Structure used for bit access /
robert_lp	0:eedb7d567a5d	270	uint32_t w; /!< Type used for word access /
robert_lp	0:eedb7d567a5d	271	} IPSR_Type;
robert_lp	0:eedb7d567a5d	272
robert_lp	0:eedb7d567a5d	273	/* IPSR Register Definitions */
robert_lp	0:eedb7d567a5d	274	#define IPSR_ISR_Pos 0U /!< IPSR: ISR Position /
robert_lp	0:eedb7d567a5d	275	#define IPSR_ISR_Msk (0x1FFUL /<< IPSR_ISR_Pos/) /!< IPSR: ISR Mask /
robert_lp	0:eedb7d567a5d	276
robert_lp	0:eedb7d567a5d	277
robert_lp	0:eedb7d567a5d	278	/**
robert_lp	0:eedb7d567a5d	279	\brief Union type to access the Special-Purpose Program Status Registers (xPSR).
robert_lp	0:eedb7d567a5d	280	*/
robert_lp	0:eedb7d567a5d	281	typedef union
robert_lp	0:eedb7d567a5d	282	{
robert_lp	0:eedb7d567a5d	283	struct
robert_lp	0:eedb7d567a5d	284	{
robert_lp	0:eedb7d567a5d	285	uint32_t ISR:9; /!< bit: 0.. 8 Exception number /
robert_lp	0:eedb7d567a5d	286	uint32_t _reserved0:15; /!< bit: 9..23 Reserved /
robert_lp	0:eedb7d567a5d	287	uint32_t T:1; /!< bit: 24 Thumb bit (read 0) /
robert_lp	0:eedb7d567a5d	288	uint32_t _reserved1:3; /!< bit: 25..27 Reserved /
robert_lp	0:eedb7d567a5d	289	uint32_t V:1; /!< bit: 28 Overflow condition code flag /
robert_lp	0:eedb7d567a5d	290	uint32_t C:1; /!< bit: 29 Carry condition code flag /
robert_lp	0:eedb7d567a5d	291	uint32_t Z:1; /!< bit: 30 Zero condition code flag /
robert_lp	0:eedb7d567a5d	292	uint32_t N:1; /!< bit: 31 Negative condition code flag /
robert_lp	0:eedb7d567a5d	293	} b; /!< Structure used for bit access /
robert_lp	0:eedb7d567a5d	294	uint32_t w; /!< Type used for word access /
robert_lp	0:eedb7d567a5d	295	} xPSR_Type;
robert_lp	0:eedb7d567a5d	296
robert_lp	0:eedb7d567a5d	297	/* xPSR Register Definitions */
robert_lp	0:eedb7d567a5d	298	#define xPSR_N_Pos 31U /!< xPSR: N Position /
robert_lp	0:eedb7d567a5d	299	#define xPSR_N_Msk (1UL << xPSR_N_Pos) /!< xPSR: N Mask /
robert_lp	0:eedb7d567a5d	300
robert_lp	0:eedb7d567a5d	301	#define xPSR_Z_Pos 30U /!< xPSR: Z Position /
robert_lp	0:eedb7d567a5d	302	#define xPSR_Z_Msk (1UL << xPSR_Z_Pos) /!< xPSR: Z Mask /
robert_lp	0:eedb7d567a5d	303
robert_lp	0:eedb7d567a5d	304	#define xPSR_C_Pos 29U /!< xPSR: C Position /
robert_lp	0:eedb7d567a5d	305	#define xPSR_C_Msk (1UL << xPSR_C_Pos) /!< xPSR: C Mask /
robert_lp	0:eedb7d567a5d	306
robert_lp	0:eedb7d567a5d	307	#define xPSR_V_Pos 28U /!< xPSR: V Position /
robert_lp	0:eedb7d567a5d	308	#define xPSR_V_Msk (1UL << xPSR_V_Pos) /!< xPSR: V Mask /
robert_lp	0:eedb7d567a5d	309
robert_lp	0:eedb7d567a5d	310	#define xPSR_T_Pos 24U /!< xPSR: T Position /
robert_lp	0:eedb7d567a5d	311	#define xPSR_T_Msk (1UL << xPSR_T_Pos) /!< xPSR: T Mask /
robert_lp	0:eedb7d567a5d	312
robert_lp	0:eedb7d567a5d	313	#define xPSR_ISR_Pos 0U /!< xPSR: ISR Position /
robert_lp	0:eedb7d567a5d	314	#define xPSR_ISR_Msk (0x1FFUL /<< xPSR_ISR_Pos/) /!< xPSR: ISR Mask /
robert_lp	0:eedb7d567a5d	315
robert_lp	0:eedb7d567a5d	316
robert_lp	0:eedb7d567a5d	317	/**
robert_lp	0:eedb7d567a5d	318	\brief Union type to access the Control Registers (CONTROL).
robert_lp	0:eedb7d567a5d	319	*/
robert_lp	0:eedb7d567a5d	320	typedef union
robert_lp	0:eedb7d567a5d	321	{
robert_lp	0:eedb7d567a5d	322	struct
robert_lp	0:eedb7d567a5d	323	{
robert_lp	0:eedb7d567a5d	324	uint32_t nPRIV:1; /!< bit: 0 Execution privilege in Thread mode /
robert_lp	0:eedb7d567a5d	325	uint32_t SPSEL:1; /!< bit: 1 Stack-pointer select /
robert_lp	0:eedb7d567a5d	326	uint32_t _reserved1:30; /!< bit: 2..31 Reserved /
robert_lp	0:eedb7d567a5d	327	} b; /!< Structure used for bit access /
robert_lp	0:eedb7d567a5d	328	uint32_t w; /!< Type used for word access /
robert_lp	0:eedb7d567a5d	329	} CONTROL_Type;
robert_lp	0:eedb7d567a5d	330
robert_lp	0:eedb7d567a5d	331	/* CONTROL Register Definitions */
robert_lp	0:eedb7d567a5d	332	#define CONTROL_SPSEL_Pos 1U /!< CONTROL: SPSEL Position /
robert_lp	0:eedb7d567a5d	333	#define CONTROL_SPSEL_Msk (1UL << CONTROL_SPSEL_Pos) /!< CONTROL: SPSEL Mask /
robert_lp	0:eedb7d567a5d	334
robert_lp	0:eedb7d567a5d	335	#define CONTROL_nPRIV_Pos 0U /!< CONTROL: nPRIV Position /
robert_lp	0:eedb7d567a5d	336	#define CONTROL_nPRIV_Msk (1UL /<< CONTROL_nPRIV_Pos/) /!< CONTROL: nPRIV Mask /
robert_lp	0:eedb7d567a5d	337
robert_lp	0:eedb7d567a5d	338	/@} end of group CMSIS_CORE /
robert_lp	0:eedb7d567a5d	339
robert_lp	0:eedb7d567a5d	340
robert_lp	0:eedb7d567a5d	341	/**
robert_lp	0:eedb7d567a5d	342	\ingroup CMSIS_core_register
robert_lp	0:eedb7d567a5d	343	\defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
robert_lp	0:eedb7d567a5d	344	\brief Type definitions for the NVIC Registers
robert_lp	0:eedb7d567a5d	345	@{
robert_lp	0:eedb7d567a5d	346	*/
robert_lp	0:eedb7d567a5d	347
robert_lp	0:eedb7d567a5d	348	/**
robert_lp	0:eedb7d567a5d	349	\brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
robert_lp	0:eedb7d567a5d	350	*/
robert_lp	0:eedb7d567a5d	351	typedef struct
robert_lp	0:eedb7d567a5d	352	{
robert_lp	0:eedb7d567a5d	353	__IOM uint32_t ISER[16U]; /!< Offset: 0x000 (R/W) Interrupt Set Enable Register /
robert_lp	0:eedb7d567a5d	354	uint32_t RESERVED0[16U];
robert_lp	0:eedb7d567a5d	355	__IOM uint32_t ICER[16U]; /!< Offset: 0x080 (R/W) Interrupt Clear Enable Register /
robert_lp	0:eedb7d567a5d	356	uint32_t RSERVED1[16U];
robert_lp	0:eedb7d567a5d	357	__IOM uint32_t ISPR[16U]; /!< Offset: 0x100 (R/W) Interrupt Set Pending Register /
robert_lp	0:eedb7d567a5d	358	uint32_t RESERVED2[16U];
robert_lp	0:eedb7d567a5d	359	__IOM uint32_t ICPR[16U]; /!< Offset: 0x180 (R/W) Interrupt Clear Pending Register /
robert_lp	0:eedb7d567a5d	360	uint32_t RESERVED3[16U];
robert_lp	0:eedb7d567a5d	361	__IOM uint32_t IABR[16U]; /!< Offset: 0x200 (R/W) Interrupt Active bit Register /
robert_lp	0:eedb7d567a5d	362	uint32_t RESERVED4[16U];
robert_lp	0:eedb7d567a5d	363	__IOM uint32_t ITNS[16U]; /!< Offset: 0x280 (R/W) Interrupt Non-Secure State Register /
robert_lp	0:eedb7d567a5d	364	uint32_t RESERVED5[16U];
robert_lp	0:eedb7d567a5d	365	__IOM uint32_t IPR[124U]; /!< Offset: 0x300 (R/W) Interrupt Priority Register /
robert_lp	0:eedb7d567a5d	366	} NVIC_Type;
robert_lp	0:eedb7d567a5d	367
robert_lp	0:eedb7d567a5d	368	/@} end of group CMSIS_NVIC /
robert_lp	0:eedb7d567a5d	369
robert_lp	0:eedb7d567a5d	370
robert_lp	0:eedb7d567a5d	371	/**
robert_lp	0:eedb7d567a5d	372	\ingroup CMSIS_core_register
robert_lp	0:eedb7d567a5d	373	\defgroup CMSIS_SCB System Control Block (SCB)
robert_lp	0:eedb7d567a5d	374	\brief Type definitions for the System Control Block Registers
robert_lp	0:eedb7d567a5d	375	@{
robert_lp	0:eedb7d567a5d	376	*/
robert_lp	0:eedb7d567a5d	377
robert_lp	0:eedb7d567a5d	378	/**
robert_lp	0:eedb7d567a5d	379	\brief Structure type to access the System Control Block (SCB).
robert_lp	0:eedb7d567a5d	380	*/
robert_lp	0:eedb7d567a5d	381	typedef struct
robert_lp	0:eedb7d567a5d	382	{
robert_lp	0:eedb7d567a5d	383	__IM uint32_t CPUID; /!< Offset: 0x000 (R/ ) CPUID Base Register /
robert_lp	0:eedb7d567a5d	384	__IOM uint32_t ICSR; /!< Offset: 0x004 (R/W) Interrupt Control and State Register /
robert_lp	0:eedb7d567a5d	385	#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
robert_lp	0:eedb7d567a5d	386	__IOM uint32_t VTOR; /!< Offset: 0x008 (R/W) Vector Table Offset Register /
robert_lp	0:eedb7d567a5d	387	#else
robert_lp	0:eedb7d567a5d	388	uint32_t RESERVED0;
robert_lp	0:eedb7d567a5d	389	#endif
robert_lp	0:eedb7d567a5d	390	__IOM uint32_t AIRCR; /!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register /
robert_lp	0:eedb7d567a5d	391	__IOM uint32_t SCR; /!< Offset: 0x010 (R/W) System Control Register /
robert_lp	0:eedb7d567a5d	392	__IOM uint32_t CCR; /!< Offset: 0x014 (R/W) Configuration Control Register /
robert_lp	0:eedb7d567a5d	393	uint32_t RESERVED1;
robert_lp	0:eedb7d567a5d	394	__IOM uint32_t SHPR[2U]; /!< Offset: 0x01C (R/W) System Handlers Priority Registers. [0] is RESERVED /
robert_lp	0:eedb7d567a5d	395	__IOM uint32_t SHCSR; /!< Offset: 0x024 (R/W) System Handler Control and State Register /
robert_lp	0:eedb7d567a5d	396	} SCB_Type;
robert_lp	0:eedb7d567a5d	397
robert_lp	0:eedb7d567a5d	398	/* SCB CPUID Register Definitions */
robert_lp	0:eedb7d567a5d	399	#define SCB_CPUID_IMPLEMENTER_Pos 24U /!< SCB CPUID: IMPLEMENTER Position /
robert_lp	0:eedb7d567a5d	400	#define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /!< SCB CPUID: IMPLEMENTER Mask /
robert_lp	0:eedb7d567a5d	401
robert_lp	0:eedb7d567a5d	402	#define SCB_CPUID_VARIANT_Pos 20U /!< SCB CPUID: VARIANT Position /
robert_lp	0:eedb7d567a5d	403	#define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /!< SCB CPUID: VARIANT Mask /
robert_lp	0:eedb7d567a5d	404
robert_lp	0:eedb7d567a5d	405	#define SCB_CPUID_ARCHITECTURE_Pos 16U /!< SCB CPUID: ARCHITECTURE Position /
robert_lp	0:eedb7d567a5d	406	#define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /!< SCB CPUID: ARCHITECTURE Mask /
robert_lp	0:eedb7d567a5d	407
robert_lp	0:eedb7d567a5d	408	#define SCB_CPUID_PARTNO_Pos 4U /!< SCB CPUID: PARTNO Position /
robert_lp	0:eedb7d567a5d	409	#define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /!< SCB CPUID: PARTNO Mask /
robert_lp	0:eedb7d567a5d	410
robert_lp	0:eedb7d567a5d	411	#define SCB_CPUID_REVISION_Pos 0U /!< SCB CPUID: REVISION Position /
robert_lp	0:eedb7d567a5d	412	#define SCB_CPUID_REVISION_Msk (0xFUL /<< SCB_CPUID_REVISION_Pos/) /!< SCB CPUID: REVISION Mask /
robert_lp	0:eedb7d567a5d	413
robert_lp	0:eedb7d567a5d	414	/* SCB Interrupt Control State Register Definitions */
robert_lp	0:eedb7d567a5d	415	#define SCB_ICSR_PENDNMISET_Pos 31U /!< SCB ICSR: PENDNMISET Position /
robert_lp	0:eedb7d567a5d	416	#define SCB_ICSR_PENDNMISET_Msk (1UL << SCB_ICSR_PENDNMISET_Pos) /!< SCB ICSR: PENDNMISET Mask /
robert_lp	0:eedb7d567a5d	417
robert_lp	0:eedb7d567a5d	418	#define SCB_ICSR_PENDNMICLR_Pos 30U /!< SCB ICSR: PENDNMICLR Position /
robert_lp	0:eedb7d567a5d	419	#define SCB_ICSR_PENDNMICLR_Msk (1UL << SCB_ICSR_PENDNMICLR_Pos) /!< SCB ICSR: PENDNMICLR Mask /
robert_lp	0:eedb7d567a5d	420
robert_lp	0:eedb7d567a5d	421	#define SCB_ICSR_PENDSVSET_Pos 28U /!< SCB ICSR: PENDSVSET Position /
robert_lp	0:eedb7d567a5d	422	#define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /!< SCB ICSR: PENDSVSET Mask /
robert_lp	0:eedb7d567a5d	423
robert_lp	0:eedb7d567a5d	424	#define SCB_ICSR_PENDSVCLR_Pos 27U /!< SCB ICSR: PENDSVCLR Position /
robert_lp	0:eedb7d567a5d	425	#define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /!< SCB ICSR: PENDSVCLR Mask /
robert_lp	0:eedb7d567a5d	426
robert_lp	0:eedb7d567a5d	427	#define SCB_ICSR_PENDSTSET_Pos 26U /!< SCB ICSR: PENDSTSET Position /
robert_lp	0:eedb7d567a5d	428	#define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /!< SCB ICSR: PENDSTSET Mask /
robert_lp	0:eedb7d567a5d	429
robert_lp	0:eedb7d567a5d	430	#define SCB_ICSR_PENDSTCLR_Pos 25U /!< SCB ICSR: PENDSTCLR Position /
robert_lp	0:eedb7d567a5d	431	#define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /!< SCB ICSR: PENDSTCLR Mask /
robert_lp	0:eedb7d567a5d	432
robert_lp	0:eedb7d567a5d	433	#define SCB_ICSR_STTNS_Pos 24U /!< SCB ICSR: STTNS Position (Security Extension) /
robert_lp	0:eedb7d567a5d	434	#define SCB_ICSR_STTNS_Msk (1UL << SCB_ICSR_STTNS_Pos) /!< SCB ICSR: STTNS Mask (Security Extension) /
robert_lp	0:eedb7d567a5d	435
robert_lp	0:eedb7d567a5d	436	#define SCB_ICSR_ISRPREEMPT_Pos 23U /!< SCB ICSR: ISRPREEMPT Position /
robert_lp	0:eedb7d567a5d	437	#define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /!< SCB ICSR: ISRPREEMPT Mask /
robert_lp	0:eedb7d567a5d	438
robert_lp	0:eedb7d567a5d	439	#define SCB_ICSR_ISRPENDING_Pos 22U /!< SCB ICSR: ISRPENDING Position /
robert_lp	0:eedb7d567a5d	440	#define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /!< SCB ICSR: ISRPENDING Mask /
robert_lp	0:eedb7d567a5d	441
robert_lp	0:eedb7d567a5d	442	#define SCB_ICSR_VECTPENDING_Pos 12U /!< SCB ICSR: VECTPENDING Position /
robert_lp	0:eedb7d567a5d	443	#define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /!< SCB ICSR: VECTPENDING Mask /
robert_lp	0:eedb7d567a5d	444
robert_lp	0:eedb7d567a5d	445	#define SCB_ICSR_RETTOBASE_Pos 11U /!< SCB ICSR: RETTOBASE Position /
robert_lp	0:eedb7d567a5d	446	#define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /!< SCB ICSR: RETTOBASE Mask /
robert_lp	0:eedb7d567a5d	447
robert_lp	0:eedb7d567a5d	448	#define SCB_ICSR_VECTACTIVE_Pos 0U /!< SCB ICSR: VECTACTIVE Position /
robert_lp	0:eedb7d567a5d	449	#define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL /<< SCB_ICSR_VECTACTIVE_Pos/) /!< SCB ICSR: VECTACTIVE Mask /
robert_lp	0:eedb7d567a5d	450
robert_lp	0:eedb7d567a5d	451	#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
robert_lp	0:eedb7d567a5d	452	/* SCB Vector Table Offset Register Definitions */
robert_lp	0:eedb7d567a5d	453	#define SCB_VTOR_TBLOFF_Pos 7U /!< SCB VTOR: TBLOFF Position /
robert_lp	0:eedb7d567a5d	454	#define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /!< SCB VTOR: TBLOFF Mask /
robert_lp	0:eedb7d567a5d	455	#endif
robert_lp	0:eedb7d567a5d	456
robert_lp	0:eedb7d567a5d	457	/* SCB Application Interrupt and Reset Control Register Definitions */
robert_lp	0:eedb7d567a5d	458	#define SCB_AIRCR_VECTKEY_Pos 16U /!< SCB AIRCR: VECTKEY Position /
robert_lp	0:eedb7d567a5d	459	#define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /!< SCB AIRCR: VECTKEY Mask /
robert_lp	0:eedb7d567a5d	460
robert_lp	0:eedb7d567a5d	461	#define SCB_AIRCR_VECTKEYSTAT_Pos 16U /!< SCB AIRCR: VECTKEYSTAT Position /
robert_lp	0:eedb7d567a5d	462	#define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /!< SCB AIRCR: VECTKEYSTAT Mask /
robert_lp	0:eedb7d567a5d	463
robert_lp	0:eedb7d567a5d	464	#define SCB_AIRCR_ENDIANESS_Pos 15U /!< SCB AIRCR: ENDIANESS Position /
robert_lp	0:eedb7d567a5d	465	#define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /!< SCB AIRCR: ENDIANESS Mask /
robert_lp	0:eedb7d567a5d	466
robert_lp	0:eedb7d567a5d	467	#define SCB_AIRCR_PRIS_Pos 14U /!< SCB AIRCR: PRIS Position /
robert_lp	0:eedb7d567a5d	468	#define SCB_AIRCR_PRIS_Msk (1UL << SCB_AIRCR_PRIS_Pos) /!< SCB AIRCR: PRIS Mask /
robert_lp	0:eedb7d567a5d	469
robert_lp	0:eedb7d567a5d	470	#define SCB_AIRCR_BFHFNMINS_Pos 13U /!< SCB AIRCR: BFHFNMINS Position /
robert_lp	0:eedb7d567a5d	471	#define SCB_AIRCR_BFHFNMINS_Msk (1UL << SCB_AIRCR_BFHFNMINS_Pos) /!< SCB AIRCR: BFHFNMINS Mask /
robert_lp	0:eedb7d567a5d	472
robert_lp	0:eedb7d567a5d	473	#define SCB_AIRCR_SYSRESETREQS_Pos 3U /!< SCB AIRCR: SYSRESETREQS Position /
robert_lp	0:eedb7d567a5d	474	#define SCB_AIRCR_SYSRESETREQS_Msk (1UL << SCB_AIRCR_SYSRESETREQS_Pos) /!< SCB AIRCR: SYSRESETREQS Mask /
robert_lp	0:eedb7d567a5d	475
robert_lp	0:eedb7d567a5d	476	#define SCB_AIRCR_SYSRESETREQ_Pos 2U /!< SCB AIRCR: SYSRESETREQ Position /
robert_lp	0:eedb7d567a5d	477	#define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /!< SCB AIRCR: SYSRESETREQ Mask /
robert_lp	0:eedb7d567a5d	478
robert_lp	0:eedb7d567a5d	479	#define SCB_AIRCR_VECTCLRACTIVE_Pos 1U /!< SCB AIRCR: VECTCLRACTIVE Position /
robert_lp	0:eedb7d567a5d	480	#define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /!< SCB AIRCR: VECTCLRACTIVE Mask /
robert_lp	0:eedb7d567a5d	481
robert_lp	0:eedb7d567a5d	482	/* SCB System Control Register Definitions */
robert_lp	0:eedb7d567a5d	483	#define SCB_SCR_SEVONPEND_Pos 4U /!< SCB SCR: SEVONPEND Position /
robert_lp	0:eedb7d567a5d	484	#define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /!< SCB SCR: SEVONPEND Mask /
robert_lp	0:eedb7d567a5d	485
robert_lp	0:eedb7d567a5d	486	#define SCB_SCR_SLEEPDEEPS_Pos 3U /!< SCB SCR: SLEEPDEEPS Position /
robert_lp	0:eedb7d567a5d	487	#define SCB_SCR_SLEEPDEEPS_Msk (1UL << SCB_SCR_SLEEPDEEPS_Pos) /!< SCB SCR: SLEEPDEEPS Mask /
robert_lp	0:eedb7d567a5d	488
robert_lp	0:eedb7d567a5d	489	#define SCB_SCR_SLEEPDEEP_Pos 2U /!< SCB SCR: SLEEPDEEP Position /
robert_lp	0:eedb7d567a5d	490	#define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /!< SCB SCR: SLEEPDEEP Mask /
robert_lp	0:eedb7d567a5d	491
robert_lp	0:eedb7d567a5d	492	#define SCB_SCR_SLEEPONEXIT_Pos 1U /!< SCB SCR: SLEEPONEXIT Position /
robert_lp	0:eedb7d567a5d	493	#define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /!< SCB SCR: SLEEPONEXIT Mask /
robert_lp	0:eedb7d567a5d	494
robert_lp	0:eedb7d567a5d	495	/* SCB Configuration Control Register Definitions */
robert_lp	0:eedb7d567a5d	496	#define SCB_CCR_BP_Pos 18U /!< SCB CCR: BP Position /
robert_lp	0:eedb7d567a5d	497	#define SCB_CCR_BP_Msk (1UL << SCB_CCR_BP_Pos) /!< SCB CCR: BP Mask /
robert_lp	0:eedb7d567a5d	498
robert_lp	0:eedb7d567a5d	499	#define SCB_CCR_IC_Pos 17U /!< SCB CCR: IC Position /
robert_lp	0:eedb7d567a5d	500	#define SCB_CCR_IC_Msk (1UL << SCB_CCR_IC_Pos) /!< SCB CCR: IC Mask /
robert_lp	0:eedb7d567a5d	501
robert_lp	0:eedb7d567a5d	502	#define SCB_CCR_DC_Pos 16U /!< SCB CCR: DC Position /
robert_lp	0:eedb7d567a5d	503	#define SCB_CCR_DC_Msk (1UL << SCB_CCR_DC_Pos) /!< SCB CCR: DC Mask /
robert_lp	0:eedb7d567a5d	504
robert_lp	0:eedb7d567a5d	505	#define SCB_CCR_STKOFHFNMIGN_Pos 10U /!< SCB CCR: STKOFHFNMIGN Position /
robert_lp	0:eedb7d567a5d	506	#define SCB_CCR_STKOFHFNMIGN_Msk (1UL << SCB_CCR_STKOFHFNMIGN_Pos) /!< SCB CCR: STKOFHFNMIGN Mask /
robert_lp	0:eedb7d567a5d	507
robert_lp	0:eedb7d567a5d	508	#define SCB_CCR_BFHFNMIGN_Pos 8U /!< SCB CCR: BFHFNMIGN Position /
robert_lp	0:eedb7d567a5d	509	#define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /!< SCB CCR: BFHFNMIGN Mask /
robert_lp	0:eedb7d567a5d	510
robert_lp	0:eedb7d567a5d	511	#define SCB_CCR_DIV_0_TRP_Pos 4U /!< SCB CCR: DIV_0_TRP Position /
robert_lp	0:eedb7d567a5d	512	#define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /!< SCB CCR: DIV_0_TRP Mask /
robert_lp	0:eedb7d567a5d	513
robert_lp	0:eedb7d567a5d	514	#define SCB_CCR_UNALIGN_TRP_Pos 3U /!< SCB CCR: UNALIGN_TRP Position /
robert_lp	0:eedb7d567a5d	515	#define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /!< SCB CCR: UNALIGN_TRP Mask /
robert_lp	0:eedb7d567a5d	516
robert_lp	0:eedb7d567a5d	517	#define SCB_CCR_USERSETMPEND_Pos 1U /!< SCB CCR: USERSETMPEND Position /
robert_lp	0:eedb7d567a5d	518	#define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /!< SCB CCR: USERSETMPEND Mask /
robert_lp	0:eedb7d567a5d	519
robert_lp	0:eedb7d567a5d	520	/* SCB System Handler Control and State Register Definitions */
robert_lp	0:eedb7d567a5d	521	#define SCB_SHCSR_HARDFAULTPENDED_Pos 21U /!< SCB SHCSR: HARDFAULTPENDED Position /
robert_lp	0:eedb7d567a5d	522	#define SCB_SHCSR_HARDFAULTPENDED_Msk (1UL << SCB_SHCSR_HARDFAULTPENDED_Pos) /!< SCB SHCSR: HARDFAULTPENDED Mask /
robert_lp	0:eedb7d567a5d	523
robert_lp	0:eedb7d567a5d	524	#define SCB_SHCSR_SVCALLPENDED_Pos 15U /!< SCB SHCSR: SVCALLPENDED Position /
robert_lp	0:eedb7d567a5d	525	#define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /!< SCB SHCSR: SVCALLPENDED Mask /
robert_lp	0:eedb7d567a5d	526
robert_lp	0:eedb7d567a5d	527	#define SCB_SHCSR_SYSTICKACT_Pos 11U /!< SCB SHCSR: SYSTICKACT Position /
robert_lp	0:eedb7d567a5d	528	#define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /!< SCB SHCSR: SYSTICKACT Mask /
robert_lp	0:eedb7d567a5d	529
robert_lp	0:eedb7d567a5d	530	#define SCB_SHCSR_PENDSVACT_Pos 10U /!< SCB SHCSR: PENDSVACT Position /
robert_lp	0:eedb7d567a5d	531	#define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /!< SCB SHCSR: PENDSVACT Mask /
robert_lp	0:eedb7d567a5d	532
robert_lp	0:eedb7d567a5d	533	#define SCB_SHCSR_SVCALLACT_Pos 7U /!< SCB SHCSR: SVCALLACT Position /
robert_lp	0:eedb7d567a5d	534	#define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /!< SCB SHCSR: SVCALLACT Mask /
robert_lp	0:eedb7d567a5d	535
robert_lp	0:eedb7d567a5d	536	#define SCB_SHCSR_NMIACT_Pos 5U /!< SCB SHCSR: NMIACT Position /
robert_lp	0:eedb7d567a5d	537	#define SCB_SHCSR_NMIACT_Msk (1UL << SCB_SHCSR_NMIACT_Pos) /!< SCB SHCSR: NMIACT Mask /
robert_lp	0:eedb7d567a5d	538
robert_lp	0:eedb7d567a5d	539	#define SCB_SHCSR_HARDFAULTACT_Pos 2U /!< SCB SHCSR: HARDFAULTACT Position /
robert_lp	0:eedb7d567a5d	540	#define SCB_SHCSR_HARDFAULTACT_Msk (1UL << SCB_SHCSR_HARDFAULTACT_Pos) /!< SCB SHCSR: HARDFAULTACT Mask /
robert_lp	0:eedb7d567a5d	541
robert_lp	0:eedb7d567a5d	542	/@} end of group CMSIS_SCB /
robert_lp	0:eedb7d567a5d	543
robert_lp	0:eedb7d567a5d	544
robert_lp	0:eedb7d567a5d	545	/**
robert_lp	0:eedb7d567a5d	546	\ingroup CMSIS_core_register
robert_lp	0:eedb7d567a5d	547	\defgroup CMSIS_SysTick System Tick Timer (SysTick)
robert_lp	0:eedb7d567a5d	548	\brief Type definitions for the System Timer Registers.
robert_lp	0:eedb7d567a5d	549	@{
robert_lp	0:eedb7d567a5d	550	*/
robert_lp	0:eedb7d567a5d	551
robert_lp	0:eedb7d567a5d	552	/**
robert_lp	0:eedb7d567a5d	553	\brief Structure type to access the System Timer (SysTick).
robert_lp	0:eedb7d567a5d	554	*/
robert_lp	0:eedb7d567a5d	555	typedef struct
robert_lp	0:eedb7d567a5d	556	{
robert_lp	0:eedb7d567a5d	557	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SysTick Control and Status Register /
robert_lp	0:eedb7d567a5d	558	__IOM uint32_t LOAD; /!< Offset: 0x004 (R/W) SysTick Reload Value Register /
robert_lp	0:eedb7d567a5d	559	__IOM uint32_t VAL; /!< Offset: 0x008 (R/W) SysTick Current Value Register /
robert_lp	0:eedb7d567a5d	560	__IM uint32_t CALIB; /!< Offset: 0x00C (R/ ) SysTick Calibration Register /
robert_lp	0:eedb7d567a5d	561	} SysTick_Type;
robert_lp	0:eedb7d567a5d	562
robert_lp	0:eedb7d567a5d	563	/* SysTick Control / Status Register Definitions */
robert_lp	0:eedb7d567a5d	564	#define SysTick_CTRL_COUNTFLAG_Pos 16U /!< SysTick CTRL: COUNTFLAG Position /
robert_lp	0:eedb7d567a5d	565	#define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /!< SysTick CTRL: COUNTFLAG Mask /
robert_lp	0:eedb7d567a5d	566
robert_lp	0:eedb7d567a5d	567	#define SysTick_CTRL_CLKSOURCE_Pos 2U /!< SysTick CTRL: CLKSOURCE Position /
robert_lp	0:eedb7d567a5d	568	#define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /!< SysTick CTRL: CLKSOURCE Mask /
robert_lp	0:eedb7d567a5d	569
robert_lp	0:eedb7d567a5d	570	#define SysTick_CTRL_TICKINT_Pos 1U /!< SysTick CTRL: TICKINT Position /
robert_lp	0:eedb7d567a5d	571	#define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /!< SysTick CTRL: TICKINT Mask /
robert_lp	0:eedb7d567a5d	572
robert_lp	0:eedb7d567a5d	573	#define SysTick_CTRL_ENABLE_Pos 0U /!< SysTick CTRL: ENABLE Position /
robert_lp	0:eedb7d567a5d	574	#define SysTick_CTRL_ENABLE_Msk (1UL /<< SysTick_CTRL_ENABLE_Pos/) /!< SysTick CTRL: ENABLE Mask /
robert_lp	0:eedb7d567a5d	575
robert_lp	0:eedb7d567a5d	576	/* SysTick Reload Register Definitions */
robert_lp	0:eedb7d567a5d	577	#define SysTick_LOAD_RELOAD_Pos 0U /!< SysTick LOAD: RELOAD Position /
robert_lp	0:eedb7d567a5d	578	#define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL /<< SysTick_LOAD_RELOAD_Pos/) /!< SysTick LOAD: RELOAD Mask /
robert_lp	0:eedb7d567a5d	579
robert_lp	0:eedb7d567a5d	580	/* SysTick Current Register Definitions */
robert_lp	0:eedb7d567a5d	581	#define SysTick_VAL_CURRENT_Pos 0U /!< SysTick VAL: CURRENT Position /
robert_lp	0:eedb7d567a5d	582	#define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL /<< SysTick_VAL_CURRENT_Pos/) /!< SysTick VAL: CURRENT Mask /
robert_lp	0:eedb7d567a5d	583
robert_lp	0:eedb7d567a5d	584	/* SysTick Calibration Register Definitions */
robert_lp	0:eedb7d567a5d	585	#define SysTick_CALIB_NOREF_Pos 31U /!< SysTick CALIB: NOREF Position /
robert_lp	0:eedb7d567a5d	586	#define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /!< SysTick CALIB: NOREF Mask /
robert_lp	0:eedb7d567a5d	587
robert_lp	0:eedb7d567a5d	588	#define SysTick_CALIB_SKEW_Pos 30U /!< SysTick CALIB: SKEW Position /
robert_lp	0:eedb7d567a5d	589	#define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /!< SysTick CALIB: SKEW Mask /
robert_lp	0:eedb7d567a5d	590
robert_lp	0:eedb7d567a5d	591	#define SysTick_CALIB_TENMS_Pos 0U /!< SysTick CALIB: TENMS Position /
robert_lp	0:eedb7d567a5d	592	#define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL /<< SysTick_CALIB_TENMS_Pos/) /!< SysTick CALIB: TENMS Mask /
robert_lp	0:eedb7d567a5d	593
robert_lp	0:eedb7d567a5d	594	/@} end of group CMSIS_SysTick /
robert_lp	0:eedb7d567a5d	595
robert_lp	0:eedb7d567a5d	596
robert_lp	0:eedb7d567a5d	597	/**
robert_lp	0:eedb7d567a5d	598	\ingroup CMSIS_core_register
robert_lp	0:eedb7d567a5d	599	\defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
robert_lp	0:eedb7d567a5d	600	\brief Type definitions for the Data Watchpoint and Trace (DWT)
robert_lp	0:eedb7d567a5d	601	@{
robert_lp	0:eedb7d567a5d	602	*/
robert_lp	0:eedb7d567a5d	603
robert_lp	0:eedb7d567a5d	604	/**
robert_lp	0:eedb7d567a5d	605	\brief Structure type to access the Data Watchpoint and Trace Register (DWT).
robert_lp	0:eedb7d567a5d	606	*/
robert_lp	0:eedb7d567a5d	607	typedef struct
robert_lp	0:eedb7d567a5d	608	{
robert_lp	0:eedb7d567a5d	609	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) Control Register /
robert_lp	0:eedb7d567a5d	610	uint32_t RESERVED0[6U];
robert_lp	0:eedb7d567a5d	611	__IM uint32_t PCSR; /!< Offset: 0x01C (R/ ) Program Counter Sample Register /
robert_lp	0:eedb7d567a5d	612	__IOM uint32_t COMP0; /!< Offset: 0x020 (R/W) Comparator Register 0 /
robert_lp	0:eedb7d567a5d	613	uint32_t RESERVED1[1U];
robert_lp	0:eedb7d567a5d	614	__IOM uint32_t FUNCTION0; /!< Offset: 0x028 (R/W) Function Register 0 /
robert_lp	0:eedb7d567a5d	615	uint32_t RESERVED2[1U];
robert_lp	0:eedb7d567a5d	616	__IOM uint32_t COMP1; /!< Offset: 0x030 (R/W) Comparator Register 1 /
robert_lp	0:eedb7d567a5d	617	uint32_t RESERVED3[1U];
robert_lp	0:eedb7d567a5d	618	__IOM uint32_t FUNCTION1; /!< Offset: 0x038 (R/W) Function Register 1 /
robert_lp	0:eedb7d567a5d	619	uint32_t RESERVED4[1U];
robert_lp	0:eedb7d567a5d	620	__IOM uint32_t COMP2; /!< Offset: 0x040 (R/W) Comparator Register 2 /
robert_lp	0:eedb7d567a5d	621	uint32_t RESERVED5[1U];
robert_lp	0:eedb7d567a5d	622	__IOM uint32_t FUNCTION2; /!< Offset: 0x048 (R/W) Function Register 2 /
robert_lp	0:eedb7d567a5d	623	uint32_t RESERVED6[1U];
robert_lp	0:eedb7d567a5d	624	__IOM uint32_t COMP3; /!< Offset: 0x050 (R/W) Comparator Register 3 /
robert_lp	0:eedb7d567a5d	625	uint32_t RESERVED7[1U];
robert_lp	0:eedb7d567a5d	626	__IOM uint32_t FUNCTION3; /!< Offset: 0x058 (R/W) Function Register 3 /
robert_lp	0:eedb7d567a5d	627	uint32_t RESERVED8[1U];
robert_lp	0:eedb7d567a5d	628	__IOM uint32_t COMP4; /!< Offset: 0x060 (R/W) Comparator Register 4 /
robert_lp	0:eedb7d567a5d	629	uint32_t RESERVED9[1U];
robert_lp	0:eedb7d567a5d	630	__IOM uint32_t FUNCTION4; /!< Offset: 0x068 (R/W) Function Register 4 /
robert_lp	0:eedb7d567a5d	631	uint32_t RESERVED10[1U];
robert_lp	0:eedb7d567a5d	632	__IOM uint32_t COMP5; /!< Offset: 0x070 (R/W) Comparator Register 5 /
robert_lp	0:eedb7d567a5d	633	uint32_t RESERVED11[1U];
robert_lp	0:eedb7d567a5d	634	__IOM uint32_t FUNCTION5; /!< Offset: 0x078 (R/W) Function Register 5 /
robert_lp	0:eedb7d567a5d	635	uint32_t RESERVED12[1U];
robert_lp	0:eedb7d567a5d	636	__IOM uint32_t COMP6; /!< Offset: 0x080 (R/W) Comparator Register 6 /
robert_lp	0:eedb7d567a5d	637	uint32_t RESERVED13[1U];
robert_lp	0:eedb7d567a5d	638	__IOM uint32_t FUNCTION6; /!< Offset: 0x088 (R/W) Function Register 6 /
robert_lp	0:eedb7d567a5d	639	uint32_t RESERVED14[1U];
robert_lp	0:eedb7d567a5d	640	__IOM uint32_t COMP7; /!< Offset: 0x090 (R/W) Comparator Register 7 /
robert_lp	0:eedb7d567a5d	641	uint32_t RESERVED15[1U];
robert_lp	0:eedb7d567a5d	642	__IOM uint32_t FUNCTION7; /!< Offset: 0x098 (R/W) Function Register 7 /
robert_lp	0:eedb7d567a5d	643	uint32_t RESERVED16[1U];
robert_lp	0:eedb7d567a5d	644	__IOM uint32_t COMP8; /!< Offset: 0x0A0 (R/W) Comparator Register 8 /
robert_lp	0:eedb7d567a5d	645	uint32_t RESERVED17[1U];
robert_lp	0:eedb7d567a5d	646	__IOM uint32_t FUNCTION8; /!< Offset: 0x0A8 (R/W) Function Register 8 /
robert_lp	0:eedb7d567a5d	647	uint32_t RESERVED18[1U];
robert_lp	0:eedb7d567a5d	648	__IOM uint32_t COMP9; /!< Offset: 0x0B0 (R/W) Comparator Register 9 /
robert_lp	0:eedb7d567a5d	649	uint32_t RESERVED19[1U];
robert_lp	0:eedb7d567a5d	650	__IOM uint32_t FUNCTION9; /!< Offset: 0x0B8 (R/W) Function Register 9 /
robert_lp	0:eedb7d567a5d	651	uint32_t RESERVED20[1U];
robert_lp	0:eedb7d567a5d	652	__IOM uint32_t COMP10; /!< Offset: 0x0C0 (R/W) Comparator Register 10 /
robert_lp	0:eedb7d567a5d	653	uint32_t RESERVED21[1U];
robert_lp	0:eedb7d567a5d	654	__IOM uint32_t FUNCTION10; /!< Offset: 0x0C8 (R/W) Function Register 10 /
robert_lp	0:eedb7d567a5d	655	uint32_t RESERVED22[1U];
robert_lp	0:eedb7d567a5d	656	__IOM uint32_t COMP11; /!< Offset: 0x0D0 (R/W) Comparator Register 11 /
robert_lp	0:eedb7d567a5d	657	uint32_t RESERVED23[1U];
robert_lp	0:eedb7d567a5d	658	__IOM uint32_t FUNCTION11; /!< Offset: 0x0D8 (R/W) Function Register 11 /
robert_lp	0:eedb7d567a5d	659	uint32_t RESERVED24[1U];
robert_lp	0:eedb7d567a5d	660	__IOM uint32_t COMP12; /!< Offset: 0x0E0 (R/W) Comparator Register 12 /
robert_lp	0:eedb7d567a5d	661	uint32_t RESERVED25[1U];
robert_lp	0:eedb7d567a5d	662	__IOM uint32_t FUNCTION12; /!< Offset: 0x0E8 (R/W) Function Register 12 /
robert_lp	0:eedb7d567a5d	663	uint32_t RESERVED26[1U];
robert_lp	0:eedb7d567a5d	664	__IOM uint32_t COMP13; /!< Offset: 0x0F0 (R/W) Comparator Register 13 /
robert_lp	0:eedb7d567a5d	665	uint32_t RESERVED27[1U];
robert_lp	0:eedb7d567a5d	666	__IOM uint32_t FUNCTION13; /!< Offset: 0x0F8 (R/W) Function Register 13 /
robert_lp	0:eedb7d567a5d	667	uint32_t RESERVED28[1U];
robert_lp	0:eedb7d567a5d	668	__IOM uint32_t COMP14; /!< Offset: 0x100 (R/W) Comparator Register 14 /
robert_lp	0:eedb7d567a5d	669	uint32_t RESERVED29[1U];
robert_lp	0:eedb7d567a5d	670	__IOM uint32_t FUNCTION14; /!< Offset: 0x108 (R/W) Function Register 14 /
robert_lp	0:eedb7d567a5d	671	uint32_t RESERVED30[1U];
robert_lp	0:eedb7d567a5d	672	__IOM uint32_t COMP15; /!< Offset: 0x110 (R/W) Comparator Register 15 /
robert_lp	0:eedb7d567a5d	673	uint32_t RESERVED31[1U];
robert_lp	0:eedb7d567a5d	674	__IOM uint32_t FUNCTION15; /!< Offset: 0x118 (R/W) Function Register 15 /
robert_lp	0:eedb7d567a5d	675	} DWT_Type;
robert_lp	0:eedb7d567a5d	676
robert_lp	0:eedb7d567a5d	677	/* DWT Control Register Definitions */
robert_lp	0:eedb7d567a5d	678	#define DWT_CTRL_NUMCOMP_Pos 28U /!< DWT CTRL: NUMCOMP Position /
robert_lp	0:eedb7d567a5d	679	#define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /!< DWT CTRL: NUMCOMP Mask /
robert_lp	0:eedb7d567a5d	680
robert_lp	0:eedb7d567a5d	681	#define DWT_CTRL_NOTRCPKT_Pos 27U /!< DWT CTRL: NOTRCPKT Position /
robert_lp	0:eedb7d567a5d	682	#define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /!< DWT CTRL: NOTRCPKT Mask /
robert_lp	0:eedb7d567a5d	683
robert_lp	0:eedb7d567a5d	684	#define DWT_CTRL_NOEXTTRIG_Pos 26U /!< DWT CTRL: NOEXTTRIG Position /
robert_lp	0:eedb7d567a5d	685	#define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /!< DWT CTRL: NOEXTTRIG Mask /
robert_lp	0:eedb7d567a5d	686
robert_lp	0:eedb7d567a5d	687	#define DWT_CTRL_NOCYCCNT_Pos 25U /!< DWT CTRL: NOCYCCNT Position /
robert_lp	0:eedb7d567a5d	688	#define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /!< DWT CTRL: NOCYCCNT Mask /
robert_lp	0:eedb7d567a5d	689
robert_lp	0:eedb7d567a5d	690	#define DWT_CTRL_NOPRFCNT_Pos 24U /!< DWT CTRL: NOPRFCNT Position /
robert_lp	0:eedb7d567a5d	691	#define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /!< DWT CTRL: NOPRFCNT Mask /
robert_lp	0:eedb7d567a5d	692
robert_lp	0:eedb7d567a5d	693	/* DWT Comparator Function Register Definitions */
robert_lp	0:eedb7d567a5d	694	#define DWT_FUNCTION_ID_Pos 27U /!< DWT FUNCTION: ID Position /
robert_lp	0:eedb7d567a5d	695	#define DWT_FUNCTION_ID_Msk (0x1FUL << DWT_FUNCTION_ID_Pos) /!< DWT FUNCTION: ID Mask /
robert_lp	0:eedb7d567a5d	696
robert_lp	0:eedb7d567a5d	697	#define DWT_FUNCTION_MATCHED_Pos 24U /!< DWT FUNCTION: MATCHED Position /
robert_lp	0:eedb7d567a5d	698	#define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /!< DWT FUNCTION: MATCHED Mask /
robert_lp	0:eedb7d567a5d	699
robert_lp	0:eedb7d567a5d	700	#define DWT_FUNCTION_DATAVSIZE_Pos 10U /!< DWT FUNCTION: DATAVSIZE Position /
robert_lp	0:eedb7d567a5d	701	#define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /!< DWT FUNCTION: DATAVSIZE Mask /
robert_lp	0:eedb7d567a5d	702
robert_lp	0:eedb7d567a5d	703	#define DWT_FUNCTION_ACTION_Pos 4U /!< DWT FUNCTION: ACTION Position /
robert_lp	0:eedb7d567a5d	704	#define DWT_FUNCTION_ACTION_Msk (0x3UL << DWT_FUNCTION_ACTION_Pos) /!< DWT FUNCTION: ACTION Mask /
robert_lp	0:eedb7d567a5d	705
robert_lp	0:eedb7d567a5d	706	#define DWT_FUNCTION_MATCH_Pos 0U /!< DWT FUNCTION: MATCH Position /
robert_lp	0:eedb7d567a5d	707	#define DWT_FUNCTION_MATCH_Msk (0xFUL /<< DWT_FUNCTION_MATCH_Pos/) /!< DWT FUNCTION: MATCH Mask /
robert_lp	0:eedb7d567a5d	708
robert_lp	0:eedb7d567a5d	709	/@}/ /* end of group CMSIS_DWT */
robert_lp	0:eedb7d567a5d	710
robert_lp	0:eedb7d567a5d	711
robert_lp	0:eedb7d567a5d	712	/**
robert_lp	0:eedb7d567a5d	713	\ingroup CMSIS_core_register
robert_lp	0:eedb7d567a5d	714	\defgroup CMSIS_TPI Trace Port Interface (TPI)
robert_lp	0:eedb7d567a5d	715	\brief Type definitions for the Trace Port Interface (TPI)
robert_lp	0:eedb7d567a5d	716	@{
robert_lp	0:eedb7d567a5d	717	*/
robert_lp	0:eedb7d567a5d	718
robert_lp	0:eedb7d567a5d	719	/**
robert_lp	0:eedb7d567a5d	720	\brief Structure type to access the Trace Port Interface Register (TPI).
robert_lp	0:eedb7d567a5d	721	*/
robert_lp	0:eedb7d567a5d	722	typedef struct
robert_lp	0:eedb7d567a5d	723	{
robert_lp	0:eedb7d567a5d	724	__IOM uint32_t SSPSR; /!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register /
robert_lp	0:eedb7d567a5d	725	__IOM uint32_t CSPSR; /!< Offset: 0x004 (R/W) Current Parallel Port Size Register /
robert_lp	0:eedb7d567a5d	726	uint32_t RESERVED0[2U];
robert_lp	0:eedb7d567a5d	727	__IOM uint32_t ACPR; /!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register /
robert_lp	0:eedb7d567a5d	728	uint32_t RESERVED1[55U];
robert_lp	0:eedb7d567a5d	729	__IOM uint32_t SPPR; /!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register /
robert_lp	0:eedb7d567a5d	730	uint32_t RESERVED2[131U];
robert_lp	0:eedb7d567a5d	731	__IM uint32_t FFSR; /!< Offset: 0x300 (R/ ) Formatter and Flush Status Register /
robert_lp	0:eedb7d567a5d	732	__IOM uint32_t FFCR; /!< Offset: 0x304 (R/W) Formatter and Flush Control Register /
robert_lp	0:eedb7d567a5d	733	__IM uint32_t FSCR; /!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register /
robert_lp	0:eedb7d567a5d	734	uint32_t RESERVED3[759U];
robert_lp	0:eedb7d567a5d	735	__IM uint32_t TRIGGER; /!< Offset: 0xEE8 (R/ ) TRIGGER /
robert_lp	0:eedb7d567a5d	736	__IM uint32_t FIFO0; /!< Offset: 0xEEC (R/ ) Integration ETM Data /
robert_lp	0:eedb7d567a5d	737	__IM uint32_t ITATBCTR2; /!< Offset: 0xEF0 (R/ ) ITATBCTR2 /
robert_lp	0:eedb7d567a5d	738	uint32_t RESERVED4[1U];
robert_lp	0:eedb7d567a5d	739	__IM uint32_t ITATBCTR0; /!< Offset: 0xEF8 (R/ ) ITATBCTR0 /
robert_lp	0:eedb7d567a5d	740	__IM uint32_t FIFO1; /!< Offset: 0xEFC (R/ ) Integration ITM Data /
robert_lp	0:eedb7d567a5d	741	__IOM uint32_t ITCTRL; /!< Offset: 0xF00 (R/W) Integration Mode Control /
robert_lp	0:eedb7d567a5d	742	uint32_t RESERVED5[39U];
robert_lp	0:eedb7d567a5d	743	__IOM uint32_t CLAIMSET; /!< Offset: 0xFA0 (R/W) Claim tag set /
robert_lp	0:eedb7d567a5d	744	__IOM uint32_t CLAIMCLR; /!< Offset: 0xFA4 (R/W) Claim tag clear /
robert_lp	0:eedb7d567a5d	745	uint32_t RESERVED7[8U];
robert_lp	0:eedb7d567a5d	746	__IM uint32_t DEVID; /!< Offset: 0xFC8 (R/ ) TPIU_DEVID /
robert_lp	0:eedb7d567a5d	747	__IM uint32_t DEVTYPE; /!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE /
robert_lp	0:eedb7d567a5d	748	} TPI_Type;
robert_lp	0:eedb7d567a5d	749
robert_lp	0:eedb7d567a5d	750	/* TPI Asynchronous Clock Prescaler Register Definitions */
robert_lp	0:eedb7d567a5d	751	#define TPI_ACPR_PRESCALER_Pos 0U /!< TPI ACPR: PRESCALER Position /
robert_lp	0:eedb7d567a5d	752	#define TPI_ACPR_PRESCALER_Msk (0x1FFFUL /<< TPI_ACPR_PRESCALER_Pos/) /!< TPI ACPR: PRESCALER Mask /
robert_lp	0:eedb7d567a5d	753
robert_lp	0:eedb7d567a5d	754	/* TPI Selected Pin Protocol Register Definitions */
robert_lp	0:eedb7d567a5d	755	#define TPI_SPPR_TXMODE_Pos 0U /!< TPI SPPR: TXMODE Position /
robert_lp	0:eedb7d567a5d	756	#define TPI_SPPR_TXMODE_Msk (0x3UL /<< TPI_SPPR_TXMODE_Pos/) /!< TPI SPPR: TXMODE Mask /
robert_lp	0:eedb7d567a5d	757
robert_lp	0:eedb7d567a5d	758	/* TPI Formatter and Flush Status Register Definitions */
robert_lp	0:eedb7d567a5d	759	#define TPI_FFSR_FtNonStop_Pos 3U /!< TPI FFSR: FtNonStop Position /
robert_lp	0:eedb7d567a5d	760	#define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /!< TPI FFSR: FtNonStop Mask /
robert_lp	0:eedb7d567a5d	761
robert_lp	0:eedb7d567a5d	762	#define TPI_FFSR_TCPresent_Pos 2U /!< TPI FFSR: TCPresent Position /
robert_lp	0:eedb7d567a5d	763	#define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /!< TPI FFSR: TCPresent Mask /
robert_lp	0:eedb7d567a5d	764
robert_lp	0:eedb7d567a5d	765	#define TPI_FFSR_FtStopped_Pos 1U /!< TPI FFSR: FtStopped Position /
robert_lp	0:eedb7d567a5d	766	#define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /!< TPI FFSR: FtStopped Mask /
robert_lp	0:eedb7d567a5d	767
robert_lp	0:eedb7d567a5d	768	#define TPI_FFSR_FlInProg_Pos 0U /!< TPI FFSR: FlInProg Position /
robert_lp	0:eedb7d567a5d	769	#define TPI_FFSR_FlInProg_Msk (0x1UL /<< TPI_FFSR_FlInProg_Pos/) /!< TPI FFSR: FlInProg Mask /
robert_lp	0:eedb7d567a5d	770
robert_lp	0:eedb7d567a5d	771	/* TPI Formatter and Flush Control Register Definitions */
robert_lp	0:eedb7d567a5d	772	#define TPI_FFCR_TrigIn_Pos 8U /!< TPI FFCR: TrigIn Position /
robert_lp	0:eedb7d567a5d	773	#define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /!< TPI FFCR: TrigIn Mask /
robert_lp	0:eedb7d567a5d	774
robert_lp	0:eedb7d567a5d	775	#define TPI_FFCR_EnFCont_Pos 1U /!< TPI FFCR: EnFCont Position /
robert_lp	0:eedb7d567a5d	776	#define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /!< TPI FFCR: EnFCont Mask /
robert_lp	0:eedb7d567a5d	777
robert_lp	0:eedb7d567a5d	778	/* TPI TRIGGER Register Definitions */
robert_lp	0:eedb7d567a5d	779	#define TPI_TRIGGER_TRIGGER_Pos 0U /!< TPI TRIGGER: TRIGGER Position /
robert_lp	0:eedb7d567a5d	780	#define TPI_TRIGGER_TRIGGER_Msk (0x1UL /<< TPI_TRIGGER_TRIGGER_Pos/) /!< TPI TRIGGER: TRIGGER Mask /
robert_lp	0:eedb7d567a5d	781
robert_lp	0:eedb7d567a5d	782	/* TPI Integration ETM Data Register Definitions (FIFO0) */
robert_lp	0:eedb7d567a5d	783	#define TPI_FIFO0_ITM_ATVALID_Pos 29U /!< TPI FIFO0: ITM_ATVALID Position /
robert_lp	0:eedb7d567a5d	784	#define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /!< TPI FIFO0: ITM_ATVALID Mask /
robert_lp	0:eedb7d567a5d	785
robert_lp	0:eedb7d567a5d	786	#define TPI_FIFO0_ITM_bytecount_Pos 27U /!< TPI FIFO0: ITM_bytecount Position /
robert_lp	0:eedb7d567a5d	787	#define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /!< TPI FIFO0: ITM_bytecount Mask /
robert_lp	0:eedb7d567a5d	788
robert_lp	0:eedb7d567a5d	789	#define TPI_FIFO0_ETM_ATVALID_Pos 26U /!< TPI FIFO0: ETM_ATVALID Position /
robert_lp	0:eedb7d567a5d	790	#define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /!< TPI FIFO0: ETM_ATVALID Mask /
robert_lp	0:eedb7d567a5d	791
robert_lp	0:eedb7d567a5d	792	#define TPI_FIFO0_ETM_bytecount_Pos 24U /!< TPI FIFO0: ETM_bytecount Position /
robert_lp	0:eedb7d567a5d	793	#define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /!< TPI FIFO0: ETM_bytecount Mask /
robert_lp	0:eedb7d567a5d	794
robert_lp	0:eedb7d567a5d	795	#define TPI_FIFO0_ETM2_Pos 16U /!< TPI FIFO0: ETM2 Position /
robert_lp	0:eedb7d567a5d	796	#define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /!< TPI FIFO0: ETM2 Mask /
robert_lp	0:eedb7d567a5d	797
robert_lp	0:eedb7d567a5d	798	#define TPI_FIFO0_ETM1_Pos 8U /!< TPI FIFO0: ETM1 Position /
robert_lp	0:eedb7d567a5d	799	#define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /!< TPI FIFO0: ETM1 Mask /
robert_lp	0:eedb7d567a5d	800
robert_lp	0:eedb7d567a5d	801	#define TPI_FIFO0_ETM0_Pos 0U /!< TPI FIFO0: ETM0 Position /
robert_lp	0:eedb7d567a5d	802	#define TPI_FIFO0_ETM0_Msk (0xFFUL /<< TPI_FIFO0_ETM0_Pos/) /!< TPI FIFO0: ETM0 Mask /
robert_lp	0:eedb7d567a5d	803
robert_lp	0:eedb7d567a5d	804	/* TPI ITATBCTR2 Register Definitions */
robert_lp	0:eedb7d567a5d	805	#define TPI_ITATBCTR2_ATREADY_Pos 0U /!< TPI ITATBCTR2: ATREADY Position /
robert_lp	0:eedb7d567a5d	806	#define TPI_ITATBCTR2_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR2_ATREADY_Pos/) /!< TPI ITATBCTR2: ATREADY Mask /
robert_lp	0:eedb7d567a5d	807
robert_lp	0:eedb7d567a5d	808	/* TPI Integration ITM Data Register Definitions (FIFO1) */
robert_lp	0:eedb7d567a5d	809	#define TPI_FIFO1_ITM_ATVALID_Pos 29U /!< TPI FIFO1: ITM_ATVALID Position /
robert_lp	0:eedb7d567a5d	810	#define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /!< TPI FIFO1: ITM_ATVALID Mask /
robert_lp	0:eedb7d567a5d	811
robert_lp	0:eedb7d567a5d	812	#define TPI_FIFO1_ITM_bytecount_Pos 27U /!< TPI FIFO1: ITM_bytecount Position /
robert_lp	0:eedb7d567a5d	813	#define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /!< TPI FIFO1: ITM_bytecount Mask /
robert_lp	0:eedb7d567a5d	814
robert_lp	0:eedb7d567a5d	815	#define TPI_FIFO1_ETM_ATVALID_Pos 26U /!< TPI FIFO1: ETM_ATVALID Position /
robert_lp	0:eedb7d567a5d	816	#define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /!< TPI FIFO1: ETM_ATVALID Mask /
robert_lp	0:eedb7d567a5d	817
robert_lp	0:eedb7d567a5d	818	#define TPI_FIFO1_ETM_bytecount_Pos 24U /!< TPI FIFO1: ETM_bytecount Position /
robert_lp	0:eedb7d567a5d	819	#define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /!< TPI FIFO1: ETM_bytecount Mask /
robert_lp	0:eedb7d567a5d	820
robert_lp	0:eedb7d567a5d	821	#define TPI_FIFO1_ITM2_Pos 16U /!< TPI FIFO1: ITM2 Position /
robert_lp	0:eedb7d567a5d	822	#define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /!< TPI FIFO1: ITM2 Mask /
robert_lp	0:eedb7d567a5d	823
robert_lp	0:eedb7d567a5d	824	#define TPI_FIFO1_ITM1_Pos 8U /!< TPI FIFO1: ITM1 Position /
robert_lp	0:eedb7d567a5d	825	#define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /!< TPI FIFO1: ITM1 Mask /
robert_lp	0:eedb7d567a5d	826
robert_lp	0:eedb7d567a5d	827	#define TPI_FIFO1_ITM0_Pos 0U /!< TPI FIFO1: ITM0 Position /
robert_lp	0:eedb7d567a5d	828	#define TPI_FIFO1_ITM0_Msk (0xFFUL /<< TPI_FIFO1_ITM0_Pos/) /!< TPI FIFO1: ITM0 Mask /
robert_lp	0:eedb7d567a5d	829
robert_lp	0:eedb7d567a5d	830	/* TPI ITATBCTR0 Register Definitions */
robert_lp	0:eedb7d567a5d	831	#define TPI_ITATBCTR0_ATREADY_Pos 0U /!< TPI ITATBCTR0: ATREADY Position /
robert_lp	0:eedb7d567a5d	832	#define TPI_ITATBCTR0_ATREADY_Msk (0x1UL /<< TPI_ITATBCTR0_ATREADY_Pos/) /!< TPI ITATBCTR0: ATREADY Mask /
robert_lp	0:eedb7d567a5d	833
robert_lp	0:eedb7d567a5d	834	/* TPI Integration Mode Control Register Definitions */
robert_lp	0:eedb7d567a5d	835	#define TPI_ITCTRL_Mode_Pos 0U /!< TPI ITCTRL: Mode Position /
robert_lp	0:eedb7d567a5d	836	#define TPI_ITCTRL_Mode_Msk (0x1UL /<< TPI_ITCTRL_Mode_Pos/) /!< TPI ITCTRL: Mode Mask /
robert_lp	0:eedb7d567a5d	837
robert_lp	0:eedb7d567a5d	838	/* TPI DEVID Register Definitions */
robert_lp	0:eedb7d567a5d	839	#define TPI_DEVID_NRZVALID_Pos 11U /!< TPI DEVID: NRZVALID Position /
robert_lp	0:eedb7d567a5d	840	#define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /!< TPI DEVID: NRZVALID Mask /
robert_lp	0:eedb7d567a5d	841
robert_lp	0:eedb7d567a5d	842	#define TPI_DEVID_MANCVALID_Pos 10U /!< TPI DEVID: MANCVALID Position /
robert_lp	0:eedb7d567a5d	843	#define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /!< TPI DEVID: MANCVALID Mask /
robert_lp	0:eedb7d567a5d	844
robert_lp	0:eedb7d567a5d	845	#define TPI_DEVID_PTINVALID_Pos 9U /!< TPI DEVID: PTINVALID Position /
robert_lp	0:eedb7d567a5d	846	#define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /!< TPI DEVID: PTINVALID Mask /
robert_lp	0:eedb7d567a5d	847
robert_lp	0:eedb7d567a5d	848	#define TPI_DEVID_MinBufSz_Pos 6U /!< TPI DEVID: MinBufSz Position /
robert_lp	0:eedb7d567a5d	849	#define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /!< TPI DEVID: MinBufSz Mask /
robert_lp	0:eedb7d567a5d	850
robert_lp	0:eedb7d567a5d	851	#define TPI_DEVID_AsynClkIn_Pos 5U /!< TPI DEVID: AsynClkIn Position /
robert_lp	0:eedb7d567a5d	852	#define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /!< TPI DEVID: AsynClkIn Mask /
robert_lp	0:eedb7d567a5d	853
robert_lp	0:eedb7d567a5d	854	#define TPI_DEVID_NrTraceInput_Pos 0U /!< TPI DEVID: NrTraceInput Position /
robert_lp	0:eedb7d567a5d	855	#define TPI_DEVID_NrTraceInput_Msk (0x1FUL /<< TPI_DEVID_NrTraceInput_Pos/) /!< TPI DEVID: NrTraceInput Mask /
robert_lp	0:eedb7d567a5d	856
robert_lp	0:eedb7d567a5d	857	/* TPI DEVTYPE Register Definitions */
robert_lp	0:eedb7d567a5d	858	#define TPI_DEVTYPE_MajorType_Pos 4U /!< TPI DEVTYPE: MajorType Position /
robert_lp	0:eedb7d567a5d	859	#define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /!< TPI DEVTYPE: MajorType Mask /
robert_lp	0:eedb7d567a5d	860
robert_lp	0:eedb7d567a5d	861	#define TPI_DEVTYPE_SubType_Pos 0U /!< TPI DEVTYPE: SubType Position /
robert_lp	0:eedb7d567a5d	862	#define TPI_DEVTYPE_SubType_Msk (0xFUL /<< TPI_DEVTYPE_SubType_Pos/) /!< TPI DEVTYPE: SubType Mask /
robert_lp	0:eedb7d567a5d	863
robert_lp	0:eedb7d567a5d	864	/@}/ /* end of group CMSIS_TPI */
robert_lp	0:eedb7d567a5d	865
robert_lp	0:eedb7d567a5d	866
robert_lp	0:eedb7d567a5d	867	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
robert_lp	0:eedb7d567a5d	868	/**
robert_lp	0:eedb7d567a5d	869	\ingroup CMSIS_core_register
robert_lp	0:eedb7d567a5d	870	\defgroup CMSIS_MPU Memory Protection Unit (MPU)
robert_lp	0:eedb7d567a5d	871	\brief Type definitions for the Memory Protection Unit (MPU)
robert_lp	0:eedb7d567a5d	872	@{
robert_lp	0:eedb7d567a5d	873	*/
robert_lp	0:eedb7d567a5d	874
robert_lp	0:eedb7d567a5d	875	/**
robert_lp	0:eedb7d567a5d	876	\brief Structure type to access the Memory Protection Unit (MPU).
robert_lp	0:eedb7d567a5d	877	*/
robert_lp	0:eedb7d567a5d	878	typedef struct
robert_lp	0:eedb7d567a5d	879	{
robert_lp	0:eedb7d567a5d	880	__IM uint32_t TYPE; /!< Offset: 0x000 (R/ ) MPU Type Register /
robert_lp	0:eedb7d567a5d	881	__IOM uint32_t CTRL; /!< Offset: 0x004 (R/W) MPU Control Register /
robert_lp	0:eedb7d567a5d	882	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) MPU Region Number Register /
robert_lp	0:eedb7d567a5d	883	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) MPU Region Base Address Register /
robert_lp	0:eedb7d567a5d	884	__IOM uint32_t RLAR; /!< Offset: 0x010 (R/W) MPU Region Limit Address Register /
robert_lp	0:eedb7d567a5d	885	uint32_t RESERVED0[7U];
robert_lp	0:eedb7d567a5d	886	union {
robert_lp	0:eedb7d567a5d	887	__IOM uint32_t MAIR[2];
robert_lp	0:eedb7d567a5d	888	struct {
robert_lp	0:eedb7d567a5d	889	__IOM uint32_t MAIR0; /!< Offset: 0x030 (R/W) MPU Memory Attribute Indirection Register 0 /
robert_lp	0:eedb7d567a5d	890	__IOM uint32_t MAIR1; /!< Offset: 0x034 (R/W) MPU Memory Attribute Indirection Register 1 /
robert_lp	0:eedb7d567a5d	891	};
robert_lp	0:eedb7d567a5d	892	};
robert_lp	0:eedb7d567a5d	893	} MPU_Type;
robert_lp	0:eedb7d567a5d	894
robert_lp	0:eedb7d567a5d	895	#define MPU_TYPE_RALIASES 1U
robert_lp	0:eedb7d567a5d	896
robert_lp	0:eedb7d567a5d	897	/* MPU Type Register Definitions */
robert_lp	0:eedb7d567a5d	898	#define MPU_TYPE_IREGION_Pos 16U /!< MPU TYPE: IREGION Position /
robert_lp	0:eedb7d567a5d	899	#define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /!< MPU TYPE: IREGION Mask /
robert_lp	0:eedb7d567a5d	900
robert_lp	0:eedb7d567a5d	901	#define MPU_TYPE_DREGION_Pos 8U /!< MPU TYPE: DREGION Position /
robert_lp	0:eedb7d567a5d	902	#define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /!< MPU TYPE: DREGION Mask /
robert_lp	0:eedb7d567a5d	903
robert_lp	0:eedb7d567a5d	904	#define MPU_TYPE_SEPARATE_Pos 0U /!< MPU TYPE: SEPARATE Position /
robert_lp	0:eedb7d567a5d	905	#define MPU_TYPE_SEPARATE_Msk (1UL /<< MPU_TYPE_SEPARATE_Pos/) /!< MPU TYPE: SEPARATE Mask /
robert_lp	0:eedb7d567a5d	906
robert_lp	0:eedb7d567a5d	907	/* MPU Control Register Definitions */
robert_lp	0:eedb7d567a5d	908	#define MPU_CTRL_PRIVDEFENA_Pos 2U /!< MPU CTRL: PRIVDEFENA Position /
robert_lp	0:eedb7d567a5d	909	#define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /!< MPU CTRL: PRIVDEFENA Mask /
robert_lp	0:eedb7d567a5d	910
robert_lp	0:eedb7d567a5d	911	#define MPU_CTRL_HFNMIENA_Pos 1U /!< MPU CTRL: HFNMIENA Position /
robert_lp	0:eedb7d567a5d	912	#define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /!< MPU CTRL: HFNMIENA Mask /
robert_lp	0:eedb7d567a5d	913
robert_lp	0:eedb7d567a5d	914	#define MPU_CTRL_ENABLE_Pos 0U /!< MPU CTRL: ENABLE Position /
robert_lp	0:eedb7d567a5d	915	#define MPU_CTRL_ENABLE_Msk (1UL /<< MPU_CTRL_ENABLE_Pos/) /!< MPU CTRL: ENABLE Mask /
robert_lp	0:eedb7d567a5d	916
robert_lp	0:eedb7d567a5d	917	/* MPU Region Number Register Definitions */
robert_lp	0:eedb7d567a5d	918	#define MPU_RNR_REGION_Pos 0U /!< MPU RNR: REGION Position /
robert_lp	0:eedb7d567a5d	919	#define MPU_RNR_REGION_Msk (0xFFUL /<< MPU_RNR_REGION_Pos/) /!< MPU RNR: REGION Mask /
robert_lp	0:eedb7d567a5d	920
robert_lp	0:eedb7d567a5d	921	/* MPU Region Base Address Register Definitions */
robert_lp	0:eedb7d567a5d	922	#define MPU_RBAR_BASE_Pos 5U /!< MPU RBAR: BASE Position /
robert_lp	0:eedb7d567a5d	923	#define MPU_RBAR_BASE_Msk (0x7FFFFFFUL << MPU_RBAR_BASE_Pos) /!< MPU RBAR: BASE Mask /
robert_lp	0:eedb7d567a5d	924
robert_lp	0:eedb7d567a5d	925	#define MPU_RBAR_SH_Pos 3U /!< MPU RBAR: SH Position /
robert_lp	0:eedb7d567a5d	926	#define MPU_RBAR_SH_Msk (0x3UL << MPU_RBAR_SH_Pos) /!< MPU RBAR: SH Mask /
robert_lp	0:eedb7d567a5d	927
robert_lp	0:eedb7d567a5d	928	#define MPU_RBAR_AP_Pos 1U /!< MPU RBAR: AP Position /
robert_lp	0:eedb7d567a5d	929	#define MPU_RBAR_AP_Msk (0x3UL << MPU_RBAR_AP_Pos) /!< MPU RBAR: AP Mask /
robert_lp	0:eedb7d567a5d	930
robert_lp	0:eedb7d567a5d	931	#define MPU_RBAR_XN_Pos 0U /!< MPU RBAR: XN Position /
robert_lp	0:eedb7d567a5d	932	#define MPU_RBAR_XN_Msk (01UL /<< MPU_RBAR_XN_Pos/) /!< MPU RBAR: XN Mask /
robert_lp	0:eedb7d567a5d	933
robert_lp	0:eedb7d567a5d	934	/* MPU Region Limit Address Register Definitions */
robert_lp	0:eedb7d567a5d	935	#define MPU_RLAR_LIMIT_Pos 5U /!< MPU RLAR: LIMIT Position /
robert_lp	0:eedb7d567a5d	936	#define MPU_RLAR_LIMIT_Msk (0x7FFFFFFUL << MPU_RLAR_LIMIT_Pos) /!< MPU RLAR: LIMIT Mask /
robert_lp	0:eedb7d567a5d	937
robert_lp	0:eedb7d567a5d	938	#define MPU_RLAR_AttrIndx_Pos 1U /!< MPU RLAR: AttrIndx Position /
robert_lp	0:eedb7d567a5d	939	#define MPU_RLAR_AttrIndx_Msk (0x7UL << MPU_RLAR_AttrIndx_Pos) /!< MPU RLAR: AttrIndx Mask /
robert_lp	0:eedb7d567a5d	940
robert_lp	0:eedb7d567a5d	941	#define MPU_RLAR_EN_Pos 0U /!< MPU RLAR: EN Position /
robert_lp	0:eedb7d567a5d	942	#define MPU_RLAR_EN_Msk (1UL /<< MPU_RLAR_EN_Pos/) /!< MPU RLAR: EN Mask /
robert_lp	0:eedb7d567a5d	943
robert_lp	0:eedb7d567a5d	944	/* MPU Memory Attribute Indirection Register 0 Definitions */
robert_lp	0:eedb7d567a5d	945	#define MPU_MAIR0_Attr3_Pos 24U /!< MPU MAIR0: Attr3 Position /
robert_lp	0:eedb7d567a5d	946	#define MPU_MAIR0_Attr3_Msk (0xFFUL << MPU_MAIR0_Attr3_Pos) /!< MPU MAIR0: Attr3 Mask /
robert_lp	0:eedb7d567a5d	947
robert_lp	0:eedb7d567a5d	948	#define MPU_MAIR0_Attr2_Pos 16U /!< MPU MAIR0: Attr2 Position /
robert_lp	0:eedb7d567a5d	949	#define MPU_MAIR0_Attr2_Msk (0xFFUL << MPU_MAIR0_Attr2_Pos) /!< MPU MAIR0: Attr2 Mask /
robert_lp	0:eedb7d567a5d	950
robert_lp	0:eedb7d567a5d	951	#define MPU_MAIR0_Attr1_Pos 8U /!< MPU MAIR0: Attr1 Position /
robert_lp	0:eedb7d567a5d	952	#define MPU_MAIR0_Attr1_Msk (0xFFUL << MPU_MAIR0_Attr1_Pos) /!< MPU MAIR0: Attr1 Mask /
robert_lp	0:eedb7d567a5d	953
robert_lp	0:eedb7d567a5d	954	#define MPU_MAIR0_Attr0_Pos 0U /!< MPU MAIR0: Attr0 Position /
robert_lp	0:eedb7d567a5d	955	#define MPU_MAIR0_Attr0_Msk (0xFFUL /<< MPU_MAIR0_Attr0_Pos/) /!< MPU MAIR0: Attr0 Mask /
robert_lp	0:eedb7d567a5d	956
robert_lp	0:eedb7d567a5d	957	/* MPU Memory Attribute Indirection Register 1 Definitions */
robert_lp	0:eedb7d567a5d	958	#define MPU_MAIR1_Attr7_Pos 24U /!< MPU MAIR1: Attr7 Position /
robert_lp	0:eedb7d567a5d	959	#define MPU_MAIR1_Attr7_Msk (0xFFUL << MPU_MAIR1_Attr7_Pos) /!< MPU MAIR1: Attr7 Mask /
robert_lp	0:eedb7d567a5d	960
robert_lp	0:eedb7d567a5d	961	#define MPU_MAIR1_Attr6_Pos 16U /!< MPU MAIR1: Attr6 Position /
robert_lp	0:eedb7d567a5d	962	#define MPU_MAIR1_Attr6_Msk (0xFFUL << MPU_MAIR1_Attr6_Pos) /!< MPU MAIR1: Attr6 Mask /
robert_lp	0:eedb7d567a5d	963
robert_lp	0:eedb7d567a5d	964	#define MPU_MAIR1_Attr5_Pos 8U /!< MPU MAIR1: Attr5 Position /
robert_lp	0:eedb7d567a5d	965	#define MPU_MAIR1_Attr5_Msk (0xFFUL << MPU_MAIR1_Attr5_Pos) /!< MPU MAIR1: Attr5 Mask /
robert_lp	0:eedb7d567a5d	966
robert_lp	0:eedb7d567a5d	967	#define MPU_MAIR1_Attr4_Pos 0U /!< MPU MAIR1: Attr4 Position /
robert_lp	0:eedb7d567a5d	968	#define MPU_MAIR1_Attr4_Msk (0xFFUL /<< MPU_MAIR1_Attr4_Pos/) /!< MPU MAIR1: Attr4 Mask /
robert_lp	0:eedb7d567a5d	969
robert_lp	0:eedb7d567a5d	970	/@} end of group CMSIS_MPU /
robert_lp	0:eedb7d567a5d	971	#endif
robert_lp	0:eedb7d567a5d	972
robert_lp	0:eedb7d567a5d	973
robert_lp	0:eedb7d567a5d	974	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
robert_lp	0:eedb7d567a5d	975	/**
robert_lp	0:eedb7d567a5d	976	\ingroup CMSIS_core_register
robert_lp	0:eedb7d567a5d	977	\defgroup CMSIS_SAU Security Attribution Unit (SAU)
robert_lp	0:eedb7d567a5d	978	\brief Type definitions for the Security Attribution Unit (SAU)
robert_lp	0:eedb7d567a5d	979	@{
robert_lp	0:eedb7d567a5d	980	*/
robert_lp	0:eedb7d567a5d	981
robert_lp	0:eedb7d567a5d	982	/**
robert_lp	0:eedb7d567a5d	983	\brief Structure type to access the Security Attribution Unit (SAU).
robert_lp	0:eedb7d567a5d	984	*/
robert_lp	0:eedb7d567a5d	985	typedef struct
robert_lp	0:eedb7d567a5d	986	{
robert_lp	0:eedb7d567a5d	987	__IOM uint32_t CTRL; /!< Offset: 0x000 (R/W) SAU Control Register /
robert_lp	0:eedb7d567a5d	988	__IM uint32_t TYPE; /!< Offset: 0x004 (R/ ) SAU Type Register /
robert_lp	0:eedb7d567a5d	989	#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
robert_lp	0:eedb7d567a5d	990	__IOM uint32_t RNR; /!< Offset: 0x008 (R/W) SAU Region Number Register /
robert_lp	0:eedb7d567a5d	991	__IOM uint32_t RBAR; /!< Offset: 0x00C (R/W) SAU Region Base Address Register /
robert_lp	0:eedb7d567a5d	992	__IOM uint32_t RLAR; /!< Offset: 0x010 (R/W) SAU Region Limit Address Register /
robert_lp	0:eedb7d567a5d	993	#endif
robert_lp	0:eedb7d567a5d	994	} SAU_Type;
robert_lp	0:eedb7d567a5d	995
robert_lp	0:eedb7d567a5d	996	/* SAU Control Register Definitions */
robert_lp	0:eedb7d567a5d	997	#define SAU_CTRL_ALLNS_Pos 1U /!< SAU CTRL: ALLNS Position /
robert_lp	0:eedb7d567a5d	998	#define SAU_CTRL_ALLNS_Msk (1UL << SAU_CTRL_ALLNS_Pos) /!< SAU CTRL: ALLNS Mask /
robert_lp	0:eedb7d567a5d	999
robert_lp	0:eedb7d567a5d	1000	#define SAU_CTRL_ENABLE_Pos 0U /!< SAU CTRL: ENABLE Position /
robert_lp	0:eedb7d567a5d	1001	#define SAU_CTRL_ENABLE_Msk (1UL /<< SAU_CTRL_ENABLE_Pos/) /!< SAU CTRL: ENABLE Mask /
robert_lp	0:eedb7d567a5d	1002
robert_lp	0:eedb7d567a5d	1003	/* SAU Type Register Definitions */
robert_lp	0:eedb7d567a5d	1004	#define SAU_TYPE_SREGION_Pos 0U /!< SAU TYPE: SREGION Position /
robert_lp	0:eedb7d567a5d	1005	#define SAU_TYPE_SREGION_Msk (0xFFUL /<< SAU_TYPE_SREGION_Pos/) /!< SAU TYPE: SREGION Mask /
robert_lp	0:eedb7d567a5d	1006
robert_lp	0:eedb7d567a5d	1007	#if defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U)
robert_lp	0:eedb7d567a5d	1008	/* SAU Region Number Register Definitions */
robert_lp	0:eedb7d567a5d	1009	#define SAU_RNR_REGION_Pos 0U /!< SAU RNR: REGION Position /
robert_lp	0:eedb7d567a5d	1010	#define SAU_RNR_REGION_Msk (0xFFUL /<< SAU_RNR_REGION_Pos/) /!< SAU RNR: REGION Mask /
robert_lp	0:eedb7d567a5d	1011
robert_lp	0:eedb7d567a5d	1012	/* SAU Region Base Address Register Definitions */
robert_lp	0:eedb7d567a5d	1013	#define SAU_RBAR_BADDR_Pos 5U /!< SAU RBAR: BADDR Position /
robert_lp	0:eedb7d567a5d	1014	#define SAU_RBAR_BADDR_Msk (0x7FFFFFFUL << SAU_RBAR_BADDR_Pos) /!< SAU RBAR: BADDR Mask /
robert_lp	0:eedb7d567a5d	1015
robert_lp	0:eedb7d567a5d	1016	/* SAU Region Limit Address Register Definitions */
robert_lp	0:eedb7d567a5d	1017	#define SAU_RLAR_LADDR_Pos 5U /!< SAU RLAR: LADDR Position /
robert_lp	0:eedb7d567a5d	1018	#define SAU_RLAR_LADDR_Msk (0x7FFFFFFUL << SAU_RLAR_LADDR_Pos) /!< SAU RLAR: LADDR Mask /
robert_lp	0:eedb7d567a5d	1019
robert_lp	0:eedb7d567a5d	1020	#define SAU_RLAR_NSC_Pos 1U /!< SAU RLAR: NSC Position /
robert_lp	0:eedb7d567a5d	1021	#define SAU_RLAR_NSC_Msk (1UL << SAU_RLAR_NSC_Pos) /!< SAU RLAR: NSC Mask /
robert_lp	0:eedb7d567a5d	1022
robert_lp	0:eedb7d567a5d	1023	#define SAU_RLAR_ENABLE_Pos 0U /!< SAU RLAR: ENABLE Position /
robert_lp	0:eedb7d567a5d	1024	#define SAU_RLAR_ENABLE_Msk (1UL /<< SAU_RLAR_ENABLE_Pos/) /!< SAU RLAR: ENABLE Mask /
robert_lp	0:eedb7d567a5d	1025
robert_lp	0:eedb7d567a5d	1026	#endif /* defined (__SAUREGION_PRESENT) && (__SAUREGION_PRESENT == 1U) */
robert_lp	0:eedb7d567a5d	1027
robert_lp	0:eedb7d567a5d	1028	/@} end of group CMSIS_SAU /
robert_lp	0:eedb7d567a5d	1029	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
robert_lp	0:eedb7d567a5d	1030
robert_lp	0:eedb7d567a5d	1031
robert_lp	0:eedb7d567a5d	1032	/**
robert_lp	0:eedb7d567a5d	1033	\ingroup CMSIS_core_register
robert_lp	0:eedb7d567a5d	1034	\defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
robert_lp	0:eedb7d567a5d	1035	\brief Type definitions for the Core Debug Registers
robert_lp	0:eedb7d567a5d	1036	@{
robert_lp	0:eedb7d567a5d	1037	*/
robert_lp	0:eedb7d567a5d	1038
robert_lp	0:eedb7d567a5d	1039	/**
robert_lp	0:eedb7d567a5d	1040	\brief Structure type to access the Core Debug Register (CoreDebug).
robert_lp	0:eedb7d567a5d	1041	*/
robert_lp	0:eedb7d567a5d	1042	typedef struct
robert_lp	0:eedb7d567a5d	1043	{
robert_lp	0:eedb7d567a5d	1044	__IOM uint32_t DHCSR; /!< Offset: 0x000 (R/W) Debug Halting Control and Status Register /
robert_lp	0:eedb7d567a5d	1045	__OM uint32_t DCRSR; /!< Offset: 0x004 ( /W) Debug Core Register Selector Register /
robert_lp	0:eedb7d567a5d	1046	__IOM uint32_t DCRDR; /!< Offset: 0x008 (R/W) Debug Core Register Data Register /
robert_lp	0:eedb7d567a5d	1047	__IOM uint32_t DEMCR; /!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register /
robert_lp	0:eedb7d567a5d	1048	uint32_t RESERVED4[1U];
robert_lp	0:eedb7d567a5d	1049	__IOM uint32_t DAUTHCTRL; /!< Offset: 0x014 (R/W) Debug Authentication Control Register /
robert_lp	0:eedb7d567a5d	1050	__IOM uint32_t DSCSR; /!< Offset: 0x018 (R/W) Debug Security Control and Status Register /
robert_lp	0:eedb7d567a5d	1051	} CoreDebug_Type;
robert_lp	0:eedb7d567a5d	1052
robert_lp	0:eedb7d567a5d	1053	/* Debug Halting Control and Status Register Definitions */
robert_lp	0:eedb7d567a5d	1054	#define CoreDebug_DHCSR_DBGKEY_Pos 16U /!< CoreDebug DHCSR: DBGKEY Position /
robert_lp	0:eedb7d567a5d	1055	#define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /!< CoreDebug DHCSR: DBGKEY Mask /
robert_lp	0:eedb7d567a5d	1056
robert_lp	0:eedb7d567a5d	1057	#define CoreDebug_DHCSR_S_RESTART_ST_Pos 26U /!< CoreDebug DHCSR: S_RESTART_ST Position /
robert_lp	0:eedb7d567a5d	1058	#define CoreDebug_DHCSR_S_RESTART_ST_Msk (1UL << CoreDebug_DHCSR_S_RESTART_ST_Pos) /!< CoreDebug DHCSR: S_RESTART_ST Mask /
robert_lp	0:eedb7d567a5d	1059
robert_lp	0:eedb7d567a5d	1060	#define CoreDebug_DHCSR_S_RESET_ST_Pos 25U /!< CoreDebug DHCSR: S_RESET_ST Position /
robert_lp	0:eedb7d567a5d	1061	#define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /!< CoreDebug DHCSR: S_RESET_ST Mask /
robert_lp	0:eedb7d567a5d	1062
robert_lp	0:eedb7d567a5d	1063	#define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24U /!< CoreDebug DHCSR: S_RETIRE_ST Position /
robert_lp	0:eedb7d567a5d	1064	#define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /!< CoreDebug DHCSR: S_RETIRE_ST Mask /
robert_lp	0:eedb7d567a5d	1065
robert_lp	0:eedb7d567a5d	1066	#define CoreDebug_DHCSR_S_LOCKUP_Pos 19U /!< CoreDebug DHCSR: S_LOCKUP Position /
robert_lp	0:eedb7d567a5d	1067	#define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /!< CoreDebug DHCSR: S_LOCKUP Mask /
robert_lp	0:eedb7d567a5d	1068
robert_lp	0:eedb7d567a5d	1069	#define CoreDebug_DHCSR_S_SLEEP_Pos 18U /!< CoreDebug DHCSR: S_SLEEP Position /
robert_lp	0:eedb7d567a5d	1070	#define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /!< CoreDebug DHCSR: S_SLEEP Mask /
robert_lp	0:eedb7d567a5d	1071
robert_lp	0:eedb7d567a5d	1072	#define CoreDebug_DHCSR_S_HALT_Pos 17U /!< CoreDebug DHCSR: S_HALT Position /
robert_lp	0:eedb7d567a5d	1073	#define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /!< CoreDebug DHCSR: S_HALT Mask /
robert_lp	0:eedb7d567a5d	1074
robert_lp	0:eedb7d567a5d	1075	#define CoreDebug_DHCSR_S_REGRDY_Pos 16U /!< CoreDebug DHCSR: S_REGRDY Position /
robert_lp	0:eedb7d567a5d	1076	#define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /!< CoreDebug DHCSR: S_REGRDY Mask /
robert_lp	0:eedb7d567a5d	1077
robert_lp	0:eedb7d567a5d	1078	#define CoreDebug_DHCSR_C_MASKINTS_Pos 3U /!< CoreDebug DHCSR: C_MASKINTS Position /
robert_lp	0:eedb7d567a5d	1079	#define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /!< CoreDebug DHCSR: C_MASKINTS Mask /
robert_lp	0:eedb7d567a5d	1080
robert_lp	0:eedb7d567a5d	1081	#define CoreDebug_DHCSR_C_STEP_Pos 2U /!< CoreDebug DHCSR: C_STEP Position /
robert_lp	0:eedb7d567a5d	1082	#define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /!< CoreDebug DHCSR: C_STEP Mask /
robert_lp	0:eedb7d567a5d	1083
robert_lp	0:eedb7d567a5d	1084	#define CoreDebug_DHCSR_C_HALT_Pos 1U /!< CoreDebug DHCSR: C_HALT Position /
robert_lp	0:eedb7d567a5d	1085	#define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /!< CoreDebug DHCSR: C_HALT Mask /
robert_lp	0:eedb7d567a5d	1086
robert_lp	0:eedb7d567a5d	1087	#define CoreDebug_DHCSR_C_DEBUGEN_Pos 0U /!< CoreDebug DHCSR: C_DEBUGEN Position /
robert_lp	0:eedb7d567a5d	1088	#define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL /<< CoreDebug_DHCSR_C_DEBUGEN_Pos/) /!< CoreDebug DHCSR: C_DEBUGEN Mask /
robert_lp	0:eedb7d567a5d	1089
robert_lp	0:eedb7d567a5d	1090	/* Debug Core Register Selector Register Definitions */
robert_lp	0:eedb7d567a5d	1091	#define CoreDebug_DCRSR_REGWnR_Pos 16U /!< CoreDebug DCRSR: REGWnR Position /
robert_lp	0:eedb7d567a5d	1092	#define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /!< CoreDebug DCRSR: REGWnR Mask /
robert_lp	0:eedb7d567a5d	1093
robert_lp	0:eedb7d567a5d	1094	#define CoreDebug_DCRSR_REGSEL_Pos 0U /!< CoreDebug DCRSR: REGSEL Position /
robert_lp	0:eedb7d567a5d	1095	#define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL /<< CoreDebug_DCRSR_REGSEL_Pos/) /!< CoreDebug DCRSR: REGSEL Mask /
robert_lp	0:eedb7d567a5d	1096
robert_lp	0:eedb7d567a5d	1097	/* Debug Exception and Monitor Control Register */
robert_lp	0:eedb7d567a5d	1098	#define CoreDebug_DEMCR_DWTENA_Pos 24U /!< CoreDebug DEMCR: DWTENA Position /
robert_lp	0:eedb7d567a5d	1099	#define CoreDebug_DEMCR_DWTENA_Msk (1UL << CoreDebug_DEMCR_DWTENA_Pos) /!< CoreDebug DEMCR: DWTENA Mask /
robert_lp	0:eedb7d567a5d	1100
robert_lp	0:eedb7d567a5d	1101	#define CoreDebug_DEMCR_VC_HARDERR_Pos 10U /!< CoreDebug DEMCR: VC_HARDERR Position /
robert_lp	0:eedb7d567a5d	1102	#define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /!< CoreDebug DEMCR: VC_HARDERR Mask /
robert_lp	0:eedb7d567a5d	1103
robert_lp	0:eedb7d567a5d	1104	#define CoreDebug_DEMCR_VC_CORERESET_Pos 0U /!< CoreDebug DEMCR: VC_CORERESET Position /
robert_lp	0:eedb7d567a5d	1105	#define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL /<< CoreDebug_DEMCR_VC_CORERESET_Pos/) /!< CoreDebug DEMCR: VC_CORERESET Mask /
robert_lp	0:eedb7d567a5d	1106
robert_lp	0:eedb7d567a5d	1107	/* Debug Authentication Control Register Definitions */
robert_lp	0:eedb7d567a5d	1108	#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos 3U /!< CoreDebug DAUTHCTRL: INTSPNIDEN, Position /
robert_lp	0:eedb7d567a5d	1109	#define CoreDebug_DAUTHCTRL_INTSPNIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPNIDEN_Pos) /!< CoreDebug DAUTHCTRL: INTSPNIDEN, Mask /
robert_lp	0:eedb7d567a5d	1110
robert_lp	0:eedb7d567a5d	1111	#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos 2U /!< CoreDebug DAUTHCTRL: SPNIDENSEL Position /
robert_lp	0:eedb7d567a5d	1112	#define CoreDebug_DAUTHCTRL_SPNIDENSEL_Msk (1UL << CoreDebug_DAUTHCTRL_SPNIDENSEL_Pos) /!< CoreDebug DAUTHCTRL: SPNIDENSEL Mask /
robert_lp	0:eedb7d567a5d	1113
robert_lp	0:eedb7d567a5d	1114	#define CoreDebug_DAUTHCTRL_INTSPIDEN_Pos 1U /!< CoreDebug DAUTHCTRL: INTSPIDEN Position /
robert_lp	0:eedb7d567a5d	1115	#define CoreDebug_DAUTHCTRL_INTSPIDEN_Msk (1UL << CoreDebug_DAUTHCTRL_INTSPIDEN_Pos) /!< CoreDebug DAUTHCTRL: INTSPIDEN Mask /
robert_lp	0:eedb7d567a5d	1116
robert_lp	0:eedb7d567a5d	1117	#define CoreDebug_DAUTHCTRL_SPIDENSEL_Pos 0U /!< CoreDebug DAUTHCTRL: SPIDENSEL Position /
robert_lp	0:eedb7d567a5d	1118	#define CoreDebug_DAUTHCTRL_SPIDENSEL_Msk (1UL /<< CoreDebug_DAUTHCTRL_SPIDENSEL_Pos/) /!< CoreDebug DAUTHCTRL: SPIDENSEL Mask /
robert_lp	0:eedb7d567a5d	1119
robert_lp	0:eedb7d567a5d	1120	/* Debug Security Control and Status Register Definitions */
robert_lp	0:eedb7d567a5d	1121	#define CoreDebug_DSCSR_CDS_Pos 16U /!< CoreDebug DSCSR: CDS Position /
robert_lp	0:eedb7d567a5d	1122	#define CoreDebug_DSCSR_CDS_Msk (1UL << CoreDebug_DSCSR_CDS_Pos) /!< CoreDebug DSCSR: CDS Mask /
robert_lp	0:eedb7d567a5d	1123
robert_lp	0:eedb7d567a5d	1124	#define CoreDebug_DSCSR_SBRSEL_Pos 1U /!< CoreDebug DSCSR: SBRSEL Position /
robert_lp	0:eedb7d567a5d	1125	#define CoreDebug_DSCSR_SBRSEL_Msk (1UL << CoreDebug_DSCSR_SBRSEL_Pos) /!< CoreDebug DSCSR: SBRSEL Mask /
robert_lp	0:eedb7d567a5d	1126
robert_lp	0:eedb7d567a5d	1127	#define CoreDebug_DSCSR_SBRSELEN_Pos 0U /!< CoreDebug DSCSR: SBRSELEN Position /
robert_lp	0:eedb7d567a5d	1128	#define CoreDebug_DSCSR_SBRSELEN_Msk (1UL /<< CoreDebug_DSCSR_SBRSELEN_Pos/) /!< CoreDebug DSCSR: SBRSELEN Mask /
robert_lp	0:eedb7d567a5d	1129
robert_lp	0:eedb7d567a5d	1130	/@} end of group CMSIS_CoreDebug /
robert_lp	0:eedb7d567a5d	1131
robert_lp	0:eedb7d567a5d	1132
robert_lp	0:eedb7d567a5d	1133	/**
robert_lp	0:eedb7d567a5d	1134	\ingroup CMSIS_core_register
robert_lp	0:eedb7d567a5d	1135	\defgroup CMSIS_core_bitfield Core register bit field macros
robert_lp	0:eedb7d567a5d	1136	\brief Macros for use with bit field definitions (xxx_Pos, xxx_Msk).
robert_lp	0:eedb7d567a5d	1137	@{
robert_lp	0:eedb7d567a5d	1138	*/
robert_lp	0:eedb7d567a5d	1139
robert_lp	0:eedb7d567a5d	1140	/**
robert_lp	0:eedb7d567a5d	1141	\brief Mask and shift a bit field value for use in a register bit range.
robert_lp	0:eedb7d567a5d	1142	\param[in] field Name of the register bit field.
robert_lp	0:eedb7d567a5d	1143	\param[in] value Value of the bit field. This parameter is interpreted as an uint32_t type.
robert_lp	0:eedb7d567a5d	1144	\return Masked and shifted value.
robert_lp	0:eedb7d567a5d	1145	*/
robert_lp	0:eedb7d567a5d	1146	#define _VAL2FLD(field, value) (((uint32_t)(value) << field ## _Pos) & field ## _Msk)
robert_lp	0:eedb7d567a5d	1147
robert_lp	0:eedb7d567a5d	1148	/**
robert_lp	0:eedb7d567a5d	1149	\brief Mask and shift a register value to extract a bit filed value.
robert_lp	0:eedb7d567a5d	1150	\param[in] field Name of the register bit field.
robert_lp	0:eedb7d567a5d	1151	\param[in] value Value of register. This parameter is interpreted as an uint32_t type.
robert_lp	0:eedb7d567a5d	1152	\return Masked and shifted bit field value.
robert_lp	0:eedb7d567a5d	1153	*/
robert_lp	0:eedb7d567a5d	1154	#define _FLD2VAL(field, value) (((uint32_t)(value) & field ## _Msk) >> field ## _Pos)
robert_lp	0:eedb7d567a5d	1155
robert_lp	0:eedb7d567a5d	1156	/@} end of group CMSIS_core_bitfield /
robert_lp	0:eedb7d567a5d	1157
robert_lp	0:eedb7d567a5d	1158
robert_lp	0:eedb7d567a5d	1159	/**
robert_lp	0:eedb7d567a5d	1160	\ingroup CMSIS_core_register
robert_lp	0:eedb7d567a5d	1161	\defgroup CMSIS_core_base Core Definitions
robert_lp	0:eedb7d567a5d	1162	\brief Definitions for base addresses, unions, and structures.
robert_lp	0:eedb7d567a5d	1163	@{
robert_lp	0:eedb7d567a5d	1164	*/
robert_lp	0:eedb7d567a5d	1165
robert_lp	0:eedb7d567a5d	1166	/* Memory mapping of Core Hardware */
robert_lp	0:eedb7d567a5d	1167	#define SCS_BASE (0xE000E000UL) /!< System Control Space Base Address /
robert_lp	0:eedb7d567a5d	1168	#define DWT_BASE (0xE0001000UL) /!< DWT Base Address /
robert_lp	0:eedb7d567a5d	1169	#define TPI_BASE (0xE0040000UL) /!< TPI Base Address /
robert_lp	0:eedb7d567a5d	1170	#define CoreDebug_BASE (0xE000EDF0UL) /!< Core Debug Base Address /
robert_lp	0:eedb7d567a5d	1171	#define SysTick_BASE (SCS_BASE + 0x0010UL) /!< SysTick Base Address /
robert_lp	0:eedb7d567a5d	1172	#define NVIC_BASE (SCS_BASE + 0x0100UL) /!< NVIC Base Address /
robert_lp	0:eedb7d567a5d	1173	#define SCB_BASE (SCS_BASE + 0x0D00UL) /!< System Control Block Base Address /
robert_lp	0:eedb7d567a5d	1174
robert_lp	0:eedb7d567a5d	1175
robert_lp	0:eedb7d567a5d	1176	#define SCB ((SCB_Type ) SCB_BASE ) /!< SCB configuration struct */
robert_lp	0:eedb7d567a5d	1177	#define SysTick ((SysTick_Type ) SysTick_BASE ) /!< SysTick configuration struct */
robert_lp	0:eedb7d567a5d	1178	#define NVIC ((NVIC_Type ) NVIC_BASE ) /!< NVIC configuration struct */
robert_lp	0:eedb7d567a5d	1179	#define DWT ((DWT_Type ) DWT_BASE ) /!< DWT configuration struct */
robert_lp	0:eedb7d567a5d	1180	#define TPI ((TPI_Type ) TPI_BASE ) /!< TPI configuration struct */
robert_lp	0:eedb7d567a5d	1181	#define CoreDebug ((CoreDebug_Type ) CoreDebug_BASE ) /!< Core Debug configuration struct */
robert_lp	0:eedb7d567a5d	1182
robert_lp	0:eedb7d567a5d	1183	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
robert_lp	0:eedb7d567a5d	1184	#define MPU_BASE (SCS_BASE + 0x0D90UL) /!< Memory Protection Unit /
robert_lp	0:eedb7d567a5d	1185	#define MPU ((MPU_Type ) MPU_BASE ) /!< Memory Protection Unit */
robert_lp	0:eedb7d567a5d	1186	#endif
robert_lp	0:eedb7d567a5d	1187
robert_lp	0:eedb7d567a5d	1188	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
robert_lp	0:eedb7d567a5d	1189	#define SAU_BASE (SCS_BASE + 0x0DD0UL) /!< Security Attribution Unit /
robert_lp	0:eedb7d567a5d	1190	#define SAU ((SAU_Type ) SAU_BASE ) /!< Security Attribution Unit */
robert_lp	0:eedb7d567a5d	1191	#endif
robert_lp	0:eedb7d567a5d	1192
robert_lp	0:eedb7d567a5d	1193	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
robert_lp	0:eedb7d567a5d	1194	#define SCS_BASE_NS (0xE002E000UL) /!< System Control Space Base Address (non-secure address space) /
robert_lp	0:eedb7d567a5d	1195	#define CoreDebug_BASE_NS (0xE002EDF0UL) /!< Core Debug Base Address (non-secure address space) /
robert_lp	0:eedb7d567a5d	1196	#define SysTick_BASE_NS (SCS_BASE_NS + 0x0010UL) /!< SysTick Base Address (non-secure address space) /
robert_lp	0:eedb7d567a5d	1197	#define NVIC_BASE_NS (SCS_BASE_NS + 0x0100UL) /!< NVIC Base Address (non-secure address space) /
robert_lp	0:eedb7d567a5d	1198	#define SCB_BASE_NS (SCS_BASE_NS + 0x0D00UL) /!< System Control Block Base Address (non-secure address space) /
robert_lp	0:eedb7d567a5d	1199
robert_lp	0:eedb7d567a5d	1200	#define SCB_NS ((SCB_Type ) SCB_BASE_NS ) /!< SCB configuration struct (non-secure address space) */
robert_lp	0:eedb7d567a5d	1201	#define SysTick_NS ((SysTick_Type ) SysTick_BASE_NS ) /!< SysTick configuration struct (non-secure address space) */
robert_lp	0:eedb7d567a5d	1202	#define NVIC_NS ((NVIC_Type ) NVIC_BASE_NS ) /!< NVIC configuration struct (non-secure address space) */
robert_lp	0:eedb7d567a5d	1203	#define CoreDebug_NS ((CoreDebug_Type ) CoreDebug_BASE_NS) /!< Core Debug configuration struct (non-secure address space) */
robert_lp	0:eedb7d567a5d	1204
robert_lp	0:eedb7d567a5d	1205	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
robert_lp	0:eedb7d567a5d	1206	#define MPU_BASE_NS (SCS_BASE_NS + 0x0D90UL) /!< Memory Protection Unit (non-secure address space) /
robert_lp	0:eedb7d567a5d	1207	#define MPU_NS ((MPU_Type ) MPU_BASE_NS ) /!< Memory Protection Unit (non-secure address space) */
robert_lp	0:eedb7d567a5d	1208	#endif
robert_lp	0:eedb7d567a5d	1209
robert_lp	0:eedb7d567a5d	1210	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
robert_lp	0:eedb7d567a5d	1211	/@} /
robert_lp	0:eedb7d567a5d	1212
robert_lp	0:eedb7d567a5d	1213
robert_lp	0:eedb7d567a5d	1214
robert_lp	0:eedb7d567a5d	1215	/*******************************************************************************
robert_lp	0:eedb7d567a5d	1216	* Hardware Abstraction Layer
robert_lp	0:eedb7d567a5d	1217	Core Function Interface contains:
robert_lp	0:eedb7d567a5d	1218	- Core NVIC Functions
robert_lp	0:eedb7d567a5d	1219	- Core SysTick Functions
robert_lp	0:eedb7d567a5d	1220	- Core Register Access Functions
robert_lp	0:eedb7d567a5d	1221	******************************************************************************/
robert_lp	0:eedb7d567a5d	1222	/**
robert_lp	0:eedb7d567a5d	1223	\defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
robert_lp	0:eedb7d567a5d	1224	*/
robert_lp	0:eedb7d567a5d	1225
robert_lp	0:eedb7d567a5d	1226
robert_lp	0:eedb7d567a5d	1227
robert_lp	0:eedb7d567a5d	1228	/* ########################## NVIC functions #################################### */
robert_lp	0:eedb7d567a5d	1229	/**
robert_lp	0:eedb7d567a5d	1230	\ingroup CMSIS_Core_FunctionInterface
robert_lp	0:eedb7d567a5d	1231	\defgroup CMSIS_Core_NVICFunctions NVIC Functions
robert_lp	0:eedb7d567a5d	1232	\brief Functions that manage interrupts and exceptions via the NVIC.
robert_lp	0:eedb7d567a5d	1233	@{
robert_lp	0:eedb7d567a5d	1234	*/
robert_lp	0:eedb7d567a5d	1235
robert_lp	0:eedb7d567a5d	1236	#ifdef CMSIS_NVIC_VIRTUAL
robert_lp	0:eedb7d567a5d	1237	#ifndef CMSIS_NVIC_VIRTUAL_HEADER_FILE
robert_lp	0:eedb7d567a5d	1238	#define CMSIS_NVIC_VIRTUAL_HEADER_FILE "cmsis_nvic_virtual.h"
robert_lp	0:eedb7d567a5d	1239	#endif
robert_lp	0:eedb7d567a5d	1240	#include CMSIS_NVIC_VIRTUAL_HEADER_FILE
robert_lp	0:eedb7d567a5d	1241	#else
robert_lp	0:eedb7d567a5d	1242	/#define NVIC_SetPriorityGrouping __NVIC_SetPriorityGrouping not available for Armv8-M Baseline /
robert_lp	0:eedb7d567a5d	1243	/#define NVIC_GetPriorityGrouping __NVIC_GetPriorityGrouping not available for Armv8-M Baseline /
robert_lp	0:eedb7d567a5d	1244	#define NVIC_EnableIRQ __NVIC_EnableIRQ
robert_lp	0:eedb7d567a5d	1245	#define NVIC_GetEnableIRQ __NVIC_GetEnableIRQ
robert_lp	0:eedb7d567a5d	1246	#define NVIC_DisableIRQ __NVIC_DisableIRQ
robert_lp	0:eedb7d567a5d	1247	#define NVIC_GetPendingIRQ __NVIC_GetPendingIRQ
robert_lp	0:eedb7d567a5d	1248	#define NVIC_SetPendingIRQ __NVIC_SetPendingIRQ
robert_lp	0:eedb7d567a5d	1249	#define NVIC_ClearPendingIRQ __NVIC_ClearPendingIRQ
robert_lp	0:eedb7d567a5d	1250	#define NVIC_GetActive __NVIC_GetActive
robert_lp	0:eedb7d567a5d	1251	#define NVIC_SetPriority __NVIC_SetPriority
robert_lp	0:eedb7d567a5d	1252	#define NVIC_GetPriority __NVIC_GetPriority
robert_lp	0:eedb7d567a5d	1253	#define NVIC_SystemReset __NVIC_SystemReset
robert_lp	0:eedb7d567a5d	1254	#endif /* CMSIS_NVIC_VIRTUAL */
robert_lp	0:eedb7d567a5d	1255
robert_lp	0:eedb7d567a5d	1256	#ifdef CMSIS_VECTAB_VIRTUAL
robert_lp	0:eedb7d567a5d	1257	#ifndef CMSIS_VECTAB_VIRTUAL_HEADER_FILE
robert_lp	0:eedb7d567a5d	1258	#define CMSIS_VECTAB_VIRTUAL_HEADER_FILE "cmsis_vectab_virtual.h"
robert_lp	0:eedb7d567a5d	1259	#endif
robert_lp	0:eedb7d567a5d	1260	#include CMSIS_VECTAB_VIRTUAL_HEADER_FILE
robert_lp	0:eedb7d567a5d	1261	#else
robert_lp	0:eedb7d567a5d	1262	#define NVIC_SetVector __NVIC_SetVector
robert_lp	0:eedb7d567a5d	1263	#define NVIC_GetVector __NVIC_GetVector
robert_lp	0:eedb7d567a5d	1264	#endif /* (CMSIS_VECTAB_VIRTUAL) */
robert_lp	0:eedb7d567a5d	1265
robert_lp	0:eedb7d567a5d	1266	#define NVIC_USER_IRQ_OFFSET 16
robert_lp	0:eedb7d567a5d	1267
robert_lp	0:eedb7d567a5d	1268
robert_lp	0:eedb7d567a5d	1269	/* Interrupt Priorities are WORD accessible only under Armv6-M */
robert_lp	0:eedb7d567a5d	1270	/* The following MACROS handle generation of the register offset and byte masks */
robert_lp	0:eedb7d567a5d	1271	#define _BIT_SHIFT(IRQn) ( ((((uint32_t)(int32_t)(IRQn)) ) & 0x03UL) * 8UL)
robert_lp	0:eedb7d567a5d	1272	#define _SHP_IDX(IRQn) ( (((((uint32_t)(int32_t)(IRQn)) & 0x0FUL)-8UL) >> 2UL) )
robert_lp	0:eedb7d567a5d	1273	#define _IP_IDX(IRQn) ( (((uint32_t)(int32_t)(IRQn)) >> 2UL) )
robert_lp	0:eedb7d567a5d	1274
robert_lp	0:eedb7d567a5d	1275
robert_lp	0:eedb7d567a5d	1276	/**
robert_lp	0:eedb7d567a5d	1277	\brief Enable Interrupt
robert_lp	0:eedb7d567a5d	1278	\details Enables a device specific interrupt in the NVIC interrupt controller.
robert_lp	0:eedb7d567a5d	1279	\param [in] IRQn Device specific interrupt number.
robert_lp	0:eedb7d567a5d	1280	\note IRQn must not be negative.
robert_lp	0:eedb7d567a5d	1281	*/
robert_lp	0:eedb7d567a5d	1282	__STATIC_INLINE void __NVIC_EnableIRQ(IRQn_Type IRQn)
robert_lp	0:eedb7d567a5d	1283	{
robert_lp	0:eedb7d567a5d	1284	if ((int32_t)(IRQn) >= 0)
robert_lp	0:eedb7d567a5d	1285	{
robert_lp	0:eedb7d567a5d	1286	NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
robert_lp	0:eedb7d567a5d	1287	}
robert_lp	0:eedb7d567a5d	1288	}
robert_lp	0:eedb7d567a5d	1289
robert_lp	0:eedb7d567a5d	1290
robert_lp	0:eedb7d567a5d	1291	/**
robert_lp	0:eedb7d567a5d	1292	\brief Get Interrupt Enable status
robert_lp	0:eedb7d567a5d	1293	\details Returns a device specific interrupt enable status from the NVIC interrupt controller.
robert_lp	0:eedb7d567a5d	1294	\param [in] IRQn Device specific interrupt number.
robert_lp	0:eedb7d567a5d	1295	\return 0 Interrupt is not enabled.
robert_lp	0:eedb7d567a5d	1296	\return 1 Interrupt is enabled.
robert_lp	0:eedb7d567a5d	1297	\note IRQn must not be negative.
robert_lp	0:eedb7d567a5d	1298	*/
robert_lp	0:eedb7d567a5d	1299	__STATIC_INLINE uint32_t __NVIC_GetEnableIRQ(IRQn_Type IRQn)
robert_lp	0:eedb7d567a5d	1300	{
robert_lp	0:eedb7d567a5d	1301	if ((int32_t)(IRQn) >= 0)
robert_lp	0:eedb7d567a5d	1302	{
robert_lp	0:eedb7d567a5d	1303	return((uint32_t)(((NVIC->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
robert_lp	0:eedb7d567a5d	1304	}
robert_lp	0:eedb7d567a5d	1305	else
robert_lp	0:eedb7d567a5d	1306	{
robert_lp	0:eedb7d567a5d	1307	return(0U);
robert_lp	0:eedb7d567a5d	1308	}
robert_lp	0:eedb7d567a5d	1309	}
robert_lp	0:eedb7d567a5d	1310
robert_lp	0:eedb7d567a5d	1311
robert_lp	0:eedb7d567a5d	1312	/**
robert_lp	0:eedb7d567a5d	1313	\brief Disable Interrupt
robert_lp	0:eedb7d567a5d	1314	\details Disables a device specific interrupt in the NVIC interrupt controller.
robert_lp	0:eedb7d567a5d	1315	\param [in] IRQn Device specific interrupt number.
robert_lp	0:eedb7d567a5d	1316	\note IRQn must not be negative.
robert_lp	0:eedb7d567a5d	1317	*/
robert_lp	0:eedb7d567a5d	1318	__STATIC_INLINE void __NVIC_DisableIRQ(IRQn_Type IRQn)
robert_lp	0:eedb7d567a5d	1319	{
robert_lp	0:eedb7d567a5d	1320	if ((int32_t)(IRQn) >= 0)
robert_lp	0:eedb7d567a5d	1321	{
robert_lp	0:eedb7d567a5d	1322	NVIC->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
robert_lp	0:eedb7d567a5d	1323	__DSB();
robert_lp	0:eedb7d567a5d	1324	__ISB();
robert_lp	0:eedb7d567a5d	1325	}
robert_lp	0:eedb7d567a5d	1326	}
robert_lp	0:eedb7d567a5d	1327
robert_lp	0:eedb7d567a5d	1328
robert_lp	0:eedb7d567a5d	1329	/**
robert_lp	0:eedb7d567a5d	1330	\brief Get Pending Interrupt
robert_lp	0:eedb7d567a5d	1331	\details Reads the NVIC pending register and returns the pending bit for the specified device specific interrupt.
robert_lp	0:eedb7d567a5d	1332	\param [in] IRQn Device specific interrupt number.
robert_lp	0:eedb7d567a5d	1333	\return 0 Interrupt status is not pending.
robert_lp	0:eedb7d567a5d	1334	\return 1 Interrupt status is pending.
robert_lp	0:eedb7d567a5d	1335	\note IRQn must not be negative.
robert_lp	0:eedb7d567a5d	1336	*/
robert_lp	0:eedb7d567a5d	1337	__STATIC_INLINE uint32_t __NVIC_GetPendingIRQ(IRQn_Type IRQn)
robert_lp	0:eedb7d567a5d	1338	{
robert_lp	0:eedb7d567a5d	1339	if ((int32_t)(IRQn) >= 0)
robert_lp	0:eedb7d567a5d	1340	{
robert_lp	0:eedb7d567a5d	1341	return((uint32_t)(((NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
robert_lp	0:eedb7d567a5d	1342	}
robert_lp	0:eedb7d567a5d	1343	else
robert_lp	0:eedb7d567a5d	1344	{
robert_lp	0:eedb7d567a5d	1345	return(0U);
robert_lp	0:eedb7d567a5d	1346	}
robert_lp	0:eedb7d567a5d	1347	}
robert_lp	0:eedb7d567a5d	1348
robert_lp	0:eedb7d567a5d	1349
robert_lp	0:eedb7d567a5d	1350	/**
robert_lp	0:eedb7d567a5d	1351	\brief Set Pending Interrupt
robert_lp	0:eedb7d567a5d	1352	\details Sets the pending bit of a device specific interrupt in the NVIC pending register.
robert_lp	0:eedb7d567a5d	1353	\param [in] IRQn Device specific interrupt number.
robert_lp	0:eedb7d567a5d	1354	\note IRQn must not be negative.
robert_lp	0:eedb7d567a5d	1355	*/
robert_lp	0:eedb7d567a5d	1356	__STATIC_INLINE void __NVIC_SetPendingIRQ(IRQn_Type IRQn)
robert_lp	0:eedb7d567a5d	1357	{
robert_lp	0:eedb7d567a5d	1358	if ((int32_t)(IRQn) >= 0)
robert_lp	0:eedb7d567a5d	1359	{
robert_lp	0:eedb7d567a5d	1360	NVIC->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
robert_lp	0:eedb7d567a5d	1361	}
robert_lp	0:eedb7d567a5d	1362	}
robert_lp	0:eedb7d567a5d	1363
robert_lp	0:eedb7d567a5d	1364
robert_lp	0:eedb7d567a5d	1365	/**
robert_lp	0:eedb7d567a5d	1366	\brief Clear Pending Interrupt
robert_lp	0:eedb7d567a5d	1367	\details Clears the pending bit of a device specific interrupt in the NVIC pending register.
robert_lp	0:eedb7d567a5d	1368	\param [in] IRQn Device specific interrupt number.
robert_lp	0:eedb7d567a5d	1369	\note IRQn must not be negative.
robert_lp	0:eedb7d567a5d	1370	*/
robert_lp	0:eedb7d567a5d	1371	__STATIC_INLINE void __NVIC_ClearPendingIRQ(IRQn_Type IRQn)
robert_lp	0:eedb7d567a5d	1372	{
robert_lp	0:eedb7d567a5d	1373	if ((int32_t)(IRQn) >= 0)
robert_lp	0:eedb7d567a5d	1374	{
robert_lp	0:eedb7d567a5d	1375	NVIC->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
robert_lp	0:eedb7d567a5d	1376	}
robert_lp	0:eedb7d567a5d	1377	}
robert_lp	0:eedb7d567a5d	1378
robert_lp	0:eedb7d567a5d	1379
robert_lp	0:eedb7d567a5d	1380	/**
robert_lp	0:eedb7d567a5d	1381	\brief Get Active Interrupt
robert_lp	0:eedb7d567a5d	1382	\details Reads the active register in the NVIC and returns the active bit for the device specific interrupt.
robert_lp	0:eedb7d567a5d	1383	\param [in] IRQn Device specific interrupt number.
robert_lp	0:eedb7d567a5d	1384	\return 0 Interrupt status is not active.
robert_lp	0:eedb7d567a5d	1385	\return 1 Interrupt status is active.
robert_lp	0:eedb7d567a5d	1386	\note IRQn must not be negative.
robert_lp	0:eedb7d567a5d	1387	*/
robert_lp	0:eedb7d567a5d	1388	__STATIC_INLINE uint32_t __NVIC_GetActive(IRQn_Type IRQn)
robert_lp	0:eedb7d567a5d	1389	{
robert_lp	0:eedb7d567a5d	1390	if ((int32_t)(IRQn) >= 0)
robert_lp	0:eedb7d567a5d	1391	{
robert_lp	0:eedb7d567a5d	1392	return((uint32_t)(((NVIC->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
robert_lp	0:eedb7d567a5d	1393	}
robert_lp	0:eedb7d567a5d	1394	else
robert_lp	0:eedb7d567a5d	1395	{
robert_lp	0:eedb7d567a5d	1396	return(0U);
robert_lp	0:eedb7d567a5d	1397	}
robert_lp	0:eedb7d567a5d	1398	}
robert_lp	0:eedb7d567a5d	1399
robert_lp	0:eedb7d567a5d	1400
robert_lp	0:eedb7d567a5d	1401	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
robert_lp	0:eedb7d567a5d	1402	/**
robert_lp	0:eedb7d567a5d	1403	\brief Get Interrupt Target State
robert_lp	0:eedb7d567a5d	1404	\details Reads the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
robert_lp	0:eedb7d567a5d	1405	\param [in] IRQn Device specific interrupt number.
robert_lp	0:eedb7d567a5d	1406	\return 0 if interrupt is assigned to Secure
robert_lp	0:eedb7d567a5d	1407	\return 1 if interrupt is assigned to Non Secure
robert_lp	0:eedb7d567a5d	1408	\note IRQn must not be negative.
robert_lp	0:eedb7d567a5d	1409	*/
robert_lp	0:eedb7d567a5d	1410	__STATIC_INLINE uint32_t NVIC_GetTargetState(IRQn_Type IRQn)
robert_lp	0:eedb7d567a5d	1411	{
robert_lp	0:eedb7d567a5d	1412	if ((int32_t)(IRQn) >= 0)
robert_lp	0:eedb7d567a5d	1413	{
robert_lp	0:eedb7d567a5d	1414	return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
robert_lp	0:eedb7d567a5d	1415	}
robert_lp	0:eedb7d567a5d	1416	else
robert_lp	0:eedb7d567a5d	1417	{
robert_lp	0:eedb7d567a5d	1418	return(0U);
robert_lp	0:eedb7d567a5d	1419	}
robert_lp	0:eedb7d567a5d	1420	}
robert_lp	0:eedb7d567a5d	1421
robert_lp	0:eedb7d567a5d	1422
robert_lp	0:eedb7d567a5d	1423	/**
robert_lp	0:eedb7d567a5d	1424	\brief Set Interrupt Target State
robert_lp	0:eedb7d567a5d	1425	\details Sets the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
robert_lp	0:eedb7d567a5d	1426	\param [in] IRQn Device specific interrupt number.
robert_lp	0:eedb7d567a5d	1427	\return 0 if interrupt is assigned to Secure
robert_lp	0:eedb7d567a5d	1428	1 if interrupt is assigned to Non Secure
robert_lp	0:eedb7d567a5d	1429	\note IRQn must not be negative.
robert_lp	0:eedb7d567a5d	1430	*/
robert_lp	0:eedb7d567a5d	1431	__STATIC_INLINE uint32_t NVIC_SetTargetState(IRQn_Type IRQn)
robert_lp	0:eedb7d567a5d	1432	{
robert_lp	0:eedb7d567a5d	1433	if ((int32_t)(IRQn) >= 0)
robert_lp	0:eedb7d567a5d	1434	{
robert_lp	0:eedb7d567a5d	1435	NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] \|= ((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
robert_lp	0:eedb7d567a5d	1436	return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
robert_lp	0:eedb7d567a5d	1437	}
robert_lp	0:eedb7d567a5d	1438	else
robert_lp	0:eedb7d567a5d	1439	{
robert_lp	0:eedb7d567a5d	1440	return(0U);
robert_lp	0:eedb7d567a5d	1441	}
robert_lp	0:eedb7d567a5d	1442	}
robert_lp	0:eedb7d567a5d	1443
robert_lp	0:eedb7d567a5d	1444
robert_lp	0:eedb7d567a5d	1445	/**
robert_lp	0:eedb7d567a5d	1446	\brief Clear Interrupt Target State
robert_lp	0:eedb7d567a5d	1447	\details Clears the interrupt target field in the NVIC and returns the interrupt target bit for the device specific interrupt.
robert_lp	0:eedb7d567a5d	1448	\param [in] IRQn Device specific interrupt number.
robert_lp	0:eedb7d567a5d	1449	\return 0 if interrupt is assigned to Secure
robert_lp	0:eedb7d567a5d	1450	1 if interrupt is assigned to Non Secure
robert_lp	0:eedb7d567a5d	1451	\note IRQn must not be negative.
robert_lp	0:eedb7d567a5d	1452	*/
robert_lp	0:eedb7d567a5d	1453	__STATIC_INLINE uint32_t NVIC_ClearTargetState(IRQn_Type IRQn)
robert_lp	0:eedb7d567a5d	1454	{
robert_lp	0:eedb7d567a5d	1455	if ((int32_t)(IRQn) >= 0)
robert_lp	0:eedb7d567a5d	1456	{
robert_lp	0:eedb7d567a5d	1457	NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] &= ~((uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL)));
robert_lp	0:eedb7d567a5d	1458	return((uint32_t)(((NVIC->ITNS[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
robert_lp	0:eedb7d567a5d	1459	}
robert_lp	0:eedb7d567a5d	1460	else
robert_lp	0:eedb7d567a5d	1461	{
robert_lp	0:eedb7d567a5d	1462	return(0U);
robert_lp	0:eedb7d567a5d	1463	}
robert_lp	0:eedb7d567a5d	1464	}
robert_lp	0:eedb7d567a5d	1465	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
robert_lp	0:eedb7d567a5d	1466
robert_lp	0:eedb7d567a5d	1467
robert_lp	0:eedb7d567a5d	1468	/**
robert_lp	0:eedb7d567a5d	1469	\brief Set Interrupt Priority
robert_lp	0:eedb7d567a5d	1470	\details Sets the priority of a device specific interrupt or a processor exception.
robert_lp	0:eedb7d567a5d	1471	The interrupt number can be positive to specify a device specific interrupt,
robert_lp	0:eedb7d567a5d	1472	or negative to specify a processor exception.
robert_lp	0:eedb7d567a5d	1473	\param [in] IRQn Interrupt number.
robert_lp	0:eedb7d567a5d	1474	\param [in] priority Priority to set.
robert_lp	0:eedb7d567a5d	1475	\note The priority cannot be set for every processor exception.
robert_lp	0:eedb7d567a5d	1476	*/
robert_lp	0:eedb7d567a5d	1477	__STATIC_INLINE void __NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
robert_lp	0:eedb7d567a5d	1478	{
robert_lp	0:eedb7d567a5d	1479	if ((int32_t)(IRQn) >= 0)
robert_lp	0:eedb7d567a5d	1480	{
robert_lp	0:eedb7d567a5d	1481	NVIC->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) \|
robert_lp	0:eedb7d567a5d	1482	(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
robert_lp	0:eedb7d567a5d	1483	}
robert_lp	0:eedb7d567a5d	1484	else
robert_lp	0:eedb7d567a5d	1485	{
robert_lp	0:eedb7d567a5d	1486	SCB->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) \|
robert_lp	0:eedb7d567a5d	1487	(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
robert_lp	0:eedb7d567a5d	1488	}
robert_lp	0:eedb7d567a5d	1489	}
robert_lp	0:eedb7d567a5d	1490
robert_lp	0:eedb7d567a5d	1491
robert_lp	0:eedb7d567a5d	1492	/**
robert_lp	0:eedb7d567a5d	1493	\brief Get Interrupt Priority
robert_lp	0:eedb7d567a5d	1494	\details Reads the priority of a device specific interrupt or a processor exception.
robert_lp	0:eedb7d567a5d	1495	The interrupt number can be positive to specify a device specific interrupt,
robert_lp	0:eedb7d567a5d	1496	or negative to specify a processor exception.
robert_lp	0:eedb7d567a5d	1497	\param [in] IRQn Interrupt number.
robert_lp	0:eedb7d567a5d	1498	\return Interrupt Priority.
robert_lp	0:eedb7d567a5d	1499	Value is aligned automatically to the implemented priority bits of the microcontroller.
robert_lp	0:eedb7d567a5d	1500	*/
robert_lp	0:eedb7d567a5d	1501	__STATIC_INLINE uint32_t __NVIC_GetPriority(IRQn_Type IRQn)
robert_lp	0:eedb7d567a5d	1502	{
robert_lp	0:eedb7d567a5d	1503
robert_lp	0:eedb7d567a5d	1504	if ((int32_t)(IRQn) >= 0)
robert_lp	0:eedb7d567a5d	1505	{
robert_lp	0:eedb7d567a5d	1506	return((uint32_t)(((NVIC->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
robert_lp	0:eedb7d567a5d	1507	}
robert_lp	0:eedb7d567a5d	1508	else
robert_lp	0:eedb7d567a5d	1509	{
robert_lp	0:eedb7d567a5d	1510	return((uint32_t)(((SCB->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
robert_lp	0:eedb7d567a5d	1511	}
robert_lp	0:eedb7d567a5d	1512	}
robert_lp	0:eedb7d567a5d	1513
robert_lp	0:eedb7d567a5d	1514
robert_lp	0:eedb7d567a5d	1515	/**
robert_lp	0:eedb7d567a5d	1516	\brief Set Interrupt Vector
robert_lp	0:eedb7d567a5d	1517	\details Sets an interrupt vector in SRAM based interrupt vector table.
robert_lp	0:eedb7d567a5d	1518	The interrupt number can be positive to specify a device specific interrupt,
robert_lp	0:eedb7d567a5d	1519	or negative to specify a processor exception.
robert_lp	0:eedb7d567a5d	1520	VTOR must been relocated to SRAM before.
robert_lp	0:eedb7d567a5d	1521	If VTOR is not present address 0 must be mapped to SRAM.
robert_lp	0:eedb7d567a5d	1522	\param [in] IRQn Interrupt number
robert_lp	0:eedb7d567a5d	1523	\param [in] vector Address of interrupt handler function
robert_lp	0:eedb7d567a5d	1524	*/
robert_lp	0:eedb7d567a5d	1525	__STATIC_INLINE void __NVIC_SetVector(IRQn_Type IRQn, uint32_t vector)
robert_lp	0:eedb7d567a5d	1526	{
robert_lp	0:eedb7d567a5d	1527	#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
robert_lp	0:eedb7d567a5d	1528	uint32_t vectors = (uint32_t )SCB->VTOR;
robert_lp	0:eedb7d567a5d	1529	#else
robert_lp	0:eedb7d567a5d	1530	uint32_t vectors = (uint32_t )0x0U;
robert_lp	0:eedb7d567a5d	1531	#endif
robert_lp	0:eedb7d567a5d	1532	vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET] = vector;
robert_lp	0:eedb7d567a5d	1533	}
robert_lp	0:eedb7d567a5d	1534
robert_lp	0:eedb7d567a5d	1535
robert_lp	0:eedb7d567a5d	1536	/**
robert_lp	0:eedb7d567a5d	1537	\brief Get Interrupt Vector
robert_lp	0:eedb7d567a5d	1538	\details Reads an interrupt vector from interrupt vector table.
robert_lp	0:eedb7d567a5d	1539	The interrupt number can be positive to specify a device specific interrupt,
robert_lp	0:eedb7d567a5d	1540	or negative to specify a processor exception.
robert_lp	0:eedb7d567a5d	1541	\param [in] IRQn Interrupt number.
robert_lp	0:eedb7d567a5d	1542	\return Address of interrupt handler function
robert_lp	0:eedb7d567a5d	1543	*/
robert_lp	0:eedb7d567a5d	1544	__STATIC_INLINE uint32_t __NVIC_GetVector(IRQn_Type IRQn)
robert_lp	0:eedb7d567a5d	1545	{
robert_lp	0:eedb7d567a5d	1546	#if defined (__VTOR_PRESENT) && (__VTOR_PRESENT == 1U)
robert_lp	0:eedb7d567a5d	1547	uint32_t vectors = (uint32_t )SCB->VTOR;
robert_lp	0:eedb7d567a5d	1548	#else
robert_lp	0:eedb7d567a5d	1549	uint32_t vectors = (uint32_t )0x0U;
robert_lp	0:eedb7d567a5d	1550	#endif
robert_lp	0:eedb7d567a5d	1551	return vectors[(int32_t)IRQn + NVIC_USER_IRQ_OFFSET];
robert_lp	0:eedb7d567a5d	1552	}
robert_lp	0:eedb7d567a5d	1553
robert_lp	0:eedb7d567a5d	1554
robert_lp	0:eedb7d567a5d	1555	/**
robert_lp	0:eedb7d567a5d	1556	\brief System Reset
robert_lp	0:eedb7d567a5d	1557	\details Initiates a system reset request to reset the MCU.
robert_lp	0:eedb7d567a5d	1558	*/
robert_lp	0:eedb7d567a5d	1559	__STATIC_INLINE void __NVIC_SystemReset(void)
robert_lp	0:eedb7d567a5d	1560	{
robert_lp	0:eedb7d567a5d	1561	__DSB(); /* Ensure all outstanding memory accesses included
robert_lp	0:eedb7d567a5d	1562	buffered write are completed before reset */
robert_lp	0:eedb7d567a5d	1563	SCB->AIRCR = ((0x5FAUL << SCB_AIRCR_VECTKEY_Pos) \|
robert_lp	0:eedb7d567a5d	1564	SCB_AIRCR_SYSRESETREQ_Msk);
robert_lp	0:eedb7d567a5d	1565	__DSB(); /* Ensure completion of memory access */
robert_lp	0:eedb7d567a5d	1566
robert_lp	0:eedb7d567a5d	1567	for(;;) /* wait until reset */
robert_lp	0:eedb7d567a5d	1568	{
robert_lp	0:eedb7d567a5d	1569	__NOP();
robert_lp	0:eedb7d567a5d	1570	}
robert_lp	0:eedb7d567a5d	1571	}
robert_lp	0:eedb7d567a5d	1572
robert_lp	0:eedb7d567a5d	1573	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
robert_lp	0:eedb7d567a5d	1574	/**
robert_lp	0:eedb7d567a5d	1575	\brief Enable Interrupt (non-secure)
robert_lp	0:eedb7d567a5d	1576	\details Enables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
robert_lp	0:eedb7d567a5d	1577	\param [in] IRQn Device specific interrupt number.
robert_lp	0:eedb7d567a5d	1578	\note IRQn must not be negative.
robert_lp	0:eedb7d567a5d	1579	*/
robert_lp	0:eedb7d567a5d	1580	__STATIC_INLINE void TZ_NVIC_EnableIRQ_NS(IRQn_Type IRQn)
robert_lp	0:eedb7d567a5d	1581	{
robert_lp	0:eedb7d567a5d	1582	if ((int32_t)(IRQn) >= 0)
robert_lp	0:eedb7d567a5d	1583	{
robert_lp	0:eedb7d567a5d	1584	NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
robert_lp	0:eedb7d567a5d	1585	}
robert_lp	0:eedb7d567a5d	1586	}
robert_lp	0:eedb7d567a5d	1587
robert_lp	0:eedb7d567a5d	1588
robert_lp	0:eedb7d567a5d	1589	/**
robert_lp	0:eedb7d567a5d	1590	\brief Get Interrupt Enable status (non-secure)
robert_lp	0:eedb7d567a5d	1591	\details Returns a device specific interrupt enable status from the non-secure NVIC interrupt controller when in secure state.
robert_lp	0:eedb7d567a5d	1592	\param [in] IRQn Device specific interrupt number.
robert_lp	0:eedb7d567a5d	1593	\return 0 Interrupt is not enabled.
robert_lp	0:eedb7d567a5d	1594	\return 1 Interrupt is enabled.
robert_lp	0:eedb7d567a5d	1595	\note IRQn must not be negative.
robert_lp	0:eedb7d567a5d	1596	*/
robert_lp	0:eedb7d567a5d	1597	__STATIC_INLINE uint32_t TZ_NVIC_GetEnableIRQ_NS(IRQn_Type IRQn)
robert_lp	0:eedb7d567a5d	1598	{
robert_lp	0:eedb7d567a5d	1599	if ((int32_t)(IRQn) >= 0)
robert_lp	0:eedb7d567a5d	1600	{
robert_lp	0:eedb7d567a5d	1601	return((uint32_t)(((NVIC_NS->ISER[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
robert_lp	0:eedb7d567a5d	1602	}
robert_lp	0:eedb7d567a5d	1603	else
robert_lp	0:eedb7d567a5d	1604	{
robert_lp	0:eedb7d567a5d	1605	return(0U);
robert_lp	0:eedb7d567a5d	1606	}
robert_lp	0:eedb7d567a5d	1607	}
robert_lp	0:eedb7d567a5d	1608
robert_lp	0:eedb7d567a5d	1609
robert_lp	0:eedb7d567a5d	1610	/**
robert_lp	0:eedb7d567a5d	1611	\brief Disable Interrupt (non-secure)
robert_lp	0:eedb7d567a5d	1612	\details Disables a device specific interrupt in the non-secure NVIC interrupt controller when in secure state.
robert_lp	0:eedb7d567a5d	1613	\param [in] IRQn Device specific interrupt number.
robert_lp	0:eedb7d567a5d	1614	\note IRQn must not be negative.
robert_lp	0:eedb7d567a5d	1615	*/
robert_lp	0:eedb7d567a5d	1616	__STATIC_INLINE void TZ_NVIC_DisableIRQ_NS(IRQn_Type IRQn)
robert_lp	0:eedb7d567a5d	1617	{
robert_lp	0:eedb7d567a5d	1618	if ((int32_t)(IRQn) >= 0)
robert_lp	0:eedb7d567a5d	1619	{
robert_lp	0:eedb7d567a5d	1620	NVIC_NS->ICER[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
robert_lp	0:eedb7d567a5d	1621	}
robert_lp	0:eedb7d567a5d	1622	}
robert_lp	0:eedb7d567a5d	1623
robert_lp	0:eedb7d567a5d	1624
robert_lp	0:eedb7d567a5d	1625	/**
robert_lp	0:eedb7d567a5d	1626	\brief Get Pending Interrupt (non-secure)
robert_lp	0:eedb7d567a5d	1627	\details Reads the NVIC pending register in the non-secure NVIC when in secure state and returns the pending bit for the specified device specific interrupt.
robert_lp	0:eedb7d567a5d	1628	\param [in] IRQn Device specific interrupt number.
robert_lp	0:eedb7d567a5d	1629	\return 0 Interrupt status is not pending.
robert_lp	0:eedb7d567a5d	1630	\return 1 Interrupt status is pending.
robert_lp	0:eedb7d567a5d	1631	\note IRQn must not be negative.
robert_lp	0:eedb7d567a5d	1632	*/
robert_lp	0:eedb7d567a5d	1633	__STATIC_INLINE uint32_t TZ_NVIC_GetPendingIRQ_NS(IRQn_Type IRQn)
robert_lp	0:eedb7d567a5d	1634	{
robert_lp	0:eedb7d567a5d	1635	if ((int32_t)(IRQn) >= 0)
robert_lp	0:eedb7d567a5d	1636	{
robert_lp	0:eedb7d567a5d	1637	return((uint32_t)(((NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
robert_lp	0:eedb7d567a5d	1638	}
robert_lp	0:eedb7d567a5d	1639	else
robert_lp	0:eedb7d567a5d	1640	{
robert_lp	0:eedb7d567a5d	1641	return(0U);
robert_lp	0:eedb7d567a5d	1642	}
robert_lp	0:eedb7d567a5d	1643	}
robert_lp	0:eedb7d567a5d	1644
robert_lp	0:eedb7d567a5d	1645
robert_lp	0:eedb7d567a5d	1646	/**
robert_lp	0:eedb7d567a5d	1647	\brief Set Pending Interrupt (non-secure)
robert_lp	0:eedb7d567a5d	1648	\details Sets the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
robert_lp	0:eedb7d567a5d	1649	\param [in] IRQn Device specific interrupt number.
robert_lp	0:eedb7d567a5d	1650	\note IRQn must not be negative.
robert_lp	0:eedb7d567a5d	1651	*/
robert_lp	0:eedb7d567a5d	1652	__STATIC_INLINE void TZ_NVIC_SetPendingIRQ_NS(IRQn_Type IRQn)
robert_lp	0:eedb7d567a5d	1653	{
robert_lp	0:eedb7d567a5d	1654	if ((int32_t)(IRQn) >= 0)
robert_lp	0:eedb7d567a5d	1655	{
robert_lp	0:eedb7d567a5d	1656	NVIC_NS->ISPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
robert_lp	0:eedb7d567a5d	1657	}
robert_lp	0:eedb7d567a5d	1658	}
robert_lp	0:eedb7d567a5d	1659
robert_lp	0:eedb7d567a5d	1660
robert_lp	0:eedb7d567a5d	1661	/**
robert_lp	0:eedb7d567a5d	1662	\brief Clear Pending Interrupt (non-secure)
robert_lp	0:eedb7d567a5d	1663	\details Clears the pending bit of a device specific interrupt in the non-secure NVIC pending register when in secure state.
robert_lp	0:eedb7d567a5d	1664	\param [in] IRQn Device specific interrupt number.
robert_lp	0:eedb7d567a5d	1665	\note IRQn must not be negative.
robert_lp	0:eedb7d567a5d	1666	*/
robert_lp	0:eedb7d567a5d	1667	__STATIC_INLINE void TZ_NVIC_ClearPendingIRQ_NS(IRQn_Type IRQn)
robert_lp	0:eedb7d567a5d	1668	{
robert_lp	0:eedb7d567a5d	1669	if ((int32_t)(IRQn) >= 0)
robert_lp	0:eedb7d567a5d	1670	{
robert_lp	0:eedb7d567a5d	1671	NVIC_NS->ICPR[(((uint32_t)IRQn) >> 5UL)] = (uint32_t)(1UL << (((uint32_t)IRQn) & 0x1FUL));
robert_lp	0:eedb7d567a5d	1672	}
robert_lp	0:eedb7d567a5d	1673	}
robert_lp	0:eedb7d567a5d	1674
robert_lp	0:eedb7d567a5d	1675
robert_lp	0:eedb7d567a5d	1676	/**
robert_lp	0:eedb7d567a5d	1677	\brief Get Active Interrupt (non-secure)
robert_lp	0:eedb7d567a5d	1678	\details Reads the active register in non-secure NVIC when in secure state and returns the active bit for the device specific interrupt.
robert_lp	0:eedb7d567a5d	1679	\param [in] IRQn Device specific interrupt number.
robert_lp	0:eedb7d567a5d	1680	\return 0 Interrupt status is not active.
robert_lp	0:eedb7d567a5d	1681	\return 1 Interrupt status is active.
robert_lp	0:eedb7d567a5d	1682	\note IRQn must not be negative.
robert_lp	0:eedb7d567a5d	1683	*/
robert_lp	0:eedb7d567a5d	1684	__STATIC_INLINE uint32_t TZ_NVIC_GetActive_NS(IRQn_Type IRQn)
robert_lp	0:eedb7d567a5d	1685	{
robert_lp	0:eedb7d567a5d	1686	if ((int32_t)(IRQn) >= 0)
robert_lp	0:eedb7d567a5d	1687	{
robert_lp	0:eedb7d567a5d	1688	return((uint32_t)(((NVIC_NS->IABR[(((uint32_t)IRQn) >> 5UL)] & (1UL << (((uint32_t)IRQn) & 0x1FUL))) != 0UL) ? 1UL : 0UL));
robert_lp	0:eedb7d567a5d	1689	}
robert_lp	0:eedb7d567a5d	1690	else
robert_lp	0:eedb7d567a5d	1691	{
robert_lp	0:eedb7d567a5d	1692	return(0U);
robert_lp	0:eedb7d567a5d	1693	}
robert_lp	0:eedb7d567a5d	1694	}
robert_lp	0:eedb7d567a5d	1695
robert_lp	0:eedb7d567a5d	1696
robert_lp	0:eedb7d567a5d	1697	/**
robert_lp	0:eedb7d567a5d	1698	\brief Set Interrupt Priority (non-secure)
robert_lp	0:eedb7d567a5d	1699	\details Sets the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
robert_lp	0:eedb7d567a5d	1700	The interrupt number can be positive to specify a device specific interrupt,
robert_lp	0:eedb7d567a5d	1701	or negative to specify a processor exception.
robert_lp	0:eedb7d567a5d	1702	\param [in] IRQn Interrupt number.
robert_lp	0:eedb7d567a5d	1703	\param [in] priority Priority to set.
robert_lp	0:eedb7d567a5d	1704	\note The priority cannot be set for every non-secure processor exception.
robert_lp	0:eedb7d567a5d	1705	*/
robert_lp	0:eedb7d567a5d	1706	__STATIC_INLINE void TZ_NVIC_SetPriority_NS(IRQn_Type IRQn, uint32_t priority)
robert_lp	0:eedb7d567a5d	1707	{
robert_lp	0:eedb7d567a5d	1708	if ((int32_t)(IRQn) >= 0)
robert_lp	0:eedb7d567a5d	1709	{
robert_lp	0:eedb7d567a5d	1710	NVIC_NS->IPR[_IP_IDX(IRQn)] = ((uint32_t)(NVIC_NS->IPR[_IP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) \|
robert_lp	0:eedb7d567a5d	1711	(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
robert_lp	0:eedb7d567a5d	1712	}
robert_lp	0:eedb7d567a5d	1713	else
robert_lp	0:eedb7d567a5d	1714	{
robert_lp	0:eedb7d567a5d	1715	SCB_NS->SHPR[_SHP_IDX(IRQn)] = ((uint32_t)(SCB_NS->SHPR[_SHP_IDX(IRQn)] & ~(0xFFUL << _BIT_SHIFT(IRQn))) \|
robert_lp	0:eedb7d567a5d	1716	(((priority << (8U - __NVIC_PRIO_BITS)) & (uint32_t)0xFFUL) << _BIT_SHIFT(IRQn)));
robert_lp	0:eedb7d567a5d	1717	}
robert_lp	0:eedb7d567a5d	1718	}
robert_lp	0:eedb7d567a5d	1719
robert_lp	0:eedb7d567a5d	1720
robert_lp	0:eedb7d567a5d	1721	/**
robert_lp	0:eedb7d567a5d	1722	\brief Get Interrupt Priority (non-secure)
robert_lp	0:eedb7d567a5d	1723	\details Reads the priority of a non-secure device specific interrupt or a non-secure processor exception when in secure state.
robert_lp	0:eedb7d567a5d	1724	The interrupt number can be positive to specify a device specific interrupt,
robert_lp	0:eedb7d567a5d	1725	or negative to specify a processor exception.
robert_lp	0:eedb7d567a5d	1726	\param [in] IRQn Interrupt number.
robert_lp	0:eedb7d567a5d	1727	\return Interrupt Priority. Value is aligned automatically to the implemented priority bits of the microcontroller.
robert_lp	0:eedb7d567a5d	1728	*/
robert_lp	0:eedb7d567a5d	1729	__STATIC_INLINE uint32_t TZ_NVIC_GetPriority_NS(IRQn_Type IRQn)
robert_lp	0:eedb7d567a5d	1730	{
robert_lp	0:eedb7d567a5d	1731
robert_lp	0:eedb7d567a5d	1732	if ((int32_t)(IRQn) >= 0)
robert_lp	0:eedb7d567a5d	1733	{
robert_lp	0:eedb7d567a5d	1734	return((uint32_t)(((NVIC_NS->IPR[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
robert_lp	0:eedb7d567a5d	1735	}
robert_lp	0:eedb7d567a5d	1736	else
robert_lp	0:eedb7d567a5d	1737	{
robert_lp	0:eedb7d567a5d	1738	return((uint32_t)(((SCB_NS->SHPR[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) & (uint32_t)0xFFUL) >> (8U - __NVIC_PRIO_BITS)));
robert_lp	0:eedb7d567a5d	1739	}
robert_lp	0:eedb7d567a5d	1740	}
robert_lp	0:eedb7d567a5d	1741	#endif /* defined (__ARM_FEATURE_CMSE) &&(__ARM_FEATURE_CMSE == 3U) */
robert_lp	0:eedb7d567a5d	1742
robert_lp	0:eedb7d567a5d	1743	/@} end of CMSIS_Core_NVICFunctions /
robert_lp	0:eedb7d567a5d	1744
robert_lp	0:eedb7d567a5d	1745	/* ########################## MPU functions #################################### */
robert_lp	0:eedb7d567a5d	1746
robert_lp	0:eedb7d567a5d	1747	#if defined (__MPU_PRESENT) && (__MPU_PRESENT == 1U)
robert_lp	0:eedb7d567a5d	1748
robert_lp	0:eedb7d567a5d	1749	#include "mpu_armv8.h"
robert_lp	0:eedb7d567a5d	1750
robert_lp	0:eedb7d567a5d	1751	#endif
robert_lp	0:eedb7d567a5d	1752
robert_lp	0:eedb7d567a5d	1753	/* ########################## FPU functions #################################### */
robert_lp	0:eedb7d567a5d	1754	/**
robert_lp	0:eedb7d567a5d	1755	\ingroup CMSIS_Core_FunctionInterface
robert_lp	0:eedb7d567a5d	1756	\defgroup CMSIS_Core_FpuFunctions FPU Functions
robert_lp	0:eedb7d567a5d	1757	\brief Function that provides FPU type.
robert_lp	0:eedb7d567a5d	1758	@{
robert_lp	0:eedb7d567a5d	1759	*/
robert_lp	0:eedb7d567a5d	1760
robert_lp	0:eedb7d567a5d	1761	/**
robert_lp	0:eedb7d567a5d	1762	\brief get FPU type
robert_lp	0:eedb7d567a5d	1763	\details returns the FPU type
robert_lp	0:eedb7d567a5d	1764	\returns
robert_lp	0:eedb7d567a5d	1765	- \b 0: No FPU
robert_lp	0:eedb7d567a5d	1766	- \b 1: Single precision FPU
robert_lp	0:eedb7d567a5d	1767	- \b 2: Double + Single precision FPU
robert_lp	0:eedb7d567a5d	1768	*/
robert_lp	0:eedb7d567a5d	1769	__STATIC_INLINE uint32_t SCB_GetFPUType(void)
robert_lp	0:eedb7d567a5d	1770	{
robert_lp	0:eedb7d567a5d	1771	return 0U; /* No FPU */
robert_lp	0:eedb7d567a5d	1772	}
robert_lp	0:eedb7d567a5d	1773
robert_lp	0:eedb7d567a5d	1774
robert_lp	0:eedb7d567a5d	1775	/@} end of CMSIS_Core_FpuFunctions /
robert_lp	0:eedb7d567a5d	1776
robert_lp	0:eedb7d567a5d	1777
robert_lp	0:eedb7d567a5d	1778
robert_lp	0:eedb7d567a5d	1779	/* ########################## SAU functions #################################### */
robert_lp	0:eedb7d567a5d	1780	/**
robert_lp	0:eedb7d567a5d	1781	\ingroup CMSIS_Core_FunctionInterface
robert_lp	0:eedb7d567a5d	1782	\defgroup CMSIS_Core_SAUFunctions SAU Functions
robert_lp	0:eedb7d567a5d	1783	\brief Functions that configure the SAU.
robert_lp	0:eedb7d567a5d	1784	@{
robert_lp	0:eedb7d567a5d	1785	*/
robert_lp	0:eedb7d567a5d	1786
robert_lp	0:eedb7d567a5d	1787	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
robert_lp	0:eedb7d567a5d	1788
robert_lp	0:eedb7d567a5d	1789	/**
robert_lp	0:eedb7d567a5d	1790	\brief Enable SAU
robert_lp	0:eedb7d567a5d	1791	\details Enables the Security Attribution Unit (SAU).
robert_lp	0:eedb7d567a5d	1792	*/
robert_lp	0:eedb7d567a5d	1793	__STATIC_INLINE void TZ_SAU_Enable(void)
robert_lp	0:eedb7d567a5d	1794	{
robert_lp	0:eedb7d567a5d	1795	SAU->CTRL \|= (SAU_CTRL_ENABLE_Msk);
robert_lp	0:eedb7d567a5d	1796	}
robert_lp	0:eedb7d567a5d	1797
robert_lp	0:eedb7d567a5d	1798
robert_lp	0:eedb7d567a5d	1799
robert_lp	0:eedb7d567a5d	1800	/**
robert_lp	0:eedb7d567a5d	1801	\brief Disable SAU
robert_lp	0:eedb7d567a5d	1802	\details Disables the Security Attribution Unit (SAU).
robert_lp	0:eedb7d567a5d	1803	*/
robert_lp	0:eedb7d567a5d	1804	__STATIC_INLINE void TZ_SAU_Disable(void)
robert_lp	0:eedb7d567a5d	1805	{
robert_lp	0:eedb7d567a5d	1806	SAU->CTRL &= ~(SAU_CTRL_ENABLE_Msk);
robert_lp	0:eedb7d567a5d	1807	}
robert_lp	0:eedb7d567a5d	1808
robert_lp	0:eedb7d567a5d	1809	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
robert_lp	0:eedb7d567a5d	1810
robert_lp	0:eedb7d567a5d	1811	/@} end of CMSIS_Core_SAUFunctions /
robert_lp	0:eedb7d567a5d	1812
robert_lp	0:eedb7d567a5d	1813
robert_lp	0:eedb7d567a5d	1814
robert_lp	0:eedb7d567a5d	1815
robert_lp	0:eedb7d567a5d	1816	/* ################################## SysTick function ############################################ */
robert_lp	0:eedb7d567a5d	1817	/**
robert_lp	0:eedb7d567a5d	1818	\ingroup CMSIS_Core_FunctionInterface
robert_lp	0:eedb7d567a5d	1819	\defgroup CMSIS_Core_SysTickFunctions SysTick Functions
robert_lp	0:eedb7d567a5d	1820	\brief Functions that configure the System.
robert_lp	0:eedb7d567a5d	1821	@{
robert_lp	0:eedb7d567a5d	1822	*/
robert_lp	0:eedb7d567a5d	1823
robert_lp	0:eedb7d567a5d	1824	#if defined (__Vendor_SysTickConfig) && (__Vendor_SysTickConfig == 0U)
robert_lp	0:eedb7d567a5d	1825
robert_lp	0:eedb7d567a5d	1826	/**
robert_lp	0:eedb7d567a5d	1827	\brief System Tick Configuration
robert_lp	0:eedb7d567a5d	1828	\details Initializes the System Timer and its interrupt, and starts the System Tick Timer.
robert_lp	0:eedb7d567a5d	1829	Counter is in free running mode to generate periodic interrupts.
robert_lp	0:eedb7d567a5d	1830	\param [in] ticks Number of ticks between two interrupts.
robert_lp	0:eedb7d567a5d	1831	\return 0 Function succeeded.
robert_lp	0:eedb7d567a5d	1832	\return 1 Function failed.
robert_lp	0:eedb7d567a5d	1833	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
robert_lp	0:eedb7d567a5d	1834	function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
robert_lp	0:eedb7d567a5d	1835	must contain a vendor-specific implementation of this function.
robert_lp	0:eedb7d567a5d	1836	*/
robert_lp	0:eedb7d567a5d	1837	__STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
robert_lp	0:eedb7d567a5d	1838	{
robert_lp	0:eedb7d567a5d	1839	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
robert_lp	0:eedb7d567a5d	1840	{
robert_lp	0:eedb7d567a5d	1841	return (1UL); /* Reload value impossible */
robert_lp	0:eedb7d567a5d	1842	}
robert_lp	0:eedb7d567a5d	1843
robert_lp	0:eedb7d567a5d	1844	SysTick->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
robert_lp	0:eedb7d567a5d	1845	NVIC_SetPriority (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
robert_lp	0:eedb7d567a5d	1846	SysTick->VAL = 0UL; /* Load the SysTick Counter Value */
robert_lp	0:eedb7d567a5d	1847	SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
robert_lp	0:eedb7d567a5d	1848	SysTick_CTRL_TICKINT_Msk \|
robert_lp	0:eedb7d567a5d	1849	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
robert_lp	0:eedb7d567a5d	1850	return (0UL); /* Function successful */
robert_lp	0:eedb7d567a5d	1851	}
robert_lp	0:eedb7d567a5d	1852
robert_lp	0:eedb7d567a5d	1853	#if defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U)
robert_lp	0:eedb7d567a5d	1854	/**
robert_lp	0:eedb7d567a5d	1855	\brief System Tick Configuration (non-secure)
robert_lp	0:eedb7d567a5d	1856	\details Initializes the non-secure System Timer and its interrupt when in secure state, and starts the System Tick Timer.
robert_lp	0:eedb7d567a5d	1857	Counter is in free running mode to generate periodic interrupts.
robert_lp	0:eedb7d567a5d	1858	\param [in] ticks Number of ticks between two interrupts.
robert_lp	0:eedb7d567a5d	1859	\return 0 Function succeeded.
robert_lp	0:eedb7d567a5d	1860	\return 1 Function failed.
robert_lp	0:eedb7d567a5d	1861	\note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
robert_lp	0:eedb7d567a5d	1862	function <b>TZ_SysTick_Config_NS</b> is not included. In this case, the file <b><i>device</i>.h</b>
robert_lp	0:eedb7d567a5d	1863	must contain a vendor-specific implementation of this function.
robert_lp	0:eedb7d567a5d	1864
robert_lp	0:eedb7d567a5d	1865	*/
robert_lp	0:eedb7d567a5d	1866	__STATIC_INLINE uint32_t TZ_SysTick_Config_NS(uint32_t ticks)
robert_lp	0:eedb7d567a5d	1867	{
robert_lp	0:eedb7d567a5d	1868	if ((ticks - 1UL) > SysTick_LOAD_RELOAD_Msk)
robert_lp	0:eedb7d567a5d	1869	{
robert_lp	0:eedb7d567a5d	1870	return (1UL); /* Reload value impossible */
robert_lp	0:eedb7d567a5d	1871	}
robert_lp	0:eedb7d567a5d	1872
robert_lp	0:eedb7d567a5d	1873	SysTick_NS->LOAD = (uint32_t)(ticks - 1UL); /* set reload register */
robert_lp	0:eedb7d567a5d	1874	TZ_NVIC_SetPriority_NS (SysTick_IRQn, (1UL << __NVIC_PRIO_BITS) - 1UL); /* set Priority for Systick Interrupt */
robert_lp	0:eedb7d567a5d	1875	SysTick_NS->VAL = 0UL; /* Load the SysTick Counter Value */
robert_lp	0:eedb7d567a5d	1876	SysTick_NS->CTRL = SysTick_CTRL_CLKSOURCE_Msk \|
robert_lp	0:eedb7d567a5d	1877	SysTick_CTRL_TICKINT_Msk \|
robert_lp	0:eedb7d567a5d	1878	SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
robert_lp	0:eedb7d567a5d	1879	return (0UL); /* Function successful */
robert_lp	0:eedb7d567a5d	1880	}
robert_lp	0:eedb7d567a5d	1881	#endif /* defined (__ARM_FEATURE_CMSE) && (__ARM_FEATURE_CMSE == 3U) */
robert_lp	0:eedb7d567a5d	1882
robert_lp	0:eedb7d567a5d	1883	#endif
robert_lp	0:eedb7d567a5d	1884
robert_lp	0:eedb7d567a5d	1885	/@} end of CMSIS_Core_SysTickFunctions /
robert_lp	0:eedb7d567a5d	1886
robert_lp	0:eedb7d567a5d	1887
robert_lp	0:eedb7d567a5d	1888
robert_lp	0:eedb7d567a5d	1889
robert_lp	0:eedb7d567a5d	1890	#ifdef __cplusplus
robert_lp	0:eedb7d567a5d	1891	}
robert_lp	0:eedb7d567a5d	1892	#endif
robert_lp	0:eedb7d567a5d	1893
robert_lp	0:eedb7d567a5d	1894	#endif /* __CORE_ARMV8MBL_H_DEPENDANT */
robert_lp	0:eedb7d567a5d	1895
robert_lp	0:eedb7d567a5d	1896	#endif /* __CMSIS_GENERIC */
robert_lp	0:eedb7d567a5d	1897

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Type:	Library
Created:	12 Apr 2018
Imports:	163
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	0
Followers:	5

The code in this repository is Apache licensed.

Core/include/core_armv8mbl.h@0:eedb7d567a5d, 2018-04-12 (annotated)

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