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lwip-eth/arch/TARGET_NXP/lpc17xx_emac.h@0:b2805b6888dc, 2016-06-20 (annotated)

Committer:
robert_jw
Date:
Mon Jun 20 01:40:20 2016 +0000
Revision:
0:b2805b6888dc
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UserRevisionLine numberNew contents of line
robert_jw 0:b2805b6888dc 1 /**********************************************************************
robert_jw 0:b2805b6888dc 2 * $Id$ lpc17xx_emac.h 2010-05-21
robert_jw 0:b2805b6888dc 3 *//**
robert_jw 0:b2805b6888dc 4 * @file lpc17xx_emac.h
robert_jw 0:b2805b6888dc 5 * @brief Contains all macro definitions and function prototypes
robert_jw 0:b2805b6888dc 6 * support for Ethernet MAC firmware library on LPC17xx
robert_jw 0:b2805b6888dc 7 * @version 2.0
robert_jw 0:b2805b6888dc 8 * @date 21. May. 2010
robert_jw 0:b2805b6888dc 9 * @author NXP MCU SW Application Team
robert_jw 0:b2805b6888dc 10 *
robert_jw 0:b2805b6888dc 11 * Copyright(C) 2010, NXP Semiconductor
robert_jw 0:b2805b6888dc 12 * All rights reserved.
robert_jw 0:b2805b6888dc 13 *
robert_jw 0:b2805b6888dc 14 ***********************************************************************
robert_jw 0:b2805b6888dc 15 * Software that is described herein is for illustrative purposes only
robert_jw 0:b2805b6888dc 16 * which provides customers with programming information regarding the
robert_jw 0:b2805b6888dc 17 * products. This software is supplied "AS IS" without any warranties.
robert_jw 0:b2805b6888dc 18 * NXP Semiconductors assumes no responsibility or liability for the
robert_jw 0:b2805b6888dc 19 * use of the software, conveys no license or title under any patent,
robert_jw 0:b2805b6888dc 20 * copyright, or mask work right to the product. NXP Semiconductors
robert_jw 0:b2805b6888dc 21 * reserves the right to make changes in the software without
robert_jw 0:b2805b6888dc 22 * notification. NXP Semiconductors also make no representation or
robert_jw 0:b2805b6888dc 23 * warranty that such application will be suitable for the specified
robert_jw 0:b2805b6888dc 24 * use without further testing or modification.
robert_jw 0:b2805b6888dc 25 **********************************************************************/
robert_jw 0:b2805b6888dc 26
robert_jw 0:b2805b6888dc 27 /* Peripheral group ----------------------------------------------------------- */
robert_jw 0:b2805b6888dc 28 /** @defgroup EMAC EMAC (Ethernet Media Access Controller)
robert_jw 0:b2805b6888dc 29 * @ingroup LPC1700CMSIS_FwLib_Drivers
robert_jw 0:b2805b6888dc 30 * @{
robert_jw 0:b2805b6888dc 31 */
robert_jw 0:b2805b6888dc 32
robert_jw 0:b2805b6888dc 33 #ifndef LPC17XX_EMAC_H_
robert_jw 0:b2805b6888dc 34 #define LPC17XX_EMAC_H_
robert_jw 0:b2805b6888dc 35
robert_jw 0:b2805b6888dc 36 /* Includes ------------------------------------------------------------------- */
robert_jw 0:b2805b6888dc 37 #include "cmsis.h"
robert_jw 0:b2805b6888dc 38
robert_jw 0:b2805b6888dc 39 #ifdef __cplusplus
robert_jw 0:b2805b6888dc 40 extern "C"
robert_jw 0:b2805b6888dc 41 {
robert_jw 0:b2805b6888dc 42 #endif
robert_jw 0:b2805b6888dc 43
robert_jw 0:b2805b6888dc 44 #define MCB_LPC_1768
robert_jw 0:b2805b6888dc 45 //#define IAR_LPC_1768
robert_jw 0:b2805b6888dc 46
robert_jw 0:b2805b6888dc 47 /* Public Macros -------------------------------------------------------------- */
robert_jw 0:b2805b6888dc 48 /** @defgroup EMAC_Public_Macros EMAC Public Macros
robert_jw 0:b2805b6888dc 49 * @{
robert_jw 0:b2805b6888dc 50 */
robert_jw 0:b2805b6888dc 51
robert_jw 0:b2805b6888dc 52
robert_jw 0:b2805b6888dc 53 /* EMAC PHY status type definitions */
robert_jw 0:b2805b6888dc 54 #define EMAC_PHY_STAT_LINK (0) /**< Link Status */
robert_jw 0:b2805b6888dc 55 #define EMAC_PHY_STAT_SPEED (1) /**< Speed Status */
robert_jw 0:b2805b6888dc 56 #define EMAC_PHY_STAT_DUP (2) /**< Duplex Status */
robert_jw 0:b2805b6888dc 57
robert_jw 0:b2805b6888dc 58 /* EMAC PHY device Speed definitions */
robert_jw 0:b2805b6888dc 59 #define EMAC_MODE_AUTO (0) /**< Auto-negotiation mode */
robert_jw 0:b2805b6888dc 60 #define EMAC_MODE_10M_FULL (1) /**< 10Mbps FullDuplex mode */
robert_jw 0:b2805b6888dc 61 #define EMAC_MODE_10M_HALF (2) /**< 10Mbps HalfDuplex mode */
robert_jw 0:b2805b6888dc 62 #define EMAC_MODE_100M_FULL (3) /**< 100Mbps FullDuplex mode */
robert_jw 0:b2805b6888dc 63 #define EMAC_MODE_100M_HALF (4) /**< 100Mbps HalfDuplex mode */
robert_jw 0:b2805b6888dc 64
robert_jw 0:b2805b6888dc 65 /**
robert_jw 0:b2805b6888dc 66 * @}
robert_jw 0:b2805b6888dc 67 */
robert_jw 0:b2805b6888dc 68 /* Private Macros ------------------------------------------------------------- */
robert_jw 0:b2805b6888dc 69 /** @defgroup EMAC_Private_Macros EMAC Private Macros
robert_jw 0:b2805b6888dc 70 * @{
robert_jw 0:b2805b6888dc 71 */
robert_jw 0:b2805b6888dc 72
robert_jw 0:b2805b6888dc 73
robert_jw 0:b2805b6888dc 74 /* EMAC Memory Buffer configuration for 16K Ethernet RAM */
robert_jw 0:b2805b6888dc 75 #define EMAC_NUM_RX_FRAG 4 /**< Num.of RX Fragments 4*1536= 6.0kB */
robert_jw 0:b2805b6888dc 76 #define EMAC_NUM_TX_FRAG 3 /**< Num.of TX Fragments 3*1536= 4.6kB */
robert_jw 0:b2805b6888dc 77 #define EMAC_ETH_MAX_FLEN 1536 /**< Max. Ethernet Frame Size */
robert_jw 0:b2805b6888dc 78 #define EMAC_TX_FRAME_TOUT 0x00100000 /**< Frame Transmit timeout count */
robert_jw 0:b2805b6888dc 79
robert_jw 0:b2805b6888dc 80 /* --------------------- BIT DEFINITIONS -------------------------------------- */
robert_jw 0:b2805b6888dc 81 /*********************************************************************//**
robert_jw 0:b2805b6888dc 82 * Macro defines for MAC Configuration Register 1
robert_jw 0:b2805b6888dc 83 **********************************************************************/
robert_jw 0:b2805b6888dc 84 #define EMAC_MAC1_REC_EN 0x00000001 /**< Receive Enable */
robert_jw 0:b2805b6888dc 85 #define EMAC_MAC1_PASS_ALL 0x00000002 /**< Pass All Receive Frames */
robert_jw 0:b2805b6888dc 86 #define EMAC_MAC1_RX_FLOWC 0x00000004 /**< RX Flow Control */
robert_jw 0:b2805b6888dc 87 #define EMAC_MAC1_TX_FLOWC 0x00000008 /**< TX Flow Control */
robert_jw 0:b2805b6888dc 88 #define EMAC_MAC1_LOOPB 0x00000010 /**< Loop Back Mode */
robert_jw 0:b2805b6888dc 89 #define EMAC_MAC1_RES_TX 0x00000100 /**< Reset TX Logic */
robert_jw 0:b2805b6888dc 90 #define EMAC_MAC1_RES_MCS_TX 0x00000200 /**< Reset MAC TX Control Sublayer */
robert_jw 0:b2805b6888dc 91 #define EMAC_MAC1_RES_RX 0x00000400 /**< Reset RX Logic */
robert_jw 0:b2805b6888dc 92 #define EMAC_MAC1_RES_MCS_RX 0x00000800 /**< Reset MAC RX Control Sublayer */
robert_jw 0:b2805b6888dc 93 #define EMAC_MAC1_SIM_RES 0x00004000 /**< Simulation Reset */
robert_jw 0:b2805b6888dc 94 #define EMAC_MAC1_SOFT_RES 0x00008000 /**< Soft Reset MAC */
robert_jw 0:b2805b6888dc 95
robert_jw 0:b2805b6888dc 96 /*********************************************************************//**
robert_jw 0:b2805b6888dc 97 * Macro defines for MAC Configuration Register 2
robert_jw 0:b2805b6888dc 98 **********************************************************************/
robert_jw 0:b2805b6888dc 99 #define EMAC_MAC2_FULL_DUP 0x00000001 /**< Full-Duplex Mode */
robert_jw 0:b2805b6888dc 100 #define EMAC_MAC2_FRM_LEN_CHK 0x00000002 /**< Frame Length Checking */
robert_jw 0:b2805b6888dc 101 #define EMAC_MAC2_HUGE_FRM_EN 0x00000004 /**< Huge Frame Enable */
robert_jw 0:b2805b6888dc 102 #define EMAC_MAC2_DLY_CRC 0x00000008 /**< Delayed CRC Mode */
robert_jw 0:b2805b6888dc 103 #define EMAC_MAC2_CRC_EN 0x00000010 /**< Append CRC to every Frame */
robert_jw 0:b2805b6888dc 104 #define EMAC_MAC2_PAD_EN 0x00000020 /**< Pad all Short Frames */
robert_jw 0:b2805b6888dc 105 #define EMAC_MAC2_VLAN_PAD_EN 0x00000040 /**< VLAN Pad Enable */
robert_jw 0:b2805b6888dc 106 #define EMAC_MAC2_ADET_PAD_EN 0x00000080 /**< Auto Detect Pad Enable */
robert_jw 0:b2805b6888dc 107 #define EMAC_MAC2_PPREAM_ENF 0x00000100 /**< Pure Preamble Enforcement */
robert_jw 0:b2805b6888dc 108 #define EMAC_MAC2_LPREAM_ENF 0x00000200 /**< Long Preamble Enforcement */
robert_jw 0:b2805b6888dc 109 #define EMAC_MAC2_NO_BACKOFF 0x00001000 /**< No Backoff Algorithm */
robert_jw 0:b2805b6888dc 110 #define EMAC_MAC2_BACK_PRESSURE 0x00002000 /**< Backoff Presurre / No Backoff */
robert_jw 0:b2805b6888dc 111 #define EMAC_MAC2_EXCESS_DEF 0x00004000 /**< Excess Defer */
robert_jw 0:b2805b6888dc 112
robert_jw 0:b2805b6888dc 113 /*********************************************************************//**
robert_jw 0:b2805b6888dc 114 * Macro defines for Back-to-Back Inter-Packet-Gap Register
robert_jw 0:b2805b6888dc 115 **********************************************************************/
robert_jw 0:b2805b6888dc 116 /** Programmable field representing the nibble time offset of the minimum possible period
robert_jw 0:b2805b6888dc 117 * between the end of any transmitted packet to the beginning of the next */
robert_jw 0:b2805b6888dc 118 #define EMAC_IPGT_BBIPG(n) (n&0x7F)
robert_jw 0:b2805b6888dc 119 /** Recommended value for Full Duplex of Programmable field representing the nibble time
robert_jw 0:b2805b6888dc 120 * offset of the minimum possible period between the end of any transmitted packet to the
robert_jw 0:b2805b6888dc 121 * beginning of the next */
robert_jw 0:b2805b6888dc 122 #define EMAC_IPGT_FULL_DUP (EMAC_IPGT_BBIPG(0x15))
robert_jw 0:b2805b6888dc 123 /** Recommended value for Half Duplex of Programmable field representing the nibble time
robert_jw 0:b2805b6888dc 124 * offset of the minimum possible period between the end of any transmitted packet to the
robert_jw 0:b2805b6888dc 125 * beginning of the next */
robert_jw 0:b2805b6888dc 126 #define EMAC_IPGT_HALF_DUP (EMAC_IPGT_BBIPG(0x12))
robert_jw 0:b2805b6888dc 127
robert_jw 0:b2805b6888dc 128 /*********************************************************************//**
robert_jw 0:b2805b6888dc 129 * Macro defines for Non Back-to-Back Inter-Packet-Gap Register
robert_jw 0:b2805b6888dc 130 **********************************************************************/
robert_jw 0:b2805b6888dc 131 /** Programmable field representing the Non-Back-to-Back Inter-Packet-Gap */
robert_jw 0:b2805b6888dc 132 #define EMAC_IPGR_NBBIPG_P2(n) (n&0x7F)
robert_jw 0:b2805b6888dc 133 /** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 1 */
robert_jw 0:b2805b6888dc 134 #define EMAC_IPGR_P2_DEF (EMAC_IPGR_NBBIPG_P2(0x12))
robert_jw 0:b2805b6888dc 135 /** Programmable field representing the optional carrierSense window referenced in
robert_jw 0:b2805b6888dc 136 * IEEE 802.3/4.2.3.2.1 'Carrier Deference' */
robert_jw 0:b2805b6888dc 137 #define EMAC_IPGR_NBBIPG_P1(n) ((n&0x7F)<<8)
robert_jw 0:b2805b6888dc 138 /** Recommended value for Programmable field representing the Non-Back-to-Back Inter-Packet-Gap Part 2 */
robert_jw 0:b2805b6888dc 139 #define EMAC_IPGR_P1_DEF EMAC_IPGR_NBBIPG_P1(0x0C)
robert_jw 0:b2805b6888dc 140
robert_jw 0:b2805b6888dc 141 /*********************************************************************//**
robert_jw 0:b2805b6888dc 142 * Macro defines for Collision Window/Retry Register
robert_jw 0:b2805b6888dc 143 **********************************************************************/
robert_jw 0:b2805b6888dc 144 /** Programmable field specifying the number of retransmission attempts following a collision before
robert_jw 0:b2805b6888dc 145 * aborting the packet due to excessive collisions */
robert_jw 0:b2805b6888dc 146 #define EMAC_CLRT_MAX_RETX(n) (n&0x0F)
robert_jw 0:b2805b6888dc 147 /** Programmable field representing the slot time or collision window during which collisions occur
robert_jw 0:b2805b6888dc 148 * in properly configured networks */
robert_jw 0:b2805b6888dc 149 #define EMAC_CLRT_COLL(n) ((n&0x3F)<<8)
robert_jw 0:b2805b6888dc 150 /** Default value for Collision Window / Retry register */
robert_jw 0:b2805b6888dc 151 #define EMAC_CLRT_DEF ((EMAC_CLRT_MAX_RETX(0x0F))|(EMAC_CLRT_COLL(0x37)))
robert_jw 0:b2805b6888dc 152
robert_jw 0:b2805b6888dc 153 /*********************************************************************//**
robert_jw 0:b2805b6888dc 154 * Macro defines for Maximum Frame Register
robert_jw 0:b2805b6888dc 155 **********************************************************************/
robert_jw 0:b2805b6888dc 156 /** Represents a maximum receive frame of 1536 octets */
robert_jw 0:b2805b6888dc 157 #define EMAC_MAXF_MAXFRMLEN(n) (n&0xFFFF)
robert_jw 0:b2805b6888dc 158
robert_jw 0:b2805b6888dc 159 /*********************************************************************//**
robert_jw 0:b2805b6888dc 160 * Macro defines for PHY Support Register
robert_jw 0:b2805b6888dc 161 **********************************************************************/
robert_jw 0:b2805b6888dc 162 #define EMAC_SUPP_SPEED 0x00000100 /**< Reduced MII Logic Current Speed */
robert_jw 0:b2805b6888dc 163 #define EMAC_SUPP_RES_RMII 0x00000800 /**< Reset Reduced MII Logic */
robert_jw 0:b2805b6888dc 164
robert_jw 0:b2805b6888dc 165 /*********************************************************************//**
robert_jw 0:b2805b6888dc 166 * Macro defines for Test Register
robert_jw 0:b2805b6888dc 167 **********************************************************************/
robert_jw 0:b2805b6888dc 168 #define EMAC_TEST_SHCUT_PQUANTA 0x00000001 /**< Shortcut Pause Quanta */
robert_jw 0:b2805b6888dc 169 #define EMAC_TEST_TST_PAUSE 0x00000002 /**< Test Pause */
robert_jw 0:b2805b6888dc 170 #define EMAC_TEST_TST_BACKP 0x00000004 /**< Test Back Pressure */
robert_jw 0:b2805b6888dc 171
robert_jw 0:b2805b6888dc 172 /*********************************************************************//**
robert_jw 0:b2805b6888dc 173 * Macro defines for MII Management Configuration Register
robert_jw 0:b2805b6888dc 174 **********************************************************************/
robert_jw 0:b2805b6888dc 175 #define EMAC_MCFG_SCAN_INC 0x00000001 /**< Scan Increment PHY Address */
robert_jw 0:b2805b6888dc 176 #define EMAC_MCFG_SUPP_PREAM 0x00000002 /**< Suppress Preamble */
robert_jw 0:b2805b6888dc 177 #define EMAC_MCFG_CLK_SEL(n) ((n&0x0F)<<2) /**< Clock Select Field */
robert_jw 0:b2805b6888dc 178 #define EMAC_MCFG_RES_MII 0x00008000 /**< Reset MII Management Hardware */
robert_jw 0:b2805b6888dc 179 #define EMAC_MCFG_MII_MAXCLK 2500000UL /**< MII Clock max */
robert_jw 0:b2805b6888dc 180
robert_jw 0:b2805b6888dc 181 /*********************************************************************//**
robert_jw 0:b2805b6888dc 182 * Macro defines for MII Management Command Register
robert_jw 0:b2805b6888dc 183 **********************************************************************/
robert_jw 0:b2805b6888dc 184 #define EMAC_MCMD_READ 0x00000001 /**< MII Read */
robert_jw 0:b2805b6888dc 185 #define EMAC_MCMD_SCAN 0x00000002 /**< MII Scan continuously */
robert_jw 0:b2805b6888dc 186
robert_jw 0:b2805b6888dc 187 #define EMAC_MII_WR_TOUT 0x00050000 /**< MII Write timeout count */
robert_jw 0:b2805b6888dc 188 #define EMAC_MII_RD_TOUT 0x00050000 /**< MII Read timeout count */
robert_jw 0:b2805b6888dc 189
robert_jw 0:b2805b6888dc 190 /*********************************************************************//**
robert_jw 0:b2805b6888dc 191 * Macro defines for MII Management Address Register
robert_jw 0:b2805b6888dc 192 **********************************************************************/
robert_jw 0:b2805b6888dc 193 #define EMAC_MADR_REG_ADR(n) (n&0x1F) /**< MII Register Address field */
robert_jw 0:b2805b6888dc 194 #define EMAC_MADR_PHY_ADR(n) ((n&0x1F)<<8) /**< PHY Address Field */
robert_jw 0:b2805b6888dc 195
robert_jw 0:b2805b6888dc 196 /*********************************************************************//**
robert_jw 0:b2805b6888dc 197 * Macro defines for MII Management Write Data Register
robert_jw 0:b2805b6888dc 198 **********************************************************************/
robert_jw 0:b2805b6888dc 199 #define EMAC_MWTD_DATA(n) (n&0xFFFF) /**< Data field for MMI Management Write Data register */
robert_jw 0:b2805b6888dc 200
robert_jw 0:b2805b6888dc 201 /*********************************************************************//**
robert_jw 0:b2805b6888dc 202 * Macro defines for MII Management Read Data Register
robert_jw 0:b2805b6888dc 203 **********************************************************************/
robert_jw 0:b2805b6888dc 204 #define EMAC_MRDD_DATA(n) (n&0xFFFF) /**< Data field for MMI Management Read Data register */
robert_jw 0:b2805b6888dc 205
robert_jw 0:b2805b6888dc 206 /*********************************************************************//**
robert_jw 0:b2805b6888dc 207 * Macro defines for MII Management Indicators Register
robert_jw 0:b2805b6888dc 208 **********************************************************************/
robert_jw 0:b2805b6888dc 209 #define EMAC_MIND_BUSY 0x00000001 /**< MII is Busy */
robert_jw 0:b2805b6888dc 210 #define EMAC_MIND_SCAN 0x00000002 /**< MII Scanning in Progress */
robert_jw 0:b2805b6888dc 211 #define EMAC_MIND_NOT_VAL 0x00000004 /**< MII Read Data not valid */
robert_jw 0:b2805b6888dc 212 #define EMAC_MIND_MII_LINK_FAIL 0x00000008 /**< MII Link Failed */
robert_jw 0:b2805b6888dc 213
robert_jw 0:b2805b6888dc 214 /* Station Address 0 Register */
robert_jw 0:b2805b6888dc 215 /* Station Address 1 Register */
robert_jw 0:b2805b6888dc 216 /* Station Address 2 Register */
robert_jw 0:b2805b6888dc 217
robert_jw 0:b2805b6888dc 218
robert_jw 0:b2805b6888dc 219 /* Control register definitions --------------------------------------------------------------------------- */
robert_jw 0:b2805b6888dc 220 /*********************************************************************//**
robert_jw 0:b2805b6888dc 221 * Macro defines for Command Register
robert_jw 0:b2805b6888dc 222 **********************************************************************/
robert_jw 0:b2805b6888dc 223 #define EMAC_CR_RX_EN 0x00000001 /**< Enable Receive */
robert_jw 0:b2805b6888dc 224 #define EMAC_CR_TX_EN 0x00000002 /**< Enable Transmit */
robert_jw 0:b2805b6888dc 225 #define EMAC_CR_REG_RES 0x00000008 /**< Reset Host Registers */
robert_jw 0:b2805b6888dc 226 #define EMAC_CR_TX_RES 0x00000010 /**< Reset Transmit Datapath */
robert_jw 0:b2805b6888dc 227 #define EMAC_CR_RX_RES 0x00000020 /**< Reset Receive Datapath */
robert_jw 0:b2805b6888dc 228 #define EMAC_CR_PASS_RUNT_FRM 0x00000040 /**< Pass Runt Frames */
robert_jw 0:b2805b6888dc 229 #define EMAC_CR_PASS_RX_FILT 0x00000080 /**< Pass RX Filter */
robert_jw 0:b2805b6888dc 230 #define EMAC_CR_TX_FLOW_CTRL 0x00000100 /**< TX Flow Control */
robert_jw 0:b2805b6888dc 231 #define EMAC_CR_RMII 0x00000200 /**< Reduced MII Interface */
robert_jw 0:b2805b6888dc 232 #define EMAC_CR_FULL_DUP 0x00000400 /**< Full Duplex */
robert_jw 0:b2805b6888dc 233
robert_jw 0:b2805b6888dc 234 /*********************************************************************//**
robert_jw 0:b2805b6888dc 235 * Macro defines for Status Register
robert_jw 0:b2805b6888dc 236 **********************************************************************/
robert_jw 0:b2805b6888dc 237 #define EMAC_SR_RX_EN 0x00000001 /**< Enable Receive */
robert_jw 0:b2805b6888dc 238 #define EMAC_SR_TX_EN 0x00000002 /**< Enable Transmit */
robert_jw 0:b2805b6888dc 239
robert_jw 0:b2805b6888dc 240 /*********************************************************************//**
robert_jw 0:b2805b6888dc 241 * Macro defines for Transmit Status Vector 0 Register
robert_jw 0:b2805b6888dc 242 **********************************************************************/
robert_jw 0:b2805b6888dc 243 #define EMAC_TSV0_CRC_ERR 0x00000001 /**< CRC error */
robert_jw 0:b2805b6888dc 244 #define EMAC_TSV0_LEN_CHKERR 0x00000002 /**< Length Check Error */
robert_jw 0:b2805b6888dc 245 #define EMAC_TSV0_LEN_OUTRNG 0x00000004 /**< Length Out of Range */
robert_jw 0:b2805b6888dc 246 #define EMAC_TSV0_DONE 0x00000008 /**< Tramsmission Completed */
robert_jw 0:b2805b6888dc 247 #define EMAC_TSV0_MCAST 0x00000010 /**< Multicast Destination */
robert_jw 0:b2805b6888dc 248 #define EMAC_TSV0_BCAST 0x00000020 /**< Broadcast Destination */
robert_jw 0:b2805b6888dc 249 #define EMAC_TSV0_PKT_DEFER 0x00000040 /**< Packet Deferred */
robert_jw 0:b2805b6888dc 250 #define EMAC_TSV0_EXC_DEFER 0x00000080 /**< Excessive Packet Deferral */
robert_jw 0:b2805b6888dc 251 #define EMAC_TSV0_EXC_COLL 0x00000100 /**< Excessive Collision */
robert_jw 0:b2805b6888dc 252 #define EMAC_TSV0_LATE_COLL 0x00000200 /**< Late Collision Occured */
robert_jw 0:b2805b6888dc 253 #define EMAC_TSV0_GIANT 0x00000400 /**< Giant Frame */
robert_jw 0:b2805b6888dc 254 #define EMAC_TSV0_UNDERRUN 0x00000800 /**< Buffer Underrun */
robert_jw 0:b2805b6888dc 255 #define EMAC_TSV0_BYTES 0x0FFFF000 /**< Total Bytes Transferred */
robert_jw 0:b2805b6888dc 256 #define EMAC_TSV0_CTRL_FRAME 0x10000000 /**< Control Frame */
robert_jw 0:b2805b6888dc 257 #define EMAC_TSV0_PAUSE 0x20000000 /**< Pause Frame */
robert_jw 0:b2805b6888dc 258 #define EMAC_TSV0_BACK_PRESS 0x40000000 /**< Backpressure Method Applied */
robert_jw 0:b2805b6888dc 259 #define EMAC_TSV0_VLAN 0x80000000 /**< VLAN Frame */
robert_jw 0:b2805b6888dc 260
robert_jw 0:b2805b6888dc 261 /*********************************************************************//**
robert_jw 0:b2805b6888dc 262 * Macro defines for Transmit Status Vector 1 Register
robert_jw 0:b2805b6888dc 263 **********************************************************************/
robert_jw 0:b2805b6888dc 264 #define EMAC_TSV1_BYTE_CNT 0x0000FFFF /**< Transmit Byte Count */
robert_jw 0:b2805b6888dc 265 #define EMAC_TSV1_COLL_CNT 0x000F0000 /**< Transmit Collision Count */
robert_jw 0:b2805b6888dc 266
robert_jw 0:b2805b6888dc 267 /*********************************************************************//**
robert_jw 0:b2805b6888dc 268 * Macro defines for Receive Status Vector Register
robert_jw 0:b2805b6888dc 269 **********************************************************************/
robert_jw 0:b2805b6888dc 270 #define EMAC_RSV_BYTE_CNT 0x0000FFFF /**< Receive Byte Count */
robert_jw 0:b2805b6888dc 271 #define EMAC_RSV_PKT_IGNORED 0x00010000 /**< Packet Previously Ignored */
robert_jw 0:b2805b6888dc 272 #define EMAC_RSV_RXDV_SEEN 0x00020000 /**< RXDV Event Previously Seen */
robert_jw 0:b2805b6888dc 273 #define EMAC_RSV_CARR_SEEN 0x00040000 /**< Carrier Event Previously Seen */
robert_jw 0:b2805b6888dc 274 #define EMAC_RSV_REC_CODEV 0x00080000 /**< Receive Code Violation */
robert_jw 0:b2805b6888dc 275 #define EMAC_RSV_CRC_ERR 0x00100000 /**< CRC Error */
robert_jw 0:b2805b6888dc 276 #define EMAC_RSV_LEN_CHKERR 0x00200000 /**< Length Check Error */
robert_jw 0:b2805b6888dc 277 #define EMAC_RSV_LEN_OUTRNG 0x00400000 /**< Length Out of Range */
robert_jw 0:b2805b6888dc 278 #define EMAC_RSV_REC_OK 0x00800000 /**< Frame Received OK */
robert_jw 0:b2805b6888dc 279 #define EMAC_RSV_MCAST 0x01000000 /**< Multicast Frame */
robert_jw 0:b2805b6888dc 280 #define EMAC_RSV_BCAST 0x02000000 /**< Broadcast Frame */
robert_jw 0:b2805b6888dc 281 #define EMAC_RSV_DRIB_NIBB 0x04000000 /**< Dribble Nibble */
robert_jw 0:b2805b6888dc 282 #define EMAC_RSV_CTRL_FRAME 0x08000000 /**< Control Frame */
robert_jw 0:b2805b6888dc 283 #define EMAC_RSV_PAUSE 0x10000000 /**< Pause Frame */
robert_jw 0:b2805b6888dc 284 #define EMAC_RSV_UNSUPP_OPC 0x20000000 /**< Unsupported Opcode */
robert_jw 0:b2805b6888dc 285 #define EMAC_RSV_VLAN 0x40000000 /**< VLAN Frame */
robert_jw 0:b2805b6888dc 286
robert_jw 0:b2805b6888dc 287 /*********************************************************************//**
robert_jw 0:b2805b6888dc 288 * Macro defines for Flow Control Counter Register
robert_jw 0:b2805b6888dc 289 **********************************************************************/
robert_jw 0:b2805b6888dc 290 #define EMAC_FCC_MIRR_CNT(n) (n&0xFFFF) /**< Mirror Counter */
robert_jw 0:b2805b6888dc 291 #define EMAC_FCC_PAUSE_TIM(n) ((n&0xFFFF)<<16) /**< Pause Timer */
robert_jw 0:b2805b6888dc 292
robert_jw 0:b2805b6888dc 293 /*********************************************************************//**
robert_jw 0:b2805b6888dc 294 * Macro defines for Flow Control Status Register
robert_jw 0:b2805b6888dc 295 **********************************************************************/
robert_jw 0:b2805b6888dc 296 #define EMAC_FCS_MIRR_CNT(n) (n&0xFFFF) /**< Mirror Counter Current */
robert_jw 0:b2805b6888dc 297
robert_jw 0:b2805b6888dc 298
robert_jw 0:b2805b6888dc 299 /* Receive filter register definitions -------------------------------------------------------- */
robert_jw 0:b2805b6888dc 300 /*********************************************************************//**
robert_jw 0:b2805b6888dc 301 * Macro defines for Receive Filter Control Register
robert_jw 0:b2805b6888dc 302 **********************************************************************/
robert_jw 0:b2805b6888dc 303 #define EMAC_RFC_UCAST_EN 0x00000001 /**< Accept Unicast Frames Enable */
robert_jw 0:b2805b6888dc 304 #define EMAC_RFC_BCAST_EN 0x00000002 /**< Accept Broadcast Frames Enable */
robert_jw 0:b2805b6888dc 305 #define EMAC_RFC_MCAST_EN 0x00000004 /**< Accept Multicast Frames Enable */
robert_jw 0:b2805b6888dc 306 #define EMAC_RFC_UCAST_HASH_EN 0x00000008 /**< Accept Unicast Hash Filter Frames */
robert_jw 0:b2805b6888dc 307 #define EMAC_RFC_MCAST_HASH_EN 0x00000010 /**< Accept Multicast Hash Filter Fram.*/
robert_jw 0:b2805b6888dc 308 #define EMAC_RFC_PERFECT_EN 0x00000020 /**< Accept Perfect Match Enable */
robert_jw 0:b2805b6888dc 309 #define EMAC_RFC_MAGP_WOL_EN 0x00001000 /**< Magic Packet Filter WoL Enable */
robert_jw 0:b2805b6888dc 310 #define EMAC_RFC_PFILT_WOL_EN 0x00002000 /**< Perfect Filter WoL Enable */
robert_jw 0:b2805b6888dc 311
robert_jw 0:b2805b6888dc 312 /*********************************************************************//**
robert_jw 0:b2805b6888dc 313 * Macro defines for Receive Filter WoL Status/Clear Registers
robert_jw 0:b2805b6888dc 314 **********************************************************************/
robert_jw 0:b2805b6888dc 315 #define EMAC_WOL_UCAST 0x00000001 /**< Unicast Frame caused WoL */
robert_jw 0:b2805b6888dc 316 #define EMAC_WOL_BCAST 0x00000002 /**< Broadcast Frame caused WoL */
robert_jw 0:b2805b6888dc 317 #define EMAC_WOL_MCAST 0x00000004 /**< Multicast Frame caused WoL */
robert_jw 0:b2805b6888dc 318 #define EMAC_WOL_UCAST_HASH 0x00000008 /**< Unicast Hash Filter Frame WoL */
robert_jw 0:b2805b6888dc 319 #define EMAC_WOL_MCAST_HASH 0x00000010 /**< Multicast Hash Filter Frame WoL */
robert_jw 0:b2805b6888dc 320 #define EMAC_WOL_PERFECT 0x00000020 /**< Perfect Filter WoL */
robert_jw 0:b2805b6888dc 321 #define EMAC_WOL_RX_FILTER 0x00000080 /**< RX Filter caused WoL */
robert_jw 0:b2805b6888dc 322 #define EMAC_WOL_MAG_PACKET 0x00000100 /**< Magic Packet Filter caused WoL */
robert_jw 0:b2805b6888dc 323 #define EMAC_WOL_BITMASK 0x01BF /**< Receive Filter WoL Status/Clear bitmasl value */
robert_jw 0:b2805b6888dc 324
robert_jw 0:b2805b6888dc 325
robert_jw 0:b2805b6888dc 326 /* Module control register definitions ---------------------------------------------------- */
robert_jw 0:b2805b6888dc 327 /*********************************************************************//**
robert_jw 0:b2805b6888dc 328 * Macro defines for Interrupt Status/Enable/Clear/Set Registers
robert_jw 0:b2805b6888dc 329 **********************************************************************/
robert_jw 0:b2805b6888dc 330 #define EMAC_INT_RX_OVERRUN 0x00000001 /**< Overrun Error in RX Queue */
robert_jw 0:b2805b6888dc 331 #define EMAC_INT_RX_ERR 0x00000002 /**< Receive Error */
robert_jw 0:b2805b6888dc 332 #define EMAC_INT_RX_FIN 0x00000004 /**< RX Finished Process Descriptors */
robert_jw 0:b2805b6888dc 333 #define EMAC_INT_RX_DONE 0x00000008 /**< Receive Done */
robert_jw 0:b2805b6888dc 334 #define EMAC_INT_TX_UNDERRUN 0x00000010 /**< Transmit Underrun */
robert_jw 0:b2805b6888dc 335 #define EMAC_INT_TX_ERR 0x00000020 /**< Transmit Error */
robert_jw 0:b2805b6888dc 336 #define EMAC_INT_TX_FIN 0x00000040 /**< TX Finished Process Descriptors */
robert_jw 0:b2805b6888dc 337 #define EMAC_INT_TX_DONE 0x00000080 /**< Transmit Done */
robert_jw 0:b2805b6888dc 338 #define EMAC_INT_SOFT_INT 0x00001000 /**< Software Triggered Interrupt */
robert_jw 0:b2805b6888dc 339 #define EMAC_INT_WAKEUP 0x00002000 /**< Wakeup Event Interrupt */
robert_jw 0:b2805b6888dc 340
robert_jw 0:b2805b6888dc 341 /*********************************************************************//**
robert_jw 0:b2805b6888dc 342 * Macro defines for Power Down Register
robert_jw 0:b2805b6888dc 343 **********************************************************************/
robert_jw 0:b2805b6888dc 344 #define EMAC_PD_POWER_DOWN 0x80000000 /**< Power Down MAC */
robert_jw 0:b2805b6888dc 345
robert_jw 0:b2805b6888dc 346 /* Descriptor and status formats ---------------------------------------------------- */
robert_jw 0:b2805b6888dc 347 /*********************************************************************//**
robert_jw 0:b2805b6888dc 348 * Macro defines for RX Descriptor Control Word
robert_jw 0:b2805b6888dc 349 **********************************************************************/
robert_jw 0:b2805b6888dc 350 #define EMAC_RCTRL_SIZE(n) (n&0x7FF) /**< Buffer size field */
robert_jw 0:b2805b6888dc 351 #define EMAC_RCTRL_INT 0x80000000 /**< Generate RxDone Interrupt */
robert_jw 0:b2805b6888dc 352
robert_jw 0:b2805b6888dc 353 /*********************************************************************//**
robert_jw 0:b2805b6888dc 354 * Macro defines for RX Status Hash CRC Word
robert_jw 0:b2805b6888dc 355 **********************************************************************/
robert_jw 0:b2805b6888dc 356 #define EMAC_RHASH_SA 0x000001FF /**< Hash CRC for Source Address */
robert_jw 0:b2805b6888dc 357 #define EMAC_RHASH_DA 0x001FF000 /**< Hash CRC for Destination Address */
robert_jw 0:b2805b6888dc 358
robert_jw 0:b2805b6888dc 359 /*********************************************************************//**
robert_jw 0:b2805b6888dc 360 * Macro defines for RX Status Information Word
robert_jw 0:b2805b6888dc 361 **********************************************************************/
robert_jw 0:b2805b6888dc 362 #define EMAC_RINFO_SIZE 0x000007FF /**< Data size in bytes */
robert_jw 0:b2805b6888dc 363 #define EMAC_RINFO_CTRL_FRAME 0x00040000 /**< Control Frame */
robert_jw 0:b2805b6888dc 364 #define EMAC_RINFO_VLAN 0x00080000 /**< VLAN Frame */
robert_jw 0:b2805b6888dc 365 #define EMAC_RINFO_FAIL_FILT 0x00100000 /**< RX Filter Failed */
robert_jw 0:b2805b6888dc 366 #define EMAC_RINFO_MCAST 0x00200000 /**< Multicast Frame */
robert_jw 0:b2805b6888dc 367 #define EMAC_RINFO_BCAST 0x00400000 /**< Broadcast Frame */
robert_jw 0:b2805b6888dc 368 #define EMAC_RINFO_CRC_ERR 0x00800000 /**< CRC Error in Frame */
robert_jw 0:b2805b6888dc 369 #define EMAC_RINFO_SYM_ERR 0x01000000 /**< Symbol Error from PHY */
robert_jw 0:b2805b6888dc 370 #define EMAC_RINFO_LEN_ERR 0x02000000 /**< Length Error */
robert_jw 0:b2805b6888dc 371 #define EMAC_RINFO_RANGE_ERR 0x04000000 /**< Range Error (exceeded max. size) */
robert_jw 0:b2805b6888dc 372 #define EMAC_RINFO_ALIGN_ERR 0x08000000 /**< Alignment Error */
robert_jw 0:b2805b6888dc 373 #define EMAC_RINFO_OVERRUN 0x10000000 /**< Receive overrun */
robert_jw 0:b2805b6888dc 374 #define EMAC_RINFO_NO_DESCR 0x20000000 /**< No new Descriptor available */
robert_jw 0:b2805b6888dc 375 #define EMAC_RINFO_LAST_FLAG 0x40000000 /**< Last Fragment in Frame */
robert_jw 0:b2805b6888dc 376 #define EMAC_RINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */
robert_jw 0:b2805b6888dc 377 #define EMAC_RINFO_ERR_MASK (EMAC_RINFO_FAIL_FILT | EMAC_RINFO_CRC_ERR | EMAC_RINFO_SYM_ERR | \
robert_jw 0:b2805b6888dc 378 EMAC_RINFO_LEN_ERR | EMAC_RINFO_ALIGN_ERR | EMAC_RINFO_OVERRUN)
robert_jw 0:b2805b6888dc 379
robert_jw 0:b2805b6888dc 380 /*********************************************************************//**
robert_jw 0:b2805b6888dc 381 * Macro defines for TX Descriptor Control Word
robert_jw 0:b2805b6888dc 382 **********************************************************************/
robert_jw 0:b2805b6888dc 383 #define EMAC_TCTRL_SIZE 0x000007FF /**< Size of data buffer in bytes */
robert_jw 0:b2805b6888dc 384 #define EMAC_TCTRL_OVERRIDE 0x04000000 /**< Override Default MAC Registers */
robert_jw 0:b2805b6888dc 385 #define EMAC_TCTRL_HUGE 0x08000000 /**< Enable Huge Frame */
robert_jw 0:b2805b6888dc 386 #define EMAC_TCTRL_PAD 0x10000000 /**< Pad short Frames to 64 bytes */
robert_jw 0:b2805b6888dc 387 #define EMAC_TCTRL_CRC 0x20000000 /**< Append a hardware CRC to Frame */
robert_jw 0:b2805b6888dc 388 #define EMAC_TCTRL_LAST 0x40000000 /**< Last Descriptor for TX Frame */
robert_jw 0:b2805b6888dc 389 #define EMAC_TCTRL_INT 0x80000000 /**< Generate TxDone Interrupt */
robert_jw 0:b2805b6888dc 390
robert_jw 0:b2805b6888dc 391 /*********************************************************************//**
robert_jw 0:b2805b6888dc 392 * Macro defines for TX Status Information Word
robert_jw 0:b2805b6888dc 393 **********************************************************************/
robert_jw 0:b2805b6888dc 394 #define EMAC_TINFO_COL_CNT 0x01E00000 /**< Collision Count */
robert_jw 0:b2805b6888dc 395 #define EMAC_TINFO_DEFER 0x02000000 /**< Packet Deferred (not an error) */
robert_jw 0:b2805b6888dc 396 #define EMAC_TINFO_EXCESS_DEF 0x04000000 /**< Excessive Deferral */
robert_jw 0:b2805b6888dc 397 #define EMAC_TINFO_EXCESS_COL 0x08000000 /**< Excessive Collision */
robert_jw 0:b2805b6888dc 398 #define EMAC_TINFO_LATE_COL 0x10000000 /**< Late Collision Occured */
robert_jw 0:b2805b6888dc 399 #define EMAC_TINFO_UNDERRUN 0x20000000 /**< Transmit Underrun */
robert_jw 0:b2805b6888dc 400 #define EMAC_TINFO_NO_DESCR 0x40000000 /**< No new Descriptor available */
robert_jw 0:b2805b6888dc 401 #define EMAC_TINFO_ERR 0x80000000 /**< Error Occured (OR of all errors) */
robert_jw 0:b2805b6888dc 402
robert_jw 0:b2805b6888dc 403 #ifdef MCB_LPC_1768
robert_jw 0:b2805b6888dc 404 /* DP83848C PHY definition ------------------------------------------------------------ */
robert_jw 0:b2805b6888dc 405
robert_jw 0:b2805b6888dc 406 /** PHY device reset time out definition */
robert_jw 0:b2805b6888dc 407 #define EMAC_PHY_RESP_TOUT 0x100000UL
robert_jw 0:b2805b6888dc 408
robert_jw 0:b2805b6888dc 409 /* ENET Device Revision ID */
robert_jw 0:b2805b6888dc 410 #define EMAC_OLD_EMAC_MODULE_ID 0x39022000 /**< Rev. ID for first rev '-' */
robert_jw 0:b2805b6888dc 411
robert_jw 0:b2805b6888dc 412 /*********************************************************************//**
robert_jw 0:b2805b6888dc 413 * Macro defines for DP83848C PHY Registers
robert_jw 0:b2805b6888dc 414 **********************************************************************/
robert_jw 0:b2805b6888dc 415 #define EMAC_PHY_REG_BMCR 0x00 /**< Basic Mode Control Register */
robert_jw 0:b2805b6888dc 416 #define EMAC_PHY_REG_BMSR 0x01 /**< Basic Mode Status Register */
robert_jw 0:b2805b6888dc 417 #define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */
robert_jw 0:b2805b6888dc 418 #define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */
robert_jw 0:b2805b6888dc 419 #define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */
robert_jw 0:b2805b6888dc 420 #define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Abitily */
robert_jw 0:b2805b6888dc 421 #define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */
robert_jw 0:b2805b6888dc 422 #define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */
robert_jw 0:b2805b6888dc 423 #define EMAC_PHY_REG_LPNPA 0x08
robert_jw 0:b2805b6888dc 424
robert_jw 0:b2805b6888dc 425 /*********************************************************************//**
robert_jw 0:b2805b6888dc 426 * Macro defines for PHY Extended Registers
robert_jw 0:b2805b6888dc 427 **********************************************************************/
robert_jw 0:b2805b6888dc 428 #define EMAC_PHY_REG_STS 0x10 /**< Status Register */
robert_jw 0:b2805b6888dc 429 #define EMAC_PHY_REG_MICR 0x11 /**< MII Interrupt Control Register */
robert_jw 0:b2805b6888dc 430 #define EMAC_PHY_REG_MISR 0x12 /**< MII Interrupt Status Register */
robert_jw 0:b2805b6888dc 431 #define EMAC_PHY_REG_FCSCR 0x14 /**< False Carrier Sense Counter */
robert_jw 0:b2805b6888dc 432 #define EMAC_PHY_REG_RECR 0x15 /**< Receive Error Counter */
robert_jw 0:b2805b6888dc 433 #define EMAC_PHY_REG_PCSR 0x16 /**< PCS Sublayer Config. and Status */
robert_jw 0:b2805b6888dc 434 #define EMAC_PHY_REG_RBR 0x17 /**< RMII and Bypass Register */
robert_jw 0:b2805b6888dc 435 #define EMAC_PHY_REG_LEDCR 0x18 /**< LED Direct Control Register */
robert_jw 0:b2805b6888dc 436 #define EMAC_PHY_REG_PHYCR 0x19 /**< PHY Control Register */
robert_jw 0:b2805b6888dc 437 #define EMAC_PHY_REG_10BTSCR 0x1A /**< 10Base-T Status/Control Register */
robert_jw 0:b2805b6888dc 438 #define EMAC_PHY_REG_CDCTRL1 0x1B /**< CD Test Control and BIST Extens. */
robert_jw 0:b2805b6888dc 439 #define EMAC_PHY_REG_EDCR 0x1D /**< Energy Detect Control Register */
robert_jw 0:b2805b6888dc 440
robert_jw 0:b2805b6888dc 441 /*********************************************************************//**
robert_jw 0:b2805b6888dc 442 * Macro defines for PHY Basic Mode Control Register
robert_jw 0:b2805b6888dc 443 **********************************************************************/
robert_jw 0:b2805b6888dc 444 #define EMAC_PHY_BMCR_RESET (1<<15) /**< Reset bit */
robert_jw 0:b2805b6888dc 445 #define EMAC_PHY_BMCR_LOOPBACK (1<<14) /**< Loop back */
robert_jw 0:b2805b6888dc 446 #define EMAC_PHY_BMCR_SPEED_SEL (1<<13) /**< Speed selection */
robert_jw 0:b2805b6888dc 447 #define EMAC_PHY_BMCR_AN (1<<12) /**< Auto Negotiation */
robert_jw 0:b2805b6888dc 448 #define EMAC_PHY_BMCR_POWERDOWN (1<<11) /**< Power down mode */
robert_jw 0:b2805b6888dc 449 #define EMAC_PHY_BMCR_ISOLATE (1<<10) /**< Isolate */
robert_jw 0:b2805b6888dc 450 #define EMAC_PHY_BMCR_RE_AN (1<<9) /**< Restart auto negotiation */
robert_jw 0:b2805b6888dc 451 #define EMAC_PHY_BMCR_DUPLEX (1<<8) /**< Duplex mode */
robert_jw 0:b2805b6888dc 452
robert_jw 0:b2805b6888dc 453 /*********************************************************************//**
robert_jw 0:b2805b6888dc 454 * Macro defines for PHY Basic Mode Status Status Register
robert_jw 0:b2805b6888dc 455 **********************************************************************/
robert_jw 0:b2805b6888dc 456 #define EMAC_PHY_BMSR_100BE_T4 (1<<15) /**< 100 base T4 */
robert_jw 0:b2805b6888dc 457 #define EMAC_PHY_BMSR_100TX_FULL (1<<14) /**< 100 base full duplex */
robert_jw 0:b2805b6888dc 458 #define EMAC_PHY_BMSR_100TX_HALF (1<<13) /**< 100 base half duplex */
robert_jw 0:b2805b6888dc 459 #define EMAC_PHY_BMSR_10BE_FULL (1<<12) /**< 10 base T full duplex */
robert_jw 0:b2805b6888dc 460 #define EMAC_PHY_BMSR_10BE_HALF (1<<11) /**< 10 base T half duplex */
robert_jw 0:b2805b6888dc 461 #define EMAC_PHY_BMSR_NOPREAM (1<<6) /**< MF Preamable Supress */
robert_jw 0:b2805b6888dc 462 #define EMAC_PHY_BMSR_AUTO_DONE (1<<5) /**< Auto negotiation complete */
robert_jw 0:b2805b6888dc 463 #define EMAC_PHY_BMSR_REMOTE_FAULT (1<<4) /**< Remote fault */
robert_jw 0:b2805b6888dc 464 #define EMAC_PHY_BMSR_NO_AUTO (1<<3) /**< Auto Negotiation ability */
robert_jw 0:b2805b6888dc 465 #define EMAC_PHY_BMSR_LINK_ESTABLISHED (1<<2) /**< Link status */
robert_jw 0:b2805b6888dc 466
robert_jw 0:b2805b6888dc 467 /*********************************************************************//**
robert_jw 0:b2805b6888dc 468 * Macro defines for PHY Status Register
robert_jw 0:b2805b6888dc 469 **********************************************************************/
robert_jw 0:b2805b6888dc 470 #define EMAC_PHY_SR_REMOTE_FAULT (1<<6) /**< Remote Fault */
robert_jw 0:b2805b6888dc 471 #define EMAC_PHY_SR_JABBER (1<<5) /**< Jabber detect */
robert_jw 0:b2805b6888dc 472 #define EMAC_PHY_SR_AUTO_DONE (1<<4) /**< Auto Negotiation complete */
robert_jw 0:b2805b6888dc 473 #define EMAC_PHY_SR_LOOPBACK (1<<3) /**< Loop back status */
robert_jw 0:b2805b6888dc 474 #define EMAC_PHY_SR_DUP (1<<2) /**< Duplex status */
robert_jw 0:b2805b6888dc 475 #define EMAC_PHY_SR_SPEED (1<<1) /**< Speed status */
robert_jw 0:b2805b6888dc 476 #define EMAC_PHY_SR_LINK (1<<0) /**< Link Status */
robert_jw 0:b2805b6888dc 477
robert_jw 0:b2805b6888dc 478 #define EMAC_PHY_FULLD_100M 0x2100 /**< Full Duplex 100Mbit */
robert_jw 0:b2805b6888dc 479 #define EMAC_PHY_HALFD_100M 0x2000 /**< Half Duplex 100Mbit */
robert_jw 0:b2805b6888dc 480 #define EMAC_PHY_FULLD_10M 0x0100 /**< Full Duplex 10Mbit */
robert_jw 0:b2805b6888dc 481 #define EMAC_PHY_HALFD_10M 0x0000 /**< Half Duplex 10MBit */
robert_jw 0:b2805b6888dc 482 #define EMAC_PHY_AUTO_NEG 0x3000 /**< Select Auto Negotiation */
robert_jw 0:b2805b6888dc 483
robert_jw 0:b2805b6888dc 484 #define EMAC_DEF_ADR 0x0100 /**< Default PHY device address */
robert_jw 0:b2805b6888dc 485 #define EMAC_DP83848C_ID 0x20005C90 /**< PHY Identifier */
robert_jw 0:b2805b6888dc 486
robert_jw 0:b2805b6888dc 487 #define EMAC_PHY_SR_100_SPEED ((1<<14)|(1<<13))
robert_jw 0:b2805b6888dc 488 #define EMAC_PHY_SR_FULL_DUP ((1<<14)|(1<<12))
robert_jw 0:b2805b6888dc 489 #define EMAC_PHY_BMSR_LINK_STATUS (1<<2) /**< Link status */
robert_jw 0:b2805b6888dc 490
robert_jw 0:b2805b6888dc 491 #elif defined(IAR_LPC_1768)
robert_jw 0:b2805b6888dc 492 /* KSZ8721BL PHY definition ------------------------------------------------------------ */
robert_jw 0:b2805b6888dc 493 /** PHY device reset time out definition */
robert_jw 0:b2805b6888dc 494 #define EMAC_PHY_RESP_TOUT 0x100000UL
robert_jw 0:b2805b6888dc 495
robert_jw 0:b2805b6888dc 496 /* ENET Device Revision ID */
robert_jw 0:b2805b6888dc 497 #define EMAC_OLD_EMAC_MODULE_ID 0x39022000 /**< Rev. ID for first rev '-' */
robert_jw 0:b2805b6888dc 498
robert_jw 0:b2805b6888dc 499 /*********************************************************************//**
robert_jw 0:b2805b6888dc 500 * Macro defines for KSZ8721BL PHY Registers
robert_jw 0:b2805b6888dc 501 **********************************************************************/
robert_jw 0:b2805b6888dc 502 #define EMAC_PHY_REG_BMCR 0x00 /**< Basic Mode Control Register */
robert_jw 0:b2805b6888dc 503 #define EMAC_PHY_REG_BMSR 0x01 /**< Basic Mode Status Register */
robert_jw 0:b2805b6888dc 504 #define EMAC_PHY_REG_IDR1 0x02 /**< PHY Identifier 1 */
robert_jw 0:b2805b6888dc 505 #define EMAC_PHY_REG_IDR2 0x03 /**< PHY Identifier 2 */
robert_jw 0:b2805b6888dc 506 #define EMAC_PHY_REG_ANAR 0x04 /**< Auto-Negotiation Advertisement */
robert_jw 0:b2805b6888dc 507 #define EMAC_PHY_REG_ANLPAR 0x05 /**< Auto-Neg. Link Partner Abitily */
robert_jw 0:b2805b6888dc 508 #define EMAC_PHY_REG_ANER 0x06 /**< Auto-Neg. Expansion Register */
robert_jw 0:b2805b6888dc 509 #define EMAC_PHY_REG_ANNPTR 0x07 /**< Auto-Neg. Next Page TX */
robert_jw 0:b2805b6888dc 510 #define EMAC_PHY_REG_LPNPA 0x08 /**< Link Partner Next Page Ability */
robert_jw 0:b2805b6888dc 511 #define EMAC_PHY_REG_REC 0x15 /**< RXError Counter Register */
robert_jw 0:b2805b6888dc 512 #define EMAC_PHY_REG_ISC 0x1b /**< Interrupt Control/Status Register */
robert_jw 0:b2805b6888dc 513 #define EMAC_PHY_REG_100BASE 0x1f /**< 100BASE-TX PHY Control Register */
robert_jw 0:b2805b6888dc 514
robert_jw 0:b2805b6888dc 515 /*********************************************************************//**
robert_jw 0:b2805b6888dc 516 * Macro defines for PHY Basic Mode Control Register
robert_jw 0:b2805b6888dc 517 **********************************************************************/
robert_jw 0:b2805b6888dc 518 #define EMAC_PHY_BMCR_RESET (1<<15) /**< Reset bit */
robert_jw 0:b2805b6888dc 519 #define EMAC_PHY_BMCR_LOOPBACK (1<<14) /**< Loop back */
robert_jw 0:b2805b6888dc 520 #define EMAC_PHY_BMCR_SPEED_SEL (1<<13) /**< Speed selection */
robert_jw 0:b2805b6888dc 521 #define EMAC_PHY_BMCR_AN (1<<12) /**< Auto Negotiation */
robert_jw 0:b2805b6888dc 522 #define EMAC_PHY_BMCR_POWERDOWN (1<<11) /**< Power down mode */
robert_jw 0:b2805b6888dc 523 #define EMAC_PHY_BMCR_ISOLATE (1<<10) /**< Isolate */
robert_jw 0:b2805b6888dc 524 #define EMAC_PHY_BMCR_RE_AN (1<<9) /**< Restart auto negotiation */
robert_jw 0:b2805b6888dc 525 #define EMAC_PHY_BMCR_DUPLEX (1<<8) /**< Duplex mode */
robert_jw 0:b2805b6888dc 526 #define EMAC_PHY_BMCR_COLLISION (1<<7) /**< Collision test */
robert_jw 0:b2805b6888dc 527 #define EMAC_PHY_BMCR_TXDIS (1<<0) /**< Disable transmit */
robert_jw 0:b2805b6888dc 528
robert_jw 0:b2805b6888dc 529 /*********************************************************************//**
robert_jw 0:b2805b6888dc 530 * Macro defines for PHY Basic Mode Status Register
robert_jw 0:b2805b6888dc 531 **********************************************************************/
robert_jw 0:b2805b6888dc 532 #define EMAC_PHY_BMSR_100BE_T4 (1<<15) /**< 100 base T4 */
robert_jw 0:b2805b6888dc 533 #define EMAC_PHY_BMSR_100TX_FULL (1<<14) /**< 100 base full duplex */
robert_jw 0:b2805b6888dc 534 #define EMAC_PHY_BMSR_100TX_HALF (1<<13) /**< 100 base half duplex */
robert_jw 0:b2805b6888dc 535 #define EMAC_PHY_BMSR_10BE_FULL (1<<12) /**< 10 base T full duplex */
robert_jw 0:b2805b6888dc 536 #define EMAC_PHY_BMSR_10BE_HALF (1<<11) /**< 10 base T half duplex */
robert_jw 0:b2805b6888dc 537 #define EMAC_PHY_BMSR_NOPREAM (1<<6) /**< MF Preamable Supress */
robert_jw 0:b2805b6888dc 538 #define EMAC_PHY_BMSR_AUTO_DONE (1<<5) /**< Auto negotiation complete */
robert_jw 0:b2805b6888dc 539 #define EMAC_PHY_BMSR_REMOTE_FAULT (1<<4) /**< Remote fault */
robert_jw 0:b2805b6888dc 540 #define EMAC_PHY_BMSR_NO_AUTO (1<<3) /**< Auto Negotiation ability */
robert_jw 0:b2805b6888dc 541 #define EMAC_PHY_BMSR_LINK_STATUS (1<<2) /**< Link status */
robert_jw 0:b2805b6888dc 542 #define EMAC_PHY_BMSR_JABBER_DETECT (1<<1) /**< Jabber detect */
robert_jw 0:b2805b6888dc 543 #define EMAC_PHY_BMSR_EXTEND (1<<0) /**< Extended support */
robert_jw 0:b2805b6888dc 544
robert_jw 0:b2805b6888dc 545 /*********************************************************************//**
robert_jw 0:b2805b6888dc 546 * Macro defines for PHY Identifier
robert_jw 0:b2805b6888dc 547 **********************************************************************/
robert_jw 0:b2805b6888dc 548 /* PHY Identifier 1 bitmap definitions */
robert_jw 0:b2805b6888dc 549 #define EMAC_PHY_IDR1(n) (n & 0xFFFF) /**< PHY ID1 Number */
robert_jw 0:b2805b6888dc 550
robert_jw 0:b2805b6888dc 551 /* PHY Identifier 2 bitmap definitions */
robert_jw 0:b2805b6888dc 552 #define EMAC_PHY_IDR2(n) (n & 0xFFFF) /**< PHY ID2 Number */
robert_jw 0:b2805b6888dc 553
robert_jw 0:b2805b6888dc 554 /*********************************************************************//**
robert_jw 0:b2805b6888dc 555 * Macro defines for Auto-Negotiation Advertisement
robert_jw 0:b2805b6888dc 556 **********************************************************************/
robert_jw 0:b2805b6888dc 557 #define EMAC_PHY_AN_NEXTPAGE (1<<15) /**< Next page capable */
robert_jw 0:b2805b6888dc 558 #define EMAC_PHY_AN_REMOTE_FAULT (1<<13) /**< Remote Fault support */
robert_jw 0:b2805b6888dc 559 #define EMAC_PHY_AN_PAUSE (1<<10) /**< Pause support */
robert_jw 0:b2805b6888dc 560 #define EMAC_PHY_AN_100BASE_T4 (1<<9) /**< T4 capable */
robert_jw 0:b2805b6888dc 561 #define EMAC_PHY_AN_100BASE_TX_FD (1<<8) /**< TX with Full-duplex capable */
robert_jw 0:b2805b6888dc 562 #define EMAC_PHY_AN_100BASE_TX (1<<7) /**< TX capable */
robert_jw 0:b2805b6888dc 563 #define EMAC_PHY_AN_10BASE_T_FD (1<<6) /**< 10Mbps with full-duplex capable */
robert_jw 0:b2805b6888dc 564 #define EMAC_PHY_AN_10BASE_T (1<<5) /**< 10Mbps capable */
robert_jw 0:b2805b6888dc 565 #define EMAC_PHY_AN_FIELD(n) (n & 0x1F) /**< Selector Field */
robert_jw 0:b2805b6888dc 566
robert_jw 0:b2805b6888dc 567 #define EMAC_PHY_FULLD_100M 0x2100 /**< Full Duplex 100Mbit */
robert_jw 0:b2805b6888dc 568 #define EMAC_PHY_HALFD_100M 0x2000 /**< Half Duplex 100Mbit */
robert_jw 0:b2805b6888dc 569 #define EMAC_PHY_FULLD_10M 0x0100 /**< Full Duplex 10Mbit */
robert_jw 0:b2805b6888dc 570 #define EMAC_PHY_HALFD_10M 0x0000 /**< Half Duplex 10MBit */
robert_jw 0:b2805b6888dc 571 #define EMAC_PHY_AUTO_NEG 0x3000 /**< Select Auto Negotiation */
robert_jw 0:b2805b6888dc 572
robert_jw 0:b2805b6888dc 573 #define EMAC_PHY_SR_100_SPEED ((1<<14)|(1<<13))
robert_jw 0:b2805b6888dc 574 #define EMAC_PHY_SR_FULL_DUP ((1<<14)|(1<<12))
robert_jw 0:b2805b6888dc 575
robert_jw 0:b2805b6888dc 576 #define EMAC_DEF_ADR (0x01<<8) /**< Default PHY device address */
robert_jw 0:b2805b6888dc 577 #define EMAC_KSZ8721BL_ID ((0x22 << 16) | 0x1619 ) /**< PHY Identifier */
robert_jw 0:b2805b6888dc 578 #endif
robert_jw 0:b2805b6888dc 579
robert_jw 0:b2805b6888dc 580 /**
robert_jw 0:b2805b6888dc 581 * @}
robert_jw 0:b2805b6888dc 582 */
robert_jw 0:b2805b6888dc 583
robert_jw 0:b2805b6888dc 584
robert_jw 0:b2805b6888dc 585 /* Public Types --------------------------------------------------------------- */
robert_jw 0:b2805b6888dc 586 /** @defgroup EMAC_Public_Types EMAC Public Types
robert_jw 0:b2805b6888dc 587 * @{
robert_jw 0:b2805b6888dc 588 */
robert_jw 0:b2805b6888dc 589
robert_jw 0:b2805b6888dc 590 /* Descriptor and status formats ---------------------------------------------- */
robert_jw 0:b2805b6888dc 591
robert_jw 0:b2805b6888dc 592 /**
robert_jw 0:b2805b6888dc 593 * @brief RX Descriptor structure type definition
robert_jw 0:b2805b6888dc 594 */
robert_jw 0:b2805b6888dc 595 typedef struct {
robert_jw 0:b2805b6888dc 596 uint32_t Packet; /**< Receive Packet Descriptor */
robert_jw 0:b2805b6888dc 597 uint32_t Ctrl; /**< Receive Control Descriptor */
robert_jw 0:b2805b6888dc 598 } RX_Desc;
robert_jw 0:b2805b6888dc 599
robert_jw 0:b2805b6888dc 600 /**
robert_jw 0:b2805b6888dc 601 * @brief RX Status structure type definition
robert_jw 0:b2805b6888dc 602 */
robert_jw 0:b2805b6888dc 603 typedef struct {
robert_jw 0:b2805b6888dc 604 uint32_t Info; /**< Receive Information Status */
robert_jw 0:b2805b6888dc 605 uint32_t HashCRC; /**< Receive Hash CRC Status */
robert_jw 0:b2805b6888dc 606 } RX_Stat;
robert_jw 0:b2805b6888dc 607
robert_jw 0:b2805b6888dc 608 /**
robert_jw 0:b2805b6888dc 609 * @brief TX Descriptor structure type definition
robert_jw 0:b2805b6888dc 610 */
robert_jw 0:b2805b6888dc 611 typedef struct {
robert_jw 0:b2805b6888dc 612 uint32_t Packet; /**< Transmit Packet Descriptor */
robert_jw 0:b2805b6888dc 613 uint32_t Ctrl; /**< Transmit Control Descriptor */
robert_jw 0:b2805b6888dc 614 } TX_Desc;
robert_jw 0:b2805b6888dc 615
robert_jw 0:b2805b6888dc 616 /**
robert_jw 0:b2805b6888dc 617 * @brief TX Status structure type definition
robert_jw 0:b2805b6888dc 618 */
robert_jw 0:b2805b6888dc 619 typedef struct {
robert_jw 0:b2805b6888dc 620 uint32_t Info; /**< Transmit Information Status */
robert_jw 0:b2805b6888dc 621 } TX_Stat;
robert_jw 0:b2805b6888dc 622
robert_jw 0:b2805b6888dc 623
robert_jw 0:b2805b6888dc 624 /**
robert_jw 0:b2805b6888dc 625 * @brief TX Data Buffer structure definition
robert_jw 0:b2805b6888dc 626 */
robert_jw 0:b2805b6888dc 627 typedef struct {
robert_jw 0:b2805b6888dc 628 uint32_t ulDataLen; /**< Data length */
robert_jw 0:b2805b6888dc 629 uint32_t *pbDataBuf; /**< A word-align data pointer to data buffer */
robert_jw 0:b2805b6888dc 630 } EMAC_PACKETBUF_Type;
robert_jw 0:b2805b6888dc 631
robert_jw 0:b2805b6888dc 632 /**
robert_jw 0:b2805b6888dc 633 * @brief EMAC configuration structure definition
robert_jw 0:b2805b6888dc 634 */
robert_jw 0:b2805b6888dc 635 typedef struct {
robert_jw 0:b2805b6888dc 636 uint32_t Mode; /**< Supported EMAC PHY device speed, should be one of the following:
robert_jw 0:b2805b6888dc 637 - EMAC_MODE_AUTO
robert_jw 0:b2805b6888dc 638 - EMAC_MODE_10M_FULL
robert_jw 0:b2805b6888dc 639 - EMAC_MODE_10M_HALF
robert_jw 0:b2805b6888dc 640 - EMAC_MODE_100M_FULL
robert_jw 0:b2805b6888dc 641 - EMAC_MODE_100M_HALF
robert_jw 0:b2805b6888dc 642 */
robert_jw 0:b2805b6888dc 643 uint8_t *pbEMAC_Addr; /**< Pointer to EMAC Station address that contains 6-bytes
robert_jw 0:b2805b6888dc 644 of MAC address, it must be sorted in order (bEMAC_Addr[0]..[5])
robert_jw 0:b2805b6888dc 645 */
robert_jw 0:b2805b6888dc 646 } EMAC_CFG_Type;
robert_jw 0:b2805b6888dc 647
robert_jw 0:b2805b6888dc 648 /** Ethernet block power/clock control bit*/
robert_jw 0:b2805b6888dc 649 #define CLKPWR_PCONP_PCENET ((uint32_t)(1<<30))
robert_jw 0:b2805b6888dc 650
robert_jw 0:b2805b6888dc 651 #ifdef __cplusplus
robert_jw 0:b2805b6888dc 652 }
robert_jw 0:b2805b6888dc 653 #endif
robert_jw 0:b2805b6888dc 654
robert_jw 0:b2805b6888dc 655 #endif /* LPC17XX_EMAC_H_ */
robert_jw 0:b2805b6888dc 656
robert_jw 0:b2805b6888dc 657 /**
robert_jw 0:b2805b6888dc 658 * @}
robert_jw 0:b2805b6888dc 659 */
robert_jw 0:b2805b6888dc 660
robert_jw 0:b2805b6888dc 661 /* --------------------------------- End Of File ------------------------------ */