岡本 陸 / Mbed 2 deprecated VL53L0X_STM32compatible_3

レーザー用のプログラムです（複数不可） 正規の方法じゃないから問題が起こるかもね がんばって

Dependencies:   mbed

Fork of VL53L0X_STM32compatible_2 by 2018年春ロボ1班

VL53L0X_SH.h@3:ce75ca8e2011, 2017-12-26 (annotated)

Committer:
riku3141
Date:
Tue Dec 26 05:35:10 2017 +0000
Revision:
3:ce75ca8e2011
Parent:
2:30363c43d575 
test

Who changed what in which revision?

UserRevisionLine numberNew contents of line
open4416 0:d738e3a03cf8 1 #ifndef VL53L0X_SH_h
open4416 0:d738e3a03cf8 2 #define VL53L0X_SH_h
open4416 0:d738e3a03cf8 3 #include "mbed.h"
open4416 0:d738e3a03cf8 4
riku3141 1:4fe66089799c 5 //extern I2C i2c;
open4416 0:d738e3a03cf8 6 class VL53L0X
open4416 0:d738e3a03cf8 7 {
open4416 0:d738e3a03cf8 8 public:
open4416 0:d738e3a03cf8 9 // register addresses from API vl53l0x_device.h (ordered as listed there)
open4416 0:d738e3a03cf8 10 enum regAddr {
open4416 0:d738e3a03cf8 11 SYSRANGE_START = 0x00,
open4416 0:d738e3a03cf8 12
open4416 0:d738e3a03cf8 13 SYSTEM_THRESH_HIGH = 0x0C,
open4416 0:d738e3a03cf8 14 SYSTEM_THRESH_LOW = 0x0E,
open4416 0:d738e3a03cf8 15
open4416 0:d738e3a03cf8 16 SYSTEM_SEQUENCE_CONFIG = 0x01,
open4416 0:d738e3a03cf8 17 SYSTEM_RANGE_CONFIG = 0x09,
open4416 0:d738e3a03cf8 18 SYSTEM_INTERMEASUREMENT_PERIOD = 0x04,
open4416 0:d738e3a03cf8 19
open4416 0:d738e3a03cf8 20 SYSTEM_INTERRUPT_CONFIG_GPIO = 0x0A,
open4416 0:d738e3a03cf8 21
open4416 0:d738e3a03cf8 22 GPIO_HV_MUX_ACTIVE_HIGH = 0x84,
open4416 0:d738e3a03cf8 23
open4416 0:d738e3a03cf8 24 SYSTEM_INTERRUPT_CLEAR = 0x0B,
open4416 0:d738e3a03cf8 25
open4416 0:d738e3a03cf8 26 RESULT_INTERRUPT_STATUS = 0x13,
open4416 0:d738e3a03cf8 27 RESULT_RANGE_STATUS = 0x14,
open4416 0:d738e3a03cf8 28
open4416 0:d738e3a03cf8 29 RESULT_CORE_AMBIENT_WINDOW_EVENTS_RTN = 0xBC,
open4416 0:d738e3a03cf8 30 RESULT_CORE_RANGING_TOTAL_EVENTS_RTN = 0xC0,
open4416 0:d738e3a03cf8 31 RESULT_CORE_AMBIENT_WINDOW_EVENTS_REF = 0xD0,
open4416 0:d738e3a03cf8 32 RESULT_CORE_RANGING_TOTAL_EVENTS_REF = 0xD4,
open4416 0:d738e3a03cf8 33 RESULT_PEAK_SIGNAL_RATE_REF = 0xB6,
open4416 0:d738e3a03cf8 34
open4416 0:d738e3a03cf8 35 ALGO_PART_TO_PART_RANGE_OFFSET_MM = 0x28,
open4416 0:d738e3a03cf8 36
open4416 0:d738e3a03cf8 37 I2C_SLAVE_DEVICE_ADDRESS = 0x8A,
open4416 0:d738e3a03cf8 38
open4416 0:d738e3a03cf8 39 MSRC_CONFIG_CONTROL = 0x60,
open4416 0:d738e3a03cf8 40
open4416 0:d738e3a03cf8 41 PRE_RANGE_CONFIG_MIN_SNR = 0x27,
open4416 0:d738e3a03cf8 42 PRE_RANGE_CONFIG_VALID_PHASE_LOW = 0x56,
open4416 0:d738e3a03cf8 43 PRE_RANGE_CONFIG_VALID_PHASE_HIGH = 0x57,
open4416 0:d738e3a03cf8 44 PRE_RANGE_MIN_COUNT_RATE_RTN_LIMIT = 0x64,
open4416 0:d738e3a03cf8 45
open4416 0:d738e3a03cf8 46 FINAL_RANGE_CONFIG_MIN_SNR = 0x67,
open4416 0:d738e3a03cf8 47 FINAL_RANGE_CONFIG_VALID_PHASE_LOW = 0x47,
open4416 0:d738e3a03cf8 48 FINAL_RANGE_CONFIG_VALID_PHASE_HIGH = 0x48,
open4416 0:d738e3a03cf8 49 FINAL_RANGE_CONFIG_MIN_COUNT_RATE_RTN_LIMIT = 0x44,
open4416 0:d738e3a03cf8 50
open4416 0:d738e3a03cf8 51 PRE_RANGE_CONFIG_SIGMA_THRESH_HI = 0x61,
open4416 0:d738e3a03cf8 52 PRE_RANGE_CONFIG_SIGMA_THRESH_LO = 0x62,
open4416 0:d738e3a03cf8 53
open4416 0:d738e3a03cf8 54 PRE_RANGE_CONFIG_VCSEL_PERIOD = 0x50,
open4416 0:d738e3a03cf8 55 PRE_RANGE_CONFIG_TIMEOUT_MACROP_HI = 0x51,
open4416 0:d738e3a03cf8 56 PRE_RANGE_CONFIG_TIMEOUT_MACROP_LO = 0x52,
open4416 0:d738e3a03cf8 57
open4416 0:d738e3a03cf8 58 SYSTEM_HISTOGRAM_BIN = 0x81,
open4416 0:d738e3a03cf8 59 HISTOGRAM_CONFIG_INITIAL_PHASE_SELECT = 0x33,
open4416 0:d738e3a03cf8 60 HISTOGRAM_CONFIG_READOUT_CTRL = 0x55,
open4416 0:d738e3a03cf8 61
open4416 0:d738e3a03cf8 62 FINAL_RANGE_CONFIG_VCSEL_PERIOD = 0x70,
open4416 0:d738e3a03cf8 63 FINAL_RANGE_CONFIG_TIMEOUT_MACROP_HI = 0x71,
open4416 0:d738e3a03cf8 64 FINAL_RANGE_CONFIG_TIMEOUT_MACROP_LO = 0x72,
open4416 0:d738e3a03cf8 65 CROSSTALK_COMPENSATION_PEAK_RATE_MCPS = 0x20,
open4416 0:d738e3a03cf8 66
open4416 0:d738e3a03cf8 67 MSRC_CONFIG_TIMEOUT_MACROP = 0x46,
open4416 0:d738e3a03cf8 68
open4416 0:d738e3a03cf8 69 SOFT_RESET_GO2_SOFT_RESET_N = 0xBF,
open4416 0:d738e3a03cf8 70 IDENTIFICATION_MODEL_ID = 0xC0,
open4416 0:d738e3a03cf8 71 IDENTIFICATION_REVISION_ID = 0xC2,
open4416 0:d738e3a03cf8 72
open4416 0:d738e3a03cf8 73 OSC_CALIBRATE_VAL = 0xF8,
open4416 0:d738e3a03cf8 74
open4416 0:d738e3a03cf8 75 GLOBAL_CONFIG_VCSEL_WIDTH = 0x32,
open4416 0:d738e3a03cf8 76 GLOBAL_CONFIG_SPAD_ENABLES_REF_0 = 0xB0,
open4416 0:d738e3a03cf8 77 GLOBAL_CONFIG_SPAD_ENABLES_REF_1 = 0xB1,
open4416 0:d738e3a03cf8 78 GLOBAL_CONFIG_SPAD_ENABLES_REF_2 = 0xB2,
open4416 0:d738e3a03cf8 79 GLOBAL_CONFIG_SPAD_ENABLES_REF_3 = 0xB3,
open4416 0:d738e3a03cf8 80 GLOBAL_CONFIG_SPAD_ENABLES_REF_4 = 0xB4,
open4416 0:d738e3a03cf8 81 GLOBAL_CONFIG_SPAD_ENABLES_REF_5 = 0xB5,
open4416 0:d738e3a03cf8 82
open4416 0:d738e3a03cf8 83 GLOBAL_CONFIG_REF_EN_START_SELECT = 0xB6,
open4416 0:d738e3a03cf8 84 DYNAMIC_SPAD_NUM_REQUESTED_REF_SPAD = 0x4E,
open4416 0:d738e3a03cf8 85 DYNAMIC_SPAD_REF_EN_START_OFFSET = 0x4F,
open4416 0:d738e3a03cf8 86 POWER_MANAGEMENT_GO1_POWER_FORCE = 0x80,
open4416 0:d738e3a03cf8 87
open4416 0:d738e3a03cf8 88 VHV_CONFIG_PAD_SCL_SDA__EXTSUP_HV = 0x89,
open4416 0:d738e3a03cf8 89
open4416 0:d738e3a03cf8 90 ALGO_PHASECAL_LIM = 0x30,
open4416 0:d738e3a03cf8 91 ALGO_PHASECAL_CONFIG_TIMEOUT = 0x30,
open4416 0:d738e3a03cf8 92 };
open4416 0:d738e3a03cf8 93
open4416 0:d738e3a03cf8 94 enum vcselPeriodType { VcselPeriodPreRange, VcselPeriodFinalRange };
open4416 0:d738e3a03cf8 95
open4416 0:d738e3a03cf8 96 char last_status; // status of last I2C transmission
open4416 0:d738e3a03cf8 97
open4416 0:d738e3a03cf8 98 VL53L0X(void);
open4416 0:d738e3a03cf8 99
open4416 0:d738e3a03cf8 100 void setAddress(char new_addr);
open4416 0:d738e3a03cf8 101 inline char getAddress(void) {
open4416 0:d738e3a03cf8 102 return address;
open4416 0:d738e3a03cf8 103 }
open4416 0:d738e3a03cf8 104
open4416 0:d738e3a03cf8 105 bool init(bool io_2v8 = true);
open4416 0:d738e3a03cf8 106
open4416 0:d738e3a03cf8 107 void writeReg(char reg, char value);
open4416 0:d738e3a03cf8 108 void writeReg16Bit(char reg, short value);
open4416 0:d738e3a03cf8 109 void writeReg32Bit(char reg, long value);
open4416 0:d738e3a03cf8 110 char readReg(char reg);
open4416 0:d738e3a03cf8 111 short readReg16Bit(char reg);
open4416 0:d738e3a03cf8 112 long readReg32Bit(char reg);
open4416 0:d738e3a03cf8 113
open4416 0:d738e3a03cf8 114 void writeMulti(char reg, char const * src, char count);
open4416 0:d738e3a03cf8 115 void readMulti(char reg, char * dst, char count);
open4416 0:d738e3a03cf8 116
open4416 0:d738e3a03cf8 117 bool setSignalRateLimit(float limit_Mcps);
open4416 0:d738e3a03cf8 118 float getSignalRateLimit(void);
open4416 0:d738e3a03cf8 119
open4416 0:d738e3a03cf8 120 bool setMeasurementTimingBudget(long budget_us);
open4416 0:d738e3a03cf8 121 long getMeasurementTimingBudget(void);
open4416 0:d738e3a03cf8 122
open4416 0:d738e3a03cf8 123 bool setVcselPulsePeriod(vcselPeriodType type, char period_pclks);
open4416 0:d738e3a03cf8 124 char getVcselPulsePeriod(vcselPeriodType type);
open4416 0:d738e3a03cf8 125
open4416 0:d738e3a03cf8 126 void startContinuous(long period_ms = 0);
open4416 0:d738e3a03cf8 127 void stopContinuous(void);
open4416 0:d738e3a03cf8 128 short readRangeContinuousMillimeters(void);
open4416 0:d738e3a03cf8 129 short readRangeSingleMillimeters(void);
open4416 0:d738e3a03cf8 130
open4416 0:d738e3a03cf8 131 inline void setTimeout(short timeout) {
open4416 0:d738e3a03cf8 132 io_timeout = timeout;
open4416 0:d738e3a03cf8 133 }
open4416 0:d738e3a03cf8 134 inline short getTimeout(void) {
open4416 0:d738e3a03cf8 135 return io_timeout;
open4416 0:d738e3a03cf8 136 }
open4416 0:d738e3a03cf8 137 bool timeoutOccurred(void);
riku3141 2:30363c43d575 138
riku3141 2:30363c43d575 139 char address;
open4416 0:d738e3a03cf8 140
open4416 0:d738e3a03cf8 141 private:
open4416 0:d738e3a03cf8 142 // TCC: Target CentreCheck
open4416 0:d738e3a03cf8 143 // MSRC: Minimum Signal Rate Check
open4416 0:d738e3a03cf8 144 // DSS: Dynamic Spad Selection
open4416 0:d738e3a03cf8 145
open4416 0:d738e3a03cf8 146 struct SequenceStepEnables {
open4416 0:d738e3a03cf8 147 bool tcc, msrc, dss, pre_range, final_range;
open4416 0:d738e3a03cf8 148 };
open4416 0:d738e3a03cf8 149
open4416 0:d738e3a03cf8 150 struct SequenceStepTimeouts {
open4416 0:d738e3a03cf8 151 short pre_range_vcsel_period_pclks, final_range_vcsel_period_pclks;
open4416 0:d738e3a03cf8 152
open4416 0:d738e3a03cf8 153 short msrc_dss_tcc_mclks, pre_range_mclks, final_range_mclks;
open4416 0:d738e3a03cf8 154 long msrc_dss_tcc_us, pre_range_us, final_range_us;
open4416 0:d738e3a03cf8 155 };
open4416 0:d738e3a03cf8 156
open4416 0:d738e3a03cf8 157 char data_w_2[2]; //buff for write
open4416 0:d738e3a03cf8 158 char data_w_3[3]; //buff for write
open4416 0:d738e3a03cf8 159 char data_w_5[5]; //buff for write
open4416 0:d738e3a03cf8 160 char data_r_1[1]; //buff for read
open4416 0:d738e3a03cf8 161 char data_r_2[2]; //buff for read
open4416 0:d738e3a03cf8 162 char data_r_4[4]; //buff for read
riku3141 2:30363c43d575 163 // char address;
open4416 0:d738e3a03cf8 164 short io_timeout;
open4416 0:d738e3a03cf8 165 bool did_timeout;
open4416 0:d738e3a03cf8 166 short timeout_start_ms;
open4416 0:d738e3a03cf8 167
open4416 0:d738e3a03cf8 168 char stop_variable; // read by init and used when starting measurement; is StopVariable field of VL53L0X_DevData_t structure in API
open4416 0:d738e3a03cf8 169 long measurement_timing_budget_us;
open4416 0:d738e3a03cf8 170
open4416 0:d738e3a03cf8 171 bool getSpadInfo(char * count, bool * type_is_aperture);
open4416 0:d738e3a03cf8 172
open4416 0:d738e3a03cf8 173 void getSequenceStepEnables(SequenceStepEnables * enables);
open4416 0:d738e3a03cf8 174 void getSequenceStepTimeouts(SequenceStepEnables const * enables, SequenceStepTimeouts * timeouts);
open4416 0:d738e3a03cf8 175
open4416 0:d738e3a03cf8 176 bool performSingleRefCalibration(char vhv_init_byte);
open4416 0:d738e3a03cf8 177
open4416 0:d738e3a03cf8 178 static short decodeTimeout(short value);
open4416 0:d738e3a03cf8 179 static short encodeTimeout(short timeout_mclks);
open4416 0:d738e3a03cf8 180 static long timeoutMclksToMicroseconds(short timeout_period_mclks, char vcsel_period_pclks);
open4416 0:d738e3a03cf8 181 static long timeoutMicrosecondsToMclks(long timeout_period_us, char vcsel_period_pclks);
open4416 0:d738e3a03cf8 182 };
open4416 0:d738e3a03cf8 183
open4416 0:d738e3a03cf8 184 #endif