岡本 陸 / Mbed 2 deprecated VL53L0X_STM32compatible_3

レーザー用のプログラムです（複数不可） 正規の方法じゃないから問題が起こるかもね がんばって

Dependencies:   mbed

Fork of VL53L0X_STM32compatible_2 by 2018年春ロボ1班

VL53L0X_SH.cpp@3:ce75ca8e2011, 2017-12-26 (annotated)

Committer:
riku3141
Date:
Tue Dec 26 05:35:10 2017 +0000
Revision:
3:ce75ca8e2011
Parent:
0:d738e3a03cf8 
test

Who changed what in which revision?

UserRevisionLine numberNew contents of line
open4416 0:d738e3a03cf8 1 // Most of the functionality of this library is based on the VL53L0X API
open4416 0:d738e3a03cf8 2 // provided by ST (STSW-IMG005), and some of the explanatory comments are quoted
open4416 0:d738e3a03cf8 3 // or paraphrased from the API source code, API user manual (UM2039), and the
open4416 0:d738e3a03cf8 4 // VL53L0X datasheet.
open4416 0:d738e3a03cf8 5
open4416 0:d738e3a03cf8 6 #include <VL53L0X_SH.h>
open4416 0:d738e3a03cf8 7 #include "mbed.h"
open4416 0:d738e3a03cf8 8 // Defines /////////////////////////////////////////////////////////////////////
open4416 0:d738e3a03cf8 9
open4416 0:d738e3a03cf8 10 // The Arduino two-wire interface uses a 7-bit number for the address,
open4416 0:d738e3a03cf8 11 // and sets the last bit correctly based on reads and writes
open4416 0:d738e3a03cf8 12 #define ADDRESS_DEFAULT 0b0101001
open4416 0:d738e3a03cf8 13
open4416 0:d738e3a03cf8 14 // Record the current time to check an upcoming timeout against
open4416 0:d738e3a03cf8 15 //#define startTimeout() (timeout_start_ms = millis())
open4416 0:d738e3a03cf8 16
open4416 0:d738e3a03cf8 17 // Check if timeout is enabled (set to nonzero value) and has expired
open4416 0:d738e3a03cf8 18 //#define checkTimeoutExpired() (io_timeout > 0 && ((short)millis() - timeout_start_ms) > io_timeout)
open4416 0:d738e3a03cf8 19
open4416 0:d738e3a03cf8 20 // Decode VCSEL (vertical cavity surface emitting laser) pulse period in PCLKs
open4416 0:d738e3a03cf8 21 // from register value
open4416 0:d738e3a03cf8 22 // based on VL53L0X_decode_vcsel_period()
open4416 0:d738e3a03cf8 23 #define decodeVcselPeriod(reg_val) (((reg_val) + 1) << 1)
open4416 0:d738e3a03cf8 24
open4416 0:d738e3a03cf8 25 // Encode VCSEL pulse period register value from period in PCLKs
open4416 0:d738e3a03cf8 26 // based on VL53L0X_encode_vcsel_period()
open4416 0:d738e3a03cf8 27 #define encodeVcselPeriod(period_pclks) (((period_pclks) >> 1) - 1)
open4416 0:d738e3a03cf8 28
open4416 0:d738e3a03cf8 29 // Calculate macro period in *nanoseconds* from VCSEL period in PCLKs
open4416 0:d738e3a03cf8 30 // based on VL53L0X_calc_macro_period_ps()
open4416 0:d738e3a03cf8 31 // PLL_period_ps = 1655; macro_period_vclks = 2304
open4416 0:d738e3a03cf8 32 #define calcMacroPeriod(vcsel_period_pclks) ((((long)2304 * (vcsel_period_pclks) * 1655) + 500) / 1000)
open4416 0:d738e3a03cf8 33
open4416 0:d738e3a03cf8 34 // Constructors ////////////////////////////////////////////////////////////////
open4416 0:d738e3a03cf8 35 I2C i2c(D14, D15); //I2C reg(SDA, SCL)
open4416 0:d738e3a03cf8 36
open4416 0:d738e3a03cf8 37 VL53L0X::VL53L0X(void)
open4416 0:d738e3a03cf8 38 : address(ADDRESS_DEFAULT)
open4416 0:d738e3a03cf8 39 , io_timeout(0) // no timeout
open4416 0:d738e3a03cf8 40 , did_timeout(false)
open4416 0:d738e3a03cf8 41 {
open4416 0:d738e3a03cf8 42 }
open4416 0:d738e3a03cf8 43
open4416 0:d738e3a03cf8 44 // Public Methods //////////////////////////////////////////////////////////////
open4416 0:d738e3a03cf8 45
open4416 0:d738e3a03cf8 46 void VL53L0X::setAddress(char new_addr)
open4416 0:d738e3a03cf8 47 {
open4416 0:d738e3a03cf8 48 writeReg(I2C_SLAVE_DEVICE_ADDRESS, new_addr & 0x7F);
open4416 0:d738e3a03cf8 49 address = new_addr;
open4416 0:d738e3a03cf8 50 }
open4416 0:d738e3a03cf8 51
open4416 0:d738e3a03cf8 52 // Initialize sensor using sequence based on VL53L0X_DataInit(),
open4416 0:d738e3a03cf8 53 // VL53L0X_StaticInit(), and VL53L0X_PerformRefCalibration().
open4416 0:d738e3a03cf8 54 // This function does not perform reference SPAD calibration
open4416 0:d738e3a03cf8 55 // (VL53L0X_PerformRefSpadManagement()), since the API user manual says that it
open4416 0:d738e3a03cf8 56 // is performed by ST on the bare modules; it seems like that should work well
open4416 0:d738e3a03cf8 57 // enough unless a cover glass is added.
open4416 0:d738e3a03cf8 58 // If io_2v8 (optional) is true or not given, the sensor is configured for 2V8
open4416 0:d738e3a03cf8 59 // mode.
open4416 0:d738e3a03cf8 60 bool VL53L0X::init(bool io_2v8)
open4416 0:d738e3a03cf8 61 {
open4416 0:d738e3a03cf8 62 if (io_2v8) {
open4416 0:d738e3a03cf8 63 writeReg(VHV_CONFIG_PAD_SCL_SDA__EXTSUP_HV,
open4416 0:d738e3a03cf8 64 readReg(VHV_CONFIG_PAD_SCL_SDA__EXTSUP_HV) | 0x01); // set bit 0
open4416 0:d738e3a03cf8 65 }
open4416 0:d738e3a03cf8 66 // "Set I2C standard mode"
open4416 0:d738e3a03cf8 67 writeReg(0x88, 0x00);
open4416 0:d738e3a03cf8 68 writeReg(0x80, 0x01);
open4416 0:d738e3a03cf8 69 writeReg(0xFF, 0x01);
open4416 0:d738e3a03cf8 70 writeReg(0x00, 0x00);
open4416 0:d738e3a03cf8 71 stop_variable = readReg(0x91);
open4416 0:d738e3a03cf8 72 writeReg(0x00, 0x01);
open4416 0:d738e3a03cf8 73 writeReg(0xFF, 0x00);
open4416 0:d738e3a03cf8 74 writeReg(0x80, 0x00);
open4416 0:d738e3a03cf8 75
open4416 0:d738e3a03cf8 76 // disable SIGNAL_RATE_MSRC (bit 1) and SIGNAL_RATE_PRE_RANGE (bit 4) limit checks
open4416 0:d738e3a03cf8 77 writeReg(MSRC_CONFIG_CONTROL, readReg(MSRC_CONFIG_CONTROL) | 0x12);
open4416 0:d738e3a03cf8 78
open4416 0:d738e3a03cf8 79 // set final range signal rate limit to 0.25 MCPS (million counts per second)
open4416 0:d738e3a03cf8 80 setSignalRateLimit(0.25);
open4416 0:d738e3a03cf8 81
open4416 0:d738e3a03cf8 82 writeReg(SYSTEM_SEQUENCE_CONFIG, 0xFF);
open4416 0:d738e3a03cf8 83
open4416 0:d738e3a03cf8 84 // VL53L0X_DataInit() end
open4416 0:d738e3a03cf8 85
open4416 0:d738e3a03cf8 86 // VL53L0X_StaticInit() begin
open4416 0:d738e3a03cf8 87
open4416 0:d738e3a03cf8 88 char spad_count;
open4416 0:d738e3a03cf8 89 bool spad_type_is_aperture;
open4416 0:d738e3a03cf8 90 if (!getSpadInfo(&spad_count, &spad_type_is_aperture)) {
open4416 0:d738e3a03cf8 91 return false;
open4416 0:d738e3a03cf8 92 }
open4416 0:d738e3a03cf8 93
open4416 0:d738e3a03cf8 94 // The SPAD map (RefGoodSpadMap) is read by VL53L0X_get_info_from_device() in
open4416 0:d738e3a03cf8 95 // the API, but the same data seems to be more easily readable from
open4416 0:d738e3a03cf8 96 // GLOBAL_CONFIG_SPAD_ENABLES_REF_0 through _6, so read it from there
open4416 0:d738e3a03cf8 97 char ref_spad_map[6];
open4416 0:d738e3a03cf8 98 readMulti(GLOBAL_CONFIG_SPAD_ENABLES_REF_0, ref_spad_map, 6);
open4416 0:d738e3a03cf8 99
open4416 0:d738e3a03cf8 100 // -- VL53L0X_set_reference_spads() begin (assume NVM values are valid)
open4416 0:d738e3a03cf8 101
open4416 0:d738e3a03cf8 102 writeReg(0xFF, 0x01);
open4416 0:d738e3a03cf8 103 writeReg(DYNAMIC_SPAD_REF_EN_START_OFFSET, 0x00);
open4416 0:d738e3a03cf8 104 writeReg(DYNAMIC_SPAD_NUM_REQUESTED_REF_SPAD, 0x2C);
open4416 0:d738e3a03cf8 105 writeReg(0xFF, 0x00);
open4416 0:d738e3a03cf8 106 writeReg(GLOBAL_CONFIG_REF_EN_START_SELECT, 0xB4);
open4416 0:d738e3a03cf8 107
open4416 0:d738e3a03cf8 108 char first_spad_to_enable = spad_type_is_aperture ? 12 : 0; // 12 is the first aperture spad
open4416 0:d738e3a03cf8 109 char spads_enabled = 0;
open4416 0:d738e3a03cf8 110
open4416 0:d738e3a03cf8 111 for (char i = 0; i < 48; i++) {
open4416 0:d738e3a03cf8 112 if (i < first_spad_to_enable || spads_enabled == spad_count) {
open4416 0:d738e3a03cf8 113 // This bit is lower than the first one that should be enabled, or
open4416 0:d738e3a03cf8 114 // (reference_spad_count) bits have already been enabled, so zero this bit
open4416 0:d738e3a03cf8 115 ref_spad_map[i / 8] &= ~(1 << (i % 8));
open4416 0:d738e3a03cf8 116 } else if ((ref_spad_map[i / 8] >> (i % 8)) & 0x1) {
open4416 0:d738e3a03cf8 117 spads_enabled++;
open4416 0:d738e3a03cf8 118 }
open4416 0:d738e3a03cf8 119 }
open4416 0:d738e3a03cf8 120
open4416 0:d738e3a03cf8 121 writeMulti(GLOBAL_CONFIG_SPAD_ENABLES_REF_0, ref_spad_map, 6);
open4416 0:d738e3a03cf8 122
open4416 0:d738e3a03cf8 123 // -- VL53L0X_set_reference_spads() end
open4416 0:d738e3a03cf8 124
open4416 0:d738e3a03cf8 125 // -- VL53L0X_load_tuning_settings() begin
open4416 0:d738e3a03cf8 126 // DefaultTuningSettings from vl53l0x_tuning.h
open4416 0:d738e3a03cf8 127
open4416 0:d738e3a03cf8 128 writeReg(0xFF, 0x01);
open4416 0:d738e3a03cf8 129 writeReg(0x00, 0x00);
open4416 0:d738e3a03cf8 130
open4416 0:d738e3a03cf8 131 writeReg(0xFF, 0x00);
open4416 0:d738e3a03cf8 132 writeReg(0x09, 0x00);
open4416 0:d738e3a03cf8 133 writeReg(0x10, 0x00);
open4416 0:d738e3a03cf8 134 writeReg(0x11, 0x00);
open4416 0:d738e3a03cf8 135
open4416 0:d738e3a03cf8 136 writeReg(0x24, 0x01);
open4416 0:d738e3a03cf8 137 writeReg(0x25, 0xFF);
open4416 0:d738e3a03cf8 138 writeReg(0x75, 0x00);
open4416 0:d738e3a03cf8 139
open4416 0:d738e3a03cf8 140 writeReg(0xFF, 0x01);
open4416 0:d738e3a03cf8 141 writeReg(0x4E, 0x2C);
open4416 0:d738e3a03cf8 142 writeReg(0x48, 0x00);
open4416 0:d738e3a03cf8 143 writeReg(0x30, 0x20);
open4416 0:d738e3a03cf8 144
open4416 0:d738e3a03cf8 145 writeReg(0xFF, 0x00);
open4416 0:d738e3a03cf8 146 writeReg(0x30, 0x09);
open4416 0:d738e3a03cf8 147 writeReg(0x54, 0x00);
open4416 0:d738e3a03cf8 148 writeReg(0x31, 0x04);
open4416 0:d738e3a03cf8 149 writeReg(0x32, 0x03);
open4416 0:d738e3a03cf8 150 writeReg(0x40, 0x83);
open4416 0:d738e3a03cf8 151 writeReg(0x46, 0x25);
open4416 0:d738e3a03cf8 152 writeReg(0x60, 0x00);
open4416 0:d738e3a03cf8 153 writeReg(0x27, 0x00);
open4416 0:d738e3a03cf8 154 writeReg(0x50, 0x06);
open4416 0:d738e3a03cf8 155 writeReg(0x51, 0x00);
open4416 0:d738e3a03cf8 156 writeReg(0x52, 0x96);
open4416 0:d738e3a03cf8 157 writeReg(0x56, 0x08);
open4416 0:d738e3a03cf8 158 writeReg(0x57, 0x30);
open4416 0:d738e3a03cf8 159 writeReg(0x61, 0x00);
open4416 0:d738e3a03cf8 160 writeReg(0x62, 0x00);
open4416 0:d738e3a03cf8 161 writeReg(0x64, 0x00);
open4416 0:d738e3a03cf8 162 writeReg(0x65, 0x00);
open4416 0:d738e3a03cf8 163 writeReg(0x66, 0xA0);
open4416 0:d738e3a03cf8 164
open4416 0:d738e3a03cf8 165 writeReg(0xFF, 0x01);
open4416 0:d738e3a03cf8 166 writeReg(0x22, 0x32);
open4416 0:d738e3a03cf8 167 writeReg(0x47, 0x14);
open4416 0:d738e3a03cf8 168 writeReg(0x49, 0xFF);
open4416 0:d738e3a03cf8 169 writeReg(0x4A, 0x00);
open4416 0:d738e3a03cf8 170
open4416 0:d738e3a03cf8 171 writeReg(0xFF, 0x00);
open4416 0:d738e3a03cf8 172 writeReg(0x7A, 0x0A);
open4416 0:d738e3a03cf8 173 writeReg(0x7B, 0x00);
open4416 0:d738e3a03cf8 174 writeReg(0x78, 0x21);
open4416 0:d738e3a03cf8 175
open4416 0:d738e3a03cf8 176 writeReg(0xFF, 0x01);
open4416 0:d738e3a03cf8 177 writeReg(0x23, 0x34);
open4416 0:d738e3a03cf8 178 writeReg(0x42, 0x00);
open4416 0:d738e3a03cf8 179 writeReg(0x44, 0xFF);
open4416 0:d738e3a03cf8 180 writeReg(0x45, 0x26);
open4416 0:d738e3a03cf8 181 writeReg(0x46, 0x05);
open4416 0:d738e3a03cf8 182 writeReg(0x40, 0x40);
open4416 0:d738e3a03cf8 183 writeReg(0x0E, 0x06);
open4416 0:d738e3a03cf8 184 writeReg(0x20, 0x1A);
open4416 0:d738e3a03cf8 185 writeReg(0x43, 0x40);
open4416 0:d738e3a03cf8 186
open4416 0:d738e3a03cf8 187 writeReg(0xFF, 0x00);
open4416 0:d738e3a03cf8 188 writeReg(0x34, 0x03);
open4416 0:d738e3a03cf8 189 writeReg(0x35, 0x44);
open4416 0:d738e3a03cf8 190
open4416 0:d738e3a03cf8 191 writeReg(0xFF, 0x01);
open4416 0:d738e3a03cf8 192 writeReg(0x31, 0x04);
open4416 0:d738e3a03cf8 193 writeReg(0x4B, 0x09);
open4416 0:d738e3a03cf8 194 writeReg(0x4C, 0x05);
open4416 0:d738e3a03cf8 195 writeReg(0x4D, 0x04);
open4416 0:d738e3a03cf8 196
open4416 0:d738e3a03cf8 197 writeReg(0xFF, 0x00);
open4416 0:d738e3a03cf8 198 writeReg(0x44, 0x00);
open4416 0:d738e3a03cf8 199 writeReg(0x45, 0x20);
open4416 0:d738e3a03cf8 200 writeReg(0x47, 0x08);
open4416 0:d738e3a03cf8 201 writeReg(0x48, 0x28);
open4416 0:d738e3a03cf8 202 writeReg(0x67, 0x00);
open4416 0:d738e3a03cf8 203 writeReg(0x70, 0x04);
open4416 0:d738e3a03cf8 204 writeReg(0x71, 0x01);
open4416 0:d738e3a03cf8 205 writeReg(0x72, 0xFE);
open4416 0:d738e3a03cf8 206 writeReg(0x76, 0x00);
open4416 0:d738e3a03cf8 207 writeReg(0x77, 0x00);
open4416 0:d738e3a03cf8 208
open4416 0:d738e3a03cf8 209 writeReg(0xFF, 0x01);
open4416 0:d738e3a03cf8 210 writeReg(0x0D, 0x01);
open4416 0:d738e3a03cf8 211
open4416 0:d738e3a03cf8 212 writeReg(0xFF, 0x00);
open4416 0:d738e3a03cf8 213 writeReg(0x80, 0x01);
open4416 0:d738e3a03cf8 214 writeReg(0x01, 0xF8);
open4416 0:d738e3a03cf8 215
open4416 0:d738e3a03cf8 216 writeReg(0xFF, 0x01);
open4416 0:d738e3a03cf8 217 writeReg(0x8E, 0x01);
open4416 0:d738e3a03cf8 218 writeReg(0x00, 0x01);
open4416 0:d738e3a03cf8 219 writeReg(0xFF, 0x00);
open4416 0:d738e3a03cf8 220 writeReg(0x80, 0x00);
open4416 0:d738e3a03cf8 221
open4416 0:d738e3a03cf8 222 // -- VL53L0X_load_tuning_settings() end
open4416 0:d738e3a03cf8 223
open4416 0:d738e3a03cf8 224 // "Set interrupt config to new sample ready"
open4416 0:d738e3a03cf8 225 // -- VL53L0X_SetGpioConfig() begin
open4416 0:d738e3a03cf8 226
open4416 0:d738e3a03cf8 227 writeReg(SYSTEM_INTERRUPT_CONFIG_GPIO, 0x04);
open4416 0:d738e3a03cf8 228 writeReg(GPIO_HV_MUX_ACTIVE_HIGH, readReg(GPIO_HV_MUX_ACTIVE_HIGH) & ~0x10); // active low
open4416 0:d738e3a03cf8 229 writeReg(SYSTEM_INTERRUPT_CLEAR, 0x01);
open4416 0:d738e3a03cf8 230
open4416 0:d738e3a03cf8 231 // -- VL53L0X_SetGpioConfig() end
open4416 0:d738e3a03cf8 232
open4416 0:d738e3a03cf8 233 measurement_timing_budget_us = getMeasurementTimingBudget();
open4416 0:d738e3a03cf8 234
open4416 0:d738e3a03cf8 235 // "Disable MSRC and TCC by default"
open4416 0:d738e3a03cf8 236 // MSRC = Minimum Signal Rate Check
open4416 0:d738e3a03cf8 237 // TCC = Target CentreCheck
open4416 0:d738e3a03cf8 238 // -- VL53L0X_SetSequenceStepEnable() begin
open4416 0:d738e3a03cf8 239
open4416 0:d738e3a03cf8 240 writeReg(SYSTEM_SEQUENCE_CONFIG, 0xE8);
open4416 0:d738e3a03cf8 241
open4416 0:d738e3a03cf8 242 // -- VL53L0X_SetSequenceStepEnable() end
open4416 0:d738e3a03cf8 243
open4416 0:d738e3a03cf8 244 // "Recalculate timing budget"
open4416 0:d738e3a03cf8 245 setMeasurementTimingBudget(measurement_timing_budget_us);
open4416 0:d738e3a03cf8 246
open4416 0:d738e3a03cf8 247 // VL53L0X_StaticInit() end
open4416 0:d738e3a03cf8 248
open4416 0:d738e3a03cf8 249 // VL53L0X_PerformRefCalibration() begin (VL53L0X_perform_ref_calibration())
open4416 0:d738e3a03cf8 250
open4416 0:d738e3a03cf8 251 // -- VL53L0X_perform_vhv_calibration() begin
open4416 0:d738e3a03cf8 252
open4416 0:d738e3a03cf8 253 writeReg(SYSTEM_SEQUENCE_CONFIG, 0x01);
open4416 0:d738e3a03cf8 254 if (!performSingleRefCalibration(0x40)) {
open4416 0:d738e3a03cf8 255 return false;
open4416 0:d738e3a03cf8 256 }
open4416 0:d738e3a03cf8 257
open4416 0:d738e3a03cf8 258 // -- VL53L0X_perform_vhv_calibration() end
open4416 0:d738e3a03cf8 259
open4416 0:d738e3a03cf8 260 // -- VL53L0X_perform_phase_calibration() begin
open4416 0:d738e3a03cf8 261
open4416 0:d738e3a03cf8 262 writeReg(SYSTEM_SEQUENCE_CONFIG, 0x02);
open4416 0:d738e3a03cf8 263 if (!performSingleRefCalibration(0x00)) {
open4416 0:d738e3a03cf8 264 return false;
open4416 0:d738e3a03cf8 265 }
open4416 0:d738e3a03cf8 266
open4416 0:d738e3a03cf8 267 // -- VL53L0X_perform_phase_calibration() end
open4416 0:d738e3a03cf8 268
open4416 0:d738e3a03cf8 269 // "restore the previous Sequence Config"
open4416 0:d738e3a03cf8 270 writeReg(SYSTEM_SEQUENCE_CONFIG, 0xE8);
open4416 0:d738e3a03cf8 271
open4416 0:d738e3a03cf8 272 // VL53L0X_PerformRefCalibration() end
open4416 0:d738e3a03cf8 273
open4416 0:d738e3a03cf8 274 return true;
open4416 0:d738e3a03cf8 275 }
open4416 0:d738e3a03cf8 276
open4416 0:d738e3a03cf8 277 // Write an 8-bit register
open4416 0:d738e3a03cf8 278 void VL53L0X::writeReg(char reg, char value)
open4416 0:d738e3a03cf8 279 {
open4416 0:d738e3a03cf8 280 data_w_2[0] = reg;
open4416 0:d738e3a03cf8 281 data_w_2[1] = value;
open4416 0:d738e3a03cf8 282 i2c.write( address<<1 | 0x00, data_w_2, 2, 0);
open4416 0:d738e3a03cf8 283 }
open4416 0:d738e3a03cf8 284
open4416 0:d738e3a03cf8 285 // Write a 16-bit register
open4416 0:d738e3a03cf8 286 void VL53L0X::writeReg16Bit(char reg, short value)
open4416 0:d738e3a03cf8 287 {
open4416 0:d738e3a03cf8 288 data_w_3[0] = reg;
open4416 0:d738e3a03cf8 289 data_w_3[1] = (value >> 8) & 0xFF;
open4416 0:d738e3a03cf8 290 data_w_3[2] = (value ) & 0xFF;
open4416 0:d738e3a03cf8 291 i2c.write( address<<1 | 0x00, data_w_3, 3, 0);
open4416 0:d738e3a03cf8 292 }
open4416 0:d738e3a03cf8 293
open4416 0:d738e3a03cf8 294 // Write a 32-bit register
open4416 0:d738e3a03cf8 295 void VL53L0X::writeReg32Bit(char reg, long value)
open4416 0:d738e3a03cf8 296 {
open4416 0:d738e3a03cf8 297 data_w_5[0] = reg;
open4416 0:d738e3a03cf8 298 data_w_5[1] = (value >> 24) & 0xFF;
open4416 0:d738e3a03cf8 299 data_w_5[2] = (value >> 16) & 0xFF;
open4416 0:d738e3a03cf8 300 data_w_5[3] = (value >> 8) & 0xFF;
open4416 0:d738e3a03cf8 301 data_w_5[4] = (value ) & 0xFF;
open4416 0:d738e3a03cf8 302 i2c.write( address<<1 | 0x00, data_w_5, 5, 0);
open4416 0:d738e3a03cf8 303 }
open4416 0:d738e3a03cf8 304
open4416 0:d738e3a03cf8 305 // Read an 8-bit register
open4416 0:d738e3a03cf8 306 char VL53L0X::readReg(char reg)
open4416 0:d738e3a03cf8 307 {
open4416 0:d738e3a03cf8 308 char value[1];
open4416 0:d738e3a03cf8 309 data_r_1[0] = reg;
open4416 0:d738e3a03cf8 310 i2c.write( address<<1 | 0x00, data_r_1, 1, 0);
open4416 0:d738e3a03cf8 311 i2c.read ( address<<1 | 0x01, value, 1, 0);
open4416 0:d738e3a03cf8 312 return value[0];
open4416 0:d738e3a03cf8 313 }
open4416 0:d738e3a03cf8 314
open4416 0:d738e3a03cf8 315 // Read a 16-bit register
open4416 0:d738e3a03cf8 316 short VL53L0X::readReg16Bit(char reg)
open4416 0:d738e3a03cf8 317 {
open4416 0:d738e3a03cf8 318 short value;
open4416 0:d738e3a03cf8 319 data_r_1[0] = reg;
open4416 0:d738e3a03cf8 320 i2c.write( address<<1 | 0x00, data_r_1, 1, 0);
open4416 0:d738e3a03cf8 321 i2c.read ( address<<1 | 0x01, data_r_2, 2, 0);
open4416 0:d738e3a03cf8 322 value = data_r_2[0] << 8 | data_r_2[1];
open4416 0:d738e3a03cf8 323 return value;
open4416 0:d738e3a03cf8 324 }
open4416 0:d738e3a03cf8 325
open4416 0:d738e3a03cf8 326 // Read a 32-bit register
open4416 0:d738e3a03cf8 327 long VL53L0X::readReg32Bit(char reg)
open4416 0:d738e3a03cf8 328 {
open4416 0:d738e3a03cf8 329 long value;
open4416 0:d738e3a03cf8 330 data_r_1[0] = reg;
open4416 0:d738e3a03cf8 331 i2c.write( address<<1 | 0x00, data_r_1, 1, 0);
open4416 0:d738e3a03cf8 332 i2c.read ( address<<1 | 0x01, data_r_4, 4, 0);
open4416 0:d738e3a03cf8 333 value = data_r_4[0] << 24;
open4416 0:d738e3a03cf8 334 value |= data_r_4[1] << 16;
open4416 0:d738e3a03cf8 335 value |= data_r_4[2] << 8;
open4416 0:d738e3a03cf8 336 value |= data_r_4[3] ;
open4416 0:d738e3a03cf8 337 return value;
open4416 0:d738e3a03cf8 338 }
open4416 0:d738e3a03cf8 339
open4416 0:d738e3a03cf8 340 // Write an arbitrary number of bytes from the given array to the sensor,
open4416 0:d738e3a03cf8 341 // starting at the given register
open4416 0:d738e3a03cf8 342 void VL53L0X::writeMulti(char reg, char const * src, char count)
open4416 0:d738e3a03cf8 343 {
open4416 0:d738e3a03cf8 344 char data_w_n[count];
open4416 0:d738e3a03cf8 345 data_w_n[0] = reg;
open4416 0:d738e3a03cf8 346 for(int i=0; i<count; i++) {
open4416 0:d738e3a03cf8 347 data_w_n[i+1] = *(src+i);
open4416 0:d738e3a03cf8 348 }
open4416 0:d738e3a03cf8 349 i2c.write( address<<1 | 0x00, data_w_n, count, 0);
open4416 0:d738e3a03cf8 350 }
open4416 0:d738e3a03cf8 351
open4416 0:d738e3a03cf8 352 // Read an arbitrary number of bytes from the sensor, starting at the given
open4416 0:d738e3a03cf8 353 // register, into the given array
open4416 0:d738e3a03cf8 354 void VL53L0X::readMulti(char reg, char * dst, char count)
open4416 0:d738e3a03cf8 355 {
open4416 0:d738e3a03cf8 356 char data_r_n[count];
open4416 0:d738e3a03cf8 357 data_r_1[0] = reg;
open4416 0:d738e3a03cf8 358 i2c.write( address<<1 | 0x00, data_r_1, 1, 0);
open4416 0:d738e3a03cf8 359 i2c.read ( address<<1 | 0x01, data_r_n, count, 0);
open4416 0:d738e3a03cf8 360 for(int i=0; i<count; i++) {
open4416 0:d738e3a03cf8 361 *(dst+i) = data_r_n[i];
open4416 0:d738e3a03cf8 362 }
open4416 0:d738e3a03cf8 363 }
open4416 0:d738e3a03cf8 364
open4416 0:d738e3a03cf8 365 // Set the return signal rate limit check value in units of MCPS (mega counts
open4416 0:d738e3a03cf8 366 // per second). "This represents the amplitude of the signal reflected from the
open4416 0:d738e3a03cf8 367 // target and detected by the device"; setting this limit presumably determines
open4416 0:d738e3a03cf8 368 // the minimum measurement necessary for the sensor to report a valid reading.
open4416 0:d738e3a03cf8 369 // Setting a lower limit increases the potential range of the sensor but also
open4416 0:d738e3a03cf8 370 // seems to increase the likelihood of getting an inaccurate reading because of
open4416 0:d738e3a03cf8 371 // unwanted reflections from objects other than the intended target.
open4416 0:d738e3a03cf8 372 // Defaults to 0.25 MCPS as initialized by the ST API and this library.
open4416 0:d738e3a03cf8 373 bool VL53L0X::setSignalRateLimit(float limit_Mcps)
open4416 0:d738e3a03cf8 374 {
open4416 0:d738e3a03cf8 375 if (limit_Mcps < 0 || limit_Mcps > 511.99f) {
open4416 0:d738e3a03cf8 376 return false;
open4416 0:d738e3a03cf8 377 }
open4416 0:d738e3a03cf8 378
open4416 0:d738e3a03cf8 379 // Q9.7 fixed point format (9 integer bits, 7 fractional bits)
open4416 0:d738e3a03cf8 380 writeReg16Bit(FINAL_RANGE_CONFIG_MIN_COUNT_RATE_RTN_LIMIT, limit_Mcps * (1 << 7));
open4416 0:d738e3a03cf8 381 return true;
open4416 0:d738e3a03cf8 382 }
open4416 0:d738e3a03cf8 383
open4416 0:d738e3a03cf8 384 // Get the return signal rate limit check value in MCPS
open4416 0:d738e3a03cf8 385 float VL53L0X::getSignalRateLimit(void)
open4416 0:d738e3a03cf8 386 {
open4416 0:d738e3a03cf8 387 return (float)readReg16Bit(FINAL_RANGE_CONFIG_MIN_COUNT_RATE_RTN_LIMIT) / (1 << 7);
open4416 0:d738e3a03cf8 388 }
open4416 0:d738e3a03cf8 389
open4416 0:d738e3a03cf8 390 // Set the measurement timing budget in microseconds, which is the time allowed
open4416 0:d738e3a03cf8 391 // for one measurement; the ST API and this library take care of splitting the
open4416 0:d738e3a03cf8 392 // timing budget among the sub-steps in the ranging sequence. A longer timing
open4416 0:d738e3a03cf8 393 // budget allows for more accurate measurements. Increasing the budget by a
open4416 0:d738e3a03cf8 394 // factor of N decreases the range measurement standard deviation by a factor of
open4416 0:d738e3a03cf8 395 // sqrt(N). Defaults to about 33 milliseconds; the minimum is 20 ms.
open4416 0:d738e3a03cf8 396 // based on VL53L0X_set_measurement_timing_budget_micro_seconds()
open4416 0:d738e3a03cf8 397 bool VL53L0X::setMeasurementTimingBudget(long budget_us)
open4416 0:d738e3a03cf8 398 {
open4416 0:d738e3a03cf8 399 SequenceStepEnables enables;
open4416 0:d738e3a03cf8 400 SequenceStepTimeouts timeouts;
open4416 0:d738e3a03cf8 401
open4416 0:d738e3a03cf8 402 short const StartOverhead = 1320; // note that this is different than the value in get_
open4416 0:d738e3a03cf8 403 short const EndOverhead = 960;
open4416 0:d738e3a03cf8 404 short const MsrcOverhead = 660;
open4416 0:d738e3a03cf8 405 short const TccOverhead = 590;
open4416 0:d738e3a03cf8 406 short const DssOverhead = 690;
open4416 0:d738e3a03cf8 407 short const PreRangeOverhead = 660;
open4416 0:d738e3a03cf8 408 short const FinalRangeOverhead = 550;
open4416 0:d738e3a03cf8 409
open4416 0:d738e3a03cf8 410 long const MinTimingBudget = 20000;
open4416 0:d738e3a03cf8 411
open4416 0:d738e3a03cf8 412 if (budget_us < MinTimingBudget) {
open4416 0:d738e3a03cf8 413 return false;
open4416 0:d738e3a03cf8 414 }
open4416 0:d738e3a03cf8 415
open4416 0:d738e3a03cf8 416 long used_budget_us = StartOverhead + EndOverhead;
open4416 0:d738e3a03cf8 417
open4416 0:d738e3a03cf8 418 getSequenceStepEnables(&enables);
open4416 0:d738e3a03cf8 419 getSequenceStepTimeouts(&enables, &timeouts);
open4416 0:d738e3a03cf8 420
open4416 0:d738e3a03cf8 421 if (enables.tcc) {
open4416 0:d738e3a03cf8 422 used_budget_us += (timeouts.msrc_dss_tcc_us + TccOverhead);
open4416 0:d738e3a03cf8 423 }
open4416 0:d738e3a03cf8 424
open4416 0:d738e3a03cf8 425 if (enables.dss) {
open4416 0:d738e3a03cf8 426 used_budget_us += 2 * (timeouts.msrc_dss_tcc_us + DssOverhead);
open4416 0:d738e3a03cf8 427 } else if (enables.msrc) {
open4416 0:d738e3a03cf8 428 used_budget_us += (timeouts.msrc_dss_tcc_us + MsrcOverhead);
open4416 0:d738e3a03cf8 429 }
open4416 0:d738e3a03cf8 430
open4416 0:d738e3a03cf8 431 if (enables.pre_range) {
open4416 0:d738e3a03cf8 432 used_budget_us += (timeouts.pre_range_us + PreRangeOverhead);
open4416 0:d738e3a03cf8 433 }
open4416 0:d738e3a03cf8 434
open4416 0:d738e3a03cf8 435 if (enables.final_range) {
open4416 0:d738e3a03cf8 436 used_budget_us += FinalRangeOverhead;
open4416 0:d738e3a03cf8 437
open4416 0:d738e3a03cf8 438 // "Note that the final range timeout is determined by the timing
open4416 0:d738e3a03cf8 439 // budget and the sum of all other timeouts within the sequence.
open4416 0:d738e3a03cf8 440 // If there is no room for the final range timeout, then an error
open4416 0:d738e3a03cf8 441 // will be set. Otherwise the remaining time will be applied to
open4416 0:d738e3a03cf8 442 // the final range."
open4416 0:d738e3a03cf8 443
open4416 0:d738e3a03cf8 444 if (used_budget_us > budget_us) {
open4416 0:d738e3a03cf8 445 // "Requested timeout too big."
open4416 0:d738e3a03cf8 446 return false;
open4416 0:d738e3a03cf8 447 }
open4416 0:d738e3a03cf8 448
open4416 0:d738e3a03cf8 449 long final_range_timeout_us = budget_us - used_budget_us;
open4416 0:d738e3a03cf8 450
open4416 0:d738e3a03cf8 451 // set_sequence_step_timeout() begin
open4416 0:d738e3a03cf8 452 // (SequenceStepId == VL53L0X_SEQUENCESTEP_FINAL_RANGE)
open4416 0:d738e3a03cf8 453
open4416 0:d738e3a03cf8 454 // "For the final range timeout, the pre-range timeout
open4416 0:d738e3a03cf8 455 // must be added. To do this both final and pre-range
open4416 0:d738e3a03cf8 456 // timeouts must be expressed in macro periods MClks
open4416 0:d738e3a03cf8 457 // because they have different vcsel periods."
open4416 0:d738e3a03cf8 458
open4416 0:d738e3a03cf8 459 short final_range_timeout_mclks =
open4416 0:d738e3a03cf8 460 timeoutMicrosecondsToMclks(final_range_timeout_us,
open4416 0:d738e3a03cf8 461 timeouts.final_range_vcsel_period_pclks);
open4416 0:d738e3a03cf8 462
open4416 0:d738e3a03cf8 463 if (enables.pre_range) {
open4416 0:d738e3a03cf8 464 final_range_timeout_mclks += timeouts.pre_range_mclks;
open4416 0:d738e3a03cf8 465 }
open4416 0:d738e3a03cf8 466
open4416 0:d738e3a03cf8 467 writeReg16Bit(FINAL_RANGE_CONFIG_TIMEOUT_MACROP_HI,
open4416 0:d738e3a03cf8 468 encodeTimeout(final_range_timeout_mclks));
open4416 0:d738e3a03cf8 469
open4416 0:d738e3a03cf8 470 // set_sequence_step_timeout() end
open4416 0:d738e3a03cf8 471
open4416 0:d738e3a03cf8 472 measurement_timing_budget_us = budget_us; // store for internal reuse
open4416 0:d738e3a03cf8 473 }
open4416 0:d738e3a03cf8 474 return true;
open4416 0:d738e3a03cf8 475 }
open4416 0:d738e3a03cf8 476
open4416 0:d738e3a03cf8 477 // Get the measurement timing budget in microseconds
open4416 0:d738e3a03cf8 478 // based on VL53L0X_get_measurement_timing_budget_micro_seconds()
open4416 0:d738e3a03cf8 479 // in us
open4416 0:d738e3a03cf8 480 long VL53L0X::getMeasurementTimingBudget(void)
open4416 0:d738e3a03cf8 481 {
open4416 0:d738e3a03cf8 482 SequenceStepEnables enables;
open4416 0:d738e3a03cf8 483 SequenceStepTimeouts timeouts;
open4416 0:d738e3a03cf8 484
open4416 0:d738e3a03cf8 485 short const StartOverhead = 1910; // note that this is different than the value in set_
open4416 0:d738e3a03cf8 486 short const EndOverhead = 960;
open4416 0:d738e3a03cf8 487 short const MsrcOverhead = 660;
open4416 0:d738e3a03cf8 488 short const TccOverhead = 590;
open4416 0:d738e3a03cf8 489 short const DssOverhead = 690;
open4416 0:d738e3a03cf8 490 short const PreRangeOverhead = 660;
open4416 0:d738e3a03cf8 491 short const FinalRangeOverhead = 550;
open4416 0:d738e3a03cf8 492
open4416 0:d738e3a03cf8 493 // "Start and end overhead times always present"
open4416 0:d738e3a03cf8 494 long budget_us = StartOverhead + EndOverhead;
open4416 0:d738e3a03cf8 495
open4416 0:d738e3a03cf8 496 getSequenceStepEnables(&enables);
open4416 0:d738e3a03cf8 497 getSequenceStepTimeouts(&enables, &timeouts);
open4416 0:d738e3a03cf8 498
open4416 0:d738e3a03cf8 499 if (enables.tcc) {
open4416 0:d738e3a03cf8 500 budget_us += (timeouts.msrc_dss_tcc_us + TccOverhead);
open4416 0:d738e3a03cf8 501 }
open4416 0:d738e3a03cf8 502
open4416 0:d738e3a03cf8 503 if (enables.dss) {
open4416 0:d738e3a03cf8 504 budget_us += 2 * (timeouts.msrc_dss_tcc_us + DssOverhead);
open4416 0:d738e3a03cf8 505 } else if (enables.msrc) {
open4416 0:d738e3a03cf8 506 budget_us += (timeouts.msrc_dss_tcc_us + MsrcOverhead);
open4416 0:d738e3a03cf8 507 }
open4416 0:d738e3a03cf8 508
open4416 0:d738e3a03cf8 509 if (enables.pre_range) {
open4416 0:d738e3a03cf8 510 budget_us += (timeouts.pre_range_us + PreRangeOverhead);
open4416 0:d738e3a03cf8 511 }
open4416 0:d738e3a03cf8 512
open4416 0:d738e3a03cf8 513 if (enables.final_range) {
open4416 0:d738e3a03cf8 514 budget_us += (timeouts.final_range_us + FinalRangeOverhead);
open4416 0:d738e3a03cf8 515 }
open4416 0:d738e3a03cf8 516
open4416 0:d738e3a03cf8 517 measurement_timing_budget_us = budget_us; // store for internal reuse
open4416 0:d738e3a03cf8 518 return budget_us;
open4416 0:d738e3a03cf8 519 }
open4416 0:d738e3a03cf8 520
open4416 0:d738e3a03cf8 521 // Set the VCSEL (vertical cavity surface emitting laser) pulse period for the
open4416 0:d738e3a03cf8 522 // given period type (pre-range or final range) to the given value in PCLKs.
open4416 0:d738e3a03cf8 523 // Longer periods seem to increase the potential range of the sensor.
open4416 0:d738e3a03cf8 524 // Valid values are (even numbers only):
open4416 0:d738e3a03cf8 525 // pre: 12 to 18 (initialized default: 14)
open4416 0:d738e3a03cf8 526 // final: 8 to 14 (initialized default: 10)
open4416 0:d738e3a03cf8 527 // based on VL53L0X_set_vcsel_pulse_period()
open4416 0:d738e3a03cf8 528 bool VL53L0X::setVcselPulsePeriod(vcselPeriodType type, char period_pclks)
open4416 0:d738e3a03cf8 529 {
open4416 0:d738e3a03cf8 530 char vcsel_period_reg = encodeVcselPeriod(period_pclks);
open4416 0:d738e3a03cf8 531
open4416 0:d738e3a03cf8 532 SequenceStepEnables enables;
open4416 0:d738e3a03cf8 533 SequenceStepTimeouts timeouts;
open4416 0:d738e3a03cf8 534
open4416 0:d738e3a03cf8 535 getSequenceStepEnables(&enables);
open4416 0:d738e3a03cf8 536 getSequenceStepTimeouts(&enables, &timeouts);
open4416 0:d738e3a03cf8 537
open4416 0:d738e3a03cf8 538 // "Apply specific settings for the requested clock period"
open4416 0:d738e3a03cf8 539 // "Re-calculate and apply timeouts, in macro periods"
open4416 0:d738e3a03cf8 540
open4416 0:d738e3a03cf8 541 // "When the VCSEL period for the pre or final range is changed,
open4416 0:d738e3a03cf8 542 // the corresponding timeout must be read from the device using
open4416 0:d738e3a03cf8 543 // the current VCSEL period, then the new VCSEL period can be
open4416 0:d738e3a03cf8 544 // applied. The timeout then must be written back to the device
open4416 0:d738e3a03cf8 545 // using the new VCSEL period.
open4416 0:d738e3a03cf8 546 //
open4416 0:d738e3a03cf8 547 // For the MSRC timeout, the same applies - this timeout being
open4416 0:d738e3a03cf8 548 // dependant on the pre-range vcsel period."
open4416 0:d738e3a03cf8 549
open4416 0:d738e3a03cf8 550
open4416 0:d738e3a03cf8 551 if (type == VcselPeriodPreRange) {
open4416 0:d738e3a03cf8 552 // "Set phase check limits"
open4416 0:d738e3a03cf8 553 switch (period_pclks) {
open4416 0:d738e3a03cf8 554 case 12:
open4416 0:d738e3a03cf8 555 writeReg(PRE_RANGE_CONFIG_VALID_PHASE_HIGH, 0x18);
open4416 0:d738e3a03cf8 556 break;
open4416 0:d738e3a03cf8 557
open4416 0:d738e3a03cf8 558 case 14:
open4416 0:d738e3a03cf8 559 writeReg(PRE_RANGE_CONFIG_VALID_PHASE_HIGH, 0x30);
open4416 0:d738e3a03cf8 560 break;
open4416 0:d738e3a03cf8 561
open4416 0:d738e3a03cf8 562 case 16:
open4416 0:d738e3a03cf8 563 writeReg(PRE_RANGE_CONFIG_VALID_PHASE_HIGH, 0x40);
open4416 0:d738e3a03cf8 564 break;
open4416 0:d738e3a03cf8 565
open4416 0:d738e3a03cf8 566 case 18:
open4416 0:d738e3a03cf8 567 writeReg(PRE_RANGE_CONFIG_VALID_PHASE_HIGH, 0x50);
open4416 0:d738e3a03cf8 568 break;
open4416 0:d738e3a03cf8 569
open4416 0:d738e3a03cf8 570 default:
open4416 0:d738e3a03cf8 571 // invalid period
open4416 0:d738e3a03cf8 572 return false;
open4416 0:d738e3a03cf8 573 }
open4416 0:d738e3a03cf8 574 writeReg(PRE_RANGE_CONFIG_VALID_PHASE_LOW, 0x08);
open4416 0:d738e3a03cf8 575
open4416 0:d738e3a03cf8 576 // apply new VCSEL period
open4416 0:d738e3a03cf8 577 writeReg(PRE_RANGE_CONFIG_VCSEL_PERIOD, vcsel_period_reg);
open4416 0:d738e3a03cf8 578
open4416 0:d738e3a03cf8 579 // update timeouts
open4416 0:d738e3a03cf8 580
open4416 0:d738e3a03cf8 581 // set_sequence_step_timeout() begin
open4416 0:d738e3a03cf8 582 // (SequenceStepId == VL53L0X_SEQUENCESTEP_PRE_RANGE)
open4416 0:d738e3a03cf8 583
open4416 0:d738e3a03cf8 584 short new_pre_range_timeout_mclks =
open4416 0:d738e3a03cf8 585 timeoutMicrosecondsToMclks(timeouts.pre_range_us, period_pclks);
open4416 0:d738e3a03cf8 586
open4416 0:d738e3a03cf8 587 writeReg16Bit(PRE_RANGE_CONFIG_TIMEOUT_MACROP_HI,
open4416 0:d738e3a03cf8 588 encodeTimeout(new_pre_range_timeout_mclks));
open4416 0:d738e3a03cf8 589
open4416 0:d738e3a03cf8 590 // set_sequence_step_timeout() end
open4416 0:d738e3a03cf8 591
open4416 0:d738e3a03cf8 592 // set_sequence_step_timeout() begin
open4416 0:d738e3a03cf8 593 // (SequenceStepId == VL53L0X_SEQUENCESTEP_MSRC)
open4416 0:d738e3a03cf8 594
open4416 0:d738e3a03cf8 595 short new_msrc_timeout_mclks =
open4416 0:d738e3a03cf8 596 timeoutMicrosecondsToMclks(timeouts.msrc_dss_tcc_us, period_pclks);
open4416 0:d738e3a03cf8 597
open4416 0:d738e3a03cf8 598 writeReg(MSRC_CONFIG_TIMEOUT_MACROP,
open4416 0:d738e3a03cf8 599 (new_msrc_timeout_mclks > 256) ? 255 : (new_msrc_timeout_mclks - 1));
open4416 0:d738e3a03cf8 600
open4416 0:d738e3a03cf8 601 // set_sequence_step_timeout() end
open4416 0:d738e3a03cf8 602 } else if (type == VcselPeriodFinalRange) {
open4416 0:d738e3a03cf8 603 switch (period_pclks) {
open4416 0:d738e3a03cf8 604 case 8:
open4416 0:d738e3a03cf8 605 writeReg(FINAL_RANGE_CONFIG_VALID_PHASE_HIGH, 0x10);
open4416 0:d738e3a03cf8 606 writeReg(FINAL_RANGE_CONFIG_VALID_PHASE_LOW, 0x08);
open4416 0:d738e3a03cf8 607 writeReg(GLOBAL_CONFIG_VCSEL_WIDTH, 0x02);
open4416 0:d738e3a03cf8 608 writeReg(ALGO_PHASECAL_CONFIG_TIMEOUT, 0x0C);
open4416 0:d738e3a03cf8 609 writeReg(0xFF, 0x01);
open4416 0:d738e3a03cf8 610 writeReg(ALGO_PHASECAL_LIM, 0x30);
open4416 0:d738e3a03cf8 611 writeReg(0xFF, 0x00);
open4416 0:d738e3a03cf8 612 break;
open4416 0:d738e3a03cf8 613
open4416 0:d738e3a03cf8 614 case 10:
open4416 0:d738e3a03cf8 615 writeReg(FINAL_RANGE_CONFIG_VALID_PHASE_HIGH, 0x28);
open4416 0:d738e3a03cf8 616 writeReg(FINAL_RANGE_CONFIG_VALID_PHASE_LOW, 0x08);
open4416 0:d738e3a03cf8 617 writeReg(GLOBAL_CONFIG_VCSEL_WIDTH, 0x03);
open4416 0:d738e3a03cf8 618 writeReg(ALGO_PHASECAL_CONFIG_TIMEOUT, 0x09);
open4416 0:d738e3a03cf8 619 writeReg(0xFF, 0x01);
open4416 0:d738e3a03cf8 620 writeReg(ALGO_PHASECAL_LIM, 0x20);
open4416 0:d738e3a03cf8 621 writeReg(0xFF, 0x00);
open4416 0:d738e3a03cf8 622 break;
open4416 0:d738e3a03cf8 623
open4416 0:d738e3a03cf8 624 case 12:
open4416 0:d738e3a03cf8 625 writeReg(FINAL_RANGE_CONFIG_VALID_PHASE_HIGH, 0x38);
open4416 0:d738e3a03cf8 626 writeReg(FINAL_RANGE_CONFIG_VALID_PHASE_LOW, 0x08);
open4416 0:d738e3a03cf8 627 writeReg(GLOBAL_CONFIG_VCSEL_WIDTH, 0x03);
open4416 0:d738e3a03cf8 628 writeReg(ALGO_PHASECAL_CONFIG_TIMEOUT, 0x08);
open4416 0:d738e3a03cf8 629 writeReg(0xFF, 0x01);
open4416 0:d738e3a03cf8 630 writeReg(ALGO_PHASECAL_LIM, 0x20);
open4416 0:d738e3a03cf8 631 writeReg(0xFF, 0x00);
open4416 0:d738e3a03cf8 632 break;
open4416 0:d738e3a03cf8 633
open4416 0:d738e3a03cf8 634 case 14:
open4416 0:d738e3a03cf8 635 writeReg(FINAL_RANGE_CONFIG_VALID_PHASE_HIGH, 0x48);
open4416 0:d738e3a03cf8 636 writeReg(FINAL_RANGE_CONFIG_VALID_PHASE_LOW, 0x08);
open4416 0:d738e3a03cf8 637 writeReg(GLOBAL_CONFIG_VCSEL_WIDTH, 0x03);
open4416 0:d738e3a03cf8 638 writeReg(ALGO_PHASECAL_CONFIG_TIMEOUT, 0x07);
open4416 0:d738e3a03cf8 639 writeReg(0xFF, 0x01);
open4416 0:d738e3a03cf8 640 writeReg(ALGO_PHASECAL_LIM, 0x20);
open4416 0:d738e3a03cf8 641 writeReg(0xFF, 0x00);
open4416 0:d738e3a03cf8 642 break;
open4416 0:d738e3a03cf8 643
open4416 0:d738e3a03cf8 644 default:
open4416 0:d738e3a03cf8 645 // invalid period
open4416 0:d738e3a03cf8 646 return false;
open4416 0:d738e3a03cf8 647 }
open4416 0:d738e3a03cf8 648
open4416 0:d738e3a03cf8 649 // apply new VCSEL period
open4416 0:d738e3a03cf8 650 writeReg(FINAL_RANGE_CONFIG_VCSEL_PERIOD, vcsel_period_reg);
open4416 0:d738e3a03cf8 651
open4416 0:d738e3a03cf8 652 // update timeouts
open4416 0:d738e3a03cf8 653
open4416 0:d738e3a03cf8 654 // set_sequence_step_timeout() begin
open4416 0:d738e3a03cf8 655 // (SequenceStepId == VL53L0X_SEQUENCESTEP_FINAL_RANGE)
open4416 0:d738e3a03cf8 656
open4416 0:d738e3a03cf8 657 // "For the final range timeout, the pre-range timeout
open4416 0:d738e3a03cf8 658 // must be added. To do this both final and pre-range
open4416 0:d738e3a03cf8 659 // timeouts must be expressed in macro periods MClks
open4416 0:d738e3a03cf8 660 // because they have different vcsel periods."
open4416 0:d738e3a03cf8 661
open4416 0:d738e3a03cf8 662 short new_final_range_timeout_mclks =
open4416 0:d738e3a03cf8 663 timeoutMicrosecondsToMclks(timeouts.final_range_us, period_pclks);
open4416 0:d738e3a03cf8 664
open4416 0:d738e3a03cf8 665 if (enables.pre_range) {
open4416 0:d738e3a03cf8 666 new_final_range_timeout_mclks += timeouts.pre_range_mclks;
open4416 0:d738e3a03cf8 667 }
open4416 0:d738e3a03cf8 668
open4416 0:d738e3a03cf8 669 writeReg16Bit(FINAL_RANGE_CONFIG_TIMEOUT_MACROP_HI,
open4416 0:d738e3a03cf8 670 encodeTimeout(new_final_range_timeout_mclks));
open4416 0:d738e3a03cf8 671
open4416 0:d738e3a03cf8 672 // set_sequence_step_timeout end
open4416 0:d738e3a03cf8 673 } else {
open4416 0:d738e3a03cf8 674 // invalid type
open4416 0:d738e3a03cf8 675 return false;
open4416 0:d738e3a03cf8 676 }
open4416 0:d738e3a03cf8 677
open4416 0:d738e3a03cf8 678 // "Finally, the timing budget must be re-applied"
open4416 0:d738e3a03cf8 679
open4416 0:d738e3a03cf8 680 setMeasurementTimingBudget(measurement_timing_budget_us);
open4416 0:d738e3a03cf8 681
open4416 0:d738e3a03cf8 682 // "Perform the phase calibration. This is needed after changing on vcsel period."
open4416 0:d738e3a03cf8 683 // VL53L0X_perform_phase_calibration() begin
open4416 0:d738e3a03cf8 684
open4416 0:d738e3a03cf8 685 char sequence_config = readReg(SYSTEM_SEQUENCE_CONFIG);
open4416 0:d738e3a03cf8 686 writeReg(SYSTEM_SEQUENCE_CONFIG, 0x02);
open4416 0:d738e3a03cf8 687 performSingleRefCalibration(0x0);
open4416 0:d738e3a03cf8 688 writeReg(SYSTEM_SEQUENCE_CONFIG, sequence_config);
open4416 0:d738e3a03cf8 689
open4416 0:d738e3a03cf8 690 // VL53L0X_perform_phase_calibration() end
open4416 0:d738e3a03cf8 691
open4416 0:d738e3a03cf8 692 return true;
open4416 0:d738e3a03cf8 693 }
open4416 0:d738e3a03cf8 694
open4416 0:d738e3a03cf8 695 // Get the VCSEL pulse period in PCLKs for the given period type.
open4416 0:d738e3a03cf8 696 // based on VL53L0X_get_vcsel_pulse_period()
open4416 0:d738e3a03cf8 697 char VL53L0X::getVcselPulsePeriod(vcselPeriodType type)
open4416 0:d738e3a03cf8 698 {
open4416 0:d738e3a03cf8 699 if (type == VcselPeriodPreRange) {
open4416 0:d738e3a03cf8 700 return decodeVcselPeriod(readReg(PRE_RANGE_CONFIG_VCSEL_PERIOD));
open4416 0:d738e3a03cf8 701 } else if (type == VcselPeriodFinalRange) {
open4416 0:d738e3a03cf8 702 return decodeVcselPeriod(readReg(FINAL_RANGE_CONFIG_VCSEL_PERIOD));
open4416 0:d738e3a03cf8 703 } else {
open4416 0:d738e3a03cf8 704 return 255;
open4416 0:d738e3a03cf8 705 }
open4416 0:d738e3a03cf8 706 }
open4416 0:d738e3a03cf8 707
open4416 0:d738e3a03cf8 708 // Start continuous ranging measurements. If period_ms (optional) is 0 or not
open4416 0:d738e3a03cf8 709 // given, continuous back-to-back mode is used (the sensor takes measurements as
open4416 0:d738e3a03cf8 710 // often as possible); otherwise, continuous timed mode is used, with the given
open4416 0:d738e3a03cf8 711 // inter-measurement period in milliseconds determining how often the sensor
open4416 0:d738e3a03cf8 712 // takes a measurement.
open4416 0:d738e3a03cf8 713 // based on VL53L0X_StartMeasurement()
open4416 0:d738e3a03cf8 714 void VL53L0X::startContinuous(long period_ms)
open4416 0:d738e3a03cf8 715 {
open4416 0:d738e3a03cf8 716 writeReg(0x80, 0x01);
open4416 0:d738e3a03cf8 717 writeReg(0xFF, 0x01);
open4416 0:d738e3a03cf8 718 writeReg(0x00, 0x00);
open4416 0:d738e3a03cf8 719 writeReg(0x91, stop_variable);
open4416 0:d738e3a03cf8 720 writeReg(0x00, 0x01);
open4416 0:d738e3a03cf8 721 writeReg(0xFF, 0x00);
open4416 0:d738e3a03cf8 722 writeReg(0x80, 0x00);
open4416 0:d738e3a03cf8 723
open4416 0:d738e3a03cf8 724 if (period_ms != 0) {
open4416 0:d738e3a03cf8 725 // continuous timed mode
open4416 0:d738e3a03cf8 726
open4416 0:d738e3a03cf8 727 // VL53L0X_SetInterMeasurementPeriodMilliSeconds() begin
open4416 0:d738e3a03cf8 728
open4416 0:d738e3a03cf8 729 short osc_calibrate_val = readReg16Bit(OSC_CALIBRATE_VAL);
open4416 0:d738e3a03cf8 730
open4416 0:d738e3a03cf8 731 if (osc_calibrate_val != 0) {
open4416 0:d738e3a03cf8 732 period_ms *= osc_calibrate_val;
open4416 0:d738e3a03cf8 733 }
open4416 0:d738e3a03cf8 734
open4416 0:d738e3a03cf8 735 writeReg32Bit(SYSTEM_INTERMEASUREMENT_PERIOD, period_ms);
open4416 0:d738e3a03cf8 736
open4416 0:d738e3a03cf8 737 // VL53L0X_SetInterMeasurementPeriodMilliSeconds() end
open4416 0:d738e3a03cf8 738
open4416 0:d738e3a03cf8 739 writeReg(SYSRANGE_START, 0x04); // VL53L0X_REG_SYSRANGE_MODE_TIMED
open4416 0:d738e3a03cf8 740 } else {
open4416 0:d738e3a03cf8 741 // continuous back-to-back mode
open4416 0:d738e3a03cf8 742 writeReg(SYSRANGE_START, 0x02); // VL53L0X_REG_SYSRANGE_MODE_BACKTOBACK
open4416 0:d738e3a03cf8 743 }
open4416 0:d738e3a03cf8 744 }
open4416 0:d738e3a03cf8 745
open4416 0:d738e3a03cf8 746 // Stop continuous measurements
open4416 0:d738e3a03cf8 747 // based on VL53L0X_StopMeasurement()
open4416 0:d738e3a03cf8 748 void VL53L0X::stopContinuous(void)
open4416 0:d738e3a03cf8 749 {
open4416 0:d738e3a03cf8 750 writeReg(SYSRANGE_START, 0x01); // VL53L0X_REG_SYSRANGE_MODE_SINGLESHOT
open4416 0:d738e3a03cf8 751
open4416 0:d738e3a03cf8 752 writeReg(0xFF, 0x01);
open4416 0:d738e3a03cf8 753 writeReg(0x00, 0x00);
open4416 0:d738e3a03cf8 754 writeReg(0x91, 0x00);
open4416 0:d738e3a03cf8 755 writeReg(0x00, 0x01);
open4416 0:d738e3a03cf8 756 writeReg(0xFF, 0x00);
open4416 0:d738e3a03cf8 757 }
open4416 0:d738e3a03cf8 758
open4416 0:d738e3a03cf8 759 // Returns a range reading in millimeters when continuous mode is active
open4416 0:d738e3a03cf8 760 // (readRangeSingleMillimeters() also calls this function after starting a
open4416 0:d738e3a03cf8 761 // single-shot range measurement)
open4416 0:d738e3a03cf8 762 short VL53L0X::readRangeContinuousMillimeters(void)
open4416 0:d738e3a03cf8 763 {
open4416 0:d738e3a03cf8 764 // startTimeout();
open4416 0:d738e3a03cf8 765 // while ((readReg(RESULT_INTERRUPT_STATUS) & 0x07) == 0) {
open4416 0:d738e3a03cf8 766 // if (checkTimeoutExpired()) {
open4416 0:d738e3a03cf8 767 // did_timeout = true;
open4416 0:d738e3a03cf8 768 // return 32767;
open4416 0:d738e3a03cf8 769 // }
open4416 0:d738e3a03cf8 770 // }
open4416 0:d738e3a03cf8 771
open4416 0:d738e3a03cf8 772 // assumptions: Linearity Corrective Gain is 1000 (default);
open4416 0:d738e3a03cf8 773 // fractional ranging is not enabled
open4416 0:d738e3a03cf8 774 short range = readReg16Bit(RESULT_RANGE_STATUS + 10);
open4416 0:d738e3a03cf8 775
open4416 0:d738e3a03cf8 776 writeReg(SYSTEM_INTERRUPT_CLEAR, 0x01);
open4416 0:d738e3a03cf8 777
open4416 0:d738e3a03cf8 778 return range;
open4416 0:d738e3a03cf8 779 }
open4416 0:d738e3a03cf8 780
open4416 0:d738e3a03cf8 781 // Performs a single-shot range measurement and returns the reading in
open4416 0:d738e3a03cf8 782 // millimeters
open4416 0:d738e3a03cf8 783 // based on VL53L0X_PerformSingleRangingMeasurement()
open4416 0:d738e3a03cf8 784 short VL53L0X::readRangeSingleMillimeters(void)
open4416 0:d738e3a03cf8 785 {
open4416 0:d738e3a03cf8 786 writeReg(0x80, 0x01);
open4416 0:d738e3a03cf8 787 writeReg(0xFF, 0x01);
open4416 0:d738e3a03cf8 788 writeReg(0x00, 0x00);
open4416 0:d738e3a03cf8 789 writeReg(0x91, stop_variable);
open4416 0:d738e3a03cf8 790 writeReg(0x00, 0x01);
open4416 0:d738e3a03cf8 791 writeReg(0xFF, 0x00);
open4416 0:d738e3a03cf8 792 writeReg(0x80, 0x00);
open4416 0:d738e3a03cf8 793
open4416 0:d738e3a03cf8 794 writeReg(SYSRANGE_START, 0x01);
open4416 0:d738e3a03cf8 795
open4416 0:d738e3a03cf8 796 // "Wait until start bit has been cleared"
open4416 0:d738e3a03cf8 797 // startTimeout();
open4416 0:d738e3a03cf8 798 // while (readReg(SYSRANGE_START) & 0x01) {
open4416 0:d738e3a03cf8 799 // if (checkTimeoutExpired()) {
open4416 0:d738e3a03cf8 800 // did_timeout = true;
open4416 0:d738e3a03cf8 801 // return 32767;
open4416 0:d738e3a03cf8 802 // }
open4416 0:d738e3a03cf8 803 // }
open4416 0:d738e3a03cf8 804
open4416 0:d738e3a03cf8 805 return readRangeContinuousMillimeters();
open4416 0:d738e3a03cf8 806 }
open4416 0:d738e3a03cf8 807
open4416 0:d738e3a03cf8 808 // Did a timeout occur in one of the read functions since the last call to
open4416 0:d738e3a03cf8 809 // timeoutOccurred()?
open4416 0:d738e3a03cf8 810 bool VL53L0X::timeoutOccurred()
open4416 0:d738e3a03cf8 811 {
open4416 0:d738e3a03cf8 812 bool tmp = did_timeout;
open4416 0:d738e3a03cf8 813 did_timeout = false;
open4416 0:d738e3a03cf8 814 return tmp;
open4416 0:d738e3a03cf8 815 }
open4416 0:d738e3a03cf8 816
open4416 0:d738e3a03cf8 817 // Private Methods /////////////////////////////////////////////////////////////
open4416 0:d738e3a03cf8 818
open4416 0:d738e3a03cf8 819 // Get reference SPAD (single photon avalanche diode) count and type
open4416 0:d738e3a03cf8 820 // based on VL53L0X_get_info_from_device(),
open4416 0:d738e3a03cf8 821 // but only gets reference SPAD count and type
open4416 0:d738e3a03cf8 822 bool VL53L0X::getSpadInfo(char * count, bool * type_is_aperture)
open4416 0:d738e3a03cf8 823 {
open4416 0:d738e3a03cf8 824 char tmp;
open4416 0:d738e3a03cf8 825
open4416 0:d738e3a03cf8 826 writeReg(0x80, 0x01);
open4416 0:d738e3a03cf8 827 writeReg(0xFF, 0x01);
open4416 0:d738e3a03cf8 828 writeReg(0x00, 0x00);
open4416 0:d738e3a03cf8 829
open4416 0:d738e3a03cf8 830 writeReg(0xFF, 0x06);
open4416 0:d738e3a03cf8 831 writeReg(0x83, readReg(0x83) | 0x04);
open4416 0:d738e3a03cf8 832 writeReg(0xFF, 0x07);
open4416 0:d738e3a03cf8 833 writeReg(0x81, 0x01);
open4416 0:d738e3a03cf8 834
open4416 0:d738e3a03cf8 835 writeReg(0x80, 0x01);
open4416 0:d738e3a03cf8 836
open4416 0:d738e3a03cf8 837 writeReg(0x94, 0x6b);
open4416 0:d738e3a03cf8 838 writeReg(0x83, 0x00);
open4416 0:d738e3a03cf8 839 // startTimeout();
open4416 0:d738e3a03cf8 840 wait_ms(1);
open4416 0:d738e3a03cf8 841 while (readReg(0x83) == 0x00) {
open4416 0:d738e3a03cf8 842 // if (checkTimeoutExpired()) {
open4416 0:d738e3a03cf8 843 // return false;
open4416 0:d738e3a03cf8 844 // }
open4416 0:d738e3a03cf8 845 }
open4416 0:d738e3a03cf8 846 writeReg(0x83, 0x01);
open4416 0:d738e3a03cf8 847 tmp = readReg(0x92);
open4416 0:d738e3a03cf8 848
open4416 0:d738e3a03cf8 849 *count = tmp & 0x7f;
open4416 0:d738e3a03cf8 850 *type_is_aperture = (tmp >> 7) & 0x01;
open4416 0:d738e3a03cf8 851
open4416 0:d738e3a03cf8 852 writeReg(0x81, 0x00);
open4416 0:d738e3a03cf8 853 writeReg(0xFF, 0x06);
open4416 0:d738e3a03cf8 854 writeReg(0x83, readReg( 0x83 & ~0x04));
open4416 0:d738e3a03cf8 855 writeReg(0xFF, 0x01);
open4416 0:d738e3a03cf8 856 writeReg(0x00, 0x01);
open4416 0:d738e3a03cf8 857
open4416 0:d738e3a03cf8 858 writeReg(0xFF, 0x00);
open4416 0:d738e3a03cf8 859 writeReg(0x80, 0x00);
open4416 0:d738e3a03cf8 860
open4416 0:d738e3a03cf8 861 return true;
open4416 0:d738e3a03cf8 862 }
open4416 0:d738e3a03cf8 863
open4416 0:d738e3a03cf8 864 // Get sequence step enables
open4416 0:d738e3a03cf8 865 // based on VL53L0X_GetSequenceStepEnables()
open4416 0:d738e3a03cf8 866 void VL53L0X::getSequenceStepEnables(SequenceStepEnables * enables)
open4416 0:d738e3a03cf8 867 {
open4416 0:d738e3a03cf8 868 char sequence_config = readReg(SYSTEM_SEQUENCE_CONFIG);
open4416 0:d738e3a03cf8 869
open4416 0:d738e3a03cf8 870 enables->tcc = (sequence_config >> 4) & 0x1;
open4416 0:d738e3a03cf8 871 enables->dss = (sequence_config >> 3) & 0x1;
open4416 0:d738e3a03cf8 872 enables->msrc = (sequence_config >> 2) & 0x1;
open4416 0:d738e3a03cf8 873 enables->pre_range = (sequence_config >> 6) & 0x1;
open4416 0:d738e3a03cf8 874 enables->final_range = (sequence_config >> 7) & 0x1;
open4416 0:d738e3a03cf8 875 }
open4416 0:d738e3a03cf8 876
open4416 0:d738e3a03cf8 877 // Get sequence step timeouts
open4416 0:d738e3a03cf8 878 // based on get_sequence_step_timeout(),
open4416 0:d738e3a03cf8 879 // but gets all timeouts instead of just the requested one, and also stores
open4416 0:d738e3a03cf8 880 // intermediate values
open4416 0:d738e3a03cf8 881 void VL53L0X::getSequenceStepTimeouts(SequenceStepEnables const * enables, SequenceStepTimeouts * timeouts)
open4416 0:d738e3a03cf8 882 {
open4416 0:d738e3a03cf8 883 timeouts->pre_range_vcsel_period_pclks = getVcselPulsePeriod(VcselPeriodPreRange);
open4416 0:d738e3a03cf8 884
open4416 0:d738e3a03cf8 885 timeouts->msrc_dss_tcc_mclks = readReg(MSRC_CONFIG_TIMEOUT_MACROP) + 1;
open4416 0:d738e3a03cf8 886 timeouts->msrc_dss_tcc_us =
open4416 0:d738e3a03cf8 887 timeoutMclksToMicroseconds(timeouts->msrc_dss_tcc_mclks,
open4416 0:d738e3a03cf8 888 timeouts->pre_range_vcsel_period_pclks);
open4416 0:d738e3a03cf8 889
open4416 0:d738e3a03cf8 890 timeouts->pre_range_mclks =
open4416 0:d738e3a03cf8 891 decodeTimeout(readReg16Bit(PRE_RANGE_CONFIG_TIMEOUT_MACROP_HI));
open4416 0:d738e3a03cf8 892 timeouts->pre_range_us =
open4416 0:d738e3a03cf8 893 timeoutMclksToMicroseconds(timeouts->pre_range_mclks,
open4416 0:d738e3a03cf8 894 timeouts->pre_range_vcsel_period_pclks);
open4416 0:d738e3a03cf8 895
open4416 0:d738e3a03cf8 896 timeouts->final_range_vcsel_period_pclks = getVcselPulsePeriod(VcselPeriodFinalRange);
open4416 0:d738e3a03cf8 897
open4416 0:d738e3a03cf8 898 timeouts->final_range_mclks =
open4416 0:d738e3a03cf8 899 decodeTimeout(readReg16Bit(FINAL_RANGE_CONFIG_TIMEOUT_MACROP_HI));
open4416 0:d738e3a03cf8 900
open4416 0:d738e3a03cf8 901 if (enables->pre_range) {
open4416 0:d738e3a03cf8 902 timeouts->final_range_mclks -= timeouts->pre_range_mclks;
open4416 0:d738e3a03cf8 903 }
open4416 0:d738e3a03cf8 904
open4416 0:d738e3a03cf8 905 timeouts->final_range_us =
open4416 0:d738e3a03cf8 906 timeoutMclksToMicroseconds(timeouts->final_range_mclks,
open4416 0:d738e3a03cf8 907 timeouts->final_range_vcsel_period_pclks);
open4416 0:d738e3a03cf8 908 }
open4416 0:d738e3a03cf8 909
open4416 0:d738e3a03cf8 910 // Decode sequence step timeout in MCLKs from register value
open4416 0:d738e3a03cf8 911 // based on VL53L0X_decode_timeout()
open4416 0:d738e3a03cf8 912 // Note: the original function returned a long, but the return value is
open4416 0:d738e3a03cf8 913 // always stored in a short.
open4416 0:d738e3a03cf8 914 short VL53L0X::decodeTimeout(short reg_val)
open4416 0:d738e3a03cf8 915 {
open4416 0:d738e3a03cf8 916 // format: "(LSByte * 2^MSByte) + 1"
open4416 0:d738e3a03cf8 917 return (short)((reg_val & 0x00FF) <<
open4416 0:d738e3a03cf8 918 (short)((reg_val & 0xFF00) >> 8)) + 1;
open4416 0:d738e3a03cf8 919 }
open4416 0:d738e3a03cf8 920
open4416 0:d738e3a03cf8 921 // Encode sequence step timeout register value from timeout in MCLKs
open4416 0:d738e3a03cf8 922 // based on VL53L0X_encode_timeout()
open4416 0:d738e3a03cf8 923 // Note: the original function took a short, but the argument passed to it
open4416 0:d738e3a03cf8 924 // is always a short.
open4416 0:d738e3a03cf8 925 short VL53L0X::encodeTimeout(short timeout_mclks)
open4416 0:d738e3a03cf8 926 {
open4416 0:d738e3a03cf8 927 // format: "(LSByte * 2^MSByte) + 1"
open4416 0:d738e3a03cf8 928
open4416 0:d738e3a03cf8 929 long ls_byte = 0;
open4416 0:d738e3a03cf8 930 short ms_byte = 0;
open4416 0:d738e3a03cf8 931
open4416 0:d738e3a03cf8 932 if (timeout_mclks > 0) {
open4416 0:d738e3a03cf8 933 ls_byte = timeout_mclks - 1;
open4416 0:d738e3a03cf8 934
open4416 0:d738e3a03cf8 935 while ((ls_byte & 0xFFFFFF00) > 0) {
open4416 0:d738e3a03cf8 936 ls_byte >>= 1;
open4416 0:d738e3a03cf8 937 ms_byte++;
open4416 0:d738e3a03cf8 938 }
open4416 0:d738e3a03cf8 939
open4416 0:d738e3a03cf8 940 return (ms_byte << 8) | (ls_byte & 0xFF);
open4416 0:d738e3a03cf8 941 } else {
open4416 0:d738e3a03cf8 942 return 0;
open4416 0:d738e3a03cf8 943 }
open4416 0:d738e3a03cf8 944 }
open4416 0:d738e3a03cf8 945
open4416 0:d738e3a03cf8 946 // Convert sequence step timeout from MCLKs to microseconds with given VCSEL period in PCLKs
open4416 0:d738e3a03cf8 947 // based on VL53L0X_calc_timeout_us()
open4416 0:d738e3a03cf8 948 long VL53L0X::timeoutMclksToMicroseconds(short timeout_period_mclks, char vcsel_period_pclks)
open4416 0:d738e3a03cf8 949 {
open4416 0:d738e3a03cf8 950 long macro_period_ns = calcMacroPeriod(vcsel_period_pclks);
open4416 0:d738e3a03cf8 951
open4416 0:d738e3a03cf8 952 return ((timeout_period_mclks * macro_period_ns) + (macro_period_ns / 2)) / 1000;
open4416 0:d738e3a03cf8 953 }
open4416 0:d738e3a03cf8 954
open4416 0:d738e3a03cf8 955 // Convert sequence step timeout from microseconds to MCLKs with given VCSEL period in PCLKs
open4416 0:d738e3a03cf8 956 // based on VL53L0X_calc_timeout_mclks()
open4416 0:d738e3a03cf8 957 long VL53L0X::timeoutMicrosecondsToMclks(long timeout_period_us, char vcsel_period_pclks)
open4416 0:d738e3a03cf8 958 {
open4416 0:d738e3a03cf8 959 long macro_period_ns = calcMacroPeriod(vcsel_period_pclks);
open4416 0:d738e3a03cf8 960
open4416 0:d738e3a03cf8 961 return (((timeout_period_us * 1000) + (macro_period_ns / 2)) / macro_period_ns);
open4416 0:d738e3a03cf8 962 }
open4416 0:d738e3a03cf8 963
open4416 0:d738e3a03cf8 964
open4416 0:d738e3a03cf8 965 // based on VL53L0X_perform_single_ref_calibration()
open4416 0:d738e3a03cf8 966 bool VL53L0X::performSingleRefCalibration(char vhv_init_byte)
open4416 0:d738e3a03cf8 967 {
open4416 0:d738e3a03cf8 968 writeReg(SYSRANGE_START, 0x01 | vhv_init_byte); // VL53L0X_REG_SYSRANGE_MODE_START_STOP
open4416 0:d738e3a03cf8 969
open4416 0:d738e3a03cf8 970 // startTimeout();
open4416 0:d738e3a03cf8 971 wait_ms(1);
open4416 0:d738e3a03cf8 972 while ((readReg(RESULT_INTERRUPT_STATUS) & 0x07) == 0) {
open4416 0:d738e3a03cf8 973 // if (checkTimeoutExpired()) {
open4416 0:d738e3a03cf8 974 // return false;
open4416 0:d738e3a03cf8 975 // }
open4416 0:d738e3a03cf8 976 }
open4416 0:d738e3a03cf8 977
open4416 0:d738e3a03cf8 978 writeReg(SYSTEM_INTERRUPT_CLEAR, 0x01);
open4416 0:d738e3a03cf8 979
open4416 0:d738e3a03cf8 980 writeReg(SYSRANGE_START, 0x00);
open4416 0:d738e3a03cf8 981
open4416 0:d738e3a03cf8 982 return true;
open4416 0:d738e3a03cf8 983 }