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Diff: targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_usart.h
- Revision:
- 50:a417edff4437
- Parent:
- 0:9b334a45a8ff
- Child:
- 144:ef7eb2e8f9f7
diff -r 57ac6e3cdfd3 -r a417edff4437 targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_usart.h
--- a/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_usart.h Wed Jan 13 12:45:11 2016 +0000
+++ b/targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_usart.h Fri Jan 15 07:45:16 2016 +0000
@@ -2,10 +2,10 @@
* @file em_usart.h
* @brief Universal synchronous/asynchronous receiver/transmitter (USART/UART)
* peripheral API
- * @version 3.20.12
+ * @version 4.2.1
*******************************************************************************
* @section License
- * <b>(C) Copyright 2014 Silicon Labs, http://www.silabs.com</b>
+ * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
*******************************************************************************
*
* Permission is granted to anyone to use this software for any purpose,
@@ -32,8 +32,8 @@
******************************************************************************/
-#ifndef __SILICON_LABS_EM_USART_H_
-#define __SILICON_LABS_EM_USART_H_
+#ifndef __SILICON_LABS_EM_USART_H__
+#define __SILICON_LABS_EM_USART_H__
#include "em_device.h"
#if defined(USART_COUNT) && (USART_COUNT > 0)
@@ -165,21 +165,21 @@
usartIrDAPrsCh1 = USART_IRCTRL_IRPRSSEL_PRSCH1, /**< PRS channel 1 */
usartIrDAPrsCh2 = USART_IRCTRL_IRPRSSEL_PRSCH2, /**< PRS channel 2 */
usartIrDAPrsCh3 = USART_IRCTRL_IRPRSSEL_PRSCH3, /**< PRS channel 3 */
-#if defined( USART_IRCTRL_IRPRSSEL_PRSCH4 )
+#if defined(USART_IRCTRL_IRPRSSEL_PRSCH4)
usartIrDAPrsCh4 = USART_IRCTRL_IRPRSSEL_PRSCH4, /**< PRS channel 4 */
#endif
-#if defined( USART_IRCTRL_IRPRSSEL_PRSCH5 )
+#if defined(USART_IRCTRL_IRPRSSEL_PRSCH5)
usartIrDAPrsCh5 = USART_IRCTRL_IRPRSSEL_PRSCH5, /**< PRS channel 5 */
#endif
-#if defined( USART_IRCTRL_IRPRSSEL_PRSCH6 )
+#if defined(USART_IRCTRL_IRPRSSEL_PRSCH6)
usartIrDAPrsCh6 = USART_IRCTRL_IRPRSSEL_PRSCH6, /**< PRS channel 6 */
#endif
-#if defined( USART_IRCTRL_IRPRSSEL_PRSCH7 )
+#if defined(USART_IRCTRL_IRPRSSEL_PRSCH7)
usartIrDAPrsCh7 = USART_IRCTRL_IRPRSSEL_PRSCH7, /**< PRS channel 7 */
#endif
} USART_IrDAPrsSel_Typedef;
-#if defined( _USART_I2SCTRL_MASK )
+#if defined(_USART_I2SCTRL_MASK)
/** I2S format selection. */
typedef enum
{
@@ -201,7 +201,7 @@
} USART_I2sJustify_TypeDef;
#endif
-#if defined( _USART_INPUT_MASK )
+#if defined(_USART_INPUT_MASK)
/** USART Rx input PRS selection. */
typedef enum
{
@@ -210,14 +210,14 @@
usartPrsRxCh2 = USART_INPUT_RXPRSSEL_PRSCH2, /**< PRSCH2 selected as USART_INPUT */
usartPrsRxCh3 = USART_INPUT_RXPRSSEL_PRSCH3, /**< PRSCH3 selected as USART_INPUT */
-#if defined( USART_INPUT_RXPRSSEL_PRSCH7 )
+#if defined(USART_INPUT_RXPRSSEL_PRSCH7)
usartPrsRxCh4 = USART_INPUT_RXPRSSEL_PRSCH4, /**< PRSCH4 selected as USART_INPUT */
usartPrsRxCh5 = USART_INPUT_RXPRSSEL_PRSCH5, /**< PRSCH5 selected as USART_INPUT */
usartPrsRxCh6 = USART_INPUT_RXPRSSEL_PRSCH6, /**< PRSCH6 selected as USART_INPUT */
usartPrsRxCh7 = USART_INPUT_RXPRSSEL_PRSCH7, /**< PRSCH7 selected as USART_INPUT */
#endif
-#if defined( USART_INPUT_RXPRSSEL_PRSCH11 )
+#if defined(USART_INPUT_RXPRSSEL_PRSCH11)
usartPrsRxCh8 = USART_INPUT_RXPRSSEL_PRSCH8, /**< PRSCH8 selected as USART_INPUT */
usartPrsRxCh9 = USART_INPUT_RXPRSSEL_PRSCH9, /**< PRSCH9 selected as USART_INPUT */
usartPrsRxCh10 = USART_INPUT_RXPRSSEL_PRSCH10, /**< PRSCH10 selected as USART_INPUT */
@@ -234,7 +234,7 @@
usartPrsTriggerCh2 = USART_TRIGCTRL_TSEL_PRSCH2, /**< PRSCH0 selected as USART Trigger */
usartPrsTriggerCh3 = USART_TRIGCTRL_TSEL_PRSCH3, /**< PRSCH0 selected as USART Trigger */
-#if defined( USART_TRIGCTRL_TSEL_PRSCH7 )
+#if defined(USART_TRIGCTRL_TSEL_PRSCH7)
usartPrsTriggerCh4 = USART_TRIGCTRL_TSEL_PRSCH4, /**< PRSCH0 selected as USART Trigger */
usartPrsTriggerCh5 = USART_TRIGCTRL_TSEL_PRSCH5, /**< PRSCH0 selected as USART Trigger */
usartPrsTriggerCh6 = USART_TRIGCTRL_TSEL_PRSCH6, /**< PRSCH0 selected as USART Trigger */
@@ -274,7 +274,7 @@
/** Number of stopbits to use. */
USART_Stopbits_TypeDef stopbits;
-#if defined( USART_INPUT_RXPRS ) && defined( USART_CTRL_MVDIS )
+#if defined(USART_INPUT_RXPRS) && defined(USART_CTRL_MVDIS)
/** Majority Vote Disable for 16x, 8x and 6x oversampling modes. */
bool mvdis;
@@ -284,12 +284,20 @@
/** Select PRS channel for USART Rx. (Only valid if prsRxEnable is true). */
USART_PrsRxCh_TypeDef prsRxCh;
#endif
+#if defined(_USART_TIMING_CSHOLD_MASK)
+ /** Auto CS enabling */
+ bool autoCsEnable;
+ /** Auto CS hold time in baud cycles */
+ uint8_t autoCsHold;
+ /** Auto CS setup time in baud cycles */
+ uint8_t autoCsSetup;
+#endif
} USART_InitAsync_TypeDef;
/** USART PRS trigger enable */
typedef struct
{
-#if defined( USART_TRIGCTRL_AUTOTXTEN )
+#if defined(USART_TRIGCTRL_AUTOTXTEN)
/** Enable AUTOTX */
bool autoTxTriggerEnable;
#endif
@@ -302,45 +310,66 @@
} USART_PrsTriggerInit_TypeDef;
/** Default config for USART async init structure. */
-#if defined( USART_INPUT_RXPRS ) && defined( USART_CTRL_MVDIS )
-#define USART_INITASYNC_DEFAULT \
- { usartEnable, /* Enable RX/TX when init completed. */ \
- 0, /* Use current configured reference clock for configuring baudrate. */ \
- 115200, /* 115200 bits/s. */ \
- usartOVS16, /* 16x oversampling. */ \
- usartDatabits8, /* 8 databits. */ \
- usartNoParity, /* No parity. */ \
- usartStopbits1, /* 1 stopbit. */ \
- false, /* Do not disable majority vote. */ \
- false, /* Not USART PRS input mode. */ \
- usartPrsRxCh0 /* PRS channel 0. */ \
- }
+#if defined(_USART_TIMING_CSHOLD_MASK) && defined(USART_CTRL_MVDIS)
+#define USART_INITASYNC_DEFAULT \
+{ \
+ usartEnable, /* Enable RX/TX when init completed. */ \
+ 0, /* Use current configured reference clock for configuring baudrate. */ \
+ 115200, /* 115200 bits/s. */ \
+ usartOVS16, /* 16x oversampling. */ \
+ usartDatabits8, /* 8 databits. */ \
+ usartNoParity, /* No parity. */ \
+ usartStopbits1, /* 1 stopbit. */ \
+ false, /* Do not disable majority vote. */ \
+ false, /* Not USART PRS input mode. */ \
+ usartPrsRxCh0, /* PRS channel 0. */ \
+ false, /* Auto CS functionality enable/disable switch */ \
+ 0, /* Auto CS Hold cycles */ \
+ 0 /* Auto CS Setup cycles */ \
+}
+#elif defined(USART_INPUT_RXPRS) && defined(USART_CTRL_MVDIS)
+#define USART_INITASYNC_DEFAULT \
+{ \
+ usartEnable, /* Enable RX/TX when init completed. */ \
+ 0, /* Use current configured reference clock for configuring baudrate. */ \
+ 115200, /* 115200 bits/s. */ \
+ usartOVS16, /* 16x oversampling. */ \
+ usartDatabits8, /* 8 databits. */ \
+ usartNoParity, /* No parity. */ \
+ usartStopbits1, /* 1 stopbit. */ \
+ false, /* Do not disable majority vote. */ \
+ false, /* Not USART PRS input mode. */ \
+ usartPrsRxCh0 /* PRS channel 0. */ \
+}
#else
-#define USART_INITASYNC_DEFAULT \
- { usartEnable, /* Enable RX/TX when init completed. */ \
- 0, /* Use current configured reference clock for configuring baudrate. */ \
- 115200, /* 115200 bits/s. */ \
- usartOVS16, /* 16x oversampling. */ \
- usartDatabits8, /* 8 databits. */ \
- usartNoParity, /* No parity. */ \
- usartStopbits1 /* 1 stopbit. */ \
- }
+#define USART_INITASYNC_DEFAULT \
+{ \
+ usartEnable, /* Enable RX/TX when init completed. */ \
+ 0, /* Use current configured reference clock for configuring baudrate. */ \
+ 115200, /* 115200 bits/s. */ \
+ usartOVS16, /* 16x oversampling. */ \
+ usartDatabits8, /* 8 databits. */ \
+ usartNoParity, /* No parity. */ \
+ usartStopbits1 /* 1 stopbit. */ \
+}
#endif
/** Default config for USART PRS triggering structure. */
-#if defined ( USART_TRIGCTRL_AUTOTXTEN )
-#define USART_INITPRSTRIGGER_DEFAULT \
- { false, /* Do not enable autoTX triggering. */ \
- false, /* Do not enable receive triggering. */ \
- false, /* Do not enable transmit triggering. */ \
- usartPrsTriggerCh0 /* Set default channel to zero. */ \
- }
+#if defined(USART_TRIGCTRL_AUTOTXTEN)
+#define USART_INITPRSTRIGGER_DEFAULT \
+{ \
+ false, /* Do not enable autoTX triggering. */ \
+ false, /* Do not enable receive triggering. */ \
+ false, /* Do not enable transmit triggering. */ \
+ usartPrsTriggerCh0 /* Set default channel to zero. */ \
+}
#else
-#define USART_INITPRSTRIGGER_DEFAULT \
- { false, /* Do not enable receive triggering. */ \
- false, /* Do not enable transmit triggering. */ \
- usartPrsTriggerCh0 /* Set default channel to zero. */ \
- }
+#define USART_INITPRSTRIGGER_DEFAULT \
+{ \
+ false, /* Do not enable receive triggering. */ \
+ false, /* Do not enable transmit triggering. */ \
+ usartPrsTriggerCh0 /* Set default channel to zero. */ \
+}
#endif
/** Synchronous mode init structure. */
@@ -370,7 +399,7 @@
/** Clock polarity/phase mode. */
USART_ClockMode_TypeDef clockMode;
-#if defined( USART_INPUT_RXPRS ) && defined( USART_TRIGCTRL_AUTOTXTEN )
+#if defined(USART_INPUT_RXPRS) && defined(USART_TRIGCTRL_AUTOTXTEN)
/** Enable USART Rx via PRS. */
bool prsRxEnable;
@@ -381,32 +410,59 @@
* If TX is empty, underflows are generated. */
bool autoTx;
#endif
+#if defined(_USART_TIMING_CSHOLD_MASK)
+ /** Auto CS enabling */
+ bool autoCsEnable;
+ /** Auto CS hold time in baud cycles */
+ uint8_t autoCsHold;
+ /** Auto CS setup time in baud cycles */
+ uint8_t autoCsSetup;
+#endif
} USART_InitSync_TypeDef;
/** Default config for USART sync init structure. */
-#if defined( USART_INPUT_RXPRS ) && defined( USART_TRIGCTRL_AUTOTXTEN )
-#define USART_INITSYNC_DEFAULT \
- { usartEnable, /* Enable RX/TX when init completed. */ \
- 0, /* Use current configured reference clock for configuring baudrate. */ \
- 1000000, /* 1 Mbits/s. */ \
- usartDatabits8, /* 8 databits. */ \
- true, /* Master mode. */ \
- false, /* Send least significant bit first. */ \
- usartClockMode0, /* Clock idle low, sample on rising edge. */ \
- false, /* Not USART PRS input mode. */ \
- usartPrsRxCh0, /* PRS channel 0. */ \
- false /* No AUTOTX mode. */ \
- }
+#if defined(_USART_TIMING_CSHOLD_MASK)
+#define USART_INITSYNC_DEFAULT \
+{ \
+ usartEnable, /* Enable RX/TX when init completed. */ \
+ 0, /* Use current configured reference clock for configuring baudrate. */ \
+ 1000000, /* 1 Mbits/s. */ \
+ usartDatabits8, /* 8 databits. */ \
+ true, /* Master mode. */ \
+ false, /* Send least significant bit first. */ \
+ usartClockMode0, /* Clock idle low, sample on rising edge. */ \
+ false, /* Not USART PRS input mode. */ \
+ usartPrsRxCh0, /* PRS channel 0. */ \
+ false, /* No AUTOTX mode. */ \
+ false, /* No AUTOCS mode */ \
+ 0, /* Auto CS Hold cycles */ \
+ 0 /* Auto CS Setup cycles */ \
+}
+#elif defined(USART_INPUT_RXPRS) && defined(USART_TRIGCTRL_AUTOTXTEN)
+#define USART_INITSYNC_DEFAULT \
+{ \
+ usartEnable, /* Enable RX/TX when init completed. */ \
+ 0, /* Use current configured reference clock for configuring baudrate. */ \
+ 1000000, /* 1 Mbits/s. */ \
+ usartDatabits8, /* 8 databits. */ \
+ true, /* Master mode. */ \
+ false, /* Send least significant bit first. */ \
+ usartClockMode0, /* Clock idle low, sample on rising edge. */ \
+ false, /* Not USART PRS input mode. */ \
+ usartPrsRxCh0, /* PRS channel 0. */ \
+ false /* No AUTOTX mode. */ \
+}
#else
-#define USART_INITSYNC_DEFAULT \
- { usartEnable, /* Enable RX/TX when init completed. */ \
- 0, /* Use current configured reference clock for configuring baudrate. */ \
- 1000000, /* 1 Mbits/s. */ \
- usartDatabits8, /* 8 databits. */ \
- true, /* Master mode. */ \
- false, /* Send least significant bit first. */ \
- usartClockMode0 /* Clock idle low, sample on rising edge. */ \
- }
+#define USART_INITSYNC_DEFAULT \
+{ \
+ usartEnable, /* Enable RX/TX when init completed. */ \
+ 0, /* Use current configured reference clock for configuring baudrate. */ \
+ 1000000, /* 1 Mbits/s. */ \
+ usartDatabits8, /* 8 databits. */ \
+ true, /* Master mode. */ \
+ false, /* Send least significant bit first. */ \
+ usartClockMode0 /* Clock idle low, sample on rising edge. */ \
+}
#endif
@@ -437,25 +493,26 @@
/** Default config for IrDA mode init structure. */
-#define USART_INITIRDA_DEFAULT \
- { \
- { usartEnable, /* Enable RX/TX when init completed. */ \
- 0, /* Use current configured reference clock for configuring baudrate. */ \
- 115200, /* 115200 bits/s. */ \
- usartOVS16, /* 16x oversampling. */ \
- usartDatabits8, /* 8 databits. */ \
- usartEvenParity, /* Even parity. */ \
- usartStopbits1 /* 1 stopbit. */ \
- }, \
- false, /* Rx invert disabled. */ \
- false, /* Filtering disabled. */ \
- usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \
- false, /* Routing to PRS is disabled. */ \
- usartIrDAPrsCh0 /* PRS channel 0. */ \
- }
+#define USART_INITIRDA_DEFAULT \
+{ \
+ { \
+ usartEnable, /* Enable RX/TX when init completed. */ \
+ 0, /* Use current configured reference clock for configuring baudrate. */ \
+ 115200, /* 115200 bits/s. */ \
+ usartOVS16, /* 16x oversampling. */ \
+ usartDatabits8, /* 8 databits. */ \
+ usartEvenParity, /* Even parity. */ \
+ usartStopbits1 /* 1 stopbit. */ \
+ }, \
+ false, /* Rx invert disabled. */ \
+ false, /* Filtering disabled. */ \
+ usartIrDAPwTHREE, /* Pulse width is set to ONE. */ \
+ false, /* Routing to PRS is disabled. */ \
+ usartIrDAPrsCh0 /* PRS channel 0. */ \
+}
-#if defined( _USART_I2SCTRL_MASK )
+#if defined(_USART_I2SCTRL_MASK)
/** I2S mode init structure. Inherited from synchronous mode init structure */
typedef struct
{
@@ -482,25 +539,26 @@
/** Default config for I2S mode init structure. */
-#define USART_INITI2S_DEFAULT \
- { \
- { usartEnableTx, /* Enable TX when init completed. */ \
- 0, /* Use current configured reference clock for configuring baudrate. */ \
- 1000000, /* Baudrate 1M bits/s. */ \
- usartDatabits16, /* 16 databits. */ \
- true, /* Operate as I2S master. */ \
- true, /* Most significant bit first. */ \
- usartClockMode0, /* Clock idle low, sample on rising edge. */ \
- false, /* Don't enable USARTRx via PRS. */ \
- usartPrsRxCh0, /* PRS channel selection (dummy). */ \
- false /* Disable AUTOTX mode. */ \
- }, \
- usartI2sFormatW16D16, /* 16-bit word, 16-bit data */ \
- true, /* Delay on I2S data. */ \
- false, /* No DMA split. */ \
- usartI2sJustifyLeft, /* Data is left-justified within the frame */ \
- false /* Stereo mode. */ \
- }
+#define USART_INITI2S_DEFAULT \
+{ \
+ { \
+ usartEnableTx, /* Enable TX when init completed. */ \
+ 0, /* Use current configured reference clock for configuring baudrate. */ \
+ 1000000, /* Baudrate 1M bits/s. */ \
+ usartDatabits16, /* 16 databits. */ \
+ true, /* Operate as I2S master. */ \
+ true, /* Most significant bit first. */ \
+ usartClockMode0, /* Clock idle low, sample on rising edge. */ \
+ false, /* Don't enable USARTRx via PRS. */ \
+ usartPrsRxCh0, /* PRS channel selection (dummy). */ \
+ false /* Disable AUTOTX mode. */ \
+ }, \
+ usartI2sFormatW16D16, /* 16-bit word, 16-bit data */ \
+ true, /* Delay on I2S data. */ \
+ false, /* No DMA split. */ \
+ usartI2sJustifyLeft, /* Data is left-justified within the frame */ \
+ false /* Stereo mode. */ \
+}
#endif
/*******************************************************************************
@@ -523,11 +581,11 @@
void USART_InitAsync(USART_TypeDef *usart, const USART_InitAsync_TypeDef *init);
void USART_InitSync(USART_TypeDef *usart, const USART_InitSync_TypeDef *init);
-#if defined(USART0) || ( (USART_COUNT == 1) && defined( USART1 ) )
+#if defined(USART0) || ((USART_COUNT == 1) && defined(USART1))
void USART_InitIrDA(const USART_InitIrDA_TypeDef *init);
#endif
-#if defined( _USART_I2SCTRL_MASK )
+#if defined(_USART_I2SCTRL_MASK)
void USART_InitI2s(USART_TypeDef *usart, USART_InitI2s_TypeDef *init);
#endif
void USART_InitPrsTrigger(USART_TypeDef *usart, const USART_PrsTriggerInit_TypeDef *init);
@@ -563,7 +621,7 @@
******************************************************************************/
__STATIC_INLINE void USART_IntDisable(USART_TypeDef *usart, uint32_t flags)
{
- usart->IEN &= ~(flags);
+ usart->IEN &= ~flags;
}
@@ -630,14 +688,14 @@
******************************************************************************/
__STATIC_INLINE uint32_t USART_IntGetEnabled(USART_TypeDef *usart)
{
- uint32_t tmp;
+ uint32_t ien;
/* Store USARTx->IEN in temporary variable in order to define explicit order
* of volatile accesses. */
- tmp = usart->IEN;
+ ien = usart->IEN;
/* Bitwise AND of pending and enabled interrupts */
- return usart->IF & tmp;
+ return usart->IF & ien;
}
@@ -669,7 +727,7 @@
* STATUS register value.
*
******************************************************************************/
-static __INLINE uint32_t USART_StatusGet(USART_TypeDef *usart)
+__STATIC_INLINE uint32_t USART_StatusGet(USART_TypeDef *usart)
{
return usart->STATUS;
}
@@ -709,9 +767,9 @@
* @return
* Data received.
******************************************************************************/
-static __INLINE uint8_t USART_RxDataGet(USART_TypeDef *usart)
+__STATIC_INLINE uint8_t USART_RxDataGet(USART_TypeDef *usart)
{
- return (uint8_t) (usart->RXDATA);
+ return (uint8_t)usart->RXDATA;
}
@@ -747,9 +805,9 @@
* @return
* Data received.
******************************************************************************/
-static __INLINE uint16_t USART_RxDoubleGet(USART_TypeDef *usart)
+__STATIC_INLINE uint16_t USART_RxDoubleGet(USART_TypeDef *usart)
{
- return (uint16_t) (usart->RXDOUBLE);
+ return (uint16_t)usart->RXDOUBLE;
}
@@ -783,7 +841,7 @@
* @return
* Data received.
******************************************************************************/
-static __INLINE uint32_t USART_RxDoubleXGet(USART_TypeDef *usart)
+__STATIC_INLINE uint32_t USART_RxDoubleXGet(USART_TypeDef *usart)
{
return usart->RXDOUBLEX;
}
@@ -818,9 +876,9 @@
* @return
* Data received.
******************************************************************************/
-static __INLINE uint16_t USART_RxDataXGet(USART_TypeDef *usart)
+__STATIC_INLINE uint16_t USART_RxDataXGet(USART_TypeDef *usart)
{
- return (uint16_t) (usart->RXDATAX);
+ return (uint16_t)usart->RXDATAX;
}
uint8_t USART_SpiTransfer(USART_TypeDef *usart, uint8_t data);
@@ -838,4 +896,4 @@
#endif
#endif /* defined(USART_COUNT) && (USART_COUNT > 0) */
-#endif /* __SILICON_LABS_EM_USART_H_ */
+#endif /* __SILICON_LABS_EM_USART_H__ */