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targets/hal/TARGET_Silicon_Labs/TARGET_EFM32/emlib/inc/em_ebi.h@144:ef7eb2e8f9f7, 2016-09-02 (annotated)

Committer:
<>
Date:
Fri Sep 02 15:07:44 2016 +0100
Revision:
144:ef7eb2e8f9f7
Parent:
50:a417edff4437 
This updates the lib to the mbed lib v125

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 2 * @file em_ebi.h
<> 144:ef7eb2e8f9f7 3 * @brief External Bus Iterface (EBI) peripheral API
<> 144:ef7eb2e8f9f7 4 * @version 4.2.1
<> 144:ef7eb2e8f9f7 5 *******************************************************************************
<> 144:ef7eb2e8f9f7 6 * @section License
<> 144:ef7eb2e8f9f7 7 * <b>(C) Copyright 2015 Silicon Labs, http://www.silabs.com</b>
<> 144:ef7eb2e8f9f7 8 *******************************************************************************
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Permission is granted to anyone to use this software for any purpose,
<> 144:ef7eb2e8f9f7 11 * including commercial applications, and to alter it and redistribute it
<> 144:ef7eb2e8f9f7 12 * freely, subject to the following restrictions:
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * 1. The origin of this software must not be misrepresented; you must not
<> 144:ef7eb2e8f9f7 15 * claim that you wrote the original software.
<> 144:ef7eb2e8f9f7 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 144:ef7eb2e8f9f7 17 * misrepresented as being the original software.
<> 144:ef7eb2e8f9f7 18 * 3. This notice may not be removed or altered from any source distribution.
<> 144:ef7eb2e8f9f7 19 *
<> 144:ef7eb2e8f9f7 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Labs has no
<> 144:ef7eb2e8f9f7 21 * obligation to support this Software. Silicon Labs is providing the
<> 144:ef7eb2e8f9f7 22 * Software "AS IS", with no express or implied warranties of any kind,
<> 144:ef7eb2e8f9f7 23 * including, but not limited to, any implied warranties of merchantability
<> 144:ef7eb2e8f9f7 24 * or fitness for any particular purpose or warranties against infringement
<> 144:ef7eb2e8f9f7 25 * of any proprietary rights of a third party.
<> 144:ef7eb2e8f9f7 26 *
<> 144:ef7eb2e8f9f7 27 * Silicon Labs will not be liable for any consequential, incidental, or
<> 144:ef7eb2e8f9f7 28 * special damages, or any other relief, or for any claim by any third party,
<> 144:ef7eb2e8f9f7 29 * arising from your use of this Software.
<> 144:ef7eb2e8f9f7 30 *
<> 144:ef7eb2e8f9f7 31 ******************************************************************************/
<> 144:ef7eb2e8f9f7 32
<> 144:ef7eb2e8f9f7 33 #ifndef __SILICON_LABS_EM_EBI_H__
<> 144:ef7eb2e8f9f7 34 #define __SILICON_LABS_EM_EBI_H__
<> 144:ef7eb2e8f9f7 35
<> 144:ef7eb2e8f9f7 36 #include "em_device.h"
<> 144:ef7eb2e8f9f7 37 #if defined(EBI_COUNT) && (EBI_COUNT > 0)
<> 144:ef7eb2e8f9f7 38
<> 144:ef7eb2e8f9f7 39 #include <stdint.h>
<> 144:ef7eb2e8f9f7 40 #include <stdbool.h>
<> 144:ef7eb2e8f9f7 41 #include "em_assert.h"
<> 144:ef7eb2e8f9f7 42
<> 144:ef7eb2e8f9f7 43 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 44 extern "C" {
<> 144:ef7eb2e8f9f7 45 #endif
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 48 * @addtogroup EM_Library
<> 144:ef7eb2e8f9f7 49 * @{
<> 144:ef7eb2e8f9f7 50 ******************************************************************************/
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 53 * @addtogroup EBI
<> 144:ef7eb2e8f9f7 54 * @{
<> 144:ef7eb2e8f9f7 55 ******************************************************************************/
<> 144:ef7eb2e8f9f7 56
<> 144:ef7eb2e8f9f7 57 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 58 * @verbatim
<> 144:ef7eb2e8f9f7 59 *
<> 144:ef7eb2e8f9f7 60 * --------- ---------
<> 144:ef7eb2e8f9f7 61 * | | /| |\ | Ext. |
<> 144:ef7eb2e8f9f7 62 * | EBI | / --------- \ | Async |
<> 144:ef7eb2e8f9f7 63 * | | \ --------- / | Device|
<> 144:ef7eb2e8f9f7 64 * | | \| |/ | |
<> 144:ef7eb2e8f9f7 65 * --------- ---------
<> 144:ef7eb2e8f9f7 66 * Parallel interface
<> 144:ef7eb2e8f9f7 67 *
<> 144:ef7eb2e8f9f7 68 * @endverbatim
<> 144:ef7eb2e8f9f7 69 ******************************************************************************/
<> 144:ef7eb2e8f9f7 70
<> 144:ef7eb2e8f9f7 71 /*******************************************************************************
<> 144:ef7eb2e8f9f7 72 ******************************* DEFINES ***********************************
<> 144:ef7eb2e8f9f7 73 ******************************************************************************/
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 #define EBI_BANK0 (uint32_t)(1 << 1) /**< EBI address bank 0 */
<> 144:ef7eb2e8f9f7 76 #define EBI_BANK1 (uint32_t)(1 << 2) /**< EBI address bank 1 */
<> 144:ef7eb2e8f9f7 77 #define EBI_BANK2 (uint32_t)(1 << 3) /**< EBI address bank 2 */
<> 144:ef7eb2e8f9f7 78 #define EBI_BANK3 (uint32_t)(1 << 4) /**< EBI address bank 3 */
<> 144:ef7eb2e8f9f7 79
<> 144:ef7eb2e8f9f7 80 #define EBI_CS0 (uint32_t)(1 << 1) /**< EBI chip select line 0 */
<> 144:ef7eb2e8f9f7 81 #define EBI_CS1 (uint32_t)(1 << 2) /**< EBI chip select line 1 */
<> 144:ef7eb2e8f9f7 82 #define EBI_CS2 (uint32_t)(1 << 3) /**< EBI chip select line 2 */
<> 144:ef7eb2e8f9f7 83 #define EBI_CS3 (uint32_t)(1 << 4) /**< EBI chip select line 3 */
<> 144:ef7eb2e8f9f7 84
<> 144:ef7eb2e8f9f7 85 /*******************************************************************************
<> 144:ef7eb2e8f9f7 86 ******************************** ENUMS ************************************
<> 144:ef7eb2e8f9f7 87 ******************************************************************************/
<> 144:ef7eb2e8f9f7 88
<> 144:ef7eb2e8f9f7 89 /** EBI Mode of operation */
<> 144:ef7eb2e8f9f7 90 typedef enum
<> 144:ef7eb2e8f9f7 91 {
<> 144:ef7eb2e8f9f7 92 /** 8 data bits, 8 address bits */
<> 144:ef7eb2e8f9f7 93 ebiModeD8A8 = EBI_CTRL_MODE_D8A8,
<> 144:ef7eb2e8f9f7 94 /** 16 data bits, 16 address bits, using address latch enable */
<> 144:ef7eb2e8f9f7 95 ebiModeD16A16ALE = EBI_CTRL_MODE_D16A16ALE,
<> 144:ef7eb2e8f9f7 96 /** 8 data bits, 24 address bits, using address latch enable */
<> 144:ef7eb2e8f9f7 97 ebiModeD8A24ALE = EBI_CTRL_MODE_D8A24ALE,
<> 144:ef7eb2e8f9f7 98 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
<> 144:ef7eb2e8f9f7 99 /** Mode D16 */
<> 144:ef7eb2e8f9f7 100 ebiModeD16 = EBI_CTRL_MODE_D16,
<> 144:ef7eb2e8f9f7 101 #endif
<> 144:ef7eb2e8f9f7 102 } EBI_Mode_TypeDef;
<> 144:ef7eb2e8f9f7 103
<> 144:ef7eb2e8f9f7 104 /** EBI Polarity configuration */
<> 144:ef7eb2e8f9f7 105 typedef enum
<> 144:ef7eb2e8f9f7 106 {
<> 144:ef7eb2e8f9f7 107 /** Active Low */
<> 144:ef7eb2e8f9f7 108 ebiActiveLow = 0,
<> 144:ef7eb2e8f9f7 109 /** Active High */
<> 144:ef7eb2e8f9f7 110 ebiActiveHigh = 1
<> 144:ef7eb2e8f9f7 111 } EBI_Polarity_TypeDef;
<> 144:ef7eb2e8f9f7 112
<> 144:ef7eb2e8f9f7 113 /** EBI Pin Line types */
<> 144:ef7eb2e8f9f7 114 typedef enum
<> 144:ef7eb2e8f9f7 115 {
<> 144:ef7eb2e8f9f7 116 /** Address Ready line */
<> 144:ef7eb2e8f9f7 117 ebiLineARDY,
<> 144:ef7eb2e8f9f7 118 /** Address Latch Enable line */
<> 144:ef7eb2e8f9f7 119 ebiLineALE,
<> 144:ef7eb2e8f9f7 120 /** Write Enable line */
<> 144:ef7eb2e8f9f7 121 ebiLineWE,
<> 144:ef7eb2e8f9f7 122 /** Read Enable line */
<> 144:ef7eb2e8f9f7 123 ebiLineRE,
<> 144:ef7eb2e8f9f7 124 /** Chip Select line */
<> 144:ef7eb2e8f9f7 125 ebiLineCS,
<> 144:ef7eb2e8f9f7 126 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
<> 144:ef7eb2e8f9f7 127 /** BL line */
<> 144:ef7eb2e8f9f7 128 ebiLineBL,
<> 144:ef7eb2e8f9f7 129 #endif
<> 144:ef7eb2e8f9f7 130 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
<> 144:ef7eb2e8f9f7 131 /** TFT VSYNC line */
<> 144:ef7eb2e8f9f7 132 ebiLineTFTVSync,
<> 144:ef7eb2e8f9f7 133 /** TFT HSYNC line */
<> 144:ef7eb2e8f9f7 134 ebiLineTFTHSync,
<> 144:ef7eb2e8f9f7 135 /** TFT Data enable line */
<> 144:ef7eb2e8f9f7 136 ebiLineTFTDataEn,
<> 144:ef7eb2e8f9f7 137 /** TFT DCLK line */
<> 144:ef7eb2e8f9f7 138 ebiLineTFTDClk,
<> 144:ef7eb2e8f9f7 139 /** TFT Chip select line */
<> 144:ef7eb2e8f9f7 140 ebiLineTFTCS,
<> 144:ef7eb2e8f9f7 141 #endif
<> 144:ef7eb2e8f9f7 142 } EBI_Line_TypeDef;
<> 144:ef7eb2e8f9f7 143
<> 144:ef7eb2e8f9f7 144 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
<> 144:ef7eb2e8f9f7 145 /** Address Pin Enable, lower limit - lower range of pins to enable */
<> 144:ef7eb2e8f9f7 146 typedef enum
<> 144:ef7eb2e8f9f7 147 {
<> 144:ef7eb2e8f9f7 148 /** Adress lines EBI_A[0] and upwards are enabled by APEN */
<> 144:ef7eb2e8f9f7 149 ebiALowA0 = EBI_ROUTE_ALB_A0,
<> 144:ef7eb2e8f9f7 150 /** Adress lines EBI_A[8] and upwards are enabled by APEN */
<> 144:ef7eb2e8f9f7 151 ebiALowA8 = EBI_ROUTE_ALB_A8,
<> 144:ef7eb2e8f9f7 152 /** Adress lines EBI_A[16] and upwards are enabled by APEN */
<> 144:ef7eb2e8f9f7 153 ebiALowA16 = EBI_ROUTE_ALB_A16,
<> 144:ef7eb2e8f9f7 154 /** Adress lines EBI_A[24] and upwards are enabled by APEN */
<> 144:ef7eb2e8f9f7 155 ebiALowA24 = EBI_ROUTE_ALB_A24,
<> 144:ef7eb2e8f9f7 156 } EBI_ALow_TypeDef;
<> 144:ef7eb2e8f9f7 157
<> 144:ef7eb2e8f9f7 158 /** Adress Pin Enable, high limit - higher limit of pins to enable */
<> 144:ef7eb2e8f9f7 159 typedef enum
<> 144:ef7eb2e8f9f7 160 {
<> 144:ef7eb2e8f9f7 161 /** All EBI_A pins are disabled */
<> 144:ef7eb2e8f9f7 162 ebiAHighA0 = EBI_ROUTE_APEN_A0,
<> 144:ef7eb2e8f9f7 163 /** All EBI_A[4:ALow] are enabled */
<> 144:ef7eb2e8f9f7 164 ebiAHighA5 = EBI_ROUTE_APEN_A5,
<> 144:ef7eb2e8f9f7 165 /** All EBI_A[5:ALow] are enabled */
<> 144:ef7eb2e8f9f7 166 ebiAHighA6 = EBI_ROUTE_APEN_A6,
<> 144:ef7eb2e8f9f7 167 /** All EBI_A[6:ALow] are enabled */
<> 144:ef7eb2e8f9f7 168 ebiAHighA7 = EBI_ROUTE_APEN_A7,
<> 144:ef7eb2e8f9f7 169 /** All EBI_A[7:ALow] are enabled */
<> 144:ef7eb2e8f9f7 170 ebiAHighA8 = EBI_ROUTE_APEN_A8,
<> 144:ef7eb2e8f9f7 171 /** All EBI_A[8:ALow] are enabled */
<> 144:ef7eb2e8f9f7 172 ebiAHighA9 = EBI_ROUTE_APEN_A9,
<> 144:ef7eb2e8f9f7 173 /** All EBI_A[9:ALow] are enabled */
<> 144:ef7eb2e8f9f7 174 ebiAHighA10 = EBI_ROUTE_APEN_A10,
<> 144:ef7eb2e8f9f7 175 /** All EBI_A[10:ALow] are enabled */
<> 144:ef7eb2e8f9f7 176 ebiAHighA11 = EBI_ROUTE_APEN_A11,
<> 144:ef7eb2e8f9f7 177 /** All EBI_A[11:ALow] are enabled */
<> 144:ef7eb2e8f9f7 178 ebiAHighA12 = EBI_ROUTE_APEN_A12,
<> 144:ef7eb2e8f9f7 179 /** All EBI_A[12:ALow] are enabled */
<> 144:ef7eb2e8f9f7 180 ebiAHighA13 = EBI_ROUTE_APEN_A13,
<> 144:ef7eb2e8f9f7 181 /** All EBI_A[13:ALow] are enabled */
<> 144:ef7eb2e8f9f7 182 ebiAHighA14 = EBI_ROUTE_APEN_A14,
<> 144:ef7eb2e8f9f7 183 /** All EBI_A[14:ALow] are enabled */
<> 144:ef7eb2e8f9f7 184 ebiAHighA15 = EBI_ROUTE_APEN_A15,
<> 144:ef7eb2e8f9f7 185 /** All EBI_A[15:ALow] are enabled */
<> 144:ef7eb2e8f9f7 186 ebiAHighA16 = EBI_ROUTE_APEN_A16,
<> 144:ef7eb2e8f9f7 187 /** All EBI_A[16:ALow] are enabled */
<> 144:ef7eb2e8f9f7 188 ebiAHighA17 = EBI_ROUTE_APEN_A17,
<> 144:ef7eb2e8f9f7 189 /** All EBI_A[17:ALow] are enabled */
<> 144:ef7eb2e8f9f7 190 ebiAHighA18 = EBI_ROUTE_APEN_A18,
<> 144:ef7eb2e8f9f7 191 /** All EBI_A[18:ALow] are enabled */
<> 144:ef7eb2e8f9f7 192 ebiAHighA19 = EBI_ROUTE_APEN_A19,
<> 144:ef7eb2e8f9f7 193 /** All EBI_A[19:ALow] are enabled */
<> 144:ef7eb2e8f9f7 194 ebiAHighA20 = EBI_ROUTE_APEN_A20,
<> 144:ef7eb2e8f9f7 195 /** All EBI_A[20:ALow] are enabled */
<> 144:ef7eb2e8f9f7 196 ebiAHighA21 = EBI_ROUTE_APEN_A21,
<> 144:ef7eb2e8f9f7 197 /** All EBI_A[21:ALow] are enabled */
<> 144:ef7eb2e8f9f7 198 ebiAHighA22 = EBI_ROUTE_APEN_A22,
<> 144:ef7eb2e8f9f7 199 /** All EBI_A[22:ALow] are enabled */
<> 144:ef7eb2e8f9f7 200 ebiAHighA23 = EBI_ROUTE_APEN_A23,
<> 144:ef7eb2e8f9f7 201 /** All EBI_A[23:ALow] are enabled */
<> 144:ef7eb2e8f9f7 202 ebiAHighA24 = EBI_ROUTE_APEN_A24,
<> 144:ef7eb2e8f9f7 203 /** All EBI_A[24:ALow] are enabled */
<> 144:ef7eb2e8f9f7 204 ebiAHighA25 = EBI_ROUTE_APEN_A25,
<> 144:ef7eb2e8f9f7 205 /** All EBI_A[25:ALow] are enabled */
<> 144:ef7eb2e8f9f7 206 ebiAHighA26 = EBI_ROUTE_APEN_A26,
<> 144:ef7eb2e8f9f7 207 /** All EBI_A[26:ALow] are enabled */
<> 144:ef7eb2e8f9f7 208 ebiAHighA27 = EBI_ROUTE_APEN_A27,
<> 144:ef7eb2e8f9f7 209 /** All EBI_A[27:ALow] are enabled */
<> 144:ef7eb2e8f9f7 210 ebiAHighA28 = EBI_ROUTE_APEN_A28,
<> 144:ef7eb2e8f9f7 211 } EBI_AHigh_TypeDef;
<> 144:ef7eb2e8f9f7 212
<> 144:ef7eb2e8f9f7 213 /** EBI I/O Alternate Pin Location */
<> 144:ef7eb2e8f9f7 214 typedef enum {
<> 144:ef7eb2e8f9f7 215 /** EBI PIN I/O Location 0 */
<> 144:ef7eb2e8f9f7 216 ebiLocation0 = EBI_ROUTE_LOCATION_LOC0,
<> 144:ef7eb2e8f9f7 217 /** EBI PIN I/O Location 1 */
<> 144:ef7eb2e8f9f7 218 ebiLocation1 = EBI_ROUTE_LOCATION_LOC1,
<> 144:ef7eb2e8f9f7 219 /** EBI PIN I/O Location 2 */
<> 144:ef7eb2e8f9f7 220 ebiLocation2 = EBI_ROUTE_LOCATION_LOC2
<> 144:ef7eb2e8f9f7 221 } EBI_Location_TypeDef;
<> 144:ef7eb2e8f9f7 222 #endif
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 /* TFT support */
<> 144:ef7eb2e8f9f7 225 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
<> 144:ef7eb2e8f9f7 226 /** EBI TFT Graphics Bank Select */
<> 144:ef7eb2e8f9f7 227 typedef enum
<> 144:ef7eb2e8f9f7 228 {
<> 144:ef7eb2e8f9f7 229 /** Memory BANK0 contains frame buffer */
<> 144:ef7eb2e8f9f7 230 ebiTFTBank0 = EBI_TFTCTRL_BANKSEL_BANK0,
<> 144:ef7eb2e8f9f7 231 /** Memory BANK1 contains frame buffer */
<> 144:ef7eb2e8f9f7 232 ebiTFTBank1 = EBI_TFTCTRL_BANKSEL_BANK1,
<> 144:ef7eb2e8f9f7 233 /** Memory BANK2 contains frame buffer */
<> 144:ef7eb2e8f9f7 234 ebiTFTBank2 = EBI_TFTCTRL_BANKSEL_BANK2,
<> 144:ef7eb2e8f9f7 235 /** Memory BANK3 contains frame buffer */
<> 144:ef7eb2e8f9f7 236 ebiTFTBank3 = EBI_TFTCTRL_BANKSEL_BANK3
<> 144:ef7eb2e8f9f7 237 } EBI_TFTBank_TypeDef;
<> 144:ef7eb2e8f9f7 238
<> 144:ef7eb2e8f9f7 239 /** Masking and Alpha blending source color*/
<> 144:ef7eb2e8f9f7 240 typedef enum
<> 144:ef7eb2e8f9f7 241 {
<> 144:ef7eb2e8f9f7 242 /** Use memory as source color for masking/alpha blending */
<> 144:ef7eb2e8f9f7 243 ebiTFTColorSrcMem = EBI_TFTCTRL_COLOR1SRC_MEM,
<> 144:ef7eb2e8f9f7 244 /** Use PIXEL1 register as source color for masking/alpha blending */
<> 144:ef7eb2e8f9f7 245 ebiTFTColorSrcPixel1 = EBI_TFTCTRL_COLOR1SRC_PIXEL1,
<> 144:ef7eb2e8f9f7 246 } EBI_TFTColorSrc_TypeDef;
<> 144:ef7eb2e8f9f7 247
<> 144:ef7eb2e8f9f7 248 /** Bus Data Interleave Mode */
<> 144:ef7eb2e8f9f7 249 typedef enum
<> 144:ef7eb2e8f9f7 250 {
<> 144:ef7eb2e8f9f7 251 /** Unlimited interleaved accesses per EBI_DCLK period. Can cause jitter */
<> 144:ef7eb2e8f9f7 252 ebiTFTInterleaveUnlimited = EBI_TFTCTRL_INTERLEAVE_UNLIMITED,
<> 144:ef7eb2e8f9f7 253 /** Allow 1 interleaved access per EBI_DCLK period */
<> 144:ef7eb2e8f9f7 254 ebiTFTInterleaveOnePerDClk = EBI_TFTCTRL_INTERLEAVE_ONEPERDCLK,
<> 144:ef7eb2e8f9f7 255 /** Only allow accesses during porch periods */
<> 144:ef7eb2e8f9f7 256 ebiTFTInterleavePorch = EBI_TFTCTRL_INTERLEAVE_PORCH,
<> 144:ef7eb2e8f9f7 257 } EBI_TFTInterleave_TypeDef;
<> 144:ef7eb2e8f9f7 258
<> 144:ef7eb2e8f9f7 259 /** Control frame base pointer copy */
<> 144:ef7eb2e8f9f7 260 typedef enum
<> 144:ef7eb2e8f9f7 261 {
<> 144:ef7eb2e8f9f7 262 /** Trigger update of frame buffer pointer on vertical sync */
<> 144:ef7eb2e8f9f7 263 ebiTFTFrameBufTriggerVSync = EBI_TFTCTRL_FBCTRIG_VSYNC,
<> 144:ef7eb2e8f9f7 264 /** Trigger update of frame buffer pointer on horizontal sync */
<> 144:ef7eb2e8f9f7 265 ebiTFTFrameBufTriggerHSync = EBI_TFTCTRL_FBCTRIG_HSYNC,
<> 144:ef7eb2e8f9f7 266 } EBI_TFTFrameBufTrigger_TypeDef;
<> 144:ef7eb2e8f9f7 267
<> 144:ef7eb2e8f9f7 268 /** Control of mask and alpha blending mode */
<> 144:ef7eb2e8f9f7 269 typedef enum
<> 144:ef7eb2e8f9f7 270 {
<> 144:ef7eb2e8f9f7 271 /** Masking and blending are disabled */
<> 144:ef7eb2e8f9f7 272 ebiTFTMBDisabled = EBI_TFTCTRL_MASKBLEND_DISABLED,
<> 144:ef7eb2e8f9f7 273 /** Internal masking */
<> 144:ef7eb2e8f9f7 274 ebiTFTMBIMask = EBI_TFTCTRL_MASKBLEND_IMASK,
<> 144:ef7eb2e8f9f7 275 /** Internal alpha blending */
<> 144:ef7eb2e8f9f7 276 ebiTFTMBIAlpha = EBI_TFTCTRL_MASKBLEND_IALPHA,
<> 144:ef7eb2e8f9f7 277 /** Internal masking and alpha blending are enabled */
<> 144:ef7eb2e8f9f7 278 ebiTFTMBIMaskAlpha = EBI_TFTCTRL_MASKBLEND_IMASKIALPHA,
<> 144:ef7eb2e8f9f7 279 /** External masking */
<> 144:ef7eb2e8f9f7 280 ebiTFTMBEMask = EBI_TFTCTRL_MASKBLEND_EMASK,
<> 144:ef7eb2e8f9f7 281 /** External alpha blending */
<> 144:ef7eb2e8f9f7 282 ebiTFTMBEAlpha = EBI_TFTCTRL_MASKBLEND_EALPHA,
<> 144:ef7eb2e8f9f7 283 /** External masking and alpha blending */
<> 144:ef7eb2e8f9f7 284 ebiTFTMBEMaskAlpha = EBI_TFTCTRL_MASKBLEND_EMASKEALPHA,
<> 144:ef7eb2e8f9f7 285 } EBI_TFTMaskBlend_TypeDef;
<> 144:ef7eb2e8f9f7 286
<> 144:ef7eb2e8f9f7 287 /** TFT Direct Drive mode */
<> 144:ef7eb2e8f9f7 288 typedef enum
<> 144:ef7eb2e8f9f7 289 {
<> 144:ef7eb2e8f9f7 290 /** Disabled */
<> 144:ef7eb2e8f9f7 291 ebiTFTDDModeDisabled = EBI_TFTCTRL_DD_DISABLED,
<> 144:ef7eb2e8f9f7 292 /** Direct Drive from internal memory */
<> 144:ef7eb2e8f9f7 293 ebiTFTDDModeInternal = EBI_TFTCTRL_DD_INTERNAL,
<> 144:ef7eb2e8f9f7 294 /** Direct Drive from external memory */
<> 144:ef7eb2e8f9f7 295 ebiTFTDDModeExternal = EBI_TFTCTRL_DD_EXTERNAL,
<> 144:ef7eb2e8f9f7 296 } EBI_TFTDDMode_TypeDef;
<> 144:ef7eb2e8f9f7 297
<> 144:ef7eb2e8f9f7 298 /** TFT Data Increment Width */
<> 144:ef7eb2e8f9f7 299 typedef enum
<> 144:ef7eb2e8f9f7 300 {
<> 144:ef7eb2e8f9f7 301 /** Pixel increments are 1 byte at a time */
<> 144:ef7eb2e8f9f7 302 ebiTFTWidthByte = EBI_TFTCTRL_WIDTH_BYTE,
<> 144:ef7eb2e8f9f7 303 /** Pixel increments are 2 bytes (half word) */
<> 144:ef7eb2e8f9f7 304 ebiTFTWidthHalfWord = EBI_TFTCTRL_WIDTH_HALFWORD,
<> 144:ef7eb2e8f9f7 305 } EBI_TFTWidth_TypeDef;
<> 144:ef7eb2e8f9f7 306
<> 144:ef7eb2e8f9f7 307 #endif
<> 144:ef7eb2e8f9f7 308
<> 144:ef7eb2e8f9f7 309 /*******************************************************************************
<> 144:ef7eb2e8f9f7 310 ******************************* STRUCTS ***********************************
<> 144:ef7eb2e8f9f7 311 ******************************************************************************/
<> 144:ef7eb2e8f9f7 312
<> 144:ef7eb2e8f9f7 313 /** EBI Initialization structure */
<> 144:ef7eb2e8f9f7 314 typedef struct
<> 144:ef7eb2e8f9f7 315 {
<> 144:ef7eb2e8f9f7 316 /** EBI operation mode, data and address limits */
<> 144:ef7eb2e8f9f7 317 EBI_Mode_TypeDef mode;
<> 144:ef7eb2e8f9f7 318 /** Address Ready pin polarity, active high or low */
<> 144:ef7eb2e8f9f7 319 EBI_Polarity_TypeDef ardyPolarity;
<> 144:ef7eb2e8f9f7 320 /** Address Latch Enable pin polarity, active high or low */
<> 144:ef7eb2e8f9f7 321 EBI_Polarity_TypeDef alePolarity;
<> 144:ef7eb2e8f9f7 322 /** Write Enable pin polarity, active high or low */
<> 144:ef7eb2e8f9f7 323 EBI_Polarity_TypeDef wePolarity;
<> 144:ef7eb2e8f9f7 324 /** Read Enable pin polarity, active high or low */
<> 144:ef7eb2e8f9f7 325 EBI_Polarity_TypeDef rePolarity;
<> 144:ef7eb2e8f9f7 326 /** Chip Select pin polarity, active high or low */
<> 144:ef7eb2e8f9f7 327 EBI_Polarity_TypeDef csPolarity;
<> 144:ef7eb2e8f9f7 328 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
<> 144:ef7eb2e8f9f7 329 /** Byte Lane pin polaritym, active high or low */
<> 144:ef7eb2e8f9f7 330 EBI_Polarity_TypeDef blPolarity;
<> 144:ef7eb2e8f9f7 331 /** Flag to enable or disable Byte Lane support */
<> 144:ef7eb2e8f9f7 332 bool blEnable;
<> 144:ef7eb2e8f9f7 333 /** Flag to enable or disable idle state insertion between transfers */
<> 144:ef7eb2e8f9f7 334 bool noIdle;
<> 144:ef7eb2e8f9f7 335 #endif
<> 144:ef7eb2e8f9f7 336 /** Flag to enable or disable Address Ready support */
<> 144:ef7eb2e8f9f7 337 bool ardyEnable;
<> 144:ef7eb2e8f9f7 338 /** Set to turn off 32 cycle timeout ability */
<> 144:ef7eb2e8f9f7 339 bool ardyDisableTimeout;
<> 144:ef7eb2e8f9f7 340 /** Mask of flags which selects address banks to configure EBI_BANK<0-3> */
<> 144:ef7eb2e8f9f7 341 uint32_t banks;
<> 144:ef7eb2e8f9f7 342 /** Mask of flags which selects chip select lines to configure EBI_CS<0-3> */
<> 144:ef7eb2e8f9f7 343 uint32_t csLines;
<> 144:ef7eb2e8f9f7 344 /** Number of cycles address is held after Adress Latch Enable is asserted */
<> 144:ef7eb2e8f9f7 345 int addrSetupCycles;
<> 144:ef7eb2e8f9f7 346 /** Number of cycles address is driven onto the ADDRDAT bus before ALE is asserted */
<> 144:ef7eb2e8f9f7 347 int addrHoldCycles;
<> 144:ef7eb2e8f9f7 348 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
<> 144:ef7eb2e8f9f7 349 /** Enable or disables half cycle duration of the ALE strobe in the last address setup cycle */
<> 144:ef7eb2e8f9f7 350 bool addrHalfALE;
<> 144:ef7eb2e8f9f7 351 #endif
<> 144:ef7eb2e8f9f7 352 /** Number of cycles for address setup before REn is asserted */
<> 144:ef7eb2e8f9f7 353 int readSetupCycles;
<> 144:ef7eb2e8f9f7 354 /** Number of cycles REn is held active */
<> 144:ef7eb2e8f9f7 355 int readStrobeCycles;
<> 144:ef7eb2e8f9f7 356 /** Number of cycles CSn is held active after REn is deasserted */
<> 144:ef7eb2e8f9f7 357 int readHoldCycles;
<> 144:ef7eb2e8f9f7 358 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
<> 144:ef7eb2e8f9f7 359 /** Enable or disable page mode reads */
<> 144:ef7eb2e8f9f7 360 bool readPageMode;
<> 144:ef7eb2e8f9f7 361 /** Enables or disable prefetching from sequential addresses */
<> 144:ef7eb2e8f9f7 362 bool readPrefetch;
<> 144:ef7eb2e8f9f7 363 /** Enabled or disables half cycle duration of the REn signal in the last strobe cycle */
<> 144:ef7eb2e8f9f7 364 bool readHalfRE;
<> 144:ef7eb2e8f9f7 365 #endif
<> 144:ef7eb2e8f9f7 366 /** Number of cycles for address setup before WEn is asserted */
<> 144:ef7eb2e8f9f7 367 int writeSetupCycles;
<> 144:ef7eb2e8f9f7 368 /** Number of cycles WEn is held active */
<> 144:ef7eb2e8f9f7 369 int writeStrobeCycles;
<> 144:ef7eb2e8f9f7 370 /** Number of cycles CSn is held active after WEn is deasserted */
<> 144:ef7eb2e8f9f7 371 int writeHoldCycles;
<> 144:ef7eb2e8f9f7 372 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
<> 144:ef7eb2e8f9f7 373 /** Enable or disable the write buffer */
<> 144:ef7eb2e8f9f7 374 bool writeBufferDisable;
<> 144:ef7eb2e8f9f7 375 /** Enables or disables half cycle duration of the WEn signal in the last strobe cycle */
<> 144:ef7eb2e8f9f7 376 bool writeHalfWE;
<> 144:ef7eb2e8f9f7 377 /** Lower address pin limit to enable */
<> 144:ef7eb2e8f9f7 378 EBI_ALow_TypeDef aLow;
<> 144:ef7eb2e8f9f7 379 /** High address pin limit to enable */
<> 144:ef7eb2e8f9f7 380 EBI_AHigh_TypeDef aHigh;
<> 144:ef7eb2e8f9f7 381 /** Pin Location */
<> 144:ef7eb2e8f9f7 382 EBI_Location_TypeDef location;
<> 144:ef7eb2e8f9f7 383 #endif
<> 144:ef7eb2e8f9f7 384 /** Flag, if EBI should be enabled after configuration */
<> 144:ef7eb2e8f9f7 385 bool enable;
<> 144:ef7eb2e8f9f7 386 } EBI_Init_TypeDef;
<> 144:ef7eb2e8f9f7 387
<> 144:ef7eb2e8f9f7 388 /** Default config for EBI init structures */
<> 144:ef7eb2e8f9f7 389 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
<> 144:ef7eb2e8f9f7 390 #define EBI_INIT_DEFAULT \
<> 144:ef7eb2e8f9f7 391 { \
<> 144:ef7eb2e8f9f7 392 ebiModeD8A8, /* 8 bit address, 8 bit data */ \
<> 144:ef7eb2e8f9f7 393 ebiActiveLow, /* ARDY polarity */ \
<> 144:ef7eb2e8f9f7 394 ebiActiveLow, /* ALE polarity */ \
<> 144:ef7eb2e8f9f7 395 ebiActiveLow, /* WE polarity */ \
<> 144:ef7eb2e8f9f7 396 ebiActiveLow, /* RE polarity */ \
<> 144:ef7eb2e8f9f7 397 ebiActiveLow, /* CS polarity */ \
<> 144:ef7eb2e8f9f7 398 ebiActiveLow, /* BL polarity */ \
<> 144:ef7eb2e8f9f7 399 false, /* enable BL */ \
<> 144:ef7eb2e8f9f7 400 false, /* enable NOIDLE */ \
<> 144:ef7eb2e8f9f7 401 false, /* enable ARDY */ \
<> 144:ef7eb2e8f9f7 402 false, /* don't disable ARDY timeout */ \
<> 144:ef7eb2e8f9f7 403 EBI_BANK0, /* enable bank 0 */ \
<> 144:ef7eb2e8f9f7 404 EBI_CS0, /* enable chip select 0 */ \
<> 144:ef7eb2e8f9f7 405 0, /* addr setup cycles */ \
<> 144:ef7eb2e8f9f7 406 1, /* addr hold cycles */ \
<> 144:ef7eb2e8f9f7 407 false, /* do not enable half cycle ALE strobe */ \
<> 144:ef7eb2e8f9f7 408 0, /* read setup cycles */ \
<> 144:ef7eb2e8f9f7 409 0, /* read strobe cycles */ \
<> 144:ef7eb2e8f9f7 410 0, /* read hold cycles */ \
<> 144:ef7eb2e8f9f7 411 false, /* disable page mode */ \
<> 144:ef7eb2e8f9f7 412 false, /* disable prefetch */ \
<> 144:ef7eb2e8f9f7 413 false, /* do not enable half cycle REn strobe */ \
<> 144:ef7eb2e8f9f7 414 0, /* write setup cycles */ \
<> 144:ef7eb2e8f9f7 415 0, /* write strobe cycles */ \
<> 144:ef7eb2e8f9f7 416 1, /* write hold cycles */ \
<> 144:ef7eb2e8f9f7 417 false, /* do not disable the write buffer */ \
<> 144:ef7eb2e8f9f7 418 false, /* do not enable halc cycle WEn strobe */ \
<> 144:ef7eb2e8f9f7 419 ebiALowA0, /* ALB - Low bound, address lines */ \
<> 144:ef7eb2e8f9f7 420 ebiAHighA0, /* APEN - High bound, address lines */ \
<> 144:ef7eb2e8f9f7 421 ebiLocation0, /* Use Location 0 */ \
<> 144:ef7eb2e8f9f7 422 true, /* enable EBI */ \
<> 144:ef7eb2e8f9f7 423 }
<> 144:ef7eb2e8f9f7 424 #else
<> 144:ef7eb2e8f9f7 425 #define EBI_INIT_DEFAULT \
<> 144:ef7eb2e8f9f7 426 { \
<> 144:ef7eb2e8f9f7 427 ebiModeD8A8, /* 8 bit address, 8 bit data */ \
<> 144:ef7eb2e8f9f7 428 ebiActiveLow, /* ARDY polarity */ \
<> 144:ef7eb2e8f9f7 429 ebiActiveLow, /* ALE polarity */ \
<> 144:ef7eb2e8f9f7 430 ebiActiveLow, /* WE polarity */ \
<> 144:ef7eb2e8f9f7 431 ebiActiveLow, /* RE polarity */ \
<> 144:ef7eb2e8f9f7 432 ebiActiveLow, /* CS polarity */ \
<> 144:ef7eb2e8f9f7 433 false, /* enable ARDY */ \
<> 144:ef7eb2e8f9f7 434 false, /* don't disable ARDY timeout */ \
<> 144:ef7eb2e8f9f7 435 EBI_BANK0, /* enable bank 0 */ \
<> 144:ef7eb2e8f9f7 436 EBI_CS0, /* enable chip select 0 */ \
<> 144:ef7eb2e8f9f7 437 0, /* addr setup cycles */ \
<> 144:ef7eb2e8f9f7 438 1, /* addr hold cycles */ \
<> 144:ef7eb2e8f9f7 439 0, /* read setup cycles */ \
<> 144:ef7eb2e8f9f7 440 0, /* read strobe cycles */ \
<> 144:ef7eb2e8f9f7 441 0, /* read hold cycles */ \
<> 144:ef7eb2e8f9f7 442 0, /* write setup cycles */ \
<> 144:ef7eb2e8f9f7 443 0, /* write strobe cycles */ \
<> 144:ef7eb2e8f9f7 444 1, /* write hold cycles */ \
<> 144:ef7eb2e8f9f7 445 true, /* enable EBI */ \
<> 144:ef7eb2e8f9f7 446 }
<> 144:ef7eb2e8f9f7 447 #endif
<> 144:ef7eb2e8f9f7 448
<> 144:ef7eb2e8f9f7 449 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
<> 144:ef7eb2e8f9f7 450
<> 144:ef7eb2e8f9f7 451 /** TFT Initialization structure */
<> 144:ef7eb2e8f9f7 452 typedef struct
<> 144:ef7eb2e8f9f7 453 {
<> 144:ef7eb2e8f9f7 454 /** External memory bank for driving display */
<> 144:ef7eb2e8f9f7 455 EBI_TFTBank_TypeDef bank;
<> 144:ef7eb2e8f9f7 456 /** Width */
<> 144:ef7eb2e8f9f7 457 EBI_TFTWidth_TypeDef width;
<> 144:ef7eb2e8f9f7 458 /** Color source for masking and alpha blending */
<> 144:ef7eb2e8f9f7 459 EBI_TFTColorSrc_TypeDef colSrc;
<> 144:ef7eb2e8f9f7 460 /** Bus Interleave mode */
<> 144:ef7eb2e8f9f7 461 EBI_TFTInterleave_TypeDef interleave;
<> 144:ef7eb2e8f9f7 462 /** Trigger for updating frame buffer pointer */
<> 144:ef7eb2e8f9f7 463 EBI_TFTFrameBufTrigger_TypeDef fbTrigger;
<> 144:ef7eb2e8f9f7 464 /** Drive DCLK from negative clock edge of internal clock */
<> 144:ef7eb2e8f9f7 465 bool shiftDClk;
<> 144:ef7eb2e8f9f7 466 /** Masking and alpha blending mode */
<> 144:ef7eb2e8f9f7 467 EBI_TFTMaskBlend_TypeDef maskBlend;
<> 144:ef7eb2e8f9f7 468 /** TFT Direct Drive mode */
<> 144:ef7eb2e8f9f7 469 EBI_TFTDDMode_TypeDef driveMode;
<> 144:ef7eb2e8f9f7 470 /** TFT Polarity for Chip Select (CS) Line */
<> 144:ef7eb2e8f9f7 471 EBI_Polarity_TypeDef csPolarity;
<> 144:ef7eb2e8f9f7 472 /** TFT Polarity for Data Clock (DCLK) Line */
<> 144:ef7eb2e8f9f7 473 EBI_Polarity_TypeDef dclkPolarity;
<> 144:ef7eb2e8f9f7 474 /** TFT Polarity for Data Enable (DATAEN) Line */
<> 144:ef7eb2e8f9f7 475 EBI_Polarity_TypeDef dataenPolarity;
<> 144:ef7eb2e8f9f7 476 /** TFT Polarity for Horizontal Sync (HSYNC) Line */
<> 144:ef7eb2e8f9f7 477 EBI_Polarity_TypeDef hsyncPolarity;
<> 144:ef7eb2e8f9f7 478 /** TFT Polarity for Vertical Sync (VSYNC) Line */
<> 144:ef7eb2e8f9f7 479 EBI_Polarity_TypeDef vsyncPolarity;
<> 144:ef7eb2e8f9f7 480 /** Horizontal size in pixels */
<> 144:ef7eb2e8f9f7 481 int hsize;
<> 144:ef7eb2e8f9f7 482 /** Horizontal Front Porch Size */
<> 144:ef7eb2e8f9f7 483 int hPorchFront;
<> 144:ef7eb2e8f9f7 484 /** Horizontal Back Porch Size */
<> 144:ef7eb2e8f9f7 485 int hPorchBack;
<> 144:ef7eb2e8f9f7 486 /** Horizontal Synchronization Pulse Width */
<> 144:ef7eb2e8f9f7 487 int hPulseWidth;
<> 144:ef7eb2e8f9f7 488 /** Vertical size in pixels */
<> 144:ef7eb2e8f9f7 489 int vsize;
<> 144:ef7eb2e8f9f7 490 /** Vertical Front Porch Size */
<> 144:ef7eb2e8f9f7 491 int vPorchFront;
<> 144:ef7eb2e8f9f7 492 /** Vertical Back Porch Size */
<> 144:ef7eb2e8f9f7 493 int vPorchBack;
<> 144:ef7eb2e8f9f7 494 /** Vertical Synchronization Pulse Width */
<> 144:ef7eb2e8f9f7 495 int vPulseWidth;
<> 144:ef7eb2e8f9f7 496 /** TFT Frame Buffer address, offset to EBI bank base address */
<> 144:ef7eb2e8f9f7 497 uint32_t addressOffset;
<> 144:ef7eb2e8f9f7 498 /** TFT DCLK period in internal cycles */
<> 144:ef7eb2e8f9f7 499 int dclkPeriod;
<> 144:ef7eb2e8f9f7 500 /** Starting position of External Direct Drive relative to DCLK inactive edge */
<> 144:ef7eb2e8f9f7 501 int startPosition;
<> 144:ef7eb2e8f9f7 502 /** Number of cycles RGB data is driven before active edge of DCLK */
<> 144:ef7eb2e8f9f7 503 int setupCycles;
<> 144:ef7eb2e8f9f7 504 /** Number of cycles RGB data is held after active edge of DCLK */
<> 144:ef7eb2e8f9f7 505 int holdCycles;
<> 144:ef7eb2e8f9f7 506 } EBI_TFTInit_TypeDef;
<> 144:ef7eb2e8f9f7 507
<> 144:ef7eb2e8f9f7 508 /** Default configuration for EBI TFT init structure */
<> 144:ef7eb2e8f9f7 509 #define EBI_TFTINIT_DEFAULT \
<> 144:ef7eb2e8f9f7 510 { \
<> 144:ef7eb2e8f9f7 511 ebiTFTBank0, /* Select EBI Bank 0 */ \
<> 144:ef7eb2e8f9f7 512 ebiTFTWidthHalfWord, /* Select 2-byte increments */ \
<> 144:ef7eb2e8f9f7 513 ebiTFTColorSrcMem, /* Use memory as source for mask/blending */ \
<> 144:ef7eb2e8f9f7 514 ebiTFTInterleaveUnlimited, /* Unlimited interleaved accesses */ \
<> 144:ef7eb2e8f9f7 515 ebiTFTFrameBufTriggerVSync, /* VSYNC as frame buffer update trigger */ \
<> 144:ef7eb2e8f9f7 516 false, /* Drive DCLK from negative edge of internal clock */ \
<> 144:ef7eb2e8f9f7 517 ebiTFTMBDisabled, /* No masking and alpha blending enabled */ \
<> 144:ef7eb2e8f9f7 518 ebiTFTDDModeExternal, /* Drive from external memory */ \
<> 144:ef7eb2e8f9f7 519 ebiActiveLow, /* CS Active Low polarity */ \
<> 144:ef7eb2e8f9f7 520 ebiActiveLow, /* DCLK Active Low polarity */ \
<> 144:ef7eb2e8f9f7 521 ebiActiveLow, /* DATAEN Active Low polarity */ \
<> 144:ef7eb2e8f9f7 522 ebiActiveLow, /* HSYNC Active Low polarity */ \
<> 144:ef7eb2e8f9f7 523 ebiActiveLow, /* VSYNC Active Low polarity */ \
<> 144:ef7eb2e8f9f7 524 320, /* Horizontal size in pixels */ \
<> 144:ef7eb2e8f9f7 525 1, /* Horizontal Front Porch */ \
<> 144:ef7eb2e8f9f7 526 29, /* Horizontal Back Porch */ \
<> 144:ef7eb2e8f9f7 527 2, /* Horizontal Synchronization Pulse Width */ \
<> 144:ef7eb2e8f9f7 528 240, /* Vertical size in pixels */ \
<> 144:ef7eb2e8f9f7 529 1, /* Vertical Front Porch */ \
<> 144:ef7eb2e8f9f7 530 4, /* Vertical Back Porch */ \
<> 144:ef7eb2e8f9f7 531 2, /* Vertical Synchronization Pulse Width */ \
<> 144:ef7eb2e8f9f7 532 0x0000, /* Address offset to EBI memory base */ \
<> 144:ef7eb2e8f9f7 533 5, /* DCLK Period */ \
<> 144:ef7eb2e8f9f7 534 2, /* DCLK Start */ \
<> 144:ef7eb2e8f9f7 535 1, /* DCLK Setup cycles */ \
<> 144:ef7eb2e8f9f7 536 1, /* DCLK Hold cycles */ \
<> 144:ef7eb2e8f9f7 537 }
<> 144:ef7eb2e8f9f7 538
<> 144:ef7eb2e8f9f7 539 #endif
<> 144:ef7eb2e8f9f7 540 /*******************************************************************************
<> 144:ef7eb2e8f9f7 541 ***************************** PROTOTYPES **********************************
<> 144:ef7eb2e8f9f7 542 ******************************************************************************/
<> 144:ef7eb2e8f9f7 543
<> 144:ef7eb2e8f9f7 544 void EBI_Init(const EBI_Init_TypeDef *ebiInit);
<> 144:ef7eb2e8f9f7 545 void EBI_Disable(void);
<> 144:ef7eb2e8f9f7 546 uint32_t EBI_BankAddress(uint32_t bank);
<> 144:ef7eb2e8f9f7 547 void EBI_BankEnable(uint32_t banks, bool enable);
<> 144:ef7eb2e8f9f7 548
<> 144:ef7eb2e8f9f7 549 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
<> 144:ef7eb2e8f9f7 550 void EBI_TFTInit(const EBI_TFTInit_TypeDef *ebiTFTInit);
<> 144:ef7eb2e8f9f7 551 void EBI_TFTSizeSet(uint32_t horizontal, uint32_t vertical);
<> 144:ef7eb2e8f9f7 552 void EBI_TFTHPorchSet(int front, int back, int pulseWidth);
<> 144:ef7eb2e8f9f7 553 void EBI_TFTVPorchSet(int front, int back, int pulseWidth);
<> 144:ef7eb2e8f9f7 554 void EBI_TFTTimingSet(int dclkPeriod, int start, int setup, int hold);
<> 144:ef7eb2e8f9f7 555 #endif
<> 144:ef7eb2e8f9f7 556
<> 144:ef7eb2e8f9f7 557 #if defined(_EFM32_GIANT_FAMILY) || defined(_EFM32_WONDER_FAMILY)
<> 144:ef7eb2e8f9f7 558 /* This functionality is only available on devices with independent timing support */
<> 144:ef7eb2e8f9f7 559 void EBI_BankReadTimingSet(uint32_t bank, int setupCycles, int strobeCycles, int holdCycles);
<> 144:ef7eb2e8f9f7 560 void EBI_BankReadTimingConfig(uint32_t bank, bool pageMode, bool prefetch, bool halfRE);
<> 144:ef7eb2e8f9f7 561
<> 144:ef7eb2e8f9f7 562 void EBI_BankWriteTimingSet(uint32_t bank, int setupCycles, int strobeCycles, int holdCycles);
<> 144:ef7eb2e8f9f7 563 void EBI_BankWriteTimingConfig(uint32_t bank, bool writeBufDisable, bool halfWE);
<> 144:ef7eb2e8f9f7 564
<> 144:ef7eb2e8f9f7 565 void EBI_BankAddressTimingSet(uint32_t bank, int setupCycles, int holdCycles);
<> 144:ef7eb2e8f9f7 566 void EBI_BankAddressTimingConfig(uint32_t bank, bool halfALE);
<> 144:ef7eb2e8f9f7 567
<> 144:ef7eb2e8f9f7 568 void EBI_BankPolaritySet(uint32_t bank, EBI_Line_TypeDef line, EBI_Polarity_TypeDef polarity);
<> 144:ef7eb2e8f9f7 569 void EBI_BankByteLaneEnable(uint32_t bank, bool enable);
<> 144:ef7eb2e8f9f7 570 void EBI_AltMapEnable(bool enable);
<> 144:ef7eb2e8f9f7 571
<> 144:ef7eb2e8f9f7 572 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 573 * @brief
<> 144:ef7eb2e8f9f7 574 * Enable or disable TFT Direct Drive
<> 144:ef7eb2e8f9f7 575 *
<> 144:ef7eb2e8f9f7 576 * @param[in] mode
<> 144:ef7eb2e8f9f7 577 * Drive from Internal or External memory, or Disable Direct Drive
<> 144:ef7eb2e8f9f7 578 ******************************************************************************/
<> 144:ef7eb2e8f9f7 579 __STATIC_INLINE void EBI_TFTEnable(EBI_TFTDDMode_TypeDef mode)
<> 144:ef7eb2e8f9f7 580 {
<> 144:ef7eb2e8f9f7 581 EBI->TFTCTRL = (EBI->TFTCTRL & ~(_EBI_TFTCTRL_DD_MASK)) | (uint32_t) mode;
<> 144:ef7eb2e8f9f7 582 }
<> 144:ef7eb2e8f9f7 583
<> 144:ef7eb2e8f9f7 584
<> 144:ef7eb2e8f9f7 585 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 586 * @brief
<> 144:ef7eb2e8f9f7 587 * Configure frame buffer pointer
<> 144:ef7eb2e8f9f7 588 *
<> 144:ef7eb2e8f9f7 589 * @param[in] address
<> 144:ef7eb2e8f9f7 590 * Frame pointer address, as offset by EBI base address
<> 144:ef7eb2e8f9f7 591 ******************************************************************************/
<> 144:ef7eb2e8f9f7 592 __STATIC_INLINE void EBI_TFTFrameBaseSet(uint32_t address)
<> 144:ef7eb2e8f9f7 593 {
<> 144:ef7eb2e8f9f7 594 EBI->TFTFRAMEBASE = (uint32_t) address;
<> 144:ef7eb2e8f9f7 595 }
<> 144:ef7eb2e8f9f7 596
<> 144:ef7eb2e8f9f7 597
<> 144:ef7eb2e8f9f7 598 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 599 * @brief Set TFT Pixel Color 0 or 1
<> 144:ef7eb2e8f9f7 600 *
<> 144:ef7eb2e8f9f7 601 * @param[in] pixel
<> 144:ef7eb2e8f9f7 602 * Which pixel instance to set
<> 144:ef7eb2e8f9f7 603 * @param[in] color
<> 144:ef7eb2e8f9f7 604 * Color of pixel, 16-bit value
<> 144:ef7eb2e8f9f7 605 ******************************************************************************/
<> 144:ef7eb2e8f9f7 606 __STATIC_INLINE void EBI_TFTPixelSet(int pixel, uint32_t color)
<> 144:ef7eb2e8f9f7 607 {
<> 144:ef7eb2e8f9f7 608 EFM_ASSERT(pixel == 0 || pixel == 1);
<> 144:ef7eb2e8f9f7 609
<> 144:ef7eb2e8f9f7 610 if (pixel == 0)
<> 144:ef7eb2e8f9f7 611 {
<> 144:ef7eb2e8f9f7 612 EBI->TFTPIXEL0 = color;
<> 144:ef7eb2e8f9f7 613 }
<> 144:ef7eb2e8f9f7 614 if (pixel == 1)
<> 144:ef7eb2e8f9f7 615 {
<> 144:ef7eb2e8f9f7 616 EBI->TFTPIXEL1 = color;
<> 144:ef7eb2e8f9f7 617 }
<> 144:ef7eb2e8f9f7 618 }
<> 144:ef7eb2e8f9f7 619
<> 144:ef7eb2e8f9f7 620
<> 144:ef7eb2e8f9f7 621 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 622 * @brief Masking and Blending Mode Set
<> 144:ef7eb2e8f9f7 623 *
<> 144:ef7eb2e8f9f7 624 * @param[in] maskBlend
<> 144:ef7eb2e8f9f7 625 * Masking and alpha blending mode
<> 144:ef7eb2e8f9f7 626 ******************************************************************************/
<> 144:ef7eb2e8f9f7 627 __STATIC_INLINE void EBI_TFTMaskBlendMode(EBI_TFTMaskBlend_TypeDef maskBlend)
<> 144:ef7eb2e8f9f7 628 {
<> 144:ef7eb2e8f9f7 629 EBI->TFTCTRL = (EBI->TFTCTRL & (~_EBI_TFTCTRL_MASKBLEND_MASK))|maskBlend;
<> 144:ef7eb2e8f9f7 630 }
<> 144:ef7eb2e8f9f7 631
<> 144:ef7eb2e8f9f7 632
<> 144:ef7eb2e8f9f7 633 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 634 * @brief Set TFT Alpha Blending Factor
<> 144:ef7eb2e8f9f7 635 *
<> 144:ef7eb2e8f9f7 636 * @param[in] alpha
<> 144:ef7eb2e8f9f7 637 * 8-bit value indicating blending factor
<> 144:ef7eb2e8f9f7 638 ******************************************************************************/
<> 144:ef7eb2e8f9f7 639 __STATIC_INLINE void EBI_TFTAlphaBlendSet(uint8_t alpha)
<> 144:ef7eb2e8f9f7 640 {
<> 144:ef7eb2e8f9f7 641 EBI->TFTALPHA = alpha;
<> 144:ef7eb2e8f9f7 642 }
<> 144:ef7eb2e8f9f7 643
<> 144:ef7eb2e8f9f7 644
<> 144:ef7eb2e8f9f7 645 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 646 * @brief Set TFT mask value
<> 144:ef7eb2e8f9f7 647 * Data accesses that matches this value are suppressed
<> 144:ef7eb2e8f9f7 648 * @param[in] mask
<> 144:ef7eb2e8f9f7 649 ******************************************************************************/
<> 144:ef7eb2e8f9f7 650 __STATIC_INLINE void EBI_TFTMaskSet(uint32_t mask)
<> 144:ef7eb2e8f9f7 651 {
<> 144:ef7eb2e8f9f7 652 EBI->TFTMASK = mask;
<> 144:ef7eb2e8f9f7 653 }
<> 144:ef7eb2e8f9f7 654
<> 144:ef7eb2e8f9f7 655
<> 144:ef7eb2e8f9f7 656 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 657 * @brief Get current vertical position counter
<> 144:ef7eb2e8f9f7 658 * @return
<> 144:ef7eb2e8f9f7 659 * Returns the current line position for the visible part of a frame
<> 144:ef7eb2e8f9f7 660 ******************************************************************************/
<> 144:ef7eb2e8f9f7 661 __STATIC_INLINE uint32_t EBI_TFTVCount(void)
<> 144:ef7eb2e8f9f7 662 {
<> 144:ef7eb2e8f9f7 663 return((EBI->TFTSTATUS & _EBI_TFTSTATUS_VCNT_MASK) >> _EBI_TFTSTATUS_VCNT_SHIFT);
<> 144:ef7eb2e8f9f7 664 }
<> 144:ef7eb2e8f9f7 665
<> 144:ef7eb2e8f9f7 666
<> 144:ef7eb2e8f9f7 667 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 668 * @brief Get current horizontal position counter
<> 144:ef7eb2e8f9f7 669 * @return
<> 144:ef7eb2e8f9f7 670 * Returns the current horizontal pixel position within a visible line
<> 144:ef7eb2e8f9f7 671 ******************************************************************************/
<> 144:ef7eb2e8f9f7 672 __STATIC_INLINE uint32_t EBI_TFTHCount(void)
<> 144:ef7eb2e8f9f7 673 {
<> 144:ef7eb2e8f9f7 674 return((EBI->TFTSTATUS & _EBI_TFTSTATUS_HCNT_MASK) >> _EBI_TFTSTATUS_HCNT_SHIFT);
<> 144:ef7eb2e8f9f7 675 }
<> 144:ef7eb2e8f9f7 676
<> 144:ef7eb2e8f9f7 677
<> 144:ef7eb2e8f9f7 678 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 679 * @brief Set Frame Buffer Trigger
<> 144:ef7eb2e8f9f7 680 *
<> 144:ef7eb2e8f9f7 681 * @details
<> 144:ef7eb2e8f9f7 682 * Frame buffer pointer will be updated either on each horizontal line (hsync)
<> 144:ef7eb2e8f9f7 683 * or vertical update (vsync).
<> 144:ef7eb2e8f9f7 684 *
<> 144:ef7eb2e8f9f7 685 * @param[in] sync
<> 144:ef7eb2e8f9f7 686 * Trigger update of frame buffer pointer on vertical or horisontal sync.
<> 144:ef7eb2e8f9f7 687 ******************************************************************************/
<> 144:ef7eb2e8f9f7 688 __STATIC_INLINE void EBI_TFTFBTriggerSet(EBI_TFTFrameBufTrigger_TypeDef sync)
<> 144:ef7eb2e8f9f7 689 {
<> 144:ef7eb2e8f9f7 690 EBI->TFTCTRL = ((EBI->TFTCTRL & ~_EBI_TFTCTRL_FBCTRIG_MASK)|sync);
<> 144:ef7eb2e8f9f7 691 }
<> 144:ef7eb2e8f9f7 692
<> 144:ef7eb2e8f9f7 693
<> 144:ef7eb2e8f9f7 694 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 695 * @brief Set horizontal TFT stride value in number of bytes
<> 144:ef7eb2e8f9f7 696 *
<> 144:ef7eb2e8f9f7 697 * @param[in] nbytes
<> 144:ef7eb2e8f9f7 698 * Number of bytes to add to frame buffer pointer after each horizontal line
<> 144:ef7eb2e8f9f7 699 * update
<> 144:ef7eb2e8f9f7 700 ******************************************************************************/
<> 144:ef7eb2e8f9f7 701 __STATIC_INLINE void EBI_TFTHStrideSet(uint32_t nbytes)
<> 144:ef7eb2e8f9f7 702 {
<> 144:ef7eb2e8f9f7 703 EFM_ASSERT(nbytes < 0x1000);
<> 144:ef7eb2e8f9f7 704
<> 144:ef7eb2e8f9f7 705 EBI->TFTSTRIDE = (EBI->TFTSTRIDE & ~(_EBI_TFTSTRIDE_HSTRIDE_MASK))|
<> 144:ef7eb2e8f9f7 706 (nbytes<<_EBI_TFTSTRIDE_HSTRIDE_SHIFT);
<> 144:ef7eb2e8f9f7 707 }
<> 144:ef7eb2e8f9f7 708
<> 144:ef7eb2e8f9f7 709
<> 144:ef7eb2e8f9f7 710 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 711 * @brief
<> 144:ef7eb2e8f9f7 712 * Clear one or more pending EBI interrupts.
<> 144:ef7eb2e8f9f7 713 * @param[in] flags
<> 144:ef7eb2e8f9f7 714 * Pending EBI interrupt source to clear. Use a logical OR combination
<> 144:ef7eb2e8f9f7 715 * of valid interrupt flags for the EBI module (EBI_IF_nnn).
<> 144:ef7eb2e8f9f7 716 ******************************************************************************/
<> 144:ef7eb2e8f9f7 717 __STATIC_INLINE void EBI_IntClear(uint32_t flags)
<> 144:ef7eb2e8f9f7 718 {
<> 144:ef7eb2e8f9f7 719 EBI->IFC = flags;
<> 144:ef7eb2e8f9f7 720 }
<> 144:ef7eb2e8f9f7 721
<> 144:ef7eb2e8f9f7 722
<> 144:ef7eb2e8f9f7 723 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 724 * @brief
<> 144:ef7eb2e8f9f7 725 * Set one or more pending EBI interrupts.
<> 144:ef7eb2e8f9f7 726 *
<> 144:ef7eb2e8f9f7 727 * @param[in] flags
<> 144:ef7eb2e8f9f7 728 * EBI interrupt sources to set to pending. Use a logical OR combination of
<> 144:ef7eb2e8f9f7 729 * valid interrupt flags for the EBI module (EBI_IF_nnn).
<> 144:ef7eb2e8f9f7 730 ******************************************************************************/
<> 144:ef7eb2e8f9f7 731 __STATIC_INLINE void EBI_IntSet(uint32_t flags)
<> 144:ef7eb2e8f9f7 732 {
<> 144:ef7eb2e8f9f7 733 EBI->IFS = flags;
<> 144:ef7eb2e8f9f7 734 }
<> 144:ef7eb2e8f9f7 735
<> 144:ef7eb2e8f9f7 736
<> 144:ef7eb2e8f9f7 737 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 738 * @brief
<> 144:ef7eb2e8f9f7 739 * Disable one or more EBI interrupts.
<> 144:ef7eb2e8f9f7 740 *
<> 144:ef7eb2e8f9f7 741 * @param[in] flags
<> 144:ef7eb2e8f9f7 742 * EBI interrupt sources to disable. Use logical OR combination of valid
<> 144:ef7eb2e8f9f7 743 * interrupt flags for the EBI module (EBI_IF_nnn)
<> 144:ef7eb2e8f9f7 744 ******************************************************************************/
<> 144:ef7eb2e8f9f7 745 __STATIC_INLINE void EBI_IntDisable(uint32_t flags)
<> 144:ef7eb2e8f9f7 746 {
<> 144:ef7eb2e8f9f7 747 EBI->IEN &= ~(flags);
<> 144:ef7eb2e8f9f7 748 }
<> 144:ef7eb2e8f9f7 749
<> 144:ef7eb2e8f9f7 750
<> 144:ef7eb2e8f9f7 751 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 752 * @brief
<> 144:ef7eb2e8f9f7 753 * Enable one or more EBI interrupts.
<> 144:ef7eb2e8f9f7 754 *
<> 144:ef7eb2e8f9f7 755 * @param[in] flags
<> 144:ef7eb2e8f9f7 756 * EBI interrupt sources to enable. Use logical OR combination of valid
<> 144:ef7eb2e8f9f7 757 * interrupt flags for the EBI module (EBI_IF_nnn)
<> 144:ef7eb2e8f9f7 758 ******************************************************************************/
<> 144:ef7eb2e8f9f7 759 __STATIC_INLINE void EBI_IntEnable(uint32_t flags)
<> 144:ef7eb2e8f9f7 760 {
<> 144:ef7eb2e8f9f7 761 EBI->IEN |= flags;
<> 144:ef7eb2e8f9f7 762 }
<> 144:ef7eb2e8f9f7 763
<> 144:ef7eb2e8f9f7 764
<> 144:ef7eb2e8f9f7 765 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 766 * @brief
<> 144:ef7eb2e8f9f7 767 * Get pending EBI interrupt flags.
<> 144:ef7eb2e8f9f7 768 *
<> 144:ef7eb2e8f9f7 769 * @note
<> 144:ef7eb2e8f9f7 770 * The event bits are not cleared by the use of this function
<> 144:ef7eb2e8f9f7 771 *
<> 144:ef7eb2e8f9f7 772 * @return
<> 144:ef7eb2e8f9f7 773 * EBI interrupt sources pending, a logical combination of valid EBI
<> 144:ef7eb2e8f9f7 774 * interrupt flags, EBI_IF_nnn
<> 144:ef7eb2e8f9f7 775 ******************************************************************************/
<> 144:ef7eb2e8f9f7 776 __STATIC_INLINE uint32_t EBI_IntGet(void)
<> 144:ef7eb2e8f9f7 777 {
<> 144:ef7eb2e8f9f7 778 return EBI->IF;
<> 144:ef7eb2e8f9f7 779 }
<> 144:ef7eb2e8f9f7 780
<> 144:ef7eb2e8f9f7 781
<> 144:ef7eb2e8f9f7 782 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 783 * @brief
<> 144:ef7eb2e8f9f7 784 * Get enabled and pending EBI interrupt flags.
<> 144:ef7eb2e8f9f7 785 * Useful for handling more interrupt sources in the same interrupt handler.
<> 144:ef7eb2e8f9f7 786 *
<> 144:ef7eb2e8f9f7 787 * @note
<> 144:ef7eb2e8f9f7 788 * Interrupt flags are not cleared by the use of this function.
<> 144:ef7eb2e8f9f7 789 *
<> 144:ef7eb2e8f9f7 790 * @return
<> 144:ef7eb2e8f9f7 791 * Pending and enabled EBI interrupt sources
<> 144:ef7eb2e8f9f7 792 * The return value is the bitwise AND of
<> 144:ef7eb2e8f9f7 793 * - the enabled interrupt sources in EBI_IEN and
<> 144:ef7eb2e8f9f7 794 * - the pending interrupt flags EBI_IF
<> 144:ef7eb2e8f9f7 795 ******************************************************************************/
<> 144:ef7eb2e8f9f7 796 __STATIC_INLINE uint32_t EBI_IntGetEnabled(void)
<> 144:ef7eb2e8f9f7 797 {
<> 144:ef7eb2e8f9f7 798 uint32_t ien;
<> 144:ef7eb2e8f9f7 799
<> 144:ef7eb2e8f9f7 800 ien = EBI->IEN;
<> 144:ef7eb2e8f9f7 801 return EBI->IF & ien;
<> 144:ef7eb2e8f9f7 802 }
<> 144:ef7eb2e8f9f7 803
<> 144:ef7eb2e8f9f7 804
<> 144:ef7eb2e8f9f7 805 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 806 * @brief
<> 144:ef7eb2e8f9f7 807 * Start ECC generator on NAND flash transfers.
<> 144:ef7eb2e8f9f7 808 ******************************************************************************/
<> 144:ef7eb2e8f9f7 809 __STATIC_INLINE void EBI_StartNandEccGen(void)
<> 144:ef7eb2e8f9f7 810 {
<> 144:ef7eb2e8f9f7 811 EBI->CMD = EBI_CMD_ECCSTART | EBI_CMD_ECCCLEAR;
<> 144:ef7eb2e8f9f7 812 }
<> 144:ef7eb2e8f9f7 813
<> 144:ef7eb2e8f9f7 814
<> 144:ef7eb2e8f9f7 815 /***************************************************************************//**
<> 144:ef7eb2e8f9f7 816 * @brief
<> 144:ef7eb2e8f9f7 817 * Stop NAND flash ECC generator and return generated ECC.
<> 144:ef7eb2e8f9f7 818 *
<> 144:ef7eb2e8f9f7 819 * @return
<> 144:ef7eb2e8f9f7 820 * The generated ECC.
<> 144:ef7eb2e8f9f7 821 ******************************************************************************/
<> 144:ef7eb2e8f9f7 822 __STATIC_INLINE uint32_t EBI_StopNandEccGen( void )
<> 144:ef7eb2e8f9f7 823 {
<> 144:ef7eb2e8f9f7 824 EBI->CMD = EBI_CMD_ECCSTOP;
<> 144:ef7eb2e8f9f7 825 return EBI->ECCPARITY;
<> 144:ef7eb2e8f9f7 826 }
<> 144:ef7eb2e8f9f7 827 #endif
<> 144:ef7eb2e8f9f7 828
<> 144:ef7eb2e8f9f7 829 void EBI_ChipSelectEnable(uint32_t banks, bool enable);
<> 144:ef7eb2e8f9f7 830 void EBI_ReadTimingSet(int setupCycles, int strobeCycles, int holdCycles);
<> 144:ef7eb2e8f9f7 831 void EBI_WriteTimingSet(int setupCycles, int strobeCycles, int holdCycles);
<> 144:ef7eb2e8f9f7 832 void EBI_AddressTimingSet(int setupCycles, int holdCycles);
<> 144:ef7eb2e8f9f7 833 void EBI_PolaritySet(EBI_Line_TypeDef line, EBI_Polarity_TypeDef polarity);
<> 144:ef7eb2e8f9f7 834
<> 144:ef7eb2e8f9f7 835 /** @} (end addtogroup EBI) */
<> 144:ef7eb2e8f9f7 836 /** @} (end addtogroup EM_Library) */
<> 144:ef7eb2e8f9f7 837
<> 144:ef7eb2e8f9f7 838 #ifdef __cplusplus
<> 144:ef7eb2e8f9f7 839 }
<> 144:ef7eb2e8f9f7 840 #endif
<> 144:ef7eb2e8f9f7 841
<> 144:ef7eb2e8f9f7 842 #endif /* defined(EBI_COUNT) && (EBI_COUNT > 0) */
<> 144:ef7eb2e8f9f7 843
<> 144:ef7eb2e8f9f7 844 #endif /* __SILICON_LABS_EM_EBI_H__ */