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targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32HG_STK3400/efm32hg_i2c.h@0:9b334a45a8ff, 2015-10-01 (annotated)
- Committer:
- bogdanm
- Date:
- Thu Oct 01 15:25:22 2015 +0300
- Revision:
- 0:9b334a45a8ff
- Child:
- 50:a417edff4437
Initial commit on mbed-dev
Replaces mbed-src (now inactive)
Who changed what in which revision?
| User | Revision | Line number | New contents of line |
|---|---|---|---|
| bogdanm | 0:9b334a45a8ff | 1 | /**************************************************************************//** |
| bogdanm | 0:9b334a45a8ff | 2 | * @file efm32hg_i2c.h |
| bogdanm | 0:9b334a45a8ff | 3 | * @brief EFM32HG_I2C register and bit field definitions |
| bogdanm | 0:9b334a45a8ff | 4 | * @version 3.20.12 |
| bogdanm | 0:9b334a45a8ff | 5 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 6 | * @section License |
| bogdanm | 0:9b334a45a8ff | 7 | * <b>(C) Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b> |
| bogdanm | 0:9b334a45a8ff | 8 | ****************************************************************************** |
| bogdanm | 0:9b334a45a8ff | 9 | * |
| bogdanm | 0:9b334a45a8ff | 10 | * Permission is granted to anyone to use this software for any purpose, |
| bogdanm | 0:9b334a45a8ff | 11 | * including commercial applications, and to alter it and redistribute it |
| bogdanm | 0:9b334a45a8ff | 12 | * freely, subject to the following restrictions: |
| bogdanm | 0:9b334a45a8ff | 13 | * |
| bogdanm | 0:9b334a45a8ff | 14 | * 1. The origin of this software must not be misrepresented; you must not |
| bogdanm | 0:9b334a45a8ff | 15 | * claim that you wrote the original software.@n |
| bogdanm | 0:9b334a45a8ff | 16 | * 2. Altered source versions must be plainly marked as such, and must not be |
| bogdanm | 0:9b334a45a8ff | 17 | * misrepresented as being the original software.@n |
| bogdanm | 0:9b334a45a8ff | 18 | * 3. This notice may not be removed or altered from any source distribution. |
| bogdanm | 0:9b334a45a8ff | 19 | * |
| bogdanm | 0:9b334a45a8ff | 20 | * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc. |
| bogdanm | 0:9b334a45a8ff | 21 | * has no obligation to support this Software. Silicon Laboratories, Inc. is |
| bogdanm | 0:9b334a45a8ff | 22 | * providing the Software "AS IS", with no express or implied warranties of any |
| bogdanm | 0:9b334a45a8ff | 23 | * kind, including, but not limited to, any implied warranties of |
| bogdanm | 0:9b334a45a8ff | 24 | * merchantability or fitness for any particular purpose or warranties against |
| bogdanm | 0:9b334a45a8ff | 25 | * infringement of any proprietary rights of a third party. |
| bogdanm | 0:9b334a45a8ff | 26 | * |
| bogdanm | 0:9b334a45a8ff | 27 | * Silicon Laboratories, Inc. will not be liable for any consequential, |
| bogdanm | 0:9b334a45a8ff | 28 | * incidental, or special damages, or any other relief, or for any claim by |
| bogdanm | 0:9b334a45a8ff | 29 | * any third party, arising from your use of this Software. |
| bogdanm | 0:9b334a45a8ff | 30 | * |
| bogdanm | 0:9b334a45a8ff | 31 | *****************************************************************************/ |
| bogdanm | 0:9b334a45a8ff | 32 | /**************************************************************************//** |
| bogdanm | 0:9b334a45a8ff | 33 | * @defgroup EFM32HG_I2C |
| bogdanm | 0:9b334a45a8ff | 34 | * @{ |
| bogdanm | 0:9b334a45a8ff | 35 | * @brief EFM32HG_I2C Register Declaration |
| bogdanm | 0:9b334a45a8ff | 36 | *****************************************************************************/ |
| bogdanm | 0:9b334a45a8ff | 37 | typedef struct |
| bogdanm | 0:9b334a45a8ff | 38 | { |
| bogdanm | 0:9b334a45a8ff | 39 | __IO uint32_t CTRL; /**< Control Register */ |
| bogdanm | 0:9b334a45a8ff | 40 | __IO uint32_t CMD; /**< Command Register */ |
| bogdanm | 0:9b334a45a8ff | 41 | __I uint32_t STATE; /**< State Register */ |
| bogdanm | 0:9b334a45a8ff | 42 | __I uint32_t STATUS; /**< Status Register */ |
| bogdanm | 0:9b334a45a8ff | 43 | __IO uint32_t CLKDIV; /**< Clock Division Register */ |
| bogdanm | 0:9b334a45a8ff | 44 | __IO uint32_t SADDR; /**< Slave Address Register */ |
| bogdanm | 0:9b334a45a8ff | 45 | __IO uint32_t SADDRMASK; /**< Slave Address Mask Register */ |
| bogdanm | 0:9b334a45a8ff | 46 | __I uint32_t RXDATA; /**< Receive Buffer Data Register */ |
| bogdanm | 0:9b334a45a8ff | 47 | __I uint32_t RXDATAP; /**< Receive Buffer Data Peek Register */ |
| bogdanm | 0:9b334a45a8ff | 48 | __IO uint32_t TXDATA; /**< Transmit Buffer Data Register */ |
| bogdanm | 0:9b334a45a8ff | 49 | __I uint32_t IF; /**< Interrupt Flag Register */ |
| bogdanm | 0:9b334a45a8ff | 50 | __IO uint32_t IFS; /**< Interrupt Flag Set Register */ |
| bogdanm | 0:9b334a45a8ff | 51 | __IO uint32_t IFC; /**< Interrupt Flag Clear Register */ |
| bogdanm | 0:9b334a45a8ff | 52 | __IO uint32_t IEN; /**< Interrupt Enable Register */ |
| bogdanm | 0:9b334a45a8ff | 53 | __IO uint32_t ROUTE; /**< I/O Routing Register */ |
| bogdanm | 0:9b334a45a8ff | 54 | } I2C_TypeDef; /** @} */ |
| bogdanm | 0:9b334a45a8ff | 55 | |
| bogdanm | 0:9b334a45a8ff | 56 | /**************************************************************************//** |
| bogdanm | 0:9b334a45a8ff | 57 | * @defgroup EFM32HG_I2C_BitFields |
| bogdanm | 0:9b334a45a8ff | 58 | * @{ |
| bogdanm | 0:9b334a45a8ff | 59 | *****************************************************************************/ |
| bogdanm | 0:9b334a45a8ff | 60 | |
| bogdanm | 0:9b334a45a8ff | 61 | /* Bit fields for I2C CTRL */ |
| bogdanm | 0:9b334a45a8ff | 62 | #define _I2C_CTRL_RESETVALUE 0x00000000UL /**< Default value for I2C_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 63 | #define _I2C_CTRL_MASK 0x0007B37FUL /**< Mask for I2C_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 64 | #define I2C_CTRL_EN (0x1UL << 0) /**< I2C Enable */ |
| bogdanm | 0:9b334a45a8ff | 65 | #define _I2C_CTRL_EN_SHIFT 0 /**< Shift value for I2C_EN */ |
| bogdanm | 0:9b334a45a8ff | 66 | #define _I2C_CTRL_EN_MASK 0x1UL /**< Bit mask for I2C_EN */ |
| bogdanm | 0:9b334a45a8ff | 67 | #define _I2C_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 68 | #define I2C_CTRL_EN_DEFAULT (_I2C_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 69 | #define I2C_CTRL_SLAVE (0x1UL << 1) /**< Addressable as Slave */ |
| bogdanm | 0:9b334a45a8ff | 70 | #define _I2C_CTRL_SLAVE_SHIFT 1 /**< Shift value for I2C_SLAVE */ |
| bogdanm | 0:9b334a45a8ff | 71 | #define _I2C_CTRL_SLAVE_MASK 0x2UL /**< Bit mask for I2C_SLAVE */ |
| bogdanm | 0:9b334a45a8ff | 72 | #define _I2C_CTRL_SLAVE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 73 | #define I2C_CTRL_SLAVE_DEFAULT (_I2C_CTRL_SLAVE_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 74 | #define I2C_CTRL_AUTOACK (0x1UL << 2) /**< Automatic Acknowledge */ |
| bogdanm | 0:9b334a45a8ff | 75 | #define _I2C_CTRL_AUTOACK_SHIFT 2 /**< Shift value for I2C_AUTOACK */ |
| bogdanm | 0:9b334a45a8ff | 76 | #define _I2C_CTRL_AUTOACK_MASK 0x4UL /**< Bit mask for I2C_AUTOACK */ |
| bogdanm | 0:9b334a45a8ff | 77 | #define _I2C_CTRL_AUTOACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 78 | #define I2C_CTRL_AUTOACK_DEFAULT (_I2C_CTRL_AUTOACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 79 | #define I2C_CTRL_AUTOSE (0x1UL << 3) /**< Automatic STOP when Empty */ |
| bogdanm | 0:9b334a45a8ff | 80 | #define _I2C_CTRL_AUTOSE_SHIFT 3 /**< Shift value for I2C_AUTOSE */ |
| bogdanm | 0:9b334a45a8ff | 81 | #define _I2C_CTRL_AUTOSE_MASK 0x8UL /**< Bit mask for I2C_AUTOSE */ |
| bogdanm | 0:9b334a45a8ff | 82 | #define _I2C_CTRL_AUTOSE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 83 | #define I2C_CTRL_AUTOSE_DEFAULT (_I2C_CTRL_AUTOSE_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 84 | #define I2C_CTRL_AUTOSN (0x1UL << 4) /**< Automatic STOP on NACK */ |
| bogdanm | 0:9b334a45a8ff | 85 | #define _I2C_CTRL_AUTOSN_SHIFT 4 /**< Shift value for I2C_AUTOSN */ |
| bogdanm | 0:9b334a45a8ff | 86 | #define _I2C_CTRL_AUTOSN_MASK 0x10UL /**< Bit mask for I2C_AUTOSN */ |
| bogdanm | 0:9b334a45a8ff | 87 | #define _I2C_CTRL_AUTOSN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 88 | #define I2C_CTRL_AUTOSN_DEFAULT (_I2C_CTRL_AUTOSN_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 89 | #define I2C_CTRL_ARBDIS (0x1UL << 5) /**< Arbitration Disable */ |
| bogdanm | 0:9b334a45a8ff | 90 | #define _I2C_CTRL_ARBDIS_SHIFT 5 /**< Shift value for I2C_ARBDIS */ |
| bogdanm | 0:9b334a45a8ff | 91 | #define _I2C_CTRL_ARBDIS_MASK 0x20UL /**< Bit mask for I2C_ARBDIS */ |
| bogdanm | 0:9b334a45a8ff | 92 | #define _I2C_CTRL_ARBDIS_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 93 | #define I2C_CTRL_ARBDIS_DEFAULT (_I2C_CTRL_ARBDIS_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 94 | #define I2C_CTRL_GCAMEN (0x1UL << 6) /**< General Call Address Match Enable */ |
| bogdanm | 0:9b334a45a8ff | 95 | #define _I2C_CTRL_GCAMEN_SHIFT 6 /**< Shift value for I2C_GCAMEN */ |
| bogdanm | 0:9b334a45a8ff | 96 | #define _I2C_CTRL_GCAMEN_MASK 0x40UL /**< Bit mask for I2C_GCAMEN */ |
| bogdanm | 0:9b334a45a8ff | 97 | #define _I2C_CTRL_GCAMEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 98 | #define I2C_CTRL_GCAMEN_DEFAULT (_I2C_CTRL_GCAMEN_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 99 | #define _I2C_CTRL_CLHR_SHIFT 8 /**< Shift value for I2C_CLHR */ |
| bogdanm | 0:9b334a45a8ff | 100 | #define _I2C_CTRL_CLHR_MASK 0x300UL /**< Bit mask for I2C_CLHR */ |
| bogdanm | 0:9b334a45a8ff | 101 | #define _I2C_CTRL_CLHR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 102 | #define _I2C_CTRL_CLHR_STANDARD 0x00000000UL /**< Mode STANDARD for I2C_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 103 | #define _I2C_CTRL_CLHR_ASYMMETRIC 0x00000001UL /**< Mode ASYMMETRIC for I2C_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 104 | #define _I2C_CTRL_CLHR_FAST 0x00000002UL /**< Mode FAST for I2C_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 105 | #define I2C_CTRL_CLHR_DEFAULT (_I2C_CTRL_CLHR_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 106 | #define I2C_CTRL_CLHR_STANDARD (_I2C_CTRL_CLHR_STANDARD << 8) /**< Shifted mode STANDARD for I2C_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 107 | #define I2C_CTRL_CLHR_ASYMMETRIC (_I2C_CTRL_CLHR_ASYMMETRIC << 8) /**< Shifted mode ASYMMETRIC for I2C_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 108 | #define I2C_CTRL_CLHR_FAST (_I2C_CTRL_CLHR_FAST << 8) /**< Shifted mode FAST for I2C_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 109 | #define _I2C_CTRL_BITO_SHIFT 12 /**< Shift value for I2C_BITO */ |
| bogdanm | 0:9b334a45a8ff | 110 | #define _I2C_CTRL_BITO_MASK 0x3000UL /**< Bit mask for I2C_BITO */ |
| bogdanm | 0:9b334a45a8ff | 111 | #define _I2C_CTRL_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 112 | #define _I2C_CTRL_BITO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 113 | #define _I2C_CTRL_BITO_40PCC 0x00000001UL /**< Mode 40PCC for I2C_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 114 | #define _I2C_CTRL_BITO_80PCC 0x00000002UL /**< Mode 80PCC for I2C_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 115 | #define _I2C_CTRL_BITO_160PCC 0x00000003UL /**< Mode 160PCC for I2C_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 116 | #define I2C_CTRL_BITO_DEFAULT (_I2C_CTRL_BITO_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 117 | #define I2C_CTRL_BITO_OFF (_I2C_CTRL_BITO_OFF << 12) /**< Shifted mode OFF for I2C_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 118 | #define I2C_CTRL_BITO_40PCC (_I2C_CTRL_BITO_40PCC << 12) /**< Shifted mode 40PCC for I2C_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 119 | #define I2C_CTRL_BITO_80PCC (_I2C_CTRL_BITO_80PCC << 12) /**< Shifted mode 80PCC for I2C_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 120 | #define I2C_CTRL_BITO_160PCC (_I2C_CTRL_BITO_160PCC << 12) /**< Shifted mode 160PCC for I2C_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 121 | #define I2C_CTRL_GIBITO (0x1UL << 15) /**< Go Idle on Bus Idle Timeout */ |
| bogdanm | 0:9b334a45a8ff | 122 | #define _I2C_CTRL_GIBITO_SHIFT 15 /**< Shift value for I2C_GIBITO */ |
| bogdanm | 0:9b334a45a8ff | 123 | #define _I2C_CTRL_GIBITO_MASK 0x8000UL /**< Bit mask for I2C_GIBITO */ |
| bogdanm | 0:9b334a45a8ff | 124 | #define _I2C_CTRL_GIBITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 125 | #define I2C_CTRL_GIBITO_DEFAULT (_I2C_CTRL_GIBITO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 126 | #define _I2C_CTRL_CLTO_SHIFT 16 /**< Shift value for I2C_CLTO */ |
| bogdanm | 0:9b334a45a8ff | 127 | #define _I2C_CTRL_CLTO_MASK 0x70000UL /**< Bit mask for I2C_CLTO */ |
| bogdanm | 0:9b334a45a8ff | 128 | #define _I2C_CTRL_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 129 | #define _I2C_CTRL_CLTO_OFF 0x00000000UL /**< Mode OFF for I2C_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 130 | #define _I2C_CTRL_CLTO_40PCC 0x00000001UL /**< Mode 40PCC for I2C_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 131 | #define _I2C_CTRL_CLTO_80PCC 0x00000002UL /**< Mode 80PCC for I2C_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 132 | #define _I2C_CTRL_CLTO_160PCC 0x00000003UL /**< Mode 160PCC for I2C_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 133 | #define _I2C_CTRL_CLTO_320PPC 0x00000004UL /**< Mode 320PPC for I2C_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 134 | #define _I2C_CTRL_CLTO_1024PPC 0x00000005UL /**< Mode 1024PPC for I2C_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 135 | #define I2C_CTRL_CLTO_DEFAULT (_I2C_CTRL_CLTO_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 136 | #define I2C_CTRL_CLTO_OFF (_I2C_CTRL_CLTO_OFF << 16) /**< Shifted mode OFF for I2C_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 137 | #define I2C_CTRL_CLTO_40PCC (_I2C_CTRL_CLTO_40PCC << 16) /**< Shifted mode 40PCC for I2C_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 138 | #define I2C_CTRL_CLTO_80PCC (_I2C_CTRL_CLTO_80PCC << 16) /**< Shifted mode 80PCC for I2C_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 139 | #define I2C_CTRL_CLTO_160PCC (_I2C_CTRL_CLTO_160PCC << 16) /**< Shifted mode 160PCC for I2C_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 140 | #define I2C_CTRL_CLTO_320PPC (_I2C_CTRL_CLTO_320PPC << 16) /**< Shifted mode 320PPC for I2C_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 141 | #define I2C_CTRL_CLTO_1024PPC (_I2C_CTRL_CLTO_1024PPC << 16) /**< Shifted mode 1024PPC for I2C_CTRL */ |
| bogdanm | 0:9b334a45a8ff | 142 | |
| bogdanm | 0:9b334a45a8ff | 143 | /* Bit fields for I2C CMD */ |
| bogdanm | 0:9b334a45a8ff | 144 | #define _I2C_CMD_RESETVALUE 0x00000000UL /**< Default value for I2C_CMD */ |
| bogdanm | 0:9b334a45a8ff | 145 | #define _I2C_CMD_MASK 0x000000FFUL /**< Mask for I2C_CMD */ |
| bogdanm | 0:9b334a45a8ff | 146 | #define I2C_CMD_START (0x1UL << 0) /**< Send start condition */ |
| bogdanm | 0:9b334a45a8ff | 147 | #define _I2C_CMD_START_SHIFT 0 /**< Shift value for I2C_START */ |
| bogdanm | 0:9b334a45a8ff | 148 | #define _I2C_CMD_START_MASK 0x1UL /**< Bit mask for I2C_START */ |
| bogdanm | 0:9b334a45a8ff | 149 | #define _I2C_CMD_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ |
| bogdanm | 0:9b334a45a8ff | 150 | #define I2C_CMD_START_DEFAULT (_I2C_CMD_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CMD */ |
| bogdanm | 0:9b334a45a8ff | 151 | #define I2C_CMD_STOP (0x1UL << 1) /**< Send stop condition */ |
| bogdanm | 0:9b334a45a8ff | 152 | #define _I2C_CMD_STOP_SHIFT 1 /**< Shift value for I2C_STOP */ |
| bogdanm | 0:9b334a45a8ff | 153 | #define _I2C_CMD_STOP_MASK 0x2UL /**< Bit mask for I2C_STOP */ |
| bogdanm | 0:9b334a45a8ff | 154 | #define _I2C_CMD_STOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ |
| bogdanm | 0:9b334a45a8ff | 155 | #define I2C_CMD_STOP_DEFAULT (_I2C_CMD_STOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_CMD */ |
| bogdanm | 0:9b334a45a8ff | 156 | #define I2C_CMD_ACK (0x1UL << 2) /**< Send ACK */ |
| bogdanm | 0:9b334a45a8ff | 157 | #define _I2C_CMD_ACK_SHIFT 2 /**< Shift value for I2C_ACK */ |
| bogdanm | 0:9b334a45a8ff | 158 | #define _I2C_CMD_ACK_MASK 0x4UL /**< Bit mask for I2C_ACK */ |
| bogdanm | 0:9b334a45a8ff | 159 | #define _I2C_CMD_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ |
| bogdanm | 0:9b334a45a8ff | 160 | #define I2C_CMD_ACK_DEFAULT (_I2C_CMD_ACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_CMD */ |
| bogdanm | 0:9b334a45a8ff | 161 | #define I2C_CMD_NACK (0x1UL << 3) /**< Send NACK */ |
| bogdanm | 0:9b334a45a8ff | 162 | #define _I2C_CMD_NACK_SHIFT 3 /**< Shift value for I2C_NACK */ |
| bogdanm | 0:9b334a45a8ff | 163 | #define _I2C_CMD_NACK_MASK 0x8UL /**< Bit mask for I2C_NACK */ |
| bogdanm | 0:9b334a45a8ff | 164 | #define _I2C_CMD_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ |
| bogdanm | 0:9b334a45a8ff | 165 | #define I2C_CMD_NACK_DEFAULT (_I2C_CMD_NACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_CMD */ |
| bogdanm | 0:9b334a45a8ff | 166 | #define I2C_CMD_CONT (0x1UL << 4) /**< Continue transmission */ |
| bogdanm | 0:9b334a45a8ff | 167 | #define _I2C_CMD_CONT_SHIFT 4 /**< Shift value for I2C_CONT */ |
| bogdanm | 0:9b334a45a8ff | 168 | #define _I2C_CMD_CONT_MASK 0x10UL /**< Bit mask for I2C_CONT */ |
| bogdanm | 0:9b334a45a8ff | 169 | #define _I2C_CMD_CONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ |
| bogdanm | 0:9b334a45a8ff | 170 | #define I2C_CMD_CONT_DEFAULT (_I2C_CMD_CONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_CMD */ |
| bogdanm | 0:9b334a45a8ff | 171 | #define I2C_CMD_ABORT (0x1UL << 5) /**< Abort transmission */ |
| bogdanm | 0:9b334a45a8ff | 172 | #define _I2C_CMD_ABORT_SHIFT 5 /**< Shift value for I2C_ABORT */ |
| bogdanm | 0:9b334a45a8ff | 173 | #define _I2C_CMD_ABORT_MASK 0x20UL /**< Bit mask for I2C_ABORT */ |
| bogdanm | 0:9b334a45a8ff | 174 | #define _I2C_CMD_ABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ |
| bogdanm | 0:9b334a45a8ff | 175 | #define I2C_CMD_ABORT_DEFAULT (_I2C_CMD_ABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_CMD */ |
| bogdanm | 0:9b334a45a8ff | 176 | #define I2C_CMD_CLEARTX (0x1UL << 6) /**< Clear TX */ |
| bogdanm | 0:9b334a45a8ff | 177 | #define _I2C_CMD_CLEARTX_SHIFT 6 /**< Shift value for I2C_CLEARTX */ |
| bogdanm | 0:9b334a45a8ff | 178 | #define _I2C_CMD_CLEARTX_MASK 0x40UL /**< Bit mask for I2C_CLEARTX */ |
| bogdanm | 0:9b334a45a8ff | 179 | #define _I2C_CMD_CLEARTX_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ |
| bogdanm | 0:9b334a45a8ff | 180 | #define I2C_CMD_CLEARTX_DEFAULT (_I2C_CMD_CLEARTX_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_CMD */ |
| bogdanm | 0:9b334a45a8ff | 181 | #define I2C_CMD_CLEARPC (0x1UL << 7) /**< Clear Pending Commands */ |
| bogdanm | 0:9b334a45a8ff | 182 | #define _I2C_CMD_CLEARPC_SHIFT 7 /**< Shift value for I2C_CLEARPC */ |
| bogdanm | 0:9b334a45a8ff | 183 | #define _I2C_CMD_CLEARPC_MASK 0x80UL /**< Bit mask for I2C_CLEARPC */ |
| bogdanm | 0:9b334a45a8ff | 184 | #define _I2C_CMD_CLEARPC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CMD */ |
| bogdanm | 0:9b334a45a8ff | 185 | #define I2C_CMD_CLEARPC_DEFAULT (_I2C_CMD_CLEARPC_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_CMD */ |
| bogdanm | 0:9b334a45a8ff | 186 | |
| bogdanm | 0:9b334a45a8ff | 187 | /* Bit fields for I2C STATE */ |
| bogdanm | 0:9b334a45a8ff | 188 | #define _I2C_STATE_RESETVALUE 0x00000001UL /**< Default value for I2C_STATE */ |
| bogdanm | 0:9b334a45a8ff | 189 | #define _I2C_STATE_MASK 0x000000FFUL /**< Mask for I2C_STATE */ |
| bogdanm | 0:9b334a45a8ff | 190 | #define I2C_STATE_BUSY (0x1UL << 0) /**< Bus Busy */ |
| bogdanm | 0:9b334a45a8ff | 191 | #define _I2C_STATE_BUSY_SHIFT 0 /**< Shift value for I2C_BUSY */ |
| bogdanm | 0:9b334a45a8ff | 192 | #define _I2C_STATE_BUSY_MASK 0x1UL /**< Bit mask for I2C_BUSY */ |
| bogdanm | 0:9b334a45a8ff | 193 | #define _I2C_STATE_BUSY_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATE */ |
| bogdanm | 0:9b334a45a8ff | 194 | #define I2C_STATE_BUSY_DEFAULT (_I2C_STATE_BUSY_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATE */ |
| bogdanm | 0:9b334a45a8ff | 195 | #define I2C_STATE_MASTER (0x1UL << 1) /**< Master */ |
| bogdanm | 0:9b334a45a8ff | 196 | #define _I2C_STATE_MASTER_SHIFT 1 /**< Shift value for I2C_MASTER */ |
| bogdanm | 0:9b334a45a8ff | 197 | #define _I2C_STATE_MASTER_MASK 0x2UL /**< Bit mask for I2C_MASTER */ |
| bogdanm | 0:9b334a45a8ff | 198 | #define _I2C_STATE_MASTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ |
| bogdanm | 0:9b334a45a8ff | 199 | #define I2C_STATE_MASTER_DEFAULT (_I2C_STATE_MASTER_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATE */ |
| bogdanm | 0:9b334a45a8ff | 200 | #define I2C_STATE_TRANSMITTER (0x1UL << 2) /**< Transmitter */ |
| bogdanm | 0:9b334a45a8ff | 201 | #define _I2C_STATE_TRANSMITTER_SHIFT 2 /**< Shift value for I2C_TRANSMITTER */ |
| bogdanm | 0:9b334a45a8ff | 202 | #define _I2C_STATE_TRANSMITTER_MASK 0x4UL /**< Bit mask for I2C_TRANSMITTER */ |
| bogdanm | 0:9b334a45a8ff | 203 | #define _I2C_STATE_TRANSMITTER_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ |
| bogdanm | 0:9b334a45a8ff | 204 | #define I2C_STATE_TRANSMITTER_DEFAULT (_I2C_STATE_TRANSMITTER_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATE */ |
| bogdanm | 0:9b334a45a8ff | 205 | #define I2C_STATE_NACKED (0x1UL << 3) /**< Nack Received */ |
| bogdanm | 0:9b334a45a8ff | 206 | #define _I2C_STATE_NACKED_SHIFT 3 /**< Shift value for I2C_NACKED */ |
| bogdanm | 0:9b334a45a8ff | 207 | #define _I2C_STATE_NACKED_MASK 0x8UL /**< Bit mask for I2C_NACKED */ |
| bogdanm | 0:9b334a45a8ff | 208 | #define _I2C_STATE_NACKED_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ |
| bogdanm | 0:9b334a45a8ff | 209 | #define I2C_STATE_NACKED_DEFAULT (_I2C_STATE_NACKED_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATE */ |
| bogdanm | 0:9b334a45a8ff | 210 | #define I2C_STATE_BUSHOLD (0x1UL << 4) /**< Bus Held */ |
| bogdanm | 0:9b334a45a8ff | 211 | #define _I2C_STATE_BUSHOLD_SHIFT 4 /**< Shift value for I2C_BUSHOLD */ |
| bogdanm | 0:9b334a45a8ff | 212 | #define _I2C_STATE_BUSHOLD_MASK 0x10UL /**< Bit mask for I2C_BUSHOLD */ |
| bogdanm | 0:9b334a45a8ff | 213 | #define _I2C_STATE_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ |
| bogdanm | 0:9b334a45a8ff | 214 | #define I2C_STATE_BUSHOLD_DEFAULT (_I2C_STATE_BUSHOLD_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATE */ |
| bogdanm | 0:9b334a45a8ff | 215 | #define _I2C_STATE_STATE_SHIFT 5 /**< Shift value for I2C_STATE */ |
| bogdanm | 0:9b334a45a8ff | 216 | #define _I2C_STATE_STATE_MASK 0xE0UL /**< Bit mask for I2C_STATE */ |
| bogdanm | 0:9b334a45a8ff | 217 | #define _I2C_STATE_STATE_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATE */ |
| bogdanm | 0:9b334a45a8ff | 218 | #define _I2C_STATE_STATE_IDLE 0x00000000UL /**< Mode IDLE for I2C_STATE */ |
| bogdanm | 0:9b334a45a8ff | 219 | #define _I2C_STATE_STATE_WAIT 0x00000001UL /**< Mode WAIT for I2C_STATE */ |
| bogdanm | 0:9b334a45a8ff | 220 | #define _I2C_STATE_STATE_START 0x00000002UL /**< Mode START for I2C_STATE */ |
| bogdanm | 0:9b334a45a8ff | 221 | #define _I2C_STATE_STATE_ADDR 0x00000003UL /**< Mode ADDR for I2C_STATE */ |
| bogdanm | 0:9b334a45a8ff | 222 | #define _I2C_STATE_STATE_ADDRACK 0x00000004UL /**< Mode ADDRACK for I2C_STATE */ |
| bogdanm | 0:9b334a45a8ff | 223 | #define _I2C_STATE_STATE_DATA 0x00000005UL /**< Mode DATA for I2C_STATE */ |
| bogdanm | 0:9b334a45a8ff | 224 | #define _I2C_STATE_STATE_DATAACK 0x00000006UL /**< Mode DATAACK for I2C_STATE */ |
| bogdanm | 0:9b334a45a8ff | 225 | #define I2C_STATE_STATE_DEFAULT (_I2C_STATE_STATE_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATE */ |
| bogdanm | 0:9b334a45a8ff | 226 | #define I2C_STATE_STATE_IDLE (_I2C_STATE_STATE_IDLE << 5) /**< Shifted mode IDLE for I2C_STATE */ |
| bogdanm | 0:9b334a45a8ff | 227 | #define I2C_STATE_STATE_WAIT (_I2C_STATE_STATE_WAIT << 5) /**< Shifted mode WAIT for I2C_STATE */ |
| bogdanm | 0:9b334a45a8ff | 228 | #define I2C_STATE_STATE_START (_I2C_STATE_STATE_START << 5) /**< Shifted mode START for I2C_STATE */ |
| bogdanm | 0:9b334a45a8ff | 229 | #define I2C_STATE_STATE_ADDR (_I2C_STATE_STATE_ADDR << 5) /**< Shifted mode ADDR for I2C_STATE */ |
| bogdanm | 0:9b334a45a8ff | 230 | #define I2C_STATE_STATE_ADDRACK (_I2C_STATE_STATE_ADDRACK << 5) /**< Shifted mode ADDRACK for I2C_STATE */ |
| bogdanm | 0:9b334a45a8ff | 231 | #define I2C_STATE_STATE_DATA (_I2C_STATE_STATE_DATA << 5) /**< Shifted mode DATA for I2C_STATE */ |
| bogdanm | 0:9b334a45a8ff | 232 | #define I2C_STATE_STATE_DATAACK (_I2C_STATE_STATE_DATAACK << 5) /**< Shifted mode DATAACK for I2C_STATE */ |
| bogdanm | 0:9b334a45a8ff | 233 | |
| bogdanm | 0:9b334a45a8ff | 234 | /* Bit fields for I2C STATUS */ |
| bogdanm | 0:9b334a45a8ff | 235 | #define _I2C_STATUS_RESETVALUE 0x00000080UL /**< Default value for I2C_STATUS */ |
| bogdanm | 0:9b334a45a8ff | 236 | #define _I2C_STATUS_MASK 0x000001FFUL /**< Mask for I2C_STATUS */ |
| bogdanm | 0:9b334a45a8ff | 237 | #define I2C_STATUS_PSTART (0x1UL << 0) /**< Pending START */ |
| bogdanm | 0:9b334a45a8ff | 238 | #define _I2C_STATUS_PSTART_SHIFT 0 /**< Shift value for I2C_PSTART */ |
| bogdanm | 0:9b334a45a8ff | 239 | #define _I2C_STATUS_PSTART_MASK 0x1UL /**< Bit mask for I2C_PSTART */ |
| bogdanm | 0:9b334a45a8ff | 240 | #define _I2C_STATUS_PSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ |
| bogdanm | 0:9b334a45a8ff | 241 | #define I2C_STATUS_PSTART_DEFAULT (_I2C_STATUS_PSTART_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_STATUS */ |
| bogdanm | 0:9b334a45a8ff | 242 | #define I2C_STATUS_PSTOP (0x1UL << 1) /**< Pending STOP */ |
| bogdanm | 0:9b334a45a8ff | 243 | #define _I2C_STATUS_PSTOP_SHIFT 1 /**< Shift value for I2C_PSTOP */ |
| bogdanm | 0:9b334a45a8ff | 244 | #define _I2C_STATUS_PSTOP_MASK 0x2UL /**< Bit mask for I2C_PSTOP */ |
| bogdanm | 0:9b334a45a8ff | 245 | #define _I2C_STATUS_PSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ |
| bogdanm | 0:9b334a45a8ff | 246 | #define I2C_STATUS_PSTOP_DEFAULT (_I2C_STATUS_PSTOP_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_STATUS */ |
| bogdanm | 0:9b334a45a8ff | 247 | #define I2C_STATUS_PACK (0x1UL << 2) /**< Pending ACK */ |
| bogdanm | 0:9b334a45a8ff | 248 | #define _I2C_STATUS_PACK_SHIFT 2 /**< Shift value for I2C_PACK */ |
| bogdanm | 0:9b334a45a8ff | 249 | #define _I2C_STATUS_PACK_MASK 0x4UL /**< Bit mask for I2C_PACK */ |
| bogdanm | 0:9b334a45a8ff | 250 | #define _I2C_STATUS_PACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ |
| bogdanm | 0:9b334a45a8ff | 251 | #define I2C_STATUS_PACK_DEFAULT (_I2C_STATUS_PACK_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_STATUS */ |
| bogdanm | 0:9b334a45a8ff | 252 | #define I2C_STATUS_PNACK (0x1UL << 3) /**< Pending NACK */ |
| bogdanm | 0:9b334a45a8ff | 253 | #define _I2C_STATUS_PNACK_SHIFT 3 /**< Shift value for I2C_PNACK */ |
| bogdanm | 0:9b334a45a8ff | 254 | #define _I2C_STATUS_PNACK_MASK 0x8UL /**< Bit mask for I2C_PNACK */ |
| bogdanm | 0:9b334a45a8ff | 255 | #define _I2C_STATUS_PNACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ |
| bogdanm | 0:9b334a45a8ff | 256 | #define I2C_STATUS_PNACK_DEFAULT (_I2C_STATUS_PNACK_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_STATUS */ |
| bogdanm | 0:9b334a45a8ff | 257 | #define I2C_STATUS_PCONT (0x1UL << 4) /**< Pending continue */ |
| bogdanm | 0:9b334a45a8ff | 258 | #define _I2C_STATUS_PCONT_SHIFT 4 /**< Shift value for I2C_PCONT */ |
| bogdanm | 0:9b334a45a8ff | 259 | #define _I2C_STATUS_PCONT_MASK 0x10UL /**< Bit mask for I2C_PCONT */ |
| bogdanm | 0:9b334a45a8ff | 260 | #define _I2C_STATUS_PCONT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ |
| bogdanm | 0:9b334a45a8ff | 261 | #define I2C_STATUS_PCONT_DEFAULT (_I2C_STATUS_PCONT_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_STATUS */ |
| bogdanm | 0:9b334a45a8ff | 262 | #define I2C_STATUS_PABORT (0x1UL << 5) /**< Pending abort */ |
| bogdanm | 0:9b334a45a8ff | 263 | #define _I2C_STATUS_PABORT_SHIFT 5 /**< Shift value for I2C_PABORT */ |
| bogdanm | 0:9b334a45a8ff | 264 | #define _I2C_STATUS_PABORT_MASK 0x20UL /**< Bit mask for I2C_PABORT */ |
| bogdanm | 0:9b334a45a8ff | 265 | #define _I2C_STATUS_PABORT_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ |
| bogdanm | 0:9b334a45a8ff | 266 | #define I2C_STATUS_PABORT_DEFAULT (_I2C_STATUS_PABORT_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_STATUS */ |
| bogdanm | 0:9b334a45a8ff | 267 | #define I2C_STATUS_TXC (0x1UL << 6) /**< TX Complete */ |
| bogdanm | 0:9b334a45a8ff | 268 | #define _I2C_STATUS_TXC_SHIFT 6 /**< Shift value for I2C_TXC */ |
| bogdanm | 0:9b334a45a8ff | 269 | #define _I2C_STATUS_TXC_MASK 0x40UL /**< Bit mask for I2C_TXC */ |
| bogdanm | 0:9b334a45a8ff | 270 | #define _I2C_STATUS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ |
| bogdanm | 0:9b334a45a8ff | 271 | #define I2C_STATUS_TXC_DEFAULT (_I2C_STATUS_TXC_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_STATUS */ |
| bogdanm | 0:9b334a45a8ff | 272 | #define I2C_STATUS_TXBL (0x1UL << 7) /**< TX Buffer Level */ |
| bogdanm | 0:9b334a45a8ff | 273 | #define _I2C_STATUS_TXBL_SHIFT 7 /**< Shift value for I2C_TXBL */ |
| bogdanm | 0:9b334a45a8ff | 274 | #define _I2C_STATUS_TXBL_MASK 0x80UL /**< Bit mask for I2C_TXBL */ |
| bogdanm | 0:9b334a45a8ff | 275 | #define _I2C_STATUS_TXBL_DEFAULT 0x00000001UL /**< Mode DEFAULT for I2C_STATUS */ |
| bogdanm | 0:9b334a45a8ff | 276 | #define I2C_STATUS_TXBL_DEFAULT (_I2C_STATUS_TXBL_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_STATUS */ |
| bogdanm | 0:9b334a45a8ff | 277 | #define I2C_STATUS_RXDATAV (0x1UL << 8) /**< RX Data Valid */ |
| bogdanm | 0:9b334a45a8ff | 278 | #define _I2C_STATUS_RXDATAV_SHIFT 8 /**< Shift value for I2C_RXDATAV */ |
| bogdanm | 0:9b334a45a8ff | 279 | #define _I2C_STATUS_RXDATAV_MASK 0x100UL /**< Bit mask for I2C_RXDATAV */ |
| bogdanm | 0:9b334a45a8ff | 280 | #define _I2C_STATUS_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_STATUS */ |
| bogdanm | 0:9b334a45a8ff | 281 | #define I2C_STATUS_RXDATAV_DEFAULT (_I2C_STATUS_RXDATAV_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_STATUS */ |
| bogdanm | 0:9b334a45a8ff | 282 | |
| bogdanm | 0:9b334a45a8ff | 283 | /* Bit fields for I2C CLKDIV */ |
| bogdanm | 0:9b334a45a8ff | 284 | #define _I2C_CLKDIV_RESETVALUE 0x00000000UL /**< Default value for I2C_CLKDIV */ |
| bogdanm | 0:9b334a45a8ff | 285 | #define _I2C_CLKDIV_MASK 0x000001FFUL /**< Mask for I2C_CLKDIV */ |
| bogdanm | 0:9b334a45a8ff | 286 | #define _I2C_CLKDIV_DIV_SHIFT 0 /**< Shift value for I2C_DIV */ |
| bogdanm | 0:9b334a45a8ff | 287 | #define _I2C_CLKDIV_DIV_MASK 0x1FFUL /**< Bit mask for I2C_DIV */ |
| bogdanm | 0:9b334a45a8ff | 288 | #define _I2C_CLKDIV_DIV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_CLKDIV */ |
| bogdanm | 0:9b334a45a8ff | 289 | #define I2C_CLKDIV_DIV_DEFAULT (_I2C_CLKDIV_DIV_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_CLKDIV */ |
| bogdanm | 0:9b334a45a8ff | 290 | |
| bogdanm | 0:9b334a45a8ff | 291 | /* Bit fields for I2C SADDR */ |
| bogdanm | 0:9b334a45a8ff | 292 | #define _I2C_SADDR_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDR */ |
| bogdanm | 0:9b334a45a8ff | 293 | #define _I2C_SADDR_MASK 0x000000FEUL /**< Mask for I2C_SADDR */ |
| bogdanm | 0:9b334a45a8ff | 294 | #define _I2C_SADDR_ADDR_SHIFT 1 /**< Shift value for I2C_ADDR */ |
| bogdanm | 0:9b334a45a8ff | 295 | #define _I2C_SADDR_ADDR_MASK 0xFEUL /**< Bit mask for I2C_ADDR */ |
| bogdanm | 0:9b334a45a8ff | 296 | #define _I2C_SADDR_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDR */ |
| bogdanm | 0:9b334a45a8ff | 297 | #define I2C_SADDR_ADDR_DEFAULT (_I2C_SADDR_ADDR_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDR */ |
| bogdanm | 0:9b334a45a8ff | 298 | |
| bogdanm | 0:9b334a45a8ff | 299 | /* Bit fields for I2C SADDRMASK */ |
| bogdanm | 0:9b334a45a8ff | 300 | #define _I2C_SADDRMASK_RESETVALUE 0x00000000UL /**< Default value for I2C_SADDRMASK */ |
| bogdanm | 0:9b334a45a8ff | 301 | #define _I2C_SADDRMASK_MASK 0x000000FEUL /**< Mask for I2C_SADDRMASK */ |
| bogdanm | 0:9b334a45a8ff | 302 | #define _I2C_SADDRMASK_MASK_SHIFT 1 /**< Shift value for I2C_MASK */ |
| bogdanm | 0:9b334a45a8ff | 303 | #define _I2C_SADDRMASK_MASK_MASK 0xFEUL /**< Bit mask for I2C_MASK */ |
| bogdanm | 0:9b334a45a8ff | 304 | #define _I2C_SADDRMASK_MASK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_SADDRMASK */ |
| bogdanm | 0:9b334a45a8ff | 305 | #define I2C_SADDRMASK_MASK_DEFAULT (_I2C_SADDRMASK_MASK_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_SADDRMASK */ |
| bogdanm | 0:9b334a45a8ff | 306 | |
| bogdanm | 0:9b334a45a8ff | 307 | /* Bit fields for I2C RXDATA */ |
| bogdanm | 0:9b334a45a8ff | 308 | #define _I2C_RXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATA */ |
| bogdanm | 0:9b334a45a8ff | 309 | #define _I2C_RXDATA_MASK 0x000000FFUL /**< Mask for I2C_RXDATA */ |
| bogdanm | 0:9b334a45a8ff | 310 | #define _I2C_RXDATA_RXDATA_SHIFT 0 /**< Shift value for I2C_RXDATA */ |
| bogdanm | 0:9b334a45a8ff | 311 | #define _I2C_RXDATA_RXDATA_MASK 0xFFUL /**< Bit mask for I2C_RXDATA */ |
| bogdanm | 0:9b334a45a8ff | 312 | #define _I2C_RXDATA_RXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATA */ |
| bogdanm | 0:9b334a45a8ff | 313 | #define I2C_RXDATA_RXDATA_DEFAULT (_I2C_RXDATA_RXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATA */ |
| bogdanm | 0:9b334a45a8ff | 314 | |
| bogdanm | 0:9b334a45a8ff | 315 | /* Bit fields for I2C RXDATAP */ |
| bogdanm | 0:9b334a45a8ff | 316 | #define _I2C_RXDATAP_RESETVALUE 0x00000000UL /**< Default value for I2C_RXDATAP */ |
| bogdanm | 0:9b334a45a8ff | 317 | #define _I2C_RXDATAP_MASK 0x000000FFUL /**< Mask for I2C_RXDATAP */ |
| bogdanm | 0:9b334a45a8ff | 318 | #define _I2C_RXDATAP_RXDATAP_SHIFT 0 /**< Shift value for I2C_RXDATAP */ |
| bogdanm | 0:9b334a45a8ff | 319 | #define _I2C_RXDATAP_RXDATAP_MASK 0xFFUL /**< Bit mask for I2C_RXDATAP */ |
| bogdanm | 0:9b334a45a8ff | 320 | #define _I2C_RXDATAP_RXDATAP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_RXDATAP */ |
| bogdanm | 0:9b334a45a8ff | 321 | #define I2C_RXDATAP_RXDATAP_DEFAULT (_I2C_RXDATAP_RXDATAP_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_RXDATAP */ |
| bogdanm | 0:9b334a45a8ff | 322 | |
| bogdanm | 0:9b334a45a8ff | 323 | /* Bit fields for I2C TXDATA */ |
| bogdanm | 0:9b334a45a8ff | 324 | #define _I2C_TXDATA_RESETVALUE 0x00000000UL /**< Default value for I2C_TXDATA */ |
| bogdanm | 0:9b334a45a8ff | 325 | #define _I2C_TXDATA_MASK 0x000000FFUL /**< Mask for I2C_TXDATA */ |
| bogdanm | 0:9b334a45a8ff | 326 | #define _I2C_TXDATA_TXDATA_SHIFT 0 /**< Shift value for I2C_TXDATA */ |
| bogdanm | 0:9b334a45a8ff | 327 | #define _I2C_TXDATA_TXDATA_MASK 0xFFUL /**< Bit mask for I2C_TXDATA */ |
| bogdanm | 0:9b334a45a8ff | 328 | #define _I2C_TXDATA_TXDATA_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_TXDATA */ |
| bogdanm | 0:9b334a45a8ff | 329 | #define I2C_TXDATA_TXDATA_DEFAULT (_I2C_TXDATA_TXDATA_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_TXDATA */ |
| bogdanm | 0:9b334a45a8ff | 330 | |
| bogdanm | 0:9b334a45a8ff | 331 | /* Bit fields for I2C IF */ |
| bogdanm | 0:9b334a45a8ff | 332 | #define _I2C_IF_RESETVALUE 0x00000010UL /**< Default value for I2C_IF */ |
| bogdanm | 0:9b334a45a8ff | 333 | #define _I2C_IF_MASK 0x0001FFFFUL /**< Mask for I2C_IF */ |
| bogdanm | 0:9b334a45a8ff | 334 | #define I2C_IF_START (0x1UL << 0) /**< START condition Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 335 | #define _I2C_IF_START_SHIFT 0 /**< Shift value for I2C_START */ |
| bogdanm | 0:9b334a45a8ff | 336 | #define _I2C_IF_START_MASK 0x1UL /**< Bit mask for I2C_START */ |
| bogdanm | 0:9b334a45a8ff | 337 | #define _I2C_IF_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ |
| bogdanm | 0:9b334a45a8ff | 338 | #define I2C_IF_START_DEFAULT (_I2C_IF_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IF */ |
| bogdanm | 0:9b334a45a8ff | 339 | #define I2C_IF_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 340 | #define _I2C_IF_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ |
| bogdanm | 0:9b334a45a8ff | 341 | #define _I2C_IF_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ |
| bogdanm | 0:9b334a45a8ff | 342 | #define _I2C_IF_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ |
| bogdanm | 0:9b334a45a8ff | 343 | #define I2C_IF_RSTART_DEFAULT (_I2C_IF_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IF */ |
| bogdanm | 0:9b334a45a8ff | 344 | #define I2C_IF_ADDR (0x1UL << 2) /**< Address Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 345 | #define _I2C_IF_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ |
| bogdanm | 0:9b334a45a8ff | 346 | #define _I2C_IF_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ |
| bogdanm | 0:9b334a45a8ff | 347 | #define _I2C_IF_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ |
| bogdanm | 0:9b334a45a8ff | 348 | #define I2C_IF_ADDR_DEFAULT (_I2C_IF_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IF */ |
| bogdanm | 0:9b334a45a8ff | 349 | #define I2C_IF_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 350 | #define _I2C_IF_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ |
| bogdanm | 0:9b334a45a8ff | 351 | #define _I2C_IF_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ |
| bogdanm | 0:9b334a45a8ff | 352 | #define _I2C_IF_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ |
| bogdanm | 0:9b334a45a8ff | 353 | #define I2C_IF_TXC_DEFAULT (_I2C_IF_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IF */ |
| bogdanm | 0:9b334a45a8ff | 354 | #define I2C_IF_TXBL (0x1UL << 4) /**< Transmit Buffer Level Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 355 | #define _I2C_IF_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */ |
| bogdanm | 0:9b334a45a8ff | 356 | #define _I2C_IF_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */ |
| bogdanm | 0:9b334a45a8ff | 357 | #define _I2C_IF_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ |
| bogdanm | 0:9b334a45a8ff | 358 | #define I2C_IF_TXBL_DEFAULT (_I2C_IF_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IF */ |
| bogdanm | 0:9b334a45a8ff | 359 | #define I2C_IF_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 360 | #define _I2C_IF_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */ |
| bogdanm | 0:9b334a45a8ff | 361 | #define _I2C_IF_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */ |
| bogdanm | 0:9b334a45a8ff | 362 | #define _I2C_IF_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ |
| bogdanm | 0:9b334a45a8ff | 363 | #define I2C_IF_RXDATAV_DEFAULT (_I2C_IF_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IF */ |
| bogdanm | 0:9b334a45a8ff | 364 | #define I2C_IF_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 365 | #define _I2C_IF_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ |
| bogdanm | 0:9b334a45a8ff | 366 | #define _I2C_IF_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ |
| bogdanm | 0:9b334a45a8ff | 367 | #define _I2C_IF_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ |
| bogdanm | 0:9b334a45a8ff | 368 | #define I2C_IF_ACK_DEFAULT (_I2C_IF_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IF */ |
| bogdanm | 0:9b334a45a8ff | 369 | #define I2C_IF_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 370 | #define _I2C_IF_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ |
| bogdanm | 0:9b334a45a8ff | 371 | #define _I2C_IF_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ |
| bogdanm | 0:9b334a45a8ff | 372 | #define _I2C_IF_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ |
| bogdanm | 0:9b334a45a8ff | 373 | #define I2C_IF_NACK_DEFAULT (_I2C_IF_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IF */ |
| bogdanm | 0:9b334a45a8ff | 374 | #define I2C_IF_MSTOP (0x1UL << 8) /**< Master STOP Condition Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 375 | #define _I2C_IF_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ |
| bogdanm | 0:9b334a45a8ff | 376 | #define _I2C_IF_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ |
| bogdanm | 0:9b334a45a8ff | 377 | #define _I2C_IF_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ |
| bogdanm | 0:9b334a45a8ff | 378 | #define I2C_IF_MSTOP_DEFAULT (_I2C_IF_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IF */ |
| bogdanm | 0:9b334a45a8ff | 379 | #define I2C_IF_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 380 | #define _I2C_IF_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ |
| bogdanm | 0:9b334a45a8ff | 381 | #define _I2C_IF_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ |
| bogdanm | 0:9b334a45a8ff | 382 | #define _I2C_IF_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ |
| bogdanm | 0:9b334a45a8ff | 383 | #define I2C_IF_ARBLOST_DEFAULT (_I2C_IF_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IF */ |
| bogdanm | 0:9b334a45a8ff | 384 | #define I2C_IF_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 385 | #define _I2C_IF_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ |
| bogdanm | 0:9b334a45a8ff | 386 | #define _I2C_IF_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ |
| bogdanm | 0:9b334a45a8ff | 387 | #define _I2C_IF_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ |
| bogdanm | 0:9b334a45a8ff | 388 | #define I2C_IF_BUSERR_DEFAULT (_I2C_IF_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IF */ |
| bogdanm | 0:9b334a45a8ff | 389 | #define I2C_IF_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 390 | #define _I2C_IF_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ |
| bogdanm | 0:9b334a45a8ff | 391 | #define _I2C_IF_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ |
| bogdanm | 0:9b334a45a8ff | 392 | #define _I2C_IF_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ |
| bogdanm | 0:9b334a45a8ff | 393 | #define I2C_IF_BUSHOLD_DEFAULT (_I2C_IF_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IF */ |
| bogdanm | 0:9b334a45a8ff | 394 | #define I2C_IF_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 395 | #define _I2C_IF_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ |
| bogdanm | 0:9b334a45a8ff | 396 | #define _I2C_IF_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ |
| bogdanm | 0:9b334a45a8ff | 397 | #define _I2C_IF_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ |
| bogdanm | 0:9b334a45a8ff | 398 | #define I2C_IF_TXOF_DEFAULT (_I2C_IF_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IF */ |
| bogdanm | 0:9b334a45a8ff | 399 | #define I2C_IF_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 400 | #define _I2C_IF_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ |
| bogdanm | 0:9b334a45a8ff | 401 | #define _I2C_IF_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ |
| bogdanm | 0:9b334a45a8ff | 402 | #define _I2C_IF_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ |
| bogdanm | 0:9b334a45a8ff | 403 | #define I2C_IF_RXUF_DEFAULT (_I2C_IF_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IF */ |
| bogdanm | 0:9b334a45a8ff | 404 | #define I2C_IF_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 405 | #define _I2C_IF_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ |
| bogdanm | 0:9b334a45a8ff | 406 | #define _I2C_IF_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ |
| bogdanm | 0:9b334a45a8ff | 407 | #define _I2C_IF_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ |
| bogdanm | 0:9b334a45a8ff | 408 | #define I2C_IF_BITO_DEFAULT (_I2C_IF_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IF */ |
| bogdanm | 0:9b334a45a8ff | 409 | #define I2C_IF_CLTO (0x1UL << 15) /**< Clock Low Timeout Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 410 | #define _I2C_IF_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ |
| bogdanm | 0:9b334a45a8ff | 411 | #define _I2C_IF_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ |
| bogdanm | 0:9b334a45a8ff | 412 | #define _I2C_IF_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ |
| bogdanm | 0:9b334a45a8ff | 413 | #define I2C_IF_CLTO_DEFAULT (_I2C_IF_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IF */ |
| bogdanm | 0:9b334a45a8ff | 414 | #define I2C_IF_SSTOP (0x1UL << 16) /**< Slave STOP condition Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 415 | #define _I2C_IF_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ |
| bogdanm | 0:9b334a45a8ff | 416 | #define _I2C_IF_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ |
| bogdanm | 0:9b334a45a8ff | 417 | #define _I2C_IF_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IF */ |
| bogdanm | 0:9b334a45a8ff | 418 | #define I2C_IF_SSTOP_DEFAULT (_I2C_IF_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IF */ |
| bogdanm | 0:9b334a45a8ff | 419 | |
| bogdanm | 0:9b334a45a8ff | 420 | /* Bit fields for I2C IFS */ |
| bogdanm | 0:9b334a45a8ff | 421 | #define _I2C_IFS_RESETVALUE 0x00000000UL /**< Default value for I2C_IFS */ |
| bogdanm | 0:9b334a45a8ff | 422 | #define _I2C_IFS_MASK 0x0001FFCFUL /**< Mask for I2C_IFS */ |
| bogdanm | 0:9b334a45a8ff | 423 | #define I2C_IFS_START (0x1UL << 0) /**< Set START Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 424 | #define _I2C_IFS_START_SHIFT 0 /**< Shift value for I2C_START */ |
| bogdanm | 0:9b334a45a8ff | 425 | #define _I2C_IFS_START_MASK 0x1UL /**< Bit mask for I2C_START */ |
| bogdanm | 0:9b334a45a8ff | 426 | #define _I2C_IFS_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ |
| bogdanm | 0:9b334a45a8ff | 427 | #define I2C_IFS_START_DEFAULT (_I2C_IFS_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IFS */ |
| bogdanm | 0:9b334a45a8ff | 428 | #define I2C_IFS_RSTART (0x1UL << 1) /**< Set Repeated START Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 429 | #define _I2C_IFS_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ |
| bogdanm | 0:9b334a45a8ff | 430 | #define _I2C_IFS_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ |
| bogdanm | 0:9b334a45a8ff | 431 | #define _I2C_IFS_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ |
| bogdanm | 0:9b334a45a8ff | 432 | #define I2C_IFS_RSTART_DEFAULT (_I2C_IFS_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IFS */ |
| bogdanm | 0:9b334a45a8ff | 433 | #define I2C_IFS_ADDR (0x1UL << 2) /**< Set Address Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 434 | #define _I2C_IFS_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ |
| bogdanm | 0:9b334a45a8ff | 435 | #define _I2C_IFS_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ |
| bogdanm | 0:9b334a45a8ff | 436 | #define _I2C_IFS_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ |
| bogdanm | 0:9b334a45a8ff | 437 | #define I2C_IFS_ADDR_DEFAULT (_I2C_IFS_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IFS */ |
| bogdanm | 0:9b334a45a8ff | 438 | #define I2C_IFS_TXC (0x1UL << 3) /**< Set Transfer Completed Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 439 | #define _I2C_IFS_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ |
| bogdanm | 0:9b334a45a8ff | 440 | #define _I2C_IFS_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ |
| bogdanm | 0:9b334a45a8ff | 441 | #define _I2C_IFS_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ |
| bogdanm | 0:9b334a45a8ff | 442 | #define I2C_IFS_TXC_DEFAULT (_I2C_IFS_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IFS */ |
| bogdanm | 0:9b334a45a8ff | 443 | #define I2C_IFS_ACK (0x1UL << 6) /**< Set Acknowledge Received Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 444 | #define _I2C_IFS_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ |
| bogdanm | 0:9b334a45a8ff | 445 | #define _I2C_IFS_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ |
| bogdanm | 0:9b334a45a8ff | 446 | #define _I2C_IFS_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ |
| bogdanm | 0:9b334a45a8ff | 447 | #define I2C_IFS_ACK_DEFAULT (_I2C_IFS_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IFS */ |
| bogdanm | 0:9b334a45a8ff | 448 | #define I2C_IFS_NACK (0x1UL << 7) /**< Set Not Acknowledge Received Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 449 | #define _I2C_IFS_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ |
| bogdanm | 0:9b334a45a8ff | 450 | #define _I2C_IFS_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ |
| bogdanm | 0:9b334a45a8ff | 451 | #define _I2C_IFS_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ |
| bogdanm | 0:9b334a45a8ff | 452 | #define I2C_IFS_NACK_DEFAULT (_I2C_IFS_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IFS */ |
| bogdanm | 0:9b334a45a8ff | 453 | #define I2C_IFS_MSTOP (0x1UL << 8) /**< Set MSTOP Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 454 | #define _I2C_IFS_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ |
| bogdanm | 0:9b334a45a8ff | 455 | #define _I2C_IFS_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ |
| bogdanm | 0:9b334a45a8ff | 456 | #define _I2C_IFS_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ |
| bogdanm | 0:9b334a45a8ff | 457 | #define I2C_IFS_MSTOP_DEFAULT (_I2C_IFS_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IFS */ |
| bogdanm | 0:9b334a45a8ff | 458 | #define I2C_IFS_ARBLOST (0x1UL << 9) /**< Set Arbitration Lost Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 459 | #define _I2C_IFS_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ |
| bogdanm | 0:9b334a45a8ff | 460 | #define _I2C_IFS_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ |
| bogdanm | 0:9b334a45a8ff | 461 | #define _I2C_IFS_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ |
| bogdanm | 0:9b334a45a8ff | 462 | #define I2C_IFS_ARBLOST_DEFAULT (_I2C_IFS_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IFS */ |
| bogdanm | 0:9b334a45a8ff | 463 | #define I2C_IFS_BUSERR (0x1UL << 10) /**< Set Bus Error Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 464 | #define _I2C_IFS_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ |
| bogdanm | 0:9b334a45a8ff | 465 | #define _I2C_IFS_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ |
| bogdanm | 0:9b334a45a8ff | 466 | #define _I2C_IFS_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ |
| bogdanm | 0:9b334a45a8ff | 467 | #define I2C_IFS_BUSERR_DEFAULT (_I2C_IFS_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IFS */ |
| bogdanm | 0:9b334a45a8ff | 468 | #define I2C_IFS_BUSHOLD (0x1UL << 11) /**< Set Bus Held Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 469 | #define _I2C_IFS_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ |
| bogdanm | 0:9b334a45a8ff | 470 | #define _I2C_IFS_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ |
| bogdanm | 0:9b334a45a8ff | 471 | #define _I2C_IFS_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ |
| bogdanm | 0:9b334a45a8ff | 472 | #define I2C_IFS_BUSHOLD_DEFAULT (_I2C_IFS_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IFS */ |
| bogdanm | 0:9b334a45a8ff | 473 | #define I2C_IFS_TXOF (0x1UL << 12) /**< Set Transmit Buffer Overflow Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 474 | #define _I2C_IFS_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ |
| bogdanm | 0:9b334a45a8ff | 475 | #define _I2C_IFS_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ |
| bogdanm | 0:9b334a45a8ff | 476 | #define _I2C_IFS_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ |
| bogdanm | 0:9b334a45a8ff | 477 | #define I2C_IFS_TXOF_DEFAULT (_I2C_IFS_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IFS */ |
| bogdanm | 0:9b334a45a8ff | 478 | #define I2C_IFS_RXUF (0x1UL << 13) /**< Set Receive Buffer Underflow Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 479 | #define _I2C_IFS_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ |
| bogdanm | 0:9b334a45a8ff | 480 | #define _I2C_IFS_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ |
| bogdanm | 0:9b334a45a8ff | 481 | #define _I2C_IFS_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ |
| bogdanm | 0:9b334a45a8ff | 482 | #define I2C_IFS_RXUF_DEFAULT (_I2C_IFS_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IFS */ |
| bogdanm | 0:9b334a45a8ff | 483 | #define I2C_IFS_BITO (0x1UL << 14) /**< Set Bus Idle Timeout Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 484 | #define _I2C_IFS_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ |
| bogdanm | 0:9b334a45a8ff | 485 | #define _I2C_IFS_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ |
| bogdanm | 0:9b334a45a8ff | 486 | #define _I2C_IFS_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ |
| bogdanm | 0:9b334a45a8ff | 487 | #define I2C_IFS_BITO_DEFAULT (_I2C_IFS_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IFS */ |
| bogdanm | 0:9b334a45a8ff | 488 | #define I2C_IFS_CLTO (0x1UL << 15) /**< Set Clock Low Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 489 | #define _I2C_IFS_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ |
| bogdanm | 0:9b334a45a8ff | 490 | #define _I2C_IFS_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ |
| bogdanm | 0:9b334a45a8ff | 491 | #define _I2C_IFS_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ |
| bogdanm | 0:9b334a45a8ff | 492 | #define I2C_IFS_CLTO_DEFAULT (_I2C_IFS_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IFS */ |
| bogdanm | 0:9b334a45a8ff | 493 | #define I2C_IFS_SSTOP (0x1UL << 16) /**< Set SSTOP Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 494 | #define _I2C_IFS_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ |
| bogdanm | 0:9b334a45a8ff | 495 | #define _I2C_IFS_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ |
| bogdanm | 0:9b334a45a8ff | 496 | #define _I2C_IFS_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFS */ |
| bogdanm | 0:9b334a45a8ff | 497 | #define I2C_IFS_SSTOP_DEFAULT (_I2C_IFS_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IFS */ |
| bogdanm | 0:9b334a45a8ff | 498 | |
| bogdanm | 0:9b334a45a8ff | 499 | /* Bit fields for I2C IFC */ |
| bogdanm | 0:9b334a45a8ff | 500 | #define _I2C_IFC_RESETVALUE 0x00000000UL /**< Default value for I2C_IFC */ |
| bogdanm | 0:9b334a45a8ff | 501 | #define _I2C_IFC_MASK 0x0001FFCFUL /**< Mask for I2C_IFC */ |
| bogdanm | 0:9b334a45a8ff | 502 | #define I2C_IFC_START (0x1UL << 0) /**< Clear START Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 503 | #define _I2C_IFC_START_SHIFT 0 /**< Shift value for I2C_START */ |
| bogdanm | 0:9b334a45a8ff | 504 | #define _I2C_IFC_START_MASK 0x1UL /**< Bit mask for I2C_START */ |
| bogdanm | 0:9b334a45a8ff | 505 | #define _I2C_IFC_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ |
| bogdanm | 0:9b334a45a8ff | 506 | #define I2C_IFC_START_DEFAULT (_I2C_IFC_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IFC */ |
| bogdanm | 0:9b334a45a8ff | 507 | #define I2C_IFC_RSTART (0x1UL << 1) /**< Clear Repeated START Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 508 | #define _I2C_IFC_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ |
| bogdanm | 0:9b334a45a8ff | 509 | #define _I2C_IFC_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ |
| bogdanm | 0:9b334a45a8ff | 510 | #define _I2C_IFC_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ |
| bogdanm | 0:9b334a45a8ff | 511 | #define I2C_IFC_RSTART_DEFAULT (_I2C_IFC_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IFC */ |
| bogdanm | 0:9b334a45a8ff | 512 | #define I2C_IFC_ADDR (0x1UL << 2) /**< Clear Address Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 513 | #define _I2C_IFC_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ |
| bogdanm | 0:9b334a45a8ff | 514 | #define _I2C_IFC_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ |
| bogdanm | 0:9b334a45a8ff | 515 | #define _I2C_IFC_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ |
| bogdanm | 0:9b334a45a8ff | 516 | #define I2C_IFC_ADDR_DEFAULT (_I2C_IFC_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IFC */ |
| bogdanm | 0:9b334a45a8ff | 517 | #define I2C_IFC_TXC (0x1UL << 3) /**< Clear Transfer Completed Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 518 | #define _I2C_IFC_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ |
| bogdanm | 0:9b334a45a8ff | 519 | #define _I2C_IFC_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ |
| bogdanm | 0:9b334a45a8ff | 520 | #define _I2C_IFC_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ |
| bogdanm | 0:9b334a45a8ff | 521 | #define I2C_IFC_TXC_DEFAULT (_I2C_IFC_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IFC */ |
| bogdanm | 0:9b334a45a8ff | 522 | #define I2C_IFC_ACK (0x1UL << 6) /**< Clear Acknowledge Received Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 523 | #define _I2C_IFC_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ |
| bogdanm | 0:9b334a45a8ff | 524 | #define _I2C_IFC_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ |
| bogdanm | 0:9b334a45a8ff | 525 | #define _I2C_IFC_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ |
| bogdanm | 0:9b334a45a8ff | 526 | #define I2C_IFC_ACK_DEFAULT (_I2C_IFC_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IFC */ |
| bogdanm | 0:9b334a45a8ff | 527 | #define I2C_IFC_NACK (0x1UL << 7) /**< Clear Not Acknowledge Received Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 528 | #define _I2C_IFC_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ |
| bogdanm | 0:9b334a45a8ff | 529 | #define _I2C_IFC_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ |
| bogdanm | 0:9b334a45a8ff | 530 | #define _I2C_IFC_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ |
| bogdanm | 0:9b334a45a8ff | 531 | #define I2C_IFC_NACK_DEFAULT (_I2C_IFC_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IFC */ |
| bogdanm | 0:9b334a45a8ff | 532 | #define I2C_IFC_MSTOP (0x1UL << 8) /**< Clear MSTOP Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 533 | #define _I2C_IFC_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ |
| bogdanm | 0:9b334a45a8ff | 534 | #define _I2C_IFC_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ |
| bogdanm | 0:9b334a45a8ff | 535 | #define _I2C_IFC_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ |
| bogdanm | 0:9b334a45a8ff | 536 | #define I2C_IFC_MSTOP_DEFAULT (_I2C_IFC_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IFC */ |
| bogdanm | 0:9b334a45a8ff | 537 | #define I2C_IFC_ARBLOST (0x1UL << 9) /**< Clear Arbitration Lost Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 538 | #define _I2C_IFC_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ |
| bogdanm | 0:9b334a45a8ff | 539 | #define _I2C_IFC_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ |
| bogdanm | 0:9b334a45a8ff | 540 | #define _I2C_IFC_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ |
| bogdanm | 0:9b334a45a8ff | 541 | #define I2C_IFC_ARBLOST_DEFAULT (_I2C_IFC_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IFC */ |
| bogdanm | 0:9b334a45a8ff | 542 | #define I2C_IFC_BUSERR (0x1UL << 10) /**< Clear Bus Error Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 543 | #define _I2C_IFC_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ |
| bogdanm | 0:9b334a45a8ff | 544 | #define _I2C_IFC_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ |
| bogdanm | 0:9b334a45a8ff | 545 | #define _I2C_IFC_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ |
| bogdanm | 0:9b334a45a8ff | 546 | #define I2C_IFC_BUSERR_DEFAULT (_I2C_IFC_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IFC */ |
| bogdanm | 0:9b334a45a8ff | 547 | #define I2C_IFC_BUSHOLD (0x1UL << 11) /**< Clear Bus Held Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 548 | #define _I2C_IFC_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ |
| bogdanm | 0:9b334a45a8ff | 549 | #define _I2C_IFC_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ |
| bogdanm | 0:9b334a45a8ff | 550 | #define _I2C_IFC_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ |
| bogdanm | 0:9b334a45a8ff | 551 | #define I2C_IFC_BUSHOLD_DEFAULT (_I2C_IFC_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IFC */ |
| bogdanm | 0:9b334a45a8ff | 552 | #define I2C_IFC_TXOF (0x1UL << 12) /**< Clear Transmit Buffer Overflow Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 553 | #define _I2C_IFC_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ |
| bogdanm | 0:9b334a45a8ff | 554 | #define _I2C_IFC_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ |
| bogdanm | 0:9b334a45a8ff | 555 | #define _I2C_IFC_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ |
| bogdanm | 0:9b334a45a8ff | 556 | #define I2C_IFC_TXOF_DEFAULT (_I2C_IFC_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IFC */ |
| bogdanm | 0:9b334a45a8ff | 557 | #define I2C_IFC_RXUF (0x1UL << 13) /**< Clear Receive Buffer Underflow Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 558 | #define _I2C_IFC_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ |
| bogdanm | 0:9b334a45a8ff | 559 | #define _I2C_IFC_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ |
| bogdanm | 0:9b334a45a8ff | 560 | #define _I2C_IFC_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ |
| bogdanm | 0:9b334a45a8ff | 561 | #define I2C_IFC_RXUF_DEFAULT (_I2C_IFC_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IFC */ |
| bogdanm | 0:9b334a45a8ff | 562 | #define I2C_IFC_BITO (0x1UL << 14) /**< Clear Bus Idle Timeout Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 563 | #define _I2C_IFC_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ |
| bogdanm | 0:9b334a45a8ff | 564 | #define _I2C_IFC_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ |
| bogdanm | 0:9b334a45a8ff | 565 | #define _I2C_IFC_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ |
| bogdanm | 0:9b334a45a8ff | 566 | #define I2C_IFC_BITO_DEFAULT (_I2C_IFC_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IFC */ |
| bogdanm | 0:9b334a45a8ff | 567 | #define I2C_IFC_CLTO (0x1UL << 15) /**< Clear Clock Low Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 568 | #define _I2C_IFC_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ |
| bogdanm | 0:9b334a45a8ff | 569 | #define _I2C_IFC_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ |
| bogdanm | 0:9b334a45a8ff | 570 | #define _I2C_IFC_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ |
| bogdanm | 0:9b334a45a8ff | 571 | #define I2C_IFC_CLTO_DEFAULT (_I2C_IFC_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IFC */ |
| bogdanm | 0:9b334a45a8ff | 572 | #define I2C_IFC_SSTOP (0x1UL << 16) /**< Clear SSTOP Interrupt Flag */ |
| bogdanm | 0:9b334a45a8ff | 573 | #define _I2C_IFC_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ |
| bogdanm | 0:9b334a45a8ff | 574 | #define _I2C_IFC_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ |
| bogdanm | 0:9b334a45a8ff | 575 | #define _I2C_IFC_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IFC */ |
| bogdanm | 0:9b334a45a8ff | 576 | #define I2C_IFC_SSTOP_DEFAULT (_I2C_IFC_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IFC */ |
| bogdanm | 0:9b334a45a8ff | 577 | |
| bogdanm | 0:9b334a45a8ff | 578 | /* Bit fields for I2C IEN */ |
| bogdanm | 0:9b334a45a8ff | 579 | #define _I2C_IEN_RESETVALUE 0x00000000UL /**< Default value for I2C_IEN */ |
| bogdanm | 0:9b334a45a8ff | 580 | #define _I2C_IEN_MASK 0x0001FFFFUL /**< Mask for I2C_IEN */ |
| bogdanm | 0:9b334a45a8ff | 581 | #define I2C_IEN_START (0x1UL << 0) /**< START Condition Interrupt Enable */ |
| bogdanm | 0:9b334a45a8ff | 582 | #define _I2C_IEN_START_SHIFT 0 /**< Shift value for I2C_START */ |
| bogdanm | 0:9b334a45a8ff | 583 | #define _I2C_IEN_START_MASK 0x1UL /**< Bit mask for I2C_START */ |
| bogdanm | 0:9b334a45a8ff | 584 | #define _I2C_IEN_START_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ |
| bogdanm | 0:9b334a45a8ff | 585 | #define I2C_IEN_START_DEFAULT (_I2C_IEN_START_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_IEN */ |
| bogdanm | 0:9b334a45a8ff | 586 | #define I2C_IEN_RSTART (0x1UL << 1) /**< Repeated START condition Interrupt Enable */ |
| bogdanm | 0:9b334a45a8ff | 587 | #define _I2C_IEN_RSTART_SHIFT 1 /**< Shift value for I2C_RSTART */ |
| bogdanm | 0:9b334a45a8ff | 588 | #define _I2C_IEN_RSTART_MASK 0x2UL /**< Bit mask for I2C_RSTART */ |
| bogdanm | 0:9b334a45a8ff | 589 | #define _I2C_IEN_RSTART_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ |
| bogdanm | 0:9b334a45a8ff | 590 | #define I2C_IEN_RSTART_DEFAULT (_I2C_IEN_RSTART_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_IEN */ |
| bogdanm | 0:9b334a45a8ff | 591 | #define I2C_IEN_ADDR (0x1UL << 2) /**< Address Interrupt Enable */ |
| bogdanm | 0:9b334a45a8ff | 592 | #define _I2C_IEN_ADDR_SHIFT 2 /**< Shift value for I2C_ADDR */ |
| bogdanm | 0:9b334a45a8ff | 593 | #define _I2C_IEN_ADDR_MASK 0x4UL /**< Bit mask for I2C_ADDR */ |
| bogdanm | 0:9b334a45a8ff | 594 | #define _I2C_IEN_ADDR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ |
| bogdanm | 0:9b334a45a8ff | 595 | #define I2C_IEN_ADDR_DEFAULT (_I2C_IEN_ADDR_DEFAULT << 2) /**< Shifted mode DEFAULT for I2C_IEN */ |
| bogdanm | 0:9b334a45a8ff | 596 | #define I2C_IEN_TXC (0x1UL << 3) /**< Transfer Completed Interrupt Enable */ |
| bogdanm | 0:9b334a45a8ff | 597 | #define _I2C_IEN_TXC_SHIFT 3 /**< Shift value for I2C_TXC */ |
| bogdanm | 0:9b334a45a8ff | 598 | #define _I2C_IEN_TXC_MASK 0x8UL /**< Bit mask for I2C_TXC */ |
| bogdanm | 0:9b334a45a8ff | 599 | #define _I2C_IEN_TXC_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ |
| bogdanm | 0:9b334a45a8ff | 600 | #define I2C_IEN_TXC_DEFAULT (_I2C_IEN_TXC_DEFAULT << 3) /**< Shifted mode DEFAULT for I2C_IEN */ |
| bogdanm | 0:9b334a45a8ff | 601 | #define I2C_IEN_TXBL (0x1UL << 4) /**< Transmit Buffer level Interrupt Enable */ |
| bogdanm | 0:9b334a45a8ff | 602 | #define _I2C_IEN_TXBL_SHIFT 4 /**< Shift value for I2C_TXBL */ |
| bogdanm | 0:9b334a45a8ff | 603 | #define _I2C_IEN_TXBL_MASK 0x10UL /**< Bit mask for I2C_TXBL */ |
| bogdanm | 0:9b334a45a8ff | 604 | #define _I2C_IEN_TXBL_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ |
| bogdanm | 0:9b334a45a8ff | 605 | #define I2C_IEN_TXBL_DEFAULT (_I2C_IEN_TXBL_DEFAULT << 4) /**< Shifted mode DEFAULT for I2C_IEN */ |
| bogdanm | 0:9b334a45a8ff | 606 | #define I2C_IEN_RXDATAV (0x1UL << 5) /**< Receive Data Valid Interrupt Enable */ |
| bogdanm | 0:9b334a45a8ff | 607 | #define _I2C_IEN_RXDATAV_SHIFT 5 /**< Shift value for I2C_RXDATAV */ |
| bogdanm | 0:9b334a45a8ff | 608 | #define _I2C_IEN_RXDATAV_MASK 0x20UL /**< Bit mask for I2C_RXDATAV */ |
| bogdanm | 0:9b334a45a8ff | 609 | #define _I2C_IEN_RXDATAV_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ |
| bogdanm | 0:9b334a45a8ff | 610 | #define I2C_IEN_RXDATAV_DEFAULT (_I2C_IEN_RXDATAV_DEFAULT << 5) /**< Shifted mode DEFAULT for I2C_IEN */ |
| bogdanm | 0:9b334a45a8ff | 611 | #define I2C_IEN_ACK (0x1UL << 6) /**< Acknowledge Received Interrupt Enable */ |
| bogdanm | 0:9b334a45a8ff | 612 | #define _I2C_IEN_ACK_SHIFT 6 /**< Shift value for I2C_ACK */ |
| bogdanm | 0:9b334a45a8ff | 613 | #define _I2C_IEN_ACK_MASK 0x40UL /**< Bit mask for I2C_ACK */ |
| bogdanm | 0:9b334a45a8ff | 614 | #define _I2C_IEN_ACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ |
| bogdanm | 0:9b334a45a8ff | 615 | #define I2C_IEN_ACK_DEFAULT (_I2C_IEN_ACK_DEFAULT << 6) /**< Shifted mode DEFAULT for I2C_IEN */ |
| bogdanm | 0:9b334a45a8ff | 616 | #define I2C_IEN_NACK (0x1UL << 7) /**< Not Acknowledge Received Interrupt Enable */ |
| bogdanm | 0:9b334a45a8ff | 617 | #define _I2C_IEN_NACK_SHIFT 7 /**< Shift value for I2C_NACK */ |
| bogdanm | 0:9b334a45a8ff | 618 | #define _I2C_IEN_NACK_MASK 0x80UL /**< Bit mask for I2C_NACK */ |
| bogdanm | 0:9b334a45a8ff | 619 | #define _I2C_IEN_NACK_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ |
| bogdanm | 0:9b334a45a8ff | 620 | #define I2C_IEN_NACK_DEFAULT (_I2C_IEN_NACK_DEFAULT << 7) /**< Shifted mode DEFAULT for I2C_IEN */ |
| bogdanm | 0:9b334a45a8ff | 621 | #define I2C_IEN_MSTOP (0x1UL << 8) /**< MSTOP Interrupt Enable */ |
| bogdanm | 0:9b334a45a8ff | 622 | #define _I2C_IEN_MSTOP_SHIFT 8 /**< Shift value for I2C_MSTOP */ |
| bogdanm | 0:9b334a45a8ff | 623 | #define _I2C_IEN_MSTOP_MASK 0x100UL /**< Bit mask for I2C_MSTOP */ |
| bogdanm | 0:9b334a45a8ff | 624 | #define _I2C_IEN_MSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ |
| bogdanm | 0:9b334a45a8ff | 625 | #define I2C_IEN_MSTOP_DEFAULT (_I2C_IEN_MSTOP_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_IEN */ |
| bogdanm | 0:9b334a45a8ff | 626 | #define I2C_IEN_ARBLOST (0x1UL << 9) /**< Arbitration Lost Interrupt Enable */ |
| bogdanm | 0:9b334a45a8ff | 627 | #define _I2C_IEN_ARBLOST_SHIFT 9 /**< Shift value for I2C_ARBLOST */ |
| bogdanm | 0:9b334a45a8ff | 628 | #define _I2C_IEN_ARBLOST_MASK 0x200UL /**< Bit mask for I2C_ARBLOST */ |
| bogdanm | 0:9b334a45a8ff | 629 | #define _I2C_IEN_ARBLOST_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ |
| bogdanm | 0:9b334a45a8ff | 630 | #define I2C_IEN_ARBLOST_DEFAULT (_I2C_IEN_ARBLOST_DEFAULT << 9) /**< Shifted mode DEFAULT for I2C_IEN */ |
| bogdanm | 0:9b334a45a8ff | 631 | #define I2C_IEN_BUSERR (0x1UL << 10) /**< Bus Error Interrupt Enable */ |
| bogdanm | 0:9b334a45a8ff | 632 | #define _I2C_IEN_BUSERR_SHIFT 10 /**< Shift value for I2C_BUSERR */ |
| bogdanm | 0:9b334a45a8ff | 633 | #define _I2C_IEN_BUSERR_MASK 0x400UL /**< Bit mask for I2C_BUSERR */ |
| bogdanm | 0:9b334a45a8ff | 634 | #define _I2C_IEN_BUSERR_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ |
| bogdanm | 0:9b334a45a8ff | 635 | #define I2C_IEN_BUSERR_DEFAULT (_I2C_IEN_BUSERR_DEFAULT << 10) /**< Shifted mode DEFAULT for I2C_IEN */ |
| bogdanm | 0:9b334a45a8ff | 636 | #define I2C_IEN_BUSHOLD (0x1UL << 11) /**< Bus Held Interrupt Enable */ |
| bogdanm | 0:9b334a45a8ff | 637 | #define _I2C_IEN_BUSHOLD_SHIFT 11 /**< Shift value for I2C_BUSHOLD */ |
| bogdanm | 0:9b334a45a8ff | 638 | #define _I2C_IEN_BUSHOLD_MASK 0x800UL /**< Bit mask for I2C_BUSHOLD */ |
| bogdanm | 0:9b334a45a8ff | 639 | #define _I2C_IEN_BUSHOLD_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ |
| bogdanm | 0:9b334a45a8ff | 640 | #define I2C_IEN_BUSHOLD_DEFAULT (_I2C_IEN_BUSHOLD_DEFAULT << 11) /**< Shifted mode DEFAULT for I2C_IEN */ |
| bogdanm | 0:9b334a45a8ff | 641 | #define I2C_IEN_TXOF (0x1UL << 12) /**< Transmit Buffer Overflow Interrupt Enable */ |
| bogdanm | 0:9b334a45a8ff | 642 | #define _I2C_IEN_TXOF_SHIFT 12 /**< Shift value for I2C_TXOF */ |
| bogdanm | 0:9b334a45a8ff | 643 | #define _I2C_IEN_TXOF_MASK 0x1000UL /**< Bit mask for I2C_TXOF */ |
| bogdanm | 0:9b334a45a8ff | 644 | #define _I2C_IEN_TXOF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ |
| bogdanm | 0:9b334a45a8ff | 645 | #define I2C_IEN_TXOF_DEFAULT (_I2C_IEN_TXOF_DEFAULT << 12) /**< Shifted mode DEFAULT for I2C_IEN */ |
| bogdanm | 0:9b334a45a8ff | 646 | #define I2C_IEN_RXUF (0x1UL << 13) /**< Receive Buffer Underflow Interrupt Enable */ |
| bogdanm | 0:9b334a45a8ff | 647 | #define _I2C_IEN_RXUF_SHIFT 13 /**< Shift value for I2C_RXUF */ |
| bogdanm | 0:9b334a45a8ff | 648 | #define _I2C_IEN_RXUF_MASK 0x2000UL /**< Bit mask for I2C_RXUF */ |
| bogdanm | 0:9b334a45a8ff | 649 | #define _I2C_IEN_RXUF_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ |
| bogdanm | 0:9b334a45a8ff | 650 | #define I2C_IEN_RXUF_DEFAULT (_I2C_IEN_RXUF_DEFAULT << 13) /**< Shifted mode DEFAULT for I2C_IEN */ |
| bogdanm | 0:9b334a45a8ff | 651 | #define I2C_IEN_BITO (0x1UL << 14) /**< Bus Idle Timeout Interrupt Enable */ |
| bogdanm | 0:9b334a45a8ff | 652 | #define _I2C_IEN_BITO_SHIFT 14 /**< Shift value for I2C_BITO */ |
| bogdanm | 0:9b334a45a8ff | 653 | #define _I2C_IEN_BITO_MASK 0x4000UL /**< Bit mask for I2C_BITO */ |
| bogdanm | 0:9b334a45a8ff | 654 | #define _I2C_IEN_BITO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ |
| bogdanm | 0:9b334a45a8ff | 655 | #define I2C_IEN_BITO_DEFAULT (_I2C_IEN_BITO_DEFAULT << 14) /**< Shifted mode DEFAULT for I2C_IEN */ |
| bogdanm | 0:9b334a45a8ff | 656 | #define I2C_IEN_CLTO (0x1UL << 15) /**< Clock Low Interrupt Enable */ |
| bogdanm | 0:9b334a45a8ff | 657 | #define _I2C_IEN_CLTO_SHIFT 15 /**< Shift value for I2C_CLTO */ |
| bogdanm | 0:9b334a45a8ff | 658 | #define _I2C_IEN_CLTO_MASK 0x8000UL /**< Bit mask for I2C_CLTO */ |
| bogdanm | 0:9b334a45a8ff | 659 | #define _I2C_IEN_CLTO_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ |
| bogdanm | 0:9b334a45a8ff | 660 | #define I2C_IEN_CLTO_DEFAULT (_I2C_IEN_CLTO_DEFAULT << 15) /**< Shifted mode DEFAULT for I2C_IEN */ |
| bogdanm | 0:9b334a45a8ff | 661 | #define I2C_IEN_SSTOP (0x1UL << 16) /**< SSTOP Interrupt Enable */ |
| bogdanm | 0:9b334a45a8ff | 662 | #define _I2C_IEN_SSTOP_SHIFT 16 /**< Shift value for I2C_SSTOP */ |
| bogdanm | 0:9b334a45a8ff | 663 | #define _I2C_IEN_SSTOP_MASK 0x10000UL /**< Bit mask for I2C_SSTOP */ |
| bogdanm | 0:9b334a45a8ff | 664 | #define _I2C_IEN_SSTOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_IEN */ |
| bogdanm | 0:9b334a45a8ff | 665 | #define I2C_IEN_SSTOP_DEFAULT (_I2C_IEN_SSTOP_DEFAULT << 16) /**< Shifted mode DEFAULT for I2C_IEN */ |
| bogdanm | 0:9b334a45a8ff | 666 | |
| bogdanm | 0:9b334a45a8ff | 667 | /* Bit fields for I2C ROUTE */ |
| bogdanm | 0:9b334a45a8ff | 668 | #define _I2C_ROUTE_RESETVALUE 0x00000000UL /**< Default value for I2C_ROUTE */ |
| bogdanm | 0:9b334a45a8ff | 669 | #define _I2C_ROUTE_MASK 0x00000703UL /**< Mask for I2C_ROUTE */ |
| bogdanm | 0:9b334a45a8ff | 670 | #define I2C_ROUTE_SDAPEN (0x1UL << 0) /**< SDA Pin Enable */ |
| bogdanm | 0:9b334a45a8ff | 671 | #define _I2C_ROUTE_SDAPEN_SHIFT 0 /**< Shift value for I2C_SDAPEN */ |
| bogdanm | 0:9b334a45a8ff | 672 | #define _I2C_ROUTE_SDAPEN_MASK 0x1UL /**< Bit mask for I2C_SDAPEN */ |
| bogdanm | 0:9b334a45a8ff | 673 | #define _I2C_ROUTE_SDAPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTE */ |
| bogdanm | 0:9b334a45a8ff | 674 | #define I2C_ROUTE_SDAPEN_DEFAULT (_I2C_ROUTE_SDAPEN_DEFAULT << 0) /**< Shifted mode DEFAULT for I2C_ROUTE */ |
| bogdanm | 0:9b334a45a8ff | 675 | #define I2C_ROUTE_SCLPEN (0x1UL << 1) /**< SCL Pin Enable */ |
| bogdanm | 0:9b334a45a8ff | 676 | #define _I2C_ROUTE_SCLPEN_SHIFT 1 /**< Shift value for I2C_SCLPEN */ |
| bogdanm | 0:9b334a45a8ff | 677 | #define _I2C_ROUTE_SCLPEN_MASK 0x2UL /**< Bit mask for I2C_SCLPEN */ |
| bogdanm | 0:9b334a45a8ff | 678 | #define _I2C_ROUTE_SCLPEN_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTE */ |
| bogdanm | 0:9b334a45a8ff | 679 | #define I2C_ROUTE_SCLPEN_DEFAULT (_I2C_ROUTE_SCLPEN_DEFAULT << 1) /**< Shifted mode DEFAULT for I2C_ROUTE */ |
| bogdanm | 0:9b334a45a8ff | 680 | #define _I2C_ROUTE_LOCATION_SHIFT 8 /**< Shift value for I2C_LOCATION */ |
| bogdanm | 0:9b334a45a8ff | 681 | #define _I2C_ROUTE_LOCATION_MASK 0x700UL /**< Bit mask for I2C_LOCATION */ |
| bogdanm | 0:9b334a45a8ff | 682 | #define _I2C_ROUTE_LOCATION_LOC0 0x00000000UL /**< Mode LOC0 for I2C_ROUTE */ |
| bogdanm | 0:9b334a45a8ff | 683 | #define _I2C_ROUTE_LOCATION_DEFAULT 0x00000000UL /**< Mode DEFAULT for I2C_ROUTE */ |
| bogdanm | 0:9b334a45a8ff | 684 | #define _I2C_ROUTE_LOCATION_LOC1 0x00000001UL /**< Mode LOC1 for I2C_ROUTE */ |
| bogdanm | 0:9b334a45a8ff | 685 | #define _I2C_ROUTE_LOCATION_LOC2 0x00000002UL /**< Mode LOC2 for I2C_ROUTE */ |
| bogdanm | 0:9b334a45a8ff | 686 | #define _I2C_ROUTE_LOCATION_LOC3 0x00000003UL /**< Mode LOC3 for I2C_ROUTE */ |
| bogdanm | 0:9b334a45a8ff | 687 | #define _I2C_ROUTE_LOCATION_LOC4 0x00000004UL /**< Mode LOC4 for I2C_ROUTE */ |
| bogdanm | 0:9b334a45a8ff | 688 | #define _I2C_ROUTE_LOCATION_LOC5 0x00000005UL /**< Mode LOC5 for I2C_ROUTE */ |
| bogdanm | 0:9b334a45a8ff | 689 | #define _I2C_ROUTE_LOCATION_LOC6 0x00000006UL /**< Mode LOC6 for I2C_ROUTE */ |
| bogdanm | 0:9b334a45a8ff | 690 | #define I2C_ROUTE_LOCATION_LOC0 (_I2C_ROUTE_LOCATION_LOC0 << 8) /**< Shifted mode LOC0 for I2C_ROUTE */ |
| bogdanm | 0:9b334a45a8ff | 691 | #define I2C_ROUTE_LOCATION_DEFAULT (_I2C_ROUTE_LOCATION_DEFAULT << 8) /**< Shifted mode DEFAULT for I2C_ROUTE */ |
| bogdanm | 0:9b334a45a8ff | 692 | #define I2C_ROUTE_LOCATION_LOC1 (_I2C_ROUTE_LOCATION_LOC1 << 8) /**< Shifted mode LOC1 for I2C_ROUTE */ |
| bogdanm | 0:9b334a45a8ff | 693 | #define I2C_ROUTE_LOCATION_LOC2 (_I2C_ROUTE_LOCATION_LOC2 << 8) /**< Shifted mode LOC2 for I2C_ROUTE */ |
| bogdanm | 0:9b334a45a8ff | 694 | #define I2C_ROUTE_LOCATION_LOC3 (_I2C_ROUTE_LOCATION_LOC3 << 8) /**< Shifted mode LOC3 for I2C_ROUTE */ |
| bogdanm | 0:9b334a45a8ff | 695 | #define I2C_ROUTE_LOCATION_LOC4 (_I2C_ROUTE_LOCATION_LOC4 << 8) /**< Shifted mode LOC4 for I2C_ROUTE */ |
| bogdanm | 0:9b334a45a8ff | 696 | #define I2C_ROUTE_LOCATION_LOC5 (_I2C_ROUTE_LOCATION_LOC5 << 8) /**< Shifted mode LOC5 for I2C_ROUTE */ |
| bogdanm | 0:9b334a45a8ff | 697 | #define I2C_ROUTE_LOCATION_LOC6 (_I2C_ROUTE_LOCATION_LOC6 << 8) /**< Shifted mode LOC6 for I2C_ROUTE */ |
| bogdanm | 0:9b334a45a8ff | 698 | |
| bogdanm | 0:9b334a45a8ff | 699 | /** @} End of group EFM32HG_I2C */ |
| bogdanm | 0:9b334a45a8ff | 700 | |
| bogdanm | 0:9b334a45a8ff | 701 |