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targets/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/device/efm32lg_rtc.h@149:156823d33999, 2016-10-28 (annotated)

Committer:
<>
Date:
Fri Oct 28 11:17:30 2016 +0100
Revision:
149:156823d33999
Parent:
targets/cmsis/TARGET_Silicon_Labs/TARGET_EFM32/TARGET_EFM32LG_STK3600/efm32lg_rtc.h@144:ef7eb2e8f9f7 
This updates the lib to the mbed lib v128



NOTE: This release includes a restructuring of the file and directory locations and thus some

include paths in your code may need updating accordingly.

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 2 * @file efm32lg_rtc.h
<> 144:ef7eb2e8f9f7 3 * @brief EFM32LG_RTC register and bit field definitions
<> 144:ef7eb2e8f9f7 4 * @version 4.2.0
<> 144:ef7eb2e8f9f7 5 ******************************************************************************
<> 144:ef7eb2e8f9f7 6 * @section License
<> 144:ef7eb2e8f9f7 7 * <b>Copyright 2015 Silicon Laboratories, Inc. http://www.silabs.com</b>
<> 144:ef7eb2e8f9f7 8 ******************************************************************************
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Permission is granted to anyone to use this software for any purpose,
<> 144:ef7eb2e8f9f7 11 * including commercial applications, and to alter it and redistribute it
<> 144:ef7eb2e8f9f7 12 * freely, subject to the following restrictions:
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * 1. The origin of this software must not be misrepresented; you must not
<> 144:ef7eb2e8f9f7 15 * claim that you wrote the original software.@n
<> 144:ef7eb2e8f9f7 16 * 2. Altered source versions must be plainly marked as such, and must not be
<> 144:ef7eb2e8f9f7 17 * misrepresented as being the original software.@n
<> 144:ef7eb2e8f9f7 18 * 3. This notice may not be removed or altered from any source distribution.
<> 144:ef7eb2e8f9f7 19 *
<> 144:ef7eb2e8f9f7 20 * DISCLAIMER OF WARRANTY/LIMITATION OF REMEDIES: Silicon Laboratories, Inc.
<> 144:ef7eb2e8f9f7 21 * has no obligation to support this Software. Silicon Laboratories, Inc. is
<> 144:ef7eb2e8f9f7 22 * providing the Software "AS IS", with no express or implied warranties of any
<> 144:ef7eb2e8f9f7 23 * kind, including, but not limited to, any implied warranties of
<> 144:ef7eb2e8f9f7 24 * merchantability or fitness for any particular purpose or warranties against
<> 144:ef7eb2e8f9f7 25 * infringement of any proprietary rights of a third party.
<> 144:ef7eb2e8f9f7 26 *
<> 144:ef7eb2e8f9f7 27 * Silicon Laboratories, Inc. will not be liable for any consequential,
<> 144:ef7eb2e8f9f7 28 * incidental, or special damages, or any other relief, or for any claim by
<> 144:ef7eb2e8f9f7 29 * any third party, arising from your use of this Software.
<> 144:ef7eb2e8f9f7 30 *
<> 144:ef7eb2e8f9f7 31 *****************************************************************************/
<> 144:ef7eb2e8f9f7 32 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 33 * @addtogroup Parts
<> 144:ef7eb2e8f9f7 34 * @{
<> 144:ef7eb2e8f9f7 35 ******************************************************************************/
<> 144:ef7eb2e8f9f7 36 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 37 * @defgroup EFM32LG_RTC
<> 144:ef7eb2e8f9f7 38 * @{
<> 144:ef7eb2e8f9f7 39 * @brief EFM32LG_RTC Register Declaration
<> 144:ef7eb2e8f9f7 40 *****************************************************************************/
<> 144:ef7eb2e8f9f7 41 typedef struct
<> 144:ef7eb2e8f9f7 42 {
<> 144:ef7eb2e8f9f7 43 __IO uint32_t CTRL; /**< Control Register */
<> 144:ef7eb2e8f9f7 44 __IO uint32_t CNT; /**< Counter Value Register */
<> 144:ef7eb2e8f9f7 45 __IO uint32_t COMP0; /**< Compare Value Register 0 */
<> 144:ef7eb2e8f9f7 46 __IO uint32_t COMP1; /**< Compare Value Register 1 */
<> 144:ef7eb2e8f9f7 47 __I uint32_t IF; /**< Interrupt Flag Register */
<> 144:ef7eb2e8f9f7 48 __IO uint32_t IFS; /**< Interrupt Flag Set Register */
<> 144:ef7eb2e8f9f7 49 __IO uint32_t IFC; /**< Interrupt Flag Clear Register */
<> 144:ef7eb2e8f9f7 50 __IO uint32_t IEN; /**< Interrupt Enable Register */
<> 144:ef7eb2e8f9f7 51
<> 144:ef7eb2e8f9f7 52 __IO uint32_t FREEZE; /**< Freeze Register */
<> 144:ef7eb2e8f9f7 53 __I uint32_t SYNCBUSY; /**< Synchronization Busy Register */
<> 144:ef7eb2e8f9f7 54 } RTC_TypeDef; /** @} */
<> 144:ef7eb2e8f9f7 55
<> 144:ef7eb2e8f9f7 56 /**************************************************************************//**
<> 144:ef7eb2e8f9f7 57 * @defgroup EFM32LG_RTC_BitFields
<> 144:ef7eb2e8f9f7 58 * @{
<> 144:ef7eb2e8f9f7 59 *****************************************************************************/
<> 144:ef7eb2e8f9f7 60
<> 144:ef7eb2e8f9f7 61 /* Bit fields for RTC CTRL */
<> 144:ef7eb2e8f9f7 62 #define _RTC_CTRL_RESETVALUE 0x00000000UL /**< Default value for RTC_CTRL */
<> 144:ef7eb2e8f9f7 63 #define _RTC_CTRL_MASK 0x00000007UL /**< Mask for RTC_CTRL */
<> 144:ef7eb2e8f9f7 64 #define RTC_CTRL_EN (0x1UL << 0) /**< RTC Enable */
<> 144:ef7eb2e8f9f7 65 #define _RTC_CTRL_EN_SHIFT 0 /**< Shift value for RTC_EN */
<> 144:ef7eb2e8f9f7 66 #define _RTC_CTRL_EN_MASK 0x1UL /**< Bit mask for RTC_EN */
<> 144:ef7eb2e8f9f7 67 #define _RTC_CTRL_EN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CTRL */
<> 144:ef7eb2e8f9f7 68 #define RTC_CTRL_EN_DEFAULT (_RTC_CTRL_EN_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_CTRL */
<> 144:ef7eb2e8f9f7 69 #define RTC_CTRL_DEBUGRUN (0x1UL << 1) /**< Debug Mode Run Enable */
<> 144:ef7eb2e8f9f7 70 #define _RTC_CTRL_DEBUGRUN_SHIFT 1 /**< Shift value for RTC_DEBUGRUN */
<> 144:ef7eb2e8f9f7 71 #define _RTC_CTRL_DEBUGRUN_MASK 0x2UL /**< Bit mask for RTC_DEBUGRUN */
<> 144:ef7eb2e8f9f7 72 #define _RTC_CTRL_DEBUGRUN_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CTRL */
<> 144:ef7eb2e8f9f7 73 #define RTC_CTRL_DEBUGRUN_DEFAULT (_RTC_CTRL_DEBUGRUN_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_CTRL */
<> 144:ef7eb2e8f9f7 74 #define RTC_CTRL_COMP0TOP (0x1UL << 2) /**< Compare Channel 0 is Top Value */
<> 144:ef7eb2e8f9f7 75 #define _RTC_CTRL_COMP0TOP_SHIFT 2 /**< Shift value for RTC_COMP0TOP */
<> 144:ef7eb2e8f9f7 76 #define _RTC_CTRL_COMP0TOP_MASK 0x4UL /**< Bit mask for RTC_COMP0TOP */
<> 144:ef7eb2e8f9f7 77 #define _RTC_CTRL_COMP0TOP_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CTRL */
<> 144:ef7eb2e8f9f7 78 #define _RTC_CTRL_COMP0TOP_DISABLE 0x00000000UL /**< Mode DISABLE for RTC_CTRL */
<> 144:ef7eb2e8f9f7 79 #define _RTC_CTRL_COMP0TOP_ENABLE 0x00000001UL /**< Mode ENABLE for RTC_CTRL */
<> 144:ef7eb2e8f9f7 80 #define RTC_CTRL_COMP0TOP_DEFAULT (_RTC_CTRL_COMP0TOP_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_CTRL */
<> 144:ef7eb2e8f9f7 81 #define RTC_CTRL_COMP0TOP_DISABLE (_RTC_CTRL_COMP0TOP_DISABLE << 2) /**< Shifted mode DISABLE for RTC_CTRL */
<> 144:ef7eb2e8f9f7 82 #define RTC_CTRL_COMP0TOP_ENABLE (_RTC_CTRL_COMP0TOP_ENABLE << 2) /**< Shifted mode ENABLE for RTC_CTRL */
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 /* Bit fields for RTC CNT */
<> 144:ef7eb2e8f9f7 85 #define _RTC_CNT_RESETVALUE 0x00000000UL /**< Default value for RTC_CNT */
<> 144:ef7eb2e8f9f7 86 #define _RTC_CNT_MASK 0x00FFFFFFUL /**< Mask for RTC_CNT */
<> 144:ef7eb2e8f9f7 87 #define _RTC_CNT_CNT_SHIFT 0 /**< Shift value for RTC_CNT */
<> 144:ef7eb2e8f9f7 88 #define _RTC_CNT_CNT_MASK 0xFFFFFFUL /**< Bit mask for RTC_CNT */
<> 144:ef7eb2e8f9f7 89 #define _RTC_CNT_CNT_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_CNT */
<> 144:ef7eb2e8f9f7 90 #define RTC_CNT_CNT_DEFAULT (_RTC_CNT_CNT_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_CNT */
<> 144:ef7eb2e8f9f7 91
<> 144:ef7eb2e8f9f7 92 /* Bit fields for RTC COMP0 */
<> 144:ef7eb2e8f9f7 93 #define _RTC_COMP0_RESETVALUE 0x00000000UL /**< Default value for RTC_COMP0 */
<> 144:ef7eb2e8f9f7 94 #define _RTC_COMP0_MASK 0x00FFFFFFUL /**< Mask for RTC_COMP0 */
<> 144:ef7eb2e8f9f7 95 #define _RTC_COMP0_COMP0_SHIFT 0 /**< Shift value for RTC_COMP0 */
<> 144:ef7eb2e8f9f7 96 #define _RTC_COMP0_COMP0_MASK 0xFFFFFFUL /**< Bit mask for RTC_COMP0 */
<> 144:ef7eb2e8f9f7 97 #define _RTC_COMP0_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_COMP0 */
<> 144:ef7eb2e8f9f7 98 #define RTC_COMP0_COMP0_DEFAULT (_RTC_COMP0_COMP0_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_COMP0 */
<> 144:ef7eb2e8f9f7 99
<> 144:ef7eb2e8f9f7 100 /* Bit fields for RTC COMP1 */
<> 144:ef7eb2e8f9f7 101 #define _RTC_COMP1_RESETVALUE 0x00000000UL /**< Default value for RTC_COMP1 */
<> 144:ef7eb2e8f9f7 102 #define _RTC_COMP1_MASK 0x00FFFFFFUL /**< Mask for RTC_COMP1 */
<> 144:ef7eb2e8f9f7 103 #define _RTC_COMP1_COMP1_SHIFT 0 /**< Shift value for RTC_COMP1 */
<> 144:ef7eb2e8f9f7 104 #define _RTC_COMP1_COMP1_MASK 0xFFFFFFUL /**< Bit mask for RTC_COMP1 */
<> 144:ef7eb2e8f9f7 105 #define _RTC_COMP1_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_COMP1 */
<> 144:ef7eb2e8f9f7 106 #define RTC_COMP1_COMP1_DEFAULT (_RTC_COMP1_COMP1_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_COMP1 */
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 /* Bit fields for RTC IF */
<> 144:ef7eb2e8f9f7 109 #define _RTC_IF_RESETVALUE 0x00000000UL /**< Default value for RTC_IF */
<> 144:ef7eb2e8f9f7 110 #define _RTC_IF_MASK 0x00000007UL /**< Mask for RTC_IF */
<> 144:ef7eb2e8f9f7 111 #define RTC_IF_OF (0x1UL << 0) /**< Overflow Interrupt Flag */
<> 144:ef7eb2e8f9f7 112 #define _RTC_IF_OF_SHIFT 0 /**< Shift value for RTC_OF */
<> 144:ef7eb2e8f9f7 113 #define _RTC_IF_OF_MASK 0x1UL /**< Bit mask for RTC_OF */
<> 144:ef7eb2e8f9f7 114 #define _RTC_IF_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IF */
<> 144:ef7eb2e8f9f7 115 #define RTC_IF_OF_DEFAULT (_RTC_IF_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_IF */
<> 144:ef7eb2e8f9f7 116 #define RTC_IF_COMP0 (0x1UL << 1) /**< Compare Match 0 Interrupt Flag */
<> 144:ef7eb2e8f9f7 117 #define _RTC_IF_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */
<> 144:ef7eb2e8f9f7 118 #define _RTC_IF_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */
<> 144:ef7eb2e8f9f7 119 #define _RTC_IF_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IF */
<> 144:ef7eb2e8f9f7 120 #define RTC_IF_COMP0_DEFAULT (_RTC_IF_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_IF */
<> 144:ef7eb2e8f9f7 121 #define RTC_IF_COMP1 (0x1UL << 2) /**< Compare Match 1 Interrupt Flag */
<> 144:ef7eb2e8f9f7 122 #define _RTC_IF_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */
<> 144:ef7eb2e8f9f7 123 #define _RTC_IF_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */
<> 144:ef7eb2e8f9f7 124 #define _RTC_IF_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IF */
<> 144:ef7eb2e8f9f7 125 #define RTC_IF_COMP1_DEFAULT (_RTC_IF_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_IF */
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 /* Bit fields for RTC IFS */
<> 144:ef7eb2e8f9f7 128 #define _RTC_IFS_RESETVALUE 0x00000000UL /**< Default value for RTC_IFS */
<> 144:ef7eb2e8f9f7 129 #define _RTC_IFS_MASK 0x00000007UL /**< Mask for RTC_IFS */
<> 144:ef7eb2e8f9f7 130 #define RTC_IFS_OF (0x1UL << 0) /**< Set Overflow Interrupt Flag */
<> 144:ef7eb2e8f9f7 131 #define _RTC_IFS_OF_SHIFT 0 /**< Shift value for RTC_OF */
<> 144:ef7eb2e8f9f7 132 #define _RTC_IFS_OF_MASK 0x1UL /**< Bit mask for RTC_OF */
<> 144:ef7eb2e8f9f7 133 #define _RTC_IFS_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFS */
<> 144:ef7eb2e8f9f7 134 #define RTC_IFS_OF_DEFAULT (_RTC_IFS_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_IFS */
<> 144:ef7eb2e8f9f7 135 #define RTC_IFS_COMP0 (0x1UL << 1) /**< Set Compare match 0 Interrupt Flag */
<> 144:ef7eb2e8f9f7 136 #define _RTC_IFS_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */
<> 144:ef7eb2e8f9f7 137 #define _RTC_IFS_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */
<> 144:ef7eb2e8f9f7 138 #define _RTC_IFS_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFS */
<> 144:ef7eb2e8f9f7 139 #define RTC_IFS_COMP0_DEFAULT (_RTC_IFS_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_IFS */
<> 144:ef7eb2e8f9f7 140 #define RTC_IFS_COMP1 (0x1UL << 2) /**< Set Compare match 1 Interrupt Flag */
<> 144:ef7eb2e8f9f7 141 #define _RTC_IFS_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */
<> 144:ef7eb2e8f9f7 142 #define _RTC_IFS_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */
<> 144:ef7eb2e8f9f7 143 #define _RTC_IFS_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFS */
<> 144:ef7eb2e8f9f7 144 #define RTC_IFS_COMP1_DEFAULT (_RTC_IFS_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_IFS */
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 /* Bit fields for RTC IFC */
<> 144:ef7eb2e8f9f7 147 #define _RTC_IFC_RESETVALUE 0x00000000UL /**< Default value for RTC_IFC */
<> 144:ef7eb2e8f9f7 148 #define _RTC_IFC_MASK 0x00000007UL /**< Mask for RTC_IFC */
<> 144:ef7eb2e8f9f7 149 #define RTC_IFC_OF (0x1UL << 0) /**< Clear Overflow Interrupt Flag */
<> 144:ef7eb2e8f9f7 150 #define _RTC_IFC_OF_SHIFT 0 /**< Shift value for RTC_OF */
<> 144:ef7eb2e8f9f7 151 #define _RTC_IFC_OF_MASK 0x1UL /**< Bit mask for RTC_OF */
<> 144:ef7eb2e8f9f7 152 #define _RTC_IFC_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFC */
<> 144:ef7eb2e8f9f7 153 #define RTC_IFC_OF_DEFAULT (_RTC_IFC_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_IFC */
<> 144:ef7eb2e8f9f7 154 #define RTC_IFC_COMP0 (0x1UL << 1) /**< Clear Compare match 0 Interrupt Flag */
<> 144:ef7eb2e8f9f7 155 #define _RTC_IFC_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */
<> 144:ef7eb2e8f9f7 156 #define _RTC_IFC_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */
<> 144:ef7eb2e8f9f7 157 #define _RTC_IFC_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFC */
<> 144:ef7eb2e8f9f7 158 #define RTC_IFC_COMP0_DEFAULT (_RTC_IFC_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_IFC */
<> 144:ef7eb2e8f9f7 159 #define RTC_IFC_COMP1 (0x1UL << 2) /**< Clear Compare match 1 Interrupt Flag */
<> 144:ef7eb2e8f9f7 160 #define _RTC_IFC_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */
<> 144:ef7eb2e8f9f7 161 #define _RTC_IFC_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */
<> 144:ef7eb2e8f9f7 162 #define _RTC_IFC_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IFC */
<> 144:ef7eb2e8f9f7 163 #define RTC_IFC_COMP1_DEFAULT (_RTC_IFC_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_IFC */
<> 144:ef7eb2e8f9f7 164
<> 144:ef7eb2e8f9f7 165 /* Bit fields for RTC IEN */
<> 144:ef7eb2e8f9f7 166 #define _RTC_IEN_RESETVALUE 0x00000000UL /**< Default value for RTC_IEN */
<> 144:ef7eb2e8f9f7 167 #define _RTC_IEN_MASK 0x00000007UL /**< Mask for RTC_IEN */
<> 144:ef7eb2e8f9f7 168 #define RTC_IEN_OF (0x1UL << 0) /**< Overflow Interrupt Enable */
<> 144:ef7eb2e8f9f7 169 #define _RTC_IEN_OF_SHIFT 0 /**< Shift value for RTC_OF */
<> 144:ef7eb2e8f9f7 170 #define _RTC_IEN_OF_MASK 0x1UL /**< Bit mask for RTC_OF */
<> 144:ef7eb2e8f9f7 171 #define _RTC_IEN_OF_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IEN */
<> 144:ef7eb2e8f9f7 172 #define RTC_IEN_OF_DEFAULT (_RTC_IEN_OF_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_IEN */
<> 144:ef7eb2e8f9f7 173 #define RTC_IEN_COMP0 (0x1UL << 1) /**< Compare Match 0 Interrupt Enable */
<> 144:ef7eb2e8f9f7 174 #define _RTC_IEN_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */
<> 144:ef7eb2e8f9f7 175 #define _RTC_IEN_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */
<> 144:ef7eb2e8f9f7 176 #define _RTC_IEN_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IEN */
<> 144:ef7eb2e8f9f7 177 #define RTC_IEN_COMP0_DEFAULT (_RTC_IEN_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_IEN */
<> 144:ef7eb2e8f9f7 178 #define RTC_IEN_COMP1 (0x1UL << 2) /**< Compare Match 1 Interrupt Enable */
<> 144:ef7eb2e8f9f7 179 #define _RTC_IEN_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */
<> 144:ef7eb2e8f9f7 180 #define _RTC_IEN_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */
<> 144:ef7eb2e8f9f7 181 #define _RTC_IEN_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_IEN */
<> 144:ef7eb2e8f9f7 182 #define RTC_IEN_COMP1_DEFAULT (_RTC_IEN_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_IEN */
<> 144:ef7eb2e8f9f7 183
<> 144:ef7eb2e8f9f7 184 /* Bit fields for RTC FREEZE */
<> 144:ef7eb2e8f9f7 185 #define _RTC_FREEZE_RESETVALUE 0x00000000UL /**< Default value for RTC_FREEZE */
<> 144:ef7eb2e8f9f7 186 #define _RTC_FREEZE_MASK 0x00000001UL /**< Mask for RTC_FREEZE */
<> 144:ef7eb2e8f9f7 187 #define RTC_FREEZE_REGFREEZE (0x1UL << 0) /**< Register Update Freeze */
<> 144:ef7eb2e8f9f7 188 #define _RTC_FREEZE_REGFREEZE_SHIFT 0 /**< Shift value for RTC_REGFREEZE */
<> 144:ef7eb2e8f9f7 189 #define _RTC_FREEZE_REGFREEZE_MASK 0x1UL /**< Bit mask for RTC_REGFREEZE */
<> 144:ef7eb2e8f9f7 190 #define _RTC_FREEZE_REGFREEZE_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_FREEZE */
<> 144:ef7eb2e8f9f7 191 #define _RTC_FREEZE_REGFREEZE_UPDATE 0x00000000UL /**< Mode UPDATE for RTC_FREEZE */
<> 144:ef7eb2e8f9f7 192 #define _RTC_FREEZE_REGFREEZE_FREEZE 0x00000001UL /**< Mode FREEZE for RTC_FREEZE */
<> 144:ef7eb2e8f9f7 193 #define RTC_FREEZE_REGFREEZE_DEFAULT (_RTC_FREEZE_REGFREEZE_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_FREEZE */
<> 144:ef7eb2e8f9f7 194 #define RTC_FREEZE_REGFREEZE_UPDATE (_RTC_FREEZE_REGFREEZE_UPDATE << 0) /**< Shifted mode UPDATE for RTC_FREEZE */
<> 144:ef7eb2e8f9f7 195 #define RTC_FREEZE_REGFREEZE_FREEZE (_RTC_FREEZE_REGFREEZE_FREEZE << 0) /**< Shifted mode FREEZE for RTC_FREEZE */
<> 144:ef7eb2e8f9f7 196
<> 144:ef7eb2e8f9f7 197 /* Bit fields for RTC SYNCBUSY */
<> 144:ef7eb2e8f9f7 198 #define _RTC_SYNCBUSY_RESETVALUE 0x00000000UL /**< Default value for RTC_SYNCBUSY */
<> 144:ef7eb2e8f9f7 199 #define _RTC_SYNCBUSY_MASK 0x00000007UL /**< Mask for RTC_SYNCBUSY */
<> 144:ef7eb2e8f9f7 200 #define RTC_SYNCBUSY_CTRL (0x1UL << 0) /**< CTRL Register Busy */
<> 144:ef7eb2e8f9f7 201 #define _RTC_SYNCBUSY_CTRL_SHIFT 0 /**< Shift value for RTC_CTRL */
<> 144:ef7eb2e8f9f7 202 #define _RTC_SYNCBUSY_CTRL_MASK 0x1UL /**< Bit mask for RTC_CTRL */
<> 144:ef7eb2e8f9f7 203 #define _RTC_SYNCBUSY_CTRL_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_SYNCBUSY */
<> 144:ef7eb2e8f9f7 204 #define RTC_SYNCBUSY_CTRL_DEFAULT (_RTC_SYNCBUSY_CTRL_DEFAULT << 0) /**< Shifted mode DEFAULT for RTC_SYNCBUSY */
<> 144:ef7eb2e8f9f7 205 #define RTC_SYNCBUSY_COMP0 (0x1UL << 1) /**< COMP0 Register Busy */
<> 144:ef7eb2e8f9f7 206 #define _RTC_SYNCBUSY_COMP0_SHIFT 1 /**< Shift value for RTC_COMP0 */
<> 144:ef7eb2e8f9f7 207 #define _RTC_SYNCBUSY_COMP0_MASK 0x2UL /**< Bit mask for RTC_COMP0 */
<> 144:ef7eb2e8f9f7 208 #define _RTC_SYNCBUSY_COMP0_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_SYNCBUSY */
<> 144:ef7eb2e8f9f7 209 #define RTC_SYNCBUSY_COMP0_DEFAULT (_RTC_SYNCBUSY_COMP0_DEFAULT << 1) /**< Shifted mode DEFAULT for RTC_SYNCBUSY */
<> 144:ef7eb2e8f9f7 210 #define RTC_SYNCBUSY_COMP1 (0x1UL << 2) /**< COMP1 Register Busy */
<> 144:ef7eb2e8f9f7 211 #define _RTC_SYNCBUSY_COMP1_SHIFT 2 /**< Shift value for RTC_COMP1 */
<> 144:ef7eb2e8f9f7 212 #define _RTC_SYNCBUSY_COMP1_MASK 0x4UL /**< Bit mask for RTC_COMP1 */
<> 144:ef7eb2e8f9f7 213 #define _RTC_SYNCBUSY_COMP1_DEFAULT 0x00000000UL /**< Mode DEFAULT for RTC_SYNCBUSY */
<> 144:ef7eb2e8f9f7 214 #define RTC_SYNCBUSY_COMP1_DEFAULT (_RTC_SYNCBUSY_COMP1_DEFAULT << 2) /**< Shifted mode DEFAULT for RTC_SYNCBUSY */
<> 144:ef7eb2e8f9f7 215
<> 144:ef7eb2e8f9f7 216 /** @} End of group EFM32LG_RTC */
<> 144:ef7eb2e8f9f7 217 /** @} End of group Parts */
<> 144:ef7eb2e8f9f7 218