rik te winkel / mbed-dev

Forked mbed-dev as I use an 20 pins stm32F042 and not the 32 pins version

Dependents:   Numitron_clock

Fork of mbed-dev by mbed official

targets/TARGET_Maxim/TARGET_MAX32625/mxc/spis.h@153:0a78729d3229, 2017-01-22 (annotated)

Committer:
riktw
Date:
Sun Jan 22 22:20:36 2017 +0000
Revision:
153:0a78729d3229
Parent:
150:02e0a0aed4ec 
Back to 8Mhz clock. Revision 1.0

Who changed what in which revision?

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<> 150:02e0a0aed4ec 1 /*******************************************************************************
<> 150:02e0a0aed4ec 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 150:02e0a0aed4ec 3 *
<> 150:02e0a0aed4ec 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 150:02e0a0aed4ec 5 * copy of this software and associated documentation files (the "Software"),
<> 150:02e0a0aed4ec 6 * to deal in the Software without restriction, including without limitation
<> 150:02e0a0aed4ec 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 150:02e0a0aed4ec 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 150:02e0a0aed4ec 9 * Software is furnished to do so, subject to the following conditions:
<> 150:02e0a0aed4ec 10 *
<> 150:02e0a0aed4ec 11 * The above copyright notice and this permission notice shall be included
<> 150:02e0a0aed4ec 12 * in all copies or substantial portions of the Software.
<> 150:02e0a0aed4ec 13 *
<> 150:02e0a0aed4ec 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 150:02e0a0aed4ec 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 150:02e0a0aed4ec 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 150:02e0a0aed4ec 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 150:02e0a0aed4ec 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 150:02e0a0aed4ec 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 150:02e0a0aed4ec 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 150:02e0a0aed4ec 21 *
<> 150:02e0a0aed4ec 22 * Except as contained in this notice, the name of Maxim Integrated
<> 150:02e0a0aed4ec 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 150:02e0a0aed4ec 24 * Products, Inc. Branding Policy.
<> 150:02e0a0aed4ec 25 *
<> 150:02e0a0aed4ec 26 * The mere transfer of this software does not imply any licenses
<> 150:02e0a0aed4ec 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 150:02e0a0aed4ec 28 * trademarks, maskwork rights, or any other form of intellectual
<> 150:02e0a0aed4ec 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 150:02e0a0aed4ec 30 * ownership rights.
<> 150:02e0a0aed4ec 31 *
<> 150:02e0a0aed4ec 32 * $Date: 2016-05-18 16:27:43 -0500 (Wed, 18 May 2016) $
<> 150:02e0a0aed4ec 33 * $Revision: 22908 $
<> 150:02e0a0aed4ec 34 *
<> 150:02e0a0aed4ec 35 ******************************************************************************/
<> 150:02e0a0aed4ec 36
<> 150:02e0a0aed4ec 37 /**
<> 150:02e0a0aed4ec 38 * @file spis.s
<> 150:02e0a0aed4ec 39 * @brief SPI Slave driver header file.
<> 150:02e0a0aed4ec 40 */
<> 150:02e0a0aed4ec 41
<> 150:02e0a0aed4ec 42 #include "mxc_config.h"
<> 150:02e0a0aed4ec 43 #include "mxc_sys.h"
<> 150:02e0a0aed4ec 44 #include "spis_regs.h"
<> 150:02e0a0aed4ec 45
<> 150:02e0a0aed4ec 46 #ifndef _SPIS_H_
<> 150:02e0a0aed4ec 47 #define _SPIS_H_
<> 150:02e0a0aed4ec 48
<> 150:02e0a0aed4ec 49 #ifdef __cplusplus
<> 150:02e0a0aed4ec 50 extern "C" {
<> 150:02e0a0aed4ec 51 #endif
<> 150:02e0a0aed4ec 52
<> 150:02e0a0aed4ec 53 /***** Definitions *****/
<> 150:02e0a0aed4ec 54
<> 150:02e0a0aed4ec 55 /// @brief Number of data lines to use.
<> 150:02e0a0aed4ec 56 typedef enum {
<> 150:02e0a0aed4ec 57 SPIS_WIDTH_1 = 0,
<> 150:02e0a0aed4ec 58 SPIS_WIDTH_2 = 1,
<> 150:02e0a0aed4ec 59 SPIS_WIDTH_4 = 2
<> 150:02e0a0aed4ec 60 } spis_width_t;
<> 150:02e0a0aed4ec 61
<> 150:02e0a0aed4ec 62 /// @brief SPIS Transaction request.
<> 150:02e0a0aed4ec 63 typedef struct spis_req spis_req_t;
<> 150:02e0a0aed4ec 64 struct spis_req {
<> 150:02e0a0aed4ec 65 uint8_t deass; ///< End the transaction when SS is deasserted.
<> 150:02e0a0aed4ec 66 const uint8_t *tx_data; ///< TX buffer.
<> 150:02e0a0aed4ec 67 uint8_t *rx_data; ///< RX buffer.
<> 150:02e0a0aed4ec 68 spis_width_t width; ///< Number of data lines to use.
<> 150:02e0a0aed4ec 69 unsigned len; ///< Number of bytes to send.
<> 150:02e0a0aed4ec 70 unsigned read_num; ///< Number of bytes transacted.
<> 150:02e0a0aed4ec 71 unsigned write_num; ///< Number of bytes transacted.
<> 150:02e0a0aed4ec 72
<> 150:02e0a0aed4ec 73 /**
<> 150:02e0a0aed4ec 74 * @brief Callback for asynchronous request.
<> 150:02e0a0aed4ec 75 * @param spis_req_t* Pointer to the transaction request.
<> 150:02e0a0aed4ec 76 * @param int Error code.
<> 150:02e0a0aed4ec 77 */
<> 150:02e0a0aed4ec 78 void (*callback)(spis_req_t*, int);
<> 150:02e0a0aed4ec 79 };
<> 150:02e0a0aed4ec 80
<> 150:02e0a0aed4ec 81 /***** Globals *****/
<> 150:02e0a0aed4ec 82
<> 150:02e0a0aed4ec 83 /***** Function Prototypes *****/
<> 150:02e0a0aed4ec 84
<> 150:02e0a0aed4ec 85 /**
<> 150:02e0a0aed4ec 86 * @brief Initialize SPIS module.
<> 150:02e0a0aed4ec 87 * @param spis Pointer to SPIS regs.
<> 150:02e0a0aed4ec 88 * @param cfg Pointer to SPIS configuration.
<> 150:02e0a0aed4ec 89 * @param mode SPI Mode to configure the slave.
<> 150:02e0a0aed4ec 90 * @param sys_cfg Pointer to system configuration object.
<> 150:02e0a0aed4ec 91 * @returns #E_NO_ERROR if everything is successful.
<> 150:02e0a0aed4ec 92 */
<> 150:02e0a0aed4ec 93 int SPIS_Init(mxc_spis_regs_t *spis, uint8_t mode, const sys_cfg_spis_t *sys_cfg);
<> 150:02e0a0aed4ec 94
<> 150:02e0a0aed4ec 95
<> 150:02e0a0aed4ec 96 /**
<> 150:02e0a0aed4ec 97 * @brief Shutdown SPIS module.
<> 150:02e0a0aed4ec 98 * @param spis Pointer to SPIS regs.
<> 150:02e0a0aed4ec 99 * @returns #E_NO_ERROR if everything is successful
<> 150:02e0a0aed4ec 100 */
<> 150:02e0a0aed4ec 101 int SPIS_Shutdown(mxc_spis_regs_t *spis);
<> 150:02e0a0aed4ec 102
<> 150:02e0a0aed4ec 103 /**
<> 150:02e0a0aed4ec 104 * @brief Read/write SPIS data. Will block until transaction is complete.
<> 150:02e0a0aed4ec 105 * @param spis Pointer to SPIS regs.
<> 150:02e0a0aed4ec 106 * @param req Request for a SPIS transaction.
<> 150:02e0a0aed4ec 107 * @note Callback is ignored.
<> 150:02e0a0aed4ec 108 * @returns Bytes transacted if everything is successful, error if unsuccessful.
<> 150:02e0a0aed4ec 109 */
<> 150:02e0a0aed4ec 110 int SPIS_Trans(mxc_spis_regs_t *spis, spis_req_t *req);
<> 150:02e0a0aed4ec 111
<> 150:02e0a0aed4ec 112 /**
<> 150:02e0a0aed4ec 113 * @brief Asynchronously read/write SPIS data.
<> 150:02e0a0aed4ec 114 * @param spis Pointer to SPIS regs.
<> 150:02e0a0aed4ec 115 * @param req Request for a SPIS transaction.
<> 150:02e0a0aed4ec 116 * @note Request struct must remain allocated until callback.
<> 150:02e0a0aed4ec 117 * @returns #E_NO_ERROR if everything is successful, error if unsuccessful.
<> 150:02e0a0aed4ec 118 */
<> 150:02e0a0aed4ec 119 int SPIS_TransAsync(mxc_spis_regs_t *spis, spis_req_t *req);
<> 150:02e0a0aed4ec 120
<> 150:02e0a0aed4ec 121 /**
<> 150:02e0a0aed4ec 122 * @brief Abort asynchronous request.
<> 150:02e0a0aed4ec 123 * @param req Pointer to request for a SPIS transaction.
<> 150:02e0a0aed4ec 124 * @returns #E_NO_ERROR if request aborted, error if unsuccessful.
<> 150:02e0a0aed4ec 125 */
<> 150:02e0a0aed4ec 126 int SPIS_AbortAsync(spis_req_t *req);
<> 150:02e0a0aed4ec 127
<> 150:02e0a0aed4ec 128 /**
<> 150:02e0a0aed4ec 129 * @brief SPIS interrupt handler.
<> 150:02e0a0aed4ec 130 * @details This function should be called by the application from the interrupt
<> 150:02e0a0aed4ec 131 * handler if SPIS interrupts are enabled. Alternately, this function
<> 150:02e0a0aed4ec 132 * can be periodically called by the application if SPIS interrupts are
<> 150:02e0a0aed4ec 133 * disabled.
<> 150:02e0a0aed4ec 134 * @param spis Base address of the SPIS module.
<> 150:02e0a0aed4ec 135 */
<> 150:02e0a0aed4ec 136 void SPIS_Handler(mxc_spis_regs_t *spis);
<> 150:02e0a0aed4ec 137
<> 150:02e0a0aed4ec 138 /**
<> 150:02e0a0aed4ec 139 * @brief Check the SPIS to see if it's busy.
<> 150:02e0a0aed4ec 140 * @param spis Pointer to SPIS regs.
<> 150:02e0a0aed4ec 141 * @returns #E_NO_ERROR if idle, #E_BUSY if in use.
<> 150:02e0a0aed4ec 142 */
<> 150:02e0a0aed4ec 143 int SPIS_Busy(mxc_spis_regs_t *spis);
<> 150:02e0a0aed4ec 144
<> 150:02e0a0aed4ec 145 /**
<> 150:02e0a0aed4ec 146 * @brief Attempt to prepare the SPIS for sleep.
<> 150:02e0a0aed4ec 147 * @param spis Pointer to SPIS regs.
<> 150:02e0a0aed4ec 148 * @details Checks for any ongoing transactions. Disables interrupts if the SPIS
<> 150:02e0a0aed4ec 149 is idle.
<> 150:02e0a0aed4ec 150 * @returns #E_NO_ERROR if ready to sleep, #E_BUSY if not ready for sleep.
<> 150:02e0a0aed4ec 151 */
<> 150:02e0a0aed4ec 152 int SPIS_PrepForSleep(mxc_spis_regs_t *spis);
<> 150:02e0a0aed4ec 153
<> 150:02e0a0aed4ec 154 /**
<> 150:02e0a0aed4ec 155 * @brief Enables the SPIS without overwriting existing configuration.
<> 150:02e0a0aed4ec 156 * @param spis Pointer to SPIS regs.
<> 150:02e0a0aed4ec 157 */
<> 150:02e0a0aed4ec 158 __STATIC_INLINE void SPIS_Enable(mxc_spis_regs_t *spis)
<> 150:02e0a0aed4ec 159 {
<> 150:02e0a0aed4ec 160 spis->gen_ctrl |= (MXC_F_SPIS_GEN_CTRL_SPI_SLAVE_EN |
<> 150:02e0a0aed4ec 161 MXC_F_SPIS_GEN_CTRL_TX_FIFO_EN | MXC_F_SPIS_GEN_CTRL_RX_FIFO_EN);
<> 150:02e0a0aed4ec 162 }
<> 150:02e0a0aed4ec 163
<> 150:02e0a0aed4ec 164 /**
<> 150:02e0a0aed4ec 165 * @brief Drain all of the data in the RXFIFO.
<> 150:02e0a0aed4ec 166 * @param spis Pointer to UART regs.
<> 150:02e0a0aed4ec 167 */
<> 150:02e0a0aed4ec 168 __STATIC_INLINE void SPIS_DrainRX(mxc_spis_regs_t *spis)
<> 150:02e0a0aed4ec 169 {
<> 150:02e0a0aed4ec 170 uint32_t ctrl_save = spis->gen_ctrl;
<> 150:02e0a0aed4ec 171 spis->gen_ctrl = (ctrl_save & ~MXC_F_SPIS_GEN_CTRL_RX_FIFO_EN);
<> 150:02e0a0aed4ec 172 spis->gen_ctrl = ctrl_save;
<> 150:02e0a0aed4ec 173 }
<> 150:02e0a0aed4ec 174
<> 150:02e0a0aed4ec 175 /**
<> 150:02e0a0aed4ec 176 * @brief Drain all of the data in the TXFIFO.
<> 150:02e0a0aed4ec 177 * @param spis Pointer to UART regs.
<> 150:02e0a0aed4ec 178 */
<> 150:02e0a0aed4ec 179 __STATIC_INLINE void SPIS_DrainTX(mxc_spis_regs_t *spis)
<> 150:02e0a0aed4ec 180 {
<> 150:02e0a0aed4ec 181 uint32_t ctrl_save = spis->gen_ctrl;
<> 150:02e0a0aed4ec 182 spis->gen_ctrl = (ctrl_save & ~MXC_F_SPIS_GEN_CTRL_TX_FIFO_EN);
<> 150:02e0a0aed4ec 183 spis->gen_ctrl = ctrl_save;
<> 150:02e0a0aed4ec 184 }
<> 150:02e0a0aed4ec 185
<> 150:02e0a0aed4ec 186 /**
<> 150:02e0a0aed4ec 187 * @brief TX FIFO availability.
<> 150:02e0a0aed4ec 188 * @param spis Pointer to UART regs.
<> 150:02e0a0aed4ec 189 * @returns Number of empty bytes available in write FIFO.
<> 150:02e0a0aed4ec 190 */
<> 150:02e0a0aed4ec 191 __STATIC_INLINE unsigned SPIS_NumWriteAvail(mxc_spis_regs_t *spis)
<> 150:02e0a0aed4ec 192 {
<> 150:02e0a0aed4ec 193 return (MXC_CFG_SPIS_FIFO_DEPTH - ((spis->fifo_stat &
<> 150:02e0a0aed4ec 194 MXC_F_SPIS_FIFO_STAT_TX_FIFO_USED) >> MXC_F_SPIS_FIFO_STAT_TX_FIFO_USED_POS));
<> 150:02e0a0aed4ec 195 }
<> 150:02e0a0aed4ec 196
<> 150:02e0a0aed4ec 197 /**
<> 150:02e0a0aed4ec 198 * @brief RX FIFO availability.
<> 150:02e0a0aed4ec 199 * @param spis Pointer to UART regs.
<> 150:02e0a0aed4ec 200 * @returns Number of bytes in read FIFO.
<> 150:02e0a0aed4ec 201 */
<> 150:02e0a0aed4ec 202 __STATIC_INLINE unsigned SPIS_NumReadAvail(mxc_spis_regs_t *spis)
<> 150:02e0a0aed4ec 203 {
<> 150:02e0a0aed4ec 204 return ((spis->fifo_stat & MXC_F_SPIS_FIFO_STAT_RX_FIFO_USED) >>
<> 150:02e0a0aed4ec 205 MXC_F_SPIS_FIFO_STAT_RX_FIFO_USED_POS);
<> 150:02e0a0aed4ec 206 }
<> 150:02e0a0aed4ec 207
<> 150:02e0a0aed4ec 208 /**
<> 150:02e0a0aed4ec 209 * @brief Clear interrupt flags.
<> 150:02e0a0aed4ec 210 * @param spis Pointer to SPIS regs.
<> 150:02e0a0aed4ec 211 * @param mask Mask of interrupts to clear.
<> 150:02e0a0aed4ec 212 */
<> 150:02e0a0aed4ec 213 __STATIC_INLINE void SPIS_ClearFlags(mxc_spis_regs_t *spis, uint32_t mask)
<> 150:02e0a0aed4ec 214 {
<> 150:02e0a0aed4ec 215 spis->intfl = mask;
<> 150:02e0a0aed4ec 216 }
<> 150:02e0a0aed4ec 217
<> 150:02e0a0aed4ec 218 /**
<> 150:02e0a0aed4ec 219 * @brief Get interrupt flags.
<> 150:02e0a0aed4ec 220 * @param spis Pointer to SPIS regs.
<> 150:02e0a0aed4ec 221 * @returns Mask of active flags.
<> 150:02e0a0aed4ec 222 */
<> 150:02e0a0aed4ec 223 __STATIC_INLINE unsigned SPIS_GetFlags(mxc_spis_regs_t *spis)
<> 150:02e0a0aed4ec 224 {
<> 150:02e0a0aed4ec 225 return (spis->intfl);
<> 150:02e0a0aed4ec 226 }
<> 150:02e0a0aed4ec 227
<> 150:02e0a0aed4ec 228 #ifdef __cplusplus
<> 150:02e0a0aed4ec 229 }
<> 150:02e0a0aed4ec 230 #endif
<> 150:02e0a0aed4ec 231
<> 150:02e0a0aed4ec 232 #endif /* _SPIS_H_ */