rik te winkel / mbed-dev

Forked mbed-dev as I use an 20 pins stm32F042 and not the 32 pins version

Dependents:   Numitron_clock

Fork of mbed-dev by mbed official

targets/TARGET_Maxim/TARGET_MAX32625/mxc/pt.c@153:0a78729d3229, 2017-01-22 (annotated)

Committer:
riktw
Date:
Sun Jan 22 22:20:36 2017 +0000
Revision:
153:0a78729d3229
Parent:
150:02e0a0aed4ec 
Back to 8Mhz clock. Revision 1.0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 150:02e0a0aed4ec 1 /*******************************************************************************
<> 150:02e0a0aed4ec 2 * Copyright (C) 2016 Maxim Integrated Products, Inc., All Rights Reserved.
<> 150:02e0a0aed4ec 3 *
<> 150:02e0a0aed4ec 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 150:02e0a0aed4ec 5 * copy of this software and associated documentation files (the "Software"),
<> 150:02e0a0aed4ec 6 * to deal in the Software without restriction, including without limitation
<> 150:02e0a0aed4ec 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 150:02e0a0aed4ec 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 150:02e0a0aed4ec 9 * Software is furnished to do so, subject to the following conditions:
<> 150:02e0a0aed4ec 10 *
<> 150:02e0a0aed4ec 11 * The above copyright notice and this permission notice shall be included
<> 150:02e0a0aed4ec 12 * in all copies or substantial portions of the Software.
<> 150:02e0a0aed4ec 13 *
<> 150:02e0a0aed4ec 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 150:02e0a0aed4ec 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 150:02e0a0aed4ec 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 150:02e0a0aed4ec 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 150:02e0a0aed4ec 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 150:02e0a0aed4ec 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 150:02e0a0aed4ec 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 150:02e0a0aed4ec 21 *
<> 150:02e0a0aed4ec 22 * Except as contained in this notice, the name of Maxim Integrated
<> 150:02e0a0aed4ec 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 150:02e0a0aed4ec 24 * Products, Inc. Branding Policy.
<> 150:02e0a0aed4ec 25 *
<> 150:02e0a0aed4ec 26 * The mere transfer of this software does not imply any licenses
<> 150:02e0a0aed4ec 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 150:02e0a0aed4ec 28 * trademarks, maskwork rights, or any other form of intellectual
<> 150:02e0a0aed4ec 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 150:02e0a0aed4ec 30 * ownership rights.
<> 150:02e0a0aed4ec 31 *
<> 150:02e0a0aed4ec 32 * $Date: 2016-03-11 11:46:37 -0600 (Fri, 11 Mar 2016) $
<> 150:02e0a0aed4ec 33 * $Revision: 21839 $
<> 150:02e0a0aed4ec 34 *
<> 150:02e0a0aed4ec 35 ******************************************************************************/
<> 150:02e0a0aed4ec 36
<> 150:02e0a0aed4ec 37 #include <stddef.h>
<> 150:02e0a0aed4ec 38 #include "pt.h"
<> 150:02e0a0aed4ec 39
<> 150:02e0a0aed4ec 40 /******************************************************************************/
<> 150:02e0a0aed4ec 41 void PT_Init(sys_pt_clk_scale clk_scale)
<> 150:02e0a0aed4ec 42 {
<> 150:02e0a0aed4ec 43 //disable all pulse trains
<> 150:02e0a0aed4ec 44 MXC_PTG->enable = 0;
<> 150:02e0a0aed4ec 45
<> 150:02e0a0aed4ec 46 //clear all interrupts
<> 150:02e0a0aed4ec 47 MXC_PTG->intfl = MXC_PTG->intfl;
<> 150:02e0a0aed4ec 48
<> 150:02e0a0aed4ec 49 SYS_PT_Init(clk_scale);
<> 150:02e0a0aed4ec 50 }
<> 150:02e0a0aed4ec 51
<> 150:02e0a0aed4ec 52 /******************************************************************************/
<> 150:02e0a0aed4ec 53 int PT_PTConfig(mxc_pt_regs_t *pt, pt_pt_cfg_t *cfg, const sys_cfg_pt_t *sysCfg)
<> 150:02e0a0aed4ec 54 {
<> 150:02e0a0aed4ec 55 int err;
<> 150:02e0a0aed4ec 56 uint32_t ptClock;
<> 150:02e0a0aed4ec 57 uint32_t rate;
<> 150:02e0a0aed4ec 58
<> 150:02e0a0aed4ec 59 //check for valid base pointer
<> 150:02e0a0aed4ec 60 MXC_ASSERT(MXC_PT_GET_IDX(pt) >= 0);
<> 150:02e0a0aed4ec 61
<> 150:02e0a0aed4ec 62 if(cfg == NULL)
<> 150:02e0a0aed4ec 63 return E_NULL_PTR;
<> 150:02e0a0aed4ec 64
<> 150:02e0a0aed4ec 65 if(cfg->bps == 0)
<> 150:02e0a0aed4ec 66 return E_BAD_PARAM;
<> 150:02e0a0aed4ec 67
<> 150:02e0a0aed4ec 68 //disable pulse train
<> 150:02e0a0aed4ec 69 PT_Stop(pt);
<> 150:02e0a0aed4ec 70
<> 150:02e0a0aed4ec 71 //setup system GPIO configuration
<> 150:02e0a0aed4ec 72 if((err = SYS_PT_Config(pt, sysCfg)) != E_NO_ERROR)
<> 150:02e0a0aed4ec 73 return err;
<> 150:02e0a0aed4ec 74
<> 150:02e0a0aed4ec 75 //get PT clock frequency from SYS level
<> 150:02e0a0aed4ec 76 ptClock = SYS_PT_GetFreq();
<> 150:02e0a0aed4ec 77
<> 150:02e0a0aed4ec 78 if(ptClock == 0)
<> 150:02e0a0aed4ec 79 return E_UNINITIALIZED;
<> 150:02e0a0aed4ec 80
<> 150:02e0a0aed4ec 81 if(ptClock < (cfg->bps))
<> 150:02e0a0aed4ec 82 return E_BAD_STATE;
<> 150:02e0a0aed4ec 83
<> 150:02e0a0aed4ec 84 rate = (ptClock / (cfg->bps));
<> 150:02e0a0aed4ec 85
<> 150:02e0a0aed4ec 86 pt->rate_length = ((rate << MXC_F_PT_RATE_LENGTH_RATE_CONTROL_POS)
<> 150:02e0a0aed4ec 87 & MXC_F_PT_RATE_LENGTH_RATE_CONTROL) |
<> 150:02e0a0aed4ec 88 ((cfg->ptLength << MXC_F_PT_RATE_LENGTH_MODE_POS)
<> 150:02e0a0aed4ec 89 & MXC_F_PT_RATE_LENGTH_MODE);
<> 150:02e0a0aed4ec 90
<> 150:02e0a0aed4ec 91 pt->train = cfg->pattern;
<> 150:02e0a0aed4ec 92 pt->loop = ((cfg->loop << MXC_F_PT_LOOP_COUNT_POS) & MXC_F_PT_LOOP_COUNT) |
<> 150:02e0a0aed4ec 93 ((cfg->loopDelay << MXC_F_PT_LOOP_DELAY_POS) & MXC_F_PT_LOOP_DELAY);
<> 150:02e0a0aed4ec 94
<> 150:02e0a0aed4ec 95 return E_NO_ERROR;
<> 150:02e0a0aed4ec 96 }
<> 150:02e0a0aed4ec 97
<> 150:02e0a0aed4ec 98 /******************************************************************************/
<> 150:02e0a0aed4ec 99 int PT_SqrWaveConfig(mxc_pt_regs_t *pt, uint32_t freq, const sys_cfg_pt_t *sysCfg)
<> 150:02e0a0aed4ec 100 {
<> 150:02e0a0aed4ec 101 int err;
<> 150:02e0a0aed4ec 102 uint32_t ptClock;
<> 150:02e0a0aed4ec 103 uint32_t rate;
<> 150:02e0a0aed4ec 104
<> 150:02e0a0aed4ec 105 //check for valid base pointer
<> 150:02e0a0aed4ec 106 MXC_ASSERT(MXC_PT_GET_IDX(pt) >= 0);
<> 150:02e0a0aed4ec 107
<> 150:02e0a0aed4ec 108 if(freq == 0)
<> 150:02e0a0aed4ec 109 return E_BAD_PARAM;
<> 150:02e0a0aed4ec 110
<> 150:02e0a0aed4ec 111 //disable pulse train
<> 150:02e0a0aed4ec 112 PT_Stop(pt);
<> 150:02e0a0aed4ec 113
<> 150:02e0a0aed4ec 114 //setup system GPIO configuration
<> 150:02e0a0aed4ec 115 if((err = SYS_PT_Config(pt, sysCfg)) != E_NO_ERROR)
<> 150:02e0a0aed4ec 116 return err;
<> 150:02e0a0aed4ec 117
<> 150:02e0a0aed4ec 118 //get PT clock frequency from SYS level
<> 150:02e0a0aed4ec 119 ptClock = SYS_PT_GetFreq();
<> 150:02e0a0aed4ec 120
<> 150:02e0a0aed4ec 121 if(ptClock == 0)
<> 150:02e0a0aed4ec 122 return E_UNINITIALIZED;
<> 150:02e0a0aed4ec 123
<> 150:02e0a0aed4ec 124 if(ptClock < (2*freq))
<> 150:02e0a0aed4ec 125 return E_BAD_STATE;
<> 150:02e0a0aed4ec 126
<> 150:02e0a0aed4ec 127 rate = (ptClock / (2*freq)) + 1;
<> 150:02e0a0aed4ec 128
<> 150:02e0a0aed4ec 129 pt->rate_length = ((rate << MXC_F_PT_RATE_LENGTH_RATE_CONTROL_POS)
<> 150:02e0a0aed4ec 130 & MXC_F_PT_RATE_LENGTH_RATE_CONTROL) |
<> 150:02e0a0aed4ec 131 (MXC_V_PT_RATE_LENGTH_MODE_SQUARE_WAVE << MXC_F_PT_RATE_LENGTH_MODE_POS);
<> 150:02e0a0aed4ec 132
<> 150:02e0a0aed4ec 133 return E_NO_ERROR;
<> 150:02e0a0aed4ec 134 }