rik te winkel / mbed-dev

Forked mbed-dev as I use an 20 pins stm32F042 and not the 32 pins version

Dependents:   Numitron_clock

Fork of mbed-dev by mbed official

targets/TARGET_Maxim/TARGET_MAX32610/rtc_api.c@153:0a78729d3229, 2017-01-22 (annotated)

Committer:
riktw
Date:
Sun Jan 22 22:20:36 2017 +0000
Revision:
153:0a78729d3229
Parent:
149:156823d33999 
Back to 8Mhz clock. Revision 1.0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*******************************************************************************
<> 144:ef7eb2e8f9f7 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 144:ef7eb2e8f9f7 5 * copy of this software and associated documentation files (the "Software"),
<> 144:ef7eb2e8f9f7 6 * to deal in the Software without restriction, including without limitation
<> 144:ef7eb2e8f9f7 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 144:ef7eb2e8f9f7 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 144:ef7eb2e8f9f7 9 * Software is furnished to do so, subject to the following conditions:
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * The above copyright notice and this permission notice shall be included
<> 144:ef7eb2e8f9f7 12 * in all copies or substantial portions of the Software.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 144:ef7eb2e8f9f7 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 144:ef7eb2e8f9f7 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 144:ef7eb2e8f9f7 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 144:ef7eb2e8f9f7 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 144:ef7eb2e8f9f7 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * Except as contained in this notice, the name of Maxim Integrated
<> 144:ef7eb2e8f9f7 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 144:ef7eb2e8f9f7 24 * Products, Inc. Branding Policy.
<> 144:ef7eb2e8f9f7 25 *
<> 144:ef7eb2e8f9f7 26 * The mere transfer of this software does not imply any licenses
<> 144:ef7eb2e8f9f7 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 144:ef7eb2e8f9f7 28 * trademarks, maskwork rights, or any other form of intellectual
<> 144:ef7eb2e8f9f7 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 144:ef7eb2e8f9f7 30 * ownership rights.
<> 144:ef7eb2e8f9f7 31 *******************************************************************************
<> 144:ef7eb2e8f9f7 32 */
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #include "rtc_api.h"
<> 144:ef7eb2e8f9f7 35 #include "lp_ticker_api.h"
<> 144:ef7eb2e8f9f7 36 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 37 #include "rtc_regs.h"
<> 144:ef7eb2e8f9f7 38 #include "pwrseq_regs.h"
<> 144:ef7eb2e8f9f7 39 #include "clkman_regs.h"
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 #define PRESCALE_VAL MXC_E_RTC_PRESCALE_DIV_2_0 // Set the divider for the 4kHz clock
<> 144:ef7eb2e8f9f7 42 #define SHIFT_AMT (MXC_E_RTC_PRESCALE_DIV_2_12 - PRESCALE_VAL)
<> 144:ef7eb2e8f9f7 43
<> 144:ef7eb2e8f9f7 44 #define WINDOW 1000
<> 144:ef7eb2e8f9f7 45
<> 144:ef7eb2e8f9f7 46 static int rtc_inited = 0;
<> 144:ef7eb2e8f9f7 47 static volatile uint32_t overflow_cnt = 0;
<> 144:ef7eb2e8f9f7 48
<> 144:ef7eb2e8f9f7 49 static uint64_t rtc_read64(void);
<> 144:ef7eb2e8f9f7 50
<> 144:ef7eb2e8f9f7 51 //******************************************************************************
<> 144:ef7eb2e8f9f7 52 static void overflow_handler(void)
<> 144:ef7eb2e8f9f7 53 {
<> 144:ef7eb2e8f9f7 54 MXC_RTCTMR->flags = MXC_F_RTC_FLAGS_OVERFLOW;
<> 144:ef7eb2e8f9f7 55 MXC_PWRSEQ->flags = MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER;
<> 144:ef7eb2e8f9f7 56 overflow_cnt++;
<> 144:ef7eb2e8f9f7 57 }
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 //******************************************************************************
<> 144:ef7eb2e8f9f7 60 void rtc_init(void)
<> 144:ef7eb2e8f9f7 61 {
<> 144:ef7eb2e8f9f7 62 if (rtc_inited) {
<> 144:ef7eb2e8f9f7 63 return;
<> 144:ef7eb2e8f9f7 64 }
<> 144:ef7eb2e8f9f7 65 rtc_inited = 1;
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 overflow_cnt = 0;
<> 144:ef7eb2e8f9f7 68
<> 144:ef7eb2e8f9f7 69 // Enable the clock to the synchronizer
<> 144:ef7eb2e8f9f7 70 MXC_CLKMAN->clk_ctrl_13_rtc_int_sync = MXC_E_CLKMAN_CLK_SCALE_ENABLED;
<> 144:ef7eb2e8f9f7 71
<> 144:ef7eb2e8f9f7 72 // Enable the clock to the RTC
<> 144:ef7eb2e8f9f7 73 MXC_PWRSEQ->reg0 |= MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN;
<> 144:ef7eb2e8f9f7 74
<> 144:ef7eb2e8f9f7 75 // Prepare interrupt handlers
<> 144:ef7eb2e8f9f7 76 NVIC_SetVector(RTC0_IRQn, (uint32_t)lp_ticker_irq_handler);
<> 144:ef7eb2e8f9f7 77 NVIC_EnableIRQ(RTC0_IRQn);
<> 144:ef7eb2e8f9f7 78 NVIC_SetVector(RTC3_IRQn, (uint32_t)overflow_handler);
<> 144:ef7eb2e8f9f7 79 NVIC_EnableIRQ(RTC3_IRQn);
<> 144:ef7eb2e8f9f7 80
<> 144:ef7eb2e8f9f7 81 // Enable wakeup on RTC rollover
<> 144:ef7eb2e8f9f7 82 MXC_PWRSEQ->msk_flags &= ~MXC_F_PWRSEQ_MSK_FLAGS_RTC_ROLLOVER;
<> 144:ef7eb2e8f9f7 83
<> 144:ef7eb2e8f9f7 84 /* RTC registers are only reset on a power cycle. Do not reconfigure the RTC
<> 144:ef7eb2e8f9f7 85 * if it is already running.
<> 144:ef7eb2e8f9f7 86 */
<> 144:ef7eb2e8f9f7 87 if (!(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_ENABLE)) {
<> 144:ef7eb2e8f9f7 88 // Set the clock divider
<> 144:ef7eb2e8f9f7 89 MXC_RTCTMR->prescale = PRESCALE_VAL;
<> 144:ef7eb2e8f9f7 90
<> 144:ef7eb2e8f9f7 91 // Enable the overflow interrupt
<> 144:ef7eb2e8f9f7 92 MXC_RTCTMR->inten |= MXC_F_RTC_FLAGS_OVERFLOW;
<> 144:ef7eb2e8f9f7 93
<> 144:ef7eb2e8f9f7 94 // Restart the timer from 0
<> 144:ef7eb2e8f9f7 95 MXC_RTCTMR->timer = 0;
<> 144:ef7eb2e8f9f7 96
<> 144:ef7eb2e8f9f7 97 // Enable the RTC
<> 144:ef7eb2e8f9f7 98 MXC_RTCTMR->ctrl |= MXC_F_RTC_CTRL_ENABLE;
<> 144:ef7eb2e8f9f7 99 }
<> 144:ef7eb2e8f9f7 100 }
<> 144:ef7eb2e8f9f7 101
<> 144:ef7eb2e8f9f7 102 //******************************************************************************
<> 144:ef7eb2e8f9f7 103 void lp_ticker_init(void)
<> 144:ef7eb2e8f9f7 104 {
<> 144:ef7eb2e8f9f7 105 rtc_init();
<> 144:ef7eb2e8f9f7 106 }
<> 144:ef7eb2e8f9f7 107
<> 144:ef7eb2e8f9f7 108 //******************************************************************************
<> 144:ef7eb2e8f9f7 109 void rtc_free(void)
<> 144:ef7eb2e8f9f7 110 {
<> 144:ef7eb2e8f9f7 111 if (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_ENABLE) {
<> 144:ef7eb2e8f9f7 112 // Clear and disable RTC
<> 144:ef7eb2e8f9f7 113 MXC_RTCTMR->ctrl |= MXC_F_RTC_CTRL_CLEAR;
<> 144:ef7eb2e8f9f7 114 MXC_RTCTMR->ctrl &= ~MXC_F_RTC_CTRL_ENABLE;
<> 144:ef7eb2e8f9f7 115
<> 144:ef7eb2e8f9f7 116 // Wait for pending transactions
<> 144:ef7eb2e8f9f7 117 while(MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_PENDING);
<> 144:ef7eb2e8f9f7 118 }
<> 144:ef7eb2e8f9f7 119
<> 144:ef7eb2e8f9f7 120 // Disable the clock to the RTC
<> 144:ef7eb2e8f9f7 121 MXC_PWRSEQ->reg0 &= ~(MXC_F_PWRSEQ_REG0_PWR_RTCEN_RUN | MXC_F_PWRSEQ_REG0_PWR_RTCEN_SLP);
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 // Disable the clock to the synchronizer
<> 144:ef7eb2e8f9f7 124 MXC_CLKMAN->clk_ctrl_13_rtc_int_sync = MXC_E_CLKMAN_CLK_SCALE_DISABLED;
<> 144:ef7eb2e8f9f7 125 }
<> 144:ef7eb2e8f9f7 126
<> 144:ef7eb2e8f9f7 127 //******************************************************************************
<> 144:ef7eb2e8f9f7 128 int rtc_isenabled(void)
<> 144:ef7eb2e8f9f7 129 {
<> 144:ef7eb2e8f9f7 130 return (MXC_RTCTMR->ctrl & MXC_F_RTC_CTRL_ENABLE);
<> 144:ef7eb2e8f9f7 131 }
<> 144:ef7eb2e8f9f7 132
<> 144:ef7eb2e8f9f7 133 //******************************************************************************
<> 144:ef7eb2e8f9f7 134 time_t rtc_read(void)
<> 144:ef7eb2e8f9f7 135 {
<> 144:ef7eb2e8f9f7 136 uint32_t ovf_cnt_1, ovf_cnt_2, timer_cnt;
<> 144:ef7eb2e8f9f7 137 uint32_t ovf1, ovf2;
<> 144:ef7eb2e8f9f7 138
<> 144:ef7eb2e8f9f7 139 // Ensure coherency between overflow_cnt and timer
<> 144:ef7eb2e8f9f7 140 do {
<> 144:ef7eb2e8f9f7 141 ovf_cnt_1 = overflow_cnt;
<> 144:ef7eb2e8f9f7 142 ovf1 = MXC_RTCTMR->flags & MXC_F_RTC_FLAGS_OVERFLOW;
<> 144:ef7eb2e8f9f7 143 timer_cnt = MXC_RTCTMR->timer;
<> 144:ef7eb2e8f9f7 144 ovf2 = MXC_RTCTMR->flags & MXC_F_RTC_FLAGS_OVERFLOW;
<> 144:ef7eb2e8f9f7 145 ovf_cnt_2 = overflow_cnt;
<> 144:ef7eb2e8f9f7 146 } while ((ovf_cnt_1 != ovf_cnt_2) || (ovf1 != ovf2));
<> 144:ef7eb2e8f9f7 147
<> 144:ef7eb2e8f9f7 148 // Account for an unserviced interrupt
<> 144:ef7eb2e8f9f7 149 if (ovf1) {
<> 144:ef7eb2e8f9f7 150 ovf_cnt_1++;
<> 144:ef7eb2e8f9f7 151 }
<> 144:ef7eb2e8f9f7 152
<> 144:ef7eb2e8f9f7 153 return (timer_cnt >> SHIFT_AMT) + (ovf_cnt_1 << (32 - SHIFT_AMT));
<> 144:ef7eb2e8f9f7 154 }
<> 144:ef7eb2e8f9f7 155
<> 144:ef7eb2e8f9f7 156 //******************************************************************************
<> 144:ef7eb2e8f9f7 157 static uint64_t rtc_read64(void)
<> 144:ef7eb2e8f9f7 158 {
<> 144:ef7eb2e8f9f7 159 uint32_t ovf_cnt_1, ovf_cnt_2, timer_cnt;
<> 144:ef7eb2e8f9f7 160 uint32_t ovf1, ovf2;
<> 144:ef7eb2e8f9f7 161 uint64_t current_us;
<> 144:ef7eb2e8f9f7 162
<> 144:ef7eb2e8f9f7 163 // Ensure coherency between overflow_cnt and timer
<> 144:ef7eb2e8f9f7 164 do {
<> 144:ef7eb2e8f9f7 165 ovf_cnt_1 = overflow_cnt;
<> 144:ef7eb2e8f9f7 166 ovf1 = MXC_RTCTMR->flags & MXC_F_RTC_FLAGS_OVERFLOW;
<> 144:ef7eb2e8f9f7 167 timer_cnt = MXC_RTCTMR->timer;
<> 144:ef7eb2e8f9f7 168 ovf2 = MXC_RTCTMR->flags & MXC_F_RTC_FLAGS_OVERFLOW;
<> 144:ef7eb2e8f9f7 169 ovf_cnt_2 = overflow_cnt;
<> 144:ef7eb2e8f9f7 170 } while ((ovf_cnt_1 != ovf_cnt_2) || (ovf1 != ovf2));
<> 144:ef7eb2e8f9f7 171
<> 144:ef7eb2e8f9f7 172 // Account for an unserviced interrupt
<> 144:ef7eb2e8f9f7 173 if (ovf1) {
<> 144:ef7eb2e8f9f7 174 ovf_cnt_1++;
<> 144:ef7eb2e8f9f7 175 }
<> 144:ef7eb2e8f9f7 176
<> 144:ef7eb2e8f9f7 177 current_us = (((uint64_t)timer_cnt * 1000000) >> SHIFT_AMT) + (((uint64_t)ovf_cnt_1 * 1000000) << (32 - SHIFT_AMT));
<> 144:ef7eb2e8f9f7 178
<> 144:ef7eb2e8f9f7 179 return current_us;
<> 144:ef7eb2e8f9f7 180 }
<> 144:ef7eb2e8f9f7 181
<> 144:ef7eb2e8f9f7 182 //******************************************************************************
<> 144:ef7eb2e8f9f7 183 void rtc_write(time_t t)
<> 144:ef7eb2e8f9f7 184 {
<> 144:ef7eb2e8f9f7 185 MXC_RTCTMR->ctrl &= ~MXC_F_RTC_CTRL_ENABLE; // disable the timer while updating
<> 144:ef7eb2e8f9f7 186 MXC_RTCTMR->timer = t << SHIFT_AMT;
<> 144:ef7eb2e8f9f7 187 overflow_cnt = t >> (32 - SHIFT_AMT);
<> 144:ef7eb2e8f9f7 188 MXC_RTCTMR->ctrl |= MXC_F_RTC_CTRL_ENABLE; // enable the timer while updating
<> 144:ef7eb2e8f9f7 189 }
<> 144:ef7eb2e8f9f7 190
<> 144:ef7eb2e8f9f7 191 //******************************************************************************
<> 144:ef7eb2e8f9f7 192 void lp_ticker_set_interrupt(timestamp_t timestamp)
<> 144:ef7eb2e8f9f7 193 {
<> 144:ef7eb2e8f9f7 194 uint32_t comp_value;
<> 144:ef7eb2e8f9f7 195 uint64_t curr_ts64;
<> 144:ef7eb2e8f9f7 196 uint64_t ts64;
<> 144:ef7eb2e8f9f7 197
<> 144:ef7eb2e8f9f7 198 // Note: interrupts are disabled before this function is called.
<> 144:ef7eb2e8f9f7 199
<> 144:ef7eb2e8f9f7 200 // Disable the alarm while it is prepared
<> 144:ef7eb2e8f9f7 201 MXC_RTCTMR->inten &= ~MXC_F_RTC_INTEN_COMP0;
<> 144:ef7eb2e8f9f7 202
<> 144:ef7eb2e8f9f7 203 curr_ts64 = rtc_read64();
<> 144:ef7eb2e8f9f7 204 ts64 = (uint64_t)timestamp | (curr_ts64 & 0xFFFFFFFF00000000ULL);
<> 144:ef7eb2e8f9f7 205
<> 144:ef7eb2e8f9f7 206 // If this event is older than a recent window, it must be in the future
<> 144:ef7eb2e8f9f7 207 if ((ts64 < (curr_ts64 - WINDOW)) && ((curr_ts64 - WINDOW) < curr_ts64)) {
<> 144:ef7eb2e8f9f7 208 ts64 += 0x100000000ULL;
<> 144:ef7eb2e8f9f7 209 }
<> 144:ef7eb2e8f9f7 210
<> 144:ef7eb2e8f9f7 211 uint32_t timer = MXC_RTCTMR->timer;
<> 144:ef7eb2e8f9f7 212 if (ts64 <= curr_ts64) {
<> 144:ef7eb2e8f9f7 213 // This event has already occurred. Set the alarm to expire immediately.
<> 144:ef7eb2e8f9f7 214 comp_value = timer + 1;
<> 144:ef7eb2e8f9f7 215 } else {
<> 144:ef7eb2e8f9f7 216 comp_value = (ts64 << SHIFT_AMT) / 1000000;
<> 144:ef7eb2e8f9f7 217 }
<> 144:ef7eb2e8f9f7 218
<> 144:ef7eb2e8f9f7 219 // Ensure that the compare value is far enough in the future to guarantee the interrupt occurs.
<> 144:ef7eb2e8f9f7 220 if ((comp_value < (timer + 2)) && (comp_value > (timer - 10))) {
<> 144:ef7eb2e8f9f7 221 comp_value = timer + 2;
<> 144:ef7eb2e8f9f7 222 }
<> 144:ef7eb2e8f9f7 223
<> 144:ef7eb2e8f9f7 224 MXC_RTCTMR->comp[0] = comp_value;
<> 144:ef7eb2e8f9f7 225 MXC_RTCTMR->flags = MXC_F_RTC_FLAGS_COMP0; // clear interrupt
<> 144:ef7eb2e8f9f7 226 MXC_RTCTMR->inten |= MXC_F_RTC_INTEN_COMP0; // enable the interrupt
<> 144:ef7eb2e8f9f7 227
<> 144:ef7eb2e8f9f7 228 // Enable wakeup from RTC
<> 144:ef7eb2e8f9f7 229 MXC_PWRSEQ->msk_flags &= ~MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0;
<> 144:ef7eb2e8f9f7 230 }
<> 144:ef7eb2e8f9f7 231
<> 144:ef7eb2e8f9f7 232 //******************************************************************************
<> 144:ef7eb2e8f9f7 233 inline void lp_ticker_disable_interrupt(void)
<> 144:ef7eb2e8f9f7 234 {
<> 144:ef7eb2e8f9f7 235 MXC_RTCTMR->inten &= ~MXC_F_RTC_INTEN_COMP0;
<> 144:ef7eb2e8f9f7 236 }
<> 144:ef7eb2e8f9f7 237
<> 144:ef7eb2e8f9f7 238 //******************************************************************************
<> 144:ef7eb2e8f9f7 239 inline void lp_ticker_clear_interrupt(void)
<> 144:ef7eb2e8f9f7 240 {
<> 144:ef7eb2e8f9f7 241 MXC_RTCTMR->flags = MXC_F_RTC_FLAGS_ASYNC_CLR_FLAGS;
<> 144:ef7eb2e8f9f7 242 MXC_PWRSEQ->flags = MXC_F_PWRSEQ_MSK_FLAGS_RTC_CMPR0;
<> 144:ef7eb2e8f9f7 243 }
<> 144:ef7eb2e8f9f7 244
<> 144:ef7eb2e8f9f7 245 //******************************************************************************
<> 144:ef7eb2e8f9f7 246 inline uint32_t lp_ticker_read(void)
<> 144:ef7eb2e8f9f7 247 {
<> 144:ef7eb2e8f9f7 248 return rtc_read64();
<> 144:ef7eb2e8f9f7 249 }