rik te winkel / mbed-dev

Forked mbed-dev as I use an 20 pins stm32F042 and not the 32 pins version

Dependents:   Numitron_clock

Fork of mbed-dev by mbed official

targets/TARGET_Maxim/TARGET_MAX32610/analogin_api.c@153:0a78729d3229, 2017-01-22 (annotated)

Committer:
riktw
Date:
Sun Jan 22 22:20:36 2017 +0000
Revision:
153:0a78729d3229
Parent:
149:156823d33999 
Back to 8Mhz clock. Revision 1.0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /*******************************************************************************
<> 144:ef7eb2e8f9f7 2 * Copyright (C) 2015 Maxim Integrated Products, Inc., All Rights Reserved.
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Permission is hereby granted, free of charge, to any person obtaining a
<> 144:ef7eb2e8f9f7 5 * copy of this software and associated documentation files (the "Software"),
<> 144:ef7eb2e8f9f7 6 * to deal in the Software without restriction, including without limitation
<> 144:ef7eb2e8f9f7 7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
<> 144:ef7eb2e8f9f7 8 * and/or sell copies of the Software, and to permit persons to whom the
<> 144:ef7eb2e8f9f7 9 * Software is furnished to do so, subject to the following conditions:
<> 144:ef7eb2e8f9f7 10 *
<> 144:ef7eb2e8f9f7 11 * The above copyright notice and this permission notice shall be included
<> 144:ef7eb2e8f9f7 12 * in all copies or substantial portions of the Software.
<> 144:ef7eb2e8f9f7 13 *
<> 144:ef7eb2e8f9f7 14 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
<> 144:ef7eb2e8f9f7 15 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
<> 144:ef7eb2e8f9f7 16 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
<> 144:ef7eb2e8f9f7 17 * IN NO EVENT SHALL MAXIM INTEGRATED BE LIABLE FOR ANY CLAIM, DAMAGES
<> 144:ef7eb2e8f9f7 18 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
<> 144:ef7eb2e8f9f7 19 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
<> 144:ef7eb2e8f9f7 20 * OTHER DEALINGS IN THE SOFTWARE.
<> 144:ef7eb2e8f9f7 21 *
<> 144:ef7eb2e8f9f7 22 * Except as contained in this notice, the name of Maxim Integrated
<> 144:ef7eb2e8f9f7 23 * Products, Inc. shall not be used except as stated in the Maxim Integrated
<> 144:ef7eb2e8f9f7 24 * Products, Inc. Branding Policy.
<> 144:ef7eb2e8f9f7 25 *
<> 144:ef7eb2e8f9f7 26 * The mere transfer of this software does not imply any licenses
<> 144:ef7eb2e8f9f7 27 * of trade secrets, proprietary technology, copyrights, patents,
<> 144:ef7eb2e8f9f7 28 * trademarks, maskwork rights, or any other form of intellectual
<> 144:ef7eb2e8f9f7 29 * property whatsoever. Maxim Integrated Products, Inc. retains all
<> 144:ef7eb2e8f9f7 30 * ownership rights.
<> 144:ef7eb2e8f9f7 31 *******************************************************************************
<> 144:ef7eb2e8f9f7 32 */
<> 144:ef7eb2e8f9f7 33
<> 144:ef7eb2e8f9f7 34 #include "mbed_assert.h"
<> 144:ef7eb2e8f9f7 35 #include "analogin_api.h"
<> 144:ef7eb2e8f9f7 36 #include "clkman_regs.h"
<> 144:ef7eb2e8f9f7 37 #include "pwrman_regs.h"
<> 144:ef7eb2e8f9f7 38 #include "afe_regs.h"
<> 144:ef7eb2e8f9f7 39 #include "PeripheralPins.h"
<> 144:ef7eb2e8f9f7 40
<> 144:ef7eb2e8f9f7 41 #define PGA_TRK_CNT 0x1F
<> 144:ef7eb2e8f9f7 42 #define ADC_ACT_CNT 0x1
<> 144:ef7eb2e8f9f7 43 #define ADC_PGA_CNT 0x1
<> 144:ef7eb2e8f9f7 44 #define ADC_ACQ_CNT 0x1
<> 144:ef7eb2e8f9f7 45 #define ADC_SLP_CNT 0x1
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 //******************************************************************************
<> 144:ef7eb2e8f9f7 48 void analogin_init(analogin_t *obj, PinName pin)
<> 144:ef7eb2e8f9f7 49 {
<> 144:ef7eb2e8f9f7 50 // Make sure pin is an analog pin we can use for ADC
<> 144:ef7eb2e8f9f7 51 MBED_ASSERT((ADCName)pinmap_peripheral(pin, PinMap_ADC) != (ADCName)NC);
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 // Set the object pointer
<> 144:ef7eb2e8f9f7 54 obj->adc = MXC_ADC;
<> 144:ef7eb2e8f9f7 55 obj->adccfg = MXC_ADCCFG;
<> 144:ef7eb2e8f9f7 56 obj->adc_fifo = MXC_ADC_FIFO;
<> 144:ef7eb2e8f9f7 57 obj->adc_pin = pin;
<> 144:ef7eb2e8f9f7 58
<> 144:ef7eb2e8f9f7 59 // Set the ADC clock to the system clock frequency
<> 144:ef7eb2e8f9f7 60 MXC_SET_FIELD(&MXC_CLKMAN->clk_ctrl, MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT,
<> 144:ef7eb2e8f9f7 61 (MXC_F_CLKMAN_CLK_CTRL_ADC_GATE_N | (MXC_E_CLKMAN_ADC_SOURCE_SELECT_SYSTEM <<
<> 144:ef7eb2e8f9f7 62 MXC_F_CLKMAN_CLK_CTRL_ADC_SOURCE_SELECT_POS)));
<> 144:ef7eb2e8f9f7 63
<> 144:ef7eb2e8f9f7 64 // Enable AFE power
<> 144:ef7eb2e8f9f7 65 MXC_PWRMAN->pwr_rst_ctrl |= MXC_F_PWRMAN_PWR_RST_CTRL_AFE_POWERED;
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 // Setup and hold window
<> 144:ef7eb2e8f9f7 68 MXC_SET_FIELD(&obj->adc->tg_ctrl0, MXC_F_ADC_TG_CTRL0_PGA_TRK_CNT, PGA_TRK_CNT);
<> 144:ef7eb2e8f9f7 69
<> 144:ef7eb2e8f9f7 70 // Setup sampling count and timing
<> 144:ef7eb2e8f9f7 71 MXC_SET_FIELD(&obj->adc->tg_ctrl1, (MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT |
<> 144:ef7eb2e8f9f7 72 MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT | MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT),
<> 144:ef7eb2e8f9f7 73 ((ADC_PGA_CNT << MXC_F_ADC_TG_CTRL1_PGA_ACQ_CNT_POS) |
<> 144:ef7eb2e8f9f7 74 (ADC_ACQ_CNT << MXC_F_ADC_TG_CTRL1_ADC_ACQ_CNT_POS) |
<> 144:ef7eb2e8f9f7 75 (ADC_SLP_CNT << MXC_F_ADC_TG_CTRL1_ADC_SLP_CNT_POS) |
<> 144:ef7eb2e8f9f7 76 (MXC_F_ADC_TG_CTRL1_ADC_BRST_CNT)));
<> 144:ef7eb2e8f9f7 77 }
<> 144:ef7eb2e8f9f7 78
<> 144:ef7eb2e8f9f7 79 //******************************************************************************
<> 144:ef7eb2e8f9f7 80 float analogin_read(analogin_t *obj)
<> 144:ef7eb2e8f9f7 81 {
<> 144:ef7eb2e8f9f7 82 // Convert integer to float
<> 144:ef7eb2e8f9f7 83 return (((float)analogin_read_u16(obj)/(float)0xFFFF));
<> 144:ef7eb2e8f9f7 84 }
<> 144:ef7eb2e8f9f7 85
<> 144:ef7eb2e8f9f7 86 //******************************************************************************
<> 144:ef7eb2e8f9f7 87 uint16_t analogin_read_u16(analogin_t *obj)
<> 144:ef7eb2e8f9f7 88 {
<> 144:ef7eb2e8f9f7 89 // Set the pin to take readings from
<> 144:ef7eb2e8f9f7 90 unsigned mux_pos;
<> 144:ef7eb2e8f9f7 91 unsigned diff = 0;
<> 144:ef7eb2e8f9f7 92 if(obj->adc_pin >> PORT_SHIFT == 0xB) {
<> 144:ef7eb2e8f9f7 93 mux_pos = (obj->adc_pin & 0xF) + 8;
<> 144:ef7eb2e8f9f7 94 } else {
<> 144:ef7eb2e8f9f7 95 mux_pos = (obj->adc_pin & 0xF);
<> 144:ef7eb2e8f9f7 96 }
<> 144:ef7eb2e8f9f7 97
<> 144:ef7eb2e8f9f7 98 if(obj->adc_pin >> PORT_SHIFT == 0xC) {
<> 144:ef7eb2e8f9f7 99 diff = 1;
<> 144:ef7eb2e8f9f7 100 mux_pos = (obj->adc_pin & 0xF) + 8;
<> 144:ef7eb2e8f9f7 101 }
<> 144:ef7eb2e8f9f7 102
<> 144:ef7eb2e8f9f7 103 // Reset the ADC
<> 144:ef7eb2e8f9f7 104 obj->adc->ctrl0 |= MXC_F_ADC_CTRL0_CPU_ADC_RST;
<> 144:ef7eb2e8f9f7 105
<> 144:ef7eb2e8f9f7 106 // Enable the ADC
<> 144:ef7eb2e8f9f7 107 obj->adc->ctrl0 |= MXC_F_ADC_CTRL0_CPU_ADC_EN;
<> 144:ef7eb2e8f9f7 108
<> 144:ef7eb2e8f9f7 109 // Setup the ADC clock
<> 144:ef7eb2e8f9f7 110 MXC_SET_FIELD(&obj->adc->ctrl0, (MXC_F_ADC_CTRL0_ADC_MODE | MXC_F_ADC_CTRL0_AVG_MODE |
<> 144:ef7eb2e8f9f7 111 MXC_F_ADC_CTRL0_ADC_CLK_MODE | MXC_F_ADC_CTRL0_ADC_BI_POL),
<> 144:ef7eb2e8f9f7 112 ((MXC_E_ADC_MODE_SMPLCNT_FULL_RATE << MXC_F_ADC_CTRL0_ADC_MODE_POS) |
<> 144:ef7eb2e8f9f7 113 (MXC_E_ADC_AVG_MODE_FILTER_OUTPUT << MXC_F_ADC_CTRL0_AVG_MODE_POS) |
<> 144:ef7eb2e8f9f7 114 (0x2 << MXC_F_ADC_CTRL0_ADC_CLK_MODE_POS) |
<> 144:ef7eb2e8f9f7 115 MXC_F_ADC_CTRL0_ADC_CLK_EN));
<> 144:ef7eb2e8f9f7 116
<> 144:ef7eb2e8f9f7 117 // Setup the input multiplexor
<> 144:ef7eb2e8f9f7 118 MXC_SET_FIELD(&obj->adc->pga_ctrl, (MXC_F_ADC_PGA_CTRL_MUX_CH_SEL |
<> 144:ef7eb2e8f9f7 119 MXC_F_ADC_PGA_CTRL_MUX_DIFF | MXC_F_ADC_PGA_CTRL_PGA_GAIN),
<> 144:ef7eb2e8f9f7 120 ((mux_pos << MXC_F_ADC_PGA_CTRL_MUX_CH_SEL_POS) |
<> 144:ef7eb2e8f9f7 121 (diff << MXC_F_ADC_PGA_CTRL_MUX_DIFF_POS)));
<> 144:ef7eb2e8f9f7 122
<> 144:ef7eb2e8f9f7 123 // Setup voltage reference
<> 144:ef7eb2e8f9f7 124 MXC_SET_FIELD(&MXC_AFE->ctrl1, MXC_F_AFE_CTRL1_REF_ADC_VOLT_SEL,
<> 144:ef7eb2e8f9f7 125 (MXC_F_AFE_CTRL1_REF_ADC_POWERUP | MXC_F_AFE_CTRL1_REF_BLK_POWERUP |
<> 144:ef7eb2e8f9f7 126 (MXC_E_AFE_REF_VOLT_SEL_1500 << MXC_F_AFE_CTRL1_REF_ADC_VOLT_SEL_POS)));
<> 144:ef7eb2e8f9f7 127
<> 144:ef7eb2e8f9f7 128 // Clear the done bit
<> 144:ef7eb2e8f9f7 129 obj->adc->intr = MXC_F_ADC_INTR_DONE_IF;
<> 144:ef7eb2e8f9f7 130
<> 144:ef7eb2e8f9f7 131 // Take one sample
<> 144:ef7eb2e8f9f7 132 obj->adc->tg_ctrl0 |= (1 << MXC_F_ADC_TG_CTRL0_ADC_SMPL_CNT_POS);
<> 144:ef7eb2e8f9f7 133
<> 144:ef7eb2e8f9f7 134 // Set the start bit to take the sample
<> 144:ef7eb2e8f9f7 135 obj->adc->ctrl0 |= MXC_F_ADC_CTRL0_CPU_ADC_START;
<> 144:ef7eb2e8f9f7 136
<> 144:ef7eb2e8f9f7 137 // Wait for the conversion to complete
<> 144:ef7eb2e8f9f7 138 while(!(obj->adc->intr & MXC_F_ADC_INTR_DONE_IF)) {}
<> 144:ef7eb2e8f9f7 139
<> 144:ef7eb2e8f9f7 140 // Get sample from the fifo
<> 144:ef7eb2e8f9f7 141 uint16_t sample = (uint16_t)(obj->adc->out & 0xFFFF);
<> 144:ef7eb2e8f9f7 142
<> 144:ef7eb2e8f9f7 143 // Disable ADC
<> 144:ef7eb2e8f9f7 144 obj->adc->ctrl0 &= ~MXC_F_ADC_CTRL0_CPU_ADC_EN;
<> 144:ef7eb2e8f9f7 145
<> 144:ef7eb2e8f9f7 146 return (sample - 1);
<> 144:ef7eb2e8f9f7 147 }