rik te winkel / mbed-dev

Forked mbed-dev as I use an 20 pins stm32F042 and not the 32 pins version

Dependents:   Numitron_clock

Fork of mbed-dev by mbed official

targets/TARGET_Freescale/TARGET_KLXX/sleep.c@153:0a78729d3229, 2017-01-22 (annotated)

Committer:
riktw
Date:
Sun Jan 22 22:20:36 2017 +0000
Revision:
153:0a78729d3229
Parent:
149:156823d33999 
Back to 8Mhz clock. Revision 1.0

Who changed what in which revision?

UserRevisionLine numberNew contents of line
<> 144:ef7eb2e8f9f7 1 /* mbed Microcontroller Library
<> 144:ef7eb2e8f9f7 2 * Copyright (c) 2006-2013 ARM Limited
<> 144:ef7eb2e8f9f7 3 *
<> 144:ef7eb2e8f9f7 4 * Licensed under the Apache License, Version 2.0 (the "License");
<> 144:ef7eb2e8f9f7 5 * you may not use this file except in compliance with the License.
<> 144:ef7eb2e8f9f7 6 * You may obtain a copy of the License at
<> 144:ef7eb2e8f9f7 7 *
<> 144:ef7eb2e8f9f7 8 * http://www.apache.org/licenses/LICENSE-2.0
<> 144:ef7eb2e8f9f7 9 *
<> 144:ef7eb2e8f9f7 10 * Unless required by applicable law or agreed to in writing, software
<> 144:ef7eb2e8f9f7 11 * distributed under the License is distributed on an "AS IS" BASIS,
<> 144:ef7eb2e8f9f7 12 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
<> 144:ef7eb2e8f9f7 13 * See the License for the specific language governing permissions and
<> 144:ef7eb2e8f9f7 14 * limitations under the License.
<> 144:ef7eb2e8f9f7 15 */
<> 144:ef7eb2e8f9f7 16 #include "sleep_api.h"
<> 144:ef7eb2e8f9f7 17 #include "cmsis.h"
<> 144:ef7eb2e8f9f7 18 #include "PeripheralPins.h"
<> 144:ef7eb2e8f9f7 19
<> 144:ef7eb2e8f9f7 20 //Normal wait mode
<> 144:ef7eb2e8f9f7 21 void sleep(void)
<> 144:ef7eb2e8f9f7 22 {
<> 144:ef7eb2e8f9f7 23 SMC->PMPROT = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK;
<> 144:ef7eb2e8f9f7 24
<> 144:ef7eb2e8f9f7 25 //Normal sleep mode for ARM core:
<> 144:ef7eb2e8f9f7 26 SCB->SCR = 0;
<> 144:ef7eb2e8f9f7 27 __WFI();
<> 144:ef7eb2e8f9f7 28 }
<> 144:ef7eb2e8f9f7 29
<> 144:ef7eb2e8f9f7 30 //Very low-power stop mode
<> 144:ef7eb2e8f9f7 31 void deepsleep(void)
<> 144:ef7eb2e8f9f7 32 {
<> 144:ef7eb2e8f9f7 33 //Check if ADC is enabled and HS mode is set, if yes disable it (lowers power consumption by 60uA)
<> 144:ef7eb2e8f9f7 34 uint8_t ADC_HSC = 0;
<> 144:ef7eb2e8f9f7 35 if (SIM->SCGC6 & SIM_SCGC6_ADC0_MASK) {
<> 144:ef7eb2e8f9f7 36 if (ADC0->CFG2 & ADC_CFG2_ADHSC_MASK) {
<> 144:ef7eb2e8f9f7 37 ADC_HSC = 1;
<> 144:ef7eb2e8f9f7 38 ADC0->CFG2 &= ~(ADC_CFG2_ADHSC_MASK);
<> 144:ef7eb2e8f9f7 39 }
<> 144:ef7eb2e8f9f7 40 }
<> 144:ef7eb2e8f9f7 41
<> 144:ef7eb2e8f9f7 42 #if ! defined(TARGET_KL43Z)
<> 144:ef7eb2e8f9f7 43 //Check if PLL/FLL is enabled:
<> 144:ef7eb2e8f9f7 44 uint32_t PLL_FLL_en = (MCG->C1 & MCG_C1_CLKS_MASK) == MCG_C1_CLKS(0);
<> 144:ef7eb2e8f9f7 45 #endif
<> 144:ef7eb2e8f9f7 46
<> 144:ef7eb2e8f9f7 47 SMC->PMPROT = SMC_PMPROT_AVLLS_MASK | SMC_PMPROT_ALLS_MASK | SMC_PMPROT_AVLP_MASK;
<> 144:ef7eb2e8f9f7 48 SMC->PMCTRL = SMC_PMCTRL_STOPM(2);
<> 144:ef7eb2e8f9f7 49
<> 144:ef7eb2e8f9f7 50 //Deep sleep for ARM core:
<> 144:ef7eb2e8f9f7 51 SCB->SCR = 1<<SCB_SCR_SLEEPDEEP_Pos;
<> 144:ef7eb2e8f9f7 52
<> 144:ef7eb2e8f9f7 53 __WFI();
<> 144:ef7eb2e8f9f7 54
<> 144:ef7eb2e8f9f7 55 #if ! defined(TARGET_KL43Z)
<> 144:ef7eb2e8f9f7 56 //Switch back to PLL as clock source if needed
<> 144:ef7eb2e8f9f7 57 //The interrupt that woke up the device will run at reduced speed
<> 144:ef7eb2e8f9f7 58 if (PLL_FLL_en) {
<> 144:ef7eb2e8f9f7 59 #ifdef MCG_C5_PLLCLKEN0_MASK //PLL available
<> 144:ef7eb2e8f9f7 60 if (MCG->C6 & (1<<MCG_C6_PLLS_SHIFT) != 0) /* If PLL */
<> 144:ef7eb2e8f9f7 61 while((MCG->S & MCG_S_LOCK0_MASK) == 0x00U); /* Wait until locked */
<> 144:ef7eb2e8f9f7 62 #endif
<> 144:ef7eb2e8f9f7 63 MCG->C1 &= ~MCG_C1_CLKS_MASK;
<> 144:ef7eb2e8f9f7 64 }
<> 144:ef7eb2e8f9f7 65 #endif
<> 144:ef7eb2e8f9f7 66
<> 144:ef7eb2e8f9f7 67 if (ADC_HSC) {
<> 144:ef7eb2e8f9f7 68 ADC0->CFG2 |= (ADC_CFG2_ADHSC_MASK);
<> 144:ef7eb2e8f9f7 69 }
<> 144:ef7eb2e8f9f7 70 }