won't compile

Committer:
richardv
Date:
Wed Nov 02 23:50:52 2016 +0000
Revision:
0:b079fa4ed182
DMA RAM DAC

Who changed what in which revision?

UserRevisionLine numberNew contents of line
richardv 0:b079fa4ed182 1 /**************************************************************************//**
richardv 0:b079fa4ed182 2 * @file core_cmInstr.h
richardv 0:b079fa4ed182 3 * @brief CMSIS Cortex-M Core Instruction Access Header File
richardv 0:b079fa4ed182 4 * @version V3.20
richardv 0:b079fa4ed182 5 * @date 05. March 2013
richardv 0:b079fa4ed182 6 *
richardv 0:b079fa4ed182 7 * @note
richardv 0:b079fa4ed182 8 *
richardv 0:b079fa4ed182 9 ******************************************************************************/
richardv 0:b079fa4ed182 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
richardv 0:b079fa4ed182 11
richardv 0:b079fa4ed182 12 All rights reserved.
richardv 0:b079fa4ed182 13 Redistribution and use in source and binary forms, with or without
richardv 0:b079fa4ed182 14 modification, are permitted provided that the following conditions are met:
richardv 0:b079fa4ed182 15 - Redistributions of source code must retain the above copyright
richardv 0:b079fa4ed182 16 notice, this list of conditions and the following disclaimer.
richardv 0:b079fa4ed182 17 - Redistributions in binary form must reproduce the above copyright
richardv 0:b079fa4ed182 18 notice, this list of conditions and the following disclaimer in the
richardv 0:b079fa4ed182 19 documentation and/or other materials provided with the distribution.
richardv 0:b079fa4ed182 20 - Neither the name of ARM nor the names of its contributors may be used
richardv 0:b079fa4ed182 21 to endorse or promote products derived from this software without
richardv 0:b079fa4ed182 22 specific prior written permission.
richardv 0:b079fa4ed182 23 *
richardv 0:b079fa4ed182 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
richardv 0:b079fa4ed182 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
richardv 0:b079fa4ed182 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
richardv 0:b079fa4ed182 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
richardv 0:b079fa4ed182 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
richardv 0:b079fa4ed182 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
richardv 0:b079fa4ed182 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
richardv 0:b079fa4ed182 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
richardv 0:b079fa4ed182 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
richardv 0:b079fa4ed182 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
richardv 0:b079fa4ed182 34 POSSIBILITY OF SUCH DAMAGE.
richardv 0:b079fa4ed182 35 ---------------------------------------------------------------------------*/
richardv 0:b079fa4ed182 36
richardv 0:b079fa4ed182 37
richardv 0:b079fa4ed182 38 #ifndef __CORE_CMINSTR_H
richardv 0:b079fa4ed182 39 #define __CORE_CMINSTR_H
richardv 0:b079fa4ed182 40
richardv 0:b079fa4ed182 41
richardv 0:b079fa4ed182 42 /* ########################## Core Instruction Access ######################### */
richardv 0:b079fa4ed182 43 /** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
richardv 0:b079fa4ed182 44 Access to dedicated instructions
richardv 0:b079fa4ed182 45 @{
richardv 0:b079fa4ed182 46 */
richardv 0:b079fa4ed182 47
richardv 0:b079fa4ed182 48 #if defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
richardv 0:b079fa4ed182 49 /* ARM armcc specific functions */
richardv 0:b079fa4ed182 50
richardv 0:b079fa4ed182 51 #if (__ARMCC_VERSION < 400677)
richardv 0:b079fa4ed182 52 #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
richardv 0:b079fa4ed182 53 #endif
richardv 0:b079fa4ed182 54
richardv 0:b079fa4ed182 55
richardv 0:b079fa4ed182 56 /** \brief No Operation
richardv 0:b079fa4ed182 57
richardv 0:b079fa4ed182 58 No Operation does nothing. This instruction can be used for code alignment purposes.
richardv 0:b079fa4ed182 59 */
richardv 0:b079fa4ed182 60 #define __NOP __nop
richardv 0:b079fa4ed182 61
richardv 0:b079fa4ed182 62
richardv 0:b079fa4ed182 63 /** \brief Wait For Interrupt
richardv 0:b079fa4ed182 64
richardv 0:b079fa4ed182 65 Wait For Interrupt is a hint instruction that suspends execution
richardv 0:b079fa4ed182 66 until one of a number of events occurs.
richardv 0:b079fa4ed182 67 */
richardv 0:b079fa4ed182 68 #define __WFI __wfi
richardv 0:b079fa4ed182 69
richardv 0:b079fa4ed182 70
richardv 0:b079fa4ed182 71 /** \brief Wait For Event
richardv 0:b079fa4ed182 72
richardv 0:b079fa4ed182 73 Wait For Event is a hint instruction that permits the processor to enter
richardv 0:b079fa4ed182 74 a low-power state until one of a number of events occurs.
richardv 0:b079fa4ed182 75 */
richardv 0:b079fa4ed182 76 #define __WFE __wfe
richardv 0:b079fa4ed182 77
richardv 0:b079fa4ed182 78
richardv 0:b079fa4ed182 79 /** \brief Send Event
richardv 0:b079fa4ed182 80
richardv 0:b079fa4ed182 81 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
richardv 0:b079fa4ed182 82 */
richardv 0:b079fa4ed182 83 #define __SEV __sev
richardv 0:b079fa4ed182 84
richardv 0:b079fa4ed182 85
richardv 0:b079fa4ed182 86 /** \brief Instruction Synchronization Barrier
richardv 0:b079fa4ed182 87
richardv 0:b079fa4ed182 88 Instruction Synchronization Barrier flushes the pipeline in the processor,
richardv 0:b079fa4ed182 89 so that all instructions following the ISB are fetched from cache or
richardv 0:b079fa4ed182 90 memory, after the instruction has been completed.
richardv 0:b079fa4ed182 91 */
richardv 0:b079fa4ed182 92 #define __ISB() __isb(0xF)
richardv 0:b079fa4ed182 93
richardv 0:b079fa4ed182 94
richardv 0:b079fa4ed182 95 /** \brief Data Synchronization Barrier
richardv 0:b079fa4ed182 96
richardv 0:b079fa4ed182 97 This function acts as a special kind of Data Memory Barrier.
richardv 0:b079fa4ed182 98 It completes when all explicit memory accesses before this instruction complete.
richardv 0:b079fa4ed182 99 */
richardv 0:b079fa4ed182 100 #define __DSB() __dsb(0xF)
richardv 0:b079fa4ed182 101
richardv 0:b079fa4ed182 102
richardv 0:b079fa4ed182 103 /** \brief Data Memory Barrier
richardv 0:b079fa4ed182 104
richardv 0:b079fa4ed182 105 This function ensures the apparent order of the explicit memory operations before
richardv 0:b079fa4ed182 106 and after the instruction, without ensuring their completion.
richardv 0:b079fa4ed182 107 */
richardv 0:b079fa4ed182 108 #define __DMB() __dmb(0xF)
richardv 0:b079fa4ed182 109
richardv 0:b079fa4ed182 110
richardv 0:b079fa4ed182 111 /** \brief Reverse byte order (32 bit)
richardv 0:b079fa4ed182 112
richardv 0:b079fa4ed182 113 This function reverses the byte order in integer value.
richardv 0:b079fa4ed182 114
richardv 0:b079fa4ed182 115 \param [in] value Value to reverse
richardv 0:b079fa4ed182 116 \return Reversed value
richardv 0:b079fa4ed182 117 */
richardv 0:b079fa4ed182 118 #define __REV __rev
richardv 0:b079fa4ed182 119
richardv 0:b079fa4ed182 120
richardv 0:b079fa4ed182 121 /** \brief Reverse byte order (16 bit)
richardv 0:b079fa4ed182 122
richardv 0:b079fa4ed182 123 This function reverses the byte order in two unsigned short values.
richardv 0:b079fa4ed182 124
richardv 0:b079fa4ed182 125 \param [in] value Value to reverse
richardv 0:b079fa4ed182 126 \return Reversed value
richardv 0:b079fa4ed182 127 */
richardv 0:b079fa4ed182 128 #ifndef __NO_EMBEDDED_ASM
richardv 0:b079fa4ed182 129 __attribute__((section(".rev16_text"))) __STATIC_INLINE __ASM uint32_t __REV16(uint32_t value)
richardv 0:b079fa4ed182 130 {
richardv 0:b079fa4ed182 131 rev16 r0, r0
richardv 0:b079fa4ed182 132 bx lr
richardv 0:b079fa4ed182 133 }
richardv 0:b079fa4ed182 134 #endif
richardv 0:b079fa4ed182 135
richardv 0:b079fa4ed182 136 /** \brief Reverse byte order in signed short value
richardv 0:b079fa4ed182 137
richardv 0:b079fa4ed182 138 This function reverses the byte order in a signed short value with sign extension to integer.
richardv 0:b079fa4ed182 139
richardv 0:b079fa4ed182 140 \param [in] value Value to reverse
richardv 0:b079fa4ed182 141 \return Reversed value
richardv 0:b079fa4ed182 142 */
richardv 0:b079fa4ed182 143 #ifndef __NO_EMBEDDED_ASM
richardv 0:b079fa4ed182 144 __attribute__((section(".revsh_text"))) __STATIC_INLINE __ASM int32_t __REVSH(int32_t value)
richardv 0:b079fa4ed182 145 {
richardv 0:b079fa4ed182 146 revsh r0, r0
richardv 0:b079fa4ed182 147 bx lr
richardv 0:b079fa4ed182 148 }
richardv 0:b079fa4ed182 149 #endif
richardv 0:b079fa4ed182 150
richardv 0:b079fa4ed182 151
richardv 0:b079fa4ed182 152 /** \brief Rotate Right in unsigned value (32 bit)
richardv 0:b079fa4ed182 153
richardv 0:b079fa4ed182 154 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
richardv 0:b079fa4ed182 155
richardv 0:b079fa4ed182 156 \param [in] value Value to rotate
richardv 0:b079fa4ed182 157 \param [in] value Number of Bits to rotate
richardv 0:b079fa4ed182 158 \return Rotated value
richardv 0:b079fa4ed182 159 */
richardv 0:b079fa4ed182 160 #define __ROR __ror
richardv 0:b079fa4ed182 161
richardv 0:b079fa4ed182 162
richardv 0:b079fa4ed182 163 /** \brief Breakpoint
richardv 0:b079fa4ed182 164
richardv 0:b079fa4ed182 165 This function causes the processor to enter Debug state.
richardv 0:b079fa4ed182 166 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
richardv 0:b079fa4ed182 167
richardv 0:b079fa4ed182 168 \param [in] value is ignored by the processor.
richardv 0:b079fa4ed182 169 If required, a debugger can use it to store additional information about the breakpoint.
richardv 0:b079fa4ed182 170 */
richardv 0:b079fa4ed182 171 #define __BKPT(value) __breakpoint(value)
richardv 0:b079fa4ed182 172
richardv 0:b079fa4ed182 173
richardv 0:b079fa4ed182 174 #if (__CORTEX_M >= 0x03)
richardv 0:b079fa4ed182 175
richardv 0:b079fa4ed182 176 /** \brief Reverse bit order of value
richardv 0:b079fa4ed182 177
richardv 0:b079fa4ed182 178 This function reverses the bit order of the given value.
richardv 0:b079fa4ed182 179
richardv 0:b079fa4ed182 180 \param [in] value Value to reverse
richardv 0:b079fa4ed182 181 \return Reversed value
richardv 0:b079fa4ed182 182 */
richardv 0:b079fa4ed182 183 #define __RBIT __rbit
richardv 0:b079fa4ed182 184
richardv 0:b079fa4ed182 185
richardv 0:b079fa4ed182 186 /** \brief LDR Exclusive (8 bit)
richardv 0:b079fa4ed182 187
richardv 0:b079fa4ed182 188 This function performs a exclusive LDR command for 8 bit value.
richardv 0:b079fa4ed182 189
richardv 0:b079fa4ed182 190 \param [in] ptr Pointer to data
richardv 0:b079fa4ed182 191 \return value of type uint8_t at (*ptr)
richardv 0:b079fa4ed182 192 */
richardv 0:b079fa4ed182 193 #define __LDREXB(ptr) ((uint8_t ) __ldrex(ptr))
richardv 0:b079fa4ed182 194
richardv 0:b079fa4ed182 195
richardv 0:b079fa4ed182 196 /** \brief LDR Exclusive (16 bit)
richardv 0:b079fa4ed182 197
richardv 0:b079fa4ed182 198 This function performs a exclusive LDR command for 16 bit values.
richardv 0:b079fa4ed182 199
richardv 0:b079fa4ed182 200 \param [in] ptr Pointer to data
richardv 0:b079fa4ed182 201 \return value of type uint16_t at (*ptr)
richardv 0:b079fa4ed182 202 */
richardv 0:b079fa4ed182 203 #define __LDREXH(ptr) ((uint16_t) __ldrex(ptr))
richardv 0:b079fa4ed182 204
richardv 0:b079fa4ed182 205
richardv 0:b079fa4ed182 206 /** \brief LDR Exclusive (32 bit)
richardv 0:b079fa4ed182 207
richardv 0:b079fa4ed182 208 This function performs a exclusive LDR command for 32 bit values.
richardv 0:b079fa4ed182 209
richardv 0:b079fa4ed182 210 \param [in] ptr Pointer to data
richardv 0:b079fa4ed182 211 \return value of type uint32_t at (*ptr)
richardv 0:b079fa4ed182 212 */
richardv 0:b079fa4ed182 213 #define __LDREXW(ptr) ((uint32_t ) __ldrex(ptr))
richardv 0:b079fa4ed182 214
richardv 0:b079fa4ed182 215
richardv 0:b079fa4ed182 216 /** \brief STR Exclusive (8 bit)
richardv 0:b079fa4ed182 217
richardv 0:b079fa4ed182 218 This function performs a exclusive STR command for 8 bit values.
richardv 0:b079fa4ed182 219
richardv 0:b079fa4ed182 220 \param [in] value Value to store
richardv 0:b079fa4ed182 221 \param [in] ptr Pointer to location
richardv 0:b079fa4ed182 222 \return 0 Function succeeded
richardv 0:b079fa4ed182 223 \return 1 Function failed
richardv 0:b079fa4ed182 224 */
richardv 0:b079fa4ed182 225 #define __STREXB(value, ptr) __strex(value, ptr)
richardv 0:b079fa4ed182 226
richardv 0:b079fa4ed182 227
richardv 0:b079fa4ed182 228 /** \brief STR Exclusive (16 bit)
richardv 0:b079fa4ed182 229
richardv 0:b079fa4ed182 230 This function performs a exclusive STR command for 16 bit values.
richardv 0:b079fa4ed182 231
richardv 0:b079fa4ed182 232 \param [in] value Value to store
richardv 0:b079fa4ed182 233 \param [in] ptr Pointer to location
richardv 0:b079fa4ed182 234 \return 0 Function succeeded
richardv 0:b079fa4ed182 235 \return 1 Function failed
richardv 0:b079fa4ed182 236 */
richardv 0:b079fa4ed182 237 #define __STREXH(value, ptr) __strex(value, ptr)
richardv 0:b079fa4ed182 238
richardv 0:b079fa4ed182 239
richardv 0:b079fa4ed182 240 /** \brief STR Exclusive (32 bit)
richardv 0:b079fa4ed182 241
richardv 0:b079fa4ed182 242 This function performs a exclusive STR command for 32 bit values.
richardv 0:b079fa4ed182 243
richardv 0:b079fa4ed182 244 \param [in] value Value to store
richardv 0:b079fa4ed182 245 \param [in] ptr Pointer to location
richardv 0:b079fa4ed182 246 \return 0 Function succeeded
richardv 0:b079fa4ed182 247 \return 1 Function failed
richardv 0:b079fa4ed182 248 */
richardv 0:b079fa4ed182 249 #define __STREXW(value, ptr) __strex(value, ptr)
richardv 0:b079fa4ed182 250
richardv 0:b079fa4ed182 251
richardv 0:b079fa4ed182 252 /** \brief Remove the exclusive lock
richardv 0:b079fa4ed182 253
richardv 0:b079fa4ed182 254 This function removes the exclusive lock which is created by LDREX.
richardv 0:b079fa4ed182 255
richardv 0:b079fa4ed182 256 */
richardv 0:b079fa4ed182 257 #define __CLREX __clrex
richardv 0:b079fa4ed182 258
richardv 0:b079fa4ed182 259
richardv 0:b079fa4ed182 260 /** \brief Signed Saturate
richardv 0:b079fa4ed182 261
richardv 0:b079fa4ed182 262 This function saturates a signed value.
richardv 0:b079fa4ed182 263
richardv 0:b079fa4ed182 264 \param [in] value Value to be saturated
richardv 0:b079fa4ed182 265 \param [in] sat Bit position to saturate to (1..32)
richardv 0:b079fa4ed182 266 \return Saturated value
richardv 0:b079fa4ed182 267 */
richardv 0:b079fa4ed182 268 #define __SSAT __ssat
richardv 0:b079fa4ed182 269
richardv 0:b079fa4ed182 270
richardv 0:b079fa4ed182 271 /** \brief Unsigned Saturate
richardv 0:b079fa4ed182 272
richardv 0:b079fa4ed182 273 This function saturates an unsigned value.
richardv 0:b079fa4ed182 274
richardv 0:b079fa4ed182 275 \param [in] value Value to be saturated
richardv 0:b079fa4ed182 276 \param [in] sat Bit position to saturate to (0..31)
richardv 0:b079fa4ed182 277 \return Saturated value
richardv 0:b079fa4ed182 278 */
richardv 0:b079fa4ed182 279 #define __USAT __usat
richardv 0:b079fa4ed182 280
richardv 0:b079fa4ed182 281
richardv 0:b079fa4ed182 282 /** \brief Count leading zeros
richardv 0:b079fa4ed182 283
richardv 0:b079fa4ed182 284 This function counts the number of leading zeros of a data value.
richardv 0:b079fa4ed182 285
richardv 0:b079fa4ed182 286 \param [in] value Value to count the leading zeros
richardv 0:b079fa4ed182 287 \return number of leading zeros in value
richardv 0:b079fa4ed182 288 */
richardv 0:b079fa4ed182 289 #define __CLZ __clz
richardv 0:b079fa4ed182 290
richardv 0:b079fa4ed182 291 #endif /* (__CORTEX_M >= 0x03) */
richardv 0:b079fa4ed182 292
richardv 0:b079fa4ed182 293
richardv 0:b079fa4ed182 294
richardv 0:b079fa4ed182 295 #elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
richardv 0:b079fa4ed182 296 /* IAR iccarm specific functions */
richardv 0:b079fa4ed182 297
richardv 0:b079fa4ed182 298 #include <cmsis_iar.h>
richardv 0:b079fa4ed182 299
richardv 0:b079fa4ed182 300
richardv 0:b079fa4ed182 301 #elif defined ( __TMS470__ ) /*---------------- TI CCS Compiler ------------------*/
richardv 0:b079fa4ed182 302 /* TI CCS specific functions */
richardv 0:b079fa4ed182 303
richardv 0:b079fa4ed182 304 #include <cmsis_ccs.h>
richardv 0:b079fa4ed182 305
richardv 0:b079fa4ed182 306
richardv 0:b079fa4ed182 307 #elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
richardv 0:b079fa4ed182 308 /* GNU gcc specific functions */
richardv 0:b079fa4ed182 309
richardv 0:b079fa4ed182 310 /* Define macros for porting to both thumb1 and thumb2.
richardv 0:b079fa4ed182 311 * For thumb1, use low register (r0-r7), specified by constrant "l"
richardv 0:b079fa4ed182 312 * Otherwise, use general registers, specified by constrant "r" */
richardv 0:b079fa4ed182 313 #if defined (__thumb__) && !defined (__thumb2__)
richardv 0:b079fa4ed182 314 #define __CMSIS_GCC_OUT_REG(r) "=l" (r)
richardv 0:b079fa4ed182 315 #define __CMSIS_GCC_USE_REG(r) "l" (r)
richardv 0:b079fa4ed182 316 #else
richardv 0:b079fa4ed182 317 #define __CMSIS_GCC_OUT_REG(r) "=r" (r)
richardv 0:b079fa4ed182 318 #define __CMSIS_GCC_USE_REG(r) "r" (r)
richardv 0:b079fa4ed182 319 #endif
richardv 0:b079fa4ed182 320
richardv 0:b079fa4ed182 321 /** \brief No Operation
richardv 0:b079fa4ed182 322
richardv 0:b079fa4ed182 323 No Operation does nothing. This instruction can be used for code alignment purposes.
richardv 0:b079fa4ed182 324 */
richardv 0:b079fa4ed182 325 __attribute__( ( always_inline ) ) __STATIC_INLINE void __NOP(void)
richardv 0:b079fa4ed182 326 {
richardv 0:b079fa4ed182 327 __ASM volatile ("nop");
richardv 0:b079fa4ed182 328 }
richardv 0:b079fa4ed182 329
richardv 0:b079fa4ed182 330
richardv 0:b079fa4ed182 331 /** \brief Wait For Interrupt
richardv 0:b079fa4ed182 332
richardv 0:b079fa4ed182 333 Wait For Interrupt is a hint instruction that suspends execution
richardv 0:b079fa4ed182 334 until one of a number of events occurs.
richardv 0:b079fa4ed182 335 */
richardv 0:b079fa4ed182 336 __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFI(void)
richardv 0:b079fa4ed182 337 {
richardv 0:b079fa4ed182 338 __ASM volatile ("wfi");
richardv 0:b079fa4ed182 339 }
richardv 0:b079fa4ed182 340
richardv 0:b079fa4ed182 341
richardv 0:b079fa4ed182 342 /** \brief Wait For Event
richardv 0:b079fa4ed182 343
richardv 0:b079fa4ed182 344 Wait For Event is a hint instruction that permits the processor to enter
richardv 0:b079fa4ed182 345 a low-power state until one of a number of events occurs.
richardv 0:b079fa4ed182 346 */
richardv 0:b079fa4ed182 347 __attribute__( ( always_inline ) ) __STATIC_INLINE void __WFE(void)
richardv 0:b079fa4ed182 348 {
richardv 0:b079fa4ed182 349 __ASM volatile ("wfe");
richardv 0:b079fa4ed182 350 }
richardv 0:b079fa4ed182 351
richardv 0:b079fa4ed182 352
richardv 0:b079fa4ed182 353 /** \brief Send Event
richardv 0:b079fa4ed182 354
richardv 0:b079fa4ed182 355 Send Event is a hint instruction. It causes an event to be signaled to the CPU.
richardv 0:b079fa4ed182 356 */
richardv 0:b079fa4ed182 357 __attribute__( ( always_inline ) ) __STATIC_INLINE void __SEV(void)
richardv 0:b079fa4ed182 358 {
richardv 0:b079fa4ed182 359 __ASM volatile ("sev");
richardv 0:b079fa4ed182 360 }
richardv 0:b079fa4ed182 361
richardv 0:b079fa4ed182 362
richardv 0:b079fa4ed182 363 /** \brief Instruction Synchronization Barrier
richardv 0:b079fa4ed182 364
richardv 0:b079fa4ed182 365 Instruction Synchronization Barrier flushes the pipeline in the processor,
richardv 0:b079fa4ed182 366 so that all instructions following the ISB are fetched from cache or
richardv 0:b079fa4ed182 367 memory, after the instruction has been completed.
richardv 0:b079fa4ed182 368 */
richardv 0:b079fa4ed182 369 __attribute__( ( always_inline ) ) __STATIC_INLINE void __ISB(void)
richardv 0:b079fa4ed182 370 {
richardv 0:b079fa4ed182 371 __ASM volatile ("isb");
richardv 0:b079fa4ed182 372 }
richardv 0:b079fa4ed182 373
richardv 0:b079fa4ed182 374
richardv 0:b079fa4ed182 375 /** \brief Data Synchronization Barrier
richardv 0:b079fa4ed182 376
richardv 0:b079fa4ed182 377 This function acts as a special kind of Data Memory Barrier.
richardv 0:b079fa4ed182 378 It completes when all explicit memory accesses before this instruction complete.
richardv 0:b079fa4ed182 379 */
richardv 0:b079fa4ed182 380 __attribute__( ( always_inline ) ) __STATIC_INLINE void __DSB(void)
richardv 0:b079fa4ed182 381 {
richardv 0:b079fa4ed182 382 __ASM volatile ("dsb");
richardv 0:b079fa4ed182 383 }
richardv 0:b079fa4ed182 384
richardv 0:b079fa4ed182 385
richardv 0:b079fa4ed182 386 /** \brief Data Memory Barrier
richardv 0:b079fa4ed182 387
richardv 0:b079fa4ed182 388 This function ensures the apparent order of the explicit memory operations before
richardv 0:b079fa4ed182 389 and after the instruction, without ensuring their completion.
richardv 0:b079fa4ed182 390 */
richardv 0:b079fa4ed182 391 __attribute__( ( always_inline ) ) __STATIC_INLINE void __DMB(void)
richardv 0:b079fa4ed182 392 {
richardv 0:b079fa4ed182 393 __ASM volatile ("dmb");
richardv 0:b079fa4ed182 394 }
richardv 0:b079fa4ed182 395
richardv 0:b079fa4ed182 396
richardv 0:b079fa4ed182 397 /** \brief Reverse byte order (32 bit)
richardv 0:b079fa4ed182 398
richardv 0:b079fa4ed182 399 This function reverses the byte order in integer value.
richardv 0:b079fa4ed182 400
richardv 0:b079fa4ed182 401 \param [in] value Value to reverse
richardv 0:b079fa4ed182 402 \return Reversed value
richardv 0:b079fa4ed182 403 */
richardv 0:b079fa4ed182 404 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV(uint32_t value)
richardv 0:b079fa4ed182 405 {
richardv 0:b079fa4ed182 406 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 5)
richardv 0:b079fa4ed182 407 return __builtin_bswap32(value);
richardv 0:b079fa4ed182 408 #else
richardv 0:b079fa4ed182 409 uint32_t result;
richardv 0:b079fa4ed182 410
richardv 0:b079fa4ed182 411 __ASM volatile ("rev %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
richardv 0:b079fa4ed182 412 return(result);
richardv 0:b079fa4ed182 413 #endif
richardv 0:b079fa4ed182 414 }
richardv 0:b079fa4ed182 415
richardv 0:b079fa4ed182 416
richardv 0:b079fa4ed182 417 /** \brief Reverse byte order (16 bit)
richardv 0:b079fa4ed182 418
richardv 0:b079fa4ed182 419 This function reverses the byte order in two unsigned short values.
richardv 0:b079fa4ed182 420
richardv 0:b079fa4ed182 421 \param [in] value Value to reverse
richardv 0:b079fa4ed182 422 \return Reversed value
richardv 0:b079fa4ed182 423 */
richardv 0:b079fa4ed182 424 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __REV16(uint32_t value)
richardv 0:b079fa4ed182 425 {
richardv 0:b079fa4ed182 426 uint32_t result;
richardv 0:b079fa4ed182 427
richardv 0:b079fa4ed182 428 __ASM volatile ("rev16 %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
richardv 0:b079fa4ed182 429 return(result);
richardv 0:b079fa4ed182 430 }
richardv 0:b079fa4ed182 431
richardv 0:b079fa4ed182 432
richardv 0:b079fa4ed182 433 /** \brief Reverse byte order in signed short value
richardv 0:b079fa4ed182 434
richardv 0:b079fa4ed182 435 This function reverses the byte order in a signed short value with sign extension to integer.
richardv 0:b079fa4ed182 436
richardv 0:b079fa4ed182 437 \param [in] value Value to reverse
richardv 0:b079fa4ed182 438 \return Reversed value
richardv 0:b079fa4ed182 439 */
richardv 0:b079fa4ed182 440 __attribute__( ( always_inline ) ) __STATIC_INLINE int32_t __REVSH(int32_t value)
richardv 0:b079fa4ed182 441 {
richardv 0:b079fa4ed182 442 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
richardv 0:b079fa4ed182 443 return (short)__builtin_bswap16(value);
richardv 0:b079fa4ed182 444 #else
richardv 0:b079fa4ed182 445 uint32_t result;
richardv 0:b079fa4ed182 446
richardv 0:b079fa4ed182 447 __ASM volatile ("revsh %0, %1" : __CMSIS_GCC_OUT_REG (result) : __CMSIS_GCC_USE_REG (value) );
richardv 0:b079fa4ed182 448 return(result);
richardv 0:b079fa4ed182 449 #endif
richardv 0:b079fa4ed182 450 }
richardv 0:b079fa4ed182 451
richardv 0:b079fa4ed182 452
richardv 0:b079fa4ed182 453 /** \brief Rotate Right in unsigned value (32 bit)
richardv 0:b079fa4ed182 454
richardv 0:b079fa4ed182 455 This function Rotate Right (immediate) provides the value of the contents of a register rotated by a variable number of bits.
richardv 0:b079fa4ed182 456
richardv 0:b079fa4ed182 457 \param [in] value Value to rotate
richardv 0:b079fa4ed182 458 \param [in] value Number of Bits to rotate
richardv 0:b079fa4ed182 459 \return Rotated value
richardv 0:b079fa4ed182 460 */
richardv 0:b079fa4ed182 461 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __ROR(uint32_t op1, uint32_t op2)
richardv 0:b079fa4ed182 462 {
richardv 0:b079fa4ed182 463 return (op1 >> op2) | (op1 << (32 - op2));
richardv 0:b079fa4ed182 464 }
richardv 0:b079fa4ed182 465
richardv 0:b079fa4ed182 466
richardv 0:b079fa4ed182 467 /** \brief Breakpoint
richardv 0:b079fa4ed182 468
richardv 0:b079fa4ed182 469 This function causes the processor to enter Debug state.
richardv 0:b079fa4ed182 470 Debug tools can use this to investigate system state when the instruction at a particular address is reached.
richardv 0:b079fa4ed182 471
richardv 0:b079fa4ed182 472 \param [in] value is ignored by the processor.
richardv 0:b079fa4ed182 473 If required, a debugger can use it to store additional information about the breakpoint.
richardv 0:b079fa4ed182 474 */
richardv 0:b079fa4ed182 475 #define __BKPT(value) __ASM volatile ("bkpt "#value)
richardv 0:b079fa4ed182 476
richardv 0:b079fa4ed182 477
richardv 0:b079fa4ed182 478 #if (__CORTEX_M >= 0x03)
richardv 0:b079fa4ed182 479
richardv 0:b079fa4ed182 480 /** \brief Reverse bit order of value
richardv 0:b079fa4ed182 481
richardv 0:b079fa4ed182 482 This function reverses the bit order of the given value.
richardv 0:b079fa4ed182 483
richardv 0:b079fa4ed182 484 \param [in] value Value to reverse
richardv 0:b079fa4ed182 485 \return Reversed value
richardv 0:b079fa4ed182 486 */
richardv 0:b079fa4ed182 487 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __RBIT(uint32_t value)
richardv 0:b079fa4ed182 488 {
richardv 0:b079fa4ed182 489 uint32_t result;
richardv 0:b079fa4ed182 490
richardv 0:b079fa4ed182 491 __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
richardv 0:b079fa4ed182 492 return(result);
richardv 0:b079fa4ed182 493 }
richardv 0:b079fa4ed182 494
richardv 0:b079fa4ed182 495
richardv 0:b079fa4ed182 496 /** \brief LDR Exclusive (8 bit)
richardv 0:b079fa4ed182 497
richardv 0:b079fa4ed182 498 This function performs a exclusive LDR command for 8 bit value.
richardv 0:b079fa4ed182 499
richardv 0:b079fa4ed182 500 \param [in] ptr Pointer to data
richardv 0:b079fa4ed182 501 \return value of type uint8_t at (*ptr)
richardv 0:b079fa4ed182 502 */
richardv 0:b079fa4ed182 503 __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __LDREXB(volatile uint8_t *addr)
richardv 0:b079fa4ed182 504 {
richardv 0:b079fa4ed182 505 uint32_t result;
richardv 0:b079fa4ed182 506
richardv 0:b079fa4ed182 507 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
richardv 0:b079fa4ed182 508 __ASM volatile ("ldrexb %0, %1" : "=r" (result) : "Q" (*addr) );
richardv 0:b079fa4ed182 509 #else
richardv 0:b079fa4ed182 510 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
richardv 0:b079fa4ed182 511 accepted by assembler. So has to use following less efficient pattern.
richardv 0:b079fa4ed182 512 */
richardv 0:b079fa4ed182 513 __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
richardv 0:b079fa4ed182 514 #endif
richardv 0:b079fa4ed182 515 return(result);
richardv 0:b079fa4ed182 516 }
richardv 0:b079fa4ed182 517
richardv 0:b079fa4ed182 518
richardv 0:b079fa4ed182 519 /** \brief LDR Exclusive (16 bit)
richardv 0:b079fa4ed182 520
richardv 0:b079fa4ed182 521 This function performs a exclusive LDR command for 16 bit values.
richardv 0:b079fa4ed182 522
richardv 0:b079fa4ed182 523 \param [in] ptr Pointer to data
richardv 0:b079fa4ed182 524 \return value of type uint16_t at (*ptr)
richardv 0:b079fa4ed182 525 */
richardv 0:b079fa4ed182 526 __attribute__( ( always_inline ) ) __STATIC_INLINE uint16_t __LDREXH(volatile uint16_t *addr)
richardv 0:b079fa4ed182 527 {
richardv 0:b079fa4ed182 528 uint32_t result;
richardv 0:b079fa4ed182 529
richardv 0:b079fa4ed182 530 #if (__GNUC__ > 4) || (__GNUC__ == 4 && __GNUC_MINOR__ >= 8)
richardv 0:b079fa4ed182 531 __ASM volatile ("ldrexh %0, %1" : "=r" (result) : "Q" (*addr) );
richardv 0:b079fa4ed182 532 #else
richardv 0:b079fa4ed182 533 /* Prior to GCC 4.8, "Q" will be expanded to [rx, #0] which is not
richardv 0:b079fa4ed182 534 accepted by assembler. So has to use following less efficient pattern.
richardv 0:b079fa4ed182 535 */
richardv 0:b079fa4ed182 536 __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) : "memory" );
richardv 0:b079fa4ed182 537 #endif
richardv 0:b079fa4ed182 538 return(result);
richardv 0:b079fa4ed182 539 }
richardv 0:b079fa4ed182 540
richardv 0:b079fa4ed182 541
richardv 0:b079fa4ed182 542 /** \brief LDR Exclusive (32 bit)
richardv 0:b079fa4ed182 543
richardv 0:b079fa4ed182 544 This function performs a exclusive LDR command for 32 bit values.
richardv 0:b079fa4ed182 545
richardv 0:b079fa4ed182 546 \param [in] ptr Pointer to data
richardv 0:b079fa4ed182 547 \return value of type uint32_t at (*ptr)
richardv 0:b079fa4ed182 548 */
richardv 0:b079fa4ed182 549 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __LDREXW(volatile uint32_t *addr)
richardv 0:b079fa4ed182 550 {
richardv 0:b079fa4ed182 551 uint32_t result;
richardv 0:b079fa4ed182 552
richardv 0:b079fa4ed182 553 __ASM volatile ("ldrex %0, %1" : "=r" (result) : "Q" (*addr) );
richardv 0:b079fa4ed182 554 return(result);
richardv 0:b079fa4ed182 555 }
richardv 0:b079fa4ed182 556
richardv 0:b079fa4ed182 557
richardv 0:b079fa4ed182 558 /** \brief STR Exclusive (8 bit)
richardv 0:b079fa4ed182 559
richardv 0:b079fa4ed182 560 This function performs a exclusive STR command for 8 bit values.
richardv 0:b079fa4ed182 561
richardv 0:b079fa4ed182 562 \param [in] value Value to store
richardv 0:b079fa4ed182 563 \param [in] ptr Pointer to location
richardv 0:b079fa4ed182 564 \return 0 Function succeeded
richardv 0:b079fa4ed182 565 \return 1 Function failed
richardv 0:b079fa4ed182 566 */
richardv 0:b079fa4ed182 567 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
richardv 0:b079fa4ed182 568 {
richardv 0:b079fa4ed182 569 uint32_t result;
richardv 0:b079fa4ed182 570
richardv 0:b079fa4ed182 571 __ASM volatile ("strexb %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
richardv 0:b079fa4ed182 572 return(result);
richardv 0:b079fa4ed182 573 }
richardv 0:b079fa4ed182 574
richardv 0:b079fa4ed182 575
richardv 0:b079fa4ed182 576 /** \brief STR Exclusive (16 bit)
richardv 0:b079fa4ed182 577
richardv 0:b079fa4ed182 578 This function performs a exclusive STR command for 16 bit values.
richardv 0:b079fa4ed182 579
richardv 0:b079fa4ed182 580 \param [in] value Value to store
richardv 0:b079fa4ed182 581 \param [in] ptr Pointer to location
richardv 0:b079fa4ed182 582 \return 0 Function succeeded
richardv 0:b079fa4ed182 583 \return 1 Function failed
richardv 0:b079fa4ed182 584 */
richardv 0:b079fa4ed182 585 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
richardv 0:b079fa4ed182 586 {
richardv 0:b079fa4ed182 587 uint32_t result;
richardv 0:b079fa4ed182 588
richardv 0:b079fa4ed182 589 __ASM volatile ("strexh %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
richardv 0:b079fa4ed182 590 return(result);
richardv 0:b079fa4ed182 591 }
richardv 0:b079fa4ed182 592
richardv 0:b079fa4ed182 593
richardv 0:b079fa4ed182 594 /** \brief STR Exclusive (32 bit)
richardv 0:b079fa4ed182 595
richardv 0:b079fa4ed182 596 This function performs a exclusive STR command for 32 bit values.
richardv 0:b079fa4ed182 597
richardv 0:b079fa4ed182 598 \param [in] value Value to store
richardv 0:b079fa4ed182 599 \param [in] ptr Pointer to location
richardv 0:b079fa4ed182 600 \return 0 Function succeeded
richardv 0:b079fa4ed182 601 \return 1 Function failed
richardv 0:b079fa4ed182 602 */
richardv 0:b079fa4ed182 603 __attribute__( ( always_inline ) ) __STATIC_INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
richardv 0:b079fa4ed182 604 {
richardv 0:b079fa4ed182 605 uint32_t result;
richardv 0:b079fa4ed182 606
richardv 0:b079fa4ed182 607 __ASM volatile ("strex %0, %2, %1" : "=&r" (result), "=Q" (*addr) : "r" (value) );
richardv 0:b079fa4ed182 608 return(result);
richardv 0:b079fa4ed182 609 }
richardv 0:b079fa4ed182 610
richardv 0:b079fa4ed182 611
richardv 0:b079fa4ed182 612 /** \brief Remove the exclusive lock
richardv 0:b079fa4ed182 613
richardv 0:b079fa4ed182 614 This function removes the exclusive lock which is created by LDREX.
richardv 0:b079fa4ed182 615
richardv 0:b079fa4ed182 616 */
richardv 0:b079fa4ed182 617 __attribute__( ( always_inline ) ) __STATIC_INLINE void __CLREX(void)
richardv 0:b079fa4ed182 618 {
richardv 0:b079fa4ed182 619 __ASM volatile ("clrex" ::: "memory");
richardv 0:b079fa4ed182 620 }
richardv 0:b079fa4ed182 621
richardv 0:b079fa4ed182 622
richardv 0:b079fa4ed182 623 /** \brief Signed Saturate
richardv 0:b079fa4ed182 624
richardv 0:b079fa4ed182 625 This function saturates a signed value.
richardv 0:b079fa4ed182 626
richardv 0:b079fa4ed182 627 \param [in] value Value to be saturated
richardv 0:b079fa4ed182 628 \param [in] sat Bit position to saturate to (1..32)
richardv 0:b079fa4ed182 629 \return Saturated value
richardv 0:b079fa4ed182 630 */
richardv 0:b079fa4ed182 631 #define __SSAT(ARG1,ARG2) \
richardv 0:b079fa4ed182 632 ({ \
richardv 0:b079fa4ed182 633 uint32_t __RES, __ARG1 = (ARG1); \
richardv 0:b079fa4ed182 634 __ASM ("ssat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
richardv 0:b079fa4ed182 635 __RES; \
richardv 0:b079fa4ed182 636 })
richardv 0:b079fa4ed182 637
richardv 0:b079fa4ed182 638
richardv 0:b079fa4ed182 639 /** \brief Unsigned Saturate
richardv 0:b079fa4ed182 640
richardv 0:b079fa4ed182 641 This function saturates an unsigned value.
richardv 0:b079fa4ed182 642
richardv 0:b079fa4ed182 643 \param [in] value Value to be saturated
richardv 0:b079fa4ed182 644 \param [in] sat Bit position to saturate to (0..31)
richardv 0:b079fa4ed182 645 \return Saturated value
richardv 0:b079fa4ed182 646 */
richardv 0:b079fa4ed182 647 #define __USAT(ARG1,ARG2) \
richardv 0:b079fa4ed182 648 ({ \
richardv 0:b079fa4ed182 649 uint32_t __RES, __ARG1 = (ARG1); \
richardv 0:b079fa4ed182 650 __ASM ("usat %0, %1, %2" : "=r" (__RES) : "I" (ARG2), "r" (__ARG1) ); \
richardv 0:b079fa4ed182 651 __RES; \
richardv 0:b079fa4ed182 652 })
richardv 0:b079fa4ed182 653
richardv 0:b079fa4ed182 654
richardv 0:b079fa4ed182 655 /** \brief Count leading zeros
richardv 0:b079fa4ed182 656
richardv 0:b079fa4ed182 657 This function counts the number of leading zeros of a data value.
richardv 0:b079fa4ed182 658
richardv 0:b079fa4ed182 659 \param [in] value Value to count the leading zeros
richardv 0:b079fa4ed182 660 \return number of leading zeros in value
richardv 0:b079fa4ed182 661 */
richardv 0:b079fa4ed182 662 __attribute__( ( always_inline ) ) __STATIC_INLINE uint8_t __CLZ(uint32_t value)
richardv 0:b079fa4ed182 663 {
richardv 0:b079fa4ed182 664 uint32_t result;
richardv 0:b079fa4ed182 665
richardv 0:b079fa4ed182 666 __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
richardv 0:b079fa4ed182 667 return(result);
richardv 0:b079fa4ed182 668 }
richardv 0:b079fa4ed182 669
richardv 0:b079fa4ed182 670 #endif /* (__CORTEX_M >= 0x03) */
richardv 0:b079fa4ed182 671
richardv 0:b079fa4ed182 672
richardv 0:b079fa4ed182 673
richardv 0:b079fa4ed182 674
richardv 0:b079fa4ed182 675 #elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
richardv 0:b079fa4ed182 676 /* TASKING carm specific functions */
richardv 0:b079fa4ed182 677
richardv 0:b079fa4ed182 678 /*
richardv 0:b079fa4ed182 679 * The CMSIS functions have been implemented as intrinsics in the compiler.
richardv 0:b079fa4ed182 680 * Please use "carm -?i" to get an up to date list of all intrinsics,
richardv 0:b079fa4ed182 681 * Including the CMSIS ones.
richardv 0:b079fa4ed182 682 */
richardv 0:b079fa4ed182 683
richardv 0:b079fa4ed182 684 #endif
richardv 0:b079fa4ed182 685
richardv 0:b079fa4ed182 686 /*@}*/ /* end of group CMSIS_Core_InstructionInterface */
richardv 0:b079fa4ed182 687
richardv 0:b079fa4ed182 688 #endif /* __CORE_CMINSTR_H */