Richard Vasquez / DMA_RAM_DAC

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core_cm4.h@0:b079fa4ed182, 2016-11-02 (annotated)

Committer:
richardv
Date:
Wed Nov 02 23:50:52 2016 +0000
Revision:
0:b079fa4ed182
DMA RAM DAC

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richardv 0:b079fa4ed182 1 /**************************************************************************//**
richardv 0:b079fa4ed182 2 * @file core_cm4.h
richardv 0:b079fa4ed182 3 * @brief CMSIS Cortex-M4 Core Peripheral Access Layer Header File
richardv 0:b079fa4ed182 4 * @version V3.20
richardv 0:b079fa4ed182 5 * @date 25. February 2013
richardv 0:b079fa4ed182 6 *
richardv 0:b079fa4ed182 7 * @note
richardv 0:b079fa4ed182 8 *
richardv 0:b079fa4ed182 9 ******************************************************************************/
richardv 0:b079fa4ed182 10 /* Copyright (c) 2009 - 2013 ARM LIMITED
richardv 0:b079fa4ed182 11
richardv 0:b079fa4ed182 12 All rights reserved.
richardv 0:b079fa4ed182 13 Redistribution and use in source and binary forms, with or without
richardv 0:b079fa4ed182 14 modification, are permitted provided that the following conditions are met:
richardv 0:b079fa4ed182 15 - Redistributions of source code must retain the above copyright
richardv 0:b079fa4ed182 16 notice, this list of conditions and the following disclaimer.
richardv 0:b079fa4ed182 17 - Redistributions in binary form must reproduce the above copyright
richardv 0:b079fa4ed182 18 notice, this list of conditions and the following disclaimer in the
richardv 0:b079fa4ed182 19 documentation and/or other materials provided with the distribution.
richardv 0:b079fa4ed182 20 - Neither the name of ARM nor the names of its contributors may be used
richardv 0:b079fa4ed182 21 to endorse or promote products derived from this software without
richardv 0:b079fa4ed182 22 specific prior written permission.
richardv 0:b079fa4ed182 23 *
richardv 0:b079fa4ed182 24 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
richardv 0:b079fa4ed182 25 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
richardv 0:b079fa4ed182 26 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
richardv 0:b079fa4ed182 27 ARE DISCLAIMED. IN NO EVENT SHALL COPYRIGHT HOLDERS AND CONTRIBUTORS BE
richardv 0:b079fa4ed182 28 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
richardv 0:b079fa4ed182 29 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
richardv 0:b079fa4ed182 30 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
richardv 0:b079fa4ed182 31 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
richardv 0:b079fa4ed182 32 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
richardv 0:b079fa4ed182 33 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
richardv 0:b079fa4ed182 34 POSSIBILITY OF SUCH DAMAGE.
richardv 0:b079fa4ed182 35 ---------------------------------------------------------------------------*/
richardv 0:b079fa4ed182 36
richardv 0:b079fa4ed182 37
richardv 0:b079fa4ed182 38 #if defined ( __ICCARM__ )
richardv 0:b079fa4ed182 39 #pragma system_include /* treat file as system include file for MISRA check */
richardv 0:b079fa4ed182 40 #endif
richardv 0:b079fa4ed182 41
richardv 0:b079fa4ed182 42 #ifdef __cplusplus
richardv 0:b079fa4ed182 43 extern "C" {
richardv 0:b079fa4ed182 44 #endif
richardv 0:b079fa4ed182 45
richardv 0:b079fa4ed182 46 #ifndef __CORE_CM4_H_GENERIC
richardv 0:b079fa4ed182 47 #define __CORE_CM4_H_GENERIC
richardv 0:b079fa4ed182 48
richardv 0:b079fa4ed182 49 /** \page CMSIS_MISRA_Exceptions MISRA-C:2004 Compliance Exceptions
richardv 0:b079fa4ed182 50 CMSIS violates the following MISRA-C:2004 rules:
richardv 0:b079fa4ed182 51
richardv 0:b079fa4ed182 52 \li Required Rule 8.5, object/function definition in header file.<br>
richardv 0:b079fa4ed182 53 Function definitions in header files are used to allow 'inlining'.
richardv 0:b079fa4ed182 54
richardv 0:b079fa4ed182 55 \li Required Rule 18.4, declaration of union type or object of union type: '{...}'.<br>
richardv 0:b079fa4ed182 56 Unions are used for effective representation of core registers.
richardv 0:b079fa4ed182 57
richardv 0:b079fa4ed182 58 \li Advisory Rule 19.7, Function-like macro defined.<br>
richardv 0:b079fa4ed182 59 Function-like macros are used to allow more efficient code.
richardv 0:b079fa4ed182 60 */
richardv 0:b079fa4ed182 61
richardv 0:b079fa4ed182 62
richardv 0:b079fa4ed182 63 /*******************************************************************************
richardv 0:b079fa4ed182 64 * CMSIS definitions
richardv 0:b079fa4ed182 65 ******************************************************************************/
richardv 0:b079fa4ed182 66 /** \ingroup Cortex_M4
richardv 0:b079fa4ed182 67 @{
richardv 0:b079fa4ed182 68 */
richardv 0:b079fa4ed182 69
richardv 0:b079fa4ed182 70 /* CMSIS CM4 definitions */
richardv 0:b079fa4ed182 71 #define __CM4_CMSIS_VERSION_MAIN (0x03) /*!< [31:16] CMSIS HAL main version */
richardv 0:b079fa4ed182 72 #define __CM4_CMSIS_VERSION_SUB (0x20) /*!< [15:0] CMSIS HAL sub version */
richardv 0:b079fa4ed182 73 #define __CM4_CMSIS_VERSION ((__CM4_CMSIS_VERSION_MAIN << 16) | \
richardv 0:b079fa4ed182 74 __CM4_CMSIS_VERSION_SUB ) /*!< CMSIS HAL version number */
richardv 0:b079fa4ed182 75
richardv 0:b079fa4ed182 76 #define __CORTEX_M (0x04) /*!< Cortex-M Core */
richardv 0:b079fa4ed182 77
richardv 0:b079fa4ed182 78
richardv 0:b079fa4ed182 79 #if defined ( __CC_ARM )
richardv 0:b079fa4ed182 80 #define __ASM __asm /*!< asm keyword for ARM Compiler */
richardv 0:b079fa4ed182 81 #define __INLINE __inline /*!< inline keyword for ARM Compiler */
richardv 0:b079fa4ed182 82 #define __STATIC_INLINE static __inline
richardv 0:b079fa4ed182 83
richardv 0:b079fa4ed182 84 #elif defined ( __ICCARM__ )
richardv 0:b079fa4ed182 85 #define __ASM __asm /*!< asm keyword for IAR Compiler */
richardv 0:b079fa4ed182 86 #define __INLINE inline /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
richardv 0:b079fa4ed182 87 #define __STATIC_INLINE static inline
richardv 0:b079fa4ed182 88
richardv 0:b079fa4ed182 89 #elif defined ( __TMS470__ )
richardv 0:b079fa4ed182 90 #define __ASM __asm /*!< asm keyword for TI CCS Compiler */
richardv 0:b079fa4ed182 91 #define __STATIC_INLINE static inline
richardv 0:b079fa4ed182 92
richardv 0:b079fa4ed182 93 #elif defined ( __GNUC__ )
richardv 0:b079fa4ed182 94 #define __ASM __asm /*!< asm keyword for GNU Compiler */
richardv 0:b079fa4ed182 95 #define __INLINE inline /*!< inline keyword for GNU Compiler */
richardv 0:b079fa4ed182 96 #define __STATIC_INLINE static inline
richardv 0:b079fa4ed182 97
richardv 0:b079fa4ed182 98 #elif defined ( __TASKING__ )
richardv 0:b079fa4ed182 99 #define __ASM __asm /*!< asm keyword for TASKING Compiler */
richardv 0:b079fa4ed182 100 #define __INLINE inline /*!< inline keyword for TASKING Compiler */
richardv 0:b079fa4ed182 101 #define __STATIC_INLINE static inline
richardv 0:b079fa4ed182 102
richardv 0:b079fa4ed182 103 #endif
richardv 0:b079fa4ed182 104
richardv 0:b079fa4ed182 105 /** __FPU_USED indicates whether an FPU is used or not. For this, __FPU_PRESENT has to be checked prior to making use of FPU specific registers and functions.
richardv 0:b079fa4ed182 106 */
richardv 0:b079fa4ed182 107 #if defined ( __CC_ARM )
richardv 0:b079fa4ed182 108 #if defined __TARGET_FPU_VFP
richardv 0:b079fa4ed182 109 #if (__FPU_PRESENT == 1)
richardv 0:b079fa4ed182 110 #define __FPU_USED 1
richardv 0:b079fa4ed182 111 #else
richardv 0:b079fa4ed182 112 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
richardv 0:b079fa4ed182 113 #define __FPU_USED 0
richardv 0:b079fa4ed182 114 #endif
richardv 0:b079fa4ed182 115 #else
richardv 0:b079fa4ed182 116 #define __FPU_USED 0
richardv 0:b079fa4ed182 117 #endif
richardv 0:b079fa4ed182 118
richardv 0:b079fa4ed182 119 #elif defined ( __ICCARM__ )
richardv 0:b079fa4ed182 120 #if defined __ARMVFP__
richardv 0:b079fa4ed182 121 #if (__FPU_PRESENT == 1)
richardv 0:b079fa4ed182 122 #define __FPU_USED 1
richardv 0:b079fa4ed182 123 #else
richardv 0:b079fa4ed182 124 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
richardv 0:b079fa4ed182 125 #define __FPU_USED 0
richardv 0:b079fa4ed182 126 #endif
richardv 0:b079fa4ed182 127 #else
richardv 0:b079fa4ed182 128 #define __FPU_USED 0
richardv 0:b079fa4ed182 129 #endif
richardv 0:b079fa4ed182 130
richardv 0:b079fa4ed182 131 #elif defined ( __TMS470__ )
richardv 0:b079fa4ed182 132 #if defined __TI_VFP_SUPPORT__
richardv 0:b079fa4ed182 133 #if (__FPU_PRESENT == 1)
richardv 0:b079fa4ed182 134 #define __FPU_USED 1
richardv 0:b079fa4ed182 135 #else
richardv 0:b079fa4ed182 136 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
richardv 0:b079fa4ed182 137 #define __FPU_USED 0
richardv 0:b079fa4ed182 138 #endif
richardv 0:b079fa4ed182 139 #else
richardv 0:b079fa4ed182 140 #define __FPU_USED 0
richardv 0:b079fa4ed182 141 #endif
richardv 0:b079fa4ed182 142
richardv 0:b079fa4ed182 143 #elif defined ( __GNUC__ )
richardv 0:b079fa4ed182 144 #if defined (__VFP_FP__) && !defined(__SOFTFP__)
richardv 0:b079fa4ed182 145 #if (__FPU_PRESENT == 1)
richardv 0:b079fa4ed182 146 #define __FPU_USED 1
richardv 0:b079fa4ed182 147 #else
richardv 0:b079fa4ed182 148 #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
richardv 0:b079fa4ed182 149 #define __FPU_USED 0
richardv 0:b079fa4ed182 150 #endif
richardv 0:b079fa4ed182 151 #else
richardv 0:b079fa4ed182 152 #define __FPU_USED 0
richardv 0:b079fa4ed182 153 #endif
richardv 0:b079fa4ed182 154
richardv 0:b079fa4ed182 155 #elif defined ( __TASKING__ )
richardv 0:b079fa4ed182 156 #if defined __FPU_VFP__
richardv 0:b079fa4ed182 157 #if (__FPU_PRESENT == 1)
richardv 0:b079fa4ed182 158 #define __FPU_USED 1
richardv 0:b079fa4ed182 159 #else
richardv 0:b079fa4ed182 160 #error "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
richardv 0:b079fa4ed182 161 #define __FPU_USED 0
richardv 0:b079fa4ed182 162 #endif
richardv 0:b079fa4ed182 163 #else
richardv 0:b079fa4ed182 164 #define __FPU_USED 0
richardv 0:b079fa4ed182 165 #endif
richardv 0:b079fa4ed182 166 #endif
richardv 0:b079fa4ed182 167
richardv 0:b079fa4ed182 168 #include <stdint.h> /* standard types definitions */
richardv 0:b079fa4ed182 169 #include <core_cmInstr.h> /* Core Instruction Access */
richardv 0:b079fa4ed182 170 #include <core_cmFunc.h> /* Core Function Access */
richardv 0:b079fa4ed182 171 #include <core_cm4_simd.h> /* Compiler specific SIMD Intrinsics */
richardv 0:b079fa4ed182 172
richardv 0:b079fa4ed182 173 #endif /* __CORE_CM4_H_GENERIC */
richardv 0:b079fa4ed182 174
richardv 0:b079fa4ed182 175 #ifndef __CMSIS_GENERIC
richardv 0:b079fa4ed182 176
richardv 0:b079fa4ed182 177 #ifndef __CORE_CM4_H_DEPENDANT
richardv 0:b079fa4ed182 178 #define __CORE_CM4_H_DEPENDANT
richardv 0:b079fa4ed182 179
richardv 0:b079fa4ed182 180 /* check device defines and use defaults */
richardv 0:b079fa4ed182 181 #if defined __CHECK_DEVICE_DEFINES
richardv 0:b079fa4ed182 182 #ifndef __CM4_REV
richardv 0:b079fa4ed182 183 #define __CM4_REV 0x0000
richardv 0:b079fa4ed182 184 #warning "__CM4_REV not defined in device header file; using default!"
richardv 0:b079fa4ed182 185 #endif
richardv 0:b079fa4ed182 186
richardv 0:b079fa4ed182 187 #ifndef __FPU_PRESENT
richardv 0:b079fa4ed182 188 #define __FPU_PRESENT 0
richardv 0:b079fa4ed182 189 #warning "__FPU_PRESENT not defined in device header file; using default!"
richardv 0:b079fa4ed182 190 #endif
richardv 0:b079fa4ed182 191
richardv 0:b079fa4ed182 192 #ifndef __MPU_PRESENT
richardv 0:b079fa4ed182 193 #define __MPU_PRESENT 0
richardv 0:b079fa4ed182 194 #warning "__MPU_PRESENT not defined in device header file; using default!"
richardv 0:b079fa4ed182 195 #endif
richardv 0:b079fa4ed182 196
richardv 0:b079fa4ed182 197 #ifndef __NVIC_PRIO_BITS
richardv 0:b079fa4ed182 198 #define __NVIC_PRIO_BITS 4
richardv 0:b079fa4ed182 199 #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
richardv 0:b079fa4ed182 200 #endif
richardv 0:b079fa4ed182 201
richardv 0:b079fa4ed182 202 #ifndef __Vendor_SysTickConfig
richardv 0:b079fa4ed182 203 #define __Vendor_SysTickConfig 0
richardv 0:b079fa4ed182 204 #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
richardv 0:b079fa4ed182 205 #endif
richardv 0:b079fa4ed182 206 #endif
richardv 0:b079fa4ed182 207
richardv 0:b079fa4ed182 208 /* IO definitions (access restrictions to peripheral registers) */
richardv 0:b079fa4ed182 209 /**
richardv 0:b079fa4ed182 210 \defgroup CMSIS_glob_defs CMSIS Global Defines
richardv 0:b079fa4ed182 211
richardv 0:b079fa4ed182 212 <strong>IO Type Qualifiers</strong> are used
richardv 0:b079fa4ed182 213 \li to specify the access to peripheral variables.
richardv 0:b079fa4ed182 214 \li for automatic generation of peripheral register debug information.
richardv 0:b079fa4ed182 215 */
richardv 0:b079fa4ed182 216 #ifdef __cplusplus
richardv 0:b079fa4ed182 217 #define __I volatile /*!< Defines 'read only' permissions */
richardv 0:b079fa4ed182 218 #else
richardv 0:b079fa4ed182 219 #define __I volatile const /*!< Defines 'read only' permissions */
richardv 0:b079fa4ed182 220 #endif
richardv 0:b079fa4ed182 221 #define __O volatile /*!< Defines 'write only' permissions */
richardv 0:b079fa4ed182 222 #define __IO volatile /*!< Defines 'read / write' permissions */
richardv 0:b079fa4ed182 223
richardv 0:b079fa4ed182 224 /*@} end of group Cortex_M4 */
richardv 0:b079fa4ed182 225
richardv 0:b079fa4ed182 226
richardv 0:b079fa4ed182 227
richardv 0:b079fa4ed182 228 /*******************************************************************************
richardv 0:b079fa4ed182 229 * Register Abstraction
richardv 0:b079fa4ed182 230 Core Register contain:
richardv 0:b079fa4ed182 231 - Core Register
richardv 0:b079fa4ed182 232 - Core NVIC Register
richardv 0:b079fa4ed182 233 - Core SCB Register
richardv 0:b079fa4ed182 234 - Core SysTick Register
richardv 0:b079fa4ed182 235 - Core Debug Register
richardv 0:b079fa4ed182 236 - Core MPU Register
richardv 0:b079fa4ed182 237 - Core FPU Register
richardv 0:b079fa4ed182 238 ******************************************************************************/
richardv 0:b079fa4ed182 239 /** \defgroup CMSIS_core_register Defines and Type Definitions
richardv 0:b079fa4ed182 240 \brief Type definitions and defines for Cortex-M processor based devices.
richardv 0:b079fa4ed182 241 */
richardv 0:b079fa4ed182 242
richardv 0:b079fa4ed182 243 /** \ingroup CMSIS_core_register
richardv 0:b079fa4ed182 244 \defgroup CMSIS_CORE Status and Control Registers
richardv 0:b079fa4ed182 245 \brief Core Register type definitions.
richardv 0:b079fa4ed182 246 @{
richardv 0:b079fa4ed182 247 */
richardv 0:b079fa4ed182 248
richardv 0:b079fa4ed182 249 /** \brief Union type to access the Application Program Status Register (APSR).
richardv 0:b079fa4ed182 250 */
richardv 0:b079fa4ed182 251 typedef union
richardv 0:b079fa4ed182 252 {
richardv 0:b079fa4ed182 253 struct
richardv 0:b079fa4ed182 254 {
richardv 0:b079fa4ed182 255 #if (__CORTEX_M != 0x04)
richardv 0:b079fa4ed182 256 uint32_t _reserved0:27; /*!< bit: 0..26 Reserved */
richardv 0:b079fa4ed182 257 #else
richardv 0:b079fa4ed182 258 uint32_t _reserved0:16; /*!< bit: 0..15 Reserved */
richardv 0:b079fa4ed182 259 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
richardv 0:b079fa4ed182 260 uint32_t _reserved1:7; /*!< bit: 20..26 Reserved */
richardv 0:b079fa4ed182 261 #endif
richardv 0:b079fa4ed182 262 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
richardv 0:b079fa4ed182 263 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
richardv 0:b079fa4ed182 264 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
richardv 0:b079fa4ed182 265 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
richardv 0:b079fa4ed182 266 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
richardv 0:b079fa4ed182 267 } b; /*!< Structure used for bit access */
richardv 0:b079fa4ed182 268 uint32_t w; /*!< Type used for word access */
richardv 0:b079fa4ed182 269 } APSR_Type;
richardv 0:b079fa4ed182 270
richardv 0:b079fa4ed182 271
richardv 0:b079fa4ed182 272 /** \brief Union type to access the Interrupt Program Status Register (IPSR).
richardv 0:b079fa4ed182 273 */
richardv 0:b079fa4ed182 274 typedef union
richardv 0:b079fa4ed182 275 {
richardv 0:b079fa4ed182 276 struct
richardv 0:b079fa4ed182 277 {
richardv 0:b079fa4ed182 278 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
richardv 0:b079fa4ed182 279 uint32_t _reserved0:23; /*!< bit: 9..31 Reserved */
richardv 0:b079fa4ed182 280 } b; /*!< Structure used for bit access */
richardv 0:b079fa4ed182 281 uint32_t w; /*!< Type used for word access */
richardv 0:b079fa4ed182 282 } IPSR_Type;
richardv 0:b079fa4ed182 283
richardv 0:b079fa4ed182 284
richardv 0:b079fa4ed182 285 /** \brief Union type to access the Special-Purpose Program Status Registers (xPSR).
richardv 0:b079fa4ed182 286 */
richardv 0:b079fa4ed182 287 typedef union
richardv 0:b079fa4ed182 288 {
richardv 0:b079fa4ed182 289 struct
richardv 0:b079fa4ed182 290 {
richardv 0:b079fa4ed182 291 uint32_t ISR:9; /*!< bit: 0.. 8 Exception number */
richardv 0:b079fa4ed182 292 #if (__CORTEX_M != 0x04)
richardv 0:b079fa4ed182 293 uint32_t _reserved0:15; /*!< bit: 9..23 Reserved */
richardv 0:b079fa4ed182 294 #else
richardv 0:b079fa4ed182 295 uint32_t _reserved0:7; /*!< bit: 9..15 Reserved */
richardv 0:b079fa4ed182 296 uint32_t GE:4; /*!< bit: 16..19 Greater than or Equal flags */
richardv 0:b079fa4ed182 297 uint32_t _reserved1:4; /*!< bit: 20..23 Reserved */
richardv 0:b079fa4ed182 298 #endif
richardv 0:b079fa4ed182 299 uint32_t T:1; /*!< bit: 24 Thumb bit (read 0) */
richardv 0:b079fa4ed182 300 uint32_t IT:2; /*!< bit: 25..26 saved IT state (read 0) */
richardv 0:b079fa4ed182 301 uint32_t Q:1; /*!< bit: 27 Saturation condition flag */
richardv 0:b079fa4ed182 302 uint32_t V:1; /*!< bit: 28 Overflow condition code flag */
richardv 0:b079fa4ed182 303 uint32_t C:1; /*!< bit: 29 Carry condition code flag */
richardv 0:b079fa4ed182 304 uint32_t Z:1; /*!< bit: 30 Zero condition code flag */
richardv 0:b079fa4ed182 305 uint32_t N:1; /*!< bit: 31 Negative condition code flag */
richardv 0:b079fa4ed182 306 } b; /*!< Structure used for bit access */
richardv 0:b079fa4ed182 307 uint32_t w; /*!< Type used for word access */
richardv 0:b079fa4ed182 308 } xPSR_Type;
richardv 0:b079fa4ed182 309
richardv 0:b079fa4ed182 310
richardv 0:b079fa4ed182 311 /** \brief Union type to access the Control Registers (CONTROL).
richardv 0:b079fa4ed182 312 */
richardv 0:b079fa4ed182 313 typedef union
richardv 0:b079fa4ed182 314 {
richardv 0:b079fa4ed182 315 struct
richardv 0:b079fa4ed182 316 {
richardv 0:b079fa4ed182 317 uint32_t nPRIV:1; /*!< bit: 0 Execution privilege in Thread mode */
richardv 0:b079fa4ed182 318 uint32_t SPSEL:1; /*!< bit: 1 Stack to be used */
richardv 0:b079fa4ed182 319 uint32_t FPCA:1; /*!< bit: 2 FP extension active flag */
richardv 0:b079fa4ed182 320 uint32_t _reserved0:29; /*!< bit: 3..31 Reserved */
richardv 0:b079fa4ed182 321 } b; /*!< Structure used for bit access */
richardv 0:b079fa4ed182 322 uint32_t w; /*!< Type used for word access */
richardv 0:b079fa4ed182 323 } CONTROL_Type;
richardv 0:b079fa4ed182 324
richardv 0:b079fa4ed182 325 /*@} end of group CMSIS_CORE */
richardv 0:b079fa4ed182 326
richardv 0:b079fa4ed182 327
richardv 0:b079fa4ed182 328 /** \ingroup CMSIS_core_register
richardv 0:b079fa4ed182 329 \defgroup CMSIS_NVIC Nested Vectored Interrupt Controller (NVIC)
richardv 0:b079fa4ed182 330 \brief Type definitions for the NVIC Registers
richardv 0:b079fa4ed182 331 @{
richardv 0:b079fa4ed182 332 */
richardv 0:b079fa4ed182 333
richardv 0:b079fa4ed182 334 /** \brief Structure type to access the Nested Vectored Interrupt Controller (NVIC).
richardv 0:b079fa4ed182 335 */
richardv 0:b079fa4ed182 336 typedef struct
richardv 0:b079fa4ed182 337 {
richardv 0:b079fa4ed182 338 __IO uint32_t ISER[8]; /*!< Offset: 0x000 (R/W) Interrupt Set Enable Register */
richardv 0:b079fa4ed182 339 uint32_t RESERVED0[24];
richardv 0:b079fa4ed182 340 __IO uint32_t ICER[8]; /*!< Offset: 0x080 (R/W) Interrupt Clear Enable Register */
richardv 0:b079fa4ed182 341 uint32_t RSERVED1[24];
richardv 0:b079fa4ed182 342 __IO uint32_t ISPR[8]; /*!< Offset: 0x100 (R/W) Interrupt Set Pending Register */
richardv 0:b079fa4ed182 343 uint32_t RESERVED2[24];
richardv 0:b079fa4ed182 344 __IO uint32_t ICPR[8]; /*!< Offset: 0x180 (R/W) Interrupt Clear Pending Register */
richardv 0:b079fa4ed182 345 uint32_t RESERVED3[24];
richardv 0:b079fa4ed182 346 __IO uint32_t IABR[8]; /*!< Offset: 0x200 (R/W) Interrupt Active bit Register */
richardv 0:b079fa4ed182 347 uint32_t RESERVED4[56];
richardv 0:b079fa4ed182 348 __IO uint8_t IP[240]; /*!< Offset: 0x300 (R/W) Interrupt Priority Register (8Bit wide) */
richardv 0:b079fa4ed182 349 uint32_t RESERVED5[644];
richardv 0:b079fa4ed182 350 __O uint32_t STIR; /*!< Offset: 0xE00 ( /W) Software Trigger Interrupt Register */
richardv 0:b079fa4ed182 351 } NVIC_Type;
richardv 0:b079fa4ed182 352
richardv 0:b079fa4ed182 353 /* Software Triggered Interrupt Register Definitions */
richardv 0:b079fa4ed182 354 #define NVIC_STIR_INTID_Pos 0 /*!< STIR: INTLINESNUM Position */
richardv 0:b079fa4ed182 355 #define NVIC_STIR_INTID_Msk (0x1FFUL << NVIC_STIR_INTID_Pos) /*!< STIR: INTLINESNUM Mask */
richardv 0:b079fa4ed182 356
richardv 0:b079fa4ed182 357 /*@} end of group CMSIS_NVIC */
richardv 0:b079fa4ed182 358
richardv 0:b079fa4ed182 359
richardv 0:b079fa4ed182 360 /** \ingroup CMSIS_core_register
richardv 0:b079fa4ed182 361 \defgroup CMSIS_SCB System Control Block (SCB)
richardv 0:b079fa4ed182 362 \brief Type definitions for the System Control Block Registers
richardv 0:b079fa4ed182 363 @{
richardv 0:b079fa4ed182 364 */
richardv 0:b079fa4ed182 365
richardv 0:b079fa4ed182 366 /** \brief Structure type to access the System Control Block (SCB).
richardv 0:b079fa4ed182 367 */
richardv 0:b079fa4ed182 368 typedef struct
richardv 0:b079fa4ed182 369 {
richardv 0:b079fa4ed182 370 __I uint32_t CPUID; /*!< Offset: 0x000 (R/ ) CPUID Base Register */
richardv 0:b079fa4ed182 371 __IO uint32_t ICSR; /*!< Offset: 0x004 (R/W) Interrupt Control and State Register */
richardv 0:b079fa4ed182 372 __IO uint32_t VTOR; /*!< Offset: 0x008 (R/W) Vector Table Offset Register */
richardv 0:b079fa4ed182 373 __IO uint32_t AIRCR; /*!< Offset: 0x00C (R/W) Application Interrupt and Reset Control Register */
richardv 0:b079fa4ed182 374 __IO uint32_t SCR; /*!< Offset: 0x010 (R/W) System Control Register */
richardv 0:b079fa4ed182 375 __IO uint32_t CCR; /*!< Offset: 0x014 (R/W) Configuration Control Register */
richardv 0:b079fa4ed182 376 __IO uint8_t SHP[12]; /*!< Offset: 0x018 (R/W) System Handlers Priority Registers (4-7, 8-11, 12-15) */
richardv 0:b079fa4ed182 377 __IO uint32_t SHCSR; /*!< Offset: 0x024 (R/W) System Handler Control and State Register */
richardv 0:b079fa4ed182 378 __IO uint32_t CFSR; /*!< Offset: 0x028 (R/W) Configurable Fault Status Register */
richardv 0:b079fa4ed182 379 __IO uint32_t HFSR; /*!< Offset: 0x02C (R/W) HardFault Status Register */
richardv 0:b079fa4ed182 380 __IO uint32_t DFSR; /*!< Offset: 0x030 (R/W) Debug Fault Status Register */
richardv 0:b079fa4ed182 381 __IO uint32_t MMFAR; /*!< Offset: 0x034 (R/W) MemManage Fault Address Register */
richardv 0:b079fa4ed182 382 __IO uint32_t BFAR; /*!< Offset: 0x038 (R/W) BusFault Address Register */
richardv 0:b079fa4ed182 383 __IO uint32_t AFSR; /*!< Offset: 0x03C (R/W) Auxiliary Fault Status Register */
richardv 0:b079fa4ed182 384 __I uint32_t PFR[2]; /*!< Offset: 0x040 (R/ ) Processor Feature Register */
richardv 0:b079fa4ed182 385 __I uint32_t DFR; /*!< Offset: 0x048 (R/ ) Debug Feature Register */
richardv 0:b079fa4ed182 386 __I uint32_t ADR; /*!< Offset: 0x04C (R/ ) Auxiliary Feature Register */
richardv 0:b079fa4ed182 387 __I uint32_t MMFR[4]; /*!< Offset: 0x050 (R/ ) Memory Model Feature Register */
richardv 0:b079fa4ed182 388 __I uint32_t ISAR[5]; /*!< Offset: 0x060 (R/ ) Instruction Set Attributes Register */
richardv 0:b079fa4ed182 389 uint32_t RESERVED0[5];
richardv 0:b079fa4ed182 390 __IO uint32_t CPACR; /*!< Offset: 0x088 (R/W) Coprocessor Access Control Register */
richardv 0:b079fa4ed182 391 } SCB_Type;
richardv 0:b079fa4ed182 392
richardv 0:b079fa4ed182 393 /* SCB CPUID Register Definitions */
richardv 0:b079fa4ed182 394 #define SCB_CPUID_IMPLEMENTER_Pos 24 /*!< SCB CPUID: IMPLEMENTER Position */
richardv 0:b079fa4ed182 395 #define SCB_CPUID_IMPLEMENTER_Msk (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos) /*!< SCB CPUID: IMPLEMENTER Mask */
richardv 0:b079fa4ed182 396
richardv 0:b079fa4ed182 397 #define SCB_CPUID_VARIANT_Pos 20 /*!< SCB CPUID: VARIANT Position */
richardv 0:b079fa4ed182 398 #define SCB_CPUID_VARIANT_Msk (0xFUL << SCB_CPUID_VARIANT_Pos) /*!< SCB CPUID: VARIANT Mask */
richardv 0:b079fa4ed182 399
richardv 0:b079fa4ed182 400 #define SCB_CPUID_ARCHITECTURE_Pos 16 /*!< SCB CPUID: ARCHITECTURE Position */
richardv 0:b079fa4ed182 401 #define SCB_CPUID_ARCHITECTURE_Msk (0xFUL << SCB_CPUID_ARCHITECTURE_Pos) /*!< SCB CPUID: ARCHITECTURE Mask */
richardv 0:b079fa4ed182 402
richardv 0:b079fa4ed182 403 #define SCB_CPUID_PARTNO_Pos 4 /*!< SCB CPUID: PARTNO Position */
richardv 0:b079fa4ed182 404 #define SCB_CPUID_PARTNO_Msk (0xFFFUL << SCB_CPUID_PARTNO_Pos) /*!< SCB CPUID: PARTNO Mask */
richardv 0:b079fa4ed182 405
richardv 0:b079fa4ed182 406 #define SCB_CPUID_REVISION_Pos 0 /*!< SCB CPUID: REVISION Position */
richardv 0:b079fa4ed182 407 #define SCB_CPUID_REVISION_Msk (0xFUL << SCB_CPUID_REVISION_Pos) /*!< SCB CPUID: REVISION Mask */
richardv 0:b079fa4ed182 408
richardv 0:b079fa4ed182 409 /* SCB Interrupt Control State Register Definitions */
richardv 0:b079fa4ed182 410 #define SCB_ICSR_NMIPENDSET_Pos 31 /*!< SCB ICSR: NMIPENDSET Position */
richardv 0:b079fa4ed182 411 #define SCB_ICSR_NMIPENDSET_Msk (1UL << SCB_ICSR_NMIPENDSET_Pos) /*!< SCB ICSR: NMIPENDSET Mask */
richardv 0:b079fa4ed182 412
richardv 0:b079fa4ed182 413 #define SCB_ICSR_PENDSVSET_Pos 28 /*!< SCB ICSR: PENDSVSET Position */
richardv 0:b079fa4ed182 414 #define SCB_ICSR_PENDSVSET_Msk (1UL << SCB_ICSR_PENDSVSET_Pos) /*!< SCB ICSR: PENDSVSET Mask */
richardv 0:b079fa4ed182 415
richardv 0:b079fa4ed182 416 #define SCB_ICSR_PENDSVCLR_Pos 27 /*!< SCB ICSR: PENDSVCLR Position */
richardv 0:b079fa4ed182 417 #define SCB_ICSR_PENDSVCLR_Msk (1UL << SCB_ICSR_PENDSVCLR_Pos) /*!< SCB ICSR: PENDSVCLR Mask */
richardv 0:b079fa4ed182 418
richardv 0:b079fa4ed182 419 #define SCB_ICSR_PENDSTSET_Pos 26 /*!< SCB ICSR: PENDSTSET Position */
richardv 0:b079fa4ed182 420 #define SCB_ICSR_PENDSTSET_Msk (1UL << SCB_ICSR_PENDSTSET_Pos) /*!< SCB ICSR: PENDSTSET Mask */
richardv 0:b079fa4ed182 421
richardv 0:b079fa4ed182 422 #define SCB_ICSR_PENDSTCLR_Pos 25 /*!< SCB ICSR: PENDSTCLR Position */
richardv 0:b079fa4ed182 423 #define SCB_ICSR_PENDSTCLR_Msk (1UL << SCB_ICSR_PENDSTCLR_Pos) /*!< SCB ICSR: PENDSTCLR Mask */
richardv 0:b079fa4ed182 424
richardv 0:b079fa4ed182 425 #define SCB_ICSR_ISRPREEMPT_Pos 23 /*!< SCB ICSR: ISRPREEMPT Position */
richardv 0:b079fa4ed182 426 #define SCB_ICSR_ISRPREEMPT_Msk (1UL << SCB_ICSR_ISRPREEMPT_Pos) /*!< SCB ICSR: ISRPREEMPT Mask */
richardv 0:b079fa4ed182 427
richardv 0:b079fa4ed182 428 #define SCB_ICSR_ISRPENDING_Pos 22 /*!< SCB ICSR: ISRPENDING Position */
richardv 0:b079fa4ed182 429 #define SCB_ICSR_ISRPENDING_Msk (1UL << SCB_ICSR_ISRPENDING_Pos) /*!< SCB ICSR: ISRPENDING Mask */
richardv 0:b079fa4ed182 430
richardv 0:b079fa4ed182 431 #define SCB_ICSR_VECTPENDING_Pos 12 /*!< SCB ICSR: VECTPENDING Position */
richardv 0:b079fa4ed182 432 #define SCB_ICSR_VECTPENDING_Msk (0x1FFUL << SCB_ICSR_VECTPENDING_Pos) /*!< SCB ICSR: VECTPENDING Mask */
richardv 0:b079fa4ed182 433
richardv 0:b079fa4ed182 434 #define SCB_ICSR_RETTOBASE_Pos 11 /*!< SCB ICSR: RETTOBASE Position */
richardv 0:b079fa4ed182 435 #define SCB_ICSR_RETTOBASE_Msk (1UL << SCB_ICSR_RETTOBASE_Pos) /*!< SCB ICSR: RETTOBASE Mask */
richardv 0:b079fa4ed182 436
richardv 0:b079fa4ed182 437 #define SCB_ICSR_VECTACTIVE_Pos 0 /*!< SCB ICSR: VECTACTIVE Position */
richardv 0:b079fa4ed182 438 #define SCB_ICSR_VECTACTIVE_Msk (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos) /*!< SCB ICSR: VECTACTIVE Mask */
richardv 0:b079fa4ed182 439
richardv 0:b079fa4ed182 440 /* SCB Vector Table Offset Register Definitions */
richardv 0:b079fa4ed182 441 #define SCB_VTOR_TBLOFF_Pos 7 /*!< SCB VTOR: TBLOFF Position */
richardv 0:b079fa4ed182 442 #define SCB_VTOR_TBLOFF_Msk (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos) /*!< SCB VTOR: TBLOFF Mask */
richardv 0:b079fa4ed182 443
richardv 0:b079fa4ed182 444 /* SCB Application Interrupt and Reset Control Register Definitions */
richardv 0:b079fa4ed182 445 #define SCB_AIRCR_VECTKEY_Pos 16 /*!< SCB AIRCR: VECTKEY Position */
richardv 0:b079fa4ed182 446 #define SCB_AIRCR_VECTKEY_Msk (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos) /*!< SCB AIRCR: VECTKEY Mask */
richardv 0:b079fa4ed182 447
richardv 0:b079fa4ed182 448 #define SCB_AIRCR_VECTKEYSTAT_Pos 16 /*!< SCB AIRCR: VECTKEYSTAT Position */
richardv 0:b079fa4ed182 449 #define SCB_AIRCR_VECTKEYSTAT_Msk (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos) /*!< SCB AIRCR: VECTKEYSTAT Mask */
richardv 0:b079fa4ed182 450
richardv 0:b079fa4ed182 451 #define SCB_AIRCR_ENDIANESS_Pos 15 /*!< SCB AIRCR: ENDIANESS Position */
richardv 0:b079fa4ed182 452 #define SCB_AIRCR_ENDIANESS_Msk (1UL << SCB_AIRCR_ENDIANESS_Pos) /*!< SCB AIRCR: ENDIANESS Mask */
richardv 0:b079fa4ed182 453
richardv 0:b079fa4ed182 454 #define SCB_AIRCR_PRIGROUP_Pos 8 /*!< SCB AIRCR: PRIGROUP Position */
richardv 0:b079fa4ed182 455 #define SCB_AIRCR_PRIGROUP_Msk (7UL << SCB_AIRCR_PRIGROUP_Pos) /*!< SCB AIRCR: PRIGROUP Mask */
richardv 0:b079fa4ed182 456
richardv 0:b079fa4ed182 457 #define SCB_AIRCR_SYSRESETREQ_Pos 2 /*!< SCB AIRCR: SYSRESETREQ Position */
richardv 0:b079fa4ed182 458 #define SCB_AIRCR_SYSRESETREQ_Msk (1UL << SCB_AIRCR_SYSRESETREQ_Pos) /*!< SCB AIRCR: SYSRESETREQ Mask */
richardv 0:b079fa4ed182 459
richardv 0:b079fa4ed182 460 #define SCB_AIRCR_VECTCLRACTIVE_Pos 1 /*!< SCB AIRCR: VECTCLRACTIVE Position */
richardv 0:b079fa4ed182 461 #define SCB_AIRCR_VECTCLRACTIVE_Msk (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos) /*!< SCB AIRCR: VECTCLRACTIVE Mask */
richardv 0:b079fa4ed182 462
richardv 0:b079fa4ed182 463 #define SCB_AIRCR_VECTRESET_Pos 0 /*!< SCB AIRCR: VECTRESET Position */
richardv 0:b079fa4ed182 464 #define SCB_AIRCR_VECTRESET_Msk (1UL << SCB_AIRCR_VECTRESET_Pos) /*!< SCB AIRCR: VECTRESET Mask */
richardv 0:b079fa4ed182 465
richardv 0:b079fa4ed182 466 /* SCB System Control Register Definitions */
richardv 0:b079fa4ed182 467 #define SCB_SCR_SEVONPEND_Pos 4 /*!< SCB SCR: SEVONPEND Position */
richardv 0:b079fa4ed182 468 #define SCB_SCR_SEVONPEND_Msk (1UL << SCB_SCR_SEVONPEND_Pos) /*!< SCB SCR: SEVONPEND Mask */
richardv 0:b079fa4ed182 469
richardv 0:b079fa4ed182 470 #define SCB_SCR_SLEEPDEEP_Pos 2 /*!< SCB SCR: SLEEPDEEP Position */
richardv 0:b079fa4ed182 471 #define SCB_SCR_SLEEPDEEP_Msk (1UL << SCB_SCR_SLEEPDEEP_Pos) /*!< SCB SCR: SLEEPDEEP Mask */
richardv 0:b079fa4ed182 472
richardv 0:b079fa4ed182 473 #define SCB_SCR_SLEEPONEXIT_Pos 1 /*!< SCB SCR: SLEEPONEXIT Position */
richardv 0:b079fa4ed182 474 #define SCB_SCR_SLEEPONEXIT_Msk (1UL << SCB_SCR_SLEEPONEXIT_Pos) /*!< SCB SCR: SLEEPONEXIT Mask */
richardv 0:b079fa4ed182 475
richardv 0:b079fa4ed182 476 /* SCB Configuration Control Register Definitions */
richardv 0:b079fa4ed182 477 #define SCB_CCR_STKALIGN_Pos 9 /*!< SCB CCR: STKALIGN Position */
richardv 0:b079fa4ed182 478 #define SCB_CCR_STKALIGN_Msk (1UL << SCB_CCR_STKALIGN_Pos) /*!< SCB CCR: STKALIGN Mask */
richardv 0:b079fa4ed182 479
richardv 0:b079fa4ed182 480 #define SCB_CCR_BFHFNMIGN_Pos 8 /*!< SCB CCR: BFHFNMIGN Position */
richardv 0:b079fa4ed182 481 #define SCB_CCR_BFHFNMIGN_Msk (1UL << SCB_CCR_BFHFNMIGN_Pos) /*!< SCB CCR: BFHFNMIGN Mask */
richardv 0:b079fa4ed182 482
richardv 0:b079fa4ed182 483 #define SCB_CCR_DIV_0_TRP_Pos 4 /*!< SCB CCR: DIV_0_TRP Position */
richardv 0:b079fa4ed182 484 #define SCB_CCR_DIV_0_TRP_Msk (1UL << SCB_CCR_DIV_0_TRP_Pos) /*!< SCB CCR: DIV_0_TRP Mask */
richardv 0:b079fa4ed182 485
richardv 0:b079fa4ed182 486 #define SCB_CCR_UNALIGN_TRP_Pos 3 /*!< SCB CCR: UNALIGN_TRP Position */
richardv 0:b079fa4ed182 487 #define SCB_CCR_UNALIGN_TRP_Msk (1UL << SCB_CCR_UNALIGN_TRP_Pos) /*!< SCB CCR: UNALIGN_TRP Mask */
richardv 0:b079fa4ed182 488
richardv 0:b079fa4ed182 489 #define SCB_CCR_USERSETMPEND_Pos 1 /*!< SCB CCR: USERSETMPEND Position */
richardv 0:b079fa4ed182 490 #define SCB_CCR_USERSETMPEND_Msk (1UL << SCB_CCR_USERSETMPEND_Pos) /*!< SCB CCR: USERSETMPEND Mask */
richardv 0:b079fa4ed182 491
richardv 0:b079fa4ed182 492 #define SCB_CCR_NONBASETHRDENA_Pos 0 /*!< SCB CCR: NONBASETHRDENA Position */
richardv 0:b079fa4ed182 493 #define SCB_CCR_NONBASETHRDENA_Msk (1UL << SCB_CCR_NONBASETHRDENA_Pos) /*!< SCB CCR: NONBASETHRDENA Mask */
richardv 0:b079fa4ed182 494
richardv 0:b079fa4ed182 495 /* SCB System Handler Control and State Register Definitions */
richardv 0:b079fa4ed182 496 #define SCB_SHCSR_USGFAULTENA_Pos 18 /*!< SCB SHCSR: USGFAULTENA Position */
richardv 0:b079fa4ed182 497 #define SCB_SHCSR_USGFAULTENA_Msk (1UL << SCB_SHCSR_USGFAULTENA_Pos) /*!< SCB SHCSR: USGFAULTENA Mask */
richardv 0:b079fa4ed182 498
richardv 0:b079fa4ed182 499 #define SCB_SHCSR_BUSFAULTENA_Pos 17 /*!< SCB SHCSR: BUSFAULTENA Position */
richardv 0:b079fa4ed182 500 #define SCB_SHCSR_BUSFAULTENA_Msk (1UL << SCB_SHCSR_BUSFAULTENA_Pos) /*!< SCB SHCSR: BUSFAULTENA Mask */
richardv 0:b079fa4ed182 501
richardv 0:b079fa4ed182 502 #define SCB_SHCSR_MEMFAULTENA_Pos 16 /*!< SCB SHCSR: MEMFAULTENA Position */
richardv 0:b079fa4ed182 503 #define SCB_SHCSR_MEMFAULTENA_Msk (1UL << SCB_SHCSR_MEMFAULTENA_Pos) /*!< SCB SHCSR: MEMFAULTENA Mask */
richardv 0:b079fa4ed182 504
richardv 0:b079fa4ed182 505 #define SCB_SHCSR_SVCALLPENDED_Pos 15 /*!< SCB SHCSR: SVCALLPENDED Position */
richardv 0:b079fa4ed182 506 #define SCB_SHCSR_SVCALLPENDED_Msk (1UL << SCB_SHCSR_SVCALLPENDED_Pos) /*!< SCB SHCSR: SVCALLPENDED Mask */
richardv 0:b079fa4ed182 507
richardv 0:b079fa4ed182 508 #define SCB_SHCSR_BUSFAULTPENDED_Pos 14 /*!< SCB SHCSR: BUSFAULTPENDED Position */
richardv 0:b079fa4ed182 509 #define SCB_SHCSR_BUSFAULTPENDED_Msk (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos) /*!< SCB SHCSR: BUSFAULTPENDED Mask */
richardv 0:b079fa4ed182 510
richardv 0:b079fa4ed182 511 #define SCB_SHCSR_MEMFAULTPENDED_Pos 13 /*!< SCB SHCSR: MEMFAULTPENDED Position */
richardv 0:b079fa4ed182 512 #define SCB_SHCSR_MEMFAULTPENDED_Msk (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos) /*!< SCB SHCSR: MEMFAULTPENDED Mask */
richardv 0:b079fa4ed182 513
richardv 0:b079fa4ed182 514 #define SCB_SHCSR_USGFAULTPENDED_Pos 12 /*!< SCB SHCSR: USGFAULTPENDED Position */
richardv 0:b079fa4ed182 515 #define SCB_SHCSR_USGFAULTPENDED_Msk (1UL << SCB_SHCSR_USGFAULTPENDED_Pos) /*!< SCB SHCSR: USGFAULTPENDED Mask */
richardv 0:b079fa4ed182 516
richardv 0:b079fa4ed182 517 #define SCB_SHCSR_SYSTICKACT_Pos 11 /*!< SCB SHCSR: SYSTICKACT Position */
richardv 0:b079fa4ed182 518 #define SCB_SHCSR_SYSTICKACT_Msk (1UL << SCB_SHCSR_SYSTICKACT_Pos) /*!< SCB SHCSR: SYSTICKACT Mask */
richardv 0:b079fa4ed182 519
richardv 0:b079fa4ed182 520 #define SCB_SHCSR_PENDSVACT_Pos 10 /*!< SCB SHCSR: PENDSVACT Position */
richardv 0:b079fa4ed182 521 #define SCB_SHCSR_PENDSVACT_Msk (1UL << SCB_SHCSR_PENDSVACT_Pos) /*!< SCB SHCSR: PENDSVACT Mask */
richardv 0:b079fa4ed182 522
richardv 0:b079fa4ed182 523 #define SCB_SHCSR_MONITORACT_Pos 8 /*!< SCB SHCSR: MONITORACT Position */
richardv 0:b079fa4ed182 524 #define SCB_SHCSR_MONITORACT_Msk (1UL << SCB_SHCSR_MONITORACT_Pos) /*!< SCB SHCSR: MONITORACT Mask */
richardv 0:b079fa4ed182 525
richardv 0:b079fa4ed182 526 #define SCB_SHCSR_SVCALLACT_Pos 7 /*!< SCB SHCSR: SVCALLACT Position */
richardv 0:b079fa4ed182 527 #define SCB_SHCSR_SVCALLACT_Msk (1UL << SCB_SHCSR_SVCALLACT_Pos) /*!< SCB SHCSR: SVCALLACT Mask */
richardv 0:b079fa4ed182 528
richardv 0:b079fa4ed182 529 #define SCB_SHCSR_USGFAULTACT_Pos 3 /*!< SCB SHCSR: USGFAULTACT Position */
richardv 0:b079fa4ed182 530 #define SCB_SHCSR_USGFAULTACT_Msk (1UL << SCB_SHCSR_USGFAULTACT_Pos) /*!< SCB SHCSR: USGFAULTACT Mask */
richardv 0:b079fa4ed182 531
richardv 0:b079fa4ed182 532 #define SCB_SHCSR_BUSFAULTACT_Pos 1 /*!< SCB SHCSR: BUSFAULTACT Position */
richardv 0:b079fa4ed182 533 #define SCB_SHCSR_BUSFAULTACT_Msk (1UL << SCB_SHCSR_BUSFAULTACT_Pos) /*!< SCB SHCSR: BUSFAULTACT Mask */
richardv 0:b079fa4ed182 534
richardv 0:b079fa4ed182 535 #define SCB_SHCSR_MEMFAULTACT_Pos 0 /*!< SCB SHCSR: MEMFAULTACT Position */
richardv 0:b079fa4ed182 536 #define SCB_SHCSR_MEMFAULTACT_Msk (1UL << SCB_SHCSR_MEMFAULTACT_Pos) /*!< SCB SHCSR: MEMFAULTACT Mask */
richardv 0:b079fa4ed182 537
richardv 0:b079fa4ed182 538 /* SCB Configurable Fault Status Registers Definitions */
richardv 0:b079fa4ed182 539 #define SCB_CFSR_USGFAULTSR_Pos 16 /*!< SCB CFSR: Usage Fault Status Register Position */
richardv 0:b079fa4ed182 540 #define SCB_CFSR_USGFAULTSR_Msk (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos) /*!< SCB CFSR: Usage Fault Status Register Mask */
richardv 0:b079fa4ed182 541
richardv 0:b079fa4ed182 542 #define SCB_CFSR_BUSFAULTSR_Pos 8 /*!< SCB CFSR: Bus Fault Status Register Position */
richardv 0:b079fa4ed182 543 #define SCB_CFSR_BUSFAULTSR_Msk (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos) /*!< SCB CFSR: Bus Fault Status Register Mask */
richardv 0:b079fa4ed182 544
richardv 0:b079fa4ed182 545 #define SCB_CFSR_MEMFAULTSR_Pos 0 /*!< SCB CFSR: Memory Manage Fault Status Register Position */
richardv 0:b079fa4ed182 546 #define SCB_CFSR_MEMFAULTSR_Msk (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos) /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
richardv 0:b079fa4ed182 547
richardv 0:b079fa4ed182 548 /* SCB Hard Fault Status Registers Definitions */
richardv 0:b079fa4ed182 549 #define SCB_HFSR_DEBUGEVT_Pos 31 /*!< SCB HFSR: DEBUGEVT Position */
richardv 0:b079fa4ed182 550 #define SCB_HFSR_DEBUGEVT_Msk (1UL << SCB_HFSR_DEBUGEVT_Pos) /*!< SCB HFSR: DEBUGEVT Mask */
richardv 0:b079fa4ed182 551
richardv 0:b079fa4ed182 552 #define SCB_HFSR_FORCED_Pos 30 /*!< SCB HFSR: FORCED Position */
richardv 0:b079fa4ed182 553 #define SCB_HFSR_FORCED_Msk (1UL << SCB_HFSR_FORCED_Pos) /*!< SCB HFSR: FORCED Mask */
richardv 0:b079fa4ed182 554
richardv 0:b079fa4ed182 555 #define SCB_HFSR_VECTTBL_Pos 1 /*!< SCB HFSR: VECTTBL Position */
richardv 0:b079fa4ed182 556 #define SCB_HFSR_VECTTBL_Msk (1UL << SCB_HFSR_VECTTBL_Pos) /*!< SCB HFSR: VECTTBL Mask */
richardv 0:b079fa4ed182 557
richardv 0:b079fa4ed182 558 /* SCB Debug Fault Status Register Definitions */
richardv 0:b079fa4ed182 559 #define SCB_DFSR_EXTERNAL_Pos 4 /*!< SCB DFSR: EXTERNAL Position */
richardv 0:b079fa4ed182 560 #define SCB_DFSR_EXTERNAL_Msk (1UL << SCB_DFSR_EXTERNAL_Pos) /*!< SCB DFSR: EXTERNAL Mask */
richardv 0:b079fa4ed182 561
richardv 0:b079fa4ed182 562 #define SCB_DFSR_VCATCH_Pos 3 /*!< SCB DFSR: VCATCH Position */
richardv 0:b079fa4ed182 563 #define SCB_DFSR_VCATCH_Msk (1UL << SCB_DFSR_VCATCH_Pos) /*!< SCB DFSR: VCATCH Mask */
richardv 0:b079fa4ed182 564
richardv 0:b079fa4ed182 565 #define SCB_DFSR_DWTTRAP_Pos 2 /*!< SCB DFSR: DWTTRAP Position */
richardv 0:b079fa4ed182 566 #define SCB_DFSR_DWTTRAP_Msk (1UL << SCB_DFSR_DWTTRAP_Pos) /*!< SCB DFSR: DWTTRAP Mask */
richardv 0:b079fa4ed182 567
richardv 0:b079fa4ed182 568 #define SCB_DFSR_BKPT_Pos 1 /*!< SCB DFSR: BKPT Position */
richardv 0:b079fa4ed182 569 #define SCB_DFSR_BKPT_Msk (1UL << SCB_DFSR_BKPT_Pos) /*!< SCB DFSR: BKPT Mask */
richardv 0:b079fa4ed182 570
richardv 0:b079fa4ed182 571 #define SCB_DFSR_HALTED_Pos 0 /*!< SCB DFSR: HALTED Position */
richardv 0:b079fa4ed182 572 #define SCB_DFSR_HALTED_Msk (1UL << SCB_DFSR_HALTED_Pos) /*!< SCB DFSR: HALTED Mask */
richardv 0:b079fa4ed182 573
richardv 0:b079fa4ed182 574 /*@} end of group CMSIS_SCB */
richardv 0:b079fa4ed182 575
richardv 0:b079fa4ed182 576
richardv 0:b079fa4ed182 577 /** \ingroup CMSIS_core_register
richardv 0:b079fa4ed182 578 \defgroup CMSIS_SCnSCB System Controls not in SCB (SCnSCB)
richardv 0:b079fa4ed182 579 \brief Type definitions for the System Control and ID Register not in the SCB
richardv 0:b079fa4ed182 580 @{
richardv 0:b079fa4ed182 581 */
richardv 0:b079fa4ed182 582
richardv 0:b079fa4ed182 583 /** \brief Structure type to access the System Control and ID Register not in the SCB.
richardv 0:b079fa4ed182 584 */
richardv 0:b079fa4ed182 585 typedef struct
richardv 0:b079fa4ed182 586 {
richardv 0:b079fa4ed182 587 uint32_t RESERVED0[1];
richardv 0:b079fa4ed182 588 __I uint32_t ICTR; /*!< Offset: 0x004 (R/ ) Interrupt Controller Type Register */
richardv 0:b079fa4ed182 589 __IO uint32_t ACTLR; /*!< Offset: 0x008 (R/W) Auxiliary Control Register */
richardv 0:b079fa4ed182 590 } SCnSCB_Type;
richardv 0:b079fa4ed182 591
richardv 0:b079fa4ed182 592 /* Interrupt Controller Type Register Definitions */
richardv 0:b079fa4ed182 593 #define SCnSCB_ICTR_INTLINESNUM_Pos 0 /*!< ICTR: INTLINESNUM Position */
richardv 0:b079fa4ed182 594 #define SCnSCB_ICTR_INTLINESNUM_Msk (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos) /*!< ICTR: INTLINESNUM Mask */
richardv 0:b079fa4ed182 595
richardv 0:b079fa4ed182 596 /* Auxiliary Control Register Definitions */
richardv 0:b079fa4ed182 597 #define SCnSCB_ACTLR_DISOOFP_Pos 9 /*!< ACTLR: DISOOFP Position */
richardv 0:b079fa4ed182 598 #define SCnSCB_ACTLR_DISOOFP_Msk (1UL << SCnSCB_ACTLR_DISOOFP_Pos) /*!< ACTLR: DISOOFP Mask */
richardv 0:b079fa4ed182 599
richardv 0:b079fa4ed182 600 #define SCnSCB_ACTLR_DISFPCA_Pos 8 /*!< ACTLR: DISFPCA Position */
richardv 0:b079fa4ed182 601 #define SCnSCB_ACTLR_DISFPCA_Msk (1UL << SCnSCB_ACTLR_DISFPCA_Pos) /*!< ACTLR: DISFPCA Mask */
richardv 0:b079fa4ed182 602
richardv 0:b079fa4ed182 603 #define SCnSCB_ACTLR_DISFOLD_Pos 2 /*!< ACTLR: DISFOLD Position */
richardv 0:b079fa4ed182 604 #define SCnSCB_ACTLR_DISFOLD_Msk (1UL << SCnSCB_ACTLR_DISFOLD_Pos) /*!< ACTLR: DISFOLD Mask */
richardv 0:b079fa4ed182 605
richardv 0:b079fa4ed182 606 #define SCnSCB_ACTLR_DISDEFWBUF_Pos 1 /*!< ACTLR: DISDEFWBUF Position */
richardv 0:b079fa4ed182 607 #define SCnSCB_ACTLR_DISDEFWBUF_Msk (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos) /*!< ACTLR: DISDEFWBUF Mask */
richardv 0:b079fa4ed182 608
richardv 0:b079fa4ed182 609 #define SCnSCB_ACTLR_DISMCYCINT_Pos 0 /*!< ACTLR: DISMCYCINT Position */
richardv 0:b079fa4ed182 610 #define SCnSCB_ACTLR_DISMCYCINT_Msk (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos) /*!< ACTLR: DISMCYCINT Mask */
richardv 0:b079fa4ed182 611
richardv 0:b079fa4ed182 612 /*@} end of group CMSIS_SCnotSCB */
richardv 0:b079fa4ed182 613
richardv 0:b079fa4ed182 614
richardv 0:b079fa4ed182 615 /** \ingroup CMSIS_core_register
richardv 0:b079fa4ed182 616 \defgroup CMSIS_SysTick System Tick Timer (SysTick)
richardv 0:b079fa4ed182 617 \brief Type definitions for the System Timer Registers.
richardv 0:b079fa4ed182 618 @{
richardv 0:b079fa4ed182 619 */
richardv 0:b079fa4ed182 620
richardv 0:b079fa4ed182 621 /** \brief Structure type to access the System Timer (SysTick).
richardv 0:b079fa4ed182 622 */
richardv 0:b079fa4ed182 623 typedef struct
richardv 0:b079fa4ed182 624 {
richardv 0:b079fa4ed182 625 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) SysTick Control and Status Register */
richardv 0:b079fa4ed182 626 __IO uint32_t LOAD; /*!< Offset: 0x004 (R/W) SysTick Reload Value Register */
richardv 0:b079fa4ed182 627 __IO uint32_t VAL; /*!< Offset: 0x008 (R/W) SysTick Current Value Register */
richardv 0:b079fa4ed182 628 __I uint32_t CALIB; /*!< Offset: 0x00C (R/ ) SysTick Calibration Register */
richardv 0:b079fa4ed182 629 } SysTick_Type;
richardv 0:b079fa4ed182 630
richardv 0:b079fa4ed182 631 /* SysTick Control / Status Register Definitions */
richardv 0:b079fa4ed182 632 #define SysTick_CTRL_COUNTFLAG_Pos 16 /*!< SysTick CTRL: COUNTFLAG Position */
richardv 0:b079fa4ed182 633 #define SysTick_CTRL_COUNTFLAG_Msk (1UL << SysTick_CTRL_COUNTFLAG_Pos) /*!< SysTick CTRL: COUNTFLAG Mask */
richardv 0:b079fa4ed182 634
richardv 0:b079fa4ed182 635 #define SysTick_CTRL_CLKSOURCE_Pos 2 /*!< SysTick CTRL: CLKSOURCE Position */
richardv 0:b079fa4ed182 636 #define SysTick_CTRL_CLKSOURCE_Msk (1UL << SysTick_CTRL_CLKSOURCE_Pos) /*!< SysTick CTRL: CLKSOURCE Mask */
richardv 0:b079fa4ed182 637
richardv 0:b079fa4ed182 638 #define SysTick_CTRL_TICKINT_Pos 1 /*!< SysTick CTRL: TICKINT Position */
richardv 0:b079fa4ed182 639 #define SysTick_CTRL_TICKINT_Msk (1UL << SysTick_CTRL_TICKINT_Pos) /*!< SysTick CTRL: TICKINT Mask */
richardv 0:b079fa4ed182 640
richardv 0:b079fa4ed182 641 #define SysTick_CTRL_ENABLE_Pos 0 /*!< SysTick CTRL: ENABLE Position */
richardv 0:b079fa4ed182 642 #define SysTick_CTRL_ENABLE_Msk (1UL << SysTick_CTRL_ENABLE_Pos) /*!< SysTick CTRL: ENABLE Mask */
richardv 0:b079fa4ed182 643
richardv 0:b079fa4ed182 644 /* SysTick Reload Register Definitions */
richardv 0:b079fa4ed182 645 #define SysTick_LOAD_RELOAD_Pos 0 /*!< SysTick LOAD: RELOAD Position */
richardv 0:b079fa4ed182 646 #define SysTick_LOAD_RELOAD_Msk (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos) /*!< SysTick LOAD: RELOAD Mask */
richardv 0:b079fa4ed182 647
richardv 0:b079fa4ed182 648 /* SysTick Current Register Definitions */
richardv 0:b079fa4ed182 649 #define SysTick_VAL_CURRENT_Pos 0 /*!< SysTick VAL: CURRENT Position */
richardv 0:b079fa4ed182 650 #define SysTick_VAL_CURRENT_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick VAL: CURRENT Mask */
richardv 0:b079fa4ed182 651
richardv 0:b079fa4ed182 652 /* SysTick Calibration Register Definitions */
richardv 0:b079fa4ed182 653 #define SysTick_CALIB_NOREF_Pos 31 /*!< SysTick CALIB: NOREF Position */
richardv 0:b079fa4ed182 654 #define SysTick_CALIB_NOREF_Msk (1UL << SysTick_CALIB_NOREF_Pos) /*!< SysTick CALIB: NOREF Mask */
richardv 0:b079fa4ed182 655
richardv 0:b079fa4ed182 656 #define SysTick_CALIB_SKEW_Pos 30 /*!< SysTick CALIB: SKEW Position */
richardv 0:b079fa4ed182 657 #define SysTick_CALIB_SKEW_Msk (1UL << SysTick_CALIB_SKEW_Pos) /*!< SysTick CALIB: SKEW Mask */
richardv 0:b079fa4ed182 658
richardv 0:b079fa4ed182 659 #define SysTick_CALIB_TENMS_Pos 0 /*!< SysTick CALIB: TENMS Position */
richardv 0:b079fa4ed182 660 #define SysTick_CALIB_TENMS_Msk (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos) /*!< SysTick CALIB: TENMS Mask */
richardv 0:b079fa4ed182 661
richardv 0:b079fa4ed182 662 /*@} end of group CMSIS_SysTick */
richardv 0:b079fa4ed182 663
richardv 0:b079fa4ed182 664
richardv 0:b079fa4ed182 665 /** \ingroup CMSIS_core_register
richardv 0:b079fa4ed182 666 \defgroup CMSIS_ITM Instrumentation Trace Macrocell (ITM)
richardv 0:b079fa4ed182 667 \brief Type definitions for the Instrumentation Trace Macrocell (ITM)
richardv 0:b079fa4ed182 668 @{
richardv 0:b079fa4ed182 669 */
richardv 0:b079fa4ed182 670
richardv 0:b079fa4ed182 671 /** \brief Structure type to access the Instrumentation Trace Macrocell Register (ITM).
richardv 0:b079fa4ed182 672 */
richardv 0:b079fa4ed182 673 typedef struct
richardv 0:b079fa4ed182 674 {
richardv 0:b079fa4ed182 675 __O union
richardv 0:b079fa4ed182 676 {
richardv 0:b079fa4ed182 677 __O uint8_t u8; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 8-bit */
richardv 0:b079fa4ed182 678 __O uint16_t u16; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 16-bit */
richardv 0:b079fa4ed182 679 __O uint32_t u32; /*!< Offset: 0x000 ( /W) ITM Stimulus Port 32-bit */
richardv 0:b079fa4ed182 680 } PORT [32]; /*!< Offset: 0x000 ( /W) ITM Stimulus Port Registers */
richardv 0:b079fa4ed182 681 uint32_t RESERVED0[864];
richardv 0:b079fa4ed182 682 __IO uint32_t TER; /*!< Offset: 0xE00 (R/W) ITM Trace Enable Register */
richardv 0:b079fa4ed182 683 uint32_t RESERVED1[15];
richardv 0:b079fa4ed182 684 __IO uint32_t TPR; /*!< Offset: 0xE40 (R/W) ITM Trace Privilege Register */
richardv 0:b079fa4ed182 685 uint32_t RESERVED2[15];
richardv 0:b079fa4ed182 686 __IO uint32_t TCR; /*!< Offset: 0xE80 (R/W) ITM Trace Control Register */
richardv 0:b079fa4ed182 687 uint32_t RESERVED3[29];
richardv 0:b079fa4ed182 688 __O uint32_t IWR; /*!< Offset: 0xEF8 ( /W) ITM Integration Write Register */
richardv 0:b079fa4ed182 689 __I uint32_t IRR; /*!< Offset: 0xEFC (R/ ) ITM Integration Read Register */
richardv 0:b079fa4ed182 690 __IO uint32_t IMCR; /*!< Offset: 0xF00 (R/W) ITM Integration Mode Control Register */
richardv 0:b079fa4ed182 691 uint32_t RESERVED4[43];
richardv 0:b079fa4ed182 692 __O uint32_t LAR; /*!< Offset: 0xFB0 ( /W) ITM Lock Access Register */
richardv 0:b079fa4ed182 693 __I uint32_t LSR; /*!< Offset: 0xFB4 (R/ ) ITM Lock Status Register */
richardv 0:b079fa4ed182 694 uint32_t RESERVED5[6];
richardv 0:b079fa4ed182 695 __I uint32_t PID4; /*!< Offset: 0xFD0 (R/ ) ITM Peripheral Identification Register #4 */
richardv 0:b079fa4ed182 696 __I uint32_t PID5; /*!< Offset: 0xFD4 (R/ ) ITM Peripheral Identification Register #5 */
richardv 0:b079fa4ed182 697 __I uint32_t PID6; /*!< Offset: 0xFD8 (R/ ) ITM Peripheral Identification Register #6 */
richardv 0:b079fa4ed182 698 __I uint32_t PID7; /*!< Offset: 0xFDC (R/ ) ITM Peripheral Identification Register #7 */
richardv 0:b079fa4ed182 699 __I uint32_t PID0; /*!< Offset: 0xFE0 (R/ ) ITM Peripheral Identification Register #0 */
richardv 0:b079fa4ed182 700 __I uint32_t PID1; /*!< Offset: 0xFE4 (R/ ) ITM Peripheral Identification Register #1 */
richardv 0:b079fa4ed182 701 __I uint32_t PID2; /*!< Offset: 0xFE8 (R/ ) ITM Peripheral Identification Register #2 */
richardv 0:b079fa4ed182 702 __I uint32_t PID3; /*!< Offset: 0xFEC (R/ ) ITM Peripheral Identification Register #3 */
richardv 0:b079fa4ed182 703 __I uint32_t CID0; /*!< Offset: 0xFF0 (R/ ) ITM Component Identification Register #0 */
richardv 0:b079fa4ed182 704 __I uint32_t CID1; /*!< Offset: 0xFF4 (R/ ) ITM Component Identification Register #1 */
richardv 0:b079fa4ed182 705 __I uint32_t CID2; /*!< Offset: 0xFF8 (R/ ) ITM Component Identification Register #2 */
richardv 0:b079fa4ed182 706 __I uint32_t CID3; /*!< Offset: 0xFFC (R/ ) ITM Component Identification Register #3 */
richardv 0:b079fa4ed182 707 } ITM_Type;
richardv 0:b079fa4ed182 708
richardv 0:b079fa4ed182 709 /* ITM Trace Privilege Register Definitions */
richardv 0:b079fa4ed182 710 #define ITM_TPR_PRIVMASK_Pos 0 /*!< ITM TPR: PRIVMASK Position */
richardv 0:b079fa4ed182 711 #define ITM_TPR_PRIVMASK_Msk (0xFUL << ITM_TPR_PRIVMASK_Pos) /*!< ITM TPR: PRIVMASK Mask */
richardv 0:b079fa4ed182 712
richardv 0:b079fa4ed182 713 /* ITM Trace Control Register Definitions */
richardv 0:b079fa4ed182 714 #define ITM_TCR_BUSY_Pos 23 /*!< ITM TCR: BUSY Position */
richardv 0:b079fa4ed182 715 #define ITM_TCR_BUSY_Msk (1UL << ITM_TCR_BUSY_Pos) /*!< ITM TCR: BUSY Mask */
richardv 0:b079fa4ed182 716
richardv 0:b079fa4ed182 717 #define ITM_TCR_TraceBusID_Pos 16 /*!< ITM TCR: ATBID Position */
richardv 0:b079fa4ed182 718 #define ITM_TCR_TraceBusID_Msk (0x7FUL << ITM_TCR_TraceBusID_Pos) /*!< ITM TCR: ATBID Mask */
richardv 0:b079fa4ed182 719
richardv 0:b079fa4ed182 720 #define ITM_TCR_GTSFREQ_Pos 10 /*!< ITM TCR: Global timestamp frequency Position */
richardv 0:b079fa4ed182 721 #define ITM_TCR_GTSFREQ_Msk (3UL << ITM_TCR_GTSFREQ_Pos) /*!< ITM TCR: Global timestamp frequency Mask */
richardv 0:b079fa4ed182 722
richardv 0:b079fa4ed182 723 #define ITM_TCR_TSPrescale_Pos 8 /*!< ITM TCR: TSPrescale Position */
richardv 0:b079fa4ed182 724 #define ITM_TCR_TSPrescale_Msk (3UL << ITM_TCR_TSPrescale_Pos) /*!< ITM TCR: TSPrescale Mask */
richardv 0:b079fa4ed182 725
richardv 0:b079fa4ed182 726 #define ITM_TCR_SWOENA_Pos 4 /*!< ITM TCR: SWOENA Position */
richardv 0:b079fa4ed182 727 #define ITM_TCR_SWOENA_Msk (1UL << ITM_TCR_SWOENA_Pos) /*!< ITM TCR: SWOENA Mask */
richardv 0:b079fa4ed182 728
richardv 0:b079fa4ed182 729 #define ITM_TCR_DWTENA_Pos 3 /*!< ITM TCR: DWTENA Position */
richardv 0:b079fa4ed182 730 #define ITM_TCR_DWTENA_Msk (1UL << ITM_TCR_DWTENA_Pos) /*!< ITM TCR: DWTENA Mask */
richardv 0:b079fa4ed182 731
richardv 0:b079fa4ed182 732 #define ITM_TCR_SYNCENA_Pos 2 /*!< ITM TCR: SYNCENA Position */
richardv 0:b079fa4ed182 733 #define ITM_TCR_SYNCENA_Msk (1UL << ITM_TCR_SYNCENA_Pos) /*!< ITM TCR: SYNCENA Mask */
richardv 0:b079fa4ed182 734
richardv 0:b079fa4ed182 735 #define ITM_TCR_TSENA_Pos 1 /*!< ITM TCR: TSENA Position */
richardv 0:b079fa4ed182 736 #define ITM_TCR_TSENA_Msk (1UL << ITM_TCR_TSENA_Pos) /*!< ITM TCR: TSENA Mask */
richardv 0:b079fa4ed182 737
richardv 0:b079fa4ed182 738 #define ITM_TCR_ITMENA_Pos 0 /*!< ITM TCR: ITM Enable bit Position */
richardv 0:b079fa4ed182 739 #define ITM_TCR_ITMENA_Msk (1UL << ITM_TCR_ITMENA_Pos) /*!< ITM TCR: ITM Enable bit Mask */
richardv 0:b079fa4ed182 740
richardv 0:b079fa4ed182 741 /* ITM Integration Write Register Definitions */
richardv 0:b079fa4ed182 742 #define ITM_IWR_ATVALIDM_Pos 0 /*!< ITM IWR: ATVALIDM Position */
richardv 0:b079fa4ed182 743 #define ITM_IWR_ATVALIDM_Msk (1UL << ITM_IWR_ATVALIDM_Pos) /*!< ITM IWR: ATVALIDM Mask */
richardv 0:b079fa4ed182 744
richardv 0:b079fa4ed182 745 /* ITM Integration Read Register Definitions */
richardv 0:b079fa4ed182 746 #define ITM_IRR_ATREADYM_Pos 0 /*!< ITM IRR: ATREADYM Position */
richardv 0:b079fa4ed182 747 #define ITM_IRR_ATREADYM_Msk (1UL << ITM_IRR_ATREADYM_Pos) /*!< ITM IRR: ATREADYM Mask */
richardv 0:b079fa4ed182 748
richardv 0:b079fa4ed182 749 /* ITM Integration Mode Control Register Definitions */
richardv 0:b079fa4ed182 750 #define ITM_IMCR_INTEGRATION_Pos 0 /*!< ITM IMCR: INTEGRATION Position */
richardv 0:b079fa4ed182 751 #define ITM_IMCR_INTEGRATION_Msk (1UL << ITM_IMCR_INTEGRATION_Pos) /*!< ITM IMCR: INTEGRATION Mask */
richardv 0:b079fa4ed182 752
richardv 0:b079fa4ed182 753 /* ITM Lock Status Register Definitions */
richardv 0:b079fa4ed182 754 #define ITM_LSR_ByteAcc_Pos 2 /*!< ITM LSR: ByteAcc Position */
richardv 0:b079fa4ed182 755 #define ITM_LSR_ByteAcc_Msk (1UL << ITM_LSR_ByteAcc_Pos) /*!< ITM LSR: ByteAcc Mask */
richardv 0:b079fa4ed182 756
richardv 0:b079fa4ed182 757 #define ITM_LSR_Access_Pos 1 /*!< ITM LSR: Access Position */
richardv 0:b079fa4ed182 758 #define ITM_LSR_Access_Msk (1UL << ITM_LSR_Access_Pos) /*!< ITM LSR: Access Mask */
richardv 0:b079fa4ed182 759
richardv 0:b079fa4ed182 760 #define ITM_LSR_Present_Pos 0 /*!< ITM LSR: Present Position */
richardv 0:b079fa4ed182 761 #define ITM_LSR_Present_Msk (1UL << ITM_LSR_Present_Pos) /*!< ITM LSR: Present Mask */
richardv 0:b079fa4ed182 762
richardv 0:b079fa4ed182 763 /*@}*/ /* end of group CMSIS_ITM */
richardv 0:b079fa4ed182 764
richardv 0:b079fa4ed182 765
richardv 0:b079fa4ed182 766 /** \ingroup CMSIS_core_register
richardv 0:b079fa4ed182 767 \defgroup CMSIS_DWT Data Watchpoint and Trace (DWT)
richardv 0:b079fa4ed182 768 \brief Type definitions for the Data Watchpoint and Trace (DWT)
richardv 0:b079fa4ed182 769 @{
richardv 0:b079fa4ed182 770 */
richardv 0:b079fa4ed182 771
richardv 0:b079fa4ed182 772 /** \brief Structure type to access the Data Watchpoint and Trace Register (DWT).
richardv 0:b079fa4ed182 773 */
richardv 0:b079fa4ed182 774 typedef struct
richardv 0:b079fa4ed182 775 {
richardv 0:b079fa4ed182 776 __IO uint32_t CTRL; /*!< Offset: 0x000 (R/W) Control Register */
richardv 0:b079fa4ed182 777 __IO uint32_t CYCCNT; /*!< Offset: 0x004 (R/W) Cycle Count Register */
richardv 0:b079fa4ed182 778 __IO uint32_t CPICNT; /*!< Offset: 0x008 (R/W) CPI Count Register */
richardv 0:b079fa4ed182 779 __IO uint32_t EXCCNT; /*!< Offset: 0x00C (R/W) Exception Overhead Count Register */
richardv 0:b079fa4ed182 780 __IO uint32_t SLEEPCNT; /*!< Offset: 0x010 (R/W) Sleep Count Register */
richardv 0:b079fa4ed182 781 __IO uint32_t LSUCNT; /*!< Offset: 0x014 (R/W) LSU Count Register */
richardv 0:b079fa4ed182 782 __IO uint32_t FOLDCNT; /*!< Offset: 0x018 (R/W) Folded-instruction Count Register */
richardv 0:b079fa4ed182 783 __I uint32_t PCSR; /*!< Offset: 0x01C (R/ ) Program Counter Sample Register */
richardv 0:b079fa4ed182 784 __IO uint32_t COMP0; /*!< Offset: 0x020 (R/W) Comparator Register 0 */
richardv 0:b079fa4ed182 785 __IO uint32_t MASK0; /*!< Offset: 0x024 (R/W) Mask Register 0 */
richardv 0:b079fa4ed182 786 __IO uint32_t FUNCTION0; /*!< Offset: 0x028 (R/W) Function Register 0 */
richardv 0:b079fa4ed182 787 uint32_t RESERVED0[1];
richardv 0:b079fa4ed182 788 __IO uint32_t COMP1; /*!< Offset: 0x030 (R/W) Comparator Register 1 */
richardv 0:b079fa4ed182 789 __IO uint32_t MASK1; /*!< Offset: 0x034 (R/W) Mask Register 1 */
richardv 0:b079fa4ed182 790 __IO uint32_t FUNCTION1; /*!< Offset: 0x038 (R/W) Function Register 1 */
richardv 0:b079fa4ed182 791 uint32_t RESERVED1[1];
richardv 0:b079fa4ed182 792 __IO uint32_t COMP2; /*!< Offset: 0x040 (R/W) Comparator Register 2 */
richardv 0:b079fa4ed182 793 __IO uint32_t MASK2; /*!< Offset: 0x044 (R/W) Mask Register 2 */
richardv 0:b079fa4ed182 794 __IO uint32_t FUNCTION2; /*!< Offset: 0x048 (R/W) Function Register 2 */
richardv 0:b079fa4ed182 795 uint32_t RESERVED2[1];
richardv 0:b079fa4ed182 796 __IO uint32_t COMP3; /*!< Offset: 0x050 (R/W) Comparator Register 3 */
richardv 0:b079fa4ed182 797 __IO uint32_t MASK3; /*!< Offset: 0x054 (R/W) Mask Register 3 */
richardv 0:b079fa4ed182 798 __IO uint32_t FUNCTION3; /*!< Offset: 0x058 (R/W) Function Register 3 */
richardv 0:b079fa4ed182 799 } DWT_Type;
richardv 0:b079fa4ed182 800
richardv 0:b079fa4ed182 801 /* DWT Control Register Definitions */
richardv 0:b079fa4ed182 802 #define DWT_CTRL_NUMCOMP_Pos 28 /*!< DWT CTRL: NUMCOMP Position */
richardv 0:b079fa4ed182 803 #define DWT_CTRL_NUMCOMP_Msk (0xFUL << DWT_CTRL_NUMCOMP_Pos) /*!< DWT CTRL: NUMCOMP Mask */
richardv 0:b079fa4ed182 804
richardv 0:b079fa4ed182 805 #define DWT_CTRL_NOTRCPKT_Pos 27 /*!< DWT CTRL: NOTRCPKT Position */
richardv 0:b079fa4ed182 806 #define DWT_CTRL_NOTRCPKT_Msk (0x1UL << DWT_CTRL_NOTRCPKT_Pos) /*!< DWT CTRL: NOTRCPKT Mask */
richardv 0:b079fa4ed182 807
richardv 0:b079fa4ed182 808 #define DWT_CTRL_NOEXTTRIG_Pos 26 /*!< DWT CTRL: NOEXTTRIG Position */
richardv 0:b079fa4ed182 809 #define DWT_CTRL_NOEXTTRIG_Msk (0x1UL << DWT_CTRL_NOEXTTRIG_Pos) /*!< DWT CTRL: NOEXTTRIG Mask */
richardv 0:b079fa4ed182 810
richardv 0:b079fa4ed182 811 #define DWT_CTRL_NOCYCCNT_Pos 25 /*!< DWT CTRL: NOCYCCNT Position */
richardv 0:b079fa4ed182 812 #define DWT_CTRL_NOCYCCNT_Msk (0x1UL << DWT_CTRL_NOCYCCNT_Pos) /*!< DWT CTRL: NOCYCCNT Mask */
richardv 0:b079fa4ed182 813
richardv 0:b079fa4ed182 814 #define DWT_CTRL_NOPRFCNT_Pos 24 /*!< DWT CTRL: NOPRFCNT Position */
richardv 0:b079fa4ed182 815 #define DWT_CTRL_NOPRFCNT_Msk (0x1UL << DWT_CTRL_NOPRFCNT_Pos) /*!< DWT CTRL: NOPRFCNT Mask */
richardv 0:b079fa4ed182 816
richardv 0:b079fa4ed182 817 #define DWT_CTRL_CYCEVTENA_Pos 22 /*!< DWT CTRL: CYCEVTENA Position */
richardv 0:b079fa4ed182 818 #define DWT_CTRL_CYCEVTENA_Msk (0x1UL << DWT_CTRL_CYCEVTENA_Pos) /*!< DWT CTRL: CYCEVTENA Mask */
richardv 0:b079fa4ed182 819
richardv 0:b079fa4ed182 820 #define DWT_CTRL_FOLDEVTENA_Pos 21 /*!< DWT CTRL: FOLDEVTENA Position */
richardv 0:b079fa4ed182 821 #define DWT_CTRL_FOLDEVTENA_Msk (0x1UL << DWT_CTRL_FOLDEVTENA_Pos) /*!< DWT CTRL: FOLDEVTENA Mask */
richardv 0:b079fa4ed182 822
richardv 0:b079fa4ed182 823 #define DWT_CTRL_LSUEVTENA_Pos 20 /*!< DWT CTRL: LSUEVTENA Position */
richardv 0:b079fa4ed182 824 #define DWT_CTRL_LSUEVTENA_Msk (0x1UL << DWT_CTRL_LSUEVTENA_Pos) /*!< DWT CTRL: LSUEVTENA Mask */
richardv 0:b079fa4ed182 825
richardv 0:b079fa4ed182 826 #define DWT_CTRL_SLEEPEVTENA_Pos 19 /*!< DWT CTRL: SLEEPEVTENA Position */
richardv 0:b079fa4ed182 827 #define DWT_CTRL_SLEEPEVTENA_Msk (0x1UL << DWT_CTRL_SLEEPEVTENA_Pos) /*!< DWT CTRL: SLEEPEVTENA Mask */
richardv 0:b079fa4ed182 828
richardv 0:b079fa4ed182 829 #define DWT_CTRL_EXCEVTENA_Pos 18 /*!< DWT CTRL: EXCEVTENA Position */
richardv 0:b079fa4ed182 830 #define DWT_CTRL_EXCEVTENA_Msk (0x1UL << DWT_CTRL_EXCEVTENA_Pos) /*!< DWT CTRL: EXCEVTENA Mask */
richardv 0:b079fa4ed182 831
richardv 0:b079fa4ed182 832 #define DWT_CTRL_CPIEVTENA_Pos 17 /*!< DWT CTRL: CPIEVTENA Position */
richardv 0:b079fa4ed182 833 #define DWT_CTRL_CPIEVTENA_Msk (0x1UL << DWT_CTRL_CPIEVTENA_Pos) /*!< DWT CTRL: CPIEVTENA Mask */
richardv 0:b079fa4ed182 834
richardv 0:b079fa4ed182 835 #define DWT_CTRL_EXCTRCENA_Pos 16 /*!< DWT CTRL: EXCTRCENA Position */
richardv 0:b079fa4ed182 836 #define DWT_CTRL_EXCTRCENA_Msk (0x1UL << DWT_CTRL_EXCTRCENA_Pos) /*!< DWT CTRL: EXCTRCENA Mask */
richardv 0:b079fa4ed182 837
richardv 0:b079fa4ed182 838 #define DWT_CTRL_PCSAMPLENA_Pos 12 /*!< DWT CTRL: PCSAMPLENA Position */
richardv 0:b079fa4ed182 839 #define DWT_CTRL_PCSAMPLENA_Msk (0x1UL << DWT_CTRL_PCSAMPLENA_Pos) /*!< DWT CTRL: PCSAMPLENA Mask */
richardv 0:b079fa4ed182 840
richardv 0:b079fa4ed182 841 #define DWT_CTRL_SYNCTAP_Pos 10 /*!< DWT CTRL: SYNCTAP Position */
richardv 0:b079fa4ed182 842 #define DWT_CTRL_SYNCTAP_Msk (0x3UL << DWT_CTRL_SYNCTAP_Pos) /*!< DWT CTRL: SYNCTAP Mask */
richardv 0:b079fa4ed182 843
richardv 0:b079fa4ed182 844 #define DWT_CTRL_CYCTAP_Pos 9 /*!< DWT CTRL: CYCTAP Position */
richardv 0:b079fa4ed182 845 #define DWT_CTRL_CYCTAP_Msk (0x1UL << DWT_CTRL_CYCTAP_Pos) /*!< DWT CTRL: CYCTAP Mask */
richardv 0:b079fa4ed182 846
richardv 0:b079fa4ed182 847 #define DWT_CTRL_POSTINIT_Pos 5 /*!< DWT CTRL: POSTINIT Position */
richardv 0:b079fa4ed182 848 #define DWT_CTRL_POSTINIT_Msk (0xFUL << DWT_CTRL_POSTINIT_Pos) /*!< DWT CTRL: POSTINIT Mask */
richardv 0:b079fa4ed182 849
richardv 0:b079fa4ed182 850 #define DWT_CTRL_POSTPRESET_Pos 1 /*!< DWT CTRL: POSTPRESET Position */
richardv 0:b079fa4ed182 851 #define DWT_CTRL_POSTPRESET_Msk (0xFUL << DWT_CTRL_POSTPRESET_Pos) /*!< DWT CTRL: POSTPRESET Mask */
richardv 0:b079fa4ed182 852
richardv 0:b079fa4ed182 853 #define DWT_CTRL_CYCCNTENA_Pos 0 /*!< DWT CTRL: CYCCNTENA Position */
richardv 0:b079fa4ed182 854 #define DWT_CTRL_CYCCNTENA_Msk (0x1UL << DWT_CTRL_CYCCNTENA_Pos) /*!< DWT CTRL: CYCCNTENA Mask */
richardv 0:b079fa4ed182 855
richardv 0:b079fa4ed182 856 /* DWT CPI Count Register Definitions */
richardv 0:b079fa4ed182 857 #define DWT_CPICNT_CPICNT_Pos 0 /*!< DWT CPICNT: CPICNT Position */
richardv 0:b079fa4ed182 858 #define DWT_CPICNT_CPICNT_Msk (0xFFUL << DWT_CPICNT_CPICNT_Pos) /*!< DWT CPICNT: CPICNT Mask */
richardv 0:b079fa4ed182 859
richardv 0:b079fa4ed182 860 /* DWT Exception Overhead Count Register Definitions */
richardv 0:b079fa4ed182 861 #define DWT_EXCCNT_EXCCNT_Pos 0 /*!< DWT EXCCNT: EXCCNT Position */
richardv 0:b079fa4ed182 862 #define DWT_EXCCNT_EXCCNT_Msk (0xFFUL << DWT_EXCCNT_EXCCNT_Pos) /*!< DWT EXCCNT: EXCCNT Mask */
richardv 0:b079fa4ed182 863
richardv 0:b079fa4ed182 864 /* DWT Sleep Count Register Definitions */
richardv 0:b079fa4ed182 865 #define DWT_SLEEPCNT_SLEEPCNT_Pos 0 /*!< DWT SLEEPCNT: SLEEPCNT Position */
richardv 0:b079fa4ed182 866 #define DWT_SLEEPCNT_SLEEPCNT_Msk (0xFFUL << DWT_SLEEPCNT_SLEEPCNT_Pos) /*!< DWT SLEEPCNT: SLEEPCNT Mask */
richardv 0:b079fa4ed182 867
richardv 0:b079fa4ed182 868 /* DWT LSU Count Register Definitions */
richardv 0:b079fa4ed182 869 #define DWT_LSUCNT_LSUCNT_Pos 0 /*!< DWT LSUCNT: LSUCNT Position */
richardv 0:b079fa4ed182 870 #define DWT_LSUCNT_LSUCNT_Msk (0xFFUL << DWT_LSUCNT_LSUCNT_Pos) /*!< DWT LSUCNT: LSUCNT Mask */
richardv 0:b079fa4ed182 871
richardv 0:b079fa4ed182 872 /* DWT Folded-instruction Count Register Definitions */
richardv 0:b079fa4ed182 873 #define DWT_FOLDCNT_FOLDCNT_Pos 0 /*!< DWT FOLDCNT: FOLDCNT Position */
richardv 0:b079fa4ed182 874 #define DWT_FOLDCNT_FOLDCNT_Msk (0xFFUL << DWT_FOLDCNT_FOLDCNT_Pos) /*!< DWT FOLDCNT: FOLDCNT Mask */
richardv 0:b079fa4ed182 875
richardv 0:b079fa4ed182 876 /* DWT Comparator Mask Register Definitions */
richardv 0:b079fa4ed182 877 #define DWT_MASK_MASK_Pos 0 /*!< DWT MASK: MASK Position */
richardv 0:b079fa4ed182 878 #define DWT_MASK_MASK_Msk (0x1FUL << DWT_MASK_MASK_Pos) /*!< DWT MASK: MASK Mask */
richardv 0:b079fa4ed182 879
richardv 0:b079fa4ed182 880 /* DWT Comparator Function Register Definitions */
richardv 0:b079fa4ed182 881 #define DWT_FUNCTION_MATCHED_Pos 24 /*!< DWT FUNCTION: MATCHED Position */
richardv 0:b079fa4ed182 882 #define DWT_FUNCTION_MATCHED_Msk (0x1UL << DWT_FUNCTION_MATCHED_Pos) /*!< DWT FUNCTION: MATCHED Mask */
richardv 0:b079fa4ed182 883
richardv 0:b079fa4ed182 884 #define DWT_FUNCTION_DATAVADDR1_Pos 16 /*!< DWT FUNCTION: DATAVADDR1 Position */
richardv 0:b079fa4ed182 885 #define DWT_FUNCTION_DATAVADDR1_Msk (0xFUL << DWT_FUNCTION_DATAVADDR1_Pos) /*!< DWT FUNCTION: DATAVADDR1 Mask */
richardv 0:b079fa4ed182 886
richardv 0:b079fa4ed182 887 #define DWT_FUNCTION_DATAVADDR0_Pos 12 /*!< DWT FUNCTION: DATAVADDR0 Position */
richardv 0:b079fa4ed182 888 #define DWT_FUNCTION_DATAVADDR0_Msk (0xFUL << DWT_FUNCTION_DATAVADDR0_Pos) /*!< DWT FUNCTION: DATAVADDR0 Mask */
richardv 0:b079fa4ed182 889
richardv 0:b079fa4ed182 890 #define DWT_FUNCTION_DATAVSIZE_Pos 10 /*!< DWT FUNCTION: DATAVSIZE Position */
richardv 0:b079fa4ed182 891 #define DWT_FUNCTION_DATAVSIZE_Msk (0x3UL << DWT_FUNCTION_DATAVSIZE_Pos) /*!< DWT FUNCTION: DATAVSIZE Mask */
richardv 0:b079fa4ed182 892
richardv 0:b079fa4ed182 893 #define DWT_FUNCTION_LNK1ENA_Pos 9 /*!< DWT FUNCTION: LNK1ENA Position */
richardv 0:b079fa4ed182 894 #define DWT_FUNCTION_LNK1ENA_Msk (0x1UL << DWT_FUNCTION_LNK1ENA_Pos) /*!< DWT FUNCTION: LNK1ENA Mask */
richardv 0:b079fa4ed182 895
richardv 0:b079fa4ed182 896 #define DWT_FUNCTION_DATAVMATCH_Pos 8 /*!< DWT FUNCTION: DATAVMATCH Position */
richardv 0:b079fa4ed182 897 #define DWT_FUNCTION_DATAVMATCH_Msk (0x1UL << DWT_FUNCTION_DATAVMATCH_Pos) /*!< DWT FUNCTION: DATAVMATCH Mask */
richardv 0:b079fa4ed182 898
richardv 0:b079fa4ed182 899 #define DWT_FUNCTION_CYCMATCH_Pos 7 /*!< DWT FUNCTION: CYCMATCH Position */
richardv 0:b079fa4ed182 900 #define DWT_FUNCTION_CYCMATCH_Msk (0x1UL << DWT_FUNCTION_CYCMATCH_Pos) /*!< DWT FUNCTION: CYCMATCH Mask */
richardv 0:b079fa4ed182 901
richardv 0:b079fa4ed182 902 #define DWT_FUNCTION_EMITRANGE_Pos 5 /*!< DWT FUNCTION: EMITRANGE Position */
richardv 0:b079fa4ed182 903 #define DWT_FUNCTION_EMITRANGE_Msk (0x1UL << DWT_FUNCTION_EMITRANGE_Pos) /*!< DWT FUNCTION: EMITRANGE Mask */
richardv 0:b079fa4ed182 904
richardv 0:b079fa4ed182 905 #define DWT_FUNCTION_FUNCTION_Pos 0 /*!< DWT FUNCTION: FUNCTION Position */
richardv 0:b079fa4ed182 906 #define DWT_FUNCTION_FUNCTION_Msk (0xFUL << DWT_FUNCTION_FUNCTION_Pos) /*!< DWT FUNCTION: FUNCTION Mask */
richardv 0:b079fa4ed182 907
richardv 0:b079fa4ed182 908 /*@}*/ /* end of group CMSIS_DWT */
richardv 0:b079fa4ed182 909
richardv 0:b079fa4ed182 910
richardv 0:b079fa4ed182 911 /** \ingroup CMSIS_core_register
richardv 0:b079fa4ed182 912 \defgroup CMSIS_TPI Trace Port Interface (TPI)
richardv 0:b079fa4ed182 913 \brief Type definitions for the Trace Port Interface (TPI)
richardv 0:b079fa4ed182 914 @{
richardv 0:b079fa4ed182 915 */
richardv 0:b079fa4ed182 916
richardv 0:b079fa4ed182 917 /** \brief Structure type to access the Trace Port Interface Register (TPI).
richardv 0:b079fa4ed182 918 */
richardv 0:b079fa4ed182 919 typedef struct
richardv 0:b079fa4ed182 920 {
richardv 0:b079fa4ed182 921 __IO uint32_t SSPSR; /*!< Offset: 0x000 (R/ ) Supported Parallel Port Size Register */
richardv 0:b079fa4ed182 922 __IO uint32_t CSPSR; /*!< Offset: 0x004 (R/W) Current Parallel Port Size Register */
richardv 0:b079fa4ed182 923 uint32_t RESERVED0[2];
richardv 0:b079fa4ed182 924 __IO uint32_t ACPR; /*!< Offset: 0x010 (R/W) Asynchronous Clock Prescaler Register */
richardv 0:b079fa4ed182 925 uint32_t RESERVED1[55];
richardv 0:b079fa4ed182 926 __IO uint32_t SPPR; /*!< Offset: 0x0F0 (R/W) Selected Pin Protocol Register */
richardv 0:b079fa4ed182 927 uint32_t RESERVED2[131];
richardv 0:b079fa4ed182 928 __I uint32_t FFSR; /*!< Offset: 0x300 (R/ ) Formatter and Flush Status Register */
richardv 0:b079fa4ed182 929 __IO uint32_t FFCR; /*!< Offset: 0x304 (R/W) Formatter and Flush Control Register */
richardv 0:b079fa4ed182 930 __I uint32_t FSCR; /*!< Offset: 0x308 (R/ ) Formatter Synchronization Counter Register */
richardv 0:b079fa4ed182 931 uint32_t RESERVED3[759];
richardv 0:b079fa4ed182 932 __I uint32_t TRIGGER; /*!< Offset: 0xEE8 (R/ ) TRIGGER */
richardv 0:b079fa4ed182 933 __I uint32_t FIFO0; /*!< Offset: 0xEEC (R/ ) Integration ETM Data */
richardv 0:b079fa4ed182 934 __I uint32_t ITATBCTR2; /*!< Offset: 0xEF0 (R/ ) ITATBCTR2 */
richardv 0:b079fa4ed182 935 uint32_t RESERVED4[1];
richardv 0:b079fa4ed182 936 __I uint32_t ITATBCTR0; /*!< Offset: 0xEF8 (R/ ) ITATBCTR0 */
richardv 0:b079fa4ed182 937 __I uint32_t FIFO1; /*!< Offset: 0xEFC (R/ ) Integration ITM Data */
richardv 0:b079fa4ed182 938 __IO uint32_t ITCTRL; /*!< Offset: 0xF00 (R/W) Integration Mode Control */
richardv 0:b079fa4ed182 939 uint32_t RESERVED5[39];
richardv 0:b079fa4ed182 940 __IO uint32_t CLAIMSET; /*!< Offset: 0xFA0 (R/W) Claim tag set */
richardv 0:b079fa4ed182 941 __IO uint32_t CLAIMCLR; /*!< Offset: 0xFA4 (R/W) Claim tag clear */
richardv 0:b079fa4ed182 942 uint32_t RESERVED7[8];
richardv 0:b079fa4ed182 943 __I uint32_t DEVID; /*!< Offset: 0xFC8 (R/ ) TPIU_DEVID */
richardv 0:b079fa4ed182 944 __I uint32_t DEVTYPE; /*!< Offset: 0xFCC (R/ ) TPIU_DEVTYPE */
richardv 0:b079fa4ed182 945 } TPI_Type;
richardv 0:b079fa4ed182 946
richardv 0:b079fa4ed182 947 /* TPI Asynchronous Clock Prescaler Register Definitions */
richardv 0:b079fa4ed182 948 #define TPI_ACPR_PRESCALER_Pos 0 /*!< TPI ACPR: PRESCALER Position */
richardv 0:b079fa4ed182 949 #define TPI_ACPR_PRESCALER_Msk (0x1FFFUL << TPI_ACPR_PRESCALER_Pos) /*!< TPI ACPR: PRESCALER Mask */
richardv 0:b079fa4ed182 950
richardv 0:b079fa4ed182 951 /* TPI Selected Pin Protocol Register Definitions */
richardv 0:b079fa4ed182 952 #define TPI_SPPR_TXMODE_Pos 0 /*!< TPI SPPR: TXMODE Position */
richardv 0:b079fa4ed182 953 #define TPI_SPPR_TXMODE_Msk (0x3UL << TPI_SPPR_TXMODE_Pos) /*!< TPI SPPR: TXMODE Mask */
richardv 0:b079fa4ed182 954
richardv 0:b079fa4ed182 955 /* TPI Formatter and Flush Status Register Definitions */
richardv 0:b079fa4ed182 956 #define TPI_FFSR_FtNonStop_Pos 3 /*!< TPI FFSR: FtNonStop Position */
richardv 0:b079fa4ed182 957 #define TPI_FFSR_FtNonStop_Msk (0x1UL << TPI_FFSR_FtNonStop_Pos) /*!< TPI FFSR: FtNonStop Mask */
richardv 0:b079fa4ed182 958
richardv 0:b079fa4ed182 959 #define TPI_FFSR_TCPresent_Pos 2 /*!< TPI FFSR: TCPresent Position */
richardv 0:b079fa4ed182 960 #define TPI_FFSR_TCPresent_Msk (0x1UL << TPI_FFSR_TCPresent_Pos) /*!< TPI FFSR: TCPresent Mask */
richardv 0:b079fa4ed182 961
richardv 0:b079fa4ed182 962 #define TPI_FFSR_FtStopped_Pos 1 /*!< TPI FFSR: FtStopped Position */
richardv 0:b079fa4ed182 963 #define TPI_FFSR_FtStopped_Msk (0x1UL << TPI_FFSR_FtStopped_Pos) /*!< TPI FFSR: FtStopped Mask */
richardv 0:b079fa4ed182 964
richardv 0:b079fa4ed182 965 #define TPI_FFSR_FlInProg_Pos 0 /*!< TPI FFSR: FlInProg Position */
richardv 0:b079fa4ed182 966 #define TPI_FFSR_FlInProg_Msk (0x1UL << TPI_FFSR_FlInProg_Pos) /*!< TPI FFSR: FlInProg Mask */
richardv 0:b079fa4ed182 967
richardv 0:b079fa4ed182 968 /* TPI Formatter and Flush Control Register Definitions */
richardv 0:b079fa4ed182 969 #define TPI_FFCR_TrigIn_Pos 8 /*!< TPI FFCR: TrigIn Position */
richardv 0:b079fa4ed182 970 #define TPI_FFCR_TrigIn_Msk (0x1UL << TPI_FFCR_TrigIn_Pos) /*!< TPI FFCR: TrigIn Mask */
richardv 0:b079fa4ed182 971
richardv 0:b079fa4ed182 972 #define TPI_FFCR_EnFCont_Pos 1 /*!< TPI FFCR: EnFCont Position */
richardv 0:b079fa4ed182 973 #define TPI_FFCR_EnFCont_Msk (0x1UL << TPI_FFCR_EnFCont_Pos) /*!< TPI FFCR: EnFCont Mask */
richardv 0:b079fa4ed182 974
richardv 0:b079fa4ed182 975 /* TPI TRIGGER Register Definitions */
richardv 0:b079fa4ed182 976 #define TPI_TRIGGER_TRIGGER_Pos 0 /*!< TPI TRIGGER: TRIGGER Position */
richardv 0:b079fa4ed182 977 #define TPI_TRIGGER_TRIGGER_Msk (0x1UL << TPI_TRIGGER_TRIGGER_Pos) /*!< TPI TRIGGER: TRIGGER Mask */
richardv 0:b079fa4ed182 978
richardv 0:b079fa4ed182 979 /* TPI Integration ETM Data Register Definitions (FIFO0) */
richardv 0:b079fa4ed182 980 #define TPI_FIFO0_ITM_ATVALID_Pos 29 /*!< TPI FIFO0: ITM_ATVALID Position */
richardv 0:b079fa4ed182 981 #define TPI_FIFO0_ITM_ATVALID_Msk (0x3UL << TPI_FIFO0_ITM_ATVALID_Pos) /*!< TPI FIFO0: ITM_ATVALID Mask */
richardv 0:b079fa4ed182 982
richardv 0:b079fa4ed182 983 #define TPI_FIFO0_ITM_bytecount_Pos 27 /*!< TPI FIFO0: ITM_bytecount Position */
richardv 0:b079fa4ed182 984 #define TPI_FIFO0_ITM_bytecount_Msk (0x3UL << TPI_FIFO0_ITM_bytecount_Pos) /*!< TPI FIFO0: ITM_bytecount Mask */
richardv 0:b079fa4ed182 985
richardv 0:b079fa4ed182 986 #define TPI_FIFO0_ETM_ATVALID_Pos 26 /*!< TPI FIFO0: ETM_ATVALID Position */
richardv 0:b079fa4ed182 987 #define TPI_FIFO0_ETM_ATVALID_Msk (0x3UL << TPI_FIFO0_ETM_ATVALID_Pos) /*!< TPI FIFO0: ETM_ATVALID Mask */
richardv 0:b079fa4ed182 988
richardv 0:b079fa4ed182 989 #define TPI_FIFO0_ETM_bytecount_Pos 24 /*!< TPI FIFO0: ETM_bytecount Position */
richardv 0:b079fa4ed182 990 #define TPI_FIFO0_ETM_bytecount_Msk (0x3UL << TPI_FIFO0_ETM_bytecount_Pos) /*!< TPI FIFO0: ETM_bytecount Mask */
richardv 0:b079fa4ed182 991
richardv 0:b079fa4ed182 992 #define TPI_FIFO0_ETM2_Pos 16 /*!< TPI FIFO0: ETM2 Position */
richardv 0:b079fa4ed182 993 #define TPI_FIFO0_ETM2_Msk (0xFFUL << TPI_FIFO0_ETM2_Pos) /*!< TPI FIFO0: ETM2 Mask */
richardv 0:b079fa4ed182 994
richardv 0:b079fa4ed182 995 #define TPI_FIFO0_ETM1_Pos 8 /*!< TPI FIFO0: ETM1 Position */
richardv 0:b079fa4ed182 996 #define TPI_FIFO0_ETM1_Msk (0xFFUL << TPI_FIFO0_ETM1_Pos) /*!< TPI FIFO0: ETM1 Mask */
richardv 0:b079fa4ed182 997
richardv 0:b079fa4ed182 998 #define TPI_FIFO0_ETM0_Pos 0 /*!< TPI FIFO0: ETM0 Position */
richardv 0:b079fa4ed182 999 #define TPI_FIFO0_ETM0_Msk (0xFFUL << TPI_FIFO0_ETM0_Pos) /*!< TPI FIFO0: ETM0 Mask */
richardv 0:b079fa4ed182 1000
richardv 0:b079fa4ed182 1001 /* TPI ITATBCTR2 Register Definitions */
richardv 0:b079fa4ed182 1002 #define TPI_ITATBCTR2_ATREADY_Pos 0 /*!< TPI ITATBCTR2: ATREADY Position */
richardv 0:b079fa4ed182 1003 #define TPI_ITATBCTR2_ATREADY_Msk (0x1UL << TPI_ITATBCTR2_ATREADY_Pos) /*!< TPI ITATBCTR2: ATREADY Mask */
richardv 0:b079fa4ed182 1004
richardv 0:b079fa4ed182 1005 /* TPI Integration ITM Data Register Definitions (FIFO1) */
richardv 0:b079fa4ed182 1006 #define TPI_FIFO1_ITM_ATVALID_Pos 29 /*!< TPI FIFO1: ITM_ATVALID Position */
richardv 0:b079fa4ed182 1007 #define TPI_FIFO1_ITM_ATVALID_Msk (0x3UL << TPI_FIFO1_ITM_ATVALID_Pos) /*!< TPI FIFO1: ITM_ATVALID Mask */
richardv 0:b079fa4ed182 1008
richardv 0:b079fa4ed182 1009 #define TPI_FIFO1_ITM_bytecount_Pos 27 /*!< TPI FIFO1: ITM_bytecount Position */
richardv 0:b079fa4ed182 1010 #define TPI_FIFO1_ITM_bytecount_Msk (0x3UL << TPI_FIFO1_ITM_bytecount_Pos) /*!< TPI FIFO1: ITM_bytecount Mask */
richardv 0:b079fa4ed182 1011
richardv 0:b079fa4ed182 1012 #define TPI_FIFO1_ETM_ATVALID_Pos 26 /*!< TPI FIFO1: ETM_ATVALID Position */
richardv 0:b079fa4ed182 1013 #define TPI_FIFO1_ETM_ATVALID_Msk (0x3UL << TPI_FIFO1_ETM_ATVALID_Pos) /*!< TPI FIFO1: ETM_ATVALID Mask */
richardv 0:b079fa4ed182 1014
richardv 0:b079fa4ed182 1015 #define TPI_FIFO1_ETM_bytecount_Pos 24 /*!< TPI FIFO1: ETM_bytecount Position */
richardv 0:b079fa4ed182 1016 #define TPI_FIFO1_ETM_bytecount_Msk (0x3UL << TPI_FIFO1_ETM_bytecount_Pos) /*!< TPI FIFO1: ETM_bytecount Mask */
richardv 0:b079fa4ed182 1017
richardv 0:b079fa4ed182 1018 #define TPI_FIFO1_ITM2_Pos 16 /*!< TPI FIFO1: ITM2 Position */
richardv 0:b079fa4ed182 1019 #define TPI_FIFO1_ITM2_Msk (0xFFUL << TPI_FIFO1_ITM2_Pos) /*!< TPI FIFO1: ITM2 Mask */
richardv 0:b079fa4ed182 1020
richardv 0:b079fa4ed182 1021 #define TPI_FIFO1_ITM1_Pos 8 /*!< TPI FIFO1: ITM1 Position */
richardv 0:b079fa4ed182 1022 #define TPI_FIFO1_ITM1_Msk (0xFFUL << TPI_FIFO1_ITM1_Pos) /*!< TPI FIFO1: ITM1 Mask */
richardv 0:b079fa4ed182 1023
richardv 0:b079fa4ed182 1024 #define TPI_FIFO1_ITM0_Pos 0 /*!< TPI FIFO1: ITM0 Position */
richardv 0:b079fa4ed182 1025 #define TPI_FIFO1_ITM0_Msk (0xFFUL << TPI_FIFO1_ITM0_Pos) /*!< TPI FIFO1: ITM0 Mask */
richardv 0:b079fa4ed182 1026
richardv 0:b079fa4ed182 1027 /* TPI ITATBCTR0 Register Definitions */
richardv 0:b079fa4ed182 1028 #define TPI_ITATBCTR0_ATREADY_Pos 0 /*!< TPI ITATBCTR0: ATREADY Position */
richardv 0:b079fa4ed182 1029 #define TPI_ITATBCTR0_ATREADY_Msk (0x1UL << TPI_ITATBCTR0_ATREADY_Pos) /*!< TPI ITATBCTR0: ATREADY Mask */
richardv 0:b079fa4ed182 1030
richardv 0:b079fa4ed182 1031 /* TPI Integration Mode Control Register Definitions */
richardv 0:b079fa4ed182 1032 #define TPI_ITCTRL_Mode_Pos 0 /*!< TPI ITCTRL: Mode Position */
richardv 0:b079fa4ed182 1033 #define TPI_ITCTRL_Mode_Msk (0x1UL << TPI_ITCTRL_Mode_Pos) /*!< TPI ITCTRL: Mode Mask */
richardv 0:b079fa4ed182 1034
richardv 0:b079fa4ed182 1035 /* TPI DEVID Register Definitions */
richardv 0:b079fa4ed182 1036 #define TPI_DEVID_NRZVALID_Pos 11 /*!< TPI DEVID: NRZVALID Position */
richardv 0:b079fa4ed182 1037 #define TPI_DEVID_NRZVALID_Msk (0x1UL << TPI_DEVID_NRZVALID_Pos) /*!< TPI DEVID: NRZVALID Mask */
richardv 0:b079fa4ed182 1038
richardv 0:b079fa4ed182 1039 #define TPI_DEVID_MANCVALID_Pos 10 /*!< TPI DEVID: MANCVALID Position */
richardv 0:b079fa4ed182 1040 #define TPI_DEVID_MANCVALID_Msk (0x1UL << TPI_DEVID_MANCVALID_Pos) /*!< TPI DEVID: MANCVALID Mask */
richardv 0:b079fa4ed182 1041
richardv 0:b079fa4ed182 1042 #define TPI_DEVID_PTINVALID_Pos 9 /*!< TPI DEVID: PTINVALID Position */
richardv 0:b079fa4ed182 1043 #define TPI_DEVID_PTINVALID_Msk (0x1UL << TPI_DEVID_PTINVALID_Pos) /*!< TPI DEVID: PTINVALID Mask */
richardv 0:b079fa4ed182 1044
richardv 0:b079fa4ed182 1045 #define TPI_DEVID_MinBufSz_Pos 6 /*!< TPI DEVID: MinBufSz Position */
richardv 0:b079fa4ed182 1046 #define TPI_DEVID_MinBufSz_Msk (0x7UL << TPI_DEVID_MinBufSz_Pos) /*!< TPI DEVID: MinBufSz Mask */
richardv 0:b079fa4ed182 1047
richardv 0:b079fa4ed182 1048 #define TPI_DEVID_AsynClkIn_Pos 5 /*!< TPI DEVID: AsynClkIn Position */
richardv 0:b079fa4ed182 1049 #define TPI_DEVID_AsynClkIn_Msk (0x1UL << TPI_DEVID_AsynClkIn_Pos) /*!< TPI DEVID: AsynClkIn Mask */
richardv 0:b079fa4ed182 1050
richardv 0:b079fa4ed182 1051 #define TPI_DEVID_NrTraceInput_Pos 0 /*!< TPI DEVID: NrTraceInput Position */
richardv 0:b079fa4ed182 1052 #define TPI_DEVID_NrTraceInput_Msk (0x1FUL << TPI_DEVID_NrTraceInput_Pos) /*!< TPI DEVID: NrTraceInput Mask */
richardv 0:b079fa4ed182 1053
richardv 0:b079fa4ed182 1054 /* TPI DEVTYPE Register Definitions */
richardv 0:b079fa4ed182 1055 #define TPI_DEVTYPE_SubType_Pos 0 /*!< TPI DEVTYPE: SubType Position */
richardv 0:b079fa4ed182 1056 #define TPI_DEVTYPE_SubType_Msk (0xFUL << TPI_DEVTYPE_SubType_Pos) /*!< TPI DEVTYPE: SubType Mask */
richardv 0:b079fa4ed182 1057
richardv 0:b079fa4ed182 1058 #define TPI_DEVTYPE_MajorType_Pos 4 /*!< TPI DEVTYPE: MajorType Position */
richardv 0:b079fa4ed182 1059 #define TPI_DEVTYPE_MajorType_Msk (0xFUL << TPI_DEVTYPE_MajorType_Pos) /*!< TPI DEVTYPE: MajorType Mask */
richardv 0:b079fa4ed182 1060
richardv 0:b079fa4ed182 1061 /*@}*/ /* end of group CMSIS_TPI */
richardv 0:b079fa4ed182 1062
richardv 0:b079fa4ed182 1063
richardv 0:b079fa4ed182 1064 #if (__MPU_PRESENT == 1)
richardv 0:b079fa4ed182 1065 /** \ingroup CMSIS_core_register
richardv 0:b079fa4ed182 1066 \defgroup CMSIS_MPU Memory Protection Unit (MPU)
richardv 0:b079fa4ed182 1067 \brief Type definitions for the Memory Protection Unit (MPU)
richardv 0:b079fa4ed182 1068 @{
richardv 0:b079fa4ed182 1069 */
richardv 0:b079fa4ed182 1070
richardv 0:b079fa4ed182 1071 /** \brief Structure type to access the Memory Protection Unit (MPU).
richardv 0:b079fa4ed182 1072 */
richardv 0:b079fa4ed182 1073 typedef struct
richardv 0:b079fa4ed182 1074 {
richardv 0:b079fa4ed182 1075 __I uint32_t TYPE; /*!< Offset: 0x000 (R/ ) MPU Type Register */
richardv 0:b079fa4ed182 1076 __IO uint32_t CTRL; /*!< Offset: 0x004 (R/W) MPU Control Register */
richardv 0:b079fa4ed182 1077 __IO uint32_t RNR; /*!< Offset: 0x008 (R/W) MPU Region RNRber Register */
richardv 0:b079fa4ed182 1078 __IO uint32_t RBAR; /*!< Offset: 0x00C (R/W) MPU Region Base Address Register */
richardv 0:b079fa4ed182 1079 __IO uint32_t RASR; /*!< Offset: 0x010 (R/W) MPU Region Attribute and Size Register */
richardv 0:b079fa4ed182 1080 __IO uint32_t RBAR_A1; /*!< Offset: 0x014 (R/W) MPU Alias 1 Region Base Address Register */
richardv 0:b079fa4ed182 1081 __IO uint32_t RASR_A1; /*!< Offset: 0x018 (R/W) MPU Alias 1 Region Attribute and Size Register */
richardv 0:b079fa4ed182 1082 __IO uint32_t RBAR_A2; /*!< Offset: 0x01C (R/W) MPU Alias 2 Region Base Address Register */
richardv 0:b079fa4ed182 1083 __IO uint32_t RASR_A2; /*!< Offset: 0x020 (R/W) MPU Alias 2 Region Attribute and Size Register */
richardv 0:b079fa4ed182 1084 __IO uint32_t RBAR_A3; /*!< Offset: 0x024 (R/W) MPU Alias 3 Region Base Address Register */
richardv 0:b079fa4ed182 1085 __IO uint32_t RASR_A3; /*!< Offset: 0x028 (R/W) MPU Alias 3 Region Attribute and Size Register */
richardv 0:b079fa4ed182 1086 } MPU_Type;
richardv 0:b079fa4ed182 1087
richardv 0:b079fa4ed182 1088 /* MPU Type Register */
richardv 0:b079fa4ed182 1089 #define MPU_TYPE_IREGION_Pos 16 /*!< MPU TYPE: IREGION Position */
richardv 0:b079fa4ed182 1090 #define MPU_TYPE_IREGION_Msk (0xFFUL << MPU_TYPE_IREGION_Pos) /*!< MPU TYPE: IREGION Mask */
richardv 0:b079fa4ed182 1091
richardv 0:b079fa4ed182 1092 #define MPU_TYPE_DREGION_Pos 8 /*!< MPU TYPE: DREGION Position */
richardv 0:b079fa4ed182 1093 #define MPU_TYPE_DREGION_Msk (0xFFUL << MPU_TYPE_DREGION_Pos) /*!< MPU TYPE: DREGION Mask */
richardv 0:b079fa4ed182 1094
richardv 0:b079fa4ed182 1095 #define MPU_TYPE_SEPARATE_Pos 0 /*!< MPU TYPE: SEPARATE Position */
richardv 0:b079fa4ed182 1096 #define MPU_TYPE_SEPARATE_Msk (1UL << MPU_TYPE_SEPARATE_Pos) /*!< MPU TYPE: SEPARATE Mask */
richardv 0:b079fa4ed182 1097
richardv 0:b079fa4ed182 1098 /* MPU Control Register */
richardv 0:b079fa4ed182 1099 #define MPU_CTRL_PRIVDEFENA_Pos 2 /*!< MPU CTRL: PRIVDEFENA Position */
richardv 0:b079fa4ed182 1100 #define MPU_CTRL_PRIVDEFENA_Msk (1UL << MPU_CTRL_PRIVDEFENA_Pos) /*!< MPU CTRL: PRIVDEFENA Mask */
richardv 0:b079fa4ed182 1101
richardv 0:b079fa4ed182 1102 #define MPU_CTRL_HFNMIENA_Pos 1 /*!< MPU CTRL: HFNMIENA Position */
richardv 0:b079fa4ed182 1103 #define MPU_CTRL_HFNMIENA_Msk (1UL << MPU_CTRL_HFNMIENA_Pos) /*!< MPU CTRL: HFNMIENA Mask */
richardv 0:b079fa4ed182 1104
richardv 0:b079fa4ed182 1105 #define MPU_CTRL_ENABLE_Pos 0 /*!< MPU CTRL: ENABLE Position */
richardv 0:b079fa4ed182 1106 #define MPU_CTRL_ENABLE_Msk (1UL << MPU_CTRL_ENABLE_Pos) /*!< MPU CTRL: ENABLE Mask */
richardv 0:b079fa4ed182 1107
richardv 0:b079fa4ed182 1108 /* MPU Region Number Register */
richardv 0:b079fa4ed182 1109 #define MPU_RNR_REGION_Pos 0 /*!< MPU RNR: REGION Position */
richardv 0:b079fa4ed182 1110 #define MPU_RNR_REGION_Msk (0xFFUL << MPU_RNR_REGION_Pos) /*!< MPU RNR: REGION Mask */
richardv 0:b079fa4ed182 1111
richardv 0:b079fa4ed182 1112 /* MPU Region Base Address Register */
richardv 0:b079fa4ed182 1113 #define MPU_RBAR_ADDR_Pos 5 /*!< MPU RBAR: ADDR Position */
richardv 0:b079fa4ed182 1114 #define MPU_RBAR_ADDR_Msk (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos) /*!< MPU RBAR: ADDR Mask */
richardv 0:b079fa4ed182 1115
richardv 0:b079fa4ed182 1116 #define MPU_RBAR_VALID_Pos 4 /*!< MPU RBAR: VALID Position */
richardv 0:b079fa4ed182 1117 #define MPU_RBAR_VALID_Msk (1UL << MPU_RBAR_VALID_Pos) /*!< MPU RBAR: VALID Mask */
richardv 0:b079fa4ed182 1118
richardv 0:b079fa4ed182 1119 #define MPU_RBAR_REGION_Pos 0 /*!< MPU RBAR: REGION Position */
richardv 0:b079fa4ed182 1120 #define MPU_RBAR_REGION_Msk (0xFUL << MPU_RBAR_REGION_Pos) /*!< MPU RBAR: REGION Mask */
richardv 0:b079fa4ed182 1121
richardv 0:b079fa4ed182 1122 /* MPU Region Attribute and Size Register */
richardv 0:b079fa4ed182 1123 #define MPU_RASR_ATTRS_Pos 16 /*!< MPU RASR: MPU Region Attribute field Position */
richardv 0:b079fa4ed182 1124 #define MPU_RASR_ATTRS_Msk (0xFFFFUL << MPU_RASR_ATTRS_Pos) /*!< MPU RASR: MPU Region Attribute field Mask */
richardv 0:b079fa4ed182 1125
richardv 0:b079fa4ed182 1126 #define MPU_RASR_XN_Pos 28 /*!< MPU RASR: ATTRS.XN Position */
richardv 0:b079fa4ed182 1127 #define MPU_RASR_XN_Msk (1UL << MPU_RASR_XN_Pos) /*!< MPU RASR: ATTRS.XN Mask */
richardv 0:b079fa4ed182 1128
richardv 0:b079fa4ed182 1129 #define MPU_RASR_AP_Pos 24 /*!< MPU RASR: ATTRS.AP Position */
richardv 0:b079fa4ed182 1130 #define MPU_RASR_AP_Msk (0x7UL << MPU_RASR_AP_Pos) /*!< MPU RASR: ATTRS.AP Mask */
richardv 0:b079fa4ed182 1131
richardv 0:b079fa4ed182 1132 #define MPU_RASR_TEX_Pos 19 /*!< MPU RASR: ATTRS.TEX Position */
richardv 0:b079fa4ed182 1133 #define MPU_RASR_TEX_Msk (0x7UL << MPU_RASR_TEX_Pos) /*!< MPU RASR: ATTRS.TEX Mask */
richardv 0:b079fa4ed182 1134
richardv 0:b079fa4ed182 1135 #define MPU_RASR_S_Pos 18 /*!< MPU RASR: ATTRS.S Position */
richardv 0:b079fa4ed182 1136 #define MPU_RASR_S_Msk (1UL << MPU_RASR_S_Pos) /*!< MPU RASR: ATTRS.S Mask */
richardv 0:b079fa4ed182 1137
richardv 0:b079fa4ed182 1138 #define MPU_RASR_C_Pos 17 /*!< MPU RASR: ATTRS.C Position */
richardv 0:b079fa4ed182 1139 #define MPU_RASR_C_Msk (1UL << MPU_RASR_C_Pos) /*!< MPU RASR: ATTRS.C Mask */
richardv 0:b079fa4ed182 1140
richardv 0:b079fa4ed182 1141 #define MPU_RASR_B_Pos 16 /*!< MPU RASR: ATTRS.B Position */
richardv 0:b079fa4ed182 1142 #define MPU_RASR_B_Msk (1UL << MPU_RASR_B_Pos) /*!< MPU RASR: ATTRS.B Mask */
richardv 0:b079fa4ed182 1143
richardv 0:b079fa4ed182 1144 #define MPU_RASR_SRD_Pos 8 /*!< MPU RASR: Sub-Region Disable Position */
richardv 0:b079fa4ed182 1145 #define MPU_RASR_SRD_Msk (0xFFUL << MPU_RASR_SRD_Pos) /*!< MPU RASR: Sub-Region Disable Mask */
richardv 0:b079fa4ed182 1146
richardv 0:b079fa4ed182 1147 #define MPU_RASR_SIZE_Pos 1 /*!< MPU RASR: Region Size Field Position */
richardv 0:b079fa4ed182 1148 #define MPU_RASR_SIZE_Msk (0x1FUL << MPU_RASR_SIZE_Pos) /*!< MPU RASR: Region Size Field Mask */
richardv 0:b079fa4ed182 1149
richardv 0:b079fa4ed182 1150 #define MPU_RASR_ENABLE_Pos 0 /*!< MPU RASR: Region enable bit Position */
richardv 0:b079fa4ed182 1151 #define MPU_RASR_ENABLE_Msk (1UL << MPU_RASR_ENABLE_Pos) /*!< MPU RASR: Region enable bit Disable Mask */
richardv 0:b079fa4ed182 1152
richardv 0:b079fa4ed182 1153 /*@} end of group CMSIS_MPU */
richardv 0:b079fa4ed182 1154 #endif
richardv 0:b079fa4ed182 1155
richardv 0:b079fa4ed182 1156
richardv 0:b079fa4ed182 1157 #if (__FPU_PRESENT == 1)
richardv 0:b079fa4ed182 1158 /** \ingroup CMSIS_core_register
richardv 0:b079fa4ed182 1159 \defgroup CMSIS_FPU Floating Point Unit (FPU)
richardv 0:b079fa4ed182 1160 \brief Type definitions for the Floating Point Unit (FPU)
richardv 0:b079fa4ed182 1161 @{
richardv 0:b079fa4ed182 1162 */
richardv 0:b079fa4ed182 1163
richardv 0:b079fa4ed182 1164 /** \brief Structure type to access the Floating Point Unit (FPU).
richardv 0:b079fa4ed182 1165 */
richardv 0:b079fa4ed182 1166 typedef struct
richardv 0:b079fa4ed182 1167 {
richardv 0:b079fa4ed182 1168 uint32_t RESERVED0[1];
richardv 0:b079fa4ed182 1169 __IO uint32_t FPCCR; /*!< Offset: 0x004 (R/W) Floating-Point Context Control Register */
richardv 0:b079fa4ed182 1170 __IO uint32_t FPCAR; /*!< Offset: 0x008 (R/W) Floating-Point Context Address Register */
richardv 0:b079fa4ed182 1171 __IO uint32_t FPDSCR; /*!< Offset: 0x00C (R/W) Floating-Point Default Status Control Register */
richardv 0:b079fa4ed182 1172 __I uint32_t MVFR0; /*!< Offset: 0x010 (R/ ) Media and FP Feature Register 0 */
richardv 0:b079fa4ed182 1173 __I uint32_t MVFR1; /*!< Offset: 0x014 (R/ ) Media and FP Feature Register 1 */
richardv 0:b079fa4ed182 1174 } FPU_Type;
richardv 0:b079fa4ed182 1175
richardv 0:b079fa4ed182 1176 /* Floating-Point Context Control Register */
richardv 0:b079fa4ed182 1177 #define FPU_FPCCR_ASPEN_Pos 31 /*!< FPCCR: ASPEN bit Position */
richardv 0:b079fa4ed182 1178 #define FPU_FPCCR_ASPEN_Msk (1UL << FPU_FPCCR_ASPEN_Pos) /*!< FPCCR: ASPEN bit Mask */
richardv 0:b079fa4ed182 1179
richardv 0:b079fa4ed182 1180 #define FPU_FPCCR_LSPEN_Pos 30 /*!< FPCCR: LSPEN Position */
richardv 0:b079fa4ed182 1181 #define FPU_FPCCR_LSPEN_Msk (1UL << FPU_FPCCR_LSPEN_Pos) /*!< FPCCR: LSPEN bit Mask */
richardv 0:b079fa4ed182 1182
richardv 0:b079fa4ed182 1183 #define FPU_FPCCR_MONRDY_Pos 8 /*!< FPCCR: MONRDY Position */
richardv 0:b079fa4ed182 1184 #define FPU_FPCCR_MONRDY_Msk (1UL << FPU_FPCCR_MONRDY_Pos) /*!< FPCCR: MONRDY bit Mask */
richardv 0:b079fa4ed182 1185
richardv 0:b079fa4ed182 1186 #define FPU_FPCCR_BFRDY_Pos 6 /*!< FPCCR: BFRDY Position */
richardv 0:b079fa4ed182 1187 #define FPU_FPCCR_BFRDY_Msk (1UL << FPU_FPCCR_BFRDY_Pos) /*!< FPCCR: BFRDY bit Mask */
richardv 0:b079fa4ed182 1188
richardv 0:b079fa4ed182 1189 #define FPU_FPCCR_MMRDY_Pos 5 /*!< FPCCR: MMRDY Position */
richardv 0:b079fa4ed182 1190 #define FPU_FPCCR_MMRDY_Msk (1UL << FPU_FPCCR_MMRDY_Pos) /*!< FPCCR: MMRDY bit Mask */
richardv 0:b079fa4ed182 1191
richardv 0:b079fa4ed182 1192 #define FPU_FPCCR_HFRDY_Pos 4 /*!< FPCCR: HFRDY Position */
richardv 0:b079fa4ed182 1193 #define FPU_FPCCR_HFRDY_Msk (1UL << FPU_FPCCR_HFRDY_Pos) /*!< FPCCR: HFRDY bit Mask */
richardv 0:b079fa4ed182 1194
richardv 0:b079fa4ed182 1195 #define FPU_FPCCR_THREAD_Pos 3 /*!< FPCCR: processor mode bit Position */
richardv 0:b079fa4ed182 1196 #define FPU_FPCCR_THREAD_Msk (1UL << FPU_FPCCR_THREAD_Pos) /*!< FPCCR: processor mode active bit Mask */
richardv 0:b079fa4ed182 1197
richardv 0:b079fa4ed182 1198 #define FPU_FPCCR_USER_Pos 1 /*!< FPCCR: privilege level bit Position */
richardv 0:b079fa4ed182 1199 #define FPU_FPCCR_USER_Msk (1UL << FPU_FPCCR_USER_Pos) /*!< FPCCR: privilege level bit Mask */
richardv 0:b079fa4ed182 1200
richardv 0:b079fa4ed182 1201 #define FPU_FPCCR_LSPACT_Pos 0 /*!< FPCCR: Lazy state preservation active bit Position */
richardv 0:b079fa4ed182 1202 #define FPU_FPCCR_LSPACT_Msk (1UL << FPU_FPCCR_LSPACT_Pos) /*!< FPCCR: Lazy state preservation active bit Mask */
richardv 0:b079fa4ed182 1203
richardv 0:b079fa4ed182 1204 /* Floating-Point Context Address Register */
richardv 0:b079fa4ed182 1205 #define FPU_FPCAR_ADDRESS_Pos 3 /*!< FPCAR: ADDRESS bit Position */
richardv 0:b079fa4ed182 1206 #define FPU_FPCAR_ADDRESS_Msk (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos) /*!< FPCAR: ADDRESS bit Mask */
richardv 0:b079fa4ed182 1207
richardv 0:b079fa4ed182 1208 /* Floating-Point Default Status Control Register */
richardv 0:b079fa4ed182 1209 #define FPU_FPDSCR_AHP_Pos 26 /*!< FPDSCR: AHP bit Position */
richardv 0:b079fa4ed182 1210 #define FPU_FPDSCR_AHP_Msk (1UL << FPU_FPDSCR_AHP_Pos) /*!< FPDSCR: AHP bit Mask */
richardv 0:b079fa4ed182 1211
richardv 0:b079fa4ed182 1212 #define FPU_FPDSCR_DN_Pos 25 /*!< FPDSCR: DN bit Position */
richardv 0:b079fa4ed182 1213 #define FPU_FPDSCR_DN_Msk (1UL << FPU_FPDSCR_DN_Pos) /*!< FPDSCR: DN bit Mask */
richardv 0:b079fa4ed182 1214
richardv 0:b079fa4ed182 1215 #define FPU_FPDSCR_FZ_Pos 24 /*!< FPDSCR: FZ bit Position */
richardv 0:b079fa4ed182 1216 #define FPU_FPDSCR_FZ_Msk (1UL << FPU_FPDSCR_FZ_Pos) /*!< FPDSCR: FZ bit Mask */
richardv 0:b079fa4ed182 1217
richardv 0:b079fa4ed182 1218 #define FPU_FPDSCR_RMode_Pos 22 /*!< FPDSCR: RMode bit Position */
richardv 0:b079fa4ed182 1219 #define FPU_FPDSCR_RMode_Msk (3UL << FPU_FPDSCR_RMode_Pos) /*!< FPDSCR: RMode bit Mask */
richardv 0:b079fa4ed182 1220
richardv 0:b079fa4ed182 1221 /* Media and FP Feature Register 0 */
richardv 0:b079fa4ed182 1222 #define FPU_MVFR0_FP_rounding_modes_Pos 28 /*!< MVFR0: FP rounding modes bits Position */
richardv 0:b079fa4ed182 1223 #define FPU_MVFR0_FP_rounding_modes_Msk (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos) /*!< MVFR0: FP rounding modes bits Mask */
richardv 0:b079fa4ed182 1224
richardv 0:b079fa4ed182 1225 #define FPU_MVFR0_Short_vectors_Pos 24 /*!< MVFR0: Short vectors bits Position */
richardv 0:b079fa4ed182 1226 #define FPU_MVFR0_Short_vectors_Msk (0xFUL << FPU_MVFR0_Short_vectors_Pos) /*!< MVFR0: Short vectors bits Mask */
richardv 0:b079fa4ed182 1227
richardv 0:b079fa4ed182 1228 #define FPU_MVFR0_Square_root_Pos 20 /*!< MVFR0: Square root bits Position */
richardv 0:b079fa4ed182 1229 #define FPU_MVFR0_Square_root_Msk (0xFUL << FPU_MVFR0_Square_root_Pos) /*!< MVFR0: Square root bits Mask */
richardv 0:b079fa4ed182 1230
richardv 0:b079fa4ed182 1231 #define FPU_MVFR0_Divide_Pos 16 /*!< MVFR0: Divide bits Position */
richardv 0:b079fa4ed182 1232 #define FPU_MVFR0_Divide_Msk (0xFUL << FPU_MVFR0_Divide_Pos) /*!< MVFR0: Divide bits Mask */
richardv 0:b079fa4ed182 1233
richardv 0:b079fa4ed182 1234 #define FPU_MVFR0_FP_excep_trapping_Pos 12 /*!< MVFR0: FP exception trapping bits Position */
richardv 0:b079fa4ed182 1235 #define FPU_MVFR0_FP_excep_trapping_Msk (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos) /*!< MVFR0: FP exception trapping bits Mask */
richardv 0:b079fa4ed182 1236
richardv 0:b079fa4ed182 1237 #define FPU_MVFR0_Double_precision_Pos 8 /*!< MVFR0: Double-precision bits Position */
richardv 0:b079fa4ed182 1238 #define FPU_MVFR0_Double_precision_Msk (0xFUL << FPU_MVFR0_Double_precision_Pos) /*!< MVFR0: Double-precision bits Mask */
richardv 0:b079fa4ed182 1239
richardv 0:b079fa4ed182 1240 #define FPU_MVFR0_Single_precision_Pos 4 /*!< MVFR0: Single-precision bits Position */
richardv 0:b079fa4ed182 1241 #define FPU_MVFR0_Single_precision_Msk (0xFUL << FPU_MVFR0_Single_precision_Pos) /*!< MVFR0: Single-precision bits Mask */
richardv 0:b079fa4ed182 1242
richardv 0:b079fa4ed182 1243 #define FPU_MVFR0_A_SIMD_registers_Pos 0 /*!< MVFR0: A_SIMD registers bits Position */
richardv 0:b079fa4ed182 1244 #define FPU_MVFR0_A_SIMD_registers_Msk (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos) /*!< MVFR0: A_SIMD registers bits Mask */
richardv 0:b079fa4ed182 1245
richardv 0:b079fa4ed182 1246 /* Media and FP Feature Register 1 */
richardv 0:b079fa4ed182 1247 #define FPU_MVFR1_FP_fused_MAC_Pos 28 /*!< MVFR1: FP fused MAC bits Position */
richardv 0:b079fa4ed182 1248 #define FPU_MVFR1_FP_fused_MAC_Msk (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos) /*!< MVFR1: FP fused MAC bits Mask */
richardv 0:b079fa4ed182 1249
richardv 0:b079fa4ed182 1250 #define FPU_MVFR1_FP_HPFP_Pos 24 /*!< MVFR1: FP HPFP bits Position */
richardv 0:b079fa4ed182 1251 #define FPU_MVFR1_FP_HPFP_Msk (0xFUL << FPU_MVFR1_FP_HPFP_Pos) /*!< MVFR1: FP HPFP bits Mask */
richardv 0:b079fa4ed182 1252
richardv 0:b079fa4ed182 1253 #define FPU_MVFR1_D_NaN_mode_Pos 4 /*!< MVFR1: D_NaN mode bits Position */
richardv 0:b079fa4ed182 1254 #define FPU_MVFR1_D_NaN_mode_Msk (0xFUL << FPU_MVFR1_D_NaN_mode_Pos) /*!< MVFR1: D_NaN mode bits Mask */
richardv 0:b079fa4ed182 1255
richardv 0:b079fa4ed182 1256 #define FPU_MVFR1_FtZ_mode_Pos 0 /*!< MVFR1: FtZ mode bits Position */
richardv 0:b079fa4ed182 1257 #define FPU_MVFR1_FtZ_mode_Msk (0xFUL << FPU_MVFR1_FtZ_mode_Pos) /*!< MVFR1: FtZ mode bits Mask */
richardv 0:b079fa4ed182 1258
richardv 0:b079fa4ed182 1259 /*@} end of group CMSIS_FPU */
richardv 0:b079fa4ed182 1260 #endif
richardv 0:b079fa4ed182 1261
richardv 0:b079fa4ed182 1262
richardv 0:b079fa4ed182 1263 /** \ingroup CMSIS_core_register
richardv 0:b079fa4ed182 1264 \defgroup CMSIS_CoreDebug Core Debug Registers (CoreDebug)
richardv 0:b079fa4ed182 1265 \brief Type definitions for the Core Debug Registers
richardv 0:b079fa4ed182 1266 @{
richardv 0:b079fa4ed182 1267 */
richardv 0:b079fa4ed182 1268
richardv 0:b079fa4ed182 1269 /** \brief Structure type to access the Core Debug Register (CoreDebug).
richardv 0:b079fa4ed182 1270 */
richardv 0:b079fa4ed182 1271 typedef struct
richardv 0:b079fa4ed182 1272 {
richardv 0:b079fa4ed182 1273 __IO uint32_t DHCSR; /*!< Offset: 0x000 (R/W) Debug Halting Control and Status Register */
richardv 0:b079fa4ed182 1274 __O uint32_t DCRSR; /*!< Offset: 0x004 ( /W) Debug Core Register Selector Register */
richardv 0:b079fa4ed182 1275 __IO uint32_t DCRDR; /*!< Offset: 0x008 (R/W) Debug Core Register Data Register */
richardv 0:b079fa4ed182 1276 __IO uint32_t DEMCR; /*!< Offset: 0x00C (R/W) Debug Exception and Monitor Control Register */
richardv 0:b079fa4ed182 1277 } CoreDebug_Type;
richardv 0:b079fa4ed182 1278
richardv 0:b079fa4ed182 1279 /* Debug Halting Control and Status Register */
richardv 0:b079fa4ed182 1280 #define CoreDebug_DHCSR_DBGKEY_Pos 16 /*!< CoreDebug DHCSR: DBGKEY Position */
richardv 0:b079fa4ed182 1281 #define CoreDebug_DHCSR_DBGKEY_Msk (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos) /*!< CoreDebug DHCSR: DBGKEY Mask */
richardv 0:b079fa4ed182 1282
richardv 0:b079fa4ed182 1283 #define CoreDebug_DHCSR_S_RESET_ST_Pos 25 /*!< CoreDebug DHCSR: S_RESET_ST Position */
richardv 0:b079fa4ed182 1284 #define CoreDebug_DHCSR_S_RESET_ST_Msk (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos) /*!< CoreDebug DHCSR: S_RESET_ST Mask */
richardv 0:b079fa4ed182 1285
richardv 0:b079fa4ed182 1286 #define CoreDebug_DHCSR_S_RETIRE_ST_Pos 24 /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
richardv 0:b079fa4ed182 1287 #define CoreDebug_DHCSR_S_RETIRE_ST_Msk (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos) /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
richardv 0:b079fa4ed182 1288
richardv 0:b079fa4ed182 1289 #define CoreDebug_DHCSR_S_LOCKUP_Pos 19 /*!< CoreDebug DHCSR: S_LOCKUP Position */
richardv 0:b079fa4ed182 1290 #define CoreDebug_DHCSR_S_LOCKUP_Msk (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos) /*!< CoreDebug DHCSR: S_LOCKUP Mask */
richardv 0:b079fa4ed182 1291
richardv 0:b079fa4ed182 1292 #define CoreDebug_DHCSR_S_SLEEP_Pos 18 /*!< CoreDebug DHCSR: S_SLEEP Position */
richardv 0:b079fa4ed182 1293 #define CoreDebug_DHCSR_S_SLEEP_Msk (1UL << CoreDebug_DHCSR_S_SLEEP_Pos) /*!< CoreDebug DHCSR: S_SLEEP Mask */
richardv 0:b079fa4ed182 1294
richardv 0:b079fa4ed182 1295 #define CoreDebug_DHCSR_S_HALT_Pos 17 /*!< CoreDebug DHCSR: S_HALT Position */
richardv 0:b079fa4ed182 1296 #define CoreDebug_DHCSR_S_HALT_Msk (1UL << CoreDebug_DHCSR_S_HALT_Pos) /*!< CoreDebug DHCSR: S_HALT Mask */
richardv 0:b079fa4ed182 1297
richardv 0:b079fa4ed182 1298 #define CoreDebug_DHCSR_S_REGRDY_Pos 16 /*!< CoreDebug DHCSR: S_REGRDY Position */
richardv 0:b079fa4ed182 1299 #define CoreDebug_DHCSR_S_REGRDY_Msk (1UL << CoreDebug_DHCSR_S_REGRDY_Pos) /*!< CoreDebug DHCSR: S_REGRDY Mask */
richardv 0:b079fa4ed182 1300
richardv 0:b079fa4ed182 1301 #define CoreDebug_DHCSR_C_SNAPSTALL_Pos 5 /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
richardv 0:b079fa4ed182 1302 #define CoreDebug_DHCSR_C_SNAPSTALL_Msk (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos) /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
richardv 0:b079fa4ed182 1303
richardv 0:b079fa4ed182 1304 #define CoreDebug_DHCSR_C_MASKINTS_Pos 3 /*!< CoreDebug DHCSR: C_MASKINTS Position */
richardv 0:b079fa4ed182 1305 #define CoreDebug_DHCSR_C_MASKINTS_Msk (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos) /*!< CoreDebug DHCSR: C_MASKINTS Mask */
richardv 0:b079fa4ed182 1306
richardv 0:b079fa4ed182 1307 #define CoreDebug_DHCSR_C_STEP_Pos 2 /*!< CoreDebug DHCSR: C_STEP Position */
richardv 0:b079fa4ed182 1308 #define CoreDebug_DHCSR_C_STEP_Msk (1UL << CoreDebug_DHCSR_C_STEP_Pos) /*!< CoreDebug DHCSR: C_STEP Mask */
richardv 0:b079fa4ed182 1309
richardv 0:b079fa4ed182 1310 #define CoreDebug_DHCSR_C_HALT_Pos 1 /*!< CoreDebug DHCSR: C_HALT Position */
richardv 0:b079fa4ed182 1311 #define CoreDebug_DHCSR_C_HALT_Msk (1UL << CoreDebug_DHCSR_C_HALT_Pos) /*!< CoreDebug DHCSR: C_HALT Mask */
richardv 0:b079fa4ed182 1312
richardv 0:b079fa4ed182 1313 #define CoreDebug_DHCSR_C_DEBUGEN_Pos 0 /*!< CoreDebug DHCSR: C_DEBUGEN Position */
richardv 0:b079fa4ed182 1314 #define CoreDebug_DHCSR_C_DEBUGEN_Msk (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos) /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
richardv 0:b079fa4ed182 1315
richardv 0:b079fa4ed182 1316 /* Debug Core Register Selector Register */
richardv 0:b079fa4ed182 1317 #define CoreDebug_DCRSR_REGWnR_Pos 16 /*!< CoreDebug DCRSR: REGWnR Position */
richardv 0:b079fa4ed182 1318 #define CoreDebug_DCRSR_REGWnR_Msk (1UL << CoreDebug_DCRSR_REGWnR_Pos) /*!< CoreDebug DCRSR: REGWnR Mask */
richardv 0:b079fa4ed182 1319
richardv 0:b079fa4ed182 1320 #define CoreDebug_DCRSR_REGSEL_Pos 0 /*!< CoreDebug DCRSR: REGSEL Position */
richardv 0:b079fa4ed182 1321 #define CoreDebug_DCRSR_REGSEL_Msk (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos) /*!< CoreDebug DCRSR: REGSEL Mask */
richardv 0:b079fa4ed182 1322
richardv 0:b079fa4ed182 1323 /* Debug Exception and Monitor Control Register */
richardv 0:b079fa4ed182 1324 #define CoreDebug_DEMCR_TRCENA_Pos 24 /*!< CoreDebug DEMCR: TRCENA Position */
richardv 0:b079fa4ed182 1325 #define CoreDebug_DEMCR_TRCENA_Msk (1UL << CoreDebug_DEMCR_TRCENA_Pos) /*!< CoreDebug DEMCR: TRCENA Mask */
richardv 0:b079fa4ed182 1326
richardv 0:b079fa4ed182 1327 #define CoreDebug_DEMCR_MON_REQ_Pos 19 /*!< CoreDebug DEMCR: MON_REQ Position */
richardv 0:b079fa4ed182 1328 #define CoreDebug_DEMCR_MON_REQ_Msk (1UL << CoreDebug_DEMCR_MON_REQ_Pos) /*!< CoreDebug DEMCR: MON_REQ Mask */
richardv 0:b079fa4ed182 1329
richardv 0:b079fa4ed182 1330 #define CoreDebug_DEMCR_MON_STEP_Pos 18 /*!< CoreDebug DEMCR: MON_STEP Position */
richardv 0:b079fa4ed182 1331 #define CoreDebug_DEMCR_MON_STEP_Msk (1UL << CoreDebug_DEMCR_MON_STEP_Pos) /*!< CoreDebug DEMCR: MON_STEP Mask */
richardv 0:b079fa4ed182 1332
richardv 0:b079fa4ed182 1333 #define CoreDebug_DEMCR_MON_PEND_Pos 17 /*!< CoreDebug DEMCR: MON_PEND Position */
richardv 0:b079fa4ed182 1334 #define CoreDebug_DEMCR_MON_PEND_Msk (1UL << CoreDebug_DEMCR_MON_PEND_Pos) /*!< CoreDebug DEMCR: MON_PEND Mask */
richardv 0:b079fa4ed182 1335
richardv 0:b079fa4ed182 1336 #define CoreDebug_DEMCR_MON_EN_Pos 16 /*!< CoreDebug DEMCR: MON_EN Position */
richardv 0:b079fa4ed182 1337 #define CoreDebug_DEMCR_MON_EN_Msk (1UL << CoreDebug_DEMCR_MON_EN_Pos) /*!< CoreDebug DEMCR: MON_EN Mask */
richardv 0:b079fa4ed182 1338
richardv 0:b079fa4ed182 1339 #define CoreDebug_DEMCR_VC_HARDERR_Pos 10 /*!< CoreDebug DEMCR: VC_HARDERR Position */
richardv 0:b079fa4ed182 1340 #define CoreDebug_DEMCR_VC_HARDERR_Msk (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos) /*!< CoreDebug DEMCR: VC_HARDERR Mask */
richardv 0:b079fa4ed182 1341
richardv 0:b079fa4ed182 1342 #define CoreDebug_DEMCR_VC_INTERR_Pos 9 /*!< CoreDebug DEMCR: VC_INTERR Position */
richardv 0:b079fa4ed182 1343 #define CoreDebug_DEMCR_VC_INTERR_Msk (1UL << CoreDebug_DEMCR_VC_INTERR_Pos) /*!< CoreDebug DEMCR: VC_INTERR Mask */
richardv 0:b079fa4ed182 1344
richardv 0:b079fa4ed182 1345 #define CoreDebug_DEMCR_VC_BUSERR_Pos 8 /*!< CoreDebug DEMCR: VC_BUSERR Position */
richardv 0:b079fa4ed182 1346 #define CoreDebug_DEMCR_VC_BUSERR_Msk (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos) /*!< CoreDebug DEMCR: VC_BUSERR Mask */
richardv 0:b079fa4ed182 1347
richardv 0:b079fa4ed182 1348 #define CoreDebug_DEMCR_VC_STATERR_Pos 7 /*!< CoreDebug DEMCR: VC_STATERR Position */
richardv 0:b079fa4ed182 1349 #define CoreDebug_DEMCR_VC_STATERR_Msk (1UL << CoreDebug_DEMCR_VC_STATERR_Pos) /*!< CoreDebug DEMCR: VC_STATERR Mask */
richardv 0:b079fa4ed182 1350
richardv 0:b079fa4ed182 1351 #define CoreDebug_DEMCR_VC_CHKERR_Pos 6 /*!< CoreDebug DEMCR: VC_CHKERR Position */
richardv 0:b079fa4ed182 1352 #define CoreDebug_DEMCR_VC_CHKERR_Msk (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos) /*!< CoreDebug DEMCR: VC_CHKERR Mask */
richardv 0:b079fa4ed182 1353
richardv 0:b079fa4ed182 1354 #define CoreDebug_DEMCR_VC_NOCPERR_Pos 5 /*!< CoreDebug DEMCR: VC_NOCPERR Position */
richardv 0:b079fa4ed182 1355 #define CoreDebug_DEMCR_VC_NOCPERR_Msk (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos) /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
richardv 0:b079fa4ed182 1356
richardv 0:b079fa4ed182 1357 #define CoreDebug_DEMCR_VC_MMERR_Pos 4 /*!< CoreDebug DEMCR: VC_MMERR Position */
richardv 0:b079fa4ed182 1358 #define CoreDebug_DEMCR_VC_MMERR_Msk (1UL << CoreDebug_DEMCR_VC_MMERR_Pos) /*!< CoreDebug DEMCR: VC_MMERR Mask */
richardv 0:b079fa4ed182 1359
richardv 0:b079fa4ed182 1360 #define CoreDebug_DEMCR_VC_CORERESET_Pos 0 /*!< CoreDebug DEMCR: VC_CORERESET Position */
richardv 0:b079fa4ed182 1361 #define CoreDebug_DEMCR_VC_CORERESET_Msk (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos) /*!< CoreDebug DEMCR: VC_CORERESET Mask */
richardv 0:b079fa4ed182 1362
richardv 0:b079fa4ed182 1363 /*@} end of group CMSIS_CoreDebug */
richardv 0:b079fa4ed182 1364
richardv 0:b079fa4ed182 1365
richardv 0:b079fa4ed182 1366 /** \ingroup CMSIS_core_register
richardv 0:b079fa4ed182 1367 \defgroup CMSIS_core_base Core Definitions
richardv 0:b079fa4ed182 1368 \brief Definitions for base addresses, unions, and structures.
richardv 0:b079fa4ed182 1369 @{
richardv 0:b079fa4ed182 1370 */
richardv 0:b079fa4ed182 1371
richardv 0:b079fa4ed182 1372 /* Memory mapping of Cortex-M4 Hardware */
richardv 0:b079fa4ed182 1373 #define SCS_BASE (0xE000E000UL) /*!< System Control Space Base Address */
richardv 0:b079fa4ed182 1374 #define ITM_BASE (0xE0000000UL) /*!< ITM Base Address */
richardv 0:b079fa4ed182 1375 #define DWT_BASE (0xE0001000UL) /*!< DWT Base Address */
richardv 0:b079fa4ed182 1376 #define TPI_BASE (0xE0040000UL) /*!< TPI Base Address */
richardv 0:b079fa4ed182 1377 #define CoreDebug_BASE (0xE000EDF0UL) /*!< Core Debug Base Address */
richardv 0:b079fa4ed182 1378 #define SysTick_BASE (SCS_BASE + 0x0010UL) /*!< SysTick Base Address */
richardv 0:b079fa4ed182 1379 #define NVIC_BASE (SCS_BASE + 0x0100UL) /*!< NVIC Base Address */
richardv 0:b079fa4ed182 1380 #define SCB_BASE (SCS_BASE + 0x0D00UL) /*!< System Control Block Base Address */
richardv 0:b079fa4ed182 1381
richardv 0:b079fa4ed182 1382 #define SCnSCB ((SCnSCB_Type *) SCS_BASE ) /*!< System control Register not in SCB */
richardv 0:b079fa4ed182 1383 #define SCB ((SCB_Type *) SCB_BASE ) /*!< SCB configuration struct */
richardv 0:b079fa4ed182 1384 #define SysTick ((SysTick_Type *) SysTick_BASE ) /*!< SysTick configuration struct */
richardv 0:b079fa4ed182 1385 #define NVIC ((NVIC_Type *) NVIC_BASE ) /*!< NVIC configuration struct */
richardv 0:b079fa4ed182 1386 #define ITM ((ITM_Type *) ITM_BASE ) /*!< ITM configuration struct */
richardv 0:b079fa4ed182 1387 #define DWT ((DWT_Type *) DWT_BASE ) /*!< DWT configuration struct */
richardv 0:b079fa4ed182 1388 #define TPI ((TPI_Type *) TPI_BASE ) /*!< TPI configuration struct */
richardv 0:b079fa4ed182 1389 #define CoreDebug ((CoreDebug_Type *) CoreDebug_BASE) /*!< Core Debug configuration struct */
richardv 0:b079fa4ed182 1390
richardv 0:b079fa4ed182 1391 #if (__MPU_PRESENT == 1)
richardv 0:b079fa4ed182 1392 #define MPU_BASE (SCS_BASE + 0x0D90UL) /*!< Memory Protection Unit */
richardv 0:b079fa4ed182 1393 #define MPU ((MPU_Type *) MPU_BASE ) /*!< Memory Protection Unit */
richardv 0:b079fa4ed182 1394 #endif
richardv 0:b079fa4ed182 1395
richardv 0:b079fa4ed182 1396 #if (__FPU_PRESENT == 1)
richardv 0:b079fa4ed182 1397 #define FPU_BASE (SCS_BASE + 0x0F30UL) /*!< Floating Point Unit */
richardv 0:b079fa4ed182 1398 #define FPU ((FPU_Type *) FPU_BASE ) /*!< Floating Point Unit */
richardv 0:b079fa4ed182 1399 #endif
richardv 0:b079fa4ed182 1400
richardv 0:b079fa4ed182 1401 /*@} */
richardv 0:b079fa4ed182 1402
richardv 0:b079fa4ed182 1403
richardv 0:b079fa4ed182 1404
richardv 0:b079fa4ed182 1405 /*******************************************************************************
richardv 0:b079fa4ed182 1406 * Hardware Abstraction Layer
richardv 0:b079fa4ed182 1407 Core Function Interface contains:
richardv 0:b079fa4ed182 1408 - Core NVIC Functions
richardv 0:b079fa4ed182 1409 - Core SysTick Functions
richardv 0:b079fa4ed182 1410 - Core Debug Functions
richardv 0:b079fa4ed182 1411 - Core Register Access Functions
richardv 0:b079fa4ed182 1412 ******************************************************************************/
richardv 0:b079fa4ed182 1413 /** \defgroup CMSIS_Core_FunctionInterface Functions and Instructions Reference
richardv 0:b079fa4ed182 1414 */
richardv 0:b079fa4ed182 1415
richardv 0:b079fa4ed182 1416
richardv 0:b079fa4ed182 1417
richardv 0:b079fa4ed182 1418 /* ########################## NVIC functions #################################### */
richardv 0:b079fa4ed182 1419 /** \ingroup CMSIS_Core_FunctionInterface
richardv 0:b079fa4ed182 1420 \defgroup CMSIS_Core_NVICFunctions NVIC Functions
richardv 0:b079fa4ed182 1421 \brief Functions that manage interrupts and exceptions via the NVIC.
richardv 0:b079fa4ed182 1422 @{
richardv 0:b079fa4ed182 1423 */
richardv 0:b079fa4ed182 1424
richardv 0:b079fa4ed182 1425 /** \brief Set Priority Grouping
richardv 0:b079fa4ed182 1426
richardv 0:b079fa4ed182 1427 The function sets the priority grouping field using the required unlock sequence.
richardv 0:b079fa4ed182 1428 The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
richardv 0:b079fa4ed182 1429 Only values from 0..7 are used.
richardv 0:b079fa4ed182 1430 In case of a conflict between priority grouping and available
richardv 0:b079fa4ed182 1431 priority bits (__NVIC_PRIO_BITS), the smallest possible priority group is set.
richardv 0:b079fa4ed182 1432
richardv 0:b079fa4ed182 1433 \param [in] PriorityGroup Priority grouping field.
richardv 0:b079fa4ed182 1434 */
richardv 0:b079fa4ed182 1435 __STATIC_INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
richardv 0:b079fa4ed182 1436 {
richardv 0:b079fa4ed182 1437 uint32_t reg_value;
richardv 0:b079fa4ed182 1438 uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07); /* only values 0..7 are used */
richardv 0:b079fa4ed182 1439
richardv 0:b079fa4ed182 1440 reg_value = SCB->AIRCR; /* read old register configuration */
richardv 0:b079fa4ed182 1441 reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk); /* clear bits to change */
richardv 0:b079fa4ed182 1442 reg_value = (reg_value |
richardv 0:b079fa4ed182 1443 ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
richardv 0:b079fa4ed182 1444 (PriorityGroupTmp << 8)); /* Insert write key and priorty group */
richardv 0:b079fa4ed182 1445 SCB->AIRCR = reg_value;
richardv 0:b079fa4ed182 1446 }
richardv 0:b079fa4ed182 1447
richardv 0:b079fa4ed182 1448
richardv 0:b079fa4ed182 1449 /** \brief Get Priority Grouping
richardv 0:b079fa4ed182 1450
richardv 0:b079fa4ed182 1451 The function reads the priority grouping field from the NVIC Interrupt Controller.
richardv 0:b079fa4ed182 1452
richardv 0:b079fa4ed182 1453 \return Priority grouping field (SCB->AIRCR [10:8] PRIGROUP field).
richardv 0:b079fa4ed182 1454 */
richardv 0:b079fa4ed182 1455 __STATIC_INLINE uint32_t NVIC_GetPriorityGrouping(void)
richardv 0:b079fa4ed182 1456 {
richardv 0:b079fa4ed182 1457 return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos); /* read priority grouping field */
richardv 0:b079fa4ed182 1458 }
richardv 0:b079fa4ed182 1459
richardv 0:b079fa4ed182 1460
richardv 0:b079fa4ed182 1461 /** \brief Enable External Interrupt
richardv 0:b079fa4ed182 1462
richardv 0:b079fa4ed182 1463 The function enables a device-specific interrupt in the NVIC interrupt controller.
richardv 0:b079fa4ed182 1464
richardv 0:b079fa4ed182 1465 \param [in] IRQn External interrupt number. Value cannot be negative.
richardv 0:b079fa4ed182 1466 */
richardv 0:b079fa4ed182 1467 __STATIC_INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
richardv 0:b079fa4ed182 1468 {
richardv 0:b079fa4ed182 1469 /* NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); enable interrupt */
richardv 0:b079fa4ed182 1470 NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
richardv 0:b079fa4ed182 1471 }
richardv 0:b079fa4ed182 1472
richardv 0:b079fa4ed182 1473
richardv 0:b079fa4ed182 1474 /** \brief Disable External Interrupt
richardv 0:b079fa4ed182 1475
richardv 0:b079fa4ed182 1476 The function disables a device-specific interrupt in the NVIC interrupt controller.
richardv 0:b079fa4ed182 1477
richardv 0:b079fa4ed182 1478 \param [in] IRQn External interrupt number. Value cannot be negative.
richardv 0:b079fa4ed182 1479 */
richardv 0:b079fa4ed182 1480 __STATIC_INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
richardv 0:b079fa4ed182 1481 {
richardv 0:b079fa4ed182 1482 NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
richardv 0:b079fa4ed182 1483 }
richardv 0:b079fa4ed182 1484
richardv 0:b079fa4ed182 1485
richardv 0:b079fa4ed182 1486 /** \brief Get Pending Interrupt
richardv 0:b079fa4ed182 1487
richardv 0:b079fa4ed182 1488 The function reads the pending register in the NVIC and returns the pending bit
richardv 0:b079fa4ed182 1489 for the specified interrupt.
richardv 0:b079fa4ed182 1490
richardv 0:b079fa4ed182 1491 \param [in] IRQn Interrupt number.
richardv 0:b079fa4ed182 1492
richardv 0:b079fa4ed182 1493 \return 0 Interrupt status is not pending.
richardv 0:b079fa4ed182 1494 \return 1 Interrupt status is pending.
richardv 0:b079fa4ed182 1495 */
richardv 0:b079fa4ed182 1496 __STATIC_INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
richardv 0:b079fa4ed182 1497 {
richardv 0:b079fa4ed182 1498 return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
richardv 0:b079fa4ed182 1499 }
richardv 0:b079fa4ed182 1500
richardv 0:b079fa4ed182 1501
richardv 0:b079fa4ed182 1502 /** \brief Set Pending Interrupt
richardv 0:b079fa4ed182 1503
richardv 0:b079fa4ed182 1504 The function sets the pending bit of an external interrupt.
richardv 0:b079fa4ed182 1505
richardv 0:b079fa4ed182 1506 \param [in] IRQn Interrupt number. Value cannot be negative.
richardv 0:b079fa4ed182 1507 */
richardv 0:b079fa4ed182 1508 __STATIC_INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
richardv 0:b079fa4ed182 1509 {
richardv 0:b079fa4ed182 1510 NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
richardv 0:b079fa4ed182 1511 }
richardv 0:b079fa4ed182 1512
richardv 0:b079fa4ed182 1513
richardv 0:b079fa4ed182 1514 /** \brief Clear Pending Interrupt
richardv 0:b079fa4ed182 1515
richardv 0:b079fa4ed182 1516 The function clears the pending bit of an external interrupt.
richardv 0:b079fa4ed182 1517
richardv 0:b079fa4ed182 1518 \param [in] IRQn External interrupt number. Value cannot be negative.
richardv 0:b079fa4ed182 1519 */
richardv 0:b079fa4ed182 1520 __STATIC_INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
richardv 0:b079fa4ed182 1521 {
richardv 0:b079fa4ed182 1522 NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
richardv 0:b079fa4ed182 1523 }
richardv 0:b079fa4ed182 1524
richardv 0:b079fa4ed182 1525
richardv 0:b079fa4ed182 1526 /** \brief Get Active Interrupt
richardv 0:b079fa4ed182 1527
richardv 0:b079fa4ed182 1528 The function reads the active register in NVIC and returns the active bit.
richardv 0:b079fa4ed182 1529
richardv 0:b079fa4ed182 1530 \param [in] IRQn Interrupt number.
richardv 0:b079fa4ed182 1531
richardv 0:b079fa4ed182 1532 \return 0 Interrupt status is not active.
richardv 0:b079fa4ed182 1533 \return 1 Interrupt status is active.
richardv 0:b079fa4ed182 1534 */
richardv 0:b079fa4ed182 1535 __STATIC_INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
richardv 0:b079fa4ed182 1536 {
richardv 0:b079fa4ed182 1537 return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
richardv 0:b079fa4ed182 1538 }
richardv 0:b079fa4ed182 1539
richardv 0:b079fa4ed182 1540
richardv 0:b079fa4ed182 1541 /** \brief Set Interrupt Priority
richardv 0:b079fa4ed182 1542
richardv 0:b079fa4ed182 1543 The function sets the priority of an interrupt.
richardv 0:b079fa4ed182 1544
richardv 0:b079fa4ed182 1545 \note The priority cannot be set for every core interrupt.
richardv 0:b079fa4ed182 1546
richardv 0:b079fa4ed182 1547 \param [in] IRQn Interrupt number.
richardv 0:b079fa4ed182 1548 \param [in] priority Priority to set.
richardv 0:b079fa4ed182 1549 */
richardv 0:b079fa4ed182 1550 __STATIC_INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
richardv 0:b079fa4ed182 1551 {
richardv 0:b079fa4ed182 1552 if(IRQn < 0) {
richardv 0:b079fa4ed182 1553 SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M System Interrupts */
richardv 0:b079fa4ed182 1554 else {
richardv 0:b079fa4ed182 1555 NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for device specific Interrupts */
richardv 0:b079fa4ed182 1556 }
richardv 0:b079fa4ed182 1557
richardv 0:b079fa4ed182 1558
richardv 0:b079fa4ed182 1559 /** \brief Get Interrupt Priority
richardv 0:b079fa4ed182 1560
richardv 0:b079fa4ed182 1561 The function reads the priority of an interrupt. The interrupt
richardv 0:b079fa4ed182 1562 number can be positive to specify an external (device specific)
richardv 0:b079fa4ed182 1563 interrupt, or negative to specify an internal (core) interrupt.
richardv 0:b079fa4ed182 1564
richardv 0:b079fa4ed182 1565
richardv 0:b079fa4ed182 1566 \param [in] IRQn Interrupt number.
richardv 0:b079fa4ed182 1567 \return Interrupt Priority. Value is aligned automatically to the implemented
richardv 0:b079fa4ed182 1568 priority bits of the microcontroller.
richardv 0:b079fa4ed182 1569 */
richardv 0:b079fa4ed182 1570 __STATIC_INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
richardv 0:b079fa4ed182 1571 {
richardv 0:b079fa4ed182 1572
richardv 0:b079fa4ed182 1573 if(IRQn < 0) {
richardv 0:b079fa4ed182 1574 return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for Cortex-M system interrupts */
richardv 0:b079fa4ed182 1575 else {
richardv 0:b079fa4ed182 1576 return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)] >> (8 - __NVIC_PRIO_BITS))); } /* get priority for device specific interrupts */
richardv 0:b079fa4ed182 1577 }
richardv 0:b079fa4ed182 1578
richardv 0:b079fa4ed182 1579
richardv 0:b079fa4ed182 1580 /** \brief Encode Priority
richardv 0:b079fa4ed182 1581
richardv 0:b079fa4ed182 1582 The function encodes the priority for an interrupt with the given priority group,
richardv 0:b079fa4ed182 1583 preemptive priority value, and subpriority value.
richardv 0:b079fa4ed182 1584 In case of a conflict between priority grouping and available
richardv 0:b079fa4ed182 1585 priority bits (__NVIC_PRIO_BITS), the samllest possible priority group is set.
richardv 0:b079fa4ed182 1586
richardv 0:b079fa4ed182 1587 \param [in] PriorityGroup Used priority group.
richardv 0:b079fa4ed182 1588 \param [in] PreemptPriority Preemptive priority value (starting from 0).
richardv 0:b079fa4ed182 1589 \param [in] SubPriority Subpriority value (starting from 0).
richardv 0:b079fa4ed182 1590 \return Encoded priority. Value can be used in the function \ref NVIC_SetPriority().
richardv 0:b079fa4ed182 1591 */
richardv 0:b079fa4ed182 1592 __STATIC_INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
richardv 0:b079fa4ed182 1593 {
richardv 0:b079fa4ed182 1594 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
richardv 0:b079fa4ed182 1595 uint32_t PreemptPriorityBits;
richardv 0:b079fa4ed182 1596 uint32_t SubPriorityBits;
richardv 0:b079fa4ed182 1597
richardv 0:b079fa4ed182 1598 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
richardv 0:b079fa4ed182 1599 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
richardv 0:b079fa4ed182 1600
richardv 0:b079fa4ed182 1601 return (
richardv 0:b079fa4ed182 1602 ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
richardv 0:b079fa4ed182 1603 ((SubPriority & ((1 << (SubPriorityBits )) - 1)))
richardv 0:b079fa4ed182 1604 );
richardv 0:b079fa4ed182 1605 }
richardv 0:b079fa4ed182 1606
richardv 0:b079fa4ed182 1607
richardv 0:b079fa4ed182 1608 /** \brief Decode Priority
richardv 0:b079fa4ed182 1609
richardv 0:b079fa4ed182 1610 The function decodes an interrupt priority value with a given priority group to
richardv 0:b079fa4ed182 1611 preemptive priority value and subpriority value.
richardv 0:b079fa4ed182 1612 In case of a conflict between priority grouping and available
richardv 0:b079fa4ed182 1613 priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
richardv 0:b079fa4ed182 1614
richardv 0:b079fa4ed182 1615 \param [in] Priority Priority value, which can be retrieved with the function \ref NVIC_GetPriority().
richardv 0:b079fa4ed182 1616 \param [in] PriorityGroup Used priority group.
richardv 0:b079fa4ed182 1617 \param [out] pPreemptPriority Preemptive priority value (starting from 0).
richardv 0:b079fa4ed182 1618 \param [out] pSubPriority Subpriority value (starting from 0).
richardv 0:b079fa4ed182 1619 */
richardv 0:b079fa4ed182 1620 __STATIC_INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
richardv 0:b079fa4ed182 1621 {
richardv 0:b079fa4ed182 1622 uint32_t PriorityGroupTmp = (PriorityGroup & 0x07); /* only values 0..7 are used */
richardv 0:b079fa4ed182 1623 uint32_t PreemptPriorityBits;
richardv 0:b079fa4ed182 1624 uint32_t SubPriorityBits;
richardv 0:b079fa4ed182 1625
richardv 0:b079fa4ed182 1626 PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
richardv 0:b079fa4ed182 1627 SubPriorityBits = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
richardv 0:b079fa4ed182 1628
richardv 0:b079fa4ed182 1629 *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
richardv 0:b079fa4ed182 1630 *pSubPriority = (Priority ) & ((1 << (SubPriorityBits )) - 1);
richardv 0:b079fa4ed182 1631 }
richardv 0:b079fa4ed182 1632
richardv 0:b079fa4ed182 1633
richardv 0:b079fa4ed182 1634 /** \brief System Reset
richardv 0:b079fa4ed182 1635
richardv 0:b079fa4ed182 1636 The function initiates a system reset request to reset the MCU.
richardv 0:b079fa4ed182 1637 */
richardv 0:b079fa4ed182 1638 __STATIC_INLINE void NVIC_SystemReset(void)
richardv 0:b079fa4ed182 1639 {
richardv 0:b079fa4ed182 1640 __DSB(); /* Ensure all outstanding memory accesses included
richardv 0:b079fa4ed182 1641 buffered write are completed before reset */
richardv 0:b079fa4ed182 1642 SCB->AIRCR = ((0x5FA << SCB_AIRCR_VECTKEY_Pos) |
richardv 0:b079fa4ed182 1643 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
richardv 0:b079fa4ed182 1644 SCB_AIRCR_SYSRESETREQ_Msk); /* Keep priority group unchanged */
richardv 0:b079fa4ed182 1645 __DSB(); /* Ensure completion of memory access */
richardv 0:b079fa4ed182 1646 while(1); /* wait until reset */
richardv 0:b079fa4ed182 1647 }
richardv 0:b079fa4ed182 1648
richardv 0:b079fa4ed182 1649 /*@} end of CMSIS_Core_NVICFunctions */
richardv 0:b079fa4ed182 1650
richardv 0:b079fa4ed182 1651
richardv 0:b079fa4ed182 1652
richardv 0:b079fa4ed182 1653 /* ################################## SysTick function ############################################ */
richardv 0:b079fa4ed182 1654 /** \ingroup CMSIS_Core_FunctionInterface
richardv 0:b079fa4ed182 1655 \defgroup CMSIS_Core_SysTickFunctions SysTick Functions
richardv 0:b079fa4ed182 1656 \brief Functions that configure the System.
richardv 0:b079fa4ed182 1657 @{
richardv 0:b079fa4ed182 1658 */
richardv 0:b079fa4ed182 1659
richardv 0:b079fa4ed182 1660 #if (__Vendor_SysTickConfig == 0)
richardv 0:b079fa4ed182 1661
richardv 0:b079fa4ed182 1662 /** \brief System Tick Configuration
richardv 0:b079fa4ed182 1663
richardv 0:b079fa4ed182 1664 The function initializes the System Timer and its interrupt, and starts the System Tick Timer.
richardv 0:b079fa4ed182 1665 Counter is in free running mode to generate periodic interrupts.
richardv 0:b079fa4ed182 1666
richardv 0:b079fa4ed182 1667 \param [in] ticks Number of ticks between two interrupts.
richardv 0:b079fa4ed182 1668
richardv 0:b079fa4ed182 1669 \return 0 Function succeeded.
richardv 0:b079fa4ed182 1670 \return 1 Function failed.
richardv 0:b079fa4ed182 1671
richardv 0:b079fa4ed182 1672 \note When the variable <b>__Vendor_SysTickConfig</b> is set to 1, then the
richardv 0:b079fa4ed182 1673 function <b>SysTick_Config</b> is not included. In this case, the file <b><i>device</i>.h</b>
richardv 0:b079fa4ed182 1674 must contain a vendor-specific implementation of this function.
richardv 0:b079fa4ed182 1675
richardv 0:b079fa4ed182 1676 */
richardv 0:b079fa4ed182 1677 __STATIC_INLINE uint32_t SysTick_Config(uint32_t ticks)
richardv 0:b079fa4ed182 1678 {
richardv 0:b079fa4ed182 1679 if ((ticks - 1) > SysTick_LOAD_RELOAD_Msk) return (1); /* Reload value impossible */
richardv 0:b079fa4ed182 1680
richardv 0:b079fa4ed182 1681 SysTick->LOAD = ticks - 1; /* set reload register */
richardv 0:b079fa4ed182 1682 NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1); /* set Priority for Systick Interrupt */
richardv 0:b079fa4ed182 1683 SysTick->VAL = 0; /* Load the SysTick Counter Value */
richardv 0:b079fa4ed182 1684 SysTick->CTRL = SysTick_CTRL_CLKSOURCE_Msk |
richardv 0:b079fa4ed182 1685 SysTick_CTRL_TICKINT_Msk |
richardv 0:b079fa4ed182 1686 SysTick_CTRL_ENABLE_Msk; /* Enable SysTick IRQ and SysTick Timer */
richardv 0:b079fa4ed182 1687 return (0); /* Function successful */
richardv 0:b079fa4ed182 1688 }
richardv 0:b079fa4ed182 1689
richardv 0:b079fa4ed182 1690 #endif
richardv 0:b079fa4ed182 1691
richardv 0:b079fa4ed182 1692 /*@} end of CMSIS_Core_SysTickFunctions */
richardv 0:b079fa4ed182 1693
richardv 0:b079fa4ed182 1694
richardv 0:b079fa4ed182 1695
richardv 0:b079fa4ed182 1696 /* ##################################### Debug In/Output function ########################################### */
richardv 0:b079fa4ed182 1697 /** \ingroup CMSIS_Core_FunctionInterface
richardv 0:b079fa4ed182 1698 \defgroup CMSIS_core_DebugFunctions ITM Functions
richardv 0:b079fa4ed182 1699 \brief Functions that access the ITM debug interface.
richardv 0:b079fa4ed182 1700 @{
richardv 0:b079fa4ed182 1701 */
richardv 0:b079fa4ed182 1702
richardv 0:b079fa4ed182 1703 extern volatile int32_t ITM_RxBuffer; /*!< External variable to receive characters. */
richardv 0:b079fa4ed182 1704 #define ITM_RXBUFFER_EMPTY 0x5AA55AA5 /*!< Value identifying \ref ITM_RxBuffer is ready for next character. */
richardv 0:b079fa4ed182 1705
richardv 0:b079fa4ed182 1706
richardv 0:b079fa4ed182 1707 /** \brief ITM Send Character
richardv 0:b079fa4ed182 1708
richardv 0:b079fa4ed182 1709 The function transmits a character via the ITM channel 0, and
richardv 0:b079fa4ed182 1710 \li Just returns when no debugger is connected that has booked the output.
richardv 0:b079fa4ed182 1711 \li Is blocking when a debugger is connected, but the previous character sent has not been transmitted.
richardv 0:b079fa4ed182 1712
richardv 0:b079fa4ed182 1713 \param [in] ch Character to transmit.
richardv 0:b079fa4ed182 1714
richardv 0:b079fa4ed182 1715 \returns Character to transmit.
richardv 0:b079fa4ed182 1716 */
richardv 0:b079fa4ed182 1717 __STATIC_INLINE uint32_t ITM_SendChar (uint32_t ch)
richardv 0:b079fa4ed182 1718 {
richardv 0:b079fa4ed182 1719 if ((ITM->TCR & ITM_TCR_ITMENA_Msk) && /* ITM enabled */
richardv 0:b079fa4ed182 1720 (ITM->TER & (1UL << 0) ) ) /* ITM Port #0 enabled */
richardv 0:b079fa4ed182 1721 {
richardv 0:b079fa4ed182 1722 while (ITM->PORT[0].u32 == 0);
richardv 0:b079fa4ed182 1723 ITM->PORT[0].u8 = (uint8_t) ch;
richardv 0:b079fa4ed182 1724 }
richardv 0:b079fa4ed182 1725 return (ch);
richardv 0:b079fa4ed182 1726 }
richardv 0:b079fa4ed182 1727
richardv 0:b079fa4ed182 1728
richardv 0:b079fa4ed182 1729 /** \brief ITM Receive Character
richardv 0:b079fa4ed182 1730
richardv 0:b079fa4ed182 1731 The function inputs a character via the external variable \ref ITM_RxBuffer.
richardv 0:b079fa4ed182 1732
richardv 0:b079fa4ed182 1733 \return Received character.
richardv 0:b079fa4ed182 1734 \return -1 No character pending.
richardv 0:b079fa4ed182 1735 */
richardv 0:b079fa4ed182 1736 __STATIC_INLINE int32_t ITM_ReceiveChar (void) {
richardv 0:b079fa4ed182 1737 int32_t ch = -1; /* no character available */
richardv 0:b079fa4ed182 1738
richardv 0:b079fa4ed182 1739 if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
richardv 0:b079fa4ed182 1740 ch = ITM_RxBuffer;
richardv 0:b079fa4ed182 1741 ITM_RxBuffer = ITM_RXBUFFER_EMPTY; /* ready for next character */
richardv 0:b079fa4ed182 1742 }
richardv 0:b079fa4ed182 1743
richardv 0:b079fa4ed182 1744 return (ch);
richardv 0:b079fa4ed182 1745 }
richardv 0:b079fa4ed182 1746
richardv 0:b079fa4ed182 1747
richardv 0:b079fa4ed182 1748 /** \brief ITM Check Character
richardv 0:b079fa4ed182 1749
richardv 0:b079fa4ed182 1750 The function checks whether a character is pending for reading in the variable \ref ITM_RxBuffer.
richardv 0:b079fa4ed182 1751
richardv 0:b079fa4ed182 1752 \return 0 No character available.
richardv 0:b079fa4ed182 1753 \return 1 Character available.
richardv 0:b079fa4ed182 1754 */
richardv 0:b079fa4ed182 1755 __STATIC_INLINE int32_t ITM_CheckChar (void) {
richardv 0:b079fa4ed182 1756
richardv 0:b079fa4ed182 1757 if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
richardv 0:b079fa4ed182 1758 return (0); /* no character available */
richardv 0:b079fa4ed182 1759 } else {
richardv 0:b079fa4ed182 1760 return (1); /* character available */
richardv 0:b079fa4ed182 1761 }
richardv 0:b079fa4ed182 1762 }
richardv 0:b079fa4ed182 1763
richardv 0:b079fa4ed182 1764 /*@} end of CMSIS_core_DebugFunctions */
richardv 0:b079fa4ed182 1765
richardv 0:b079fa4ed182 1766 #endif /* __CORE_CM4_H_DEPENDANT */
richardv 0:b079fa4ed182 1767
richardv 0:b079fa4ed182 1768 #endif /* __CMSIS_GENERIC */
richardv 0:b079fa4ed182 1769
richardv 0:b079fa4ed182 1770 #ifdef __cplusplus
richardv 0:b079fa4ed182 1771 }
richardv 0:b079fa4ed182 1772 #endif