Richard Vasquez / DMA_RAM_DAC

won't compile

system_stm32f30x.c@0:b079fa4ed182, 2016-11-02 (annotated)

Committer:
richardv
Date:
Wed Nov 02 23:50:52 2016 +0000
Revision:
0:b079fa4ed182
DMA RAM DAC

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richardv 0:b079fa4ed182 1 /**
richardv 0:b079fa4ed182 2 ******************************************************************************
richardv 0:b079fa4ed182 3 * @file system_stm32f30x.c
richardv 0:b079fa4ed182 4 * @author MCD Application Team
richardv 0:b079fa4ed182 5 * @version V1.0.0
richardv 0:b079fa4ed182 6 * @date 20-June-2014
richardv 0:b079fa4ed182 7 * @brief CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
richardv 0:b079fa4ed182 8 * This file contains the system clock configuration for STM32F30x devices
richardv 0:b079fa4ed182 9 * and is customized for use with stm32f301_nucleo Kit.
richardv 0:b079fa4ed182 10 * The STM32F30x is configured to run at 72 MHz, following the three
richardv 0:b079fa4ed182 11 * configuration below:
richardv 0:b079fa4ed182 12 * - PLL_SOURCE_HSI (default) : HSI (~8MHz) used to clock the PLL, and
richardv 0:b079fa4ed182 13 * the PLL is used as system clock source,
richardv 0:b079fa4ed182 14 * 64 MHz is maximum frequency on PLL HSI mode.
richardv 0:b079fa4ed182 15 * - PLL_SOURCE_HSE : HSE (8MHz) used to clock the PLL, and
richardv 0:b079fa4ed182 16 * the PLL is used as system clock source.
richardv 0:b079fa4ed182 17 * - PLL_SOURCE_HSE_BYPASS : HSE bypassed with an external clock
richardv 0:b079fa4ed182 18 * (8MHz, coming from ST-Link) used to clock
richardv 0:b079fa4ed182 19 * the PLL, and the PLL is used as system
richardv 0:b079fa4ed182 20 * clock source.
richardv 0:b079fa4ed182 21 *
richardv 0:b079fa4ed182 22 * 1. This file provides two functions and one global variable to be called from
richardv 0:b079fa4ed182 23 * user application:
richardv 0:b079fa4ed182 24 * - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
richardv 0:b079fa4ed182 25 * and Divider factors, AHB/APBx prescalers and Flash settings),
richardv 0:b079fa4ed182 26 * depending on the configuration made in the clock xls tool.
richardv 0:b079fa4ed182 27 * This function is called at startup just after reset and
richardv 0:b079fa4ed182 28 * before branch to main program. This call is made inside
richardv 0:b079fa4ed182 29 * the "startup_stm32f334x8.s" file.
richardv 0:b079fa4ed182 30 *
richardv 0:b079fa4ed182 31 * - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
richardv 0:b079fa4ed182 32 * by the user application to setup the SysTick
richardv 0:b079fa4ed182 33 * timer or configure other parameters.
richardv 0:b079fa4ed182 34 *
richardv 0:b079fa4ed182 35 * - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
richardv 0:b079fa4ed182 36 * be called whenever the core clock is changed
richardv 0:b079fa4ed182 37 * during program execution.
richardv 0:b079fa4ed182 38 *
richardv 0:b079fa4ed182 39 * 2. After each device reset the HSI (8 MHz) is used as system clock source.
richardv 0:b079fa4ed182 40 * Then SystemInit() function is called, in "startup_stm32f334x8.s" file, to
richardv 0:b079fa4ed182 41 * configure the system clock before to branch to main program.
richardv 0:b079fa4ed182 42 *
richardv 0:b079fa4ed182 43 * 3. If the system clock source selected by user fails to startup, the SystemInit()
richardv 0:b079fa4ed182 44 * function will do nothing and HSI still used as system clock source. User can
richardv 0:b079fa4ed182 45 * add some code to deal with this issue inside the SetSysClock() function.
richardv 0:b079fa4ed182 46 *
richardv 0:b079fa4ed182 47 * 4. The default value of HSE crystal is set to 8MHz, refer to "HSE_VALUE" define
richardv 0:b079fa4ed182 48 * in "stm32f30x.h" file. When HSE is used as system clock source, directly or
richardv 0:b079fa4ed182 49 * through PLL, and you are using different crystal you have to adapt the HSE
richardv 0:b079fa4ed182 50 * value to your own configuration.
richardv 0:b079fa4ed182 51 *
richardv 0:b079fa4ed182 52 *
richardv 0:b079fa4ed182 53 ******************************************************************************
richardv 0:b079fa4ed182 54 * @attention
richardv 0:b079fa4ed182 55 *
richardv 0:b079fa4ed182 56 * <h2><center>&copy; COPYRIGHT 2014 STMicroelectronics</center></h2>
richardv 0:b079fa4ed182 57 *
richardv 0:b079fa4ed182 58 * Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
richardv 0:b079fa4ed182 59 * You may not use this file except in compliance with the License.
richardv 0:b079fa4ed182 60 * You may obtain a copy of the License at:
richardv 0:b079fa4ed182 61 *
richardv 0:b079fa4ed182 62 * http://www.st.com/software_license_agreement_liberty_v2
richardv 0:b079fa4ed182 63 *
richardv 0:b079fa4ed182 64 * Unless required by applicable law or agreed to in writing, software
richardv 0:b079fa4ed182 65 * distributed under the License is distributed on an "AS IS" BASIS,
richardv 0:b079fa4ed182 66 * WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
richardv 0:b079fa4ed182 67 * See the License for the specific language governing permissions and
richardv 0:b079fa4ed182 68 * limitations under the License.
richardv 0:b079fa4ed182 69 *
richardv 0:b079fa4ed182 70 ******************************************************************************
richardv 0:b079fa4ed182 71 */
richardv 0:b079fa4ed182 72
richardv 0:b079fa4ed182 73 /** @addtogroup CMSIS
richardv 0:b079fa4ed182 74 * @{
richardv 0:b079fa4ed182 75 */
richardv 0:b079fa4ed182 76
richardv 0:b079fa4ed182 77 /** @addtogroup stm32f30x_system
richardv 0:b079fa4ed182 78 * @{
richardv 0:b079fa4ed182 79 */
richardv 0:b079fa4ed182 80
richardv 0:b079fa4ed182 81 /** @addtogroup STM32F30x_System_Private_Includes
richardv 0:b079fa4ed182 82 * @{
richardv 0:b079fa4ed182 83 */
richardv 0:b079fa4ed182 84
richardv 0:b079fa4ed182 85 #include "stm32f30x.h"
richardv 0:b079fa4ed182 86
richardv 0:b079fa4ed182 87 /**
richardv 0:b079fa4ed182 88 * @}
richardv 0:b079fa4ed182 89 */
richardv 0:b079fa4ed182 90
richardv 0:b079fa4ed182 91 /** @addtogroup STM32F30x_System_Private_TypesDefinitions
richardv 0:b079fa4ed182 92 * @{
richardv 0:b079fa4ed182 93 */
richardv 0:b079fa4ed182 94
richardv 0:b079fa4ed182 95 /**
richardv 0:b079fa4ed182 96 * @}
richardv 0:b079fa4ed182 97 */
richardv 0:b079fa4ed182 98
richardv 0:b079fa4ed182 99 /** @addtogroup STM32F30x_System_Private_Defines
richardv 0:b079fa4ed182 100 * @{
richardv 0:b079fa4ed182 101 */
richardv 0:b079fa4ed182 102 /*!< Uncomment the following line if you need to relocate your vector Table in
richardv 0:b079fa4ed182 103 Internal SRAM. */
richardv 0:b079fa4ed182 104 /* #define VECT_TAB_SRAM */
richardv 0:b079fa4ed182 105 #define VECT_TAB_OFFSET 0x0 /*!< Vector Table base offset field.
richardv 0:b079fa4ed182 106 This value must be a multiple of 0x200. */
richardv 0:b079fa4ed182 107 /**
richardv 0:b079fa4ed182 108 * @}
richardv 0:b079fa4ed182 109 */
richardv 0:b079fa4ed182 110
richardv 0:b079fa4ed182 111 /** @addtogroup STM32F30x_System_Private_Macros
richardv 0:b079fa4ed182 112 * @{
richardv 0:b079fa4ed182 113 */
richardv 0:b079fa4ed182 114
richardv 0:b079fa4ed182 115 /**
richardv 0:b079fa4ed182 116 * @}
richardv 0:b079fa4ed182 117 */
richardv 0:b079fa4ed182 118
richardv 0:b079fa4ed182 119 /** @addtogroup STM32F30x_System_Private_Variables
richardv 0:b079fa4ed182 120 * @{
richardv 0:b079fa4ed182 121 */
richardv 0:b079fa4ed182 122
richardv 0:b079fa4ed182 123 #define PLL_SOURCE_HSI // HSI (~8 MHz) used to clock the PLL, and the PLL is used as system clock source
richardv 0:b079fa4ed182 124 //#define PLL_SOURCE_HSE // HSE (8MHz) used to clock the PLL, and the PLL is used as system clock source
richardv 0:b079fa4ed182 125 //#define PLL_SOURCE_HSE_BYPASS // HSE bypassed with an external clock (8MHz, coming from ST-Link) used to clock
richardv 0:b079fa4ed182 126
richardv 0:b079fa4ed182 127
richardv 0:b079fa4ed182 128 uint32_t SystemCoreClock = 72000000;
richardv 0:b079fa4ed182 129
richardv 0:b079fa4ed182 130 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
richardv 0:b079fa4ed182 131
richardv 0:b079fa4ed182 132 /**
richardv 0:b079fa4ed182 133 * @}
richardv 0:b079fa4ed182 134 */
richardv 0:b079fa4ed182 135
richardv 0:b079fa4ed182 136 /** @addtogroup STM32F30x_System_Private_FunctionPrototypes
richardv 0:b079fa4ed182 137 * @{
richardv 0:b079fa4ed182 138 */
richardv 0:b079fa4ed182 139
richardv 0:b079fa4ed182 140 static void SetSysClock(void);
richardv 0:b079fa4ed182 141
richardv 0:b079fa4ed182 142 /**
richardv 0:b079fa4ed182 143 * @}
richardv 0:b079fa4ed182 144 */
richardv 0:b079fa4ed182 145
richardv 0:b079fa4ed182 146 /** @addtogroup STM32F30x_System_Private_Functions
richardv 0:b079fa4ed182 147 * @{
richardv 0:b079fa4ed182 148 */
richardv 0:b079fa4ed182 149
richardv 0:b079fa4ed182 150 /**
richardv 0:b079fa4ed182 151 * @brief Setup the microcontroller system
richardv 0:b079fa4ed182 152 * Initialize the Embedded Flash Interface, the PLL and update the
richardv 0:b079fa4ed182 153 * SystemFrequency variable.
richardv 0:b079fa4ed182 154 * @param None
richardv 0:b079fa4ed182 155 * @retval None
richardv 0:b079fa4ed182 156 */
richardv 0:b079fa4ed182 157 void SystemInit(void)
richardv 0:b079fa4ed182 158 {
richardv 0:b079fa4ed182 159 /* FPU settings ------------------------------------------------------------*/
richardv 0:b079fa4ed182 160 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
richardv 0:b079fa4ed182 161 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
richardv 0:b079fa4ed182 162 #endif
richardv 0:b079fa4ed182 163
richardv 0:b079fa4ed182 164 /* Reset the RCC clock configuration to the default reset state ------------*/
richardv 0:b079fa4ed182 165 /* Set HSION bit */
richardv 0:b079fa4ed182 166 RCC->CR |= (uint32_t)0x00000001;
richardv 0:b079fa4ed182 167
richardv 0:b079fa4ed182 168 /* Reset CFGR register */
richardv 0:b079fa4ed182 169 RCC->CFGR &= (uint32_t) 0x08C0C00C;
richardv 0:b079fa4ed182 170
richardv 0:b079fa4ed182 171 /* Reset HSEON, CSSON and PLLON bits */
richardv 0:b079fa4ed182 172 RCC->CR &= (uint32_t)0xFEF6FFFF;
richardv 0:b079fa4ed182 173
richardv 0:b079fa4ed182 174 /* Reset HSEBYP bit */
richardv 0:b079fa4ed182 175 RCC->CR &= (uint32_t)0xFFFBFFFF;
richardv 0:b079fa4ed182 176
richardv 0:b079fa4ed182 177 /* Reset PREDIV1[3:0] bits */
richardv 0:b079fa4ed182 178 RCC->CFGR2 &= (uint32_t)0xFFFFFFF0;
richardv 0:b079fa4ed182 179
richardv 0:b079fa4ed182 180 /* Reset USARTSW[1:0], I2CSW and TIMs bits */
richardv 0:b079fa4ed182 181 RCC->CFGR3 &= (uint32_t)0xFFF0FECC;
richardv 0:b079fa4ed182 182
richardv 0:b079fa4ed182 183 /* Disable all interrupts */
richardv 0:b079fa4ed182 184 RCC->CIR = 0x00000000;
richardv 0:b079fa4ed182 185
richardv 0:b079fa4ed182 186 /* Configure the System clock source, PLL Multiplier and Divider factors,
richardv 0:b079fa4ed182 187 AHB/APBx prescalers and Flash settings ----------------------------------*/
richardv 0:b079fa4ed182 188 SetSysClock();
richardv 0:b079fa4ed182 189
richardv 0:b079fa4ed182 190 #ifdef VECT_TAB_SRAM
richardv 0:b079fa4ed182 191 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM. */
richardv 0:b079fa4ed182 192 #else
richardv 0:b079fa4ed182 193 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH. */
richardv 0:b079fa4ed182 194 #endif
richardv 0:b079fa4ed182 195 }
richardv 0:b079fa4ed182 196
richardv 0:b079fa4ed182 197 /**
richardv 0:b079fa4ed182 198 * @brief Update SystemCoreClock variable according to Clock Register Values.
richardv 0:b079fa4ed182 199 * The SystemCoreClock variable contains the core clock (HCLK), it can
richardv 0:b079fa4ed182 200 * be used by the user application to setup the SysTick timer or configure
richardv 0:b079fa4ed182 201 * other parameters.
richardv 0:b079fa4ed182 202 *
richardv 0:b079fa4ed182 203 * @note Each time the core clock (HCLK) changes, this function must be called
richardv 0:b079fa4ed182 204 * to update SystemCoreClock variable value. Otherwise, any configuration
richardv 0:b079fa4ed182 205 * based on this variable will be incorrect.
richardv 0:b079fa4ed182 206 *
richardv 0:b079fa4ed182 207 * @note - The system frequency computed by this function is not the real
richardv 0:b079fa4ed182 208 * frequency in the chip. It is calculated based on the predefined
richardv 0:b079fa4ed182 209 * constant and the selected clock source:
richardv 0:b079fa4ed182 210 *
richardv 0:b079fa4ed182 211 * - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
richardv 0:b079fa4ed182 212 *
richardv 0:b079fa4ed182 213 * - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
richardv 0:b079fa4ed182 214 *
richardv 0:b079fa4ed182 215 * - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**)
richardv 0:b079fa4ed182 216 * or HSI_VALUE(*) multiplied/divided by the PLL factors.
richardv 0:b079fa4ed182 217 *
richardv 0:b079fa4ed182 218 * (*) HSI_VALUE is a constant defined in stm32f30x.h file (default value
richardv 0:b079fa4ed182 219 * 8 MHz) but the real value may vary depending on the variations
richardv 0:b079fa4ed182 220 * in voltage and temperature.
richardv 0:b079fa4ed182 221 *
richardv 0:b079fa4ed182 222 * (**) HSE_VALUE is a constant defined in stm32f30x.h file (default value
richardv 0:b079fa4ed182 223 * 8 MHz), user has to ensure that HSE_VALUE is same as the real
richardv 0:b079fa4ed182 224 * frequency of the crystal used. Otherwise, this function may
richardv 0:b079fa4ed182 225 * have wrong result.
richardv 0:b079fa4ed182 226 *
richardv 0:b079fa4ed182 227 * - The result of this function could be not correct when using fractional
richardv 0:b079fa4ed182 228 * value for HSE crystal.
richardv 0:b079fa4ed182 229 *
richardv 0:b079fa4ed182 230 * @param None
richardv 0:b079fa4ed182 231 * @retval None
richardv 0:b079fa4ed182 232 */
richardv 0:b079fa4ed182 233 void SystemCoreClockUpdate (void)
richardv 0:b079fa4ed182 234 {
richardv 0:b079fa4ed182 235 uint32_t tmp = 0, pllmull = 0, pllsource = 0, prediv1factor = 0;
richardv 0:b079fa4ed182 236
richardv 0:b079fa4ed182 237 /* Get SYSCLK source -------------------------------------------------------*/
richardv 0:b079fa4ed182 238 tmp = RCC->CFGR & RCC_CFGR_SWS;
richardv 0:b079fa4ed182 239
richardv 0:b079fa4ed182 240 switch (tmp)
richardv 0:b079fa4ed182 241 {
richardv 0:b079fa4ed182 242 case 0x00: /* HSI used as system clock */
richardv 0:b079fa4ed182 243 SystemCoreClock = HSI_VALUE;
richardv 0:b079fa4ed182 244 break;
richardv 0:b079fa4ed182 245 case 0x04: /* HSE used as system clock */
richardv 0:b079fa4ed182 246 SystemCoreClock = HSE_VALUE;
richardv 0:b079fa4ed182 247 break;
richardv 0:b079fa4ed182 248 case 0x08: /* PLL used as system clock */
richardv 0:b079fa4ed182 249 /* Get PLL clock source and multiplication factor ----------------------*/
richardv 0:b079fa4ed182 250 pllmull = RCC->CFGR & RCC_CFGR_PLLMULL;
richardv 0:b079fa4ed182 251 pllsource = RCC->CFGR & RCC_CFGR_PLLSRC;
richardv 0:b079fa4ed182 252 pllmull = ( pllmull >> 18) + 2;
richardv 0:b079fa4ed182 253
richardv 0:b079fa4ed182 254 if (pllsource == 0x00)
richardv 0:b079fa4ed182 255 {
richardv 0:b079fa4ed182 256 /* HSI oscillator clock divided by 2 selected as PLL clock entry */
richardv 0:b079fa4ed182 257 SystemCoreClock = (HSI_VALUE >> 1) * pllmull;
richardv 0:b079fa4ed182 258 }
richardv 0:b079fa4ed182 259 else
richardv 0:b079fa4ed182 260 {
richardv 0:b079fa4ed182 261 prediv1factor = (RCC->CFGR2 & RCC_CFGR2_PREDIV1) + 1;
richardv 0:b079fa4ed182 262 /* HSE oscillator clock selected as PREDIV1 clock entry */
richardv 0:b079fa4ed182 263 SystemCoreClock = (HSE_VALUE / prediv1factor) * pllmull;
richardv 0:b079fa4ed182 264 }
richardv 0:b079fa4ed182 265 break;
richardv 0:b079fa4ed182 266 default: /* HSI used as system clock */
richardv 0:b079fa4ed182 267 SystemCoreClock = HSI_VALUE;
richardv 0:b079fa4ed182 268 break;
richardv 0:b079fa4ed182 269 }
richardv 0:b079fa4ed182 270 /* Compute HCLK clock frequency ----------------*/
richardv 0:b079fa4ed182 271 /* Get HCLK prescaler */
richardv 0:b079fa4ed182 272 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
richardv 0:b079fa4ed182 273 /* HCLK clock frequency */
richardv 0:b079fa4ed182 274 SystemCoreClock >>= tmp;
richardv 0:b079fa4ed182 275 }
richardv 0:b079fa4ed182 276
richardv 0:b079fa4ed182 277 /**
richardv 0:b079fa4ed182 278 * @brief Configures the System clock source, PLL Multiplier and Divider factors,
richardv 0:b079fa4ed182 279 * AHB/APBx prescalers and Flash settings
richardv 0:b079fa4ed182 280 * @note This function should be called only once the RCC clock configuration
richardv 0:b079fa4ed182 281 * is reset to the default reset state (done in SystemInit() function).
richardv 0:b079fa4ed182 282 * @param None
richardv 0:b079fa4ed182 283 * @retval None
richardv 0:b079fa4ed182 284 */
richardv 0:b079fa4ed182 285 static void SetSysClock(void)
richardv 0:b079fa4ed182 286 {
richardv 0:b079fa4ed182 287 __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
richardv 0:b079fa4ed182 288
richardv 0:b079fa4ed182 289 #ifdef PLL_SOURCE_HSI
richardv 0:b079fa4ed182 290 /* At this stage the HSI is already enabled */
richardv 0:b079fa4ed182 291
richardv 0:b079fa4ed182 292 /* PLL configuration: PLLCLK = HSI/2 *16 = 64 MHz Max frequency on PLL HSI mode*/
richardv 0:b079fa4ed182 293 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLMULL));
richardv 0:b079fa4ed182 294 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_HSI_Div2 | RCC_CFGR_PLLMULL16);
richardv 0:b079fa4ed182 295
richardv 0:b079fa4ed182 296
richardv 0:b079fa4ed182 297 #else /* PLL_SOURCE_HSE_BYPASS or PLL_SOURCE_HSE */
richardv 0:b079fa4ed182 298
richardv 0:b079fa4ed182 299 /* Enable HSE */
richardv 0:b079fa4ed182 300 RCC->CR |= ((uint32_t)RCC_CR_HSEON);
richardv 0:b079fa4ed182 301 #ifdef PLL_SOURCE_HSE_BYPASS
richardv 0:b079fa4ed182 302 RCC->CR |= ((uint32_t)RCC_CR_HSEBYP);
richardv 0:b079fa4ed182 303 #endif /* PLL_SOURCE_HSE_BYPASS */
richardv 0:b079fa4ed182 304
richardv 0:b079fa4ed182 305 /* Wait till HSE is ready and if Time out is reached exit */
richardv 0:b079fa4ed182 306 do
richardv 0:b079fa4ed182 307 {
richardv 0:b079fa4ed182 308 HSEStatus = RCC->CR & RCC_CR_HSERDY;
richardv 0:b079fa4ed182 309 StartUpCounter++;
richardv 0:b079fa4ed182 310 } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
richardv 0:b079fa4ed182 311
richardv 0:b079fa4ed182 312 if ((RCC->CR & RCC_CR_HSERDY) != RESET)
richardv 0:b079fa4ed182 313 {
richardv 0:b079fa4ed182 314 HSEStatus = (uint32_t)0x01;
richardv 0:b079fa4ed182 315 }
richardv 0:b079fa4ed182 316 else
richardv 0:b079fa4ed182 317 {
richardv 0:b079fa4ed182 318 HSEStatus = (uint32_t)0x00;
richardv 0:b079fa4ed182 319 }
richardv 0:b079fa4ed182 320
richardv 0:b079fa4ed182 321 if (HSEStatus == (uint32_t)0x01)
richardv 0:b079fa4ed182 322 {
richardv 0:b079fa4ed182 323 /* PLL configuration: PLLCLK = HSE * 9 = 72 MHz */
richardv 0:b079fa4ed182 324 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_PLLSRC | RCC_CFGR_PLLXTPRE |
richardv 0:b079fa4ed182 325 RCC_CFGR_PLLMULL));
richardv 0:b079fa4ed182 326 RCC->CFGR |= (uint32_t)(RCC_CFGR_PLLSRC_PREDIV1 | RCC_CFGR_PLLMULL9);
richardv 0:b079fa4ed182 327 }
richardv 0:b079fa4ed182 328
richardv 0:b079fa4ed182 329 else
richardv 0:b079fa4ed182 330 { /* If HSE fails to start-up, the application will have wrong clock
richardv 0:b079fa4ed182 331 configuration. User can add here some code to deal with this error */
richardv 0:b079fa4ed182 332 }
richardv 0:b079fa4ed182 333
richardv 0:b079fa4ed182 334 #endif /*PLL_SOURCE_HSI*/
richardv 0:b079fa4ed182 335
richardv 0:b079fa4ed182 336 /* Enable Prefetch Buffer and set Flash Latency */
richardv 0:b079fa4ed182 337 FLASH->ACR = FLASH_ACR_PRFTBE | FLASH_ACR_LATENCY_1;
richardv 0:b079fa4ed182 338 /* HCLK = SYSCLK */
richardv 0:b079fa4ed182 339 RCC->CFGR |= (uint32_t)RCC_CFGR_HPRE_DIV1;
richardv 0:b079fa4ed182 340
richardv 0:b079fa4ed182 341 /* PCLK2 = HCLK */
richardv 0:b079fa4ed182 342 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE2_DIV1;
richardv 0:b079fa4ed182 343
richardv 0:b079fa4ed182 344 /* PCLK1 = HCLK */
richardv 0:b079fa4ed182 345 RCC->CFGR |= (uint32_t)RCC_CFGR_PPRE1_DIV2;
richardv 0:b079fa4ed182 346
richardv 0:b079fa4ed182 347 /* Enable PLL */
richardv 0:b079fa4ed182 348 RCC->CR |= RCC_CR_PLLON;
richardv 0:b079fa4ed182 349
richardv 0:b079fa4ed182 350 /* Wait till PLL is ready */
richardv 0:b079fa4ed182 351 while((RCC->CR & RCC_CR_PLLRDY) == 0)
richardv 0:b079fa4ed182 352 {
richardv 0:b079fa4ed182 353 }
richardv 0:b079fa4ed182 354
richardv 0:b079fa4ed182 355 /* Select PLL as system clock source */
richardv 0:b079fa4ed182 356 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
richardv 0:b079fa4ed182 357 RCC->CFGR |= (uint32_t)RCC_CFGR_SW_PLL;
richardv 0:b079fa4ed182 358
richardv 0:b079fa4ed182 359 /* Wait till PLL is used as system clock source */
richardv 0:b079fa4ed182 360 while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS) != (uint32_t)RCC_CFGR_SWS_PLL)
richardv 0:b079fa4ed182 361 {
richardv 0:b079fa4ed182 362 }
richardv 0:b079fa4ed182 363
richardv 0:b079fa4ed182 364 }
richardv 0:b079fa4ed182 365
richardv 0:b079fa4ed182 366 /**
richardv 0:b079fa4ed182 367 * @}
richardv 0:b079fa4ed182 368 */
richardv 0:b079fa4ed182 369
richardv 0:b079fa4ed182 370 /**
richardv 0:b079fa4ed182 371 * @}
richardv 0:b079fa4ed182 372 */
richardv 0:b079fa4ed182 373
richardv 0:b079fa4ed182 374 /**
richardv 0:b079fa4ed182 375 * @}
richardv 0:b079fa4ed182 376 */
richardv 0:b079fa4ed182 377
richardv 0:b079fa4ed182 378 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/