DMA_RAM_DAC - won't compile

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stm32f30x_tim.h@0:b079fa4ed182, 2016-11-02 (annotated)

Committer:: richardv
Date:: Wed Nov 02 23:50:52 2016 +0000
Revision:: 0:b079fa4ed182

DMA RAM DAC

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richardv	0:b079fa4ed182	1	/**
richardv	0:b079fa4ed182	2	******************************************************************************
richardv	0:b079fa4ed182	3	* @file stm32f30x_tim.h
richardv	0:b079fa4ed182	4	* @author MCD Application Team
richardv	0:b079fa4ed182	5	* @version V1.1.1
richardv	0:b079fa4ed182	6	* @date 04-April-2014
richardv	0:b079fa4ed182	7	* @brief This file contains all the functions prototypes for the TIM firmware
richardv	0:b079fa4ed182	8	* library.
richardv	0:b079fa4ed182	9	******************************************************************************
richardv	0:b079fa4ed182	10	* @attention
richardv	0:b079fa4ed182	11	*
richardv	0:b079fa4ed182	12	* <h2><center>© COPYRIGHT 2014 STMicroelectronics</center></h2>
richardv	0:b079fa4ed182	13	*
richardv	0:b079fa4ed182	14	* Licensed under MCD-ST Liberty SW License Agreement V2, (the "License");
richardv	0:b079fa4ed182	15	* You may not use this file except in compliance with the License.
richardv	0:b079fa4ed182	16	* You may obtain a copy of the License at:
richardv	0:b079fa4ed182	17	*
richardv	0:b079fa4ed182	18	* http://www.st.com/software_license_agreement_liberty_v2
richardv	0:b079fa4ed182	19	*
richardv	0:b079fa4ed182	20	* Unless required by applicable law or agreed to in writing, software
richardv	0:b079fa4ed182	21	* distributed under the License is distributed on an "AS IS" BASIS,
richardv	0:b079fa4ed182	22	* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
richardv	0:b079fa4ed182	23	* See the License for the specific language governing permissions and
richardv	0:b079fa4ed182	24	* limitations under the License.
richardv	0:b079fa4ed182	25	*
richardv	0:b079fa4ed182	26	******************************************************************************
richardv	0:b079fa4ed182	27	*/
richardv	0:b079fa4ed182	28
richardv	0:b079fa4ed182	29	/* Define to prevent recursive inclusion -------------------------------------*/
richardv	0:b079fa4ed182	30	#ifndef __STM32F30x_TIM_H
richardv	0:b079fa4ed182	31	#define __STM32F30x_TIM_H
richardv	0:b079fa4ed182	32
richardv	0:b079fa4ed182	33	#ifdef __cplusplus
richardv	0:b079fa4ed182	34	extern "C" {
richardv	0:b079fa4ed182	35	#endif
richardv	0:b079fa4ed182	36
richardv	0:b079fa4ed182	37	/* Includes ------------------------------------------------------------------*/
richardv	0:b079fa4ed182	38	#include "stm32f30x.h"
richardv	0:b079fa4ed182	39
richardv	0:b079fa4ed182	40	/** @addtogroup stm32f30x_StdPeriph_Driver
richardv	0:b079fa4ed182	41	* @{
richardv	0:b079fa4ed182	42	*/
richardv	0:b079fa4ed182	43
richardv	0:b079fa4ed182	44	/** @addtogroup TIM
richardv	0:b079fa4ed182	45	* @{
richardv	0:b079fa4ed182	46	*/
richardv	0:b079fa4ed182	47
richardv	0:b079fa4ed182	48	/* Exported types ------------------------------------------------------------*/
richardv	0:b079fa4ed182	49
richardv	0:b079fa4ed182	50	/**
richardv	0:b079fa4ed182	51	* @brief TIM Time Base Init structure definition
richardv	0:b079fa4ed182	52	* @note This structure is used with all TIMx except for TIM6 and TIM7.
richardv	0:b079fa4ed182	53	*/
richardv	0:b079fa4ed182	54
richardv	0:b079fa4ed182	55	typedef struct
richardv	0:b079fa4ed182	56	{
richardv	0:b079fa4ed182	57	uint16_t TIM_Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
richardv	0:b079fa4ed182	58	This parameter can be a number between 0x0000 and 0xFFFF */
richardv	0:b079fa4ed182	59
richardv	0:b079fa4ed182	60	uint16_t TIM_CounterMode; /*!< Specifies the counter mode.
richardv	0:b079fa4ed182	61	This parameter can be a value of @ref TIM_Counter_Mode */
richardv	0:b079fa4ed182	62
richardv	0:b079fa4ed182	63	uint32_t TIM_Period; /*!< Specifies the period value to be loaded into the active
richardv	0:b079fa4ed182	64	Auto-Reload Register at the next update event.
richardv	0:b079fa4ed182	65	This parameter must be a number between 0x0000 and 0xFFFF. */
richardv	0:b079fa4ed182	66
richardv	0:b079fa4ed182	67	uint16_t TIM_ClockDivision; /*!< Specifies the clock division.
richardv	0:b079fa4ed182	68	This parameter can be a value of @ref TIM_Clock_Division_CKD */
richardv	0:b079fa4ed182	69
richardv	0:b079fa4ed182	70	uint16_t TIM_RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
richardv	0:b079fa4ed182	71	reaches zero, an update event is generated and counting restarts
richardv	0:b079fa4ed182	72	from the RCR value (N).
richardv	0:b079fa4ed182	73	This means in PWM mode that (N+1) corresponds to:
richardv	0:b079fa4ed182	74	- the number of PWM periods in edge-aligned mode
richardv	0:b079fa4ed182	75	- the number of half PWM period in center-aligned mode
richardv	0:b079fa4ed182	76	This parameter must be a number between 0x00 and 0xFF.
richardv	0:b079fa4ed182	77	@note This parameter is valid only for TIM1 and TIM8. */
richardv	0:b079fa4ed182	78	} TIM_TimeBaseInitTypeDef;
richardv	0:b079fa4ed182	79
richardv	0:b079fa4ed182	80	/**
richardv	0:b079fa4ed182	81	* @brief TIM Output Compare Init structure definition
richardv	0:b079fa4ed182	82	*/
richardv	0:b079fa4ed182	83
richardv	0:b079fa4ed182	84	typedef struct
richardv	0:b079fa4ed182	85	{
richardv	0:b079fa4ed182	86	uint32_t TIM_OCMode; /*!< Specifies the TIM mode.
richardv	0:b079fa4ed182	87	This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
richardv	0:b079fa4ed182	88
richardv	0:b079fa4ed182	89	uint16_t TIM_OutputState; /*!< Specifies the TIM Output Compare state.
richardv	0:b079fa4ed182	90	This parameter can be a value of @ref TIM_Output_Compare_State */
richardv	0:b079fa4ed182	91
richardv	0:b079fa4ed182	92	uint16_t TIM_OutputNState; /*!< Specifies the TIM complementary Output Compare state.
richardv	0:b079fa4ed182	93	This parameter can be a value of @ref TIM_Output_Compare_N_State
richardv	0:b079fa4ed182	94	@note This parameter is valid only for TIM1 and TIM8. */
richardv	0:b079fa4ed182	95
richardv	0:b079fa4ed182	96	uint32_t TIM_Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
richardv	0:b079fa4ed182	97	This parameter can be a number between 0x0000 and 0xFFFF */
richardv	0:b079fa4ed182	98
richardv	0:b079fa4ed182	99	uint16_t TIM_OCPolarity; /*!< Specifies the output polarity.
richardv	0:b079fa4ed182	100	This parameter can be a value of @ref TIM_Output_Compare_Polarity */
richardv	0:b079fa4ed182	101
richardv	0:b079fa4ed182	102	uint16_t TIM_OCNPolarity; /*!< Specifies the complementary output polarity.
richardv	0:b079fa4ed182	103	This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
richardv	0:b079fa4ed182	104	@note This parameter is valid only for TIM1 and TIM8. */
richardv	0:b079fa4ed182	105
richardv	0:b079fa4ed182	106	uint16_t TIM_OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
richardv	0:b079fa4ed182	107	This parameter can be a value of @ref TIM_Output_Compare_Idle_State
richardv	0:b079fa4ed182	108	@note This parameter is valid only for TIM1 and TIM8. */
richardv	0:b079fa4ed182	109
richardv	0:b079fa4ed182	110	uint16_t TIM_OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
richardv	0:b079fa4ed182	111	This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
richardv	0:b079fa4ed182	112	@note This parameter is valid only for TIM1 and TIM8. */
richardv	0:b079fa4ed182	113	} TIM_OCInitTypeDef;
richardv	0:b079fa4ed182	114
richardv	0:b079fa4ed182	115	/**
richardv	0:b079fa4ed182	116	* @brief TIM Input Capture Init structure definition
richardv	0:b079fa4ed182	117	*/
richardv	0:b079fa4ed182	118
richardv	0:b079fa4ed182	119	typedef struct
richardv	0:b079fa4ed182	120	{
richardv	0:b079fa4ed182	121
richardv	0:b079fa4ed182	122	uint16_t TIM_Channel; /*!< Specifies the TIM channel.
richardv	0:b079fa4ed182	123	This parameter can be a value of @ref TIM_Channel */
richardv	0:b079fa4ed182	124
richardv	0:b079fa4ed182	125	uint16_t TIM_ICPolarity; /*!< Specifies the active edge of the input signal.
richardv	0:b079fa4ed182	126	This parameter can be a value of @ref TIM_Input_Capture_Polarity */
richardv	0:b079fa4ed182	127
richardv	0:b079fa4ed182	128	uint16_t TIM_ICSelection; /*!< Specifies the input.
richardv	0:b079fa4ed182	129	This parameter can be a value of @ref TIM_Input_Capture_Selection */
richardv	0:b079fa4ed182	130
richardv	0:b079fa4ed182	131	uint16_t TIM_ICPrescaler; /*!< Specifies the Input Capture Prescaler.
richardv	0:b079fa4ed182	132	This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
richardv	0:b079fa4ed182	133
richardv	0:b079fa4ed182	134	uint16_t TIM_ICFilter; /*!< Specifies the input capture filter.
richardv	0:b079fa4ed182	135	This parameter can be a number between 0x0 and 0xF */
richardv	0:b079fa4ed182	136	} TIM_ICInitTypeDef;
richardv	0:b079fa4ed182	137
richardv	0:b079fa4ed182	138	/**
richardv	0:b079fa4ed182	139	* @brief BDTR structure definition
richardv	0:b079fa4ed182	140	* @note This structure is used only with TIM1 and TIM8.
richardv	0:b079fa4ed182	141	*/
richardv	0:b079fa4ed182	142
richardv	0:b079fa4ed182	143	typedef struct
richardv	0:b079fa4ed182	144	{
richardv	0:b079fa4ed182	145
richardv	0:b079fa4ed182	146	uint16_t TIM_OSSRState; /*!< Specifies the Off-State selection used in Run mode.
richardv	0:b079fa4ed182	147	This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
richardv	0:b079fa4ed182	148
richardv	0:b079fa4ed182	149	uint16_t TIM_OSSIState; /*!< Specifies the Off-State used in Idle state.
richardv	0:b079fa4ed182	150	This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
richardv	0:b079fa4ed182	151
richardv	0:b079fa4ed182	152	uint16_t TIM_LOCKLevel; /*!< Specifies the LOCK level parameters.
richardv	0:b079fa4ed182	153	This parameter can be a value of @ref TIM_Lock_level */
richardv	0:b079fa4ed182	154
richardv	0:b079fa4ed182	155	uint16_t TIM_DeadTime; /*!< Specifies the delay time between the switching-off and the
richardv	0:b079fa4ed182	156	switching-on of the outputs.
richardv	0:b079fa4ed182	157	This parameter can be a number between 0x00 and 0xFF */
richardv	0:b079fa4ed182	158
richardv	0:b079fa4ed182	159	uint16_t TIM_Break; /*!< Specifies whether the TIM Break input is enabled or not.
richardv	0:b079fa4ed182	160	This parameter can be a value of @ref TIM_Break_Input_enable_disable */
richardv	0:b079fa4ed182	161
richardv	0:b079fa4ed182	162	uint16_t TIM_BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
richardv	0:b079fa4ed182	163	This parameter can be a value of @ref TIM_Break_Polarity */
richardv	0:b079fa4ed182	164
richardv	0:b079fa4ed182	165	uint16_t TIM_AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
richardv	0:b079fa4ed182	166	This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
richardv	0:b079fa4ed182	167	} TIM_BDTRInitTypeDef;
richardv	0:b079fa4ed182	168
richardv	0:b079fa4ed182	169	/* Exported constants --------------------------------------------------------*/
richardv	0:b079fa4ed182	170
richardv	0:b079fa4ed182	171	/** @defgroup TIM_Exported_constants
richardv	0:b079fa4ed182	172	* @{
richardv	0:b079fa4ed182	173	*/
richardv	0:b079fa4ed182	174
richardv	0:b079fa4ed182	175	#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) \|\| \
richardv	0:b079fa4ed182	176	((PERIPH) == TIM2) \|\| \
richardv	0:b079fa4ed182	177	((PERIPH) == TIM3) \|\| \
richardv	0:b079fa4ed182	178	((PERIPH) == TIM4) \|\| \
richardv	0:b079fa4ed182	179	((PERIPH) == TIM6) \|\| \
richardv	0:b079fa4ed182	180	((PERIPH) == TIM7) \|\| \
richardv	0:b079fa4ed182	181	((PERIPH) == TIM8) \|\| \
richardv	0:b079fa4ed182	182	((PERIPH) == TIM15) \|\| \
richardv	0:b079fa4ed182	183	((PERIPH) == TIM16) \|\| \
richardv	0:b079fa4ed182	184	((PERIPH) == TIM17))
richardv	0:b079fa4ed182	185	/* LIST1: TIM1, TIM2, TIM3, TIM4, TIM8, TIM15, TIM16 and TIM17 */
richardv	0:b079fa4ed182	186	#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) \|\| \
richardv	0:b079fa4ed182	187	((PERIPH) == TIM2) \|\| \
richardv	0:b079fa4ed182	188	((PERIPH) == TIM3) \|\| \
richardv	0:b079fa4ed182	189	((PERIPH) == TIM4) \|\| \
richardv	0:b079fa4ed182	190	((PERIPH) == TIM8) \|\| \
richardv	0:b079fa4ed182	191	((PERIPH) == TIM15) \|\| \
richardv	0:b079fa4ed182	192	((PERIPH) == TIM16) \|\| \
richardv	0:b079fa4ed182	193	((PERIPH) == TIM17))
richardv	0:b079fa4ed182	194
richardv	0:b079fa4ed182	195	/* LIST2: TIM1, TIM2, TIM3, TIM4, TIM8 and TIM15 */
richardv	0:b079fa4ed182	196	#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) \|\| \
richardv	0:b079fa4ed182	197	((PERIPH) == TIM2) \|\| \
richardv	0:b079fa4ed182	198	((PERIPH) == TIM3) \|\| \
richardv	0:b079fa4ed182	199	((PERIPH) == TIM4) \|\| \
richardv	0:b079fa4ed182	200	((PERIPH) == TIM8) \|\| \
richardv	0:b079fa4ed182	201	((PERIPH) == TIM15))
richardv	0:b079fa4ed182	202	/* LIST3: TIM1, TIM2, TIM3, TIM4 and TIM8 */
richardv	0:b079fa4ed182	203	#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) \|\| \
richardv	0:b079fa4ed182	204	((PERIPH) == TIM2) \|\| \
richardv	0:b079fa4ed182	205	((PERIPH) == TIM3) \|\| \
richardv	0:b079fa4ed182	206	((PERIPH) == TIM4) \|\| \
richardv	0:b079fa4ed182	207	((PERIPH) == TIM8))
richardv	0:b079fa4ed182	208	/* LIST4: TIM1 and TIM8 */
richardv	0:b079fa4ed182	209	#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) \|\|\
richardv	0:b079fa4ed182	210	((PERIPH) == TIM8))
richardv	0:b079fa4ed182	211	/* LIST5: TIM1, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7 and TIM8 */
richardv	0:b079fa4ed182	212	#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) \|\| \
richardv	0:b079fa4ed182	213	((PERIPH) == TIM2) \|\| \
richardv	0:b079fa4ed182	214	((PERIPH) == TIM3) \|\| \
richardv	0:b079fa4ed182	215	((PERIPH) == TIM4) \|\| \
richardv	0:b079fa4ed182	216	((PERIPH) == TIM6) \|\| \
richardv	0:b079fa4ed182	217	((PERIPH) == TIM7) \|\| \
richardv	0:b079fa4ed182	218	((PERIPH) == TIM8))
richardv	0:b079fa4ed182	219	/* LIST6: TIM1, TIM8, TIM15, TIM16 and TIM17 */
richardv	0:b079fa4ed182	220	#define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) \|\| \
richardv	0:b079fa4ed182	221	((PERIPH) == TIM8) \|\| \
richardv	0:b079fa4ed182	222	((PERIPH) == TIM15) \|\| \
richardv	0:b079fa4ed182	223	((PERIPH) == TIM16) \|\| \
richardv	0:b079fa4ed182	224	((PERIPH) == TIM17))
richardv	0:b079fa4ed182	225
richardv	0:b079fa4ed182	226	/* LIST5: TIM1, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7 and TIM8 */
richardv	0:b079fa4ed182	227	#define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) \|\| \
richardv	0:b079fa4ed182	228	((PERIPH) == TIM2) \|\| \
richardv	0:b079fa4ed182	229	((PERIPH) == TIM3) \|\| \
richardv	0:b079fa4ed182	230	((PERIPH) == TIM4) \|\| \
richardv	0:b079fa4ed182	231	((PERIPH) == TIM6) \|\| \
richardv	0:b079fa4ed182	232	((PERIPH) == TIM7) \|\| \
richardv	0:b079fa4ed182	233	((PERIPH) == TIM8) \|\| \
richardv	0:b079fa4ed182	234	((PERIPH) == TIM15))
richardv	0:b079fa4ed182	235	/* LIST8: TIM16 (option register) */
richardv	0:b079fa4ed182	236	#define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM16)\|\| \
richardv	0:b079fa4ed182	237	((PERIPH) == TIM1)\|\|\
richardv	0:b079fa4ed182	238	((PERIPH) == TIM8))
richardv	0:b079fa4ed182	239
richardv	0:b079fa4ed182	240	/** @defgroup TIM_Output_Compare_and_PWM_modes
richardv	0:b079fa4ed182	241	* @{
richardv	0:b079fa4ed182	242	*/
richardv	0:b079fa4ed182	243
richardv	0:b079fa4ed182	244	#define TIM_OCMode_Timing ((uint32_t)0x00000)
richardv	0:b079fa4ed182	245	#define TIM_OCMode_Active ((uint32_t)0x00010)
richardv	0:b079fa4ed182	246	#define TIM_OCMode_Inactive ((uint32_t)0x00020)
richardv	0:b079fa4ed182	247	#define TIM_OCMode_Toggle ((uint32_t)0x00030)
richardv	0:b079fa4ed182	248	#define TIM_OCMode_PWM1 ((uint32_t)0x00060)
richardv	0:b079fa4ed182	249	#define TIM_OCMode_PWM2 ((uint32_t)0x00070)
richardv	0:b079fa4ed182	250
richardv	0:b079fa4ed182	251	#define TIM_OCMode_Retrigerrable_OPM1 ((uint32_t)0x10000)
richardv	0:b079fa4ed182	252	#define TIM_OCMode_Retrigerrable_OPM2 ((uint32_t)0x10010)
richardv	0:b079fa4ed182	253	#define TIM_OCMode_Combined_PWM1 ((uint32_t)0x10040)
richardv	0:b079fa4ed182	254	#define TIM_OCMode_Combined_PWM2 ((uint32_t)0x10050)
richardv	0:b079fa4ed182	255	#define TIM_OCMode_Asymmetric_PWM1 ((uint32_t)0x10060)
richardv	0:b079fa4ed182	256	#define TIM_OCMode_Asymmetric_PWM2 ((uint32_t)0x10070)
richardv	0:b079fa4ed182	257
richardv	0:b079fa4ed182	258	#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) \|\| \
richardv	0:b079fa4ed182	259	((MODE) == TIM_OCMode_Active) \|\| \
richardv	0:b079fa4ed182	260	((MODE) == TIM_OCMode_Inactive) \|\| \
richardv	0:b079fa4ed182	261	((MODE) == TIM_OCMode_Toggle)\|\| \
richardv	0:b079fa4ed182	262	((MODE) == TIM_OCMode_PWM1) \|\| \
richardv	0:b079fa4ed182	263	((MODE) == TIM_OCMode_PWM2) \|\| \
richardv	0:b079fa4ed182	264	((MODE) == TIM_OCMode_Retrigerrable_OPM1) \|\| \
richardv	0:b079fa4ed182	265	((MODE) == TIM_OCMode_Retrigerrable_OPM2) \|\| \
richardv	0:b079fa4ed182	266	((MODE) == TIM_OCMode_Combined_PWM1) \|\| \
richardv	0:b079fa4ed182	267	((MODE) == TIM_OCMode_Combined_PWM2) \|\| \
richardv	0:b079fa4ed182	268	((MODE) == TIM_OCMode_Asymmetric_PWM1) \|\| \
richardv	0:b079fa4ed182	269	((MODE) == TIM_OCMode_Asymmetric_PWM2))
richardv	0:b079fa4ed182	270
richardv	0:b079fa4ed182	271	#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) \|\| \
richardv	0:b079fa4ed182	272	((MODE) == TIM_OCMode_Active) \|\| \
richardv	0:b079fa4ed182	273	((MODE) == TIM_OCMode_Inactive) \|\| \
richardv	0:b079fa4ed182	274	((MODE) == TIM_OCMode_Toggle)\|\| \
richardv	0:b079fa4ed182	275	((MODE) == TIM_OCMode_PWM1) \|\| \
richardv	0:b079fa4ed182	276	((MODE) == TIM_OCMode_PWM2) \|\| \
richardv	0:b079fa4ed182	277	((MODE) == TIM_ForcedAction_Active) \|\| \
richardv	0:b079fa4ed182	278	((MODE) == TIM_ForcedAction_InActive) \|\| \
richardv	0:b079fa4ed182	279	((MODE) == TIM_OCMode_Retrigerrable_OPM1) \|\| \
richardv	0:b079fa4ed182	280	((MODE) == TIM_OCMode_Retrigerrable_OPM2) \|\| \
richardv	0:b079fa4ed182	281	((MODE) == TIM_OCMode_Combined_PWM1) \|\| \
richardv	0:b079fa4ed182	282	((MODE) == TIM_OCMode_Combined_PWM2) \|\| \
richardv	0:b079fa4ed182	283	((MODE) == TIM_OCMode_Asymmetric_PWM1) \|\| \
richardv	0:b079fa4ed182	284	((MODE) == TIM_OCMode_Asymmetric_PWM2))
richardv	0:b079fa4ed182	285	/**
richardv	0:b079fa4ed182	286	* @}
richardv	0:b079fa4ed182	287	*/
richardv	0:b079fa4ed182	288
richardv	0:b079fa4ed182	289	/** @defgroup TIM_One_Pulse_Mode
richardv	0:b079fa4ed182	290	* @{
richardv	0:b079fa4ed182	291	*/
richardv	0:b079fa4ed182	292
richardv	0:b079fa4ed182	293	#define TIM_OPMode_Single ((uint16_t)0x0008)
richardv	0:b079fa4ed182	294	#define TIM_OPMode_Repetitive ((uint16_t)0x0000)
richardv	0:b079fa4ed182	295	#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) \|\| \
richardv	0:b079fa4ed182	296	((MODE) == TIM_OPMode_Repetitive))
richardv	0:b079fa4ed182	297	/**
richardv	0:b079fa4ed182	298	* @}
richardv	0:b079fa4ed182	299	*/
richardv	0:b079fa4ed182	300
richardv	0:b079fa4ed182	301	/** @defgroup TIM_Channel
richardv	0:b079fa4ed182	302	* @{
richardv	0:b079fa4ed182	303	*/
richardv	0:b079fa4ed182	304
richardv	0:b079fa4ed182	305	#define TIM_Channel_1 ((uint16_t)0x0000)
richardv	0:b079fa4ed182	306	#define TIM_Channel_2 ((uint16_t)0x0004)
richardv	0:b079fa4ed182	307	#define TIM_Channel_3 ((uint16_t)0x0008)
richardv	0:b079fa4ed182	308	#define TIM_Channel_4 ((uint16_t)0x000C)
richardv	0:b079fa4ed182	309	#define TIM_Channel_5 ((uint16_t)0x0010)
richardv	0:b079fa4ed182	310	#define TIM_Channel_6 ((uint16_t)0x0014)
richardv	0:b079fa4ed182	311
richardv	0:b079fa4ed182	312	#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) \|\| \
richardv	0:b079fa4ed182	313	((CHANNEL) == TIM_Channel_2) \|\| \
richardv	0:b079fa4ed182	314	((CHANNEL) == TIM_Channel_3) \|\| \
richardv	0:b079fa4ed182	315	((CHANNEL) == TIM_Channel_4))
richardv	0:b079fa4ed182	316
richardv	0:b079fa4ed182	317	#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) \|\| \
richardv	0:b079fa4ed182	318	((CHANNEL) == TIM_Channel_2))
richardv	0:b079fa4ed182	319	#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) \|\| \
richardv	0:b079fa4ed182	320	((CHANNEL) == TIM_Channel_2) \|\| \
richardv	0:b079fa4ed182	321	((CHANNEL) == TIM_Channel_3))
richardv	0:b079fa4ed182	322	/**
richardv	0:b079fa4ed182	323	* @}
richardv	0:b079fa4ed182	324	*/
richardv	0:b079fa4ed182	325
richardv	0:b079fa4ed182	326	/** @defgroup TIM_Clock_Division_CKD
richardv	0:b079fa4ed182	327	* @{
richardv	0:b079fa4ed182	328	*/
richardv	0:b079fa4ed182	329
richardv	0:b079fa4ed182	330	#define TIM_CKD_DIV1 ((uint16_t)0x0000)
richardv	0:b079fa4ed182	331	#define TIM_CKD_DIV2 ((uint16_t)0x0100)
richardv	0:b079fa4ed182	332	#define TIM_CKD_DIV4 ((uint16_t)0x0200)
richardv	0:b079fa4ed182	333	#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) \|\| \
richardv	0:b079fa4ed182	334	((DIV) == TIM_CKD_DIV2) \|\| \
richardv	0:b079fa4ed182	335	((DIV) == TIM_CKD_DIV4))
richardv	0:b079fa4ed182	336	/**
richardv	0:b079fa4ed182	337	* @}
richardv	0:b079fa4ed182	338	*/
richardv	0:b079fa4ed182	339
richardv	0:b079fa4ed182	340	/** @defgroup TIM_Counter_Mode
richardv	0:b079fa4ed182	341	* @{
richardv	0:b079fa4ed182	342	*/
richardv	0:b079fa4ed182	343
richardv	0:b079fa4ed182	344	#define TIM_CounterMode_Up ((uint16_t)0x0000)
richardv	0:b079fa4ed182	345	#define TIM_CounterMode_Down ((uint16_t)0x0010)
richardv	0:b079fa4ed182	346	#define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)
richardv	0:b079fa4ed182	347	#define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)
richardv	0:b079fa4ed182	348	#define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)
richardv	0:b079fa4ed182	349	#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) \|\| \
richardv	0:b079fa4ed182	350	((MODE) == TIM_CounterMode_Down) \|\| \
richardv	0:b079fa4ed182	351	((MODE) == TIM_CounterMode_CenterAligned1) \|\| \
richardv	0:b079fa4ed182	352	((MODE) == TIM_CounterMode_CenterAligned2) \|\| \
richardv	0:b079fa4ed182	353	((MODE) == TIM_CounterMode_CenterAligned3))
richardv	0:b079fa4ed182	354	/**
richardv	0:b079fa4ed182	355	* @}
richardv	0:b079fa4ed182	356	*/
richardv	0:b079fa4ed182	357
richardv	0:b079fa4ed182	358	/** @defgroup TIM_Output_Compare_Polarity
richardv	0:b079fa4ed182	359	* @{
richardv	0:b079fa4ed182	360	*/
richardv	0:b079fa4ed182	361
richardv	0:b079fa4ed182	362	#define TIM_OCPolarity_High ((uint16_t)0x0000)
richardv	0:b079fa4ed182	363	#define TIM_OCPolarity_Low ((uint16_t)0x0002)
richardv	0:b079fa4ed182	364	#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) \|\| \
richardv	0:b079fa4ed182	365	((POLARITY) == TIM_OCPolarity_Low))
richardv	0:b079fa4ed182	366	/**
richardv	0:b079fa4ed182	367	* @}
richardv	0:b079fa4ed182	368	*/
richardv	0:b079fa4ed182	369
richardv	0:b079fa4ed182	370	/** @defgroup TIM_Output_Compare_N_Polarity
richardv	0:b079fa4ed182	371	* @{
richardv	0:b079fa4ed182	372	*/
richardv	0:b079fa4ed182	373
richardv	0:b079fa4ed182	374	#define TIM_OCNPolarity_High ((uint16_t)0x0000)
richardv	0:b079fa4ed182	375	#define TIM_OCNPolarity_Low ((uint16_t)0x0008)
richardv	0:b079fa4ed182	376	#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) \|\| \
richardv	0:b079fa4ed182	377	((POLARITY) == TIM_OCNPolarity_Low))
richardv	0:b079fa4ed182	378	/**
richardv	0:b079fa4ed182	379	* @}
richardv	0:b079fa4ed182	380	*/
richardv	0:b079fa4ed182	381
richardv	0:b079fa4ed182	382	/** @defgroup TIM_Output_Compare_State
richardv	0:b079fa4ed182	383	* @{
richardv	0:b079fa4ed182	384	*/
richardv	0:b079fa4ed182	385
richardv	0:b079fa4ed182	386	#define TIM_OutputState_Disable ((uint16_t)0x0000)
richardv	0:b079fa4ed182	387	#define TIM_OutputState_Enable ((uint16_t)0x0001)
richardv	0:b079fa4ed182	388	#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) \|\| \
richardv	0:b079fa4ed182	389	((STATE) == TIM_OutputState_Enable))
richardv	0:b079fa4ed182	390	/**
richardv	0:b079fa4ed182	391	* @}
richardv	0:b079fa4ed182	392	*/
richardv	0:b079fa4ed182	393
richardv	0:b079fa4ed182	394	/** @defgroup TIM_Output_Compare_N_State
richardv	0:b079fa4ed182	395	* @{
richardv	0:b079fa4ed182	396	*/
richardv	0:b079fa4ed182	397
richardv	0:b079fa4ed182	398	#define TIM_OutputNState_Disable ((uint16_t)0x0000)
richardv	0:b079fa4ed182	399	#define TIM_OutputNState_Enable ((uint16_t)0x0004)
richardv	0:b079fa4ed182	400	#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) \|\| \
richardv	0:b079fa4ed182	401	((STATE) == TIM_OutputNState_Enable))
richardv	0:b079fa4ed182	402	/**
richardv	0:b079fa4ed182	403	* @}
richardv	0:b079fa4ed182	404	*/
richardv	0:b079fa4ed182	405
richardv	0:b079fa4ed182	406	/** @defgroup TIM_Capture_Compare_State
richardv	0:b079fa4ed182	407	* @{
richardv	0:b079fa4ed182	408	*/
richardv	0:b079fa4ed182	409
richardv	0:b079fa4ed182	410	#define TIM_CCx_Enable ((uint16_t)0x0001)
richardv	0:b079fa4ed182	411	#define TIM_CCx_Disable ((uint16_t)0x0000)
richardv	0:b079fa4ed182	412	#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) \|\| \
richardv	0:b079fa4ed182	413	((CCX) == TIM_CCx_Disable))
richardv	0:b079fa4ed182	414	/**
richardv	0:b079fa4ed182	415	* @}
richardv	0:b079fa4ed182	416	*/
richardv	0:b079fa4ed182	417
richardv	0:b079fa4ed182	418	/** @defgroup TIM_Capture_Compare_N_State
richardv	0:b079fa4ed182	419	* @{
richardv	0:b079fa4ed182	420	*/
richardv	0:b079fa4ed182	421
richardv	0:b079fa4ed182	422	#define TIM_CCxN_Enable ((uint16_t)0x0004)
richardv	0:b079fa4ed182	423	#define TIM_CCxN_Disable ((uint16_t)0x0000)
richardv	0:b079fa4ed182	424	#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) \|\| \
richardv	0:b079fa4ed182	425	((CCXN) == TIM_CCxN_Disable))
richardv	0:b079fa4ed182	426	/**
richardv	0:b079fa4ed182	427	* @}
richardv	0:b079fa4ed182	428	*/
richardv	0:b079fa4ed182	429
richardv	0:b079fa4ed182	430	/** @defgroup TIM_Break_Input_enable_disable
richardv	0:b079fa4ed182	431	* @{
richardv	0:b079fa4ed182	432	*/
richardv	0:b079fa4ed182	433
richardv	0:b079fa4ed182	434	#define TIM_Break_Enable ((uint16_t)0x1000)
richardv	0:b079fa4ed182	435	#define TIM_Break_Disable ((uint16_t)0x0000)
richardv	0:b079fa4ed182	436	#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) \|\| \
richardv	0:b079fa4ed182	437	((STATE) == TIM_Break_Disable))
richardv	0:b079fa4ed182	438	/**
richardv	0:b079fa4ed182	439	* @}
richardv	0:b079fa4ed182	440	*/
richardv	0:b079fa4ed182	441
richardv	0:b079fa4ed182	442	/** @defgroup TIM_Break1_Input_enable_disable
richardv	0:b079fa4ed182	443	* @{
richardv	0:b079fa4ed182	444	*/
richardv	0:b079fa4ed182	445
richardv	0:b079fa4ed182	446	#define TIM_Break1_Enable ((uint32_t)0x00001000)
richardv	0:b079fa4ed182	447	#define TIM_Break1_Disable ((uint32_t)0x00000000)
richardv	0:b079fa4ed182	448	#define IS_TIM_BREAK1_STATE(STATE) (((STATE) == TIM_Break1_Enable) \|\| \
richardv	0:b079fa4ed182	449	((STATE) == TIM_Break1_Disable))
richardv	0:b079fa4ed182	450	/**
richardv	0:b079fa4ed182	451	* @}
richardv	0:b079fa4ed182	452	*/
richardv	0:b079fa4ed182	453
richardv	0:b079fa4ed182	454	/** @defgroup TIM_Break2_Input_enable_disable
richardv	0:b079fa4ed182	455	* @{
richardv	0:b079fa4ed182	456	*/
richardv	0:b079fa4ed182	457
richardv	0:b079fa4ed182	458	#define TIM_Break2_Enable ((uint32_t)0x01000000)
richardv	0:b079fa4ed182	459	#define TIM_Break2_Disable ((uint32_t)0x00000000)
richardv	0:b079fa4ed182	460	#define IS_TIM_BREAK2_STATE(STATE) (((STATE) == TIM_Break2_Enable) \|\| \
richardv	0:b079fa4ed182	461	((STATE) == TIM_Break2_Disable))
richardv	0:b079fa4ed182	462	/**
richardv	0:b079fa4ed182	463	* @}
richardv	0:b079fa4ed182	464	*/
richardv	0:b079fa4ed182	465
richardv	0:b079fa4ed182	466	/** @defgroup TIM_Break_Polarity
richardv	0:b079fa4ed182	467	* @{
richardv	0:b079fa4ed182	468	*/
richardv	0:b079fa4ed182	469
richardv	0:b079fa4ed182	470	#define TIM_BreakPolarity_Low ((uint16_t)0x0000)
richardv	0:b079fa4ed182	471	#define TIM_BreakPolarity_High ((uint16_t)0x2000)
richardv	0:b079fa4ed182	472	#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) \|\| \
richardv	0:b079fa4ed182	473	((POLARITY) == TIM_BreakPolarity_High))
richardv	0:b079fa4ed182	474	/**
richardv	0:b079fa4ed182	475	* @}
richardv	0:b079fa4ed182	476	*/
richardv	0:b079fa4ed182	477
richardv	0:b079fa4ed182	478	/** @defgroup TIM_Break1_Polarity
richardv	0:b079fa4ed182	479	* @{
richardv	0:b079fa4ed182	480	*/
richardv	0:b079fa4ed182	481
richardv	0:b079fa4ed182	482	#define TIM_Break1Polarity_Low ((uint32_t)0x00000000)
richardv	0:b079fa4ed182	483	#define TIM_Break1Polarity_High ((uint32_t)0x00002000)
richardv	0:b079fa4ed182	484	#define IS_TIM_BREAK1_POLARITY(POLARITY) (((POLARITY) == TIM_Break1Polarity_Low) \|\| \
richardv	0:b079fa4ed182	485	((POLARITY) == TIM_Break1Polarity_High))
richardv	0:b079fa4ed182	486	/**
richardv	0:b079fa4ed182	487	* @}
richardv	0:b079fa4ed182	488	*/
richardv	0:b079fa4ed182	489
richardv	0:b079fa4ed182	490	/** @defgroup TIM_Break2_Polarity
richardv	0:b079fa4ed182	491	* @{
richardv	0:b079fa4ed182	492	*/
richardv	0:b079fa4ed182	493
richardv	0:b079fa4ed182	494	#define TIM_Break2Polarity_Low ((uint32_t)0x00000000)
richardv	0:b079fa4ed182	495	#define TIM_Break2Polarity_High ((uint32_t)0x02000000)
richardv	0:b079fa4ed182	496	#define IS_TIM_BREAK2_POLARITY(POLARITY) (((POLARITY) == TIM_Break2Polarity_Low) \|\| \
richardv	0:b079fa4ed182	497	((POLARITY) == TIM_Break2Polarity_High))
richardv	0:b079fa4ed182	498	/**
richardv	0:b079fa4ed182	499	* @}
richardv	0:b079fa4ed182	500	*/
richardv	0:b079fa4ed182	501
richardv	0:b079fa4ed182	502	/** @defgroup TIM_Break1_Filter
richardv	0:b079fa4ed182	503	* @{
richardv	0:b079fa4ed182	504	*/
richardv	0:b079fa4ed182	505
richardv	0:b079fa4ed182	506	#define IS_TIM_BREAK1_FILTER(FILTER) ((FILTER) <= 0xF)
richardv	0:b079fa4ed182	507	/**
richardv	0:b079fa4ed182	508	* @}
richardv	0:b079fa4ed182	509	*/
richardv	0:b079fa4ed182	510
richardv	0:b079fa4ed182	511	/** @defgroup TIM_Break2_Filter
richardv	0:b079fa4ed182	512	* @{
richardv	0:b079fa4ed182	513	*/
richardv	0:b079fa4ed182	514
richardv	0:b079fa4ed182	515	#define IS_TIM_BREAK2_FILTER(FILTER) ((FILTER) <= 0xF)
richardv	0:b079fa4ed182	516	/**
richardv	0:b079fa4ed182	517	* @}
richardv	0:b079fa4ed182	518	*/
richardv	0:b079fa4ed182	519
richardv	0:b079fa4ed182	520	/** @defgroup TIM_AOE_Bit_Set_Reset
richardv	0:b079fa4ed182	521	* @{
richardv	0:b079fa4ed182	522	*/
richardv	0:b079fa4ed182	523
richardv	0:b079fa4ed182	524	#define TIM_AutomaticOutput_Enable ((uint16_t)0x4000)
richardv	0:b079fa4ed182	525	#define TIM_AutomaticOutput_Disable ((uint16_t)0x0000)
richardv	0:b079fa4ed182	526	#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) \|\| \
richardv	0:b079fa4ed182	527	((STATE) == TIM_AutomaticOutput_Disable))
richardv	0:b079fa4ed182	528	/**
richardv	0:b079fa4ed182	529	* @}
richardv	0:b079fa4ed182	530	*/
richardv	0:b079fa4ed182	531
richardv	0:b079fa4ed182	532	/** @defgroup TIM_Lock_level
richardv	0:b079fa4ed182	533	* @{
richardv	0:b079fa4ed182	534	*/
richardv	0:b079fa4ed182	535
richardv	0:b079fa4ed182	536	#define TIM_LOCKLevel_OFF ((uint16_t)0x0000)
richardv	0:b079fa4ed182	537	#define TIM_LOCKLevel_1 ((uint16_t)0x0100)
richardv	0:b079fa4ed182	538	#define TIM_LOCKLevel_2 ((uint16_t)0x0200)
richardv	0:b079fa4ed182	539	#define TIM_LOCKLevel_3 ((uint16_t)0x0300)
richardv	0:b079fa4ed182	540	#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) \|\| \
richardv	0:b079fa4ed182	541	((LEVEL) == TIM_LOCKLevel_1) \|\| \
richardv	0:b079fa4ed182	542	((LEVEL) == TIM_LOCKLevel_2) \|\| \
richardv	0:b079fa4ed182	543	((LEVEL) == TIM_LOCKLevel_3))
richardv	0:b079fa4ed182	544	/**
richardv	0:b079fa4ed182	545	* @}
richardv	0:b079fa4ed182	546	*/
richardv	0:b079fa4ed182	547
richardv	0:b079fa4ed182	548	/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state
richardv	0:b079fa4ed182	549	* @{
richardv	0:b079fa4ed182	550	*/
richardv	0:b079fa4ed182	551
richardv	0:b079fa4ed182	552	#define TIM_OSSIState_Enable ((uint16_t)0x0400)
richardv	0:b079fa4ed182	553	#define TIM_OSSIState_Disable ((uint16_t)0x0000)
richardv	0:b079fa4ed182	554	#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) \|\| \
richardv	0:b079fa4ed182	555	((STATE) == TIM_OSSIState_Disable))
richardv	0:b079fa4ed182	556	/**
richardv	0:b079fa4ed182	557	* @}
richardv	0:b079fa4ed182	558	*/
richardv	0:b079fa4ed182	559
richardv	0:b079fa4ed182	560	/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state
richardv	0:b079fa4ed182	561	* @{
richardv	0:b079fa4ed182	562	*/
richardv	0:b079fa4ed182	563
richardv	0:b079fa4ed182	564	#define TIM_OSSRState_Enable ((uint16_t)0x0800)
richardv	0:b079fa4ed182	565	#define TIM_OSSRState_Disable ((uint16_t)0x0000)
richardv	0:b079fa4ed182	566	#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) \|\| \
richardv	0:b079fa4ed182	567	((STATE) == TIM_OSSRState_Disable))
richardv	0:b079fa4ed182	568	/**
richardv	0:b079fa4ed182	569	* @}
richardv	0:b079fa4ed182	570	*/
richardv	0:b079fa4ed182	571
richardv	0:b079fa4ed182	572	/** @defgroup TIM_Output_Compare_Idle_State
richardv	0:b079fa4ed182	573	* @{
richardv	0:b079fa4ed182	574	*/
richardv	0:b079fa4ed182	575
richardv	0:b079fa4ed182	576	#define TIM_OCIdleState_Set ((uint16_t)0x0100)
richardv	0:b079fa4ed182	577	#define TIM_OCIdleState_Reset ((uint16_t)0x0000)
richardv	0:b079fa4ed182	578	#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) \|\| \
richardv	0:b079fa4ed182	579	((STATE) == TIM_OCIdleState_Reset))
richardv	0:b079fa4ed182	580	/**
richardv	0:b079fa4ed182	581	* @}
richardv	0:b079fa4ed182	582	*/
richardv	0:b079fa4ed182	583
richardv	0:b079fa4ed182	584	/** @defgroup TIM_Output_Compare_N_Idle_State
richardv	0:b079fa4ed182	585	* @{
richardv	0:b079fa4ed182	586	*/
richardv	0:b079fa4ed182	587
richardv	0:b079fa4ed182	588	#define TIM_OCNIdleState_Set ((uint16_t)0x0200)
richardv	0:b079fa4ed182	589	#define TIM_OCNIdleState_Reset ((uint16_t)0x0000)
richardv	0:b079fa4ed182	590	#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) \|\| \
richardv	0:b079fa4ed182	591	((STATE) == TIM_OCNIdleState_Reset))
richardv	0:b079fa4ed182	592	/**
richardv	0:b079fa4ed182	593	* @}
richardv	0:b079fa4ed182	594	*/
richardv	0:b079fa4ed182	595
richardv	0:b079fa4ed182	596	/** @defgroup TIM_Input_Capture_Polarity
richardv	0:b079fa4ed182	597	* @{
richardv	0:b079fa4ed182	598	*/
richardv	0:b079fa4ed182	599
richardv	0:b079fa4ed182	600	#define TIM_ICPolarity_Rising ((uint16_t)0x0000)
richardv	0:b079fa4ed182	601	#define TIM_ICPolarity_Falling ((uint16_t)0x0002)
richardv	0:b079fa4ed182	602	#define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)
richardv	0:b079fa4ed182	603	#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) \|\| \
richardv	0:b079fa4ed182	604	((POLARITY) == TIM_ICPolarity_Falling)\|\| \
richardv	0:b079fa4ed182	605	((POLARITY) == TIM_ICPolarity_BothEdge))
richardv	0:b079fa4ed182	606	/**
richardv	0:b079fa4ed182	607	* @}
richardv	0:b079fa4ed182	608	*/
richardv	0:b079fa4ed182	609
richardv	0:b079fa4ed182	610	/** @defgroup TIM_Input_Capture_Selection
richardv	0:b079fa4ed182	611	* @{
richardv	0:b079fa4ed182	612	*/
richardv	0:b079fa4ed182	613
richardv	0:b079fa4ed182	614	#define TIM_ICSelection_DirectTI ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be
richardv	0:b079fa4ed182	615	connected to IC1, IC2, IC3 or IC4, respectively */
richardv	0:b079fa4ed182	616	#define TIM_ICSelection_IndirectTI ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be
richardv	0:b079fa4ed182	617	connected to IC2, IC1, IC4 or IC3, respectively. */
richardv	0:b079fa4ed182	618	#define TIM_ICSelection_TRC ((uint16_t)0x0003) /!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. /
richardv	0:b079fa4ed182	619	#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) \|\| \
richardv	0:b079fa4ed182	620	((SELECTION) == TIM_ICSelection_IndirectTI) \|\| \
richardv	0:b079fa4ed182	621	((SELECTION) == TIM_ICSelection_TRC))
richardv	0:b079fa4ed182	622	/**
richardv	0:b079fa4ed182	623	* @}
richardv	0:b079fa4ed182	624	*/
richardv	0:b079fa4ed182	625
richardv	0:b079fa4ed182	626	/** @defgroup TIM_Input_Capture_Prescaler
richardv	0:b079fa4ed182	627	* @{
richardv	0:b079fa4ed182	628	*/
richardv	0:b079fa4ed182	629
richardv	0:b079fa4ed182	630	#define TIM_ICPSC_DIV1 ((uint16_t)0x0000) /!< Capture performed each time an edge is detected on the capture input. /
richardv	0:b079fa4ed182	631	#define TIM_ICPSC_DIV2 ((uint16_t)0x0004) /!< Capture performed once every 2 events. /
richardv	0:b079fa4ed182	632	#define TIM_ICPSC_DIV4 ((uint16_t)0x0008) /!< Capture performed once every 4 events. /
richardv	0:b079fa4ed182	633	#define TIM_ICPSC_DIV8 ((uint16_t)0x000C) /!< Capture performed once every 8 events. /
richardv	0:b079fa4ed182	634	#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) \|\| \
richardv	0:b079fa4ed182	635	((PRESCALER) == TIM_ICPSC_DIV2) \|\| \
richardv	0:b079fa4ed182	636	((PRESCALER) == TIM_ICPSC_DIV4) \|\| \
richardv	0:b079fa4ed182	637	((PRESCALER) == TIM_ICPSC_DIV8))
richardv	0:b079fa4ed182	638	/**
richardv	0:b079fa4ed182	639	* @}
richardv	0:b079fa4ed182	640	*/
richardv	0:b079fa4ed182	641
richardv	0:b079fa4ed182	642	/** @defgroup TIM_interrupt_sources
richardv	0:b079fa4ed182	643	* @{
richardv	0:b079fa4ed182	644	*/
richardv	0:b079fa4ed182	645
richardv	0:b079fa4ed182	646	#define TIM_IT_Update ((uint16_t)0x0001)
richardv	0:b079fa4ed182	647	#define TIM_IT_CC1 ((uint16_t)0x0002)
richardv	0:b079fa4ed182	648	#define TIM_IT_CC2 ((uint16_t)0x0004)
richardv	0:b079fa4ed182	649	#define TIM_IT_CC3 ((uint16_t)0x0008)
richardv	0:b079fa4ed182	650	#define TIM_IT_CC4 ((uint16_t)0x0010)
richardv	0:b079fa4ed182	651	#define TIM_IT_COM ((uint16_t)0x0020)
richardv	0:b079fa4ed182	652	#define TIM_IT_Trigger ((uint16_t)0x0040)
richardv	0:b079fa4ed182	653	#define TIM_IT_Break ((uint16_t)0x0080)
richardv	0:b079fa4ed182	654	#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
richardv	0:b079fa4ed182	655
richardv	0:b079fa4ed182	656	#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) \|\| \
richardv	0:b079fa4ed182	657	((IT) == TIM_IT_CC1) \|\| \
richardv	0:b079fa4ed182	658	((IT) == TIM_IT_CC2) \|\| \
richardv	0:b079fa4ed182	659	((IT) == TIM_IT_CC3) \|\| \
richardv	0:b079fa4ed182	660	((IT) == TIM_IT_CC4) \|\| \
richardv	0:b079fa4ed182	661	((IT) == TIM_IT_COM) \|\| \
richardv	0:b079fa4ed182	662	((IT) == TIM_IT_Trigger) \|\| \
richardv	0:b079fa4ed182	663	((IT) == TIM_IT_Break))
richardv	0:b079fa4ed182	664	/**
richardv	0:b079fa4ed182	665	* @}
richardv	0:b079fa4ed182	666	*/
richardv	0:b079fa4ed182	667
richardv	0:b079fa4ed182	668	/** @defgroup TIM_DMA_Base_address
richardv	0:b079fa4ed182	669	* @{
richardv	0:b079fa4ed182	670	*/
richardv	0:b079fa4ed182	671
richardv	0:b079fa4ed182	672	#define TIM_DMABase_CR1 ((uint16_t)0x0000)
richardv	0:b079fa4ed182	673	#define TIM_DMABase_CR2 ((uint16_t)0x0001)
richardv	0:b079fa4ed182	674	#define TIM_DMABase_SMCR ((uint16_t)0x0002)
richardv	0:b079fa4ed182	675	#define TIM_DMABase_DIER ((uint16_t)0x0003)
richardv	0:b079fa4ed182	676	#define TIM_DMABase_SR ((uint16_t)0x0004)
richardv	0:b079fa4ed182	677	#define TIM_DMABase_EGR ((uint16_t)0x0005)
richardv	0:b079fa4ed182	678	#define TIM_DMABase_CCMR1 ((uint16_t)0x0006)
richardv	0:b079fa4ed182	679	#define TIM_DMABase_CCMR2 ((uint16_t)0x0007)
richardv	0:b079fa4ed182	680	#define TIM_DMABase_CCER ((uint16_t)0x0008)
richardv	0:b079fa4ed182	681	#define TIM_DMABase_CNT ((uint16_t)0x0009)
richardv	0:b079fa4ed182	682	#define TIM_DMABase_PSC ((uint16_t)0x000A)
richardv	0:b079fa4ed182	683	#define TIM_DMABase_ARR ((uint16_t)0x000B)
richardv	0:b079fa4ed182	684	#define TIM_DMABase_RCR ((uint16_t)0x000C)
richardv	0:b079fa4ed182	685	#define TIM_DMABase_CCR1 ((uint16_t)0x000D)
richardv	0:b079fa4ed182	686	#define TIM_DMABase_CCR2 ((uint16_t)0x000E)
richardv	0:b079fa4ed182	687	#define TIM_DMABase_CCR3 ((uint16_t)0x000F)
richardv	0:b079fa4ed182	688	#define TIM_DMABase_CCR4 ((uint16_t)0x0010)
richardv	0:b079fa4ed182	689	#define TIM_DMABase_BDTR ((uint16_t)0x0011)
richardv	0:b079fa4ed182	690	#define TIM_DMABase_DCR ((uint16_t)0x0012)
richardv	0:b079fa4ed182	691	#define TIM_DMABase_OR ((uint16_t)0x0013)
richardv	0:b079fa4ed182	692	#define TIM_DMABase_CCMR3 ((uint16_t)0x0014)
richardv	0:b079fa4ed182	693	#define TIM_DMABase_CCR5 ((uint16_t)0x0015)
richardv	0:b079fa4ed182	694	#define TIM_DMABase_CCR6 ((uint16_t)0x0016)
richardv	0:b079fa4ed182	695	#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) \|\| \
richardv	0:b079fa4ed182	696	((BASE) == TIM_DMABase_CR2) \|\| \
richardv	0:b079fa4ed182	697	((BASE) == TIM_DMABase_SMCR) \|\| \
richardv	0:b079fa4ed182	698	((BASE) == TIM_DMABase_DIER) \|\| \
richardv	0:b079fa4ed182	699	((BASE) == TIM_DMABase_SR) \|\| \
richardv	0:b079fa4ed182	700	((BASE) == TIM_DMABase_EGR) \|\| \
richardv	0:b079fa4ed182	701	((BASE) == TIM_DMABase_CCMR1) \|\| \
richardv	0:b079fa4ed182	702	((BASE) == TIM_DMABase_CCMR2) \|\| \
richardv	0:b079fa4ed182	703	((BASE) == TIM_DMABase_CCER) \|\| \
richardv	0:b079fa4ed182	704	((BASE) == TIM_DMABase_CNT) \|\| \
richardv	0:b079fa4ed182	705	((BASE) == TIM_DMABase_PSC) \|\| \
richardv	0:b079fa4ed182	706	((BASE) == TIM_DMABase_ARR) \|\| \
richardv	0:b079fa4ed182	707	((BASE) == TIM_DMABase_RCR) \|\| \
richardv	0:b079fa4ed182	708	((BASE) == TIM_DMABase_CCR1) \|\| \
richardv	0:b079fa4ed182	709	((BASE) == TIM_DMABase_CCR2) \|\| \
richardv	0:b079fa4ed182	710	((BASE) == TIM_DMABase_CCR3) \|\| \
richardv	0:b079fa4ed182	711	((BASE) == TIM_DMABase_CCR4) \|\| \
richardv	0:b079fa4ed182	712	((BASE) == TIM_DMABase_BDTR) \|\| \
richardv	0:b079fa4ed182	713	((BASE) == TIM_DMABase_DCR) \|\| \
richardv	0:b079fa4ed182	714	((BASE) == TIM_DMABase_OR) \|\| \
richardv	0:b079fa4ed182	715	((BASE) == TIM_DMABase_CCMR3) \|\| \
richardv	0:b079fa4ed182	716	((BASE) == TIM_DMABase_CCR5) \|\| \
richardv	0:b079fa4ed182	717	((BASE) == TIM_DMABase_CCR6))
richardv	0:b079fa4ed182	718	/**
richardv	0:b079fa4ed182	719	* @}
richardv	0:b079fa4ed182	720	*/
richardv	0:b079fa4ed182	721
richardv	0:b079fa4ed182	722	/** @defgroup TIM_DMA_Burst_Length
richardv	0:b079fa4ed182	723	* @{
richardv	0:b079fa4ed182	724	*/
richardv	0:b079fa4ed182	725
richardv	0:b079fa4ed182	726	#define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000)
richardv	0:b079fa4ed182	727	#define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100)
richardv	0:b079fa4ed182	728	#define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200)
richardv	0:b079fa4ed182	729	#define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300)
richardv	0:b079fa4ed182	730	#define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400)
richardv	0:b079fa4ed182	731	#define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500)
richardv	0:b079fa4ed182	732	#define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600)
richardv	0:b079fa4ed182	733	#define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700)
richardv	0:b079fa4ed182	734	#define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800)
richardv	0:b079fa4ed182	735	#define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900)
richardv	0:b079fa4ed182	736	#define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00)
richardv	0:b079fa4ed182	737	#define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00)
richardv	0:b079fa4ed182	738	#define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00)
richardv	0:b079fa4ed182	739	#define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00)
richardv	0:b079fa4ed182	740	#define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00)
richardv	0:b079fa4ed182	741	#define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00)
richardv	0:b079fa4ed182	742	#define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000)
richardv	0:b079fa4ed182	743	#define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100)
richardv	0:b079fa4ed182	744	#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) \|\| \
richardv	0:b079fa4ed182	745	((LENGTH) == TIM_DMABurstLength_2Transfers) \|\| \
richardv	0:b079fa4ed182	746	((LENGTH) == TIM_DMABurstLength_3Transfers) \|\| \
richardv	0:b079fa4ed182	747	((LENGTH) == TIM_DMABurstLength_4Transfers) \|\| \
richardv	0:b079fa4ed182	748	((LENGTH) == TIM_DMABurstLength_5Transfers) \|\| \
richardv	0:b079fa4ed182	749	((LENGTH) == TIM_DMABurstLength_6Transfers) \|\| \
richardv	0:b079fa4ed182	750	((LENGTH) == TIM_DMABurstLength_7Transfers) \|\| \
richardv	0:b079fa4ed182	751	((LENGTH) == TIM_DMABurstLength_8Transfers) \|\| \
richardv	0:b079fa4ed182	752	((LENGTH) == TIM_DMABurstLength_9Transfers) \|\| \
richardv	0:b079fa4ed182	753	((LENGTH) == TIM_DMABurstLength_10Transfers) \|\| \
richardv	0:b079fa4ed182	754	((LENGTH) == TIM_DMABurstLength_11Transfers) \|\| \
richardv	0:b079fa4ed182	755	((LENGTH) == TIM_DMABurstLength_12Transfers) \|\| \
richardv	0:b079fa4ed182	756	((LENGTH) == TIM_DMABurstLength_13Transfers) \|\| \
richardv	0:b079fa4ed182	757	((LENGTH) == TIM_DMABurstLength_14Transfers) \|\| \
richardv	0:b079fa4ed182	758	((LENGTH) == TIM_DMABurstLength_15Transfers) \|\| \
richardv	0:b079fa4ed182	759	((LENGTH) == TIM_DMABurstLength_16Transfers) \|\| \
richardv	0:b079fa4ed182	760	((LENGTH) == TIM_DMABurstLength_17Transfers) \|\| \
richardv	0:b079fa4ed182	761	((LENGTH) == TIM_DMABurstLength_18Transfers))
richardv	0:b079fa4ed182	762	/**
richardv	0:b079fa4ed182	763	* @}
richardv	0:b079fa4ed182	764	*/
richardv	0:b079fa4ed182	765
richardv	0:b079fa4ed182	766	/** @defgroup TIM_DMA_sources
richardv	0:b079fa4ed182	767	* @{
richardv	0:b079fa4ed182	768	*/
richardv	0:b079fa4ed182	769
richardv	0:b079fa4ed182	770	#define TIM_DMA_Update ((uint16_t)0x0100)
richardv	0:b079fa4ed182	771	#define TIM_DMA_CC1 ((uint16_t)0x0200)
richardv	0:b079fa4ed182	772	#define TIM_DMA_CC2 ((uint16_t)0x0400)
richardv	0:b079fa4ed182	773	#define TIM_DMA_CC3 ((uint16_t)0x0800)
richardv	0:b079fa4ed182	774	#define TIM_DMA_CC4 ((uint16_t)0x1000)
richardv	0:b079fa4ed182	775	#define TIM_DMA_COM ((uint16_t)0x2000)
richardv	0:b079fa4ed182	776	#define TIM_DMA_Trigger ((uint16_t)0x4000)
richardv	0:b079fa4ed182	777	#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
richardv	0:b079fa4ed182	778
richardv	0:b079fa4ed182	779	/**
richardv	0:b079fa4ed182	780	* @}
richardv	0:b079fa4ed182	781	*/
richardv	0:b079fa4ed182	782
richardv	0:b079fa4ed182	783	/** @defgroup TIM_External_Trigger_Prescaler
richardv	0:b079fa4ed182	784	* @{
richardv	0:b079fa4ed182	785	*/
richardv	0:b079fa4ed182	786
richardv	0:b079fa4ed182	787	#define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)
richardv	0:b079fa4ed182	788	#define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)
richardv	0:b079fa4ed182	789	#define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)
richardv	0:b079fa4ed182	790	#define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)
richardv	0:b079fa4ed182	791	#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) \|\| \
richardv	0:b079fa4ed182	792	((PRESCALER) == TIM_ExtTRGPSC_DIV2) \|\| \
richardv	0:b079fa4ed182	793	((PRESCALER) == TIM_ExtTRGPSC_DIV4) \|\| \
richardv	0:b079fa4ed182	794	((PRESCALER) == TIM_ExtTRGPSC_DIV8))
richardv	0:b079fa4ed182	795	/**
richardv	0:b079fa4ed182	796	* @}
richardv	0:b079fa4ed182	797	*/
richardv	0:b079fa4ed182	798
richardv	0:b079fa4ed182	799	/** @defgroup TIM_Internal_Trigger_Selection
richardv	0:b079fa4ed182	800	* @{
richardv	0:b079fa4ed182	801	*/
richardv	0:b079fa4ed182	802
richardv	0:b079fa4ed182	803	#define TIM_TS_ITR0 ((uint16_t)0x0000)
richardv	0:b079fa4ed182	804	#define TIM_TS_ITR1 ((uint16_t)0x0010)
richardv	0:b079fa4ed182	805	#define TIM_TS_ITR2 ((uint16_t)0x0020)
richardv	0:b079fa4ed182	806	#define TIM_TS_ITR3 ((uint16_t)0x0030)
richardv	0:b079fa4ed182	807	#define TIM_TS_TI1F_ED ((uint16_t)0x0040)
richardv	0:b079fa4ed182	808	#define TIM_TS_TI1FP1 ((uint16_t)0x0050)
richardv	0:b079fa4ed182	809	#define TIM_TS_TI2FP2 ((uint16_t)0x0060)
richardv	0:b079fa4ed182	810	#define TIM_TS_ETRF ((uint16_t)0x0070)
richardv	0:b079fa4ed182	811	#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
richardv	0:b079fa4ed182	812	((SELECTION) == TIM_TS_ITR1) \|\| \
richardv	0:b079fa4ed182	813	((SELECTION) == TIM_TS_ITR2) \|\| \
richardv	0:b079fa4ed182	814	((SELECTION) == TIM_TS_ITR3) \|\| \
richardv	0:b079fa4ed182	815	((SELECTION) == TIM_TS_TI1F_ED) \|\| \
richardv	0:b079fa4ed182	816	((SELECTION) == TIM_TS_TI1FP1) \|\| \
richardv	0:b079fa4ed182	817	((SELECTION) == TIM_TS_TI2FP2) \|\| \
richardv	0:b079fa4ed182	818	((SELECTION) == TIM_TS_ETRF))
richardv	0:b079fa4ed182	819	#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) \|\| \
richardv	0:b079fa4ed182	820	((SELECTION) == TIM_TS_ITR1) \|\| \
richardv	0:b079fa4ed182	821	((SELECTION) == TIM_TS_ITR2) \|\| \
richardv	0:b079fa4ed182	822	((SELECTION) == TIM_TS_ITR3))
richardv	0:b079fa4ed182	823	/**
richardv	0:b079fa4ed182	824	* @}
richardv	0:b079fa4ed182	825	*/
richardv	0:b079fa4ed182	826
richardv	0:b079fa4ed182	827	/** @defgroup TIM_TIx_External_Clock_Source
richardv	0:b079fa4ed182	828	* @{
richardv	0:b079fa4ed182	829	*/
richardv	0:b079fa4ed182	830
richardv	0:b079fa4ed182	831	#define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)
richardv	0:b079fa4ed182	832	#define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)
richardv	0:b079fa4ed182	833	#define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)
richardv	0:b079fa4ed182	834
richardv	0:b079fa4ed182	835	/**
richardv	0:b079fa4ed182	836	* @}
richardv	0:b079fa4ed182	837	*/
richardv	0:b079fa4ed182	838
richardv	0:b079fa4ed182	839	/** @defgroup TIM_External_Trigger_Polarity
richardv	0:b079fa4ed182	840	* @{
richardv	0:b079fa4ed182	841	*/
richardv	0:b079fa4ed182	842	#define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)
richardv	0:b079fa4ed182	843	#define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)
richardv	0:b079fa4ed182	844	#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) \|\| \
richardv	0:b079fa4ed182	845	((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
richardv	0:b079fa4ed182	846	/**
richardv	0:b079fa4ed182	847	* @}
richardv	0:b079fa4ed182	848	*/
richardv	0:b079fa4ed182	849
richardv	0:b079fa4ed182	850	/** @defgroup TIM_Prescaler_Reload_Mode
richardv	0:b079fa4ed182	851	* @{
richardv	0:b079fa4ed182	852	*/
richardv	0:b079fa4ed182	853
richardv	0:b079fa4ed182	854	#define TIM_PSCReloadMode_Update ((uint16_t)0x0000)
richardv	0:b079fa4ed182	855	#define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)
richardv	0:b079fa4ed182	856	#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) \|\| \
richardv	0:b079fa4ed182	857	((RELOAD) == TIM_PSCReloadMode_Immediate))
richardv	0:b079fa4ed182	858	/**
richardv	0:b079fa4ed182	859	* @}
richardv	0:b079fa4ed182	860	*/
richardv	0:b079fa4ed182	861
richardv	0:b079fa4ed182	862	/** @defgroup TIM_Forced_Action
richardv	0:b079fa4ed182	863	* @{
richardv	0:b079fa4ed182	864	*/
richardv	0:b079fa4ed182	865
richardv	0:b079fa4ed182	866	#define TIM_ForcedAction_Active ((uint16_t)0x0050)
richardv	0:b079fa4ed182	867	#define TIM_ForcedAction_InActive ((uint16_t)0x0040)
richardv	0:b079fa4ed182	868	#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) \|\| \
richardv	0:b079fa4ed182	869	((ACTION) == TIM_ForcedAction_InActive))
richardv	0:b079fa4ed182	870	/**
richardv	0:b079fa4ed182	871	* @}
richardv	0:b079fa4ed182	872	*/
richardv	0:b079fa4ed182	873
richardv	0:b079fa4ed182	874	/** @defgroup TIM_Encoder_Mode
richardv	0:b079fa4ed182	875	* @{
richardv	0:b079fa4ed182	876	*/
richardv	0:b079fa4ed182	877
richardv	0:b079fa4ed182	878	#define TIM_EncoderMode_TI1 ((uint16_t)0x0001)
richardv	0:b079fa4ed182	879	#define TIM_EncoderMode_TI2 ((uint16_t)0x0002)
richardv	0:b079fa4ed182	880	#define TIM_EncoderMode_TI12 ((uint16_t)0x0003)
richardv	0:b079fa4ed182	881	#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) \|\| \
richardv	0:b079fa4ed182	882	((MODE) == TIM_EncoderMode_TI2) \|\| \
richardv	0:b079fa4ed182	883	((MODE) == TIM_EncoderMode_TI12))
richardv	0:b079fa4ed182	884	/**
richardv	0:b079fa4ed182	885	* @}
richardv	0:b079fa4ed182	886	*/
richardv	0:b079fa4ed182	887
richardv	0:b079fa4ed182	888
richardv	0:b079fa4ed182	889	/** @defgroup TIM_Event_Source
richardv	0:b079fa4ed182	890	* @{
richardv	0:b079fa4ed182	891	*/
richardv	0:b079fa4ed182	892
richardv	0:b079fa4ed182	893	#define TIM_EventSource_Update ((uint16_t)0x0001)
richardv	0:b079fa4ed182	894	#define TIM_EventSource_CC1 ((uint16_t)0x0002)
richardv	0:b079fa4ed182	895	#define TIM_EventSource_CC2 ((uint16_t)0x0004)
richardv	0:b079fa4ed182	896	#define TIM_EventSource_CC3 ((uint16_t)0x0008)
richardv	0:b079fa4ed182	897	#define TIM_EventSource_CC4 ((uint16_t)0x0010)
richardv	0:b079fa4ed182	898	#define TIM_EventSource_COM ((uint16_t)0x0020)
richardv	0:b079fa4ed182	899	#define TIM_EventSource_Trigger ((uint16_t)0x0040)
richardv	0:b079fa4ed182	900	#define TIM_EventSource_Break ((uint16_t)0x0080)
richardv	0:b079fa4ed182	901	#define TIM_EventSource_Break2 ((uint16_t)0x0100)
richardv	0:b079fa4ed182	902	#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFE00) == 0x0000) && ((SOURCE) != 0x0000))
richardv	0:b079fa4ed182	903
richardv	0:b079fa4ed182	904	/**
richardv	0:b079fa4ed182	905	* @}
richardv	0:b079fa4ed182	906	*/
richardv	0:b079fa4ed182	907
richardv	0:b079fa4ed182	908	/** @defgroup TIM_Update_Source
richardv	0:b079fa4ed182	909	* @{
richardv	0:b079fa4ed182	910	*/
richardv	0:b079fa4ed182	911
richardv	0:b079fa4ed182	912	#define TIM_UpdateSource_Global ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow
richardv	0:b079fa4ed182	913	or the setting of UG bit, or an update generation
richardv	0:b079fa4ed182	914	through the slave mode controller. */
richardv	0:b079fa4ed182	915	#define TIM_UpdateSource_Regular ((uint16_t)0x0001) /!< Source of update is counter overflow/underflow. /
richardv	0:b079fa4ed182	916	#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) \|\| \
richardv	0:b079fa4ed182	917	((SOURCE) == TIM_UpdateSource_Regular))
richardv	0:b079fa4ed182	918	/**
richardv	0:b079fa4ed182	919	* @}
richardv	0:b079fa4ed182	920	*/
richardv	0:b079fa4ed182	921
richardv	0:b079fa4ed182	922	/** @defgroup TIM_Output_Compare_Preload_State
richardv	0:b079fa4ed182	923	* @{
richardv	0:b079fa4ed182	924	*/
richardv	0:b079fa4ed182	925
richardv	0:b079fa4ed182	926	#define TIM_OCPreload_Enable ((uint16_t)0x0008)
richardv	0:b079fa4ed182	927	#define TIM_OCPreload_Disable ((uint16_t)0x0000)
richardv	0:b079fa4ed182	928	#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) \|\| \
richardv	0:b079fa4ed182	929	((STATE) == TIM_OCPreload_Disable))
richardv	0:b079fa4ed182	930	/**
richardv	0:b079fa4ed182	931	* @}
richardv	0:b079fa4ed182	932	*/
richardv	0:b079fa4ed182	933
richardv	0:b079fa4ed182	934	/** @defgroup TIM_Output_Compare_Fast_State
richardv	0:b079fa4ed182	935	* @{
richardv	0:b079fa4ed182	936	*/
richardv	0:b079fa4ed182	937
richardv	0:b079fa4ed182	938	#define TIM_OCFast_Enable ((uint16_t)0x0004)
richardv	0:b079fa4ed182	939	#define TIM_OCFast_Disable ((uint16_t)0x0000)
richardv	0:b079fa4ed182	940	#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) \|\| \
richardv	0:b079fa4ed182	941	((STATE) == TIM_OCFast_Disable))
richardv	0:b079fa4ed182	942
richardv	0:b079fa4ed182	943	/**
richardv	0:b079fa4ed182	944	* @}
richardv	0:b079fa4ed182	945	*/
richardv	0:b079fa4ed182	946
richardv	0:b079fa4ed182	947	/** @defgroup TIM_Output_Compare_Clear_State
richardv	0:b079fa4ed182	948	* @{
richardv	0:b079fa4ed182	949	*/
richardv	0:b079fa4ed182	950
richardv	0:b079fa4ed182	951	#define TIM_OCClear_Enable ((uint16_t)0x0080)
richardv	0:b079fa4ed182	952	#define TIM_OCClear_Disable ((uint16_t)0x0000)
richardv	0:b079fa4ed182	953	#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) \|\| \
richardv	0:b079fa4ed182	954	((STATE) == TIM_OCClear_Disable))
richardv	0:b079fa4ed182	955	/**
richardv	0:b079fa4ed182	956	* @}
richardv	0:b079fa4ed182	957	*/
richardv	0:b079fa4ed182	958
richardv	0:b079fa4ed182	959	/** @defgroup TIM_Trigger_Output_Source
richardv	0:b079fa4ed182	960	* @{
richardv	0:b079fa4ed182	961	*/
richardv	0:b079fa4ed182	962
richardv	0:b079fa4ed182	963	#define TIM_TRGOSource_Reset ((uint16_t)0x0000)
richardv	0:b079fa4ed182	964	#define TIM_TRGOSource_Enable ((uint16_t)0x0010)
richardv	0:b079fa4ed182	965	#define TIM_TRGOSource_Update ((uint16_t)0x0020)
richardv	0:b079fa4ed182	966	#define TIM_TRGOSource_OC1 ((uint16_t)0x0030)
richardv	0:b079fa4ed182	967	#define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)
richardv	0:b079fa4ed182	968	#define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)
richardv	0:b079fa4ed182	969	#define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)
richardv	0:b079fa4ed182	970	#define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)
richardv	0:b079fa4ed182	971	#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) \|\| \
richardv	0:b079fa4ed182	972	((SOURCE) == TIM_TRGOSource_Enable) \|\| \
richardv	0:b079fa4ed182	973	((SOURCE) == TIM_TRGOSource_Update) \|\| \
richardv	0:b079fa4ed182	974	((SOURCE) == TIM_TRGOSource_OC1) \|\| \
richardv	0:b079fa4ed182	975	((SOURCE) == TIM_TRGOSource_OC1Ref) \|\| \
richardv	0:b079fa4ed182	976	((SOURCE) == TIM_TRGOSource_OC2Ref) \|\| \
richardv	0:b079fa4ed182	977	((SOURCE) == TIM_TRGOSource_OC3Ref) \|\| \
richardv	0:b079fa4ed182	978	((SOURCE) == TIM_TRGOSource_OC4Ref))
richardv	0:b079fa4ed182	979
richardv	0:b079fa4ed182	980
richardv	0:b079fa4ed182	981	#define TIM_TRGO2Source_Reset ((uint32_t)0x00000000)
richardv	0:b079fa4ed182	982	#define TIM_TRGO2Source_Enable ((uint32_t)0x00100000)
richardv	0:b079fa4ed182	983	#define TIM_TRGO2Source_Update ((uint32_t)0x00200000)
richardv	0:b079fa4ed182	984	#define TIM_TRGO2Source_OC1 ((uint32_t)0x00300000)
richardv	0:b079fa4ed182	985	#define TIM_TRGO2Source_OC1Ref ((uint32_t)0x00400000)
richardv	0:b079fa4ed182	986	#define TIM_TRGO2Source_OC2Ref ((uint32_t)0x00500000)
richardv	0:b079fa4ed182	987	#define TIM_TRGO2Source_OC3Ref ((uint32_t)0x00600000)
richardv	0:b079fa4ed182	988	#define TIM_TRGO2Source_OC4Ref ((uint32_t)0x00700000)
richardv	0:b079fa4ed182	989	#define TIM_TRGO2Source_OC5Ref ((uint32_t)0x00800000)
richardv	0:b079fa4ed182	990	#define TIM_TRGO2Source_OC6Ref ((uint32_t)0x00900000)
richardv	0:b079fa4ed182	991	#define TIM_TRGO2Source_OC4Ref_RisingFalling ((uint32_t)0x00A00000)
richardv	0:b079fa4ed182	992	#define TIM_TRGO2Source_OC6Ref_RisingFalling ((uint32_t)0x00B00000)
richardv	0:b079fa4ed182	993	#define TIM_TRGO2Source_OC4RefRising_OC6RefRising ((uint32_t)0x00C00000)
richardv	0:b079fa4ed182	994	#define TIM_TRGO2Source_OC4RefRising_OC6RefFalling ((uint32_t)0x00D00000)
richardv	0:b079fa4ed182	995	#define TIM_TRGO2Source_OC5RefRising_OC6RefRising ((uint32_t)0x00E00000)
richardv	0:b079fa4ed182	996	#define TIM_TRGO2Source_OC5RefRising_OC6RefFalling ((uint32_t)0x00F00000)
richardv	0:b079fa4ed182	997	#define IS_TIM_TRGO2_SOURCE(SOURCE) (((SOURCE) == TIM_TRGO2Source_Reset) \|\| \
richardv	0:b079fa4ed182	998	((SOURCE) == TIM_TRGO2Source_Enable) \|\| \
richardv	0:b079fa4ed182	999	((SOURCE) == TIM_TRGO2Source_Update) \|\| \
richardv	0:b079fa4ed182	1000	((SOURCE) == TIM_TRGO2Source_OC1) \|\| \
richardv	0:b079fa4ed182	1001	((SOURCE) == TIM_TRGO2Source_OC1Ref) \|\| \
richardv	0:b079fa4ed182	1002	((SOURCE) == TIM_TRGO2Source_OC2Ref) \|\| \
richardv	0:b079fa4ed182	1003	((SOURCE) == TIM_TRGO2Source_OC3Ref) \|\| \
richardv	0:b079fa4ed182	1004	((SOURCE) == TIM_TRGO2Source_OC4Ref) \|\| \
richardv	0:b079fa4ed182	1005	((SOURCE) == TIM_TRGO2Source_OC5Ref) \|\| \
richardv	0:b079fa4ed182	1006	((SOURCE) == TIM_TRGO2Source_OC6Ref) \|\| \
richardv	0:b079fa4ed182	1007	((SOURCE) == TIM_TRGO2Source_OC4Ref_RisingFalling) \|\| \
richardv	0:b079fa4ed182	1008	((SOURCE) == TIM_TRGO2Source_OC6Ref_RisingFalling) \|\| \
richardv	0:b079fa4ed182	1009	((SOURCE) == TIM_TRGO2Source_OC4RefRising_OC6RefRising) \|\| \
richardv	0:b079fa4ed182	1010	((SOURCE) == TIM_TRGO2Source_OC4RefRising_OC6RefFalling) \|\| \
richardv	0:b079fa4ed182	1011	((SOURCE) == TIM_TRGO2Source_OC5RefRising_OC6RefRising) \|\| \
richardv	0:b079fa4ed182	1012	((SOURCE) == TIM_TRGO2Source_OC5RefRising_OC6RefFalling))
richardv	0:b079fa4ed182	1013	/**
richardv	0:b079fa4ed182	1014	* @}
richardv	0:b079fa4ed182	1015	*/
richardv	0:b079fa4ed182	1016
richardv	0:b079fa4ed182	1017	/** @defgroup TIM_Slave_Mode
richardv	0:b079fa4ed182	1018	* @{
richardv	0:b079fa4ed182	1019	*/
richardv	0:b079fa4ed182	1020
richardv	0:b079fa4ed182	1021	#define TIM_SlaveMode_Reset ((uint32_t)0x00004)
richardv	0:b079fa4ed182	1022	#define TIM_SlaveMode_Gated ((uint32_t)0x00005)
richardv	0:b079fa4ed182	1023	#define TIM_SlaveMode_Trigger ((uint32_t)0x00006)
richardv	0:b079fa4ed182	1024	#define TIM_SlaveMode_External1 ((uint32_t)0x00007)
richardv	0:b079fa4ed182	1025	#define TIM_SlaveMode_Combined_ResetTrigger ((uint32_t)0x10000)
richardv	0:b079fa4ed182	1026	#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) \|\| \
richardv	0:b079fa4ed182	1027	((MODE) == TIM_SlaveMode_Gated) \|\| \
richardv	0:b079fa4ed182	1028	((MODE) == TIM_SlaveMode_Trigger) \|\| \
richardv	0:b079fa4ed182	1029	((MODE) == TIM_SlaveMode_External1) \|\| \
richardv	0:b079fa4ed182	1030	((MODE) == TIM_SlaveMode_Combined_ResetTrigger))
richardv	0:b079fa4ed182	1031	/**
richardv	0:b079fa4ed182	1032	* @}
richardv	0:b079fa4ed182	1033	*/
richardv	0:b079fa4ed182	1034
richardv	0:b079fa4ed182	1035	/** @defgroup TIM_Master_Slave_Mode
richardv	0:b079fa4ed182	1036	* @{
richardv	0:b079fa4ed182	1037	*/
richardv	0:b079fa4ed182	1038
richardv	0:b079fa4ed182	1039	#define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)
richardv	0:b079fa4ed182	1040	#define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)
richardv	0:b079fa4ed182	1041	#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) \|\| \
richardv	0:b079fa4ed182	1042	((STATE) == TIM_MasterSlaveMode_Disable))
richardv	0:b079fa4ed182	1043	/**
richardv	0:b079fa4ed182	1044	* @}
richardv	0:b079fa4ed182	1045	*/
richardv	0:b079fa4ed182	1046	/** @defgroup TIM_Remap
richardv	0:b079fa4ed182	1047	* @{
richardv	0:b079fa4ed182	1048	*/
richardv	0:b079fa4ed182	1049	#define TIM16_GPIO ((uint16_t)0x0000)
richardv	0:b079fa4ed182	1050	#define TIM16_RTC_CLK ((uint16_t)0x0001)
richardv	0:b079fa4ed182	1051	#define TIM16_HSEDiv32 ((uint16_t)0x0002)
richardv	0:b079fa4ed182	1052	#define TIM16_MCO ((uint16_t)0x0003)
richardv	0:b079fa4ed182	1053
richardv	0:b079fa4ed182	1054	#define TIM1_ADC1_AWDG1 ((uint16_t)0x0001)
richardv	0:b079fa4ed182	1055	#define TIM1_ADC1_AWDG2 ((uint16_t)0x0002)
richardv	0:b079fa4ed182	1056	#define TIM1_ADC1_AWDG3 ((uint16_t)0x0003)
richardv	0:b079fa4ed182	1057	#define TIM1_ADC4_AWDG1 ((uint16_t)0x0004)
richardv	0:b079fa4ed182	1058	#define TIM1_ADC4_AWDG2 ((uint16_t)0x0008)
richardv	0:b079fa4ed182	1059	#define TIM1_ADC4_AWDG3 ((uint16_t)0x000C)
richardv	0:b079fa4ed182	1060
richardv	0:b079fa4ed182	1061	#define TIM8_ADC2_AWDG1 ((uint16_t)0x0001)
richardv	0:b079fa4ed182	1062	#define TIM8_ADC2_AWDG2 ((uint16_t)0x0002)
richardv	0:b079fa4ed182	1063	#define TIM8_ADC2_AWDG3 ((uint16_t)0x0003)
richardv	0:b079fa4ed182	1064	#define TIM8_ADC3_AWDG1 ((uint16_t)0x0004)
richardv	0:b079fa4ed182	1065	#define TIM8_ADC3_AWDG2 ((uint16_t)0x0008)
richardv	0:b079fa4ed182	1066	#define TIM8_ADC3_AWDG3 ((uint16_t)0x000C)
richardv	0:b079fa4ed182	1067
richardv	0:b079fa4ed182	1068	#define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM16_GPIO)\|\| \
richardv	0:b079fa4ed182	1069	((TIM_REMAP) == TIM16_RTC_CLK) \|\| \
richardv	0:b079fa4ed182	1070	((TIM_REMAP) == TIM16_HSEDiv32) \|\| \
richardv	0:b079fa4ed182	1071	((TIM_REMAP) == TIM16_MCO) \|\|\
richardv	0:b079fa4ed182	1072	((TIM_REMAP) == TIM1_ADC1_AWDG1) \|\|\
richardv	0:b079fa4ed182	1073	((TIM_REMAP) == TIM1_ADC1_AWDG2) \|\|\
richardv	0:b079fa4ed182	1074	((TIM_REMAP) == TIM1_ADC1_AWDG3) \|\|\
richardv	0:b079fa4ed182	1075	((TIM_REMAP) == TIM1_ADC4_AWDG1) \|\|\
richardv	0:b079fa4ed182	1076	((TIM_REMAP) == TIM1_ADC4_AWDG2) \|\|\
richardv	0:b079fa4ed182	1077	((TIM_REMAP) == TIM1_ADC4_AWDG3) \|\|\
richardv	0:b079fa4ed182	1078	((TIM_REMAP) == TIM8_ADC2_AWDG1) \|\|\
richardv	0:b079fa4ed182	1079	((TIM_REMAP) == TIM8_ADC2_AWDG2) \|\|\
richardv	0:b079fa4ed182	1080	((TIM_REMAP) == TIM8_ADC2_AWDG3) \|\|\
richardv	0:b079fa4ed182	1081	((TIM_REMAP) == TIM8_ADC3_AWDG1) \|\|\
richardv	0:b079fa4ed182	1082	((TIM_REMAP) == TIM8_ADC3_AWDG2) \|\|\
richardv	0:b079fa4ed182	1083	((TIM_REMAP) == TIM8_ADC3_AWDG3))
richardv	0:b079fa4ed182	1084
richardv	0:b079fa4ed182	1085	/**
richardv	0:b079fa4ed182	1086	* @}
richardv	0:b079fa4ed182	1087	*/
richardv	0:b079fa4ed182	1088	/** @defgroup TIM_Flags
richardv	0:b079fa4ed182	1089	* @{
richardv	0:b079fa4ed182	1090	*/
richardv	0:b079fa4ed182	1091
richardv	0:b079fa4ed182	1092	#define TIM_FLAG_Update ((uint32_t)0x00001)
richardv	0:b079fa4ed182	1093	#define TIM_FLAG_CC1 ((uint32_t)0x00002)
richardv	0:b079fa4ed182	1094	#define TIM_FLAG_CC2 ((uint32_t)0x00004)
richardv	0:b079fa4ed182	1095	#define TIM_FLAG_CC3 ((uint32_t)0x00008)
richardv	0:b079fa4ed182	1096	#define TIM_FLAG_CC4 ((uint32_t)0x00010)
richardv	0:b079fa4ed182	1097	#define TIM_FLAG_COM ((uint32_t)0x00020)
richardv	0:b079fa4ed182	1098	#define TIM_FLAG_Trigger ((uint32_t)0x00040)
richardv	0:b079fa4ed182	1099	#define TIM_FLAG_Break ((uint32_t)0x00080)
richardv	0:b079fa4ed182	1100	#define TIM_FLAG_Break2 ((uint32_t)0x00100)
richardv	0:b079fa4ed182	1101	#define TIM_FLAG_CC1OF ((uint32_t)0x00200)
richardv	0:b079fa4ed182	1102	#define TIM_FLAG_CC2OF ((uint32_t)0x00400)
richardv	0:b079fa4ed182	1103	#define TIM_FLAG_CC3OF ((uint32_t)0x00800)
richardv	0:b079fa4ed182	1104	#define TIM_FLAG_CC4OF ((uint32_t)0x01000)
richardv	0:b079fa4ed182	1105	#define TIM_FLAG_CC5 ((uint32_t)0x10000)
richardv	0:b079fa4ed182	1106	#define TIM_FLAG_CC6 ((uint32_t)0x20000)
richardv	0:b079fa4ed182	1107	#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) \|\| \
richardv	0:b079fa4ed182	1108	((FLAG) == TIM_FLAG_CC1) \|\| \
richardv	0:b079fa4ed182	1109	((FLAG) == TIM_FLAG_CC2) \|\| \
richardv	0:b079fa4ed182	1110	((FLAG) == TIM_FLAG_CC3) \|\| \
richardv	0:b079fa4ed182	1111	((FLAG) == TIM_FLAG_CC4) \|\| \
richardv	0:b079fa4ed182	1112	((FLAG) == TIM_FLAG_COM) \|\| \
richardv	0:b079fa4ed182	1113	((FLAG) == TIM_FLAG_Trigger) \|\| \
richardv	0:b079fa4ed182	1114	((FLAG) == TIM_FLAG_Break) \|\| \
richardv	0:b079fa4ed182	1115	((FLAG) == TIM_FLAG_Break2) \|\| \
richardv	0:b079fa4ed182	1116	((FLAG) == TIM_FLAG_CC1OF) \|\| \
richardv	0:b079fa4ed182	1117	((FLAG) == TIM_FLAG_CC2OF) \|\| \
richardv	0:b079fa4ed182	1118	((FLAG) == TIM_FLAG_CC3OF) \|\| \
richardv	0:b079fa4ed182	1119	((FLAG) == TIM_FLAG_CC4OF) \|\|\
richardv	0:b079fa4ed182	1120	((FLAG) == TIM_FLAG_CC5) \|\|\
richardv	0:b079fa4ed182	1121	((FLAG) == TIM_FLAG_CC6))
richardv	0:b079fa4ed182	1122
richardv	0:b079fa4ed182	1123	#define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint32_t)0xE000) == 0x0000) && ((TIM_FLAG) != 0x0000))
richardv	0:b079fa4ed182	1124	/**
richardv	0:b079fa4ed182	1125	* @}
richardv	0:b079fa4ed182	1126	*/
richardv	0:b079fa4ed182	1127
richardv	0:b079fa4ed182	1128	/** @defgroup TIM_OCReferenceClear
richardv	0:b079fa4ed182	1129	* @{
richardv	0:b079fa4ed182	1130	*/
richardv	0:b079fa4ed182	1131	#define TIM_OCReferenceClear_ETRF ((uint16_t)0x0008)
richardv	0:b079fa4ed182	1132	#define TIM_OCReferenceClear_OCREFCLR ((uint16_t)0x0000)
richardv	0:b079fa4ed182	1133	#define TIM_OCREFERENCECECLEAR_SOURCE(SOURCE) (((SOURCE) == TIM_OCReferenceClear_ETRF) \|\| \
richardv	0:b079fa4ed182	1134	((SOURCE) == TIM_OCReferenceClear_OCREFCLR))
richardv	0:b079fa4ed182	1135
richardv	0:b079fa4ed182	1136	/** @defgroup TIM_Input_Capture_Filer_Value
richardv	0:b079fa4ed182	1137	* @{
richardv	0:b079fa4ed182	1138	*/
richardv	0:b079fa4ed182	1139
richardv	0:b079fa4ed182	1140	#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
richardv	0:b079fa4ed182	1141	/**
richardv	0:b079fa4ed182	1142	* @}
richardv	0:b079fa4ed182	1143	*/
richardv	0:b079fa4ed182	1144
richardv	0:b079fa4ed182	1145	/** @defgroup TIM_External_Trigger_Filter
richardv	0:b079fa4ed182	1146	* @{
richardv	0:b079fa4ed182	1147	*/
richardv	0:b079fa4ed182	1148
richardv	0:b079fa4ed182	1149	#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
richardv	0:b079fa4ed182	1150	/**
richardv	0:b079fa4ed182	1151	* @}
richardv	0:b079fa4ed182	1152	*/
richardv	0:b079fa4ed182	1153
richardv	0:b079fa4ed182	1154	/** @defgroup TIM_Legacy
richardv	0:b079fa4ed182	1155	* @{
richardv	0:b079fa4ed182	1156	*/
richardv	0:b079fa4ed182	1157
richardv	0:b079fa4ed182	1158	#define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer
richardv	0:b079fa4ed182	1159	#define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers
richardv	0:b079fa4ed182	1160	#define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers
richardv	0:b079fa4ed182	1161	#define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers
richardv	0:b079fa4ed182	1162	#define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers
richardv	0:b079fa4ed182	1163	#define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers
richardv	0:b079fa4ed182	1164	#define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers
richardv	0:b079fa4ed182	1165	#define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers
richardv	0:b079fa4ed182	1166	#define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers
richardv	0:b079fa4ed182	1167	#define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers
richardv	0:b079fa4ed182	1168	#define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers
richardv	0:b079fa4ed182	1169	#define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers
richardv	0:b079fa4ed182	1170	#define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers
richardv	0:b079fa4ed182	1171	#define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers
richardv	0:b079fa4ed182	1172	#define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers
richardv	0:b079fa4ed182	1173	#define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers
richardv	0:b079fa4ed182	1174	#define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers
richardv	0:b079fa4ed182	1175	#define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers
richardv	0:b079fa4ed182	1176	/**
richardv	0:b079fa4ed182	1177	* @}
richardv	0:b079fa4ed182	1178	*/
richardv	0:b079fa4ed182	1179
richardv	0:b079fa4ed182	1180	/**
richardv	0:b079fa4ed182	1181	* @}
richardv	0:b079fa4ed182	1182	*/
richardv	0:b079fa4ed182	1183
richardv	0:b079fa4ed182	1184	/* Exported macro ------------------------------------------------------------*/
richardv	0:b079fa4ed182	1185	/* Exported functions --------------------------------------------------------*/
richardv	0:b079fa4ed182	1186
richardv	0:b079fa4ed182	1187	/* TimeBase management ********************************************************/
richardv	0:b079fa4ed182	1188	void TIM_DeInit(TIM_TypeDef* TIMx);
richardv	0:b079fa4ed182	1189	void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
richardv	0:b079fa4ed182	1190	void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
richardv	0:b079fa4ed182	1191	void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
richardv	0:b079fa4ed182	1192	void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
richardv	0:b079fa4ed182	1193	void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter);
richardv	0:b079fa4ed182	1194	void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload);
richardv	0:b079fa4ed182	1195	uint32_t TIM_GetCounter(TIM_TypeDef* TIMx);
richardv	0:b079fa4ed182	1196	uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
richardv	0:b079fa4ed182	1197	void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
richardv	0:b079fa4ed182	1198	void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
richardv	0:b079fa4ed182	1199	void TIM_UIFRemap(TIM_TypeDef* TIMx, FunctionalState NewState);
richardv	0:b079fa4ed182	1200	void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
richardv	0:b079fa4ed182	1201	void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
richardv	0:b079fa4ed182	1202	void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
richardv	0:b079fa4ed182	1203	void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
richardv	0:b079fa4ed182	1204
richardv	0:b079fa4ed182	1205	/* Output Compare management **************************************************/
richardv	0:b079fa4ed182	1206	void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
richardv	0:b079fa4ed182	1207	void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
richardv	0:b079fa4ed182	1208	void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
richardv	0:b079fa4ed182	1209	void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
richardv	0:b079fa4ed182	1210	void TIM_OC5Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
richardv	0:b079fa4ed182	1211	void TIM_OC6Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
richardv	0:b079fa4ed182	1212	void TIM_SelectGC5C1(TIM_TypeDef* TIMx, FunctionalState NewState);
richardv	0:b079fa4ed182	1213	void TIM_SelectGC5C2(TIM_TypeDef* TIMx, FunctionalState NewState);
richardv	0:b079fa4ed182	1214	void TIM_SelectGC5C3(TIM_TypeDef* TIMx, FunctionalState NewState);
richardv	0:b079fa4ed182	1215	void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
richardv	0:b079fa4ed182	1216	void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint32_t TIM_OCMode);
richardv	0:b079fa4ed182	1217	void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1);
richardv	0:b079fa4ed182	1218	void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2);
richardv	0:b079fa4ed182	1219	void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3);
richardv	0:b079fa4ed182	1220	void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4);
richardv	0:b079fa4ed182	1221	void TIM_SetCompare5(TIM_TypeDef* TIMx, uint32_t Compare5);
richardv	0:b079fa4ed182	1222	void TIM_SetCompare6(TIM_TypeDef* TIMx, uint32_t Compare6);
richardv	0:b079fa4ed182	1223	void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
richardv	0:b079fa4ed182	1224	void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
richardv	0:b079fa4ed182	1225	void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
richardv	0:b079fa4ed182	1226	void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
richardv	0:b079fa4ed182	1227	void TIM_ForcedOC5Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
richardv	0:b079fa4ed182	1228	void TIM_ForcedOC6Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
richardv	0:b079fa4ed182	1229	void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
richardv	0:b079fa4ed182	1230	void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
richardv	0:b079fa4ed182	1231	void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
richardv	0:b079fa4ed182	1232	void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
richardv	0:b079fa4ed182	1233	void TIM_OC5PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
richardv	0:b079fa4ed182	1234	void TIM_OC6PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
richardv	0:b079fa4ed182	1235	void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
richardv	0:b079fa4ed182	1236	void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
richardv	0:b079fa4ed182	1237	void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
richardv	0:b079fa4ed182	1238	void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
richardv	0:b079fa4ed182	1239	void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
richardv	0:b079fa4ed182	1240	void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
richardv	0:b079fa4ed182	1241	void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
richardv	0:b079fa4ed182	1242	void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
richardv	0:b079fa4ed182	1243	void TIM_ClearOC5Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
richardv	0:b079fa4ed182	1244	void TIM_ClearOC6Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
richardv	0:b079fa4ed182	1245	void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear);
richardv	0:b079fa4ed182	1246	void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
richardv	0:b079fa4ed182	1247	void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
richardv	0:b079fa4ed182	1248	void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
richardv	0:b079fa4ed182	1249	void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
richardv	0:b079fa4ed182	1250	void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
richardv	0:b079fa4ed182	1251	void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
richardv	0:b079fa4ed182	1252	void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
richardv	0:b079fa4ed182	1253	void TIM_OC5PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
richardv	0:b079fa4ed182	1254	void TIM_OC6PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
richardv	0:b079fa4ed182	1255	void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
richardv	0:b079fa4ed182	1256	void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
richardv	0:b079fa4ed182	1257
richardv	0:b079fa4ed182	1258	/* Input Capture management ***************************************************/
richardv	0:b079fa4ed182	1259	void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
richardv	0:b079fa4ed182	1260	void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
richardv	0:b079fa4ed182	1261	void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
richardv	0:b079fa4ed182	1262	uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx);
richardv	0:b079fa4ed182	1263	uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx);
richardv	0:b079fa4ed182	1264	uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx);
richardv	0:b079fa4ed182	1265	uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx);
richardv	0:b079fa4ed182	1266	void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
richardv	0:b079fa4ed182	1267	void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
richardv	0:b079fa4ed182	1268	void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
richardv	0:b079fa4ed182	1269	void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
richardv	0:b079fa4ed182	1270
richardv	0:b079fa4ed182	1271	/* Advanced-control timers (TIM1 and TIM8) specific features ******************/
richardv	0:b079fa4ed182	1272	void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
richardv	0:b079fa4ed182	1273	void TIM_Break1Config(TIM_TypeDef* TIMx, uint32_t TIM_Break1Polarity, uint8_t TIM_Break1Filter);
richardv	0:b079fa4ed182	1274	void TIM_Break2Config(TIM_TypeDef* TIMx, uint32_t TIM_Break2Polarity, uint8_t TIM_Break2Filter);
richardv	0:b079fa4ed182	1275	void TIM_Break1Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
richardv	0:b079fa4ed182	1276	void TIM_Break2Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
richardv	0:b079fa4ed182	1277	void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);
richardv	0:b079fa4ed182	1278	void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);
richardv	0:b079fa4ed182	1279	void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);
richardv	0:b079fa4ed182	1280	void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);
richardv	0:b079fa4ed182	1281
richardv	0:b079fa4ed182	1282	/* Interrupts, DMA and flags management ***************************************/
richardv	0:b079fa4ed182	1283	void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
richardv	0:b079fa4ed182	1284	void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
richardv	0:b079fa4ed182	1285	FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint32_t TIM_FLAG);
richardv	0:b079fa4ed182	1286	void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
richardv	0:b079fa4ed182	1287	ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
richardv	0:b079fa4ed182	1288	void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
richardv	0:b079fa4ed182	1289	void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
richardv	0:b079fa4ed182	1290	void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
richardv	0:b079fa4ed182	1291	void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
richardv	0:b079fa4ed182	1292
richardv	0:b079fa4ed182	1293	/* Clocks management **********************************************************/
richardv	0:b079fa4ed182	1294	void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
richardv	0:b079fa4ed182	1295	void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
richardv	0:b079fa4ed182	1296	void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
richardv	0:b079fa4ed182	1297	uint16_t TIM_ICPolarity, uint16_t ICFilter);
richardv	0:b079fa4ed182	1298	void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
richardv	0:b079fa4ed182	1299	uint16_t ExtTRGFilter);
richardv	0:b079fa4ed182	1300	void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
richardv	0:b079fa4ed182	1301	uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
richardv	0:b079fa4ed182	1302
richardv	0:b079fa4ed182	1303	/* Synchronization management *************************************************/
richardv	0:b079fa4ed182	1304	void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
richardv	0:b079fa4ed182	1305	void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
richardv	0:b079fa4ed182	1306	void TIM_SelectOutputTrigger2(TIM_TypeDef* TIMx, uint32_t TIM_TRGO2Source);
richardv	0:b079fa4ed182	1307	void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint32_t TIM_SlaveMode);
richardv	0:b079fa4ed182	1308	void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
richardv	0:b079fa4ed182	1309	void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
richardv	0:b079fa4ed182	1310	uint16_t ExtTRGFilter);
richardv	0:b079fa4ed182	1311
richardv	0:b079fa4ed182	1312	/* Specific interface management **********************************************/
richardv	0:b079fa4ed182	1313	void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
richardv	0:b079fa4ed182	1314	uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
richardv	0:b079fa4ed182	1315	void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
richardv	0:b079fa4ed182	1316
richardv	0:b079fa4ed182	1317	/* Specific remapping management **********************************************/
richardv	0:b079fa4ed182	1318	void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap);
richardv	0:b079fa4ed182	1319
richardv	0:b079fa4ed182	1320	#ifdef __cplusplus
richardv	0:b079fa4ed182	1321	}
richardv	0:b079fa4ed182	1322	#endif
richardv	0:b079fa4ed182	1323
richardv	0:b079fa4ed182	1324	#endif /__STM32F30x_TIM_H /
richardv	0:b079fa4ed182	1325
richardv	0:b079fa4ed182	1326	/**
richardv	0:b079fa4ed182	1327	* @}
richardv	0:b079fa4ed182	1328	*/
richardv	0:b079fa4ed182	1329
richardv	0:b079fa4ed182	1330	/**
richardv	0:b079fa4ed182	1331	* @}
richardv	0:b079fa4ed182	1332	*/
richardv	0:b079fa4ed182	1333
richardv	0:b079fa4ed182	1334	/********************** (C) COPYRIGHT STMicroelectronics *END OF FILE**/

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Type:	Program
Created:	02 Nov 2016
Imports:	8
Forks:	0
Commits:	1
Dependents:	0
Dependencies:	0
Followers:	1

stm32f30x_tim.h@0:b079fa4ed182, 2016-11-02 (annotated)

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